github.com/gagliardetto/golang-go@v0.0.0-20201020153340-53909ea70814/cmd/internal/obj/mips/a.out.go (about) 1 // cmd/9c/9.out.h from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package mips 31 32 import ( 33 "github.com/gagliardetto/golang-go/cmd/internal/obj" 34 ) 35 36 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p mips 37 38 /* 39 * mips 64 40 */ 41 const ( 42 NSNAME = 8 43 NSYM = 50 44 NREG = 32 /* number of general registers */ 45 NFREG = 32 /* number of floating point registers */ 46 ) 47 48 const ( 49 REG_R0 = obj.RBaseMIPS + iota // must be a multiple of 32 50 REG_R1 51 REG_R2 52 REG_R3 53 REG_R4 54 REG_R5 55 REG_R6 56 REG_R7 57 REG_R8 58 REG_R9 59 REG_R10 60 REG_R11 61 REG_R12 62 REG_R13 63 REG_R14 64 REG_R15 65 REG_R16 66 REG_R17 67 REG_R18 68 REG_R19 69 REG_R20 70 REG_R21 71 REG_R22 72 REG_R23 73 REG_R24 74 REG_R25 75 REG_R26 76 REG_R27 77 REG_R28 78 REG_R29 79 REG_R30 80 REG_R31 81 82 REG_F0 // must be a multiple of 32 83 REG_F1 84 REG_F2 85 REG_F3 86 REG_F4 87 REG_F5 88 REG_F6 89 REG_F7 90 REG_F8 91 REG_F9 92 REG_F10 93 REG_F11 94 REG_F12 95 REG_F13 96 REG_F14 97 REG_F15 98 REG_F16 99 REG_F17 100 REG_F18 101 REG_F19 102 REG_F20 103 REG_F21 104 REG_F22 105 REG_F23 106 REG_F24 107 REG_F25 108 REG_F26 109 REG_F27 110 REG_F28 111 REG_F29 112 REG_F30 113 REG_F31 114 115 // co-processor 0 control registers 116 REG_M0 // must be a multiple of 32 117 REG_M1 118 REG_M2 119 REG_M3 120 REG_M4 121 REG_M5 122 REG_M6 123 REG_M7 124 REG_M8 125 REG_M9 126 REG_M10 127 REG_M11 128 REG_M12 129 REG_M13 130 REG_M14 131 REG_M15 132 REG_M16 133 REG_M17 134 REG_M18 135 REG_M19 136 REG_M20 137 REG_M21 138 REG_M22 139 REG_M23 140 REG_M24 141 REG_M25 142 REG_M26 143 REG_M27 144 REG_M28 145 REG_M29 146 REG_M30 147 REG_M31 148 149 // FPU control registers 150 REG_FCR0 // must be a multiple of 32 151 REG_FCR1 152 REG_FCR2 153 REG_FCR3 154 REG_FCR4 155 REG_FCR5 156 REG_FCR6 157 REG_FCR7 158 REG_FCR8 159 REG_FCR9 160 REG_FCR10 161 REG_FCR11 162 REG_FCR12 163 REG_FCR13 164 REG_FCR14 165 REG_FCR15 166 REG_FCR16 167 REG_FCR17 168 REG_FCR18 169 REG_FCR19 170 REG_FCR20 171 REG_FCR21 172 REG_FCR22 173 REG_FCR23 174 REG_FCR24 175 REG_FCR25 176 REG_FCR26 177 REG_FCR27 178 REG_FCR28 179 REG_FCR29 180 REG_FCR30 181 REG_FCR31 182 183 REG_HI 184 REG_LO 185 186 REG_LAST = REG_LO // the last defined register 187 188 REG_SPECIAL = REG_M0 189 190 REGZERO = REG_R0 /* set to zero */ 191 REGSP = REG_R29 192 REGSB = REG_R28 193 REGLINK = REG_R31 194 REGRET = REG_R1 195 REGARG = -1 /* -1 disables passing the first argument in register */ 196 REGRT1 = REG_R1 /* reserved for runtime, duffzero and duffcopy */ 197 REGRT2 = REG_R2 /* reserved for runtime, duffcopy */ 198 REGCTXT = REG_R22 /* context for closures */ 199 REGG = REG_R30 /* G */ 200 REGTMP = REG_R23 /* used by the linker */ 201 FREGRET = REG_F0 202 ) 203 204 // https://llvm.org/svn/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td search for DwarfRegNum 205 // https://gcc.gnu.org/viewcvs/gcc/trunk/gcc/config/mips/mips.c?view=co&revision=258099&content-type=text%2Fplain search for mips_dwarf_regno 206 // For now, this is adequate for both 32 and 64 bit. 207 var MIPSDWARFRegisters = map[int16]int16{} 208 209 func init() { 210 // f assigns dwarfregisters[from:to] = (base):(to-from+base) 211 f := func(from, to, base int16) { 212 for r := int16(from); r <= to; r++ { 213 MIPSDWARFRegisters[r] = (r - from) + base 214 } 215 } 216 f(REG_R0, REG_R31, 0) 217 f(REG_F0, REG_F31, 32) // For 32-bit MIPS, compiler only uses even numbered registers -- see cmd/compile/internal/ssa/gen/MIPSOps.go 218 MIPSDWARFRegisters[REG_HI] = 64 219 MIPSDWARFRegisters[REG_LO] = 65 220 } 221 222 const ( 223 BIG = 32766 224 ) 225 226 const ( 227 /* mark flags */ 228 FOLL = 1 << 0 229 LABEL = 1 << 1 230 LEAF = 1 << 2 231 SYNC = 1 << 3 232 BRANCH = 1 << 4 233 LOAD = 1 << 5 234 FCMP = 1 << 6 235 NOSCHED = 1 << 7 236 237 NSCHED = 20 238 ) 239 240 const ( 241 C_NONE = iota 242 C_REG 243 C_FREG 244 C_FCREG 245 C_MREG /* special processor register */ 246 C_HI 247 C_LO 248 C_ZCON 249 C_SCON /* 16 bit signed */ 250 C_UCON /* 32 bit signed, low 16 bits 0 */ 251 C_ADD0CON 252 C_AND0CON 253 C_ADDCON /* -0x8000 <= v < 0 */ 254 C_ANDCON /* 0 < v <= 0xFFFF */ 255 C_LCON /* other 32 */ 256 C_DCON /* other 64 (could subdivide further) */ 257 C_SACON /* $n(REG) where n <= int16 */ 258 C_SECON 259 C_LACON /* $n(REG) where int16 < n <= int32 */ 260 C_LECON 261 C_DACON /* $n(REG) where int32 < n */ 262 C_STCON /* $tlsvar */ 263 C_SBRA 264 C_LBRA 265 C_SAUTO 266 C_LAUTO 267 C_SEXT 268 C_LEXT 269 C_ZOREG 270 C_SOREG 271 C_LOREG 272 C_GOK 273 C_ADDR 274 C_TLS 275 C_TEXTSIZE 276 277 C_NCLASS /* must be the last */ 278 ) 279 280 const ( 281 AABSD = obj.ABaseMIPS + obj.A_ARCHSPECIFIC + iota 282 AABSF 283 AABSW 284 AADD 285 AADDD 286 AADDF 287 AADDU 288 AADDW 289 AAND 290 ABEQ 291 ABFPF 292 ABFPT 293 ABGEZ 294 ABGEZAL 295 ABGTZ 296 ABLEZ 297 ABLTZ 298 ABLTZAL 299 ABNE 300 ABREAK 301 ACLO 302 ACLZ 303 ACMOVF 304 ACMOVN 305 ACMOVT 306 ACMOVZ 307 ACMPEQD 308 ACMPEQF 309 ACMPGED 310 ACMPGEF 311 ACMPGTD 312 ACMPGTF 313 ADIV 314 ADIVD 315 ADIVF 316 ADIVU 317 ADIVW 318 AGOK 319 ALL 320 ALLV 321 ALUI 322 AMADD 323 AMOVB 324 AMOVBU 325 AMOVD 326 AMOVDF 327 AMOVDW 328 AMOVF 329 AMOVFD 330 AMOVFW 331 AMOVH 332 AMOVHU 333 AMOVW 334 AMOVWD 335 AMOVWF 336 AMOVWL 337 AMOVWR 338 AMSUB 339 AMUL 340 AMULD 341 AMULF 342 AMULU 343 AMULW 344 ANEGD 345 ANEGF 346 ANEGW 347 ANEGV 348 ANOOP // hardware nop 349 ANOR 350 AOR 351 AREM 352 AREMU 353 ARFE 354 ASC 355 ASCV 356 ASGT 357 ASGTU 358 ASLL 359 ASQRTD 360 ASQRTF 361 ASRA 362 ASRL 363 ASUB 364 ASUBD 365 ASUBF 366 ASUBU 367 ASUBW 368 ASYNC 369 ASYSCALL 370 ATEQ 371 ATLBP 372 ATLBR 373 ATLBWI 374 ATLBWR 375 ATNE 376 AWORD 377 AXOR 378 379 /* 64-bit */ 380 AMOVV 381 AMOVVL 382 AMOVVR 383 ASLLV 384 ASRAV 385 ASRLV 386 ADIVV 387 ADIVVU 388 AREMV 389 AREMVU 390 AMULV 391 AMULVU 392 AADDV 393 AADDVU 394 ASUBV 395 ASUBVU 396 397 /* 64-bit FP */ 398 ATRUNCFV 399 ATRUNCDV 400 ATRUNCFW 401 ATRUNCDW 402 AMOVWU 403 AMOVFV 404 AMOVDV 405 AMOVVF 406 AMOVVD 407 408 ALAST 409 410 // aliases 411 AJMP = obj.AJMP 412 AJAL = obj.ACALL 413 ARET = obj.ARET 414 ) 415 416 func init() { 417 // The asm encoder generally assumes that the lowest 5 bits of the 418 // REG_XX constants match the machine instruction encoding, i.e. 419 // the lowest 5 bits is the register number. 420 // Check this here. 421 if REG_R0%32 != 0 { 422 panic("REG_R0 is not a multiple of 32") 423 } 424 if REG_F0%32 != 0 { 425 panic("REG_F0 is not a multiple of 32") 426 } 427 if REG_M0%32 != 0 { 428 panic("REG_M0 is not a multiple of 32") 429 } 430 if REG_FCR0%32 != 0 { 431 panic("REG_FCR0 is not a multiple of 32") 432 } 433 }