github.com/go-asm/go@v1.21.1-0.20240213172139-40c5ead50c48/cmd/obj/s390x/asmz.go (about) 1 // Based on github.com/go-asm/go/cmd/obj/ppc64/asm9.go. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package s390x 31 32 import ( 33 "fmt" 34 "log" 35 "math" 36 "sort" 37 38 "github.com/go-asm/go/cmd/obj" 39 "github.com/go-asm/go/cmd/objabi" 40 ) 41 42 // ctxtz holds state while assembling a single function. 43 // Each function gets a fresh ctxtz. 44 // This allows for multiple functions to be safely concurrently assembled. 45 type ctxtz struct { 46 ctxt *obj.Link 47 newprog obj.ProgAlloc 48 cursym *obj.LSym 49 autosize int32 50 instoffset int64 51 pc int64 52 } 53 54 // instruction layout. 55 const ( 56 funcAlign = 16 57 ) 58 59 type Optab struct { 60 as obj.As // opcode 61 i uint8 // handler index 62 a1 uint8 // From 63 a2 uint8 // Reg 64 a3 uint8 // RestArgs[0] 65 a4 uint8 // RestArgs[1] 66 a5 uint8 // RestArgs[2] 67 a6 uint8 // To 68 } 69 70 var optab = []Optab{ 71 // zero-length instructions 72 {i: 0, as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE}, 73 {i: 0, as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE}, 74 {i: 0, as: obj.APCDATA, a1: C_LCON, a6: C_LCON}, 75 {i: 0, as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR}, 76 {i: 0, as: obj.ANOP}, 77 {i: 0, as: obj.ANOP, a1: C_SAUTO}, 78 79 // move register 80 {i: 1, as: AMOVD, a1: C_REG, a6: C_REG}, 81 {i: 1, as: AMOVB, a1: C_REG, a6: C_REG}, 82 {i: 1, as: AMOVBZ, a1: C_REG, a6: C_REG}, 83 {i: 1, as: AMOVW, a1: C_REG, a6: C_REG}, 84 {i: 1, as: AMOVWZ, a1: C_REG, a6: C_REG}, 85 {i: 1, as: AFMOVD, a1: C_FREG, a6: C_FREG}, 86 {i: 1, as: AMOVDBR, a1: C_REG, a6: C_REG}, 87 88 // load constant 89 {i: 26, as: AMOVD, a1: C_LACON, a6: C_REG}, 90 {i: 26, as: AMOVW, a1: C_LACON, a6: C_REG}, 91 {i: 26, as: AMOVWZ, a1: C_LACON, a6: C_REG}, 92 {i: 3, as: AMOVD, a1: C_DCON, a6: C_REG}, 93 {i: 3, as: AMOVW, a1: C_DCON, a6: C_REG}, 94 {i: 3, as: AMOVWZ, a1: C_DCON, a6: C_REG}, 95 {i: 3, as: AMOVB, a1: C_DCON, a6: C_REG}, 96 {i: 3, as: AMOVBZ, a1: C_DCON, a6: C_REG}, 97 98 // store constant 99 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LAUTO}, 100 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LAUTO}, 101 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LAUTO}, 102 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LAUTO}, 103 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LAUTO}, 104 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LAUTO}, 105 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LAUTO}, 106 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LAUTO}, 107 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO}, 108 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO}, 109 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG}, 110 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG}, 111 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG}, 112 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG}, 113 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG}, 114 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG}, 115 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LOREG}, 116 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LOREG}, 117 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LOREG}, 118 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LOREG}, 119 120 // store 121 {i: 35, as: AMOVD, a1: C_REG, a6: C_LAUTO}, 122 {i: 35, as: AMOVW, a1: C_REG, a6: C_LAUTO}, 123 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LAUTO}, 124 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LAUTO}, 125 {i: 35, as: AMOVB, a1: C_REG, a6: C_LAUTO}, 126 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LAUTO}, 127 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LAUTO}, 128 {i: 35, as: AMOVD, a1: C_REG, a6: C_LOREG}, 129 {i: 35, as: AMOVW, a1: C_REG, a6: C_LOREG}, 130 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LOREG}, 131 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LOREG}, 132 {i: 35, as: AMOVB, a1: C_REG, a6: C_LOREG}, 133 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LOREG}, 134 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LOREG}, 135 {i: 74, as: AMOVD, a1: C_REG, a6: C_ADDR}, 136 {i: 74, as: AMOVW, a1: C_REG, a6: C_ADDR}, 137 {i: 74, as: AMOVWZ, a1: C_REG, a6: C_ADDR}, 138 {i: 74, as: AMOVBZ, a1: C_REG, a6: C_ADDR}, 139 {i: 74, as: AMOVB, a1: C_REG, a6: C_ADDR}, 140 141 // load 142 {i: 36, as: AMOVD, a1: C_LAUTO, a6: C_REG}, 143 {i: 36, as: AMOVW, a1: C_LAUTO, a6: C_REG}, 144 {i: 36, as: AMOVWZ, a1: C_LAUTO, a6: C_REG}, 145 {i: 36, as: AMOVBZ, a1: C_LAUTO, a6: C_REG}, 146 {i: 36, as: AMOVB, a1: C_LAUTO, a6: C_REG}, 147 {i: 36, as: AMOVDBR, a1: C_LAUTO, a6: C_REG}, 148 {i: 36, as: AMOVHBR, a1: C_LAUTO, a6: C_REG}, 149 {i: 36, as: AMOVD, a1: C_LOREG, a6: C_REG}, 150 {i: 36, as: AMOVW, a1: C_LOREG, a6: C_REG}, 151 {i: 36, as: AMOVWZ, a1: C_LOREG, a6: C_REG}, 152 {i: 36, as: AMOVBZ, a1: C_LOREG, a6: C_REG}, 153 {i: 36, as: AMOVB, a1: C_LOREG, a6: C_REG}, 154 {i: 36, as: AMOVDBR, a1: C_LOREG, a6: C_REG}, 155 {i: 36, as: AMOVHBR, a1: C_LOREG, a6: C_REG}, 156 {i: 75, as: AMOVD, a1: C_ADDR, a6: C_REG}, 157 {i: 75, as: AMOVW, a1: C_ADDR, a6: C_REG}, 158 {i: 75, as: AMOVWZ, a1: C_ADDR, a6: C_REG}, 159 {i: 75, as: AMOVBZ, a1: C_ADDR, a6: C_REG}, 160 {i: 75, as: AMOVB, a1: C_ADDR, a6: C_REG}, 161 162 // interlocked load and op 163 {i: 99, as: ALAAG, a1: C_REG, a2: C_REG, a6: C_LOREG}, 164 165 // integer arithmetic 166 {i: 2, as: AADD, a1: C_REG, a2: C_REG, a6: C_REG}, 167 {i: 2, as: AADD, a1: C_REG, a6: C_REG}, 168 {i: 22, as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG}, 169 {i: 22, as: AADD, a1: C_LCON, a6: C_REG}, 170 {i: 12, as: AADD, a1: C_LOREG, a6: C_REG}, 171 {i: 12, as: AADD, a1: C_LAUTO, a6: C_REG}, 172 {i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG}, 173 {i: 21, as: ASUB, a1: C_LCON, a6: C_REG}, 174 {i: 12, as: ASUB, a1: C_LOREG, a6: C_REG}, 175 {i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG}, 176 {i: 4, as: AMULHD, a1: C_REG, a6: C_REG}, 177 {i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG}, 178 {i: 62, as: AMLGR, a1: C_REG, a6: C_REG}, 179 {i: 2, as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG}, 180 {i: 2, as: ADIVW, a1: C_REG, a6: C_REG}, 181 {i: 10, as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG}, 182 {i: 10, as: ASUB, a1: C_REG, a6: C_REG}, 183 {i: 47, as: ANEG, a1: C_REG, a6: C_REG}, 184 {i: 47, as: ANEG, a6: C_REG}, 185 186 // integer logical 187 {i: 6, as: AAND, a1: C_REG, a2: C_REG, a6: C_REG}, 188 {i: 6, as: AAND, a1: C_REG, a6: C_REG}, 189 {i: 23, as: AAND, a1: C_LCON, a6: C_REG}, 190 {i: 12, as: AAND, a1: C_LOREG, a6: C_REG}, 191 {i: 12, as: AAND, a1: C_LAUTO, a6: C_REG}, 192 {i: 6, as: AANDW, a1: C_REG, a2: C_REG, a6: C_REG}, 193 {i: 6, as: AANDW, a1: C_REG, a6: C_REG}, 194 {i: 24, as: AANDW, a1: C_LCON, a6: C_REG}, 195 {i: 12, as: AANDW, a1: C_LOREG, a6: C_REG}, 196 {i: 12, as: AANDW, a1: C_LAUTO, a6: C_REG}, 197 {i: 7, as: ASLD, a1: C_REG, a6: C_REG}, 198 {i: 7, as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG}, 199 {i: 7, as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG}, 200 {i: 7, as: ASLD, a1: C_SCON, a6: C_REG}, 201 {i: 13, as: ARNSBG, a1: C_SCON, a3: C_SCON, a4: C_SCON, a5: C_REG, a6: C_REG}, 202 203 // compare and swap 204 {i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG}, 205 206 // floating point 207 {i: 32, as: AFADD, a1: C_FREG, a6: C_FREG}, 208 {i: 33, as: AFABS, a1: C_FREG, a6: C_FREG}, 209 {i: 33, as: AFABS, a6: C_FREG}, 210 {i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG}, 211 {i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG}, 212 {i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG}, 213 {i: 36, as: AFMOVD, a1: C_LOREG, a6: C_FREG}, 214 {i: 75, as: AFMOVD, a1: C_ADDR, a6: C_FREG}, 215 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LAUTO}, 216 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LOREG}, 217 {i: 74, as: AFMOVD, a1: C_FREG, a6: C_ADDR}, 218 {i: 67, as: AFMOVD, a1: C_ZCON, a6: C_FREG}, 219 {i: 81, as: ALDGR, a1: C_REG, a6: C_FREG}, 220 {i: 81, as: ALGDR, a1: C_FREG, a6: C_REG}, 221 {i: 82, as: ACEFBRA, a1: C_REG, a6: C_FREG}, 222 {i: 83, as: ACFEBRA, a1: C_FREG, a6: C_REG}, 223 {i: 48, as: AFIEBR, a1: C_SCON, a2: C_FREG, a6: C_FREG}, 224 {i: 49, as: ACPSDR, a1: C_FREG, a2: C_FREG, a6: C_FREG}, 225 {i: 50, as: ALTDBR, a1: C_FREG, a6: C_FREG}, 226 {i: 51, as: ATCDB, a1: C_FREG, a6: C_SCON}, 227 228 // load symbol address (plus offset) 229 {i: 19, as: AMOVD, a1: C_SYMADDR, a6: C_REG}, 230 {i: 93, as: AMOVD, a1: C_GOTADDR, a6: C_REG}, 231 {i: 94, as: AMOVD, a1: C_TLS_LE, a6: C_REG}, 232 {i: 95, as: AMOVD, a1: C_TLS_IE, a6: C_REG}, 233 234 // system call 235 {i: 5, as: ASYSCALL}, 236 {i: 77, as: ASYSCALL, a1: C_SCON}, 237 238 // branch 239 {i: 16, as: ABEQ, a6: C_SBRA}, 240 {i: 16, as: ABRC, a1: C_SCON, a6: C_SBRA}, 241 {i: 11, as: ABR, a6: C_LBRA}, 242 {i: 16, as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA}, 243 {i: 18, as: ABR, a6: C_REG}, 244 {i: 18, as: ABR, a1: C_REG, a6: C_REG}, 245 {i: 15, as: ABR, a6: C_ZOREG}, 246 {i: 15, as: ABC, a6: C_ZOREG}, 247 248 // compare and branch 249 {i: 89, as: ACGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA}, 250 {i: 89, as: ACMPBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA}, 251 {i: 89, as: ACLGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA}, 252 {i: 89, as: ACMPUBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA}, 253 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA}, 254 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_SCON, a6: C_SBRA}, 255 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_ADDCON, a6: C_SBRA}, 256 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_SCON, a6: C_SBRA}, 257 {i: 90, as: ACLGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA}, 258 {i: 90, as: ACMPUBEQ, a1: C_REG, a3: C_ANDCON, a6: C_SBRA}, 259 260 // branch on count 261 {i: 41, as: ABRCT, a1: C_REG, a6: C_SBRA}, 262 {i: 41, as: ABRCTG, a1: C_REG, a6: C_SBRA}, 263 264 // move on condition 265 {i: 17, as: AMOVDEQ, a1: C_REG, a6: C_REG}, 266 267 // load on condition 268 {i: 25, as: ALOCGR, a1: C_SCON, a2: C_REG, a6: C_REG}, 269 270 // find leftmost one 271 {i: 8, as: AFLOGR, a1: C_REG, a6: C_REG}, 272 273 // population count 274 {i: 9, as: APOPCNT, a1: C_REG, a6: C_REG}, 275 276 // compare 277 {i: 70, as: ACMP, a1: C_REG, a6: C_REG}, 278 {i: 71, as: ACMP, a1: C_REG, a6: C_LCON}, 279 {i: 70, as: ACMPU, a1: C_REG, a6: C_REG}, 280 {i: 71, as: ACMPU, a1: C_REG, a6: C_LCON}, 281 {i: 70, as: AFCMPO, a1: C_FREG, a6: C_FREG}, 282 {i: 70, as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG}, 283 284 // test under mask 285 {i: 91, as: ATMHH, a1: C_REG, a6: C_ANDCON}, 286 287 // insert program mask 288 {i: 92, as: AIPM, a1: C_REG}, 289 290 // set program mask 291 {i: 76, as: ASPM, a1: C_REG}, 292 293 // 32-bit access registers 294 {i: 68, as: AMOVW, a1: C_AREG, a6: C_REG}, 295 {i: 68, as: AMOVWZ, a1: C_AREG, a6: C_REG}, 296 {i: 69, as: AMOVW, a1: C_REG, a6: C_AREG}, 297 {i: 69, as: AMOVWZ, a1: C_REG, a6: C_AREG}, 298 299 // macros 300 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LOREG}, 301 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LAUTO}, 302 303 // load/store multiple 304 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LOREG}, 305 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LAUTO}, 306 {i: 98, as: ALMG, a1: C_LOREG, a2: C_REG, a6: C_REG}, 307 {i: 98, as: ALMG, a1: C_LAUTO, a2: C_REG, a6: C_REG}, 308 309 // bytes 310 {i: 40, as: ABYTE, a1: C_SCON}, 311 {i: 40, as: AWORD, a1: C_LCON}, 312 {i: 31, as: ADWORD, a1: C_LCON}, 313 {i: 31, as: ADWORD, a1: C_DCON}, 314 315 // fast synchronization 316 {i: 80, as: ASYNC}, 317 318 // store clock 319 {i: 88, as: ASTCK, a6: C_SAUTO}, 320 {i: 88, as: ASTCK, a6: C_SOREG}, 321 322 // storage and storage 323 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LOREG}, 324 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LAUTO}, 325 {i: 84, as: AMVC, a1: C_SCON, a3: C_LAUTO, a6: C_LAUTO}, 326 327 // address 328 {i: 85, as: ALARL, a1: C_LCON, a6: C_REG}, 329 {i: 85, as: ALARL, a1: C_SYMADDR, a6: C_REG}, 330 {i: 86, as: ALA, a1: C_SOREG, a6: C_REG}, 331 {i: 86, as: ALA, a1: C_SAUTO, a6: C_REG}, 332 {i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG}, 333 334 // undefined (deliberate illegal instruction) 335 {i: 78, as: obj.AUNDEF}, 336 337 // Break point instruction(0x0001 opcode) 338 {i: 73, as: ABRRK}, 339 340 // 2 byte no-operation 341 {i: 66, as: ANOPH}, 342 343 // crypto instructions 344 345 // KM 346 {i: 124, as: AKM, a1: C_REG, a6: C_REG}, 347 348 // KDSA 349 {i: 125, as: AKDSA, a1: C_REG, a6: C_REG}, 350 351 // KMA 352 {i: 126, as: AKMA, a1: C_REG, a2: C_REG, a6: C_REG}, 353 354 // vector instructions 355 356 // VRX store 357 {i: 100, as: AVST, a1: C_VREG, a6: C_SOREG}, 358 {i: 100, as: AVST, a1: C_VREG, a6: C_SAUTO}, 359 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG}, 360 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO}, 361 362 // VRX load 363 {i: 101, as: AVL, a1: C_SOREG, a6: C_VREG}, 364 {i: 101, as: AVL, a1: C_SAUTO, a6: C_VREG}, 365 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG}, 366 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG}, 367 368 // VRV scatter 369 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG}, 370 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO}, 371 372 // VRV gather 373 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG}, 374 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG}, 375 376 // VRS element shift/rotate and load gr to/from vr element 377 {i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG}, 378 {i: 104, as: AVESLG, a1: C_REG, a2: C_VREG, a6: C_VREG}, 379 {i: 104, as: AVESLG, a1: C_SCON, a6: C_VREG}, 380 {i: 104, as: AVESLG, a1: C_REG, a6: C_VREG}, 381 {i: 104, as: AVLGVG, a1: C_SCON, a2: C_VREG, a6: C_REG}, 382 {i: 104, as: AVLGVG, a1: C_REG, a2: C_VREG, a6: C_REG}, 383 {i: 104, as: AVLVGG, a1: C_SCON, a2: C_REG, a6: C_VREG}, 384 {i: 104, as: AVLVGG, a1: C_REG, a2: C_REG, a6: C_VREG}, 385 386 // VRS store multiple 387 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SOREG}, 388 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SAUTO}, 389 390 // VRS load multiple 391 {i: 106, as: AVLM, a1: C_SOREG, a2: C_VREG, a6: C_VREG}, 392 {i: 106, as: AVLM, a1: C_SAUTO, a2: C_VREG, a6: C_VREG}, 393 394 // VRS store with length 395 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SOREG}, 396 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SAUTO}, 397 398 // VRS load with length 399 {i: 108, as: AVLL, a1: C_REG, a3: C_SOREG, a6: C_VREG}, 400 {i: 108, as: AVLL, a1: C_REG, a3: C_SAUTO, a6: C_VREG}, 401 402 // VRI-a 403 {i: 109, as: AVGBM, a1: C_ANDCON, a6: C_VREG}, 404 {i: 109, as: AVZERO, a6: C_VREG}, 405 {i: 109, as: AVREPIG, a1: C_ADDCON, a6: C_VREG}, 406 {i: 109, as: AVREPIG, a1: C_SCON, a6: C_VREG}, 407 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_ADDCON, a6: C_VREG}, 408 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_SCON, a6: C_VREG}, 409 410 // VRI-b generate mask 411 {i: 110, as: AVGMG, a1: C_SCON, a3: C_SCON, a6: C_VREG}, 412 413 // VRI-c replicate 414 {i: 111, as: AVREPG, a1: C_UCON, a2: C_VREG, a6: C_VREG}, 415 416 // VRI-d element rotate and insert under mask and 417 // shift left double by byte 418 {i: 112, as: AVERIMG, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 419 {i: 112, as: AVSLDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 420 421 // VRI-d fp test data class immediate 422 {i: 113, as: AVFTCIDB, a1: C_SCON, a2: C_VREG, a6: C_VREG}, 423 424 // VRR-a load reg 425 {i: 114, as: AVLR, a1: C_VREG, a6: C_VREG}, 426 427 // VRR-a compare 428 {i: 115, as: AVECG, a1: C_VREG, a6: C_VREG}, 429 430 // VRR-b 431 {i: 117, as: AVCEQG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 432 {i: 117, as: AVFAEF, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 433 {i: 117, as: AVPKSG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 434 435 // VRR-c 436 {i: 118, as: AVAQ, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 437 {i: 118, as: AVAQ, a1: C_VREG, a6: C_VREG}, 438 {i: 118, as: AVNOT, a1: C_VREG, a6: C_VREG}, 439 {i: 123, as: AVPDI, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 440 441 // VRR-c shifts 442 {i: 119, as: AVERLLVG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 443 {i: 119, as: AVERLLVG, a1: C_VREG, a6: C_VREG}, 444 445 // VRR-d 446 {i: 120, as: AVACQ, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 447 448 // VRR-e 449 {i: 121, as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 450 451 // VRR-f 452 {i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG}, 453 } 454 455 var oprange [ALAST & obj.AMask][]Optab 456 457 var xcmp [C_NCLASS][C_NCLASS]bool 458 459 func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 460 if ctxt.Retpoline { 461 ctxt.Diag("-spectre=ret not supported on s390x") 462 ctxt.Retpoline = false // don't keep printing 463 } 464 465 p := cursym.Func().Text 466 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 467 return 468 } 469 470 if oprange[AORW&obj.AMask] == nil { 471 ctxt.Diag("s390x ops not initialized, call s390x.buildop first") 472 } 473 474 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 475 476 buffer := make([]byte, 0) 477 changed := true 478 loop := 0 479 nrelocs0 := len(c.cursym.R) 480 for changed { 481 if loop > 100 { 482 c.ctxt.Diag("stuck in spanz loop") 483 break 484 } 485 changed = false 486 buffer = buffer[:0] 487 for i := range c.cursym.R[nrelocs0:] { 488 c.cursym.R[nrelocs0+i] = obj.Reloc{} 489 } 490 c.cursym.R = c.cursym.R[:nrelocs0] // preserve marker relocations generated by the compiler 491 for p := c.cursym.Func().Text; p != nil; p = p.Link { 492 pc := int64(len(buffer)) 493 if pc != p.Pc { 494 changed = true 495 } 496 p.Pc = pc 497 c.pc = p.Pc 498 c.asmout(p, &buffer) 499 if pc == int64(len(buffer)) { 500 switch p.As { 501 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT: 502 // ok 503 default: 504 c.ctxt.Diag("zero-width instruction\n%v", p) 505 } 506 } 507 } 508 loop++ 509 } 510 511 c.cursym.Size = int64(len(buffer)) 512 if c.cursym.Size%funcAlign != 0 { 513 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign) 514 } 515 c.cursym.Grow(c.cursym.Size) 516 copy(c.cursym.P, buffer) 517 518 // Mark nonpreemptible instruction sequences. 519 // We use REGTMP as a scratch register during call injection, 520 // so instruction sequences that use REGTMP are unsafe to 521 // preempt asynchronously. 522 obj.MarkUnsafePoints(c.ctxt, c.cursym.Func().Text, c.newprog, c.isUnsafePoint, nil) 523 } 524 525 // Return whether p is an unsafe point. 526 func (c *ctxtz) isUnsafePoint(p *obj.Prog) bool { 527 if p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP { 528 return true 529 } 530 for _, a := range p.RestArgs { 531 if a.Reg == REGTMP { 532 return true 533 } 534 } 535 return p.Mark&USETMP != 0 536 } 537 538 func isint32(v int64) bool { 539 return int64(int32(v)) == v 540 } 541 542 func isuint32(v uint64) bool { 543 return uint64(uint32(v)) == v 544 } 545 546 func (c *ctxtz) aclass(a *obj.Addr) int { 547 switch a.Type { 548 case obj.TYPE_NONE: 549 return C_NONE 550 551 case obj.TYPE_REG: 552 if REG_R0 <= a.Reg && a.Reg <= REG_R15 { 553 return C_REG 554 } 555 if REG_F0 <= a.Reg && a.Reg <= REG_F15 { 556 return C_FREG 557 } 558 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 { 559 return C_AREG 560 } 561 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 562 return C_VREG 563 } 564 return C_GOK 565 566 case obj.TYPE_MEM: 567 switch a.Name { 568 case obj.NAME_EXTERN, 569 obj.NAME_STATIC: 570 if a.Sym == nil { 571 // must have a symbol 572 break 573 } 574 c.instoffset = a.Offset 575 if a.Sym.Type == objabi.STLSBSS { 576 if c.ctxt.Flag_shared { 577 return C_TLS_IE // initial exec model 578 } 579 return C_TLS_LE // local exec model 580 } 581 return C_ADDR 582 583 case obj.NAME_GOTREF: 584 return C_GOTADDR 585 586 case obj.NAME_AUTO: 587 if a.Reg == REGSP { 588 // unset base register for better printing, since 589 // a.Offset is still relative to pseudo-SP. 590 a.Reg = obj.REG_NONE 591 } 592 c.instoffset = int64(c.autosize) + a.Offset 593 if c.instoffset >= -BIG && c.instoffset < BIG { 594 return C_SAUTO 595 } 596 return C_LAUTO 597 598 case obj.NAME_PARAM: 599 if a.Reg == REGSP { 600 // unset base register for better printing, since 601 // a.Offset is still relative to pseudo-FP. 602 a.Reg = obj.REG_NONE 603 } 604 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize 605 if c.instoffset >= -BIG && c.instoffset < BIG { 606 return C_SAUTO 607 } 608 return C_LAUTO 609 610 case obj.NAME_NONE: 611 c.instoffset = a.Offset 612 if c.instoffset == 0 { 613 return C_ZOREG 614 } 615 if c.instoffset >= -BIG && c.instoffset < BIG { 616 return C_SOREG 617 } 618 return C_LOREG 619 } 620 621 return C_GOK 622 623 case obj.TYPE_TEXTSIZE: 624 return C_TEXTSIZE 625 626 case obj.TYPE_FCONST: 627 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 { 628 return C_ZCON 629 } 630 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val) 631 632 case obj.TYPE_CONST, 633 obj.TYPE_ADDR: 634 switch a.Name { 635 case obj.NAME_NONE: 636 c.instoffset = a.Offset 637 if a.Reg != 0 { 638 if -BIG <= c.instoffset && c.instoffset <= BIG { 639 return C_SACON 640 } 641 if isint32(c.instoffset) { 642 return C_LACON 643 } 644 return C_DACON 645 } 646 647 case obj.NAME_EXTERN, 648 obj.NAME_STATIC: 649 s := a.Sym 650 if s == nil { 651 return C_GOK 652 } 653 c.instoffset = a.Offset 654 655 return C_SYMADDR 656 657 case obj.NAME_AUTO: 658 if a.Reg == REGSP { 659 // unset base register for better printing, since 660 // a.Offset is still relative to pseudo-SP. 661 a.Reg = obj.REG_NONE 662 } 663 c.instoffset = int64(c.autosize) + a.Offset 664 if c.instoffset >= -BIG && c.instoffset < BIG { 665 return C_SACON 666 } 667 return C_LACON 668 669 case obj.NAME_PARAM: 670 if a.Reg == REGSP { 671 // unset base register for better printing, since 672 // a.Offset is still relative to pseudo-FP. 673 a.Reg = obj.REG_NONE 674 } 675 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize 676 if c.instoffset >= -BIG && c.instoffset < BIG { 677 return C_SACON 678 } 679 return C_LACON 680 681 default: 682 return C_GOK 683 } 684 685 if c.instoffset == 0 { 686 return C_ZCON 687 } 688 if c.instoffset >= 0 { 689 if c.instoffset <= 0x7fff { 690 return C_SCON 691 } 692 if c.instoffset <= 0xffff { 693 return C_ANDCON 694 } 695 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && （(instoffset & (1<<31)) == 0) */ 696 return C_UCON 697 } 698 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 699 return C_LCON 700 } 701 return C_DCON 702 } 703 704 if c.instoffset >= -0x8000 { 705 return C_ADDCON 706 } 707 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 708 return C_UCON 709 } 710 if isint32(c.instoffset) { 711 return C_LCON 712 } 713 return C_DCON 714 715 case obj.TYPE_BRANCH: 716 return C_SBRA 717 } 718 719 return C_GOK 720 } 721 722 func (c *ctxtz) oplook(p *obj.Prog) *Optab { 723 // Return cached optab entry if available. 724 if p.Optab != 0 { 725 return &optab[p.Optab-1] 726 } 727 if len(p.RestArgs) > 3 { 728 c.ctxt.Diag("too many RestArgs: got %v, maximum is 3\n", len(p.RestArgs)) 729 return nil 730 } 731 732 // Initialize classes for all arguments. 733 p.From.Class = int8(c.aclass(&p.From) + 1) 734 p.To.Class = int8(c.aclass(&p.To) + 1) 735 for i := range p.RestArgs { 736 p.RestArgs[i].Addr.Class = int8(c.aclass(&p.RestArgs[i].Addr) + 1) 737 } 738 739 // Mirrors the argument list in Optab. 740 args := [...]int8{ 741 p.From.Class - 1, 742 C_NONE, // p.Reg 743 C_NONE, // p.RestArgs[0] 744 C_NONE, // p.RestArgs[1] 745 C_NONE, // p.RestArgs[2] 746 p.To.Class - 1, 747 } 748 // Fill in argument class for p.Reg. 749 switch { 750 case REG_R0 <= p.Reg && p.Reg <= REG_R15: 751 args[1] = C_REG 752 case REG_V0 <= p.Reg && p.Reg <= REG_V31: 753 args[1] = C_VREG 754 case REG_F0 <= p.Reg && p.Reg <= REG_F15: 755 args[1] = C_FREG 756 case REG_AR0 <= p.Reg && p.Reg <= REG_AR15: 757 args[1] = C_AREG 758 } 759 // Fill in argument classes for p.RestArgs. 760 for i, a := range p.RestArgs { 761 args[2+i] = a.Class - 1 762 } 763 764 // Lookup op in optab. 765 ops := oprange[p.As&obj.AMask] 766 cmp := [len(args)]*[C_NCLASS]bool{} 767 for i := range cmp { 768 cmp[i] = &xcmp[args[i]] 769 } 770 for i := range ops { 771 op := &ops[i] 772 if cmp[0][op.a1] && cmp[1][op.a2] && 773 cmp[2][op.a3] && cmp[3][op.a4] && 774 cmp[4][op.a5] && cmp[5][op.a6] { 775 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 776 return op 777 } 778 } 779 780 // Cannot find a case; abort. 781 s := "" 782 for _, a := range args { 783 s += fmt.Sprintf(" %v", DRconv(int(a))) 784 } 785 c.ctxt.Diag("illegal combination %v%v\n", p.As, s) 786 c.ctxt.Diag("prog: %v\n", p) 787 return nil 788 } 789 790 func cmp(a int, b int) bool { 791 if a == b { 792 return true 793 } 794 switch a { 795 case C_DCON: 796 if b == C_LCON { 797 return true 798 } 799 fallthrough 800 case C_LCON: 801 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 802 return true 803 } 804 805 case C_ADDCON: 806 if b == C_ZCON || b == C_SCON { 807 return true 808 } 809 810 case C_ANDCON: 811 if b == C_ZCON || b == C_SCON { 812 return true 813 } 814 815 case C_UCON: 816 if b == C_ZCON || b == C_SCON { 817 return true 818 } 819 820 case C_SCON: 821 if b == C_ZCON { 822 return true 823 } 824 825 case C_LACON: 826 if b == C_SACON { 827 return true 828 } 829 830 case C_LBRA: 831 if b == C_SBRA { 832 return true 833 } 834 835 case C_LAUTO: 836 if b == C_SAUTO { 837 return true 838 } 839 840 case C_LOREG: 841 if b == C_ZOREG || b == C_SOREG { 842 return true 843 } 844 845 case C_SOREG: 846 if b == C_ZOREG { 847 return true 848 } 849 850 case C_ANY: 851 return true 852 } 853 854 return false 855 } 856 857 type ocmp []Optab 858 859 func (x ocmp) Len() int { 860 return len(x) 861 } 862 863 func (x ocmp) Swap(i, j int) { 864 x[i], x[j] = x[j], x[i] 865 } 866 867 func (x ocmp) Less(i, j int) bool { 868 p1 := &x[i] 869 p2 := &x[j] 870 n := int(p1.as) - int(p2.as) 871 if n != 0 { 872 return n < 0 873 } 874 n = int(p1.a1) - int(p2.a1) 875 if n != 0 { 876 return n < 0 877 } 878 n = int(p1.a2) - int(p2.a2) 879 if n != 0 { 880 return n < 0 881 } 882 n = int(p1.a3) - int(p2.a3) 883 if n != 0 { 884 return n < 0 885 } 886 n = int(p1.a4) - int(p2.a4) 887 if n != 0 { 888 return n < 0 889 } 890 return false 891 } 892 func opset(a, b obj.As) { 893 oprange[a&obj.AMask] = oprange[b&obj.AMask] 894 } 895 896 func buildop(ctxt *obj.Link) { 897 if oprange[AORW&obj.AMask] != nil { 898 // Already initialized; stop now. 899 // This happens in the cmd/asm tests, 900 // each of which re-initializes the arch. 901 return 902 } 903 904 for i := 0; i < C_NCLASS; i++ { 905 for n := 0; n < C_NCLASS; n++ { 906 if cmp(n, i) { 907 xcmp[i][n] = true 908 } 909 } 910 } 911 sort.Sort(ocmp(optab)) 912 for i := 0; i < len(optab); i++ { 913 r := optab[i].as 914 start := i 915 for ; i+1 < len(optab); i++ { 916 if optab[i+1].as != r { 917 break 918 } 919 } 920 oprange[r&obj.AMask] = optab[start : i+1] 921 922 // opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array. 923 // oprange[] is used by oplook() to find the Optab entry that applies to a given Prog. 924 switch r { 925 case AADD: 926 opset(AADDC, r) 927 opset(AADDW, r) 928 opset(AADDE, r) 929 opset(AMULLD, r) 930 opset(AMULLW, r) 931 case ADIVW: 932 opset(ADIVD, r) 933 opset(ADIVDU, r) 934 opset(ADIVWU, r) 935 opset(AMODD, r) 936 opset(AMODDU, r) 937 opset(AMODW, r) 938 opset(AMODWU, r) 939 case AMULHD: 940 opset(AMULHDU, r) 941 case AMOVBZ: 942 opset(AMOVH, r) 943 opset(AMOVHZ, r) 944 case ALA: 945 opset(ALAY, r) 946 case AMVC: 947 opset(AMVCIN, r) 948 opset(ACLC, r) 949 opset(AXC, r) 950 opset(AOC, r) 951 opset(ANC, r) 952 case ASTCK: 953 opset(ASTCKC, r) 954 opset(ASTCKE, r) 955 opset(ASTCKF, r) 956 case ALAAG: 957 opset(ALAA, r) 958 opset(ALAAL, r) 959 opset(ALAALG, r) 960 opset(ALAN, r) 961 opset(ALANG, r) 962 opset(ALAX, r) 963 opset(ALAXG, r) 964 opset(ALAO, r) 965 opset(ALAOG, r) 966 case ASTMG: 967 opset(ASTMY, r) 968 case ALMG: 969 opset(ALMY, r) 970 case ABEQ: 971 opset(ABGE, r) 972 opset(ABGT, r) 973 opset(ABLE, r) 974 opset(ABLT, r) 975 opset(ABNE, r) 976 opset(ABVC, r) 977 opset(ABVS, r) 978 opset(ABLEU, r) 979 opset(ABLTU, r) 980 case ABR: 981 opset(ABL, r) 982 case ABC: 983 opset(ABCL, r) 984 case AFABS: 985 opset(AFNABS, r) 986 opset(ALPDFR, r) 987 opset(ALNDFR, r) 988 opset(AFNEG, r) 989 opset(AFNEGS, r) 990 opset(ALEDBR, r) 991 opset(ALDEBR, r) 992 opset(AFSQRT, r) 993 opset(AFSQRTS, r) 994 case AFADD: 995 opset(AFADDS, r) 996 opset(AFDIV, r) 997 opset(AFDIVS, r) 998 opset(AFSUB, r) 999 opset(AFSUBS, r) 1000 case AFMADD: 1001 opset(AFMADDS, r) 1002 opset(AFMSUB, r) 1003 opset(AFMSUBS, r) 1004 case AFMUL: 1005 opset(AFMULS, r) 1006 case AFCMPO: 1007 opset(AFCMPU, r) 1008 opset(ACEBR, r) 1009 case AAND: 1010 opset(AOR, r) 1011 opset(AXOR, r) 1012 case AANDW: 1013 opset(AORW, r) 1014 opset(AXORW, r) 1015 case ASLD: 1016 opset(ASRD, r) 1017 opset(ASLW, r) 1018 opset(ASRW, r) 1019 opset(ASRAD, r) 1020 opset(ASRAW, r) 1021 opset(ARLL, r) 1022 opset(ARLLG, r) 1023 case ARNSBG: 1024 opset(ARXSBG, r) 1025 opset(AROSBG, r) 1026 opset(ARNSBGT, r) 1027 opset(ARXSBGT, r) 1028 opset(AROSBGT, r) 1029 opset(ARISBG, r) 1030 opset(ARISBGN, r) 1031 opset(ARISBGZ, r) 1032 opset(ARISBGNZ, r) 1033 opset(ARISBHG, r) 1034 opset(ARISBLG, r) 1035 opset(ARISBHGZ, r) 1036 opset(ARISBLGZ, r) 1037 case ACSG: 1038 opset(ACS, r) 1039 case ASUB: 1040 opset(ASUBC, r) 1041 opset(ASUBE, r) 1042 opset(ASUBW, r) 1043 case ANEG: 1044 opset(ANEGW, r) 1045 case AFMOVD: 1046 opset(AFMOVS, r) 1047 case AMOVDBR: 1048 opset(AMOVWBR, r) 1049 case ACMP: 1050 opset(ACMPW, r) 1051 case ACMPU: 1052 opset(ACMPWU, r) 1053 case ATMHH: 1054 opset(ATMHL, r) 1055 opset(ATMLH, r) 1056 opset(ATMLL, r) 1057 case ACEFBRA: 1058 opset(ACDFBRA, r) 1059 opset(ACEGBRA, r) 1060 opset(ACDGBRA, r) 1061 opset(ACELFBR, r) 1062 opset(ACDLFBR, r) 1063 opset(ACELGBR, r) 1064 opset(ACDLGBR, r) 1065 case ACFEBRA: 1066 opset(ACFDBRA, r) 1067 opset(ACGEBRA, r) 1068 opset(ACGDBRA, r) 1069 opset(ACLFEBR, r) 1070 opset(ACLFDBR, r) 1071 opset(ACLGEBR, r) 1072 opset(ACLGDBR, r) 1073 case AFIEBR: 1074 opset(AFIDBR, r) 1075 case ACMPBEQ: 1076 opset(ACMPBGE, r) 1077 opset(ACMPBGT, r) 1078 opset(ACMPBLE, r) 1079 opset(ACMPBLT, r) 1080 opset(ACMPBNE, r) 1081 case ACMPUBEQ: 1082 opset(ACMPUBGE, r) 1083 opset(ACMPUBGT, r) 1084 opset(ACMPUBLE, r) 1085 opset(ACMPUBLT, r) 1086 opset(ACMPUBNE, r) 1087 case ACGRJ: 1088 opset(ACRJ, r) 1089 case ACLGRJ: 1090 opset(ACLRJ, r) 1091 case ACGIJ: 1092 opset(ACIJ, r) 1093 case ACLGIJ: 1094 opset(ACLIJ, r) 1095 case AMOVDEQ: 1096 opset(AMOVDGE, r) 1097 opset(AMOVDGT, r) 1098 opset(AMOVDLE, r) 1099 opset(AMOVDLT, r) 1100 opset(AMOVDNE, r) 1101 case ALOCGR: 1102 opset(ALOCR, r) 1103 case ALTDBR: 1104 opset(ALTEBR, r) 1105 case ATCDB: 1106 opset(ATCEB, r) 1107 case AVL: 1108 opset(AVLLEZB, r) 1109 opset(AVLLEZH, r) 1110 opset(AVLLEZF, r) 1111 opset(AVLLEZG, r) 1112 opset(AVLREPB, r) 1113 opset(AVLREPH, r) 1114 opset(AVLREPF, r) 1115 opset(AVLREPG, r) 1116 case AVLEG: 1117 opset(AVLBB, r) 1118 opset(AVLEB, r) 1119 opset(AVLEH, r) 1120 opset(AVLEF, r) 1121 opset(AVLEG, r) 1122 opset(AVLREP, r) 1123 case AVSTEG: 1124 opset(AVSTEB, r) 1125 opset(AVSTEH, r) 1126 opset(AVSTEF, r) 1127 case AVSCEG: 1128 opset(AVSCEF, r) 1129 case AVGEG: 1130 opset(AVGEF, r) 1131 case AVESLG: 1132 opset(AVESLB, r) 1133 opset(AVESLH, r) 1134 opset(AVESLF, r) 1135 opset(AVERLLB, r) 1136 opset(AVERLLH, r) 1137 opset(AVERLLF, r) 1138 opset(AVERLLG, r) 1139 opset(AVESRAB, r) 1140 opset(AVESRAH, r) 1141 opset(AVESRAF, r) 1142 opset(AVESRAG, r) 1143 opset(AVESRLB, r) 1144 opset(AVESRLH, r) 1145 opset(AVESRLF, r) 1146 opset(AVESRLG, r) 1147 case AVLGVG: 1148 opset(AVLGVB, r) 1149 opset(AVLGVH, r) 1150 opset(AVLGVF, r) 1151 case AVLVGG: 1152 opset(AVLVGB, r) 1153 opset(AVLVGH, r) 1154 opset(AVLVGF, r) 1155 case AVZERO: 1156 opset(AVONE, r) 1157 case AVREPIG: 1158 opset(AVREPIB, r) 1159 opset(AVREPIH, r) 1160 opset(AVREPIF, r) 1161 case AVLEIG: 1162 opset(AVLEIB, r) 1163 opset(AVLEIH, r) 1164 opset(AVLEIF, r) 1165 case AVGMG: 1166 opset(AVGMB, r) 1167 opset(AVGMH, r) 1168 opset(AVGMF, r) 1169 case AVREPG: 1170 opset(AVREPB, r) 1171 opset(AVREPH, r) 1172 opset(AVREPF, r) 1173 case AVERIMG: 1174 opset(AVERIMB, r) 1175 opset(AVERIMH, r) 1176 opset(AVERIMF, r) 1177 case AVFTCIDB: 1178 opset(AWFTCIDB, r) 1179 case AVLR: 1180 opset(AVUPHB, r) 1181 opset(AVUPHH, r) 1182 opset(AVUPHF, r) 1183 opset(AVUPLHB, r) 1184 opset(AVUPLHH, r) 1185 opset(AVUPLHF, r) 1186 opset(AVUPLB, r) 1187 opset(AVUPLHW, r) 1188 opset(AVUPLF, r) 1189 opset(AVUPLLB, r) 1190 opset(AVUPLLH, r) 1191 opset(AVUPLLF, r) 1192 opset(AVCLZB, r) 1193 opset(AVCLZH, r) 1194 opset(AVCLZF, r) 1195 opset(AVCLZG, r) 1196 opset(AVCTZB, r) 1197 opset(AVCTZH, r) 1198 opset(AVCTZF, r) 1199 opset(AVCTZG, r) 1200 opset(AVLDEB, r) 1201 opset(AWLDEB, r) 1202 opset(AVFLCDB, r) 1203 opset(AWFLCDB, r) 1204 opset(AVFLNDB, r) 1205 opset(AWFLNDB, r) 1206 opset(AVFLPDB, r) 1207 opset(AWFLPDB, r) 1208 opset(AVFSQDB, r) 1209 opset(AWFSQDB, r) 1210 opset(AVISTRB, r) 1211 opset(AVISTRH, r) 1212 opset(AVISTRF, r) 1213 opset(AVISTRBS, r) 1214 opset(AVISTRHS, r) 1215 opset(AVISTRFS, r) 1216 opset(AVLCB, r) 1217 opset(AVLCH, r) 1218 opset(AVLCF, r) 1219 opset(AVLCG, r) 1220 opset(AVLPB, r) 1221 opset(AVLPH, r) 1222 opset(AVLPF, r) 1223 opset(AVLPG, r) 1224 opset(AVPOPCT, r) 1225 opset(AVSEGB, r) 1226 opset(AVSEGH, r) 1227 opset(AVSEGF, r) 1228 case AVECG: 1229 opset(AVECB, r) 1230 opset(AVECH, r) 1231 opset(AVECF, r) 1232 opset(AVECLB, r) 1233 opset(AVECLH, r) 1234 opset(AVECLF, r) 1235 opset(AVECLG, r) 1236 opset(AWFCDB, r) 1237 opset(AWFKDB, r) 1238 case AVCEQG: 1239 opset(AVCEQB, r) 1240 opset(AVCEQH, r) 1241 opset(AVCEQF, r) 1242 opset(AVCEQBS, r) 1243 opset(AVCEQHS, r) 1244 opset(AVCEQFS, r) 1245 opset(AVCEQGS, r) 1246 opset(AVCHB, r) 1247 opset(AVCHH, r) 1248 opset(AVCHF, r) 1249 opset(AVCHG, r) 1250 opset(AVCHBS, r) 1251 opset(AVCHHS, r) 1252 opset(AVCHFS, r) 1253 opset(AVCHGS, r) 1254 opset(AVCHLB, r) 1255 opset(AVCHLH, r) 1256 opset(AVCHLF, r) 1257 opset(AVCHLG, r) 1258 opset(AVCHLBS, r) 1259 opset(AVCHLHS, r) 1260 opset(AVCHLFS, r) 1261 opset(AVCHLGS, r) 1262 case AVFAEF: 1263 opset(AVFAEB, r) 1264 opset(AVFAEH, r) 1265 opset(AVFAEBS, r) 1266 opset(AVFAEHS, r) 1267 opset(AVFAEFS, r) 1268 opset(AVFAEZB, r) 1269 opset(AVFAEZH, r) 1270 opset(AVFAEZF, r) 1271 opset(AVFAEZBS, r) 1272 opset(AVFAEZHS, r) 1273 opset(AVFAEZFS, r) 1274 opset(AVFEEB, r) 1275 opset(AVFEEH, r) 1276 opset(AVFEEF, r) 1277 opset(AVFEEBS, r) 1278 opset(AVFEEHS, r) 1279 opset(AVFEEFS, r) 1280 opset(AVFEEZB, r) 1281 opset(AVFEEZH, r) 1282 opset(AVFEEZF, r) 1283 opset(AVFEEZBS, r) 1284 opset(AVFEEZHS, r) 1285 opset(AVFEEZFS, r) 1286 opset(AVFENEB, r) 1287 opset(AVFENEH, r) 1288 opset(AVFENEF, r) 1289 opset(AVFENEBS, r) 1290 opset(AVFENEHS, r) 1291 opset(AVFENEFS, r) 1292 opset(AVFENEZB, r) 1293 opset(AVFENEZH, r) 1294 opset(AVFENEZF, r) 1295 opset(AVFENEZBS, r) 1296 opset(AVFENEZHS, r) 1297 opset(AVFENEZFS, r) 1298 case AVPKSG: 1299 opset(AVPKSH, r) 1300 opset(AVPKSF, r) 1301 opset(AVPKSHS, r) 1302 opset(AVPKSFS, r) 1303 opset(AVPKSGS, r) 1304 opset(AVPKLSH, r) 1305 opset(AVPKLSF, r) 1306 opset(AVPKLSG, r) 1307 opset(AVPKLSHS, r) 1308 opset(AVPKLSFS, r) 1309 opset(AVPKLSGS, r) 1310 case AVAQ: 1311 opset(AVAB, r) 1312 opset(AVAH, r) 1313 opset(AVAF, r) 1314 opset(AVAG, r) 1315 opset(AVACCB, r) 1316 opset(AVACCH, r) 1317 opset(AVACCF, r) 1318 opset(AVACCG, r) 1319 opset(AVACCQ, r) 1320 opset(AVN, r) 1321 opset(AVNC, r) 1322 opset(AVAVGB, r) 1323 opset(AVAVGH, r) 1324 opset(AVAVGF, r) 1325 opset(AVAVGG, r) 1326 opset(AVAVGLB, r) 1327 opset(AVAVGLH, r) 1328 opset(AVAVGLF, r) 1329 opset(AVAVGLG, r) 1330 opset(AVCKSM, r) 1331 opset(AVX, r) 1332 opset(AVFADB, r) 1333 opset(AWFADB, r) 1334 opset(AVFCEDB, r) 1335 opset(AVFCEDBS, r) 1336 opset(AWFCEDB, r) 1337 opset(AWFCEDBS, r) 1338 opset(AVFCHDB, r) 1339 opset(AVFCHDBS, r) 1340 opset(AWFCHDB, r) 1341 opset(AWFCHDBS, r) 1342 opset(AVFCHEDB, r) 1343 opset(AVFCHEDBS, r) 1344 opset(AWFCHEDB, r) 1345 opset(AWFCHEDBS, r) 1346 opset(AVFMDB, r) 1347 opset(AWFMDB, r) 1348 opset(AVGFMB, r) 1349 opset(AVGFMH, r) 1350 opset(AVGFMF, r) 1351 opset(AVGFMG, r) 1352 opset(AVMXB, r) 1353 opset(AVMXH, r) 1354 opset(AVMXF, r) 1355 opset(AVMXG, r) 1356 opset(AVMXLB, r) 1357 opset(AVMXLH, r) 1358 opset(AVMXLF, r) 1359 opset(AVMXLG, r) 1360 opset(AVMNB, r) 1361 opset(AVMNH, r) 1362 opset(AVMNF, r) 1363 opset(AVMNG, r) 1364 opset(AVMNLB, r) 1365 opset(AVMNLH, r) 1366 opset(AVMNLF, r) 1367 opset(AVMNLG, r) 1368 opset(AVMRHB, r) 1369 opset(AVMRHH, r) 1370 opset(AVMRHF, r) 1371 opset(AVMRHG, r) 1372 opset(AVMRLB, r) 1373 opset(AVMRLH, r) 1374 opset(AVMRLF, r) 1375 opset(AVMRLG, r) 1376 opset(AVMEB, r) 1377 opset(AVMEH, r) 1378 opset(AVMEF, r) 1379 opset(AVMLEB, r) 1380 opset(AVMLEH, r) 1381 opset(AVMLEF, r) 1382 opset(AVMOB, r) 1383 opset(AVMOH, r) 1384 opset(AVMOF, r) 1385 opset(AVMLOB, r) 1386 opset(AVMLOH, r) 1387 opset(AVMLOF, r) 1388 opset(AVMHB, r) 1389 opset(AVMHH, r) 1390 opset(AVMHF, r) 1391 opset(AVMLHB, r) 1392 opset(AVMLHH, r) 1393 opset(AVMLHF, r) 1394 opset(AVMLH, r) 1395 opset(AVMLHW, r) 1396 opset(AVMLF, r) 1397 opset(AVNO, r) 1398 opset(AVO, r) 1399 opset(AVPKH, r) 1400 opset(AVPKF, r) 1401 opset(AVPKG, r) 1402 opset(AVSUMGH, r) 1403 opset(AVSUMGF, r) 1404 opset(AVSUMQF, r) 1405 opset(AVSUMQG, r) 1406 opset(AVSUMB, r) 1407 opset(AVSUMH, r) 1408 case AVERLLVG: 1409 opset(AVERLLVB, r) 1410 opset(AVERLLVH, r) 1411 opset(AVERLLVF, r) 1412 opset(AVESLVB, r) 1413 opset(AVESLVH, r) 1414 opset(AVESLVF, r) 1415 opset(AVESLVG, r) 1416 opset(AVESRAVB, r) 1417 opset(AVESRAVH, r) 1418 opset(AVESRAVF, r) 1419 opset(AVESRAVG, r) 1420 opset(AVESRLVB, r) 1421 opset(AVESRLVH, r) 1422 opset(AVESRLVF, r) 1423 opset(AVESRLVG, r) 1424 opset(AVFDDB, r) 1425 opset(AWFDDB, r) 1426 opset(AVFSDB, r) 1427 opset(AWFSDB, r) 1428 opset(AVSL, r) 1429 opset(AVSLB, r) 1430 opset(AVSRA, r) 1431 opset(AVSRAB, r) 1432 opset(AVSRL, r) 1433 opset(AVSRLB, r) 1434 opset(AVSB, r) 1435 opset(AVSH, r) 1436 opset(AVSF, r) 1437 opset(AVSG, r) 1438 opset(AVSQ, r) 1439 opset(AVSCBIB, r) 1440 opset(AVSCBIH, r) 1441 opset(AVSCBIF, r) 1442 opset(AVSCBIG, r) 1443 opset(AVSCBIQ, r) 1444 case AVACQ: 1445 opset(AVACCCQ, r) 1446 opset(AVGFMAB, r) 1447 opset(AVGFMAH, r) 1448 opset(AVGFMAF, r) 1449 opset(AVGFMAG, r) 1450 opset(AVMALB, r) 1451 opset(AVMALHW, r) 1452 opset(AVMALF, r) 1453 opset(AVMAHB, r) 1454 opset(AVMAHH, r) 1455 opset(AVMAHF, r) 1456 opset(AVMALHB, r) 1457 opset(AVMALHH, r) 1458 opset(AVMALHF, r) 1459 opset(AVMAEB, r) 1460 opset(AVMAEH, r) 1461 opset(AVMAEF, r) 1462 opset(AVMALEB, r) 1463 opset(AVMALEH, r) 1464 opset(AVMALEF, r) 1465 opset(AVMAOB, r) 1466 opset(AVMAOH, r) 1467 opset(AVMAOF, r) 1468 opset(AVMALOB, r) 1469 opset(AVMALOH, r) 1470 opset(AVMALOF, r) 1471 opset(AVSTRCB, r) 1472 opset(AVSTRCH, r) 1473 opset(AVSTRCF, r) 1474 opset(AVSTRCBS, r) 1475 opset(AVSTRCHS, r) 1476 opset(AVSTRCFS, r) 1477 opset(AVSTRCZB, r) 1478 opset(AVSTRCZH, r) 1479 opset(AVSTRCZF, r) 1480 opset(AVSTRCZBS, r) 1481 opset(AVSTRCZHS, r) 1482 opset(AVSTRCZFS, r) 1483 opset(AVSBCBIQ, r) 1484 opset(AVSBIQ, r) 1485 opset(AVMSLG, r) 1486 opset(AVMSLEG, r) 1487 opset(AVMSLOG, r) 1488 opset(AVMSLEOG, r) 1489 case AVSEL: 1490 opset(AVFMADB, r) 1491 opset(AWFMADB, r) 1492 opset(AVFMSDB, r) 1493 opset(AWFMSDB, r) 1494 opset(AVPERM, r) 1495 case AKM: 1496 opset(AKMC, r) 1497 opset(AKLMD, r) 1498 opset(AKIMD, r) 1499 case AKMA: 1500 opset(AKMCTR, r) 1501 } 1502 } 1503 } 1504 1505 const ( 1506 op_A uint32 = 0x5A00 // FORMAT_RX1 ADD (32) 1507 op_AD uint32 = 0x6A00 // FORMAT_RX1 ADD NORMALIZED (long HFP) 1508 op_ADB uint32 = 0xED1A // FORMAT_RXE ADD (long BFP) 1509 op_ADBR uint32 = 0xB31A // FORMAT_RRE ADD (long BFP) 1510 op_ADR uint32 = 0x2A00 // FORMAT_RR ADD NORMALIZED (long HFP) 1511 op_ADTR uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1512 op_ADTRA uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1513 op_AE uint32 = 0x7A00 // FORMAT_RX1 ADD NORMALIZED (short HFP) 1514 op_AEB uint32 = 0xED0A // FORMAT_RXE ADD (short BFP) 1515 op_AEBR uint32 = 0xB30A // FORMAT_RRE ADD (short BFP) 1516 op_AER uint32 = 0x3A00 // FORMAT_RR ADD NORMALIZED (short HFP) 1517 op_AFI uint32 = 0xC209 // FORMAT_RIL1 ADD IMMEDIATE (32) 1518 op_AG uint32 = 0xE308 // FORMAT_RXY1 ADD (64) 1519 op_AGF uint32 = 0xE318 // FORMAT_RXY1 ADD (64<-32) 1520 op_AGFI uint32 = 0xC208 // FORMAT_RIL1 ADD IMMEDIATE (64<-32) 1521 op_AGFR uint32 = 0xB918 // FORMAT_RRE ADD (64<-32) 1522 op_AGHI uint32 = 0xA70B // FORMAT_RI1 ADD HALFWORD IMMEDIATE (64) 1523 op_AGHIK uint32 = 0xECD9 // FORMAT_RIE4 ADD IMMEDIATE (64<-16) 1524 op_AGR uint32 = 0xB908 // FORMAT_RRE ADD (64) 1525 op_AGRK uint32 = 0xB9E8 // FORMAT_RRF1 ADD (64) 1526 op_AGSI uint32 = 0xEB7A // FORMAT_SIY ADD IMMEDIATE (64<-8) 1527 op_AH uint32 = 0x4A00 // FORMAT_RX1 ADD HALFWORD 1528 op_AHHHR uint32 = 0xB9C8 // FORMAT_RRF1 ADD HIGH (32) 1529 op_AHHLR uint32 = 0xB9D8 // FORMAT_RRF1 ADD HIGH (32) 1530 op_AHI uint32 = 0xA70A // FORMAT_RI1 ADD HALFWORD IMMEDIATE (32) 1531 op_AHIK uint32 = 0xECD8 // FORMAT_RIE4 ADD IMMEDIATE (32<-16) 1532 op_AHY uint32 = 0xE37A // FORMAT_RXY1 ADD HALFWORD 1533 op_AIH uint32 = 0xCC08 // FORMAT_RIL1 ADD IMMEDIATE HIGH (32) 1534 op_AL uint32 = 0x5E00 // FORMAT_RX1 ADD LOGICAL (32) 1535 op_ALC uint32 = 0xE398 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (32) 1536 op_ALCG uint32 = 0xE388 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (64) 1537 op_ALCGR uint32 = 0xB988 // FORMAT_RRE ADD LOGICAL WITH CARRY (64) 1538 op_ALCR uint32 = 0xB998 // FORMAT_RRE ADD LOGICAL WITH CARRY (32) 1539 op_ALFI uint32 = 0xC20B // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (32) 1540 op_ALG uint32 = 0xE30A // FORMAT_RXY1 ADD LOGICAL (64) 1541 op_ALGF uint32 = 0xE31A // FORMAT_RXY1 ADD LOGICAL (64<-32) 1542 op_ALGFI uint32 = 0xC20A // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (64<-32) 1543 op_ALGFR uint32 = 0xB91A // FORMAT_RRE ADD LOGICAL (64<-32) 1544 op_ALGHSIK uint32 = 0xECDB // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16) 1545 op_ALGR uint32 = 0xB90A // FORMAT_RRE ADD LOGICAL (64) 1546 op_ALGRK uint32 = 0xB9EA // FORMAT_RRF1 ADD LOGICAL (64) 1547 op_ALGSI uint32 = 0xEB7E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8) 1548 op_ALHHHR uint32 = 0xB9CA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1549 op_ALHHLR uint32 = 0xB9DA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1550 op_ALHSIK uint32 = 0xECDA // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16) 1551 op_ALR uint32 = 0x1E00 // FORMAT_RR ADD LOGICAL (32) 1552 op_ALRK uint32 = 0xB9FA // FORMAT_RRF1 ADD LOGICAL (32) 1553 op_ALSI uint32 = 0xEB6E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8) 1554 op_ALSIH uint32 = 0xCC0A // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1555 op_ALSIHN uint32 = 0xCC0B // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1556 op_ALY uint32 = 0xE35E // FORMAT_RXY1 ADD LOGICAL (32) 1557 op_AP uint32 = 0xFA00 // FORMAT_SS2 ADD DECIMAL 1558 op_AR uint32 = 0x1A00 // FORMAT_RR ADD (32) 1559 op_ARK uint32 = 0xB9F8 // FORMAT_RRF1 ADD (32) 1560 op_ASI uint32 = 0xEB6A // FORMAT_SIY ADD IMMEDIATE (32<-8) 1561 op_AU uint32 = 0x7E00 // FORMAT_RX1 ADD UNNORMALIZED (short HFP) 1562 op_AUR uint32 = 0x3E00 // FORMAT_RR ADD UNNORMALIZED (short HFP) 1563 op_AW uint32 = 0x6E00 // FORMAT_RX1 ADD UNNORMALIZED (long HFP) 1564 op_AWR uint32 = 0x2E00 // FORMAT_RR ADD UNNORMALIZED (long HFP) 1565 op_AXBR uint32 = 0xB34A // FORMAT_RRE ADD (extended BFP) 1566 op_AXR uint32 = 0x3600 // FORMAT_RR ADD NORMALIZED (extended HFP) 1567 op_AXTR uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1568 op_AXTRA uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1569 op_AY uint32 = 0xE35A // FORMAT_RXY1 ADD (32) 1570 op_BAKR uint32 = 0xB240 // FORMAT_RRE BRANCH AND STACK 1571 op_BAL uint32 = 0x4500 // FORMAT_RX1 BRANCH AND LINK 1572 op_BALR uint32 = 0x0500 // FORMAT_RR BRANCH AND LINK 1573 op_BAS uint32 = 0x4D00 // FORMAT_RX1 BRANCH AND SAVE 1574 op_BASR uint32 = 0x0D00 // FORMAT_RR BRANCH AND SAVE 1575 op_BASSM uint32 = 0x0C00 // FORMAT_RR BRANCH AND SAVE AND SET MODE 1576 op_BC uint32 = 0x4700 // FORMAT_RX2 BRANCH ON CONDITION 1577 op_BCR uint32 = 0x0700 // FORMAT_RR BRANCH ON CONDITION 1578 op_BCT uint32 = 0x4600 // FORMAT_RX1 BRANCH ON COUNT (32) 1579 op_BCTG uint32 = 0xE346 // FORMAT_RXY1 BRANCH ON COUNT (64) 1580 op_BCTGR uint32 = 0xB946 // FORMAT_RRE BRANCH ON COUNT (64) 1581 op_BCTR uint32 = 0x0600 // FORMAT_RR BRANCH ON COUNT (32) 1582 op_BPP uint32 = 0xC700 // FORMAT_SMI BRANCH PREDICTION PRELOAD 1583 op_BPRP uint32 = 0xC500 // FORMAT_MII BRANCH PREDICTION RELATIVE PRELOAD 1584 op_BRAS uint32 = 0xA705 // FORMAT_RI2 BRANCH RELATIVE AND SAVE 1585 op_BRASL uint32 = 0xC005 // FORMAT_RIL2 BRANCH RELATIVE AND SAVE LONG 1586 op_BRC uint32 = 0xA704 // FORMAT_RI3 BRANCH RELATIVE ON CONDITION 1587 op_BRCL uint32 = 0xC004 // FORMAT_RIL3 BRANCH RELATIVE ON CONDITION LONG 1588 op_BRCT uint32 = 0xA706 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (32) 1589 op_BRCTG uint32 = 0xA707 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (64) 1590 op_BRCTH uint32 = 0xCC06 // FORMAT_RIL2 BRANCH RELATIVE ON COUNT HIGH (32) 1591 op_BRXH uint32 = 0x8400 // FORMAT_RSI BRANCH RELATIVE ON INDEX HIGH (32) 1592 op_BRXHG uint32 = 0xEC44 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX HIGH (64) 1593 op_BRXLE uint32 = 0x8500 // FORMAT_RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32) 1594 op_BRXLG uint32 = 0xEC45 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX LOW OR EQ. (64) 1595 op_BSA uint32 = 0xB25A // FORMAT_RRE BRANCH AND SET AUTHORITY 1596 op_BSG uint32 = 0xB258 // FORMAT_RRE BRANCH IN SUBSPACE GROUP 1597 op_BSM uint32 = 0x0B00 // FORMAT_RR BRANCH AND SET MODE 1598 op_BXH uint32 = 0x8600 // FORMAT_RS1 BRANCH ON INDEX HIGH (32) 1599 op_BXHG uint32 = 0xEB44 // FORMAT_RSY1 BRANCH ON INDEX HIGH (64) 1600 op_BXLE uint32 = 0x8700 // FORMAT_RS1 BRANCH ON INDEX LOW OR EQUAL (32) 1601 op_BXLEG uint32 = 0xEB45 // FORMAT_RSY1 BRANCH ON INDEX LOW OR EQUAL (64) 1602 op_C uint32 = 0x5900 // FORMAT_RX1 COMPARE (32) 1603 op_CD uint32 = 0x6900 // FORMAT_RX1 COMPARE (long HFP) 1604 op_CDB uint32 = 0xED19 // FORMAT_RXE COMPARE (long BFP) 1605 op_CDBR uint32 = 0xB319 // FORMAT_RRE COMPARE (long BFP) 1606 op_CDFBR uint32 = 0xB395 // FORMAT_RRE CONVERT FROM FIXED (32 to long BFP) 1607 op_CDFBRA uint32 = 0xB395 // FORMAT_RRF5 CONVERT FROM FIXED (32 to long BFP) 1608 op_CDFR uint32 = 0xB3B5 // FORMAT_RRE CONVERT FROM FIXED (32 to long HFP) 1609 op_CDFTR uint32 = 0xB951 // FORMAT_RRE CONVERT FROM FIXED (32 to long DFP) 1610 op_CDGBR uint32 = 0xB3A5 // FORMAT_RRE CONVERT FROM FIXED (64 to long BFP) 1611 op_CDGBRA uint32 = 0xB3A5 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long BFP) 1612 op_CDGR uint32 = 0xB3C5 // FORMAT_RRE CONVERT FROM FIXED (64 to long HFP) 1613 op_CDGTR uint32 = 0xB3F1 // FORMAT_RRE CONVERT FROM FIXED (64 to long DFP) 1614 op_CDGTRA uint32 = 0xB3F1 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long DFP) 1615 op_CDLFBR uint32 = 0xB391 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long BFP) 1616 op_CDLFTR uint32 = 0xB953 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long DFP) 1617 op_CDLGBR uint32 = 0xB3A1 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long BFP) 1618 op_CDLGTR uint32 = 0xB952 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long DFP) 1619 op_CDR uint32 = 0x2900 // FORMAT_RR COMPARE (long HFP) 1620 op_CDS uint32 = 0xBB00 // FORMAT_RS1 COMPARE DOUBLE AND SWAP (32) 1621 op_CDSG uint32 = 0xEB3E // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (64) 1622 op_CDSTR uint32 = 0xB3F3 // FORMAT_RRE CONVERT FROM SIGNED PACKED (64 to long DFP) 1623 op_CDSY uint32 = 0xEB31 // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (32) 1624 op_CDTR uint32 = 0xB3E4 // FORMAT_RRE COMPARE (long DFP) 1625 op_CDUTR uint32 = 0xB3F2 // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP) 1626 op_CDZT uint32 = 0xEDAA // FORMAT_RSL CONVERT FROM ZONED (to long DFP) 1627 op_CE uint32 = 0x7900 // FORMAT_RX1 COMPARE (short HFP) 1628 op_CEB uint32 = 0xED09 // FORMAT_RXE COMPARE (short BFP) 1629 op_CEBR uint32 = 0xB309 // FORMAT_RRE COMPARE (short BFP) 1630 op_CEDTR uint32 = 0xB3F4 // FORMAT_RRE COMPARE BIASED EXPONENT (long DFP) 1631 op_CEFBR uint32 = 0xB394 // FORMAT_RRE CONVERT FROM FIXED (32 to short BFP) 1632 op_CEFBRA uint32 = 0xB394 // FORMAT_RRF5 CONVERT FROM FIXED (32 to short BFP) 1633 op_CEFR uint32 = 0xB3B4 // FORMAT_RRE CONVERT FROM FIXED (32 to short HFP) 1634 op_CEGBR uint32 = 0xB3A4 // FORMAT_RRE CONVERT FROM FIXED (64 to short BFP) 1635 op_CEGBRA uint32 = 0xB3A4 // FORMAT_RRF5 CONVERT FROM FIXED (64 to short BFP) 1636 op_CEGR uint32 = 0xB3C4 // FORMAT_RRE CONVERT FROM FIXED (64 to short HFP) 1637 op_CELFBR uint32 = 0xB390 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to short BFP) 1638 op_CELGBR uint32 = 0xB3A0 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to short BFP) 1639 op_CER uint32 = 0x3900 // FORMAT_RR COMPARE (short HFP) 1640 op_CEXTR uint32 = 0xB3FC // FORMAT_RRE COMPARE BIASED EXPONENT (extended DFP) 1641 op_CFC uint32 = 0xB21A // FORMAT_S COMPARE AND FORM CODEWORD 1642 op_CFDBR uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1643 op_CFDBRA uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1644 op_CFDR uint32 = 0xB3B9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 32) 1645 op_CFDTR uint32 = 0xB941 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 32) 1646 op_CFEBR uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1647 op_CFEBRA uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1648 op_CFER uint32 = 0xB3B8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 32) 1649 op_CFI uint32 = 0xC20D // FORMAT_RIL1 COMPARE IMMEDIATE (32) 1650 op_CFXBR uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1651 op_CFXBRA uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1652 op_CFXR uint32 = 0xB3BA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 32) 1653 op_CFXTR uint32 = 0xB949 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 32) 1654 op_CG uint32 = 0xE320 // FORMAT_RXY1 COMPARE (64) 1655 op_CGDBR uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1656 op_CGDBRA uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1657 op_CGDR uint32 = 0xB3C9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 64) 1658 op_CGDTR uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1659 op_CGDTRA uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1660 op_CGEBR uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1661 op_CGEBRA uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1662 op_CGER uint32 = 0xB3C8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 64) 1663 op_CGF uint32 = 0xE330 // FORMAT_RXY1 COMPARE (64<-32) 1664 op_CGFI uint32 = 0xC20C // FORMAT_RIL1 COMPARE IMMEDIATE (64<-32) 1665 op_CGFR uint32 = 0xB930 // FORMAT_RRE COMPARE (64<-32) 1666 op_CGFRL uint32 = 0xC60C // FORMAT_RIL2 COMPARE RELATIVE LONG (64<-32) 1667 op_CGH uint32 = 0xE334 // FORMAT_RXY1 COMPARE HALFWORD (64<-16) 1668 op_CGHI uint32 = 0xA70F // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (64<-16) 1669 op_CGHRL uint32 = 0xC604 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (64<-16) 1670 op_CGHSI uint32 = 0xE558 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (64<-16) 1671 op_CGIB uint32 = 0xECFC // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (64<-8) 1672 op_CGIJ uint32 = 0xEC7C // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8) 1673 op_CGIT uint32 = 0xEC70 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (64<-16) 1674 op_CGR uint32 = 0xB920 // FORMAT_RRE COMPARE (64) 1675 op_CGRB uint32 = 0xECE4 // FORMAT_RRS COMPARE AND BRANCH (64) 1676 op_CGRJ uint32 = 0xEC64 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (64) 1677 op_CGRL uint32 = 0xC608 // FORMAT_RIL2 COMPARE RELATIVE LONG (64) 1678 op_CGRT uint32 = 0xB960 // FORMAT_RRF3 COMPARE AND TRAP (64) 1679 op_CGXBR uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1680 op_CGXBRA uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1681 op_CGXR uint32 = 0xB3CA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 64) 1682 op_CGXTR uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1683 op_CGXTRA uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1684 op_CH uint32 = 0x4900 // FORMAT_RX1 COMPARE HALFWORD (32<-16) 1685 op_CHF uint32 = 0xE3CD // FORMAT_RXY1 COMPARE HIGH (32) 1686 op_CHHR uint32 = 0xB9CD // FORMAT_RRE COMPARE HIGH (32) 1687 op_CHHSI uint32 = 0xE554 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (16) 1688 op_CHI uint32 = 0xA70E // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (32<-16) 1689 op_CHLR uint32 = 0xB9DD // FORMAT_RRE COMPARE HIGH (32) 1690 op_CHRL uint32 = 0xC605 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (32<-16) 1691 op_CHSI uint32 = 0xE55C // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (32<-16) 1692 op_CHY uint32 = 0xE379 // FORMAT_RXY1 COMPARE HALFWORD (32<-16) 1693 op_CIB uint32 = 0xECFE // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (32<-8) 1694 op_CIH uint32 = 0xCC0D // FORMAT_RIL1 COMPARE IMMEDIATE HIGH (32) 1695 op_CIJ uint32 = 0xEC7E // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8) 1696 op_CIT uint32 = 0xEC72 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (32<-16) 1697 op_CKSM uint32 = 0xB241 // FORMAT_RRE CHECKSUM 1698 op_CL uint32 = 0x5500 // FORMAT_RX1 COMPARE LOGICAL (32) 1699 op_CLC uint32 = 0xD500 // FORMAT_SS1 COMPARE LOGICAL (character) 1700 op_CLCL uint32 = 0x0F00 // FORMAT_RR COMPARE LOGICAL LONG 1701 op_CLCLE uint32 = 0xA900 // FORMAT_RS1 COMPARE LOGICAL LONG EXTENDED 1702 op_CLCLU uint32 = 0xEB8F // FORMAT_RSY1 COMPARE LOGICAL LONG UNICODE 1703 op_CLFDBR uint32 = 0xB39D // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 32) 1704 op_CLFDTR uint32 = 0xB943 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 32) 1705 op_CLFEBR uint32 = 0xB39C // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 32) 1706 op_CLFHSI uint32 = 0xE55D // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (32<-16) 1707 op_CLFI uint32 = 0xC20F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (32) 1708 op_CLFIT uint32 = 0xEC73 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16) 1709 op_CLFXBR uint32 = 0xB39E // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 32) 1710 op_CLFXTR uint32 = 0xB94B // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 32) 1711 op_CLG uint32 = 0xE321 // FORMAT_RXY1 COMPARE LOGICAL (64) 1712 op_CLGDBR uint32 = 0xB3AD // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 64) 1713 op_CLGDTR uint32 = 0xB942 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 64) 1714 op_CLGEBR uint32 = 0xB3AC // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 64) 1715 op_CLGF uint32 = 0xE331 // FORMAT_RXY1 COMPARE LOGICAL (64<-32) 1716 op_CLGFI uint32 = 0xC20E // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (64<-32) 1717 op_CLGFR uint32 = 0xB931 // FORMAT_RRE COMPARE LOGICAL (64<-32) 1718 op_CLGFRL uint32 = 0xC60E // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-32) 1719 op_CLGHRL uint32 = 0xC606 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-16) 1720 op_CLGHSI uint32 = 0xE559 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (64<-16) 1721 op_CLGIB uint32 = 0xECFD // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8) 1722 op_CLGIJ uint32 = 0xEC7D // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (64<-8) 1723 op_CLGIT uint32 = 0xEC71 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16) 1724 op_CLGR uint32 = 0xB921 // FORMAT_RRE COMPARE LOGICAL (64) 1725 op_CLGRB uint32 = 0xECE5 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (64) 1726 op_CLGRJ uint32 = 0xEC65 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (64) 1727 op_CLGRL uint32 = 0xC60A // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64) 1728 op_CLGRT uint32 = 0xB961 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (64) 1729 op_CLGT uint32 = 0xEB2B // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (64) 1730 op_CLGXBR uint32 = 0xB3AE // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 64) 1731 op_CLGXTR uint32 = 0xB94A // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 64) 1732 op_CLHF uint32 = 0xE3CF // FORMAT_RXY1 COMPARE LOGICAL HIGH (32) 1733 op_CLHHR uint32 = 0xB9CF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1734 op_CLHHSI uint32 = 0xE555 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (16) 1735 op_CLHLR uint32 = 0xB9DF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1736 op_CLHRL uint32 = 0xC607 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32<-16) 1737 op_CLI uint32 = 0x9500 // FORMAT_SI COMPARE LOGICAL (immediate) 1738 op_CLIB uint32 = 0xECFF // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8) 1739 op_CLIH uint32 = 0xCC0F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE HIGH (32) 1740 op_CLIJ uint32 = 0xEC7F // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (32<-8) 1741 op_CLIY uint32 = 0xEB55 // FORMAT_SIY COMPARE LOGICAL (immediate) 1742 op_CLM uint32 = 0xBD00 // FORMAT_RS2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1743 op_CLMH uint32 = 0xEB20 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (high) 1744 op_CLMY uint32 = 0xEB21 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1745 op_CLR uint32 = 0x1500 // FORMAT_RR COMPARE LOGICAL (32) 1746 op_CLRB uint32 = 0xECF7 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (32) 1747 op_CLRJ uint32 = 0xEC77 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (32) 1748 op_CLRL uint32 = 0xC60F // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32) 1749 op_CLRT uint32 = 0xB973 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (32) 1750 op_CLST uint32 = 0xB25D // FORMAT_RRE COMPARE LOGICAL STRING 1751 op_CLT uint32 = 0xEB23 // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (32) 1752 op_CLY uint32 = 0xE355 // FORMAT_RXY1 COMPARE LOGICAL (32) 1753 op_CMPSC uint32 = 0xB263 // FORMAT_RRE COMPRESSION CALL 1754 op_CP uint32 = 0xF900 // FORMAT_SS2 COMPARE DECIMAL 1755 op_CPSDR uint32 = 0xB372 // FORMAT_RRF2 COPY SIGN (long) 1756 op_CPYA uint32 = 0xB24D // FORMAT_RRE COPY ACCESS 1757 op_CR uint32 = 0x1900 // FORMAT_RR COMPARE (32) 1758 op_CRB uint32 = 0xECF6 // FORMAT_RRS COMPARE AND BRANCH (32) 1759 op_CRDTE uint32 = 0xB98F // FORMAT_RRF2 COMPARE AND REPLACE DAT TABLE ENTRY 1760 op_CRJ uint32 = 0xEC76 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (32) 1761 op_CRL uint32 = 0xC60D // FORMAT_RIL2 COMPARE RELATIVE LONG (32) 1762 op_CRT uint32 = 0xB972 // FORMAT_RRF3 COMPARE AND TRAP (32) 1763 op_CS uint32 = 0xBA00 // FORMAT_RS1 COMPARE AND SWAP (32) 1764 op_CSCH uint32 = 0xB230 // FORMAT_S CLEAR SUBCHANNEL 1765 op_CSDTR uint32 = 0xB3E3 // FORMAT_RRF4 CONVERT TO SIGNED PACKED (long DFP to 64) 1766 op_CSG uint32 = 0xEB30 // FORMAT_RSY1 COMPARE AND SWAP (64) 1767 op_CSP uint32 = 0xB250 // FORMAT_RRE COMPARE AND SWAP AND PURGE 1768 op_CSPG uint32 = 0xB98A // FORMAT_RRE COMPARE AND SWAP AND PURGE 1769 op_CSST uint32 = 0xC802 // FORMAT_SSF COMPARE AND SWAP AND STORE 1770 op_CSXTR uint32 = 0xB3EB // FORMAT_RRF4 CONVERT TO SIGNED PACKED (extended DFP to 128) 1771 op_CSY uint32 = 0xEB14 // FORMAT_RSY1 COMPARE AND SWAP (32) 1772 op_CU12 uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-16 1773 op_CU14 uint32 = 0xB9B0 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-32 1774 op_CU21 uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-8 1775 op_CU24 uint32 = 0xB9B1 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-32 1776 op_CU41 uint32 = 0xB9B2 // FORMAT_RRE CONVERT UTF-32 TO UTF-8 1777 op_CU42 uint32 = 0xB9B3 // FORMAT_RRE CONVERT UTF-32 TO UTF-16 1778 op_CUDTR uint32 = 0xB3E2 // FORMAT_RRE CONVERT TO UNSIGNED PACKED (long DFP to 64) 1779 op_CUSE uint32 = 0xB257 // FORMAT_RRE COMPARE UNTIL SUBSTRING EQUAL 1780 op_CUTFU uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UNICODE 1781 op_CUUTF uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UNICODE TO UTF-8 1782 op_CUXTR uint32 = 0xB3EA // FORMAT_RRE CONVERT TO UNSIGNED PACKED (extended DFP to 128) 1783 op_CVB uint32 = 0x4F00 // FORMAT_RX1 CONVERT TO BINARY (32) 1784 op_CVBG uint32 = 0xE30E // FORMAT_RXY1 CONVERT TO BINARY (64) 1785 op_CVBY uint32 = 0xE306 // FORMAT_RXY1 CONVERT TO BINARY (32) 1786 op_CVD uint32 = 0x4E00 // FORMAT_RX1 CONVERT TO DECIMAL (32) 1787 op_CVDG uint32 = 0xE32E // FORMAT_RXY1 CONVERT TO DECIMAL (64) 1788 op_CVDY uint32 = 0xE326 // FORMAT_RXY1 CONVERT TO DECIMAL (32) 1789 op_CXBR uint32 = 0xB349 // FORMAT_RRE COMPARE (extended BFP) 1790 op_CXFBR uint32 = 0xB396 // FORMAT_RRE CONVERT FROM FIXED (32 to extended BFP) 1791 op_CXFBRA uint32 = 0xB396 // FORMAT_RRF5 CONVERT FROM FIXED (32 to extended BFP) 1792 op_CXFR uint32 = 0xB3B6 // FORMAT_RRE CONVERT FROM FIXED (32 to extended HFP) 1793 op_CXFTR uint32 = 0xB959 // FORMAT_RRE CONVERT FROM FIXED (32 to extended DFP) 1794 op_CXGBR uint32 = 0xB3A6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended BFP) 1795 op_CXGBRA uint32 = 0xB3A6 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended BFP) 1796 op_CXGR uint32 = 0xB3C6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended HFP) 1797 op_CXGTR uint32 = 0xB3F9 // FORMAT_RRE CONVERT FROM FIXED (64 to extended DFP) 1798 op_CXGTRA uint32 = 0xB3F9 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended DFP) 1799 op_CXLFBR uint32 = 0xB392 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended BFP) 1800 op_CXLFTR uint32 = 0xB95B // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended DFP) 1801 op_CXLGBR uint32 = 0xB3A2 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended BFP) 1802 op_CXLGTR uint32 = 0xB95A // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended DFP) 1803 op_CXR uint32 = 0xB369 // FORMAT_RRE COMPARE (extended HFP) 1804 op_CXSTR uint32 = 0xB3FB // FORMAT_RRE CONVERT FROM SIGNED PACKED (128 to extended DFP) 1805 op_CXTR uint32 = 0xB3EC // FORMAT_RRE COMPARE (extended DFP) 1806 op_CXUTR uint32 = 0xB3FA // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) 1807 op_CXZT uint32 = 0xEDAB // FORMAT_RSL CONVERT FROM ZONED (to extended DFP) 1808 op_CY uint32 = 0xE359 // FORMAT_RXY1 COMPARE (32) 1809 op_CZDT uint32 = 0xEDA8 // FORMAT_RSL CONVERT TO ZONED (from long DFP) 1810 op_CZXT uint32 = 0xEDA9 // FORMAT_RSL CONVERT TO ZONED (from extended DFP) 1811 op_D uint32 = 0x5D00 // FORMAT_RX1 DIVIDE (32<-64) 1812 op_DD uint32 = 0x6D00 // FORMAT_RX1 DIVIDE (long HFP) 1813 op_DDB uint32 = 0xED1D // FORMAT_RXE DIVIDE (long BFP) 1814 op_DDBR uint32 = 0xB31D // FORMAT_RRE DIVIDE (long BFP) 1815 op_DDR uint32 = 0x2D00 // FORMAT_RR DIVIDE (long HFP) 1816 op_DDTR uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1817 op_DDTRA uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1818 op_DE uint32 = 0x7D00 // FORMAT_RX1 DIVIDE (short HFP) 1819 op_DEB uint32 = 0xED0D // FORMAT_RXE DIVIDE (short BFP) 1820 op_DEBR uint32 = 0xB30D // FORMAT_RRE DIVIDE (short BFP) 1821 op_DER uint32 = 0x3D00 // FORMAT_RR DIVIDE (short HFP) 1822 op_DIDBR uint32 = 0xB35B // FORMAT_RRF2 DIVIDE TO INTEGER (long BFP) 1823 op_DIEBR uint32 = 0xB353 // FORMAT_RRF2 DIVIDE TO INTEGER (short BFP) 1824 op_DL uint32 = 0xE397 // FORMAT_RXY1 DIVIDE LOGICAL (32<-64) 1825 op_DLG uint32 = 0xE387 // FORMAT_RXY1 DIVIDE LOGICAL (64<-128) 1826 op_DLGR uint32 = 0xB987 // FORMAT_RRE DIVIDE LOGICAL (64<-128) 1827 op_DLR uint32 = 0xB997 // FORMAT_RRE DIVIDE LOGICAL (32<-64) 1828 op_DP uint32 = 0xFD00 // FORMAT_SS2 DIVIDE DECIMAL 1829 op_DR uint32 = 0x1D00 // FORMAT_RR DIVIDE (32<-64) 1830 op_DSG uint32 = 0xE30D // FORMAT_RXY1 DIVIDE SINGLE (64) 1831 op_DSGF uint32 = 0xE31D // FORMAT_RXY1 DIVIDE SINGLE (64<-32) 1832 op_DSGFR uint32 = 0xB91D // FORMAT_RRE DIVIDE SINGLE (64<-32) 1833 op_DSGR uint32 = 0xB90D // FORMAT_RRE DIVIDE SINGLE (64) 1834 op_DXBR uint32 = 0xB34D // FORMAT_RRE DIVIDE (extended BFP) 1835 op_DXR uint32 = 0xB22D // FORMAT_RRE DIVIDE (extended HFP) 1836 op_DXTR uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1837 op_DXTRA uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1838 op_EAR uint32 = 0xB24F // FORMAT_RRE EXTRACT ACCESS 1839 op_ECAG uint32 = 0xEB4C // FORMAT_RSY1 EXTRACT CACHE ATTRIBUTE 1840 op_ECTG uint32 = 0xC801 // FORMAT_SSF EXTRACT CPU TIME 1841 op_ED uint32 = 0xDE00 // FORMAT_SS1 EDIT 1842 op_EDMK uint32 = 0xDF00 // FORMAT_SS1 EDIT AND MARK 1843 op_EEDTR uint32 = 0xB3E5 // FORMAT_RRE EXTRACT BIASED EXPONENT (long DFP to 64) 1844 op_EEXTR uint32 = 0xB3ED // FORMAT_RRE EXTRACT BIASED EXPONENT (extended DFP to 64) 1845 op_EFPC uint32 = 0xB38C // FORMAT_RRE EXTRACT FPC 1846 op_EPAIR uint32 = 0xB99A // FORMAT_RRE EXTRACT PRIMARY ASN AND INSTANCE 1847 op_EPAR uint32 = 0xB226 // FORMAT_RRE EXTRACT PRIMARY ASN 1848 op_EPSW uint32 = 0xB98D // FORMAT_RRE EXTRACT PSW 1849 op_EREG uint32 = 0xB249 // FORMAT_RRE EXTRACT STACKED REGISTERS (32) 1850 op_EREGG uint32 = 0xB90E // FORMAT_RRE EXTRACT STACKED REGISTERS (64) 1851 op_ESAIR uint32 = 0xB99B // FORMAT_RRE EXTRACT SECONDARY ASN AND INSTANCE 1852 op_ESAR uint32 = 0xB227 // FORMAT_RRE EXTRACT SECONDARY ASN 1853 op_ESDTR uint32 = 0xB3E7 // FORMAT_RRE EXTRACT SIGNIFICANCE (long DFP) 1854 op_ESEA uint32 = 0xB99D // FORMAT_RRE EXTRACT AND SET EXTENDED AUTHORITY 1855 op_ESTA uint32 = 0xB24A // FORMAT_RRE EXTRACT STACKED STATE 1856 op_ESXTR uint32 = 0xB3EF // FORMAT_RRE EXTRACT SIGNIFICANCE (extended DFP) 1857 op_ETND uint32 = 0xB2EC // FORMAT_RRE EXTRACT TRANSACTION NESTING DEPTH 1858 op_EX uint32 = 0x4400 // FORMAT_RX1 EXECUTE 1859 op_EXRL uint32 = 0xC600 // FORMAT_RIL2 EXECUTE RELATIVE LONG 1860 op_FIDBR uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1861 op_FIDBRA uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1862 op_FIDR uint32 = 0xB37F // FORMAT_RRE LOAD FP INTEGER (long HFP) 1863 op_FIDTR uint32 = 0xB3D7 // FORMAT_RRF5 LOAD FP INTEGER (long DFP) 1864 op_FIEBR uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1865 op_FIEBRA uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1866 op_FIER uint32 = 0xB377 // FORMAT_RRE LOAD FP INTEGER (short HFP) 1867 op_FIXBR uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1868 op_FIXBRA uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1869 op_FIXR uint32 = 0xB367 // FORMAT_RRE LOAD FP INTEGER (extended HFP) 1870 op_FIXTR uint32 = 0xB3DF // FORMAT_RRF5 LOAD FP INTEGER (extended DFP) 1871 op_FLOGR uint32 = 0xB983 // FORMAT_RRE FIND LEFTMOST ONE 1872 op_HDR uint32 = 0x2400 // FORMAT_RR HALVE (long HFP) 1873 op_HER uint32 = 0x3400 // FORMAT_RR HALVE (short HFP) 1874 op_HSCH uint32 = 0xB231 // FORMAT_S HALT SUBCHANNEL 1875 op_IAC uint32 = 0xB224 // FORMAT_RRE INSERT ADDRESS SPACE CONTROL 1876 op_IC uint32 = 0x4300 // FORMAT_RX1 INSERT CHARACTER 1877 op_ICM uint32 = 0xBF00 // FORMAT_RS2 INSERT CHARACTERS UNDER MASK (low) 1878 op_ICMH uint32 = 0xEB80 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (high) 1879 op_ICMY uint32 = 0xEB81 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (low) 1880 op_ICY uint32 = 0xE373 // FORMAT_RXY1 INSERT CHARACTER 1881 op_IDTE uint32 = 0xB98E // FORMAT_RRF2 INVALIDATE DAT TABLE ENTRY 1882 op_IEDTR uint32 = 0xB3F6 // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to long DFP) 1883 op_IEXTR uint32 = 0xB3FE // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to extended DFP) 1884 op_IIHF uint32 = 0xC008 // FORMAT_RIL1 INSERT IMMEDIATE (high) 1885 op_IIHH uint32 = 0xA500 // FORMAT_RI1 INSERT IMMEDIATE (high high) 1886 op_IIHL uint32 = 0xA501 // FORMAT_RI1 INSERT IMMEDIATE (high low) 1887 op_IILF uint32 = 0xC009 // FORMAT_RIL1 INSERT IMMEDIATE (low) 1888 op_IILH uint32 = 0xA502 // FORMAT_RI1 INSERT IMMEDIATE (low high) 1889 op_IILL uint32 = 0xA503 // FORMAT_RI1 INSERT IMMEDIATE (low low) 1890 op_IPK uint32 = 0xB20B // FORMAT_S INSERT PSW KEY 1891 op_IPM uint32 = 0xB222 // FORMAT_RRE INSERT PROGRAM MASK 1892 op_IPTE uint32 = 0xB221 // FORMAT_RRF1 INVALIDATE PAGE TABLE ENTRY 1893 op_ISKE uint32 = 0xB229 // FORMAT_RRE INSERT STORAGE KEY EXTENDED 1894 op_IVSK uint32 = 0xB223 // FORMAT_RRE INSERT VIRTUAL STORAGE KEY 1895 op_KDB uint32 = 0xED18 // FORMAT_RXE COMPARE AND SIGNAL (long BFP) 1896 op_KDBR uint32 = 0xB318 // FORMAT_RRE COMPARE AND SIGNAL (long BFP) 1897 op_KDTR uint32 = 0xB3E0 // FORMAT_RRE COMPARE AND SIGNAL (long DFP) 1898 op_KEB uint32 = 0xED08 // FORMAT_RXE COMPARE AND SIGNAL (short BFP) 1899 op_KEBR uint32 = 0xB308 // FORMAT_RRE COMPARE AND SIGNAL (short BFP) 1900 op_KIMD uint32 = 0xB93E // FORMAT_RRE COMPUTE INTERMEDIATE MESSAGE DIGEST 1901 op_KLMD uint32 = 0xB93F // FORMAT_RRE COMPUTE LAST MESSAGE DIGEST 1902 op_KM uint32 = 0xB92E // FORMAT_RRE CIPHER MESSAGE 1903 op_KMAC uint32 = 0xB91E // FORMAT_RRE COMPUTE MESSAGE AUTHENTICATION CODE 1904 op_KMC uint32 = 0xB92F // FORMAT_RRE CIPHER MESSAGE WITH CHAINING 1905 op_KMA uint32 = 0xB929 // FORMAT_RRF2 CIPHER MESSAGE WITH AUTHENTICATION 1906 op_KMCTR uint32 = 0xB92D // FORMAT_RRF2 CIPHER MESSAGE WITH COUNTER 1907 op_KMF uint32 = 0xB92A // FORMAT_RRE CIPHER MESSAGE WITH CFB 1908 op_KMO uint32 = 0xB92B // FORMAT_RRE CIPHER MESSAGE WITH OFB 1909 op_KXBR uint32 = 0xB348 // FORMAT_RRE COMPARE AND SIGNAL (extended BFP) 1910 op_KXTR uint32 = 0xB3E8 // FORMAT_RRE COMPARE AND SIGNAL (extended DFP) 1911 op_L uint32 = 0x5800 // FORMAT_RX1 LOAD (32) 1912 op_LA uint32 = 0x4100 // FORMAT_RX1 LOAD ADDRESS 1913 op_LAA uint32 = 0xEBF8 // FORMAT_RSY1 LOAD AND ADD (32) 1914 op_LAAG uint32 = 0xEBE8 // FORMAT_RSY1 LOAD AND ADD (64) 1915 op_LAAL uint32 = 0xEBFA // FORMAT_RSY1 LOAD AND ADD LOGICAL (32) 1916 op_LAALG uint32 = 0xEBEA // FORMAT_RSY1 LOAD AND ADD LOGICAL (64) 1917 op_LAE uint32 = 0x5100 // FORMAT_RX1 LOAD ADDRESS EXTENDED 1918 op_LAEY uint32 = 0xE375 // FORMAT_RXY1 LOAD ADDRESS EXTENDED 1919 op_LAM uint32 = 0x9A00 // FORMAT_RS1 LOAD ACCESS MULTIPLE 1920 op_LAMY uint32 = 0xEB9A // FORMAT_RSY1 LOAD ACCESS MULTIPLE 1921 op_LAN uint32 = 0xEBF4 // FORMAT_RSY1 LOAD AND AND (32) 1922 op_LANG uint32 = 0xEBE4 // FORMAT_RSY1 LOAD AND AND (64) 1923 op_LAO uint32 = 0xEBF6 // FORMAT_RSY1 LOAD AND OR (32) 1924 op_LAOG uint32 = 0xEBE6 // FORMAT_RSY1 LOAD AND OR (64) 1925 op_LARL uint32 = 0xC000 // FORMAT_RIL2 LOAD ADDRESS RELATIVE LONG 1926 op_LASP uint32 = 0xE500 // FORMAT_SSE LOAD ADDRESS SPACE PARAMETERS 1927 op_LAT uint32 = 0xE39F // FORMAT_RXY1 LOAD AND TRAP (32L<-32) 1928 op_LAX uint32 = 0xEBF7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (32) 1929 op_LAXG uint32 = 0xEBE7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (64) 1930 op_LAY uint32 = 0xE371 // FORMAT_RXY1 LOAD ADDRESS 1931 op_LB uint32 = 0xE376 // FORMAT_RXY1 LOAD BYTE (32) 1932 op_LBH uint32 = 0xE3C0 // FORMAT_RXY1 LOAD BYTE HIGH (32<-8) 1933 op_LBR uint32 = 0xB926 // FORMAT_RRE LOAD BYTE (32) 1934 op_LCDBR uint32 = 0xB313 // FORMAT_RRE LOAD COMPLEMENT (long BFP) 1935 op_LCDFR uint32 = 0xB373 // FORMAT_RRE LOAD COMPLEMENT (long) 1936 op_LCDR uint32 = 0x2300 // FORMAT_RR LOAD COMPLEMENT (long HFP) 1937 op_LCEBR uint32 = 0xB303 // FORMAT_RRE LOAD COMPLEMENT (short BFP) 1938 op_LCER uint32 = 0x3300 // FORMAT_RR LOAD COMPLEMENT (short HFP) 1939 op_LCGFR uint32 = 0xB913 // FORMAT_RRE LOAD COMPLEMENT (64<-32) 1940 op_LCGR uint32 = 0xB903 // FORMAT_RRE LOAD COMPLEMENT (64) 1941 op_LCR uint32 = 0x1300 // FORMAT_RR LOAD COMPLEMENT (32) 1942 op_LCTL uint32 = 0xB700 // FORMAT_RS1 LOAD CONTROL (32) 1943 op_LCTLG uint32 = 0xEB2F // FORMAT_RSY1 LOAD CONTROL (64) 1944 op_LCXBR uint32 = 0xB343 // FORMAT_RRE LOAD COMPLEMENT (extended BFP) 1945 op_LCXR uint32 = 0xB363 // FORMAT_RRE LOAD COMPLEMENT (extended HFP) 1946 op_LD uint32 = 0x6800 // FORMAT_RX1 LOAD (long) 1947 op_LDE uint32 = 0xED24 // FORMAT_RXE LOAD LENGTHENED (short to long HFP) 1948 op_LDEB uint32 = 0xED04 // FORMAT_RXE LOAD LENGTHENED (short to long BFP) 1949 op_LDEBR uint32 = 0xB304 // FORMAT_RRE LOAD LENGTHENED (short to long BFP) 1950 op_LDER uint32 = 0xB324 // FORMAT_RRE LOAD LENGTHENED (short to long HFP) 1951 op_LDETR uint32 = 0xB3D4 // FORMAT_RRF4 LOAD LENGTHENED (short to long DFP) 1952 op_LDGR uint32 = 0xB3C1 // FORMAT_RRE LOAD FPR FROM GR (64 to long) 1953 op_LDR uint32 = 0x2800 // FORMAT_RR LOAD (long) 1954 op_LDXBR uint32 = 0xB345 // FORMAT_RRE LOAD ROUNDED (extended to long BFP) 1955 op_LDXBRA uint32 = 0xB345 // FORMAT_RRF5 LOAD ROUNDED (extended to long BFP) 1956 op_LDXR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1957 op_LDXTR uint32 = 0xB3DD // FORMAT_RRF5 LOAD ROUNDED (extended to long DFP) 1958 op_LDY uint32 = 0xED65 // FORMAT_RXY1 LOAD (long) 1959 op_LE uint32 = 0x7800 // FORMAT_RX1 LOAD (short) 1960 op_LEDBR uint32 = 0xB344 // FORMAT_RRE LOAD ROUNDED (long to short BFP) 1961 op_LEDBRA uint32 = 0xB344 // FORMAT_RRF5 LOAD ROUNDED (long to short BFP) 1962 op_LEDR uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1963 op_LEDTR uint32 = 0xB3D5 // FORMAT_RRF5 LOAD ROUNDED (long to short DFP) 1964 op_LER uint32 = 0x3800 // FORMAT_RR LOAD (short) 1965 op_LEXBR uint32 = 0xB346 // FORMAT_RRE LOAD ROUNDED (extended to short BFP) 1966 op_LEXBRA uint32 = 0xB346 // FORMAT_RRF5 LOAD ROUNDED (extended to short BFP) 1967 op_LEXR uint32 = 0xB366 // FORMAT_RRE LOAD ROUNDED (extended to short HFP) 1968 op_LEY uint32 = 0xED64 // FORMAT_RXY1 LOAD (short) 1969 op_LFAS uint32 = 0xB2BD // FORMAT_S LOAD FPC AND SIGNAL 1970 op_LFH uint32 = 0xE3CA // FORMAT_RXY1 LOAD HIGH (32) 1971 op_LFHAT uint32 = 0xE3C8 // FORMAT_RXY1 LOAD HIGH AND TRAP (32H<-32) 1972 op_LFPC uint32 = 0xB29D // FORMAT_S LOAD FPC 1973 op_LG uint32 = 0xE304 // FORMAT_RXY1 LOAD (64) 1974 op_LGAT uint32 = 0xE385 // FORMAT_RXY1 LOAD AND TRAP (64) 1975 op_LGB uint32 = 0xE377 // FORMAT_RXY1 LOAD BYTE (64) 1976 op_LGBR uint32 = 0xB906 // FORMAT_RRE LOAD BYTE (64) 1977 op_LGDR uint32 = 0xB3CD // FORMAT_RRE LOAD GR FROM FPR (long to 64) 1978 op_LGF uint32 = 0xE314 // FORMAT_RXY1 LOAD (64<-32) 1979 op_LGFI uint32 = 0xC001 // FORMAT_RIL1 LOAD IMMEDIATE (64<-32) 1980 op_LGFR uint32 = 0xB914 // FORMAT_RRE LOAD (64<-32) 1981 op_LGFRL uint32 = 0xC40C // FORMAT_RIL2 LOAD RELATIVE LONG (64<-32) 1982 op_LGH uint32 = 0xE315 // FORMAT_RXY1 LOAD HALFWORD (64) 1983 op_LGHI uint32 = 0xA709 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (64) 1984 op_LGHR uint32 = 0xB907 // FORMAT_RRE LOAD HALFWORD (64) 1985 op_LGHRL uint32 = 0xC404 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (64<-16) 1986 op_LGR uint32 = 0xB904 // FORMAT_RRE LOAD (64) 1987 op_LGRL uint32 = 0xC408 // FORMAT_RIL2 LOAD RELATIVE LONG (64) 1988 op_LH uint32 = 0x4800 // FORMAT_RX1 LOAD HALFWORD (32) 1989 op_LHH uint32 = 0xE3C4 // FORMAT_RXY1 LOAD HALFWORD HIGH (32<-16) 1990 op_LHI uint32 = 0xA708 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (32) 1991 op_LHR uint32 = 0xB927 // FORMAT_RRE LOAD HALFWORD (32) 1992 op_LHRL uint32 = 0xC405 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (32<-16) 1993 op_LHY uint32 = 0xE378 // FORMAT_RXY1 LOAD HALFWORD (32) 1994 op_LLC uint32 = 0xE394 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (32) 1995 op_LLCH uint32 = 0xE3C2 // FORMAT_RXY1 LOAD LOGICAL CHARACTER HIGH (32<-8) 1996 op_LLCR uint32 = 0xB994 // FORMAT_RRE LOAD LOGICAL CHARACTER (32) 1997 op_LLGC uint32 = 0xE390 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (64) 1998 op_LLGCR uint32 = 0xB984 // FORMAT_RRE LOAD LOGICAL CHARACTER (64) 1999 op_LLGF uint32 = 0xE316 // FORMAT_RXY1 LOAD LOGICAL (64<-32) 2000 op_LLGFAT uint32 = 0xE39D // FORMAT_RXY1 LOAD LOGICAL AND TRAP (64<-32) 2001 op_LLGFR uint32 = 0xB916 // FORMAT_RRE LOAD LOGICAL (64<-32) 2002 op_LLGFRL uint32 = 0xC40E // FORMAT_RIL2 LOAD LOGICAL RELATIVE LONG (64<-32) 2003 op_LLGH uint32 = 0xE391 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (64) 2004 op_LLGHR uint32 = 0xB985 // FORMAT_RRE LOAD LOGICAL HALFWORD (64) 2005 op_LLGHRL uint32 = 0xC406 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16) 2006 op_LLGT uint32 = 0xE317 // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS 2007 op_LLGTAT uint32 = 0xE39C // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31) 2008 op_LLGTR uint32 = 0xB917 // FORMAT_RRE LOAD LOGICAL THIRTY ONE BITS 2009 op_LLH uint32 = 0xE395 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (32) 2010 op_LLHH uint32 = 0xE3C6 // FORMAT_RXY1 LOAD LOGICAL HALFWORD HIGH (32<-16) 2011 op_LLHR uint32 = 0xB995 // FORMAT_RRE LOAD LOGICAL HALFWORD (32) 2012 op_LLHRL uint32 = 0xC402 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16) 2013 op_LLIHF uint32 = 0xC00E // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (high) 2014 op_LLIHH uint32 = 0xA50C // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high high) 2015 op_LLIHL uint32 = 0xA50D // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high low) 2016 op_LLILF uint32 = 0xC00F // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (low) 2017 op_LLILH uint32 = 0xA50E // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low high) 2018 op_LLILL uint32 = 0xA50F // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low low) 2019 op_LM uint32 = 0x9800 // FORMAT_RS1 LOAD MULTIPLE (32) 2020 op_LMD uint32 = 0xEF00 // FORMAT_SS5 LOAD MULTIPLE DISJOINT 2021 op_LMG uint32 = 0xEB04 // FORMAT_RSY1 LOAD MULTIPLE (64) 2022 op_LMH uint32 = 0xEB96 // FORMAT_RSY1 LOAD MULTIPLE HIGH 2023 op_LMY uint32 = 0xEB98 // FORMAT_RSY1 LOAD MULTIPLE (32) 2024 op_LNDBR uint32 = 0xB311 // FORMAT_RRE LOAD NEGATIVE (long BFP) 2025 op_LNDFR uint32 = 0xB371 // FORMAT_RRE LOAD NEGATIVE (long) 2026 op_LNDR uint32 = 0x2100 // FORMAT_RR LOAD NEGATIVE (long HFP) 2027 op_LNEBR uint32 = 0xB301 // FORMAT_RRE LOAD NEGATIVE (short BFP) 2028 op_LNER uint32 = 0x3100 // FORMAT_RR LOAD NEGATIVE (short HFP) 2029 op_LNGFR uint32 = 0xB911 // FORMAT_RRE LOAD NEGATIVE (64<-32) 2030 op_LNGR uint32 = 0xB901 // FORMAT_RRE LOAD NEGATIVE (64) 2031 op_LNR uint32 = 0x1100 // FORMAT_RR LOAD NEGATIVE (32) 2032 op_LNXBR uint32 = 0xB341 // FORMAT_RRE LOAD NEGATIVE (extended BFP) 2033 op_LNXR uint32 = 0xB361 // FORMAT_RRE LOAD NEGATIVE (extended HFP) 2034 op_LOC uint32 = 0xEBF2 // FORMAT_RSY2 LOAD ON CONDITION (32) 2035 op_LOCG uint32 = 0xEBE2 // FORMAT_RSY2 LOAD ON CONDITION (64) 2036 op_LOCGR uint32 = 0xB9E2 // FORMAT_RRF3 LOAD ON CONDITION (64) 2037 op_LOCR uint32 = 0xB9F2 // FORMAT_RRF3 LOAD ON CONDITION (32) 2038 op_LPD uint32 = 0xC804 // FORMAT_SSF LOAD PAIR DISJOINT (32) 2039 op_LPDBR uint32 = 0xB310 // FORMAT_RRE LOAD POSITIVE (long BFP) 2040 op_LPDFR uint32 = 0xB370 // FORMAT_RRE LOAD POSITIVE (long) 2041 op_LPDG uint32 = 0xC805 // FORMAT_SSF LOAD PAIR DISJOINT (64) 2042 op_LPDR uint32 = 0x2000 // FORMAT_RR LOAD POSITIVE (long HFP) 2043 op_LPEBR uint32 = 0xB300 // FORMAT_RRE LOAD POSITIVE (short BFP) 2044 op_LPER uint32 = 0x3000 // FORMAT_RR LOAD POSITIVE (short HFP) 2045 op_LPGFR uint32 = 0xB910 // FORMAT_RRE LOAD POSITIVE (64<-32) 2046 op_LPGR uint32 = 0xB900 // FORMAT_RRE LOAD POSITIVE (64) 2047 op_LPQ uint32 = 0xE38F // FORMAT_RXY1 LOAD PAIR FROM QUADWORD 2048 op_LPR uint32 = 0x1000 // FORMAT_RR LOAD POSITIVE (32) 2049 op_LPSW uint32 = 0x8200 // FORMAT_S LOAD PSW 2050 op_LPSWE uint32 = 0xB2B2 // FORMAT_S LOAD PSW EXTENDED 2051 op_LPTEA uint32 = 0xB9AA // FORMAT_RRF2 LOAD PAGE TABLE ENTRY ADDRESS 2052 op_LPXBR uint32 = 0xB340 // FORMAT_RRE LOAD POSITIVE (extended BFP) 2053 op_LPXR uint32 = 0xB360 // FORMAT_RRE LOAD POSITIVE (extended HFP) 2054 op_LR uint32 = 0x1800 // FORMAT_RR LOAD (32) 2055 op_LRA uint32 = 0xB100 // FORMAT_RX1 LOAD REAL ADDRESS (32) 2056 op_LRAG uint32 = 0xE303 // FORMAT_RXY1 LOAD REAL ADDRESS (64) 2057 op_LRAY uint32 = 0xE313 // FORMAT_RXY1 LOAD REAL ADDRESS (32) 2058 op_LRDR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 2059 op_LRER uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 2060 op_LRL uint32 = 0xC40D // FORMAT_RIL2 LOAD RELATIVE LONG (32) 2061 op_LRV uint32 = 0xE31E // FORMAT_RXY1 LOAD REVERSED (32) 2062 op_LRVG uint32 = 0xE30F // FORMAT_RXY1 LOAD REVERSED (64) 2063 op_LRVGR uint32 = 0xB90F // FORMAT_RRE LOAD REVERSED (64) 2064 op_LRVH uint32 = 0xE31F // FORMAT_RXY1 LOAD REVERSED (16) 2065 op_LRVR uint32 = 0xB91F // FORMAT_RRE LOAD REVERSED (32) 2066 op_LT uint32 = 0xE312 // FORMAT_RXY1 LOAD AND TEST (32) 2067 op_LTDBR uint32 = 0xB312 // FORMAT_RRE LOAD AND TEST (long BFP) 2068 op_LTDR uint32 = 0x2200 // FORMAT_RR LOAD AND TEST (long HFP) 2069 op_LTDTR uint32 = 0xB3D6 // FORMAT_RRE LOAD AND TEST (long DFP) 2070 op_LTEBR uint32 = 0xB302 // FORMAT_RRE LOAD AND TEST (short BFP) 2071 op_LTER uint32 = 0x3200 // FORMAT_RR LOAD AND TEST (short HFP) 2072 op_LTG uint32 = 0xE302 // FORMAT_RXY1 LOAD AND TEST (64) 2073 op_LTGF uint32 = 0xE332 // FORMAT_RXY1 LOAD AND TEST (64<-32) 2074 op_LTGFR uint32 = 0xB912 // FORMAT_RRE LOAD AND TEST (64<-32) 2075 op_LTGR uint32 = 0xB902 // FORMAT_RRE LOAD AND TEST (64) 2076 op_LTR uint32 = 0x1200 // FORMAT_RR LOAD AND TEST (32) 2077 op_LTXBR uint32 = 0xB342 // FORMAT_RRE LOAD AND TEST (extended BFP) 2078 op_LTXR uint32 = 0xB362 // FORMAT_RRE LOAD AND TEST (extended HFP) 2079 op_LTXTR uint32 = 0xB3DE // FORMAT_RRE LOAD AND TEST (extended DFP) 2080 op_LURA uint32 = 0xB24B // FORMAT_RRE LOAD USING REAL ADDRESS (32) 2081 op_LURAG uint32 = 0xB905 // FORMAT_RRE LOAD USING REAL ADDRESS (64) 2082 op_LXD uint32 = 0xED25 // FORMAT_RXE LOAD LENGTHENED (long to extended HFP) 2083 op_LXDB uint32 = 0xED05 // FORMAT_RXE LOAD LENGTHENED (long to extended BFP) 2084 op_LXDBR uint32 = 0xB305 // FORMAT_RRE LOAD LENGTHENED (long to extended BFP) 2085 op_LXDR uint32 = 0xB325 // FORMAT_RRE LOAD LENGTHENED (long to extended HFP) 2086 op_LXDTR uint32 = 0xB3DC // FORMAT_RRF4 LOAD LENGTHENED (long to extended DFP) 2087 op_LXE uint32 = 0xED26 // FORMAT_RXE LOAD LENGTHENED (short to extended HFP) 2088 op_LXEB uint32 = 0xED06 // FORMAT_RXE LOAD LENGTHENED (short to extended BFP) 2089 op_LXEBR uint32 = 0xB306 // FORMAT_RRE LOAD LENGTHENED (short to extended BFP) 2090 op_LXER uint32 = 0xB326 // FORMAT_RRE LOAD LENGTHENED (short to extended HFP) 2091 op_LXR uint32 = 0xB365 // FORMAT_RRE LOAD (extended) 2092 op_LY uint32 = 0xE358 // FORMAT_RXY1 LOAD (32) 2093 op_LZDR uint32 = 0xB375 // FORMAT_RRE LOAD ZERO (long) 2094 op_LZER uint32 = 0xB374 // FORMAT_RRE LOAD ZERO (short) 2095 op_LZXR uint32 = 0xB376 // FORMAT_RRE LOAD ZERO (extended) 2096 op_M uint32 = 0x5C00 // FORMAT_RX1 MULTIPLY (64<-32) 2097 op_MAD uint32 = 0xED3E // FORMAT_RXF MULTIPLY AND ADD (long HFP) 2098 op_MADB uint32 = 0xED1E // FORMAT_RXF MULTIPLY AND ADD (long BFP) 2099 op_MADBR uint32 = 0xB31E // FORMAT_RRD MULTIPLY AND ADD (long BFP) 2100 op_MADR uint32 = 0xB33E // FORMAT_RRD MULTIPLY AND ADD (long HFP) 2101 op_MAE uint32 = 0xED2E // FORMAT_RXF MULTIPLY AND ADD (short HFP) 2102 op_MAEB uint32 = 0xED0E // FORMAT_RXF MULTIPLY AND ADD (short BFP) 2103 op_MAEBR uint32 = 0xB30E // FORMAT_RRD MULTIPLY AND ADD (short BFP) 2104 op_MAER uint32 = 0xB32E // FORMAT_RRD MULTIPLY AND ADD (short HFP) 2105 op_MAY uint32 = 0xED3A // FORMAT_RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 2106 op_MAYH uint32 = 0xED3C // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 2107 op_MAYHR uint32 = 0xB33C // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 2108 op_MAYL uint32 = 0xED38 // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 2109 op_MAYLR uint32 = 0xB338 // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 2110 op_MAYR uint32 = 0xB33A // FORMAT_RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 2111 op_MC uint32 = 0xAF00 // FORMAT_SI MONITOR CALL 2112 op_MD uint32 = 0x6C00 // FORMAT_RX1 MULTIPLY (long HFP) 2113 op_MDB uint32 = 0xED1C // FORMAT_RXE MULTIPLY (long BFP) 2114 op_MDBR uint32 = 0xB31C // FORMAT_RRE MULTIPLY (long BFP) 2115 op_MDE uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 2116 op_MDEB uint32 = 0xED0C // FORMAT_RXE MULTIPLY (short to long BFP) 2117 op_MDEBR uint32 = 0xB30C // FORMAT_RRE MULTIPLY (short to long BFP) 2118 op_MDER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 2119 op_MDR uint32 = 0x2C00 // FORMAT_RR MULTIPLY (long HFP) 2120 op_MDTR uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 2121 op_MDTRA uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 2122 op_ME uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 2123 op_MEE uint32 = 0xED37 // FORMAT_RXE MULTIPLY (short HFP) 2124 op_MEEB uint32 = 0xED17 // FORMAT_RXE MULTIPLY (short BFP) 2125 op_MEEBR uint32 = 0xB317 // FORMAT_RRE MULTIPLY (short BFP) 2126 op_MEER uint32 = 0xB337 // FORMAT_RRE MULTIPLY (short HFP) 2127 op_MER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 2128 op_MFY uint32 = 0xE35C // FORMAT_RXY1 MULTIPLY (64<-32) 2129 op_MGHI uint32 = 0xA70D // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (64) 2130 op_MH uint32 = 0x4C00 // FORMAT_RX1 MULTIPLY HALFWORD (32) 2131 op_MHI uint32 = 0xA70C // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (32) 2132 op_MHY uint32 = 0xE37C // FORMAT_RXY1 MULTIPLY HALFWORD (32) 2133 op_ML uint32 = 0xE396 // FORMAT_RXY1 MULTIPLY LOGICAL (64<-32) 2134 op_MLG uint32 = 0xE386 // FORMAT_RXY1 MULTIPLY LOGICAL (128<-64) 2135 op_MLGR uint32 = 0xB986 // FORMAT_RRE MULTIPLY LOGICAL (128<-64) 2136 op_MLR uint32 = 0xB996 // FORMAT_RRE MULTIPLY LOGICAL (64<-32) 2137 op_MP uint32 = 0xFC00 // FORMAT_SS2 MULTIPLY DECIMAL 2138 op_MR uint32 = 0x1C00 // FORMAT_RR MULTIPLY (64<-32) 2139 op_MS uint32 = 0x7100 // FORMAT_RX1 MULTIPLY SINGLE (32) 2140 op_MSCH uint32 = 0xB232 // FORMAT_S MODIFY SUBCHANNEL 2141 op_MSD uint32 = 0xED3F // FORMAT_RXF MULTIPLY AND SUBTRACT (long HFP) 2142 op_MSDB uint32 = 0xED1F // FORMAT_RXF MULTIPLY AND SUBTRACT (long BFP) 2143 op_MSDBR uint32 = 0xB31F // FORMAT_RRD MULTIPLY AND SUBTRACT (long BFP) 2144 op_MSDR uint32 = 0xB33F // FORMAT_RRD MULTIPLY AND SUBTRACT (long HFP) 2145 op_MSE uint32 = 0xED2F // FORMAT_RXF MULTIPLY AND SUBTRACT (short HFP) 2146 op_MSEB uint32 = 0xED0F // FORMAT_RXF MULTIPLY AND SUBTRACT (short BFP) 2147 op_MSEBR uint32 = 0xB30F // FORMAT_RRD MULTIPLY AND SUBTRACT (short BFP) 2148 op_MSER uint32 = 0xB32F // FORMAT_RRD MULTIPLY AND SUBTRACT (short HFP) 2149 op_MSFI uint32 = 0xC201 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (32) 2150 op_MSG uint32 = 0xE30C // FORMAT_RXY1 MULTIPLY SINGLE (64) 2151 op_MSGF uint32 = 0xE31C // FORMAT_RXY1 MULTIPLY SINGLE (64<-32) 2152 op_MSGFI uint32 = 0xC200 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (64<-32) 2153 op_MSGFR uint32 = 0xB91C // FORMAT_RRE MULTIPLY SINGLE (64<-32) 2154 op_MSGR uint32 = 0xB90C // FORMAT_RRE MULTIPLY SINGLE (64) 2155 op_MSR uint32 = 0xB252 // FORMAT_RRE MULTIPLY SINGLE (32) 2156 op_MSTA uint32 = 0xB247 // FORMAT_RRE MODIFY STACKED STATE 2157 op_MSY uint32 = 0xE351 // FORMAT_RXY1 MULTIPLY SINGLE (32) 2158 op_MVC uint32 = 0xD200 // FORMAT_SS1 MOVE (character) 2159 op_MVCDK uint32 = 0xE50F // FORMAT_SSE MOVE WITH DESTINATION KEY 2160 op_MVCIN uint32 = 0xE800 // FORMAT_SS1 MOVE INVERSE 2161 op_MVCK uint32 = 0xD900 // FORMAT_SS4 MOVE WITH KEY 2162 op_MVCL uint32 = 0x0E00 // FORMAT_RR MOVE LONG 2163 op_MVCLE uint32 = 0xA800 // FORMAT_RS1 MOVE LONG EXTENDED 2164 op_MVCLU uint32 = 0xEB8E // FORMAT_RSY1 MOVE LONG UNICODE 2165 op_MVCOS uint32 = 0xC800 // FORMAT_SSF MOVE WITH OPTIONAL SPECIFICATIONS 2166 op_MVCP uint32 = 0xDA00 // FORMAT_SS4 MOVE TO PRIMARY 2167 op_MVCS uint32 = 0xDB00 // FORMAT_SS4 MOVE TO SECONDARY 2168 op_MVCSK uint32 = 0xE50E // FORMAT_SSE MOVE WITH SOURCE KEY 2169 op_MVGHI uint32 = 0xE548 // FORMAT_SIL MOVE (64<-16) 2170 op_MVHHI uint32 = 0xE544 // FORMAT_SIL MOVE (16<-16) 2171 op_MVHI uint32 = 0xE54C // FORMAT_SIL MOVE (32<-16) 2172 op_MVI uint32 = 0x9200 // FORMAT_SI MOVE (immediate) 2173 op_MVIY uint32 = 0xEB52 // FORMAT_SIY MOVE (immediate) 2174 op_MVN uint32 = 0xD100 // FORMAT_SS1 MOVE NUMERICS 2175 op_MVO uint32 = 0xF100 // FORMAT_SS2 MOVE WITH OFFSET 2176 op_MVPG uint32 = 0xB254 // FORMAT_RRE MOVE PAGE 2177 op_MVST uint32 = 0xB255 // FORMAT_RRE MOVE STRING 2178 op_MVZ uint32 = 0xD300 // FORMAT_SS1 MOVE ZONES 2179 op_MXBR uint32 = 0xB34C // FORMAT_RRE MULTIPLY (extended BFP) 2180 op_MXD uint32 = 0x6700 // FORMAT_RX1 MULTIPLY (long to extended HFP) 2181 op_MXDB uint32 = 0xED07 // FORMAT_RXE MULTIPLY (long to extended BFP) 2182 op_MXDBR uint32 = 0xB307 // FORMAT_RRE MULTIPLY (long to extended BFP) 2183 op_MXDR uint32 = 0x2700 // FORMAT_RR MULTIPLY (long to extended HFP) 2184 op_MXR uint32 = 0x2600 // FORMAT_RR MULTIPLY (extended HFP) 2185 op_MXTR uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2186 op_MXTRA uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2187 op_MY uint32 = 0xED3B // FORMAT_RXF MULTIPLY UNNORMALIZED (long to ext. HFP) 2188 op_MYH uint32 = 0xED3D // FORMAT_RXF MULTIPLY UNNORM. (long to ext. high HFP) 2189 op_MYHR uint32 = 0xB33D // FORMAT_RRD MULTIPLY UNNORM. (long to ext. high HFP) 2190 op_MYL uint32 = 0xED39 // FORMAT_RXF MULTIPLY UNNORM. (long to ext. low HFP) 2191 op_MYLR uint32 = 0xB339 // FORMAT_RRD MULTIPLY UNNORM. (long to ext. low HFP) 2192 op_MYR uint32 = 0xB33B // FORMAT_RRD MULTIPLY UNNORMALIZED (long to ext. HFP) 2193 op_N uint32 = 0x5400 // FORMAT_RX1 AND (32) 2194 op_NC uint32 = 0xD400 // FORMAT_SS1 AND (character) 2195 op_NG uint32 = 0xE380 // FORMAT_RXY1 AND (64) 2196 op_NGR uint32 = 0xB980 // FORMAT_RRE AND (64) 2197 op_NGRK uint32 = 0xB9E4 // FORMAT_RRF1 AND (64) 2198 op_NI uint32 = 0x9400 // FORMAT_SI AND (immediate) 2199 op_NIAI uint32 = 0xB2FA // FORMAT_IE NEXT INSTRUCTION ACCESS INTENT 2200 op_NIHF uint32 = 0xC00A // FORMAT_RIL1 AND IMMEDIATE (high) 2201 op_NIHH uint32 = 0xA504 // FORMAT_RI1 AND IMMEDIATE (high high) 2202 op_NIHL uint32 = 0xA505 // FORMAT_RI1 AND IMMEDIATE (high low) 2203 op_NILF uint32 = 0xC00B // FORMAT_RIL1 AND IMMEDIATE (low) 2204 op_NILH uint32 = 0xA506 // FORMAT_RI1 AND IMMEDIATE (low high) 2205 op_NILL uint32 = 0xA507 // FORMAT_RI1 AND IMMEDIATE (low low) 2206 op_NIY uint32 = 0xEB54 // FORMAT_SIY AND (immediate) 2207 op_NR uint32 = 0x1400 // FORMAT_RR AND (32) 2208 op_NRK uint32 = 0xB9F4 // FORMAT_RRF1 AND (32) 2209 op_NTSTG uint32 = 0xE325 // FORMAT_RXY1 NONTRANSACTIONAL STORE 2210 op_NY uint32 = 0xE354 // FORMAT_RXY1 AND (32) 2211 op_O uint32 = 0x5600 // FORMAT_RX1 OR (32) 2212 op_OC uint32 = 0xD600 // FORMAT_SS1 OR (character) 2213 op_OG uint32 = 0xE381 // FORMAT_RXY1 OR (64) 2214 op_OGR uint32 = 0xB981 // FORMAT_RRE OR (64) 2215 op_OGRK uint32 = 0xB9E6 // FORMAT_RRF1 OR (64) 2216 op_OI uint32 = 0x9600 // FORMAT_SI OR (immediate) 2217 op_OIHF uint32 = 0xC00C // FORMAT_RIL1 OR IMMEDIATE (high) 2218 op_OIHH uint32 = 0xA508 // FORMAT_RI1 OR IMMEDIATE (high high) 2219 op_OIHL uint32 = 0xA509 // FORMAT_RI1 OR IMMEDIATE (high low) 2220 op_OILF uint32 = 0xC00D // FORMAT_RIL1 OR IMMEDIATE (low) 2221 op_OILH uint32 = 0xA50A // FORMAT_RI1 OR IMMEDIATE (low high) 2222 op_OILL uint32 = 0xA50B // FORMAT_RI1 OR IMMEDIATE (low low) 2223 op_OIY uint32 = 0xEB56 // FORMAT_SIY OR (immediate) 2224 op_OR uint32 = 0x1600 // FORMAT_RR OR (32) 2225 op_ORK uint32 = 0xB9F6 // FORMAT_RRF1 OR (32) 2226 op_OY uint32 = 0xE356 // FORMAT_RXY1 OR (32) 2227 op_PACK uint32 = 0xF200 // FORMAT_SS2 PACK 2228 op_PALB uint32 = 0xB248 // FORMAT_RRE PURGE ALB 2229 op_PC uint32 = 0xB218 // FORMAT_S PROGRAM CALL 2230 op_PCC uint32 = 0xB92C // FORMAT_RRE PERFORM CRYPTOGRAPHIC COMPUTATION 2231 op_PCKMO uint32 = 0xB928 // FORMAT_RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS 2232 op_PFD uint32 = 0xE336 // FORMAT_RXY2 PREFETCH DATA 2233 op_PFDRL uint32 = 0xC602 // FORMAT_RIL3 PREFETCH DATA RELATIVE LONG 2234 op_PFMF uint32 = 0xB9AF // FORMAT_RRE PERFORM FRAME MANAGEMENT FUNCTION 2235 op_PFPO uint32 = 0x010A // FORMAT_E PERFORM FLOATING-POINT OPERATION 2236 op_PGIN uint32 = 0xB22E // FORMAT_RRE PAGE IN 2237 op_PGOUT uint32 = 0xB22F // FORMAT_RRE PAGE OUT 2238 op_PKA uint32 = 0xE900 // FORMAT_SS6 PACK ASCII 2239 op_PKU uint32 = 0xE100 // FORMAT_SS6 PACK UNICODE 2240 op_PLO uint32 = 0xEE00 // FORMAT_SS5 PERFORM LOCKED OPERATION 2241 op_POPCNT uint32 = 0xB9E1 // FORMAT_RRE POPULATION COUNT 2242 op_PPA uint32 = 0xB2E8 // FORMAT_RRF3 PERFORM PROCESSOR ASSIST 2243 op_PR uint32 = 0x0101 // FORMAT_E PROGRAM RETURN 2244 op_PT uint32 = 0xB228 // FORMAT_RRE PROGRAM TRANSFER 2245 op_PTF uint32 = 0xB9A2 // FORMAT_RRE PERFORM TOPOLOGY FUNCTION 2246 op_PTFF uint32 = 0x0104 // FORMAT_E PERFORM TIMING FACILITY FUNCTION 2247 op_PTI uint32 = 0xB99E // FORMAT_RRE PROGRAM TRANSFER WITH INSTANCE 2248 op_PTLB uint32 = 0xB20D // FORMAT_S PURGE TLB 2249 op_QADTR uint32 = 0xB3F5 // FORMAT_RRF2 QUANTIZE (long DFP) 2250 op_QAXTR uint32 = 0xB3FD // FORMAT_RRF2 QUANTIZE (extended DFP) 2251 op_RCHP uint32 = 0xB23B // FORMAT_S RESET CHANNEL PATH 2252 op_RISBG uint32 = 0xEC55 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2253 op_RISBGN uint32 = 0xEC59 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2254 op_RISBHG uint32 = 0xEC5D // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS HIGH 2255 op_RISBLG uint32 = 0xEC51 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS LOW 2256 op_RLL uint32 = 0xEB1D // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (32) 2257 op_RLLG uint32 = 0xEB1C // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (64) 2258 op_RNSBG uint32 = 0xEC54 // FORMAT_RIE6 ROTATE THEN AND SELECTED BITS 2259 op_ROSBG uint32 = 0xEC56 // FORMAT_RIE6 ROTATE THEN OR SELECTED BITS 2260 op_RP uint32 = 0xB277 // FORMAT_S RESUME PROGRAM 2261 op_RRBE uint32 = 0xB22A // FORMAT_RRE RESET REFERENCE BIT EXTENDED 2262 op_RRBM uint32 = 0xB9AE // FORMAT_RRE RESET REFERENCE BITS MULTIPLE 2263 op_RRDTR uint32 = 0xB3F7 // FORMAT_RRF2 REROUND (long DFP) 2264 op_RRXTR uint32 = 0xB3FF // FORMAT_RRF2 REROUND (extended DFP) 2265 op_RSCH uint32 = 0xB238 // FORMAT_S RESUME SUBCHANNEL 2266 op_RXSBG uint32 = 0xEC57 // FORMAT_RIE6 ROTATE THEN EXCLUSIVE OR SELECTED BITS 2267 op_S uint32 = 0x5B00 // FORMAT_RX1 SUBTRACT (32) 2268 op_SAC uint32 = 0xB219 // FORMAT_S SET ADDRESS SPACE CONTROL 2269 op_SACF uint32 = 0xB279 // FORMAT_S SET ADDRESS SPACE CONTROL FAST 2270 op_SAL uint32 = 0xB237 // FORMAT_S SET ADDRESS LIMIT 2271 op_SAM24 uint32 = 0x010C // FORMAT_E SET ADDRESSING MODE (24) 2272 op_SAM31 uint32 = 0x010D // FORMAT_E SET ADDRESSING MODE (31) 2273 op_SAM64 uint32 = 0x010E // FORMAT_E SET ADDRESSING MODE (64) 2274 op_SAR uint32 = 0xB24E // FORMAT_RRE SET ACCESS 2275 op_SCHM uint32 = 0xB23C // FORMAT_S SET CHANNEL MONITOR 2276 op_SCK uint32 = 0xB204 // FORMAT_S SET CLOCK 2277 op_SCKC uint32 = 0xB206 // FORMAT_S SET CLOCK COMPARATOR 2278 op_SCKPF uint32 = 0x0107 // FORMAT_E SET CLOCK PROGRAMMABLE FIELD 2279 op_SD uint32 = 0x6B00 // FORMAT_RX1 SUBTRACT NORMALIZED (long HFP) 2280 op_SDB uint32 = 0xED1B // FORMAT_RXE SUBTRACT (long BFP) 2281 op_SDBR uint32 = 0xB31B // FORMAT_RRE SUBTRACT (long BFP) 2282 op_SDR uint32 = 0x2B00 // FORMAT_RR SUBTRACT NORMALIZED (long HFP) 2283 op_SDTR uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2284 op_SDTRA uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2285 op_SE uint32 = 0x7B00 // FORMAT_RX1 SUBTRACT NORMALIZED (short HFP) 2286 op_SEB uint32 = 0xED0B // FORMAT_RXE SUBTRACT (short BFP) 2287 op_SEBR uint32 = 0xB30B // FORMAT_RRE SUBTRACT (short BFP) 2288 op_SER uint32 = 0x3B00 // FORMAT_RR SUBTRACT NORMALIZED (short HFP) 2289 op_SFASR uint32 = 0xB385 // FORMAT_RRE SET FPC AND SIGNAL 2290 op_SFPC uint32 = 0xB384 // FORMAT_RRE SET FPC 2291 op_SG uint32 = 0xE309 // FORMAT_RXY1 SUBTRACT (64) 2292 op_SGF uint32 = 0xE319 // FORMAT_RXY1 SUBTRACT (64<-32) 2293 op_SGFR uint32 = 0xB919 // FORMAT_RRE SUBTRACT (64<-32) 2294 op_SGR uint32 = 0xB909 // FORMAT_RRE SUBTRACT (64) 2295 op_SGRK uint32 = 0xB9E9 // FORMAT_RRF1 SUBTRACT (64) 2296 op_SH uint32 = 0x4B00 // FORMAT_RX1 SUBTRACT HALFWORD 2297 op_SHHHR uint32 = 0xB9C9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2298 op_SHHLR uint32 = 0xB9D9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2299 op_SHY uint32 = 0xE37B // FORMAT_RXY1 SUBTRACT HALFWORD 2300 op_SIGP uint32 = 0xAE00 // FORMAT_RS1 SIGNAL PROCESSOR 2301 op_SL uint32 = 0x5F00 // FORMAT_RX1 SUBTRACT LOGICAL (32) 2302 op_SLA uint32 = 0x8B00 // FORMAT_RS1 SHIFT LEFT SINGLE (32) 2303 op_SLAG uint32 = 0xEB0B // FORMAT_RSY1 SHIFT LEFT SINGLE (64) 2304 op_SLAK uint32 = 0xEBDD // FORMAT_RSY1 SHIFT LEFT SINGLE (32) 2305 op_SLB uint32 = 0xE399 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (32) 2306 op_SLBG uint32 = 0xE389 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (64) 2307 op_SLBGR uint32 = 0xB989 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (64) 2308 op_SLBR uint32 = 0xB999 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (32) 2309 op_SLDA uint32 = 0x8F00 // FORMAT_RS1 SHIFT LEFT DOUBLE 2310 op_SLDL uint32 = 0x8D00 // FORMAT_RS1 SHIFT LEFT DOUBLE LOGICAL 2311 op_SLDT uint32 = 0xED40 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (long DFP) 2312 op_SLFI uint32 = 0xC205 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (32) 2313 op_SLG uint32 = 0xE30B // FORMAT_RXY1 SUBTRACT LOGICAL (64) 2314 op_SLGF uint32 = 0xE31B // FORMAT_RXY1 SUBTRACT LOGICAL (64<-32) 2315 op_SLGFI uint32 = 0xC204 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (64<-32) 2316 op_SLGFR uint32 = 0xB91B // FORMAT_RRE SUBTRACT LOGICAL (64<-32) 2317 op_SLGR uint32 = 0xB90B // FORMAT_RRE SUBTRACT LOGICAL (64) 2318 op_SLGRK uint32 = 0xB9EB // FORMAT_RRF1 SUBTRACT LOGICAL (64) 2319 op_SLHHHR uint32 = 0xB9CB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2320 op_SLHHLR uint32 = 0xB9DB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2321 op_SLL uint32 = 0x8900 // FORMAT_RS1 SHIFT LEFT SINGLE LOGICAL (32) 2322 op_SLLG uint32 = 0xEB0D // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (64) 2323 op_SLLK uint32 = 0xEBDF // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (32) 2324 op_SLR uint32 = 0x1F00 // FORMAT_RR SUBTRACT LOGICAL (32) 2325 op_SLRK uint32 = 0xB9FB // FORMAT_RRF1 SUBTRACT LOGICAL (32) 2326 op_SLXT uint32 = 0xED48 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (extended DFP) 2327 op_SLY uint32 = 0xE35F // FORMAT_RXY1 SUBTRACT LOGICAL (32) 2328 op_SP uint32 = 0xFB00 // FORMAT_SS2 SUBTRACT DECIMAL 2329 op_SPKA uint32 = 0xB20A // FORMAT_S SET PSW KEY FROM ADDRESS 2330 op_SPM uint32 = 0x0400 // FORMAT_RR SET PROGRAM MASK 2331 op_SPT uint32 = 0xB208 // FORMAT_S SET CPU TIMER 2332 op_SPX uint32 = 0xB210 // FORMAT_S SET PREFIX 2333 op_SQD uint32 = 0xED35 // FORMAT_RXE SQUARE ROOT (long HFP) 2334 op_SQDB uint32 = 0xED15 // FORMAT_RXE SQUARE ROOT (long BFP) 2335 op_SQDBR uint32 = 0xB315 // FORMAT_RRE SQUARE ROOT (long BFP) 2336 op_SQDR uint32 = 0xB244 // FORMAT_RRE SQUARE ROOT (long HFP) 2337 op_SQE uint32 = 0xED34 // FORMAT_RXE SQUARE ROOT (short HFP) 2338 op_SQEB uint32 = 0xED14 // FORMAT_RXE SQUARE ROOT (short BFP) 2339 op_SQEBR uint32 = 0xB314 // FORMAT_RRE SQUARE ROOT (short BFP) 2340 op_SQER uint32 = 0xB245 // FORMAT_RRE SQUARE ROOT (short HFP) 2341 op_SQXBR uint32 = 0xB316 // FORMAT_RRE SQUARE ROOT (extended BFP) 2342 op_SQXR uint32 = 0xB336 // FORMAT_RRE SQUARE ROOT (extended HFP) 2343 op_SR uint32 = 0x1B00 // FORMAT_RR SUBTRACT (32) 2344 op_SRA uint32 = 0x8A00 // FORMAT_RS1 SHIFT RIGHT SINGLE (32) 2345 op_SRAG uint32 = 0xEB0A // FORMAT_RSY1 SHIFT RIGHT SINGLE (64) 2346 op_SRAK uint32 = 0xEBDC // FORMAT_RSY1 SHIFT RIGHT SINGLE (32) 2347 op_SRDA uint32 = 0x8E00 // FORMAT_RS1 SHIFT RIGHT DOUBLE 2348 op_SRDL uint32 = 0x8C00 // FORMAT_RS1 SHIFT RIGHT DOUBLE LOGICAL 2349 op_SRDT uint32 = 0xED41 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (long DFP) 2350 op_SRK uint32 = 0xB9F9 // FORMAT_RRF1 SUBTRACT (32) 2351 op_SRL uint32 = 0x8800 // FORMAT_RS1 SHIFT RIGHT SINGLE LOGICAL (32) 2352 op_SRLG uint32 = 0xEB0C // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (64) 2353 op_SRLK uint32 = 0xEBDE // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (32) 2354 op_SRNM uint32 = 0xB299 // FORMAT_S SET BFP ROUNDING MODE (2 bit) 2355 op_SRNMB uint32 = 0xB2B8 // FORMAT_S SET BFP ROUNDING MODE (3 bit) 2356 op_SRNMT uint32 = 0xB2B9 // FORMAT_S SET DFP ROUNDING MODE 2357 op_SRP uint32 = 0xF000 // FORMAT_SS3 SHIFT AND ROUND DECIMAL 2358 op_SRST uint32 = 0xB25E // FORMAT_RRE SEARCH STRING 2359 op_SRSTU uint32 = 0xB9BE // FORMAT_RRE SEARCH STRING UNICODE 2360 op_SRXT uint32 = 0xED49 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (extended DFP) 2361 op_SSAIR uint32 = 0xB99F // FORMAT_RRE SET SECONDARY ASN WITH INSTANCE 2362 op_SSAR uint32 = 0xB225 // FORMAT_RRE SET SECONDARY ASN 2363 op_SSCH uint32 = 0xB233 // FORMAT_S START SUBCHANNEL 2364 op_SSKE uint32 = 0xB22B // FORMAT_RRF3 SET STORAGE KEY EXTENDED 2365 op_SSM uint32 = 0x8000 // FORMAT_S SET SYSTEM MASK 2366 op_ST uint32 = 0x5000 // FORMAT_RX1 STORE (32) 2367 op_STAM uint32 = 0x9B00 // FORMAT_RS1 STORE ACCESS MULTIPLE 2368 op_STAMY uint32 = 0xEB9B // FORMAT_RSY1 STORE ACCESS MULTIPLE 2369 op_STAP uint32 = 0xB212 // FORMAT_S STORE CPU ADDRESS 2370 op_STC uint32 = 0x4200 // FORMAT_RX1 STORE CHARACTER 2371 op_STCH uint32 = 0xE3C3 // FORMAT_RXY1 STORE CHARACTER HIGH (8) 2372 op_STCK uint32 = 0xB205 // FORMAT_S STORE CLOCK 2373 op_STCKC uint32 = 0xB207 // FORMAT_S STORE CLOCK COMPARATOR 2374 op_STCKE uint32 = 0xB278 // FORMAT_S STORE CLOCK EXTENDED 2375 op_STCKF uint32 = 0xB27C // FORMAT_S STORE CLOCK FAST 2376 op_STCM uint32 = 0xBE00 // FORMAT_RS2 STORE CHARACTERS UNDER MASK (low) 2377 op_STCMH uint32 = 0xEB2C // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (high) 2378 op_STCMY uint32 = 0xEB2D // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (low) 2379 op_STCPS uint32 = 0xB23A // FORMAT_S STORE CHANNEL PATH STATUS 2380 op_STCRW uint32 = 0xB239 // FORMAT_S STORE CHANNEL REPORT WORD 2381 op_STCTG uint32 = 0xEB25 // FORMAT_RSY1 STORE CONTROL (64) 2382 op_STCTL uint32 = 0xB600 // FORMAT_RS1 STORE CONTROL (32) 2383 op_STCY uint32 = 0xE372 // FORMAT_RXY1 STORE CHARACTER 2384 op_STD uint32 = 0x6000 // FORMAT_RX1 STORE (long) 2385 op_STDY uint32 = 0xED67 // FORMAT_RXY1 STORE (long) 2386 op_STE uint32 = 0x7000 // FORMAT_RX1 STORE (short) 2387 op_STEY uint32 = 0xED66 // FORMAT_RXY1 STORE (short) 2388 op_STFH uint32 = 0xE3CB // FORMAT_RXY1 STORE HIGH (32) 2389 op_STFL uint32 = 0xB2B1 // FORMAT_S STORE FACILITY LIST 2390 op_STFLE uint32 = 0xB2B0 // FORMAT_S STORE FACILITY LIST EXTENDED 2391 op_STFPC uint32 = 0xB29C // FORMAT_S STORE FPC 2392 op_STG uint32 = 0xE324 // FORMAT_RXY1 STORE (64) 2393 op_STGRL uint32 = 0xC40B // FORMAT_RIL2 STORE RELATIVE LONG (64) 2394 op_STH uint32 = 0x4000 // FORMAT_RX1 STORE HALFWORD 2395 op_STHH uint32 = 0xE3C7 // FORMAT_RXY1 STORE HALFWORD HIGH (16) 2396 op_STHRL uint32 = 0xC407 // FORMAT_RIL2 STORE HALFWORD RELATIVE LONG 2397 op_STHY uint32 = 0xE370 // FORMAT_RXY1 STORE HALFWORD 2398 op_STIDP uint32 = 0xB202 // FORMAT_S STORE CPU ID 2399 op_STM uint32 = 0x9000 // FORMAT_RS1 STORE MULTIPLE (32) 2400 op_STMG uint32 = 0xEB24 // FORMAT_RSY1 STORE MULTIPLE (64) 2401 op_STMH uint32 = 0xEB26 // FORMAT_RSY1 STORE MULTIPLE HIGH 2402 op_STMY uint32 = 0xEB90 // FORMAT_RSY1 STORE MULTIPLE (32) 2403 op_STNSM uint32 = 0xAC00 // FORMAT_SI STORE THEN AND SYSTEM MASK 2404 op_STOC uint32 = 0xEBF3 // FORMAT_RSY2 STORE ON CONDITION (32) 2405 op_STOCG uint32 = 0xEBE3 // FORMAT_RSY2 STORE ON CONDITION (64) 2406 op_STOSM uint32 = 0xAD00 // FORMAT_SI STORE THEN OR SYSTEM MASK 2407 op_STPQ uint32 = 0xE38E // FORMAT_RXY1 STORE PAIR TO QUADWORD 2408 op_STPT uint32 = 0xB209 // FORMAT_S STORE CPU TIMER 2409 op_STPX uint32 = 0xB211 // FORMAT_S STORE PREFIX 2410 op_STRAG uint32 = 0xE502 // FORMAT_SSE STORE REAL ADDRESS 2411 op_STRL uint32 = 0xC40F // FORMAT_RIL2 STORE RELATIVE LONG (32) 2412 op_STRV uint32 = 0xE33E // FORMAT_RXY1 STORE REVERSED (32) 2413 op_STRVG uint32 = 0xE32F // FORMAT_RXY1 STORE REVERSED (64) 2414 op_STRVH uint32 = 0xE33F // FORMAT_RXY1 STORE REVERSED (16) 2415 op_STSCH uint32 = 0xB234 // FORMAT_S STORE SUBCHANNEL 2416 op_STSI uint32 = 0xB27D // FORMAT_S STORE SYSTEM INFORMATION 2417 op_STURA uint32 = 0xB246 // FORMAT_RRE STORE USING REAL ADDRESS (32) 2418 op_STURG uint32 = 0xB925 // FORMAT_RRE STORE USING REAL ADDRESS (64) 2419 op_STY uint32 = 0xE350 // FORMAT_RXY1 STORE (32) 2420 op_SU uint32 = 0x7F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (short HFP) 2421 op_SUR uint32 = 0x3F00 // FORMAT_RR SUBTRACT UNNORMALIZED (short HFP) 2422 op_SVC uint32 = 0x0A00 // FORMAT_I SUPERVISOR CALL 2423 op_SW uint32 = 0x6F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (long HFP) 2424 op_SWR uint32 = 0x2F00 // FORMAT_RR SUBTRACT UNNORMALIZED (long HFP) 2425 op_SXBR uint32 = 0xB34B // FORMAT_RRE SUBTRACT (extended BFP) 2426 op_SXR uint32 = 0x3700 // FORMAT_RR SUBTRACT NORMALIZED (extended HFP) 2427 op_SXTR uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2428 op_SXTRA uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2429 op_SY uint32 = 0xE35B // FORMAT_RXY1 SUBTRACT (32) 2430 op_TABORT uint32 = 0xB2FC // FORMAT_S TRANSACTION ABORT 2431 op_TAM uint32 = 0x010B // FORMAT_E TEST ADDRESSING MODE 2432 op_TAR uint32 = 0xB24C // FORMAT_RRE TEST ACCESS 2433 op_TB uint32 = 0xB22C // FORMAT_RRE TEST BLOCK 2434 op_TBDR uint32 = 0xB351 // FORMAT_RRF5 CONVERT HFP TO BFP (long) 2435 op_TBEDR uint32 = 0xB350 // FORMAT_RRF5 CONVERT HFP TO BFP (long to short) 2436 op_TBEGIN uint32 = 0xE560 // FORMAT_SIL TRANSACTION BEGIN 2437 op_TBEGINC uint32 = 0xE561 // FORMAT_SIL TRANSACTION BEGIN 2438 op_TCDB uint32 = 0xED11 // FORMAT_RXE TEST DATA CLASS (long BFP) 2439 op_TCEB uint32 = 0xED10 // FORMAT_RXE TEST DATA CLASS (short BFP) 2440 op_TCXB uint32 = 0xED12 // FORMAT_RXE TEST DATA CLASS (extended BFP) 2441 op_TDCDT uint32 = 0xED54 // FORMAT_RXE TEST DATA CLASS (long DFP) 2442 op_TDCET uint32 = 0xED50 // FORMAT_RXE TEST DATA CLASS (short DFP) 2443 op_TDCXT uint32 = 0xED58 // FORMAT_RXE TEST DATA CLASS (extended DFP) 2444 op_TDGDT uint32 = 0xED55 // FORMAT_RXE TEST DATA GROUP (long DFP) 2445 op_TDGET uint32 = 0xED51 // FORMAT_RXE TEST DATA GROUP (short DFP) 2446 op_TDGXT uint32 = 0xED59 // FORMAT_RXE TEST DATA GROUP (extended DFP) 2447 op_TEND uint32 = 0xB2F8 // FORMAT_S TRANSACTION END 2448 op_THDER uint32 = 0xB358 // FORMAT_RRE CONVERT BFP TO HFP (short to long) 2449 op_THDR uint32 = 0xB359 // FORMAT_RRE CONVERT BFP TO HFP (long) 2450 op_TM uint32 = 0x9100 // FORMAT_SI TEST UNDER MASK 2451 op_TMH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK HIGH 2452 op_TMHH uint32 = 0xA702 // FORMAT_RI1 TEST UNDER MASK (high high) 2453 op_TMHL uint32 = 0xA703 // FORMAT_RI1 TEST UNDER MASK (high low) 2454 op_TML uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK LOW 2455 op_TMLH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK (low high) 2456 op_TMLL uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK (low low) 2457 op_TMY uint32 = 0xEB51 // FORMAT_SIY TEST UNDER MASK 2458 op_TP uint32 = 0xEBC0 // FORMAT_RSL TEST DECIMAL 2459 op_TPI uint32 = 0xB236 // FORMAT_S TEST PENDING INTERRUPTION 2460 op_TPROT uint32 = 0xE501 // FORMAT_SSE TEST PROTECTION 2461 op_TR uint32 = 0xDC00 // FORMAT_SS1 TRANSLATE 2462 op_TRACE uint32 = 0x9900 // FORMAT_RS1 TRACE (32) 2463 op_TRACG uint32 = 0xEB0F // FORMAT_RSY1 TRACE (64) 2464 op_TRAP2 uint32 = 0x01FF // FORMAT_E TRAP 2465 op_TRAP4 uint32 = 0xB2FF // FORMAT_S TRAP 2466 op_TRE uint32 = 0xB2A5 // FORMAT_RRE TRANSLATE EXTENDED 2467 op_TROO uint32 = 0xB993 // FORMAT_RRF3 TRANSLATE ONE TO ONE 2468 op_TROT uint32 = 0xB992 // FORMAT_RRF3 TRANSLATE ONE TO TWO 2469 op_TRT uint32 = 0xDD00 // FORMAT_SS1 TRANSLATE AND TEST 2470 op_TRTE uint32 = 0xB9BF // FORMAT_RRF3 TRANSLATE AND TEST EXTENDED 2471 op_TRTO uint32 = 0xB991 // FORMAT_RRF3 TRANSLATE TWO TO ONE 2472 op_TRTR uint32 = 0xD000 // FORMAT_SS1 TRANSLATE AND TEST REVERSE 2473 op_TRTRE uint32 = 0xB9BD // FORMAT_RRF3 TRANSLATE AND TEST REVERSE EXTENDED 2474 op_TRTT uint32 = 0xB990 // FORMAT_RRF3 TRANSLATE TWO TO TWO 2475 op_TS uint32 = 0x9300 // FORMAT_S TEST AND SET 2476 op_TSCH uint32 = 0xB235 // FORMAT_S TEST SUBCHANNEL 2477 op_UNPK uint32 = 0xF300 // FORMAT_SS2 UNPACK 2478 op_UNPKA uint32 = 0xEA00 // FORMAT_SS1 UNPACK ASCII 2479 op_UNPKU uint32 = 0xE200 // FORMAT_SS1 UNPACK UNICODE 2480 op_UPT uint32 = 0x0102 // FORMAT_E UPDATE TREE 2481 op_X uint32 = 0x5700 // FORMAT_RX1 EXCLUSIVE OR (32) 2482 op_XC uint32 = 0xD700 // FORMAT_SS1 EXCLUSIVE OR (character) 2483 op_XG uint32 = 0xE382 // FORMAT_RXY1 EXCLUSIVE OR (64) 2484 op_XGR uint32 = 0xB982 // FORMAT_RRE EXCLUSIVE OR (64) 2485 op_XGRK uint32 = 0xB9E7 // FORMAT_RRF1 EXCLUSIVE OR (64) 2486 op_XI uint32 = 0x9700 // FORMAT_SI EXCLUSIVE OR (immediate) 2487 op_XIHF uint32 = 0xC006 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (high) 2488 op_XILF uint32 = 0xC007 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (low) 2489 op_XIY uint32 = 0xEB57 // FORMAT_SIY EXCLUSIVE OR (immediate) 2490 op_XR uint32 = 0x1700 // FORMAT_RR EXCLUSIVE OR (32) 2491 op_XRK uint32 = 0xB9F7 // FORMAT_RRF1 EXCLUSIVE OR (32) 2492 op_XSCH uint32 = 0xB276 // FORMAT_S CANCEL SUBCHANNEL 2493 op_XY uint32 = 0xE357 // FORMAT_RXY1 EXCLUSIVE OR (32) 2494 op_ZAP uint32 = 0xF800 // FORMAT_SS2 ZERO AND ADD 2495 op_BRRK uint32 = 0x0001 // FORMAT_E BREAKPOINT 2496 2497 // added in z13 2498 op_CXPT uint32 = 0xEDAF // RSL-b CONVERT FROM PACKED (to extended DFP) 2499 op_CDPT uint32 = 0xEDAE // RSL-b CONVERT FROM PACKED (to long DFP) 2500 op_CPXT uint32 = 0xEDAD // RSL-b CONVERT TO PACKED (from extended DFP) 2501 op_CPDT uint32 = 0xEDAC // RSL-b CONVERT TO PACKED (from long DFP) 2502 op_LZRF uint32 = 0xE33B // RXY-a LOAD AND ZERO RIGHTMOST BYTE (32) 2503 op_LZRG uint32 = 0xE32A // RXY-a LOAD AND ZERO RIGHTMOST BYTE (64) 2504 op_LCCB uint32 = 0xE727 // RXE LOAD COUNT TO BLOCK BOUNDARY 2505 op_LOCHHI uint32 = 0xEC4E // RIE-g LOAD HALFWORD HIGH IMMEDIATE ON CONDITION (32←16) 2506 op_LOCHI uint32 = 0xEC42 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (32←16) 2507 op_LOCGHI uint32 = 0xEC46 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (64←16) 2508 op_LOCFH uint32 = 0xEBE0 // RSY-b LOAD HIGH ON CONDITION (32) 2509 op_LOCFHR uint32 = 0xB9E0 // RRF-c LOAD HIGH ON CONDITION (32) 2510 op_LLZRGF uint32 = 0xE33A // RXY-a LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64←32) 2511 op_STOCFH uint32 = 0xEBE1 // RSY-b STORE HIGH ON CONDITION 2512 op_VA uint32 = 0xE7F3 // VRR-c VECTOR ADD 2513 op_VACC uint32 = 0xE7F1 // VRR-c VECTOR ADD COMPUTE CARRY 2514 op_VAC uint32 = 0xE7BB // VRR-d VECTOR ADD WITH CARRY 2515 op_VACCC uint32 = 0xE7B9 // VRR-d VECTOR ADD WITH CARRY COMPUTE CARRY 2516 op_VN uint32 = 0xE768 // VRR-c VECTOR AND 2517 op_VNC uint32 = 0xE769 // VRR-c VECTOR AND WITH COMPLEMENT 2518 op_VAVG uint32 = 0xE7F2 // VRR-c VECTOR AVERAGE 2519 op_VAVGL uint32 = 0xE7F0 // VRR-c VECTOR AVERAGE LOGICAL 2520 op_VCKSM uint32 = 0xE766 // VRR-c VECTOR CHECKSUM 2521 op_VCEQ uint32 = 0xE7F8 // VRR-b VECTOR COMPARE EQUAL 2522 op_VCH uint32 = 0xE7FB // VRR-b VECTOR COMPARE HIGH 2523 op_VCHL uint32 = 0xE7F9 // VRR-b VECTOR COMPARE HIGH LOGICAL 2524 op_VCLZ uint32 = 0xE753 // VRR-a VECTOR COUNT LEADING ZEROS 2525 op_VCTZ uint32 = 0xE752 // VRR-a VECTOR COUNT TRAILING ZEROS 2526 op_VEC uint32 = 0xE7DB // VRR-a VECTOR ELEMENT COMPARE 2527 op_VECL uint32 = 0xE7D9 // VRR-a VECTOR ELEMENT COMPARE LOGICAL 2528 op_VERIM uint32 = 0xE772 // VRI-d VECTOR ELEMENT ROTATE AND INSERT UNDER MASK 2529 op_VERLL uint32 = 0xE733 // VRS-a VECTOR ELEMENT ROTATE LEFT LOGICAL 2530 op_VERLLV uint32 = 0xE773 // VRR-c VECTOR ELEMENT ROTATE LEFT LOGICAL 2531 op_VESLV uint32 = 0xE770 // VRR-c VECTOR ELEMENT SHIFT LEFT 2532 op_VESL uint32 = 0xE730 // VRS-a VECTOR ELEMENT SHIFT LEFT 2533 op_VESRA uint32 = 0xE73A // VRS-a VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2534 op_VESRAV uint32 = 0xE77A // VRR-c VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2535 op_VESRL uint32 = 0xE738 // VRS-a VECTOR ELEMENT SHIFT RIGHT LOGICAL 2536 op_VESRLV uint32 = 0xE778 // VRR-c VECTOR ELEMENT SHIFT RIGHT LOGICAL 2537 op_VX uint32 = 0xE76D // VRR-c VECTOR EXCLUSIVE OR 2538 op_VFAE uint32 = 0xE782 // VRR-b VECTOR FIND ANY ELEMENT EQUAL 2539 op_VFEE uint32 = 0xE780 // VRR-b VECTOR FIND ELEMENT EQUAL 2540 op_VFENE uint32 = 0xE781 // VRR-b VECTOR FIND ELEMENT NOT EQUAL 2541 op_VFA uint32 = 0xE7E3 // VRR-c VECTOR FP ADD 2542 op_WFK uint32 = 0xE7CA // VRR-a VECTOR FP COMPARE AND SIGNAL SCALAR 2543 op_VFCE uint32 = 0xE7E8 // VRR-c VECTOR FP COMPARE EQUAL 2544 op_VFCH uint32 = 0xE7EB // VRR-c VECTOR FP COMPARE HIGH 2545 op_VFCHE uint32 = 0xE7EA // VRR-c VECTOR FP COMPARE HIGH OR EQUAL 2546 op_WFC uint32 = 0xE7CB // VRR-a VECTOR FP COMPARE SCALAR 2547 op_VCDG uint32 = 0xE7C3 // VRR-a VECTOR FP CONVERT FROM FIXED 64-BIT 2548 op_VCDLG uint32 = 0xE7C1 // VRR-a VECTOR FP CONVERT FROM LOGICAL 64-BIT 2549 op_VCGD uint32 = 0xE7C2 // VRR-a VECTOR FP CONVERT TO FIXED 64-BIT 2550 op_VCLGD uint32 = 0xE7C0 // VRR-a VECTOR FP CONVERT TO LOGICAL 64-BIT 2551 op_VFD uint32 = 0xE7E5 // VRR-c VECTOR FP DIVIDE 2552 op_VLDE uint32 = 0xE7C4 // VRR-a VECTOR FP LOAD LENGTHENED 2553 op_VLED uint32 = 0xE7C5 // VRR-a VECTOR FP LOAD ROUNDED 2554 op_VFM uint32 = 0xE7E7 // VRR-c VECTOR FP MULTIPLY 2555 op_VFMA uint32 = 0xE78F // VRR-e VECTOR FP MULTIPLY AND ADD 2556 op_VFMS uint32 = 0xE78E // VRR-e VECTOR FP MULTIPLY AND SUBTRACT 2557 op_VFPSO uint32 = 0xE7CC // VRR-a VECTOR FP PERFORM SIGN OPERATION 2558 op_VFSQ uint32 = 0xE7CE // VRR-a VECTOR FP SQUARE ROOT 2559 op_VFS uint32 = 0xE7E2 // VRR-c VECTOR FP SUBTRACT 2560 op_VFTCI uint32 = 0xE74A // VRI-e VECTOR FP TEST DATA CLASS IMMEDIATE 2561 op_VGFM uint32 = 0xE7B4 // VRR-c VECTOR GALOIS FIELD MULTIPLY SUM 2562 op_VGFMA uint32 = 0xE7BC // VRR-d VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE 2563 op_VGEF uint32 = 0xE713 // VRV VECTOR GATHER ELEMENT (32) 2564 op_VGEG uint32 = 0xE712 // VRV VECTOR GATHER ELEMENT (64) 2565 op_VGBM uint32 = 0xE744 // VRI-a VECTOR GENERATE BYTE MASK 2566 op_VGM uint32 = 0xE746 // VRI-b VECTOR GENERATE MASK 2567 op_VISTR uint32 = 0xE75C // VRR-a VECTOR ISOLATE STRING 2568 op_VL uint32 = 0xE706 // VRX VECTOR LOAD 2569 op_VLR uint32 = 0xE756 // VRR-a VECTOR LOAD 2570 op_VLREP uint32 = 0xE705 // VRX VECTOR LOAD AND REPLICATE 2571 op_VLC uint32 = 0xE7DE // VRR-a VECTOR LOAD COMPLEMENT 2572 op_VLEH uint32 = 0xE701 // VRX VECTOR LOAD ELEMENT (16) 2573 op_VLEF uint32 = 0xE703 // VRX VECTOR LOAD ELEMENT (32) 2574 op_VLEG uint32 = 0xE702 // VRX VECTOR LOAD ELEMENT (64) 2575 op_VLEB uint32 = 0xE700 // VRX VECTOR LOAD ELEMENT (8) 2576 op_VLEIH uint32 = 0xE741 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (16) 2577 op_VLEIF uint32 = 0xE743 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (32) 2578 op_VLEIG uint32 = 0xE742 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (64) 2579 op_VLEIB uint32 = 0xE740 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (8) 2580 op_VFI uint32 = 0xE7C7 // VRR-a VECTOR LOAD FP INTEGER 2581 op_VLGV uint32 = 0xE721 // VRS-c VECTOR LOAD GR FROM VR ELEMENT 2582 op_VLLEZ uint32 = 0xE704 // VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO 2583 op_VLM uint32 = 0xE736 // VRS-a VECTOR LOAD MULTIPLE 2584 op_VLP uint32 = 0xE7DF // VRR-a VECTOR LOAD POSITIVE 2585 op_VLBB uint32 = 0xE707 // VRX VECTOR LOAD TO BLOCK BOUNDARY 2586 op_VLVG uint32 = 0xE722 // VRS-b VECTOR LOAD VR ELEMENT FROM GR 2587 op_VLVGP uint32 = 0xE762 // VRR-f VECTOR LOAD VR FROM GRS DISJOINT 2588 op_VLL uint32 = 0xE737 // VRS-b VECTOR LOAD WITH LENGTH 2589 op_VMX uint32 = 0xE7FF // VRR-c VECTOR MAXIMUM 2590 op_VMXL uint32 = 0xE7FD // VRR-c VECTOR MAXIMUM LOGICAL 2591 op_VMRH uint32 = 0xE761 // VRR-c VECTOR MERGE HIGH 2592 op_VMRL uint32 = 0xE760 // VRR-c VECTOR MERGE LOW 2593 op_VMN uint32 = 0xE7FE // VRR-c VECTOR MINIMUM 2594 op_VMNL uint32 = 0xE7FC // VRR-c VECTOR MINIMUM LOGICAL 2595 op_VMAE uint32 = 0xE7AE // VRR-d VECTOR MULTIPLY AND ADD EVEN 2596 op_VMAH uint32 = 0xE7AB // VRR-d VECTOR MULTIPLY AND ADD HIGH 2597 op_VMALE uint32 = 0xE7AC // VRR-d VECTOR MULTIPLY AND ADD LOGICAL EVEN 2598 op_VMALH uint32 = 0xE7A9 // VRR-d VECTOR MULTIPLY AND ADD LOGICAL HIGH 2599 op_VMALO uint32 = 0xE7AD // VRR-d VECTOR MULTIPLY AND ADD LOGICAL ODD 2600 op_VMAL uint32 = 0xE7AA // VRR-d VECTOR MULTIPLY AND ADD LOW 2601 op_VMAO uint32 = 0xE7AF // VRR-d VECTOR MULTIPLY AND ADD ODD 2602 op_VME uint32 = 0xE7A6 // VRR-c VECTOR MULTIPLY EVEN 2603 op_VMH uint32 = 0xE7A3 // VRR-c VECTOR MULTIPLY HIGH 2604 op_VMLE uint32 = 0xE7A4 // VRR-c VECTOR MULTIPLY EVEN LOGICAL 2605 op_VMLH uint32 = 0xE7A1 // VRR-c VECTOR MULTIPLY HIGH LOGICAL 2606 op_VMLO uint32 = 0xE7A5 // VRR-c VECTOR MULTIPLY ODD LOGICAL 2607 op_VML uint32 = 0xE7A2 // VRR-c VECTOR MULTIPLY LOW 2608 op_VMO uint32 = 0xE7A7 // VRR-c VECTOR MULTIPLY ODD 2609 op_VNO uint32 = 0xE76B // VRR-c VECTOR NOR 2610 op_VO uint32 = 0xE76A // VRR-c VECTOR OR 2611 op_VPK uint32 = 0xE794 // VRR-c VECTOR PACK 2612 op_VPKLS uint32 = 0xE795 // VRR-b VECTOR PACK LOGICAL SATURATE 2613 op_VPKS uint32 = 0xE797 // VRR-b VECTOR PACK SATURATE 2614 op_VPERM uint32 = 0xE78C // VRR-e VECTOR PERMUTE 2615 op_VPDI uint32 = 0xE784 // VRR-c VECTOR PERMUTE DOUBLEWORD IMMEDIATE 2616 op_VPOPCT uint32 = 0xE750 // VRR-a VECTOR POPULATION COUNT 2617 op_VREP uint32 = 0xE74D // VRI-c VECTOR REPLICATE 2618 op_VREPI uint32 = 0xE745 // VRI-a VECTOR REPLICATE IMMEDIATE 2619 op_VSCEF uint32 = 0xE71B // VRV VECTOR SCATTER ELEMENT (32) 2620 op_VSCEG uint32 = 0xE71A // VRV VECTOR SCATTER ELEMENT (64) 2621 op_VSEL uint32 = 0xE78D // VRR-e VECTOR SELECT 2622 op_VSL uint32 = 0xE774 // VRR-c VECTOR SHIFT LEFT 2623 op_VSLB uint32 = 0xE775 // VRR-c VECTOR SHIFT LEFT BY BYTE 2624 op_VSLDB uint32 = 0xE777 // VRI-d VECTOR SHIFT LEFT DOUBLE BY BYTE 2625 op_VSRA uint32 = 0xE77E // VRR-c VECTOR SHIFT RIGHT ARITHMETIC 2626 op_VSRAB uint32 = 0xE77F // VRR-c VECTOR SHIFT RIGHT ARITHMETIC BY BYTE 2627 op_VSRL uint32 = 0xE77C // VRR-c VECTOR SHIFT RIGHT LOGICAL 2628 op_VSRLB uint32 = 0xE77D // VRR-c VECTOR SHIFT RIGHT LOGICAL BY BYTE 2629 op_VSEG uint32 = 0xE75F // VRR-a VECTOR SIGN EXTEND TO DOUBLEWORD 2630 op_VST uint32 = 0xE70E // VRX VECTOR STORE 2631 op_VSTEH uint32 = 0xE709 // VRX VECTOR STORE ELEMENT (16) 2632 op_VSTEF uint32 = 0xE70B // VRX VECTOR STORE ELEMENT (32) 2633 op_VSTEG uint32 = 0xE70A // VRX VECTOR STORE ELEMENT (64) 2634 op_VSTEB uint32 = 0xE708 // VRX VECTOR STORE ELEMENT (8) 2635 op_VSTM uint32 = 0xE73E // VRS-a VECTOR STORE MULTIPLE 2636 op_VSTL uint32 = 0xE73F // VRS-b VECTOR STORE WITH LENGTH 2637 op_VSTRC uint32 = 0xE78A // VRR-d VECTOR STRING RANGE COMPARE 2638 op_VS uint32 = 0xE7F7 // VRR-c VECTOR SUBTRACT 2639 op_VSCBI uint32 = 0xE7F5 // VRR-c VECTOR SUBTRACT COMPUTE BORROW INDICATION 2640 op_VSBCBI uint32 = 0xE7BD // VRR-d VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION 2641 op_VSBI uint32 = 0xE7BF // VRR-d VECTOR SUBTRACT WITH BORROW INDICATION 2642 op_VSUMG uint32 = 0xE765 // VRR-c VECTOR SUM ACROSS DOUBLEWORD 2643 op_VSUMQ uint32 = 0xE767 // VRR-c VECTOR SUM ACROSS QUADWORD 2644 op_VSUM uint32 = 0xE764 // VRR-c VECTOR SUM ACROSS WORD 2645 op_VTM uint32 = 0xE7D8 // VRR-a VECTOR TEST UNDER MASK 2646 op_VUPH uint32 = 0xE7D7 // VRR-a VECTOR UNPACK HIGH 2647 op_VUPLH uint32 = 0xE7D5 // VRR-a VECTOR UNPACK LOGICAL HIGH 2648 op_VUPLL uint32 = 0xE7D4 // VRR-a VECTOR UNPACK LOGICAL LOW 2649 op_VUPL uint32 = 0xE7D6 // VRR-a VECTOR UNPACK LOW 2650 op_VMSL uint32 = 0xE7B8 // VRR-d VECTOR MULTIPLY SUM LOGICAL 2651 2652 // added in z15 2653 op_KDSA uint32 = 0xB93A // FORMAT_RRE COMPUTE DIGITAL SIGNATURE AUTHENTICATION (KDSA) 2654 2655 ) 2656 2657 func oclass(a *obj.Addr) int { 2658 return int(a.Class) - 1 2659 } 2660 2661 // Add a relocation for the immediate in a RIL style instruction. 2662 // The addend will be adjusted as required. 2663 func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) *obj.Reloc { 2664 if sym == nil { 2665 c.ctxt.Diag("require symbol to apply relocation") 2666 } 2667 offset := int64(2) // relocation offset from start of instruction 2668 rel := obj.Addrel(c.cursym) 2669 rel.Off = int32(c.pc + offset) 2670 rel.Siz = 4 2671 rel.Sym = sym 2672 rel.Add = add + offset + int64(rel.Siz) 2673 rel.Type = objabi.R_PCRELDBL 2674 return rel 2675 } 2676 2677 func (c *ctxtz) addrilrelocoffset(sym *obj.LSym, add, offset int64) *obj.Reloc { 2678 if sym == nil { 2679 c.ctxt.Diag("require symbol to apply relocation") 2680 } 2681 offset += int64(2) // relocation offset from start of instruction 2682 rel := obj.Addrel(c.cursym) 2683 rel.Off = int32(c.pc + offset) 2684 rel.Siz = 4 2685 rel.Sym = sym 2686 rel.Add = add + offset + int64(rel.Siz) 2687 rel.Type = objabi.R_PCRELDBL 2688 return rel 2689 } 2690 2691 // Add a CALL relocation for the immediate in a RIL style instruction. 2692 // The addend will be adjusted as required. 2693 func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) *obj.Reloc { 2694 if sym == nil { 2695 c.ctxt.Diag("require symbol to apply relocation") 2696 } 2697 offset := int64(2) // relocation offset from start of instruction 2698 rel := obj.Addrel(c.cursym) 2699 rel.Off = int32(c.pc + offset) 2700 rel.Siz = 4 2701 rel.Sym = sym 2702 rel.Add = add + offset + int64(rel.Siz) 2703 rel.Type = objabi.R_CALL 2704 return rel 2705 } 2706 2707 func (c *ctxtz) branchMask(p *obj.Prog) CCMask { 2708 switch p.As { 2709 case ABRC, ALOCR, ALOCGR, 2710 ACRJ, ACGRJ, ACIJ, ACGIJ, 2711 ACLRJ, ACLGRJ, ACLIJ, ACLGIJ: 2712 return CCMask(p.From.Offset) 2713 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ: 2714 return Equal 2715 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE: 2716 return GreaterOrEqual 2717 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT: 2718 return Greater 2719 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE: 2720 return LessOrEqual 2721 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT: 2722 return Less 2723 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE: 2724 return NotEqual 2725 case ABLEU: // LE or unordered 2726 return NotGreater 2727 case ABLTU: // LT or unordered 2728 return LessOrUnordered 2729 case ABVC: 2730 return Never // needs extra instruction 2731 case ABVS: 2732 return Unordered 2733 } 2734 c.ctxt.Diag("unknown conditional branch %v", p.As) 2735 return Always 2736 } 2737 2738 func regtmp(p *obj.Prog) uint32 { 2739 p.Mark |= USETMP 2740 return REGTMP 2741 } 2742 2743 func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) { 2744 o := c.oplook(p) 2745 2746 if o == nil { 2747 return 2748 } 2749 2750 // If REGTMP is used in generated code, we need to set USETMP on p.Mark. 2751 // So we use regtmp(p) for REGTMP. 2752 2753 switch o.i { 2754 default: 2755 c.ctxt.Diag("unknown index %d", o.i) 2756 2757 case 0: // PSEUDO OPS 2758 break 2759 2760 case 1: // mov reg reg 2761 switch p.As { 2762 default: 2763 c.ctxt.Diag("unhandled operation: %v", p.As) 2764 case AMOVD: 2765 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2766 // sign extend 2767 case AMOVW: 2768 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2769 case AMOVH: 2770 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2771 case AMOVB: 2772 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2773 // zero extend 2774 case AMOVWZ: 2775 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2776 case AMOVHZ: 2777 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2778 case AMOVBZ: 2779 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2780 // reverse bytes 2781 case AMOVDBR: 2782 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2783 case AMOVWBR: 2784 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2785 // floating point 2786 case AFMOVD, AFMOVS: 2787 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2788 } 2789 2790 case 2: // arithmetic op reg [reg] reg 2791 r := p.Reg 2792 if r == 0 { 2793 r = p.To.Reg 2794 } 2795 2796 var opcode uint32 2797 2798 switch p.As { 2799 default: 2800 c.ctxt.Diag("invalid opcode") 2801 case AADD: 2802 opcode = op_AGRK 2803 case AADDC: 2804 opcode = op_ALGRK 2805 case AADDE: 2806 opcode = op_ALCGR 2807 case AADDW: 2808 opcode = op_ARK 2809 case AMULLW: 2810 opcode = op_MSGFR 2811 case AMULLD: 2812 opcode = op_MSGR 2813 case ADIVW, AMODW: 2814 opcode = op_DSGFR 2815 case ADIVWU, AMODWU: 2816 opcode = op_DLR 2817 case ADIVD, AMODD: 2818 opcode = op_DSGR 2819 case ADIVDU, AMODDU: 2820 opcode = op_DLGR 2821 } 2822 2823 switch p.As { 2824 default: 2825 2826 case AADD, AADDC, AADDW: 2827 if p.As == AADDW && r == p.To.Reg { 2828 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2829 } else { 2830 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2831 } 2832 2833 case AADDE, AMULLW, AMULLD: 2834 if r == p.To.Reg { 2835 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2836 } else if p.From.Reg == p.To.Reg { 2837 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2838 } else { 2839 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2840 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2841 } 2842 2843 case ADIVW, ADIVWU, ADIVD, ADIVDU: 2844 if p.As == ADIVWU || p.As == ADIVDU { 2845 zRI(op_LGHI, regtmp(p), 0, asm) 2846 } 2847 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2848 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm) 2849 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm) 2850 2851 case AMODW, AMODWU, AMODD, AMODDU: 2852 if p.As == AMODWU || p.As == AMODDU { 2853 zRI(op_LGHI, regtmp(p), 0, asm) 2854 } 2855 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2856 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm) 2857 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm) 2858 2859 } 2860 2861 case 3: // mov $constant reg 2862 v := c.vregoff(&p.From) 2863 switch p.As { 2864 case AMOVBZ: 2865 v = int64(uint8(v)) 2866 case AMOVHZ: 2867 v = int64(uint16(v)) 2868 case AMOVWZ: 2869 v = int64(uint32(v)) 2870 case AMOVB: 2871 v = int64(int8(v)) 2872 case AMOVH: 2873 v = int64(int16(v)) 2874 case AMOVW: 2875 v = int64(int32(v)) 2876 } 2877 if int64(int16(v)) == v { 2878 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm) 2879 } else if v&0xffff0000 == v { 2880 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm) 2881 } else if v&0xffff00000000 == v { 2882 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm) 2883 } else if uint64(v)&0xffff000000000000 == uint64(v) { 2884 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm) 2885 } else if int64(int32(v)) == v { 2886 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm) 2887 } else if int64(uint32(v)) == v { 2888 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2889 } else if uint64(v)&0xffffffff00000000 == uint64(v) { 2890 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2891 } else { 2892 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2893 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2894 } 2895 2896 case 4: // multiply high (a*b)>>64 2897 r := p.Reg 2898 if r == 0 { 2899 r = p.To.Reg 2900 } 2901 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2902 zRRE(op_MLGR, regtmp(p), uint32(p.From.Reg), asm) 2903 switch p.As { 2904 case AMULHDU: 2905 // Unsigned: move result into correct register. 2906 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm) 2907 case AMULHD: 2908 // Signed: need to convert result. 2909 // See Hacker's Delight 8-3. 2910 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm) 2911 zRRE(op_NGR, REGTMP2, uint32(r), asm) 2912 zRRE(op_SGR, regtmp(p), REGTMP2, asm) 2913 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm) 2914 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm) 2915 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), regtmp(p), asm) 2916 } 2917 2918 case 5: // syscall 2919 zI(op_SVC, 0, asm) 2920 2921 case 6: // logical op reg [reg] reg 2922 var oprr, oprre, oprrf uint32 2923 switch p.As { 2924 case AAND: 2925 oprre = op_NGR 2926 oprrf = op_NGRK 2927 case AANDW: 2928 oprr = op_NR 2929 oprrf = op_NRK 2930 case AOR: 2931 oprre = op_OGR 2932 oprrf = op_OGRK 2933 case AORW: 2934 oprr = op_OR 2935 oprrf = op_ORK 2936 case AXOR: 2937 oprre = op_XGR 2938 oprrf = op_XGRK 2939 case AXORW: 2940 oprr = op_XR 2941 oprrf = op_XRK 2942 } 2943 if p.Reg == 0 { 2944 if oprr != 0 { 2945 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2946 } else { 2947 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2948 } 2949 } else { 2950 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2951 } 2952 2953 case 7: // shift/rotate reg [reg] reg 2954 d2 := c.vregoff(&p.From) 2955 b2 := p.From.Reg 2956 r3 := p.Reg 2957 if r3 == 0 { 2958 r3 = p.To.Reg 2959 } 2960 r1 := p.To.Reg 2961 var opcode uint32 2962 switch p.As { 2963 default: 2964 case ASLD: 2965 opcode = op_SLLG 2966 case ASRD: 2967 opcode = op_SRLG 2968 case ASLW: 2969 opcode = op_SLLK 2970 case ASRW: 2971 opcode = op_SRLK 2972 case ARLL: 2973 opcode = op_RLL 2974 case ARLLG: 2975 opcode = op_RLLG 2976 case ASRAW: 2977 opcode = op_SRAK 2978 case ASRAD: 2979 opcode = op_SRAG 2980 } 2981 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm) 2982 2983 case 8: // find leftmost one 2984 if p.To.Reg&1 != 0 { 2985 c.ctxt.Diag("target must be an even-numbered register") 2986 } 2987 // FLOGR also writes a mask to p.To.Reg+1. 2988 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2989 2990 case 9: // population count 2991 zRRE(op_POPCNT, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2992 2993 case 10: // subtract reg [reg] reg 2994 r := int(p.Reg) 2995 2996 switch p.As { 2997 default: 2998 case ASUB: 2999 if r == 0 { 3000 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3001 } else { 3002 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 3003 } 3004 case ASUBC: 3005 if r == 0 { 3006 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3007 } else { 3008 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 3009 } 3010 case ASUBE: 3011 if r == 0 { 3012 r = int(p.To.Reg) 3013 } 3014 if r == int(p.To.Reg) { 3015 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3016 } else if p.From.Reg == p.To.Reg { 3017 zRRE(op_LGR, regtmp(p), uint32(p.From.Reg), asm) 3018 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3019 zRRE(op_SLBGR, uint32(p.To.Reg), regtmp(p), asm) 3020 } else { 3021 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3022 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3023 } 3024 case ASUBW: 3025 if r == 0 { 3026 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3027 } else { 3028 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 3029 } 3030 } 3031 3032 case 11: // br/bl 3033 v := int32(0) 3034 3035 if p.To.Target() != nil { 3036 v = int32((p.To.Target().Pc - p.Pc) >> 1) 3037 } 3038 3039 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v { 3040 zRI(op_BRC, 0xF, uint32(v), asm) 3041 } else { 3042 if p.As == ABL { 3043 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm) 3044 } else { 3045 zRIL(_c, op_BRCL, 0xF, uint32(v), asm) 3046 } 3047 if p.To.Sym != nil { 3048 c.addcallreloc(p.To.Sym, p.To.Offset) 3049 } 3050 } 3051 3052 case 12: 3053 r1 := p.To.Reg 3054 d2 := c.vregoff(&p.From) 3055 b2 := p.From.Reg 3056 if b2 == 0 { 3057 b2 = REGSP 3058 } 3059 x2 := p.From.Index 3060 if -DISP20/2 > d2 || d2 >= DISP20/2 { 3061 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm) 3062 if x2 != 0 { 3063 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm) 3064 } 3065 x2 = int16(regtmp(p)) 3066 d2 = 0 3067 } 3068 var opx, opxy uint32 3069 switch p.As { 3070 case AADD: 3071 opxy = op_AG 3072 case AADDC: 3073 opxy = op_ALG 3074 case AADDE: 3075 opxy = op_ALCG 3076 case AADDW: 3077 opx = op_A 3078 opxy = op_AY 3079 case AMULLW: 3080 opx = op_MS 3081 opxy = op_MSY 3082 case AMULLD: 3083 opxy = op_MSG 3084 case ASUB: 3085 opxy = op_SG 3086 case ASUBC: 3087 opxy = op_SLG 3088 case ASUBE: 3089 opxy = op_SLBG 3090 case ASUBW: 3091 opx = op_S 3092 opxy = op_SY 3093 case AAND: 3094 opxy = op_NG 3095 case AANDW: 3096 opx = op_N 3097 opxy = op_NY 3098 case AOR: 3099 opxy = op_OG 3100 case AORW: 3101 opx = op_O 3102 opxy = op_OY 3103 case AXOR: 3104 opxy = op_XG 3105 case AXORW: 3106 opx = op_X 3107 opxy = op_XY 3108 } 3109 if opx != 0 && 0 <= d2 && d2 < DISP12 { 3110 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 3111 } else { 3112 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 3113 } 3114 3115 case 13: // rotate, followed by operation 3116 r1 := p.To.Reg 3117 r2 := p.RestArgs[2].Reg 3118 i3 := uint8(p.From.Offset) // start 3119 i4 := uint8(p.RestArgs[0].Offset) // end 3120 i5 := uint8(p.RestArgs[1].Offset) // rotate amount 3121 switch p.As { 3122 case ARNSBGT, ARXSBGT, AROSBGT: 3123 i3 |= 0x80 // test-results 3124 case ARISBGZ, ARISBGNZ, ARISBHGZ, ARISBLGZ: 3125 i4 |= 0x80 // zero-remaining-bits 3126 } 3127 var opcode uint32 3128 switch p.As { 3129 case ARNSBG, ARNSBGT: 3130 opcode = op_RNSBG 3131 case ARXSBG, ARXSBGT: 3132 opcode = op_RXSBG 3133 case AROSBG, AROSBGT: 3134 opcode = op_ROSBG 3135 case ARISBG, ARISBGZ: 3136 opcode = op_RISBG 3137 case ARISBGN, ARISBGNZ: 3138 opcode = op_RISBGN 3139 case ARISBHG, ARISBHGZ: 3140 opcode = op_RISBHG 3141 case ARISBLG, ARISBLGZ: 3142 opcode = op_RISBLG 3143 } 3144 zRIE(_f, uint32(opcode), uint32(r1), uint32(r2), 0, uint32(i3), uint32(i4), 0, uint32(i5), asm) 3145 3146 case 15: // br/bl (reg) 3147 r := p.To.Reg 3148 if p.As == ABCL || p.As == ABL { 3149 zRR(op_BASR, uint32(REG_LR), uint32(r), asm) 3150 } else { 3151 zRR(op_BCR, uint32(Always), uint32(r), asm) 3152 } 3153 3154 case 16: // conditional branch 3155 v := int32(0) 3156 if p.To.Target() != nil { 3157 v = int32((p.To.Target().Pc - p.Pc) >> 1) 3158 } 3159 mask := uint32(c.branchMask(p)) 3160 if p.To.Sym == nil && int32(int16(v)) == v { 3161 zRI(op_BRC, mask, uint32(v), asm) 3162 } else { 3163 zRIL(_c, op_BRCL, mask, uint32(v), asm) 3164 } 3165 if p.To.Sym != nil { 3166 c.addrilreloc(p.To.Sym, p.To.Offset) 3167 } 3168 3169 case 17: // move on condition 3170 m3 := uint32(c.branchMask(p)) 3171 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3172 3173 case 18: // br/bl reg 3174 if p.As == ABL { 3175 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm) 3176 } else { 3177 zRR(op_BCR, uint32(Always), uint32(p.To.Reg), asm) 3178 } 3179 3180 case 19: // mov $sym+n(SB) reg 3181 d := c.vregoff(&p.From) 3182 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm) 3183 if d&1 != 0 { 3184 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm) 3185 d -= 1 3186 } 3187 c.addrilreloc(p.From.Sym, d) 3188 3189 case 21: // subtract $constant [reg] reg 3190 v := c.vregoff(&p.From) 3191 r := p.Reg 3192 if r == 0 { 3193 r = p.To.Reg 3194 } 3195 switch p.As { 3196 case ASUB: 3197 zRIL(_a, op_LGFI, uint32(regtmp(p)), uint32(v), asm) 3198 zRRF(op_SLGRK, uint32(regtmp(p)), 0, uint32(p.To.Reg), uint32(r), asm) 3199 case ASUBC: 3200 if r != p.To.Reg { 3201 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3202 } 3203 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm) 3204 case ASUBW: 3205 if r != p.To.Reg { 3206 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3207 } 3208 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm) 3209 } 3210 3211 case 22: // add/multiply $constant [reg] reg 3212 v := c.vregoff(&p.From) 3213 r := p.Reg 3214 if r == 0 { 3215 r = p.To.Reg 3216 } 3217 var opri, opril, oprie uint32 3218 switch p.As { 3219 case AADD: 3220 opri = op_AGHI 3221 opril = op_AGFI 3222 oprie = op_AGHIK 3223 case AADDC: 3224 opril = op_ALGFI 3225 oprie = op_ALGHSIK 3226 case AADDW: 3227 opri = op_AHI 3228 opril = op_AFI 3229 oprie = op_AHIK 3230 case AMULLW: 3231 opri = op_MHI 3232 opril = op_MSFI 3233 case AMULLD: 3234 opri = op_MGHI 3235 opril = op_MSGFI 3236 } 3237 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) { 3238 switch p.As { 3239 case AADD, AADDC, AMULLD: 3240 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3241 case AADDW, AMULLW: 3242 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3243 } 3244 r = p.To.Reg 3245 } 3246 if opri != 0 && r == p.To.Reg && int64(int16(v)) == v { 3247 zRI(opri, uint32(p.To.Reg), uint32(v), asm) 3248 } else if oprie != 0 && int64(int16(v)) == v { 3249 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm) 3250 } else { 3251 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm) 3252 } 3253 3254 case 23: // 64-bit logical op $constant reg 3255 // TODO(mundaym): merge with case 24. 3256 v := c.vregoff(&p.From) 3257 switch p.As { 3258 default: 3259 c.ctxt.Diag("%v is not supported", p) 3260 case AAND: 3261 if v >= 0 { // needs zero extend 3262 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm) 3263 zRRE(op_NGR, uint32(p.To.Reg), regtmp(p), asm) 3264 } else if int64(int16(v)) == v { 3265 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3266 } else { // r.To.Reg & 0xffffffff00000000 & uint32(v) 3267 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3268 } 3269 case AOR: 3270 if int64(uint32(v)) != v { // needs sign extend 3271 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm) 3272 zRRE(op_OGR, uint32(p.To.Reg), regtmp(p), asm) 3273 } else if int64(uint16(v)) == v { 3274 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3275 } else { 3276 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3277 } 3278 case AXOR: 3279 if int64(uint32(v)) != v { // needs sign extend 3280 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm) 3281 zRRE(op_XGR, uint32(p.To.Reg), regtmp(p), asm) 3282 } else { 3283 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3284 } 3285 } 3286 3287 case 24: // 32-bit logical op $constant reg 3288 v := c.vregoff(&p.From) 3289 switch p.As { 3290 case AANDW: 3291 if uint32(v&0xffff0000) == 0xffff0000 { 3292 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3293 } else if uint32(v&0x0000ffff) == 0x0000ffff { 3294 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3295 } else { 3296 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3297 } 3298 case AORW: 3299 if uint32(v&0xffff0000) == 0 { 3300 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3301 } else if uint32(v&0x0000ffff) == 0 { 3302 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3303 } else { 3304 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3305 } 3306 case AXORW: 3307 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3308 } 3309 3310 case 25: // load on condition (register) 3311 m3 := uint32(c.branchMask(p)) 3312 var opcode uint32 3313 switch p.As { 3314 case ALOCR: 3315 opcode = op_LOCR 3316 case ALOCGR: 3317 opcode = op_LOCGR 3318 } 3319 zRRF(opcode, m3, 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3320 3321 case 26: // MOVD $offset(base)(index), reg 3322 v := c.regoff(&p.From) 3323 r := p.From.Reg 3324 if r == 0 { 3325 r = REGSP 3326 } 3327 i := p.From.Index 3328 if v >= 0 && v < DISP12 { 3329 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3330 } else if v >= -DISP20/2 && v < DISP20/2 { 3331 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3332 } else { 3333 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm) 3334 zRX(op_LA, uint32(p.To.Reg), uint32(r), regtmp(p), uint32(i), asm) 3335 } 3336 3337 case 31: // dword 3338 wd := uint64(c.vregoff(&p.From)) 3339 *asm = append(*asm, 3340 uint8(wd>>56), 3341 uint8(wd>>48), 3342 uint8(wd>>40), 3343 uint8(wd>>32), 3344 uint8(wd>>24), 3345 uint8(wd>>16), 3346 uint8(wd>>8), 3347 uint8(wd)) 3348 3349 case 32: // float op freg freg 3350 var opcode uint32 3351 switch p.As { 3352 default: 3353 c.ctxt.Diag("invalid opcode") 3354 case AFADD: 3355 opcode = op_ADBR 3356 case AFADDS: 3357 opcode = op_AEBR 3358 case AFDIV: 3359 opcode = op_DDBR 3360 case AFDIVS: 3361 opcode = op_DEBR 3362 case AFMUL: 3363 opcode = op_MDBR 3364 case AFMULS: 3365 opcode = op_MEEBR 3366 case AFSUB: 3367 opcode = op_SDBR 3368 case AFSUBS: 3369 opcode = op_SEBR 3370 } 3371 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3372 3373 case 33: // float op [freg] freg 3374 r := p.From.Reg 3375 if oclass(&p.From) == C_NONE { 3376 r = p.To.Reg 3377 } 3378 var opcode uint32 3379 switch p.As { 3380 default: 3381 case AFABS: 3382 opcode = op_LPDBR 3383 case AFNABS: 3384 opcode = op_LNDBR 3385 case ALPDFR: 3386 opcode = op_LPDFR 3387 case ALNDFR: 3388 opcode = op_LNDFR 3389 case AFNEG: 3390 opcode = op_LCDFR 3391 case AFNEGS: 3392 opcode = op_LCEBR 3393 case ALEDBR: 3394 opcode = op_LEDBR 3395 case ALDEBR: 3396 opcode = op_LDEBR 3397 case AFSQRT: 3398 opcode = op_SQDBR 3399 case AFSQRTS: 3400 opcode = op_SQEBR 3401 } 3402 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3403 3404 case 34: // float multiply-add freg freg freg 3405 var opcode uint32 3406 switch p.As { 3407 default: 3408 c.ctxt.Diag("invalid opcode") 3409 case AFMADD: 3410 opcode = op_MADBR 3411 case AFMADDS: 3412 opcode = op_MAEBR 3413 case AFMSUB: 3414 opcode = op_MSDBR 3415 case AFMSUBS: 3416 opcode = op_MSEBR 3417 } 3418 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 3419 3420 case 35: // mov reg mem (no relocation) 3421 d2 := c.regoff(&p.To) 3422 b2 := p.To.Reg 3423 if b2 == 0 { 3424 b2 = REGSP 3425 } 3426 x2 := p.To.Index 3427 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3428 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm) 3429 if x2 != 0 { 3430 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm) 3431 } 3432 x2 = int16(regtmp(p)) 3433 d2 = 0 3434 } 3435 // Emits an RX instruction if an appropriate one exists and the displacement fits in 12 bits. Otherwise use an RXY instruction. 3436 if op, ok := c.zopstore12(p.As); ok && isU12(d2) { 3437 zRX(op, uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3438 } else { 3439 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3440 } 3441 3442 case 36: // mov mem reg (no relocation) 3443 d2 := c.regoff(&p.From) 3444 b2 := p.From.Reg 3445 if b2 == 0 { 3446 b2 = REGSP 3447 } 3448 x2 := p.From.Index 3449 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3450 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm) 3451 if x2 != 0 { 3452 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm) 3453 } 3454 x2 = int16(regtmp(p)) 3455 d2 = 0 3456 } 3457 // Emits an RX instruction if an appropriate one exists and the displacement fits in 12 bits. Otherwise use an RXY instruction. 3458 if op, ok := c.zopload12(p.As); ok && isU12(d2) { 3459 zRX(op, uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3460 } else { 3461 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3462 } 3463 3464 case 40: // word/byte 3465 wd := uint32(c.regoff(&p.From)) 3466 if p.As == AWORD { //WORD 3467 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd)) 3468 } else { //BYTE 3469 *asm = append(*asm, uint8(wd)) 3470 } 3471 3472 case 41: // branch on count 3473 r1 := p.From.Reg 3474 ri2 := (p.To.Target().Pc - p.Pc) >> 1 3475 if int64(int16(ri2)) != ri2 { 3476 c.ctxt.Diag("branch target too far away") 3477 } 3478 var opcode uint32 3479 switch p.As { 3480 case ABRCT: 3481 opcode = op_BRCT 3482 case ABRCTG: 3483 opcode = op_BRCTG 3484 } 3485 zRI(opcode, uint32(r1), uint32(ri2), asm) 3486 3487 case 47: // negate [reg] reg 3488 r := p.From.Reg 3489 if r == 0 { 3490 r = p.To.Reg 3491 } 3492 switch p.As { 3493 case ANEG: 3494 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm) 3495 case ANEGW: 3496 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm) 3497 } 3498 3499 case 48: // floating-point round to integer 3500 m3 := c.vregoff(&p.From) 3501 if 0 > m3 || m3 > 7 { 3502 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3) 3503 } 3504 var opcode uint32 3505 switch p.As { 3506 case AFIEBR: 3507 opcode = op_FIEBR 3508 case AFIDBR: 3509 opcode = op_FIDBR 3510 } 3511 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3512 3513 case 49: // copysign 3514 zRRF(op_CPSDR, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3515 3516 case 50: // load and test 3517 var opcode uint32 3518 switch p.As { 3519 case ALTEBR: 3520 opcode = op_LTEBR 3521 case ALTDBR: 3522 opcode = op_LTDBR 3523 } 3524 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3525 3526 case 51: // test data class (immediate only) 3527 var opcode uint32 3528 switch p.As { 3529 case ATCEB: 3530 opcode = op_TCEB 3531 case ATCDB: 3532 opcode = op_TCDB 3533 } 3534 d2 := c.regoff(&p.To) 3535 zRXE(opcode, uint32(p.From.Reg), 0, 0, uint32(d2), 0, asm) 3536 3537 case 62: // equivalent of Mul64 in math/bits 3538 zRRE(op_MLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3539 3540 case 66: 3541 zRR(op_BCR, uint32(Never), 0, asm) 3542 3543 case 67: // fmov $0 freg 3544 var opcode uint32 3545 switch p.As { 3546 case AFMOVS: 3547 opcode = op_LZER 3548 case AFMOVD: 3549 opcode = op_LZDR 3550 } 3551 zRRE(opcode, uint32(p.To.Reg), 0, asm) 3552 3553 case 68: // movw areg reg 3554 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm) 3555 3556 case 69: // movw reg areg 3557 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm) 3558 3559 case 70: // cmp reg reg 3560 if p.As == ACMPW || p.As == ACMPWU { 3561 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3562 } else { 3563 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3564 } 3565 3566 case 71: // cmp reg $constant 3567 v := c.vregoff(&p.To) 3568 switch p.As { 3569 case ACMP, ACMPW: 3570 if int64(int32(v)) != v { 3571 c.ctxt.Diag("%v overflows an int32", v) 3572 } 3573 case ACMPU, ACMPWU: 3574 if int64(uint32(v)) != v { 3575 c.ctxt.Diag("%v overflows a uint32", v) 3576 } 3577 } 3578 if p.As == ACMP && int64(int16(v)) == v { 3579 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm) 3580 } else if p.As == ACMPW && int64(int16(v)) == v { 3581 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm) 3582 } else { 3583 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm) 3584 } 3585 3586 case 72: // mov $constant mem 3587 v := c.regoff(&p.From) 3588 d := c.regoff(&p.To) 3589 r := p.To.Reg 3590 if p.To.Index != 0 { 3591 c.ctxt.Diag("cannot use index register") 3592 } 3593 if r == 0 { 3594 r = REGSP 3595 } 3596 var opcode uint32 3597 switch p.As { 3598 case AMOVD: 3599 opcode = op_MVGHI 3600 case AMOVW, AMOVWZ: 3601 opcode = op_MVHI 3602 case AMOVH, AMOVHZ: 3603 opcode = op_MVHHI 3604 case AMOVB, AMOVBZ: 3605 opcode = op_MVI 3606 } 3607 if d < 0 || d >= DISP12 { 3608 if r == int16(regtmp(p)) { 3609 c.ctxt.Diag("displacement must be in range [0, 4096) to use %v", r) 3610 } 3611 if d >= -DISP20/2 && d < DISP20/2 { 3612 if opcode == op_MVI { 3613 opcode = op_MVIY 3614 } else { 3615 zRXY(op_LAY, uint32(regtmp(p)), 0, uint32(r), uint32(d), asm) 3616 r = int16(regtmp(p)) 3617 d = 0 3618 } 3619 } else { 3620 zRIL(_a, op_LGFI, regtmp(p), uint32(d), asm) 3621 zRX(op_LA, regtmp(p), regtmp(p), uint32(r), 0, asm) 3622 r = int16(regtmp(p)) 3623 d = 0 3624 } 3625 } 3626 switch opcode { 3627 case op_MVI: 3628 zSI(opcode, uint32(v), uint32(r), uint32(d), asm) 3629 case op_MVIY: 3630 zSIY(opcode, uint32(v), uint32(r), uint32(d), asm) 3631 default: 3632 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm) 3633 } 3634 3635 case 73: //Illegal opcode with SIGTRAP Exception 3636 zE(op_BRRK, asm) 3637 3638 case 74: // mov reg addr (including relocation) 3639 i2 := c.regoff(&p.To) 3640 switch p.As { 3641 case AMOVD: 3642 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm) 3643 case AMOVW, AMOVWZ: // The zero extension doesn't affect store instructions 3644 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm) 3645 case AMOVH, AMOVHZ: // The zero extension doesn't affect store instructions 3646 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm) 3647 case AMOVB, AMOVBZ: // The zero extension doesn't affect store instructions 3648 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3649 adj := uint32(0) // adjustment needed for odd addresses 3650 if i2&1 != 0 { 3651 i2 -= 1 3652 adj = 1 3653 } 3654 zRX(op_STC, uint32(p.From.Reg), 0, regtmp(p), adj, asm) 3655 case AFMOVD: 3656 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3657 zRX(op_STD, uint32(p.From.Reg), 0, regtmp(p), 0, asm) 3658 case AFMOVS: 3659 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3660 zRX(op_STE, uint32(p.From.Reg), 0, regtmp(p), 0, asm) 3661 } 3662 c.addrilreloc(p.To.Sym, int64(i2)) 3663 3664 case 75: // mov addr reg (including relocation) 3665 i2 := c.regoff(&p.From) 3666 switch p.As { 3667 case AMOVD: 3668 if i2&1 != 0 { 3669 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3670 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 1, asm) 3671 i2 -= 1 3672 } else { 3673 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3674 } 3675 case AMOVW: 3676 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm) 3677 case AMOVWZ: 3678 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm) 3679 case AMOVH: 3680 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm) 3681 case AMOVHZ: 3682 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm) 3683 case AMOVB, AMOVBZ: 3684 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3685 adj := uint32(0) // adjustment needed for odd addresses 3686 if i2&1 != 0 { 3687 i2 -= 1 3688 adj = 1 3689 } 3690 switch p.As { 3691 case AMOVB: 3692 zRXY(op_LGB, uint32(p.To.Reg), 0, regtmp(p), adj, asm) 3693 case AMOVBZ: 3694 zRXY(op_LLGC, uint32(p.To.Reg), 0, regtmp(p), adj, asm) 3695 } 3696 case AFMOVD: 3697 zRIL(_a, op_LARL, regtmp(p), 0, asm) 3698 zRX(op_LD, uint32(p.To.Reg), 0, regtmp(p), 0, asm) 3699 case AFMOVS: 3700 zRIL(_a, op_LARL, regtmp(p), 0, asm) 3701 zRX(op_LE, uint32(p.To.Reg), 0, regtmp(p), 0, asm) 3702 } 3703 c.addrilreloc(p.From.Sym, int64(i2)) 3704 3705 case 76: // set program mask 3706 zRR(op_SPM, uint32(p.From.Reg), 0, asm) 3707 3708 case 77: // syscall $constant 3709 if p.From.Offset > 255 || p.From.Offset < 1 { 3710 c.ctxt.Diag("illegal system call; system call number out of range: %v", p) 3711 zE(op_TRAP2, asm) // trap always 3712 } else { 3713 zI(op_SVC, uint32(p.From.Offset), asm) 3714 } 3715 3716 case 78: // undef 3717 // "An instruction consisting entirely of binary 0s is guaranteed 3718 // always to be an illegal instruction." 3719 *asm = append(*asm, 0, 0, 0, 0) 3720 3721 case 79: // compare and swap reg reg reg 3722 v := c.regoff(&p.To) 3723 if v < 0 { 3724 v = 0 3725 } 3726 if p.As == ACS { 3727 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3728 } else if p.As == ACSG { 3729 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3730 } 3731 3732 case 80: // sync 3733 zRR(op_BCR, 14, 0, asm) // fast-BCR-serialization 3734 3735 case 81: // float to fixed and fixed to float moves (no conversion) 3736 switch p.As { 3737 case ALDGR: 3738 zRRE(op_LDGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3739 case ALGDR: 3740 zRRE(op_LGDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3741 } 3742 3743 case 82: // fixed to float conversion 3744 var opcode uint32 3745 switch p.As { 3746 default: 3747 log.Fatalf("unexpected opcode %v", p.As) 3748 case ACEFBRA: 3749 opcode = op_CEFBRA 3750 case ACDFBRA: 3751 opcode = op_CDFBRA 3752 case ACEGBRA: 3753 opcode = op_CEGBRA 3754 case ACDGBRA: 3755 opcode = op_CDGBRA 3756 case ACELFBR: 3757 opcode = op_CELFBR 3758 case ACDLFBR: 3759 opcode = op_CDLFBR 3760 case ACELGBR: 3761 opcode = op_CELGBR 3762 case ACDLGBR: 3763 opcode = op_CDLGBR 3764 } 3765 // set immediate operand M3 to 0 to use the default BFP rounding mode 3766 // (usually round to nearest, ties to even) 3767 // TODO(mundaym): should this be fixed at round to nearest, ties to even? 3768 // M4 is reserved and must be 0 3769 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3770 3771 case 83: // float to fixed conversion 3772 var opcode uint32 3773 switch p.As { 3774 default: 3775 log.Fatalf("unexpected opcode %v", p.As) 3776 case ACFEBRA: 3777 opcode = op_CFEBRA 3778 case ACFDBRA: 3779 opcode = op_CFDBRA 3780 case ACGEBRA: 3781 opcode = op_CGEBRA 3782 case ACGDBRA: 3783 opcode = op_CGDBRA 3784 case ACLFEBR: 3785 opcode = op_CLFEBR 3786 case ACLFDBR: 3787 opcode = op_CLFDBR 3788 case ACLGEBR: 3789 opcode = op_CLGEBR 3790 case ACLGDBR: 3791 opcode = op_CLGDBR 3792 } 3793 // set immediate operand M3 to 5 for rounding toward zero (required by Go spec) 3794 // M4 is reserved and must be 0 3795 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3796 3797 case 84: // storage-and-storage operations $length mem mem 3798 l := c.regoff(&p.From) 3799 if l < 1 || l > 256 { 3800 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l) 3801 } 3802 if p.GetFrom3().Index != 0 || p.To.Index != 0 { 3803 c.ctxt.Diag("cannot use index reg") 3804 } 3805 b1 := p.To.Reg 3806 b2 := p.GetFrom3().Reg 3807 if b1 == 0 { 3808 b1 = REGSP 3809 } 3810 if b2 == 0 { 3811 b2 = REGSP 3812 } 3813 d1 := c.regoff(&p.To) 3814 d2 := c.regoff(p.GetFrom3()) 3815 if d1 < 0 || d1 >= DISP12 { 3816 if b2 == int16(regtmp(p)) { 3817 c.ctxt.Diag("regtmp(p) conflict") 3818 } 3819 if b1 != int16(regtmp(p)) { 3820 zRRE(op_LGR, regtmp(p), uint32(b1), asm) 3821 } 3822 zRIL(_a, op_AGFI, regtmp(p), uint32(d1), asm) 3823 if d1 == d2 && b1 == b2 { 3824 d2 = 0 3825 b2 = int16(regtmp(p)) 3826 } 3827 d1 = 0 3828 b1 = int16(regtmp(p)) 3829 } 3830 if d2 < 0 || d2 >= DISP12 { 3831 if b1 == REGTMP2 { 3832 c.ctxt.Diag("REGTMP2 conflict") 3833 } 3834 if b2 != REGTMP2 { 3835 zRRE(op_LGR, REGTMP2, uint32(b2), asm) 3836 } 3837 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm) 3838 d2 = 0 3839 b2 = REGTMP2 3840 } 3841 var opcode uint32 3842 switch p.As { 3843 default: 3844 c.ctxt.Diag("unexpected opcode %v", p.As) 3845 case AMVC: 3846 opcode = op_MVC 3847 case AMVCIN: 3848 opcode = op_MVCIN 3849 case ACLC: 3850 opcode = op_CLC 3851 // swap operand order for CLC so that it matches CMP 3852 b1, b2 = b2, b1 3853 d1, d2 = d2, d1 3854 case AXC: 3855 opcode = op_XC 3856 case AOC: 3857 opcode = op_OC 3858 case ANC: 3859 opcode = op_NC 3860 } 3861 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm) 3862 3863 case 85: // load address relative long 3864 v := c.regoff(&p.From) 3865 if p.From.Sym == nil { 3866 if (v & 1) != 0 { 3867 c.ctxt.Diag("cannot use LARL with odd offset: %v", v) 3868 } 3869 } else { 3870 c.addrilreloc(p.From.Sym, int64(v)) 3871 v = 0 3872 } 3873 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm) 3874 3875 case 86: // load address 3876 d := c.vregoff(&p.From) 3877 x := p.From.Index 3878 b := p.From.Reg 3879 if b == 0 { 3880 b = REGSP 3881 } 3882 switch p.As { 3883 case ALA: 3884 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3885 case ALAY: 3886 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3887 } 3888 3889 case 87: // execute relative long 3890 v := c.vregoff(&p.From) 3891 if p.From.Sym == nil { 3892 if v&1 != 0 { 3893 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v) 3894 } 3895 } else { 3896 c.addrilreloc(p.From.Sym, v) 3897 v = 0 3898 } 3899 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm) 3900 3901 case 88: // store clock 3902 var opcode uint32 3903 switch p.As { 3904 case ASTCK: 3905 opcode = op_STCK 3906 case ASTCKC: 3907 opcode = op_STCKC 3908 case ASTCKE: 3909 opcode = op_STCKE 3910 case ASTCKF: 3911 opcode = op_STCKF 3912 } 3913 v := c.vregoff(&p.To) 3914 r := p.To.Reg 3915 if r == 0 { 3916 r = REGSP 3917 } 3918 zS(opcode, uint32(r), uint32(v), asm) 3919 3920 case 89: // compare and branch reg reg 3921 var v int32 3922 if p.To.Target() != nil { 3923 v = int32((p.To.Target().Pc - p.Pc) >> 1) 3924 } 3925 3926 // Some instructions take a mask as the first argument. 3927 r1, r2 := p.From.Reg, p.Reg 3928 if p.From.Type == obj.TYPE_CONST { 3929 r1, r2 = p.Reg, p.RestArgs[0].Reg 3930 } 3931 m3 := uint32(c.branchMask(p)) 3932 3933 var opcode uint32 3934 switch p.As { 3935 case ACRJ: 3936 // COMPARE AND BRANCH RELATIVE (32) 3937 opcode = op_CRJ 3938 case ACGRJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3939 // COMPARE AND BRANCH RELATIVE (64) 3940 opcode = op_CGRJ 3941 case ACLRJ: 3942 // COMPARE LOGICAL AND BRANCH RELATIVE (32) 3943 opcode = op_CLRJ 3944 case ACLGRJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3945 // COMPARE LOGICAL AND BRANCH RELATIVE (64) 3946 opcode = op_CLGRJ 3947 } 3948 3949 if int32(int16(v)) != v { 3950 // The branch is too far for one instruction so crack 3951 // `CMPBEQ x, y, target` into: 3952 // 3953 // CMPBNE x, y, 2(PC) 3954 // BR target 3955 // 3956 // Note that the instruction sequence MUST NOT clobber 3957 // the condition code. 3958 m3 ^= 0xe // invert 3-bit mask 3959 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(sizeRIE+sizeRIL)/2, 0, 0, m3, 0, asm) 3960 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm) 3961 } else { 3962 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(v), 0, 0, m3, 0, asm) 3963 } 3964 3965 case 90: // compare and branch reg $constant 3966 var v int32 3967 if p.To.Target() != nil { 3968 v = int32((p.To.Target().Pc - p.Pc) >> 1) 3969 } 3970 3971 // Some instructions take a mask as the first argument. 3972 r1, i2 := p.From.Reg, p.RestArgs[0].Offset 3973 if p.From.Type == obj.TYPE_CONST { 3974 r1 = p.Reg 3975 } 3976 m3 := uint32(c.branchMask(p)) 3977 3978 var opcode uint32 3979 switch p.As { 3980 case ACIJ: 3981 opcode = op_CIJ 3982 case ACGIJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3983 opcode = op_CGIJ 3984 case ACLIJ: 3985 opcode = op_CLIJ 3986 case ACLGIJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3987 opcode = op_CLGIJ 3988 } 3989 if int32(int16(v)) != v { 3990 // The branch is too far for one instruction so crack 3991 // `CMPBEQ x, $0, target` into: 3992 // 3993 // CMPBNE x, $0, 2(PC) 3994 // BR target 3995 // 3996 // Note that the instruction sequence MUST NOT clobber 3997 // the condition code. 3998 m3 ^= 0xe // invert 3-bit mask 3999 zRIE(_c, opcode, uint32(r1), m3, uint32(sizeRIE+sizeRIL)/2, 0, 0, 0, uint32(i2), asm) 4000 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm) 4001 } else { 4002 zRIE(_c, opcode, uint32(r1), m3, uint32(v), 0, 0, 0, uint32(i2), asm) 4003 } 4004 4005 case 91: // test under mask (immediate) 4006 var opcode uint32 4007 switch p.As { 4008 case ATMHH: 4009 opcode = op_TMHH 4010 case ATMHL: 4011 opcode = op_TMHL 4012 case ATMLH: 4013 opcode = op_TMLH 4014 case ATMLL: 4015 opcode = op_TMLL 4016 } 4017 zRI(opcode, uint32(p.From.Reg), uint32(c.vregoff(&p.To)), asm) 4018 4019 case 92: // insert program mask 4020 zRRE(op_IPM, uint32(p.From.Reg), 0, asm) 4021 4022 case 93: // GOT lookup 4023 v := c.vregoff(&p.To) 4024 if v != 0 { 4025 c.ctxt.Diag("invalid offset against GOT slot %v", p) 4026 } 4027 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 4028 rel := obj.Addrel(c.cursym) 4029 rel.Off = int32(c.pc + 2) 4030 rel.Siz = 4 4031 rel.Sym = p.From.Sym 4032 rel.Type = objabi.R_GOTPCREL 4033 rel.Add = 2 + int64(rel.Siz) 4034 4035 case 94: // TLS local exec model 4036 zRIL(_b, op_LARL, regtmp(p), (sizeRIL+sizeRXY+sizeRI)>>1, asm) 4037 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 0, asm) 4038 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm) 4039 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0) 4040 rel := obj.Addrel(c.cursym) 4041 rel.Off = int32(c.pc + sizeRIL + sizeRXY + sizeRI) 4042 rel.Siz = 8 4043 rel.Sym = p.From.Sym 4044 rel.Type = objabi.R_TLS_LE 4045 rel.Add = 0 4046 4047 case 95: // TLS initial exec model 4048 // Assembly | Relocation symbol | Done Here? 4049 // -------------------------------------------------------------- 4050 // ear %r11, %a0 | | 4051 // sllg %r11, %r11, 32 | | 4052 // ear %r11, %a1 | | 4053 // larl %r10, <var>@indntpoff | R_390_TLS_IEENT | Y 4054 // lg %r10, 0(%r10) | R_390_TLS_LOAD (tag) | Y 4055 // la %r10, 0(%r10, %r11) | | 4056 // -------------------------------------------------------------- 4057 4058 // R_390_TLS_IEENT 4059 zRIL(_b, op_LARL, regtmp(p), 0, asm) 4060 ieent := obj.Addrel(c.cursym) 4061 ieent.Off = int32(c.pc + 2) 4062 ieent.Siz = 4 4063 ieent.Sym = p.From.Sym 4064 ieent.Type = objabi.R_TLS_IE 4065 ieent.Add = 2 + int64(ieent.Siz) 4066 4067 // R_390_TLS_LOAD 4068 zRXY(op_LGF, uint32(p.To.Reg), regtmp(p), 0, 0, asm) 4069 // TODO(mundaym): add R_390_TLS_LOAD relocation here 4070 // not strictly required but might allow the linker to optimize 4071 4072 case 96: // clear macro 4073 length := c.vregoff(&p.From) 4074 offset := c.vregoff(&p.To) 4075 reg := p.To.Reg 4076 if reg == 0 { 4077 reg = REGSP 4078 } 4079 if length <= 0 { 4080 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length) 4081 } 4082 for length > 0 { 4083 if offset < 0 || offset >= DISP12 { 4084 if offset >= -DISP20/2 && offset < DISP20/2 { 4085 zRXY(op_LAY, regtmp(p), uint32(reg), 0, uint32(offset), asm) 4086 } else { 4087 if reg != int16(regtmp(p)) { 4088 zRRE(op_LGR, regtmp(p), uint32(reg), asm) 4089 } 4090 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm) 4091 } 4092 reg = int16(regtmp(p)) 4093 offset = 0 4094 } 4095 size := length 4096 if size > 256 { 4097 size = 256 4098 } 4099 4100 switch size { 4101 case 1: 4102 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm) 4103 case 2: 4104 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm) 4105 case 4: 4106 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm) 4107 case 8: 4108 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm) 4109 default: 4110 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm) 4111 } 4112 4113 length -= size 4114 offset += size 4115 } 4116 4117 case 97: // store multiple 4118 rstart := p.From.Reg 4119 rend := p.Reg 4120 offset := c.regoff(&p.To) 4121 reg := p.To.Reg 4122 if reg == 0 { 4123 reg = REGSP 4124 } 4125 if offset < -DISP20/2 || offset >= DISP20/2 { 4126 if reg != int16(regtmp(p)) { 4127 zRRE(op_LGR, regtmp(p), uint32(reg), asm) 4128 } 4129 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm) 4130 reg = int16(regtmp(p)) 4131 offset = 0 4132 } 4133 switch p.As { 4134 case ASTMY: 4135 if offset >= 0 && offset < DISP12 { 4136 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4137 } else { 4138 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4139 } 4140 case ASTMG: 4141 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4142 } 4143 4144 case 98: // load multiple 4145 rstart := p.Reg 4146 rend := p.To.Reg 4147 offset := c.regoff(&p.From) 4148 reg := p.From.Reg 4149 if reg == 0 { 4150 reg = REGSP 4151 } 4152 if offset < -DISP20/2 || offset >= DISP20/2 { 4153 if reg != int16(regtmp(p)) { 4154 zRRE(op_LGR, regtmp(p), uint32(reg), asm) 4155 } 4156 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm) 4157 reg = int16(regtmp(p)) 4158 offset = 0 4159 } 4160 switch p.As { 4161 case ALMY: 4162 if offset >= 0 && offset < DISP12 { 4163 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4164 } else { 4165 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4166 } 4167 case ALMG: 4168 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4169 } 4170 4171 case 99: // interlocked load and op 4172 if p.To.Index != 0 { 4173 c.ctxt.Diag("cannot use indexed address") 4174 } 4175 offset := c.regoff(&p.To) 4176 if offset < -DISP20/2 || offset >= DISP20/2 { 4177 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset) 4178 } 4179 var opcode uint32 4180 switch p.As { 4181 case ALAA: 4182 opcode = op_LAA 4183 case ALAAG: 4184 opcode = op_LAAG 4185 case ALAAL: 4186 opcode = op_LAAL 4187 case ALAALG: 4188 opcode = op_LAALG 4189 case ALAN: 4190 opcode = op_LAN 4191 case ALANG: 4192 opcode = op_LANG 4193 case ALAX: 4194 opcode = op_LAX 4195 case ALAXG: 4196 opcode = op_LAXG 4197 case ALAO: 4198 opcode = op_LAO 4199 case ALAOG: 4200 opcode = op_LAOG 4201 } 4202 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm) 4203 4204 case 100: // VRX STORE 4205 op, m3, _ := vop(p.As) 4206 v1 := p.From.Reg 4207 if p.Reg != 0 { 4208 m3 = uint32(c.vregoff(&p.From)) 4209 v1 = p.Reg 4210 } 4211 b2 := p.To.Reg 4212 if b2 == 0 { 4213 b2 = REGSP 4214 } 4215 d2 := uint32(c.vregoff(&p.To)) 4216 zVRX(op, uint32(v1), uint32(p.To.Index), uint32(b2), d2, m3, asm) 4217 4218 case 101: // VRX LOAD 4219 op, m3, _ := vop(p.As) 4220 src := &p.From 4221 if p.GetFrom3() != nil { 4222 m3 = uint32(c.vregoff(&p.From)) 4223 src = p.GetFrom3() 4224 } 4225 b2 := src.Reg 4226 if b2 == 0 { 4227 b2 = REGSP 4228 } 4229 d2 := uint32(c.vregoff(src)) 4230 zVRX(op, uint32(p.To.Reg), uint32(src.Index), uint32(b2), d2, m3, asm) 4231 4232 case 102: // VRV SCATTER 4233 op, _, _ := vop(p.As) 4234 m3 := uint32(c.vregoff(&p.From)) 4235 b2 := p.To.Reg 4236 if b2 == 0 { 4237 b2 = REGSP 4238 } 4239 d2 := uint32(c.vregoff(&p.To)) 4240 zVRV(op, uint32(p.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 4241 4242 case 103: // VRV GATHER 4243 op, _, _ := vop(p.As) 4244 m3 := uint32(c.vregoff(&p.From)) 4245 b2 := p.GetFrom3().Reg 4246 if b2 == 0 { 4247 b2 = REGSP 4248 } 4249 d2 := uint32(c.vregoff(p.GetFrom3())) 4250 zVRV(op, uint32(p.To.Reg), uint32(p.GetFrom3().Index), uint32(b2), d2, m3, asm) 4251 4252 case 104: // VRS SHIFT/ROTATE and LOAD GR FROM VR ELEMENT 4253 op, m4, _ := vop(p.As) 4254 fr := p.Reg 4255 if fr == 0 { 4256 fr = p.To.Reg 4257 } 4258 bits := uint32(c.vregoff(&p.From)) 4259 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm) 4260 4261 case 105: // VRS STORE MULTIPLE 4262 op, _, _ := vop(p.As) 4263 offset := uint32(c.vregoff(&p.To)) 4264 reg := p.To.Reg 4265 if reg == 0 { 4266 reg = REGSP 4267 } 4268 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm) 4269 4270 case 106: // VRS LOAD MULTIPLE 4271 op, _, _ := vop(p.As) 4272 offset := uint32(c.vregoff(&p.From)) 4273 reg := p.From.Reg 4274 if reg == 0 { 4275 reg = REGSP 4276 } 4277 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm) 4278 4279 case 107: // VRS STORE WITH LENGTH 4280 op, _, _ := vop(p.As) 4281 offset := uint32(c.vregoff(&p.To)) 4282 reg := p.To.Reg 4283 if reg == 0 { 4284 reg = REGSP 4285 } 4286 zVRS(op, uint32(p.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 4287 4288 case 108: // VRS LOAD WITH LENGTH 4289 op, _, _ := vop(p.As) 4290 offset := uint32(c.vregoff(p.GetFrom3())) 4291 reg := p.GetFrom3().Reg 4292 if reg == 0 { 4293 reg = REGSP 4294 } 4295 zVRS(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 4296 4297 case 109: // VRI-a 4298 op, m3, _ := vop(p.As) 4299 i2 := uint32(c.vregoff(&p.From)) 4300 if p.GetFrom3() != nil { 4301 m3 = uint32(c.vregoff(&p.From)) 4302 i2 = uint32(c.vregoff(p.GetFrom3())) 4303 } 4304 switch p.As { 4305 case AVZERO: 4306 i2 = 0 4307 case AVONE: 4308 i2 = 0xffff 4309 } 4310 zVRIa(op, uint32(p.To.Reg), i2, m3, asm) 4311 4312 case 110: 4313 op, m4, _ := vop(p.As) 4314 i2 := uint32(c.vregoff(&p.From)) 4315 i3 := uint32(c.vregoff(p.GetFrom3())) 4316 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm) 4317 4318 case 111: 4319 op, m4, _ := vop(p.As) 4320 i2 := uint32(c.vregoff(&p.From)) 4321 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm) 4322 4323 case 112: 4324 op, m5, _ := vop(p.As) 4325 i4 := uint32(c.vregoff(&p.From)) 4326 zVRId(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), i4, m5, asm) 4327 4328 case 113: 4329 op, m4, _ := vop(p.As) 4330 m5 := singleElementMask(p.As) 4331 i3 := uint32(c.vregoff(&p.From)) 4332 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm) 4333 4334 case 114: // VRR-a 4335 op, m3, m5 := vop(p.As) 4336 m4 := singleElementMask(p.As) 4337 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm) 4338 4339 case 115: // VRR-a COMPARE 4340 op, m3, m5 := vop(p.As) 4341 m4 := singleElementMask(p.As) 4342 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm) 4343 4344 case 117: // VRR-b 4345 op, m4, m5 := vop(p.As) 4346 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm) 4347 4348 case 118: // VRR-c 4349 op, m4, m6 := vop(p.As) 4350 m5 := singleElementMask(p.As) 4351 v3 := p.Reg 4352 if v3 == 0 { 4353 v3 = p.To.Reg 4354 } 4355 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm) 4356 4357 case 119: // VRR-c SHIFT/ROTATE/DIVIDE/SUB (rhs value on the left, like SLD, DIV etc.) 4358 op, m4, m6 := vop(p.As) 4359 m5 := singleElementMask(p.As) 4360 v2 := p.Reg 4361 if v2 == 0 { 4362 v2 = p.To.Reg 4363 } 4364 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm) 4365 4366 case 120: // VRR-d 4367 op, m6, _ := vop(p.As) 4368 m5 := singleElementMask(p.As) 4369 v1 := uint32(p.To.Reg) 4370 v2 := uint32(p.From.Reg) 4371 v3 := uint32(p.Reg) 4372 v4 := uint32(p.GetFrom3().Reg) 4373 zVRRd(op, v1, v2, v3, m6, m5, v4, asm) 4374 4375 case 121: // VRR-e 4376 op, m6, _ := vop(p.As) 4377 m5 := singleElementMask(p.As) 4378 v1 := uint32(p.To.Reg) 4379 v2 := uint32(p.From.Reg) 4380 v3 := uint32(p.Reg) 4381 v4 := uint32(p.GetFrom3().Reg) 4382 zVRRe(op, v1, v2, v3, m6, m5, v4, asm) 4383 4384 case 122: // VRR-f LOAD VRS FROM GRS DISJOINT 4385 op, _, _ := vop(p.As) 4386 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 4387 4388 case 123: // VPDI $m4, V2, V3, V1 4389 op, _, _ := vop(p.As) 4390 m4 := c.regoff(&p.From) 4391 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), 0, 0, uint32(m4), asm) 4392 4393 case 124: 4394 var opcode uint32 4395 switch p.As { 4396 default: 4397 c.ctxt.Diag("unexpected opcode %v", p.As) 4398 case AKM, AKMC, AKLMD: 4399 if p.From.Reg == REG_R0 { 4400 c.ctxt.Diag("input must not be R0 in %v", p) 4401 } 4402 if p.From.Reg&1 != 0 { 4403 c.ctxt.Diag("input must be even register in %v", p) 4404 } 4405 if p.To.Reg == REG_R0 { 4406 c.ctxt.Diag("second argument must not be R0 in %v", p) 4407 } 4408 if p.To.Reg&1 != 0 { 4409 c.ctxt.Diag("second argument must be even register in %v", p) 4410 } 4411 if p.As == AKM { 4412 opcode = op_KM 4413 } else if p.As == AKMC { 4414 opcode = op_KMC 4415 } else { 4416 opcode = op_KLMD 4417 } 4418 case AKIMD: 4419 if p.To.Reg == REG_R0 { 4420 c.ctxt.Diag("second argument must not be R0 in %v", p) 4421 } 4422 if p.To.Reg&1 != 0 { 4423 c.ctxt.Diag("second argument must be even register in %v", p) 4424 } 4425 opcode = op_KIMD 4426 } 4427 zRRE(opcode, uint32(p.From.Reg), uint32(p.To.Reg), asm) 4428 4429 case 125: // KDSA sign and verify 4430 if p.To.Reg == REG_R0 { 4431 c.ctxt.Diag("second argument must not be R0 in %v", p) 4432 } 4433 if p.To.Reg&1 != 0 { 4434 c.ctxt.Diag("second argument must be an even register in %v", p) 4435 } 4436 zRRE(op_KDSA, uint32(p.From.Reg), uint32(p.To.Reg), asm) 4437 4438 case 126: // KMA and KMCTR - CIPHER MESSAGE WITH AUTHENTICATION; CIPHER MESSAGE WITH COUNTER 4439 var opcode uint32 4440 switch p.As { 4441 default: 4442 c.ctxt.Diag("unexpected opcode %v", p.As) 4443 case AKMA, AKMCTR: 4444 if p.From.Reg == REG_R0 { 4445 c.ctxt.Diag("input argument must not be R0 in %v", p) 4446 } 4447 if p.From.Reg&1 != 0 { 4448 c.ctxt.Diag("input argument must be even register in %v", p) 4449 } 4450 if p.To.Reg == REG_R0 { 4451 c.ctxt.Diag("output argument must not be R0 in %v", p) 4452 } 4453 if p.To.Reg&1 != 0 { 4454 c.ctxt.Diag("output argument must be an even register in %v", p) 4455 } 4456 if p.Reg == REG_R0 { 4457 c.ctxt.Diag("third argument must not be R0 in %v", p) 4458 } 4459 if p.Reg&1 != 0 { 4460 c.ctxt.Diag("third argument must be even register in %v", p) 4461 } 4462 if p.As == AKMA { 4463 opcode = op_KMA 4464 } else if p.As == AKMCTR { 4465 opcode = op_KMCTR 4466 } 4467 } 4468 zRRF(opcode, uint32(p.Reg), 0, uint32(p.From.Reg), uint32(p.To.Reg), asm) 4469 } 4470 } 4471 4472 func (c *ctxtz) vregoff(a *obj.Addr) int64 { 4473 c.instoffset = 0 4474 if a != nil { 4475 c.aclass(a) 4476 } 4477 return c.instoffset 4478 } 4479 4480 func (c *ctxtz) regoff(a *obj.Addr) int32 { 4481 return int32(c.vregoff(a)) 4482 } 4483 4484 // find if the displacement is within 12 bit. 4485 func isU12(displacement int32) bool { 4486 return displacement >= 0 && displacement < DISP12 4487 } 4488 4489 // zopload12 returns the RX op with 12 bit displacement for the given load. 4490 func (c *ctxtz) zopload12(a obj.As) (uint32, bool) { 4491 switch a { 4492 case AFMOVD: 4493 return op_LD, true 4494 case AFMOVS: 4495 return op_LE, true 4496 } 4497 return 0, false 4498 } 4499 4500 // zopload returns the RXY op for the given load. 4501 func (c *ctxtz) zopload(a obj.As) uint32 { 4502 switch a { 4503 // fixed point load 4504 case AMOVD: 4505 return op_LG 4506 case AMOVW: 4507 return op_LGF 4508 case AMOVWZ: 4509 return op_LLGF 4510 case AMOVH: 4511 return op_LGH 4512 case AMOVHZ: 4513 return op_LLGH 4514 case AMOVB: 4515 return op_LGB 4516 case AMOVBZ: 4517 return op_LLGC 4518 4519 // floating point load 4520 case AFMOVD: 4521 return op_LDY 4522 case AFMOVS: 4523 return op_LEY 4524 4525 // byte reversed load 4526 case AMOVDBR: 4527 return op_LRVG 4528 case AMOVWBR: 4529 return op_LRV 4530 case AMOVHBR: 4531 return op_LRVH 4532 } 4533 4534 c.ctxt.Diag("unknown store opcode %v", a) 4535 return 0 4536 } 4537 4538 // zopstore12 returns the RX op with 12 bit displacement for the given store. 4539 func (c *ctxtz) zopstore12(a obj.As) (uint32, bool) { 4540 switch a { 4541 case AFMOVD: 4542 return op_STD, true 4543 case AFMOVS: 4544 return op_STE, true 4545 case AMOVW, AMOVWZ: 4546 return op_ST, true 4547 case AMOVH, AMOVHZ: 4548 return op_STH, true 4549 case AMOVB, AMOVBZ: 4550 return op_STC, true 4551 } 4552 return 0, false 4553 } 4554 4555 // zopstore returns the RXY op for the given store. 4556 func (c *ctxtz) zopstore(a obj.As) uint32 { 4557 switch a { 4558 // fixed point store 4559 case AMOVD: 4560 return op_STG 4561 case AMOVW, AMOVWZ: 4562 return op_STY 4563 case AMOVH, AMOVHZ: 4564 return op_STHY 4565 case AMOVB, AMOVBZ: 4566 return op_STCY 4567 4568 // floating point store 4569 case AFMOVD: 4570 return op_STDY 4571 case AFMOVS: 4572 return op_STEY 4573 4574 // byte reversed store 4575 case AMOVDBR: 4576 return op_STRVG 4577 case AMOVWBR: 4578 return op_STRV 4579 case AMOVHBR: 4580 return op_STRVH 4581 } 4582 4583 c.ctxt.Diag("unknown store opcode %v", a) 4584 return 0 4585 } 4586 4587 // zoprre returns the RRE op for the given a. 4588 func (c *ctxtz) zoprre(a obj.As) uint32 { 4589 switch a { 4590 case ACMP: 4591 return op_CGR 4592 case ACMPU: 4593 return op_CLGR 4594 case AFCMPO: //ordered 4595 return op_KDBR 4596 case AFCMPU: //unordered 4597 return op_CDBR 4598 case ACEBR: 4599 return op_CEBR 4600 } 4601 c.ctxt.Diag("unknown rre opcode %v", a) 4602 return 0 4603 } 4604 4605 // zoprr returns the RR op for the given a. 4606 func (c *ctxtz) zoprr(a obj.As) uint32 { 4607 switch a { 4608 case ACMPW: 4609 return op_CR 4610 case ACMPWU: 4611 return op_CLR 4612 } 4613 c.ctxt.Diag("unknown rr opcode %v", a) 4614 return 0 4615 } 4616 4617 // zopril returns the RIL op for the given a. 4618 func (c *ctxtz) zopril(a obj.As) uint32 { 4619 switch a { 4620 case ACMP: 4621 return op_CGFI 4622 case ACMPU: 4623 return op_CLGFI 4624 case ACMPW: 4625 return op_CFI 4626 case ACMPWU: 4627 return op_CLFI 4628 } 4629 c.ctxt.Diag("unknown ril opcode %v", a) 4630 return 0 4631 } 4632 4633 // z instructions sizes 4634 const ( 4635 sizeE = 2 4636 sizeI = 2 4637 sizeIE = 4 4638 sizeMII = 6 4639 sizeRI = 4 4640 sizeRI1 = 4 4641 sizeRI2 = 4 4642 sizeRI3 = 4 4643 sizeRIE = 6 4644 sizeRIE1 = 6 4645 sizeRIE2 = 6 4646 sizeRIE3 = 6 4647 sizeRIE4 = 6 4648 sizeRIE5 = 6 4649 sizeRIE6 = 6 4650 sizeRIL = 6 4651 sizeRIL1 = 6 4652 sizeRIL2 = 6 4653 sizeRIL3 = 6 4654 sizeRIS = 6 4655 sizeRR = 2 4656 sizeRRD = 4 4657 sizeRRE = 4 4658 sizeRRF = 4 4659 sizeRRF1 = 4 4660 sizeRRF2 = 4 4661 sizeRRF3 = 4 4662 sizeRRF4 = 4 4663 sizeRRF5 = 4 4664 sizeRRR = 2 4665 sizeRRS = 6 4666 sizeRS = 4 4667 sizeRS1 = 4 4668 sizeRS2 = 4 4669 sizeRSI = 4 4670 sizeRSL = 6 4671 sizeRSY = 6 4672 sizeRSY1 = 6 4673 sizeRSY2 = 6 4674 sizeRX = 4 4675 sizeRX1 = 4 4676 sizeRX2 = 4 4677 sizeRXE = 6 4678 sizeRXF = 6 4679 sizeRXY = 6 4680 sizeRXY1 = 6 4681 sizeRXY2 = 6 4682 sizeS = 4 4683 sizeSI = 4 4684 sizeSIL = 6 4685 sizeSIY = 6 4686 sizeSMI = 6 4687 sizeSS = 6 4688 sizeSS1 = 6 4689 sizeSS2 = 6 4690 sizeSS3 = 6 4691 sizeSS4 = 6 4692 sizeSS5 = 6 4693 sizeSS6 = 6 4694 sizeSSE = 6 4695 sizeSSF = 6 4696 ) 4697 4698 // instruction format variations 4699 type form int 4700 4701 const ( 4702 _a form = iota 4703 _b 4704 _c 4705 _d 4706 _e 4707 _f 4708 ) 4709 4710 func zE(op uint32, asm *[]byte) { 4711 *asm = append(*asm, uint8(op>>8), uint8(op)) 4712 } 4713 4714 func zI(op, i1 uint32, asm *[]byte) { 4715 *asm = append(*asm, uint8(op>>8), uint8(i1)) 4716 } 4717 4718 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) { 4719 *asm = append(*asm, 4720 uint8(op>>8), 4721 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F), 4722 uint8(ri2), 4723 uint8(ri3>>16), 4724 uint8(ri3>>8), 4725 uint8(ri3)) 4726 } 4727 4728 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4729 *asm = append(*asm, 4730 uint8(op>>8), 4731 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4732 uint8(i2_ri2>>8), 4733 uint8(i2_ri2)) 4734 } 4735 4736 // Expected argument values for the instruction formats. 4737 // 4738 // Format a1 a2 a3 a4 a5 a6 a7 4739 // ------------------------------------ 4740 // a r1, 0, i2, 0, 0, m3, 0 4741 // b r1, r2, ri4, 0, 0, m3, 0 4742 // c r1, m3, ri4, 0, 0, 0, i2 4743 // d r1, r3, i2, 0, 0, 0, 0 4744 // e r1, r3, ri2, 0, 0, 0, 0 4745 // f r1, r2, 0, i3, i4, 0, i5 4746 // g r1, m3, i2, 0, 0, 0, 0 4747 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) { 4748 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F)) 4749 4750 switch f { 4751 default: 4752 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2)) 4753 case _f: 4754 *asm = append(*asm, uint8(i3), uint8(i4)) 4755 } 4756 4757 switch f { 4758 case _a, _b: 4759 *asm = append(*asm, uint8(m3)<<4) 4760 default: 4761 *asm = append(*asm, uint8(i2_i5)) 4762 } 4763 4764 *asm = append(*asm, uint8(op)) 4765 } 4766 4767 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4768 if f == _a || f == _b { 4769 r1_m1 = r1_m1 - obj.RBaseS390X // this is a register base 4770 } 4771 *asm = append(*asm, 4772 uint8(op>>8), 4773 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4774 uint8(i2_ri2>>24), 4775 uint8(i2_ri2>>16), 4776 uint8(i2_ri2>>8), 4777 uint8(i2_ri2)) 4778 } 4779 4780 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) { 4781 *asm = append(*asm, 4782 uint8(op>>8), 4783 (uint8(r1)<<4)|uint8(m3&0x0F), 4784 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F), 4785 uint8(d4), 4786 uint8(i2), 4787 uint8(op)) 4788 } 4789 4790 func zRR(op, r1, r2 uint32, asm *[]byte) { 4791 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F)) 4792 } 4793 4794 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) { 4795 *asm = append(*asm, 4796 uint8(op>>8), 4797 uint8(op), 4798 uint8(r1)<<4, 4799 (uint8(r3)<<4)|uint8(r2&0x0F)) 4800 } 4801 4802 func zRRE(op, r1, r2 uint32, asm *[]byte) { 4803 *asm = append(*asm, 4804 uint8(op>>8), 4805 uint8(op), 4806 0, 4807 (uint8(r1)<<4)|uint8(r2&0x0F)) 4808 } 4809 4810 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) { 4811 *asm = append(*asm, 4812 uint8(op>>8), 4813 uint8(op), 4814 (uint8(r3_m3)<<4)|uint8(m4&0x0F), 4815 (uint8(r1)<<4)|uint8(r2&0x0F)) 4816 } 4817 4818 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) { 4819 *asm = append(*asm, 4820 uint8(op>>8), 4821 (uint8(r1)<<4)|uint8(r2&0x0F), 4822 (uint8(b4)<<4)|uint8((d4>>8)&0x0F), 4823 uint8(d4), 4824 uint8(m3)<<4, 4825 uint8(op)) 4826 } 4827 4828 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4829 *asm = append(*asm, 4830 uint8(op>>8), 4831 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4832 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4833 uint8(d2)) 4834 } 4835 4836 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) { 4837 *asm = append(*asm, 4838 uint8(op>>8), 4839 (uint8(r1)<<4)|uint8(r3&0x0F), 4840 uint8(ri2>>8), 4841 uint8(ri2)) 4842 } 4843 4844 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) { 4845 *asm = append(*asm, 4846 uint8(op>>8), 4847 uint8(l1), 4848 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4849 uint8(d2), 4850 uint8(op)) 4851 } 4852 4853 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4854 dl2 := uint16(d2) & 0x0FFF 4855 *asm = append(*asm, 4856 uint8(op>>8), 4857 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4858 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4859 uint8(dl2), 4860 uint8(d2>>12), 4861 uint8(op)) 4862 } 4863 4864 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4865 *asm = append(*asm, 4866 uint8(op>>8), 4867 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4868 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4869 uint8(d2)) 4870 } 4871 4872 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) { 4873 *asm = append(*asm, 4874 uint8(op>>8), 4875 (uint8(r1)<<4)|uint8(x2&0x0F), 4876 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4877 uint8(d2), 4878 uint8(m3)<<4, 4879 uint8(op)) 4880 } 4881 4882 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) { 4883 *asm = append(*asm, 4884 uint8(op>>8), 4885 (uint8(r3)<<4)|uint8(x2&0x0F), 4886 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4887 uint8(d2), 4888 uint8(m1)<<4, 4889 uint8(op)) 4890 } 4891 4892 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4893 dl2 := uint16(d2) & 0x0FFF 4894 *asm = append(*asm, 4895 uint8(op>>8), 4896 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4897 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4898 uint8(dl2), 4899 uint8(d2>>12), 4900 uint8(op)) 4901 } 4902 4903 func zS(op, b2, d2 uint32, asm *[]byte) { 4904 *asm = append(*asm, 4905 uint8(op>>8), 4906 uint8(op), 4907 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4908 uint8(d2)) 4909 } 4910 4911 func zSI(op, i2, b1, d1 uint32, asm *[]byte) { 4912 *asm = append(*asm, 4913 uint8(op>>8), 4914 uint8(i2), 4915 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4916 uint8(d1)) 4917 } 4918 4919 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) { 4920 *asm = append(*asm, 4921 uint8(op>>8), 4922 uint8(op), 4923 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4924 uint8(d1), 4925 uint8(i2>>8), 4926 uint8(i2)) 4927 } 4928 4929 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) { 4930 dl1 := uint16(d1) & 0x0FFF 4931 *asm = append(*asm, 4932 uint8(op>>8), 4933 uint8(i2), 4934 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F), 4935 uint8(dl1), 4936 uint8(d1>>12), 4937 uint8(op)) 4938 } 4939 4940 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) { 4941 *asm = append(*asm, 4942 uint8(op>>8), 4943 uint8(m1)<<4, 4944 (uint8(b3)<<4)|uint8((d3>>8)&0x0F), 4945 uint8(d3), 4946 uint8(ri2>>8), 4947 uint8(ri2)) 4948 } 4949 4950 // Expected argument values for the instruction formats. 4951 // 4952 // Format a1 a2 a3 a4 a5 a6 4953 // ------------------------------- 4954 // a l1, 0, b1, d1, b2, d2 4955 // b l1, l2, b1, d1, b2, d2 4956 // c l1, i3, b1, d1, b2, d2 4957 // d r1, r3, b1, d1, b2, d2 4958 // e r1, r3, b2, d2, b4, d4 4959 // f 0, l2, b1, d1, b2, d2 4960 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) { 4961 *asm = append(*asm, uint8(op>>8)) 4962 4963 switch f { 4964 case _a: 4965 *asm = append(*asm, uint8(l1_r1)) 4966 case _b, _c, _d, _e: 4967 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F)) 4968 case _f: 4969 *asm = append(*asm, uint8(l2_i3_r3)) 4970 } 4971 4972 *asm = append(*asm, 4973 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F), 4974 uint8(d1_d2), 4975 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F), 4976 uint8(d2_d4)) 4977 } 4978 4979 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) { 4980 *asm = append(*asm, 4981 uint8(op>>8), 4982 uint8(op), 4983 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4984 uint8(d1), 4985 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4986 uint8(d2)) 4987 } 4988 4989 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) { 4990 *asm = append(*asm, 4991 uint8(op>>8), 4992 (uint8(r3)<<4)|(uint8(op)&0x0F), 4993 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4994 uint8(d1), 4995 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4996 uint8(d2)) 4997 } 4998 4999 func rxb(va, vb, vc, vd uint32) uint8 { 5000 mask := uint8(0) 5001 if va >= REG_V16 && va <= REG_V31 { 5002 mask |= 0x8 5003 } 5004 if vb >= REG_V16 && vb <= REG_V31 { 5005 mask |= 0x4 5006 } 5007 if vc >= REG_V16 && vc <= REG_V31 { 5008 mask |= 0x2 5009 } 5010 if vd >= REG_V16 && vd <= REG_V31 { 5011 mask |= 0x1 5012 } 5013 return mask 5014 } 5015 5016 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) { 5017 *asm = append(*asm, 5018 uint8(op>>8), 5019 (uint8(v1)<<4)|(uint8(x2)&0xf), 5020 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 5021 uint8(d2), 5022 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 5023 uint8(op)) 5024 } 5025 5026 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) { 5027 *asm = append(*asm, 5028 uint8(op>>8), 5029 (uint8(v1)<<4)|(uint8(v2)&0xf), 5030 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 5031 uint8(d2), 5032 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 5033 uint8(op)) 5034 } 5035 5036 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) { 5037 *asm = append(*asm, 5038 uint8(op>>8), 5039 (uint8(v1)<<4)|(uint8(v3_r3)&0xf), 5040 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 5041 uint8(d2), 5042 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0), 5043 uint8(op)) 5044 } 5045 5046 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) { 5047 *asm = append(*asm, 5048 uint8(op>>8), 5049 (uint8(v1)<<4)|(uint8(v2)&0xf), 5050 0, 5051 (uint8(m5)<<4)|(uint8(m4)&0xf), 5052 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 5053 uint8(op)) 5054 } 5055 5056 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) { 5057 *asm = append(*asm, 5058 uint8(op>>8), 5059 (uint8(v1)<<4)|(uint8(v2)&0xf), 5060 uint8(v3)<<4, 5061 uint8(m5)<<4, 5062 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 5063 uint8(op)) 5064 } 5065 5066 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) { 5067 *asm = append(*asm, 5068 uint8(op>>8), 5069 (uint8(v1)<<4)|(uint8(v2)&0xf), 5070 uint8(v3)<<4, 5071 (uint8(m6)<<4)|(uint8(m5)&0xf), 5072 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 5073 uint8(op)) 5074 } 5075 5076 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) { 5077 *asm = append(*asm, 5078 uint8(op>>8), 5079 (uint8(v1)<<4)|(uint8(v2)&0xf), 5080 (uint8(v3)<<4)|(uint8(m5)&0xf), 5081 uint8(m6)<<4, 5082 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 5083 uint8(op)) 5084 } 5085 5086 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) { 5087 *asm = append(*asm, 5088 uint8(op>>8), 5089 (uint8(v1)<<4)|(uint8(v2)&0xf), 5090 (uint8(v3)<<4)|(uint8(m6)&0xf), 5091 uint8(m5), 5092 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 5093 uint8(op)) 5094 } 5095 5096 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) { 5097 *asm = append(*asm, 5098 uint8(op>>8), 5099 (uint8(v1)<<4)|(uint8(r2)&0xf), 5100 uint8(r3)<<4, 5101 0, 5102 rxb(v1, 0, 0, 0), 5103 uint8(op)) 5104 } 5105 5106 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) { 5107 *asm = append(*asm, 5108 uint8(op>>8), 5109 uint8(v1)<<4, 5110 uint8(i2>>8), 5111 uint8(i2), 5112 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 5113 uint8(op)) 5114 } 5115 5116 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) { 5117 *asm = append(*asm, 5118 uint8(op>>8), 5119 uint8(v1)<<4, 5120 uint8(i2), 5121 uint8(i3), 5122 (uint8(m4)<<4)|rxb(v1, 0, 0, 0), 5123 uint8(op)) 5124 } 5125 5126 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) { 5127 *asm = append(*asm, 5128 uint8(op>>8), 5129 (uint8(v1)<<4)|(uint8(v3)&0xf), 5130 uint8(i2>>8), 5131 uint8(i2), 5132 (uint8(m4)<<4)|rxb(v1, v3, 0, 0), 5133 uint8(op)) 5134 } 5135 5136 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) { 5137 *asm = append(*asm, 5138 uint8(op>>8), 5139 (uint8(v1)<<4)|(uint8(v2)&0xf), 5140 uint8(v3)<<4, 5141 uint8(i4), 5142 (uint8(m5)<<4)|rxb(v1, v2, v3, 0), 5143 uint8(op)) 5144 } 5145 5146 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) { 5147 *asm = append(*asm, 5148 uint8(op>>8), 5149 (uint8(v1)<<4)|(uint8(v2)&0xf), 5150 uint8(i3>>4), 5151 (uint8(i3)<<4)|(uint8(m5)&0xf), 5152 (uint8(m4)<<4)|rxb(v1, v2, 0, 0), 5153 uint8(op)) 5154 }