github.com/gogf/gkafka@v1.0.1-0.20190702070843-033a14468069/third/golang.org/x/sys/cpu/cpu.go (about)

     1  // Copyright 2018 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  // Package cpu implements processor feature detection for
     6  // various CPU architectures.
     7  package cpu
     8  
     9  // CacheLinePad is used to pad structs to avoid false sharing.
    10  type CacheLinePad struct{ _ [cacheLineSize]byte }
    11  
    12  // X86 contains the supported CPU features of the
    13  // current X86/AMD64 platform. If the current platform
    14  // is not X86/AMD64 then all feature flags are false.
    15  //
    16  // X86 is padded to avoid false sharing. Further the HasAVX
    17  // and HasAVX2 are only set if the OS supports XMM and YMM
    18  // registers in addition to the CPUID feature bit being set.
    19  var X86 struct {
    20  	_            CacheLinePad
    21  	HasAES       bool // AES hardware implementation (AES NI)
    22  	HasADX       bool // Multi-precision add-carry instruction extensions
    23  	HasAVX       bool // Advanced vector extension
    24  	HasAVX2      bool // Advanced vector extension 2
    25  	HasBMI1      bool // Bit manipulation instruction set 1
    26  	HasBMI2      bool // Bit manipulation instruction set 2
    27  	HasERMS      bool // Enhanced REP for MOVSB and STOSB
    28  	HasFMA       bool // Fused-multiply-add instructions
    29  	HasOSXSAVE   bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers.
    30  	HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM
    31  	HasPOPCNT    bool // Hamming weight instruction POPCNT.
    32  	HasSSE2      bool // Streaming SIMD extension 2 (always available on amd64)
    33  	HasSSE3      bool // Streaming SIMD extension 3
    34  	HasSSSE3     bool // Supplemental streaming SIMD extension 3
    35  	HasSSE41     bool // Streaming SIMD extension 4 and 4.1
    36  	HasSSE42     bool // Streaming SIMD extension 4 and 4.2
    37  	_            CacheLinePad
    38  }
    39  
    40  // ARM64 contains the supported CPU features of the
    41  // current ARMv8(aarch64) platform. If the current platform
    42  // is not arm64 then all feature flags are false.
    43  var ARM64 struct {
    44  	_           CacheLinePad
    45  	HasFP       bool // Floating-point instruction set (always available)
    46  	HasASIMD    bool // Advanced SIMD (always available)
    47  	HasEVTSTRM  bool // Event stream support
    48  	HasAES      bool // AES hardware implementation
    49  	HasPMULL    bool // Polynomial multiplication instruction set
    50  	HasSHA1     bool // SHA1 hardware implementation
    51  	HasSHA2     bool // SHA2 hardware implementation
    52  	HasCRC32    bool // CRC32 hardware implementation
    53  	HasATOMICS  bool // Atomic memory operation instruction set
    54  	HasFPHP     bool // Half precision floating-point instruction set
    55  	HasASIMDHP  bool // Advanced SIMD half precision instruction set
    56  	HasCPUID    bool // CPUID identification scheme registers
    57  	HasASIMDRDM bool // Rounding double multiply add/subtract instruction set
    58  	HasJSCVT    bool // Javascript conversion from floating-point to integer
    59  	HasFCMA     bool // Floating-point multiplication and addition of complex numbers
    60  	HasLRCPC    bool // Release Consistent processor consistent support
    61  	HasDCPOP    bool // Persistent memory support
    62  	HasSHA3     bool // SHA3 hardware implementation
    63  	HasSM3      bool // SM3 hardware implementation
    64  	HasSM4      bool // SM4 hardware implementation
    65  	HasASIMDDP  bool // Advanced SIMD double precision instruction set
    66  	HasSHA512   bool // SHA512 hardware implementation
    67  	HasSVE      bool // Scalable Vector Extensions
    68  	HasASIMDFHM bool // Advanced SIMD multiplication FP16 to FP32
    69  	_           CacheLinePad
    70  }
    71  
    72  // PPC64 contains the supported CPU features of the current ppc64/ppc64le platforms.
    73  // If the current platform is not ppc64/ppc64le then all feature flags are false.
    74  //
    75  // For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00,
    76  // since there are no optional categories. There are some exceptions that also
    77  // require kernel support to work (DARN, SCV), so there are feature bits for
    78  // those as well. The minimum processor requirement is POWER8 (ISA 2.07).
    79  // The struct is padded to avoid false sharing.
    80  var PPC64 struct {
    81  	_        CacheLinePad
    82  	HasDARN  bool // Hardware random number generator (requires kernel enablement)
    83  	HasSCV   bool // Syscall vectored (requires kernel enablement)
    84  	IsPOWER8 bool // ISA v2.07 (POWER8)
    85  	IsPOWER9 bool // ISA v3.00 (POWER9)
    86  	_        CacheLinePad
    87  }