github.com/google/syzkaller@v0.0.0-20240517125934-c0f1611a36d6/sys/fuchsia/fidl.txt (about)

     1  # Copyright 2018 syzkaller project authors. All rights reserved.
     2  # Use of this source code is governed by Apache 2 LICENSE that can be found in the LICENSE file.
     3  
     4  # See https://fuchsia.dev/fuchsia-src/reference/fidl/language/wire-format
     5  
     6  include <zircon/fidl.h>
     7  
     8  type fidl_call_args[REQ_MESSAGE, REQ_HANDLES, RESP_MESSAGE, RESP_HANDLES] {
     9  	wr_bytes	ptr[in, REQ_MESSAGE]
    10  	wr_handles	ptr[in, REQ_HANDLES]
    11  	rd_bytes	ptr[out, RESP_MESSAGE]
    12  	rd_handles	ptr[out, RESP_HANDLES]
    13  	wr_num_bytes	bytesize[wr_bytes, int32]
    14  	wr_num_handles	bytesize4[wr_handles, int32]
    15  	rd_num_bytes	bytesize[rd_bytes, int32]
    16  	rd_num_handles	bytesize4[rd_handles, int32]
    17  }
    18  
    19  type fidl_union_member[TAG, TYPE] {
    20  	tag	const[TAG, int32]
    21  	data	TYPE
    22  }
    23  
    24  type fidl_message_header[METHOD_ORDINAL] {
    25  	txid		const[0, int32]
    26  	flags		array[const[0, int8], 3]
    27  	magic_number	const[1, int8]
    28  	ordinal		const[METHOD_ORDINAL, int64]
    29  }
    30  
    31  fidl_string {
    32  	size	int64
    33  	data	flags[fidl_alloc_presence, int64]
    34  }
    35  
    36  fidl_vector {
    37  	size	int64
    38  	data	flags[fidl_alloc_presence, int64]
    39  }
    40  
    41  type fidl_aligned[T] {
    42  	var	T
    43  } [align[8]]
    44  
    45  type parallel_array[A, B] {
    46  	a	array[A]
    47  	b	array[B]
    48  } [packed]
    49  
    50  fidl_alloc_presence = FIDL_ALLOC_ABSENT, FIDL_ALLOC_PRESENT, FIDL_ALLOC_PRESENT, FIDL_ALLOC_PRESENT, FIDL_ALLOC_PRESENT, FIDL_ALLOC_PRESENT
    51  fidl_handle_presence = FIDL_HANDLE_ABSENT, FIDL_HANDLE_PRESENT, FIDL_HANDLE_PRESENT, FIDL_HANDLE_PRESENT, FIDL_HANDLE_PRESENT, FIDL_HANDLE_PRESENT