github.com/goproxy0/go@v0.0.0-20171111080102-49cc0c489d2c/src/cmd/internal/obj/arm64/doc.go (about)

     1  // Copyright 2017 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package arm64
     6  
     7  /*
     8  
     9  Go Assembly for ARM64 Reference Manual
    10  
    11  1. Alphabetical list of basic instructions
    12      // TODO
    13  
    14  2. Alphabetical list of float-point instructions
    15      // TODO
    16  
    17  3. Alphabetical list of SIMD instructions
    18  
    19      VADD: Add (vector).
    20        VADD	<Vm>.T, <Vn>.<T>, <Vd>.<T>
    21          <T> Is an arrangement specifier and can have the following values:
    22          8B, 16B, H4, H8, S2, S4, D2
    23  
    24      VADDP: Add Pairwise (vector)
    25        VADDP	<Vm>.<T>, <Vn>.<T>, <Vd>.<T>
    26          <T> Is an arrangement specifier and can have the following values:
    27          B8, B16, H4, H8, S2, S4, D2
    28  
    29      VADDV: Add across Vector.
    30        VADDV	<Vn>.<T>, Vd
    31          <T> Is an arrangement specifier and can have the following values:
    32          8B, 16B, H4, H8, S4
    33  
    34      VAND: Bitwise AND (vector)
    35        VAND	<Vm>.<T>, <Vn>.<T>, <Vd>.<T>
    36          <T> Is an arrangement specifier and can have the following values:
    37          B8, B16
    38  
    39      VCMEQ: Compare bitwise Equal (vector)
    40        VCMEQ	<Vm>.<T>, <Vn>.<T>, <Vd>.<T>
    41          <T> Is an arrangement specifier and can have the following values:
    42          B8, B16, H4, H8, S2, S4, D2
    43  
    44      VDUP: Duplicate vector element to vector or scalar.
    45        VDUP	<Vn>.<Ts>[index], <Vd>.<T>
    46          <T> Is an arrangement specifier and can have the following values:
    47          8B, 16B, H4, H8, S2, S4, D2
    48          <Ts> Is an element size specifier and can have the following values:
    49          B, H, S, D
    50  
    51      VEOR: Bitwise exclusive OR (vector, register)
    52        VEOR	<Vm>.<T>, <Vn>.<T>, <Vd>.<T>
    53          <T> Is an arrangement specifier and can have the following values:
    54          B8, B16
    55  
    56      VLD1: Load multiple single-element structures
    57        VLD1	(Rn), [<Vt>.<T>, <Vt2>.<T> ...]     // no offset
    58        VLD1.P	imm(Rn), [<Vt>.<T>, <Vt2>.<T> ...]  // immediate offset variant
    59        VLD1.P	(Rn)(Rm), [<Vt>.<T>, <Vt2>.<T> ...] // register offset variant
    60          <T> Is an arrangement specifier and can have the following values:
    61          B8, B16, H4, H8, S2, S4, D1, D2
    62  
    63      VMOV: move
    64        VMOV	<Vn>.<T>[index], Rd // Move vector element to general-purpose register.
    65          <T> Is a source width specifier and can have the following values:
    66          B, H, S (Wd)
    67          D (Xd)
    68  
    69        VMOV	Rn, <Vd>.<T> // Duplicate general-purpose register to vector.
    70          <T> Is an arrangement specifier and can have the following values:
    71          B8, B16, H4, H8, S2, S4 (Wn)
    72          D2 (Xn)
    73  
    74        VMOV	<Vn>.<T>, <Vd>.<T> // Move vector.
    75          <T> Is an arrangement specifier and can have the following values:
    76          B8, B16
    77  
    78        VMOV	Rn, <Vd>.<T>[index] // Move general-purpose register to a vector element.
    79          <T> Is a source width specifier and can have the following values:
    80          B, H, S (Wd)
    81          D (Xd)
    82  
    83        VMOV	<Vn>.<T>[index], Vn  // Move vector element to scalar.
    84          <T> Is an element size specifier and can have the following values:
    85          B, H, S, D
    86  
    87      VMOVI: Move Immediate (vector).
    88        VMOVI	$imm8, <Vd>.<T>
    89          <T> is an arrangement specifier and can have the following values:
    90          8B, 16B
    91  
    92      VMOVS: Load SIMD&FP Register (immediate offset). ARMv8: LDR (immediate, SIMD&FP)
    93        Store SIMD&FP register (immediate offset). ARMv8: STR (immediate, SIMD&FP)
    94        VMOVS	(Rn), Vn
    95        VMOVS.W	imm(Rn), Vn
    96        VMOVS.P	imm(Rn), Vn
    97        VMOVS	Vn, (Rn)
    98        VMOVS.W	Vn, imm(Rn)
    99        VMOVS.P	Vn, imm(Rn)
   100  
   101      VORR: Bitwise inclusive OR (vector, register)
   102        VORR	<Vm>.<T>, <Vn>.<T>, <Vd>.<T>
   103          <T> Is an arrangement specifier and can have the following values:
   104          B8, B16
   105  
   106      VREV32: Reverse elements in 32-bit words (vector).
   107        REV32 <Vn>.<T>, <Vd>.<T>
   108          <T> Is an arrangement specifier and can have the following values:
   109          B8, B16, H4, H8
   110  
   111      VST1: Store multiple single-element structures
   112        VST1	[<Vt>.<T>, <Vt2>.<T> ...], (Rn)         // no offset
   113        VST1.P	[<Vt>.<T>, <Vt2>.<T> ...], imm(Rn)      // immediate offset variant
   114        VST1.P	[<Vt>.<T>, <Vt2>.<T> ...], (Rn)(Rm)     // register offset variant
   115          <T> Is an arrangement specifier and can have the following values:
   116          B8, B16, H4, H8, S2, S4, D1, D2
   117  
   118  4. Alphabetical list of cryptographic extension instructions
   119  
   120      SHA1C, SHA1M, SHA1P: SHA1 hash update.
   121        SHA1C	<Vm>.S4, Vn, Vd
   122        SHA1M	<Vm>.S4, Vn, Vd
   123        SHA1P	<Vm>.S4, Vn, Vd
   124  
   125      SHA1H: SHA1 fixed rotate.
   126        SHA1H	Vn, Vd
   127  
   128      SHA1SU0:   SHA1 schedule update 0.
   129      SHA256SU1: SHA256 schedule update 1.
   130        SHA1SU0	<Vm>.S4, <Vn>.S4, <Vd>.S4
   131        SHA256SU1	<Vm>.S4, <Vn>.S4, <Vd>.S4
   132  
   133      SHA1SU1:   SHA1 schedule update 1.
   134      SHA256SU0: SHA256 schedule update 0.
   135        SHA1SU1	<Vn>.S4, <Vd>.S4
   136        SHA256SU0	<Vn>.S4, <Vd>.S4
   137  
   138      SHA256H, SHA256H2: SHA256 hash update.
   139        SHA256H	<Vm>.S4, Vn, Vd
   140        SHA256H2	<Vm>.S4, Vn, Vd
   141  
   142  
   143  */