github.com/goproxy0/go@v0.0.0-20171111080102-49cc0c489d2c/src/cmd/internal/obj/ppc64/asm9.go (about) 1 // cmd/9l/optab.c, cmd/9l/asmout.c from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package ppc64 31 32 import ( 33 "cmd/internal/obj" 34 "cmd/internal/objabi" 35 "encoding/binary" 36 "fmt" 37 "log" 38 "sort" 39 ) 40 41 // ctxt9 holds state while assembling a single function. 42 // Each function gets a fresh ctxt9. 43 // This allows for multiple functions to be safely concurrently assembled. 44 type ctxt9 struct { 45 ctxt *obj.Link 46 newprog obj.ProgAlloc 47 cursym *obj.LSym 48 autosize int32 49 instoffset int64 50 pc int64 51 } 52 53 // Instruction layout. 54 55 const ( 56 funcAlign = 16 57 ) 58 59 const ( 60 r0iszero = 1 61 ) 62 63 type Optab struct { 64 as obj.As // Opcode 65 a1 uint8 66 a2 uint8 67 a3 uint8 68 a4 uint8 69 type_ int8 // cases in asmout below. E.g., 44 = st r,(ra+rb); 45 = ld (ra+rb), r 70 size int8 71 param int16 72 } 73 74 var optab = []Optab{ 75 {obj.ATEXT, C_LEXT, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 76 {obj.ATEXT, C_LEXT, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 77 {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 78 {obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 79 /* move register */ 80 {AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 4, 0}, 81 {AMOVB, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 82 {AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 83 {AMOVW, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 84 {AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 85 {AADD, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 86 {AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 87 {AADD, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 88 {AADD, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 89 {AADD, C_UCON, C_REG, C_NONE, C_REG, 20, 4, 0}, 90 {AADD, C_UCON, C_NONE, C_NONE, C_REG, 20, 4, 0}, 91 {AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 92 {AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 93 {AADDC, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 94 {AADDC, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 95 {AADDC, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 96 {AADDC, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 97 {AADDC, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 98 {AADDC, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 99 {AAND, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, no literal */ 100 {AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 101 {AANDCC, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 102 {AANDCC, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 103 {AANDCC, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 104 {AANDCC, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 105 {AANDCC, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 106 {AANDCC, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 107 {AANDCC, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 108 {AANDCC, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 109 {AMULLW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 110 {AMULLW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 111 {AMULLW, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 112 {AMULLW, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 113 {AMULLW, C_ANDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 114 {AMULLW, C_ANDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 115 {AMULLW, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 116 {AMULLW, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 117 {ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, 118 {ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 119 {ASUBC, C_REG, C_NONE, C_ADDCON, C_REG, 27, 4, 0}, 120 {ASUBC, C_REG, C_NONE, C_LCON, C_REG, 28, 12, 0}, 121 {AOR, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, literal not cc (or/xor) */ 122 {AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 123 {AOR, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 124 {AOR, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 125 {AOR, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 126 {AOR, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 127 {AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 128 {AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 129 {ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, /* op r1[,r2],r3 */ 130 {ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 131 {ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, /* op r2[,r1],r3 */ 132 {ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 133 {ASLW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 134 {ASLW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 135 {ASLD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 136 {ASLD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 137 {ASLD, C_SCON, C_REG, C_NONE, C_REG, 25, 4, 0}, 138 {ASLD, C_SCON, C_NONE, C_NONE, C_REG, 25, 4, 0}, 139 {ASLW, C_SCON, C_REG, C_NONE, C_REG, 57, 4, 0}, 140 {ASLW, C_SCON, C_NONE, C_NONE, C_REG, 57, 4, 0}, 141 {ASRAW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 142 {ASRAW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 143 {ASRAW, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 144 {ASRAW, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 145 {ASRAD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 146 {ASRAD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 147 {ASRAD, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 148 {ASRAD, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 149 {ARLWMI, C_SCON, C_REG, C_LCON, C_REG, 62, 4, 0}, 150 {ARLWMI, C_REG, C_REG, C_LCON, C_REG, 63, 4, 0}, 151 {ARLDMI, C_SCON, C_REG, C_LCON, C_REG, 30, 4, 0}, 152 {ARLDC, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 153 {ARLDCL, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 154 {ARLDCL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 155 {ARLDICL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 156 {ARLDICL, C_SCON, C_REG, C_LCON, C_REG, 14, 4, 0}, 157 {ARLDCL, C_REG, C_NONE, C_LCON, C_REG, 14, 4, 0}, 158 {AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 4, 0}, 159 {AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 4, 0}, 160 {AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 161 {AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 162 {AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 163 {AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 4, 0}, 164 {AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 4, 0}, 165 {AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 4, 0}, 166 167 /* store, short offset */ 168 {AMOVD, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 169 {AMOVW, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 170 {AMOVWZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 171 {AMOVBZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 172 {AMOVBZU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 173 {AMOVB, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 174 {AMOVBU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 175 {AMOVD, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 176 {AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 177 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 178 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 179 {AMOVB, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 180 {AMOVD, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 181 {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 182 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 183 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 184 {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 185 {AMOVD, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 186 {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 187 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 188 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 189 {AMOVBZU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 190 {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 191 {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 192 193 /* load, short offset */ 194 {AMOVD, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 195 {AMOVW, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 196 {AMOVWZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 197 {AMOVBZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 198 {AMOVBZU, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 199 {AMOVB, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 200 {AMOVBU, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 201 {AMOVD, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 202 {AMOVW, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 203 {AMOVWZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 204 {AMOVBZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 205 {AMOVB, C_SEXT, C_NONE, C_NONE, C_REG, 9, 8, REGSB}, 206 {AMOVD, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 207 {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 208 {AMOVWZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 209 {AMOVBZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 210 {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, 9, 8, REGSP}, 211 {AMOVD, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 212 {AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 213 {AMOVWZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 214 {AMOVBZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 215 {AMOVBZU, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 216 {AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 217 {AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 218 219 /* store, long offset */ 220 {AMOVD, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 221 {AMOVW, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 222 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 223 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 224 {AMOVB, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 225 {AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 226 {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 227 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 228 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 229 {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 230 {AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 231 {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 232 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 233 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 234 {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 235 {AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 236 {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 237 {AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 238 {AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 239 {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 240 241 /* load, long offset */ 242 {AMOVD, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 243 {AMOVW, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 244 {AMOVWZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 245 {AMOVBZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 246 {AMOVB, C_LEXT, C_NONE, C_NONE, C_REG, 37, 12, REGSB}, 247 {AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 248 {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 249 {AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 250 {AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 251 {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 37, 12, REGSP}, 252 {AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 253 {AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 254 {AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 255 {AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 256 {AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 37, 12, REGZERO}, 257 {AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 258 {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 259 {AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 260 {AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 261 {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 76, 12, 0}, 262 263 {AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 79, 4, 0}, 264 {AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 80, 8, 0}, 265 266 {AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 81, 8, 0}, 267 268 /* load constant */ 269 {AMOVD, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, 270 {AMOVD, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 271 {AMOVD, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 272 {AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 273 {AMOVD, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 274 {AMOVW, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 275 {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 276 {AMOVW, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 277 {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 278 {AMOVW, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 279 {AMOVWZ, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 280 {AMOVWZ, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 281 {AMOVWZ, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 282 {AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 283 {AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 284 285 /* load unsigned/long constants (TO DO: check) */ 286 {AMOVD, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 287 {AMOVD, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 288 {AMOVW, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 289 {AMOVW, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 290 {AMOVWZ, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 291 {AMOVWZ, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 292 {AMOVHBR, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 293 {AMOVHBR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 294 {AMOVHBR, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 295 {AMOVHBR, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 296 {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0}, 297 {ASYSCALL, C_REG, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 298 {ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 299 {ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 300 {ABEQ, C_CREG, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 301 {ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, 302 {ABR, C_NONE, C_NONE, C_NONE, C_LBRAPIC, 11, 8, 0}, 303 {ABC, C_SCON, C_REG, C_NONE, C_SBRA, 16, 4, 0}, 304 {ABC, C_SCON, C_REG, C_NONE, C_LBRA, 17, 4, 0}, 305 {ABR, C_NONE, C_NONE, C_NONE, C_LR, 18, 4, 0}, 306 {ABR, C_NONE, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 307 {ABR, C_REG, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 308 {ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 309 {ABC, C_NONE, C_REG, C_NONE, C_LR, 18, 4, 0}, 310 {ABC, C_NONE, C_REG, C_NONE, C_CTR, 18, 4, 0}, 311 {ABC, C_SCON, C_REG, C_NONE, C_LR, 18, 4, 0}, 312 {ABC, C_SCON, C_REG, C_NONE, C_CTR, 18, 4, 0}, 313 {ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 314 {AFMOVD, C_SEXT, C_NONE, C_NONE, C_FREG, 8, 4, REGSB}, 315 {AFMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, 8, 4, REGSP}, 316 {AFMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, 8, 4, REGZERO}, 317 {AFMOVD, C_LEXT, C_NONE, C_NONE, C_FREG, 36, 8, REGSB}, 318 {AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, 8, REGSP}, 319 {AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 8, REGZERO}, 320 {AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 8, 0}, 321 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 322 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 323 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 324 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 325 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 326 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 327 {AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 328 {AFMOVSX, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 329 {AFMOVSX, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 330 {AFMOVSX, C_FREG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 331 {AFMOVSX, C_FREG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 332 {AFMOVSZ, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 333 {AFMOVSZ, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 334 {ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 335 {AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 4, 0}, 336 {ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 337 {ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 338 {AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 339 {AEXTSB, C_REG, C_NONE, C_NONE, C_REG, 48, 4, 0}, 340 {AEXTSB, C_NONE, C_NONE, C_NONE, C_REG, 48, 4, 0}, 341 {AISEL, C_LCON, C_REG, C_REG, C_REG, 84, 4, 0}, 342 {AISEL, C_ZCON, C_REG, C_REG, C_REG, 84, 4, 0}, 343 {ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 344 {ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 4, 0}, 345 {AREM, C_REG, C_NONE, C_NONE, C_REG, 50, 12, 0}, 346 {AREM, C_REG, C_REG, C_NONE, C_REG, 50, 12, 0}, 347 {AREMU, C_REG, C_NONE, C_NONE, C_REG, 50, 16, 0}, 348 {AREMU, C_REG, C_REG, C_NONE, C_REG, 50, 16, 0}, 349 {AREMD, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 350 {AREMD, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 351 {AREMDU, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 352 {AREMDU, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 353 {AMTFSB0, C_SCON, C_NONE, C_NONE, C_NONE, 52, 4, 0}, 354 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_FREG, 53, 4, 0}, 355 {AMOVFL, C_FREG, C_NONE, C_NONE, C_FPSCR, 64, 4, 0}, 356 {AMOVFL, C_FREG, C_NONE, C_LCON, C_FPSCR, 64, 4, 0}, 357 {AMOVFL, C_LCON, C_NONE, C_NONE, C_FPSCR, 65, 4, 0}, 358 {AMOVD, C_MSR, C_NONE, C_NONE, C_REG, 54, 4, 0}, /* mfmsr */ 359 {AMOVD, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsrd */ 360 {AMOVWZ, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsr */ 361 362 /* Other ISA 2.05+ instructions */ 363 {APOPCNTD, C_REG, C_NONE, C_NONE, C_REG, 93, 4, 0}, /* population count, x-form */ 364 {ACMPB, C_REG, C_REG, C_NONE, C_REG, 92, 4, 0}, /* compare byte, x-form */ 365 {ACMPEQB, C_REG, C_REG, C_NONE, C_CREG, 92, 4, 0}, /* compare equal byte, x-form */ 366 {AFTDIV, C_FREG, C_FREG, C_NONE, C_SCON, 92, 4, 0}, /* floating test for sw divide, x-form */ 367 {AFTSQRT, C_FREG, C_NONE, C_NONE, C_SCON, 93, 4, 0}, /* floating test for sw square root, x-form */ 368 {ACOPY, C_REG, C_NONE, C_NONE, C_REG, 92, 4, 0}, /* copy/paste facility, x-form */ 369 {ADARN, C_SCON, C_NONE, C_NONE, C_REG, 92, 4, 0}, /* deliver random number, x-form */ 370 {ALDMX, C_SOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, /* load doubleword monitored, x-form */ 371 {AMADDHD, C_REG, C_REG, C_REG, C_REG, 83, 4, 0}, /* multiply-add high/low doubleword, va-form */ 372 {AADDEX, C_REG, C_REG, C_SCON, C_REG, 94, 4, 0}, /* add extended using alternate carry, z23-form */ 373 374 /* Vector instructions */ 375 376 /* Vector load */ 377 {ALV, C_SOREG, C_NONE, C_NONE, C_VREG, 45, 4, 0}, /* vector load, x-form */ 378 379 /* Vector store */ 380 {ASTV, C_VREG, C_NONE, C_NONE, C_SOREG, 44, 4, 0}, /* vector store, x-form */ 381 382 /* Vector logical */ 383 {AVAND, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector and, vx-form */ 384 {AVOR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector or, vx-form */ 385 386 /* Vector add */ 387 {AVADDUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned modulo, vx-form */ 388 {AVADDCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add & write carry unsigned, vx-form */ 389 {AVADDUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned saturate, vx-form */ 390 {AVADDSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add signed saturate, vx-form */ 391 {AVADDE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector add extended, va-form */ 392 393 /* Vector subtract */ 394 {AVSUBUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned modulo, vx-form */ 395 {AVSUBCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract & write carry unsigned, vx-form */ 396 {AVSUBUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned saturate, vx-form */ 397 {AVSUBSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract signed saturate, vx-form */ 398 {AVSUBE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector subtract extended, va-form */ 399 400 /* Vector multiply */ 401 {AVPMSUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector polynomial multiply & sum, vx-form */ 402 {AVMSUMUDM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector multiply-sum, va-form */ 403 404 /* Vector rotate */ 405 {AVR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector rotate, vx-form */ 406 407 /* Vector shift */ 408 {AVS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift, vx-form */ 409 {AVSA, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift algebraic, vx-form */ 410 {AVSOI, C_ANDCON, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector shift by octet immediate, va-form */ 411 412 /* Vector count */ 413 {AVCLZ, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector count leading zeros, vx-form */ 414 {AVPOPCNT, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector population count, vx-form */ 415 416 /* Vector compare */ 417 {AVCMPEQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare equal, vc-form */ 418 {AVCMPGT, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare greater than, vc-form */ 419 {AVCMPNEZB, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare not equal, vx-form */ 420 421 /* Vector permute */ 422 {AVPERM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector permute, va-form */ 423 424 /* Vector bit permute */ 425 {AVBPERMQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector bit permute, vx-form */ 426 427 /* Vector select */ 428 {AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector select, va-form */ 429 430 /* Vector splat */ 431 {AVSPLT, C_SCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector splat, vx-form */ 432 {AVSPLT, C_ADDCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, 433 {AVSPLTI, C_SCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector splat immediate, vx-form */ 434 {AVSPLTI, C_ADDCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, 435 436 /* Vector AES */ 437 {AVCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES cipher, vx-form */ 438 {AVNCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES inverse cipher, vx-form */ 439 {AVSBOX, C_VREG, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector AES subbytes, vx-form */ 440 441 /* Vector SHA */ 442 {AVSHASIGMA, C_ANDCON, C_VREG, C_ANDCON, C_VREG, 82, 4, 0}, /* vector SHA sigma, vx-form */ 443 444 /* VSX vector load */ 445 {ALXV, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx vector load, xx1-form */ 446 447 /* VSX vector store */ 448 {ASTXV, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx vector store, xx1-form */ 449 450 /* VSX scalar load */ 451 {ALXS, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar load, xx1-form */ 452 453 /* VSX scalar store */ 454 {ASTXS, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar store, xx1-form */ 455 456 /* VSX scalar as integer load */ 457 {ALXSI, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar as integer load, xx1-form */ 458 459 /* VSX scalar store as integer */ 460 {ASTXSI, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar as integer store, xx1-form */ 461 462 /* VSX move from VSR */ 463 {AMFVSR, C_VSREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, /* vsx move from vsr, xx1-form */ 464 {AMFVSR, C_FREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 465 {AMFVSR, C_VREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 466 467 /* VSX move to VSR */ 468 {AMTVSR, C_REG, C_NONE, C_NONE, C_VSREG, 88, 4, 0}, /* vsx move to vsr, xx1-form */ 469 {AMTVSR, C_REG, C_REG, C_NONE, C_VSREG, 88, 4, 0}, 470 {AMTVSR, C_REG, C_NONE, C_NONE, C_FREG, 88, 4, 0}, 471 {AMTVSR, C_REG, C_NONE, C_NONE, C_VREG, 88, 4, 0}, 472 473 /* VSX logical */ 474 {AXXLAND, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx and, xx3-form */ 475 {AXXLOR, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx or, xx3-form */ 476 477 /* VSX select */ 478 {AXXSEL, C_VSREG, C_VSREG, C_VSREG, C_VSREG, 91, 4, 0}, /* vsx select, xx4-form */ 479 480 /* VSX merge */ 481 {AXXMRG, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx merge, xx3-form */ 482 483 /* VSX splat */ 484 {AXXSPLT, C_VSREG, C_NONE, C_SCON, C_VSREG, 89, 4, 0}, /* vsx splat, xx2-form */ 485 486 /* VSX permute */ 487 {AXXPERM, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx permute, xx3-form */ 488 489 /* VSX shift */ 490 {AXXSI, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx shift immediate, xx3-form */ 491 492 /* VSX scalar FP-FP conversion */ 493 {AXSCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-fp conversion, xx2-form */ 494 495 /* VSX vector FP-FP conversion */ 496 {AXVCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-fp conversion, xx2-form */ 497 498 /* VSX scalar FP-integer conversion */ 499 {AXSCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-integer conversion, xx2-form */ 500 501 /* VSX scalar integer-FP conversion */ 502 {AXSCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar integer-fp conversion, xx2-form */ 503 504 /* VSX vector FP-integer conversion */ 505 {AXVCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-integer conversion, xx2-form */ 506 507 /* VSX vector integer-FP conversion */ 508 {AXVCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector integer-fp conversion, xx2-form */ 509 510 /* 64-bit special registers */ 511 {AMOVD, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 512 {AMOVD, C_REG, C_NONE, C_NONE, C_LR, 66, 4, 0}, 513 {AMOVD, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 514 {AMOVD, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 515 {AMOVD, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 516 {AMOVD, C_LR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 517 {AMOVD, C_CTR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 518 {AMOVD, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 519 520 /* 32-bit special registers (gloss over sign-extension or not?) */ 521 {AMOVW, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 522 {AMOVW, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 523 {AMOVW, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 524 {AMOVW, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 525 {AMOVW, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 526 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 527 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 528 {AMOVWZ, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 529 {AMOVWZ, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 530 {AMOVWZ, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 531 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_CREG, 73, 4, 0}, 532 {AMOVFL, C_CREG, C_NONE, C_NONE, C_CREG, 67, 4, 0}, 533 {AMOVW, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 534 {AMOVWZ, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 535 {AMOVFL, C_REG, C_NONE, C_NONE, C_LCON, 69, 4, 0}, 536 {AMOVFL, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 537 {AMOVW, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 538 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 539 {ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 540 {ACMP, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 541 {ACMP, C_REG, C_NONE, C_NONE, C_ADDCON, 71, 4, 0}, 542 {ACMP, C_REG, C_REG, C_NONE, C_ADDCON, 71, 4, 0}, 543 {ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 544 {ACMPU, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 545 {ACMPU, C_REG, C_NONE, C_NONE, C_ANDCON, 71, 4, 0}, 546 {ACMPU, C_REG, C_REG, C_NONE, C_ANDCON, 71, 4, 0}, 547 {AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 4, 0}, 548 {AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 4, 0}, 549 {ATW, C_LCON, C_REG, C_NONE, C_REG, 60, 4, 0}, 550 {ATW, C_LCON, C_REG, C_NONE, C_ADDCON, 61, 4, 0}, 551 {ADCBF, C_ZOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0}, 552 {ADCBF, C_SOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0}, 553 {ADCBF, C_ZOREG, C_REG, C_NONE, C_SCON, 43, 4, 0}, 554 {ADCBF, C_SOREG, C_NONE, C_NONE, C_SCON, 43, 4, 0}, 555 {AECOWX, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 556 {AECIWX, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 557 {AECOWX, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 558 {AECIWX, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 559 {AEIEIO, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 560 {ATLBIE, C_REG, C_NONE, C_NONE, C_NONE, 49, 4, 0}, 561 {ATLBIE, C_SCON, C_NONE, C_NONE, C_REG, 49, 4, 0}, 562 {ASLBMFEE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 563 {ASLBMTE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 564 {ASTSW, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 565 {ASTSW, C_REG, C_NONE, C_LCON, C_ZOREG, 41, 4, 0}, 566 {ALSW, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 567 {ALSW, C_ZOREG, C_NONE, C_LCON, C_REG, 42, 4, 0}, 568 {obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 4, 0}, 569 {obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0, 0}, 570 {obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0, 0}, 571 {obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0}, 572 {obj.ADUFFZERO, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 573 {obj.ADUFFCOPY, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 574 575 {obj.AXXX, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0}, 576 } 577 578 var oprange [ALAST & obj.AMask][]Optab 579 580 var xcmp [C_NCLASS][C_NCLASS]bool 581 582 func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 583 p := cursym.Func.Text 584 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 585 return 586 } 587 588 if oprange[AANDN&obj.AMask] == nil { 589 ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first") 590 } 591 592 c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 593 594 pc := int64(0) 595 p.Pc = pc 596 597 var m int 598 var o *Optab 599 for p = p.Link; p != nil; p = p.Link { 600 p.Pc = pc 601 o = c.oplook(p) 602 m = int(o.size) 603 if m == 0 { 604 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA { 605 c.ctxt.Diag("zero-width instruction\n%v", p) 606 } 607 continue 608 } 609 610 pc += int64(m) 611 } 612 613 c.cursym.Size = pc 614 615 /* 616 * if any procedure is large enough to 617 * generate a large SBRA branch, then 618 * generate extra passes putting branches 619 * around jmps to fix. this is rare. 620 */ 621 bflag := 1 622 623 var otxt int64 624 var q *obj.Prog 625 for bflag != 0 { 626 bflag = 0 627 pc = 0 628 for p = c.cursym.Func.Text.Link; p != nil; p = p.Link { 629 p.Pc = pc 630 o = c.oplook(p) 631 632 // very large conditional branches 633 if (o.type_ == 16 || o.type_ == 17) && p.Pcond != nil { 634 otxt = p.Pcond.Pc - pc 635 if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 { 636 q = c.newprog() 637 q.Link = p.Link 638 p.Link = q 639 q.As = ABR 640 q.To.Type = obj.TYPE_BRANCH 641 q.Pcond = p.Pcond 642 p.Pcond = q 643 q = c.newprog() 644 q.Link = p.Link 645 p.Link = q 646 q.As = ABR 647 q.To.Type = obj.TYPE_BRANCH 648 q.Pcond = q.Link.Link 649 650 //addnop(p->link); 651 //addnop(p); 652 bflag = 1 653 } 654 } 655 656 m = int(o.size) 657 if m == 0 { 658 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA { 659 c.ctxt.Diag("zero-width instruction\n%v", p) 660 } 661 continue 662 } 663 664 pc += int64(m) 665 } 666 667 c.cursym.Size = pc 668 } 669 670 pc += -pc & (funcAlign - 1) 671 c.cursym.Size = pc 672 673 /* 674 * lay out the code, emitting code and data relocations. 675 */ 676 677 c.cursym.Grow(c.cursym.Size) 678 679 bp := c.cursym.P 680 var i int32 681 var out [6]uint32 682 for p := c.cursym.Func.Text.Link; p != nil; p = p.Link { 683 c.pc = p.Pc 684 o = c.oplook(p) 685 if int(o.size) > 4*len(out) { 686 log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p) 687 } 688 c.asmout(p, o, out[:]) 689 for i = 0; i < int32(o.size/4); i++ { 690 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i]) 691 bp = bp[4:] 692 } 693 } 694 } 695 696 func isint32(v int64) bool { 697 return int64(int32(v)) == v 698 } 699 700 func isuint32(v uint64) bool { 701 return uint64(uint32(v)) == v 702 } 703 704 func (c *ctxt9) aclass(a *obj.Addr) int { 705 switch a.Type { 706 case obj.TYPE_NONE: 707 return C_NONE 708 709 case obj.TYPE_REG: 710 if REG_R0 <= a.Reg && a.Reg <= REG_R31 { 711 return C_REG 712 } 713 if REG_F0 <= a.Reg && a.Reg <= REG_F31 { 714 return C_FREG 715 } 716 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 717 return C_VREG 718 } 719 if REG_VS0 <= a.Reg && a.Reg <= REG_VS63 { 720 return C_VSREG 721 } 722 if REG_CR0 <= a.Reg && a.Reg <= REG_CR7 || a.Reg == REG_CR { 723 return C_CREG 724 } 725 if REG_SPR0 <= a.Reg && a.Reg <= REG_SPR0+1023 { 726 switch a.Reg { 727 case REG_LR: 728 return C_LR 729 730 case REG_XER: 731 return C_XER 732 733 case REG_CTR: 734 return C_CTR 735 } 736 737 return C_SPR 738 } 739 740 if REG_DCR0 <= a.Reg && a.Reg <= REG_DCR0+1023 { 741 return C_SPR 742 } 743 if a.Reg == REG_FPSCR { 744 return C_FPSCR 745 } 746 if a.Reg == REG_MSR { 747 return C_MSR 748 } 749 return C_GOK 750 751 case obj.TYPE_MEM: 752 switch a.Name { 753 case obj.NAME_EXTERN, 754 obj.NAME_STATIC: 755 if a.Sym == nil { 756 break 757 } 758 c.instoffset = a.Offset 759 if a.Sym != nil { // use relocation 760 if a.Sym.Type == objabi.STLSBSS { 761 if c.ctxt.Flag_shared { 762 return C_TLS_IE 763 } else { 764 return C_TLS_LE 765 } 766 } 767 return C_ADDR 768 } 769 return C_LEXT 770 771 case obj.NAME_GOTREF: 772 return C_GOTADDR 773 774 case obj.NAME_AUTO: 775 c.instoffset = int64(c.autosize) + a.Offset 776 if c.instoffset >= -BIG && c.instoffset < BIG { 777 return C_SAUTO 778 } 779 return C_LAUTO 780 781 case obj.NAME_PARAM: 782 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 783 if c.instoffset >= -BIG && c.instoffset < BIG { 784 return C_SAUTO 785 } 786 return C_LAUTO 787 788 case obj.NAME_NONE: 789 c.instoffset = a.Offset 790 if c.instoffset == 0 { 791 return C_ZOREG 792 } 793 if c.instoffset >= -BIG && c.instoffset < BIG { 794 return C_SOREG 795 } 796 return C_LOREG 797 } 798 799 return C_GOK 800 801 case obj.TYPE_TEXTSIZE: 802 return C_TEXTSIZE 803 804 case obj.TYPE_CONST, 805 obj.TYPE_ADDR: 806 switch a.Name { 807 case obj.NAME_NONE: 808 c.instoffset = a.Offset 809 if a.Reg != 0 { 810 if -BIG <= c.instoffset && c.instoffset <= BIG { 811 return C_SACON 812 } 813 if isint32(c.instoffset) { 814 return C_LACON 815 } 816 return C_DACON 817 } 818 819 goto consize 820 821 case obj.NAME_EXTERN, 822 obj.NAME_STATIC: 823 s := a.Sym 824 if s == nil { 825 break 826 } 827 828 c.instoffset = a.Offset 829 830 /* not sure why this barfs */ 831 return C_LCON 832 833 case obj.NAME_AUTO: 834 c.instoffset = int64(c.autosize) + a.Offset 835 if c.instoffset >= -BIG && c.instoffset < BIG { 836 return C_SACON 837 } 838 return C_LACON 839 840 case obj.NAME_PARAM: 841 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 842 if c.instoffset >= -BIG && c.instoffset < BIG { 843 return C_SACON 844 } 845 return C_LACON 846 } 847 848 return C_GOK 849 850 consize: 851 if c.instoffset >= 0 { 852 if c.instoffset == 0 { 853 return C_ZCON 854 } 855 if c.instoffset <= 0x7fff { 856 return C_SCON 857 } 858 if c.instoffset <= 0xffff { 859 return C_ANDCON 860 } 861 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 862 return C_UCON 863 } 864 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 865 return C_LCON 866 } 867 return C_DCON 868 } 869 870 if c.instoffset >= -0x8000 { 871 return C_ADDCON 872 } 873 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 874 return C_UCON 875 } 876 if isint32(c.instoffset) { 877 return C_LCON 878 } 879 return C_DCON 880 881 case obj.TYPE_BRANCH: 882 if a.Sym != nil && c.ctxt.Flag_dynlink { 883 return C_LBRAPIC 884 } 885 return C_SBRA 886 } 887 888 return C_GOK 889 } 890 891 func prasm(p *obj.Prog) { 892 fmt.Printf("%v\n", p) 893 } 894 895 func (c *ctxt9) oplook(p *obj.Prog) *Optab { 896 a1 := int(p.Optab) 897 if a1 != 0 { 898 return &optab[a1-1] 899 } 900 a1 = int(p.From.Class) 901 if a1 == 0 { 902 a1 = c.aclass(&p.From) + 1 903 p.From.Class = int8(a1) 904 } 905 906 a1-- 907 a3 := C_NONE + 1 908 if p.GetFrom3() != nil { 909 a3 = int(p.GetFrom3().Class) 910 if a3 == 0 { 911 a3 = c.aclass(p.GetFrom3()) + 1 912 p.GetFrom3().Class = int8(a3) 913 } 914 } 915 916 a3-- 917 a4 := int(p.To.Class) 918 if a4 == 0 { 919 a4 = c.aclass(&p.To) + 1 920 p.To.Class = int8(a4) 921 } 922 923 a4-- 924 a2 := C_NONE 925 if p.Reg != 0 { 926 if REG_R0 <= p.Reg && p.Reg <= REG_R31 { 927 a2 = C_REG 928 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 929 a2 = C_VREG 930 } else if REG_VS0 <= p.Reg && p.Reg <= REG_VS63 { 931 a2 = C_VSREG 932 } else if REG_F0 <= p.Reg && p.Reg <= REG_F31 { 933 a2 = C_FREG 934 } 935 } 936 937 //print("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4); 938 ops := oprange[p.As&obj.AMask] 939 c1 := &xcmp[a1] 940 c3 := &xcmp[a3] 941 c4 := &xcmp[a4] 942 for i := range ops { 943 op := &ops[i] 944 if int(op.a2) == a2 && c1[op.a1] && c3[op.a3] && c4[op.a4] { 945 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 946 return op 947 } 948 } 949 950 c.ctxt.Diag("illegal combination %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 951 prasm(p) 952 if ops == nil { 953 ops = optab 954 } 955 return &ops[0] 956 } 957 958 func cmp(a int, b int) bool { 959 if a == b { 960 return true 961 } 962 switch a { 963 case C_LCON: 964 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 965 return true 966 } 967 968 case C_ADDCON: 969 if b == C_ZCON || b == C_SCON { 970 return true 971 } 972 973 case C_ANDCON: 974 if b == C_ZCON || b == C_SCON { 975 return true 976 } 977 978 case C_SPR: 979 if b == C_LR || b == C_XER || b == C_CTR { 980 return true 981 } 982 983 case C_UCON: 984 if b == C_ZCON { 985 return true 986 } 987 988 case C_SCON: 989 if b == C_ZCON { 990 return true 991 } 992 993 case C_LACON: 994 if b == C_SACON { 995 return true 996 } 997 998 case C_LBRA: 999 if b == C_SBRA { 1000 return true 1001 } 1002 1003 case C_LEXT: 1004 if b == C_SEXT { 1005 return true 1006 } 1007 1008 case C_LAUTO: 1009 if b == C_SAUTO { 1010 return true 1011 } 1012 1013 case C_REG: 1014 if b == C_ZCON { 1015 return r0iszero != 0 /*TypeKind(100016)*/ 1016 } 1017 1018 case C_LOREG: 1019 if b == C_ZOREG || b == C_SOREG { 1020 return true 1021 } 1022 1023 case C_SOREG: 1024 if b == C_ZOREG { 1025 return true 1026 } 1027 1028 case C_ANY: 1029 return true 1030 } 1031 1032 return false 1033 } 1034 1035 type ocmp []Optab 1036 1037 func (x ocmp) Len() int { 1038 return len(x) 1039 } 1040 1041 func (x ocmp) Swap(i, j int) { 1042 x[i], x[j] = x[j], x[i] 1043 } 1044 1045 func (x ocmp) Less(i, j int) bool { 1046 p1 := &x[i] 1047 p2 := &x[j] 1048 n := int(p1.as) - int(p2.as) 1049 if n != 0 { 1050 return n < 0 1051 } 1052 n = int(p1.a1) - int(p2.a1) 1053 if n != 0 { 1054 return n < 0 1055 } 1056 n = int(p1.a2) - int(p2.a2) 1057 if n != 0 { 1058 return n < 0 1059 } 1060 n = int(p1.a3) - int(p2.a3) 1061 if n != 0 { 1062 return n < 0 1063 } 1064 n = int(p1.a4) - int(p2.a4) 1065 if n != 0 { 1066 return n < 0 1067 } 1068 return false 1069 } 1070 func opset(a, b0 obj.As) { 1071 oprange[a&obj.AMask] = oprange[b0] 1072 } 1073 1074 func buildop(ctxt *obj.Link) { 1075 if oprange[AANDN&obj.AMask] != nil { 1076 // Already initialized; stop now. 1077 // This happens in the cmd/asm tests, 1078 // each of which re-initializes the arch. 1079 return 1080 } 1081 1082 var n int 1083 1084 for i := 0; i < C_NCLASS; i++ { 1085 for n = 0; n < C_NCLASS; n++ { 1086 if cmp(n, i) { 1087 xcmp[i][n] = true 1088 } 1089 } 1090 } 1091 for n = 0; optab[n].as != obj.AXXX; n++ { 1092 } 1093 sort.Sort(ocmp(optab[:n])) 1094 for i := 0; i < n; i++ { 1095 r := optab[i].as 1096 r0 := r & obj.AMask 1097 start := i 1098 for optab[i].as == r { 1099 i++ 1100 } 1101 oprange[r0] = optab[start:i] 1102 i-- 1103 1104 switch r { 1105 default: 1106 ctxt.Diag("unknown op in build: %v", r) 1107 log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r) 1108 1109 case ADCBF: /* unary indexed: op (b+a); op (b) */ 1110 opset(ADCBI, r0) 1111 1112 opset(ADCBST, r0) 1113 opset(ADCBT, r0) 1114 opset(ADCBTST, r0) 1115 opset(ADCBZ, r0) 1116 opset(AICBI, r0) 1117 1118 case AECOWX: /* indexed store: op s,(b+a); op s,(b) */ 1119 opset(ASTWCCC, r0) 1120 opset(ASTBCCC, r0) 1121 1122 opset(ASTDCCC, r0) 1123 1124 case AREM: /* macro */ 1125 opset(AREMCC, r0) 1126 1127 opset(AREMV, r0) 1128 opset(AREMVCC, r0) 1129 1130 case AREMU: 1131 opset(AREMU, r0) 1132 opset(AREMUCC, r0) 1133 opset(AREMUV, r0) 1134 opset(AREMUVCC, r0) 1135 1136 case AREMD: 1137 opset(AREMDCC, r0) 1138 opset(AREMDV, r0) 1139 opset(AREMDVCC, r0) 1140 1141 case AREMDU: 1142 opset(AREMDU, r0) 1143 opset(AREMDUCC, r0) 1144 opset(AREMDUV, r0) 1145 opset(AREMDUVCC, r0) 1146 1147 case ADIVW: /* op Rb[,Ra],Rd */ 1148 opset(AMULHW, r0) 1149 1150 opset(AMULHWCC, r0) 1151 opset(AMULHWU, r0) 1152 opset(AMULHWUCC, r0) 1153 opset(AMULLWCC, r0) 1154 opset(AMULLWVCC, r0) 1155 opset(AMULLWV, r0) 1156 opset(ADIVWCC, r0) 1157 opset(ADIVWV, r0) 1158 opset(ADIVWVCC, r0) 1159 opset(ADIVWU, r0) 1160 opset(ADIVWUCC, r0) 1161 opset(ADIVWUV, r0) 1162 opset(ADIVWUVCC, r0) 1163 opset(AADDCC, r0) 1164 opset(AADDCV, r0) 1165 opset(AADDCVCC, r0) 1166 opset(AADDV, r0) 1167 opset(AADDVCC, r0) 1168 opset(AADDE, r0) 1169 opset(AADDECC, r0) 1170 opset(AADDEV, r0) 1171 opset(AADDEVCC, r0) 1172 opset(ACRAND, r0) 1173 opset(ACRANDN, r0) 1174 opset(ACREQV, r0) 1175 opset(ACRNAND, r0) 1176 opset(ACRNOR, r0) 1177 opset(ACROR, r0) 1178 opset(ACRORN, r0) 1179 opset(ACRXOR, r0) 1180 opset(AMULHD, r0) 1181 opset(AMULHDCC, r0) 1182 opset(AMULHDU, r0) 1183 opset(AMULHDUCC, r0) 1184 opset(AMULLD, r0) 1185 opset(AMULLDCC, r0) 1186 opset(AMULLDVCC, r0) 1187 opset(AMULLDV, r0) 1188 opset(ADIVD, r0) 1189 opset(ADIVDCC, r0) 1190 opset(ADIVDE, r0) 1191 opset(ADIVDEU, r0) 1192 opset(ADIVDECC, r0) 1193 opset(ADIVDEUCC, r0) 1194 opset(ADIVDVCC, r0) 1195 opset(ADIVDV, r0) 1196 opset(ADIVDU, r0) 1197 opset(ADIVDUCC, r0) 1198 opset(ADIVDUVCC, r0) 1199 opset(ADIVDUCC, r0) 1200 1201 case APOPCNTD: 1202 opset(APOPCNTW, r0) 1203 opset(APOPCNTB, r0) 1204 1205 case ACOPY: /* copy, paste. */ 1206 opset(APASTECC, r0) 1207 1208 case AMADDHD: /* maddhd, maddhdu, maddld */ 1209 opset(AMADDHDU, r0) 1210 opset(AMADDLD, r0) 1211 1212 case AMOVBZ: /* lbz, stz, rlwm(r/r), lhz, lha, stz, and x variants */ 1213 opset(AMOVH, r0) 1214 opset(AMOVHZ, r0) 1215 1216 case AMOVBZU: /* lbz[x]u, stb[x]u, lhz[x]u, lha[x]u, sth[u]x, ld[x]u, std[u]x */ 1217 opset(AMOVHU, r0) 1218 1219 opset(AMOVHZU, r0) 1220 opset(AMOVWU, r0) 1221 opset(AMOVWZU, r0) 1222 opset(AMOVDU, r0) 1223 opset(AMOVMW, r0) 1224 1225 case ALV: /* lvebx, lvehx, lvewx, lvx, lvxl, lvsl, lvsr */ 1226 opset(ALVEBX, r0) 1227 opset(ALVEHX, r0) 1228 opset(ALVEWX, r0) 1229 opset(ALVX, r0) 1230 opset(ALVXL, r0) 1231 opset(ALVSL, r0) 1232 opset(ALVSR, r0) 1233 1234 case ASTV: /* stvebx, stvehx, stvewx, stvx, stvxl */ 1235 opset(ASTVEBX, r0) 1236 opset(ASTVEHX, r0) 1237 opset(ASTVEWX, r0) 1238 opset(ASTVX, r0) 1239 opset(ASTVXL, r0) 1240 1241 case AVAND: /* vand, vandc, vnand */ 1242 opset(AVAND, r0) 1243 opset(AVANDC, r0) 1244 opset(AVNAND, r0) 1245 1246 case AVOR: /* vor, vorc, vxor, vnor, veqv */ 1247 opset(AVOR, r0) 1248 opset(AVORC, r0) 1249 opset(AVXOR, r0) 1250 opset(AVNOR, r0) 1251 opset(AVEQV, r0) 1252 1253 case AVADDUM: /* vaddubm, vadduhm, vadduwm, vaddudm, vadduqm */ 1254 opset(AVADDUBM, r0) 1255 opset(AVADDUHM, r0) 1256 opset(AVADDUWM, r0) 1257 opset(AVADDUDM, r0) 1258 opset(AVADDUQM, r0) 1259 1260 case AVADDCU: /* vaddcuq, vaddcuw */ 1261 opset(AVADDCUQ, r0) 1262 opset(AVADDCUW, r0) 1263 1264 case AVADDUS: /* vaddubs, vadduhs, vadduws */ 1265 opset(AVADDUBS, r0) 1266 opset(AVADDUHS, r0) 1267 opset(AVADDUWS, r0) 1268 1269 case AVADDSS: /* vaddsbs, vaddshs, vaddsws */ 1270 opset(AVADDSBS, r0) 1271 opset(AVADDSHS, r0) 1272 opset(AVADDSWS, r0) 1273 1274 case AVADDE: /* vaddeuqm, vaddecuq */ 1275 opset(AVADDEUQM, r0) 1276 opset(AVADDECUQ, r0) 1277 1278 case AVSUBUM: /* vsububm, vsubuhm, vsubuwm, vsubudm, vsubuqm */ 1279 opset(AVSUBUBM, r0) 1280 opset(AVSUBUHM, r0) 1281 opset(AVSUBUWM, r0) 1282 opset(AVSUBUDM, r0) 1283 opset(AVSUBUQM, r0) 1284 1285 case AVSUBCU: /* vsubcuq, vsubcuw */ 1286 opset(AVSUBCUQ, r0) 1287 opset(AVSUBCUW, r0) 1288 1289 case AVSUBUS: /* vsububs, vsubuhs, vsubuws */ 1290 opset(AVSUBUBS, r0) 1291 opset(AVSUBUHS, r0) 1292 opset(AVSUBUWS, r0) 1293 1294 case AVSUBSS: /* vsubsbs, vsubshs, vsubsws */ 1295 opset(AVSUBSBS, r0) 1296 opset(AVSUBSHS, r0) 1297 opset(AVSUBSWS, r0) 1298 1299 case AVSUBE: /* vsubeuqm, vsubecuq */ 1300 opset(AVSUBEUQM, r0) 1301 opset(AVSUBECUQ, r0) 1302 1303 case AVPMSUM: /* vpmsumb, vpmsumh, vpmsumw, vpmsumd */ 1304 opset(AVPMSUMB, r0) 1305 opset(AVPMSUMH, r0) 1306 opset(AVPMSUMW, r0) 1307 opset(AVPMSUMD, r0) 1308 1309 case AVR: /* vrlb, vrlh, vrlw, vrld */ 1310 opset(AVRLB, r0) 1311 opset(AVRLH, r0) 1312 opset(AVRLW, r0) 1313 opset(AVRLD, r0) 1314 1315 case AVS: /* vs[l,r], vs[l,r]o, vs[l,r]b, vs[l,r]h, vs[l,r]w, vs[l,r]d */ 1316 opset(AVSLB, r0) 1317 opset(AVSLH, r0) 1318 opset(AVSLW, r0) 1319 opset(AVSL, r0) 1320 opset(AVSLO, r0) 1321 opset(AVSRB, r0) 1322 opset(AVSRH, r0) 1323 opset(AVSRW, r0) 1324 opset(AVSR, r0) 1325 opset(AVSRO, r0) 1326 opset(AVSLD, r0) 1327 opset(AVSRD, r0) 1328 1329 case AVSA: /* vsrab, vsrah, vsraw, vsrad */ 1330 opset(AVSRAB, r0) 1331 opset(AVSRAH, r0) 1332 opset(AVSRAW, r0) 1333 opset(AVSRAD, r0) 1334 1335 case AVSOI: /* vsldoi */ 1336 opset(AVSLDOI, r0) 1337 1338 case AVCLZ: /* vclzb, vclzh, vclzw, vclzd */ 1339 opset(AVCLZB, r0) 1340 opset(AVCLZH, r0) 1341 opset(AVCLZW, r0) 1342 opset(AVCLZD, r0) 1343 1344 case AVPOPCNT: /* vpopcntb, vpopcnth, vpopcntw, vpopcntd */ 1345 opset(AVPOPCNTB, r0) 1346 opset(AVPOPCNTH, r0) 1347 opset(AVPOPCNTW, r0) 1348 opset(AVPOPCNTD, r0) 1349 1350 case AVCMPEQ: /* vcmpequb[.], vcmpequh[.], vcmpequw[.], vcmpequd[.] */ 1351 opset(AVCMPEQUB, r0) 1352 opset(AVCMPEQUBCC, r0) 1353 opset(AVCMPEQUH, r0) 1354 opset(AVCMPEQUHCC, r0) 1355 opset(AVCMPEQUW, r0) 1356 opset(AVCMPEQUWCC, r0) 1357 opset(AVCMPEQUD, r0) 1358 opset(AVCMPEQUDCC, r0) 1359 1360 case AVCMPGT: /* vcmpgt[u,s]b[.], vcmpgt[u,s]h[.], vcmpgt[u,s]w[.], vcmpgt[u,s]d[.] */ 1361 opset(AVCMPGTUB, r0) 1362 opset(AVCMPGTUBCC, r0) 1363 opset(AVCMPGTUH, r0) 1364 opset(AVCMPGTUHCC, r0) 1365 opset(AVCMPGTUW, r0) 1366 opset(AVCMPGTUWCC, r0) 1367 opset(AVCMPGTUD, r0) 1368 opset(AVCMPGTUDCC, r0) 1369 opset(AVCMPGTSB, r0) 1370 opset(AVCMPGTSBCC, r0) 1371 opset(AVCMPGTSH, r0) 1372 opset(AVCMPGTSHCC, r0) 1373 opset(AVCMPGTSW, r0) 1374 opset(AVCMPGTSWCC, r0) 1375 opset(AVCMPGTSD, r0) 1376 opset(AVCMPGTSDCC, r0) 1377 1378 case AVCMPNEZB: /* vcmpnezb[.] */ 1379 opset(AVCMPNEZBCC, r0) 1380 1381 case AVPERM: /* vperm */ 1382 opset(AVPERM, r0) 1383 1384 case AVBPERMQ: /* vbpermq, vbpermd */ 1385 opset(AVBPERMD, r0) 1386 1387 case AVSEL: /* vsel */ 1388 opset(AVSEL, r0) 1389 1390 case AVSPLT: /* vspltb, vsplth, vspltw */ 1391 opset(AVSPLTB, r0) 1392 opset(AVSPLTH, r0) 1393 opset(AVSPLTW, r0) 1394 1395 case AVSPLTI: /* vspltisb, vspltish, vspltisw */ 1396 opset(AVSPLTISB, r0) 1397 opset(AVSPLTISH, r0) 1398 opset(AVSPLTISW, r0) 1399 1400 case AVCIPH: /* vcipher, vcipherlast */ 1401 opset(AVCIPHER, r0) 1402 opset(AVCIPHERLAST, r0) 1403 1404 case AVNCIPH: /* vncipher, vncipherlast */ 1405 opset(AVNCIPHER, r0) 1406 opset(AVNCIPHERLAST, r0) 1407 1408 case AVSBOX: /* vsbox */ 1409 opset(AVSBOX, r0) 1410 1411 case AVSHASIGMA: /* vshasigmaw, vshasigmad */ 1412 opset(AVSHASIGMAW, r0) 1413 opset(AVSHASIGMAD, r0) 1414 1415 case ALXV: /* lxvd2x, lxvdsx, lxvw4x */ 1416 opset(ALXVD2X, r0) 1417 opset(ALXVDSX, r0) 1418 opset(ALXVW4X, r0) 1419 1420 case ASTXV: /* stxvd2x, stxvdsx, stxvw4x */ 1421 opset(ASTXVD2X, r0) 1422 opset(ASTXVW4X, r0) 1423 1424 case ALXS: /* lxsdx */ 1425 opset(ALXSDX, r0) 1426 1427 case ASTXS: /* stxsdx */ 1428 opset(ASTXSDX, r0) 1429 1430 case ALXSI: /* lxsiwax, lxsiwzx */ 1431 opset(ALXSIWAX, r0) 1432 opset(ALXSIWZX, r0) 1433 1434 case ASTXSI: /* stxsiwx */ 1435 opset(ASTXSIWX, r0) 1436 1437 case AMFVSR: /* mfvsrd, mfvsrwz (and extended mnemonics), mfvsrld */ 1438 opset(AMFVSRD, r0) 1439 opset(AMFFPRD, r0) 1440 opset(AMFVRD, r0) 1441 opset(AMFVSRWZ, r0) 1442 opset(AMFVSRLD, r0) 1443 1444 case AMTVSR: /* mtvsrd, mtvsrwa, mtvsrwz (and extended mnemonics), mtvsrdd, mtvsrws */ 1445 opset(AMTVSRD, r0) 1446 opset(AMTFPRD, r0) 1447 opset(AMTVRD, r0) 1448 opset(AMTVSRWA, r0) 1449 opset(AMTVSRWZ, r0) 1450 opset(AMTVSRDD, r0) 1451 opset(AMTVSRWS, r0) 1452 1453 case AXXLAND: /* xxland, xxlandc, xxleqv, xxlnand */ 1454 opset(AXXLANDQ, r0) 1455 opset(AXXLANDC, r0) 1456 opset(AXXLEQV, r0) 1457 opset(AXXLNAND, r0) 1458 1459 case AXXLOR: /* xxlorc, xxlnor, xxlor, xxlxor */ 1460 opset(AXXLORC, r0) 1461 opset(AXXLNOR, r0) 1462 opset(AXXLORQ, r0) 1463 opset(AXXLXOR, r0) 1464 1465 case AXXSEL: /* xxsel */ 1466 opset(AXXSEL, r0) 1467 1468 case AXXMRG: /* xxmrghw, xxmrglw */ 1469 opset(AXXMRGHW, r0) 1470 opset(AXXMRGLW, r0) 1471 1472 case AXXSPLT: /* xxspltw */ 1473 opset(AXXSPLTW, r0) 1474 1475 case AXXPERM: /* xxpermdi */ 1476 opset(AXXPERMDI, r0) 1477 1478 case AXXSI: /* xxsldwi */ 1479 opset(AXXSLDWI, r0) 1480 1481 case AXSCV: /* xscvdpsp, xscvspdp, xscvdpspn, xscvspdpn */ 1482 opset(AXSCVDPSP, r0) 1483 opset(AXSCVSPDP, r0) 1484 opset(AXSCVDPSPN, r0) 1485 opset(AXSCVSPDPN, r0) 1486 1487 case AXVCV: /* xvcvdpsp, xvcvspdp */ 1488 opset(AXVCVDPSP, r0) 1489 opset(AXVCVSPDP, r0) 1490 1491 case AXSCVX: /* xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws */ 1492 opset(AXSCVDPSXDS, r0) 1493 opset(AXSCVDPSXWS, r0) 1494 opset(AXSCVDPUXDS, r0) 1495 opset(AXSCVDPUXWS, r0) 1496 1497 case AXSCVXP: /* xscvsxddp, xscvuxddp, xscvsxdsp, xscvuxdsp */ 1498 opset(AXSCVSXDDP, r0) 1499 opset(AXSCVUXDDP, r0) 1500 opset(AXSCVSXDSP, r0) 1501 opset(AXSCVUXDSP, r0) 1502 1503 case AXVCVX: /* xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws, xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws */ 1504 opset(AXVCVDPSXDS, r0) 1505 opset(AXVCVDPSXWS, r0) 1506 opset(AXVCVDPUXDS, r0) 1507 opset(AXVCVDPUXWS, r0) 1508 opset(AXVCVSPSXDS, r0) 1509 opset(AXVCVSPSXWS, r0) 1510 opset(AXVCVSPUXDS, r0) 1511 opset(AXVCVSPUXWS, r0) 1512 1513 case AXVCVXP: /* xvcvsxddp, xvcvsxwdp, xvcvuxddp, xvcvuxwdp, xvcvsxdsp, xvcvsxwsp, xvcvuxdsp, xvcvuxwsp */ 1514 opset(AXVCVSXDDP, r0) 1515 opset(AXVCVSXWDP, r0) 1516 opset(AXVCVUXDDP, r0) 1517 opset(AXVCVUXWDP, r0) 1518 opset(AXVCVSXDSP, r0) 1519 opset(AXVCVSXWSP, r0) 1520 opset(AXVCVUXDSP, r0) 1521 opset(AXVCVUXWSP, r0) 1522 1523 case AAND: /* logical op Rb,Rs,Ra; no literal */ 1524 opset(AANDN, r0) 1525 1526 opset(AANDNCC, r0) 1527 opset(AEQV, r0) 1528 opset(AEQVCC, r0) 1529 opset(ANAND, r0) 1530 opset(ANANDCC, r0) 1531 opset(ANOR, r0) 1532 opset(ANORCC, r0) 1533 opset(AORCC, r0) 1534 opset(AORN, r0) 1535 opset(AORNCC, r0) 1536 opset(AXORCC, r0) 1537 1538 case AADDME: /* op Ra, Rd */ 1539 opset(AADDMECC, r0) 1540 1541 opset(AADDMEV, r0) 1542 opset(AADDMEVCC, r0) 1543 opset(AADDZE, r0) 1544 opset(AADDZECC, r0) 1545 opset(AADDZEV, r0) 1546 opset(AADDZEVCC, r0) 1547 opset(ASUBME, r0) 1548 opset(ASUBMECC, r0) 1549 opset(ASUBMEV, r0) 1550 opset(ASUBMEVCC, r0) 1551 opset(ASUBZE, r0) 1552 opset(ASUBZECC, r0) 1553 opset(ASUBZEV, r0) 1554 opset(ASUBZEVCC, r0) 1555 1556 case AADDC: 1557 opset(AADDCCC, r0) 1558 1559 case ABEQ: 1560 opset(ABGE, r0) 1561 opset(ABGT, r0) 1562 opset(ABLE, r0) 1563 opset(ABLT, r0) 1564 opset(ABNE, r0) 1565 opset(ABVC, r0) 1566 opset(ABVS, r0) 1567 1568 case ABR: 1569 opset(ABL, r0) 1570 1571 case ABC: 1572 opset(ABCL, r0) 1573 1574 case AEXTSB: /* op Rs, Ra */ 1575 opset(AEXTSBCC, r0) 1576 1577 opset(AEXTSH, r0) 1578 opset(AEXTSHCC, r0) 1579 opset(ACNTLZW, r0) 1580 opset(ACNTLZWCC, r0) 1581 opset(ACNTLZD, r0) 1582 opset(AEXTSW, r0) 1583 opset(AEXTSWCC, r0) 1584 opset(ACNTLZDCC, r0) 1585 1586 case AFABS: /* fop [s,]d */ 1587 opset(AFABSCC, r0) 1588 1589 opset(AFNABS, r0) 1590 opset(AFNABSCC, r0) 1591 opset(AFNEG, r0) 1592 opset(AFNEGCC, r0) 1593 opset(AFRSP, r0) 1594 opset(AFRSPCC, r0) 1595 opset(AFCTIW, r0) 1596 opset(AFCTIWCC, r0) 1597 opset(AFCTIWZ, r0) 1598 opset(AFCTIWZCC, r0) 1599 opset(AFCTID, r0) 1600 opset(AFCTIDCC, r0) 1601 opset(AFCTIDZ, r0) 1602 opset(AFCTIDZCC, r0) 1603 opset(AFCFID, r0) 1604 opset(AFCFIDCC, r0) 1605 opset(AFCFIDU, r0) 1606 opset(AFCFIDUCC, r0) 1607 opset(AFCFIDS, r0) 1608 opset(AFCFIDSCC, r0) 1609 opset(AFRES, r0) 1610 opset(AFRESCC, r0) 1611 opset(AFRIM, r0) 1612 opset(AFRIMCC, r0) 1613 opset(AFRIP, r0) 1614 opset(AFRIPCC, r0) 1615 opset(AFRIZ, r0) 1616 opset(AFRIZCC, r0) 1617 opset(AFRSQRTE, r0) 1618 opset(AFRSQRTECC, r0) 1619 opset(AFSQRT, r0) 1620 opset(AFSQRTCC, r0) 1621 opset(AFSQRTS, r0) 1622 opset(AFSQRTSCC, r0) 1623 1624 case AFADD: 1625 opset(AFADDS, r0) 1626 opset(AFADDCC, r0) 1627 opset(AFADDSCC, r0) 1628 opset(AFCPSGN, r0) 1629 opset(AFCPSGNCC, r0) 1630 opset(AFDIV, r0) 1631 opset(AFDIVS, r0) 1632 opset(AFDIVCC, r0) 1633 opset(AFDIVSCC, r0) 1634 opset(AFSUB, r0) 1635 opset(AFSUBS, r0) 1636 opset(AFSUBCC, r0) 1637 opset(AFSUBSCC, r0) 1638 1639 case AFMADD: 1640 opset(AFMADDCC, r0) 1641 opset(AFMADDS, r0) 1642 opset(AFMADDSCC, r0) 1643 opset(AFMSUB, r0) 1644 opset(AFMSUBCC, r0) 1645 opset(AFMSUBS, r0) 1646 opset(AFMSUBSCC, r0) 1647 opset(AFNMADD, r0) 1648 opset(AFNMADDCC, r0) 1649 opset(AFNMADDS, r0) 1650 opset(AFNMADDSCC, r0) 1651 opset(AFNMSUB, r0) 1652 opset(AFNMSUBCC, r0) 1653 opset(AFNMSUBS, r0) 1654 opset(AFNMSUBSCC, r0) 1655 opset(AFSEL, r0) 1656 opset(AFSELCC, r0) 1657 1658 case AFMUL: 1659 opset(AFMULS, r0) 1660 opset(AFMULCC, r0) 1661 opset(AFMULSCC, r0) 1662 1663 case AFCMPO: 1664 opset(AFCMPU, r0) 1665 1666 case AISEL: 1667 opset(AISEL, r0) 1668 1669 case AMTFSB0: 1670 opset(AMTFSB0CC, r0) 1671 opset(AMTFSB1, r0) 1672 opset(AMTFSB1CC, r0) 1673 1674 case ANEG: /* op [Ra,] Rd */ 1675 opset(ANEGCC, r0) 1676 1677 opset(ANEGV, r0) 1678 opset(ANEGVCC, r0) 1679 1680 case AOR: /* or/xor Rb,Rs,Ra; ori/xori $uimm,Rs,Ra; oris/xoris $uimm,Rs,Ra */ 1681 opset(AXOR, r0) 1682 1683 case ASLW: 1684 opset(ASLWCC, r0) 1685 opset(ASRW, r0) 1686 opset(ASRWCC, r0) 1687 opset(AROTLW, r0) 1688 1689 case ASLD: 1690 opset(ASLDCC, r0) 1691 opset(ASRD, r0) 1692 opset(ASRDCC, r0) 1693 opset(AROTL, r0) 1694 1695 case ASRAW: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1696 opset(ASRAWCC, r0) 1697 1698 case ASRAD: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1699 opset(ASRADCC, r0) 1700 1701 case ASUB: /* SUB Ra,Rb,Rd => subf Rd,ra,rb */ 1702 opset(ASUB, r0) 1703 1704 opset(ASUBCC, r0) 1705 opset(ASUBV, r0) 1706 opset(ASUBVCC, r0) 1707 opset(ASUBCCC, r0) 1708 opset(ASUBCV, r0) 1709 opset(ASUBCVCC, r0) 1710 opset(ASUBE, r0) 1711 opset(ASUBECC, r0) 1712 opset(ASUBEV, r0) 1713 opset(ASUBEVCC, r0) 1714 1715 case ASYNC: 1716 opset(AISYNC, r0) 1717 opset(ALWSYNC, r0) 1718 opset(APTESYNC, r0) 1719 opset(ATLBSYNC, r0) 1720 1721 case ARLWMI: 1722 opset(ARLWMICC, r0) 1723 opset(ARLWNM, r0) 1724 opset(ARLWNMCC, r0) 1725 1726 case ARLDMI: 1727 opset(ARLDMICC, r0) 1728 opset(ARLDIMI, r0) 1729 opset(ARLDIMICC, r0) 1730 1731 case ARLDC: 1732 opset(ARLDCCC, r0) 1733 1734 case ARLDCL: 1735 opset(ARLDCR, r0) 1736 opset(ARLDCLCC, r0) 1737 opset(ARLDCRCC, r0) 1738 1739 case ARLDICL: 1740 opset(ARLDICLCC, r0) 1741 opset(ARLDICR, r0) 1742 opset(ARLDICRCC, r0) 1743 1744 case AFMOVD: 1745 opset(AFMOVDCC, r0) 1746 opset(AFMOVDU, r0) 1747 opset(AFMOVS, r0) 1748 opset(AFMOVSU, r0) 1749 1750 case AECIWX: 1751 opset(ALBAR, r0) 1752 opset(ALWAR, r0) 1753 opset(ALDAR, r0) 1754 1755 case ASYSCALL: /* just the op; flow of control */ 1756 opset(ARFI, r0) 1757 1758 opset(ARFCI, r0) 1759 opset(ARFID, r0) 1760 opset(AHRFID, r0) 1761 1762 case AMOVHBR: 1763 opset(AMOVWBR, r0) 1764 opset(AMOVDBR, r0) 1765 1766 case ASLBMFEE: 1767 opset(ASLBMFEV, r0) 1768 1769 case ATW: 1770 opset(ATD, r0) 1771 1772 case ATLBIE: 1773 opset(ASLBIE, r0) 1774 opset(ATLBIEL, r0) 1775 1776 case AEIEIO: 1777 opset(ASLBIA, r0) 1778 1779 case ACMP: 1780 opset(ACMPW, r0) 1781 1782 case ACMPU: 1783 opset(ACMPWU, r0) 1784 1785 case ACMPB: 1786 opset(ACMPB, r0) 1787 1788 case AFTDIV: 1789 opset(AFTDIV, r0) 1790 1791 case AFTSQRT: 1792 opset(AFTSQRT, r0) 1793 1794 case AADD, 1795 AANDCC, /* and. Rb,Rs,Ra; andi. $uimm,Rs,Ra; andis. $uimm,Rs,Ra */ 1796 AFMOVSX, 1797 AFMOVSZ, 1798 ALSW, 1799 AMOVW, 1800 /* load/store/move word with sign extension; special 32-bit move; move 32-bit literals */ 1801 AMOVWZ, /* load/store/move word with zero extension; move 32-bit literals */ 1802 AMOVD, /* load/store/move 64-bit values, including 32-bit literals with/without sign-extension */ 1803 AMOVB, /* macro: move byte with sign extension */ 1804 AMOVBU, /* macro: move byte with sign extension & update */ 1805 AMOVFL, 1806 AMULLW, 1807 /* op $s[,r2],r3; op r1[,r2],r3; no cc/v */ 1808 ASUBC, /* op r1,$s,r3; op r1[,r2],r3 */ 1809 ASTSW, 1810 ASLBMTE, 1811 AWORD, 1812 ADWORD, 1813 ADARN, 1814 ALDMX, 1815 AVMSUMUDM, 1816 AADDEX, 1817 ACMPEQB, 1818 obj.ANOP, 1819 obj.ATEXT, 1820 obj.AUNDEF, 1821 obj.AFUNCDATA, 1822 obj.APCDATA, 1823 obj.ADUFFZERO, 1824 obj.ADUFFCOPY: 1825 break 1826 } 1827 } 1828 } 1829 1830 func OPVXX1(o uint32, xo uint32, oe uint32) uint32 { 1831 return o<<26 | xo<<1 | oe<<11 1832 } 1833 1834 func OPVXX2(o uint32, xo uint32, oe uint32) uint32 { 1835 return o<<26 | xo<<2 | oe<<11 1836 } 1837 1838 func OPVXX3(o uint32, xo uint32, oe uint32) uint32 { 1839 return o<<26 | xo<<3 | oe<<11 1840 } 1841 1842 func OPVXX4(o uint32, xo uint32, oe uint32) uint32 { 1843 return o<<26 | xo<<4 | oe<<11 1844 } 1845 1846 func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1847 return o<<26 | xo | oe<<11 | rc&1 1848 } 1849 1850 func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1851 return o<<26 | xo | oe<<11 | (rc&1)<<10 1852 } 1853 1854 func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1855 return o<<26 | xo<<1 | oe<<10 | rc&1 1856 } 1857 1858 func OPCC(o uint32, xo uint32, rc uint32) uint32 { 1859 return OPVCC(o, xo, 0, rc) 1860 } 1861 1862 func OP(o uint32, xo uint32) uint32 { 1863 return OPVCC(o, xo, 0, 0) 1864 } 1865 1866 /* the order is dest, a/s, b/imm for both arithmetic and logical operations */ 1867 func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 { 1868 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 1869 } 1870 1871 /* VX-form 2-register operands, r/none/r */ 1872 func AOP_RR(op uint32, d uint32, a uint32) uint32 { 1873 return op | (d&31)<<21 | (a&31)<<11 1874 } 1875 1876 /* VA-form 4-register operands */ 1877 func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1878 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6 1879 } 1880 1881 func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1882 return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF 1883 } 1884 1885 /* VX-form 2-register + UIM operands */ 1886 func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1887 return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11 1888 } 1889 1890 /* VX-form 2-register + ST + SIX operands */ 1891 func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 { 1892 return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11 1893 } 1894 1895 /* VA-form 3-register + SHB operands */ 1896 func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 { 1897 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6 1898 } 1899 1900 /* VX-form 1-register + SIM operands */ 1901 func AOP_IR(op uint32, d uint32, simm uint32) uint32 { 1902 return op | (d&31)<<21 | (simm&31)<<16 1903 } 1904 1905 /* XX1-form 3-register operands, 1 VSR operand */ 1906 func AOP_XX1(op uint32, d uint32, a uint32, b uint32) uint32 { 1907 /* For the XX-form encodings, we need the VSX register number to be exactly */ 1908 /* between 0-63, so we can properly set the rightmost bits. */ 1909 r := d - REG_VS0 1910 return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5 1911 } 1912 1913 /* XX2-form 3-register operands, 2 VSR operands */ 1914 func AOP_XX2(op uint32, d uint32, a uint32, b uint32) uint32 { 1915 xt := d - REG_VS0 1916 xb := b - REG_VS0 1917 return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5 1918 } 1919 1920 /* XX3-form 3 VSR operands */ 1921 func AOP_XX3(op uint32, d uint32, a uint32, b uint32) uint32 { 1922 xt := d - REG_VS0 1923 xa := a - REG_VS0 1924 xb := b - REG_VS0 1925 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1926 } 1927 1928 /* XX3-form 3 VSR operands + immediate */ 1929 func AOP_XX3I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1930 xt := d - REG_VS0 1931 xa := a - REG_VS0 1932 xb := b - REG_VS0 1933 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1934 } 1935 1936 /* XX4-form, 4 VSR operands */ 1937 func AOP_XX4(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1938 xt := d - REG_VS0 1939 xa := a - REG_VS0 1940 xb := b - REG_VS0 1941 xc := c - REG_VS0 1942 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1943 } 1944 1945 /* Z23-form, 3-register operands + CY field */ 1946 func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1947 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&3)<<7 1948 } 1949 1950 func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 { 1951 return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11 1952 } 1953 1954 func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 { 1955 return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF 1956 } 1957 1958 func OP_BR(op uint32, li uint32, aa uint32) uint32 { 1959 return op | li&0x03FFFFFC | aa<<1 1960 } 1961 1962 func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 { 1963 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1 1964 } 1965 1966 func OP_BCR(op uint32, bo uint32, bi uint32) uint32 { 1967 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 1968 } 1969 1970 func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 { 1971 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1 1972 } 1973 1974 func AOP_RLDIC(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 { 1975 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5 1976 } 1977 1978 func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 { 1979 return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6 1980 } 1981 1982 const ( 1983 /* each rhs is OPVCC(_, _, _, _) */ 1984 OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0 1985 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0 1986 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0 1987 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0 1988 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0 1989 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0 1990 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0 1991 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0 1992 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0 1993 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0 1994 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0 1995 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0 1996 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0 1997 OP_MFMSR = 31<<26 | 83<<1 | 0<<10 | 0 1998 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0 1999 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0 2000 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0 2001 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0 2002 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0 2003 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0 2004 OP_MTMSR = 31<<26 | 146<<1 | 0<<10 | 0 2005 OP_MTMSRD = 31<<26 | 178<<1 | 0<<10 | 0 2006 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0 2007 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0 2008 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0 2009 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0 2010 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0 2011 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0 2012 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0 2013 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0 2014 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0 2015 OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0 2016 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0 2017 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0 2018 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0 2019 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0 2020 OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0 2021 ) 2022 2023 func oclass(a *obj.Addr) int { 2024 return int(a.Class) - 1 2025 } 2026 2027 const ( 2028 D_FORM = iota 2029 DS_FORM 2030 ) 2031 2032 // This function determines when a non-indexed load or store is D or 2033 // DS form for use in finding the size of the offset field in the instruction. 2034 // The size is needed when setting the offset value in the instruction 2035 // and when generating relocation for that field. 2036 // DS form instructions include: ld, ldu, lwa, std, stdu. All other 2037 // loads and stores with an offset field are D form. This function should 2038 // only be called with the same opcodes as are handled by opstore and opload. 2039 func (c *ctxt9) opform(insn uint32) int { 2040 switch insn { 2041 default: 2042 c.ctxt.Diag("bad insn in loadform: %x", insn) 2043 case OPVCC(58, 0, 0, 0), // ld 2044 OPVCC(58, 0, 0, 1), // ldu 2045 OPVCC(58, 0, 0, 0) | 1<<1, // lwa 2046 OPVCC(62, 0, 0, 0), // std 2047 OPVCC(62, 0, 0, 1): //stdu 2048 return DS_FORM 2049 case OP_ADDI, // add 2050 OPVCC(32, 0, 0, 0), // lwz 2051 OPVCC(33, 0, 0, 0), // lwzu 2052 OPVCC(34, 0, 0, 0), // lbz 2053 OPVCC(35, 0, 0, 0), // lbzu 2054 OPVCC(40, 0, 0, 0), // lhz 2055 OPVCC(41, 0, 0, 0), // lhzu 2056 OPVCC(42, 0, 0, 0), // lha 2057 OPVCC(43, 0, 0, 0), // lhau 2058 OPVCC(46, 0, 0, 0), // lmw 2059 OPVCC(48, 0, 0, 0), // lfs 2060 OPVCC(49, 0, 0, 0), // lfsu 2061 OPVCC(50, 0, 0, 0), // lfd 2062 OPVCC(51, 0, 0, 0), // lfdu 2063 OPVCC(36, 0, 0, 0), // stw 2064 OPVCC(37, 0, 0, 0), // stwu 2065 OPVCC(38, 0, 0, 0), // stb 2066 OPVCC(39, 0, 0, 0), // stbu 2067 OPVCC(44, 0, 0, 0), // sth 2068 OPVCC(45, 0, 0, 0), // sthu 2069 OPVCC(47, 0, 0, 0), // stmw 2070 OPVCC(52, 0, 0, 0), // stfs 2071 OPVCC(53, 0, 0, 0), // stfsu 2072 OPVCC(54, 0, 0, 0), // stfd 2073 OPVCC(55, 0, 0, 0): // stfdu 2074 return D_FORM 2075 } 2076 return 0 2077 } 2078 2079 // Encode instructions and create relocation for accessing s+d according to the 2080 // instruction op with source or destination (as appropriate) register reg. 2081 func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32) (o1, o2 uint32) { 2082 var base uint32 2083 form := c.opform(op) 2084 if c.ctxt.Flag_shared { 2085 base = REG_R2 2086 } else { 2087 base = REG_R0 2088 } 2089 o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0) 2090 o2 = AOP_IRR(op, uint32(reg), REGTMP, 0) 2091 rel := obj.Addrel(c.cursym) 2092 rel.Off = int32(c.pc) 2093 rel.Siz = 8 2094 rel.Sym = s 2095 rel.Add = d 2096 if c.ctxt.Flag_shared { 2097 switch form { 2098 case D_FORM: 2099 rel.Type = objabi.R_ADDRPOWER_TOCREL 2100 case DS_FORM: 2101 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS 2102 } 2103 2104 } else { 2105 switch form { 2106 case D_FORM: 2107 rel.Type = objabi.R_ADDRPOWER 2108 case DS_FORM: 2109 rel.Type = objabi.R_ADDRPOWER_DS 2110 } 2111 } 2112 return 2113 } 2114 2115 /* 2116 * 32-bit masks 2117 */ 2118 func getmask(m []byte, v uint32) bool { 2119 m[1] = 0 2120 m[0] = m[1] 2121 if v != ^uint32(0) && v&(1<<31) != 0 && v&1 != 0 { /* MB > ME */ 2122 if getmask(m, ^v) { 2123 i := int(m[0]) 2124 m[0] = m[1] + 1 2125 m[1] = byte(i - 1) 2126 return true 2127 } 2128 2129 return false 2130 } 2131 2132 for i := 0; i < 32; i++ { 2133 if v&(1<<uint(31-i)) != 0 { 2134 m[0] = byte(i) 2135 for { 2136 m[1] = byte(i) 2137 i++ 2138 if i >= 32 || v&(1<<uint(31-i)) == 0 { 2139 break 2140 } 2141 } 2142 2143 for ; i < 32; i++ { 2144 if v&(1<<uint(31-i)) != 0 { 2145 return false 2146 } 2147 } 2148 return true 2149 } 2150 } 2151 2152 return false 2153 } 2154 2155 func (c *ctxt9) maskgen(p *obj.Prog, m []byte, v uint32) { 2156 if !getmask(m, v) { 2157 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2158 } 2159 } 2160 2161 /* 2162 * 64-bit masks (rldic etc) 2163 */ 2164 func getmask64(m []byte, v uint64) bool { 2165 m[1] = 0 2166 m[0] = m[1] 2167 for i := 0; i < 64; i++ { 2168 if v&(uint64(1)<<uint(63-i)) != 0 { 2169 m[0] = byte(i) 2170 for { 2171 m[1] = byte(i) 2172 i++ 2173 if i >= 64 || v&(uint64(1)<<uint(63-i)) == 0 { 2174 break 2175 } 2176 } 2177 2178 for ; i < 64; i++ { 2179 if v&(uint64(1)<<uint(63-i)) != 0 { 2180 return false 2181 } 2182 } 2183 return true 2184 } 2185 } 2186 2187 return false 2188 } 2189 2190 func (c *ctxt9) maskgen64(p *obj.Prog, m []byte, v uint64) { 2191 if !getmask64(m, v) { 2192 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2193 } 2194 } 2195 2196 func loadu32(r int, d int64) uint32 { 2197 v := int32(d >> 16) 2198 if isuint32(uint64(d)) { 2199 return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v)) 2200 } 2201 return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v)) 2202 } 2203 2204 func high16adjusted(d int32) uint16 { 2205 if d&0x8000 != 0 { 2206 return uint16((d >> 16) + 1) 2207 } 2208 return uint16(d >> 16) 2209 } 2210 2211 func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) { 2212 o1 := uint32(0) 2213 o2 := uint32(0) 2214 o3 := uint32(0) 2215 o4 := uint32(0) 2216 o5 := uint32(0) 2217 2218 //print("%v => case %d\n", p, o->type); 2219 switch o.type_ { 2220 default: 2221 c.ctxt.Diag("unknown type %d", o.type_) 2222 prasm(p) 2223 2224 case 0: /* pseudo ops */ 2225 break 2226 2227 case 1: /* mov r1,r2 ==> OR Rs,Rs,Ra */ 2228 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2229 v := c.regoff(&p.From) 2230 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2231 //nerrors--; 2232 c.ctxt.Diag("literal operation on R0\n%v", p) 2233 } 2234 2235 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2236 break 2237 } 2238 2239 o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg)) 2240 2241 case 2: /* int/cr/fp op Rb,[Ra],Rd */ 2242 r := int(p.Reg) 2243 2244 if r == 0 { 2245 r = int(p.To.Reg) 2246 } 2247 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2248 2249 case 3: /* mov $soreg/addcon/ucon, r ==> addis/addi $i,reg',r */ 2250 d := c.vregoff(&p.From) 2251 2252 v := int32(d) 2253 r := int(p.From.Reg) 2254 if r == 0 { 2255 r = int(o.param) 2256 } 2257 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 && (r != 0 || v != 0) { 2258 c.ctxt.Diag("literal operation on R0\n%v", p) 2259 } 2260 a := OP_ADDI 2261 if o.a1 == C_UCON { 2262 if d&0xffff != 0 { 2263 log.Fatalf("invalid handling of %v", p) 2264 } 2265 v >>= 16 2266 if r == REGZERO && isuint32(uint64(d)) { 2267 o1 = LOP_IRR(OP_ORIS, uint32(p.To.Reg), REGZERO, uint32(v)) 2268 break 2269 } 2270 2271 a = OP_ADDIS 2272 } else { 2273 if int64(int16(d)) != d { 2274 log.Fatalf("invalid handling of %v", p) 2275 } 2276 } 2277 2278 o1 = AOP_IRR(uint32(a), uint32(p.To.Reg), uint32(r), uint32(v)) 2279 2280 case 4: /* add/mul $scon,[r1],r2 */ 2281 v := c.regoff(&p.From) 2282 2283 r := int(p.Reg) 2284 if r == 0 { 2285 r = int(p.To.Reg) 2286 } 2287 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 { 2288 c.ctxt.Diag("literal operation on R0\n%v", p) 2289 } 2290 if int32(int16(v)) != v { 2291 log.Fatalf("mishandled instruction %v", p) 2292 } 2293 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2294 2295 case 5: /* syscall */ 2296 o1 = c.oprrr(p.As) 2297 2298 case 6: /* logical op Rb,[Rs,]Ra; no literal */ 2299 r := int(p.Reg) 2300 2301 if r == 0 { 2302 r = int(p.To.Reg) 2303 } 2304 // AROTL and AROTLW are extended mnemonics, which map to RLDCL and RLWNM. 2305 switch p.As { 2306 case AROTL: 2307 o1 = AOP_RLDIC(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0)) 2308 case AROTLW: 2309 o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31) 2310 default: 2311 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2312 } 2313 2314 case 7: /* mov r, soreg ==> stw o(r) */ 2315 r := int(p.To.Reg) 2316 2317 if r == 0 { 2318 r = int(o.param) 2319 } 2320 v := c.regoff(&p.To) 2321 if p.To.Type == obj.TYPE_MEM && p.To.Index != 0 { 2322 if v != 0 { 2323 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2324 } 2325 if c.ctxt.Flag_shared && r == REG_R13 { 2326 rel := obj.Addrel(c.cursym) 2327 rel.Off = int32(c.pc) 2328 rel.Siz = 4 2329 // This (and the matching part in the load case 2330 // below) are the only places in the ppc64 toolchain 2331 // that knows the name of the tls variable. Possibly 2332 // we could add some assembly syntax so that the name 2333 // of the variable does not have to be assumed. 2334 rel.Sym = c.ctxt.Lookup("runtime.tls_g") 2335 rel.Type = objabi.R_POWER_TLS 2336 } 2337 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r)) 2338 } else { 2339 if int32(int16(v)) != v { 2340 log.Fatalf("mishandled instruction %v", p) 2341 } 2342 // Offsets in DS form stores must be a multiple of 4 2343 inst := c.opstore(p.As) 2344 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2345 log.Fatalf("invalid offset for DS form load/store %v", p) 2346 } 2347 o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v)) 2348 } 2349 2350 case 8: /* mov soreg, r ==> lbz/lhz/lwz o(r) */ 2351 r := int(p.From.Reg) 2352 2353 if r == 0 { 2354 r = int(o.param) 2355 } 2356 v := c.regoff(&p.From) 2357 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2358 if v != 0 { 2359 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2360 } 2361 if c.ctxt.Flag_shared && r == REG_R13 { 2362 rel := obj.Addrel(c.cursym) 2363 rel.Off = int32(c.pc) 2364 rel.Siz = 4 2365 rel.Sym = c.ctxt.Lookup("runtime.tls_g") 2366 rel.Type = objabi.R_POWER_TLS 2367 } 2368 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2369 } else { 2370 if int32(int16(v)) != v { 2371 log.Fatalf("mishandled instruction %v", p) 2372 } 2373 // Offsets in DS form loads must be a multiple of 4 2374 inst := c.opload(p.As) 2375 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2376 log.Fatalf("invalid offset for DS form load/store %v", p) 2377 } 2378 o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v)) 2379 } 2380 2381 case 9: /* movb soreg, r ==> lbz o(r),r2; extsb r2,r2 */ 2382 r := int(p.From.Reg) 2383 2384 if r == 0 { 2385 r = int(o.param) 2386 } 2387 v := c.regoff(&p.From) 2388 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2389 if v != 0 { 2390 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2391 } 2392 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2393 } else { 2394 o1 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2395 } 2396 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2397 2398 case 10: /* sub Ra,[Rb],Rd => subf Rd,Ra,Rb */ 2399 r := int(p.Reg) 2400 2401 if r == 0 { 2402 r = int(p.To.Reg) 2403 } 2404 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r)) 2405 2406 case 11: /* br/bl lbra */ 2407 v := int32(0) 2408 2409 if p.Pcond != nil { 2410 v = int32(p.Pcond.Pc - p.Pc) 2411 if v&03 != 0 { 2412 c.ctxt.Diag("odd branch target address\n%v", p) 2413 v &^= 03 2414 } 2415 2416 if v < -(1<<25) || v >= 1<<24 { 2417 c.ctxt.Diag("branch too far\n%v", p) 2418 } 2419 } 2420 2421 o1 = OP_BR(c.opirr(p.As), uint32(v), 0) 2422 if p.To.Sym != nil { 2423 rel := obj.Addrel(c.cursym) 2424 rel.Off = int32(c.pc) 2425 rel.Siz = 4 2426 rel.Sym = p.To.Sym 2427 v += int32(p.To.Offset) 2428 if v&03 != 0 { 2429 c.ctxt.Diag("odd branch target address\n%v", p) 2430 v &^= 03 2431 } 2432 2433 rel.Add = int64(v) 2434 rel.Type = objabi.R_CALLPOWER 2435 } 2436 o2 = 0x60000000 // nop, sometimes overwritten by ld r2, 24(r1) when dynamic linking 2437 2438 case 12: /* movb r,r (extsb); movw r,r (extsw) */ 2439 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2440 v := c.regoff(&p.From) 2441 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2442 c.ctxt.Diag("literal operation on R0\n%v", p) 2443 } 2444 2445 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2446 break 2447 } 2448 2449 if p.As == AMOVW { 2450 o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2451 } else { 2452 o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2453 } 2454 2455 case 13: /* mov[bhw]z r,r; uses rlwinm not andi. to avoid changing CC */ 2456 if p.As == AMOVBZ { 2457 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31) 2458 } else if p.As == AMOVH { 2459 o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2460 } else if p.As == AMOVHZ { 2461 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31) 2462 } else if p.As == AMOVWZ { 2463 o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5 /* MB=32 */ 2464 } else { 2465 c.ctxt.Diag("internal: bad mov[bhw]z\n%v", p) 2466 } 2467 2468 case 14: /* rldc[lr] Rb,Rs,$mask,Ra -- left, right give different masks */ 2469 r := int(p.Reg) 2470 2471 if r == 0 { 2472 r = int(p.To.Reg) 2473 } 2474 d := c.vregoff(p.GetFrom3()) 2475 var a int 2476 switch p.As { 2477 // These opcodes expect a mask operand that has to be converted into the 2478 // appropriate operand. The way these were defined, not all valid masks are possible. 2479 // Left here for compatibility in case they were used or generated. 2480 case ARLDCL, ARLDCLCC: 2481 var mask [2]uint8 2482 c.maskgen64(p, mask[:], uint64(d)) 2483 2484 a = int(mask[0]) /* MB */ 2485 if mask[1] != 63 { 2486 c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p) 2487 } 2488 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2489 o1 |= (uint32(a) & 31) << 6 2490 if a&0x20 != 0 { 2491 o1 |= 1 << 5 /* mb[5] is top bit */ 2492 } 2493 2494 case ARLDCR, ARLDCRCC: 2495 var mask [2]uint8 2496 c.maskgen64(p, mask[:], uint64(d)) 2497 2498 a = int(mask[1]) /* ME */ 2499 if mask[0] != 0 { 2500 c.ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p) 2501 } 2502 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2503 o1 |= (uint32(a) & 31) << 6 2504 if a&0x20 != 0 { 2505 o1 |= 1 << 5 /* mb[5] is top bit */ 2506 } 2507 2508 // These opcodes use a shift count like the ppc64 asm, no mask conversion done 2509 case ARLDICR, ARLDICRCC: 2510 me := int(d) 2511 sh := c.regoff(&p.From) 2512 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(me)) 2513 2514 case ARLDICL, ARLDICLCC: 2515 mb := int(d) 2516 sh := c.regoff(&p.From) 2517 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(mb)) 2518 2519 default: 2520 c.ctxt.Diag("unexpected op in rldc case\n%v", p) 2521 a = 0 2522 } 2523 2524 case 17, /* bc bo,bi,lbra (same for now) */ 2525 16: /* bc bo,bi,sbra */ 2526 a := 0 2527 2528 r := int(p.Reg) 2529 2530 if p.From.Type == obj.TYPE_CONST { 2531 a = int(c.regoff(&p.From)) 2532 } else if p.From.Type == obj.TYPE_REG { 2533 if r != 0 { 2534 c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r) 2535 } 2536 // BI values for the CR 2537 switch p.From.Reg { 2538 case REG_CR0: 2539 r = BI_CR0 2540 case REG_CR1: 2541 r = BI_CR1 2542 case REG_CR2: 2543 r = BI_CR2 2544 case REG_CR3: 2545 r = BI_CR3 2546 case REG_CR4: 2547 r = BI_CR4 2548 case REG_CR5: 2549 r = BI_CR5 2550 case REG_CR6: 2551 r = BI_CR6 2552 case REG_CR7: 2553 r = BI_CR7 2554 default: 2555 c.ctxt.Diag("unrecognized register: expecting CR\n") 2556 } 2557 } 2558 v := int32(0) 2559 if p.Pcond != nil { 2560 v = int32(p.Pcond.Pc - p.Pc) 2561 } 2562 if v&03 != 0 { 2563 c.ctxt.Diag("odd branch target address\n%v", p) 2564 v &^= 03 2565 } 2566 2567 if v < -(1<<16) || v >= 1<<15 { 2568 c.ctxt.Diag("branch too far\n%v", p) 2569 } 2570 o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0) 2571 2572 case 15: /* br/bl (r) => mov r,lr; br/bl (lr) */ 2573 var v int32 2574 if p.As == ABC || p.As == ABCL { 2575 v = c.regoff(&p.To) & 31 2576 } else { 2577 v = 20 /* unconditional */ 2578 } 2579 o1 = AOP_RRR(OP_MTSPR, uint32(p.To.Reg), 0, 0) | (REG_LR&0x1f)<<16 | ((REG_LR>>5)&0x1f)<<11 2580 o2 = OPVCC(19, 16, 0, 0) 2581 if p.As == ABL || p.As == ABCL { 2582 o2 |= 1 2583 } 2584 o2 = OP_BCR(o2, uint32(v), uint32(p.To.Index)) 2585 2586 case 18: /* br/bl (lr/ctr); bc/bcl bo,bi,(lr/ctr) */ 2587 var v int32 2588 if p.As == ABC || p.As == ABCL { 2589 v = c.regoff(&p.From) & 31 2590 } else { 2591 v = 20 /* unconditional */ 2592 } 2593 r := int(p.Reg) 2594 if r == 0 { 2595 r = 0 2596 } 2597 switch oclass(&p.To) { 2598 case C_CTR: 2599 o1 = OPVCC(19, 528, 0, 0) 2600 2601 case C_LR: 2602 o1 = OPVCC(19, 16, 0, 0) 2603 2604 default: 2605 c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p) 2606 v = 0 2607 } 2608 2609 if p.As == ABL || p.As == ABCL { 2610 o1 |= 1 2611 } 2612 o1 = OP_BCR(o1, uint32(v), uint32(r)) 2613 2614 case 19: /* mov $lcon,r ==> cau+or */ 2615 d := c.vregoff(&p.From) 2616 2617 if p.From.Sym == nil { 2618 o1 = loadu32(int(p.To.Reg), d) 2619 o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d))) 2620 } else { 2621 o1, o2 = c.symbolAccess(p.From.Sym, d, p.To.Reg, OP_ADDI) 2622 } 2623 2624 //if(dlm) reloc(&p->from, p->pc, 0); 2625 2626 case 20: /* add $ucon,,r */ 2627 v := c.regoff(&p.From) 2628 2629 r := int(p.Reg) 2630 if r == 0 { 2631 r = int(p.To.Reg) 2632 } 2633 if p.As == AADD && (r0iszero == 0 /*TypeKind(100016)*/ && p.Reg == 0 || r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0) { 2634 c.ctxt.Diag("literal operation on R0\n%v", p) 2635 } 2636 o1 = AOP_IRR(c.opirr(-p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) 2637 2638 case 22: /* add $lcon,r1,r2 ==> cau+or+add */ /* could do add/sub more efficiently */ 2639 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2640 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2641 } 2642 d := c.vregoff(&p.From) 2643 o1 = loadu32(REGTMP, d) 2644 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2645 r := int(p.Reg) 2646 if r == 0 { 2647 r = int(p.To.Reg) 2648 } 2649 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2650 if p.From.Sym != nil { 2651 c.ctxt.Diag("%v is not supported", p) 2652 } 2653 2654 //if(dlm) reloc(&p->from, p->pc, 0); 2655 2656 case 23: /* and $lcon,r1,r2 ==> cau+or+and */ /* masks could be done using rlnm etc. */ 2657 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2658 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2659 } 2660 d := c.vregoff(&p.From) 2661 o1 = loadu32(REGTMP, d) 2662 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2663 r := int(p.Reg) 2664 if r == 0 { 2665 r = int(p.To.Reg) 2666 } 2667 o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2668 if p.From.Sym != nil { 2669 c.ctxt.Diag("%v is not supported", p) 2670 } 2671 2672 //if(dlm) reloc(&p->from, p->pc, 0); 2673 2674 /*24*/ 2675 case 25: 2676 /* sld[.] $sh,rS,rA -> rldicr[.] $sh,rS,mask(0,63-sh),rA; srd[.] -> rldicl */ 2677 v := c.regoff(&p.From) 2678 2679 if v < 0 { 2680 v = 0 2681 } else if v > 63 { 2682 v = 63 2683 } 2684 r := int(p.Reg) 2685 if r == 0 { 2686 r = int(p.To.Reg) 2687 } 2688 var a int 2689 op := uint32(0) 2690 switch p.As { 2691 case ASLD, ASLDCC: 2692 a = int(63 - v) 2693 op = OP_RLDICR 2694 2695 case ASRD, ASRDCC: 2696 a = int(v) 2697 v = 64 - v 2698 op = OP_RLDICL 2699 case AROTL: 2700 a = int(0) 2701 op = OP_RLDICL 2702 default: 2703 c.ctxt.Diag("unexpected op in sldi case\n%v", p) 2704 a = 0 2705 o1 = 0 2706 } 2707 2708 o1 = AOP_RLDIC(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a)) 2709 if p.As == ASLDCC || p.As == ASRDCC { 2710 o1 |= 1 // Set the condition code bit 2711 } 2712 2713 case 26: /* mov $lsext/auto/oreg,,r2 ==> addis+addi */ 2714 if p.To.Reg == REGTMP { 2715 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2716 } 2717 v := c.regoff(&p.From) 2718 r := int(p.From.Reg) 2719 if r == 0 { 2720 r = int(o.param) 2721 } 2722 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2723 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGTMP, uint32(v)) 2724 2725 case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */ 2726 v := c.regoff(p.GetFrom3()) 2727 2728 r := int(p.From.Reg) 2729 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2730 2731 case 28: /* subc r1,$lcon,r2 ==> cau+or+subfc */ 2732 if p.To.Reg == REGTMP || p.From.Reg == REGTMP { 2733 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2734 } 2735 v := c.regoff(p.GetFrom3()) 2736 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16) 2737 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(v)) 2738 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP) 2739 if p.From.Sym != nil { 2740 c.ctxt.Diag("%v is not supported", p) 2741 } 2742 2743 //if(dlm) reloc(&p->from3, p->pc, 0); 2744 2745 case 29: /* rldic[lr]? $sh,s,$mask,a -- left, right, plain give different masks */ 2746 v := c.regoff(&p.From) 2747 2748 d := c.vregoff(p.GetFrom3()) 2749 var mask [2]uint8 2750 c.maskgen64(p, mask[:], uint64(d)) 2751 var a int 2752 switch p.As { 2753 case ARLDC, ARLDCCC: 2754 a = int(mask[0]) /* MB */ 2755 if int32(mask[1]) != (63 - v) { 2756 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2757 } 2758 2759 case ARLDCL, ARLDCLCC: 2760 a = int(mask[0]) /* MB */ 2761 if mask[1] != 63 { 2762 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2763 } 2764 2765 case ARLDCR, ARLDCRCC: 2766 a = int(mask[1]) /* ME */ 2767 if mask[0] != 0 { 2768 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2769 } 2770 2771 default: 2772 c.ctxt.Diag("unexpected op in rldic case\n%v", p) 2773 a = 0 2774 } 2775 2776 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2777 o1 |= (uint32(a) & 31) << 6 2778 if v&0x20 != 0 { 2779 o1 |= 1 << 1 2780 } 2781 if a&0x20 != 0 { 2782 o1 |= 1 << 5 /* mb[5] is top bit */ 2783 } 2784 2785 case 30: /* rldimi $sh,s,$mask,a */ 2786 v := c.regoff(&p.From) 2787 2788 d := c.vregoff(p.GetFrom3()) 2789 2790 // Original opcodes had mask operands which had to be converted to a shift count as expected by 2791 // the ppc64 asm. 2792 switch p.As { 2793 case ARLDMI, ARLDMICC: 2794 var mask [2]uint8 2795 c.maskgen64(p, mask[:], uint64(d)) 2796 if int32(mask[1]) != (63 - v) { 2797 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2798 } 2799 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2800 o1 |= (uint32(mask[0]) & 31) << 6 2801 if v&0x20 != 0 { 2802 o1 |= 1 << 1 2803 } 2804 if mask[0]&0x20 != 0 { 2805 o1 |= 1 << 5 /* mb[5] is top bit */ 2806 } 2807 2808 // Opcodes with shift count operands. 2809 case ARLDIMI, ARLDIMICC: 2810 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2811 o1 |= (uint32(d) & 31) << 6 2812 if d&0x20 != 0 { 2813 o1 |= 1 << 5 2814 } 2815 if v&0x20 != 0 { 2816 o1 |= 1 << 1 2817 } 2818 } 2819 2820 case 31: /* dword */ 2821 d := c.vregoff(&p.From) 2822 2823 if c.ctxt.Arch.ByteOrder == binary.BigEndian { 2824 o1 = uint32(d >> 32) 2825 o2 = uint32(d) 2826 } else { 2827 o1 = uint32(d) 2828 o2 = uint32(d >> 32) 2829 } 2830 2831 if p.From.Sym != nil { 2832 rel := obj.Addrel(c.cursym) 2833 rel.Off = int32(c.pc) 2834 rel.Siz = 8 2835 rel.Sym = p.From.Sym 2836 rel.Add = p.From.Offset 2837 rel.Type = objabi.R_ADDR 2838 o2 = 0 2839 o1 = o2 2840 } 2841 2842 case 32: /* fmul frc,fra,frd */ 2843 r := int(p.Reg) 2844 2845 if r == 0 { 2846 r = int(p.To.Reg) 2847 } 2848 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6 2849 2850 case 33: /* fabs [frb,]frd; fmr. frb,frd */ 2851 r := int(p.From.Reg) 2852 2853 if oclass(&p.From) == C_NONE { 2854 r = int(p.To.Reg) 2855 } 2856 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r)) 2857 2858 case 34: /* FMADDx fra,frb,frc,frt (t=a*c±b) */ 2859 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.GetFrom3().Reg)&31)<<6 2860 2861 case 35: /* mov r,lext/lauto/loreg ==> cau $(v>>16),sb,r'; store o(r') */ 2862 v := c.regoff(&p.To) 2863 2864 r := int(p.To.Reg) 2865 if r == 0 { 2866 r = int(o.param) 2867 } 2868 // Offsets in DS form stores must be a multiple of 4 2869 inst := c.opstore(p.As) 2870 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2871 log.Fatalf("invalid offset for DS form load/store %v", p) 2872 } 2873 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2874 o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v)) 2875 2876 case 36: /* mov bz/h/hz lext/lauto/lreg,r ==> lbz/lha/lhz etc */ 2877 v := c.regoff(&p.From) 2878 2879 r := int(p.From.Reg) 2880 if r == 0 { 2881 r = int(o.param) 2882 } 2883 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2884 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2885 2886 case 37: /* movb lext/lauto/lreg,r ==> lbz o(reg),r; extsb r */ 2887 v := c.regoff(&p.From) 2888 2889 r := int(p.From.Reg) 2890 if r == 0 { 2891 r = int(o.param) 2892 } 2893 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2894 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2895 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2896 2897 case 40: /* word */ 2898 o1 = uint32(c.regoff(&p.From)) 2899 2900 case 41: /* stswi */ 2901 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11 2902 2903 case 42: /* lswi */ 2904 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11 2905 2906 case 43: /* data cache instructions: op (Ra+[Rb]), [th|l] */ 2907 /* TH field for dcbt/dcbtst: */ 2908 /* 0 = Block access - program will soon access EA. */ 2909 /* 8-15 = Stream access - sequence of access (data stream). See section 4.3.2 of the ISA for details. */ 2910 /* 16 = Block access - program will soon make a transient access to EA. */ 2911 /* 17 = Block access - program will not access EA for a long time. */ 2912 2913 /* L field for dcbf: */ 2914 /* 0 = invalidates the block containing EA in all processors. */ 2915 /* 1 = same as 0, but with limited scope (i.e. block in the current processor will not be reused soon). */ 2916 /* 3 = same as 1, but with even more limited scope (i.e. block in the current processor primary cache will not be reused soon). */ 2917 if p.To.Type == obj.TYPE_NONE { 2918 o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg)) 2919 } else { 2920 th := c.regoff(&p.To) 2921 o1 = AOP_RRR(c.oprrr(p.As), uint32(th), uint32(p.From.Index), uint32(p.From.Reg)) 2922 } 2923 2924 case 44: /* indexed store */ 2925 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 2926 2927 case 45: /* indexed load */ 2928 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 2929 2930 case 46: /* plain op */ 2931 o1 = c.oprrr(p.As) 2932 2933 case 47: /* op Ra, Rd; also op [Ra,] Rd */ 2934 r := int(p.From.Reg) 2935 2936 if r == 0 { 2937 r = int(p.To.Reg) 2938 } 2939 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) 2940 2941 case 48: /* op Rs, Ra */ 2942 r := int(p.From.Reg) 2943 2944 if r == 0 { 2945 r = int(p.To.Reg) 2946 } 2947 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) 2948 2949 case 49: /* op Rb; op $n, Rb */ 2950 if p.From.Type != obj.TYPE_REG { /* tlbie $L, rB */ 2951 v := c.regoff(&p.From) & 1 2952 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21 2953 } else { 2954 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg)) 2955 } 2956 2957 case 50: /* rem[u] r1[,r2],r3 */ 2958 r := int(p.Reg) 2959 2960 if r == 0 { 2961 r = int(p.To.Reg) 2962 } 2963 v := c.oprrr(p.As) 2964 t := v & (1<<10 | 1) /* OE|Rc */ 2965 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2966 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg)) 2967 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2968 if p.As == AREMU { 2969 o4 = o3 2970 2971 /* Clear top 32 bits */ 2972 o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5 2973 } 2974 2975 case 51: /* remd[u] r1[,r2],r3 */ 2976 r := int(p.Reg) 2977 2978 if r == 0 { 2979 r = int(p.To.Reg) 2980 } 2981 v := c.oprrr(p.As) 2982 t := v & (1<<10 | 1) /* OE|Rc */ 2983 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2984 o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg)) 2985 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2986 2987 case 52: /* mtfsbNx cr(n) */ 2988 v := c.regoff(&p.From) & 31 2989 2990 o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0) 2991 2992 case 53: /* mffsX ,fr1 */ 2993 o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0) 2994 2995 case 54: /* mov msr,r1; mov r1, msr*/ 2996 if oclass(&p.From) == C_REG { 2997 if p.As == AMOVD { 2998 o1 = AOP_RRR(OP_MTMSRD, uint32(p.From.Reg), 0, 0) 2999 } else { 3000 o1 = AOP_RRR(OP_MTMSR, uint32(p.From.Reg), 0, 0) 3001 } 3002 } else { 3003 o1 = AOP_RRR(OP_MFMSR, uint32(p.To.Reg), 0, 0) 3004 } 3005 3006 case 55: /* op Rb, Rd */ 3007 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg)) 3008 3009 case 56: /* sra $sh,[s,]a; srd $sh,[s,]a */ 3010 v := c.regoff(&p.From) 3011 3012 r := int(p.Reg) 3013 if r == 0 { 3014 r = int(p.To.Reg) 3015 } 3016 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31) 3017 if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) { 3018 o1 |= 1 << 1 /* mb[5] */ 3019 } 3020 3021 case 57: /* slw $sh,[s,]a -> rlwinm ... */ 3022 v := c.regoff(&p.From) 3023 3024 r := int(p.Reg) 3025 if r == 0 { 3026 r = int(p.To.Reg) 3027 } 3028 3029 /* 3030 * Let user (gs) shoot himself in the foot. 3031 * qc has already complained. 3032 * 3033 if(v < 0 || v > 31) 3034 ctxt->diag("illegal shift %ld\n%v", v, p); 3035 */ 3036 if v < 0 { 3037 v = 0 3038 } else if v > 32 { 3039 v = 32 3040 } 3041 var mask [2]uint8 3042 switch p.As { 3043 case AROTLW: 3044 mask[0], mask[1] = 0, 31 3045 case ASRW, ASRWCC: 3046 mask[0], mask[1] = uint8(v), 31 3047 v = 32 - v 3048 default: 3049 mask[0], mask[1] = 0, uint8(31-v) 3050 } 3051 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1])) 3052 if p.As == ASLWCC || p.As == ASRWCC { 3053 o1 |= 1 // set the condition code 3054 } 3055 3056 case 58: /* logical $andcon,[s],a */ 3057 v := c.regoff(&p.From) 3058 3059 r := int(p.Reg) 3060 if r == 0 { 3061 r = int(p.To.Reg) 3062 } 3063 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 3064 3065 case 59: /* or/and $ucon,,r */ 3066 v := c.regoff(&p.From) 3067 3068 r := int(p.Reg) 3069 if r == 0 { 3070 r = int(p.To.Reg) 3071 } 3072 o1 = LOP_IRR(c.opirr(-p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) /* oris, xoris, andis */ 3073 3074 case 60: /* tw to,a,b */ 3075 r := int(c.regoff(&p.From) & 31) 3076 3077 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg)) 3078 3079 case 61: /* tw to,a,$simm */ 3080 r := int(c.regoff(&p.From) & 31) 3081 3082 v := c.regoff(&p.To) 3083 o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v)) 3084 3085 case 62: /* rlwmi $sh,s,$mask,a */ 3086 v := c.regoff(&p.From) 3087 3088 var mask [2]uint8 3089 c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3()))) 3090 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v)) 3091 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 3092 3093 case 63: /* rlwmi b,s,$mask,a */ 3094 var mask [2]uint8 3095 c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3()))) 3096 3097 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(p.From.Reg)) 3098 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 3099 3100 case 64: /* mtfsf fr[, $m] {,fpcsr} */ 3101 var v int32 3102 if p.From3Type() != obj.TYPE_NONE { 3103 v = c.regoff(p.GetFrom3()) & 255 3104 } else { 3105 v = 255 3106 } 3107 o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11 3108 3109 case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */ 3110 if p.To.Reg == 0 { 3111 c.ctxt.Diag("must specify FPSCR(n)\n%v", p) 3112 } 3113 o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12 3114 3115 case 66: /* mov spr,r1; mov r1,spr, also dcr */ 3116 var r int 3117 var v int32 3118 if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 { 3119 r = int(p.From.Reg) 3120 v = int32(p.To.Reg) 3121 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3122 o1 = OPVCC(31, 451, 0, 0) /* mtdcr */ 3123 } else { 3124 o1 = OPVCC(31, 467, 0, 0) /* mtspr */ 3125 } 3126 } else { 3127 r = int(p.To.Reg) 3128 v = int32(p.From.Reg) 3129 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3130 o1 = OPVCC(31, 323, 0, 0) /* mfdcr */ 3131 } else { 3132 o1 = OPVCC(31, 339, 0, 0) /* mfspr */ 3133 } 3134 } 3135 3136 o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11 3137 3138 case 67: /* mcrf crfD,crfS */ 3139 if p.From.Type != obj.TYPE_REG || p.From.Reg < REG_CR0 || REG_CR7 < p.From.Reg || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3140 c.ctxt.Diag("illegal CR field number\n%v", p) 3141 } 3142 o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0) 3143 3144 case 68: /* mfcr rD; mfocrf CRM,rD */ 3145 if p.From.Type == obj.TYPE_REG && REG_CR0 <= p.From.Reg && p.From.Reg <= REG_CR7 { 3146 v := int32(1 << uint(7-(p.To.Reg&7))) /* CR(n) */ 3147 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) | 1<<20 | uint32(v)<<12 /* new form, mfocrf */ 3148 } else { 3149 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) /* old form, whole register */ 3150 } 3151 3152 case 69: /* mtcrf CRM,rS */ 3153 var v int32 3154 if p.From3Type() != obj.TYPE_NONE { 3155 if p.To.Reg != 0 { 3156 c.ctxt.Diag("can't use both mask and CR(n)\n%v", p) 3157 } 3158 v = c.regoff(p.GetFrom3()) & 0xff 3159 } else { 3160 if p.To.Reg == 0 { 3161 v = 0xff /* CR */ 3162 } else { 3163 v = 1 << uint(7-(p.To.Reg&7)) /* CR(n) */ 3164 } 3165 } 3166 3167 o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12 3168 3169 case 70: /* [f]cmp r,r,cr*/ 3170 var r int 3171 if p.Reg == 0 { 3172 r = 0 3173 } else { 3174 r = (int(p.Reg) & 7) << 2 3175 } 3176 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.From.Reg), uint32(p.To.Reg)) 3177 3178 case 71: /* cmp[l] r,i,cr*/ 3179 var r int 3180 if p.Reg == 0 { 3181 r = 0 3182 } else { 3183 r = (int(p.Reg) & 7) << 2 3184 } 3185 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.From.Reg), 0) | uint32(c.regoff(&p.To))&0xffff 3186 3187 case 72: /* slbmte (Rb+Rs -> slb[Rb]) -> Rs, Rb */ 3188 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg)) 3189 3190 case 73: /* mcrfs crfD,crfS */ 3191 if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3192 c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p) 3193 } 3194 o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0) 3195 3196 case 77: /* syscall $scon, syscall Rx */ 3197 if p.From.Type == obj.TYPE_CONST { 3198 if p.From.Offset > BIG || p.From.Offset < -BIG { 3199 c.ctxt.Diag("illegal syscall, sysnum too large: %v", p) 3200 } 3201 o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset)) 3202 } else if p.From.Type == obj.TYPE_REG { 3203 o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg)) 3204 } else { 3205 c.ctxt.Diag("illegal syscall: %v", p) 3206 o1 = 0x7fe00008 // trap always 3207 } 3208 3209 o2 = c.oprrr(p.As) 3210 o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO) // XOR R0, R0 3211 3212 case 78: /* undef */ 3213 o1 = 0 /* "An instruction consisting entirely of binary 0s is guaranteed 3214 always to be an illegal instruction." */ 3215 3216 /* relocation operations */ 3217 case 74: 3218 v := c.vregoff(&p.To) 3219 // Offsets in DS form stores must be a multiple of 4 3220 inst := c.opstore(p.As) 3221 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3222 log.Fatalf("invalid offset for DS form load/store %v", p) 3223 } 3224 o1, o2 = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst) 3225 3226 //if(dlm) reloc(&p->to, p->pc, 1); 3227 3228 case 75: 3229 v := c.vregoff(&p.From) 3230 // Offsets in DS form loads must be a multiple of 4 3231 inst := c.opload(p.As) 3232 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3233 log.Fatalf("invalid offset for DS form load/store %v", p) 3234 } 3235 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst) 3236 3237 //if(dlm) reloc(&p->from, p->pc, 1); 3238 3239 case 76: 3240 v := c.vregoff(&p.From) 3241 // Offsets in DS form loads must be a multiple of 4 3242 inst := c.opload(p.As) 3243 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3244 log.Fatalf("invalid offset for DS form load/store %v", p) 3245 } 3246 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst) 3247 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 3248 3249 //if(dlm) reloc(&p->from, p->pc, 1); 3250 3251 case 79: 3252 if p.From.Offset != 0 { 3253 c.ctxt.Diag("invalid offset against tls var %v", p) 3254 } 3255 o1 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGZERO, 0) 3256 rel := obj.Addrel(c.cursym) 3257 rel.Off = int32(c.pc) 3258 rel.Siz = 4 3259 rel.Sym = p.From.Sym 3260 rel.Type = objabi.R_POWER_TLS_LE 3261 3262 case 80: 3263 if p.From.Offset != 0 { 3264 c.ctxt.Diag("invalid offset against tls var %v", p) 3265 } 3266 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3267 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3268 rel := obj.Addrel(c.cursym) 3269 rel.Off = int32(c.pc) 3270 rel.Siz = 8 3271 rel.Sym = p.From.Sym 3272 rel.Type = objabi.R_POWER_TLS_IE 3273 3274 case 81: 3275 v := c.vregoff(&p.To) 3276 if v != 0 { 3277 c.ctxt.Diag("invalid offset against GOT slot %v", p) 3278 } 3279 3280 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3281 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3282 rel := obj.Addrel(c.cursym) 3283 rel.Off = int32(c.pc) 3284 rel.Siz = 8 3285 rel.Sym = p.From.Sym 3286 rel.Type = objabi.R_ADDRPOWER_GOT 3287 case 82: /* vector instructions, VX-form and VC-form */ 3288 if p.From.Type == obj.TYPE_REG { 3289 /* reg reg none OR reg reg reg */ 3290 /* 3-register operand order: VRA, VRB, VRT */ 3291 /* 2-register operand order: VRA, VRT */ 3292 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3293 } else if p.From3Type() == obj.TYPE_CONST { 3294 /* imm imm reg reg */ 3295 /* operand order: SIX, VRA, ST, VRT */ 3296 six := int(c.regoff(&p.From)) 3297 st := int(c.regoff(p.GetFrom3())) 3298 o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six)) 3299 } else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 { 3300 /* imm reg reg */ 3301 /* operand order: UIM, VRB, VRT */ 3302 uim := int(c.regoff(&p.From)) 3303 o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim)) 3304 } else { 3305 /* imm reg */ 3306 /* operand order: SIM, VRT */ 3307 sim := int(c.regoff(&p.From)) 3308 o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim)) 3309 } 3310 3311 case 83: /* vector instructions, VA-form */ 3312 if p.From.Type == obj.TYPE_REG { 3313 /* reg reg reg reg */ 3314 /* 4-register operand order: VRA, VRB, VRC, VRT */ 3315 o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg)) 3316 } else if p.From.Type == obj.TYPE_CONST { 3317 /* imm reg reg reg */ 3318 /* operand order: SHB, VRA, VRB, VRT */ 3319 shb := int(c.regoff(&p.From)) 3320 o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(shb)) 3321 } 3322 3323 case 84: // ISEL BC,RA,RB,RT -> isel rt,ra,rb,bc 3324 bc := c.vregoff(&p.From) 3325 3326 // rt = To.Reg, ra = p.Reg, rb = p.From3.Reg 3327 o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(bc)) 3328 3329 case 85: /* vector instructions, VX-form */ 3330 /* reg none reg */ 3331 /* 2-register operand order: VRB, VRT */ 3332 o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg)) 3333 3334 case 86: /* VSX indexed store, XX1-form */ 3335 /* reg reg reg */ 3336 /* 3-register operand order: XT, (RB)(RA*1) */ 3337 o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 3338 3339 case 87: /* VSX indexed load, XX1-form */ 3340 /* reg reg reg */ 3341 /* 3-register operand order: (RB)(RA*1), XT */ 3342 o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 3343 3344 case 88: /* VSX instructions, XX1-form */ 3345 /* reg reg none OR reg reg reg */ 3346 /* 3-register operand order: RA, RB, XT */ 3347 /* 2-register operand order: XS, RA or RA, XT */ 3348 xt := int32(p.To.Reg) 3349 xs := int32(p.From.Reg) 3350 /* We need to treat the special case of extended mnemonics that may have a FREG/VREG as an argument */ 3351 if REG_V0 <= xt && xt <= REG_V31 { 3352 /* Convert V0-V31 to VS32-VS63 */ 3353 xt = xt + 64 3354 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3355 } else if REG_F0 <= xt && xt <= REG_F31 { 3356 /* Convert F0-F31 to VS0-VS31 */ 3357 xt = xt + 64 3358 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3359 } else if REG_VS0 <= xt && xt <= REG_VS63 { 3360 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3361 } else if REG_V0 <= xs && xs <= REG_V31 { 3362 /* Likewise for XS */ 3363 xs = xs + 64 3364 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3365 } else if REG_F0 <= xs && xs <= REG_F31 { 3366 xs = xs + 64 3367 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3368 } else if REG_VS0 <= xs && xs <= REG_VS63 { 3369 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3370 } 3371 3372 case 89: /* VSX instructions, XX2-form */ 3373 /* reg none reg OR reg imm reg */ 3374 /* 2-register operand order: XB, XT or XB, UIM, XT*/ 3375 uim := int(c.regoff(p.GetFrom3())) 3376 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg)) 3377 3378 case 90: /* VSX instructions, XX3-form */ 3379 if p.From3Type() == obj.TYPE_NONE { 3380 /* reg reg reg */ 3381 /* 3-register operand order: XA, XB, XT */ 3382 o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3383 } else if p.From3Type() == obj.TYPE_CONST { 3384 /* reg reg reg imm */ 3385 /* operand order: XA, XB, DM, XT */ 3386 dm := int(c.regoff(p.GetFrom3())) 3387 o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm)) 3388 } 3389 3390 case 91: /* VSX instructions, XX4-form */ 3391 /* reg reg reg reg */ 3392 /* 3-register operand order: XA, XB, XC, XT */ 3393 o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg)) 3394 3395 case 92: /* X-form instructions, 3-operands */ 3396 if p.To.Type == obj.TYPE_CONST { 3397 /* imm reg reg */ 3398 xf := int32(p.From.Reg) 3399 if REG_F0 <= xf && xf <= REG_F31 { 3400 /* operand order: FRA, FRB, BF */ 3401 bf := int(c.regoff(&p.To)) << 2 3402 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg)) 3403 } else { 3404 /* operand order: RA, RB, L */ 3405 l := int(c.regoff(&p.To)) 3406 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.From.Reg), uint32(p.Reg)) 3407 } 3408 } else if p.From3Type() == obj.TYPE_CONST { 3409 /* reg reg imm */ 3410 /* operand order: RB, L, RA */ 3411 l := int(c.regoff(p.GetFrom3())) 3412 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.To.Reg), uint32(p.From.Reg)) 3413 } else if p.To.Type == obj.TYPE_REG { 3414 cr := int32(p.To.Reg) 3415 if REG_CR0 <= cr && cr <= REG_CR7 { 3416 /* cr reg reg */ 3417 /* operand order: RA, RB, BF */ 3418 bf := (int(p.To.Reg) & 7) << 2 3419 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg)) 3420 } else if p.From.Type == obj.TYPE_CONST { 3421 /* reg imm */ 3422 /* operand order: L, RT */ 3423 l := int(c.regoff(&p.From)) 3424 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(l), uint32(p.Reg)) 3425 } else { 3426 switch p.As { 3427 case ACOPY, APASTECC: 3428 o1 = AOP_RRR(c.opirr(p.As), uint32(1), uint32(p.From.Reg), uint32(p.To.Reg)) 3429 default: 3430 /* reg reg reg */ 3431 /* operand order: RS, RB, RA */ 3432 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3433 } 3434 } 3435 } 3436 3437 case 93: /* X-form instructions, 2-operands */ 3438 if p.To.Type == obj.TYPE_CONST { 3439 /* imm reg */ 3440 /* operand order: FRB, BF */ 3441 bf := int(c.regoff(&p.To)) << 2 3442 o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg)) 3443 } else if p.Reg == 0 { 3444 /* popcnt* r,r, X-form */ 3445 /* operand order: RS, RA */ 3446 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3447 } 3448 3449 case 94: /* Z23-form instructions, 4-operands */ 3450 /* reg reg reg imm */ 3451 /* operand order: RA, RB, CY, RT */ 3452 cy := int(c.regoff(p.GetFrom3())) 3453 o1 = AOP_Z23I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(cy)) 3454 } 3455 3456 out[0] = o1 3457 out[1] = o2 3458 out[2] = o3 3459 out[3] = o4 3460 out[4] = o5 3461 return 3462 } 3463 3464 func (c *ctxt9) vregoff(a *obj.Addr) int64 { 3465 c.instoffset = 0 3466 if a != nil { 3467 c.aclass(a) 3468 } 3469 return c.instoffset 3470 } 3471 3472 func (c *ctxt9) regoff(a *obj.Addr) int32 { 3473 return int32(c.vregoff(a)) 3474 } 3475 3476 func (c *ctxt9) oprrr(a obj.As) uint32 { 3477 switch a { 3478 case AADD: 3479 return OPVCC(31, 266, 0, 0) 3480 case AADDCC: 3481 return OPVCC(31, 266, 0, 1) 3482 case AADDV: 3483 return OPVCC(31, 266, 1, 0) 3484 case AADDVCC: 3485 return OPVCC(31, 266, 1, 1) 3486 case AADDC: 3487 return OPVCC(31, 10, 0, 0) 3488 case AADDCCC: 3489 return OPVCC(31, 10, 0, 1) 3490 case AADDCV: 3491 return OPVCC(31, 10, 1, 0) 3492 case AADDCVCC: 3493 return OPVCC(31, 10, 1, 1) 3494 case AADDE: 3495 return OPVCC(31, 138, 0, 0) 3496 case AADDECC: 3497 return OPVCC(31, 138, 0, 1) 3498 case AADDEV: 3499 return OPVCC(31, 138, 1, 0) 3500 case AADDEVCC: 3501 return OPVCC(31, 138, 1, 1) 3502 case AADDME: 3503 return OPVCC(31, 234, 0, 0) 3504 case AADDMECC: 3505 return OPVCC(31, 234, 0, 1) 3506 case AADDMEV: 3507 return OPVCC(31, 234, 1, 0) 3508 case AADDMEVCC: 3509 return OPVCC(31, 234, 1, 1) 3510 case AADDZE: 3511 return OPVCC(31, 202, 0, 0) 3512 case AADDZECC: 3513 return OPVCC(31, 202, 0, 1) 3514 case AADDZEV: 3515 return OPVCC(31, 202, 1, 0) 3516 case AADDZEVCC: 3517 return OPVCC(31, 202, 1, 1) 3518 case AADDEX: 3519 return OPVCC(31, 170, 0, 0) /* addex - v3.0b */ 3520 3521 case AAND: 3522 return OPVCC(31, 28, 0, 0) 3523 case AANDCC: 3524 return OPVCC(31, 28, 0, 1) 3525 case AANDN: 3526 return OPVCC(31, 60, 0, 0) 3527 case AANDNCC: 3528 return OPVCC(31, 60, 0, 1) 3529 3530 case ACMP: 3531 return OPVCC(31, 0, 0, 0) | 1<<21 /* L=1 */ 3532 case ACMPU: 3533 return OPVCC(31, 32, 0, 0) | 1<<21 3534 case ACMPW: 3535 return OPVCC(31, 0, 0, 0) /* L=0 */ 3536 case ACMPWU: 3537 return OPVCC(31, 32, 0, 0) 3538 case ACMPB: 3539 return OPVCC(31, 508, 0, 0) /* cmpb - v2.05 */ 3540 3541 case ACNTLZW: 3542 return OPVCC(31, 26, 0, 0) 3543 case ACNTLZWCC: 3544 return OPVCC(31, 26, 0, 1) 3545 case ACNTLZD: 3546 return OPVCC(31, 58, 0, 0) 3547 case ACNTLZDCC: 3548 return OPVCC(31, 58, 0, 1) 3549 3550 case ACRAND: 3551 return OPVCC(19, 257, 0, 0) 3552 case ACRANDN: 3553 return OPVCC(19, 129, 0, 0) 3554 case ACREQV: 3555 return OPVCC(19, 289, 0, 0) 3556 case ACRNAND: 3557 return OPVCC(19, 225, 0, 0) 3558 case ACRNOR: 3559 return OPVCC(19, 33, 0, 0) 3560 case ACROR: 3561 return OPVCC(19, 449, 0, 0) 3562 case ACRORN: 3563 return OPVCC(19, 417, 0, 0) 3564 case ACRXOR: 3565 return OPVCC(19, 193, 0, 0) 3566 3567 case ADCBF: 3568 return OPVCC(31, 86, 0, 0) 3569 case ADCBI: 3570 return OPVCC(31, 470, 0, 0) 3571 case ADCBST: 3572 return OPVCC(31, 54, 0, 0) 3573 case ADCBT: 3574 return OPVCC(31, 278, 0, 0) 3575 case ADCBTST: 3576 return OPVCC(31, 246, 0, 0) 3577 case ADCBZ: 3578 return OPVCC(31, 1014, 0, 0) 3579 3580 case AREM, ADIVW: 3581 return OPVCC(31, 491, 0, 0) 3582 3583 case AREMCC, ADIVWCC: 3584 return OPVCC(31, 491, 0, 1) 3585 3586 case AREMV, ADIVWV: 3587 return OPVCC(31, 491, 1, 0) 3588 3589 case AREMVCC, ADIVWVCC: 3590 return OPVCC(31, 491, 1, 1) 3591 3592 case AREMU, ADIVWU: 3593 return OPVCC(31, 459, 0, 0) 3594 3595 case AREMUCC, ADIVWUCC: 3596 return OPVCC(31, 459, 0, 1) 3597 3598 case AREMUV, ADIVWUV: 3599 return OPVCC(31, 459, 1, 0) 3600 3601 case AREMUVCC, ADIVWUVCC: 3602 return OPVCC(31, 459, 1, 1) 3603 3604 case AREMD, ADIVD: 3605 return OPVCC(31, 489, 0, 0) 3606 3607 case AREMDCC, ADIVDCC: 3608 return OPVCC(31, 489, 0, 1) 3609 3610 case ADIVDE: 3611 return OPVCC(31, 425, 0, 0) 3612 3613 case ADIVDECC: 3614 return OPVCC(31, 425, 0, 1) 3615 3616 case ADIVDEU: 3617 return OPVCC(31, 393, 0, 0) 3618 3619 case ADIVDEUCC: 3620 return OPVCC(31, 393, 0, 1) 3621 3622 case AREMDV, ADIVDV: 3623 return OPVCC(31, 489, 1, 0) 3624 3625 case AREMDVCC, ADIVDVCC: 3626 return OPVCC(31, 489, 1, 1) 3627 3628 case AREMDU, ADIVDU: 3629 return OPVCC(31, 457, 0, 0) 3630 3631 case AREMDUCC, ADIVDUCC: 3632 return OPVCC(31, 457, 0, 1) 3633 3634 case AREMDUV, ADIVDUV: 3635 return OPVCC(31, 457, 1, 0) 3636 3637 case AREMDUVCC, ADIVDUVCC: 3638 return OPVCC(31, 457, 1, 1) 3639 3640 case AEIEIO: 3641 return OPVCC(31, 854, 0, 0) 3642 3643 case AEQV: 3644 return OPVCC(31, 284, 0, 0) 3645 case AEQVCC: 3646 return OPVCC(31, 284, 0, 1) 3647 3648 case AEXTSB: 3649 return OPVCC(31, 954, 0, 0) 3650 case AEXTSBCC: 3651 return OPVCC(31, 954, 0, 1) 3652 case AEXTSH: 3653 return OPVCC(31, 922, 0, 0) 3654 case AEXTSHCC: 3655 return OPVCC(31, 922, 0, 1) 3656 case AEXTSW: 3657 return OPVCC(31, 986, 0, 0) 3658 case AEXTSWCC: 3659 return OPVCC(31, 986, 0, 1) 3660 3661 case AFABS: 3662 return OPVCC(63, 264, 0, 0) 3663 case AFABSCC: 3664 return OPVCC(63, 264, 0, 1) 3665 case AFADD: 3666 return OPVCC(63, 21, 0, 0) 3667 case AFADDCC: 3668 return OPVCC(63, 21, 0, 1) 3669 case AFADDS: 3670 return OPVCC(59, 21, 0, 0) 3671 case AFADDSCC: 3672 return OPVCC(59, 21, 0, 1) 3673 case AFCMPO: 3674 return OPVCC(63, 32, 0, 0) 3675 case AFCMPU: 3676 return OPVCC(63, 0, 0, 0) 3677 case AFCFID: 3678 return OPVCC(63, 846, 0, 0) 3679 case AFCFIDCC: 3680 return OPVCC(63, 846, 0, 1) 3681 case AFCFIDU: 3682 return OPVCC(63, 974, 0, 0) 3683 case AFCFIDUCC: 3684 return OPVCC(63, 974, 0, 1) 3685 case AFCFIDS: 3686 return OPVCC(59, 846, 0, 0) 3687 case AFCFIDSCC: 3688 return OPVCC(59, 846, 0, 1) 3689 case AFCTIW: 3690 return OPVCC(63, 14, 0, 0) 3691 case AFCTIWCC: 3692 return OPVCC(63, 14, 0, 1) 3693 case AFCTIWZ: 3694 return OPVCC(63, 15, 0, 0) 3695 case AFCTIWZCC: 3696 return OPVCC(63, 15, 0, 1) 3697 case AFCTID: 3698 return OPVCC(63, 814, 0, 0) 3699 case AFCTIDCC: 3700 return OPVCC(63, 814, 0, 1) 3701 case AFCTIDZ: 3702 return OPVCC(63, 815, 0, 0) 3703 case AFCTIDZCC: 3704 return OPVCC(63, 815, 0, 1) 3705 case AFDIV: 3706 return OPVCC(63, 18, 0, 0) 3707 case AFDIVCC: 3708 return OPVCC(63, 18, 0, 1) 3709 case AFDIVS: 3710 return OPVCC(59, 18, 0, 0) 3711 case AFDIVSCC: 3712 return OPVCC(59, 18, 0, 1) 3713 case AFMADD: 3714 return OPVCC(63, 29, 0, 0) 3715 case AFMADDCC: 3716 return OPVCC(63, 29, 0, 1) 3717 case AFMADDS: 3718 return OPVCC(59, 29, 0, 0) 3719 case AFMADDSCC: 3720 return OPVCC(59, 29, 0, 1) 3721 3722 case AFMOVS, AFMOVD: 3723 return OPVCC(63, 72, 0, 0) /* load */ 3724 case AFMOVDCC: 3725 return OPVCC(63, 72, 0, 1) 3726 case AFMSUB: 3727 return OPVCC(63, 28, 0, 0) 3728 case AFMSUBCC: 3729 return OPVCC(63, 28, 0, 1) 3730 case AFMSUBS: 3731 return OPVCC(59, 28, 0, 0) 3732 case AFMSUBSCC: 3733 return OPVCC(59, 28, 0, 1) 3734 case AFMUL: 3735 return OPVCC(63, 25, 0, 0) 3736 case AFMULCC: 3737 return OPVCC(63, 25, 0, 1) 3738 case AFMULS: 3739 return OPVCC(59, 25, 0, 0) 3740 case AFMULSCC: 3741 return OPVCC(59, 25, 0, 1) 3742 case AFNABS: 3743 return OPVCC(63, 136, 0, 0) 3744 case AFNABSCC: 3745 return OPVCC(63, 136, 0, 1) 3746 case AFNEG: 3747 return OPVCC(63, 40, 0, 0) 3748 case AFNEGCC: 3749 return OPVCC(63, 40, 0, 1) 3750 case AFNMADD: 3751 return OPVCC(63, 31, 0, 0) 3752 case AFNMADDCC: 3753 return OPVCC(63, 31, 0, 1) 3754 case AFNMADDS: 3755 return OPVCC(59, 31, 0, 0) 3756 case AFNMADDSCC: 3757 return OPVCC(59, 31, 0, 1) 3758 case AFNMSUB: 3759 return OPVCC(63, 30, 0, 0) 3760 case AFNMSUBCC: 3761 return OPVCC(63, 30, 0, 1) 3762 case AFNMSUBS: 3763 return OPVCC(59, 30, 0, 0) 3764 case AFNMSUBSCC: 3765 return OPVCC(59, 30, 0, 1) 3766 case AFCPSGN: 3767 return OPVCC(63, 8, 0, 0) 3768 case AFCPSGNCC: 3769 return OPVCC(63, 8, 0, 1) 3770 case AFRES: 3771 return OPVCC(59, 24, 0, 0) 3772 case AFRESCC: 3773 return OPVCC(59, 24, 0, 1) 3774 case AFRIM: 3775 return OPVCC(63, 488, 0, 0) 3776 case AFRIMCC: 3777 return OPVCC(63, 488, 0, 1) 3778 case AFRIP: 3779 return OPVCC(63, 456, 0, 0) 3780 case AFRIPCC: 3781 return OPVCC(63, 456, 0, 1) 3782 case AFRIZ: 3783 return OPVCC(63, 424, 0, 0) 3784 case AFRIZCC: 3785 return OPVCC(63, 424, 0, 1) 3786 case AFRSP: 3787 return OPVCC(63, 12, 0, 0) 3788 case AFRSPCC: 3789 return OPVCC(63, 12, 0, 1) 3790 case AFRSQRTE: 3791 return OPVCC(63, 26, 0, 0) 3792 case AFRSQRTECC: 3793 return OPVCC(63, 26, 0, 1) 3794 case AFSEL: 3795 return OPVCC(63, 23, 0, 0) 3796 case AFSELCC: 3797 return OPVCC(63, 23, 0, 1) 3798 case AFSQRT: 3799 return OPVCC(63, 22, 0, 0) 3800 case AFSQRTCC: 3801 return OPVCC(63, 22, 0, 1) 3802 case AFSQRTS: 3803 return OPVCC(59, 22, 0, 0) 3804 case AFSQRTSCC: 3805 return OPVCC(59, 22, 0, 1) 3806 case AFSUB: 3807 return OPVCC(63, 20, 0, 0) 3808 case AFSUBCC: 3809 return OPVCC(63, 20, 0, 1) 3810 case AFSUBS: 3811 return OPVCC(59, 20, 0, 0) 3812 case AFSUBSCC: 3813 return OPVCC(59, 20, 0, 1) 3814 3815 case AICBI: 3816 return OPVCC(31, 982, 0, 0) 3817 case AISYNC: 3818 return OPVCC(19, 150, 0, 0) 3819 3820 case AMTFSB0: 3821 return OPVCC(63, 70, 0, 0) 3822 case AMTFSB0CC: 3823 return OPVCC(63, 70, 0, 1) 3824 case AMTFSB1: 3825 return OPVCC(63, 38, 0, 0) 3826 case AMTFSB1CC: 3827 return OPVCC(63, 38, 0, 1) 3828 3829 case AMULHW: 3830 return OPVCC(31, 75, 0, 0) 3831 case AMULHWCC: 3832 return OPVCC(31, 75, 0, 1) 3833 case AMULHWU: 3834 return OPVCC(31, 11, 0, 0) 3835 case AMULHWUCC: 3836 return OPVCC(31, 11, 0, 1) 3837 case AMULLW: 3838 return OPVCC(31, 235, 0, 0) 3839 case AMULLWCC: 3840 return OPVCC(31, 235, 0, 1) 3841 case AMULLWV: 3842 return OPVCC(31, 235, 1, 0) 3843 case AMULLWVCC: 3844 return OPVCC(31, 235, 1, 1) 3845 3846 case AMULHD: 3847 return OPVCC(31, 73, 0, 0) 3848 case AMULHDCC: 3849 return OPVCC(31, 73, 0, 1) 3850 case AMULHDU: 3851 return OPVCC(31, 9, 0, 0) 3852 case AMULHDUCC: 3853 return OPVCC(31, 9, 0, 1) 3854 case AMULLD: 3855 return OPVCC(31, 233, 0, 0) 3856 case AMULLDCC: 3857 return OPVCC(31, 233, 0, 1) 3858 case AMULLDV: 3859 return OPVCC(31, 233, 1, 0) 3860 case AMULLDVCC: 3861 return OPVCC(31, 233, 1, 1) 3862 3863 case ANAND: 3864 return OPVCC(31, 476, 0, 0) 3865 case ANANDCC: 3866 return OPVCC(31, 476, 0, 1) 3867 case ANEG: 3868 return OPVCC(31, 104, 0, 0) 3869 case ANEGCC: 3870 return OPVCC(31, 104, 0, 1) 3871 case ANEGV: 3872 return OPVCC(31, 104, 1, 0) 3873 case ANEGVCC: 3874 return OPVCC(31, 104, 1, 1) 3875 case ANOR: 3876 return OPVCC(31, 124, 0, 0) 3877 case ANORCC: 3878 return OPVCC(31, 124, 0, 1) 3879 case AOR: 3880 return OPVCC(31, 444, 0, 0) 3881 case AORCC: 3882 return OPVCC(31, 444, 0, 1) 3883 case AORN: 3884 return OPVCC(31, 412, 0, 0) 3885 case AORNCC: 3886 return OPVCC(31, 412, 0, 1) 3887 3888 case APOPCNTD: 3889 return OPVCC(31, 506, 0, 0) /* popcntd - v2.06 */ 3890 case APOPCNTW: 3891 return OPVCC(31, 378, 0, 0) /* popcntw - v2.06 */ 3892 case APOPCNTB: 3893 return OPVCC(31, 122, 0, 0) /* popcntb - v2.02 */ 3894 3895 case ARFI: 3896 return OPVCC(19, 50, 0, 0) 3897 case ARFCI: 3898 return OPVCC(19, 51, 0, 0) 3899 case ARFID: 3900 return OPVCC(19, 18, 0, 0) 3901 case AHRFID: 3902 return OPVCC(19, 274, 0, 0) 3903 3904 case ARLWMI: 3905 return OPVCC(20, 0, 0, 0) 3906 case ARLWMICC: 3907 return OPVCC(20, 0, 0, 1) 3908 case ARLWNM: 3909 return OPVCC(23, 0, 0, 0) 3910 case ARLWNMCC: 3911 return OPVCC(23, 0, 0, 1) 3912 3913 case ARLDCL: 3914 return OPVCC(30, 8, 0, 0) 3915 case ARLDCR: 3916 return OPVCC(30, 9, 0, 0) 3917 3918 case ARLDICL: 3919 return OPVCC(30, 0, 0, 0) 3920 case ARLDICLCC: 3921 return OPVCC(30, 0, 0, 1) 3922 case ARLDICR: 3923 return OPVCC(30, 0, 0, 0) | 2<<1 // rldicr 3924 case ARLDICRCC: 3925 return OPVCC(30, 0, 0, 1) | 2<<1 // rldicr. 3926 3927 case ASYSCALL: 3928 return OPVCC(17, 1, 0, 0) 3929 3930 case ASLW: 3931 return OPVCC(31, 24, 0, 0) 3932 case ASLWCC: 3933 return OPVCC(31, 24, 0, 1) 3934 case ASLD: 3935 return OPVCC(31, 27, 0, 0) 3936 case ASLDCC: 3937 return OPVCC(31, 27, 0, 1) 3938 3939 case ASRAW: 3940 return OPVCC(31, 792, 0, 0) 3941 case ASRAWCC: 3942 return OPVCC(31, 792, 0, 1) 3943 case ASRAD: 3944 return OPVCC(31, 794, 0, 0) 3945 case ASRADCC: 3946 return OPVCC(31, 794, 0, 1) 3947 3948 case ASRW: 3949 return OPVCC(31, 536, 0, 0) 3950 case ASRWCC: 3951 return OPVCC(31, 536, 0, 1) 3952 case ASRD: 3953 return OPVCC(31, 539, 0, 0) 3954 case ASRDCC: 3955 return OPVCC(31, 539, 0, 1) 3956 3957 case ASUB: 3958 return OPVCC(31, 40, 0, 0) 3959 case ASUBCC: 3960 return OPVCC(31, 40, 0, 1) 3961 case ASUBV: 3962 return OPVCC(31, 40, 1, 0) 3963 case ASUBVCC: 3964 return OPVCC(31, 40, 1, 1) 3965 case ASUBC: 3966 return OPVCC(31, 8, 0, 0) 3967 case ASUBCCC: 3968 return OPVCC(31, 8, 0, 1) 3969 case ASUBCV: 3970 return OPVCC(31, 8, 1, 0) 3971 case ASUBCVCC: 3972 return OPVCC(31, 8, 1, 1) 3973 case ASUBE: 3974 return OPVCC(31, 136, 0, 0) 3975 case ASUBECC: 3976 return OPVCC(31, 136, 0, 1) 3977 case ASUBEV: 3978 return OPVCC(31, 136, 1, 0) 3979 case ASUBEVCC: 3980 return OPVCC(31, 136, 1, 1) 3981 case ASUBME: 3982 return OPVCC(31, 232, 0, 0) 3983 case ASUBMECC: 3984 return OPVCC(31, 232, 0, 1) 3985 case ASUBMEV: 3986 return OPVCC(31, 232, 1, 0) 3987 case ASUBMEVCC: 3988 return OPVCC(31, 232, 1, 1) 3989 case ASUBZE: 3990 return OPVCC(31, 200, 0, 0) 3991 case ASUBZECC: 3992 return OPVCC(31, 200, 0, 1) 3993 case ASUBZEV: 3994 return OPVCC(31, 200, 1, 0) 3995 case ASUBZEVCC: 3996 return OPVCC(31, 200, 1, 1) 3997 3998 case ASYNC: 3999 return OPVCC(31, 598, 0, 0) 4000 case ALWSYNC: 4001 return OPVCC(31, 598, 0, 0) | 1<<21 4002 4003 case APTESYNC: 4004 return OPVCC(31, 598, 0, 0) | 2<<21 4005 4006 case ATLBIE: 4007 return OPVCC(31, 306, 0, 0) 4008 case ATLBIEL: 4009 return OPVCC(31, 274, 0, 0) 4010 case ATLBSYNC: 4011 return OPVCC(31, 566, 0, 0) 4012 case ASLBIA: 4013 return OPVCC(31, 498, 0, 0) 4014 case ASLBIE: 4015 return OPVCC(31, 434, 0, 0) 4016 case ASLBMFEE: 4017 return OPVCC(31, 915, 0, 0) 4018 case ASLBMFEV: 4019 return OPVCC(31, 851, 0, 0) 4020 case ASLBMTE: 4021 return OPVCC(31, 402, 0, 0) 4022 4023 case ATW: 4024 return OPVCC(31, 4, 0, 0) 4025 case ATD: 4026 return OPVCC(31, 68, 0, 0) 4027 4028 /* Vector (VMX/Altivec) instructions */ 4029 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4030 /* are enabled starting at POWER6 (ISA 2.05). */ 4031 case AVAND: 4032 return OPVX(4, 1028, 0, 0) /* vand - v2.03 */ 4033 case AVANDC: 4034 return OPVX(4, 1092, 0, 0) /* vandc - v2.03 */ 4035 case AVNAND: 4036 return OPVX(4, 1412, 0, 0) /* vnand - v2.07 */ 4037 4038 case AVOR: 4039 return OPVX(4, 1156, 0, 0) /* vor - v2.03 */ 4040 case AVORC: 4041 return OPVX(4, 1348, 0, 0) /* vorc - v2.07 */ 4042 case AVNOR: 4043 return OPVX(4, 1284, 0, 0) /* vnor - v2.03 */ 4044 case AVXOR: 4045 return OPVX(4, 1220, 0, 0) /* vxor - v2.03 */ 4046 case AVEQV: 4047 return OPVX(4, 1668, 0, 0) /* veqv - v2.07 */ 4048 4049 case AVADDUBM: 4050 return OPVX(4, 0, 0, 0) /* vaddubm - v2.03 */ 4051 case AVADDUHM: 4052 return OPVX(4, 64, 0, 0) /* vadduhm - v2.03 */ 4053 case AVADDUWM: 4054 return OPVX(4, 128, 0, 0) /* vadduwm - v2.03 */ 4055 case AVADDUDM: 4056 return OPVX(4, 192, 0, 0) /* vaddudm - v2.07 */ 4057 case AVADDUQM: 4058 return OPVX(4, 256, 0, 0) /* vadduqm - v2.07 */ 4059 4060 case AVADDCUQ: 4061 return OPVX(4, 320, 0, 0) /* vaddcuq - v2.07 */ 4062 case AVADDCUW: 4063 return OPVX(4, 384, 0, 0) /* vaddcuw - v2.03 */ 4064 4065 case AVADDUBS: 4066 return OPVX(4, 512, 0, 0) /* vaddubs - v2.03 */ 4067 case AVADDUHS: 4068 return OPVX(4, 576, 0, 0) /* vadduhs - v2.03 */ 4069 case AVADDUWS: 4070 return OPVX(4, 640, 0, 0) /* vadduws - v2.03 */ 4071 4072 case AVADDSBS: 4073 return OPVX(4, 768, 0, 0) /* vaddsbs - v2.03 */ 4074 case AVADDSHS: 4075 return OPVX(4, 832, 0, 0) /* vaddshs - v2.03 */ 4076 case AVADDSWS: 4077 return OPVX(4, 896, 0, 0) /* vaddsws - v2.03 */ 4078 4079 case AVADDEUQM: 4080 return OPVX(4, 60, 0, 0) /* vaddeuqm - v2.07 */ 4081 case AVADDECUQ: 4082 return OPVX(4, 61, 0, 0) /* vaddecuq - v2.07 */ 4083 4084 case AVPMSUMB: 4085 return OPVX(4, 1032, 0, 0) /* vpmsumb - v2.07 */ 4086 case AVPMSUMH: 4087 return OPVX(4, 1096, 0, 0) /* vpmsumh - v2.07 */ 4088 case AVPMSUMW: 4089 return OPVX(4, 1160, 0, 0) /* vpmsumw - v2.07 */ 4090 case AVPMSUMD: 4091 return OPVX(4, 1224, 0, 0) /* vpmsumd - v2.07 */ 4092 4093 case AVMSUMUDM: 4094 return OPVX(4, 35, 0, 0) /* vmsumudm - v3.00b */ 4095 4096 case AVSUBUBM: 4097 return OPVX(4, 1024, 0, 0) /* vsububm - v2.03 */ 4098 case AVSUBUHM: 4099 return OPVX(4, 1088, 0, 0) /* vsubuhm - v2.03 */ 4100 case AVSUBUWM: 4101 return OPVX(4, 1152, 0, 0) /* vsubuwm - v2.03 */ 4102 case AVSUBUDM: 4103 return OPVX(4, 1216, 0, 0) /* vsubudm - v2.07 */ 4104 case AVSUBUQM: 4105 return OPVX(4, 1280, 0, 0) /* vsubuqm - v2.07 */ 4106 4107 case AVSUBCUQ: 4108 return OPVX(4, 1344, 0, 0) /* vsubcuq - v2.07 */ 4109 case AVSUBCUW: 4110 return OPVX(4, 1408, 0, 0) /* vsubcuw - v2.03 */ 4111 4112 case AVSUBUBS: 4113 return OPVX(4, 1536, 0, 0) /* vsububs - v2.03 */ 4114 case AVSUBUHS: 4115 return OPVX(4, 1600, 0, 0) /* vsubuhs - v2.03 */ 4116 case AVSUBUWS: 4117 return OPVX(4, 1664, 0, 0) /* vsubuws - v2.03 */ 4118 4119 case AVSUBSBS: 4120 return OPVX(4, 1792, 0, 0) /* vsubsbs - v2.03 */ 4121 case AVSUBSHS: 4122 return OPVX(4, 1856, 0, 0) /* vsubshs - v2.03 */ 4123 case AVSUBSWS: 4124 return OPVX(4, 1920, 0, 0) /* vsubsws - v2.03 */ 4125 4126 case AVSUBEUQM: 4127 return OPVX(4, 62, 0, 0) /* vsubeuqm - v2.07 */ 4128 case AVSUBECUQ: 4129 return OPVX(4, 63, 0, 0) /* vsubecuq - v2.07 */ 4130 4131 case AVRLB: 4132 return OPVX(4, 4, 0, 0) /* vrlb - v2.03 */ 4133 case AVRLH: 4134 return OPVX(4, 68, 0, 0) /* vrlh - v2.03 */ 4135 case AVRLW: 4136 return OPVX(4, 132, 0, 0) /* vrlw - v2.03 */ 4137 case AVRLD: 4138 return OPVX(4, 196, 0, 0) /* vrld - v2.07 */ 4139 4140 case AVSLB: 4141 return OPVX(4, 260, 0, 0) /* vslh - v2.03 */ 4142 case AVSLH: 4143 return OPVX(4, 324, 0, 0) /* vslh - v2.03 */ 4144 case AVSLW: 4145 return OPVX(4, 388, 0, 0) /* vslw - v2.03 */ 4146 case AVSL: 4147 return OPVX(4, 452, 0, 0) /* vsl - v2.03 */ 4148 case AVSLO: 4149 return OPVX(4, 1036, 0, 0) /* vsl - v2.03 */ 4150 case AVSRB: 4151 return OPVX(4, 516, 0, 0) /* vsrb - v2.03 */ 4152 case AVSRH: 4153 return OPVX(4, 580, 0, 0) /* vsrh - v2.03 */ 4154 case AVSRW: 4155 return OPVX(4, 644, 0, 0) /* vsrw - v2.03 */ 4156 case AVSR: 4157 return OPVX(4, 708, 0, 0) /* vsr - v2.03 */ 4158 case AVSRO: 4159 return OPVX(4, 1100, 0, 0) /* vsro - v2.03 */ 4160 case AVSLD: 4161 return OPVX(4, 1476, 0, 0) /* vsld - v2.07 */ 4162 case AVSRD: 4163 return OPVX(4, 1732, 0, 0) /* vsrd - v2.07 */ 4164 4165 case AVSRAB: 4166 return OPVX(4, 772, 0, 0) /* vsrab - v2.03 */ 4167 case AVSRAH: 4168 return OPVX(4, 836, 0, 0) /* vsrah - v2.03 */ 4169 case AVSRAW: 4170 return OPVX(4, 900, 0, 0) /* vsraw - v2.03 */ 4171 case AVSRAD: 4172 return OPVX(4, 964, 0, 0) /* vsrad - v2.07 */ 4173 4174 case AVBPERMQ: 4175 return OPVC(4, 1356, 0, 0) /* vbpermq - v2.07 */ 4176 case AVBPERMD: 4177 return OPVC(4, 1484, 0, 0) /* vbpermd - v3.00 */ 4178 4179 case AVCLZB: 4180 return OPVX(4, 1794, 0, 0) /* vclzb - v2.07 */ 4181 case AVCLZH: 4182 return OPVX(4, 1858, 0, 0) /* vclzh - v2.07 */ 4183 case AVCLZW: 4184 return OPVX(4, 1922, 0, 0) /* vclzw - v2.07 */ 4185 case AVCLZD: 4186 return OPVX(4, 1986, 0, 0) /* vclzd - v2.07 */ 4187 4188 case AVPOPCNTB: 4189 return OPVX(4, 1795, 0, 0) /* vpopcntb - v2.07 */ 4190 case AVPOPCNTH: 4191 return OPVX(4, 1859, 0, 0) /* vpopcnth - v2.07 */ 4192 case AVPOPCNTW: 4193 return OPVX(4, 1923, 0, 0) /* vpopcntw - v2.07 */ 4194 case AVPOPCNTD: 4195 return OPVX(4, 1987, 0, 0) /* vpopcntd - v2.07 */ 4196 4197 case AVCMPEQUB: 4198 return OPVC(4, 6, 0, 0) /* vcmpequb - v2.03 */ 4199 case AVCMPEQUBCC: 4200 return OPVC(4, 6, 0, 1) /* vcmpequb. - v2.03 */ 4201 case AVCMPEQUH: 4202 return OPVC(4, 70, 0, 0) /* vcmpequh - v2.03 */ 4203 case AVCMPEQUHCC: 4204 return OPVC(4, 70, 0, 1) /* vcmpequh. - v2.03 */ 4205 case AVCMPEQUW: 4206 return OPVC(4, 134, 0, 0) /* vcmpequw - v2.03 */ 4207 case AVCMPEQUWCC: 4208 return OPVC(4, 134, 0, 1) /* vcmpequw. - v2.03 */ 4209 case AVCMPEQUD: 4210 return OPVC(4, 199, 0, 0) /* vcmpequd - v2.07 */ 4211 case AVCMPEQUDCC: 4212 return OPVC(4, 199, 0, 1) /* vcmpequd. - v2.07 */ 4213 4214 case AVCMPGTUB: 4215 return OPVC(4, 518, 0, 0) /* vcmpgtub - v2.03 */ 4216 case AVCMPGTUBCC: 4217 return OPVC(4, 518, 0, 1) /* vcmpgtub. - v2.03 */ 4218 case AVCMPGTUH: 4219 return OPVC(4, 582, 0, 0) /* vcmpgtuh - v2.03 */ 4220 case AVCMPGTUHCC: 4221 return OPVC(4, 582, 0, 1) /* vcmpgtuh. - v2.03 */ 4222 case AVCMPGTUW: 4223 return OPVC(4, 646, 0, 0) /* vcmpgtuw - v2.03 */ 4224 case AVCMPGTUWCC: 4225 return OPVC(4, 646, 0, 1) /* vcmpgtuw. - v2.03 */ 4226 case AVCMPGTUD: 4227 return OPVC(4, 711, 0, 0) /* vcmpgtud - v2.07 */ 4228 case AVCMPGTUDCC: 4229 return OPVC(4, 711, 0, 1) /* vcmpgtud. v2.07 */ 4230 case AVCMPGTSB: 4231 return OPVC(4, 774, 0, 0) /* vcmpgtsb - v2.03 */ 4232 case AVCMPGTSBCC: 4233 return OPVC(4, 774, 0, 1) /* vcmpgtsb. - v2.03 */ 4234 case AVCMPGTSH: 4235 return OPVC(4, 838, 0, 0) /* vcmpgtsh - v2.03 */ 4236 case AVCMPGTSHCC: 4237 return OPVC(4, 838, 0, 1) /* vcmpgtsh. - v2.03 */ 4238 case AVCMPGTSW: 4239 return OPVC(4, 902, 0, 0) /* vcmpgtsw - v2.03 */ 4240 case AVCMPGTSWCC: 4241 return OPVC(4, 902, 0, 1) /* vcmpgtsw. - v2.03 */ 4242 case AVCMPGTSD: 4243 return OPVC(4, 967, 0, 0) /* vcmpgtsd - v2.07 */ 4244 case AVCMPGTSDCC: 4245 return OPVC(4, 967, 0, 1) /* vcmpgtsd. - v2.07 */ 4246 4247 case AVCMPNEZB: 4248 return OPVC(4, 263, 0, 0) /* vcmpnezb - v3.00 */ 4249 case AVCMPNEZBCC: 4250 return OPVC(4, 263, 0, 1) /* vcmpnezb. - v3.00 */ 4251 4252 case AVPERM: 4253 return OPVX(4, 43, 0, 0) /* vperm - v2.03 */ 4254 4255 case AVSEL: 4256 return OPVX(4, 42, 0, 0) /* vsel - v2.03 */ 4257 4258 case AVCIPHER: 4259 return OPVX(4, 1288, 0, 0) /* vcipher - v2.07 */ 4260 case AVCIPHERLAST: 4261 return OPVX(4, 1289, 0, 0) /* vcipherlast - v2.07 */ 4262 case AVNCIPHER: 4263 return OPVX(4, 1352, 0, 0) /* vncipher - v2.07 */ 4264 case AVNCIPHERLAST: 4265 return OPVX(4, 1353, 0, 0) /* vncipherlast - v2.07 */ 4266 case AVSBOX: 4267 return OPVX(4, 1480, 0, 0) /* vsbox - v2.07 */ 4268 /* End of vector instructions */ 4269 4270 /* Vector scalar (VSX) instructions */ 4271 /* ISA 2.06 enables these for POWER7. */ 4272 case AMFVSRD, AMFVRD, AMFFPRD: 4273 return OPVXX1(31, 51, 0) /* mfvsrd - v2.07 */ 4274 case AMFVSRWZ: 4275 return OPVXX1(31, 115, 0) /* mfvsrwz - v2.07 */ 4276 case AMFVSRLD: 4277 return OPVXX1(31, 307, 0) /* mfvsrld - v3.00 */ 4278 4279 case AMTVSRD, AMTFPRD, AMTVRD: 4280 return OPVXX1(31, 179, 0) /* mtvsrd - v2.07 */ 4281 case AMTVSRWA: 4282 return OPVXX1(31, 211, 0) /* mtvsrwa - v2.07 */ 4283 case AMTVSRWZ: 4284 return OPVXX1(31, 243, 0) /* mtvsrwz - v2.07 */ 4285 case AMTVSRDD: 4286 return OPVXX1(31, 435, 0) /* mtvsrdd - v3.00 */ 4287 case AMTVSRWS: 4288 return OPVXX1(31, 403, 0) /* mtvsrws - v3.00 */ 4289 4290 case AXXLANDQ: 4291 return OPVXX3(60, 130, 0) /* xxland - v2.06 */ 4292 case AXXLANDC: 4293 return OPVXX3(60, 138, 0) /* xxlandc - v2.06 */ 4294 case AXXLEQV: 4295 return OPVXX3(60, 186, 0) /* xxleqv - v2.07 */ 4296 case AXXLNAND: 4297 return OPVXX3(60, 178, 0) /* xxlnand - v2.07 */ 4298 4299 case AXXLORC: 4300 return OPVXX3(60, 170, 0) /* xxlorc - v2.07 */ 4301 case AXXLNOR: 4302 return OPVXX3(60, 162, 0) /* xxlnor - v2.06 */ 4303 case AXXLORQ: 4304 return OPVXX3(60, 146, 0) /* xxlor - v2.06 */ 4305 case AXXLXOR: 4306 return OPVXX3(60, 154, 0) /* xxlxor - v2.06 */ 4307 4308 case AXXSEL: 4309 return OPVXX4(60, 3, 0) /* xxsel - v2.06 */ 4310 4311 case AXXMRGHW: 4312 return OPVXX3(60, 18, 0) /* xxmrghw - v2.06 */ 4313 case AXXMRGLW: 4314 return OPVXX3(60, 50, 0) /* xxmrglw - v2.06 */ 4315 4316 case AXXSPLTW: 4317 return OPVXX2(60, 164, 0) /* xxspltw - v2.06 */ 4318 4319 case AXXPERMDI: 4320 return OPVXX3(60, 10, 0) /* xxpermdi - v2.06 */ 4321 4322 case AXXSLDWI: 4323 return OPVXX3(60, 2, 0) /* xxsldwi - v2.06 */ 4324 4325 case AXSCVDPSP: 4326 return OPVXX2(60, 265, 0) /* xscvdpsp - v2.06 */ 4327 case AXSCVSPDP: 4328 return OPVXX2(60, 329, 0) /* xscvspdp - v2.06 */ 4329 case AXSCVDPSPN: 4330 return OPVXX2(60, 267, 0) /* xscvdpspn - v2.07 */ 4331 case AXSCVSPDPN: 4332 return OPVXX2(60, 331, 0) /* xscvspdpn - v2.07 */ 4333 4334 case AXVCVDPSP: 4335 return OPVXX2(60, 393, 0) /* xvcvdpsp - v2.06 */ 4336 case AXVCVSPDP: 4337 return OPVXX2(60, 457, 0) /* xvcvspdp - v2.06 */ 4338 4339 case AXSCVDPSXDS: 4340 return OPVXX2(60, 344, 0) /* xscvdpsxds - v2.06 */ 4341 case AXSCVDPSXWS: 4342 return OPVXX2(60, 88, 0) /* xscvdpsxws - v2.06 */ 4343 case AXSCVDPUXDS: 4344 return OPVXX2(60, 328, 0) /* xscvdpuxds - v2.06 */ 4345 case AXSCVDPUXWS: 4346 return OPVXX2(60, 72, 0) /* xscvdpuxws - v2.06 */ 4347 4348 case AXSCVSXDDP: 4349 return OPVXX2(60, 376, 0) /* xscvsxddp - v2.06 */ 4350 case AXSCVUXDDP: 4351 return OPVXX2(60, 360, 0) /* xscvuxddp - v2.06 */ 4352 case AXSCVSXDSP: 4353 return OPVXX2(60, 312, 0) /* xscvsxdsp - v2.06 */ 4354 case AXSCVUXDSP: 4355 return OPVXX2(60, 296, 0) /* xscvuxdsp - v2.06 */ 4356 4357 case AXVCVDPSXDS: 4358 return OPVXX2(60, 472, 0) /* xvcvdpsxds - v2.06 */ 4359 case AXVCVDPSXWS: 4360 return OPVXX2(60, 216, 0) /* xvcvdpsxws - v2.06 */ 4361 case AXVCVDPUXDS: 4362 return OPVXX2(60, 456, 0) /* xvcvdpuxds - v2.06 */ 4363 case AXVCVDPUXWS: 4364 return OPVXX2(60, 200, 0) /* xvcvdpuxws - v2.06 */ 4365 case AXVCVSPSXDS: 4366 return OPVXX2(60, 408, 0) /* xvcvspsxds - v2.07 */ 4367 case AXVCVSPSXWS: 4368 return OPVXX2(60, 152, 0) /* xvcvspsxws - v2.07 */ 4369 case AXVCVSPUXDS: 4370 return OPVXX2(60, 392, 0) /* xvcvspuxds - v2.07 */ 4371 case AXVCVSPUXWS: 4372 return OPVXX2(60, 136, 0) /* xvcvspuxws - v2.07 */ 4373 4374 case AXVCVSXDDP: 4375 return OPVXX2(60, 504, 0) /* xvcvsxddp - v2.06 */ 4376 case AXVCVSXWDP: 4377 return OPVXX2(60, 248, 0) /* xvcvsxwdp - v2.06 */ 4378 case AXVCVUXDDP: 4379 return OPVXX2(60, 488, 0) /* xvcvuxddp - v2.06 */ 4380 case AXVCVUXWDP: 4381 return OPVXX2(60, 232, 0) /* xvcvuxwdp - v2.06 */ 4382 case AXVCVSXDSP: 4383 return OPVXX2(60, 440, 0) /* xvcvsxdsp - v2.06 */ 4384 case AXVCVSXWSP: 4385 return OPVXX2(60, 184, 0) /* xvcvsxwsp - v2.06 */ 4386 case AXVCVUXDSP: 4387 return OPVXX2(60, 424, 0) /* xvcvuxdsp - v2.06 */ 4388 case AXVCVUXWSP: 4389 return OPVXX2(60, 168, 0) /* xvcvuxwsp - v2.06 */ 4390 /* End of VSX instructions */ 4391 4392 case AMADDHD: 4393 return OPVX(4, 48, 0, 0) /* maddhd - v3.00 */ 4394 case AMADDHDU: 4395 return OPVX(4, 49, 0, 0) /* maddhdu - v3.00 */ 4396 case AMADDLD: 4397 return OPVX(4, 51, 0, 0) /* maddld - v3.00 */ 4398 4399 case AXOR: 4400 return OPVCC(31, 316, 0, 0) 4401 case AXORCC: 4402 return OPVCC(31, 316, 0, 1) 4403 } 4404 4405 c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a) 4406 return 0 4407 } 4408 4409 func (c *ctxt9) opirrr(a obj.As) uint32 { 4410 switch a { 4411 /* Vector (VMX/Altivec) instructions */ 4412 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4413 /* are enabled starting at POWER6 (ISA 2.05). */ 4414 case AVSLDOI: 4415 return OPVX(4, 44, 0, 0) /* vsldoi - v2.03 */ 4416 } 4417 4418 c.ctxt.Diag("bad i/r/r/r opcode %v", a) 4419 return 0 4420 } 4421 4422 func (c *ctxt9) opiirr(a obj.As) uint32 { 4423 switch a { 4424 /* Vector (VMX/Altivec) instructions */ 4425 /* ISA 2.07 enables these for POWER8 and beyond. */ 4426 case AVSHASIGMAW: 4427 return OPVX(4, 1666, 0, 0) /* vshasigmaw - v2.07 */ 4428 case AVSHASIGMAD: 4429 return OPVX(4, 1730, 0, 0) /* vshasigmad - v2.07 */ 4430 } 4431 4432 c.ctxt.Diag("bad i/i/r/r opcode %v", a) 4433 return 0 4434 } 4435 4436 func (c *ctxt9) opirr(a obj.As) uint32 { 4437 switch a { 4438 case AADD: 4439 return OPVCC(14, 0, 0, 0) 4440 case AADDC: 4441 return OPVCC(12, 0, 0, 0) 4442 case AADDCCC: 4443 return OPVCC(13, 0, 0, 0) 4444 case -AADD: 4445 return OPVCC(15, 0, 0, 0) /* ADDIS/CAU */ 4446 4447 case AANDCC: 4448 return OPVCC(28, 0, 0, 0) 4449 case -AANDCC: 4450 return OPVCC(29, 0, 0, 0) /* ANDIS./ANDIU. */ 4451 4452 case ABR: 4453 return OPVCC(18, 0, 0, 0) 4454 case ABL: 4455 return OPVCC(18, 0, 0, 0) | 1 4456 case obj.ADUFFZERO: 4457 return OPVCC(18, 0, 0, 0) | 1 4458 case obj.ADUFFCOPY: 4459 return OPVCC(18, 0, 0, 0) | 1 4460 case ABC: 4461 return OPVCC(16, 0, 0, 0) 4462 case ABCL: 4463 return OPVCC(16, 0, 0, 0) | 1 4464 4465 case ABEQ: 4466 return AOP_RRR(16<<26, 12, 2, 0) 4467 case ABGE: 4468 return AOP_RRR(16<<26, 4, 0, 0) 4469 case ABGT: 4470 return AOP_RRR(16<<26, 12, 1, 0) 4471 case ABLE: 4472 return AOP_RRR(16<<26, 4, 1, 0) 4473 case ABLT: 4474 return AOP_RRR(16<<26, 12, 0, 0) 4475 case ABNE: 4476 return AOP_RRR(16<<26, 4, 2, 0) 4477 case ABVC: 4478 return AOP_RRR(16<<26, 4, 3, 0) // apparently unordered-clear 4479 case ABVS: 4480 return AOP_RRR(16<<26, 12, 3, 0) // apparently unordered-set 4481 4482 case ACMP: 4483 return OPVCC(11, 0, 0, 0) | 1<<21 /* L=1 */ 4484 case ACMPU: 4485 return OPVCC(10, 0, 0, 0) | 1<<21 4486 case ACMPW: 4487 return OPVCC(11, 0, 0, 0) /* L=0 */ 4488 case ACMPWU: 4489 return OPVCC(10, 0, 0, 0) 4490 case ACMPEQB: 4491 return OPVCC(31, 224, 0, 0) /* cmpeqb - v3.00 */ 4492 4493 case ALSW: 4494 return OPVCC(31, 597, 0, 0) 4495 4496 case ACOPY: 4497 return OPVCC(31, 774, 0, 0) /* copy - v3.00 */ 4498 case APASTECC: 4499 return OPVCC(31, 902, 0, 1) /* paste. - v3.00 */ 4500 case ADARN: 4501 return OPVCC(31, 755, 0, 0) /* darn - v3.00 */ 4502 4503 case AMULLW: 4504 return OPVCC(7, 0, 0, 0) 4505 4506 case AOR: 4507 return OPVCC(24, 0, 0, 0) 4508 case -AOR: 4509 return OPVCC(25, 0, 0, 0) /* ORIS/ORIU */ 4510 4511 case ARLWMI: 4512 return OPVCC(20, 0, 0, 0) /* rlwimi */ 4513 case ARLWMICC: 4514 return OPVCC(20, 0, 0, 1) 4515 case ARLDMI: 4516 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4517 case ARLDMICC: 4518 return OPVCC(30, 0, 0, 1) | 3<<2 4519 case ARLDIMI: 4520 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4521 case ARLDIMICC: 4522 return OPVCC(30, 0, 0, 1) | 3<<2 4523 case ARLWNM: 4524 return OPVCC(21, 0, 0, 0) /* rlwinm */ 4525 case ARLWNMCC: 4526 return OPVCC(21, 0, 0, 1) 4527 4528 case ARLDCL: 4529 return OPVCC(30, 0, 0, 0) /* rldicl */ 4530 case ARLDCLCC: 4531 return OPVCC(30, 0, 0, 1) 4532 case ARLDCR: 4533 return OPVCC(30, 1, 0, 0) /* rldicr */ 4534 case ARLDCRCC: 4535 return OPVCC(30, 1, 0, 1) 4536 case ARLDC: 4537 return OPVCC(30, 0, 0, 0) | 2<<2 4538 case ARLDCCC: 4539 return OPVCC(30, 0, 0, 1) | 2<<2 4540 4541 case ASRAW: 4542 return OPVCC(31, 824, 0, 0) 4543 case ASRAWCC: 4544 return OPVCC(31, 824, 0, 1) 4545 case ASRAD: 4546 return OPVCC(31, (413 << 1), 0, 0) 4547 case ASRADCC: 4548 return OPVCC(31, (413 << 1), 0, 1) 4549 4550 case ASTSW: 4551 return OPVCC(31, 725, 0, 0) 4552 4553 case ASUBC: 4554 return OPVCC(8, 0, 0, 0) 4555 4556 case ATW: 4557 return OPVCC(3, 0, 0, 0) 4558 case ATD: 4559 return OPVCC(2, 0, 0, 0) 4560 4561 /* Vector (VMX/Altivec) instructions */ 4562 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4563 /* are enabled starting at POWER6 (ISA 2.05). */ 4564 case AVSPLTB: 4565 return OPVX(4, 524, 0, 0) /* vspltb - v2.03 */ 4566 case AVSPLTH: 4567 return OPVX(4, 588, 0, 0) /* vsplth - v2.03 */ 4568 case AVSPLTW: 4569 return OPVX(4, 652, 0, 0) /* vspltw - v2.03 */ 4570 4571 case AVSPLTISB: 4572 return OPVX(4, 780, 0, 0) /* vspltisb - v2.03 */ 4573 case AVSPLTISH: 4574 return OPVX(4, 844, 0, 0) /* vspltish - v2.03 */ 4575 case AVSPLTISW: 4576 return OPVX(4, 908, 0, 0) /* vspltisw - v2.03 */ 4577 /* End of vector instructions */ 4578 4579 case AFTDIV: 4580 return OPVCC(63, 128, 0, 0) /* ftdiv - v2.06 */ 4581 case AFTSQRT: 4582 return OPVCC(63, 160, 0, 0) /* ftsqrt - v2.06 */ 4583 4584 case AXOR: 4585 return OPVCC(26, 0, 0, 0) /* XORIL */ 4586 case -AXOR: 4587 return OPVCC(27, 0, 0, 0) /* XORIU */ 4588 } 4589 4590 c.ctxt.Diag("bad opcode i/r or i/r/r %v", a) 4591 return 0 4592 } 4593 4594 /* 4595 * load o(a),d 4596 */ 4597 func (c *ctxt9) opload(a obj.As) uint32 { 4598 switch a { 4599 case AMOVD: 4600 return OPVCC(58, 0, 0, 0) /* ld */ 4601 case AMOVDU: 4602 return OPVCC(58, 0, 0, 1) /* ldu */ 4603 case AMOVWZ: 4604 return OPVCC(32, 0, 0, 0) /* lwz */ 4605 case AMOVWZU: 4606 return OPVCC(33, 0, 0, 0) /* lwzu */ 4607 case AMOVW: 4608 return OPVCC(58, 0, 0, 0) | 1<<1 /* lwa */ 4609 4610 /* no AMOVWU */ 4611 case AMOVB, AMOVBZ: 4612 return OPVCC(34, 0, 0, 0) 4613 /* load */ 4614 4615 case AMOVBU, AMOVBZU: 4616 return OPVCC(35, 0, 0, 0) 4617 case AFMOVD: 4618 return OPVCC(50, 0, 0, 0) 4619 case AFMOVDU: 4620 return OPVCC(51, 0, 0, 0) 4621 case AFMOVS: 4622 return OPVCC(48, 0, 0, 0) 4623 case AFMOVSU: 4624 return OPVCC(49, 0, 0, 0) 4625 case AMOVH: 4626 return OPVCC(42, 0, 0, 0) 4627 case AMOVHU: 4628 return OPVCC(43, 0, 0, 0) 4629 case AMOVHZ: 4630 return OPVCC(40, 0, 0, 0) 4631 case AMOVHZU: 4632 return OPVCC(41, 0, 0, 0) 4633 case AMOVMW: 4634 return OPVCC(46, 0, 0, 0) /* lmw */ 4635 } 4636 4637 c.ctxt.Diag("bad load opcode %v", a) 4638 return 0 4639 } 4640 4641 /* 4642 * indexed load a(b),d 4643 */ 4644 func (c *ctxt9) oploadx(a obj.As) uint32 { 4645 switch a { 4646 case AMOVWZ: 4647 return OPVCC(31, 23, 0, 0) /* lwzx */ 4648 case AMOVWZU: 4649 return OPVCC(31, 55, 0, 0) /* lwzux */ 4650 case AMOVW: 4651 return OPVCC(31, 341, 0, 0) /* lwax */ 4652 case AMOVWU: 4653 return OPVCC(31, 373, 0, 0) /* lwaux */ 4654 4655 case AMOVB, AMOVBZ: 4656 return OPVCC(31, 87, 0, 0) /* lbzx */ 4657 4658 case AMOVBU, AMOVBZU: 4659 return OPVCC(31, 119, 0, 0) /* lbzux */ 4660 case AFMOVD: 4661 return OPVCC(31, 599, 0, 0) /* lfdx */ 4662 case AFMOVDU: 4663 return OPVCC(31, 631, 0, 0) /* lfdux */ 4664 case AFMOVS: 4665 return OPVCC(31, 535, 0, 0) /* lfsx */ 4666 case AFMOVSU: 4667 return OPVCC(31, 567, 0, 0) /* lfsux */ 4668 case AFMOVSX: 4669 return OPVCC(31, 855, 0, 0) /* lfiwax - power6, isa 2.05 */ 4670 case AFMOVSZ: 4671 return OPVCC(31, 887, 0, 0) /* lfiwzx - power7, isa 2.06 */ 4672 case AMOVH: 4673 return OPVCC(31, 343, 0, 0) /* lhax */ 4674 case AMOVHU: 4675 return OPVCC(31, 375, 0, 0) /* lhaux */ 4676 case AMOVHBR: 4677 return OPVCC(31, 790, 0, 0) /* lhbrx */ 4678 case AMOVWBR: 4679 return OPVCC(31, 534, 0, 0) /* lwbrx */ 4680 case AMOVDBR: 4681 return OPVCC(31, 532, 0, 0) /* ldbrx */ 4682 case AMOVHZ: 4683 return OPVCC(31, 279, 0, 0) /* lhzx */ 4684 case AMOVHZU: 4685 return OPVCC(31, 311, 0, 0) /* lhzux */ 4686 case AECIWX: 4687 return OPVCC(31, 310, 0, 0) /* eciwx */ 4688 case ALBAR: 4689 return OPVCC(31, 52, 0, 0) /* lbarx */ 4690 case ALWAR: 4691 return OPVCC(31, 20, 0, 0) /* lwarx */ 4692 case ALDAR: 4693 return OPVCC(31, 84, 0, 0) 4694 case ALSW: 4695 return OPVCC(31, 533, 0, 0) /* lswx */ 4696 case AMOVD: 4697 return OPVCC(31, 21, 0, 0) /* ldx */ 4698 case AMOVDU: 4699 return OPVCC(31, 53, 0, 0) /* ldux */ 4700 case ALDMX: 4701 return OPVCC(31, 309, 0, 0) /* ldmx */ 4702 4703 /* Vector (VMX/Altivec) instructions */ 4704 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4705 /* are enabled starting at POWER6 (ISA 2.05). */ 4706 case ALVEBX: 4707 return OPVCC(31, 7, 0, 0) /* lvebx - v2.03 */ 4708 case ALVEHX: 4709 return OPVCC(31, 39, 0, 0) /* lvehx - v2.03 */ 4710 case ALVEWX: 4711 return OPVCC(31, 71, 0, 0) /* lvewx - v2.03 */ 4712 case ALVX: 4713 return OPVCC(31, 103, 0, 0) /* lvx - v2.03 */ 4714 case ALVXL: 4715 return OPVCC(31, 359, 0, 0) /* lvxl - v2.03 */ 4716 case ALVSL: 4717 return OPVCC(31, 6, 0, 0) /* lvsl - v2.03 */ 4718 case ALVSR: 4719 return OPVCC(31, 38, 0, 0) /* lvsr - v2.03 */ 4720 /* End of vector instructions */ 4721 4722 /* Vector scalar (VSX) instructions */ 4723 /* ISA 2.06 enables these for POWER7. */ 4724 case ALXVD2X: 4725 return OPVXX1(31, 844, 0) /* lxvd2x - v2.06 */ 4726 case ALXVDSX: 4727 return OPVXX1(31, 332, 0) /* lxvdsx - v2.06 */ 4728 case ALXVW4X: 4729 return OPVXX1(31, 780, 0) /* lxvw4x - v2.06 */ 4730 4731 case ALXSDX: 4732 return OPVXX1(31, 588, 0) /* lxsdx - v2.06 */ 4733 4734 case ALXSIWAX: 4735 return OPVXX1(31, 76, 0) /* lxsiwax - v2.07 */ 4736 case ALXSIWZX: 4737 return OPVXX1(31, 12, 0) /* lxsiwzx - v2.07 */ 4738 /* End of vector scalar instructions */ 4739 4740 } 4741 4742 c.ctxt.Diag("bad loadx opcode %v", a) 4743 return 0 4744 } 4745 4746 /* 4747 * store s,o(d) 4748 */ 4749 func (c *ctxt9) opstore(a obj.As) uint32 { 4750 switch a { 4751 case AMOVB, AMOVBZ: 4752 return OPVCC(38, 0, 0, 0) /* stb */ 4753 4754 case AMOVBU, AMOVBZU: 4755 return OPVCC(39, 0, 0, 0) /* stbu */ 4756 case AFMOVD: 4757 return OPVCC(54, 0, 0, 0) /* stfd */ 4758 case AFMOVDU: 4759 return OPVCC(55, 0, 0, 0) /* stfdu */ 4760 case AFMOVS: 4761 return OPVCC(52, 0, 0, 0) /* stfs */ 4762 case AFMOVSU: 4763 return OPVCC(53, 0, 0, 0) /* stfsu */ 4764 4765 case AMOVHZ, AMOVH: 4766 return OPVCC(44, 0, 0, 0) /* sth */ 4767 4768 case AMOVHZU, AMOVHU: 4769 return OPVCC(45, 0, 0, 0) /* sthu */ 4770 case AMOVMW: 4771 return OPVCC(47, 0, 0, 0) /* stmw */ 4772 case ASTSW: 4773 return OPVCC(31, 725, 0, 0) /* stswi */ 4774 4775 case AMOVWZ, AMOVW: 4776 return OPVCC(36, 0, 0, 0) /* stw */ 4777 4778 case AMOVWZU, AMOVWU: 4779 return OPVCC(37, 0, 0, 0) /* stwu */ 4780 case AMOVD: 4781 return OPVCC(62, 0, 0, 0) /* std */ 4782 case AMOVDU: 4783 return OPVCC(62, 0, 0, 1) /* stdu */ 4784 } 4785 4786 c.ctxt.Diag("unknown store opcode %v", a) 4787 return 0 4788 } 4789 4790 /* 4791 * indexed store s,a(b) 4792 */ 4793 func (c *ctxt9) opstorex(a obj.As) uint32 { 4794 switch a { 4795 case AMOVB, AMOVBZ: 4796 return OPVCC(31, 215, 0, 0) /* stbx */ 4797 4798 case AMOVBU, AMOVBZU: 4799 return OPVCC(31, 247, 0, 0) /* stbux */ 4800 case AFMOVD: 4801 return OPVCC(31, 727, 0, 0) /* stfdx */ 4802 case AFMOVDU: 4803 return OPVCC(31, 759, 0, 0) /* stfdux */ 4804 case AFMOVS: 4805 return OPVCC(31, 663, 0, 0) /* stfsx */ 4806 case AFMOVSU: 4807 return OPVCC(31, 695, 0, 0) /* stfsux */ 4808 case AFMOVSX: 4809 return OPVCC(31, 983, 0, 0) /* stfiwx */ 4810 4811 case AMOVHZ, AMOVH: 4812 return OPVCC(31, 407, 0, 0) /* sthx */ 4813 case AMOVHBR: 4814 return OPVCC(31, 918, 0, 0) /* sthbrx */ 4815 4816 case AMOVHZU, AMOVHU: 4817 return OPVCC(31, 439, 0, 0) /* sthux */ 4818 4819 case AMOVWZ, AMOVW: 4820 return OPVCC(31, 151, 0, 0) /* stwx */ 4821 4822 case AMOVWZU, AMOVWU: 4823 return OPVCC(31, 183, 0, 0) /* stwux */ 4824 case ASTSW: 4825 return OPVCC(31, 661, 0, 0) /* stswx */ 4826 case AMOVWBR: 4827 return OPVCC(31, 662, 0, 0) /* stwbrx */ 4828 case ASTBCCC: 4829 return OPVCC(31, 694, 0, 1) /* stbcx. */ 4830 case ASTWCCC: 4831 return OPVCC(31, 150, 0, 1) /* stwcx. */ 4832 case ASTDCCC: 4833 return OPVCC(31, 214, 0, 1) /* stwdx. */ 4834 case AECOWX: 4835 return OPVCC(31, 438, 0, 0) /* ecowx */ 4836 case AMOVD: 4837 return OPVCC(31, 149, 0, 0) /* stdx */ 4838 case AMOVDU: 4839 return OPVCC(31, 181, 0, 0) /* stdux */ 4840 4841 /* Vector (VMX/Altivec) instructions */ 4842 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4843 /* are enabled starting at POWER6 (ISA 2.05). */ 4844 case ASTVEBX: 4845 return OPVCC(31, 135, 0, 0) /* stvebx - v2.03 */ 4846 case ASTVEHX: 4847 return OPVCC(31, 167, 0, 0) /* stvehx - v2.03 */ 4848 case ASTVEWX: 4849 return OPVCC(31, 199, 0, 0) /* stvewx - v2.03 */ 4850 case ASTVX: 4851 return OPVCC(31, 231, 0, 0) /* stvx - v2.03 */ 4852 case ASTVXL: 4853 return OPVCC(31, 487, 0, 0) /* stvxl - v2.03 */ 4854 /* End of vector instructions */ 4855 4856 /* Vector scalar (VSX) instructions */ 4857 /* ISA 2.06 enables these for POWER7. */ 4858 case ASTXVD2X: 4859 return OPVXX1(31, 972, 0) /* stxvd2x - v2.06 */ 4860 case ASTXVW4X: 4861 return OPVXX1(31, 908, 0) /* stxvw4x - v2.06 */ 4862 4863 case ASTXSDX: 4864 return OPVXX1(31, 716, 0) /* stxsdx - v2.06 */ 4865 4866 case ASTXSIWX: 4867 return OPVXX1(31, 140, 0) /* stxsiwx - v2.07 */ 4868 /* End of vector scalar instructions */ 4869 4870 } 4871 4872 c.ctxt.Diag("unknown storex opcode %v", a) 4873 return 0 4874 }