github.com/goproxy0/go@v0.0.0-20171111080102-49cc0c489d2c/src/cmd/internal/obj/s390x/asmz.go (about) 1 // Based on cmd/internal/obj/ppc64/asm9.go. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package s390x 31 32 import ( 33 "cmd/internal/obj" 34 "cmd/internal/objabi" 35 "log" 36 "math" 37 "sort" 38 ) 39 40 // ctxtz holds state while assembling a single function. 41 // Each function gets a fresh ctxtz. 42 // This allows for multiple functions to be safely concurrently assembled. 43 type ctxtz struct { 44 ctxt *obj.Link 45 newprog obj.ProgAlloc 46 cursym *obj.LSym 47 autosize int32 48 instoffset int64 49 pc int64 50 } 51 52 // instruction layout. 53 const ( 54 funcAlign = 16 55 ) 56 57 type Optab struct { 58 as obj.As // opcode 59 a1 uint8 // From 60 a2 uint8 // Reg 61 a3 uint8 // From3 62 a4 uint8 // To 63 type_ int8 64 param int16 // REGSP for auto variables 65 } 66 67 var optab = []Optab{ 68 // instruction, From, Reg, From3, To, type, param 69 Optab{obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0}, 70 Optab{obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0}, 71 72 // move register 73 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 74 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 75 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 76 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 77 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 78 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 1, 0}, 79 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 80 81 // load constant 82 Optab{AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 83 Optab{AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 84 Optab{AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 85 Optab{AMOVD, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 86 Optab{AMOVW, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 87 Optab{AMOVWZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 88 Optab{AMOVB, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 89 Optab{AMOVBZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 90 91 // store constant 92 Optab{AMOVD, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 93 Optab{AMOVD, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 94 Optab{AMOVW, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 95 Optab{AMOVW, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 96 Optab{AMOVWZ, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 97 Optab{AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 98 Optab{AMOVB, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 99 Optab{AMOVB, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 100 Optab{AMOVBZ, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 101 Optab{AMOVBZ, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 102 Optab{AMOVD, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 103 Optab{AMOVD, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 104 Optab{AMOVW, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 105 Optab{AMOVW, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 106 Optab{AMOVWZ, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 107 Optab{AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 108 Optab{AMOVB, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 109 Optab{AMOVB, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 110 Optab{AMOVBZ, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 111 Optab{AMOVBZ, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 112 113 // store 114 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 115 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 116 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 117 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 118 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 119 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 120 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 121 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 122 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 123 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 124 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 125 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 126 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 127 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 128 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 129 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 130 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 131 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 132 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 133 134 // load 135 Optab{AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 136 Optab{AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 137 Optab{AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 138 Optab{AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 139 Optab{AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 140 Optab{AMOVDBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 141 Optab{AMOVHBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 142 Optab{AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 143 Optab{AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 144 Optab{AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 145 Optab{AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 146 Optab{AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 147 Optab{AMOVDBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 148 Optab{AMOVHBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 149 Optab{AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 150 Optab{AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 151 Optab{AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 152 Optab{AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 153 Optab{AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 154 155 // interlocked load and op 156 Optab{ALAAG, C_REG, C_REG, C_NONE, C_LOREG, 99, 0}, 157 158 // integer arithmetic 159 Optab{AADD, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 160 Optab{AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 161 Optab{AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 0}, 162 Optab{AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 0}, 163 Optab{AADD, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 164 Optab{AADD, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 165 Optab{ASUB, C_LCON, C_REG, C_NONE, C_REG, 21, 0}, 166 Optab{ASUB, C_LCON, C_NONE, C_NONE, C_REG, 21, 0}, 167 Optab{ASUB, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 168 Optab{ASUB, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 169 Optab{AMULHD, C_REG, C_NONE, C_NONE, C_REG, 4, 0}, 170 Optab{AMULHD, C_REG, C_REG, C_NONE, C_REG, 4, 0}, 171 Optab{ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 172 Optab{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 173 Optab{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 0}, 174 Optab{ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 0}, 175 Optab{ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 0}, 176 Optab{ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 0}, 177 178 // integer logical 179 Optab{AAND, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 180 Optab{AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 181 Optab{AAND, C_LCON, C_NONE, C_NONE, C_REG, 23, 0}, 182 Optab{AAND, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 183 Optab{AAND, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 184 Optab{AANDW, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 185 Optab{AANDW, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 186 Optab{AANDW, C_LCON, C_NONE, C_NONE, C_REG, 24, 0}, 187 Optab{AANDW, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 188 Optab{AANDW, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 189 Optab{ASLD, C_REG, C_NONE, C_NONE, C_REG, 7, 0}, 190 Optab{ASLD, C_REG, C_REG, C_NONE, C_REG, 7, 0}, 191 Optab{ASLD, C_SCON, C_REG, C_NONE, C_REG, 7, 0}, 192 Optab{ASLD, C_SCON, C_NONE, C_NONE, C_REG, 7, 0}, 193 194 // compare and swap 195 Optab{ACSG, C_REG, C_REG, C_NONE, C_SOREG, 79, 0}, 196 197 // floating point 198 Optab{AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 199 Optab{AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 0}, 200 Optab{AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 0}, 201 Optab{AFMADD, C_FREG, C_FREG, C_NONE, C_FREG, 34, 0}, 202 Optab{AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 203 Optab{AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, REGSP}, 204 Optab{AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 0}, 205 Optab{AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 0}, 206 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 207 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 0}, 208 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 0}, 209 Optab{AFMOVD, C_ZCON, C_NONE, C_NONE, C_FREG, 67, 0}, 210 Optab{ALDGR, C_REG, C_NONE, C_NONE, C_FREG, 81, 0}, 211 Optab{ALGDR, C_FREG, C_NONE, C_NONE, C_REG, 81, 0}, 212 Optab{ACEFBRA, C_REG, C_NONE, C_NONE, C_FREG, 82, 0}, 213 Optab{ACFEBRA, C_FREG, C_NONE, C_NONE, C_REG, 83, 0}, 214 Optab{AFIEBR, C_SCON, C_FREG, C_NONE, C_FREG, 48, 0}, 215 Optab{ACPSDR, C_FREG, C_FREG, C_NONE, C_FREG, 49, 0}, 216 217 // load symbol address (plus offset) 218 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_REG, 19, 0}, 219 Optab{AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 93, 0}, 220 Optab{AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 94, 0}, 221 Optab{AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 95, 0}, 222 223 // system call 224 Optab{ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 0}, 225 Optab{ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 0}, 226 227 // branch 228 Optab{ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 0}, 229 Optab{ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 0}, 230 Optab{ABC, C_SCON, C_REG, C_NONE, C_LBRA, 16, 0}, 231 Optab{ABR, C_NONE, C_NONE, C_NONE, C_REG, 18, 0}, 232 Optab{ABR, C_REG, C_NONE, C_NONE, C_REG, 18, 0}, 233 Optab{ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 234 Optab{ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 235 Optab{ACMPBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 236 Optab{ACMPBEQ, C_REG, C_NONE, C_ADDCON, C_SBRA, 90, 0}, 237 Optab{ACMPBEQ, C_REG, C_NONE, C_SCON, C_SBRA, 90, 0}, 238 Optab{ACMPUBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 239 Optab{ACMPUBEQ, C_REG, C_NONE, C_ANDCON, C_SBRA, 90, 0}, 240 241 // move on condition 242 Optab{AMOVDEQ, C_REG, C_NONE, C_NONE, C_REG, 17, 0}, 243 244 // find leftmost one 245 Optab{AFLOGR, C_REG, C_NONE, C_NONE, C_REG, 8, 0}, 246 247 // compare 248 Optab{ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 249 Optab{ACMP, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 250 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 251 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 252 Optab{AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 0}, 253 Optab{AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 0}, 254 255 // test under mask 256 Optab{ATMHH, C_REG, C_NONE, C_NONE, C_ANDCON, 91, 0}, 257 258 // 32-bit access registers 259 Optab{AMOVW, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 260 Optab{AMOVWZ, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 261 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 262 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 263 264 // macros 265 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LOREG, 96, 0}, 266 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LAUTO, 96, REGSP}, 267 268 // load/store multiple 269 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LOREG, 97, 0}, 270 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LAUTO, 97, REGSP}, 271 Optab{ALMG, C_LOREG, C_REG, C_NONE, C_REG, 98, 0}, 272 Optab{ALMG, C_LAUTO, C_REG, C_NONE, C_REG, 98, REGSP}, 273 274 // bytes 275 Optab{ABYTE, C_SCON, C_NONE, C_NONE, C_NONE, 40, 0}, 276 Optab{AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 0}, 277 Optab{ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 0}, 278 Optab{ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 0}, 279 280 // fast synchronization 281 Optab{ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 80, 0}, 282 283 // store clock 284 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SAUTO, 88, REGSP}, 285 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SOREG, 88, 0}, 286 287 // storage and storage 288 Optab{AMVC, C_SCON, C_NONE, C_LOREG, C_LOREG, 84, 0}, 289 Optab{AMVC, C_SCON, C_NONE, C_LOREG, C_LAUTO, 84, REGSP}, 290 Optab{AMVC, C_SCON, C_NONE, C_LAUTO, C_LAUTO, 84, REGSP}, 291 292 // address 293 Optab{ALARL, C_LCON, C_NONE, C_NONE, C_REG, 85, 0}, 294 Optab{ALARL, C_SYMADDR, C_NONE, C_NONE, C_REG, 85, 0}, 295 Optab{ALA, C_SOREG, C_NONE, C_NONE, C_REG, 86, 0}, 296 Optab{ALA, C_SAUTO, C_NONE, C_NONE, C_REG, 86, REGSP}, 297 Optab{AEXRL, C_SYMADDR, C_NONE, C_NONE, C_REG, 87, 0}, 298 299 // misc 300 Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 0}, 301 Optab{obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0}, 302 Optab{obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0}, 303 Optab{obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0}, 304 Optab{obj.ANOP, C_SAUTO, C_NONE, C_NONE, C_NONE, 0, 0}, 305 306 // vector instructions 307 308 // VRX store 309 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SOREG, 100, 0}, 310 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SAUTO, 100, REGSP}, 311 Optab{AVSTEG, C_SCON, C_VREG, C_NONE, C_SOREG, 100, 0}, 312 Optab{AVSTEG, C_SCON, C_VREG, C_NONE, C_SAUTO, 100, REGSP}, 313 314 // VRX load 315 Optab{AVL, C_SOREG, C_NONE, C_NONE, C_VREG, 101, 0}, 316 Optab{AVL, C_SAUTO, C_NONE, C_NONE, C_VREG, 101, REGSP}, 317 Optab{AVLEG, C_SCON, C_NONE, C_SOREG, C_VREG, 101, 0}, 318 Optab{AVLEG, C_SCON, C_NONE, C_SAUTO, C_VREG, 101, REGSP}, 319 320 // VRV scatter 321 Optab{AVSCEG, C_SCON, C_VREG, C_NONE, C_SOREG, 102, 0}, 322 Optab{AVSCEG, C_SCON, C_VREG, C_NONE, C_SAUTO, 102, REGSP}, 323 324 // VRV gather 325 Optab{AVGEG, C_SCON, C_NONE, C_SOREG, C_VREG, 103, 0}, 326 Optab{AVGEG, C_SCON, C_NONE, C_SAUTO, C_VREG, 103, REGSP}, 327 328 // VRS element shift/rotate and load gr to/from vr element 329 Optab{AVESLG, C_SCON, C_VREG, C_NONE, C_VREG, 104, 0}, 330 Optab{AVESLG, C_REG, C_VREG, C_NONE, C_VREG, 104, 0}, 331 Optab{AVESLG, C_SCON, C_NONE, C_NONE, C_VREG, 104, 0}, 332 Optab{AVESLG, C_REG, C_NONE, C_NONE, C_VREG, 104, 0}, 333 Optab{AVLGVG, C_SCON, C_VREG, C_NONE, C_REG, 104, 0}, 334 Optab{AVLGVG, C_REG, C_VREG, C_NONE, C_REG, 104, 0}, 335 Optab{AVLVGG, C_SCON, C_REG, C_NONE, C_VREG, 104, 0}, 336 Optab{AVLVGG, C_REG, C_REG, C_NONE, C_VREG, 104, 0}, 337 338 // VRS store multiple 339 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SOREG, 105, 0}, 340 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SAUTO, 105, REGSP}, 341 342 // VRS load multiple 343 Optab{AVLM, C_SOREG, C_VREG, C_NONE, C_VREG, 106, 0}, 344 Optab{AVLM, C_SAUTO, C_VREG, C_NONE, C_VREG, 106, REGSP}, 345 346 // VRS store with length 347 Optab{AVSTL, C_REG, C_VREG, C_NONE, C_SOREG, 107, 0}, 348 Optab{AVSTL, C_REG, C_VREG, C_NONE, C_SAUTO, 107, REGSP}, 349 350 // VRS load with length 351 Optab{AVLL, C_REG, C_NONE, C_SOREG, C_VREG, 108, 0}, 352 Optab{AVLL, C_REG, C_NONE, C_SAUTO, C_VREG, 108, REGSP}, 353 354 // VRI-a 355 Optab{AVGBM, C_ANDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 356 Optab{AVZERO, C_NONE, C_NONE, C_NONE, C_VREG, 109, 0}, 357 Optab{AVREPIG, C_ADDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 358 Optab{AVREPIG, C_SCON, C_NONE, C_NONE, C_VREG, 109, 0}, 359 Optab{AVLEIG, C_SCON, C_NONE, C_ADDCON, C_VREG, 109, 0}, 360 Optab{AVLEIG, C_SCON, C_NONE, C_SCON, C_VREG, 109, 0}, 361 362 // VRI-b generate mask 363 Optab{AVGMG, C_SCON, C_NONE, C_SCON, C_VREG, 110, 0}, 364 365 // VRI-c replicate 366 Optab{AVREPG, C_UCON, C_VREG, C_NONE, C_VREG, 111, 0}, 367 368 // VRI-d element rotate and insert under mask and 369 // shift left double by byte 370 Optab{AVERIMG, C_SCON, C_VREG, C_VREG, C_VREG, 112, 0}, 371 Optab{AVSLDB, C_SCON, C_VREG, C_VREG, C_VREG, 112, 0}, 372 373 // VRI-d fp test data class immediate 374 Optab{AVFTCIDB, C_SCON, C_VREG, C_NONE, C_VREG, 113, 0}, 375 376 // VRR-a load reg 377 Optab{AVLR, C_VREG, C_NONE, C_NONE, C_VREG, 114, 0}, 378 379 // VRR-a compare 380 Optab{AVECG, C_VREG, C_NONE, C_NONE, C_VREG, 115, 0}, 381 382 // VRR-b 383 Optab{AVCEQG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 384 Optab{AVFAEF, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 385 Optab{AVPKSG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 386 387 // VRR-c 388 Optab{AVAQ, C_VREG, C_VREG, C_NONE, C_VREG, 118, 0}, 389 Optab{AVAQ, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 390 Optab{AVNOT, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 391 Optab{AVPDI, C_SCON, C_VREG, C_VREG, C_VREG, 123, 0}, 392 393 // VRR-c shifts 394 Optab{AVERLLVG, C_VREG, C_VREG, C_NONE, C_VREG, 119, 0}, 395 Optab{AVERLLVG, C_VREG, C_NONE, C_NONE, C_VREG, 119, 0}, 396 397 // VRR-d 398 // 2 3 1 4 399 Optab{AVACQ, C_VREG, C_VREG, C_VREG, C_VREG, 120, 0}, 400 401 // VRR-e 402 Optab{AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 121, 0}, 403 404 // VRR-f 405 Optab{AVLVGP, C_REG, C_REG, C_NONE, C_VREG, 122, 0}, 406 } 407 408 var oprange [ALAST & obj.AMask][]Optab 409 410 var xcmp [C_NCLASS][C_NCLASS]bool 411 412 func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 413 p := cursym.Func.Text 414 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 415 return 416 } 417 418 if oprange[AORW&obj.AMask] == nil { 419 ctxt.Diag("s390x ops not initialized, call s390x.buildop first") 420 } 421 422 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 423 424 buffer := make([]byte, 0) 425 changed := true 426 loop := 0 427 for changed { 428 if loop > 10 { 429 c.ctxt.Diag("stuck in spanz loop") 430 break 431 } 432 changed = false 433 buffer = buffer[:0] 434 c.cursym.R = make([]obj.Reloc, 0) 435 for p := c.cursym.Func.Text; p != nil; p = p.Link { 436 pc := int64(len(buffer)) 437 if pc != p.Pc { 438 changed = true 439 } 440 p.Pc = pc 441 c.pc = p.Pc 442 c.asmout(p, &buffer) 443 if pc == int64(len(buffer)) { 444 switch p.As { 445 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT: 446 // ok 447 default: 448 c.ctxt.Diag("zero-width instruction\n%v", p) 449 } 450 } 451 } 452 loop++ 453 } 454 455 c.cursym.Size = int64(len(buffer)) 456 if c.cursym.Size%funcAlign != 0 { 457 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign) 458 } 459 c.cursym.Grow(c.cursym.Size) 460 copy(c.cursym.P, buffer) 461 } 462 463 func isint32(v int64) bool { 464 return int64(int32(v)) == v 465 } 466 467 func isuint32(v uint64) bool { 468 return uint64(uint32(v)) == v 469 } 470 471 func (c *ctxtz) aclass(a *obj.Addr) int { 472 switch a.Type { 473 case obj.TYPE_NONE: 474 return C_NONE 475 476 case obj.TYPE_REG: 477 if REG_R0 <= a.Reg && a.Reg <= REG_R15 { 478 return C_REG 479 } 480 if REG_F0 <= a.Reg && a.Reg <= REG_F15 { 481 return C_FREG 482 } 483 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 { 484 return C_AREG 485 } 486 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 487 return C_VREG 488 } 489 return C_GOK 490 491 case obj.TYPE_MEM: 492 switch a.Name { 493 case obj.NAME_EXTERN, 494 obj.NAME_STATIC: 495 if a.Sym == nil { 496 // must have a symbol 497 break 498 } 499 c.instoffset = a.Offset 500 if a.Sym.Type == objabi.STLSBSS { 501 if c.ctxt.Flag_shared { 502 return C_TLS_IE // initial exec model 503 } 504 return C_TLS_LE // local exec model 505 } 506 return C_ADDR 507 508 case obj.NAME_GOTREF: 509 return C_GOTADDR 510 511 case obj.NAME_AUTO: 512 if a.Reg == REGSP { 513 // unset base register for better printing, since 514 // a.Offset is still relative to pseudo-SP. 515 a.Reg = obj.REG_NONE 516 } 517 c.instoffset = int64(c.autosize) + a.Offset 518 if c.instoffset >= -BIG && c.instoffset < BIG { 519 return C_SAUTO 520 } 521 return C_LAUTO 522 523 case obj.NAME_PARAM: 524 if a.Reg == REGSP { 525 // unset base register for better printing, since 526 // a.Offset is still relative to pseudo-FP. 527 a.Reg = obj.REG_NONE 528 } 529 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 530 if c.instoffset >= -BIG && c.instoffset < BIG { 531 return C_SAUTO 532 } 533 return C_LAUTO 534 535 case obj.NAME_NONE: 536 c.instoffset = a.Offset 537 if c.instoffset == 0 { 538 return C_ZOREG 539 } 540 if c.instoffset >= -BIG && c.instoffset < BIG { 541 return C_SOREG 542 } 543 return C_LOREG 544 } 545 546 return C_GOK 547 548 case obj.TYPE_TEXTSIZE: 549 return C_TEXTSIZE 550 551 case obj.TYPE_FCONST: 552 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 { 553 return C_ZCON 554 } 555 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val) 556 557 case obj.TYPE_CONST, 558 obj.TYPE_ADDR: 559 switch a.Name { 560 case obj.NAME_NONE: 561 c.instoffset = a.Offset 562 if a.Reg != 0 { 563 if -BIG <= c.instoffset && c.instoffset <= BIG { 564 return C_SACON 565 } 566 if isint32(c.instoffset) { 567 return C_LACON 568 } 569 return C_DACON 570 } 571 goto consize 572 573 case obj.NAME_EXTERN, 574 obj.NAME_STATIC: 575 s := a.Sym 576 if s == nil { 577 break 578 } 579 c.instoffset = a.Offset 580 581 return C_SYMADDR 582 583 case obj.NAME_AUTO: 584 if a.Reg == REGSP { 585 // unset base register for better printing, since 586 // a.Offset is still relative to pseudo-SP. 587 a.Reg = obj.REG_NONE 588 } 589 c.instoffset = int64(c.autosize) + a.Offset 590 if c.instoffset >= -BIG && c.instoffset < BIG { 591 return C_SACON 592 } 593 return C_LACON 594 595 case obj.NAME_PARAM: 596 if a.Reg == REGSP { 597 // unset base register for better printing, since 598 // a.Offset is still relative to pseudo-FP. 599 a.Reg = obj.REG_NONE 600 } 601 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 602 if c.instoffset >= -BIG && c.instoffset < BIG { 603 return C_SACON 604 } 605 return C_LACON 606 } 607 608 return C_GOK 609 610 consize: 611 if c.instoffset == 0 { 612 return C_ZCON 613 } 614 if c.instoffset >= 0 { 615 if c.instoffset <= 0x7fff { 616 return C_SCON 617 } 618 if c.instoffset <= 0xffff { 619 return C_ANDCON 620 } 621 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 622 return C_UCON 623 } 624 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 625 return C_LCON 626 } 627 return C_DCON 628 } 629 630 if c.instoffset >= -0x8000 { 631 return C_ADDCON 632 } 633 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 634 return C_UCON 635 } 636 if isint32(c.instoffset) { 637 return C_LCON 638 } 639 return C_DCON 640 641 case obj.TYPE_BRANCH: 642 return C_SBRA 643 } 644 645 return C_GOK 646 } 647 648 func (c *ctxtz) oplook(p *obj.Prog) *Optab { 649 a1 := int(p.Optab) 650 if a1 != 0 { 651 return &optab[a1-1] 652 } 653 a1 = int(p.From.Class) 654 if a1 == 0 { 655 a1 = c.aclass(&p.From) + 1 656 p.From.Class = int8(a1) 657 } 658 659 a1-- 660 a3 := C_NONE + 1 661 if p.GetFrom3() != nil { 662 a3 = int(p.GetFrom3().Class) 663 if a3 == 0 { 664 a3 = c.aclass(p.GetFrom3()) + 1 665 p.GetFrom3().Class = int8(a3) 666 } 667 } 668 669 a3-- 670 a4 := int(p.To.Class) 671 if a4 == 0 { 672 a4 = c.aclass(&p.To) + 1 673 p.To.Class = int8(a4) 674 } 675 676 a4-- 677 a2 := C_NONE 678 if p.Reg != 0 { 679 if REG_R0 <= p.Reg && p.Reg <= REG_R15 { 680 a2 = C_REG 681 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 682 a2 = C_VREG 683 } else if REG_F0 <= p.Reg && p.Reg <= REG_F15 { 684 a2 = C_FREG 685 } else if REG_AR0 <= p.Reg && p.Reg <= REG_AR15 { 686 a2 = C_AREG 687 } 688 } 689 690 ops := oprange[p.As&obj.AMask] 691 c1 := &xcmp[a1] 692 c2 := &xcmp[a2] 693 c3 := &xcmp[a3] 694 c4 := &xcmp[a4] 695 for i := range ops { 696 op := &ops[i] 697 if (int(op.a2) == a2 || c2[op.a2]) && c4[op.a4] && c1[op.a1] && c3[op.a3] { 698 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 699 return op 700 } 701 } 702 703 // cannot find a case; abort 704 c.ctxt.Diag("illegal combination %v %v %v %v %v\n", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 705 c.ctxt.Diag("prog: %v\n", p) 706 return nil 707 } 708 709 func cmp(a int, b int) bool { 710 if a == b { 711 return true 712 } 713 switch a { 714 case C_DCON: 715 if b == C_LCON { 716 return true 717 } 718 fallthrough 719 case C_LCON: 720 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 721 return true 722 } 723 724 case C_ADDCON: 725 if b == C_ZCON || b == C_SCON { 726 return true 727 } 728 729 case C_ANDCON: 730 if b == C_ZCON || b == C_SCON { 731 return true 732 } 733 734 case C_UCON: 735 if b == C_ZCON || b == C_SCON { 736 return true 737 } 738 739 case C_SCON: 740 if b == C_ZCON { 741 return true 742 } 743 744 case C_LACON: 745 if b == C_SACON { 746 return true 747 } 748 749 case C_LBRA: 750 if b == C_SBRA { 751 return true 752 } 753 754 case C_LAUTO: 755 if b == C_SAUTO { 756 return true 757 } 758 759 case C_LOREG: 760 if b == C_ZOREG || b == C_SOREG { 761 return true 762 } 763 764 case C_SOREG: 765 if b == C_ZOREG { 766 return true 767 } 768 769 case C_ANY: 770 return true 771 } 772 773 return false 774 } 775 776 type ocmp []Optab 777 778 func (x ocmp) Len() int { 779 return len(x) 780 } 781 782 func (x ocmp) Swap(i, j int) { 783 x[i], x[j] = x[j], x[i] 784 } 785 786 func (x ocmp) Less(i, j int) bool { 787 p1 := &x[i] 788 p2 := &x[j] 789 n := int(p1.as) - int(p2.as) 790 if n != 0 { 791 return n < 0 792 } 793 n = int(p1.a1) - int(p2.a1) 794 if n != 0 { 795 return n < 0 796 } 797 n = int(p1.a2) - int(p2.a2) 798 if n != 0 { 799 return n < 0 800 } 801 n = int(p1.a3) - int(p2.a3) 802 if n != 0 { 803 return n < 0 804 } 805 n = int(p1.a4) - int(p2.a4) 806 if n != 0 { 807 return n < 0 808 } 809 return false 810 } 811 func opset(a, b obj.As) { 812 oprange[a&obj.AMask] = oprange[b&obj.AMask] 813 } 814 815 func buildop(ctxt *obj.Link) { 816 if oprange[AORW&obj.AMask] != nil { 817 // Already initialized; stop now. 818 // This happens in the cmd/asm tests, 819 // each of which re-initializes the arch. 820 return 821 } 822 823 for i := 0; i < C_NCLASS; i++ { 824 for n := 0; n < C_NCLASS; n++ { 825 if cmp(n, i) { 826 xcmp[i][n] = true 827 } 828 } 829 } 830 sort.Sort(ocmp(optab)) 831 for i := 0; i < len(optab); i++ { 832 r := optab[i].as 833 start := i 834 for ; i+1 < len(optab); i++ { 835 if optab[i+1].as != r { 836 break 837 } 838 } 839 oprange[r&obj.AMask] = optab[start : i+1] 840 841 // opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array. 842 // oprange[] is used by oplook() to find the Optab entry that applies to a given Prog. 843 switch r { 844 case AADD: 845 opset(AADDC, r) 846 opset(AADDW, r) 847 opset(AMULLD, r) 848 opset(AMULLW, r) 849 case ADIVW: 850 opset(AADDE, r) 851 opset(ADIVD, r) 852 opset(ADIVDU, r) 853 opset(ADIVWU, r) 854 opset(AMODD, r) 855 opset(AMODDU, r) 856 opset(AMODW, r) 857 opset(AMODWU, r) 858 case AMULHD: 859 opset(AMULHDU, r) 860 case AMOVBZ: 861 opset(AMOVH, r) 862 opset(AMOVHZ, r) 863 case ALA: 864 opset(ALAY, r) 865 case AMVC: 866 opset(ACLC, r) 867 opset(AXC, r) 868 opset(AOC, r) 869 opset(ANC, r) 870 case ASTCK: 871 opset(ASTCKC, r) 872 opset(ASTCKE, r) 873 opset(ASTCKF, r) 874 case ALAAG: 875 opset(ALAA, r) 876 opset(ALAAL, r) 877 opset(ALAALG, r) 878 opset(ALAN, r) 879 opset(ALANG, r) 880 opset(ALAX, r) 881 opset(ALAXG, r) 882 opset(ALAO, r) 883 opset(ALAOG, r) 884 case ASTMG: 885 opset(ASTMY, r) 886 case ALMG: 887 opset(ALMY, r) 888 case ABEQ: 889 opset(ABGE, r) 890 opset(ABGT, r) 891 opset(ABLE, r) 892 opset(ABLT, r) 893 opset(ABNE, r) 894 opset(ABVC, r) 895 opset(ABVS, r) 896 opset(ABLEU, r) 897 opset(ABLTU, r) 898 case ABR: 899 opset(ABL, r) 900 case ABC: 901 opset(ABCL, r) 902 case AFABS: 903 opset(AFNABS, r) 904 opset(ALPDFR, r) 905 opset(ALNDFR, r) 906 opset(AFNEG, r) 907 opset(AFNEGS, r) 908 opset(ALEDBR, r) 909 opset(ALDEBR, r) 910 opset(AFSQRT, r) 911 opset(AFSQRTS, r) 912 case AFADD: 913 opset(AFADDS, r) 914 opset(AFDIV, r) 915 opset(AFDIVS, r) 916 opset(AFSUB, r) 917 opset(AFSUBS, r) 918 case AFMADD: 919 opset(AFMADDS, r) 920 opset(AFMSUB, r) 921 opset(AFMSUBS, r) 922 case AFMUL: 923 opset(AFMULS, r) 924 case AFCMPO: 925 opset(AFCMPU, r) 926 opset(ACEBR, r) 927 case AAND: 928 opset(AOR, r) 929 opset(AXOR, r) 930 case AANDW: 931 opset(AORW, r) 932 opset(AXORW, r) 933 case ASLD: 934 opset(ASRD, r) 935 opset(ASLW, r) 936 opset(ASRW, r) 937 opset(ASRAD, r) 938 opset(ASRAW, r) 939 opset(ARLL, r) 940 opset(ARLLG, r) 941 case ACSG: 942 opset(ACS, r) 943 case ASUB: 944 opset(ASUBC, r) 945 opset(ASUBE, r) 946 opset(ASUBW, r) 947 case ANEG: 948 opset(ANEGW, r) 949 case AFMOVD: 950 opset(AFMOVS, r) 951 case AMOVDBR: 952 opset(AMOVWBR, r) 953 case ACMP: 954 opset(ACMPW, r) 955 case ACMPU: 956 opset(ACMPWU, r) 957 case ATMHH: 958 opset(ATMHL, r) 959 opset(ATMLH, r) 960 opset(ATMLL, r) 961 case ACEFBRA: 962 opset(ACDFBRA, r) 963 opset(ACEGBRA, r) 964 opset(ACDGBRA, r) 965 opset(ACELFBR, r) 966 opset(ACDLFBR, r) 967 opset(ACELGBR, r) 968 opset(ACDLGBR, r) 969 case ACFEBRA: 970 opset(ACFDBRA, r) 971 opset(ACGEBRA, r) 972 opset(ACGDBRA, r) 973 opset(ACLFEBR, r) 974 opset(ACLFDBR, r) 975 opset(ACLGEBR, r) 976 opset(ACLGDBR, r) 977 case AFIEBR: 978 opset(AFIDBR, r) 979 case ACMPBEQ: 980 opset(ACMPBGE, r) 981 opset(ACMPBGT, r) 982 opset(ACMPBLE, r) 983 opset(ACMPBLT, r) 984 opset(ACMPBNE, r) 985 case ACMPUBEQ: 986 opset(ACMPUBGE, r) 987 opset(ACMPUBGT, r) 988 opset(ACMPUBLE, r) 989 opset(ACMPUBLT, r) 990 opset(ACMPUBNE, r) 991 case AMOVDEQ: 992 opset(AMOVDGE, r) 993 opset(AMOVDGT, r) 994 opset(AMOVDLE, r) 995 opset(AMOVDLT, r) 996 opset(AMOVDNE, r) 997 case AVL: 998 opset(AVLLEZB, r) 999 opset(AVLLEZH, r) 1000 opset(AVLLEZF, r) 1001 opset(AVLLEZG, r) 1002 opset(AVLREPB, r) 1003 opset(AVLREPH, r) 1004 opset(AVLREPF, r) 1005 opset(AVLREPG, r) 1006 case AVLEG: 1007 opset(AVLBB, r) 1008 opset(AVLEB, r) 1009 opset(AVLEH, r) 1010 opset(AVLEF, r) 1011 opset(AVLEG, r) 1012 opset(AVLREP, r) 1013 case AVSTEG: 1014 opset(AVSTEB, r) 1015 opset(AVSTEH, r) 1016 opset(AVSTEF, r) 1017 case AVSCEG: 1018 opset(AVSCEF, r) 1019 case AVGEG: 1020 opset(AVGEF, r) 1021 case AVESLG: 1022 opset(AVESLB, r) 1023 opset(AVESLH, r) 1024 opset(AVESLF, r) 1025 opset(AVERLLB, r) 1026 opset(AVERLLH, r) 1027 opset(AVERLLF, r) 1028 opset(AVERLLG, r) 1029 opset(AVESRAB, r) 1030 opset(AVESRAH, r) 1031 opset(AVESRAF, r) 1032 opset(AVESRAG, r) 1033 opset(AVESRLB, r) 1034 opset(AVESRLH, r) 1035 opset(AVESRLF, r) 1036 opset(AVESRLG, r) 1037 case AVLGVG: 1038 opset(AVLGVB, r) 1039 opset(AVLGVH, r) 1040 opset(AVLGVF, r) 1041 case AVLVGG: 1042 opset(AVLVGB, r) 1043 opset(AVLVGH, r) 1044 opset(AVLVGF, r) 1045 case AVZERO: 1046 opset(AVONE, r) 1047 case AVREPIG: 1048 opset(AVREPIB, r) 1049 opset(AVREPIH, r) 1050 opset(AVREPIF, r) 1051 case AVLEIG: 1052 opset(AVLEIB, r) 1053 opset(AVLEIH, r) 1054 opset(AVLEIF, r) 1055 case AVGMG: 1056 opset(AVGMB, r) 1057 opset(AVGMH, r) 1058 opset(AVGMF, r) 1059 case AVREPG: 1060 opset(AVREPB, r) 1061 opset(AVREPH, r) 1062 opset(AVREPF, r) 1063 case AVERIMG: 1064 opset(AVERIMB, r) 1065 opset(AVERIMH, r) 1066 opset(AVERIMF, r) 1067 case AVFTCIDB: 1068 opset(AWFTCIDB, r) 1069 case AVLR: 1070 opset(AVUPHB, r) 1071 opset(AVUPHH, r) 1072 opset(AVUPHF, r) 1073 opset(AVUPLHB, r) 1074 opset(AVUPLHH, r) 1075 opset(AVUPLHF, r) 1076 opset(AVUPLB, r) 1077 opset(AVUPLHW, r) 1078 opset(AVUPLF, r) 1079 opset(AVUPLLB, r) 1080 opset(AVUPLLH, r) 1081 opset(AVUPLLF, r) 1082 opset(AVCLZB, r) 1083 opset(AVCLZH, r) 1084 opset(AVCLZF, r) 1085 opset(AVCLZG, r) 1086 opset(AVCTZB, r) 1087 opset(AVCTZH, r) 1088 opset(AVCTZF, r) 1089 opset(AVCTZG, r) 1090 opset(AVLDEB, r) 1091 opset(AWLDEB, r) 1092 opset(AVFLCDB, r) 1093 opset(AWFLCDB, r) 1094 opset(AVFLNDB, r) 1095 opset(AWFLNDB, r) 1096 opset(AVFLPDB, r) 1097 opset(AWFLPDB, r) 1098 opset(AVFSQDB, r) 1099 opset(AWFSQDB, r) 1100 opset(AVISTRB, r) 1101 opset(AVISTRH, r) 1102 opset(AVISTRF, r) 1103 opset(AVISTRBS, r) 1104 opset(AVISTRHS, r) 1105 opset(AVISTRFS, r) 1106 opset(AVLCB, r) 1107 opset(AVLCH, r) 1108 opset(AVLCF, r) 1109 opset(AVLCG, r) 1110 opset(AVLPB, r) 1111 opset(AVLPH, r) 1112 opset(AVLPF, r) 1113 opset(AVLPG, r) 1114 opset(AVPOPCT, r) 1115 opset(AVSEGB, r) 1116 opset(AVSEGH, r) 1117 opset(AVSEGF, r) 1118 case AVECG: 1119 opset(AVECB, r) 1120 opset(AVECH, r) 1121 opset(AVECF, r) 1122 opset(AVECLB, r) 1123 opset(AVECLH, r) 1124 opset(AVECLF, r) 1125 opset(AVECLG, r) 1126 opset(AWFCDB, r) 1127 opset(AWFKDB, r) 1128 case AVCEQG: 1129 opset(AVCEQB, r) 1130 opset(AVCEQH, r) 1131 opset(AVCEQF, r) 1132 opset(AVCEQBS, r) 1133 opset(AVCEQHS, r) 1134 opset(AVCEQFS, r) 1135 opset(AVCEQGS, r) 1136 opset(AVCHB, r) 1137 opset(AVCHH, r) 1138 opset(AVCHF, r) 1139 opset(AVCHG, r) 1140 opset(AVCHBS, r) 1141 opset(AVCHHS, r) 1142 opset(AVCHFS, r) 1143 opset(AVCHGS, r) 1144 opset(AVCHLB, r) 1145 opset(AVCHLH, r) 1146 opset(AVCHLF, r) 1147 opset(AVCHLG, r) 1148 opset(AVCHLBS, r) 1149 opset(AVCHLHS, r) 1150 opset(AVCHLFS, r) 1151 opset(AVCHLGS, r) 1152 case AVFAEF: 1153 opset(AVFAEB, r) 1154 opset(AVFAEH, r) 1155 opset(AVFAEBS, r) 1156 opset(AVFAEHS, r) 1157 opset(AVFAEFS, r) 1158 opset(AVFAEZB, r) 1159 opset(AVFAEZH, r) 1160 opset(AVFAEZF, r) 1161 opset(AVFAEZBS, r) 1162 opset(AVFAEZHS, r) 1163 opset(AVFAEZFS, r) 1164 opset(AVFEEB, r) 1165 opset(AVFEEH, r) 1166 opset(AVFEEF, r) 1167 opset(AVFEEBS, r) 1168 opset(AVFEEHS, r) 1169 opset(AVFEEFS, r) 1170 opset(AVFEEZB, r) 1171 opset(AVFEEZH, r) 1172 opset(AVFEEZF, r) 1173 opset(AVFEEZBS, r) 1174 opset(AVFEEZHS, r) 1175 opset(AVFEEZFS, r) 1176 opset(AVFENEB, r) 1177 opset(AVFENEH, r) 1178 opset(AVFENEF, r) 1179 opset(AVFENEBS, r) 1180 opset(AVFENEHS, r) 1181 opset(AVFENEFS, r) 1182 opset(AVFENEZB, r) 1183 opset(AVFENEZH, r) 1184 opset(AVFENEZF, r) 1185 opset(AVFENEZBS, r) 1186 opset(AVFENEZHS, r) 1187 opset(AVFENEZFS, r) 1188 case AVPKSG: 1189 opset(AVPKSH, r) 1190 opset(AVPKSF, r) 1191 opset(AVPKSHS, r) 1192 opset(AVPKSFS, r) 1193 opset(AVPKSGS, r) 1194 opset(AVPKLSH, r) 1195 opset(AVPKLSF, r) 1196 opset(AVPKLSG, r) 1197 opset(AVPKLSHS, r) 1198 opset(AVPKLSFS, r) 1199 opset(AVPKLSGS, r) 1200 case AVAQ: 1201 opset(AVAB, r) 1202 opset(AVAH, r) 1203 opset(AVAF, r) 1204 opset(AVAG, r) 1205 opset(AVACCB, r) 1206 opset(AVACCH, r) 1207 opset(AVACCF, r) 1208 opset(AVACCG, r) 1209 opset(AVACCQ, r) 1210 opset(AVN, r) 1211 opset(AVNC, r) 1212 opset(AVAVGB, r) 1213 opset(AVAVGH, r) 1214 opset(AVAVGF, r) 1215 opset(AVAVGG, r) 1216 opset(AVAVGLB, r) 1217 opset(AVAVGLH, r) 1218 opset(AVAVGLF, r) 1219 opset(AVAVGLG, r) 1220 opset(AVCKSM, r) 1221 opset(AVX, r) 1222 opset(AVFADB, r) 1223 opset(AWFADB, r) 1224 opset(AVFCEDB, r) 1225 opset(AVFCEDBS, r) 1226 opset(AWFCEDB, r) 1227 opset(AWFCEDBS, r) 1228 opset(AVFCHDB, r) 1229 opset(AVFCHDBS, r) 1230 opset(AWFCHDB, r) 1231 opset(AWFCHDBS, r) 1232 opset(AVFCHEDB, r) 1233 opset(AVFCHEDBS, r) 1234 opset(AWFCHEDB, r) 1235 opset(AWFCHEDBS, r) 1236 opset(AVFMDB, r) 1237 opset(AWFMDB, r) 1238 opset(AVGFMB, r) 1239 opset(AVGFMH, r) 1240 opset(AVGFMF, r) 1241 opset(AVGFMG, r) 1242 opset(AVMXB, r) 1243 opset(AVMXH, r) 1244 opset(AVMXF, r) 1245 opset(AVMXG, r) 1246 opset(AVMXLB, r) 1247 opset(AVMXLH, r) 1248 opset(AVMXLF, r) 1249 opset(AVMXLG, r) 1250 opset(AVMNB, r) 1251 opset(AVMNH, r) 1252 opset(AVMNF, r) 1253 opset(AVMNG, r) 1254 opset(AVMNLB, r) 1255 opset(AVMNLH, r) 1256 opset(AVMNLF, r) 1257 opset(AVMNLG, r) 1258 opset(AVMRHB, r) 1259 opset(AVMRHH, r) 1260 opset(AVMRHF, r) 1261 opset(AVMRHG, r) 1262 opset(AVMRLB, r) 1263 opset(AVMRLH, r) 1264 opset(AVMRLF, r) 1265 opset(AVMRLG, r) 1266 opset(AVMEB, r) 1267 opset(AVMEH, r) 1268 opset(AVMEF, r) 1269 opset(AVMLEB, r) 1270 opset(AVMLEH, r) 1271 opset(AVMLEF, r) 1272 opset(AVMOB, r) 1273 opset(AVMOH, r) 1274 opset(AVMOF, r) 1275 opset(AVMLOB, r) 1276 opset(AVMLOH, r) 1277 opset(AVMLOF, r) 1278 opset(AVMHB, r) 1279 opset(AVMHH, r) 1280 opset(AVMHF, r) 1281 opset(AVMLHB, r) 1282 opset(AVMLHH, r) 1283 opset(AVMLHF, r) 1284 opset(AVMLH, r) 1285 opset(AVMLHW, r) 1286 opset(AVMLF, r) 1287 opset(AVNO, r) 1288 opset(AVO, r) 1289 opset(AVPKH, r) 1290 opset(AVPKF, r) 1291 opset(AVPKG, r) 1292 opset(AVSUMGH, r) 1293 opset(AVSUMGF, r) 1294 opset(AVSUMQF, r) 1295 opset(AVSUMQG, r) 1296 opset(AVSUMB, r) 1297 opset(AVSUMH, r) 1298 case AVERLLVG: 1299 opset(AVERLLVB, r) 1300 opset(AVERLLVH, r) 1301 opset(AVERLLVF, r) 1302 opset(AVESLVB, r) 1303 opset(AVESLVH, r) 1304 opset(AVESLVF, r) 1305 opset(AVESLVG, r) 1306 opset(AVESRAVB, r) 1307 opset(AVESRAVH, r) 1308 opset(AVESRAVF, r) 1309 opset(AVESRAVG, r) 1310 opset(AVESRLVB, r) 1311 opset(AVESRLVH, r) 1312 opset(AVESRLVF, r) 1313 opset(AVESRLVG, r) 1314 opset(AVFDDB, r) 1315 opset(AWFDDB, r) 1316 opset(AVFSDB, r) 1317 opset(AWFSDB, r) 1318 opset(AVSL, r) 1319 opset(AVSLB, r) 1320 opset(AVSRA, r) 1321 opset(AVSRAB, r) 1322 opset(AVSRL, r) 1323 opset(AVSRLB, r) 1324 opset(AVSF, r) 1325 opset(AVSG, r) 1326 opset(AVSQ, r) 1327 opset(AVSCBIB, r) 1328 opset(AVSCBIH, r) 1329 opset(AVSCBIF, r) 1330 opset(AVSCBIG, r) 1331 opset(AVSCBIQ, r) 1332 case AVACQ: 1333 opset(AVACCCQ, r) 1334 opset(AVGFMAB, r) 1335 opset(AVGFMAH, r) 1336 opset(AVGFMAF, r) 1337 opset(AVGFMAG, r) 1338 opset(AVMALB, r) 1339 opset(AVMALHW, r) 1340 opset(AVMALF, r) 1341 opset(AVMAHB, r) 1342 opset(AVMAHH, r) 1343 opset(AVMAHF, r) 1344 opset(AVMALHB, r) 1345 opset(AVMALHH, r) 1346 opset(AVMALHF, r) 1347 opset(AVMAEB, r) 1348 opset(AVMAEH, r) 1349 opset(AVMAEF, r) 1350 opset(AVMALEB, r) 1351 opset(AVMALEH, r) 1352 opset(AVMALEF, r) 1353 opset(AVMAOB, r) 1354 opset(AVMAOH, r) 1355 opset(AVMAOF, r) 1356 opset(AVMALOB, r) 1357 opset(AVMALOH, r) 1358 opset(AVMALOF, r) 1359 opset(AVSTRCB, r) 1360 opset(AVSTRCH, r) 1361 opset(AVSTRCF, r) 1362 opset(AVSTRCBS, r) 1363 opset(AVSTRCHS, r) 1364 opset(AVSTRCFS, r) 1365 opset(AVSTRCZB, r) 1366 opset(AVSTRCZH, r) 1367 opset(AVSTRCZF, r) 1368 opset(AVSTRCZBS, r) 1369 opset(AVSTRCZHS, r) 1370 opset(AVSTRCZFS, r) 1371 opset(AVSBCBIQ, r) 1372 opset(AVSBIQ, r) 1373 case AVSEL: 1374 opset(AVFMADB, r) 1375 opset(AWFMADB, r) 1376 opset(AVFMSDB, r) 1377 opset(AWFMSDB, r) 1378 opset(AVPERM, r) 1379 } 1380 } 1381 } 1382 1383 const ( 1384 op_A uint32 = 0x5A00 // FORMAT_RX1 ADD (32) 1385 op_AD uint32 = 0x6A00 // FORMAT_RX1 ADD NORMALIZED (long HFP) 1386 op_ADB uint32 = 0xED1A // FORMAT_RXE ADD (long BFP) 1387 op_ADBR uint32 = 0xB31A // FORMAT_RRE ADD (long BFP) 1388 op_ADR uint32 = 0x2A00 // FORMAT_RR ADD NORMALIZED (long HFP) 1389 op_ADTR uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1390 op_ADTRA uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1391 op_AE uint32 = 0x7A00 // FORMAT_RX1 ADD NORMALIZED (short HFP) 1392 op_AEB uint32 = 0xED0A // FORMAT_RXE ADD (short BFP) 1393 op_AEBR uint32 = 0xB30A // FORMAT_RRE ADD (short BFP) 1394 op_AER uint32 = 0x3A00 // FORMAT_RR ADD NORMALIZED (short HFP) 1395 op_AFI uint32 = 0xC209 // FORMAT_RIL1 ADD IMMEDIATE (32) 1396 op_AG uint32 = 0xE308 // FORMAT_RXY1 ADD (64) 1397 op_AGF uint32 = 0xE318 // FORMAT_RXY1 ADD (64<-32) 1398 op_AGFI uint32 = 0xC208 // FORMAT_RIL1 ADD IMMEDIATE (64<-32) 1399 op_AGFR uint32 = 0xB918 // FORMAT_RRE ADD (64<-32) 1400 op_AGHI uint32 = 0xA70B // FORMAT_RI1 ADD HALFWORD IMMEDIATE (64) 1401 op_AGHIK uint32 = 0xECD9 // FORMAT_RIE4 ADD IMMEDIATE (64<-16) 1402 op_AGR uint32 = 0xB908 // FORMAT_RRE ADD (64) 1403 op_AGRK uint32 = 0xB9E8 // FORMAT_RRF1 ADD (64) 1404 op_AGSI uint32 = 0xEB7A // FORMAT_SIY ADD IMMEDIATE (64<-8) 1405 op_AH uint32 = 0x4A00 // FORMAT_RX1 ADD HALFWORD 1406 op_AHHHR uint32 = 0xB9C8 // FORMAT_RRF1 ADD HIGH (32) 1407 op_AHHLR uint32 = 0xB9D8 // FORMAT_RRF1 ADD HIGH (32) 1408 op_AHI uint32 = 0xA70A // FORMAT_RI1 ADD HALFWORD IMMEDIATE (32) 1409 op_AHIK uint32 = 0xECD8 // FORMAT_RIE4 ADD IMMEDIATE (32<-16) 1410 op_AHY uint32 = 0xE37A // FORMAT_RXY1 ADD HALFWORD 1411 op_AIH uint32 = 0xCC08 // FORMAT_RIL1 ADD IMMEDIATE HIGH (32) 1412 op_AL uint32 = 0x5E00 // FORMAT_RX1 ADD LOGICAL (32) 1413 op_ALC uint32 = 0xE398 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (32) 1414 op_ALCG uint32 = 0xE388 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (64) 1415 op_ALCGR uint32 = 0xB988 // FORMAT_RRE ADD LOGICAL WITH CARRY (64) 1416 op_ALCR uint32 = 0xB998 // FORMAT_RRE ADD LOGICAL WITH CARRY (32) 1417 op_ALFI uint32 = 0xC20B // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (32) 1418 op_ALG uint32 = 0xE30A // FORMAT_RXY1 ADD LOGICAL (64) 1419 op_ALGF uint32 = 0xE31A // FORMAT_RXY1 ADD LOGICAL (64<-32) 1420 op_ALGFI uint32 = 0xC20A // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (64<-32) 1421 op_ALGFR uint32 = 0xB91A // FORMAT_RRE ADD LOGICAL (64<-32) 1422 op_ALGHSIK uint32 = 0xECDB // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16) 1423 op_ALGR uint32 = 0xB90A // FORMAT_RRE ADD LOGICAL (64) 1424 op_ALGRK uint32 = 0xB9EA // FORMAT_RRF1 ADD LOGICAL (64) 1425 op_ALGSI uint32 = 0xEB7E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8) 1426 op_ALHHHR uint32 = 0xB9CA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1427 op_ALHHLR uint32 = 0xB9DA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1428 op_ALHSIK uint32 = 0xECDA // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16) 1429 op_ALR uint32 = 0x1E00 // FORMAT_RR ADD LOGICAL (32) 1430 op_ALRK uint32 = 0xB9FA // FORMAT_RRF1 ADD LOGICAL (32) 1431 op_ALSI uint32 = 0xEB6E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8) 1432 op_ALSIH uint32 = 0xCC0A // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1433 op_ALSIHN uint32 = 0xCC0B // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1434 op_ALY uint32 = 0xE35E // FORMAT_RXY1 ADD LOGICAL (32) 1435 op_AP uint32 = 0xFA00 // FORMAT_SS2 ADD DECIMAL 1436 op_AR uint32 = 0x1A00 // FORMAT_RR ADD (32) 1437 op_ARK uint32 = 0xB9F8 // FORMAT_RRF1 ADD (32) 1438 op_ASI uint32 = 0xEB6A // FORMAT_SIY ADD IMMEDIATE (32<-8) 1439 op_AU uint32 = 0x7E00 // FORMAT_RX1 ADD UNNORMALIZED (short HFP) 1440 op_AUR uint32 = 0x3E00 // FORMAT_RR ADD UNNORMALIZED (short HFP) 1441 op_AW uint32 = 0x6E00 // FORMAT_RX1 ADD UNNORMALIZED (long HFP) 1442 op_AWR uint32 = 0x2E00 // FORMAT_RR ADD UNNORMALIZED (long HFP) 1443 op_AXBR uint32 = 0xB34A // FORMAT_RRE ADD (extended BFP) 1444 op_AXR uint32 = 0x3600 // FORMAT_RR ADD NORMALIZED (extended HFP) 1445 op_AXTR uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1446 op_AXTRA uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1447 op_AY uint32 = 0xE35A // FORMAT_RXY1 ADD (32) 1448 op_BAKR uint32 = 0xB240 // FORMAT_RRE BRANCH AND STACK 1449 op_BAL uint32 = 0x4500 // FORMAT_RX1 BRANCH AND LINK 1450 op_BALR uint32 = 0x0500 // FORMAT_RR BRANCH AND LINK 1451 op_BAS uint32 = 0x4D00 // FORMAT_RX1 BRANCH AND SAVE 1452 op_BASR uint32 = 0x0D00 // FORMAT_RR BRANCH AND SAVE 1453 op_BASSM uint32 = 0x0C00 // FORMAT_RR BRANCH AND SAVE AND SET MODE 1454 op_BC uint32 = 0x4700 // FORMAT_RX2 BRANCH ON CONDITION 1455 op_BCR uint32 = 0x0700 // FORMAT_RR BRANCH ON CONDITION 1456 op_BCT uint32 = 0x4600 // FORMAT_RX1 BRANCH ON COUNT (32) 1457 op_BCTG uint32 = 0xE346 // FORMAT_RXY1 BRANCH ON COUNT (64) 1458 op_BCTGR uint32 = 0xB946 // FORMAT_RRE BRANCH ON COUNT (64) 1459 op_BCTR uint32 = 0x0600 // FORMAT_RR BRANCH ON COUNT (32) 1460 op_BPP uint32 = 0xC700 // FORMAT_SMI BRANCH PREDICTION PRELOAD 1461 op_BPRP uint32 = 0xC500 // FORMAT_MII BRANCH PREDICTION RELATIVE PRELOAD 1462 op_BRAS uint32 = 0xA705 // FORMAT_RI2 BRANCH RELATIVE AND SAVE 1463 op_BRASL uint32 = 0xC005 // FORMAT_RIL2 BRANCH RELATIVE AND SAVE LONG 1464 op_BRC uint32 = 0xA704 // FORMAT_RI3 BRANCH RELATIVE ON CONDITION 1465 op_BRCL uint32 = 0xC004 // FORMAT_RIL3 BRANCH RELATIVE ON CONDITION LONG 1466 op_BRCT uint32 = 0xA706 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (32) 1467 op_BRCTG uint32 = 0xA707 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (64) 1468 op_BRCTH uint32 = 0xCC06 // FORMAT_RIL2 BRANCH RELATIVE ON COUNT HIGH (32) 1469 op_BRXH uint32 = 0x8400 // FORMAT_RSI BRANCH RELATIVE ON INDEX HIGH (32) 1470 op_BRXHG uint32 = 0xEC44 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX HIGH (64) 1471 op_BRXLE uint32 = 0x8500 // FORMAT_RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32) 1472 op_BRXLG uint32 = 0xEC45 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX LOW OR EQ. (64) 1473 op_BSA uint32 = 0xB25A // FORMAT_RRE BRANCH AND SET AUTHORITY 1474 op_BSG uint32 = 0xB258 // FORMAT_RRE BRANCH IN SUBSPACE GROUP 1475 op_BSM uint32 = 0x0B00 // FORMAT_RR BRANCH AND SET MODE 1476 op_BXH uint32 = 0x8600 // FORMAT_RS1 BRANCH ON INDEX HIGH (32) 1477 op_BXHG uint32 = 0xEB44 // FORMAT_RSY1 BRANCH ON INDEX HIGH (64) 1478 op_BXLE uint32 = 0x8700 // FORMAT_RS1 BRANCH ON INDEX LOW OR EQUAL (32) 1479 op_BXLEG uint32 = 0xEB45 // FORMAT_RSY1 BRANCH ON INDEX LOW OR EQUAL (64) 1480 op_C uint32 = 0x5900 // FORMAT_RX1 COMPARE (32) 1481 op_CD uint32 = 0x6900 // FORMAT_RX1 COMPARE (long HFP) 1482 op_CDB uint32 = 0xED19 // FORMAT_RXE COMPARE (long BFP) 1483 op_CDBR uint32 = 0xB319 // FORMAT_RRE COMPARE (long BFP) 1484 op_CDFBR uint32 = 0xB395 // FORMAT_RRE CONVERT FROM FIXED (32 to long BFP) 1485 op_CDFBRA uint32 = 0xB395 // FORMAT_RRF5 CONVERT FROM FIXED (32 to long BFP) 1486 op_CDFR uint32 = 0xB3B5 // FORMAT_RRE CONVERT FROM FIXED (32 to long HFP) 1487 op_CDFTR uint32 = 0xB951 // FORMAT_RRE CONVERT FROM FIXED (32 to long DFP) 1488 op_CDGBR uint32 = 0xB3A5 // FORMAT_RRE CONVERT FROM FIXED (64 to long BFP) 1489 op_CDGBRA uint32 = 0xB3A5 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long BFP) 1490 op_CDGR uint32 = 0xB3C5 // FORMAT_RRE CONVERT FROM FIXED (64 to long HFP) 1491 op_CDGTR uint32 = 0xB3F1 // FORMAT_RRE CONVERT FROM FIXED (64 to long DFP) 1492 op_CDGTRA uint32 = 0xB3F1 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long DFP) 1493 op_CDLFBR uint32 = 0xB391 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long BFP) 1494 op_CDLFTR uint32 = 0xB953 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long DFP) 1495 op_CDLGBR uint32 = 0xB3A1 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long BFP) 1496 op_CDLGTR uint32 = 0xB952 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long DFP) 1497 op_CDR uint32 = 0x2900 // FORMAT_RR COMPARE (long HFP) 1498 op_CDS uint32 = 0xBB00 // FORMAT_RS1 COMPARE DOUBLE AND SWAP (32) 1499 op_CDSG uint32 = 0xEB3E // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (64) 1500 op_CDSTR uint32 = 0xB3F3 // FORMAT_RRE CONVERT FROM SIGNED PACKED (64 to long DFP) 1501 op_CDSY uint32 = 0xEB31 // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (32) 1502 op_CDTR uint32 = 0xB3E4 // FORMAT_RRE COMPARE (long DFP) 1503 op_CDUTR uint32 = 0xB3F2 // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP) 1504 op_CDZT uint32 = 0xEDAA // FORMAT_RSL CONVERT FROM ZONED (to long DFP) 1505 op_CE uint32 = 0x7900 // FORMAT_RX1 COMPARE (short HFP) 1506 op_CEB uint32 = 0xED09 // FORMAT_RXE COMPARE (short BFP) 1507 op_CEBR uint32 = 0xB309 // FORMAT_RRE COMPARE (short BFP) 1508 op_CEDTR uint32 = 0xB3F4 // FORMAT_RRE COMPARE BIASED EXPONENT (long DFP) 1509 op_CEFBR uint32 = 0xB394 // FORMAT_RRE CONVERT FROM FIXED (32 to short BFP) 1510 op_CEFBRA uint32 = 0xB394 // FORMAT_RRF5 CONVERT FROM FIXED (32 to short BFP) 1511 op_CEFR uint32 = 0xB3B4 // FORMAT_RRE CONVERT FROM FIXED (32 to short HFP) 1512 op_CEGBR uint32 = 0xB3A4 // FORMAT_RRE CONVERT FROM FIXED (64 to short BFP) 1513 op_CEGBRA uint32 = 0xB3A4 // FORMAT_RRF5 CONVERT FROM FIXED (64 to short BFP) 1514 op_CEGR uint32 = 0xB3C4 // FORMAT_RRE CONVERT FROM FIXED (64 to short HFP) 1515 op_CELFBR uint32 = 0xB390 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to short BFP) 1516 op_CELGBR uint32 = 0xB3A0 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to short BFP) 1517 op_CER uint32 = 0x3900 // FORMAT_RR COMPARE (short HFP) 1518 op_CEXTR uint32 = 0xB3FC // FORMAT_RRE COMPARE BIASED EXPONENT (extended DFP) 1519 op_CFC uint32 = 0xB21A // FORMAT_S COMPARE AND FORM CODEWORD 1520 op_CFDBR uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1521 op_CFDBRA uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1522 op_CFDR uint32 = 0xB3B9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 32) 1523 op_CFDTR uint32 = 0xB941 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 32) 1524 op_CFEBR uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1525 op_CFEBRA uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1526 op_CFER uint32 = 0xB3B8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 32) 1527 op_CFI uint32 = 0xC20D // FORMAT_RIL1 COMPARE IMMEDIATE (32) 1528 op_CFXBR uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1529 op_CFXBRA uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1530 op_CFXR uint32 = 0xB3BA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 32) 1531 op_CFXTR uint32 = 0xB949 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 32) 1532 op_CG uint32 = 0xE320 // FORMAT_RXY1 COMPARE (64) 1533 op_CGDBR uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1534 op_CGDBRA uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1535 op_CGDR uint32 = 0xB3C9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 64) 1536 op_CGDTR uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1537 op_CGDTRA uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1538 op_CGEBR uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1539 op_CGEBRA uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1540 op_CGER uint32 = 0xB3C8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 64) 1541 op_CGF uint32 = 0xE330 // FORMAT_RXY1 COMPARE (64<-32) 1542 op_CGFI uint32 = 0xC20C // FORMAT_RIL1 COMPARE IMMEDIATE (64<-32) 1543 op_CGFR uint32 = 0xB930 // FORMAT_RRE COMPARE (64<-32) 1544 op_CGFRL uint32 = 0xC60C // FORMAT_RIL2 COMPARE RELATIVE LONG (64<-32) 1545 op_CGH uint32 = 0xE334 // FORMAT_RXY1 COMPARE HALFWORD (64<-16) 1546 op_CGHI uint32 = 0xA70F // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (64<-16) 1547 op_CGHRL uint32 = 0xC604 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (64<-16) 1548 op_CGHSI uint32 = 0xE558 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (64<-16) 1549 op_CGIB uint32 = 0xECFC // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (64<-8) 1550 op_CGIJ uint32 = 0xEC7C // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8) 1551 op_CGIT uint32 = 0xEC70 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (64<-16) 1552 op_CGR uint32 = 0xB920 // FORMAT_RRE COMPARE (64) 1553 op_CGRB uint32 = 0xECE4 // FORMAT_RRS COMPARE AND BRANCH (64) 1554 op_CGRJ uint32 = 0xEC64 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (64) 1555 op_CGRL uint32 = 0xC608 // FORMAT_RIL2 COMPARE RELATIVE LONG (64) 1556 op_CGRT uint32 = 0xB960 // FORMAT_RRF3 COMPARE AND TRAP (64) 1557 op_CGXBR uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1558 op_CGXBRA uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1559 op_CGXR uint32 = 0xB3CA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 64) 1560 op_CGXTR uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1561 op_CGXTRA uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1562 op_CH uint32 = 0x4900 // FORMAT_RX1 COMPARE HALFWORD (32<-16) 1563 op_CHF uint32 = 0xE3CD // FORMAT_RXY1 COMPARE HIGH (32) 1564 op_CHHR uint32 = 0xB9CD // FORMAT_RRE COMPARE HIGH (32) 1565 op_CHHSI uint32 = 0xE554 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (16) 1566 op_CHI uint32 = 0xA70E // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (32<-16) 1567 op_CHLR uint32 = 0xB9DD // FORMAT_RRE COMPARE HIGH (32) 1568 op_CHRL uint32 = 0xC605 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (32<-16) 1569 op_CHSI uint32 = 0xE55C // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (32<-16) 1570 op_CHY uint32 = 0xE379 // FORMAT_RXY1 COMPARE HALFWORD (32<-16) 1571 op_CIB uint32 = 0xECFE // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (32<-8) 1572 op_CIH uint32 = 0xCC0D // FORMAT_RIL1 COMPARE IMMEDIATE HIGH (32) 1573 op_CIJ uint32 = 0xEC7E // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8) 1574 op_CIT uint32 = 0xEC72 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (32<-16) 1575 op_CKSM uint32 = 0xB241 // FORMAT_RRE CHECKSUM 1576 op_CL uint32 = 0x5500 // FORMAT_RX1 COMPARE LOGICAL (32) 1577 op_CLC uint32 = 0xD500 // FORMAT_SS1 COMPARE LOGICAL (character) 1578 op_CLCL uint32 = 0x0F00 // FORMAT_RR COMPARE LOGICAL LONG 1579 op_CLCLE uint32 = 0xA900 // FORMAT_RS1 COMPARE LOGICAL LONG EXTENDED 1580 op_CLCLU uint32 = 0xEB8F // FORMAT_RSY1 COMPARE LOGICAL LONG UNICODE 1581 op_CLFDBR uint32 = 0xB39D // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 32) 1582 op_CLFDTR uint32 = 0xB943 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 32) 1583 op_CLFEBR uint32 = 0xB39C // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 32) 1584 op_CLFHSI uint32 = 0xE55D // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (32<-16) 1585 op_CLFI uint32 = 0xC20F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (32) 1586 op_CLFIT uint32 = 0xEC73 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16) 1587 op_CLFXBR uint32 = 0xB39E // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 32) 1588 op_CLFXTR uint32 = 0xB94B // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 32) 1589 op_CLG uint32 = 0xE321 // FORMAT_RXY1 COMPARE LOGICAL (64) 1590 op_CLGDBR uint32 = 0xB3AD // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 64) 1591 op_CLGDTR uint32 = 0xB942 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 64) 1592 op_CLGEBR uint32 = 0xB3AC // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 64) 1593 op_CLGF uint32 = 0xE331 // FORMAT_RXY1 COMPARE LOGICAL (64<-32) 1594 op_CLGFI uint32 = 0xC20E // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (64<-32) 1595 op_CLGFR uint32 = 0xB931 // FORMAT_RRE COMPARE LOGICAL (64<-32) 1596 op_CLGFRL uint32 = 0xC60E // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-32) 1597 op_CLGHRL uint32 = 0xC606 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-16) 1598 op_CLGHSI uint32 = 0xE559 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (64<-16) 1599 op_CLGIB uint32 = 0xECFD // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8) 1600 op_CLGIJ uint32 = 0xEC7D // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (64<-8) 1601 op_CLGIT uint32 = 0xEC71 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16) 1602 op_CLGR uint32 = 0xB921 // FORMAT_RRE COMPARE LOGICAL (64) 1603 op_CLGRB uint32 = 0xECE5 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (64) 1604 op_CLGRJ uint32 = 0xEC65 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (64) 1605 op_CLGRL uint32 = 0xC60A // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64) 1606 op_CLGRT uint32 = 0xB961 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (64) 1607 op_CLGT uint32 = 0xEB2B // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (64) 1608 op_CLGXBR uint32 = 0xB3AE // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 64) 1609 op_CLGXTR uint32 = 0xB94A // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 64) 1610 op_CLHF uint32 = 0xE3CF // FORMAT_RXY1 COMPARE LOGICAL HIGH (32) 1611 op_CLHHR uint32 = 0xB9CF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1612 op_CLHHSI uint32 = 0xE555 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (16) 1613 op_CLHLR uint32 = 0xB9DF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1614 op_CLHRL uint32 = 0xC607 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32<-16) 1615 op_CLI uint32 = 0x9500 // FORMAT_SI COMPARE LOGICAL (immediate) 1616 op_CLIB uint32 = 0xECFF // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8) 1617 op_CLIH uint32 = 0xCC0F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE HIGH (32) 1618 op_CLIJ uint32 = 0xEC7F // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (32<-8) 1619 op_CLIY uint32 = 0xEB55 // FORMAT_SIY COMPARE LOGICAL (immediate) 1620 op_CLM uint32 = 0xBD00 // FORMAT_RS2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1621 op_CLMH uint32 = 0xEB20 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (high) 1622 op_CLMY uint32 = 0xEB21 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1623 op_CLR uint32 = 0x1500 // FORMAT_RR COMPARE LOGICAL (32) 1624 op_CLRB uint32 = 0xECF7 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (32) 1625 op_CLRJ uint32 = 0xEC77 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (32) 1626 op_CLRL uint32 = 0xC60F // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32) 1627 op_CLRT uint32 = 0xB973 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (32) 1628 op_CLST uint32 = 0xB25D // FORMAT_RRE COMPARE LOGICAL STRING 1629 op_CLT uint32 = 0xEB23 // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (32) 1630 op_CLY uint32 = 0xE355 // FORMAT_RXY1 COMPARE LOGICAL (32) 1631 op_CMPSC uint32 = 0xB263 // FORMAT_RRE COMPRESSION CALL 1632 op_CP uint32 = 0xF900 // FORMAT_SS2 COMPARE DECIMAL 1633 op_CPSDR uint32 = 0xB372 // FORMAT_RRF2 COPY SIGN (long) 1634 op_CPYA uint32 = 0xB24D // FORMAT_RRE COPY ACCESS 1635 op_CR uint32 = 0x1900 // FORMAT_RR COMPARE (32) 1636 op_CRB uint32 = 0xECF6 // FORMAT_RRS COMPARE AND BRANCH (32) 1637 op_CRDTE uint32 = 0xB98F // FORMAT_RRF2 COMPARE AND REPLACE DAT TABLE ENTRY 1638 op_CRJ uint32 = 0xEC76 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (32) 1639 op_CRL uint32 = 0xC60D // FORMAT_RIL2 COMPARE RELATIVE LONG (32) 1640 op_CRT uint32 = 0xB972 // FORMAT_RRF3 COMPARE AND TRAP (32) 1641 op_CS uint32 = 0xBA00 // FORMAT_RS1 COMPARE AND SWAP (32) 1642 op_CSCH uint32 = 0xB230 // FORMAT_S CLEAR SUBCHANNEL 1643 op_CSDTR uint32 = 0xB3E3 // FORMAT_RRF4 CONVERT TO SIGNED PACKED (long DFP to 64) 1644 op_CSG uint32 = 0xEB30 // FORMAT_RSY1 COMPARE AND SWAP (64) 1645 op_CSP uint32 = 0xB250 // FORMAT_RRE COMPARE AND SWAP AND PURGE 1646 op_CSPG uint32 = 0xB98A // FORMAT_RRE COMPARE AND SWAP AND PURGE 1647 op_CSST uint32 = 0xC802 // FORMAT_SSF COMPARE AND SWAP AND STORE 1648 op_CSXTR uint32 = 0xB3EB // FORMAT_RRF4 CONVERT TO SIGNED PACKED (extended DFP to 128) 1649 op_CSY uint32 = 0xEB14 // FORMAT_RSY1 COMPARE AND SWAP (32) 1650 op_CU12 uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-16 1651 op_CU14 uint32 = 0xB9B0 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-32 1652 op_CU21 uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-8 1653 op_CU24 uint32 = 0xB9B1 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-32 1654 op_CU41 uint32 = 0xB9B2 // FORMAT_RRE CONVERT UTF-32 TO UTF-8 1655 op_CU42 uint32 = 0xB9B3 // FORMAT_RRE CONVERT UTF-32 TO UTF-16 1656 op_CUDTR uint32 = 0xB3E2 // FORMAT_RRE CONVERT TO UNSIGNED PACKED (long DFP to 64) 1657 op_CUSE uint32 = 0xB257 // FORMAT_RRE COMPARE UNTIL SUBSTRING EQUAL 1658 op_CUTFU uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UNICODE 1659 op_CUUTF uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UNICODE TO UTF-8 1660 op_CUXTR uint32 = 0xB3EA // FORMAT_RRE CONVERT TO UNSIGNED PACKED (extended DFP to 128) 1661 op_CVB uint32 = 0x4F00 // FORMAT_RX1 CONVERT TO BINARY (32) 1662 op_CVBG uint32 = 0xE30E // FORMAT_RXY1 CONVERT TO BINARY (64) 1663 op_CVBY uint32 = 0xE306 // FORMAT_RXY1 CONVERT TO BINARY (32) 1664 op_CVD uint32 = 0x4E00 // FORMAT_RX1 CONVERT TO DECIMAL (32) 1665 op_CVDG uint32 = 0xE32E // FORMAT_RXY1 CONVERT TO DECIMAL (64) 1666 op_CVDY uint32 = 0xE326 // FORMAT_RXY1 CONVERT TO DECIMAL (32) 1667 op_CXBR uint32 = 0xB349 // FORMAT_RRE COMPARE (extended BFP) 1668 op_CXFBR uint32 = 0xB396 // FORMAT_RRE CONVERT FROM FIXED (32 to extended BFP) 1669 op_CXFBRA uint32 = 0xB396 // FORMAT_RRF5 CONVERT FROM FIXED (32 to extended BFP) 1670 op_CXFR uint32 = 0xB3B6 // FORMAT_RRE CONVERT FROM FIXED (32 to extended HFP) 1671 op_CXFTR uint32 = 0xB959 // FORMAT_RRE CONVERT FROM FIXED (32 to extended DFP) 1672 op_CXGBR uint32 = 0xB3A6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended BFP) 1673 op_CXGBRA uint32 = 0xB3A6 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended BFP) 1674 op_CXGR uint32 = 0xB3C6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended HFP) 1675 op_CXGTR uint32 = 0xB3F9 // FORMAT_RRE CONVERT FROM FIXED (64 to extended DFP) 1676 op_CXGTRA uint32 = 0xB3F9 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended DFP) 1677 op_CXLFBR uint32 = 0xB392 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended BFP) 1678 op_CXLFTR uint32 = 0xB95B // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended DFP) 1679 op_CXLGBR uint32 = 0xB3A2 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended BFP) 1680 op_CXLGTR uint32 = 0xB95A // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended DFP) 1681 op_CXR uint32 = 0xB369 // FORMAT_RRE COMPARE (extended HFP) 1682 op_CXSTR uint32 = 0xB3FB // FORMAT_RRE CONVERT FROM SIGNED PACKED (128 to extended DFP) 1683 op_CXTR uint32 = 0xB3EC // FORMAT_RRE COMPARE (extended DFP) 1684 op_CXUTR uint32 = 0xB3FA // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) 1685 op_CXZT uint32 = 0xEDAB // FORMAT_RSL CONVERT FROM ZONED (to extended DFP) 1686 op_CY uint32 = 0xE359 // FORMAT_RXY1 COMPARE (32) 1687 op_CZDT uint32 = 0xEDA8 // FORMAT_RSL CONVERT TO ZONED (from long DFP) 1688 op_CZXT uint32 = 0xEDA9 // FORMAT_RSL CONVERT TO ZONED (from extended DFP) 1689 op_D uint32 = 0x5D00 // FORMAT_RX1 DIVIDE (32<-64) 1690 op_DD uint32 = 0x6D00 // FORMAT_RX1 DIVIDE (long HFP) 1691 op_DDB uint32 = 0xED1D // FORMAT_RXE DIVIDE (long BFP) 1692 op_DDBR uint32 = 0xB31D // FORMAT_RRE DIVIDE (long BFP) 1693 op_DDR uint32 = 0x2D00 // FORMAT_RR DIVIDE (long HFP) 1694 op_DDTR uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1695 op_DDTRA uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1696 op_DE uint32 = 0x7D00 // FORMAT_RX1 DIVIDE (short HFP) 1697 op_DEB uint32 = 0xED0D // FORMAT_RXE DIVIDE (short BFP) 1698 op_DEBR uint32 = 0xB30D // FORMAT_RRE DIVIDE (short BFP) 1699 op_DER uint32 = 0x3D00 // FORMAT_RR DIVIDE (short HFP) 1700 op_DIDBR uint32 = 0xB35B // FORMAT_RRF2 DIVIDE TO INTEGER (long BFP) 1701 op_DIEBR uint32 = 0xB353 // FORMAT_RRF2 DIVIDE TO INTEGER (short BFP) 1702 op_DL uint32 = 0xE397 // FORMAT_RXY1 DIVIDE LOGICAL (32<-64) 1703 op_DLG uint32 = 0xE387 // FORMAT_RXY1 DIVIDE LOGICAL (64<-128) 1704 op_DLGR uint32 = 0xB987 // FORMAT_RRE DIVIDE LOGICAL (64<-128) 1705 op_DLR uint32 = 0xB997 // FORMAT_RRE DIVIDE LOGICAL (32<-64) 1706 op_DP uint32 = 0xFD00 // FORMAT_SS2 DIVIDE DECIMAL 1707 op_DR uint32 = 0x1D00 // FORMAT_RR DIVIDE (32<-64) 1708 op_DSG uint32 = 0xE30D // FORMAT_RXY1 DIVIDE SINGLE (64) 1709 op_DSGF uint32 = 0xE31D // FORMAT_RXY1 DIVIDE SINGLE (64<-32) 1710 op_DSGFR uint32 = 0xB91D // FORMAT_RRE DIVIDE SINGLE (64<-32) 1711 op_DSGR uint32 = 0xB90D // FORMAT_RRE DIVIDE SINGLE (64) 1712 op_DXBR uint32 = 0xB34D // FORMAT_RRE DIVIDE (extended BFP) 1713 op_DXR uint32 = 0xB22D // FORMAT_RRE DIVIDE (extended HFP) 1714 op_DXTR uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1715 op_DXTRA uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1716 op_EAR uint32 = 0xB24F // FORMAT_RRE EXTRACT ACCESS 1717 op_ECAG uint32 = 0xEB4C // FORMAT_RSY1 EXTRACT CACHE ATTRIBUTE 1718 op_ECTG uint32 = 0xC801 // FORMAT_SSF EXTRACT CPU TIME 1719 op_ED uint32 = 0xDE00 // FORMAT_SS1 EDIT 1720 op_EDMK uint32 = 0xDF00 // FORMAT_SS1 EDIT AND MARK 1721 op_EEDTR uint32 = 0xB3E5 // FORMAT_RRE EXTRACT BIASED EXPONENT (long DFP to 64) 1722 op_EEXTR uint32 = 0xB3ED // FORMAT_RRE EXTRACT BIASED EXPONENT (extended DFP to 64) 1723 op_EFPC uint32 = 0xB38C // FORMAT_RRE EXTRACT FPC 1724 op_EPAIR uint32 = 0xB99A // FORMAT_RRE EXTRACT PRIMARY ASN AND INSTANCE 1725 op_EPAR uint32 = 0xB226 // FORMAT_RRE EXTRACT PRIMARY ASN 1726 op_EPSW uint32 = 0xB98D // FORMAT_RRE EXTRACT PSW 1727 op_EREG uint32 = 0xB249 // FORMAT_RRE EXTRACT STACKED REGISTERS (32) 1728 op_EREGG uint32 = 0xB90E // FORMAT_RRE EXTRACT STACKED REGISTERS (64) 1729 op_ESAIR uint32 = 0xB99B // FORMAT_RRE EXTRACT SECONDARY ASN AND INSTANCE 1730 op_ESAR uint32 = 0xB227 // FORMAT_RRE EXTRACT SECONDARY ASN 1731 op_ESDTR uint32 = 0xB3E7 // FORMAT_RRE EXTRACT SIGNIFICANCE (long DFP) 1732 op_ESEA uint32 = 0xB99D // FORMAT_RRE EXTRACT AND SET EXTENDED AUTHORITY 1733 op_ESTA uint32 = 0xB24A // FORMAT_RRE EXTRACT STACKED STATE 1734 op_ESXTR uint32 = 0xB3EF // FORMAT_RRE EXTRACT SIGNIFICANCE (extended DFP) 1735 op_ETND uint32 = 0xB2EC // FORMAT_RRE EXTRACT TRANSACTION NESTING DEPTH 1736 op_EX uint32 = 0x4400 // FORMAT_RX1 EXECUTE 1737 op_EXRL uint32 = 0xC600 // FORMAT_RIL2 EXECUTE RELATIVE LONG 1738 op_FIDBR uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1739 op_FIDBRA uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1740 op_FIDR uint32 = 0xB37F // FORMAT_RRE LOAD FP INTEGER (long HFP) 1741 op_FIDTR uint32 = 0xB3D7 // FORMAT_RRF5 LOAD FP INTEGER (long DFP) 1742 op_FIEBR uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1743 op_FIEBRA uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1744 op_FIER uint32 = 0xB377 // FORMAT_RRE LOAD FP INTEGER (short HFP) 1745 op_FIXBR uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1746 op_FIXBRA uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1747 op_FIXR uint32 = 0xB367 // FORMAT_RRE LOAD FP INTEGER (extended HFP) 1748 op_FIXTR uint32 = 0xB3DF // FORMAT_RRF5 LOAD FP INTEGER (extended DFP) 1749 op_FLOGR uint32 = 0xB983 // FORMAT_RRE FIND LEFTMOST ONE 1750 op_HDR uint32 = 0x2400 // FORMAT_RR HALVE (long HFP) 1751 op_HER uint32 = 0x3400 // FORMAT_RR HALVE (short HFP) 1752 op_HSCH uint32 = 0xB231 // FORMAT_S HALT SUBCHANNEL 1753 op_IAC uint32 = 0xB224 // FORMAT_RRE INSERT ADDRESS SPACE CONTROL 1754 op_IC uint32 = 0x4300 // FORMAT_RX1 INSERT CHARACTER 1755 op_ICM uint32 = 0xBF00 // FORMAT_RS2 INSERT CHARACTERS UNDER MASK (low) 1756 op_ICMH uint32 = 0xEB80 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (high) 1757 op_ICMY uint32 = 0xEB81 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (low) 1758 op_ICY uint32 = 0xE373 // FORMAT_RXY1 INSERT CHARACTER 1759 op_IDTE uint32 = 0xB98E // FORMAT_RRF2 INVALIDATE DAT TABLE ENTRY 1760 op_IEDTR uint32 = 0xB3F6 // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to long DFP) 1761 op_IEXTR uint32 = 0xB3FE // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to extended DFP) 1762 op_IIHF uint32 = 0xC008 // FORMAT_RIL1 INSERT IMMEDIATE (high) 1763 op_IIHH uint32 = 0xA500 // FORMAT_RI1 INSERT IMMEDIATE (high high) 1764 op_IIHL uint32 = 0xA501 // FORMAT_RI1 INSERT IMMEDIATE (high low) 1765 op_IILF uint32 = 0xC009 // FORMAT_RIL1 INSERT IMMEDIATE (low) 1766 op_IILH uint32 = 0xA502 // FORMAT_RI1 INSERT IMMEDIATE (low high) 1767 op_IILL uint32 = 0xA503 // FORMAT_RI1 INSERT IMMEDIATE (low low) 1768 op_IPK uint32 = 0xB20B // FORMAT_S INSERT PSW KEY 1769 op_IPM uint32 = 0xB222 // FORMAT_RRE INSERT PROGRAM MASK 1770 op_IPTE uint32 = 0xB221 // FORMAT_RRF1 INVALIDATE PAGE TABLE ENTRY 1771 op_ISKE uint32 = 0xB229 // FORMAT_RRE INSERT STORAGE KEY EXTENDED 1772 op_IVSK uint32 = 0xB223 // FORMAT_RRE INSERT VIRTUAL STORAGE KEY 1773 op_KDB uint32 = 0xED18 // FORMAT_RXE COMPARE AND SIGNAL (long BFP) 1774 op_KDBR uint32 = 0xB318 // FORMAT_RRE COMPARE AND SIGNAL (long BFP) 1775 op_KDTR uint32 = 0xB3E0 // FORMAT_RRE COMPARE AND SIGNAL (long DFP) 1776 op_KEB uint32 = 0xED08 // FORMAT_RXE COMPARE AND SIGNAL (short BFP) 1777 op_KEBR uint32 = 0xB308 // FORMAT_RRE COMPARE AND SIGNAL (short BFP) 1778 op_KIMD uint32 = 0xB93E // FORMAT_RRE COMPUTE INTERMEDIATE MESSAGE DIGEST 1779 op_KLMD uint32 = 0xB93F // FORMAT_RRE COMPUTE LAST MESSAGE DIGEST 1780 op_KM uint32 = 0xB92E // FORMAT_RRE CIPHER MESSAGE 1781 op_KMAC uint32 = 0xB91E // FORMAT_RRE COMPUTE MESSAGE AUTHENTICATION CODE 1782 op_KMC uint32 = 0xB92F // FORMAT_RRE CIPHER MESSAGE WITH CHAINING 1783 op_KMCTR uint32 = 0xB92D // FORMAT_RRF2 CIPHER MESSAGE WITH COUNTER 1784 op_KMF uint32 = 0xB92A // FORMAT_RRE CIPHER MESSAGE WITH CFB 1785 op_KMO uint32 = 0xB92B // FORMAT_RRE CIPHER MESSAGE WITH OFB 1786 op_KXBR uint32 = 0xB348 // FORMAT_RRE COMPARE AND SIGNAL (extended BFP) 1787 op_KXTR uint32 = 0xB3E8 // FORMAT_RRE COMPARE AND SIGNAL (extended DFP) 1788 op_L uint32 = 0x5800 // FORMAT_RX1 LOAD (32) 1789 op_LA uint32 = 0x4100 // FORMAT_RX1 LOAD ADDRESS 1790 op_LAA uint32 = 0xEBF8 // FORMAT_RSY1 LOAD AND ADD (32) 1791 op_LAAG uint32 = 0xEBE8 // FORMAT_RSY1 LOAD AND ADD (64) 1792 op_LAAL uint32 = 0xEBFA // FORMAT_RSY1 LOAD AND ADD LOGICAL (32) 1793 op_LAALG uint32 = 0xEBEA // FORMAT_RSY1 LOAD AND ADD LOGICAL (64) 1794 op_LAE uint32 = 0x5100 // FORMAT_RX1 LOAD ADDRESS EXTENDED 1795 op_LAEY uint32 = 0xE375 // FORMAT_RXY1 LOAD ADDRESS EXTENDED 1796 op_LAM uint32 = 0x9A00 // FORMAT_RS1 LOAD ACCESS MULTIPLE 1797 op_LAMY uint32 = 0xEB9A // FORMAT_RSY1 LOAD ACCESS MULTIPLE 1798 op_LAN uint32 = 0xEBF4 // FORMAT_RSY1 LOAD AND AND (32) 1799 op_LANG uint32 = 0xEBE4 // FORMAT_RSY1 LOAD AND AND (64) 1800 op_LAO uint32 = 0xEBF6 // FORMAT_RSY1 LOAD AND OR (32) 1801 op_LAOG uint32 = 0xEBE6 // FORMAT_RSY1 LOAD AND OR (64) 1802 op_LARL uint32 = 0xC000 // FORMAT_RIL2 LOAD ADDRESS RELATIVE LONG 1803 op_LASP uint32 = 0xE500 // FORMAT_SSE LOAD ADDRESS SPACE PARAMETERS 1804 op_LAT uint32 = 0xE39F // FORMAT_RXY1 LOAD AND TRAP (32L<-32) 1805 op_LAX uint32 = 0xEBF7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (32) 1806 op_LAXG uint32 = 0xEBE7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (64) 1807 op_LAY uint32 = 0xE371 // FORMAT_RXY1 LOAD ADDRESS 1808 op_LB uint32 = 0xE376 // FORMAT_RXY1 LOAD BYTE (32) 1809 op_LBH uint32 = 0xE3C0 // FORMAT_RXY1 LOAD BYTE HIGH (32<-8) 1810 op_LBR uint32 = 0xB926 // FORMAT_RRE LOAD BYTE (32) 1811 op_LCDBR uint32 = 0xB313 // FORMAT_RRE LOAD COMPLEMENT (long BFP) 1812 op_LCDFR uint32 = 0xB373 // FORMAT_RRE LOAD COMPLEMENT (long) 1813 op_LCDR uint32 = 0x2300 // FORMAT_RR LOAD COMPLEMENT (long HFP) 1814 op_LCEBR uint32 = 0xB303 // FORMAT_RRE LOAD COMPLEMENT (short BFP) 1815 op_LCER uint32 = 0x3300 // FORMAT_RR LOAD COMPLEMENT (short HFP) 1816 op_LCGFR uint32 = 0xB913 // FORMAT_RRE LOAD COMPLEMENT (64<-32) 1817 op_LCGR uint32 = 0xB903 // FORMAT_RRE LOAD COMPLEMENT (64) 1818 op_LCR uint32 = 0x1300 // FORMAT_RR LOAD COMPLEMENT (32) 1819 op_LCTL uint32 = 0xB700 // FORMAT_RS1 LOAD CONTROL (32) 1820 op_LCTLG uint32 = 0xEB2F // FORMAT_RSY1 LOAD CONTROL (64) 1821 op_LCXBR uint32 = 0xB343 // FORMAT_RRE LOAD COMPLEMENT (extended BFP) 1822 op_LCXR uint32 = 0xB363 // FORMAT_RRE LOAD COMPLEMENT (extended HFP) 1823 op_LD uint32 = 0x6800 // FORMAT_RX1 LOAD (long) 1824 op_LDE uint32 = 0xED24 // FORMAT_RXE LOAD LENGTHENED (short to long HFP) 1825 op_LDEB uint32 = 0xED04 // FORMAT_RXE LOAD LENGTHENED (short to long BFP) 1826 op_LDEBR uint32 = 0xB304 // FORMAT_RRE LOAD LENGTHENED (short to long BFP) 1827 op_LDER uint32 = 0xB324 // FORMAT_RRE LOAD LENGTHENED (short to long HFP) 1828 op_LDETR uint32 = 0xB3D4 // FORMAT_RRF4 LOAD LENGTHENED (short to long DFP) 1829 op_LDGR uint32 = 0xB3C1 // FORMAT_RRE LOAD FPR FROM GR (64 to long) 1830 op_LDR uint32 = 0x2800 // FORMAT_RR LOAD (long) 1831 op_LDXBR uint32 = 0xB345 // FORMAT_RRE LOAD ROUNDED (extended to long BFP) 1832 op_LDXBRA uint32 = 0xB345 // FORMAT_RRF5 LOAD ROUNDED (extended to long BFP) 1833 op_LDXR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1834 op_LDXTR uint32 = 0xB3DD // FORMAT_RRF5 LOAD ROUNDED (extended to long DFP) 1835 op_LDY uint32 = 0xED65 // FORMAT_RXY1 LOAD (long) 1836 op_LE uint32 = 0x7800 // FORMAT_RX1 LOAD (short) 1837 op_LEDBR uint32 = 0xB344 // FORMAT_RRE LOAD ROUNDED (long to short BFP) 1838 op_LEDBRA uint32 = 0xB344 // FORMAT_RRF5 LOAD ROUNDED (long to short BFP) 1839 op_LEDR uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1840 op_LEDTR uint32 = 0xB3D5 // FORMAT_RRF5 LOAD ROUNDED (long to short DFP) 1841 op_LER uint32 = 0x3800 // FORMAT_RR LOAD (short) 1842 op_LEXBR uint32 = 0xB346 // FORMAT_RRE LOAD ROUNDED (extended to short BFP) 1843 op_LEXBRA uint32 = 0xB346 // FORMAT_RRF5 LOAD ROUNDED (extended to short BFP) 1844 op_LEXR uint32 = 0xB366 // FORMAT_RRE LOAD ROUNDED (extended to short HFP) 1845 op_LEY uint32 = 0xED64 // FORMAT_RXY1 LOAD (short) 1846 op_LFAS uint32 = 0xB2BD // FORMAT_S LOAD FPC AND SIGNAL 1847 op_LFH uint32 = 0xE3CA // FORMAT_RXY1 LOAD HIGH (32) 1848 op_LFHAT uint32 = 0xE3C8 // FORMAT_RXY1 LOAD HIGH AND TRAP (32H<-32) 1849 op_LFPC uint32 = 0xB29D // FORMAT_S LOAD FPC 1850 op_LG uint32 = 0xE304 // FORMAT_RXY1 LOAD (64) 1851 op_LGAT uint32 = 0xE385 // FORMAT_RXY1 LOAD AND TRAP (64) 1852 op_LGB uint32 = 0xE377 // FORMAT_RXY1 LOAD BYTE (64) 1853 op_LGBR uint32 = 0xB906 // FORMAT_RRE LOAD BYTE (64) 1854 op_LGDR uint32 = 0xB3CD // FORMAT_RRE LOAD GR FROM FPR (long to 64) 1855 op_LGF uint32 = 0xE314 // FORMAT_RXY1 LOAD (64<-32) 1856 op_LGFI uint32 = 0xC001 // FORMAT_RIL1 LOAD IMMEDIATE (64<-32) 1857 op_LGFR uint32 = 0xB914 // FORMAT_RRE LOAD (64<-32) 1858 op_LGFRL uint32 = 0xC40C // FORMAT_RIL2 LOAD RELATIVE LONG (64<-32) 1859 op_LGH uint32 = 0xE315 // FORMAT_RXY1 LOAD HALFWORD (64) 1860 op_LGHI uint32 = 0xA709 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (64) 1861 op_LGHR uint32 = 0xB907 // FORMAT_RRE LOAD HALFWORD (64) 1862 op_LGHRL uint32 = 0xC404 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (64<-16) 1863 op_LGR uint32 = 0xB904 // FORMAT_RRE LOAD (64) 1864 op_LGRL uint32 = 0xC408 // FORMAT_RIL2 LOAD RELATIVE LONG (64) 1865 op_LH uint32 = 0x4800 // FORMAT_RX1 LOAD HALFWORD (32) 1866 op_LHH uint32 = 0xE3C4 // FORMAT_RXY1 LOAD HALFWORD HIGH (32<-16) 1867 op_LHI uint32 = 0xA708 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (32) 1868 op_LHR uint32 = 0xB927 // FORMAT_RRE LOAD HALFWORD (32) 1869 op_LHRL uint32 = 0xC405 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (32<-16) 1870 op_LHY uint32 = 0xE378 // FORMAT_RXY1 LOAD HALFWORD (32) 1871 op_LLC uint32 = 0xE394 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (32) 1872 op_LLCH uint32 = 0xE3C2 // FORMAT_RXY1 LOAD LOGICAL CHARACTER HIGH (32<-8) 1873 op_LLCR uint32 = 0xB994 // FORMAT_RRE LOAD LOGICAL CHARACTER (32) 1874 op_LLGC uint32 = 0xE390 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (64) 1875 op_LLGCR uint32 = 0xB984 // FORMAT_RRE LOAD LOGICAL CHARACTER (64) 1876 op_LLGF uint32 = 0xE316 // FORMAT_RXY1 LOAD LOGICAL (64<-32) 1877 op_LLGFAT uint32 = 0xE39D // FORMAT_RXY1 LOAD LOGICAL AND TRAP (64<-32) 1878 op_LLGFR uint32 = 0xB916 // FORMAT_RRE LOAD LOGICAL (64<-32) 1879 op_LLGFRL uint32 = 0xC40E // FORMAT_RIL2 LOAD LOGICAL RELATIVE LONG (64<-32) 1880 op_LLGH uint32 = 0xE391 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (64) 1881 op_LLGHR uint32 = 0xB985 // FORMAT_RRE LOAD LOGICAL HALFWORD (64) 1882 op_LLGHRL uint32 = 0xC406 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16) 1883 op_LLGT uint32 = 0xE317 // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS 1884 op_LLGTAT uint32 = 0xE39C // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31) 1885 op_LLGTR uint32 = 0xB917 // FORMAT_RRE LOAD LOGICAL THIRTY ONE BITS 1886 op_LLH uint32 = 0xE395 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (32) 1887 op_LLHH uint32 = 0xE3C6 // FORMAT_RXY1 LOAD LOGICAL HALFWORD HIGH (32<-16) 1888 op_LLHR uint32 = 0xB995 // FORMAT_RRE LOAD LOGICAL HALFWORD (32) 1889 op_LLHRL uint32 = 0xC402 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16) 1890 op_LLIHF uint32 = 0xC00E // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (high) 1891 op_LLIHH uint32 = 0xA50C // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high high) 1892 op_LLIHL uint32 = 0xA50D // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high low) 1893 op_LLILF uint32 = 0xC00F // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (low) 1894 op_LLILH uint32 = 0xA50E // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low high) 1895 op_LLILL uint32 = 0xA50F // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low low) 1896 op_LM uint32 = 0x9800 // FORMAT_RS1 LOAD MULTIPLE (32) 1897 op_LMD uint32 = 0xEF00 // FORMAT_SS5 LOAD MULTIPLE DISJOINT 1898 op_LMG uint32 = 0xEB04 // FORMAT_RSY1 LOAD MULTIPLE (64) 1899 op_LMH uint32 = 0xEB96 // FORMAT_RSY1 LOAD MULTIPLE HIGH 1900 op_LMY uint32 = 0xEB98 // FORMAT_RSY1 LOAD MULTIPLE (32) 1901 op_LNDBR uint32 = 0xB311 // FORMAT_RRE LOAD NEGATIVE (long BFP) 1902 op_LNDFR uint32 = 0xB371 // FORMAT_RRE LOAD NEGATIVE (long) 1903 op_LNDR uint32 = 0x2100 // FORMAT_RR LOAD NEGATIVE (long HFP) 1904 op_LNEBR uint32 = 0xB301 // FORMAT_RRE LOAD NEGATIVE (short BFP) 1905 op_LNER uint32 = 0x3100 // FORMAT_RR LOAD NEGATIVE (short HFP) 1906 op_LNGFR uint32 = 0xB911 // FORMAT_RRE LOAD NEGATIVE (64<-32) 1907 op_LNGR uint32 = 0xB901 // FORMAT_RRE LOAD NEGATIVE (64) 1908 op_LNR uint32 = 0x1100 // FORMAT_RR LOAD NEGATIVE (32) 1909 op_LNXBR uint32 = 0xB341 // FORMAT_RRE LOAD NEGATIVE (extended BFP) 1910 op_LNXR uint32 = 0xB361 // FORMAT_RRE LOAD NEGATIVE (extended HFP) 1911 op_LOC uint32 = 0xEBF2 // FORMAT_RSY2 LOAD ON CONDITION (32) 1912 op_LOCG uint32 = 0xEBE2 // FORMAT_RSY2 LOAD ON CONDITION (64) 1913 op_LOCGR uint32 = 0xB9E2 // FORMAT_RRF3 LOAD ON CONDITION (64) 1914 op_LOCR uint32 = 0xB9F2 // FORMAT_RRF3 LOAD ON CONDITION (32) 1915 op_LPD uint32 = 0xC804 // FORMAT_SSF LOAD PAIR DISJOINT (32) 1916 op_LPDBR uint32 = 0xB310 // FORMAT_RRE LOAD POSITIVE (long BFP) 1917 op_LPDFR uint32 = 0xB370 // FORMAT_RRE LOAD POSITIVE (long) 1918 op_LPDG uint32 = 0xC805 // FORMAT_SSF LOAD PAIR DISJOINT (64) 1919 op_LPDR uint32 = 0x2000 // FORMAT_RR LOAD POSITIVE (long HFP) 1920 op_LPEBR uint32 = 0xB300 // FORMAT_RRE LOAD POSITIVE (short BFP) 1921 op_LPER uint32 = 0x3000 // FORMAT_RR LOAD POSITIVE (short HFP) 1922 op_LPGFR uint32 = 0xB910 // FORMAT_RRE LOAD POSITIVE (64<-32) 1923 op_LPGR uint32 = 0xB900 // FORMAT_RRE LOAD POSITIVE (64) 1924 op_LPQ uint32 = 0xE38F // FORMAT_RXY1 LOAD PAIR FROM QUADWORD 1925 op_LPR uint32 = 0x1000 // FORMAT_RR LOAD POSITIVE (32) 1926 op_LPSW uint32 = 0x8200 // FORMAT_S LOAD PSW 1927 op_LPSWE uint32 = 0xB2B2 // FORMAT_S LOAD PSW EXTENDED 1928 op_LPTEA uint32 = 0xB9AA // FORMAT_RRF2 LOAD PAGE TABLE ENTRY ADDRESS 1929 op_LPXBR uint32 = 0xB340 // FORMAT_RRE LOAD POSITIVE (extended BFP) 1930 op_LPXR uint32 = 0xB360 // FORMAT_RRE LOAD POSITIVE (extended HFP) 1931 op_LR uint32 = 0x1800 // FORMAT_RR LOAD (32) 1932 op_LRA uint32 = 0xB100 // FORMAT_RX1 LOAD REAL ADDRESS (32) 1933 op_LRAG uint32 = 0xE303 // FORMAT_RXY1 LOAD REAL ADDRESS (64) 1934 op_LRAY uint32 = 0xE313 // FORMAT_RXY1 LOAD REAL ADDRESS (32) 1935 op_LRDR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1936 op_LRER uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1937 op_LRL uint32 = 0xC40D // FORMAT_RIL2 LOAD RELATIVE LONG (32) 1938 op_LRV uint32 = 0xE31E // FORMAT_RXY1 LOAD REVERSED (32) 1939 op_LRVG uint32 = 0xE30F // FORMAT_RXY1 LOAD REVERSED (64) 1940 op_LRVGR uint32 = 0xB90F // FORMAT_RRE LOAD REVERSED (64) 1941 op_LRVH uint32 = 0xE31F // FORMAT_RXY1 LOAD REVERSED (16) 1942 op_LRVR uint32 = 0xB91F // FORMAT_RRE LOAD REVERSED (32) 1943 op_LT uint32 = 0xE312 // FORMAT_RXY1 LOAD AND TEST (32) 1944 op_LTDBR uint32 = 0xB312 // FORMAT_RRE LOAD AND TEST (long BFP) 1945 op_LTDR uint32 = 0x2200 // FORMAT_RR LOAD AND TEST (long HFP) 1946 op_LTDTR uint32 = 0xB3D6 // FORMAT_RRE LOAD AND TEST (long DFP) 1947 op_LTEBR uint32 = 0xB302 // FORMAT_RRE LOAD AND TEST (short BFP) 1948 op_LTER uint32 = 0x3200 // FORMAT_RR LOAD AND TEST (short HFP) 1949 op_LTG uint32 = 0xE302 // FORMAT_RXY1 LOAD AND TEST (64) 1950 op_LTGF uint32 = 0xE332 // FORMAT_RXY1 LOAD AND TEST (64<-32) 1951 op_LTGFR uint32 = 0xB912 // FORMAT_RRE LOAD AND TEST (64<-32) 1952 op_LTGR uint32 = 0xB902 // FORMAT_RRE LOAD AND TEST (64) 1953 op_LTR uint32 = 0x1200 // FORMAT_RR LOAD AND TEST (32) 1954 op_LTXBR uint32 = 0xB342 // FORMAT_RRE LOAD AND TEST (extended BFP) 1955 op_LTXR uint32 = 0xB362 // FORMAT_RRE LOAD AND TEST (extended HFP) 1956 op_LTXTR uint32 = 0xB3DE // FORMAT_RRE LOAD AND TEST (extended DFP) 1957 op_LURA uint32 = 0xB24B // FORMAT_RRE LOAD USING REAL ADDRESS (32) 1958 op_LURAG uint32 = 0xB905 // FORMAT_RRE LOAD USING REAL ADDRESS (64) 1959 op_LXD uint32 = 0xED25 // FORMAT_RXE LOAD LENGTHENED (long to extended HFP) 1960 op_LXDB uint32 = 0xED05 // FORMAT_RXE LOAD LENGTHENED (long to extended BFP) 1961 op_LXDBR uint32 = 0xB305 // FORMAT_RRE LOAD LENGTHENED (long to extended BFP) 1962 op_LXDR uint32 = 0xB325 // FORMAT_RRE LOAD LENGTHENED (long to extended HFP) 1963 op_LXDTR uint32 = 0xB3DC // FORMAT_RRF4 LOAD LENGTHENED (long to extended DFP) 1964 op_LXE uint32 = 0xED26 // FORMAT_RXE LOAD LENGTHENED (short to extended HFP) 1965 op_LXEB uint32 = 0xED06 // FORMAT_RXE LOAD LENGTHENED (short to extended BFP) 1966 op_LXEBR uint32 = 0xB306 // FORMAT_RRE LOAD LENGTHENED (short to extended BFP) 1967 op_LXER uint32 = 0xB326 // FORMAT_RRE LOAD LENGTHENED (short to extended HFP) 1968 op_LXR uint32 = 0xB365 // FORMAT_RRE LOAD (extended) 1969 op_LY uint32 = 0xE358 // FORMAT_RXY1 LOAD (32) 1970 op_LZDR uint32 = 0xB375 // FORMAT_RRE LOAD ZERO (long) 1971 op_LZER uint32 = 0xB374 // FORMAT_RRE LOAD ZERO (short) 1972 op_LZXR uint32 = 0xB376 // FORMAT_RRE LOAD ZERO (extended) 1973 op_M uint32 = 0x5C00 // FORMAT_RX1 MULTIPLY (64<-32) 1974 op_MAD uint32 = 0xED3E // FORMAT_RXF MULTIPLY AND ADD (long HFP) 1975 op_MADB uint32 = 0xED1E // FORMAT_RXF MULTIPLY AND ADD (long BFP) 1976 op_MADBR uint32 = 0xB31E // FORMAT_RRD MULTIPLY AND ADD (long BFP) 1977 op_MADR uint32 = 0xB33E // FORMAT_RRD MULTIPLY AND ADD (long HFP) 1978 op_MAE uint32 = 0xED2E // FORMAT_RXF MULTIPLY AND ADD (short HFP) 1979 op_MAEB uint32 = 0xED0E // FORMAT_RXF MULTIPLY AND ADD (short BFP) 1980 op_MAEBR uint32 = 0xB30E // FORMAT_RRD MULTIPLY AND ADD (short BFP) 1981 op_MAER uint32 = 0xB32E // FORMAT_RRD MULTIPLY AND ADD (short HFP) 1982 op_MAY uint32 = 0xED3A // FORMAT_RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1983 op_MAYH uint32 = 0xED3C // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1984 op_MAYHR uint32 = 0xB33C // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1985 op_MAYL uint32 = 0xED38 // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1986 op_MAYLR uint32 = 0xB338 // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1987 op_MAYR uint32 = 0xB33A // FORMAT_RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1988 op_MC uint32 = 0xAF00 // FORMAT_SI MONITOR CALL 1989 op_MD uint32 = 0x6C00 // FORMAT_RX1 MULTIPLY (long HFP) 1990 op_MDB uint32 = 0xED1C // FORMAT_RXE MULTIPLY (long BFP) 1991 op_MDBR uint32 = 0xB31C // FORMAT_RRE MULTIPLY (long BFP) 1992 op_MDE uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1993 op_MDEB uint32 = 0xED0C // FORMAT_RXE MULTIPLY (short to long BFP) 1994 op_MDEBR uint32 = 0xB30C // FORMAT_RRE MULTIPLY (short to long BFP) 1995 op_MDER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1996 op_MDR uint32 = 0x2C00 // FORMAT_RR MULTIPLY (long HFP) 1997 op_MDTR uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1998 op_MDTRA uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1999 op_ME uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 2000 op_MEE uint32 = 0xED37 // FORMAT_RXE MULTIPLY (short HFP) 2001 op_MEEB uint32 = 0xED17 // FORMAT_RXE MULTIPLY (short BFP) 2002 op_MEEBR uint32 = 0xB317 // FORMAT_RRE MULTIPLY (short BFP) 2003 op_MEER uint32 = 0xB337 // FORMAT_RRE MULTIPLY (short HFP) 2004 op_MER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 2005 op_MFY uint32 = 0xE35C // FORMAT_RXY1 MULTIPLY (64<-32) 2006 op_MGHI uint32 = 0xA70D // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (64) 2007 op_MH uint32 = 0x4C00 // FORMAT_RX1 MULTIPLY HALFWORD (32) 2008 op_MHI uint32 = 0xA70C // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (32) 2009 op_MHY uint32 = 0xE37C // FORMAT_RXY1 MULTIPLY HALFWORD (32) 2010 op_ML uint32 = 0xE396 // FORMAT_RXY1 MULTIPLY LOGICAL (64<-32) 2011 op_MLG uint32 = 0xE386 // FORMAT_RXY1 MULTIPLY LOGICAL (128<-64) 2012 op_MLGR uint32 = 0xB986 // FORMAT_RRE MULTIPLY LOGICAL (128<-64) 2013 op_MLR uint32 = 0xB996 // FORMAT_RRE MULTIPLY LOGICAL (64<-32) 2014 op_MP uint32 = 0xFC00 // FORMAT_SS2 MULTIPLY DECIMAL 2015 op_MR uint32 = 0x1C00 // FORMAT_RR MULTIPLY (64<-32) 2016 op_MS uint32 = 0x7100 // FORMAT_RX1 MULTIPLY SINGLE (32) 2017 op_MSCH uint32 = 0xB232 // FORMAT_S MODIFY SUBCHANNEL 2018 op_MSD uint32 = 0xED3F // FORMAT_RXF MULTIPLY AND SUBTRACT (long HFP) 2019 op_MSDB uint32 = 0xED1F // FORMAT_RXF MULTIPLY AND SUBTRACT (long BFP) 2020 op_MSDBR uint32 = 0xB31F // FORMAT_RRD MULTIPLY AND SUBTRACT (long BFP) 2021 op_MSDR uint32 = 0xB33F // FORMAT_RRD MULTIPLY AND SUBTRACT (long HFP) 2022 op_MSE uint32 = 0xED2F // FORMAT_RXF MULTIPLY AND SUBTRACT (short HFP) 2023 op_MSEB uint32 = 0xED0F // FORMAT_RXF MULTIPLY AND SUBTRACT (short BFP) 2024 op_MSEBR uint32 = 0xB30F // FORMAT_RRD MULTIPLY AND SUBTRACT (short BFP) 2025 op_MSER uint32 = 0xB32F // FORMAT_RRD MULTIPLY AND SUBTRACT (short HFP) 2026 op_MSFI uint32 = 0xC201 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (32) 2027 op_MSG uint32 = 0xE30C // FORMAT_RXY1 MULTIPLY SINGLE (64) 2028 op_MSGF uint32 = 0xE31C // FORMAT_RXY1 MULTIPLY SINGLE (64<-32) 2029 op_MSGFI uint32 = 0xC200 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (64<-32) 2030 op_MSGFR uint32 = 0xB91C // FORMAT_RRE MULTIPLY SINGLE (64<-32) 2031 op_MSGR uint32 = 0xB90C // FORMAT_RRE MULTIPLY SINGLE (64) 2032 op_MSR uint32 = 0xB252 // FORMAT_RRE MULTIPLY SINGLE (32) 2033 op_MSTA uint32 = 0xB247 // FORMAT_RRE MODIFY STACKED STATE 2034 op_MSY uint32 = 0xE351 // FORMAT_RXY1 MULTIPLY SINGLE (32) 2035 op_MVC uint32 = 0xD200 // FORMAT_SS1 MOVE (character) 2036 op_MVCDK uint32 = 0xE50F // FORMAT_SSE MOVE WITH DESTINATION KEY 2037 op_MVCIN uint32 = 0xE800 // FORMAT_SS1 MOVE INVERSE 2038 op_MVCK uint32 = 0xD900 // FORMAT_SS4 MOVE WITH KEY 2039 op_MVCL uint32 = 0x0E00 // FORMAT_RR MOVE LONG 2040 op_MVCLE uint32 = 0xA800 // FORMAT_RS1 MOVE LONG EXTENDED 2041 op_MVCLU uint32 = 0xEB8E // FORMAT_RSY1 MOVE LONG UNICODE 2042 op_MVCOS uint32 = 0xC800 // FORMAT_SSF MOVE WITH OPTIONAL SPECIFICATIONS 2043 op_MVCP uint32 = 0xDA00 // FORMAT_SS4 MOVE TO PRIMARY 2044 op_MVCS uint32 = 0xDB00 // FORMAT_SS4 MOVE TO SECONDARY 2045 op_MVCSK uint32 = 0xE50E // FORMAT_SSE MOVE WITH SOURCE KEY 2046 op_MVGHI uint32 = 0xE548 // FORMAT_SIL MOVE (64<-16) 2047 op_MVHHI uint32 = 0xE544 // FORMAT_SIL MOVE (16<-16) 2048 op_MVHI uint32 = 0xE54C // FORMAT_SIL MOVE (32<-16) 2049 op_MVI uint32 = 0x9200 // FORMAT_SI MOVE (immediate) 2050 op_MVIY uint32 = 0xEB52 // FORMAT_SIY MOVE (immediate) 2051 op_MVN uint32 = 0xD100 // FORMAT_SS1 MOVE NUMERICS 2052 op_MVO uint32 = 0xF100 // FORMAT_SS2 MOVE WITH OFFSET 2053 op_MVPG uint32 = 0xB254 // FORMAT_RRE MOVE PAGE 2054 op_MVST uint32 = 0xB255 // FORMAT_RRE MOVE STRING 2055 op_MVZ uint32 = 0xD300 // FORMAT_SS1 MOVE ZONES 2056 op_MXBR uint32 = 0xB34C // FORMAT_RRE MULTIPLY (extended BFP) 2057 op_MXD uint32 = 0x6700 // FORMAT_RX1 MULTIPLY (long to extended HFP) 2058 op_MXDB uint32 = 0xED07 // FORMAT_RXE MULTIPLY (long to extended BFP) 2059 op_MXDBR uint32 = 0xB307 // FORMAT_RRE MULTIPLY (long to extended BFP) 2060 op_MXDR uint32 = 0x2700 // FORMAT_RR MULTIPLY (long to extended HFP) 2061 op_MXR uint32 = 0x2600 // FORMAT_RR MULTIPLY (extended HFP) 2062 op_MXTR uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2063 op_MXTRA uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2064 op_MY uint32 = 0xED3B // FORMAT_RXF MULTIPLY UNNORMALIZED (long to ext. HFP) 2065 op_MYH uint32 = 0xED3D // FORMAT_RXF MULTIPLY UNNORM. (long to ext. high HFP) 2066 op_MYHR uint32 = 0xB33D // FORMAT_RRD MULTIPLY UNNORM. (long to ext. high HFP) 2067 op_MYL uint32 = 0xED39 // FORMAT_RXF MULTIPLY UNNORM. (long to ext. low HFP) 2068 op_MYLR uint32 = 0xB339 // FORMAT_RRD MULTIPLY UNNORM. (long to ext. low HFP) 2069 op_MYR uint32 = 0xB33B // FORMAT_RRD MULTIPLY UNNORMALIZED (long to ext. HFP) 2070 op_N uint32 = 0x5400 // FORMAT_RX1 AND (32) 2071 op_NC uint32 = 0xD400 // FORMAT_SS1 AND (character) 2072 op_NG uint32 = 0xE380 // FORMAT_RXY1 AND (64) 2073 op_NGR uint32 = 0xB980 // FORMAT_RRE AND (64) 2074 op_NGRK uint32 = 0xB9E4 // FORMAT_RRF1 AND (64) 2075 op_NI uint32 = 0x9400 // FORMAT_SI AND (immediate) 2076 op_NIAI uint32 = 0xB2FA // FORMAT_IE NEXT INSTRUCTION ACCESS INTENT 2077 op_NIHF uint32 = 0xC00A // FORMAT_RIL1 AND IMMEDIATE (high) 2078 op_NIHH uint32 = 0xA504 // FORMAT_RI1 AND IMMEDIATE (high high) 2079 op_NIHL uint32 = 0xA505 // FORMAT_RI1 AND IMMEDIATE (high low) 2080 op_NILF uint32 = 0xC00B // FORMAT_RIL1 AND IMMEDIATE (low) 2081 op_NILH uint32 = 0xA506 // FORMAT_RI1 AND IMMEDIATE (low high) 2082 op_NILL uint32 = 0xA507 // FORMAT_RI1 AND IMMEDIATE (low low) 2083 op_NIY uint32 = 0xEB54 // FORMAT_SIY AND (immediate) 2084 op_NR uint32 = 0x1400 // FORMAT_RR AND (32) 2085 op_NRK uint32 = 0xB9F4 // FORMAT_RRF1 AND (32) 2086 op_NTSTG uint32 = 0xE325 // FORMAT_RXY1 NONTRANSACTIONAL STORE 2087 op_NY uint32 = 0xE354 // FORMAT_RXY1 AND (32) 2088 op_O uint32 = 0x5600 // FORMAT_RX1 OR (32) 2089 op_OC uint32 = 0xD600 // FORMAT_SS1 OR (character) 2090 op_OG uint32 = 0xE381 // FORMAT_RXY1 OR (64) 2091 op_OGR uint32 = 0xB981 // FORMAT_RRE OR (64) 2092 op_OGRK uint32 = 0xB9E6 // FORMAT_RRF1 OR (64) 2093 op_OI uint32 = 0x9600 // FORMAT_SI OR (immediate) 2094 op_OIHF uint32 = 0xC00C // FORMAT_RIL1 OR IMMEDIATE (high) 2095 op_OIHH uint32 = 0xA508 // FORMAT_RI1 OR IMMEDIATE (high high) 2096 op_OIHL uint32 = 0xA509 // FORMAT_RI1 OR IMMEDIATE (high low) 2097 op_OILF uint32 = 0xC00D // FORMAT_RIL1 OR IMMEDIATE (low) 2098 op_OILH uint32 = 0xA50A // FORMAT_RI1 OR IMMEDIATE (low high) 2099 op_OILL uint32 = 0xA50B // FORMAT_RI1 OR IMMEDIATE (low low) 2100 op_OIY uint32 = 0xEB56 // FORMAT_SIY OR (immediate) 2101 op_OR uint32 = 0x1600 // FORMAT_RR OR (32) 2102 op_ORK uint32 = 0xB9F6 // FORMAT_RRF1 OR (32) 2103 op_OY uint32 = 0xE356 // FORMAT_RXY1 OR (32) 2104 op_PACK uint32 = 0xF200 // FORMAT_SS2 PACK 2105 op_PALB uint32 = 0xB248 // FORMAT_RRE PURGE ALB 2106 op_PC uint32 = 0xB218 // FORMAT_S PROGRAM CALL 2107 op_PCC uint32 = 0xB92C // FORMAT_RRE PERFORM CRYPTOGRAPHIC COMPUTATION 2108 op_PCKMO uint32 = 0xB928 // FORMAT_RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS 2109 op_PFD uint32 = 0xE336 // FORMAT_RXY2 PREFETCH DATA 2110 op_PFDRL uint32 = 0xC602 // FORMAT_RIL3 PREFETCH DATA RELATIVE LONG 2111 op_PFMF uint32 = 0xB9AF // FORMAT_RRE PERFORM FRAME MANAGEMENT FUNCTION 2112 op_PFPO uint32 = 0x010A // FORMAT_E PERFORM FLOATING-POINT OPERATION 2113 op_PGIN uint32 = 0xB22E // FORMAT_RRE PAGE IN 2114 op_PGOUT uint32 = 0xB22F // FORMAT_RRE PAGE OUT 2115 op_PKA uint32 = 0xE900 // FORMAT_SS6 PACK ASCII 2116 op_PKU uint32 = 0xE100 // FORMAT_SS6 PACK UNICODE 2117 op_PLO uint32 = 0xEE00 // FORMAT_SS5 PERFORM LOCKED OPERATION 2118 op_POPCNT uint32 = 0xB9E1 // FORMAT_RRE POPULATION COUNT 2119 op_PPA uint32 = 0xB2E8 // FORMAT_RRF3 PERFORM PROCESSOR ASSIST 2120 op_PR uint32 = 0x0101 // FORMAT_E PROGRAM RETURN 2121 op_PT uint32 = 0xB228 // FORMAT_RRE PROGRAM TRANSFER 2122 op_PTF uint32 = 0xB9A2 // FORMAT_RRE PERFORM TOPOLOGY FUNCTION 2123 op_PTFF uint32 = 0x0104 // FORMAT_E PERFORM TIMING FACILITY FUNCTION 2124 op_PTI uint32 = 0xB99E // FORMAT_RRE PROGRAM TRANSFER WITH INSTANCE 2125 op_PTLB uint32 = 0xB20D // FORMAT_S PURGE TLB 2126 op_QADTR uint32 = 0xB3F5 // FORMAT_RRF2 QUANTIZE (long DFP) 2127 op_QAXTR uint32 = 0xB3FD // FORMAT_RRF2 QUANTIZE (extended DFP) 2128 op_RCHP uint32 = 0xB23B // FORMAT_S RESET CHANNEL PATH 2129 op_RISBG uint32 = 0xEC55 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2130 op_RISBGN uint32 = 0xEC59 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2131 op_RISBHG uint32 = 0xEC5D // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS HIGH 2132 op_RISBLG uint32 = 0xEC51 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS LOW 2133 op_RLL uint32 = 0xEB1D // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (32) 2134 op_RLLG uint32 = 0xEB1C // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (64) 2135 op_RNSBG uint32 = 0xEC54 // FORMAT_RIE6 ROTATE THEN AND SELECTED BITS 2136 op_ROSBG uint32 = 0xEC56 // FORMAT_RIE6 ROTATE THEN OR SELECTED BITS 2137 op_RP uint32 = 0xB277 // FORMAT_S RESUME PROGRAM 2138 op_RRBE uint32 = 0xB22A // FORMAT_RRE RESET REFERENCE BIT EXTENDED 2139 op_RRBM uint32 = 0xB9AE // FORMAT_RRE RESET REFERENCE BITS MULTIPLE 2140 op_RRDTR uint32 = 0xB3F7 // FORMAT_RRF2 REROUND (long DFP) 2141 op_RRXTR uint32 = 0xB3FF // FORMAT_RRF2 REROUND (extended DFP) 2142 op_RSCH uint32 = 0xB238 // FORMAT_S RESUME SUBCHANNEL 2143 op_RXSBG uint32 = 0xEC57 // FORMAT_RIE6 ROTATE THEN EXCLUSIVE OR SELECTED BITS 2144 op_S uint32 = 0x5B00 // FORMAT_RX1 SUBTRACT (32) 2145 op_SAC uint32 = 0xB219 // FORMAT_S SET ADDRESS SPACE CONTROL 2146 op_SACF uint32 = 0xB279 // FORMAT_S SET ADDRESS SPACE CONTROL FAST 2147 op_SAL uint32 = 0xB237 // FORMAT_S SET ADDRESS LIMIT 2148 op_SAM24 uint32 = 0x010C // FORMAT_E SET ADDRESSING MODE (24) 2149 op_SAM31 uint32 = 0x010D // FORMAT_E SET ADDRESSING MODE (31) 2150 op_SAM64 uint32 = 0x010E // FORMAT_E SET ADDRESSING MODE (64) 2151 op_SAR uint32 = 0xB24E // FORMAT_RRE SET ACCESS 2152 op_SCHM uint32 = 0xB23C // FORMAT_S SET CHANNEL MONITOR 2153 op_SCK uint32 = 0xB204 // FORMAT_S SET CLOCK 2154 op_SCKC uint32 = 0xB206 // FORMAT_S SET CLOCK COMPARATOR 2155 op_SCKPF uint32 = 0x0107 // FORMAT_E SET CLOCK PROGRAMMABLE FIELD 2156 op_SD uint32 = 0x6B00 // FORMAT_RX1 SUBTRACT NORMALIZED (long HFP) 2157 op_SDB uint32 = 0xED1B // FORMAT_RXE SUBTRACT (long BFP) 2158 op_SDBR uint32 = 0xB31B // FORMAT_RRE SUBTRACT (long BFP) 2159 op_SDR uint32 = 0x2B00 // FORMAT_RR SUBTRACT NORMALIZED (long HFP) 2160 op_SDTR uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2161 op_SDTRA uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2162 op_SE uint32 = 0x7B00 // FORMAT_RX1 SUBTRACT NORMALIZED (short HFP) 2163 op_SEB uint32 = 0xED0B // FORMAT_RXE SUBTRACT (short BFP) 2164 op_SEBR uint32 = 0xB30B // FORMAT_RRE SUBTRACT (short BFP) 2165 op_SER uint32 = 0x3B00 // FORMAT_RR SUBTRACT NORMALIZED (short HFP) 2166 op_SFASR uint32 = 0xB385 // FORMAT_RRE SET FPC AND SIGNAL 2167 op_SFPC uint32 = 0xB384 // FORMAT_RRE SET FPC 2168 op_SG uint32 = 0xE309 // FORMAT_RXY1 SUBTRACT (64) 2169 op_SGF uint32 = 0xE319 // FORMAT_RXY1 SUBTRACT (64<-32) 2170 op_SGFR uint32 = 0xB919 // FORMAT_RRE SUBTRACT (64<-32) 2171 op_SGR uint32 = 0xB909 // FORMAT_RRE SUBTRACT (64) 2172 op_SGRK uint32 = 0xB9E9 // FORMAT_RRF1 SUBTRACT (64) 2173 op_SH uint32 = 0x4B00 // FORMAT_RX1 SUBTRACT HALFWORD 2174 op_SHHHR uint32 = 0xB9C9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2175 op_SHHLR uint32 = 0xB9D9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2176 op_SHY uint32 = 0xE37B // FORMAT_RXY1 SUBTRACT HALFWORD 2177 op_SIGP uint32 = 0xAE00 // FORMAT_RS1 SIGNAL PROCESSOR 2178 op_SL uint32 = 0x5F00 // FORMAT_RX1 SUBTRACT LOGICAL (32) 2179 op_SLA uint32 = 0x8B00 // FORMAT_RS1 SHIFT LEFT SINGLE (32) 2180 op_SLAG uint32 = 0xEB0B // FORMAT_RSY1 SHIFT LEFT SINGLE (64) 2181 op_SLAK uint32 = 0xEBDD // FORMAT_RSY1 SHIFT LEFT SINGLE (32) 2182 op_SLB uint32 = 0xE399 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (32) 2183 op_SLBG uint32 = 0xE389 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (64) 2184 op_SLBGR uint32 = 0xB989 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (64) 2185 op_SLBR uint32 = 0xB999 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (32) 2186 op_SLDA uint32 = 0x8F00 // FORMAT_RS1 SHIFT LEFT DOUBLE 2187 op_SLDL uint32 = 0x8D00 // FORMAT_RS1 SHIFT LEFT DOUBLE LOGICAL 2188 op_SLDT uint32 = 0xED40 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (long DFP) 2189 op_SLFI uint32 = 0xC205 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (32) 2190 op_SLG uint32 = 0xE30B // FORMAT_RXY1 SUBTRACT LOGICAL (64) 2191 op_SLGF uint32 = 0xE31B // FORMAT_RXY1 SUBTRACT LOGICAL (64<-32) 2192 op_SLGFI uint32 = 0xC204 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (64<-32) 2193 op_SLGFR uint32 = 0xB91B // FORMAT_RRE SUBTRACT LOGICAL (64<-32) 2194 op_SLGR uint32 = 0xB90B // FORMAT_RRE SUBTRACT LOGICAL (64) 2195 op_SLGRK uint32 = 0xB9EB // FORMAT_RRF1 SUBTRACT LOGICAL (64) 2196 op_SLHHHR uint32 = 0xB9CB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2197 op_SLHHLR uint32 = 0xB9DB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2198 op_SLL uint32 = 0x8900 // FORMAT_RS1 SHIFT LEFT SINGLE LOGICAL (32) 2199 op_SLLG uint32 = 0xEB0D // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (64) 2200 op_SLLK uint32 = 0xEBDF // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (32) 2201 op_SLR uint32 = 0x1F00 // FORMAT_RR SUBTRACT LOGICAL (32) 2202 op_SLRK uint32 = 0xB9FB // FORMAT_RRF1 SUBTRACT LOGICAL (32) 2203 op_SLXT uint32 = 0xED48 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (extended DFP) 2204 op_SLY uint32 = 0xE35F // FORMAT_RXY1 SUBTRACT LOGICAL (32) 2205 op_SP uint32 = 0xFB00 // FORMAT_SS2 SUBTRACT DECIMAL 2206 op_SPKA uint32 = 0xB20A // FORMAT_S SET PSW KEY FROM ADDRESS 2207 op_SPM uint32 = 0x0400 // FORMAT_RR SET PROGRAM MASK 2208 op_SPT uint32 = 0xB208 // FORMAT_S SET CPU TIMER 2209 op_SPX uint32 = 0xB210 // FORMAT_S SET PREFIX 2210 op_SQD uint32 = 0xED35 // FORMAT_RXE SQUARE ROOT (long HFP) 2211 op_SQDB uint32 = 0xED15 // FORMAT_RXE SQUARE ROOT (long BFP) 2212 op_SQDBR uint32 = 0xB315 // FORMAT_RRE SQUARE ROOT (long BFP) 2213 op_SQDR uint32 = 0xB244 // FORMAT_RRE SQUARE ROOT (long HFP) 2214 op_SQE uint32 = 0xED34 // FORMAT_RXE SQUARE ROOT (short HFP) 2215 op_SQEB uint32 = 0xED14 // FORMAT_RXE SQUARE ROOT (short BFP) 2216 op_SQEBR uint32 = 0xB314 // FORMAT_RRE SQUARE ROOT (short BFP) 2217 op_SQER uint32 = 0xB245 // FORMAT_RRE SQUARE ROOT (short HFP) 2218 op_SQXBR uint32 = 0xB316 // FORMAT_RRE SQUARE ROOT (extended BFP) 2219 op_SQXR uint32 = 0xB336 // FORMAT_RRE SQUARE ROOT (extended HFP) 2220 op_SR uint32 = 0x1B00 // FORMAT_RR SUBTRACT (32) 2221 op_SRA uint32 = 0x8A00 // FORMAT_RS1 SHIFT RIGHT SINGLE (32) 2222 op_SRAG uint32 = 0xEB0A // FORMAT_RSY1 SHIFT RIGHT SINGLE (64) 2223 op_SRAK uint32 = 0xEBDC // FORMAT_RSY1 SHIFT RIGHT SINGLE (32) 2224 op_SRDA uint32 = 0x8E00 // FORMAT_RS1 SHIFT RIGHT DOUBLE 2225 op_SRDL uint32 = 0x8C00 // FORMAT_RS1 SHIFT RIGHT DOUBLE LOGICAL 2226 op_SRDT uint32 = 0xED41 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (long DFP) 2227 op_SRK uint32 = 0xB9F9 // FORMAT_RRF1 SUBTRACT (32) 2228 op_SRL uint32 = 0x8800 // FORMAT_RS1 SHIFT RIGHT SINGLE LOGICAL (32) 2229 op_SRLG uint32 = 0xEB0C // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (64) 2230 op_SRLK uint32 = 0xEBDE // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (32) 2231 op_SRNM uint32 = 0xB299 // FORMAT_S SET BFP ROUNDING MODE (2 bit) 2232 op_SRNMB uint32 = 0xB2B8 // FORMAT_S SET BFP ROUNDING MODE (3 bit) 2233 op_SRNMT uint32 = 0xB2B9 // FORMAT_S SET DFP ROUNDING MODE 2234 op_SRP uint32 = 0xF000 // FORMAT_SS3 SHIFT AND ROUND DECIMAL 2235 op_SRST uint32 = 0xB25E // FORMAT_RRE SEARCH STRING 2236 op_SRSTU uint32 = 0xB9BE // FORMAT_RRE SEARCH STRING UNICODE 2237 op_SRXT uint32 = 0xED49 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (extended DFP) 2238 op_SSAIR uint32 = 0xB99F // FORMAT_RRE SET SECONDARY ASN WITH INSTANCE 2239 op_SSAR uint32 = 0xB225 // FORMAT_RRE SET SECONDARY ASN 2240 op_SSCH uint32 = 0xB233 // FORMAT_S START SUBCHANNEL 2241 op_SSKE uint32 = 0xB22B // FORMAT_RRF3 SET STORAGE KEY EXTENDED 2242 op_SSM uint32 = 0x8000 // FORMAT_S SET SYSTEM MASK 2243 op_ST uint32 = 0x5000 // FORMAT_RX1 STORE (32) 2244 op_STAM uint32 = 0x9B00 // FORMAT_RS1 STORE ACCESS MULTIPLE 2245 op_STAMY uint32 = 0xEB9B // FORMAT_RSY1 STORE ACCESS MULTIPLE 2246 op_STAP uint32 = 0xB212 // FORMAT_S STORE CPU ADDRESS 2247 op_STC uint32 = 0x4200 // FORMAT_RX1 STORE CHARACTER 2248 op_STCH uint32 = 0xE3C3 // FORMAT_RXY1 STORE CHARACTER HIGH (8) 2249 op_STCK uint32 = 0xB205 // FORMAT_S STORE CLOCK 2250 op_STCKC uint32 = 0xB207 // FORMAT_S STORE CLOCK COMPARATOR 2251 op_STCKE uint32 = 0xB278 // FORMAT_S STORE CLOCK EXTENDED 2252 op_STCKF uint32 = 0xB27C // FORMAT_S STORE CLOCK FAST 2253 op_STCM uint32 = 0xBE00 // FORMAT_RS2 STORE CHARACTERS UNDER MASK (low) 2254 op_STCMH uint32 = 0xEB2C // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (high) 2255 op_STCMY uint32 = 0xEB2D // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (low) 2256 op_STCPS uint32 = 0xB23A // FORMAT_S STORE CHANNEL PATH STATUS 2257 op_STCRW uint32 = 0xB239 // FORMAT_S STORE CHANNEL REPORT WORD 2258 op_STCTG uint32 = 0xEB25 // FORMAT_RSY1 STORE CONTROL (64) 2259 op_STCTL uint32 = 0xB600 // FORMAT_RS1 STORE CONTROL (32) 2260 op_STCY uint32 = 0xE372 // FORMAT_RXY1 STORE CHARACTER 2261 op_STD uint32 = 0x6000 // FORMAT_RX1 STORE (long) 2262 op_STDY uint32 = 0xED67 // FORMAT_RXY1 STORE (long) 2263 op_STE uint32 = 0x7000 // FORMAT_RX1 STORE (short) 2264 op_STEY uint32 = 0xED66 // FORMAT_RXY1 STORE (short) 2265 op_STFH uint32 = 0xE3CB // FORMAT_RXY1 STORE HIGH (32) 2266 op_STFL uint32 = 0xB2B1 // FORMAT_S STORE FACILITY LIST 2267 op_STFLE uint32 = 0xB2B0 // FORMAT_S STORE FACILITY LIST EXTENDED 2268 op_STFPC uint32 = 0xB29C // FORMAT_S STORE FPC 2269 op_STG uint32 = 0xE324 // FORMAT_RXY1 STORE (64) 2270 op_STGRL uint32 = 0xC40B // FORMAT_RIL2 STORE RELATIVE LONG (64) 2271 op_STH uint32 = 0x4000 // FORMAT_RX1 STORE HALFWORD 2272 op_STHH uint32 = 0xE3C7 // FORMAT_RXY1 STORE HALFWORD HIGH (16) 2273 op_STHRL uint32 = 0xC407 // FORMAT_RIL2 STORE HALFWORD RELATIVE LONG 2274 op_STHY uint32 = 0xE370 // FORMAT_RXY1 STORE HALFWORD 2275 op_STIDP uint32 = 0xB202 // FORMAT_S STORE CPU ID 2276 op_STM uint32 = 0x9000 // FORMAT_RS1 STORE MULTIPLE (32) 2277 op_STMG uint32 = 0xEB24 // FORMAT_RSY1 STORE MULTIPLE (64) 2278 op_STMH uint32 = 0xEB26 // FORMAT_RSY1 STORE MULTIPLE HIGH 2279 op_STMY uint32 = 0xEB90 // FORMAT_RSY1 STORE MULTIPLE (32) 2280 op_STNSM uint32 = 0xAC00 // FORMAT_SI STORE THEN AND SYSTEM MASK 2281 op_STOC uint32 = 0xEBF3 // FORMAT_RSY2 STORE ON CONDITION (32) 2282 op_STOCG uint32 = 0xEBE3 // FORMAT_RSY2 STORE ON CONDITION (64) 2283 op_STOSM uint32 = 0xAD00 // FORMAT_SI STORE THEN OR SYSTEM MASK 2284 op_STPQ uint32 = 0xE38E // FORMAT_RXY1 STORE PAIR TO QUADWORD 2285 op_STPT uint32 = 0xB209 // FORMAT_S STORE CPU TIMER 2286 op_STPX uint32 = 0xB211 // FORMAT_S STORE PREFIX 2287 op_STRAG uint32 = 0xE502 // FORMAT_SSE STORE REAL ADDRESS 2288 op_STRL uint32 = 0xC40F // FORMAT_RIL2 STORE RELATIVE LONG (32) 2289 op_STRV uint32 = 0xE33E // FORMAT_RXY1 STORE REVERSED (32) 2290 op_STRVG uint32 = 0xE32F // FORMAT_RXY1 STORE REVERSED (64) 2291 op_STRVH uint32 = 0xE33F // FORMAT_RXY1 STORE REVERSED (16) 2292 op_STSCH uint32 = 0xB234 // FORMAT_S STORE SUBCHANNEL 2293 op_STSI uint32 = 0xB27D // FORMAT_S STORE SYSTEM INFORMATION 2294 op_STURA uint32 = 0xB246 // FORMAT_RRE STORE USING REAL ADDRESS (32) 2295 op_STURG uint32 = 0xB925 // FORMAT_RRE STORE USING REAL ADDRESS (64) 2296 op_STY uint32 = 0xE350 // FORMAT_RXY1 STORE (32) 2297 op_SU uint32 = 0x7F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (short HFP) 2298 op_SUR uint32 = 0x3F00 // FORMAT_RR SUBTRACT UNNORMALIZED (short HFP) 2299 op_SVC uint32 = 0x0A00 // FORMAT_I SUPERVISOR CALL 2300 op_SW uint32 = 0x6F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (long HFP) 2301 op_SWR uint32 = 0x2F00 // FORMAT_RR SUBTRACT UNNORMALIZED (long HFP) 2302 op_SXBR uint32 = 0xB34B // FORMAT_RRE SUBTRACT (extended BFP) 2303 op_SXR uint32 = 0x3700 // FORMAT_RR SUBTRACT NORMALIZED (extended HFP) 2304 op_SXTR uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2305 op_SXTRA uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2306 op_SY uint32 = 0xE35B // FORMAT_RXY1 SUBTRACT (32) 2307 op_TABORT uint32 = 0xB2FC // FORMAT_S TRANSACTION ABORT 2308 op_TAM uint32 = 0x010B // FORMAT_E TEST ADDRESSING MODE 2309 op_TAR uint32 = 0xB24C // FORMAT_RRE TEST ACCESS 2310 op_TB uint32 = 0xB22C // FORMAT_RRE TEST BLOCK 2311 op_TBDR uint32 = 0xB351 // FORMAT_RRF5 CONVERT HFP TO BFP (long) 2312 op_TBEDR uint32 = 0xB350 // FORMAT_RRF5 CONVERT HFP TO BFP (long to short) 2313 op_TBEGIN uint32 = 0xE560 // FORMAT_SIL TRANSACTION BEGIN 2314 op_TBEGINC uint32 = 0xE561 // FORMAT_SIL TRANSACTION BEGIN 2315 op_TCDB uint32 = 0xED11 // FORMAT_RXE TEST DATA CLASS (long BFP) 2316 op_TCEB uint32 = 0xED10 // FORMAT_RXE TEST DATA CLASS (short BFP) 2317 op_TCXB uint32 = 0xED12 // FORMAT_RXE TEST DATA CLASS (extended BFP) 2318 op_TDCDT uint32 = 0xED54 // FORMAT_RXE TEST DATA CLASS (long DFP) 2319 op_TDCET uint32 = 0xED50 // FORMAT_RXE TEST DATA CLASS (short DFP) 2320 op_TDCXT uint32 = 0xED58 // FORMAT_RXE TEST DATA CLASS (extended DFP) 2321 op_TDGDT uint32 = 0xED55 // FORMAT_RXE TEST DATA GROUP (long DFP) 2322 op_TDGET uint32 = 0xED51 // FORMAT_RXE TEST DATA GROUP (short DFP) 2323 op_TDGXT uint32 = 0xED59 // FORMAT_RXE TEST DATA GROUP (extended DFP) 2324 op_TEND uint32 = 0xB2F8 // FORMAT_S TRANSACTION END 2325 op_THDER uint32 = 0xB358 // FORMAT_RRE CONVERT BFP TO HFP (short to long) 2326 op_THDR uint32 = 0xB359 // FORMAT_RRE CONVERT BFP TO HFP (long) 2327 op_TM uint32 = 0x9100 // FORMAT_SI TEST UNDER MASK 2328 op_TMH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK HIGH 2329 op_TMHH uint32 = 0xA702 // FORMAT_RI1 TEST UNDER MASK (high high) 2330 op_TMHL uint32 = 0xA703 // FORMAT_RI1 TEST UNDER MASK (high low) 2331 op_TML uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK LOW 2332 op_TMLH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK (low high) 2333 op_TMLL uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK (low low) 2334 op_TMY uint32 = 0xEB51 // FORMAT_SIY TEST UNDER MASK 2335 op_TP uint32 = 0xEBC0 // FORMAT_RSL TEST DECIMAL 2336 op_TPI uint32 = 0xB236 // FORMAT_S TEST PENDING INTERRUPTION 2337 op_TPROT uint32 = 0xE501 // FORMAT_SSE TEST PROTECTION 2338 op_TR uint32 = 0xDC00 // FORMAT_SS1 TRANSLATE 2339 op_TRACE uint32 = 0x9900 // FORMAT_RS1 TRACE (32) 2340 op_TRACG uint32 = 0xEB0F // FORMAT_RSY1 TRACE (64) 2341 op_TRAP2 uint32 = 0x01FF // FORMAT_E TRAP 2342 op_TRAP4 uint32 = 0xB2FF // FORMAT_S TRAP 2343 op_TRE uint32 = 0xB2A5 // FORMAT_RRE TRANSLATE EXTENDED 2344 op_TROO uint32 = 0xB993 // FORMAT_RRF3 TRANSLATE ONE TO ONE 2345 op_TROT uint32 = 0xB992 // FORMAT_RRF3 TRANSLATE ONE TO TWO 2346 op_TRT uint32 = 0xDD00 // FORMAT_SS1 TRANSLATE AND TEST 2347 op_TRTE uint32 = 0xB9BF // FORMAT_RRF3 TRANSLATE AND TEST EXTENDED 2348 op_TRTO uint32 = 0xB991 // FORMAT_RRF3 TRANSLATE TWO TO ONE 2349 op_TRTR uint32 = 0xD000 // FORMAT_SS1 TRANSLATE AND TEST REVERSE 2350 op_TRTRE uint32 = 0xB9BD // FORMAT_RRF3 TRANSLATE AND TEST REVERSE EXTENDED 2351 op_TRTT uint32 = 0xB990 // FORMAT_RRF3 TRANSLATE TWO TO TWO 2352 op_TS uint32 = 0x9300 // FORMAT_S TEST AND SET 2353 op_TSCH uint32 = 0xB235 // FORMAT_S TEST SUBCHANNEL 2354 op_UNPK uint32 = 0xF300 // FORMAT_SS2 UNPACK 2355 op_UNPKA uint32 = 0xEA00 // FORMAT_SS1 UNPACK ASCII 2356 op_UNPKU uint32 = 0xE200 // FORMAT_SS1 UNPACK UNICODE 2357 op_UPT uint32 = 0x0102 // FORMAT_E UPDATE TREE 2358 op_X uint32 = 0x5700 // FORMAT_RX1 EXCLUSIVE OR (32) 2359 op_XC uint32 = 0xD700 // FORMAT_SS1 EXCLUSIVE OR (character) 2360 op_XG uint32 = 0xE382 // FORMAT_RXY1 EXCLUSIVE OR (64) 2361 op_XGR uint32 = 0xB982 // FORMAT_RRE EXCLUSIVE OR (64) 2362 op_XGRK uint32 = 0xB9E7 // FORMAT_RRF1 EXCLUSIVE OR (64) 2363 op_XI uint32 = 0x9700 // FORMAT_SI EXCLUSIVE OR (immediate) 2364 op_XIHF uint32 = 0xC006 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (high) 2365 op_XILF uint32 = 0xC007 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (low) 2366 op_XIY uint32 = 0xEB57 // FORMAT_SIY EXCLUSIVE OR (immediate) 2367 op_XR uint32 = 0x1700 // FORMAT_RR EXCLUSIVE OR (32) 2368 op_XRK uint32 = 0xB9F7 // FORMAT_RRF1 EXCLUSIVE OR (32) 2369 op_XSCH uint32 = 0xB276 // FORMAT_S CANCEL SUBCHANNEL 2370 op_XY uint32 = 0xE357 // FORMAT_RXY1 EXCLUSIVE OR (32) 2371 op_ZAP uint32 = 0xF800 // FORMAT_SS2 ZERO AND ADD 2372 2373 // added in z13 2374 op_CXPT uint32 = 0xEDAF // RSL-b CONVERT FROM PACKED (to extended DFP) 2375 op_CDPT uint32 = 0xEDAE // RSL-b CONVERT FROM PACKED (to long DFP) 2376 op_CPXT uint32 = 0xEDAD // RSL-b CONVERT TO PACKED (from extended DFP) 2377 op_CPDT uint32 = 0xEDAC // RSL-b CONVERT TO PACKED (from long DFP) 2378 op_LZRF uint32 = 0xE33B // RXY-a LOAD AND ZERO RIGHTMOST BYTE (32) 2379 op_LZRG uint32 = 0xE32A // RXY-a LOAD AND ZERO RIGHTMOST BYTE (64) 2380 op_LCCB uint32 = 0xE727 // RXE LOAD COUNT TO BLOCK BOUNDARY 2381 op_LOCHHI uint32 = 0xEC4E // RIE-g LOAD HALFWORD HIGH IMMEDIATE ON CONDITION (32←16) 2382 op_LOCHI uint32 = 0xEC42 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (32←16) 2383 op_LOCGHI uint32 = 0xEC46 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (64←16) 2384 op_LOCFH uint32 = 0xEBE0 // RSY-b LOAD HIGH ON CONDITION (32) 2385 op_LOCFHR uint32 = 0xB9E0 // RRF-c LOAD HIGH ON CONDITION (32) 2386 op_LLZRGF uint32 = 0xE33A // RXY-a LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64←32) 2387 op_STOCFH uint32 = 0xEBE1 // RSY-b STORE HIGH ON CONDITION 2388 op_VA uint32 = 0xE7F3 // VRR-c VECTOR ADD 2389 op_VACC uint32 = 0xE7F1 // VRR-c VECTOR ADD COMPUTE CARRY 2390 op_VAC uint32 = 0xE7BB // VRR-d VECTOR ADD WITH CARRY 2391 op_VACCC uint32 = 0xE7B9 // VRR-d VECTOR ADD WITH CARRY COMPUTE CARRY 2392 op_VN uint32 = 0xE768 // VRR-c VECTOR AND 2393 op_VNC uint32 = 0xE769 // VRR-c VECTOR AND WITH COMPLEMENT 2394 op_VAVG uint32 = 0xE7F2 // VRR-c VECTOR AVERAGE 2395 op_VAVGL uint32 = 0xE7F0 // VRR-c VECTOR AVERAGE LOGICAL 2396 op_VCKSM uint32 = 0xE766 // VRR-c VECTOR CHECKSUM 2397 op_VCEQ uint32 = 0xE7F8 // VRR-b VECTOR COMPARE EQUAL 2398 op_VCH uint32 = 0xE7FB // VRR-b VECTOR COMPARE HIGH 2399 op_VCHL uint32 = 0xE7F9 // VRR-b VECTOR COMPARE HIGH LOGICAL 2400 op_VCLZ uint32 = 0xE753 // VRR-a VECTOR COUNT LEADING ZEROS 2401 op_VCTZ uint32 = 0xE752 // VRR-a VECTOR COUNT TRAILING ZEROS 2402 op_VEC uint32 = 0xE7DB // VRR-a VECTOR ELEMENT COMPARE 2403 op_VECL uint32 = 0xE7D9 // VRR-a VECTOR ELEMENT COMPARE LOGICAL 2404 op_VERIM uint32 = 0xE772 // VRI-d VECTOR ELEMENT ROTATE AND INSERT UNDER MASK 2405 op_VERLL uint32 = 0xE733 // VRS-a VECTOR ELEMENT ROTATE LEFT LOGICAL 2406 op_VERLLV uint32 = 0xE773 // VRR-c VECTOR ELEMENT ROTATE LEFT LOGICAL 2407 op_VESLV uint32 = 0xE770 // VRR-c VECTOR ELEMENT SHIFT LEFT 2408 op_VESL uint32 = 0xE730 // VRS-a VECTOR ELEMENT SHIFT LEFT 2409 op_VESRA uint32 = 0xE73A // VRS-a VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2410 op_VESRAV uint32 = 0xE77A // VRR-c VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2411 op_VESRL uint32 = 0xE738 // VRS-a VECTOR ELEMENT SHIFT RIGHT LOGICAL 2412 op_VESRLV uint32 = 0xE778 // VRR-c VECTOR ELEMENT SHIFT RIGHT LOGICAL 2413 op_VX uint32 = 0xE76D // VRR-c VECTOR EXCLUSIVE OR 2414 op_VFAE uint32 = 0xE782 // VRR-b VECTOR FIND ANY ELEMENT EQUAL 2415 op_VFEE uint32 = 0xE780 // VRR-b VECTOR FIND ELEMENT EQUAL 2416 op_VFENE uint32 = 0xE781 // VRR-b VECTOR FIND ELEMENT NOT EQUAL 2417 op_VFA uint32 = 0xE7E3 // VRR-c VECTOR FP ADD 2418 op_WFK uint32 = 0xE7CA // VRR-a VECTOR FP COMPARE AND SIGNAL SCALAR 2419 op_VFCE uint32 = 0xE7E8 // VRR-c VECTOR FP COMPARE EQUAL 2420 op_VFCH uint32 = 0xE7EB // VRR-c VECTOR FP COMPARE HIGH 2421 op_VFCHE uint32 = 0xE7EA // VRR-c VECTOR FP COMPARE HIGH OR EQUAL 2422 op_WFC uint32 = 0xE7CB // VRR-a VECTOR FP COMPARE SCALAR 2423 op_VCDG uint32 = 0xE7C3 // VRR-a VECTOR FP CONVERT FROM FIXED 64-BIT 2424 op_VCDLG uint32 = 0xE7C1 // VRR-a VECTOR FP CONVERT FROM LOGICAL 64-BIT 2425 op_VCGD uint32 = 0xE7C2 // VRR-a VECTOR FP CONVERT TO FIXED 64-BIT 2426 op_VCLGD uint32 = 0xE7C0 // VRR-a VECTOR FP CONVERT TO LOGICAL 64-BIT 2427 op_VFD uint32 = 0xE7E5 // VRR-c VECTOR FP DIVIDE 2428 op_VLDE uint32 = 0xE7C4 // VRR-a VECTOR FP LOAD LENGTHENED 2429 op_VLED uint32 = 0xE7C5 // VRR-a VECTOR FP LOAD ROUNDED 2430 op_VFM uint32 = 0xE7E7 // VRR-c VECTOR FP MULTIPLY 2431 op_VFMA uint32 = 0xE78F // VRR-e VECTOR FP MULTIPLY AND ADD 2432 op_VFMS uint32 = 0xE78E // VRR-e VECTOR FP MULTIPLY AND SUBTRACT 2433 op_VFPSO uint32 = 0xE7CC // VRR-a VECTOR FP PERFORM SIGN OPERATION 2434 op_VFSQ uint32 = 0xE7CE // VRR-a VECTOR FP SQUARE ROOT 2435 op_VFS uint32 = 0xE7E2 // VRR-c VECTOR FP SUBTRACT 2436 op_VFTCI uint32 = 0xE74A // VRI-e VECTOR FP TEST DATA CLASS IMMEDIATE 2437 op_VGFM uint32 = 0xE7B4 // VRR-c VECTOR GALOIS FIELD MULTIPLY SUM 2438 op_VGFMA uint32 = 0xE7BC // VRR-d VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE 2439 op_VGEF uint32 = 0xE713 // VRV VECTOR GATHER ELEMENT (32) 2440 op_VGEG uint32 = 0xE712 // VRV VECTOR GATHER ELEMENT (64) 2441 op_VGBM uint32 = 0xE744 // VRI-a VECTOR GENERATE BYTE MASK 2442 op_VGM uint32 = 0xE746 // VRI-b VECTOR GENERATE MASK 2443 op_VISTR uint32 = 0xE75C // VRR-a VECTOR ISOLATE STRING 2444 op_VL uint32 = 0xE706 // VRX VECTOR LOAD 2445 op_VLR uint32 = 0xE756 // VRR-a VECTOR LOAD 2446 op_VLREP uint32 = 0xE705 // VRX VECTOR LOAD AND REPLICATE 2447 op_VLC uint32 = 0xE7DE // VRR-a VECTOR LOAD COMPLEMENT 2448 op_VLEH uint32 = 0xE701 // VRX VECTOR LOAD ELEMENT (16) 2449 op_VLEF uint32 = 0xE703 // VRX VECTOR LOAD ELEMENT (32) 2450 op_VLEG uint32 = 0xE702 // VRX VECTOR LOAD ELEMENT (64) 2451 op_VLEB uint32 = 0xE700 // VRX VECTOR LOAD ELEMENT (8) 2452 op_VLEIH uint32 = 0xE741 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (16) 2453 op_VLEIF uint32 = 0xE743 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (32) 2454 op_VLEIG uint32 = 0xE742 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (64) 2455 op_VLEIB uint32 = 0xE740 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (8) 2456 op_VFI uint32 = 0xE7C7 // VRR-a VECTOR LOAD FP INTEGER 2457 op_VLGV uint32 = 0xE721 // VRS-c VECTOR LOAD GR FROM VR ELEMENT 2458 op_VLLEZ uint32 = 0xE704 // VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO 2459 op_VLM uint32 = 0xE736 // VRS-a VECTOR LOAD MULTIPLE 2460 op_VLP uint32 = 0xE7DF // VRR-a VECTOR LOAD POSITIVE 2461 op_VLBB uint32 = 0xE707 // VRX VECTOR LOAD TO BLOCK BOUNDARY 2462 op_VLVG uint32 = 0xE722 // VRS-b VECTOR LOAD VR ELEMENT FROM GR 2463 op_VLVGP uint32 = 0xE762 // VRR-f VECTOR LOAD VR FROM GRS DISJOINT 2464 op_VLL uint32 = 0xE737 // VRS-b VECTOR LOAD WITH LENGTH 2465 op_VMX uint32 = 0xE7FF // VRR-c VECTOR MAXIMUM 2466 op_VMXL uint32 = 0xE7FD // VRR-c VECTOR MAXIMUM LOGICAL 2467 op_VMRH uint32 = 0xE761 // VRR-c VECTOR MERGE HIGH 2468 op_VMRL uint32 = 0xE760 // VRR-c VECTOR MERGE LOW 2469 op_VMN uint32 = 0xE7FE // VRR-c VECTOR MINIMUM 2470 op_VMNL uint32 = 0xE7FC // VRR-c VECTOR MINIMUM LOGICAL 2471 op_VMAE uint32 = 0xE7AE // VRR-d VECTOR MULTIPLY AND ADD EVEN 2472 op_VMAH uint32 = 0xE7AB // VRR-d VECTOR MULTIPLY AND ADD HIGH 2473 op_VMALE uint32 = 0xE7AC // VRR-d VECTOR MULTIPLY AND ADD LOGICAL EVEN 2474 op_VMALH uint32 = 0xE7A9 // VRR-d VECTOR MULTIPLY AND ADD LOGICAL HIGH 2475 op_VMALO uint32 = 0xE7AD // VRR-d VECTOR MULTIPLY AND ADD LOGICAL ODD 2476 op_VMAL uint32 = 0xE7AA // VRR-d VECTOR MULTIPLY AND ADD LOW 2477 op_VMAO uint32 = 0xE7AF // VRR-d VECTOR MULTIPLY AND ADD ODD 2478 op_VME uint32 = 0xE7A6 // VRR-c VECTOR MULTIPLY EVEN 2479 op_VMH uint32 = 0xE7A3 // VRR-c VECTOR MULTIPLY HIGH 2480 op_VMLE uint32 = 0xE7A4 // VRR-c VECTOR MULTIPLY EVEN LOGICAL 2481 op_VMLH uint32 = 0xE7A1 // VRR-c VECTOR MULTIPLY HIGH LOGICAL 2482 op_VMLO uint32 = 0xE7A5 // VRR-c VECTOR MULTIPLY ODD LOGICAL 2483 op_VML uint32 = 0xE7A2 // VRR-c VECTOR MULTIPLY LOW 2484 op_VMO uint32 = 0xE7A7 // VRR-c VECTOR MULTIPLY ODD 2485 op_VNO uint32 = 0xE76B // VRR-c VECTOR NOR 2486 op_VO uint32 = 0xE76A // VRR-c VECTOR OR 2487 op_VPK uint32 = 0xE794 // VRR-c VECTOR PACK 2488 op_VPKLS uint32 = 0xE795 // VRR-b VECTOR PACK LOGICAL SATURATE 2489 op_VPKS uint32 = 0xE797 // VRR-b VECTOR PACK SATURATE 2490 op_VPERM uint32 = 0xE78C // VRR-e VECTOR PERMUTE 2491 op_VPDI uint32 = 0xE784 // VRR-c VECTOR PERMUTE DOUBLEWORD IMMEDIATE 2492 op_VPOPCT uint32 = 0xE750 // VRR-a VECTOR POPULATION COUNT 2493 op_VREP uint32 = 0xE74D // VRI-c VECTOR REPLICATE 2494 op_VREPI uint32 = 0xE745 // VRI-a VECTOR REPLICATE IMMEDIATE 2495 op_VSCEF uint32 = 0xE71B // VRV VECTOR SCATTER ELEMENT (32) 2496 op_VSCEG uint32 = 0xE71A // VRV VECTOR SCATTER ELEMENT (64) 2497 op_VSEL uint32 = 0xE78D // VRR-e VECTOR SELECT 2498 op_VSL uint32 = 0xE774 // VRR-c VECTOR SHIFT LEFT 2499 op_VSLB uint32 = 0xE775 // VRR-c VECTOR SHIFT LEFT BY BYTE 2500 op_VSLDB uint32 = 0xE777 // VRI-d VECTOR SHIFT LEFT DOUBLE BY BYTE 2501 op_VSRA uint32 = 0xE77E // VRR-c VECTOR SHIFT RIGHT ARITHMETIC 2502 op_VSRAB uint32 = 0xE77F // VRR-c VECTOR SHIFT RIGHT ARITHMETIC BY BYTE 2503 op_VSRL uint32 = 0xE77C // VRR-c VECTOR SHIFT RIGHT LOGICAL 2504 op_VSRLB uint32 = 0xE77D // VRR-c VECTOR SHIFT RIGHT LOGICAL BY BYTE 2505 op_VSEG uint32 = 0xE75F // VRR-a VECTOR SIGN EXTEND TO DOUBLEWORD 2506 op_VST uint32 = 0xE70E // VRX VECTOR STORE 2507 op_VSTEH uint32 = 0xE709 // VRX VECTOR STORE ELEMENT (16) 2508 op_VSTEF uint32 = 0xE70B // VRX VECTOR STORE ELEMENT (32) 2509 op_VSTEG uint32 = 0xE70A // VRX VECTOR STORE ELEMENT (64) 2510 op_VSTEB uint32 = 0xE708 // VRX VECTOR STORE ELEMENT (8) 2511 op_VSTM uint32 = 0xE73E // VRS-a VECTOR STORE MULTIPLE 2512 op_VSTL uint32 = 0xE73F // VRS-b VECTOR STORE WITH LENGTH 2513 op_VSTRC uint32 = 0xE78A // VRR-d VECTOR STRING RANGE COMPARE 2514 op_VS uint32 = 0xE7F7 // VRR-c VECTOR SUBTRACT 2515 op_VSCBI uint32 = 0xE7F5 // VRR-c VECTOR SUBTRACT COMPUTE BORROW INDICATION 2516 op_VSBCBI uint32 = 0xE7BD // VRR-d VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION 2517 op_VSBI uint32 = 0xE7BF // VRR-d VECTOR SUBTRACT WITH BORROW INDICATION 2518 op_VSUMG uint32 = 0xE765 // VRR-c VECTOR SUM ACROSS DOUBLEWORD 2519 op_VSUMQ uint32 = 0xE767 // VRR-c VECTOR SUM ACROSS QUADWORD 2520 op_VSUM uint32 = 0xE764 // VRR-c VECTOR SUM ACROSS WORD 2521 op_VTM uint32 = 0xE7D8 // VRR-a VECTOR TEST UNDER MASK 2522 op_VUPH uint32 = 0xE7D7 // VRR-a VECTOR UNPACK HIGH 2523 op_VUPLH uint32 = 0xE7D5 // VRR-a VECTOR UNPACK LOGICAL HIGH 2524 op_VUPLL uint32 = 0xE7D4 // VRR-a VECTOR UNPACK LOGICAL LOW 2525 op_VUPL uint32 = 0xE7D6 // VRR-a VECTOR UNPACK LOW 2526 ) 2527 2528 func oclass(a *obj.Addr) int { 2529 return int(a.Class) - 1 2530 } 2531 2532 // Add a relocation for the immediate in a RIL style instruction. 2533 // The addend will be adjusted as required. 2534 func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) *obj.Reloc { 2535 if sym == nil { 2536 c.ctxt.Diag("require symbol to apply relocation") 2537 } 2538 offset := int64(2) // relocation offset from start of instruction 2539 rel := obj.Addrel(c.cursym) 2540 rel.Off = int32(c.pc + offset) 2541 rel.Siz = 4 2542 rel.Sym = sym 2543 rel.Add = add + offset + int64(rel.Siz) 2544 rel.Type = objabi.R_PCRELDBL 2545 return rel 2546 } 2547 2548 func (c *ctxtz) addrilrelocoffset(sym *obj.LSym, add, offset int64) *obj.Reloc { 2549 if sym == nil { 2550 c.ctxt.Diag("require symbol to apply relocation") 2551 } 2552 offset += int64(2) // relocation offset from start of instruction 2553 rel := obj.Addrel(c.cursym) 2554 rel.Off = int32(c.pc + offset) 2555 rel.Siz = 4 2556 rel.Sym = sym 2557 rel.Add = add + offset + int64(rel.Siz) 2558 rel.Type = objabi.R_PCRELDBL 2559 return rel 2560 } 2561 2562 // Add a CALL relocation for the immediate in a RIL style instruction. 2563 // The addend will be adjusted as required. 2564 func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) *obj.Reloc { 2565 if sym == nil { 2566 c.ctxt.Diag("require symbol to apply relocation") 2567 } 2568 offset := int64(2) // relocation offset from start of instruction 2569 rel := obj.Addrel(c.cursym) 2570 rel.Off = int32(c.pc + offset) 2571 rel.Siz = 4 2572 rel.Sym = sym 2573 rel.Add = add + offset + int64(rel.Siz) 2574 rel.Type = objabi.R_CALL 2575 return rel 2576 } 2577 2578 func (c *ctxtz) branchMask(p *obj.Prog) uint32 { 2579 switch p.As { 2580 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ: 2581 return 0x8 2582 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE: 2583 return 0xA 2584 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT: 2585 return 0x2 2586 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE: 2587 return 0xC 2588 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT: 2589 return 0x4 2590 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE: 2591 return 0x7 2592 case ABLEU: // LE or unordered 2593 return 0xD 2594 case ABLTU: // LT or unordered 2595 return 0x5 2596 case ABVC: 2597 return 0x0 // needs extra instruction 2598 case ABVS: 2599 return 0x1 // unordered 2600 } 2601 c.ctxt.Diag("unknown conditional branch %v", p.As) 2602 return 0xF 2603 } 2604 2605 func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) { 2606 o := c.oplook(p) 2607 2608 switch o.type_ { 2609 default: 2610 c.ctxt.Diag("unknown type %d", o.type_) 2611 2612 case 0: // PSEUDO OPS 2613 break 2614 2615 case 1: // mov reg reg 2616 switch p.As { 2617 default: 2618 c.ctxt.Diag("unhandled operation: %v", p.As) 2619 case AMOVD: 2620 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2621 // sign extend 2622 case AMOVW: 2623 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2624 case AMOVH: 2625 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2626 case AMOVB: 2627 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2628 // zero extend 2629 case AMOVWZ: 2630 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2631 case AMOVHZ: 2632 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2633 case AMOVBZ: 2634 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2635 // reverse bytes 2636 case AMOVDBR: 2637 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2638 case AMOVWBR: 2639 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2640 // floating point 2641 case AFMOVD, AFMOVS: 2642 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2643 } 2644 2645 case 2: // arithmetic op reg [reg] reg 2646 r := p.Reg 2647 if r == 0 { 2648 r = p.To.Reg 2649 } 2650 2651 var opcode uint32 2652 2653 switch p.As { 2654 default: 2655 c.ctxt.Diag("invalid opcode") 2656 case AADD: 2657 opcode = op_AGRK 2658 case AADDC: 2659 opcode = op_ALGRK 2660 case AADDE: 2661 opcode = op_ALCGR 2662 case AADDW: 2663 opcode = op_ARK 2664 case AMULLW: 2665 opcode = op_MSGFR 2666 case AMULLD: 2667 opcode = op_MSGR 2668 case ADIVW, AMODW: 2669 opcode = op_DSGFR 2670 case ADIVWU, AMODWU: 2671 opcode = op_DLR 2672 case ADIVD, AMODD: 2673 opcode = op_DSGR 2674 case ADIVDU, AMODDU: 2675 opcode = op_DLGR 2676 } 2677 2678 switch p.As { 2679 default: 2680 2681 case AADD, AADDC, AADDW: 2682 if p.As == AADDW && r == p.To.Reg { 2683 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2684 } else { 2685 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2686 } 2687 2688 case AADDE, AMULLW, AMULLD: 2689 if r == p.To.Reg { 2690 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2691 } else if p.From.Reg == p.To.Reg { 2692 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2693 } else { 2694 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2695 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2696 } 2697 2698 case ADIVW, ADIVWU, ADIVD, ADIVDU: 2699 if p.As == ADIVWU || p.As == ADIVDU { 2700 zRI(op_LGHI, REGTMP, 0, asm) 2701 } 2702 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2703 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2704 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm) 2705 2706 case AMODW, AMODWU, AMODD, AMODDU: 2707 if p.As == AMODWU || p.As == AMODDU { 2708 zRI(op_LGHI, REGTMP, 0, asm) 2709 } 2710 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2711 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2712 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2713 2714 } 2715 2716 case 3: // mov $constant reg 2717 v := c.vregoff(&p.From) 2718 switch p.As { 2719 case AMOVBZ: 2720 v = int64(uint8(v)) 2721 case AMOVHZ: 2722 v = int64(uint16(v)) 2723 case AMOVWZ: 2724 v = int64(uint32(v)) 2725 case AMOVB: 2726 v = int64(int8(v)) 2727 case AMOVH: 2728 v = int64(int16(v)) 2729 case AMOVW: 2730 v = int64(int32(v)) 2731 } 2732 if int64(int16(v)) == v { 2733 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm) 2734 } else if v&0xffff0000 == v { 2735 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm) 2736 } else if v&0xffff00000000 == v { 2737 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm) 2738 } else if uint64(v)&0xffff000000000000 == uint64(v) { 2739 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm) 2740 } else if int64(int32(v)) == v { 2741 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm) 2742 } else if int64(uint32(v)) == v { 2743 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2744 } else if uint64(v)&0xffffffff00000000 == uint64(v) { 2745 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2746 } else { 2747 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2748 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2749 } 2750 2751 case 4: // multiply high (a*b)>>64 2752 r := p.Reg 2753 if r == 0 { 2754 r = p.To.Reg 2755 } 2756 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2757 zRRE(op_MLGR, REGTMP, uint32(p.From.Reg), asm) 2758 switch p.As { 2759 case AMULHDU: 2760 // Unsigned: move result into correct register. 2761 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2762 case AMULHD: 2763 // Signed: need to convert result. 2764 // See Hacker's Delight 8-3. 2765 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm) 2766 zRRE(op_NGR, REGTMP2, uint32(r), asm) 2767 zRRE(op_SGR, REGTMP, REGTMP2, asm) 2768 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm) 2769 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm) 2770 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), REGTMP, asm) 2771 } 2772 2773 case 5: // syscall 2774 zI(op_SVC, 0, asm) 2775 2776 case 6: // logical op reg [reg] reg 2777 var oprr, oprre, oprrf uint32 2778 switch p.As { 2779 case AAND: 2780 oprre = op_NGR 2781 oprrf = op_NGRK 2782 case AANDW: 2783 oprr = op_NR 2784 oprrf = op_NRK 2785 case AOR: 2786 oprre = op_OGR 2787 oprrf = op_OGRK 2788 case AORW: 2789 oprr = op_OR 2790 oprrf = op_ORK 2791 case AXOR: 2792 oprre = op_XGR 2793 oprrf = op_XGRK 2794 case AXORW: 2795 oprr = op_XR 2796 oprrf = op_XRK 2797 } 2798 if p.Reg == 0 { 2799 if oprr != 0 { 2800 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2801 } else { 2802 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2803 } 2804 } else { 2805 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2806 } 2807 2808 case 7: // shift/rotate reg [reg] reg 2809 d2 := c.vregoff(&p.From) 2810 b2 := p.From.Reg 2811 r3 := p.Reg 2812 if r3 == 0 { 2813 r3 = p.To.Reg 2814 } 2815 r1 := p.To.Reg 2816 var opcode uint32 2817 switch p.As { 2818 default: 2819 case ASLD: 2820 opcode = op_SLLG 2821 case ASRD: 2822 opcode = op_SRLG 2823 case ASLW: 2824 opcode = op_SLLK 2825 case ASRW: 2826 opcode = op_SRLK 2827 case ARLL: 2828 opcode = op_RLL 2829 case ARLLG: 2830 opcode = op_RLLG 2831 case ASRAW: 2832 opcode = op_SRAK 2833 case ASRAD: 2834 opcode = op_SRAG 2835 } 2836 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm) 2837 2838 case 8: // find leftmost one 2839 if p.To.Reg&1 != 0 { 2840 c.ctxt.Diag("target must be an even-numbered register") 2841 } 2842 // FLOGR also writes a mask to p.To.Reg+1. 2843 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2844 2845 case 10: // subtract reg [reg] reg 2846 r := int(p.Reg) 2847 2848 switch p.As { 2849 default: 2850 case ASUB: 2851 if r == 0 { 2852 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2853 } else { 2854 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2855 } 2856 case ASUBC: 2857 if r == 0 { 2858 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2859 } else { 2860 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2861 } 2862 case ASUBE: 2863 if r == 0 { 2864 r = int(p.To.Reg) 2865 } 2866 if r == int(p.To.Reg) { 2867 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2868 } else if p.From.Reg == p.To.Reg { 2869 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 2870 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2871 zRRE(op_SLBGR, uint32(p.To.Reg), REGTMP, asm) 2872 } else { 2873 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2874 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2875 } 2876 case ASUBW: 2877 if r == 0 { 2878 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2879 } else { 2880 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2881 } 2882 } 2883 2884 case 11: // br/bl 2885 v := int32(0) 2886 2887 if p.Pcond != nil { 2888 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2889 } 2890 2891 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v { 2892 zRI(op_BRC, 0xF, uint32(v), asm) 2893 } else { 2894 if p.As == ABL { 2895 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm) 2896 } else { 2897 zRIL(_c, op_BRCL, 0xF, uint32(v), asm) 2898 } 2899 if p.To.Sym != nil { 2900 c.addcallreloc(p.To.Sym, p.To.Offset) 2901 } 2902 } 2903 2904 case 12: 2905 r1 := p.To.Reg 2906 d2 := c.vregoff(&p.From) 2907 b2 := p.From.Reg 2908 if b2 == 0 { 2909 b2 = o.param 2910 } 2911 x2 := p.From.Index 2912 if -DISP20/2 > d2 || d2 >= DISP20/2 { 2913 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 2914 if x2 != 0 { 2915 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 2916 } 2917 x2 = REGTMP 2918 d2 = 0 2919 } 2920 var opx, opxy uint32 2921 switch p.As { 2922 case AADD: 2923 opxy = op_AG 2924 case AADDC: 2925 opxy = op_ALG 2926 case AADDW: 2927 opx = op_A 2928 opxy = op_AY 2929 case AMULLW: 2930 opx = op_MS 2931 opxy = op_MSY 2932 case AMULLD: 2933 opxy = op_MSG 2934 case ASUB: 2935 opxy = op_SG 2936 case ASUBC: 2937 opxy = op_SLG 2938 case ASUBE: 2939 opxy = op_SLBG 2940 case ASUBW: 2941 opx = op_S 2942 opxy = op_SY 2943 case AAND: 2944 opxy = op_NG 2945 case AANDW: 2946 opx = op_N 2947 opxy = op_NY 2948 case AOR: 2949 opxy = op_OG 2950 case AORW: 2951 opx = op_O 2952 opxy = op_OY 2953 case AXOR: 2954 opxy = op_XG 2955 case AXORW: 2956 opx = op_X 2957 opxy = op_XY 2958 } 2959 if opx != 0 && 0 <= d2 && d2 < DISP12 { 2960 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 2961 } else { 2962 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 2963 } 2964 2965 case 15: // br/bl (reg) 2966 r := p.To.Reg 2967 if p.As == ABCL || p.As == ABL { 2968 zRR(op_BASR, uint32(REG_LR), uint32(r), asm) 2969 } else { 2970 zRR(op_BCR, 0xF, uint32(r), asm) 2971 } 2972 2973 case 16: // conditional branch 2974 v := int32(0) 2975 if p.Pcond != nil { 2976 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2977 } 2978 mask := c.branchMask(p) 2979 if p.To.Sym == nil && int32(int16(v)) == v { 2980 zRI(op_BRC, mask, uint32(v), asm) 2981 } else { 2982 zRIL(_c, op_BRCL, mask, uint32(v), asm) 2983 } 2984 if p.To.Sym != nil { 2985 c.addrilreloc(p.To.Sym, p.To.Offset) 2986 } 2987 2988 case 17: // move on condition 2989 m3 := c.branchMask(p) 2990 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2991 2992 case 18: // br/bl reg 2993 if p.As == ABL { 2994 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm) 2995 } else { 2996 zRR(op_BCR, 0xF, uint32(p.To.Reg), asm) 2997 } 2998 2999 case 19: // mov $sym+n(SB) reg 3000 d := c.vregoff(&p.From) 3001 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm) 3002 if d&1 != 0 { 3003 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm) 3004 d -= 1 3005 } 3006 c.addrilreloc(p.From.Sym, d) 3007 3008 case 21: // subtract $constant [reg] reg 3009 v := c.vregoff(&p.From) 3010 r := p.Reg 3011 if r == 0 { 3012 r = p.To.Reg 3013 } 3014 switch p.As { 3015 case ASUB: 3016 zRIL(_a, op_LGFI, uint32(REGTMP), uint32(v), asm) 3017 zRRF(op_SLGRK, uint32(REGTMP), 0, uint32(p.To.Reg), uint32(r), asm) 3018 case ASUBC: 3019 if r != p.To.Reg { 3020 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3021 } 3022 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm) 3023 case ASUBW: 3024 if r != p.To.Reg { 3025 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3026 } 3027 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm) 3028 } 3029 3030 case 22: // add/multiply $constant [reg] reg 3031 v := c.vregoff(&p.From) 3032 r := p.Reg 3033 if r == 0 { 3034 r = p.To.Reg 3035 } 3036 var opri, opril, oprie uint32 3037 switch p.As { 3038 case AADD: 3039 opri = op_AGHI 3040 opril = op_AGFI 3041 oprie = op_AGHIK 3042 case AADDC: 3043 opril = op_ALGFI 3044 oprie = op_ALGHSIK 3045 case AADDW: 3046 opri = op_AHI 3047 opril = op_AFI 3048 oprie = op_AHIK 3049 case AMULLW: 3050 opri = op_MHI 3051 opril = op_MSFI 3052 case AMULLD: 3053 opri = op_MGHI 3054 opril = op_MSGFI 3055 } 3056 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) { 3057 switch p.As { 3058 case AADD, AADDC, AMULLD: 3059 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3060 case AADDW, AMULLW: 3061 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3062 } 3063 r = p.To.Reg 3064 } 3065 if r == p.To.Reg { 3066 if opri != 0 && int64(int16(v)) == v { 3067 zRI(opri, uint32(p.To.Reg), uint32(v), asm) 3068 } else { 3069 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm) 3070 } 3071 } else { 3072 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm) 3073 } 3074 3075 case 23: // 64-bit logical op $constant reg 3076 // TODO(mundaym): merge with case 24. 3077 v := c.vregoff(&p.From) 3078 switch p.As { 3079 default: 3080 c.ctxt.Diag("%v is not supported", p) 3081 case AAND: 3082 if v >= 0 { // needs zero extend 3083 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3084 zRRE(op_NGR, uint32(p.To.Reg), REGTMP, asm) 3085 } else if int64(int16(v)) == v { 3086 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3087 } else { // r.To.Reg & 0xffffffff00000000 & uint32(v) 3088 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3089 } 3090 case AOR: 3091 if int64(uint32(v)) != v { // needs sign extend 3092 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3093 zRRE(op_OGR, uint32(p.To.Reg), REGTMP, asm) 3094 } else if int64(uint16(v)) == v { 3095 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3096 } else { 3097 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3098 } 3099 case AXOR: 3100 if int64(uint32(v)) != v { // needs sign extend 3101 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3102 zRRE(op_XGR, uint32(p.To.Reg), REGTMP, asm) 3103 } else { 3104 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3105 } 3106 } 3107 3108 case 24: // 32-bit logical op $constant reg 3109 v := c.vregoff(&p.From) 3110 switch p.As { 3111 case AANDW: 3112 if uint32(v&0xffff0000) == 0xffff0000 { 3113 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3114 } else if uint32(v&0x0000ffff) == 0x0000ffff { 3115 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3116 } else { 3117 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3118 } 3119 case AORW: 3120 if uint32(v&0xffff0000) == 0 { 3121 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3122 } else if uint32(v&0x0000ffff) == 0 { 3123 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3124 } else { 3125 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3126 } 3127 case AXORW: 3128 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3129 } 3130 3131 case 26: // MOVD $offset(base)(index), reg 3132 v := c.regoff(&p.From) 3133 r := p.From.Reg 3134 if r == 0 { 3135 r = o.param 3136 } 3137 i := p.From.Index 3138 if v >= 0 && v < DISP12 { 3139 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3140 } else if v >= -DISP20/2 && v < DISP20/2 { 3141 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3142 } else { 3143 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3144 zRX(op_LA, uint32(p.To.Reg), uint32(r), REGTMP, uint32(i), asm) 3145 } 3146 3147 case 31: // dword 3148 wd := uint64(c.vregoff(&p.From)) 3149 *asm = append(*asm, 3150 uint8(wd>>56), 3151 uint8(wd>>48), 3152 uint8(wd>>40), 3153 uint8(wd>>32), 3154 uint8(wd>>24), 3155 uint8(wd>>16), 3156 uint8(wd>>8), 3157 uint8(wd)) 3158 3159 case 32: // float op freg freg 3160 var opcode uint32 3161 switch p.As { 3162 default: 3163 c.ctxt.Diag("invalid opcode") 3164 case AFADD: 3165 opcode = op_ADBR 3166 case AFADDS: 3167 opcode = op_AEBR 3168 case AFDIV: 3169 opcode = op_DDBR 3170 case AFDIVS: 3171 opcode = op_DEBR 3172 case AFMUL: 3173 opcode = op_MDBR 3174 case AFMULS: 3175 opcode = op_MEEBR 3176 case AFSUB: 3177 opcode = op_SDBR 3178 case AFSUBS: 3179 opcode = op_SEBR 3180 } 3181 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3182 3183 case 33: // float op [freg] freg 3184 r := p.From.Reg 3185 if oclass(&p.From) == C_NONE { 3186 r = p.To.Reg 3187 } 3188 var opcode uint32 3189 switch p.As { 3190 default: 3191 case AFABS: 3192 opcode = op_LPDBR 3193 case AFNABS: 3194 opcode = op_LNDBR 3195 case ALPDFR: 3196 opcode = op_LPDFR 3197 case ALNDFR: 3198 opcode = op_LNDFR 3199 case AFNEG: 3200 opcode = op_LCDFR 3201 case AFNEGS: 3202 opcode = op_LCEBR 3203 case ALEDBR: 3204 opcode = op_LEDBR 3205 case ALDEBR: 3206 opcode = op_LDEBR 3207 case AFSQRT: 3208 opcode = op_SQDBR 3209 case AFSQRTS: 3210 opcode = op_SQEBR 3211 } 3212 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3213 3214 case 34: // float multiply-add freg freg freg 3215 var opcode uint32 3216 switch p.As { 3217 default: 3218 c.ctxt.Diag("invalid opcode") 3219 case AFMADD: 3220 opcode = op_MADBR 3221 case AFMADDS: 3222 opcode = op_MAEBR 3223 case AFMSUB: 3224 opcode = op_MSDBR 3225 case AFMSUBS: 3226 opcode = op_MSEBR 3227 } 3228 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 3229 3230 case 35: // mov reg mem (no relocation) 3231 d2 := c.regoff(&p.To) 3232 b2 := p.To.Reg 3233 if b2 == 0 { 3234 b2 = o.param 3235 } 3236 x2 := p.To.Index 3237 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3238 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3239 if x2 != 0 { 3240 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3241 } 3242 x2 = REGTMP 3243 d2 = 0 3244 } 3245 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3246 3247 case 36: // mov mem reg (no relocation) 3248 d2 := c.regoff(&p.From) 3249 b2 := p.From.Reg 3250 if b2 == 0 { 3251 b2 = o.param 3252 } 3253 x2 := p.From.Index 3254 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3255 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3256 if x2 != 0 { 3257 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3258 } 3259 x2 = REGTMP 3260 d2 = 0 3261 } 3262 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3263 3264 case 40: // word/byte 3265 wd := uint32(c.regoff(&p.From)) 3266 if p.As == AWORD { //WORD 3267 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd)) 3268 } else { //BYTE 3269 *asm = append(*asm, uint8(wd)) 3270 } 3271 3272 case 47: // negate [reg] reg 3273 r := p.From.Reg 3274 if r == 0 { 3275 r = p.To.Reg 3276 } 3277 switch p.As { 3278 case ANEG: 3279 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm) 3280 case ANEGW: 3281 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm) 3282 } 3283 3284 case 48: // floating-point round to integer 3285 m3 := c.vregoff(&p.From) 3286 if 0 > m3 || m3 > 7 { 3287 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3) 3288 } 3289 var opcode uint32 3290 switch p.As { 3291 case AFIEBR: 3292 opcode = op_FIEBR 3293 case AFIDBR: 3294 opcode = op_FIDBR 3295 } 3296 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3297 3298 case 49: // copysign 3299 zRRF(op_CPSDR, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3300 3301 case 67: // fmov $0 freg 3302 var opcode uint32 3303 switch p.As { 3304 case AFMOVS: 3305 opcode = op_LZER 3306 case AFMOVD: 3307 opcode = op_LZDR 3308 } 3309 zRRE(opcode, uint32(p.To.Reg), 0, asm) 3310 3311 case 68: // movw areg reg 3312 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm) 3313 3314 case 69: // movw reg areg 3315 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm) 3316 3317 case 70: // cmp reg reg 3318 if p.As == ACMPW || p.As == ACMPWU { 3319 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3320 } else { 3321 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3322 } 3323 3324 case 71: // cmp reg $constant 3325 v := c.vregoff(&p.To) 3326 switch p.As { 3327 case ACMP, ACMPW: 3328 if int64(int32(v)) != v { 3329 c.ctxt.Diag("%v overflows an int32", v) 3330 } 3331 case ACMPU, ACMPWU: 3332 if int64(uint32(v)) != v { 3333 c.ctxt.Diag("%v overflows a uint32", v) 3334 } 3335 } 3336 if p.As == ACMP && int64(int16(v)) == v { 3337 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm) 3338 } else if p.As == ACMPW && int64(int16(v)) == v { 3339 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm) 3340 } else { 3341 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm) 3342 } 3343 3344 case 72: // mov $constant mem 3345 v := c.regoff(&p.From) 3346 d := c.regoff(&p.To) 3347 r := p.To.Reg 3348 if p.To.Index != 0 { 3349 c.ctxt.Diag("cannot use index register") 3350 } 3351 if r == 0 { 3352 r = o.param 3353 } 3354 var opcode uint32 3355 switch p.As { 3356 case AMOVD: 3357 opcode = op_MVGHI 3358 case AMOVW, AMOVWZ: 3359 opcode = op_MVHI 3360 case AMOVH, AMOVHZ: 3361 opcode = op_MVHHI 3362 case AMOVB, AMOVBZ: 3363 opcode = op_MVI 3364 } 3365 if d < 0 || d >= DISP12 { 3366 if r == REGTMP { 3367 c.ctxt.Diag("displacement must be in range [0, 4096) to use %v", r) 3368 } 3369 if d >= -DISP20/2 && d < DISP20/2 { 3370 if opcode == op_MVI { 3371 opcode = op_MVIY 3372 } else { 3373 zRXY(op_LAY, uint32(REGTMP), 0, uint32(r), uint32(d), asm) 3374 r = REGTMP 3375 d = 0 3376 } 3377 } else { 3378 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm) 3379 zRX(op_LA, REGTMP, REGTMP, uint32(r), 0, asm) 3380 r = REGTMP 3381 d = 0 3382 } 3383 } 3384 switch opcode { 3385 case op_MVI: 3386 zSI(opcode, uint32(v), uint32(r), uint32(d), asm) 3387 case op_MVIY: 3388 zSIY(opcode, uint32(v), uint32(r), uint32(d), asm) 3389 default: 3390 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm) 3391 } 3392 3393 case 74: // mov reg addr (including relocation) 3394 i2 := c.regoff(&p.To) 3395 switch p.As { 3396 case AMOVD: 3397 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm) 3398 case AMOVW, AMOVWZ: // The zero extension doesn't affect store instructions 3399 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm) 3400 case AMOVH, AMOVHZ: // The zero extension doesn't affect store instructions 3401 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm) 3402 case AMOVB, AMOVBZ: // The zero extension doesn't affect store instructions 3403 zRIL(_b, op_LARL, REGTMP, 0, asm) 3404 adj := uint32(0) // adjustment needed for odd addresses 3405 if i2&1 != 0 { 3406 i2 -= 1 3407 adj = 1 3408 } 3409 zRX(op_STC, uint32(p.From.Reg), 0, REGTMP, adj, asm) 3410 case AFMOVD: 3411 zRIL(_b, op_LARL, REGTMP, 0, asm) 3412 zRX(op_STD, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3413 case AFMOVS: 3414 zRIL(_b, op_LARL, REGTMP, 0, asm) 3415 zRX(op_STE, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3416 } 3417 c.addrilreloc(p.To.Sym, int64(i2)) 3418 3419 case 75: // mov addr reg (including relocation) 3420 i2 := c.regoff(&p.From) 3421 switch p.As { 3422 case AMOVD: 3423 if i2&1 != 0 { 3424 zRIL(_b, op_LARL, REGTMP, 0, asm) 3425 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 1, asm) 3426 i2 -= 1 3427 } else { 3428 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3429 } 3430 case AMOVW: 3431 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm) 3432 case AMOVWZ: 3433 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm) 3434 case AMOVH: 3435 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm) 3436 case AMOVHZ: 3437 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm) 3438 case AMOVB, AMOVBZ: 3439 zRIL(_b, op_LARL, REGTMP, 0, asm) 3440 adj := uint32(0) // adjustment needed for odd addresses 3441 if i2&1 != 0 { 3442 i2 -= 1 3443 adj = 1 3444 } 3445 switch p.As { 3446 case AMOVB: 3447 zRXY(op_LGB, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3448 case AMOVBZ: 3449 zRXY(op_LLGC, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3450 } 3451 case AFMOVD: 3452 zRIL(_a, op_LARL, REGTMP, 0, asm) 3453 zRX(op_LD, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3454 case AFMOVS: 3455 zRIL(_a, op_LARL, REGTMP, 0, asm) 3456 zRX(op_LE, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3457 } 3458 c.addrilreloc(p.From.Sym, int64(i2)) 3459 3460 case 77: // syscall $constant 3461 if p.From.Offset > 255 || p.From.Offset < 1 { 3462 c.ctxt.Diag("illegal system call; system call number out of range: %v", p) 3463 zE(op_TRAP2, asm) // trap always 3464 } else { 3465 zI(op_SVC, uint32(p.From.Offset), asm) 3466 } 3467 3468 case 78: // undef 3469 // "An instruction consisting entirely of binary 0s is guaranteed 3470 // always to be an illegal instruction." 3471 *asm = append(*asm, 0, 0, 0, 0) 3472 3473 case 79: // compare and swap reg reg reg 3474 v := c.regoff(&p.To) 3475 if v < 0 { 3476 v = 0 3477 } 3478 if p.As == ACS { 3479 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3480 } else if p.As == ACSG { 3481 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3482 } 3483 3484 case 80: // sync 3485 zRR(op_BCR, 0xE, 0, asm) 3486 3487 case 81: // float to fixed and fixed to float moves (no conversion) 3488 switch p.As { 3489 case ALDGR: 3490 zRRE(op_LDGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3491 case ALGDR: 3492 zRRE(op_LGDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3493 } 3494 3495 case 82: // fixed to float conversion 3496 var opcode uint32 3497 switch p.As { 3498 default: 3499 log.Fatalf("unexpected opcode %v", p.As) 3500 case ACEFBRA: 3501 opcode = op_CEFBRA 3502 case ACDFBRA: 3503 opcode = op_CDFBRA 3504 case ACEGBRA: 3505 opcode = op_CEGBRA 3506 case ACDGBRA: 3507 opcode = op_CDGBRA 3508 case ACELFBR: 3509 opcode = op_CELFBR 3510 case ACDLFBR: 3511 opcode = op_CDLFBR 3512 case ACELGBR: 3513 opcode = op_CELGBR 3514 case ACDLGBR: 3515 opcode = op_CDLGBR 3516 } 3517 // set immediate operand M3 to 0 to use the default BFP rounding mode 3518 // (usually round to nearest, ties to even) 3519 // TODO(mundaym): should this be fixed at round to nearest, ties to even? 3520 // M4 is reserved and must be 0 3521 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3522 3523 case 83: // float to fixed conversion 3524 var opcode uint32 3525 switch p.As { 3526 default: 3527 log.Fatalf("unexpected opcode %v", p.As) 3528 case ACFEBRA: 3529 opcode = op_CFEBRA 3530 case ACFDBRA: 3531 opcode = op_CFDBRA 3532 case ACGEBRA: 3533 opcode = op_CGEBRA 3534 case ACGDBRA: 3535 opcode = op_CGDBRA 3536 case ACLFEBR: 3537 opcode = op_CLFEBR 3538 case ACLFDBR: 3539 opcode = op_CLFDBR 3540 case ACLGEBR: 3541 opcode = op_CLGEBR 3542 case ACLGDBR: 3543 opcode = op_CLGDBR 3544 } 3545 // set immediate operand M3 to 5 for rounding toward zero (required by Go spec) 3546 // M4 is reserved and must be 0 3547 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3548 3549 case 84: // storage-and-storage operations $length mem mem 3550 l := c.regoff(&p.From) 3551 if l < 1 || l > 256 { 3552 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l) 3553 } 3554 if p.GetFrom3().Index != 0 || p.To.Index != 0 { 3555 c.ctxt.Diag("cannot use index reg") 3556 } 3557 b1 := p.To.Reg 3558 b2 := p.GetFrom3().Reg 3559 if b1 == 0 { 3560 b1 = o.param 3561 } 3562 if b2 == 0 { 3563 b2 = o.param 3564 } 3565 d1 := c.regoff(&p.To) 3566 d2 := c.regoff(p.GetFrom3()) 3567 if d1 < 0 || d1 >= DISP12 { 3568 if b2 == REGTMP { 3569 c.ctxt.Diag("REGTMP conflict") 3570 } 3571 if b1 != REGTMP { 3572 zRRE(op_LGR, REGTMP, uint32(b1), asm) 3573 } 3574 zRIL(_a, op_AGFI, REGTMP, uint32(d1), asm) 3575 if d1 == d2 && b1 == b2 { 3576 d2 = 0 3577 b2 = REGTMP 3578 } 3579 d1 = 0 3580 b1 = REGTMP 3581 } 3582 if d2 < 0 || d2 >= DISP12 { 3583 if b1 == REGTMP2 { 3584 c.ctxt.Diag("REGTMP2 conflict") 3585 } 3586 if b2 != REGTMP2 { 3587 zRRE(op_LGR, REGTMP2, uint32(b2), asm) 3588 } 3589 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm) 3590 d2 = 0 3591 b2 = REGTMP2 3592 } 3593 var opcode uint32 3594 switch p.As { 3595 default: 3596 c.ctxt.Diag("unexpected opcode %v", p.As) 3597 case AMVC: 3598 opcode = op_MVC 3599 case ACLC: 3600 opcode = op_CLC 3601 // swap operand order for CLC so that it matches CMP 3602 b1, b2 = b2, b1 3603 d1, d2 = d2, d1 3604 case AXC: 3605 opcode = op_XC 3606 case AOC: 3607 opcode = op_OC 3608 case ANC: 3609 opcode = op_NC 3610 } 3611 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm) 3612 3613 case 85: // load address relative long 3614 v := c.regoff(&p.From) 3615 if p.From.Sym == nil { 3616 if (v & 1) != 0 { 3617 c.ctxt.Diag("cannot use LARL with odd offset: %v", v) 3618 } 3619 } else { 3620 c.addrilreloc(p.From.Sym, int64(v)) 3621 v = 0 3622 } 3623 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm) 3624 3625 case 86: // load address 3626 d := c.vregoff(&p.From) 3627 x := p.From.Index 3628 b := p.From.Reg 3629 if b == 0 { 3630 b = o.param 3631 } 3632 switch p.As { 3633 case ALA: 3634 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3635 case ALAY: 3636 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3637 } 3638 3639 case 87: // execute relative long 3640 v := c.vregoff(&p.From) 3641 if p.From.Sym == nil { 3642 if v&1 != 0 { 3643 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v) 3644 } 3645 } else { 3646 c.addrilreloc(p.From.Sym, v) 3647 v = 0 3648 } 3649 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm) 3650 3651 case 88: // store clock 3652 var opcode uint32 3653 switch p.As { 3654 case ASTCK: 3655 opcode = op_STCK 3656 case ASTCKC: 3657 opcode = op_STCKC 3658 case ASTCKE: 3659 opcode = op_STCKE 3660 case ASTCKF: 3661 opcode = op_STCKF 3662 } 3663 v := c.vregoff(&p.To) 3664 r := int(p.To.Reg) 3665 if r == 0 { 3666 r = int(o.param) 3667 } 3668 zS(opcode, uint32(r), uint32(v), asm) 3669 3670 case 89: // compare and branch reg reg 3671 var v int32 3672 if p.Pcond != nil { 3673 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3674 } 3675 var opcode, opcode2 uint32 3676 switch p.As { 3677 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3678 opcode = op_CGRJ 3679 opcode2 = op_CGR 3680 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3681 opcode = op_CLGRJ 3682 opcode2 = op_CLGR 3683 } 3684 mask := c.branchMask(p) 3685 if int32(int16(v)) != v { 3686 zRRE(opcode2, uint32(p.From.Reg), uint32(p.Reg), asm) 3687 zRIL(_c, op_BRCL, mask, uint32(v-sizeRRE/2), asm) 3688 } else { 3689 zRIE(_b, opcode, uint32(p.From.Reg), uint32(p.Reg), uint32(v), 0, 0, mask, 0, asm) 3690 } 3691 3692 case 90: // compare and branch reg $constant 3693 var v int32 3694 if p.Pcond != nil { 3695 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3696 } 3697 var opcode, opcode2 uint32 3698 switch p.As { 3699 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3700 opcode = op_CGIJ 3701 opcode2 = op_CGFI 3702 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3703 opcode = op_CLGIJ 3704 opcode2 = op_CLGFI 3705 } 3706 mask := c.branchMask(p) 3707 if int32(int16(v)) != v { 3708 zRIL(_a, opcode2, uint32(p.From.Reg), uint32(c.regoff(p.GetFrom3())), asm) 3709 zRIL(_c, op_BRCL, mask, uint32(v-sizeRIL/2), asm) 3710 } else { 3711 zRIE(_c, opcode, uint32(p.From.Reg), mask, uint32(v), 0, 0, 0, uint32(c.regoff(p.GetFrom3())), asm) 3712 } 3713 3714 case 91: // test under mask (immediate) 3715 var opcode uint32 3716 switch p.As { 3717 case ATMHH: 3718 opcode = op_TMHH 3719 case ATMHL: 3720 opcode = op_TMHL 3721 case ATMLH: 3722 opcode = op_TMLH 3723 case ATMLL: 3724 opcode = op_TMLL 3725 } 3726 zRI(opcode, uint32(p.From.Reg), uint32(c.vregoff(&p.To)), asm) 3727 3728 case 93: // GOT lookup 3729 v := c.vregoff(&p.To) 3730 if v != 0 { 3731 c.ctxt.Diag("invalid offset against GOT slot %v", p) 3732 } 3733 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3734 rel := obj.Addrel(c.cursym) 3735 rel.Off = int32(c.pc + 2) 3736 rel.Siz = 4 3737 rel.Sym = p.From.Sym 3738 rel.Type = objabi.R_GOTPCREL 3739 rel.Add = 2 + int64(rel.Siz) 3740 3741 case 94: // TLS local exec model 3742 zRIL(_b, op_LARL, REGTMP, (sizeRIL+sizeRXY+sizeRI)>>1, asm) 3743 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3744 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm) 3745 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0) 3746 rel := obj.Addrel(c.cursym) 3747 rel.Off = int32(c.pc + sizeRIL + sizeRXY + sizeRI) 3748 rel.Siz = 8 3749 rel.Sym = p.From.Sym 3750 rel.Type = objabi.R_TLS_LE 3751 rel.Add = 0 3752 3753 case 95: // TLS initial exec model 3754 // Assembly | Relocation symbol | Done Here? 3755 // -------------------------------------------------------------- 3756 // ear %r11, %a0 | | 3757 // sllg %r11, %r11, 32 | | 3758 // ear %r11, %a1 | | 3759 // larl %r10, <var>@indntpoff | R_390_TLS_IEENT | Y 3760 // lg %r10, 0(%r10) | R_390_TLS_LOAD (tag) | Y 3761 // la %r10, 0(%r10, %r11) | | 3762 // -------------------------------------------------------------- 3763 3764 // R_390_TLS_IEENT 3765 zRIL(_b, op_LARL, REGTMP, 0, asm) 3766 ieent := obj.Addrel(c.cursym) 3767 ieent.Off = int32(c.pc + 2) 3768 ieent.Siz = 4 3769 ieent.Sym = p.From.Sym 3770 ieent.Type = objabi.R_TLS_IE 3771 ieent.Add = 2 + int64(ieent.Siz) 3772 3773 // R_390_TLS_LOAD 3774 zRXY(op_LGF, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3775 // TODO(mundaym): add R_390_TLS_LOAD relocation here 3776 // not strictly required but might allow the linker to optimize 3777 3778 case 96: // clear macro 3779 length := c.vregoff(&p.From) 3780 offset := c.vregoff(&p.To) 3781 reg := p.To.Reg 3782 if reg == 0 { 3783 reg = o.param 3784 } 3785 if length <= 0 { 3786 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length) 3787 } 3788 for length > 0 { 3789 if offset < 0 || offset >= DISP12 { 3790 if offset >= -DISP20/2 && offset < DISP20/2 { 3791 zRXY(op_LAY, REGTMP, uint32(reg), 0, uint32(offset), asm) 3792 } else { 3793 if reg != REGTMP { 3794 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3795 } 3796 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3797 } 3798 reg = REGTMP 3799 offset = 0 3800 } 3801 size := length 3802 if size > 256 { 3803 size = 256 3804 } 3805 3806 switch size { 3807 case 1: 3808 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm) 3809 case 2: 3810 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm) 3811 case 4: 3812 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm) 3813 case 8: 3814 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm) 3815 default: 3816 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm) 3817 } 3818 3819 length -= size 3820 offset += size 3821 } 3822 3823 case 97: // store multiple 3824 rstart := p.From.Reg 3825 rend := p.Reg 3826 offset := c.regoff(&p.To) 3827 reg := p.To.Reg 3828 if reg == 0 { 3829 reg = o.param 3830 } 3831 if offset < -DISP20/2 || offset >= DISP20/2 { 3832 if reg != REGTMP { 3833 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3834 } 3835 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3836 reg = REGTMP 3837 offset = 0 3838 } 3839 switch p.As { 3840 case ASTMY: 3841 if offset >= 0 && offset < DISP12 { 3842 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3843 } else { 3844 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3845 } 3846 case ASTMG: 3847 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3848 } 3849 3850 case 98: // load multiple 3851 rstart := p.Reg 3852 rend := p.To.Reg 3853 offset := c.regoff(&p.From) 3854 reg := p.From.Reg 3855 if reg == 0 { 3856 reg = o.param 3857 } 3858 if offset < -DISP20/2 || offset >= DISP20/2 { 3859 if reg != REGTMP { 3860 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3861 } 3862 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3863 reg = REGTMP 3864 offset = 0 3865 } 3866 switch p.As { 3867 case ALMY: 3868 if offset >= 0 && offset < DISP12 { 3869 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3870 } else { 3871 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3872 } 3873 case ALMG: 3874 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3875 } 3876 3877 case 99: // interlocked load and op 3878 if p.To.Index != 0 { 3879 c.ctxt.Diag("cannot use indexed address") 3880 } 3881 offset := c.regoff(&p.To) 3882 if offset < -DISP20/2 || offset >= DISP20/2 { 3883 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset) 3884 } 3885 var opcode uint32 3886 switch p.As { 3887 case ALAA: 3888 opcode = op_LAA 3889 case ALAAG: 3890 opcode = op_LAAG 3891 case ALAAL: 3892 opcode = op_LAAL 3893 case ALAALG: 3894 opcode = op_LAALG 3895 case ALAN: 3896 opcode = op_LAN 3897 case ALANG: 3898 opcode = op_LANG 3899 case ALAX: 3900 opcode = op_LAX 3901 case ALAXG: 3902 opcode = op_LAXG 3903 case ALAO: 3904 opcode = op_LAO 3905 case ALAOG: 3906 opcode = op_LAOG 3907 } 3908 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm) 3909 3910 case 100: // VRX STORE 3911 op, m3, _ := vop(p.As) 3912 v1 := p.From.Reg 3913 if p.Reg != 0 { 3914 m3 = uint32(c.vregoff(&p.From)) 3915 v1 = p.Reg 3916 } 3917 b2 := p.To.Reg 3918 if b2 == 0 { 3919 b2 = o.param 3920 } 3921 d2 := uint32(c.vregoff(&p.To)) 3922 zVRX(op, uint32(v1), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3923 3924 case 101: // VRX LOAD 3925 op, m3, _ := vop(p.As) 3926 src := &p.From 3927 if p.GetFrom3() != nil { 3928 m3 = uint32(c.vregoff(&p.From)) 3929 src = p.GetFrom3() 3930 } 3931 b2 := src.Reg 3932 if b2 == 0 { 3933 b2 = o.param 3934 } 3935 d2 := uint32(c.vregoff(src)) 3936 zVRX(op, uint32(p.To.Reg), uint32(src.Index), uint32(b2), d2, m3, asm) 3937 3938 case 102: // VRV SCATTER 3939 op, _, _ := vop(p.As) 3940 m3 := uint32(c.vregoff(&p.From)) 3941 b2 := p.To.Reg 3942 if b2 == 0 { 3943 b2 = o.param 3944 } 3945 d2 := uint32(c.vregoff(&p.To)) 3946 zVRV(op, uint32(p.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3947 3948 case 103: // VRV GATHER 3949 op, _, _ := vop(p.As) 3950 m3 := uint32(c.vregoff(&p.From)) 3951 b2 := p.GetFrom3().Reg 3952 if b2 == 0 { 3953 b2 = o.param 3954 } 3955 d2 := uint32(c.vregoff(p.GetFrom3())) 3956 zVRV(op, uint32(p.To.Reg), uint32(p.GetFrom3().Index), uint32(b2), d2, m3, asm) 3957 3958 case 104: // VRS SHIFT/ROTATE and LOAD GR FROM VR ELEMENT 3959 op, m4, _ := vop(p.As) 3960 fr := p.Reg 3961 if fr == 0 { 3962 fr = p.To.Reg 3963 } 3964 bits := uint32(c.vregoff(&p.From)) 3965 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm) 3966 3967 case 105: // VRS STORE MULTIPLE 3968 op, _, _ := vop(p.As) 3969 offset := uint32(c.vregoff(&p.To)) 3970 reg := p.To.Reg 3971 if reg == 0 { 3972 reg = o.param 3973 } 3974 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm) 3975 3976 case 106: // VRS LOAD MULTIPLE 3977 op, _, _ := vop(p.As) 3978 offset := uint32(c.vregoff(&p.From)) 3979 reg := p.From.Reg 3980 if reg == 0 { 3981 reg = o.param 3982 } 3983 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm) 3984 3985 case 107: // VRS STORE WITH LENGTH 3986 op, _, _ := vop(p.As) 3987 offset := uint32(c.vregoff(&p.To)) 3988 reg := p.To.Reg 3989 if reg == 0 { 3990 reg = o.param 3991 } 3992 zVRS(op, uint32(p.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 3993 3994 case 108: // VRS LOAD WITH LENGTH 3995 op, _, _ := vop(p.As) 3996 offset := uint32(c.vregoff(p.GetFrom3())) 3997 reg := p.GetFrom3().Reg 3998 if reg == 0 { 3999 reg = o.param 4000 } 4001 zVRS(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 4002 4003 case 109: // VRI-a 4004 op, m3, _ := vop(p.As) 4005 i2 := uint32(c.vregoff(&p.From)) 4006 if p.GetFrom3() != nil { 4007 m3 = uint32(c.vregoff(&p.From)) 4008 i2 = uint32(c.vregoff(p.GetFrom3())) 4009 } 4010 switch p.As { 4011 case AVZERO: 4012 i2 = 0 4013 case AVONE: 4014 i2 = 0xffff 4015 } 4016 zVRIa(op, uint32(p.To.Reg), i2, m3, asm) 4017 4018 case 110: 4019 op, m4, _ := vop(p.As) 4020 i2 := uint32(c.vregoff(&p.From)) 4021 i3 := uint32(c.vregoff(p.GetFrom3())) 4022 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm) 4023 4024 case 111: 4025 op, m4, _ := vop(p.As) 4026 i2 := uint32(c.vregoff(&p.From)) 4027 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm) 4028 4029 case 112: 4030 op, m5, _ := vop(p.As) 4031 i4 := uint32(c.vregoff(&p.From)) 4032 zVRId(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), i4, m5, asm) 4033 4034 case 113: 4035 op, m4, _ := vop(p.As) 4036 m5 := singleElementMask(p.As) 4037 i3 := uint32(c.vregoff(&p.From)) 4038 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm) 4039 4040 case 114: // VRR-a 4041 op, m3, m5 := vop(p.As) 4042 m4 := singleElementMask(p.As) 4043 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm) 4044 4045 case 115: // VRR-a COMPARE 4046 op, m3, m5 := vop(p.As) 4047 m4 := singleElementMask(p.As) 4048 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm) 4049 4050 case 117: // VRR-b 4051 op, m4, m5 := vop(p.As) 4052 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm) 4053 4054 case 118: // VRR-c 4055 op, m4, m6 := vop(p.As) 4056 m5 := singleElementMask(p.As) 4057 v3 := p.Reg 4058 if v3 == 0 { 4059 v3 = p.To.Reg 4060 } 4061 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm) 4062 4063 case 119: // VRR-c SHIFT/ROTATE/DIVIDE/SUB (rhs value on the left, like SLD, DIV etc.) 4064 op, m4, m6 := vop(p.As) 4065 m5 := singleElementMask(p.As) 4066 v2 := p.Reg 4067 if v2 == 0 { 4068 v2 = p.To.Reg 4069 } 4070 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm) 4071 4072 case 120: // VRR-d 4073 op, m6, _ := vop(p.As) 4074 m5 := singleElementMask(p.As) 4075 v1 := uint32(p.To.Reg) 4076 v2 := uint32(p.From.Reg) 4077 v3 := uint32(p.Reg) 4078 v4 := uint32(p.GetFrom3().Reg) 4079 zVRRd(op, v1, v2, v3, m6, m5, v4, asm) 4080 4081 case 121: // VRR-e 4082 op, m6, _ := vop(p.As) 4083 m5 := singleElementMask(p.As) 4084 v1 := uint32(p.To.Reg) 4085 v2 := uint32(p.From.Reg) 4086 v3 := uint32(p.Reg) 4087 v4 := uint32(p.GetFrom3().Reg) 4088 zVRRe(op, v1, v2, v3, m6, m5, v4, asm) 4089 4090 case 122: // VRR-f LOAD VRS FROM GRS DISJOINT 4091 op, _, _ := vop(p.As) 4092 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 4093 4094 case 123: // VPDI $m4, V2, V3, V1 4095 op, _, _ := vop(p.As) 4096 m4 := c.regoff(&p.From) 4097 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), 0, 0, uint32(m4), asm) 4098 } 4099 } 4100 4101 func (c *ctxtz) vregoff(a *obj.Addr) int64 { 4102 c.instoffset = 0 4103 if a != nil { 4104 c.aclass(a) 4105 } 4106 return c.instoffset 4107 } 4108 4109 func (c *ctxtz) regoff(a *obj.Addr) int32 { 4110 return int32(c.vregoff(a)) 4111 } 4112 4113 // zopload returns the RXY op for the given load 4114 func (c *ctxtz) zopload(a obj.As) uint32 { 4115 switch a { 4116 // fixed point load 4117 case AMOVD: 4118 return op_LG 4119 case AMOVW: 4120 return op_LGF 4121 case AMOVWZ: 4122 return op_LLGF 4123 case AMOVH: 4124 return op_LGH 4125 case AMOVHZ: 4126 return op_LLGH 4127 case AMOVB: 4128 return op_LGB 4129 case AMOVBZ: 4130 return op_LLGC 4131 4132 // floating point load 4133 case AFMOVD: 4134 return op_LDY 4135 case AFMOVS: 4136 return op_LEY 4137 4138 // byte reversed load 4139 case AMOVDBR: 4140 return op_LRVG 4141 case AMOVWBR: 4142 return op_LRV 4143 case AMOVHBR: 4144 return op_LRVH 4145 } 4146 4147 c.ctxt.Diag("unknown store opcode %v", a) 4148 return 0 4149 } 4150 4151 // zopstore returns the RXY op for the given store 4152 func (c *ctxtz) zopstore(a obj.As) uint32 { 4153 switch a { 4154 // fixed point store 4155 case AMOVD: 4156 return op_STG 4157 case AMOVW, AMOVWZ: 4158 return op_STY 4159 case AMOVH, AMOVHZ: 4160 return op_STHY 4161 case AMOVB, AMOVBZ: 4162 return op_STCY 4163 4164 // floating point store 4165 case AFMOVD: 4166 return op_STDY 4167 case AFMOVS: 4168 return op_STEY 4169 4170 // byte reversed store 4171 case AMOVDBR: 4172 return op_STRVG 4173 case AMOVWBR: 4174 return op_STRV 4175 case AMOVHBR: 4176 return op_STRVH 4177 } 4178 4179 c.ctxt.Diag("unknown store opcode %v", a) 4180 return 0 4181 } 4182 4183 // zoprre returns the RRE op for the given a 4184 func (c *ctxtz) zoprre(a obj.As) uint32 { 4185 switch a { 4186 case ACMP: 4187 return op_CGR 4188 case ACMPU: 4189 return op_CLGR 4190 case AFCMPO: //ordered 4191 return op_KDBR 4192 case AFCMPU: //unordered 4193 return op_CDBR 4194 case ACEBR: 4195 return op_CEBR 4196 } 4197 c.ctxt.Diag("unknown rre opcode %v", a) 4198 return 0 4199 } 4200 4201 // zoprr returns the RR op for the given a 4202 func (c *ctxtz) zoprr(a obj.As) uint32 { 4203 switch a { 4204 case ACMPW: 4205 return op_CR 4206 case ACMPWU: 4207 return op_CLR 4208 } 4209 c.ctxt.Diag("unknown rr opcode %v", a) 4210 return 0 4211 } 4212 4213 // zopril returns the RIL op for the given a 4214 func (c *ctxtz) zopril(a obj.As) uint32 { 4215 switch a { 4216 case ACMP: 4217 return op_CGFI 4218 case ACMPU: 4219 return op_CLGFI 4220 case ACMPW: 4221 return op_CFI 4222 case ACMPWU: 4223 return op_CLFI 4224 } 4225 c.ctxt.Diag("unknown ril opcode %v", a) 4226 return 0 4227 } 4228 4229 // z instructions sizes 4230 const ( 4231 sizeE = 2 4232 sizeI = 2 4233 sizeIE = 4 4234 sizeMII = 6 4235 sizeRI = 4 4236 sizeRI1 = 4 4237 sizeRI2 = 4 4238 sizeRI3 = 4 4239 sizeRIE = 6 4240 sizeRIE1 = 6 4241 sizeRIE2 = 6 4242 sizeRIE3 = 6 4243 sizeRIE4 = 6 4244 sizeRIE5 = 6 4245 sizeRIE6 = 6 4246 sizeRIL = 6 4247 sizeRIL1 = 6 4248 sizeRIL2 = 6 4249 sizeRIL3 = 6 4250 sizeRIS = 6 4251 sizeRR = 2 4252 sizeRRD = 4 4253 sizeRRE = 4 4254 sizeRRF = 4 4255 sizeRRF1 = 4 4256 sizeRRF2 = 4 4257 sizeRRF3 = 4 4258 sizeRRF4 = 4 4259 sizeRRF5 = 4 4260 sizeRRR = 2 4261 sizeRRS = 6 4262 sizeRS = 4 4263 sizeRS1 = 4 4264 sizeRS2 = 4 4265 sizeRSI = 4 4266 sizeRSL = 6 4267 sizeRSY = 6 4268 sizeRSY1 = 6 4269 sizeRSY2 = 6 4270 sizeRX = 4 4271 sizeRX1 = 4 4272 sizeRX2 = 4 4273 sizeRXE = 6 4274 sizeRXF = 6 4275 sizeRXY = 6 4276 sizeRXY1 = 6 4277 sizeRXY2 = 6 4278 sizeS = 4 4279 sizeSI = 4 4280 sizeSIL = 6 4281 sizeSIY = 6 4282 sizeSMI = 6 4283 sizeSS = 6 4284 sizeSS1 = 6 4285 sizeSS2 = 6 4286 sizeSS3 = 6 4287 sizeSS4 = 6 4288 sizeSS5 = 6 4289 sizeSS6 = 6 4290 sizeSSE = 6 4291 sizeSSF = 6 4292 ) 4293 4294 // instruction format variations 4295 type form int 4296 4297 const ( 4298 _a form = iota 4299 _b 4300 _c 4301 _d 4302 _e 4303 _f 4304 ) 4305 4306 func zE(op uint32, asm *[]byte) { 4307 *asm = append(*asm, uint8(op>>8), uint8(op)) 4308 } 4309 4310 func zI(op, i1 uint32, asm *[]byte) { 4311 *asm = append(*asm, uint8(op>>8), uint8(i1)) 4312 } 4313 4314 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) { 4315 *asm = append(*asm, 4316 uint8(op>>8), 4317 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F), 4318 uint8(ri2), 4319 uint8(ri3>>16), 4320 uint8(ri3>>8), 4321 uint8(ri3)) 4322 } 4323 4324 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4325 *asm = append(*asm, 4326 uint8(op>>8), 4327 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4328 uint8(i2_ri2>>8), 4329 uint8(i2_ri2)) 4330 } 4331 4332 // Expected argument values for the instruction formats. 4333 // 4334 // Format a1 a2 a3 a4 a5 a6 a7 4335 // ------------------------------------ 4336 // a r1, 0, i2, 0, 0, m3, 0 4337 // b r1, r2, ri4, 0, 0, m3, 0 4338 // c r1, m3, ri4, 0, 0, 0, i2 4339 // d r1, r3, i2, 0, 0, 0, 0 4340 // e r1, r3, ri2, 0, 0, 0, 0 4341 // f r1, r2, 0, i3, i4, 0, i5 4342 // g r1, m3, i2, 0, 0, 0, 0 4343 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) { 4344 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F)) 4345 4346 switch f { 4347 default: 4348 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2)) 4349 case _f: 4350 *asm = append(*asm, uint8(i3), uint8(i4)) 4351 } 4352 4353 switch f { 4354 case _a, _b: 4355 *asm = append(*asm, uint8(m3)<<4) 4356 default: 4357 *asm = append(*asm, uint8(i2_i5)) 4358 } 4359 4360 *asm = append(*asm, uint8(op)) 4361 } 4362 4363 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4364 if f == _a || f == _b { 4365 r1_m1 = r1_m1 - obj.RBaseS390X // this is a register base 4366 } 4367 *asm = append(*asm, 4368 uint8(op>>8), 4369 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4370 uint8(i2_ri2>>24), 4371 uint8(i2_ri2>>16), 4372 uint8(i2_ri2>>8), 4373 uint8(i2_ri2)) 4374 } 4375 4376 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) { 4377 *asm = append(*asm, 4378 uint8(op>>8), 4379 (uint8(r1)<<4)|uint8(m3&0x0F), 4380 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F), 4381 uint8(d4), 4382 uint8(i2), 4383 uint8(op)) 4384 } 4385 4386 func zRR(op, r1, r2 uint32, asm *[]byte) { 4387 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F)) 4388 } 4389 4390 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) { 4391 *asm = append(*asm, 4392 uint8(op>>8), 4393 uint8(op), 4394 uint8(r1)<<4, 4395 (uint8(r3)<<4)|uint8(r2&0x0F)) 4396 } 4397 4398 func zRRE(op, r1, r2 uint32, asm *[]byte) { 4399 *asm = append(*asm, 4400 uint8(op>>8), 4401 uint8(op), 4402 0, 4403 (uint8(r1)<<4)|uint8(r2&0x0F)) 4404 } 4405 4406 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) { 4407 *asm = append(*asm, 4408 uint8(op>>8), 4409 uint8(op), 4410 (uint8(r3_m3)<<4)|uint8(m4&0x0F), 4411 (uint8(r1)<<4)|uint8(r2&0x0F)) 4412 } 4413 4414 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) { 4415 *asm = append(*asm, 4416 uint8(op>>8), 4417 (uint8(r1)<<4)|uint8(r2&0x0F), 4418 (uint8(b4)<<4)|uint8((d4>>8)&0x0F), 4419 uint8(d4), 4420 uint8(m3)<<4, 4421 uint8(op)) 4422 } 4423 4424 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4425 *asm = append(*asm, 4426 uint8(op>>8), 4427 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4428 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4429 uint8(d2)) 4430 } 4431 4432 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) { 4433 *asm = append(*asm, 4434 uint8(op>>8), 4435 (uint8(r1)<<4)|uint8(r3&0x0F), 4436 uint8(ri2>>8), 4437 uint8(ri2)) 4438 } 4439 4440 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) { 4441 *asm = append(*asm, 4442 uint8(op>>8), 4443 uint8(l1), 4444 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4445 uint8(d2), 4446 uint8(op)) 4447 } 4448 4449 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4450 dl2 := uint16(d2) & 0x0FFF 4451 *asm = append(*asm, 4452 uint8(op>>8), 4453 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4454 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4455 uint8(dl2), 4456 uint8(d2>>12), 4457 uint8(op)) 4458 } 4459 4460 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4461 *asm = append(*asm, 4462 uint8(op>>8), 4463 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4464 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4465 uint8(d2)) 4466 } 4467 4468 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) { 4469 *asm = append(*asm, 4470 uint8(op>>8), 4471 (uint8(r1)<<4)|uint8(x2&0x0F), 4472 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4473 uint8(d2), 4474 uint8(m3)<<4, 4475 uint8(op)) 4476 } 4477 4478 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) { 4479 *asm = append(*asm, 4480 uint8(op>>8), 4481 (uint8(r3)<<4)|uint8(x2&0x0F), 4482 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4483 uint8(d2), 4484 uint8(m1)<<4, 4485 uint8(op)) 4486 } 4487 4488 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4489 dl2 := uint16(d2) & 0x0FFF 4490 *asm = append(*asm, 4491 uint8(op>>8), 4492 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4493 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4494 uint8(dl2), 4495 uint8(d2>>12), 4496 uint8(op)) 4497 } 4498 4499 func zS(op, b2, d2 uint32, asm *[]byte) { 4500 *asm = append(*asm, 4501 uint8(op>>8), 4502 uint8(op), 4503 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4504 uint8(d2)) 4505 } 4506 4507 func zSI(op, i2, b1, d1 uint32, asm *[]byte) { 4508 *asm = append(*asm, 4509 uint8(op>>8), 4510 uint8(i2), 4511 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4512 uint8(d1)) 4513 } 4514 4515 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) { 4516 *asm = append(*asm, 4517 uint8(op>>8), 4518 uint8(op), 4519 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4520 uint8(d1), 4521 uint8(i2>>8), 4522 uint8(i2)) 4523 } 4524 4525 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) { 4526 dl1 := uint16(d1) & 0x0FFF 4527 *asm = append(*asm, 4528 uint8(op>>8), 4529 uint8(i2), 4530 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F), 4531 uint8(dl1), 4532 uint8(d1>>12), 4533 uint8(op)) 4534 } 4535 4536 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) { 4537 *asm = append(*asm, 4538 uint8(op>>8), 4539 uint8(m1)<<4, 4540 (uint8(b3)<<4)|uint8((d3>>8)&0x0F), 4541 uint8(d3), 4542 uint8(ri2>>8), 4543 uint8(ri2)) 4544 } 4545 4546 // Expected argument values for the instruction formats. 4547 // 4548 // Format a1 a2 a3 a4 a5 a6 4549 // ------------------------------- 4550 // a l1, 0, b1, d1, b2, d2 4551 // b l1, l2, b1, d1, b2, d2 4552 // c l1, i3, b1, d1, b2, d2 4553 // d r1, r3, b1, d1, b2, d2 4554 // e r1, r3, b2, d2, b4, d4 4555 // f 0, l2, b1, d1, b2, d2 4556 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) { 4557 *asm = append(*asm, uint8(op>>8)) 4558 4559 switch f { 4560 case _a: 4561 *asm = append(*asm, uint8(l1_r1)) 4562 case _b, _c, _d, _e: 4563 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F)) 4564 case _f: 4565 *asm = append(*asm, uint8(l2_i3_r3)) 4566 } 4567 4568 *asm = append(*asm, 4569 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F), 4570 uint8(d1_d2), 4571 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F), 4572 uint8(d2_d4)) 4573 } 4574 4575 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) { 4576 *asm = append(*asm, 4577 uint8(op>>8), 4578 uint8(op), 4579 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4580 uint8(d1), 4581 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4582 uint8(d2)) 4583 } 4584 4585 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) { 4586 *asm = append(*asm, 4587 uint8(op>>8), 4588 (uint8(r3)<<4)|(uint8(op)&0x0F), 4589 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4590 uint8(d1), 4591 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4592 uint8(d2)) 4593 } 4594 4595 func rxb(va, vb, vc, vd uint32) uint8 { 4596 mask := uint8(0) 4597 if va >= REG_V16 && va <= REG_V31 { 4598 mask |= 0x8 4599 } 4600 if vb >= REG_V16 && vb <= REG_V31 { 4601 mask |= 0x4 4602 } 4603 if vc >= REG_V16 && vc <= REG_V31 { 4604 mask |= 0x2 4605 } 4606 if vd >= REG_V16 && vd <= REG_V31 { 4607 mask |= 0x1 4608 } 4609 return mask 4610 } 4611 4612 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) { 4613 *asm = append(*asm, 4614 uint8(op>>8), 4615 (uint8(v1)<<4)|(uint8(x2)&0xf), 4616 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4617 uint8(d2), 4618 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4619 uint8(op)) 4620 } 4621 4622 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) { 4623 *asm = append(*asm, 4624 uint8(op>>8), 4625 (uint8(v1)<<4)|(uint8(v2)&0xf), 4626 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4627 uint8(d2), 4628 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4629 uint8(op)) 4630 } 4631 4632 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) { 4633 *asm = append(*asm, 4634 uint8(op>>8), 4635 (uint8(v1)<<4)|(uint8(v3_r3)&0xf), 4636 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4637 uint8(d2), 4638 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0), 4639 uint8(op)) 4640 } 4641 4642 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) { 4643 *asm = append(*asm, 4644 uint8(op>>8), 4645 (uint8(v1)<<4)|(uint8(v2)&0xf), 4646 0, 4647 (uint8(m5)<<4)|(uint8(m4)&0xf), 4648 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4649 uint8(op)) 4650 } 4651 4652 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) { 4653 *asm = append(*asm, 4654 uint8(op>>8), 4655 (uint8(v1)<<4)|(uint8(v2)&0xf), 4656 uint8(v3)<<4, 4657 uint8(m5)<<4, 4658 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4659 uint8(op)) 4660 } 4661 4662 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) { 4663 *asm = append(*asm, 4664 uint8(op>>8), 4665 (uint8(v1)<<4)|(uint8(v2)&0xf), 4666 uint8(v3)<<4, 4667 (uint8(m6)<<4)|(uint8(m5)&0xf), 4668 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4669 uint8(op)) 4670 } 4671 4672 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) { 4673 *asm = append(*asm, 4674 uint8(op>>8), 4675 (uint8(v1)<<4)|(uint8(v2)&0xf), 4676 (uint8(v3)<<4)|(uint8(m5)&0xf), 4677 uint8(m6)<<4, 4678 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4679 uint8(op)) 4680 } 4681 4682 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) { 4683 *asm = append(*asm, 4684 uint8(op>>8), 4685 (uint8(v1)<<4)|(uint8(v2)&0xf), 4686 (uint8(v3)<<4)|(uint8(m6)&0xf), 4687 uint8(m5), 4688 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4689 uint8(op)) 4690 } 4691 4692 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) { 4693 *asm = append(*asm, 4694 uint8(op>>8), 4695 (uint8(v1)<<4)|(uint8(r2)&0xf), 4696 uint8(r3)<<4, 4697 0, 4698 rxb(v1, 0, 0, 0), 4699 uint8(op)) 4700 } 4701 4702 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) { 4703 *asm = append(*asm, 4704 uint8(op>>8), 4705 uint8(v1)<<4, 4706 uint8(i2>>8), 4707 uint8(i2), 4708 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4709 uint8(op)) 4710 } 4711 4712 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) { 4713 *asm = append(*asm, 4714 uint8(op>>8), 4715 uint8(v1)<<4, 4716 uint8(i2), 4717 uint8(i3), 4718 (uint8(m4)<<4)|rxb(v1, 0, 0, 0), 4719 uint8(op)) 4720 } 4721 4722 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) { 4723 *asm = append(*asm, 4724 uint8(op>>8), 4725 (uint8(v1)<<4)|(uint8(v3)&0xf), 4726 uint8(i2>>8), 4727 uint8(i2), 4728 (uint8(m4)<<4)|rxb(v1, v3, 0, 0), 4729 uint8(op)) 4730 } 4731 4732 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) { 4733 *asm = append(*asm, 4734 uint8(op>>8), 4735 (uint8(v1)<<4)|(uint8(v2)&0xf), 4736 uint8(v3)<<4, 4737 uint8(i4), 4738 (uint8(m5)<<4)|rxb(v1, v2, v3, 0), 4739 uint8(op)) 4740 } 4741 4742 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) { 4743 *asm = append(*asm, 4744 uint8(op>>8), 4745 (uint8(v1)<<4)|(uint8(v2)&0xf), 4746 uint8(i3>>4), 4747 (uint8(i3)<<4)|(uint8(m5)&0xf), 4748 (uint8(m4)<<4)|rxb(v1, v2, 0, 0), 4749 uint8(op)) 4750 }