github.com/hikaru7719/go@v0.0.0-20181025140707-c8b2ac68906a/src/cmd/compile/internal/ssa/opGen.go (about) 1 // Code generated from gen/*Ops.go; DO NOT EDIT. 2 3 package ssa 4 5 import ( 6 "cmd/internal/obj" 7 "cmd/internal/obj/arm" 8 "cmd/internal/obj/arm64" 9 "cmd/internal/obj/mips" 10 "cmd/internal/obj/ppc64" 11 "cmd/internal/obj/s390x" 12 "cmd/internal/obj/wasm" 13 "cmd/internal/obj/x86" 14 ) 15 16 const ( 17 BlockInvalid BlockKind = iota 18 19 Block386EQ 20 Block386NE 21 Block386LT 22 Block386LE 23 Block386GT 24 Block386GE 25 Block386OS 26 Block386OC 27 Block386ULT 28 Block386ULE 29 Block386UGT 30 Block386UGE 31 Block386EQF 32 Block386NEF 33 Block386ORD 34 Block386NAN 35 36 BlockAMD64EQ 37 BlockAMD64NE 38 BlockAMD64LT 39 BlockAMD64LE 40 BlockAMD64GT 41 BlockAMD64GE 42 BlockAMD64OS 43 BlockAMD64OC 44 BlockAMD64ULT 45 BlockAMD64ULE 46 BlockAMD64UGT 47 BlockAMD64UGE 48 BlockAMD64EQF 49 BlockAMD64NEF 50 BlockAMD64ORD 51 BlockAMD64NAN 52 53 BlockARMEQ 54 BlockARMNE 55 BlockARMLT 56 BlockARMLE 57 BlockARMGT 58 BlockARMGE 59 BlockARMULT 60 BlockARMULE 61 BlockARMUGT 62 BlockARMUGE 63 64 BlockARM64EQ 65 BlockARM64NE 66 BlockARM64LT 67 BlockARM64LE 68 BlockARM64GT 69 BlockARM64GE 70 BlockARM64ULT 71 BlockARM64ULE 72 BlockARM64UGT 73 BlockARM64UGE 74 BlockARM64Z 75 BlockARM64NZ 76 BlockARM64ZW 77 BlockARM64NZW 78 BlockARM64TBZ 79 BlockARM64TBNZ 80 81 BlockMIPSEQ 82 BlockMIPSNE 83 BlockMIPSLTZ 84 BlockMIPSLEZ 85 BlockMIPSGTZ 86 BlockMIPSGEZ 87 BlockMIPSFPT 88 BlockMIPSFPF 89 90 BlockMIPS64EQ 91 BlockMIPS64NE 92 BlockMIPS64LTZ 93 BlockMIPS64LEZ 94 BlockMIPS64GTZ 95 BlockMIPS64GEZ 96 BlockMIPS64FPT 97 BlockMIPS64FPF 98 99 BlockPPC64EQ 100 BlockPPC64NE 101 BlockPPC64LT 102 BlockPPC64LE 103 BlockPPC64GT 104 BlockPPC64GE 105 BlockPPC64FLT 106 BlockPPC64FLE 107 BlockPPC64FGT 108 BlockPPC64FGE 109 110 BlockS390XEQ 111 BlockS390XNE 112 BlockS390XLT 113 BlockS390XLE 114 BlockS390XGT 115 BlockS390XGE 116 BlockS390XGTF 117 BlockS390XGEF 118 119 BlockPlain 120 BlockIf 121 BlockDefer 122 BlockRet 123 BlockRetJmp 124 BlockExit 125 BlockFirst 126 ) 127 128 var blockString = [...]string{ 129 BlockInvalid: "BlockInvalid", 130 131 Block386EQ: "EQ", 132 Block386NE: "NE", 133 Block386LT: "LT", 134 Block386LE: "LE", 135 Block386GT: "GT", 136 Block386GE: "GE", 137 Block386OS: "OS", 138 Block386OC: "OC", 139 Block386ULT: "ULT", 140 Block386ULE: "ULE", 141 Block386UGT: "UGT", 142 Block386UGE: "UGE", 143 Block386EQF: "EQF", 144 Block386NEF: "NEF", 145 Block386ORD: "ORD", 146 Block386NAN: "NAN", 147 148 BlockAMD64EQ: "EQ", 149 BlockAMD64NE: "NE", 150 BlockAMD64LT: "LT", 151 BlockAMD64LE: "LE", 152 BlockAMD64GT: "GT", 153 BlockAMD64GE: "GE", 154 BlockAMD64OS: "OS", 155 BlockAMD64OC: "OC", 156 BlockAMD64ULT: "ULT", 157 BlockAMD64ULE: "ULE", 158 BlockAMD64UGT: "UGT", 159 BlockAMD64UGE: "UGE", 160 BlockAMD64EQF: "EQF", 161 BlockAMD64NEF: "NEF", 162 BlockAMD64ORD: "ORD", 163 BlockAMD64NAN: "NAN", 164 165 BlockARMEQ: "EQ", 166 BlockARMNE: "NE", 167 BlockARMLT: "LT", 168 BlockARMLE: "LE", 169 BlockARMGT: "GT", 170 BlockARMGE: "GE", 171 BlockARMULT: "ULT", 172 BlockARMULE: "ULE", 173 BlockARMUGT: "UGT", 174 BlockARMUGE: "UGE", 175 176 BlockARM64EQ: "EQ", 177 BlockARM64NE: "NE", 178 BlockARM64LT: "LT", 179 BlockARM64LE: "LE", 180 BlockARM64GT: "GT", 181 BlockARM64GE: "GE", 182 BlockARM64ULT: "ULT", 183 BlockARM64ULE: "ULE", 184 BlockARM64UGT: "UGT", 185 BlockARM64UGE: "UGE", 186 BlockARM64Z: "Z", 187 BlockARM64NZ: "NZ", 188 BlockARM64ZW: "ZW", 189 BlockARM64NZW: "NZW", 190 BlockARM64TBZ: "TBZ", 191 BlockARM64TBNZ: "TBNZ", 192 193 BlockMIPSEQ: "EQ", 194 BlockMIPSNE: "NE", 195 BlockMIPSLTZ: "LTZ", 196 BlockMIPSLEZ: "LEZ", 197 BlockMIPSGTZ: "GTZ", 198 BlockMIPSGEZ: "GEZ", 199 BlockMIPSFPT: "FPT", 200 BlockMIPSFPF: "FPF", 201 202 BlockMIPS64EQ: "EQ", 203 BlockMIPS64NE: "NE", 204 BlockMIPS64LTZ: "LTZ", 205 BlockMIPS64LEZ: "LEZ", 206 BlockMIPS64GTZ: "GTZ", 207 BlockMIPS64GEZ: "GEZ", 208 BlockMIPS64FPT: "FPT", 209 BlockMIPS64FPF: "FPF", 210 211 BlockPPC64EQ: "EQ", 212 BlockPPC64NE: "NE", 213 BlockPPC64LT: "LT", 214 BlockPPC64LE: "LE", 215 BlockPPC64GT: "GT", 216 BlockPPC64GE: "GE", 217 BlockPPC64FLT: "FLT", 218 BlockPPC64FLE: "FLE", 219 BlockPPC64FGT: "FGT", 220 BlockPPC64FGE: "FGE", 221 222 BlockS390XEQ: "EQ", 223 BlockS390XNE: "NE", 224 BlockS390XLT: "LT", 225 BlockS390XLE: "LE", 226 BlockS390XGT: "GT", 227 BlockS390XGE: "GE", 228 BlockS390XGTF: "GTF", 229 BlockS390XGEF: "GEF", 230 231 BlockPlain: "Plain", 232 BlockIf: "If", 233 BlockDefer: "Defer", 234 BlockRet: "Ret", 235 BlockRetJmp: "RetJmp", 236 BlockExit: "Exit", 237 BlockFirst: "First", 238 } 239 240 func (k BlockKind) String() string { return blockString[k] } 241 242 const ( 243 OpInvalid Op = iota 244 245 Op386ADDSS 246 Op386ADDSD 247 Op386SUBSS 248 Op386SUBSD 249 Op386MULSS 250 Op386MULSD 251 Op386DIVSS 252 Op386DIVSD 253 Op386MOVSSload 254 Op386MOVSDload 255 Op386MOVSSconst 256 Op386MOVSDconst 257 Op386MOVSSloadidx1 258 Op386MOVSSloadidx4 259 Op386MOVSDloadidx1 260 Op386MOVSDloadidx8 261 Op386MOVSSstore 262 Op386MOVSDstore 263 Op386MOVSSstoreidx1 264 Op386MOVSSstoreidx4 265 Op386MOVSDstoreidx1 266 Op386MOVSDstoreidx8 267 Op386ADDSSload 268 Op386ADDSDload 269 Op386SUBSSload 270 Op386SUBSDload 271 Op386MULSSload 272 Op386MULSDload 273 Op386DIVSSload 274 Op386DIVSDload 275 Op386ADDL 276 Op386ADDLconst 277 Op386ADDLcarry 278 Op386ADDLconstcarry 279 Op386ADCL 280 Op386ADCLconst 281 Op386SUBL 282 Op386SUBLconst 283 Op386SUBLcarry 284 Op386SUBLconstcarry 285 Op386SBBL 286 Op386SBBLconst 287 Op386MULL 288 Op386MULLconst 289 Op386MULLU 290 Op386HMULL 291 Op386HMULLU 292 Op386MULLQU 293 Op386AVGLU 294 Op386DIVL 295 Op386DIVW 296 Op386DIVLU 297 Op386DIVWU 298 Op386MODL 299 Op386MODW 300 Op386MODLU 301 Op386MODWU 302 Op386ANDL 303 Op386ANDLconst 304 Op386ORL 305 Op386ORLconst 306 Op386XORL 307 Op386XORLconst 308 Op386CMPL 309 Op386CMPW 310 Op386CMPB 311 Op386CMPLconst 312 Op386CMPWconst 313 Op386CMPBconst 314 Op386CMPLload 315 Op386CMPWload 316 Op386CMPBload 317 Op386CMPLconstload 318 Op386CMPWconstload 319 Op386CMPBconstload 320 Op386UCOMISS 321 Op386UCOMISD 322 Op386TESTL 323 Op386TESTW 324 Op386TESTB 325 Op386TESTLconst 326 Op386TESTWconst 327 Op386TESTBconst 328 Op386SHLL 329 Op386SHLLconst 330 Op386SHRL 331 Op386SHRW 332 Op386SHRB 333 Op386SHRLconst 334 Op386SHRWconst 335 Op386SHRBconst 336 Op386SARL 337 Op386SARW 338 Op386SARB 339 Op386SARLconst 340 Op386SARWconst 341 Op386SARBconst 342 Op386ROLLconst 343 Op386ROLWconst 344 Op386ROLBconst 345 Op386ADDLload 346 Op386SUBLload 347 Op386MULLload 348 Op386ANDLload 349 Op386ORLload 350 Op386XORLload 351 Op386ADDLloadidx4 352 Op386SUBLloadidx4 353 Op386MULLloadidx4 354 Op386ANDLloadidx4 355 Op386ORLloadidx4 356 Op386XORLloadidx4 357 Op386NEGL 358 Op386NOTL 359 Op386BSFL 360 Op386BSFW 361 Op386BSRL 362 Op386BSRW 363 Op386BSWAPL 364 Op386SQRTSD 365 Op386SBBLcarrymask 366 Op386SETEQ 367 Op386SETNE 368 Op386SETL 369 Op386SETLE 370 Op386SETG 371 Op386SETGE 372 Op386SETB 373 Op386SETBE 374 Op386SETA 375 Op386SETAE 376 Op386SETO 377 Op386SETEQF 378 Op386SETNEF 379 Op386SETORD 380 Op386SETNAN 381 Op386SETGF 382 Op386SETGEF 383 Op386MOVBLSX 384 Op386MOVBLZX 385 Op386MOVWLSX 386 Op386MOVWLZX 387 Op386MOVLconst 388 Op386CVTTSD2SL 389 Op386CVTTSS2SL 390 Op386CVTSL2SS 391 Op386CVTSL2SD 392 Op386CVTSD2SS 393 Op386CVTSS2SD 394 Op386PXOR 395 Op386LEAL 396 Op386LEAL1 397 Op386LEAL2 398 Op386LEAL4 399 Op386LEAL8 400 Op386MOVBload 401 Op386MOVBLSXload 402 Op386MOVWload 403 Op386MOVWLSXload 404 Op386MOVLload 405 Op386MOVBstore 406 Op386MOVWstore 407 Op386MOVLstore 408 Op386ADDLmodify 409 Op386SUBLmodify 410 Op386ANDLmodify 411 Op386ORLmodify 412 Op386XORLmodify 413 Op386ADDLmodifyidx4 414 Op386SUBLmodifyidx4 415 Op386ANDLmodifyidx4 416 Op386ORLmodifyidx4 417 Op386XORLmodifyidx4 418 Op386ADDLconstmodify 419 Op386ANDLconstmodify 420 Op386ORLconstmodify 421 Op386XORLconstmodify 422 Op386ADDLconstmodifyidx4 423 Op386ANDLconstmodifyidx4 424 Op386ORLconstmodifyidx4 425 Op386XORLconstmodifyidx4 426 Op386MOVBloadidx1 427 Op386MOVWloadidx1 428 Op386MOVWloadidx2 429 Op386MOVLloadidx1 430 Op386MOVLloadidx4 431 Op386MOVBstoreidx1 432 Op386MOVWstoreidx1 433 Op386MOVWstoreidx2 434 Op386MOVLstoreidx1 435 Op386MOVLstoreidx4 436 Op386MOVBstoreconst 437 Op386MOVWstoreconst 438 Op386MOVLstoreconst 439 Op386MOVBstoreconstidx1 440 Op386MOVWstoreconstidx1 441 Op386MOVWstoreconstidx2 442 Op386MOVLstoreconstidx1 443 Op386MOVLstoreconstidx4 444 Op386DUFFZERO 445 Op386REPSTOSL 446 Op386CALLstatic 447 Op386CALLclosure 448 Op386CALLinter 449 Op386DUFFCOPY 450 Op386REPMOVSL 451 Op386InvertFlags 452 Op386LoweredGetG 453 Op386LoweredGetClosurePtr 454 Op386LoweredGetCallerPC 455 Op386LoweredGetCallerSP 456 Op386LoweredNilCheck 457 Op386LoweredWB 458 Op386FlagEQ 459 Op386FlagLT_ULT 460 Op386FlagLT_UGT 461 Op386FlagGT_UGT 462 Op386FlagGT_ULT 463 Op386FCHS 464 Op386MOVSSconst1 465 Op386MOVSDconst1 466 Op386MOVSSconst2 467 Op386MOVSDconst2 468 469 OpAMD64ADDSS 470 OpAMD64ADDSD 471 OpAMD64SUBSS 472 OpAMD64SUBSD 473 OpAMD64MULSS 474 OpAMD64MULSD 475 OpAMD64DIVSS 476 OpAMD64DIVSD 477 OpAMD64MOVSSload 478 OpAMD64MOVSDload 479 OpAMD64MOVSSconst 480 OpAMD64MOVSDconst 481 OpAMD64MOVSSloadidx1 482 OpAMD64MOVSSloadidx4 483 OpAMD64MOVSDloadidx1 484 OpAMD64MOVSDloadidx8 485 OpAMD64MOVSSstore 486 OpAMD64MOVSDstore 487 OpAMD64MOVSSstoreidx1 488 OpAMD64MOVSSstoreidx4 489 OpAMD64MOVSDstoreidx1 490 OpAMD64MOVSDstoreidx8 491 OpAMD64ADDSSload 492 OpAMD64ADDSDload 493 OpAMD64SUBSSload 494 OpAMD64SUBSDload 495 OpAMD64MULSSload 496 OpAMD64MULSDload 497 OpAMD64DIVSSload 498 OpAMD64DIVSDload 499 OpAMD64ADDQ 500 OpAMD64ADDL 501 OpAMD64ADDQconst 502 OpAMD64ADDLconst 503 OpAMD64ADDQconstmodify 504 OpAMD64ADDLconstmodify 505 OpAMD64SUBQ 506 OpAMD64SUBL 507 OpAMD64SUBQconst 508 OpAMD64SUBLconst 509 OpAMD64MULQ 510 OpAMD64MULL 511 OpAMD64MULQconst 512 OpAMD64MULLconst 513 OpAMD64MULLU 514 OpAMD64MULQU 515 OpAMD64HMULQ 516 OpAMD64HMULL 517 OpAMD64HMULQU 518 OpAMD64HMULLU 519 OpAMD64AVGQU 520 OpAMD64DIVQ 521 OpAMD64DIVL 522 OpAMD64DIVW 523 OpAMD64DIVQU 524 OpAMD64DIVLU 525 OpAMD64DIVWU 526 OpAMD64MULQU2 527 OpAMD64DIVQU2 528 OpAMD64ANDQ 529 OpAMD64ANDL 530 OpAMD64ANDQconst 531 OpAMD64ANDLconst 532 OpAMD64ANDQconstmodify 533 OpAMD64ANDLconstmodify 534 OpAMD64ORQ 535 OpAMD64ORL 536 OpAMD64ORQconst 537 OpAMD64ORLconst 538 OpAMD64ORQconstmodify 539 OpAMD64ORLconstmodify 540 OpAMD64XORQ 541 OpAMD64XORL 542 OpAMD64XORQconst 543 OpAMD64XORLconst 544 OpAMD64XORQconstmodify 545 OpAMD64XORLconstmodify 546 OpAMD64CMPQ 547 OpAMD64CMPL 548 OpAMD64CMPW 549 OpAMD64CMPB 550 OpAMD64CMPQconst 551 OpAMD64CMPLconst 552 OpAMD64CMPWconst 553 OpAMD64CMPBconst 554 OpAMD64CMPQload 555 OpAMD64CMPLload 556 OpAMD64CMPWload 557 OpAMD64CMPBload 558 OpAMD64CMPQconstload 559 OpAMD64CMPLconstload 560 OpAMD64CMPWconstload 561 OpAMD64CMPBconstload 562 OpAMD64UCOMISS 563 OpAMD64UCOMISD 564 OpAMD64BTL 565 OpAMD64BTQ 566 OpAMD64BTCL 567 OpAMD64BTCQ 568 OpAMD64BTRL 569 OpAMD64BTRQ 570 OpAMD64BTSL 571 OpAMD64BTSQ 572 OpAMD64BTLconst 573 OpAMD64BTQconst 574 OpAMD64BTCLconst 575 OpAMD64BTCQconst 576 OpAMD64BTRLconst 577 OpAMD64BTRQconst 578 OpAMD64BTSLconst 579 OpAMD64BTSQconst 580 OpAMD64BTCQmodify 581 OpAMD64BTCLmodify 582 OpAMD64BTSQmodify 583 OpAMD64BTSLmodify 584 OpAMD64BTRQmodify 585 OpAMD64BTRLmodify 586 OpAMD64BTCQconstmodify 587 OpAMD64BTCLconstmodify 588 OpAMD64BTSQconstmodify 589 OpAMD64BTSLconstmodify 590 OpAMD64BTRQconstmodify 591 OpAMD64BTRLconstmodify 592 OpAMD64TESTQ 593 OpAMD64TESTL 594 OpAMD64TESTW 595 OpAMD64TESTB 596 OpAMD64TESTQconst 597 OpAMD64TESTLconst 598 OpAMD64TESTWconst 599 OpAMD64TESTBconst 600 OpAMD64SHLQ 601 OpAMD64SHLL 602 OpAMD64SHLQconst 603 OpAMD64SHLLconst 604 OpAMD64SHRQ 605 OpAMD64SHRL 606 OpAMD64SHRW 607 OpAMD64SHRB 608 OpAMD64SHRQconst 609 OpAMD64SHRLconst 610 OpAMD64SHRWconst 611 OpAMD64SHRBconst 612 OpAMD64SARQ 613 OpAMD64SARL 614 OpAMD64SARW 615 OpAMD64SARB 616 OpAMD64SARQconst 617 OpAMD64SARLconst 618 OpAMD64SARWconst 619 OpAMD64SARBconst 620 OpAMD64ROLQ 621 OpAMD64ROLL 622 OpAMD64ROLW 623 OpAMD64ROLB 624 OpAMD64RORQ 625 OpAMD64RORL 626 OpAMD64RORW 627 OpAMD64RORB 628 OpAMD64ROLQconst 629 OpAMD64ROLLconst 630 OpAMD64ROLWconst 631 OpAMD64ROLBconst 632 OpAMD64ADDLload 633 OpAMD64ADDQload 634 OpAMD64SUBQload 635 OpAMD64SUBLload 636 OpAMD64ANDLload 637 OpAMD64ANDQload 638 OpAMD64ORQload 639 OpAMD64ORLload 640 OpAMD64XORQload 641 OpAMD64XORLload 642 OpAMD64ADDQmodify 643 OpAMD64SUBQmodify 644 OpAMD64ANDQmodify 645 OpAMD64ORQmodify 646 OpAMD64XORQmodify 647 OpAMD64ADDLmodify 648 OpAMD64SUBLmodify 649 OpAMD64ANDLmodify 650 OpAMD64ORLmodify 651 OpAMD64XORLmodify 652 OpAMD64NEGQ 653 OpAMD64NEGL 654 OpAMD64NOTQ 655 OpAMD64NOTL 656 OpAMD64BSFQ 657 OpAMD64BSFL 658 OpAMD64BSRQ 659 OpAMD64BSRL 660 OpAMD64CMOVQEQ 661 OpAMD64CMOVQNE 662 OpAMD64CMOVQLT 663 OpAMD64CMOVQGT 664 OpAMD64CMOVQLE 665 OpAMD64CMOVQGE 666 OpAMD64CMOVQLS 667 OpAMD64CMOVQHI 668 OpAMD64CMOVQCC 669 OpAMD64CMOVQCS 670 OpAMD64CMOVLEQ 671 OpAMD64CMOVLNE 672 OpAMD64CMOVLLT 673 OpAMD64CMOVLGT 674 OpAMD64CMOVLLE 675 OpAMD64CMOVLGE 676 OpAMD64CMOVLLS 677 OpAMD64CMOVLHI 678 OpAMD64CMOVLCC 679 OpAMD64CMOVLCS 680 OpAMD64CMOVWEQ 681 OpAMD64CMOVWNE 682 OpAMD64CMOVWLT 683 OpAMD64CMOVWGT 684 OpAMD64CMOVWLE 685 OpAMD64CMOVWGE 686 OpAMD64CMOVWLS 687 OpAMD64CMOVWHI 688 OpAMD64CMOVWCC 689 OpAMD64CMOVWCS 690 OpAMD64CMOVQEQF 691 OpAMD64CMOVQNEF 692 OpAMD64CMOVQGTF 693 OpAMD64CMOVQGEF 694 OpAMD64CMOVLEQF 695 OpAMD64CMOVLNEF 696 OpAMD64CMOVLGTF 697 OpAMD64CMOVLGEF 698 OpAMD64CMOVWEQF 699 OpAMD64CMOVWNEF 700 OpAMD64CMOVWGTF 701 OpAMD64CMOVWGEF 702 OpAMD64BSWAPQ 703 OpAMD64BSWAPL 704 OpAMD64POPCNTQ 705 OpAMD64POPCNTL 706 OpAMD64SQRTSD 707 OpAMD64ROUNDSD 708 OpAMD64SBBQcarrymask 709 OpAMD64SBBLcarrymask 710 OpAMD64SETEQ 711 OpAMD64SETNE 712 OpAMD64SETL 713 OpAMD64SETLE 714 OpAMD64SETG 715 OpAMD64SETGE 716 OpAMD64SETB 717 OpAMD64SETBE 718 OpAMD64SETA 719 OpAMD64SETAE 720 OpAMD64SETO 721 OpAMD64SETEQstore 722 OpAMD64SETNEstore 723 OpAMD64SETLstore 724 OpAMD64SETLEstore 725 OpAMD64SETGstore 726 OpAMD64SETGEstore 727 OpAMD64SETBstore 728 OpAMD64SETBEstore 729 OpAMD64SETAstore 730 OpAMD64SETAEstore 731 OpAMD64SETEQF 732 OpAMD64SETNEF 733 OpAMD64SETORD 734 OpAMD64SETNAN 735 OpAMD64SETGF 736 OpAMD64SETGEF 737 OpAMD64MOVBQSX 738 OpAMD64MOVBQZX 739 OpAMD64MOVWQSX 740 OpAMD64MOVWQZX 741 OpAMD64MOVLQSX 742 OpAMD64MOVLQZX 743 OpAMD64MOVLconst 744 OpAMD64MOVQconst 745 OpAMD64CVTTSD2SL 746 OpAMD64CVTTSD2SQ 747 OpAMD64CVTTSS2SL 748 OpAMD64CVTTSS2SQ 749 OpAMD64CVTSL2SS 750 OpAMD64CVTSL2SD 751 OpAMD64CVTSQ2SS 752 OpAMD64CVTSQ2SD 753 OpAMD64CVTSD2SS 754 OpAMD64CVTSS2SD 755 OpAMD64MOVQi2f 756 OpAMD64MOVQf2i 757 OpAMD64MOVLi2f 758 OpAMD64MOVLf2i 759 OpAMD64PXOR 760 OpAMD64LEAQ 761 OpAMD64LEAL 762 OpAMD64LEAW 763 OpAMD64LEAQ1 764 OpAMD64LEAL1 765 OpAMD64LEAW1 766 OpAMD64LEAQ2 767 OpAMD64LEAL2 768 OpAMD64LEAW2 769 OpAMD64LEAQ4 770 OpAMD64LEAL4 771 OpAMD64LEAW4 772 OpAMD64LEAQ8 773 OpAMD64LEAL8 774 OpAMD64LEAW8 775 OpAMD64MOVBload 776 OpAMD64MOVBQSXload 777 OpAMD64MOVWload 778 OpAMD64MOVWQSXload 779 OpAMD64MOVLload 780 OpAMD64MOVLQSXload 781 OpAMD64MOVQload 782 OpAMD64MOVBstore 783 OpAMD64MOVWstore 784 OpAMD64MOVLstore 785 OpAMD64MOVQstore 786 OpAMD64MOVOload 787 OpAMD64MOVOstore 788 OpAMD64MOVBloadidx1 789 OpAMD64MOVWloadidx1 790 OpAMD64MOVWloadidx2 791 OpAMD64MOVLloadidx1 792 OpAMD64MOVLloadidx4 793 OpAMD64MOVLloadidx8 794 OpAMD64MOVQloadidx1 795 OpAMD64MOVQloadidx8 796 OpAMD64MOVBstoreidx1 797 OpAMD64MOVWstoreidx1 798 OpAMD64MOVWstoreidx2 799 OpAMD64MOVLstoreidx1 800 OpAMD64MOVLstoreidx4 801 OpAMD64MOVLstoreidx8 802 OpAMD64MOVQstoreidx1 803 OpAMD64MOVQstoreidx8 804 OpAMD64MOVBstoreconst 805 OpAMD64MOVWstoreconst 806 OpAMD64MOVLstoreconst 807 OpAMD64MOVQstoreconst 808 OpAMD64MOVBstoreconstidx1 809 OpAMD64MOVWstoreconstidx1 810 OpAMD64MOVWstoreconstidx2 811 OpAMD64MOVLstoreconstidx1 812 OpAMD64MOVLstoreconstidx4 813 OpAMD64MOVQstoreconstidx1 814 OpAMD64MOVQstoreconstidx8 815 OpAMD64DUFFZERO 816 OpAMD64MOVOconst 817 OpAMD64REPSTOSQ 818 OpAMD64CALLstatic 819 OpAMD64CALLclosure 820 OpAMD64CALLinter 821 OpAMD64DUFFCOPY 822 OpAMD64REPMOVSQ 823 OpAMD64InvertFlags 824 OpAMD64LoweredGetG 825 OpAMD64LoweredGetClosurePtr 826 OpAMD64LoweredGetCallerPC 827 OpAMD64LoweredGetCallerSP 828 OpAMD64LoweredNilCheck 829 OpAMD64LoweredWB 830 OpAMD64FlagEQ 831 OpAMD64FlagLT_ULT 832 OpAMD64FlagLT_UGT 833 OpAMD64FlagGT_UGT 834 OpAMD64FlagGT_ULT 835 OpAMD64MOVLatomicload 836 OpAMD64MOVQatomicload 837 OpAMD64XCHGL 838 OpAMD64XCHGQ 839 OpAMD64XADDLlock 840 OpAMD64XADDQlock 841 OpAMD64AddTupleFirst32 842 OpAMD64AddTupleFirst64 843 OpAMD64CMPXCHGLlock 844 OpAMD64CMPXCHGQlock 845 OpAMD64ANDBlock 846 OpAMD64ORBlock 847 848 OpARMADD 849 OpARMADDconst 850 OpARMSUB 851 OpARMSUBconst 852 OpARMRSB 853 OpARMRSBconst 854 OpARMMUL 855 OpARMHMUL 856 OpARMHMULU 857 OpARMCALLudiv 858 OpARMADDS 859 OpARMADDSconst 860 OpARMADC 861 OpARMADCconst 862 OpARMSUBS 863 OpARMSUBSconst 864 OpARMRSBSconst 865 OpARMSBC 866 OpARMSBCconst 867 OpARMRSCconst 868 OpARMMULLU 869 OpARMMULA 870 OpARMMULS 871 OpARMADDF 872 OpARMADDD 873 OpARMSUBF 874 OpARMSUBD 875 OpARMMULF 876 OpARMMULD 877 OpARMNMULF 878 OpARMNMULD 879 OpARMDIVF 880 OpARMDIVD 881 OpARMMULAF 882 OpARMMULAD 883 OpARMMULSF 884 OpARMMULSD 885 OpARMAND 886 OpARMANDconst 887 OpARMOR 888 OpARMORconst 889 OpARMXOR 890 OpARMXORconst 891 OpARMBIC 892 OpARMBICconst 893 OpARMBFX 894 OpARMBFXU 895 OpARMMVN 896 OpARMNEGF 897 OpARMNEGD 898 OpARMSQRTD 899 OpARMCLZ 900 OpARMREV 901 OpARMRBIT 902 OpARMSLL 903 OpARMSLLconst 904 OpARMSRL 905 OpARMSRLconst 906 OpARMSRA 907 OpARMSRAconst 908 OpARMSRRconst 909 OpARMADDshiftLL 910 OpARMADDshiftRL 911 OpARMADDshiftRA 912 OpARMSUBshiftLL 913 OpARMSUBshiftRL 914 OpARMSUBshiftRA 915 OpARMRSBshiftLL 916 OpARMRSBshiftRL 917 OpARMRSBshiftRA 918 OpARMANDshiftLL 919 OpARMANDshiftRL 920 OpARMANDshiftRA 921 OpARMORshiftLL 922 OpARMORshiftRL 923 OpARMORshiftRA 924 OpARMXORshiftLL 925 OpARMXORshiftRL 926 OpARMXORshiftRA 927 OpARMXORshiftRR 928 OpARMBICshiftLL 929 OpARMBICshiftRL 930 OpARMBICshiftRA 931 OpARMMVNshiftLL 932 OpARMMVNshiftRL 933 OpARMMVNshiftRA 934 OpARMADCshiftLL 935 OpARMADCshiftRL 936 OpARMADCshiftRA 937 OpARMSBCshiftLL 938 OpARMSBCshiftRL 939 OpARMSBCshiftRA 940 OpARMRSCshiftLL 941 OpARMRSCshiftRL 942 OpARMRSCshiftRA 943 OpARMADDSshiftLL 944 OpARMADDSshiftRL 945 OpARMADDSshiftRA 946 OpARMSUBSshiftLL 947 OpARMSUBSshiftRL 948 OpARMSUBSshiftRA 949 OpARMRSBSshiftLL 950 OpARMRSBSshiftRL 951 OpARMRSBSshiftRA 952 OpARMADDshiftLLreg 953 OpARMADDshiftRLreg 954 OpARMADDshiftRAreg 955 OpARMSUBshiftLLreg 956 OpARMSUBshiftRLreg 957 OpARMSUBshiftRAreg 958 OpARMRSBshiftLLreg 959 OpARMRSBshiftRLreg 960 OpARMRSBshiftRAreg 961 OpARMANDshiftLLreg 962 OpARMANDshiftRLreg 963 OpARMANDshiftRAreg 964 OpARMORshiftLLreg 965 OpARMORshiftRLreg 966 OpARMORshiftRAreg 967 OpARMXORshiftLLreg 968 OpARMXORshiftRLreg 969 OpARMXORshiftRAreg 970 OpARMBICshiftLLreg 971 OpARMBICshiftRLreg 972 OpARMBICshiftRAreg 973 OpARMMVNshiftLLreg 974 OpARMMVNshiftRLreg 975 OpARMMVNshiftRAreg 976 OpARMADCshiftLLreg 977 OpARMADCshiftRLreg 978 OpARMADCshiftRAreg 979 OpARMSBCshiftLLreg 980 OpARMSBCshiftRLreg 981 OpARMSBCshiftRAreg 982 OpARMRSCshiftLLreg 983 OpARMRSCshiftRLreg 984 OpARMRSCshiftRAreg 985 OpARMADDSshiftLLreg 986 OpARMADDSshiftRLreg 987 OpARMADDSshiftRAreg 988 OpARMSUBSshiftLLreg 989 OpARMSUBSshiftRLreg 990 OpARMSUBSshiftRAreg 991 OpARMRSBSshiftLLreg 992 OpARMRSBSshiftRLreg 993 OpARMRSBSshiftRAreg 994 OpARMCMP 995 OpARMCMPconst 996 OpARMCMN 997 OpARMCMNconst 998 OpARMTST 999 OpARMTSTconst 1000 OpARMTEQ 1001 OpARMTEQconst 1002 OpARMCMPF 1003 OpARMCMPD 1004 OpARMCMPshiftLL 1005 OpARMCMPshiftRL 1006 OpARMCMPshiftRA 1007 OpARMCMNshiftLL 1008 OpARMCMNshiftRL 1009 OpARMCMNshiftRA 1010 OpARMTSTshiftLL 1011 OpARMTSTshiftRL 1012 OpARMTSTshiftRA 1013 OpARMTEQshiftLL 1014 OpARMTEQshiftRL 1015 OpARMTEQshiftRA 1016 OpARMCMPshiftLLreg 1017 OpARMCMPshiftRLreg 1018 OpARMCMPshiftRAreg 1019 OpARMCMNshiftLLreg 1020 OpARMCMNshiftRLreg 1021 OpARMCMNshiftRAreg 1022 OpARMTSTshiftLLreg 1023 OpARMTSTshiftRLreg 1024 OpARMTSTshiftRAreg 1025 OpARMTEQshiftLLreg 1026 OpARMTEQshiftRLreg 1027 OpARMTEQshiftRAreg 1028 OpARMCMPF0 1029 OpARMCMPD0 1030 OpARMMOVWconst 1031 OpARMMOVFconst 1032 OpARMMOVDconst 1033 OpARMMOVWaddr 1034 OpARMMOVBload 1035 OpARMMOVBUload 1036 OpARMMOVHload 1037 OpARMMOVHUload 1038 OpARMMOVWload 1039 OpARMMOVFload 1040 OpARMMOVDload 1041 OpARMMOVBstore 1042 OpARMMOVHstore 1043 OpARMMOVWstore 1044 OpARMMOVFstore 1045 OpARMMOVDstore 1046 OpARMMOVWloadidx 1047 OpARMMOVWloadshiftLL 1048 OpARMMOVWloadshiftRL 1049 OpARMMOVWloadshiftRA 1050 OpARMMOVBUloadidx 1051 OpARMMOVBloadidx 1052 OpARMMOVHUloadidx 1053 OpARMMOVHloadidx 1054 OpARMMOVWstoreidx 1055 OpARMMOVWstoreshiftLL 1056 OpARMMOVWstoreshiftRL 1057 OpARMMOVWstoreshiftRA 1058 OpARMMOVBstoreidx 1059 OpARMMOVHstoreidx 1060 OpARMMOVBreg 1061 OpARMMOVBUreg 1062 OpARMMOVHreg 1063 OpARMMOVHUreg 1064 OpARMMOVWreg 1065 OpARMMOVWnop 1066 OpARMMOVWF 1067 OpARMMOVWD 1068 OpARMMOVWUF 1069 OpARMMOVWUD 1070 OpARMMOVFW 1071 OpARMMOVDW 1072 OpARMMOVFWU 1073 OpARMMOVDWU 1074 OpARMMOVFD 1075 OpARMMOVDF 1076 OpARMCMOVWHSconst 1077 OpARMCMOVWLSconst 1078 OpARMSRAcond 1079 OpARMCALLstatic 1080 OpARMCALLclosure 1081 OpARMCALLinter 1082 OpARMLoweredNilCheck 1083 OpARMEqual 1084 OpARMNotEqual 1085 OpARMLessThan 1086 OpARMLessEqual 1087 OpARMGreaterThan 1088 OpARMGreaterEqual 1089 OpARMLessThanU 1090 OpARMLessEqualU 1091 OpARMGreaterThanU 1092 OpARMGreaterEqualU 1093 OpARMDUFFZERO 1094 OpARMDUFFCOPY 1095 OpARMLoweredZero 1096 OpARMLoweredMove 1097 OpARMLoweredGetClosurePtr 1098 OpARMLoweredGetCallerSP 1099 OpARMLoweredGetCallerPC 1100 OpARMFlagEQ 1101 OpARMFlagLT_ULT 1102 OpARMFlagLT_UGT 1103 OpARMFlagGT_UGT 1104 OpARMFlagGT_ULT 1105 OpARMInvertFlags 1106 OpARMLoweredWB 1107 1108 OpARM64ADD 1109 OpARM64ADDconst 1110 OpARM64SUB 1111 OpARM64SUBconst 1112 OpARM64MUL 1113 OpARM64MULW 1114 OpARM64MNEG 1115 OpARM64MNEGW 1116 OpARM64MULH 1117 OpARM64UMULH 1118 OpARM64MULL 1119 OpARM64UMULL 1120 OpARM64DIV 1121 OpARM64UDIV 1122 OpARM64DIVW 1123 OpARM64UDIVW 1124 OpARM64MOD 1125 OpARM64UMOD 1126 OpARM64MODW 1127 OpARM64UMODW 1128 OpARM64FADDS 1129 OpARM64FADDD 1130 OpARM64FSUBS 1131 OpARM64FSUBD 1132 OpARM64FMULS 1133 OpARM64FMULD 1134 OpARM64FNMULS 1135 OpARM64FNMULD 1136 OpARM64FDIVS 1137 OpARM64FDIVD 1138 OpARM64AND 1139 OpARM64ANDconst 1140 OpARM64OR 1141 OpARM64ORconst 1142 OpARM64XOR 1143 OpARM64XORconst 1144 OpARM64BIC 1145 OpARM64EON 1146 OpARM64ORN 1147 OpARM64LoweredMuluhilo 1148 OpARM64MVN 1149 OpARM64NEG 1150 OpARM64FABSD 1151 OpARM64FNEGS 1152 OpARM64FNEGD 1153 OpARM64FSQRTD 1154 OpARM64REV 1155 OpARM64REVW 1156 OpARM64REV16W 1157 OpARM64RBIT 1158 OpARM64RBITW 1159 OpARM64CLZ 1160 OpARM64CLZW 1161 OpARM64VCNT 1162 OpARM64VUADDLV 1163 OpARM64LoweredRound32F 1164 OpARM64LoweredRound64F 1165 OpARM64FMADDS 1166 OpARM64FMADDD 1167 OpARM64FNMADDS 1168 OpARM64FNMADDD 1169 OpARM64FMSUBS 1170 OpARM64FMSUBD 1171 OpARM64FNMSUBS 1172 OpARM64FNMSUBD 1173 OpARM64MADD 1174 OpARM64MADDW 1175 OpARM64MSUB 1176 OpARM64MSUBW 1177 OpARM64SLL 1178 OpARM64SLLconst 1179 OpARM64SRL 1180 OpARM64SRLconst 1181 OpARM64SRA 1182 OpARM64SRAconst 1183 OpARM64ROR 1184 OpARM64RORW 1185 OpARM64RORconst 1186 OpARM64RORWconst 1187 OpARM64EXTRconst 1188 OpARM64EXTRWconst 1189 OpARM64CMP 1190 OpARM64CMPconst 1191 OpARM64CMPW 1192 OpARM64CMPWconst 1193 OpARM64CMN 1194 OpARM64CMNconst 1195 OpARM64CMNW 1196 OpARM64CMNWconst 1197 OpARM64TST 1198 OpARM64TSTconst 1199 OpARM64TSTW 1200 OpARM64TSTWconst 1201 OpARM64FCMPS 1202 OpARM64FCMPD 1203 OpARM64MVNshiftLL 1204 OpARM64MVNshiftRL 1205 OpARM64MVNshiftRA 1206 OpARM64NEGshiftLL 1207 OpARM64NEGshiftRL 1208 OpARM64NEGshiftRA 1209 OpARM64ADDshiftLL 1210 OpARM64ADDshiftRL 1211 OpARM64ADDshiftRA 1212 OpARM64SUBshiftLL 1213 OpARM64SUBshiftRL 1214 OpARM64SUBshiftRA 1215 OpARM64ANDshiftLL 1216 OpARM64ANDshiftRL 1217 OpARM64ANDshiftRA 1218 OpARM64ORshiftLL 1219 OpARM64ORshiftRL 1220 OpARM64ORshiftRA 1221 OpARM64XORshiftLL 1222 OpARM64XORshiftRL 1223 OpARM64XORshiftRA 1224 OpARM64BICshiftLL 1225 OpARM64BICshiftRL 1226 OpARM64BICshiftRA 1227 OpARM64EONshiftLL 1228 OpARM64EONshiftRL 1229 OpARM64EONshiftRA 1230 OpARM64ORNshiftLL 1231 OpARM64ORNshiftRL 1232 OpARM64ORNshiftRA 1233 OpARM64CMPshiftLL 1234 OpARM64CMPshiftRL 1235 OpARM64CMPshiftRA 1236 OpARM64CMNshiftLL 1237 OpARM64CMNshiftRL 1238 OpARM64CMNshiftRA 1239 OpARM64TSTshiftLL 1240 OpARM64TSTshiftRL 1241 OpARM64TSTshiftRA 1242 OpARM64BFI 1243 OpARM64BFXIL 1244 OpARM64SBFIZ 1245 OpARM64SBFX 1246 OpARM64UBFIZ 1247 OpARM64UBFX 1248 OpARM64MOVDconst 1249 OpARM64FMOVSconst 1250 OpARM64FMOVDconst 1251 OpARM64MOVDaddr 1252 OpARM64MOVBload 1253 OpARM64MOVBUload 1254 OpARM64MOVHload 1255 OpARM64MOVHUload 1256 OpARM64MOVWload 1257 OpARM64MOVWUload 1258 OpARM64MOVDload 1259 OpARM64FMOVSload 1260 OpARM64FMOVDload 1261 OpARM64MOVDloadidx 1262 OpARM64MOVWloadidx 1263 OpARM64MOVWUloadidx 1264 OpARM64MOVHloadidx 1265 OpARM64MOVHUloadidx 1266 OpARM64MOVBloadidx 1267 OpARM64MOVBUloadidx 1268 OpARM64FMOVSloadidx 1269 OpARM64FMOVDloadidx 1270 OpARM64MOVHloadidx2 1271 OpARM64MOVHUloadidx2 1272 OpARM64MOVWloadidx4 1273 OpARM64MOVWUloadidx4 1274 OpARM64MOVDloadidx8 1275 OpARM64MOVBstore 1276 OpARM64MOVHstore 1277 OpARM64MOVWstore 1278 OpARM64MOVDstore 1279 OpARM64STP 1280 OpARM64FMOVSstore 1281 OpARM64FMOVDstore 1282 OpARM64MOVBstoreidx 1283 OpARM64MOVHstoreidx 1284 OpARM64MOVWstoreidx 1285 OpARM64MOVDstoreidx 1286 OpARM64FMOVSstoreidx 1287 OpARM64FMOVDstoreidx 1288 OpARM64MOVHstoreidx2 1289 OpARM64MOVWstoreidx4 1290 OpARM64MOVDstoreidx8 1291 OpARM64MOVBstorezero 1292 OpARM64MOVHstorezero 1293 OpARM64MOVWstorezero 1294 OpARM64MOVDstorezero 1295 OpARM64MOVQstorezero 1296 OpARM64MOVBstorezeroidx 1297 OpARM64MOVHstorezeroidx 1298 OpARM64MOVWstorezeroidx 1299 OpARM64MOVDstorezeroidx 1300 OpARM64MOVHstorezeroidx2 1301 OpARM64MOVWstorezeroidx4 1302 OpARM64MOVDstorezeroidx8 1303 OpARM64FMOVDgpfp 1304 OpARM64FMOVDfpgp 1305 OpARM64FMOVSgpfp 1306 OpARM64FMOVSfpgp 1307 OpARM64MOVBreg 1308 OpARM64MOVBUreg 1309 OpARM64MOVHreg 1310 OpARM64MOVHUreg 1311 OpARM64MOVWreg 1312 OpARM64MOVWUreg 1313 OpARM64MOVDreg 1314 OpARM64MOVDnop 1315 OpARM64SCVTFWS 1316 OpARM64SCVTFWD 1317 OpARM64UCVTFWS 1318 OpARM64UCVTFWD 1319 OpARM64SCVTFS 1320 OpARM64SCVTFD 1321 OpARM64UCVTFS 1322 OpARM64UCVTFD 1323 OpARM64FCVTZSSW 1324 OpARM64FCVTZSDW 1325 OpARM64FCVTZUSW 1326 OpARM64FCVTZUDW 1327 OpARM64FCVTZSS 1328 OpARM64FCVTZSD 1329 OpARM64FCVTZUS 1330 OpARM64FCVTZUD 1331 OpARM64FCVTSD 1332 OpARM64FCVTDS 1333 OpARM64FRINTAD 1334 OpARM64FRINTMD 1335 OpARM64FRINTND 1336 OpARM64FRINTPD 1337 OpARM64FRINTZD 1338 OpARM64CSEL 1339 OpARM64CSEL0 1340 OpARM64CALLstatic 1341 OpARM64CALLclosure 1342 OpARM64CALLinter 1343 OpARM64LoweredNilCheck 1344 OpARM64Equal 1345 OpARM64NotEqual 1346 OpARM64LessThan 1347 OpARM64LessEqual 1348 OpARM64GreaterThan 1349 OpARM64GreaterEqual 1350 OpARM64LessThanU 1351 OpARM64LessEqualU 1352 OpARM64GreaterThanU 1353 OpARM64GreaterEqualU 1354 OpARM64DUFFZERO 1355 OpARM64LoweredZero 1356 OpARM64DUFFCOPY 1357 OpARM64LoweredMove 1358 OpARM64LoweredGetClosurePtr 1359 OpARM64LoweredGetCallerSP 1360 OpARM64LoweredGetCallerPC 1361 OpARM64FlagEQ 1362 OpARM64FlagLT_ULT 1363 OpARM64FlagLT_UGT 1364 OpARM64FlagGT_UGT 1365 OpARM64FlagGT_ULT 1366 OpARM64InvertFlags 1367 OpARM64LDAR 1368 OpARM64LDARW 1369 OpARM64STLR 1370 OpARM64STLRW 1371 OpARM64LoweredAtomicExchange64 1372 OpARM64LoweredAtomicExchange32 1373 OpARM64LoweredAtomicAdd64 1374 OpARM64LoweredAtomicAdd32 1375 OpARM64LoweredAtomicAdd64Variant 1376 OpARM64LoweredAtomicAdd32Variant 1377 OpARM64LoweredAtomicCas64 1378 OpARM64LoweredAtomicCas32 1379 OpARM64LoweredAtomicAnd8 1380 OpARM64LoweredAtomicOr8 1381 OpARM64LoweredWB 1382 1383 OpMIPSADD 1384 OpMIPSADDconst 1385 OpMIPSSUB 1386 OpMIPSSUBconst 1387 OpMIPSMUL 1388 OpMIPSMULT 1389 OpMIPSMULTU 1390 OpMIPSDIV 1391 OpMIPSDIVU 1392 OpMIPSADDF 1393 OpMIPSADDD 1394 OpMIPSSUBF 1395 OpMIPSSUBD 1396 OpMIPSMULF 1397 OpMIPSMULD 1398 OpMIPSDIVF 1399 OpMIPSDIVD 1400 OpMIPSAND 1401 OpMIPSANDconst 1402 OpMIPSOR 1403 OpMIPSORconst 1404 OpMIPSXOR 1405 OpMIPSXORconst 1406 OpMIPSNOR 1407 OpMIPSNORconst 1408 OpMIPSNEG 1409 OpMIPSNEGF 1410 OpMIPSNEGD 1411 OpMIPSSQRTD 1412 OpMIPSSLL 1413 OpMIPSSLLconst 1414 OpMIPSSRL 1415 OpMIPSSRLconst 1416 OpMIPSSRA 1417 OpMIPSSRAconst 1418 OpMIPSCLZ 1419 OpMIPSSGT 1420 OpMIPSSGTconst 1421 OpMIPSSGTzero 1422 OpMIPSSGTU 1423 OpMIPSSGTUconst 1424 OpMIPSSGTUzero 1425 OpMIPSCMPEQF 1426 OpMIPSCMPEQD 1427 OpMIPSCMPGEF 1428 OpMIPSCMPGED 1429 OpMIPSCMPGTF 1430 OpMIPSCMPGTD 1431 OpMIPSMOVWconst 1432 OpMIPSMOVFconst 1433 OpMIPSMOVDconst 1434 OpMIPSMOVWaddr 1435 OpMIPSMOVBload 1436 OpMIPSMOVBUload 1437 OpMIPSMOVHload 1438 OpMIPSMOVHUload 1439 OpMIPSMOVWload 1440 OpMIPSMOVFload 1441 OpMIPSMOVDload 1442 OpMIPSMOVBstore 1443 OpMIPSMOVHstore 1444 OpMIPSMOVWstore 1445 OpMIPSMOVFstore 1446 OpMIPSMOVDstore 1447 OpMIPSMOVBstorezero 1448 OpMIPSMOVHstorezero 1449 OpMIPSMOVWstorezero 1450 OpMIPSMOVBreg 1451 OpMIPSMOVBUreg 1452 OpMIPSMOVHreg 1453 OpMIPSMOVHUreg 1454 OpMIPSMOVWreg 1455 OpMIPSMOVWnop 1456 OpMIPSCMOVZ 1457 OpMIPSCMOVZzero 1458 OpMIPSMOVWF 1459 OpMIPSMOVWD 1460 OpMIPSTRUNCFW 1461 OpMIPSTRUNCDW 1462 OpMIPSMOVFD 1463 OpMIPSMOVDF 1464 OpMIPSCALLstatic 1465 OpMIPSCALLclosure 1466 OpMIPSCALLinter 1467 OpMIPSLoweredAtomicLoad 1468 OpMIPSLoweredAtomicStore 1469 OpMIPSLoweredAtomicStorezero 1470 OpMIPSLoweredAtomicExchange 1471 OpMIPSLoweredAtomicAdd 1472 OpMIPSLoweredAtomicAddconst 1473 OpMIPSLoweredAtomicCas 1474 OpMIPSLoweredAtomicAnd 1475 OpMIPSLoweredAtomicOr 1476 OpMIPSLoweredZero 1477 OpMIPSLoweredMove 1478 OpMIPSLoweredNilCheck 1479 OpMIPSFPFlagTrue 1480 OpMIPSFPFlagFalse 1481 OpMIPSLoweredGetClosurePtr 1482 OpMIPSLoweredGetCallerSP 1483 OpMIPSLoweredGetCallerPC 1484 OpMIPSLoweredWB 1485 1486 OpMIPS64ADDV 1487 OpMIPS64ADDVconst 1488 OpMIPS64SUBV 1489 OpMIPS64SUBVconst 1490 OpMIPS64MULV 1491 OpMIPS64MULVU 1492 OpMIPS64DIVV 1493 OpMIPS64DIVVU 1494 OpMIPS64ADDF 1495 OpMIPS64ADDD 1496 OpMIPS64SUBF 1497 OpMIPS64SUBD 1498 OpMIPS64MULF 1499 OpMIPS64MULD 1500 OpMIPS64DIVF 1501 OpMIPS64DIVD 1502 OpMIPS64AND 1503 OpMIPS64ANDconst 1504 OpMIPS64OR 1505 OpMIPS64ORconst 1506 OpMIPS64XOR 1507 OpMIPS64XORconst 1508 OpMIPS64NOR 1509 OpMIPS64NORconst 1510 OpMIPS64NEGV 1511 OpMIPS64NEGF 1512 OpMIPS64NEGD 1513 OpMIPS64SQRTD 1514 OpMIPS64SLLV 1515 OpMIPS64SLLVconst 1516 OpMIPS64SRLV 1517 OpMIPS64SRLVconst 1518 OpMIPS64SRAV 1519 OpMIPS64SRAVconst 1520 OpMIPS64SGT 1521 OpMIPS64SGTconst 1522 OpMIPS64SGTU 1523 OpMIPS64SGTUconst 1524 OpMIPS64CMPEQF 1525 OpMIPS64CMPEQD 1526 OpMIPS64CMPGEF 1527 OpMIPS64CMPGED 1528 OpMIPS64CMPGTF 1529 OpMIPS64CMPGTD 1530 OpMIPS64MOVVconst 1531 OpMIPS64MOVFconst 1532 OpMIPS64MOVDconst 1533 OpMIPS64MOVVaddr 1534 OpMIPS64MOVBload 1535 OpMIPS64MOVBUload 1536 OpMIPS64MOVHload 1537 OpMIPS64MOVHUload 1538 OpMIPS64MOVWload 1539 OpMIPS64MOVWUload 1540 OpMIPS64MOVVload 1541 OpMIPS64MOVFload 1542 OpMIPS64MOVDload 1543 OpMIPS64MOVBstore 1544 OpMIPS64MOVHstore 1545 OpMIPS64MOVWstore 1546 OpMIPS64MOVVstore 1547 OpMIPS64MOVFstore 1548 OpMIPS64MOVDstore 1549 OpMIPS64MOVBstorezero 1550 OpMIPS64MOVHstorezero 1551 OpMIPS64MOVWstorezero 1552 OpMIPS64MOVVstorezero 1553 OpMIPS64MOVBreg 1554 OpMIPS64MOVBUreg 1555 OpMIPS64MOVHreg 1556 OpMIPS64MOVHUreg 1557 OpMIPS64MOVWreg 1558 OpMIPS64MOVWUreg 1559 OpMIPS64MOVVreg 1560 OpMIPS64MOVVnop 1561 OpMIPS64MOVWF 1562 OpMIPS64MOVWD 1563 OpMIPS64MOVVF 1564 OpMIPS64MOVVD 1565 OpMIPS64TRUNCFW 1566 OpMIPS64TRUNCDW 1567 OpMIPS64TRUNCFV 1568 OpMIPS64TRUNCDV 1569 OpMIPS64MOVFD 1570 OpMIPS64MOVDF 1571 OpMIPS64CALLstatic 1572 OpMIPS64CALLclosure 1573 OpMIPS64CALLinter 1574 OpMIPS64DUFFZERO 1575 OpMIPS64LoweredZero 1576 OpMIPS64LoweredMove 1577 OpMIPS64LoweredAtomicLoad32 1578 OpMIPS64LoweredAtomicLoad64 1579 OpMIPS64LoweredAtomicStore32 1580 OpMIPS64LoweredAtomicStore64 1581 OpMIPS64LoweredAtomicStorezero32 1582 OpMIPS64LoweredAtomicStorezero64 1583 OpMIPS64LoweredAtomicExchange32 1584 OpMIPS64LoweredAtomicExchange64 1585 OpMIPS64LoweredAtomicAdd32 1586 OpMIPS64LoweredAtomicAdd64 1587 OpMIPS64LoweredAtomicAddconst32 1588 OpMIPS64LoweredAtomicAddconst64 1589 OpMIPS64LoweredAtomicCas32 1590 OpMIPS64LoweredAtomicCas64 1591 OpMIPS64LoweredNilCheck 1592 OpMIPS64FPFlagTrue 1593 OpMIPS64FPFlagFalse 1594 OpMIPS64LoweredGetClosurePtr 1595 OpMIPS64LoweredGetCallerSP 1596 OpMIPS64LoweredGetCallerPC 1597 OpMIPS64LoweredWB 1598 1599 OpPPC64ADD 1600 OpPPC64ADDconst 1601 OpPPC64FADD 1602 OpPPC64FADDS 1603 OpPPC64SUB 1604 OpPPC64FSUB 1605 OpPPC64FSUBS 1606 OpPPC64MULLD 1607 OpPPC64MULLW 1608 OpPPC64MULHD 1609 OpPPC64MULHW 1610 OpPPC64MULHDU 1611 OpPPC64MULHWU 1612 OpPPC64LoweredMuluhilo 1613 OpPPC64FMUL 1614 OpPPC64FMULS 1615 OpPPC64FMADD 1616 OpPPC64FMADDS 1617 OpPPC64FMSUB 1618 OpPPC64FMSUBS 1619 OpPPC64SRAD 1620 OpPPC64SRAW 1621 OpPPC64SRD 1622 OpPPC64SRW 1623 OpPPC64SLD 1624 OpPPC64SLW 1625 OpPPC64ROTL 1626 OpPPC64ROTLW 1627 OpPPC64ADDconstForCarry 1628 OpPPC64MaskIfNotCarry 1629 OpPPC64SRADconst 1630 OpPPC64SRAWconst 1631 OpPPC64SRDconst 1632 OpPPC64SRWconst 1633 OpPPC64SLDconst 1634 OpPPC64SLWconst 1635 OpPPC64ROTLconst 1636 OpPPC64ROTLWconst 1637 OpPPC64CNTLZD 1638 OpPPC64CNTLZW 1639 OpPPC64POPCNTD 1640 OpPPC64POPCNTW 1641 OpPPC64POPCNTB 1642 OpPPC64FDIV 1643 OpPPC64FDIVS 1644 OpPPC64DIVD 1645 OpPPC64DIVW 1646 OpPPC64DIVDU 1647 OpPPC64DIVWU 1648 OpPPC64FCTIDZ 1649 OpPPC64FCTIWZ 1650 OpPPC64FCFID 1651 OpPPC64FCFIDS 1652 OpPPC64FRSP 1653 OpPPC64MFVSRD 1654 OpPPC64MTVSRD 1655 OpPPC64AND 1656 OpPPC64ANDN 1657 OpPPC64OR 1658 OpPPC64ORN 1659 OpPPC64NOR 1660 OpPPC64XOR 1661 OpPPC64EQV 1662 OpPPC64NEG 1663 OpPPC64FNEG 1664 OpPPC64FSQRT 1665 OpPPC64FSQRTS 1666 OpPPC64FFLOOR 1667 OpPPC64FCEIL 1668 OpPPC64FTRUNC 1669 OpPPC64FROUND 1670 OpPPC64FABS 1671 OpPPC64FNABS 1672 OpPPC64FCPSGN 1673 OpPPC64ORconst 1674 OpPPC64XORconst 1675 OpPPC64ANDconst 1676 OpPPC64ANDCCconst 1677 OpPPC64MOVBreg 1678 OpPPC64MOVBZreg 1679 OpPPC64MOVHreg 1680 OpPPC64MOVHZreg 1681 OpPPC64MOVWreg 1682 OpPPC64MOVWZreg 1683 OpPPC64MOVBZload 1684 OpPPC64MOVHload 1685 OpPPC64MOVHZload 1686 OpPPC64MOVWload 1687 OpPPC64MOVWZload 1688 OpPPC64MOVDload 1689 OpPPC64MOVDBRload 1690 OpPPC64MOVWBRload 1691 OpPPC64MOVHBRload 1692 OpPPC64MOVBZloadidx 1693 OpPPC64MOVHloadidx 1694 OpPPC64MOVHZloadidx 1695 OpPPC64MOVWloadidx 1696 OpPPC64MOVWZloadidx 1697 OpPPC64MOVDloadidx 1698 OpPPC64MOVHBRloadidx 1699 OpPPC64MOVWBRloadidx 1700 OpPPC64MOVDBRloadidx 1701 OpPPC64FMOVDloadidx 1702 OpPPC64FMOVSloadidx 1703 OpPPC64MOVDBRstore 1704 OpPPC64MOVWBRstore 1705 OpPPC64MOVHBRstore 1706 OpPPC64FMOVDload 1707 OpPPC64FMOVSload 1708 OpPPC64MOVBstore 1709 OpPPC64MOVHstore 1710 OpPPC64MOVWstore 1711 OpPPC64MOVDstore 1712 OpPPC64FMOVDstore 1713 OpPPC64FMOVSstore 1714 OpPPC64MOVBstoreidx 1715 OpPPC64MOVHstoreidx 1716 OpPPC64MOVWstoreidx 1717 OpPPC64MOVDstoreidx 1718 OpPPC64FMOVDstoreidx 1719 OpPPC64FMOVSstoreidx 1720 OpPPC64MOVHBRstoreidx 1721 OpPPC64MOVWBRstoreidx 1722 OpPPC64MOVDBRstoreidx 1723 OpPPC64MOVBstorezero 1724 OpPPC64MOVHstorezero 1725 OpPPC64MOVWstorezero 1726 OpPPC64MOVDstorezero 1727 OpPPC64MOVDaddr 1728 OpPPC64MOVDconst 1729 OpPPC64FMOVDconst 1730 OpPPC64FMOVSconst 1731 OpPPC64FCMPU 1732 OpPPC64CMP 1733 OpPPC64CMPU 1734 OpPPC64CMPW 1735 OpPPC64CMPWU 1736 OpPPC64CMPconst 1737 OpPPC64CMPUconst 1738 OpPPC64CMPWconst 1739 OpPPC64CMPWUconst 1740 OpPPC64Equal 1741 OpPPC64NotEqual 1742 OpPPC64LessThan 1743 OpPPC64FLessThan 1744 OpPPC64LessEqual 1745 OpPPC64FLessEqual 1746 OpPPC64GreaterThan 1747 OpPPC64FGreaterThan 1748 OpPPC64GreaterEqual 1749 OpPPC64FGreaterEqual 1750 OpPPC64LoweredGetClosurePtr 1751 OpPPC64LoweredGetCallerSP 1752 OpPPC64LoweredGetCallerPC 1753 OpPPC64LoweredNilCheck 1754 OpPPC64LoweredRound32F 1755 OpPPC64LoweredRound64F 1756 OpPPC64CALLstatic 1757 OpPPC64CALLclosure 1758 OpPPC64CALLinter 1759 OpPPC64LoweredZero 1760 OpPPC64LoweredMove 1761 OpPPC64LoweredAtomicStore32 1762 OpPPC64LoweredAtomicStore64 1763 OpPPC64LoweredAtomicLoad32 1764 OpPPC64LoweredAtomicLoad64 1765 OpPPC64LoweredAtomicLoadPtr 1766 OpPPC64LoweredAtomicAdd32 1767 OpPPC64LoweredAtomicAdd64 1768 OpPPC64LoweredAtomicExchange32 1769 OpPPC64LoweredAtomicExchange64 1770 OpPPC64LoweredAtomicCas64 1771 OpPPC64LoweredAtomicCas32 1772 OpPPC64LoweredAtomicAnd8 1773 OpPPC64LoweredAtomicOr8 1774 OpPPC64LoweredWB 1775 OpPPC64InvertFlags 1776 OpPPC64FlagEQ 1777 OpPPC64FlagLT 1778 OpPPC64FlagGT 1779 1780 OpS390XFADDS 1781 OpS390XFADD 1782 OpS390XFSUBS 1783 OpS390XFSUB 1784 OpS390XFMULS 1785 OpS390XFMUL 1786 OpS390XFDIVS 1787 OpS390XFDIV 1788 OpS390XFNEGS 1789 OpS390XFNEG 1790 OpS390XFMADDS 1791 OpS390XFMADD 1792 OpS390XFMSUBS 1793 OpS390XFMSUB 1794 OpS390XLPDFR 1795 OpS390XLNDFR 1796 OpS390XCPSDR 1797 OpS390XFIDBR 1798 OpS390XFMOVSload 1799 OpS390XFMOVDload 1800 OpS390XFMOVSconst 1801 OpS390XFMOVDconst 1802 OpS390XFMOVSloadidx 1803 OpS390XFMOVDloadidx 1804 OpS390XFMOVSstore 1805 OpS390XFMOVDstore 1806 OpS390XFMOVSstoreidx 1807 OpS390XFMOVDstoreidx 1808 OpS390XADD 1809 OpS390XADDW 1810 OpS390XADDconst 1811 OpS390XADDWconst 1812 OpS390XADDload 1813 OpS390XADDWload 1814 OpS390XSUB 1815 OpS390XSUBW 1816 OpS390XSUBconst 1817 OpS390XSUBWconst 1818 OpS390XSUBload 1819 OpS390XSUBWload 1820 OpS390XMULLD 1821 OpS390XMULLW 1822 OpS390XMULLDconst 1823 OpS390XMULLWconst 1824 OpS390XMULLDload 1825 OpS390XMULLWload 1826 OpS390XMULHD 1827 OpS390XMULHDU 1828 OpS390XDIVD 1829 OpS390XDIVW 1830 OpS390XDIVDU 1831 OpS390XDIVWU 1832 OpS390XMODD 1833 OpS390XMODW 1834 OpS390XMODDU 1835 OpS390XMODWU 1836 OpS390XAND 1837 OpS390XANDW 1838 OpS390XANDconst 1839 OpS390XANDWconst 1840 OpS390XANDload 1841 OpS390XANDWload 1842 OpS390XOR 1843 OpS390XORW 1844 OpS390XORconst 1845 OpS390XORWconst 1846 OpS390XORload 1847 OpS390XORWload 1848 OpS390XXOR 1849 OpS390XXORW 1850 OpS390XXORconst 1851 OpS390XXORWconst 1852 OpS390XXORload 1853 OpS390XXORWload 1854 OpS390XCMP 1855 OpS390XCMPW 1856 OpS390XCMPU 1857 OpS390XCMPWU 1858 OpS390XCMPconst 1859 OpS390XCMPWconst 1860 OpS390XCMPUconst 1861 OpS390XCMPWUconst 1862 OpS390XFCMPS 1863 OpS390XFCMP 1864 OpS390XSLD 1865 OpS390XSLW 1866 OpS390XSLDconst 1867 OpS390XSLWconst 1868 OpS390XSRD 1869 OpS390XSRW 1870 OpS390XSRDconst 1871 OpS390XSRWconst 1872 OpS390XSRAD 1873 OpS390XSRAW 1874 OpS390XSRADconst 1875 OpS390XSRAWconst 1876 OpS390XRLLG 1877 OpS390XRLL 1878 OpS390XRLLGconst 1879 OpS390XRLLconst 1880 OpS390XNEG 1881 OpS390XNEGW 1882 OpS390XNOT 1883 OpS390XNOTW 1884 OpS390XFSQRT 1885 OpS390XMOVDEQ 1886 OpS390XMOVDNE 1887 OpS390XMOVDLT 1888 OpS390XMOVDLE 1889 OpS390XMOVDGT 1890 OpS390XMOVDGE 1891 OpS390XMOVDGTnoinv 1892 OpS390XMOVDGEnoinv 1893 OpS390XMOVBreg 1894 OpS390XMOVBZreg 1895 OpS390XMOVHreg 1896 OpS390XMOVHZreg 1897 OpS390XMOVWreg 1898 OpS390XMOVWZreg 1899 OpS390XMOVDreg 1900 OpS390XMOVDnop 1901 OpS390XMOVDconst 1902 OpS390XLDGR 1903 OpS390XLGDR 1904 OpS390XCFDBRA 1905 OpS390XCGDBRA 1906 OpS390XCFEBRA 1907 OpS390XCGEBRA 1908 OpS390XCEFBRA 1909 OpS390XCDFBRA 1910 OpS390XCEGBRA 1911 OpS390XCDGBRA 1912 OpS390XLEDBR 1913 OpS390XLDEBR 1914 OpS390XMOVDaddr 1915 OpS390XMOVDaddridx 1916 OpS390XMOVBZload 1917 OpS390XMOVBload 1918 OpS390XMOVHZload 1919 OpS390XMOVHload 1920 OpS390XMOVWZload 1921 OpS390XMOVWload 1922 OpS390XMOVDload 1923 OpS390XMOVWBR 1924 OpS390XMOVDBR 1925 OpS390XMOVHBRload 1926 OpS390XMOVWBRload 1927 OpS390XMOVDBRload 1928 OpS390XMOVBstore 1929 OpS390XMOVHstore 1930 OpS390XMOVWstore 1931 OpS390XMOVDstore 1932 OpS390XMOVHBRstore 1933 OpS390XMOVWBRstore 1934 OpS390XMOVDBRstore 1935 OpS390XMVC 1936 OpS390XMOVBZloadidx 1937 OpS390XMOVBloadidx 1938 OpS390XMOVHZloadidx 1939 OpS390XMOVHloadidx 1940 OpS390XMOVWZloadidx 1941 OpS390XMOVWloadidx 1942 OpS390XMOVDloadidx 1943 OpS390XMOVHBRloadidx 1944 OpS390XMOVWBRloadidx 1945 OpS390XMOVDBRloadidx 1946 OpS390XMOVBstoreidx 1947 OpS390XMOVHstoreidx 1948 OpS390XMOVWstoreidx 1949 OpS390XMOVDstoreidx 1950 OpS390XMOVHBRstoreidx 1951 OpS390XMOVWBRstoreidx 1952 OpS390XMOVDBRstoreidx 1953 OpS390XMOVBstoreconst 1954 OpS390XMOVHstoreconst 1955 OpS390XMOVWstoreconst 1956 OpS390XMOVDstoreconst 1957 OpS390XCLEAR 1958 OpS390XCALLstatic 1959 OpS390XCALLclosure 1960 OpS390XCALLinter 1961 OpS390XInvertFlags 1962 OpS390XLoweredGetG 1963 OpS390XLoweredGetClosurePtr 1964 OpS390XLoweredGetCallerSP 1965 OpS390XLoweredGetCallerPC 1966 OpS390XLoweredNilCheck 1967 OpS390XLoweredRound32F 1968 OpS390XLoweredRound64F 1969 OpS390XLoweredWB 1970 OpS390XFlagEQ 1971 OpS390XFlagLT 1972 OpS390XFlagGT 1973 OpS390XMOVWZatomicload 1974 OpS390XMOVDatomicload 1975 OpS390XMOVWatomicstore 1976 OpS390XMOVDatomicstore 1977 OpS390XLAA 1978 OpS390XLAAG 1979 OpS390XAddTupleFirst32 1980 OpS390XAddTupleFirst64 1981 OpS390XLoweredAtomicCas32 1982 OpS390XLoweredAtomicCas64 1983 OpS390XLoweredAtomicExchange32 1984 OpS390XLoweredAtomicExchange64 1985 OpS390XFLOGR 1986 OpS390XPOPCNT 1987 OpS390XSumBytes2 1988 OpS390XSumBytes4 1989 OpS390XSumBytes8 1990 OpS390XSTMG2 1991 OpS390XSTMG3 1992 OpS390XSTMG4 1993 OpS390XSTM2 1994 OpS390XSTM3 1995 OpS390XSTM4 1996 OpS390XLoweredMove 1997 OpS390XLoweredZero 1998 1999 OpWasmLoweredStaticCall 2000 OpWasmLoweredClosureCall 2001 OpWasmLoweredInterCall 2002 OpWasmLoweredAddr 2003 OpWasmLoweredMove 2004 OpWasmLoweredZero 2005 OpWasmLoweredGetClosurePtr 2006 OpWasmLoweredGetCallerPC 2007 OpWasmLoweredGetCallerSP 2008 OpWasmLoweredNilCheck 2009 OpWasmLoweredWB 2010 OpWasmLoweredRound32F 2011 OpWasmLoweredConvert 2012 OpWasmSelect 2013 OpWasmI64Load8U 2014 OpWasmI64Load8S 2015 OpWasmI64Load16U 2016 OpWasmI64Load16S 2017 OpWasmI64Load32U 2018 OpWasmI64Load32S 2019 OpWasmI64Load 2020 OpWasmI64Store8 2021 OpWasmI64Store16 2022 OpWasmI64Store32 2023 OpWasmI64Store 2024 OpWasmF32Load 2025 OpWasmF64Load 2026 OpWasmF32Store 2027 OpWasmF64Store 2028 OpWasmI64Const 2029 OpWasmF64Const 2030 OpWasmI64Eqz 2031 OpWasmI64Eq 2032 OpWasmI64Ne 2033 OpWasmI64LtS 2034 OpWasmI64LtU 2035 OpWasmI64GtS 2036 OpWasmI64GtU 2037 OpWasmI64LeS 2038 OpWasmI64LeU 2039 OpWasmI64GeS 2040 OpWasmI64GeU 2041 OpWasmF64Eq 2042 OpWasmF64Ne 2043 OpWasmF64Lt 2044 OpWasmF64Gt 2045 OpWasmF64Le 2046 OpWasmF64Ge 2047 OpWasmI64Add 2048 OpWasmI64AddConst 2049 OpWasmI64Sub 2050 OpWasmI64Mul 2051 OpWasmI64DivS 2052 OpWasmI64DivU 2053 OpWasmI64RemS 2054 OpWasmI64RemU 2055 OpWasmI64And 2056 OpWasmI64Or 2057 OpWasmI64Xor 2058 OpWasmI64Shl 2059 OpWasmI64ShrS 2060 OpWasmI64ShrU 2061 OpWasmF64Neg 2062 OpWasmF64Add 2063 OpWasmF64Sub 2064 OpWasmF64Mul 2065 OpWasmF64Div 2066 OpWasmI64TruncSF64 2067 OpWasmI64TruncUF64 2068 OpWasmF64ConvertSI64 2069 OpWasmF64ConvertUI64 2070 2071 OpAdd8 2072 OpAdd16 2073 OpAdd32 2074 OpAdd64 2075 OpAddPtr 2076 OpAdd32F 2077 OpAdd64F 2078 OpSub8 2079 OpSub16 2080 OpSub32 2081 OpSub64 2082 OpSubPtr 2083 OpSub32F 2084 OpSub64F 2085 OpMul8 2086 OpMul16 2087 OpMul32 2088 OpMul64 2089 OpMul32F 2090 OpMul64F 2091 OpDiv32F 2092 OpDiv64F 2093 OpHmul32 2094 OpHmul32u 2095 OpHmul64 2096 OpHmul64u 2097 OpMul32uhilo 2098 OpMul64uhilo 2099 OpMul32uover 2100 OpMul64uover 2101 OpAvg32u 2102 OpAvg64u 2103 OpDiv8 2104 OpDiv8u 2105 OpDiv16 2106 OpDiv16u 2107 OpDiv32 2108 OpDiv32u 2109 OpDiv64 2110 OpDiv64u 2111 OpDiv128u 2112 OpMod8 2113 OpMod8u 2114 OpMod16 2115 OpMod16u 2116 OpMod32 2117 OpMod32u 2118 OpMod64 2119 OpMod64u 2120 OpAnd8 2121 OpAnd16 2122 OpAnd32 2123 OpAnd64 2124 OpOr8 2125 OpOr16 2126 OpOr32 2127 OpOr64 2128 OpXor8 2129 OpXor16 2130 OpXor32 2131 OpXor64 2132 OpLsh8x8 2133 OpLsh8x16 2134 OpLsh8x32 2135 OpLsh8x64 2136 OpLsh16x8 2137 OpLsh16x16 2138 OpLsh16x32 2139 OpLsh16x64 2140 OpLsh32x8 2141 OpLsh32x16 2142 OpLsh32x32 2143 OpLsh32x64 2144 OpLsh64x8 2145 OpLsh64x16 2146 OpLsh64x32 2147 OpLsh64x64 2148 OpRsh8x8 2149 OpRsh8x16 2150 OpRsh8x32 2151 OpRsh8x64 2152 OpRsh16x8 2153 OpRsh16x16 2154 OpRsh16x32 2155 OpRsh16x64 2156 OpRsh32x8 2157 OpRsh32x16 2158 OpRsh32x32 2159 OpRsh32x64 2160 OpRsh64x8 2161 OpRsh64x16 2162 OpRsh64x32 2163 OpRsh64x64 2164 OpRsh8Ux8 2165 OpRsh8Ux16 2166 OpRsh8Ux32 2167 OpRsh8Ux64 2168 OpRsh16Ux8 2169 OpRsh16Ux16 2170 OpRsh16Ux32 2171 OpRsh16Ux64 2172 OpRsh32Ux8 2173 OpRsh32Ux16 2174 OpRsh32Ux32 2175 OpRsh32Ux64 2176 OpRsh64Ux8 2177 OpRsh64Ux16 2178 OpRsh64Ux32 2179 OpRsh64Ux64 2180 OpEq8 2181 OpEq16 2182 OpEq32 2183 OpEq64 2184 OpEqPtr 2185 OpEqInter 2186 OpEqSlice 2187 OpEq32F 2188 OpEq64F 2189 OpNeq8 2190 OpNeq16 2191 OpNeq32 2192 OpNeq64 2193 OpNeqPtr 2194 OpNeqInter 2195 OpNeqSlice 2196 OpNeq32F 2197 OpNeq64F 2198 OpLess8 2199 OpLess8U 2200 OpLess16 2201 OpLess16U 2202 OpLess32 2203 OpLess32U 2204 OpLess64 2205 OpLess64U 2206 OpLess32F 2207 OpLess64F 2208 OpLeq8 2209 OpLeq8U 2210 OpLeq16 2211 OpLeq16U 2212 OpLeq32 2213 OpLeq32U 2214 OpLeq64 2215 OpLeq64U 2216 OpLeq32F 2217 OpLeq64F 2218 OpGreater8 2219 OpGreater8U 2220 OpGreater16 2221 OpGreater16U 2222 OpGreater32 2223 OpGreater32U 2224 OpGreater64 2225 OpGreater64U 2226 OpGreater32F 2227 OpGreater64F 2228 OpGeq8 2229 OpGeq8U 2230 OpGeq16 2231 OpGeq16U 2232 OpGeq32 2233 OpGeq32U 2234 OpGeq64 2235 OpGeq64U 2236 OpGeq32F 2237 OpGeq64F 2238 OpCondSelect 2239 OpAndB 2240 OpOrB 2241 OpEqB 2242 OpNeqB 2243 OpNot 2244 OpNeg8 2245 OpNeg16 2246 OpNeg32 2247 OpNeg64 2248 OpNeg32F 2249 OpNeg64F 2250 OpCom8 2251 OpCom16 2252 OpCom32 2253 OpCom64 2254 OpCtz8 2255 OpCtz16 2256 OpCtz32 2257 OpCtz64 2258 OpCtz8NonZero 2259 OpCtz16NonZero 2260 OpCtz32NonZero 2261 OpCtz64NonZero 2262 OpBitLen8 2263 OpBitLen16 2264 OpBitLen32 2265 OpBitLen64 2266 OpBswap32 2267 OpBswap64 2268 OpBitRev8 2269 OpBitRev16 2270 OpBitRev32 2271 OpBitRev64 2272 OpPopCount8 2273 OpPopCount16 2274 OpPopCount32 2275 OpPopCount64 2276 OpRotateLeft8 2277 OpRotateLeft16 2278 OpRotateLeft32 2279 OpRotateLeft64 2280 OpSqrt 2281 OpFloor 2282 OpCeil 2283 OpTrunc 2284 OpRound 2285 OpRoundToEven 2286 OpAbs 2287 OpCopysign 2288 OpPhi 2289 OpCopy 2290 OpConvert 2291 OpConstBool 2292 OpConstString 2293 OpConstNil 2294 OpConst8 2295 OpConst16 2296 OpConst32 2297 OpConst64 2298 OpConst32F 2299 OpConst64F 2300 OpConstInterface 2301 OpConstSlice 2302 OpInitMem 2303 OpArg 2304 OpAddr 2305 OpLocalAddr 2306 OpSP 2307 OpSB 2308 OpLoad 2309 OpStore 2310 OpMove 2311 OpZero 2312 OpStoreWB 2313 OpMoveWB 2314 OpZeroWB 2315 OpWB 2316 OpClosureCall 2317 OpStaticCall 2318 OpInterCall 2319 OpSignExt8to16 2320 OpSignExt8to32 2321 OpSignExt8to64 2322 OpSignExt16to32 2323 OpSignExt16to64 2324 OpSignExt32to64 2325 OpZeroExt8to16 2326 OpZeroExt8to32 2327 OpZeroExt8to64 2328 OpZeroExt16to32 2329 OpZeroExt16to64 2330 OpZeroExt32to64 2331 OpTrunc16to8 2332 OpTrunc32to8 2333 OpTrunc32to16 2334 OpTrunc64to8 2335 OpTrunc64to16 2336 OpTrunc64to32 2337 OpCvt32to32F 2338 OpCvt32to64F 2339 OpCvt64to32F 2340 OpCvt64to64F 2341 OpCvt32Fto32 2342 OpCvt32Fto64 2343 OpCvt64Fto32 2344 OpCvt64Fto64 2345 OpCvt32Fto64F 2346 OpCvt64Fto32F 2347 OpRound32F 2348 OpRound64F 2349 OpIsNonNil 2350 OpIsInBounds 2351 OpIsSliceInBounds 2352 OpNilCheck 2353 OpGetG 2354 OpGetClosurePtr 2355 OpGetCallerPC 2356 OpGetCallerSP 2357 OpPtrIndex 2358 OpOffPtr 2359 OpSliceMake 2360 OpSlicePtr 2361 OpSliceLen 2362 OpSliceCap 2363 OpComplexMake 2364 OpComplexReal 2365 OpComplexImag 2366 OpStringMake 2367 OpStringPtr 2368 OpStringLen 2369 OpIMake 2370 OpITab 2371 OpIData 2372 OpStructMake0 2373 OpStructMake1 2374 OpStructMake2 2375 OpStructMake3 2376 OpStructMake4 2377 OpStructSelect 2378 OpArrayMake0 2379 OpArrayMake1 2380 OpArraySelect 2381 OpStoreReg 2382 OpLoadReg 2383 OpFwdRef 2384 OpUnknown 2385 OpVarDef 2386 OpVarKill 2387 OpVarLive 2388 OpKeepAlive 2389 OpInt64Make 2390 OpInt64Hi 2391 OpInt64Lo 2392 OpAdd32carry 2393 OpAdd32withcarry 2394 OpSub32carry 2395 OpSub32withcarry 2396 OpSignmask 2397 OpZeromask 2398 OpSlicemask 2399 OpCvt32Uto32F 2400 OpCvt32Uto64F 2401 OpCvt32Fto32U 2402 OpCvt64Fto32U 2403 OpCvt64Uto32F 2404 OpCvt64Uto64F 2405 OpCvt32Fto64U 2406 OpCvt64Fto64U 2407 OpSelect0 2408 OpSelect1 2409 OpAtomicLoad32 2410 OpAtomicLoad64 2411 OpAtomicLoadPtr 2412 OpAtomicLoadAcq32 2413 OpAtomicStore32 2414 OpAtomicStore64 2415 OpAtomicStorePtrNoWB 2416 OpAtomicStoreRel32 2417 OpAtomicExchange32 2418 OpAtomicExchange64 2419 OpAtomicAdd32 2420 OpAtomicAdd64 2421 OpAtomicCompareAndSwap32 2422 OpAtomicCompareAndSwap64 2423 OpAtomicCompareAndSwapRel32 2424 OpAtomicAnd8 2425 OpAtomicOr8 2426 OpAtomicAdd32Variant 2427 OpAtomicAdd64Variant 2428 OpClobber 2429 ) 2430 2431 var opcodeTable = [...]opInfo{ 2432 {name: "OpInvalid"}, 2433 2434 { 2435 name: "ADDSS", 2436 argLen: 2, 2437 commutative: true, 2438 resultInArg0: true, 2439 usesScratch: true, 2440 asm: x86.AADDSS, 2441 reg: regInfo{ 2442 inputs: []inputInfo{ 2443 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2444 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2445 }, 2446 outputs: []outputInfo{ 2447 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2448 }, 2449 }, 2450 }, 2451 { 2452 name: "ADDSD", 2453 argLen: 2, 2454 commutative: true, 2455 resultInArg0: true, 2456 asm: x86.AADDSD, 2457 reg: regInfo{ 2458 inputs: []inputInfo{ 2459 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2460 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2461 }, 2462 outputs: []outputInfo{ 2463 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2464 }, 2465 }, 2466 }, 2467 { 2468 name: "SUBSS", 2469 argLen: 2, 2470 resultInArg0: true, 2471 usesScratch: true, 2472 asm: x86.ASUBSS, 2473 reg: regInfo{ 2474 inputs: []inputInfo{ 2475 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2476 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2477 }, 2478 outputs: []outputInfo{ 2479 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2480 }, 2481 }, 2482 }, 2483 { 2484 name: "SUBSD", 2485 argLen: 2, 2486 resultInArg0: true, 2487 asm: x86.ASUBSD, 2488 reg: regInfo{ 2489 inputs: []inputInfo{ 2490 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2491 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2492 }, 2493 outputs: []outputInfo{ 2494 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2495 }, 2496 }, 2497 }, 2498 { 2499 name: "MULSS", 2500 argLen: 2, 2501 commutative: true, 2502 resultInArg0: true, 2503 usesScratch: true, 2504 asm: x86.AMULSS, 2505 reg: regInfo{ 2506 inputs: []inputInfo{ 2507 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2508 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2509 }, 2510 outputs: []outputInfo{ 2511 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2512 }, 2513 }, 2514 }, 2515 { 2516 name: "MULSD", 2517 argLen: 2, 2518 commutative: true, 2519 resultInArg0: true, 2520 asm: x86.AMULSD, 2521 reg: regInfo{ 2522 inputs: []inputInfo{ 2523 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2524 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2525 }, 2526 outputs: []outputInfo{ 2527 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2528 }, 2529 }, 2530 }, 2531 { 2532 name: "DIVSS", 2533 argLen: 2, 2534 resultInArg0: true, 2535 usesScratch: true, 2536 asm: x86.ADIVSS, 2537 reg: regInfo{ 2538 inputs: []inputInfo{ 2539 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2540 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2541 }, 2542 outputs: []outputInfo{ 2543 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2544 }, 2545 }, 2546 }, 2547 { 2548 name: "DIVSD", 2549 argLen: 2, 2550 resultInArg0: true, 2551 asm: x86.ADIVSD, 2552 reg: regInfo{ 2553 inputs: []inputInfo{ 2554 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2555 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2556 }, 2557 outputs: []outputInfo{ 2558 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2559 }, 2560 }, 2561 }, 2562 { 2563 name: "MOVSSload", 2564 auxType: auxSymOff, 2565 argLen: 2, 2566 faultOnNilArg0: true, 2567 symEffect: SymRead, 2568 asm: x86.AMOVSS, 2569 reg: regInfo{ 2570 inputs: []inputInfo{ 2571 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2572 }, 2573 outputs: []outputInfo{ 2574 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2575 }, 2576 }, 2577 }, 2578 { 2579 name: "MOVSDload", 2580 auxType: auxSymOff, 2581 argLen: 2, 2582 faultOnNilArg0: true, 2583 symEffect: SymRead, 2584 asm: x86.AMOVSD, 2585 reg: regInfo{ 2586 inputs: []inputInfo{ 2587 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2588 }, 2589 outputs: []outputInfo{ 2590 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2591 }, 2592 }, 2593 }, 2594 { 2595 name: "MOVSSconst", 2596 auxType: auxFloat32, 2597 argLen: 0, 2598 rematerializeable: true, 2599 asm: x86.AMOVSS, 2600 reg: regInfo{ 2601 outputs: []outputInfo{ 2602 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2603 }, 2604 }, 2605 }, 2606 { 2607 name: "MOVSDconst", 2608 auxType: auxFloat64, 2609 argLen: 0, 2610 rematerializeable: true, 2611 asm: x86.AMOVSD, 2612 reg: regInfo{ 2613 outputs: []outputInfo{ 2614 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2615 }, 2616 }, 2617 }, 2618 { 2619 name: "MOVSSloadidx1", 2620 auxType: auxSymOff, 2621 argLen: 3, 2622 symEffect: SymRead, 2623 asm: x86.AMOVSS, 2624 reg: regInfo{ 2625 inputs: []inputInfo{ 2626 {1, 255}, // AX CX DX BX SP BP SI DI 2627 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2628 }, 2629 outputs: []outputInfo{ 2630 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2631 }, 2632 }, 2633 }, 2634 { 2635 name: "MOVSSloadidx4", 2636 auxType: auxSymOff, 2637 argLen: 3, 2638 symEffect: SymRead, 2639 asm: x86.AMOVSS, 2640 reg: regInfo{ 2641 inputs: []inputInfo{ 2642 {1, 255}, // AX CX DX BX SP BP SI DI 2643 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2644 }, 2645 outputs: []outputInfo{ 2646 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2647 }, 2648 }, 2649 }, 2650 { 2651 name: "MOVSDloadidx1", 2652 auxType: auxSymOff, 2653 argLen: 3, 2654 symEffect: SymRead, 2655 asm: x86.AMOVSD, 2656 reg: regInfo{ 2657 inputs: []inputInfo{ 2658 {1, 255}, // AX CX DX BX SP BP SI DI 2659 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2660 }, 2661 outputs: []outputInfo{ 2662 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2663 }, 2664 }, 2665 }, 2666 { 2667 name: "MOVSDloadidx8", 2668 auxType: auxSymOff, 2669 argLen: 3, 2670 symEffect: SymRead, 2671 asm: x86.AMOVSD, 2672 reg: regInfo{ 2673 inputs: []inputInfo{ 2674 {1, 255}, // AX CX DX BX SP BP SI DI 2675 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2676 }, 2677 outputs: []outputInfo{ 2678 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2679 }, 2680 }, 2681 }, 2682 { 2683 name: "MOVSSstore", 2684 auxType: auxSymOff, 2685 argLen: 3, 2686 faultOnNilArg0: true, 2687 symEffect: SymWrite, 2688 asm: x86.AMOVSS, 2689 reg: regInfo{ 2690 inputs: []inputInfo{ 2691 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2692 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2693 }, 2694 }, 2695 }, 2696 { 2697 name: "MOVSDstore", 2698 auxType: auxSymOff, 2699 argLen: 3, 2700 faultOnNilArg0: true, 2701 symEffect: SymWrite, 2702 asm: x86.AMOVSD, 2703 reg: regInfo{ 2704 inputs: []inputInfo{ 2705 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2706 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2707 }, 2708 }, 2709 }, 2710 { 2711 name: "MOVSSstoreidx1", 2712 auxType: auxSymOff, 2713 argLen: 4, 2714 symEffect: SymWrite, 2715 asm: x86.AMOVSS, 2716 reg: regInfo{ 2717 inputs: []inputInfo{ 2718 {1, 255}, // AX CX DX BX SP BP SI DI 2719 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2720 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2721 }, 2722 }, 2723 }, 2724 { 2725 name: "MOVSSstoreidx4", 2726 auxType: auxSymOff, 2727 argLen: 4, 2728 symEffect: SymWrite, 2729 asm: x86.AMOVSS, 2730 reg: regInfo{ 2731 inputs: []inputInfo{ 2732 {1, 255}, // AX CX DX BX SP BP SI DI 2733 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2734 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2735 }, 2736 }, 2737 }, 2738 { 2739 name: "MOVSDstoreidx1", 2740 auxType: auxSymOff, 2741 argLen: 4, 2742 symEffect: SymWrite, 2743 asm: x86.AMOVSD, 2744 reg: regInfo{ 2745 inputs: []inputInfo{ 2746 {1, 255}, // AX CX DX BX SP BP SI DI 2747 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2748 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2749 }, 2750 }, 2751 }, 2752 { 2753 name: "MOVSDstoreidx8", 2754 auxType: auxSymOff, 2755 argLen: 4, 2756 symEffect: SymWrite, 2757 asm: x86.AMOVSD, 2758 reg: regInfo{ 2759 inputs: []inputInfo{ 2760 {1, 255}, // AX CX DX BX SP BP SI DI 2761 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2762 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2763 }, 2764 }, 2765 }, 2766 { 2767 name: "ADDSSload", 2768 auxType: auxSymOff, 2769 argLen: 3, 2770 resultInArg0: true, 2771 faultOnNilArg1: true, 2772 symEffect: SymRead, 2773 asm: x86.AADDSS, 2774 reg: regInfo{ 2775 inputs: []inputInfo{ 2776 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2777 {1, 65791}, // AX CX DX BX SP BP SI DI SB 2778 }, 2779 outputs: []outputInfo{ 2780 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2781 }, 2782 }, 2783 }, 2784 { 2785 name: "ADDSDload", 2786 auxType: auxSymOff, 2787 argLen: 3, 2788 resultInArg0: true, 2789 faultOnNilArg1: true, 2790 symEffect: SymRead, 2791 asm: x86.AADDSD, 2792 reg: regInfo{ 2793 inputs: []inputInfo{ 2794 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2795 {1, 65791}, // AX CX DX BX SP BP SI DI SB 2796 }, 2797 outputs: []outputInfo{ 2798 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2799 }, 2800 }, 2801 }, 2802 { 2803 name: "SUBSSload", 2804 auxType: auxSymOff, 2805 argLen: 3, 2806 resultInArg0: true, 2807 faultOnNilArg1: true, 2808 symEffect: SymRead, 2809 asm: x86.ASUBSS, 2810 reg: regInfo{ 2811 inputs: []inputInfo{ 2812 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2813 {1, 65791}, // AX CX DX BX SP BP SI DI SB 2814 }, 2815 outputs: []outputInfo{ 2816 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2817 }, 2818 }, 2819 }, 2820 { 2821 name: "SUBSDload", 2822 auxType: auxSymOff, 2823 argLen: 3, 2824 resultInArg0: true, 2825 faultOnNilArg1: true, 2826 symEffect: SymRead, 2827 asm: x86.ASUBSD, 2828 reg: regInfo{ 2829 inputs: []inputInfo{ 2830 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2831 {1, 65791}, // AX CX DX BX SP BP SI DI SB 2832 }, 2833 outputs: []outputInfo{ 2834 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2835 }, 2836 }, 2837 }, 2838 { 2839 name: "MULSSload", 2840 auxType: auxSymOff, 2841 argLen: 3, 2842 resultInArg0: true, 2843 faultOnNilArg1: true, 2844 symEffect: SymRead, 2845 asm: x86.AMULSS, 2846 reg: regInfo{ 2847 inputs: []inputInfo{ 2848 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2849 {1, 65791}, // AX CX DX BX SP BP SI DI SB 2850 }, 2851 outputs: []outputInfo{ 2852 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2853 }, 2854 }, 2855 }, 2856 { 2857 name: "MULSDload", 2858 auxType: auxSymOff, 2859 argLen: 3, 2860 resultInArg0: true, 2861 faultOnNilArg1: true, 2862 symEffect: SymRead, 2863 asm: x86.AMULSD, 2864 reg: regInfo{ 2865 inputs: []inputInfo{ 2866 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2867 {1, 65791}, // AX CX DX BX SP BP SI DI SB 2868 }, 2869 outputs: []outputInfo{ 2870 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2871 }, 2872 }, 2873 }, 2874 { 2875 name: "DIVSSload", 2876 auxType: auxSymOff, 2877 argLen: 3, 2878 resultInArg0: true, 2879 faultOnNilArg1: true, 2880 symEffect: SymRead, 2881 asm: x86.ADIVSS, 2882 reg: regInfo{ 2883 inputs: []inputInfo{ 2884 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2885 {1, 65791}, // AX CX DX BX SP BP SI DI SB 2886 }, 2887 outputs: []outputInfo{ 2888 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2889 }, 2890 }, 2891 }, 2892 { 2893 name: "DIVSDload", 2894 auxType: auxSymOff, 2895 argLen: 3, 2896 resultInArg0: true, 2897 faultOnNilArg1: true, 2898 symEffect: SymRead, 2899 asm: x86.ADIVSD, 2900 reg: regInfo{ 2901 inputs: []inputInfo{ 2902 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2903 {1, 65791}, // AX CX DX BX SP BP SI DI SB 2904 }, 2905 outputs: []outputInfo{ 2906 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2907 }, 2908 }, 2909 }, 2910 { 2911 name: "ADDL", 2912 argLen: 2, 2913 commutative: true, 2914 clobberFlags: true, 2915 asm: x86.AADDL, 2916 reg: regInfo{ 2917 inputs: []inputInfo{ 2918 {1, 239}, // AX CX DX BX BP SI DI 2919 {0, 255}, // AX CX DX BX SP BP SI DI 2920 }, 2921 outputs: []outputInfo{ 2922 {0, 239}, // AX CX DX BX BP SI DI 2923 }, 2924 }, 2925 }, 2926 { 2927 name: "ADDLconst", 2928 auxType: auxInt32, 2929 argLen: 1, 2930 clobberFlags: true, 2931 asm: x86.AADDL, 2932 reg: regInfo{ 2933 inputs: []inputInfo{ 2934 {0, 255}, // AX CX DX BX SP BP SI DI 2935 }, 2936 outputs: []outputInfo{ 2937 {0, 239}, // AX CX DX BX BP SI DI 2938 }, 2939 }, 2940 }, 2941 { 2942 name: "ADDLcarry", 2943 argLen: 2, 2944 commutative: true, 2945 resultInArg0: true, 2946 asm: x86.AADDL, 2947 reg: regInfo{ 2948 inputs: []inputInfo{ 2949 {0, 239}, // AX CX DX BX BP SI DI 2950 {1, 239}, // AX CX DX BX BP SI DI 2951 }, 2952 outputs: []outputInfo{ 2953 {1, 0}, 2954 {0, 239}, // AX CX DX BX BP SI DI 2955 }, 2956 }, 2957 }, 2958 { 2959 name: "ADDLconstcarry", 2960 auxType: auxInt32, 2961 argLen: 1, 2962 resultInArg0: true, 2963 asm: x86.AADDL, 2964 reg: regInfo{ 2965 inputs: []inputInfo{ 2966 {0, 239}, // AX CX DX BX BP SI DI 2967 }, 2968 outputs: []outputInfo{ 2969 {1, 0}, 2970 {0, 239}, // AX CX DX BX BP SI DI 2971 }, 2972 }, 2973 }, 2974 { 2975 name: "ADCL", 2976 argLen: 3, 2977 commutative: true, 2978 resultInArg0: true, 2979 clobberFlags: true, 2980 asm: x86.AADCL, 2981 reg: regInfo{ 2982 inputs: []inputInfo{ 2983 {0, 239}, // AX CX DX BX BP SI DI 2984 {1, 239}, // AX CX DX BX BP SI DI 2985 }, 2986 outputs: []outputInfo{ 2987 {0, 239}, // AX CX DX BX BP SI DI 2988 }, 2989 }, 2990 }, 2991 { 2992 name: "ADCLconst", 2993 auxType: auxInt32, 2994 argLen: 2, 2995 resultInArg0: true, 2996 clobberFlags: true, 2997 asm: x86.AADCL, 2998 reg: regInfo{ 2999 inputs: []inputInfo{ 3000 {0, 239}, // AX CX DX BX BP SI DI 3001 }, 3002 outputs: []outputInfo{ 3003 {0, 239}, // AX CX DX BX BP SI DI 3004 }, 3005 }, 3006 }, 3007 { 3008 name: "SUBL", 3009 argLen: 2, 3010 resultInArg0: true, 3011 clobberFlags: true, 3012 asm: x86.ASUBL, 3013 reg: regInfo{ 3014 inputs: []inputInfo{ 3015 {0, 239}, // AX CX DX BX BP SI DI 3016 {1, 239}, // AX CX DX BX BP SI DI 3017 }, 3018 outputs: []outputInfo{ 3019 {0, 239}, // AX CX DX BX BP SI DI 3020 }, 3021 }, 3022 }, 3023 { 3024 name: "SUBLconst", 3025 auxType: auxInt32, 3026 argLen: 1, 3027 resultInArg0: true, 3028 clobberFlags: true, 3029 asm: x86.ASUBL, 3030 reg: regInfo{ 3031 inputs: []inputInfo{ 3032 {0, 239}, // AX CX DX BX BP SI DI 3033 }, 3034 outputs: []outputInfo{ 3035 {0, 239}, // AX CX DX BX BP SI DI 3036 }, 3037 }, 3038 }, 3039 { 3040 name: "SUBLcarry", 3041 argLen: 2, 3042 resultInArg0: true, 3043 asm: x86.ASUBL, 3044 reg: regInfo{ 3045 inputs: []inputInfo{ 3046 {0, 239}, // AX CX DX BX BP SI DI 3047 {1, 239}, // AX CX DX BX BP SI DI 3048 }, 3049 outputs: []outputInfo{ 3050 {1, 0}, 3051 {0, 239}, // AX CX DX BX BP SI DI 3052 }, 3053 }, 3054 }, 3055 { 3056 name: "SUBLconstcarry", 3057 auxType: auxInt32, 3058 argLen: 1, 3059 resultInArg0: true, 3060 asm: x86.ASUBL, 3061 reg: regInfo{ 3062 inputs: []inputInfo{ 3063 {0, 239}, // AX CX DX BX BP SI DI 3064 }, 3065 outputs: []outputInfo{ 3066 {1, 0}, 3067 {0, 239}, // AX CX DX BX BP SI DI 3068 }, 3069 }, 3070 }, 3071 { 3072 name: "SBBL", 3073 argLen: 3, 3074 resultInArg0: true, 3075 clobberFlags: true, 3076 asm: x86.ASBBL, 3077 reg: regInfo{ 3078 inputs: []inputInfo{ 3079 {0, 239}, // AX CX DX BX BP SI DI 3080 {1, 239}, // AX CX DX BX BP SI DI 3081 }, 3082 outputs: []outputInfo{ 3083 {0, 239}, // AX CX DX BX BP SI DI 3084 }, 3085 }, 3086 }, 3087 { 3088 name: "SBBLconst", 3089 auxType: auxInt32, 3090 argLen: 2, 3091 resultInArg0: true, 3092 clobberFlags: true, 3093 asm: x86.ASBBL, 3094 reg: regInfo{ 3095 inputs: []inputInfo{ 3096 {0, 239}, // AX CX DX BX BP SI DI 3097 }, 3098 outputs: []outputInfo{ 3099 {0, 239}, // AX CX DX BX BP SI DI 3100 }, 3101 }, 3102 }, 3103 { 3104 name: "MULL", 3105 argLen: 2, 3106 commutative: true, 3107 resultInArg0: true, 3108 clobberFlags: true, 3109 asm: x86.AIMULL, 3110 reg: regInfo{ 3111 inputs: []inputInfo{ 3112 {0, 239}, // AX CX DX BX BP SI DI 3113 {1, 239}, // AX CX DX BX BP SI DI 3114 }, 3115 outputs: []outputInfo{ 3116 {0, 239}, // AX CX DX BX BP SI DI 3117 }, 3118 }, 3119 }, 3120 { 3121 name: "MULLconst", 3122 auxType: auxInt32, 3123 argLen: 1, 3124 clobberFlags: true, 3125 asm: x86.AIMUL3L, 3126 reg: regInfo{ 3127 inputs: []inputInfo{ 3128 {0, 239}, // AX CX DX BX BP SI DI 3129 }, 3130 outputs: []outputInfo{ 3131 {0, 239}, // AX CX DX BX BP SI DI 3132 }, 3133 }, 3134 }, 3135 { 3136 name: "MULLU", 3137 argLen: 2, 3138 commutative: true, 3139 clobberFlags: true, 3140 asm: x86.AMULL, 3141 reg: regInfo{ 3142 inputs: []inputInfo{ 3143 {0, 1}, // AX 3144 {1, 255}, // AX CX DX BX SP BP SI DI 3145 }, 3146 clobbers: 4, // DX 3147 outputs: []outputInfo{ 3148 {1, 0}, 3149 {0, 1}, // AX 3150 }, 3151 }, 3152 }, 3153 { 3154 name: "HMULL", 3155 argLen: 2, 3156 commutative: true, 3157 clobberFlags: true, 3158 asm: x86.AIMULL, 3159 reg: regInfo{ 3160 inputs: []inputInfo{ 3161 {0, 1}, // AX 3162 {1, 255}, // AX CX DX BX SP BP SI DI 3163 }, 3164 clobbers: 1, // AX 3165 outputs: []outputInfo{ 3166 {0, 4}, // DX 3167 }, 3168 }, 3169 }, 3170 { 3171 name: "HMULLU", 3172 argLen: 2, 3173 commutative: true, 3174 clobberFlags: true, 3175 asm: x86.AMULL, 3176 reg: regInfo{ 3177 inputs: []inputInfo{ 3178 {0, 1}, // AX 3179 {1, 255}, // AX CX DX BX SP BP SI DI 3180 }, 3181 clobbers: 1, // AX 3182 outputs: []outputInfo{ 3183 {0, 4}, // DX 3184 }, 3185 }, 3186 }, 3187 { 3188 name: "MULLQU", 3189 argLen: 2, 3190 commutative: true, 3191 clobberFlags: true, 3192 asm: x86.AMULL, 3193 reg: regInfo{ 3194 inputs: []inputInfo{ 3195 {0, 1}, // AX 3196 {1, 255}, // AX CX DX BX SP BP SI DI 3197 }, 3198 outputs: []outputInfo{ 3199 {0, 4}, // DX 3200 {1, 1}, // AX 3201 }, 3202 }, 3203 }, 3204 { 3205 name: "AVGLU", 3206 argLen: 2, 3207 commutative: true, 3208 resultInArg0: true, 3209 clobberFlags: true, 3210 reg: regInfo{ 3211 inputs: []inputInfo{ 3212 {0, 239}, // AX CX DX BX BP SI DI 3213 {1, 239}, // AX CX DX BX BP SI DI 3214 }, 3215 outputs: []outputInfo{ 3216 {0, 239}, // AX CX DX BX BP SI DI 3217 }, 3218 }, 3219 }, 3220 { 3221 name: "DIVL", 3222 auxType: auxBool, 3223 argLen: 2, 3224 clobberFlags: true, 3225 asm: x86.AIDIVL, 3226 reg: regInfo{ 3227 inputs: []inputInfo{ 3228 {0, 1}, // AX 3229 {1, 251}, // AX CX BX SP BP SI DI 3230 }, 3231 clobbers: 4, // DX 3232 outputs: []outputInfo{ 3233 {0, 1}, // AX 3234 }, 3235 }, 3236 }, 3237 { 3238 name: "DIVW", 3239 auxType: auxBool, 3240 argLen: 2, 3241 clobberFlags: true, 3242 asm: x86.AIDIVW, 3243 reg: regInfo{ 3244 inputs: []inputInfo{ 3245 {0, 1}, // AX 3246 {1, 251}, // AX CX BX SP BP SI DI 3247 }, 3248 clobbers: 4, // DX 3249 outputs: []outputInfo{ 3250 {0, 1}, // AX 3251 }, 3252 }, 3253 }, 3254 { 3255 name: "DIVLU", 3256 argLen: 2, 3257 clobberFlags: true, 3258 asm: x86.ADIVL, 3259 reg: regInfo{ 3260 inputs: []inputInfo{ 3261 {0, 1}, // AX 3262 {1, 251}, // AX CX BX SP BP SI DI 3263 }, 3264 clobbers: 4, // DX 3265 outputs: []outputInfo{ 3266 {0, 1}, // AX 3267 }, 3268 }, 3269 }, 3270 { 3271 name: "DIVWU", 3272 argLen: 2, 3273 clobberFlags: true, 3274 asm: x86.ADIVW, 3275 reg: regInfo{ 3276 inputs: []inputInfo{ 3277 {0, 1}, // AX 3278 {1, 251}, // AX CX BX SP BP SI DI 3279 }, 3280 clobbers: 4, // DX 3281 outputs: []outputInfo{ 3282 {0, 1}, // AX 3283 }, 3284 }, 3285 }, 3286 { 3287 name: "MODL", 3288 auxType: auxBool, 3289 argLen: 2, 3290 clobberFlags: true, 3291 asm: x86.AIDIVL, 3292 reg: regInfo{ 3293 inputs: []inputInfo{ 3294 {0, 1}, // AX 3295 {1, 251}, // AX CX BX SP BP SI DI 3296 }, 3297 clobbers: 1, // AX 3298 outputs: []outputInfo{ 3299 {0, 4}, // DX 3300 }, 3301 }, 3302 }, 3303 { 3304 name: "MODW", 3305 auxType: auxBool, 3306 argLen: 2, 3307 clobberFlags: true, 3308 asm: x86.AIDIVW, 3309 reg: regInfo{ 3310 inputs: []inputInfo{ 3311 {0, 1}, // AX 3312 {1, 251}, // AX CX BX SP BP SI DI 3313 }, 3314 clobbers: 1, // AX 3315 outputs: []outputInfo{ 3316 {0, 4}, // DX 3317 }, 3318 }, 3319 }, 3320 { 3321 name: "MODLU", 3322 argLen: 2, 3323 clobberFlags: true, 3324 asm: x86.ADIVL, 3325 reg: regInfo{ 3326 inputs: []inputInfo{ 3327 {0, 1}, // AX 3328 {1, 251}, // AX CX BX SP BP SI DI 3329 }, 3330 clobbers: 1, // AX 3331 outputs: []outputInfo{ 3332 {0, 4}, // DX 3333 }, 3334 }, 3335 }, 3336 { 3337 name: "MODWU", 3338 argLen: 2, 3339 clobberFlags: true, 3340 asm: x86.ADIVW, 3341 reg: regInfo{ 3342 inputs: []inputInfo{ 3343 {0, 1}, // AX 3344 {1, 251}, // AX CX BX SP BP SI DI 3345 }, 3346 clobbers: 1, // AX 3347 outputs: []outputInfo{ 3348 {0, 4}, // DX 3349 }, 3350 }, 3351 }, 3352 { 3353 name: "ANDL", 3354 argLen: 2, 3355 commutative: true, 3356 resultInArg0: true, 3357 clobberFlags: true, 3358 asm: x86.AANDL, 3359 reg: regInfo{ 3360 inputs: []inputInfo{ 3361 {0, 239}, // AX CX DX BX BP SI DI 3362 {1, 239}, // AX CX DX BX BP SI DI 3363 }, 3364 outputs: []outputInfo{ 3365 {0, 239}, // AX CX DX BX BP SI DI 3366 }, 3367 }, 3368 }, 3369 { 3370 name: "ANDLconst", 3371 auxType: auxInt32, 3372 argLen: 1, 3373 resultInArg0: true, 3374 clobberFlags: true, 3375 asm: x86.AANDL, 3376 reg: regInfo{ 3377 inputs: []inputInfo{ 3378 {0, 239}, // AX CX DX BX BP SI DI 3379 }, 3380 outputs: []outputInfo{ 3381 {0, 239}, // AX CX DX BX BP SI DI 3382 }, 3383 }, 3384 }, 3385 { 3386 name: "ORL", 3387 argLen: 2, 3388 commutative: true, 3389 resultInArg0: true, 3390 clobberFlags: true, 3391 asm: x86.AORL, 3392 reg: regInfo{ 3393 inputs: []inputInfo{ 3394 {0, 239}, // AX CX DX BX BP SI DI 3395 {1, 239}, // AX CX DX BX BP SI DI 3396 }, 3397 outputs: []outputInfo{ 3398 {0, 239}, // AX CX DX BX BP SI DI 3399 }, 3400 }, 3401 }, 3402 { 3403 name: "ORLconst", 3404 auxType: auxInt32, 3405 argLen: 1, 3406 resultInArg0: true, 3407 clobberFlags: true, 3408 asm: x86.AORL, 3409 reg: regInfo{ 3410 inputs: []inputInfo{ 3411 {0, 239}, // AX CX DX BX BP SI DI 3412 }, 3413 outputs: []outputInfo{ 3414 {0, 239}, // AX CX DX BX BP SI DI 3415 }, 3416 }, 3417 }, 3418 { 3419 name: "XORL", 3420 argLen: 2, 3421 commutative: true, 3422 resultInArg0: true, 3423 clobberFlags: true, 3424 asm: x86.AXORL, 3425 reg: regInfo{ 3426 inputs: []inputInfo{ 3427 {0, 239}, // AX CX DX BX BP SI DI 3428 {1, 239}, // AX CX DX BX BP SI DI 3429 }, 3430 outputs: []outputInfo{ 3431 {0, 239}, // AX CX DX BX BP SI DI 3432 }, 3433 }, 3434 }, 3435 { 3436 name: "XORLconst", 3437 auxType: auxInt32, 3438 argLen: 1, 3439 resultInArg0: true, 3440 clobberFlags: true, 3441 asm: x86.AXORL, 3442 reg: regInfo{ 3443 inputs: []inputInfo{ 3444 {0, 239}, // AX CX DX BX BP SI DI 3445 }, 3446 outputs: []outputInfo{ 3447 {0, 239}, // AX CX DX BX BP SI DI 3448 }, 3449 }, 3450 }, 3451 { 3452 name: "CMPL", 3453 argLen: 2, 3454 asm: x86.ACMPL, 3455 reg: regInfo{ 3456 inputs: []inputInfo{ 3457 {0, 255}, // AX CX DX BX SP BP SI DI 3458 {1, 255}, // AX CX DX BX SP BP SI DI 3459 }, 3460 }, 3461 }, 3462 { 3463 name: "CMPW", 3464 argLen: 2, 3465 asm: x86.ACMPW, 3466 reg: regInfo{ 3467 inputs: []inputInfo{ 3468 {0, 255}, // AX CX DX BX SP BP SI DI 3469 {1, 255}, // AX CX DX BX SP BP SI DI 3470 }, 3471 }, 3472 }, 3473 { 3474 name: "CMPB", 3475 argLen: 2, 3476 asm: x86.ACMPB, 3477 reg: regInfo{ 3478 inputs: []inputInfo{ 3479 {0, 255}, // AX CX DX BX SP BP SI DI 3480 {1, 255}, // AX CX DX BX SP BP SI DI 3481 }, 3482 }, 3483 }, 3484 { 3485 name: "CMPLconst", 3486 auxType: auxInt32, 3487 argLen: 1, 3488 asm: x86.ACMPL, 3489 reg: regInfo{ 3490 inputs: []inputInfo{ 3491 {0, 255}, // AX CX DX BX SP BP SI DI 3492 }, 3493 }, 3494 }, 3495 { 3496 name: "CMPWconst", 3497 auxType: auxInt16, 3498 argLen: 1, 3499 asm: x86.ACMPW, 3500 reg: regInfo{ 3501 inputs: []inputInfo{ 3502 {0, 255}, // AX CX DX BX SP BP SI DI 3503 }, 3504 }, 3505 }, 3506 { 3507 name: "CMPBconst", 3508 auxType: auxInt8, 3509 argLen: 1, 3510 asm: x86.ACMPB, 3511 reg: regInfo{ 3512 inputs: []inputInfo{ 3513 {0, 255}, // AX CX DX BX SP BP SI DI 3514 }, 3515 }, 3516 }, 3517 { 3518 name: "CMPLload", 3519 auxType: auxSymOff, 3520 argLen: 3, 3521 faultOnNilArg0: true, 3522 symEffect: SymRead, 3523 asm: x86.ACMPL, 3524 reg: regInfo{ 3525 inputs: []inputInfo{ 3526 {1, 255}, // AX CX DX BX SP BP SI DI 3527 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3528 }, 3529 }, 3530 }, 3531 { 3532 name: "CMPWload", 3533 auxType: auxSymOff, 3534 argLen: 3, 3535 faultOnNilArg0: true, 3536 symEffect: SymRead, 3537 asm: x86.ACMPW, 3538 reg: regInfo{ 3539 inputs: []inputInfo{ 3540 {1, 255}, // AX CX DX BX SP BP SI DI 3541 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3542 }, 3543 }, 3544 }, 3545 { 3546 name: "CMPBload", 3547 auxType: auxSymOff, 3548 argLen: 3, 3549 faultOnNilArg0: true, 3550 symEffect: SymRead, 3551 asm: x86.ACMPB, 3552 reg: regInfo{ 3553 inputs: []inputInfo{ 3554 {1, 255}, // AX CX DX BX SP BP SI DI 3555 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3556 }, 3557 }, 3558 }, 3559 { 3560 name: "CMPLconstload", 3561 auxType: auxSymValAndOff, 3562 argLen: 2, 3563 faultOnNilArg0: true, 3564 symEffect: SymRead, 3565 asm: x86.ACMPL, 3566 reg: regInfo{ 3567 inputs: []inputInfo{ 3568 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3569 }, 3570 }, 3571 }, 3572 { 3573 name: "CMPWconstload", 3574 auxType: auxSymValAndOff, 3575 argLen: 2, 3576 faultOnNilArg0: true, 3577 symEffect: SymRead, 3578 asm: x86.ACMPW, 3579 reg: regInfo{ 3580 inputs: []inputInfo{ 3581 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3582 }, 3583 }, 3584 }, 3585 { 3586 name: "CMPBconstload", 3587 auxType: auxSymValAndOff, 3588 argLen: 2, 3589 faultOnNilArg0: true, 3590 symEffect: SymRead, 3591 asm: x86.ACMPB, 3592 reg: regInfo{ 3593 inputs: []inputInfo{ 3594 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3595 }, 3596 }, 3597 }, 3598 { 3599 name: "UCOMISS", 3600 argLen: 2, 3601 usesScratch: true, 3602 asm: x86.AUCOMISS, 3603 reg: regInfo{ 3604 inputs: []inputInfo{ 3605 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3606 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3607 }, 3608 }, 3609 }, 3610 { 3611 name: "UCOMISD", 3612 argLen: 2, 3613 usesScratch: true, 3614 asm: x86.AUCOMISD, 3615 reg: regInfo{ 3616 inputs: []inputInfo{ 3617 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3618 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3619 }, 3620 }, 3621 }, 3622 { 3623 name: "TESTL", 3624 argLen: 2, 3625 commutative: true, 3626 asm: x86.ATESTL, 3627 reg: regInfo{ 3628 inputs: []inputInfo{ 3629 {0, 255}, // AX CX DX BX SP BP SI DI 3630 {1, 255}, // AX CX DX BX SP BP SI DI 3631 }, 3632 }, 3633 }, 3634 { 3635 name: "TESTW", 3636 argLen: 2, 3637 commutative: true, 3638 asm: x86.ATESTW, 3639 reg: regInfo{ 3640 inputs: []inputInfo{ 3641 {0, 255}, // AX CX DX BX SP BP SI DI 3642 {1, 255}, // AX CX DX BX SP BP SI DI 3643 }, 3644 }, 3645 }, 3646 { 3647 name: "TESTB", 3648 argLen: 2, 3649 commutative: true, 3650 asm: x86.ATESTB, 3651 reg: regInfo{ 3652 inputs: []inputInfo{ 3653 {0, 255}, // AX CX DX BX SP BP SI DI 3654 {1, 255}, // AX CX DX BX SP BP SI DI 3655 }, 3656 }, 3657 }, 3658 { 3659 name: "TESTLconst", 3660 auxType: auxInt32, 3661 argLen: 1, 3662 asm: x86.ATESTL, 3663 reg: regInfo{ 3664 inputs: []inputInfo{ 3665 {0, 255}, // AX CX DX BX SP BP SI DI 3666 }, 3667 }, 3668 }, 3669 { 3670 name: "TESTWconst", 3671 auxType: auxInt16, 3672 argLen: 1, 3673 asm: x86.ATESTW, 3674 reg: regInfo{ 3675 inputs: []inputInfo{ 3676 {0, 255}, // AX CX DX BX SP BP SI DI 3677 }, 3678 }, 3679 }, 3680 { 3681 name: "TESTBconst", 3682 auxType: auxInt8, 3683 argLen: 1, 3684 asm: x86.ATESTB, 3685 reg: regInfo{ 3686 inputs: []inputInfo{ 3687 {0, 255}, // AX CX DX BX SP BP SI DI 3688 }, 3689 }, 3690 }, 3691 { 3692 name: "SHLL", 3693 argLen: 2, 3694 resultInArg0: true, 3695 clobberFlags: true, 3696 asm: x86.ASHLL, 3697 reg: regInfo{ 3698 inputs: []inputInfo{ 3699 {1, 2}, // CX 3700 {0, 239}, // AX CX DX BX BP SI DI 3701 }, 3702 outputs: []outputInfo{ 3703 {0, 239}, // AX CX DX BX BP SI DI 3704 }, 3705 }, 3706 }, 3707 { 3708 name: "SHLLconst", 3709 auxType: auxInt32, 3710 argLen: 1, 3711 resultInArg0: true, 3712 clobberFlags: true, 3713 asm: x86.ASHLL, 3714 reg: regInfo{ 3715 inputs: []inputInfo{ 3716 {0, 239}, // AX CX DX BX BP SI DI 3717 }, 3718 outputs: []outputInfo{ 3719 {0, 239}, // AX CX DX BX BP SI DI 3720 }, 3721 }, 3722 }, 3723 { 3724 name: "SHRL", 3725 argLen: 2, 3726 resultInArg0: true, 3727 clobberFlags: true, 3728 asm: x86.ASHRL, 3729 reg: regInfo{ 3730 inputs: []inputInfo{ 3731 {1, 2}, // CX 3732 {0, 239}, // AX CX DX BX BP SI DI 3733 }, 3734 outputs: []outputInfo{ 3735 {0, 239}, // AX CX DX BX BP SI DI 3736 }, 3737 }, 3738 }, 3739 { 3740 name: "SHRW", 3741 argLen: 2, 3742 resultInArg0: true, 3743 clobberFlags: true, 3744 asm: x86.ASHRW, 3745 reg: regInfo{ 3746 inputs: []inputInfo{ 3747 {1, 2}, // CX 3748 {0, 239}, // AX CX DX BX BP SI DI 3749 }, 3750 outputs: []outputInfo{ 3751 {0, 239}, // AX CX DX BX BP SI DI 3752 }, 3753 }, 3754 }, 3755 { 3756 name: "SHRB", 3757 argLen: 2, 3758 resultInArg0: true, 3759 clobberFlags: true, 3760 asm: x86.ASHRB, 3761 reg: regInfo{ 3762 inputs: []inputInfo{ 3763 {1, 2}, // CX 3764 {0, 239}, // AX CX DX BX BP SI DI 3765 }, 3766 outputs: []outputInfo{ 3767 {0, 239}, // AX CX DX BX BP SI DI 3768 }, 3769 }, 3770 }, 3771 { 3772 name: "SHRLconst", 3773 auxType: auxInt32, 3774 argLen: 1, 3775 resultInArg0: true, 3776 clobberFlags: true, 3777 asm: x86.ASHRL, 3778 reg: regInfo{ 3779 inputs: []inputInfo{ 3780 {0, 239}, // AX CX DX BX BP SI DI 3781 }, 3782 outputs: []outputInfo{ 3783 {0, 239}, // AX CX DX BX BP SI DI 3784 }, 3785 }, 3786 }, 3787 { 3788 name: "SHRWconst", 3789 auxType: auxInt16, 3790 argLen: 1, 3791 resultInArg0: true, 3792 clobberFlags: true, 3793 asm: x86.ASHRW, 3794 reg: regInfo{ 3795 inputs: []inputInfo{ 3796 {0, 239}, // AX CX DX BX BP SI DI 3797 }, 3798 outputs: []outputInfo{ 3799 {0, 239}, // AX CX DX BX BP SI DI 3800 }, 3801 }, 3802 }, 3803 { 3804 name: "SHRBconst", 3805 auxType: auxInt8, 3806 argLen: 1, 3807 resultInArg0: true, 3808 clobberFlags: true, 3809 asm: x86.ASHRB, 3810 reg: regInfo{ 3811 inputs: []inputInfo{ 3812 {0, 239}, // AX CX DX BX BP SI DI 3813 }, 3814 outputs: []outputInfo{ 3815 {0, 239}, // AX CX DX BX BP SI DI 3816 }, 3817 }, 3818 }, 3819 { 3820 name: "SARL", 3821 argLen: 2, 3822 resultInArg0: true, 3823 clobberFlags: true, 3824 asm: x86.ASARL, 3825 reg: regInfo{ 3826 inputs: []inputInfo{ 3827 {1, 2}, // CX 3828 {0, 239}, // AX CX DX BX BP SI DI 3829 }, 3830 outputs: []outputInfo{ 3831 {0, 239}, // AX CX DX BX BP SI DI 3832 }, 3833 }, 3834 }, 3835 { 3836 name: "SARW", 3837 argLen: 2, 3838 resultInArg0: true, 3839 clobberFlags: true, 3840 asm: x86.ASARW, 3841 reg: regInfo{ 3842 inputs: []inputInfo{ 3843 {1, 2}, // CX 3844 {0, 239}, // AX CX DX BX BP SI DI 3845 }, 3846 outputs: []outputInfo{ 3847 {0, 239}, // AX CX DX BX BP SI DI 3848 }, 3849 }, 3850 }, 3851 { 3852 name: "SARB", 3853 argLen: 2, 3854 resultInArg0: true, 3855 clobberFlags: true, 3856 asm: x86.ASARB, 3857 reg: regInfo{ 3858 inputs: []inputInfo{ 3859 {1, 2}, // CX 3860 {0, 239}, // AX CX DX BX BP SI DI 3861 }, 3862 outputs: []outputInfo{ 3863 {0, 239}, // AX CX DX BX BP SI DI 3864 }, 3865 }, 3866 }, 3867 { 3868 name: "SARLconst", 3869 auxType: auxInt32, 3870 argLen: 1, 3871 resultInArg0: true, 3872 clobberFlags: true, 3873 asm: x86.ASARL, 3874 reg: regInfo{ 3875 inputs: []inputInfo{ 3876 {0, 239}, // AX CX DX BX BP SI DI 3877 }, 3878 outputs: []outputInfo{ 3879 {0, 239}, // AX CX DX BX BP SI DI 3880 }, 3881 }, 3882 }, 3883 { 3884 name: "SARWconst", 3885 auxType: auxInt16, 3886 argLen: 1, 3887 resultInArg0: true, 3888 clobberFlags: true, 3889 asm: x86.ASARW, 3890 reg: regInfo{ 3891 inputs: []inputInfo{ 3892 {0, 239}, // AX CX DX BX BP SI DI 3893 }, 3894 outputs: []outputInfo{ 3895 {0, 239}, // AX CX DX BX BP SI DI 3896 }, 3897 }, 3898 }, 3899 { 3900 name: "SARBconst", 3901 auxType: auxInt8, 3902 argLen: 1, 3903 resultInArg0: true, 3904 clobberFlags: true, 3905 asm: x86.ASARB, 3906 reg: regInfo{ 3907 inputs: []inputInfo{ 3908 {0, 239}, // AX CX DX BX BP SI DI 3909 }, 3910 outputs: []outputInfo{ 3911 {0, 239}, // AX CX DX BX BP SI DI 3912 }, 3913 }, 3914 }, 3915 { 3916 name: "ROLLconst", 3917 auxType: auxInt32, 3918 argLen: 1, 3919 resultInArg0: true, 3920 clobberFlags: true, 3921 asm: x86.AROLL, 3922 reg: regInfo{ 3923 inputs: []inputInfo{ 3924 {0, 239}, // AX CX DX BX BP SI DI 3925 }, 3926 outputs: []outputInfo{ 3927 {0, 239}, // AX CX DX BX BP SI DI 3928 }, 3929 }, 3930 }, 3931 { 3932 name: "ROLWconst", 3933 auxType: auxInt16, 3934 argLen: 1, 3935 resultInArg0: true, 3936 clobberFlags: true, 3937 asm: x86.AROLW, 3938 reg: regInfo{ 3939 inputs: []inputInfo{ 3940 {0, 239}, // AX CX DX BX BP SI DI 3941 }, 3942 outputs: []outputInfo{ 3943 {0, 239}, // AX CX DX BX BP SI DI 3944 }, 3945 }, 3946 }, 3947 { 3948 name: "ROLBconst", 3949 auxType: auxInt8, 3950 argLen: 1, 3951 resultInArg0: true, 3952 clobberFlags: true, 3953 asm: x86.AROLB, 3954 reg: regInfo{ 3955 inputs: []inputInfo{ 3956 {0, 239}, // AX CX DX BX BP SI DI 3957 }, 3958 outputs: []outputInfo{ 3959 {0, 239}, // AX CX DX BX BP SI DI 3960 }, 3961 }, 3962 }, 3963 { 3964 name: "ADDLload", 3965 auxType: auxSymOff, 3966 argLen: 3, 3967 resultInArg0: true, 3968 clobberFlags: true, 3969 faultOnNilArg1: true, 3970 symEffect: SymRead, 3971 asm: x86.AADDL, 3972 reg: regInfo{ 3973 inputs: []inputInfo{ 3974 {0, 239}, // AX CX DX BX BP SI DI 3975 {1, 65791}, // AX CX DX BX SP BP SI DI SB 3976 }, 3977 outputs: []outputInfo{ 3978 {0, 239}, // AX CX DX BX BP SI DI 3979 }, 3980 }, 3981 }, 3982 { 3983 name: "SUBLload", 3984 auxType: auxSymOff, 3985 argLen: 3, 3986 resultInArg0: true, 3987 clobberFlags: true, 3988 faultOnNilArg1: true, 3989 symEffect: SymRead, 3990 asm: x86.ASUBL, 3991 reg: regInfo{ 3992 inputs: []inputInfo{ 3993 {0, 239}, // AX CX DX BX BP SI DI 3994 {1, 65791}, // AX CX DX BX SP BP SI DI SB 3995 }, 3996 outputs: []outputInfo{ 3997 {0, 239}, // AX CX DX BX BP SI DI 3998 }, 3999 }, 4000 }, 4001 { 4002 name: "MULLload", 4003 auxType: auxSymOff, 4004 argLen: 3, 4005 resultInArg0: true, 4006 clobberFlags: true, 4007 faultOnNilArg1: true, 4008 symEffect: SymRead, 4009 asm: x86.AIMULL, 4010 reg: regInfo{ 4011 inputs: []inputInfo{ 4012 {0, 239}, // AX CX DX BX BP SI DI 4013 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4014 }, 4015 outputs: []outputInfo{ 4016 {0, 239}, // AX CX DX BX BP SI DI 4017 }, 4018 }, 4019 }, 4020 { 4021 name: "ANDLload", 4022 auxType: auxSymOff, 4023 argLen: 3, 4024 resultInArg0: true, 4025 clobberFlags: true, 4026 faultOnNilArg1: true, 4027 symEffect: SymRead, 4028 asm: x86.AANDL, 4029 reg: regInfo{ 4030 inputs: []inputInfo{ 4031 {0, 239}, // AX CX DX BX BP SI DI 4032 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4033 }, 4034 outputs: []outputInfo{ 4035 {0, 239}, // AX CX DX BX BP SI DI 4036 }, 4037 }, 4038 }, 4039 { 4040 name: "ORLload", 4041 auxType: auxSymOff, 4042 argLen: 3, 4043 resultInArg0: true, 4044 clobberFlags: true, 4045 faultOnNilArg1: true, 4046 symEffect: SymRead, 4047 asm: x86.AORL, 4048 reg: regInfo{ 4049 inputs: []inputInfo{ 4050 {0, 239}, // AX CX DX BX BP SI DI 4051 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4052 }, 4053 outputs: []outputInfo{ 4054 {0, 239}, // AX CX DX BX BP SI DI 4055 }, 4056 }, 4057 }, 4058 { 4059 name: "XORLload", 4060 auxType: auxSymOff, 4061 argLen: 3, 4062 resultInArg0: true, 4063 clobberFlags: true, 4064 faultOnNilArg1: true, 4065 symEffect: SymRead, 4066 asm: x86.AXORL, 4067 reg: regInfo{ 4068 inputs: []inputInfo{ 4069 {0, 239}, // AX CX DX BX BP SI DI 4070 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4071 }, 4072 outputs: []outputInfo{ 4073 {0, 239}, // AX CX DX BX BP SI DI 4074 }, 4075 }, 4076 }, 4077 { 4078 name: "ADDLloadidx4", 4079 auxType: auxSymOff, 4080 argLen: 4, 4081 resultInArg0: true, 4082 clobberFlags: true, 4083 faultOnNilArg1: true, 4084 symEffect: SymRead, 4085 asm: x86.AADDL, 4086 reg: regInfo{ 4087 inputs: []inputInfo{ 4088 {0, 239}, // AX CX DX BX BP SI DI 4089 {2, 255}, // AX CX DX BX SP BP SI DI 4090 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4091 }, 4092 outputs: []outputInfo{ 4093 {0, 239}, // AX CX DX BX BP SI DI 4094 }, 4095 }, 4096 }, 4097 { 4098 name: "SUBLloadidx4", 4099 auxType: auxSymOff, 4100 argLen: 4, 4101 resultInArg0: true, 4102 clobberFlags: true, 4103 faultOnNilArg1: true, 4104 symEffect: SymRead, 4105 asm: x86.ASUBL, 4106 reg: regInfo{ 4107 inputs: []inputInfo{ 4108 {0, 239}, // AX CX DX BX BP SI DI 4109 {2, 255}, // AX CX DX BX SP BP SI DI 4110 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4111 }, 4112 outputs: []outputInfo{ 4113 {0, 239}, // AX CX DX BX BP SI DI 4114 }, 4115 }, 4116 }, 4117 { 4118 name: "MULLloadidx4", 4119 auxType: auxSymOff, 4120 argLen: 4, 4121 resultInArg0: true, 4122 clobberFlags: true, 4123 faultOnNilArg1: true, 4124 symEffect: SymRead, 4125 asm: x86.AIMULL, 4126 reg: regInfo{ 4127 inputs: []inputInfo{ 4128 {0, 239}, // AX CX DX BX BP SI DI 4129 {2, 255}, // AX CX DX BX SP BP SI DI 4130 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4131 }, 4132 outputs: []outputInfo{ 4133 {0, 239}, // AX CX DX BX BP SI DI 4134 }, 4135 }, 4136 }, 4137 { 4138 name: "ANDLloadidx4", 4139 auxType: auxSymOff, 4140 argLen: 4, 4141 resultInArg0: true, 4142 clobberFlags: true, 4143 faultOnNilArg1: true, 4144 symEffect: SymRead, 4145 asm: x86.AANDL, 4146 reg: regInfo{ 4147 inputs: []inputInfo{ 4148 {0, 239}, // AX CX DX BX BP SI DI 4149 {2, 255}, // AX CX DX BX SP BP SI DI 4150 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4151 }, 4152 outputs: []outputInfo{ 4153 {0, 239}, // AX CX DX BX BP SI DI 4154 }, 4155 }, 4156 }, 4157 { 4158 name: "ORLloadidx4", 4159 auxType: auxSymOff, 4160 argLen: 4, 4161 resultInArg0: true, 4162 clobberFlags: true, 4163 faultOnNilArg1: true, 4164 symEffect: SymRead, 4165 asm: x86.AORL, 4166 reg: regInfo{ 4167 inputs: []inputInfo{ 4168 {0, 239}, // AX CX DX BX BP SI DI 4169 {2, 255}, // AX CX DX BX SP BP SI DI 4170 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4171 }, 4172 outputs: []outputInfo{ 4173 {0, 239}, // AX CX DX BX BP SI DI 4174 }, 4175 }, 4176 }, 4177 { 4178 name: "XORLloadidx4", 4179 auxType: auxSymOff, 4180 argLen: 4, 4181 resultInArg0: true, 4182 clobberFlags: true, 4183 faultOnNilArg1: true, 4184 symEffect: SymRead, 4185 asm: x86.AXORL, 4186 reg: regInfo{ 4187 inputs: []inputInfo{ 4188 {0, 239}, // AX CX DX BX BP SI DI 4189 {2, 255}, // AX CX DX BX SP BP SI DI 4190 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4191 }, 4192 outputs: []outputInfo{ 4193 {0, 239}, // AX CX DX BX BP SI DI 4194 }, 4195 }, 4196 }, 4197 { 4198 name: "NEGL", 4199 argLen: 1, 4200 resultInArg0: true, 4201 clobberFlags: true, 4202 asm: x86.ANEGL, 4203 reg: regInfo{ 4204 inputs: []inputInfo{ 4205 {0, 239}, // AX CX DX BX BP SI DI 4206 }, 4207 outputs: []outputInfo{ 4208 {0, 239}, // AX CX DX BX BP SI DI 4209 }, 4210 }, 4211 }, 4212 { 4213 name: "NOTL", 4214 argLen: 1, 4215 resultInArg0: true, 4216 clobberFlags: true, 4217 asm: x86.ANOTL, 4218 reg: regInfo{ 4219 inputs: []inputInfo{ 4220 {0, 239}, // AX CX DX BX BP SI DI 4221 }, 4222 outputs: []outputInfo{ 4223 {0, 239}, // AX CX DX BX BP SI DI 4224 }, 4225 }, 4226 }, 4227 { 4228 name: "BSFL", 4229 argLen: 1, 4230 clobberFlags: true, 4231 asm: x86.ABSFL, 4232 reg: regInfo{ 4233 inputs: []inputInfo{ 4234 {0, 239}, // AX CX DX BX BP SI DI 4235 }, 4236 outputs: []outputInfo{ 4237 {0, 239}, // AX CX DX BX BP SI DI 4238 }, 4239 }, 4240 }, 4241 { 4242 name: "BSFW", 4243 argLen: 1, 4244 clobberFlags: true, 4245 asm: x86.ABSFW, 4246 reg: regInfo{ 4247 inputs: []inputInfo{ 4248 {0, 239}, // AX CX DX BX BP SI DI 4249 }, 4250 outputs: []outputInfo{ 4251 {0, 239}, // AX CX DX BX BP SI DI 4252 }, 4253 }, 4254 }, 4255 { 4256 name: "BSRL", 4257 argLen: 1, 4258 clobberFlags: true, 4259 asm: x86.ABSRL, 4260 reg: regInfo{ 4261 inputs: []inputInfo{ 4262 {0, 239}, // AX CX DX BX BP SI DI 4263 }, 4264 outputs: []outputInfo{ 4265 {0, 239}, // AX CX DX BX BP SI DI 4266 }, 4267 }, 4268 }, 4269 { 4270 name: "BSRW", 4271 argLen: 1, 4272 clobberFlags: true, 4273 asm: x86.ABSRW, 4274 reg: regInfo{ 4275 inputs: []inputInfo{ 4276 {0, 239}, // AX CX DX BX BP SI DI 4277 }, 4278 outputs: []outputInfo{ 4279 {0, 239}, // AX CX DX BX BP SI DI 4280 }, 4281 }, 4282 }, 4283 { 4284 name: "BSWAPL", 4285 argLen: 1, 4286 resultInArg0: true, 4287 clobberFlags: true, 4288 asm: x86.ABSWAPL, 4289 reg: regInfo{ 4290 inputs: []inputInfo{ 4291 {0, 239}, // AX CX DX BX BP SI DI 4292 }, 4293 outputs: []outputInfo{ 4294 {0, 239}, // AX CX DX BX BP SI DI 4295 }, 4296 }, 4297 }, 4298 { 4299 name: "SQRTSD", 4300 argLen: 1, 4301 asm: x86.ASQRTSD, 4302 reg: regInfo{ 4303 inputs: []inputInfo{ 4304 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4305 }, 4306 outputs: []outputInfo{ 4307 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4308 }, 4309 }, 4310 }, 4311 { 4312 name: "SBBLcarrymask", 4313 argLen: 1, 4314 asm: x86.ASBBL, 4315 reg: regInfo{ 4316 outputs: []outputInfo{ 4317 {0, 239}, // AX CX DX BX BP SI DI 4318 }, 4319 }, 4320 }, 4321 { 4322 name: "SETEQ", 4323 argLen: 1, 4324 asm: x86.ASETEQ, 4325 reg: regInfo{ 4326 outputs: []outputInfo{ 4327 {0, 239}, // AX CX DX BX BP SI DI 4328 }, 4329 }, 4330 }, 4331 { 4332 name: "SETNE", 4333 argLen: 1, 4334 asm: x86.ASETNE, 4335 reg: regInfo{ 4336 outputs: []outputInfo{ 4337 {0, 239}, // AX CX DX BX BP SI DI 4338 }, 4339 }, 4340 }, 4341 { 4342 name: "SETL", 4343 argLen: 1, 4344 asm: x86.ASETLT, 4345 reg: regInfo{ 4346 outputs: []outputInfo{ 4347 {0, 239}, // AX CX DX BX BP SI DI 4348 }, 4349 }, 4350 }, 4351 { 4352 name: "SETLE", 4353 argLen: 1, 4354 asm: x86.ASETLE, 4355 reg: regInfo{ 4356 outputs: []outputInfo{ 4357 {0, 239}, // AX CX DX BX BP SI DI 4358 }, 4359 }, 4360 }, 4361 { 4362 name: "SETG", 4363 argLen: 1, 4364 asm: x86.ASETGT, 4365 reg: regInfo{ 4366 outputs: []outputInfo{ 4367 {0, 239}, // AX CX DX BX BP SI DI 4368 }, 4369 }, 4370 }, 4371 { 4372 name: "SETGE", 4373 argLen: 1, 4374 asm: x86.ASETGE, 4375 reg: regInfo{ 4376 outputs: []outputInfo{ 4377 {0, 239}, // AX CX DX BX BP SI DI 4378 }, 4379 }, 4380 }, 4381 { 4382 name: "SETB", 4383 argLen: 1, 4384 asm: x86.ASETCS, 4385 reg: regInfo{ 4386 outputs: []outputInfo{ 4387 {0, 239}, // AX CX DX BX BP SI DI 4388 }, 4389 }, 4390 }, 4391 { 4392 name: "SETBE", 4393 argLen: 1, 4394 asm: x86.ASETLS, 4395 reg: regInfo{ 4396 outputs: []outputInfo{ 4397 {0, 239}, // AX CX DX BX BP SI DI 4398 }, 4399 }, 4400 }, 4401 { 4402 name: "SETA", 4403 argLen: 1, 4404 asm: x86.ASETHI, 4405 reg: regInfo{ 4406 outputs: []outputInfo{ 4407 {0, 239}, // AX CX DX BX BP SI DI 4408 }, 4409 }, 4410 }, 4411 { 4412 name: "SETAE", 4413 argLen: 1, 4414 asm: x86.ASETCC, 4415 reg: regInfo{ 4416 outputs: []outputInfo{ 4417 {0, 239}, // AX CX DX BX BP SI DI 4418 }, 4419 }, 4420 }, 4421 { 4422 name: "SETO", 4423 argLen: 1, 4424 asm: x86.ASETOS, 4425 reg: regInfo{ 4426 outputs: []outputInfo{ 4427 {0, 239}, // AX CX DX BX BP SI DI 4428 }, 4429 }, 4430 }, 4431 { 4432 name: "SETEQF", 4433 argLen: 1, 4434 clobberFlags: true, 4435 asm: x86.ASETEQ, 4436 reg: regInfo{ 4437 clobbers: 1, // AX 4438 outputs: []outputInfo{ 4439 {0, 238}, // CX DX BX BP SI DI 4440 }, 4441 }, 4442 }, 4443 { 4444 name: "SETNEF", 4445 argLen: 1, 4446 clobberFlags: true, 4447 asm: x86.ASETNE, 4448 reg: regInfo{ 4449 clobbers: 1, // AX 4450 outputs: []outputInfo{ 4451 {0, 238}, // CX DX BX BP SI DI 4452 }, 4453 }, 4454 }, 4455 { 4456 name: "SETORD", 4457 argLen: 1, 4458 asm: x86.ASETPC, 4459 reg: regInfo{ 4460 outputs: []outputInfo{ 4461 {0, 239}, // AX CX DX BX BP SI DI 4462 }, 4463 }, 4464 }, 4465 { 4466 name: "SETNAN", 4467 argLen: 1, 4468 asm: x86.ASETPS, 4469 reg: regInfo{ 4470 outputs: []outputInfo{ 4471 {0, 239}, // AX CX DX BX BP SI DI 4472 }, 4473 }, 4474 }, 4475 { 4476 name: "SETGF", 4477 argLen: 1, 4478 asm: x86.ASETHI, 4479 reg: regInfo{ 4480 outputs: []outputInfo{ 4481 {0, 239}, // AX CX DX BX BP SI DI 4482 }, 4483 }, 4484 }, 4485 { 4486 name: "SETGEF", 4487 argLen: 1, 4488 asm: x86.ASETCC, 4489 reg: regInfo{ 4490 outputs: []outputInfo{ 4491 {0, 239}, // AX CX DX BX BP SI DI 4492 }, 4493 }, 4494 }, 4495 { 4496 name: "MOVBLSX", 4497 argLen: 1, 4498 asm: x86.AMOVBLSX, 4499 reg: regInfo{ 4500 inputs: []inputInfo{ 4501 {0, 239}, // AX CX DX BX BP SI DI 4502 }, 4503 outputs: []outputInfo{ 4504 {0, 239}, // AX CX DX BX BP SI DI 4505 }, 4506 }, 4507 }, 4508 { 4509 name: "MOVBLZX", 4510 argLen: 1, 4511 asm: x86.AMOVBLZX, 4512 reg: regInfo{ 4513 inputs: []inputInfo{ 4514 {0, 239}, // AX CX DX BX BP SI DI 4515 }, 4516 outputs: []outputInfo{ 4517 {0, 239}, // AX CX DX BX BP SI DI 4518 }, 4519 }, 4520 }, 4521 { 4522 name: "MOVWLSX", 4523 argLen: 1, 4524 asm: x86.AMOVWLSX, 4525 reg: regInfo{ 4526 inputs: []inputInfo{ 4527 {0, 239}, // AX CX DX BX BP SI DI 4528 }, 4529 outputs: []outputInfo{ 4530 {0, 239}, // AX CX DX BX BP SI DI 4531 }, 4532 }, 4533 }, 4534 { 4535 name: "MOVWLZX", 4536 argLen: 1, 4537 asm: x86.AMOVWLZX, 4538 reg: regInfo{ 4539 inputs: []inputInfo{ 4540 {0, 239}, // AX CX DX BX BP SI DI 4541 }, 4542 outputs: []outputInfo{ 4543 {0, 239}, // AX CX DX BX BP SI DI 4544 }, 4545 }, 4546 }, 4547 { 4548 name: "MOVLconst", 4549 auxType: auxInt32, 4550 argLen: 0, 4551 rematerializeable: true, 4552 asm: x86.AMOVL, 4553 reg: regInfo{ 4554 outputs: []outputInfo{ 4555 {0, 239}, // AX CX DX BX BP SI DI 4556 }, 4557 }, 4558 }, 4559 { 4560 name: "CVTTSD2SL", 4561 argLen: 1, 4562 usesScratch: true, 4563 asm: x86.ACVTTSD2SL, 4564 reg: regInfo{ 4565 inputs: []inputInfo{ 4566 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4567 }, 4568 outputs: []outputInfo{ 4569 {0, 239}, // AX CX DX BX BP SI DI 4570 }, 4571 }, 4572 }, 4573 { 4574 name: "CVTTSS2SL", 4575 argLen: 1, 4576 usesScratch: true, 4577 asm: x86.ACVTTSS2SL, 4578 reg: regInfo{ 4579 inputs: []inputInfo{ 4580 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4581 }, 4582 outputs: []outputInfo{ 4583 {0, 239}, // AX CX DX BX BP SI DI 4584 }, 4585 }, 4586 }, 4587 { 4588 name: "CVTSL2SS", 4589 argLen: 1, 4590 usesScratch: true, 4591 asm: x86.ACVTSL2SS, 4592 reg: regInfo{ 4593 inputs: []inputInfo{ 4594 {0, 239}, // AX CX DX BX BP SI DI 4595 }, 4596 outputs: []outputInfo{ 4597 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4598 }, 4599 }, 4600 }, 4601 { 4602 name: "CVTSL2SD", 4603 argLen: 1, 4604 usesScratch: true, 4605 asm: x86.ACVTSL2SD, 4606 reg: regInfo{ 4607 inputs: []inputInfo{ 4608 {0, 239}, // AX CX DX BX BP SI DI 4609 }, 4610 outputs: []outputInfo{ 4611 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4612 }, 4613 }, 4614 }, 4615 { 4616 name: "CVTSD2SS", 4617 argLen: 1, 4618 usesScratch: true, 4619 asm: x86.ACVTSD2SS, 4620 reg: regInfo{ 4621 inputs: []inputInfo{ 4622 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4623 }, 4624 outputs: []outputInfo{ 4625 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4626 }, 4627 }, 4628 }, 4629 { 4630 name: "CVTSS2SD", 4631 argLen: 1, 4632 asm: x86.ACVTSS2SD, 4633 reg: regInfo{ 4634 inputs: []inputInfo{ 4635 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4636 }, 4637 outputs: []outputInfo{ 4638 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4639 }, 4640 }, 4641 }, 4642 { 4643 name: "PXOR", 4644 argLen: 2, 4645 commutative: true, 4646 resultInArg0: true, 4647 asm: x86.APXOR, 4648 reg: regInfo{ 4649 inputs: []inputInfo{ 4650 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4651 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4652 }, 4653 outputs: []outputInfo{ 4654 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4655 }, 4656 }, 4657 }, 4658 { 4659 name: "LEAL", 4660 auxType: auxSymOff, 4661 argLen: 1, 4662 rematerializeable: true, 4663 symEffect: SymAddr, 4664 reg: regInfo{ 4665 inputs: []inputInfo{ 4666 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4667 }, 4668 outputs: []outputInfo{ 4669 {0, 239}, // AX CX DX BX BP SI DI 4670 }, 4671 }, 4672 }, 4673 { 4674 name: "LEAL1", 4675 auxType: auxSymOff, 4676 argLen: 2, 4677 commutative: true, 4678 symEffect: SymAddr, 4679 reg: regInfo{ 4680 inputs: []inputInfo{ 4681 {1, 255}, // AX CX DX BX SP BP SI DI 4682 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4683 }, 4684 outputs: []outputInfo{ 4685 {0, 239}, // AX CX DX BX BP SI DI 4686 }, 4687 }, 4688 }, 4689 { 4690 name: "LEAL2", 4691 auxType: auxSymOff, 4692 argLen: 2, 4693 symEffect: SymAddr, 4694 reg: regInfo{ 4695 inputs: []inputInfo{ 4696 {1, 255}, // AX CX DX BX SP BP SI DI 4697 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4698 }, 4699 outputs: []outputInfo{ 4700 {0, 239}, // AX CX DX BX BP SI DI 4701 }, 4702 }, 4703 }, 4704 { 4705 name: "LEAL4", 4706 auxType: auxSymOff, 4707 argLen: 2, 4708 symEffect: SymAddr, 4709 reg: regInfo{ 4710 inputs: []inputInfo{ 4711 {1, 255}, // AX CX DX BX SP BP SI DI 4712 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4713 }, 4714 outputs: []outputInfo{ 4715 {0, 239}, // AX CX DX BX BP SI DI 4716 }, 4717 }, 4718 }, 4719 { 4720 name: "LEAL8", 4721 auxType: auxSymOff, 4722 argLen: 2, 4723 symEffect: SymAddr, 4724 reg: regInfo{ 4725 inputs: []inputInfo{ 4726 {1, 255}, // AX CX DX BX SP BP SI DI 4727 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4728 }, 4729 outputs: []outputInfo{ 4730 {0, 239}, // AX CX DX BX BP SI DI 4731 }, 4732 }, 4733 }, 4734 { 4735 name: "MOVBload", 4736 auxType: auxSymOff, 4737 argLen: 2, 4738 faultOnNilArg0: true, 4739 symEffect: SymRead, 4740 asm: x86.AMOVBLZX, 4741 reg: regInfo{ 4742 inputs: []inputInfo{ 4743 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4744 }, 4745 outputs: []outputInfo{ 4746 {0, 239}, // AX CX DX BX BP SI DI 4747 }, 4748 }, 4749 }, 4750 { 4751 name: "MOVBLSXload", 4752 auxType: auxSymOff, 4753 argLen: 2, 4754 faultOnNilArg0: true, 4755 symEffect: SymRead, 4756 asm: x86.AMOVBLSX, 4757 reg: regInfo{ 4758 inputs: []inputInfo{ 4759 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4760 }, 4761 outputs: []outputInfo{ 4762 {0, 239}, // AX CX DX BX BP SI DI 4763 }, 4764 }, 4765 }, 4766 { 4767 name: "MOVWload", 4768 auxType: auxSymOff, 4769 argLen: 2, 4770 faultOnNilArg0: true, 4771 symEffect: SymRead, 4772 asm: x86.AMOVWLZX, 4773 reg: regInfo{ 4774 inputs: []inputInfo{ 4775 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4776 }, 4777 outputs: []outputInfo{ 4778 {0, 239}, // AX CX DX BX BP SI DI 4779 }, 4780 }, 4781 }, 4782 { 4783 name: "MOVWLSXload", 4784 auxType: auxSymOff, 4785 argLen: 2, 4786 faultOnNilArg0: true, 4787 symEffect: SymRead, 4788 asm: x86.AMOVWLSX, 4789 reg: regInfo{ 4790 inputs: []inputInfo{ 4791 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4792 }, 4793 outputs: []outputInfo{ 4794 {0, 239}, // AX CX DX BX BP SI DI 4795 }, 4796 }, 4797 }, 4798 { 4799 name: "MOVLload", 4800 auxType: auxSymOff, 4801 argLen: 2, 4802 faultOnNilArg0: true, 4803 symEffect: SymRead, 4804 asm: x86.AMOVL, 4805 reg: regInfo{ 4806 inputs: []inputInfo{ 4807 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4808 }, 4809 outputs: []outputInfo{ 4810 {0, 239}, // AX CX DX BX BP SI DI 4811 }, 4812 }, 4813 }, 4814 { 4815 name: "MOVBstore", 4816 auxType: auxSymOff, 4817 argLen: 3, 4818 faultOnNilArg0: true, 4819 symEffect: SymWrite, 4820 asm: x86.AMOVB, 4821 reg: regInfo{ 4822 inputs: []inputInfo{ 4823 {1, 255}, // AX CX DX BX SP BP SI DI 4824 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4825 }, 4826 }, 4827 }, 4828 { 4829 name: "MOVWstore", 4830 auxType: auxSymOff, 4831 argLen: 3, 4832 faultOnNilArg0: true, 4833 symEffect: SymWrite, 4834 asm: x86.AMOVW, 4835 reg: regInfo{ 4836 inputs: []inputInfo{ 4837 {1, 255}, // AX CX DX BX SP BP SI DI 4838 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4839 }, 4840 }, 4841 }, 4842 { 4843 name: "MOVLstore", 4844 auxType: auxSymOff, 4845 argLen: 3, 4846 faultOnNilArg0: true, 4847 symEffect: SymWrite, 4848 asm: x86.AMOVL, 4849 reg: regInfo{ 4850 inputs: []inputInfo{ 4851 {1, 255}, // AX CX DX BX SP BP SI DI 4852 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4853 }, 4854 }, 4855 }, 4856 { 4857 name: "ADDLmodify", 4858 auxType: auxSymOff, 4859 argLen: 3, 4860 clobberFlags: true, 4861 faultOnNilArg0: true, 4862 symEffect: SymRead | SymWrite, 4863 asm: x86.AADDL, 4864 reg: regInfo{ 4865 inputs: []inputInfo{ 4866 {1, 255}, // AX CX DX BX SP BP SI DI 4867 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4868 }, 4869 }, 4870 }, 4871 { 4872 name: "SUBLmodify", 4873 auxType: auxSymOff, 4874 argLen: 3, 4875 clobberFlags: true, 4876 faultOnNilArg0: true, 4877 symEffect: SymRead | SymWrite, 4878 asm: x86.ASUBL, 4879 reg: regInfo{ 4880 inputs: []inputInfo{ 4881 {1, 255}, // AX CX DX BX SP BP SI DI 4882 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4883 }, 4884 }, 4885 }, 4886 { 4887 name: "ANDLmodify", 4888 auxType: auxSymOff, 4889 argLen: 3, 4890 clobberFlags: true, 4891 faultOnNilArg0: true, 4892 symEffect: SymRead | SymWrite, 4893 asm: x86.AANDL, 4894 reg: regInfo{ 4895 inputs: []inputInfo{ 4896 {1, 255}, // AX CX DX BX SP BP SI DI 4897 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4898 }, 4899 }, 4900 }, 4901 { 4902 name: "ORLmodify", 4903 auxType: auxSymOff, 4904 argLen: 3, 4905 clobberFlags: true, 4906 faultOnNilArg0: true, 4907 symEffect: SymRead | SymWrite, 4908 asm: x86.AORL, 4909 reg: regInfo{ 4910 inputs: []inputInfo{ 4911 {1, 255}, // AX CX DX BX SP BP SI DI 4912 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4913 }, 4914 }, 4915 }, 4916 { 4917 name: "XORLmodify", 4918 auxType: auxSymOff, 4919 argLen: 3, 4920 clobberFlags: true, 4921 faultOnNilArg0: true, 4922 symEffect: SymRead | SymWrite, 4923 asm: x86.AXORL, 4924 reg: regInfo{ 4925 inputs: []inputInfo{ 4926 {1, 255}, // AX CX DX BX SP BP SI DI 4927 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4928 }, 4929 }, 4930 }, 4931 { 4932 name: "ADDLmodifyidx4", 4933 auxType: auxSymOff, 4934 argLen: 4, 4935 clobberFlags: true, 4936 faultOnNilArg0: true, 4937 symEffect: SymRead | SymWrite, 4938 asm: x86.AADDL, 4939 reg: regInfo{ 4940 inputs: []inputInfo{ 4941 {1, 255}, // AX CX DX BX SP BP SI DI 4942 {2, 255}, // AX CX DX BX SP BP SI DI 4943 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4944 }, 4945 }, 4946 }, 4947 { 4948 name: "SUBLmodifyidx4", 4949 auxType: auxSymOff, 4950 argLen: 4, 4951 clobberFlags: true, 4952 faultOnNilArg0: true, 4953 symEffect: SymRead | SymWrite, 4954 asm: x86.ASUBL, 4955 reg: regInfo{ 4956 inputs: []inputInfo{ 4957 {1, 255}, // AX CX DX BX SP BP SI DI 4958 {2, 255}, // AX CX DX BX SP BP SI DI 4959 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4960 }, 4961 }, 4962 }, 4963 { 4964 name: "ANDLmodifyidx4", 4965 auxType: auxSymOff, 4966 argLen: 4, 4967 clobberFlags: true, 4968 faultOnNilArg0: true, 4969 symEffect: SymRead | SymWrite, 4970 asm: x86.AANDL, 4971 reg: regInfo{ 4972 inputs: []inputInfo{ 4973 {1, 255}, // AX CX DX BX SP BP SI DI 4974 {2, 255}, // AX CX DX BX SP BP SI DI 4975 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4976 }, 4977 }, 4978 }, 4979 { 4980 name: "ORLmodifyidx4", 4981 auxType: auxSymOff, 4982 argLen: 4, 4983 clobberFlags: true, 4984 faultOnNilArg0: true, 4985 symEffect: SymRead | SymWrite, 4986 asm: x86.AORL, 4987 reg: regInfo{ 4988 inputs: []inputInfo{ 4989 {1, 255}, // AX CX DX BX SP BP SI DI 4990 {2, 255}, // AX CX DX BX SP BP SI DI 4991 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4992 }, 4993 }, 4994 }, 4995 { 4996 name: "XORLmodifyidx4", 4997 auxType: auxSymOff, 4998 argLen: 4, 4999 clobberFlags: true, 5000 faultOnNilArg0: true, 5001 symEffect: SymRead | SymWrite, 5002 asm: x86.AXORL, 5003 reg: regInfo{ 5004 inputs: []inputInfo{ 5005 {1, 255}, // AX CX DX BX SP BP SI DI 5006 {2, 255}, // AX CX DX BX SP BP SI DI 5007 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5008 }, 5009 }, 5010 }, 5011 { 5012 name: "ADDLconstmodify", 5013 auxType: auxSymValAndOff, 5014 argLen: 2, 5015 clobberFlags: true, 5016 faultOnNilArg0: true, 5017 symEffect: SymRead | SymWrite, 5018 asm: x86.AADDL, 5019 reg: regInfo{ 5020 inputs: []inputInfo{ 5021 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5022 }, 5023 }, 5024 }, 5025 { 5026 name: "ANDLconstmodify", 5027 auxType: auxSymValAndOff, 5028 argLen: 2, 5029 clobberFlags: true, 5030 faultOnNilArg0: true, 5031 symEffect: SymRead | SymWrite, 5032 asm: x86.AANDL, 5033 reg: regInfo{ 5034 inputs: []inputInfo{ 5035 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5036 }, 5037 }, 5038 }, 5039 { 5040 name: "ORLconstmodify", 5041 auxType: auxSymValAndOff, 5042 argLen: 2, 5043 clobberFlags: true, 5044 faultOnNilArg0: true, 5045 symEffect: SymRead | SymWrite, 5046 asm: x86.AORL, 5047 reg: regInfo{ 5048 inputs: []inputInfo{ 5049 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5050 }, 5051 }, 5052 }, 5053 { 5054 name: "XORLconstmodify", 5055 auxType: auxSymValAndOff, 5056 argLen: 2, 5057 clobberFlags: true, 5058 faultOnNilArg0: true, 5059 symEffect: SymRead | SymWrite, 5060 asm: x86.AXORL, 5061 reg: regInfo{ 5062 inputs: []inputInfo{ 5063 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5064 }, 5065 }, 5066 }, 5067 { 5068 name: "ADDLconstmodifyidx4", 5069 auxType: auxSymValAndOff, 5070 argLen: 3, 5071 clobberFlags: true, 5072 faultOnNilArg0: true, 5073 symEffect: SymRead | SymWrite, 5074 asm: x86.AADDL, 5075 reg: regInfo{ 5076 inputs: []inputInfo{ 5077 {1, 255}, // AX CX DX BX SP BP SI DI 5078 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5079 }, 5080 }, 5081 }, 5082 { 5083 name: "ANDLconstmodifyidx4", 5084 auxType: auxSymValAndOff, 5085 argLen: 3, 5086 clobberFlags: true, 5087 faultOnNilArg0: true, 5088 symEffect: SymRead | SymWrite, 5089 asm: x86.AANDL, 5090 reg: regInfo{ 5091 inputs: []inputInfo{ 5092 {1, 255}, // AX CX DX BX SP BP SI DI 5093 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5094 }, 5095 }, 5096 }, 5097 { 5098 name: "ORLconstmodifyidx4", 5099 auxType: auxSymValAndOff, 5100 argLen: 3, 5101 clobberFlags: true, 5102 faultOnNilArg0: true, 5103 symEffect: SymRead | SymWrite, 5104 asm: x86.AORL, 5105 reg: regInfo{ 5106 inputs: []inputInfo{ 5107 {1, 255}, // AX CX DX BX SP BP SI DI 5108 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5109 }, 5110 }, 5111 }, 5112 { 5113 name: "XORLconstmodifyidx4", 5114 auxType: auxSymValAndOff, 5115 argLen: 3, 5116 clobberFlags: true, 5117 faultOnNilArg0: true, 5118 symEffect: SymRead | SymWrite, 5119 asm: x86.AXORL, 5120 reg: regInfo{ 5121 inputs: []inputInfo{ 5122 {1, 255}, // AX CX DX BX SP BP SI DI 5123 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5124 }, 5125 }, 5126 }, 5127 { 5128 name: "MOVBloadidx1", 5129 auxType: auxSymOff, 5130 argLen: 3, 5131 commutative: true, 5132 symEffect: SymRead, 5133 asm: x86.AMOVBLZX, 5134 reg: regInfo{ 5135 inputs: []inputInfo{ 5136 {1, 255}, // AX CX DX BX SP BP SI DI 5137 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5138 }, 5139 outputs: []outputInfo{ 5140 {0, 239}, // AX CX DX BX BP SI DI 5141 }, 5142 }, 5143 }, 5144 { 5145 name: "MOVWloadidx1", 5146 auxType: auxSymOff, 5147 argLen: 3, 5148 commutative: true, 5149 symEffect: SymRead, 5150 asm: x86.AMOVWLZX, 5151 reg: regInfo{ 5152 inputs: []inputInfo{ 5153 {1, 255}, // AX CX DX BX SP BP SI DI 5154 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5155 }, 5156 outputs: []outputInfo{ 5157 {0, 239}, // AX CX DX BX BP SI DI 5158 }, 5159 }, 5160 }, 5161 { 5162 name: "MOVWloadidx2", 5163 auxType: auxSymOff, 5164 argLen: 3, 5165 symEffect: SymRead, 5166 asm: x86.AMOVWLZX, 5167 reg: regInfo{ 5168 inputs: []inputInfo{ 5169 {1, 255}, // AX CX DX BX SP BP SI DI 5170 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5171 }, 5172 outputs: []outputInfo{ 5173 {0, 239}, // AX CX DX BX BP SI DI 5174 }, 5175 }, 5176 }, 5177 { 5178 name: "MOVLloadidx1", 5179 auxType: auxSymOff, 5180 argLen: 3, 5181 commutative: true, 5182 symEffect: SymRead, 5183 asm: x86.AMOVL, 5184 reg: regInfo{ 5185 inputs: []inputInfo{ 5186 {1, 255}, // AX CX DX BX SP BP SI DI 5187 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5188 }, 5189 outputs: []outputInfo{ 5190 {0, 239}, // AX CX DX BX BP SI DI 5191 }, 5192 }, 5193 }, 5194 { 5195 name: "MOVLloadidx4", 5196 auxType: auxSymOff, 5197 argLen: 3, 5198 symEffect: SymRead, 5199 asm: x86.AMOVL, 5200 reg: regInfo{ 5201 inputs: []inputInfo{ 5202 {1, 255}, // AX CX DX BX SP BP SI DI 5203 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5204 }, 5205 outputs: []outputInfo{ 5206 {0, 239}, // AX CX DX BX BP SI DI 5207 }, 5208 }, 5209 }, 5210 { 5211 name: "MOVBstoreidx1", 5212 auxType: auxSymOff, 5213 argLen: 4, 5214 commutative: true, 5215 symEffect: SymWrite, 5216 asm: x86.AMOVB, 5217 reg: regInfo{ 5218 inputs: []inputInfo{ 5219 {1, 255}, // AX CX DX BX SP BP SI DI 5220 {2, 255}, // AX CX DX BX SP BP SI DI 5221 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5222 }, 5223 }, 5224 }, 5225 { 5226 name: "MOVWstoreidx1", 5227 auxType: auxSymOff, 5228 argLen: 4, 5229 commutative: true, 5230 symEffect: SymWrite, 5231 asm: x86.AMOVW, 5232 reg: regInfo{ 5233 inputs: []inputInfo{ 5234 {1, 255}, // AX CX DX BX SP BP SI DI 5235 {2, 255}, // AX CX DX BX SP BP SI DI 5236 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5237 }, 5238 }, 5239 }, 5240 { 5241 name: "MOVWstoreidx2", 5242 auxType: auxSymOff, 5243 argLen: 4, 5244 symEffect: SymWrite, 5245 asm: x86.AMOVW, 5246 reg: regInfo{ 5247 inputs: []inputInfo{ 5248 {1, 255}, // AX CX DX BX SP BP SI DI 5249 {2, 255}, // AX CX DX BX SP BP SI DI 5250 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5251 }, 5252 }, 5253 }, 5254 { 5255 name: "MOVLstoreidx1", 5256 auxType: auxSymOff, 5257 argLen: 4, 5258 commutative: true, 5259 symEffect: SymWrite, 5260 asm: x86.AMOVL, 5261 reg: regInfo{ 5262 inputs: []inputInfo{ 5263 {1, 255}, // AX CX DX BX SP BP SI DI 5264 {2, 255}, // AX CX DX BX SP BP SI DI 5265 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5266 }, 5267 }, 5268 }, 5269 { 5270 name: "MOVLstoreidx4", 5271 auxType: auxSymOff, 5272 argLen: 4, 5273 symEffect: SymWrite, 5274 asm: x86.AMOVL, 5275 reg: regInfo{ 5276 inputs: []inputInfo{ 5277 {1, 255}, // AX CX DX BX SP BP SI DI 5278 {2, 255}, // AX CX DX BX SP BP SI DI 5279 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5280 }, 5281 }, 5282 }, 5283 { 5284 name: "MOVBstoreconst", 5285 auxType: auxSymValAndOff, 5286 argLen: 2, 5287 faultOnNilArg0: true, 5288 symEffect: SymWrite, 5289 asm: x86.AMOVB, 5290 reg: regInfo{ 5291 inputs: []inputInfo{ 5292 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5293 }, 5294 }, 5295 }, 5296 { 5297 name: "MOVWstoreconst", 5298 auxType: auxSymValAndOff, 5299 argLen: 2, 5300 faultOnNilArg0: true, 5301 symEffect: SymWrite, 5302 asm: x86.AMOVW, 5303 reg: regInfo{ 5304 inputs: []inputInfo{ 5305 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5306 }, 5307 }, 5308 }, 5309 { 5310 name: "MOVLstoreconst", 5311 auxType: auxSymValAndOff, 5312 argLen: 2, 5313 faultOnNilArg0: true, 5314 symEffect: SymWrite, 5315 asm: x86.AMOVL, 5316 reg: regInfo{ 5317 inputs: []inputInfo{ 5318 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5319 }, 5320 }, 5321 }, 5322 { 5323 name: "MOVBstoreconstidx1", 5324 auxType: auxSymValAndOff, 5325 argLen: 3, 5326 symEffect: SymWrite, 5327 asm: x86.AMOVB, 5328 reg: regInfo{ 5329 inputs: []inputInfo{ 5330 {1, 255}, // AX CX DX BX SP BP SI DI 5331 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5332 }, 5333 }, 5334 }, 5335 { 5336 name: "MOVWstoreconstidx1", 5337 auxType: auxSymValAndOff, 5338 argLen: 3, 5339 symEffect: SymWrite, 5340 asm: x86.AMOVW, 5341 reg: regInfo{ 5342 inputs: []inputInfo{ 5343 {1, 255}, // AX CX DX BX SP BP SI DI 5344 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5345 }, 5346 }, 5347 }, 5348 { 5349 name: "MOVWstoreconstidx2", 5350 auxType: auxSymValAndOff, 5351 argLen: 3, 5352 symEffect: SymWrite, 5353 asm: x86.AMOVW, 5354 reg: regInfo{ 5355 inputs: []inputInfo{ 5356 {1, 255}, // AX CX DX BX SP BP SI DI 5357 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5358 }, 5359 }, 5360 }, 5361 { 5362 name: "MOVLstoreconstidx1", 5363 auxType: auxSymValAndOff, 5364 argLen: 3, 5365 symEffect: SymWrite, 5366 asm: x86.AMOVL, 5367 reg: regInfo{ 5368 inputs: []inputInfo{ 5369 {1, 255}, // AX CX DX BX SP BP SI DI 5370 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5371 }, 5372 }, 5373 }, 5374 { 5375 name: "MOVLstoreconstidx4", 5376 auxType: auxSymValAndOff, 5377 argLen: 3, 5378 symEffect: SymWrite, 5379 asm: x86.AMOVL, 5380 reg: regInfo{ 5381 inputs: []inputInfo{ 5382 {1, 255}, // AX CX DX BX SP BP SI DI 5383 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5384 }, 5385 }, 5386 }, 5387 { 5388 name: "DUFFZERO", 5389 auxType: auxInt64, 5390 argLen: 3, 5391 faultOnNilArg0: true, 5392 reg: regInfo{ 5393 inputs: []inputInfo{ 5394 {0, 128}, // DI 5395 {1, 1}, // AX 5396 }, 5397 clobbers: 130, // CX DI 5398 }, 5399 }, 5400 { 5401 name: "REPSTOSL", 5402 argLen: 4, 5403 faultOnNilArg0: true, 5404 reg: regInfo{ 5405 inputs: []inputInfo{ 5406 {0, 128}, // DI 5407 {1, 2}, // CX 5408 {2, 1}, // AX 5409 }, 5410 clobbers: 130, // CX DI 5411 }, 5412 }, 5413 { 5414 name: "CALLstatic", 5415 auxType: auxSymOff, 5416 argLen: 1, 5417 clobberFlags: true, 5418 call: true, 5419 symEffect: SymNone, 5420 reg: regInfo{ 5421 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 5422 }, 5423 }, 5424 { 5425 name: "CALLclosure", 5426 auxType: auxInt64, 5427 argLen: 3, 5428 clobberFlags: true, 5429 call: true, 5430 reg: regInfo{ 5431 inputs: []inputInfo{ 5432 {1, 4}, // DX 5433 {0, 255}, // AX CX DX BX SP BP SI DI 5434 }, 5435 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 5436 }, 5437 }, 5438 { 5439 name: "CALLinter", 5440 auxType: auxInt64, 5441 argLen: 2, 5442 clobberFlags: true, 5443 call: true, 5444 reg: regInfo{ 5445 inputs: []inputInfo{ 5446 {0, 239}, // AX CX DX BX BP SI DI 5447 }, 5448 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 5449 }, 5450 }, 5451 { 5452 name: "DUFFCOPY", 5453 auxType: auxInt64, 5454 argLen: 3, 5455 clobberFlags: true, 5456 faultOnNilArg0: true, 5457 faultOnNilArg1: true, 5458 reg: regInfo{ 5459 inputs: []inputInfo{ 5460 {0, 128}, // DI 5461 {1, 64}, // SI 5462 }, 5463 clobbers: 194, // CX SI DI 5464 }, 5465 }, 5466 { 5467 name: "REPMOVSL", 5468 argLen: 4, 5469 faultOnNilArg0: true, 5470 faultOnNilArg1: true, 5471 reg: regInfo{ 5472 inputs: []inputInfo{ 5473 {0, 128}, // DI 5474 {1, 64}, // SI 5475 {2, 2}, // CX 5476 }, 5477 clobbers: 194, // CX SI DI 5478 }, 5479 }, 5480 { 5481 name: "InvertFlags", 5482 argLen: 1, 5483 reg: regInfo{}, 5484 }, 5485 { 5486 name: "LoweredGetG", 5487 argLen: 1, 5488 reg: regInfo{ 5489 outputs: []outputInfo{ 5490 {0, 239}, // AX CX DX BX BP SI DI 5491 }, 5492 }, 5493 }, 5494 { 5495 name: "LoweredGetClosurePtr", 5496 argLen: 0, 5497 zeroWidth: true, 5498 reg: regInfo{ 5499 outputs: []outputInfo{ 5500 {0, 4}, // DX 5501 }, 5502 }, 5503 }, 5504 { 5505 name: "LoweredGetCallerPC", 5506 argLen: 0, 5507 rematerializeable: true, 5508 reg: regInfo{ 5509 outputs: []outputInfo{ 5510 {0, 239}, // AX CX DX BX BP SI DI 5511 }, 5512 }, 5513 }, 5514 { 5515 name: "LoweredGetCallerSP", 5516 argLen: 0, 5517 rematerializeable: true, 5518 reg: regInfo{ 5519 outputs: []outputInfo{ 5520 {0, 239}, // AX CX DX BX BP SI DI 5521 }, 5522 }, 5523 }, 5524 { 5525 name: "LoweredNilCheck", 5526 argLen: 2, 5527 clobberFlags: true, 5528 nilCheck: true, 5529 faultOnNilArg0: true, 5530 reg: regInfo{ 5531 inputs: []inputInfo{ 5532 {0, 255}, // AX CX DX BX SP BP SI DI 5533 }, 5534 }, 5535 }, 5536 { 5537 name: "LoweredWB", 5538 auxType: auxSym, 5539 argLen: 3, 5540 clobberFlags: true, 5541 symEffect: SymNone, 5542 reg: regInfo{ 5543 inputs: []inputInfo{ 5544 {0, 128}, // DI 5545 {1, 1}, // AX 5546 }, 5547 clobbers: 65280, // X0 X1 X2 X3 X4 X5 X6 X7 5548 }, 5549 }, 5550 { 5551 name: "FlagEQ", 5552 argLen: 0, 5553 reg: regInfo{}, 5554 }, 5555 { 5556 name: "FlagLT_ULT", 5557 argLen: 0, 5558 reg: regInfo{}, 5559 }, 5560 { 5561 name: "FlagLT_UGT", 5562 argLen: 0, 5563 reg: regInfo{}, 5564 }, 5565 { 5566 name: "FlagGT_UGT", 5567 argLen: 0, 5568 reg: regInfo{}, 5569 }, 5570 { 5571 name: "FlagGT_ULT", 5572 argLen: 0, 5573 reg: regInfo{}, 5574 }, 5575 { 5576 name: "FCHS", 5577 argLen: 1, 5578 reg: regInfo{ 5579 inputs: []inputInfo{ 5580 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5581 }, 5582 outputs: []outputInfo{ 5583 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5584 }, 5585 }, 5586 }, 5587 { 5588 name: "MOVSSconst1", 5589 auxType: auxFloat32, 5590 argLen: 0, 5591 reg: regInfo{ 5592 outputs: []outputInfo{ 5593 {0, 239}, // AX CX DX BX BP SI DI 5594 }, 5595 }, 5596 }, 5597 { 5598 name: "MOVSDconst1", 5599 auxType: auxFloat64, 5600 argLen: 0, 5601 reg: regInfo{ 5602 outputs: []outputInfo{ 5603 {0, 239}, // AX CX DX BX BP SI DI 5604 }, 5605 }, 5606 }, 5607 { 5608 name: "MOVSSconst2", 5609 argLen: 1, 5610 asm: x86.AMOVSS, 5611 reg: regInfo{ 5612 inputs: []inputInfo{ 5613 {0, 239}, // AX CX DX BX BP SI DI 5614 }, 5615 outputs: []outputInfo{ 5616 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5617 }, 5618 }, 5619 }, 5620 { 5621 name: "MOVSDconst2", 5622 argLen: 1, 5623 asm: x86.AMOVSD, 5624 reg: regInfo{ 5625 inputs: []inputInfo{ 5626 {0, 239}, // AX CX DX BX BP SI DI 5627 }, 5628 outputs: []outputInfo{ 5629 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5630 }, 5631 }, 5632 }, 5633 5634 { 5635 name: "ADDSS", 5636 argLen: 2, 5637 commutative: true, 5638 resultInArg0: true, 5639 asm: x86.AADDSS, 5640 reg: regInfo{ 5641 inputs: []inputInfo{ 5642 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5643 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5644 }, 5645 outputs: []outputInfo{ 5646 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5647 }, 5648 }, 5649 }, 5650 { 5651 name: "ADDSD", 5652 argLen: 2, 5653 commutative: true, 5654 resultInArg0: true, 5655 asm: x86.AADDSD, 5656 reg: regInfo{ 5657 inputs: []inputInfo{ 5658 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5659 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5660 }, 5661 outputs: []outputInfo{ 5662 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5663 }, 5664 }, 5665 }, 5666 { 5667 name: "SUBSS", 5668 argLen: 2, 5669 resultInArg0: true, 5670 asm: x86.ASUBSS, 5671 reg: regInfo{ 5672 inputs: []inputInfo{ 5673 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5674 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5675 }, 5676 outputs: []outputInfo{ 5677 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5678 }, 5679 }, 5680 }, 5681 { 5682 name: "SUBSD", 5683 argLen: 2, 5684 resultInArg0: true, 5685 asm: x86.ASUBSD, 5686 reg: regInfo{ 5687 inputs: []inputInfo{ 5688 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5689 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5690 }, 5691 outputs: []outputInfo{ 5692 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5693 }, 5694 }, 5695 }, 5696 { 5697 name: "MULSS", 5698 argLen: 2, 5699 commutative: true, 5700 resultInArg0: true, 5701 asm: x86.AMULSS, 5702 reg: regInfo{ 5703 inputs: []inputInfo{ 5704 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5705 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5706 }, 5707 outputs: []outputInfo{ 5708 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5709 }, 5710 }, 5711 }, 5712 { 5713 name: "MULSD", 5714 argLen: 2, 5715 commutative: true, 5716 resultInArg0: true, 5717 asm: x86.AMULSD, 5718 reg: regInfo{ 5719 inputs: []inputInfo{ 5720 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5721 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5722 }, 5723 outputs: []outputInfo{ 5724 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5725 }, 5726 }, 5727 }, 5728 { 5729 name: "DIVSS", 5730 argLen: 2, 5731 resultInArg0: true, 5732 asm: x86.ADIVSS, 5733 reg: regInfo{ 5734 inputs: []inputInfo{ 5735 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5736 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5737 }, 5738 outputs: []outputInfo{ 5739 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5740 }, 5741 }, 5742 }, 5743 { 5744 name: "DIVSD", 5745 argLen: 2, 5746 resultInArg0: true, 5747 asm: x86.ADIVSD, 5748 reg: regInfo{ 5749 inputs: []inputInfo{ 5750 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5751 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5752 }, 5753 outputs: []outputInfo{ 5754 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5755 }, 5756 }, 5757 }, 5758 { 5759 name: "MOVSSload", 5760 auxType: auxSymOff, 5761 argLen: 2, 5762 faultOnNilArg0: true, 5763 symEffect: SymRead, 5764 asm: x86.AMOVSS, 5765 reg: regInfo{ 5766 inputs: []inputInfo{ 5767 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5768 }, 5769 outputs: []outputInfo{ 5770 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5771 }, 5772 }, 5773 }, 5774 { 5775 name: "MOVSDload", 5776 auxType: auxSymOff, 5777 argLen: 2, 5778 faultOnNilArg0: true, 5779 symEffect: SymRead, 5780 asm: x86.AMOVSD, 5781 reg: regInfo{ 5782 inputs: []inputInfo{ 5783 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5784 }, 5785 outputs: []outputInfo{ 5786 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5787 }, 5788 }, 5789 }, 5790 { 5791 name: "MOVSSconst", 5792 auxType: auxFloat32, 5793 argLen: 0, 5794 rematerializeable: true, 5795 asm: x86.AMOVSS, 5796 reg: regInfo{ 5797 outputs: []outputInfo{ 5798 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5799 }, 5800 }, 5801 }, 5802 { 5803 name: "MOVSDconst", 5804 auxType: auxFloat64, 5805 argLen: 0, 5806 rematerializeable: true, 5807 asm: x86.AMOVSD, 5808 reg: regInfo{ 5809 outputs: []outputInfo{ 5810 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5811 }, 5812 }, 5813 }, 5814 { 5815 name: "MOVSSloadidx1", 5816 auxType: auxSymOff, 5817 argLen: 3, 5818 symEffect: SymRead, 5819 asm: x86.AMOVSS, 5820 reg: regInfo{ 5821 inputs: []inputInfo{ 5822 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5823 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5824 }, 5825 outputs: []outputInfo{ 5826 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5827 }, 5828 }, 5829 }, 5830 { 5831 name: "MOVSSloadidx4", 5832 auxType: auxSymOff, 5833 argLen: 3, 5834 symEffect: SymRead, 5835 asm: x86.AMOVSS, 5836 reg: regInfo{ 5837 inputs: []inputInfo{ 5838 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5839 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5840 }, 5841 outputs: []outputInfo{ 5842 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5843 }, 5844 }, 5845 }, 5846 { 5847 name: "MOVSDloadidx1", 5848 auxType: auxSymOff, 5849 argLen: 3, 5850 symEffect: SymRead, 5851 asm: x86.AMOVSD, 5852 reg: regInfo{ 5853 inputs: []inputInfo{ 5854 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5855 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5856 }, 5857 outputs: []outputInfo{ 5858 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5859 }, 5860 }, 5861 }, 5862 { 5863 name: "MOVSDloadidx8", 5864 auxType: auxSymOff, 5865 argLen: 3, 5866 symEffect: SymRead, 5867 asm: x86.AMOVSD, 5868 reg: regInfo{ 5869 inputs: []inputInfo{ 5870 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5871 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5872 }, 5873 outputs: []outputInfo{ 5874 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5875 }, 5876 }, 5877 }, 5878 { 5879 name: "MOVSSstore", 5880 auxType: auxSymOff, 5881 argLen: 3, 5882 faultOnNilArg0: true, 5883 symEffect: SymWrite, 5884 asm: x86.AMOVSS, 5885 reg: regInfo{ 5886 inputs: []inputInfo{ 5887 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5888 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5889 }, 5890 }, 5891 }, 5892 { 5893 name: "MOVSDstore", 5894 auxType: auxSymOff, 5895 argLen: 3, 5896 faultOnNilArg0: true, 5897 symEffect: SymWrite, 5898 asm: x86.AMOVSD, 5899 reg: regInfo{ 5900 inputs: []inputInfo{ 5901 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5902 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5903 }, 5904 }, 5905 }, 5906 { 5907 name: "MOVSSstoreidx1", 5908 auxType: auxSymOff, 5909 argLen: 4, 5910 symEffect: SymWrite, 5911 asm: x86.AMOVSS, 5912 reg: regInfo{ 5913 inputs: []inputInfo{ 5914 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5915 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5916 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5917 }, 5918 }, 5919 }, 5920 { 5921 name: "MOVSSstoreidx4", 5922 auxType: auxSymOff, 5923 argLen: 4, 5924 symEffect: SymWrite, 5925 asm: x86.AMOVSS, 5926 reg: regInfo{ 5927 inputs: []inputInfo{ 5928 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5929 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5930 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5931 }, 5932 }, 5933 }, 5934 { 5935 name: "MOVSDstoreidx1", 5936 auxType: auxSymOff, 5937 argLen: 4, 5938 symEffect: SymWrite, 5939 asm: x86.AMOVSD, 5940 reg: regInfo{ 5941 inputs: []inputInfo{ 5942 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5943 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5944 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5945 }, 5946 }, 5947 }, 5948 { 5949 name: "MOVSDstoreidx8", 5950 auxType: auxSymOff, 5951 argLen: 4, 5952 symEffect: SymWrite, 5953 asm: x86.AMOVSD, 5954 reg: regInfo{ 5955 inputs: []inputInfo{ 5956 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5957 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5958 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5959 }, 5960 }, 5961 }, 5962 { 5963 name: "ADDSSload", 5964 auxType: auxSymOff, 5965 argLen: 3, 5966 resultInArg0: true, 5967 faultOnNilArg1: true, 5968 symEffect: SymRead, 5969 asm: x86.AADDSS, 5970 reg: regInfo{ 5971 inputs: []inputInfo{ 5972 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5973 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5974 }, 5975 outputs: []outputInfo{ 5976 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5977 }, 5978 }, 5979 }, 5980 { 5981 name: "ADDSDload", 5982 auxType: auxSymOff, 5983 argLen: 3, 5984 resultInArg0: true, 5985 faultOnNilArg1: true, 5986 symEffect: SymRead, 5987 asm: x86.AADDSD, 5988 reg: regInfo{ 5989 inputs: []inputInfo{ 5990 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5991 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5992 }, 5993 outputs: []outputInfo{ 5994 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5995 }, 5996 }, 5997 }, 5998 { 5999 name: "SUBSSload", 6000 auxType: auxSymOff, 6001 argLen: 3, 6002 resultInArg0: true, 6003 faultOnNilArg1: true, 6004 symEffect: SymRead, 6005 asm: x86.ASUBSS, 6006 reg: regInfo{ 6007 inputs: []inputInfo{ 6008 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6009 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6010 }, 6011 outputs: []outputInfo{ 6012 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6013 }, 6014 }, 6015 }, 6016 { 6017 name: "SUBSDload", 6018 auxType: auxSymOff, 6019 argLen: 3, 6020 resultInArg0: true, 6021 faultOnNilArg1: true, 6022 symEffect: SymRead, 6023 asm: x86.ASUBSD, 6024 reg: regInfo{ 6025 inputs: []inputInfo{ 6026 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6027 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6028 }, 6029 outputs: []outputInfo{ 6030 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6031 }, 6032 }, 6033 }, 6034 { 6035 name: "MULSSload", 6036 auxType: auxSymOff, 6037 argLen: 3, 6038 resultInArg0: true, 6039 faultOnNilArg1: true, 6040 symEffect: SymRead, 6041 asm: x86.AMULSS, 6042 reg: regInfo{ 6043 inputs: []inputInfo{ 6044 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6045 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6046 }, 6047 outputs: []outputInfo{ 6048 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6049 }, 6050 }, 6051 }, 6052 { 6053 name: "MULSDload", 6054 auxType: auxSymOff, 6055 argLen: 3, 6056 resultInArg0: true, 6057 faultOnNilArg1: true, 6058 symEffect: SymRead, 6059 asm: x86.AMULSD, 6060 reg: regInfo{ 6061 inputs: []inputInfo{ 6062 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6063 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6064 }, 6065 outputs: []outputInfo{ 6066 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6067 }, 6068 }, 6069 }, 6070 { 6071 name: "DIVSSload", 6072 auxType: auxSymOff, 6073 argLen: 3, 6074 resultInArg0: true, 6075 faultOnNilArg1: true, 6076 symEffect: SymRead, 6077 asm: x86.ADIVSS, 6078 reg: regInfo{ 6079 inputs: []inputInfo{ 6080 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6081 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6082 }, 6083 outputs: []outputInfo{ 6084 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6085 }, 6086 }, 6087 }, 6088 { 6089 name: "DIVSDload", 6090 auxType: auxSymOff, 6091 argLen: 3, 6092 resultInArg0: true, 6093 faultOnNilArg1: true, 6094 symEffect: SymRead, 6095 asm: x86.ADIVSD, 6096 reg: regInfo{ 6097 inputs: []inputInfo{ 6098 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6099 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6100 }, 6101 outputs: []outputInfo{ 6102 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6103 }, 6104 }, 6105 }, 6106 { 6107 name: "ADDQ", 6108 argLen: 2, 6109 commutative: true, 6110 clobberFlags: true, 6111 asm: x86.AADDQ, 6112 reg: regInfo{ 6113 inputs: []inputInfo{ 6114 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6115 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6116 }, 6117 outputs: []outputInfo{ 6118 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6119 }, 6120 }, 6121 }, 6122 { 6123 name: "ADDL", 6124 argLen: 2, 6125 commutative: true, 6126 clobberFlags: true, 6127 asm: x86.AADDL, 6128 reg: regInfo{ 6129 inputs: []inputInfo{ 6130 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6131 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6132 }, 6133 outputs: []outputInfo{ 6134 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6135 }, 6136 }, 6137 }, 6138 { 6139 name: "ADDQconst", 6140 auxType: auxInt32, 6141 argLen: 1, 6142 clobberFlags: true, 6143 asm: x86.AADDQ, 6144 reg: regInfo{ 6145 inputs: []inputInfo{ 6146 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6147 }, 6148 outputs: []outputInfo{ 6149 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6150 }, 6151 }, 6152 }, 6153 { 6154 name: "ADDLconst", 6155 auxType: auxInt32, 6156 argLen: 1, 6157 clobberFlags: true, 6158 asm: x86.AADDL, 6159 reg: regInfo{ 6160 inputs: []inputInfo{ 6161 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6162 }, 6163 outputs: []outputInfo{ 6164 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6165 }, 6166 }, 6167 }, 6168 { 6169 name: "ADDQconstmodify", 6170 auxType: auxSymValAndOff, 6171 argLen: 2, 6172 clobberFlags: true, 6173 faultOnNilArg0: true, 6174 symEffect: SymRead | SymWrite, 6175 asm: x86.AADDQ, 6176 reg: regInfo{ 6177 inputs: []inputInfo{ 6178 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6179 }, 6180 }, 6181 }, 6182 { 6183 name: "ADDLconstmodify", 6184 auxType: auxSymValAndOff, 6185 argLen: 2, 6186 clobberFlags: true, 6187 faultOnNilArg0: true, 6188 symEffect: SymRead | SymWrite, 6189 asm: x86.AADDL, 6190 reg: regInfo{ 6191 inputs: []inputInfo{ 6192 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6193 }, 6194 }, 6195 }, 6196 { 6197 name: "SUBQ", 6198 argLen: 2, 6199 resultInArg0: true, 6200 clobberFlags: true, 6201 asm: x86.ASUBQ, 6202 reg: regInfo{ 6203 inputs: []inputInfo{ 6204 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6205 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6206 }, 6207 outputs: []outputInfo{ 6208 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6209 }, 6210 }, 6211 }, 6212 { 6213 name: "SUBL", 6214 argLen: 2, 6215 resultInArg0: true, 6216 clobberFlags: true, 6217 asm: x86.ASUBL, 6218 reg: regInfo{ 6219 inputs: []inputInfo{ 6220 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6221 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6222 }, 6223 outputs: []outputInfo{ 6224 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6225 }, 6226 }, 6227 }, 6228 { 6229 name: "SUBQconst", 6230 auxType: auxInt32, 6231 argLen: 1, 6232 resultInArg0: true, 6233 clobberFlags: true, 6234 asm: x86.ASUBQ, 6235 reg: regInfo{ 6236 inputs: []inputInfo{ 6237 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6238 }, 6239 outputs: []outputInfo{ 6240 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6241 }, 6242 }, 6243 }, 6244 { 6245 name: "SUBLconst", 6246 auxType: auxInt32, 6247 argLen: 1, 6248 resultInArg0: true, 6249 clobberFlags: true, 6250 asm: x86.ASUBL, 6251 reg: regInfo{ 6252 inputs: []inputInfo{ 6253 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6254 }, 6255 outputs: []outputInfo{ 6256 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6257 }, 6258 }, 6259 }, 6260 { 6261 name: "MULQ", 6262 argLen: 2, 6263 commutative: true, 6264 resultInArg0: true, 6265 clobberFlags: true, 6266 asm: x86.AIMULQ, 6267 reg: regInfo{ 6268 inputs: []inputInfo{ 6269 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6270 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6271 }, 6272 outputs: []outputInfo{ 6273 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6274 }, 6275 }, 6276 }, 6277 { 6278 name: "MULL", 6279 argLen: 2, 6280 commutative: true, 6281 resultInArg0: true, 6282 clobberFlags: true, 6283 asm: x86.AIMULL, 6284 reg: regInfo{ 6285 inputs: []inputInfo{ 6286 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6287 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6288 }, 6289 outputs: []outputInfo{ 6290 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6291 }, 6292 }, 6293 }, 6294 { 6295 name: "MULQconst", 6296 auxType: auxInt32, 6297 argLen: 1, 6298 clobberFlags: true, 6299 asm: x86.AIMUL3Q, 6300 reg: regInfo{ 6301 inputs: []inputInfo{ 6302 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6303 }, 6304 outputs: []outputInfo{ 6305 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6306 }, 6307 }, 6308 }, 6309 { 6310 name: "MULLconst", 6311 auxType: auxInt32, 6312 argLen: 1, 6313 clobberFlags: true, 6314 asm: x86.AIMUL3L, 6315 reg: regInfo{ 6316 inputs: []inputInfo{ 6317 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6318 }, 6319 outputs: []outputInfo{ 6320 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6321 }, 6322 }, 6323 }, 6324 { 6325 name: "MULLU", 6326 argLen: 2, 6327 commutative: true, 6328 clobberFlags: true, 6329 asm: x86.AMULL, 6330 reg: regInfo{ 6331 inputs: []inputInfo{ 6332 {0, 1}, // AX 6333 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6334 }, 6335 clobbers: 4, // DX 6336 outputs: []outputInfo{ 6337 {1, 0}, 6338 {0, 1}, // AX 6339 }, 6340 }, 6341 }, 6342 { 6343 name: "MULQU", 6344 argLen: 2, 6345 commutative: true, 6346 clobberFlags: true, 6347 asm: x86.AMULQ, 6348 reg: regInfo{ 6349 inputs: []inputInfo{ 6350 {0, 1}, // AX 6351 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6352 }, 6353 clobbers: 4, // DX 6354 outputs: []outputInfo{ 6355 {1, 0}, 6356 {0, 1}, // AX 6357 }, 6358 }, 6359 }, 6360 { 6361 name: "HMULQ", 6362 argLen: 2, 6363 commutative: true, 6364 clobberFlags: true, 6365 asm: x86.AIMULQ, 6366 reg: regInfo{ 6367 inputs: []inputInfo{ 6368 {0, 1}, // AX 6369 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6370 }, 6371 clobbers: 1, // AX 6372 outputs: []outputInfo{ 6373 {0, 4}, // DX 6374 }, 6375 }, 6376 }, 6377 { 6378 name: "HMULL", 6379 argLen: 2, 6380 commutative: true, 6381 clobberFlags: true, 6382 asm: x86.AIMULL, 6383 reg: regInfo{ 6384 inputs: []inputInfo{ 6385 {0, 1}, // AX 6386 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6387 }, 6388 clobbers: 1, // AX 6389 outputs: []outputInfo{ 6390 {0, 4}, // DX 6391 }, 6392 }, 6393 }, 6394 { 6395 name: "HMULQU", 6396 argLen: 2, 6397 commutative: true, 6398 clobberFlags: true, 6399 asm: x86.AMULQ, 6400 reg: regInfo{ 6401 inputs: []inputInfo{ 6402 {0, 1}, // AX 6403 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6404 }, 6405 clobbers: 1, // AX 6406 outputs: []outputInfo{ 6407 {0, 4}, // DX 6408 }, 6409 }, 6410 }, 6411 { 6412 name: "HMULLU", 6413 argLen: 2, 6414 commutative: true, 6415 clobberFlags: true, 6416 asm: x86.AMULL, 6417 reg: regInfo{ 6418 inputs: []inputInfo{ 6419 {0, 1}, // AX 6420 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6421 }, 6422 clobbers: 1, // AX 6423 outputs: []outputInfo{ 6424 {0, 4}, // DX 6425 }, 6426 }, 6427 }, 6428 { 6429 name: "AVGQU", 6430 argLen: 2, 6431 commutative: true, 6432 resultInArg0: true, 6433 clobberFlags: true, 6434 reg: regInfo{ 6435 inputs: []inputInfo{ 6436 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6437 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6438 }, 6439 outputs: []outputInfo{ 6440 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6441 }, 6442 }, 6443 }, 6444 { 6445 name: "DIVQ", 6446 auxType: auxBool, 6447 argLen: 2, 6448 clobberFlags: true, 6449 asm: x86.AIDIVQ, 6450 reg: regInfo{ 6451 inputs: []inputInfo{ 6452 {0, 1}, // AX 6453 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6454 }, 6455 outputs: []outputInfo{ 6456 {0, 1}, // AX 6457 {1, 4}, // DX 6458 }, 6459 }, 6460 }, 6461 { 6462 name: "DIVL", 6463 auxType: auxBool, 6464 argLen: 2, 6465 clobberFlags: true, 6466 asm: x86.AIDIVL, 6467 reg: regInfo{ 6468 inputs: []inputInfo{ 6469 {0, 1}, // AX 6470 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6471 }, 6472 outputs: []outputInfo{ 6473 {0, 1}, // AX 6474 {1, 4}, // DX 6475 }, 6476 }, 6477 }, 6478 { 6479 name: "DIVW", 6480 auxType: auxBool, 6481 argLen: 2, 6482 clobberFlags: true, 6483 asm: x86.AIDIVW, 6484 reg: regInfo{ 6485 inputs: []inputInfo{ 6486 {0, 1}, // AX 6487 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6488 }, 6489 outputs: []outputInfo{ 6490 {0, 1}, // AX 6491 {1, 4}, // DX 6492 }, 6493 }, 6494 }, 6495 { 6496 name: "DIVQU", 6497 argLen: 2, 6498 clobberFlags: true, 6499 asm: x86.ADIVQ, 6500 reg: regInfo{ 6501 inputs: []inputInfo{ 6502 {0, 1}, // AX 6503 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6504 }, 6505 outputs: []outputInfo{ 6506 {0, 1}, // AX 6507 {1, 4}, // DX 6508 }, 6509 }, 6510 }, 6511 { 6512 name: "DIVLU", 6513 argLen: 2, 6514 clobberFlags: true, 6515 asm: x86.ADIVL, 6516 reg: regInfo{ 6517 inputs: []inputInfo{ 6518 {0, 1}, // AX 6519 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6520 }, 6521 outputs: []outputInfo{ 6522 {0, 1}, // AX 6523 {1, 4}, // DX 6524 }, 6525 }, 6526 }, 6527 { 6528 name: "DIVWU", 6529 argLen: 2, 6530 clobberFlags: true, 6531 asm: x86.ADIVW, 6532 reg: regInfo{ 6533 inputs: []inputInfo{ 6534 {0, 1}, // AX 6535 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6536 }, 6537 outputs: []outputInfo{ 6538 {0, 1}, // AX 6539 {1, 4}, // DX 6540 }, 6541 }, 6542 }, 6543 { 6544 name: "MULQU2", 6545 argLen: 2, 6546 commutative: true, 6547 clobberFlags: true, 6548 asm: x86.AMULQ, 6549 reg: regInfo{ 6550 inputs: []inputInfo{ 6551 {0, 1}, // AX 6552 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6553 }, 6554 outputs: []outputInfo{ 6555 {0, 4}, // DX 6556 {1, 1}, // AX 6557 }, 6558 }, 6559 }, 6560 { 6561 name: "DIVQU2", 6562 argLen: 3, 6563 clobberFlags: true, 6564 asm: x86.ADIVQ, 6565 reg: regInfo{ 6566 inputs: []inputInfo{ 6567 {0, 4}, // DX 6568 {1, 1}, // AX 6569 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6570 }, 6571 outputs: []outputInfo{ 6572 {0, 1}, // AX 6573 {1, 4}, // DX 6574 }, 6575 }, 6576 }, 6577 { 6578 name: "ANDQ", 6579 argLen: 2, 6580 commutative: true, 6581 resultInArg0: true, 6582 clobberFlags: true, 6583 asm: x86.AANDQ, 6584 reg: regInfo{ 6585 inputs: []inputInfo{ 6586 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6587 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6588 }, 6589 outputs: []outputInfo{ 6590 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6591 }, 6592 }, 6593 }, 6594 { 6595 name: "ANDL", 6596 argLen: 2, 6597 commutative: true, 6598 resultInArg0: true, 6599 clobberFlags: true, 6600 asm: x86.AANDL, 6601 reg: regInfo{ 6602 inputs: []inputInfo{ 6603 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6604 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6605 }, 6606 outputs: []outputInfo{ 6607 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6608 }, 6609 }, 6610 }, 6611 { 6612 name: "ANDQconst", 6613 auxType: auxInt32, 6614 argLen: 1, 6615 resultInArg0: true, 6616 clobberFlags: true, 6617 asm: x86.AANDQ, 6618 reg: regInfo{ 6619 inputs: []inputInfo{ 6620 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6621 }, 6622 outputs: []outputInfo{ 6623 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6624 }, 6625 }, 6626 }, 6627 { 6628 name: "ANDLconst", 6629 auxType: auxInt32, 6630 argLen: 1, 6631 resultInArg0: true, 6632 clobberFlags: true, 6633 asm: x86.AANDL, 6634 reg: regInfo{ 6635 inputs: []inputInfo{ 6636 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6637 }, 6638 outputs: []outputInfo{ 6639 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6640 }, 6641 }, 6642 }, 6643 { 6644 name: "ANDQconstmodify", 6645 auxType: auxSymValAndOff, 6646 argLen: 2, 6647 clobberFlags: true, 6648 faultOnNilArg0: true, 6649 symEffect: SymRead | SymWrite, 6650 asm: x86.AANDQ, 6651 reg: regInfo{ 6652 inputs: []inputInfo{ 6653 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6654 }, 6655 }, 6656 }, 6657 { 6658 name: "ANDLconstmodify", 6659 auxType: auxSymValAndOff, 6660 argLen: 2, 6661 clobberFlags: true, 6662 faultOnNilArg0: true, 6663 symEffect: SymRead | SymWrite, 6664 asm: x86.AANDL, 6665 reg: regInfo{ 6666 inputs: []inputInfo{ 6667 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6668 }, 6669 }, 6670 }, 6671 { 6672 name: "ORQ", 6673 argLen: 2, 6674 commutative: true, 6675 resultInArg0: true, 6676 clobberFlags: true, 6677 asm: x86.AORQ, 6678 reg: regInfo{ 6679 inputs: []inputInfo{ 6680 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6681 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6682 }, 6683 outputs: []outputInfo{ 6684 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6685 }, 6686 }, 6687 }, 6688 { 6689 name: "ORL", 6690 argLen: 2, 6691 commutative: true, 6692 resultInArg0: true, 6693 clobberFlags: true, 6694 asm: x86.AORL, 6695 reg: regInfo{ 6696 inputs: []inputInfo{ 6697 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6698 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6699 }, 6700 outputs: []outputInfo{ 6701 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6702 }, 6703 }, 6704 }, 6705 { 6706 name: "ORQconst", 6707 auxType: auxInt32, 6708 argLen: 1, 6709 resultInArg0: true, 6710 clobberFlags: true, 6711 asm: x86.AORQ, 6712 reg: regInfo{ 6713 inputs: []inputInfo{ 6714 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6715 }, 6716 outputs: []outputInfo{ 6717 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6718 }, 6719 }, 6720 }, 6721 { 6722 name: "ORLconst", 6723 auxType: auxInt32, 6724 argLen: 1, 6725 resultInArg0: true, 6726 clobberFlags: true, 6727 asm: x86.AORL, 6728 reg: regInfo{ 6729 inputs: []inputInfo{ 6730 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6731 }, 6732 outputs: []outputInfo{ 6733 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6734 }, 6735 }, 6736 }, 6737 { 6738 name: "ORQconstmodify", 6739 auxType: auxSymValAndOff, 6740 argLen: 2, 6741 clobberFlags: true, 6742 faultOnNilArg0: true, 6743 symEffect: SymRead | SymWrite, 6744 asm: x86.AORQ, 6745 reg: regInfo{ 6746 inputs: []inputInfo{ 6747 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6748 }, 6749 }, 6750 }, 6751 { 6752 name: "ORLconstmodify", 6753 auxType: auxSymValAndOff, 6754 argLen: 2, 6755 clobberFlags: true, 6756 faultOnNilArg0: true, 6757 symEffect: SymRead | SymWrite, 6758 asm: x86.AORL, 6759 reg: regInfo{ 6760 inputs: []inputInfo{ 6761 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6762 }, 6763 }, 6764 }, 6765 { 6766 name: "XORQ", 6767 argLen: 2, 6768 commutative: true, 6769 resultInArg0: true, 6770 clobberFlags: true, 6771 asm: x86.AXORQ, 6772 reg: regInfo{ 6773 inputs: []inputInfo{ 6774 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6775 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6776 }, 6777 outputs: []outputInfo{ 6778 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6779 }, 6780 }, 6781 }, 6782 { 6783 name: "XORL", 6784 argLen: 2, 6785 commutative: true, 6786 resultInArg0: true, 6787 clobberFlags: true, 6788 asm: x86.AXORL, 6789 reg: regInfo{ 6790 inputs: []inputInfo{ 6791 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6792 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6793 }, 6794 outputs: []outputInfo{ 6795 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6796 }, 6797 }, 6798 }, 6799 { 6800 name: "XORQconst", 6801 auxType: auxInt32, 6802 argLen: 1, 6803 resultInArg0: true, 6804 clobberFlags: true, 6805 asm: x86.AXORQ, 6806 reg: regInfo{ 6807 inputs: []inputInfo{ 6808 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6809 }, 6810 outputs: []outputInfo{ 6811 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6812 }, 6813 }, 6814 }, 6815 { 6816 name: "XORLconst", 6817 auxType: auxInt32, 6818 argLen: 1, 6819 resultInArg0: true, 6820 clobberFlags: true, 6821 asm: x86.AXORL, 6822 reg: regInfo{ 6823 inputs: []inputInfo{ 6824 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6825 }, 6826 outputs: []outputInfo{ 6827 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6828 }, 6829 }, 6830 }, 6831 { 6832 name: "XORQconstmodify", 6833 auxType: auxSymValAndOff, 6834 argLen: 2, 6835 clobberFlags: true, 6836 faultOnNilArg0: true, 6837 symEffect: SymRead | SymWrite, 6838 asm: x86.AXORQ, 6839 reg: regInfo{ 6840 inputs: []inputInfo{ 6841 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6842 }, 6843 }, 6844 }, 6845 { 6846 name: "XORLconstmodify", 6847 auxType: auxSymValAndOff, 6848 argLen: 2, 6849 clobberFlags: true, 6850 faultOnNilArg0: true, 6851 symEffect: SymRead | SymWrite, 6852 asm: x86.AXORL, 6853 reg: regInfo{ 6854 inputs: []inputInfo{ 6855 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6856 }, 6857 }, 6858 }, 6859 { 6860 name: "CMPQ", 6861 argLen: 2, 6862 asm: x86.ACMPQ, 6863 reg: regInfo{ 6864 inputs: []inputInfo{ 6865 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6866 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6867 }, 6868 }, 6869 }, 6870 { 6871 name: "CMPL", 6872 argLen: 2, 6873 asm: x86.ACMPL, 6874 reg: regInfo{ 6875 inputs: []inputInfo{ 6876 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6877 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6878 }, 6879 }, 6880 }, 6881 { 6882 name: "CMPW", 6883 argLen: 2, 6884 asm: x86.ACMPW, 6885 reg: regInfo{ 6886 inputs: []inputInfo{ 6887 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6888 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6889 }, 6890 }, 6891 }, 6892 { 6893 name: "CMPB", 6894 argLen: 2, 6895 asm: x86.ACMPB, 6896 reg: regInfo{ 6897 inputs: []inputInfo{ 6898 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6899 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6900 }, 6901 }, 6902 }, 6903 { 6904 name: "CMPQconst", 6905 auxType: auxInt32, 6906 argLen: 1, 6907 asm: x86.ACMPQ, 6908 reg: regInfo{ 6909 inputs: []inputInfo{ 6910 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6911 }, 6912 }, 6913 }, 6914 { 6915 name: "CMPLconst", 6916 auxType: auxInt32, 6917 argLen: 1, 6918 asm: x86.ACMPL, 6919 reg: regInfo{ 6920 inputs: []inputInfo{ 6921 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6922 }, 6923 }, 6924 }, 6925 { 6926 name: "CMPWconst", 6927 auxType: auxInt16, 6928 argLen: 1, 6929 asm: x86.ACMPW, 6930 reg: regInfo{ 6931 inputs: []inputInfo{ 6932 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6933 }, 6934 }, 6935 }, 6936 { 6937 name: "CMPBconst", 6938 auxType: auxInt8, 6939 argLen: 1, 6940 asm: x86.ACMPB, 6941 reg: regInfo{ 6942 inputs: []inputInfo{ 6943 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6944 }, 6945 }, 6946 }, 6947 { 6948 name: "CMPQload", 6949 auxType: auxSymOff, 6950 argLen: 3, 6951 faultOnNilArg0: true, 6952 symEffect: SymRead, 6953 asm: x86.ACMPQ, 6954 reg: regInfo{ 6955 inputs: []inputInfo{ 6956 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6957 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6958 }, 6959 }, 6960 }, 6961 { 6962 name: "CMPLload", 6963 auxType: auxSymOff, 6964 argLen: 3, 6965 faultOnNilArg0: true, 6966 symEffect: SymRead, 6967 asm: x86.ACMPL, 6968 reg: regInfo{ 6969 inputs: []inputInfo{ 6970 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6971 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6972 }, 6973 }, 6974 }, 6975 { 6976 name: "CMPWload", 6977 auxType: auxSymOff, 6978 argLen: 3, 6979 faultOnNilArg0: true, 6980 symEffect: SymRead, 6981 asm: x86.ACMPW, 6982 reg: regInfo{ 6983 inputs: []inputInfo{ 6984 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6985 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6986 }, 6987 }, 6988 }, 6989 { 6990 name: "CMPBload", 6991 auxType: auxSymOff, 6992 argLen: 3, 6993 faultOnNilArg0: true, 6994 symEffect: SymRead, 6995 asm: x86.ACMPB, 6996 reg: regInfo{ 6997 inputs: []inputInfo{ 6998 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6999 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7000 }, 7001 }, 7002 }, 7003 { 7004 name: "CMPQconstload", 7005 auxType: auxSymValAndOff, 7006 argLen: 2, 7007 faultOnNilArg0: true, 7008 symEffect: SymRead, 7009 asm: x86.ACMPQ, 7010 reg: regInfo{ 7011 inputs: []inputInfo{ 7012 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7013 }, 7014 }, 7015 }, 7016 { 7017 name: "CMPLconstload", 7018 auxType: auxSymValAndOff, 7019 argLen: 2, 7020 faultOnNilArg0: true, 7021 symEffect: SymRead, 7022 asm: x86.ACMPL, 7023 reg: regInfo{ 7024 inputs: []inputInfo{ 7025 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7026 }, 7027 }, 7028 }, 7029 { 7030 name: "CMPWconstload", 7031 auxType: auxSymValAndOff, 7032 argLen: 2, 7033 faultOnNilArg0: true, 7034 symEffect: SymRead, 7035 asm: x86.ACMPW, 7036 reg: regInfo{ 7037 inputs: []inputInfo{ 7038 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7039 }, 7040 }, 7041 }, 7042 { 7043 name: "CMPBconstload", 7044 auxType: auxSymValAndOff, 7045 argLen: 2, 7046 faultOnNilArg0: true, 7047 symEffect: SymRead, 7048 asm: x86.ACMPB, 7049 reg: regInfo{ 7050 inputs: []inputInfo{ 7051 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7052 }, 7053 }, 7054 }, 7055 { 7056 name: "UCOMISS", 7057 argLen: 2, 7058 asm: x86.AUCOMISS, 7059 reg: regInfo{ 7060 inputs: []inputInfo{ 7061 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7062 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7063 }, 7064 }, 7065 }, 7066 { 7067 name: "UCOMISD", 7068 argLen: 2, 7069 asm: x86.AUCOMISD, 7070 reg: regInfo{ 7071 inputs: []inputInfo{ 7072 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7073 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7074 }, 7075 }, 7076 }, 7077 { 7078 name: "BTL", 7079 argLen: 2, 7080 asm: x86.ABTL, 7081 reg: regInfo{ 7082 inputs: []inputInfo{ 7083 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7084 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7085 }, 7086 }, 7087 }, 7088 { 7089 name: "BTQ", 7090 argLen: 2, 7091 asm: x86.ABTQ, 7092 reg: regInfo{ 7093 inputs: []inputInfo{ 7094 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7095 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7096 }, 7097 }, 7098 }, 7099 { 7100 name: "BTCL", 7101 argLen: 2, 7102 resultInArg0: true, 7103 clobberFlags: true, 7104 asm: x86.ABTCL, 7105 reg: regInfo{ 7106 inputs: []inputInfo{ 7107 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7108 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7109 }, 7110 outputs: []outputInfo{ 7111 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7112 }, 7113 }, 7114 }, 7115 { 7116 name: "BTCQ", 7117 argLen: 2, 7118 resultInArg0: true, 7119 clobberFlags: true, 7120 asm: x86.ABTCQ, 7121 reg: regInfo{ 7122 inputs: []inputInfo{ 7123 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7124 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7125 }, 7126 outputs: []outputInfo{ 7127 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7128 }, 7129 }, 7130 }, 7131 { 7132 name: "BTRL", 7133 argLen: 2, 7134 resultInArg0: true, 7135 clobberFlags: true, 7136 asm: x86.ABTRL, 7137 reg: regInfo{ 7138 inputs: []inputInfo{ 7139 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7140 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7141 }, 7142 outputs: []outputInfo{ 7143 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7144 }, 7145 }, 7146 }, 7147 { 7148 name: "BTRQ", 7149 argLen: 2, 7150 resultInArg0: true, 7151 clobberFlags: true, 7152 asm: x86.ABTRQ, 7153 reg: regInfo{ 7154 inputs: []inputInfo{ 7155 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7156 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7157 }, 7158 outputs: []outputInfo{ 7159 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7160 }, 7161 }, 7162 }, 7163 { 7164 name: "BTSL", 7165 argLen: 2, 7166 resultInArg0: true, 7167 clobberFlags: true, 7168 asm: x86.ABTSL, 7169 reg: regInfo{ 7170 inputs: []inputInfo{ 7171 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7172 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7173 }, 7174 outputs: []outputInfo{ 7175 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7176 }, 7177 }, 7178 }, 7179 { 7180 name: "BTSQ", 7181 argLen: 2, 7182 resultInArg0: true, 7183 clobberFlags: true, 7184 asm: x86.ABTSQ, 7185 reg: regInfo{ 7186 inputs: []inputInfo{ 7187 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7188 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7189 }, 7190 outputs: []outputInfo{ 7191 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7192 }, 7193 }, 7194 }, 7195 { 7196 name: "BTLconst", 7197 auxType: auxInt8, 7198 argLen: 1, 7199 asm: x86.ABTL, 7200 reg: regInfo{ 7201 inputs: []inputInfo{ 7202 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7203 }, 7204 }, 7205 }, 7206 { 7207 name: "BTQconst", 7208 auxType: auxInt8, 7209 argLen: 1, 7210 asm: x86.ABTQ, 7211 reg: regInfo{ 7212 inputs: []inputInfo{ 7213 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7214 }, 7215 }, 7216 }, 7217 { 7218 name: "BTCLconst", 7219 auxType: auxInt8, 7220 argLen: 1, 7221 resultInArg0: true, 7222 clobberFlags: true, 7223 asm: x86.ABTCL, 7224 reg: regInfo{ 7225 inputs: []inputInfo{ 7226 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7227 }, 7228 outputs: []outputInfo{ 7229 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7230 }, 7231 }, 7232 }, 7233 { 7234 name: "BTCQconst", 7235 auxType: auxInt8, 7236 argLen: 1, 7237 resultInArg0: true, 7238 clobberFlags: true, 7239 asm: x86.ABTCQ, 7240 reg: regInfo{ 7241 inputs: []inputInfo{ 7242 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7243 }, 7244 outputs: []outputInfo{ 7245 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7246 }, 7247 }, 7248 }, 7249 { 7250 name: "BTRLconst", 7251 auxType: auxInt8, 7252 argLen: 1, 7253 resultInArg0: true, 7254 clobberFlags: true, 7255 asm: x86.ABTRL, 7256 reg: regInfo{ 7257 inputs: []inputInfo{ 7258 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7259 }, 7260 outputs: []outputInfo{ 7261 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7262 }, 7263 }, 7264 }, 7265 { 7266 name: "BTRQconst", 7267 auxType: auxInt8, 7268 argLen: 1, 7269 resultInArg0: true, 7270 clobberFlags: true, 7271 asm: x86.ABTRQ, 7272 reg: regInfo{ 7273 inputs: []inputInfo{ 7274 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7275 }, 7276 outputs: []outputInfo{ 7277 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7278 }, 7279 }, 7280 }, 7281 { 7282 name: "BTSLconst", 7283 auxType: auxInt8, 7284 argLen: 1, 7285 resultInArg0: true, 7286 clobberFlags: true, 7287 asm: x86.ABTSL, 7288 reg: regInfo{ 7289 inputs: []inputInfo{ 7290 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7291 }, 7292 outputs: []outputInfo{ 7293 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7294 }, 7295 }, 7296 }, 7297 { 7298 name: "BTSQconst", 7299 auxType: auxInt8, 7300 argLen: 1, 7301 resultInArg0: true, 7302 clobberFlags: true, 7303 asm: x86.ABTSQ, 7304 reg: regInfo{ 7305 inputs: []inputInfo{ 7306 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7307 }, 7308 outputs: []outputInfo{ 7309 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7310 }, 7311 }, 7312 }, 7313 { 7314 name: "BTCQmodify", 7315 auxType: auxSymOff, 7316 argLen: 3, 7317 clobberFlags: true, 7318 faultOnNilArg0: true, 7319 symEffect: SymRead | SymWrite, 7320 asm: x86.ABTCQ, 7321 reg: regInfo{ 7322 inputs: []inputInfo{ 7323 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7324 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7325 }, 7326 }, 7327 }, 7328 { 7329 name: "BTCLmodify", 7330 auxType: auxSymOff, 7331 argLen: 3, 7332 clobberFlags: true, 7333 faultOnNilArg0: true, 7334 symEffect: SymRead | SymWrite, 7335 asm: x86.ABTCL, 7336 reg: regInfo{ 7337 inputs: []inputInfo{ 7338 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7339 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7340 }, 7341 }, 7342 }, 7343 { 7344 name: "BTSQmodify", 7345 auxType: auxSymOff, 7346 argLen: 3, 7347 clobberFlags: true, 7348 faultOnNilArg0: true, 7349 symEffect: SymRead | SymWrite, 7350 asm: x86.ABTSQ, 7351 reg: regInfo{ 7352 inputs: []inputInfo{ 7353 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7354 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7355 }, 7356 }, 7357 }, 7358 { 7359 name: "BTSLmodify", 7360 auxType: auxSymOff, 7361 argLen: 3, 7362 clobberFlags: true, 7363 faultOnNilArg0: true, 7364 symEffect: SymRead | SymWrite, 7365 asm: x86.ABTSL, 7366 reg: regInfo{ 7367 inputs: []inputInfo{ 7368 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7369 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7370 }, 7371 }, 7372 }, 7373 { 7374 name: "BTRQmodify", 7375 auxType: auxSymOff, 7376 argLen: 3, 7377 clobberFlags: true, 7378 faultOnNilArg0: true, 7379 symEffect: SymRead | SymWrite, 7380 asm: x86.ABTRQ, 7381 reg: regInfo{ 7382 inputs: []inputInfo{ 7383 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7384 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7385 }, 7386 }, 7387 }, 7388 { 7389 name: "BTRLmodify", 7390 auxType: auxSymOff, 7391 argLen: 3, 7392 clobberFlags: true, 7393 faultOnNilArg0: true, 7394 symEffect: SymRead | SymWrite, 7395 asm: x86.ABTRL, 7396 reg: regInfo{ 7397 inputs: []inputInfo{ 7398 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7399 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7400 }, 7401 }, 7402 }, 7403 { 7404 name: "BTCQconstmodify", 7405 auxType: auxSymValAndOff, 7406 argLen: 2, 7407 clobberFlags: true, 7408 faultOnNilArg0: true, 7409 symEffect: SymRead | SymWrite, 7410 asm: x86.ABTCQ, 7411 reg: regInfo{ 7412 inputs: []inputInfo{ 7413 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7414 }, 7415 }, 7416 }, 7417 { 7418 name: "BTCLconstmodify", 7419 auxType: auxSymValAndOff, 7420 argLen: 2, 7421 clobberFlags: true, 7422 faultOnNilArg0: true, 7423 symEffect: SymRead | SymWrite, 7424 asm: x86.ABTCL, 7425 reg: regInfo{ 7426 inputs: []inputInfo{ 7427 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7428 }, 7429 }, 7430 }, 7431 { 7432 name: "BTSQconstmodify", 7433 auxType: auxSymValAndOff, 7434 argLen: 2, 7435 clobberFlags: true, 7436 faultOnNilArg0: true, 7437 symEffect: SymRead | SymWrite, 7438 asm: x86.ABTSQ, 7439 reg: regInfo{ 7440 inputs: []inputInfo{ 7441 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7442 }, 7443 }, 7444 }, 7445 { 7446 name: "BTSLconstmodify", 7447 auxType: auxSymValAndOff, 7448 argLen: 2, 7449 clobberFlags: true, 7450 faultOnNilArg0: true, 7451 symEffect: SymRead | SymWrite, 7452 asm: x86.ABTSL, 7453 reg: regInfo{ 7454 inputs: []inputInfo{ 7455 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7456 }, 7457 }, 7458 }, 7459 { 7460 name: "BTRQconstmodify", 7461 auxType: auxSymValAndOff, 7462 argLen: 2, 7463 clobberFlags: true, 7464 faultOnNilArg0: true, 7465 symEffect: SymRead | SymWrite, 7466 asm: x86.ABTRQ, 7467 reg: regInfo{ 7468 inputs: []inputInfo{ 7469 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7470 }, 7471 }, 7472 }, 7473 { 7474 name: "BTRLconstmodify", 7475 auxType: auxSymValAndOff, 7476 argLen: 2, 7477 clobberFlags: true, 7478 faultOnNilArg0: true, 7479 symEffect: SymRead | SymWrite, 7480 asm: x86.ABTRL, 7481 reg: regInfo{ 7482 inputs: []inputInfo{ 7483 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7484 }, 7485 }, 7486 }, 7487 { 7488 name: "TESTQ", 7489 argLen: 2, 7490 commutative: true, 7491 asm: x86.ATESTQ, 7492 reg: regInfo{ 7493 inputs: []inputInfo{ 7494 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7495 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7496 }, 7497 }, 7498 }, 7499 { 7500 name: "TESTL", 7501 argLen: 2, 7502 commutative: true, 7503 asm: x86.ATESTL, 7504 reg: regInfo{ 7505 inputs: []inputInfo{ 7506 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7507 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7508 }, 7509 }, 7510 }, 7511 { 7512 name: "TESTW", 7513 argLen: 2, 7514 commutative: true, 7515 asm: x86.ATESTW, 7516 reg: regInfo{ 7517 inputs: []inputInfo{ 7518 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7519 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7520 }, 7521 }, 7522 }, 7523 { 7524 name: "TESTB", 7525 argLen: 2, 7526 commutative: true, 7527 asm: x86.ATESTB, 7528 reg: regInfo{ 7529 inputs: []inputInfo{ 7530 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7531 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7532 }, 7533 }, 7534 }, 7535 { 7536 name: "TESTQconst", 7537 auxType: auxInt32, 7538 argLen: 1, 7539 asm: x86.ATESTQ, 7540 reg: regInfo{ 7541 inputs: []inputInfo{ 7542 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7543 }, 7544 }, 7545 }, 7546 { 7547 name: "TESTLconst", 7548 auxType: auxInt32, 7549 argLen: 1, 7550 asm: x86.ATESTL, 7551 reg: regInfo{ 7552 inputs: []inputInfo{ 7553 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7554 }, 7555 }, 7556 }, 7557 { 7558 name: "TESTWconst", 7559 auxType: auxInt16, 7560 argLen: 1, 7561 asm: x86.ATESTW, 7562 reg: regInfo{ 7563 inputs: []inputInfo{ 7564 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7565 }, 7566 }, 7567 }, 7568 { 7569 name: "TESTBconst", 7570 auxType: auxInt8, 7571 argLen: 1, 7572 asm: x86.ATESTB, 7573 reg: regInfo{ 7574 inputs: []inputInfo{ 7575 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7576 }, 7577 }, 7578 }, 7579 { 7580 name: "SHLQ", 7581 argLen: 2, 7582 resultInArg0: true, 7583 clobberFlags: true, 7584 asm: x86.ASHLQ, 7585 reg: regInfo{ 7586 inputs: []inputInfo{ 7587 {1, 2}, // CX 7588 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7589 }, 7590 outputs: []outputInfo{ 7591 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7592 }, 7593 }, 7594 }, 7595 { 7596 name: "SHLL", 7597 argLen: 2, 7598 resultInArg0: true, 7599 clobberFlags: true, 7600 asm: x86.ASHLL, 7601 reg: regInfo{ 7602 inputs: []inputInfo{ 7603 {1, 2}, // CX 7604 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7605 }, 7606 outputs: []outputInfo{ 7607 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7608 }, 7609 }, 7610 }, 7611 { 7612 name: "SHLQconst", 7613 auxType: auxInt8, 7614 argLen: 1, 7615 resultInArg0: true, 7616 clobberFlags: true, 7617 asm: x86.ASHLQ, 7618 reg: regInfo{ 7619 inputs: []inputInfo{ 7620 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7621 }, 7622 outputs: []outputInfo{ 7623 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7624 }, 7625 }, 7626 }, 7627 { 7628 name: "SHLLconst", 7629 auxType: auxInt8, 7630 argLen: 1, 7631 resultInArg0: true, 7632 clobberFlags: true, 7633 asm: x86.ASHLL, 7634 reg: regInfo{ 7635 inputs: []inputInfo{ 7636 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7637 }, 7638 outputs: []outputInfo{ 7639 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7640 }, 7641 }, 7642 }, 7643 { 7644 name: "SHRQ", 7645 argLen: 2, 7646 resultInArg0: true, 7647 clobberFlags: true, 7648 asm: x86.ASHRQ, 7649 reg: regInfo{ 7650 inputs: []inputInfo{ 7651 {1, 2}, // CX 7652 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7653 }, 7654 outputs: []outputInfo{ 7655 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7656 }, 7657 }, 7658 }, 7659 { 7660 name: "SHRL", 7661 argLen: 2, 7662 resultInArg0: true, 7663 clobberFlags: true, 7664 asm: x86.ASHRL, 7665 reg: regInfo{ 7666 inputs: []inputInfo{ 7667 {1, 2}, // CX 7668 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7669 }, 7670 outputs: []outputInfo{ 7671 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7672 }, 7673 }, 7674 }, 7675 { 7676 name: "SHRW", 7677 argLen: 2, 7678 resultInArg0: true, 7679 clobberFlags: true, 7680 asm: x86.ASHRW, 7681 reg: regInfo{ 7682 inputs: []inputInfo{ 7683 {1, 2}, // CX 7684 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7685 }, 7686 outputs: []outputInfo{ 7687 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7688 }, 7689 }, 7690 }, 7691 { 7692 name: "SHRB", 7693 argLen: 2, 7694 resultInArg0: true, 7695 clobberFlags: true, 7696 asm: x86.ASHRB, 7697 reg: regInfo{ 7698 inputs: []inputInfo{ 7699 {1, 2}, // CX 7700 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7701 }, 7702 outputs: []outputInfo{ 7703 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7704 }, 7705 }, 7706 }, 7707 { 7708 name: "SHRQconst", 7709 auxType: auxInt8, 7710 argLen: 1, 7711 resultInArg0: true, 7712 clobberFlags: true, 7713 asm: x86.ASHRQ, 7714 reg: regInfo{ 7715 inputs: []inputInfo{ 7716 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7717 }, 7718 outputs: []outputInfo{ 7719 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7720 }, 7721 }, 7722 }, 7723 { 7724 name: "SHRLconst", 7725 auxType: auxInt8, 7726 argLen: 1, 7727 resultInArg0: true, 7728 clobberFlags: true, 7729 asm: x86.ASHRL, 7730 reg: regInfo{ 7731 inputs: []inputInfo{ 7732 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7733 }, 7734 outputs: []outputInfo{ 7735 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7736 }, 7737 }, 7738 }, 7739 { 7740 name: "SHRWconst", 7741 auxType: auxInt8, 7742 argLen: 1, 7743 resultInArg0: true, 7744 clobberFlags: true, 7745 asm: x86.ASHRW, 7746 reg: regInfo{ 7747 inputs: []inputInfo{ 7748 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7749 }, 7750 outputs: []outputInfo{ 7751 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7752 }, 7753 }, 7754 }, 7755 { 7756 name: "SHRBconst", 7757 auxType: auxInt8, 7758 argLen: 1, 7759 resultInArg0: true, 7760 clobberFlags: true, 7761 asm: x86.ASHRB, 7762 reg: regInfo{ 7763 inputs: []inputInfo{ 7764 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7765 }, 7766 outputs: []outputInfo{ 7767 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7768 }, 7769 }, 7770 }, 7771 { 7772 name: "SARQ", 7773 argLen: 2, 7774 resultInArg0: true, 7775 clobberFlags: true, 7776 asm: x86.ASARQ, 7777 reg: regInfo{ 7778 inputs: []inputInfo{ 7779 {1, 2}, // CX 7780 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7781 }, 7782 outputs: []outputInfo{ 7783 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7784 }, 7785 }, 7786 }, 7787 { 7788 name: "SARL", 7789 argLen: 2, 7790 resultInArg0: true, 7791 clobberFlags: true, 7792 asm: x86.ASARL, 7793 reg: regInfo{ 7794 inputs: []inputInfo{ 7795 {1, 2}, // CX 7796 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7797 }, 7798 outputs: []outputInfo{ 7799 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7800 }, 7801 }, 7802 }, 7803 { 7804 name: "SARW", 7805 argLen: 2, 7806 resultInArg0: true, 7807 clobberFlags: true, 7808 asm: x86.ASARW, 7809 reg: regInfo{ 7810 inputs: []inputInfo{ 7811 {1, 2}, // CX 7812 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7813 }, 7814 outputs: []outputInfo{ 7815 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7816 }, 7817 }, 7818 }, 7819 { 7820 name: "SARB", 7821 argLen: 2, 7822 resultInArg0: true, 7823 clobberFlags: true, 7824 asm: x86.ASARB, 7825 reg: regInfo{ 7826 inputs: []inputInfo{ 7827 {1, 2}, // CX 7828 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7829 }, 7830 outputs: []outputInfo{ 7831 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7832 }, 7833 }, 7834 }, 7835 { 7836 name: "SARQconst", 7837 auxType: auxInt8, 7838 argLen: 1, 7839 resultInArg0: true, 7840 clobberFlags: true, 7841 asm: x86.ASARQ, 7842 reg: regInfo{ 7843 inputs: []inputInfo{ 7844 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7845 }, 7846 outputs: []outputInfo{ 7847 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7848 }, 7849 }, 7850 }, 7851 { 7852 name: "SARLconst", 7853 auxType: auxInt8, 7854 argLen: 1, 7855 resultInArg0: true, 7856 clobberFlags: true, 7857 asm: x86.ASARL, 7858 reg: regInfo{ 7859 inputs: []inputInfo{ 7860 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7861 }, 7862 outputs: []outputInfo{ 7863 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7864 }, 7865 }, 7866 }, 7867 { 7868 name: "SARWconst", 7869 auxType: auxInt8, 7870 argLen: 1, 7871 resultInArg0: true, 7872 clobberFlags: true, 7873 asm: x86.ASARW, 7874 reg: regInfo{ 7875 inputs: []inputInfo{ 7876 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7877 }, 7878 outputs: []outputInfo{ 7879 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7880 }, 7881 }, 7882 }, 7883 { 7884 name: "SARBconst", 7885 auxType: auxInt8, 7886 argLen: 1, 7887 resultInArg0: true, 7888 clobberFlags: true, 7889 asm: x86.ASARB, 7890 reg: regInfo{ 7891 inputs: []inputInfo{ 7892 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7893 }, 7894 outputs: []outputInfo{ 7895 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7896 }, 7897 }, 7898 }, 7899 { 7900 name: "ROLQ", 7901 argLen: 2, 7902 resultInArg0: true, 7903 clobberFlags: true, 7904 asm: x86.AROLQ, 7905 reg: regInfo{ 7906 inputs: []inputInfo{ 7907 {1, 2}, // CX 7908 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7909 }, 7910 outputs: []outputInfo{ 7911 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7912 }, 7913 }, 7914 }, 7915 { 7916 name: "ROLL", 7917 argLen: 2, 7918 resultInArg0: true, 7919 clobberFlags: true, 7920 asm: x86.AROLL, 7921 reg: regInfo{ 7922 inputs: []inputInfo{ 7923 {1, 2}, // CX 7924 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7925 }, 7926 outputs: []outputInfo{ 7927 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7928 }, 7929 }, 7930 }, 7931 { 7932 name: "ROLW", 7933 argLen: 2, 7934 resultInArg0: true, 7935 clobberFlags: true, 7936 asm: x86.AROLW, 7937 reg: regInfo{ 7938 inputs: []inputInfo{ 7939 {1, 2}, // CX 7940 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7941 }, 7942 outputs: []outputInfo{ 7943 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7944 }, 7945 }, 7946 }, 7947 { 7948 name: "ROLB", 7949 argLen: 2, 7950 resultInArg0: true, 7951 clobberFlags: true, 7952 asm: x86.AROLB, 7953 reg: regInfo{ 7954 inputs: []inputInfo{ 7955 {1, 2}, // CX 7956 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7957 }, 7958 outputs: []outputInfo{ 7959 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7960 }, 7961 }, 7962 }, 7963 { 7964 name: "RORQ", 7965 argLen: 2, 7966 resultInArg0: true, 7967 clobberFlags: true, 7968 asm: x86.ARORQ, 7969 reg: regInfo{ 7970 inputs: []inputInfo{ 7971 {1, 2}, // CX 7972 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7973 }, 7974 outputs: []outputInfo{ 7975 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7976 }, 7977 }, 7978 }, 7979 { 7980 name: "RORL", 7981 argLen: 2, 7982 resultInArg0: true, 7983 clobberFlags: true, 7984 asm: x86.ARORL, 7985 reg: regInfo{ 7986 inputs: []inputInfo{ 7987 {1, 2}, // CX 7988 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7989 }, 7990 outputs: []outputInfo{ 7991 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7992 }, 7993 }, 7994 }, 7995 { 7996 name: "RORW", 7997 argLen: 2, 7998 resultInArg0: true, 7999 clobberFlags: true, 8000 asm: x86.ARORW, 8001 reg: regInfo{ 8002 inputs: []inputInfo{ 8003 {1, 2}, // CX 8004 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8005 }, 8006 outputs: []outputInfo{ 8007 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8008 }, 8009 }, 8010 }, 8011 { 8012 name: "RORB", 8013 argLen: 2, 8014 resultInArg0: true, 8015 clobberFlags: true, 8016 asm: x86.ARORB, 8017 reg: regInfo{ 8018 inputs: []inputInfo{ 8019 {1, 2}, // CX 8020 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8021 }, 8022 outputs: []outputInfo{ 8023 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8024 }, 8025 }, 8026 }, 8027 { 8028 name: "ROLQconst", 8029 auxType: auxInt8, 8030 argLen: 1, 8031 resultInArg0: true, 8032 clobberFlags: true, 8033 asm: x86.AROLQ, 8034 reg: regInfo{ 8035 inputs: []inputInfo{ 8036 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8037 }, 8038 outputs: []outputInfo{ 8039 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8040 }, 8041 }, 8042 }, 8043 { 8044 name: "ROLLconst", 8045 auxType: auxInt8, 8046 argLen: 1, 8047 resultInArg0: true, 8048 clobberFlags: true, 8049 asm: x86.AROLL, 8050 reg: regInfo{ 8051 inputs: []inputInfo{ 8052 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8053 }, 8054 outputs: []outputInfo{ 8055 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8056 }, 8057 }, 8058 }, 8059 { 8060 name: "ROLWconst", 8061 auxType: auxInt8, 8062 argLen: 1, 8063 resultInArg0: true, 8064 clobberFlags: true, 8065 asm: x86.AROLW, 8066 reg: regInfo{ 8067 inputs: []inputInfo{ 8068 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8069 }, 8070 outputs: []outputInfo{ 8071 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8072 }, 8073 }, 8074 }, 8075 { 8076 name: "ROLBconst", 8077 auxType: auxInt8, 8078 argLen: 1, 8079 resultInArg0: true, 8080 clobberFlags: true, 8081 asm: x86.AROLB, 8082 reg: regInfo{ 8083 inputs: []inputInfo{ 8084 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8085 }, 8086 outputs: []outputInfo{ 8087 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8088 }, 8089 }, 8090 }, 8091 { 8092 name: "ADDLload", 8093 auxType: auxSymOff, 8094 argLen: 3, 8095 resultInArg0: true, 8096 clobberFlags: true, 8097 faultOnNilArg1: true, 8098 symEffect: SymRead, 8099 asm: x86.AADDL, 8100 reg: regInfo{ 8101 inputs: []inputInfo{ 8102 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8103 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8104 }, 8105 outputs: []outputInfo{ 8106 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8107 }, 8108 }, 8109 }, 8110 { 8111 name: "ADDQload", 8112 auxType: auxSymOff, 8113 argLen: 3, 8114 resultInArg0: true, 8115 clobberFlags: true, 8116 faultOnNilArg1: true, 8117 symEffect: SymRead, 8118 asm: x86.AADDQ, 8119 reg: regInfo{ 8120 inputs: []inputInfo{ 8121 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8122 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8123 }, 8124 outputs: []outputInfo{ 8125 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8126 }, 8127 }, 8128 }, 8129 { 8130 name: "SUBQload", 8131 auxType: auxSymOff, 8132 argLen: 3, 8133 resultInArg0: true, 8134 clobberFlags: true, 8135 faultOnNilArg1: true, 8136 symEffect: SymRead, 8137 asm: x86.ASUBQ, 8138 reg: regInfo{ 8139 inputs: []inputInfo{ 8140 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8141 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8142 }, 8143 outputs: []outputInfo{ 8144 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8145 }, 8146 }, 8147 }, 8148 { 8149 name: "SUBLload", 8150 auxType: auxSymOff, 8151 argLen: 3, 8152 resultInArg0: true, 8153 clobberFlags: true, 8154 faultOnNilArg1: true, 8155 symEffect: SymRead, 8156 asm: x86.ASUBL, 8157 reg: regInfo{ 8158 inputs: []inputInfo{ 8159 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8160 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8161 }, 8162 outputs: []outputInfo{ 8163 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8164 }, 8165 }, 8166 }, 8167 { 8168 name: "ANDLload", 8169 auxType: auxSymOff, 8170 argLen: 3, 8171 resultInArg0: true, 8172 clobberFlags: true, 8173 faultOnNilArg1: true, 8174 symEffect: SymRead, 8175 asm: x86.AANDL, 8176 reg: regInfo{ 8177 inputs: []inputInfo{ 8178 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8179 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8180 }, 8181 outputs: []outputInfo{ 8182 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8183 }, 8184 }, 8185 }, 8186 { 8187 name: "ANDQload", 8188 auxType: auxSymOff, 8189 argLen: 3, 8190 resultInArg0: true, 8191 clobberFlags: true, 8192 faultOnNilArg1: true, 8193 symEffect: SymRead, 8194 asm: x86.AANDQ, 8195 reg: regInfo{ 8196 inputs: []inputInfo{ 8197 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8198 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8199 }, 8200 outputs: []outputInfo{ 8201 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8202 }, 8203 }, 8204 }, 8205 { 8206 name: "ORQload", 8207 auxType: auxSymOff, 8208 argLen: 3, 8209 resultInArg0: true, 8210 clobberFlags: true, 8211 faultOnNilArg1: true, 8212 symEffect: SymRead, 8213 asm: x86.AORQ, 8214 reg: regInfo{ 8215 inputs: []inputInfo{ 8216 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8217 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8218 }, 8219 outputs: []outputInfo{ 8220 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8221 }, 8222 }, 8223 }, 8224 { 8225 name: "ORLload", 8226 auxType: auxSymOff, 8227 argLen: 3, 8228 resultInArg0: true, 8229 clobberFlags: true, 8230 faultOnNilArg1: true, 8231 symEffect: SymRead, 8232 asm: x86.AORL, 8233 reg: regInfo{ 8234 inputs: []inputInfo{ 8235 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8236 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8237 }, 8238 outputs: []outputInfo{ 8239 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8240 }, 8241 }, 8242 }, 8243 { 8244 name: "XORQload", 8245 auxType: auxSymOff, 8246 argLen: 3, 8247 resultInArg0: true, 8248 clobberFlags: true, 8249 faultOnNilArg1: true, 8250 symEffect: SymRead, 8251 asm: x86.AXORQ, 8252 reg: regInfo{ 8253 inputs: []inputInfo{ 8254 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8255 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8256 }, 8257 outputs: []outputInfo{ 8258 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8259 }, 8260 }, 8261 }, 8262 { 8263 name: "XORLload", 8264 auxType: auxSymOff, 8265 argLen: 3, 8266 resultInArg0: true, 8267 clobberFlags: true, 8268 faultOnNilArg1: true, 8269 symEffect: SymRead, 8270 asm: x86.AXORL, 8271 reg: regInfo{ 8272 inputs: []inputInfo{ 8273 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8274 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8275 }, 8276 outputs: []outputInfo{ 8277 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8278 }, 8279 }, 8280 }, 8281 { 8282 name: "ADDQmodify", 8283 auxType: auxSymOff, 8284 argLen: 3, 8285 clobberFlags: true, 8286 faultOnNilArg0: true, 8287 symEffect: SymRead | SymWrite, 8288 asm: x86.AADDQ, 8289 reg: regInfo{ 8290 inputs: []inputInfo{ 8291 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8292 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8293 }, 8294 }, 8295 }, 8296 { 8297 name: "SUBQmodify", 8298 auxType: auxSymOff, 8299 argLen: 3, 8300 clobberFlags: true, 8301 faultOnNilArg0: true, 8302 symEffect: SymRead | SymWrite, 8303 asm: x86.ASUBQ, 8304 reg: regInfo{ 8305 inputs: []inputInfo{ 8306 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8307 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8308 }, 8309 }, 8310 }, 8311 { 8312 name: "ANDQmodify", 8313 auxType: auxSymOff, 8314 argLen: 3, 8315 clobberFlags: true, 8316 faultOnNilArg0: true, 8317 symEffect: SymRead | SymWrite, 8318 asm: x86.AANDQ, 8319 reg: regInfo{ 8320 inputs: []inputInfo{ 8321 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8322 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8323 }, 8324 }, 8325 }, 8326 { 8327 name: "ORQmodify", 8328 auxType: auxSymOff, 8329 argLen: 3, 8330 clobberFlags: true, 8331 faultOnNilArg0: true, 8332 symEffect: SymRead | SymWrite, 8333 asm: x86.AORQ, 8334 reg: regInfo{ 8335 inputs: []inputInfo{ 8336 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8337 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8338 }, 8339 }, 8340 }, 8341 { 8342 name: "XORQmodify", 8343 auxType: auxSymOff, 8344 argLen: 3, 8345 clobberFlags: true, 8346 faultOnNilArg0: true, 8347 symEffect: SymRead | SymWrite, 8348 asm: x86.AXORQ, 8349 reg: regInfo{ 8350 inputs: []inputInfo{ 8351 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8352 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8353 }, 8354 }, 8355 }, 8356 { 8357 name: "ADDLmodify", 8358 auxType: auxSymOff, 8359 argLen: 3, 8360 clobberFlags: true, 8361 faultOnNilArg0: true, 8362 symEffect: SymRead | SymWrite, 8363 asm: x86.AADDL, 8364 reg: regInfo{ 8365 inputs: []inputInfo{ 8366 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8367 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8368 }, 8369 }, 8370 }, 8371 { 8372 name: "SUBLmodify", 8373 auxType: auxSymOff, 8374 argLen: 3, 8375 clobberFlags: true, 8376 faultOnNilArg0: true, 8377 symEffect: SymRead | SymWrite, 8378 asm: x86.ASUBL, 8379 reg: regInfo{ 8380 inputs: []inputInfo{ 8381 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8382 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8383 }, 8384 }, 8385 }, 8386 { 8387 name: "ANDLmodify", 8388 auxType: auxSymOff, 8389 argLen: 3, 8390 clobberFlags: true, 8391 faultOnNilArg0: true, 8392 symEffect: SymRead | SymWrite, 8393 asm: x86.AANDL, 8394 reg: regInfo{ 8395 inputs: []inputInfo{ 8396 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8397 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8398 }, 8399 }, 8400 }, 8401 { 8402 name: "ORLmodify", 8403 auxType: auxSymOff, 8404 argLen: 3, 8405 clobberFlags: true, 8406 faultOnNilArg0: true, 8407 symEffect: SymRead | SymWrite, 8408 asm: x86.AORL, 8409 reg: regInfo{ 8410 inputs: []inputInfo{ 8411 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8412 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8413 }, 8414 }, 8415 }, 8416 { 8417 name: "XORLmodify", 8418 auxType: auxSymOff, 8419 argLen: 3, 8420 clobberFlags: true, 8421 faultOnNilArg0: true, 8422 symEffect: SymRead | SymWrite, 8423 asm: x86.AXORL, 8424 reg: regInfo{ 8425 inputs: []inputInfo{ 8426 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8427 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8428 }, 8429 }, 8430 }, 8431 { 8432 name: "NEGQ", 8433 argLen: 1, 8434 resultInArg0: true, 8435 clobberFlags: true, 8436 asm: x86.ANEGQ, 8437 reg: regInfo{ 8438 inputs: []inputInfo{ 8439 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8440 }, 8441 outputs: []outputInfo{ 8442 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8443 }, 8444 }, 8445 }, 8446 { 8447 name: "NEGL", 8448 argLen: 1, 8449 resultInArg0: true, 8450 clobberFlags: true, 8451 asm: x86.ANEGL, 8452 reg: regInfo{ 8453 inputs: []inputInfo{ 8454 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8455 }, 8456 outputs: []outputInfo{ 8457 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8458 }, 8459 }, 8460 }, 8461 { 8462 name: "NOTQ", 8463 argLen: 1, 8464 resultInArg0: true, 8465 clobberFlags: true, 8466 asm: x86.ANOTQ, 8467 reg: regInfo{ 8468 inputs: []inputInfo{ 8469 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8470 }, 8471 outputs: []outputInfo{ 8472 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8473 }, 8474 }, 8475 }, 8476 { 8477 name: "NOTL", 8478 argLen: 1, 8479 resultInArg0: true, 8480 clobberFlags: true, 8481 asm: x86.ANOTL, 8482 reg: regInfo{ 8483 inputs: []inputInfo{ 8484 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8485 }, 8486 outputs: []outputInfo{ 8487 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8488 }, 8489 }, 8490 }, 8491 { 8492 name: "BSFQ", 8493 argLen: 1, 8494 asm: x86.ABSFQ, 8495 reg: regInfo{ 8496 inputs: []inputInfo{ 8497 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8498 }, 8499 outputs: []outputInfo{ 8500 {1, 0}, 8501 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8502 }, 8503 }, 8504 }, 8505 { 8506 name: "BSFL", 8507 argLen: 1, 8508 clobberFlags: true, 8509 asm: x86.ABSFL, 8510 reg: regInfo{ 8511 inputs: []inputInfo{ 8512 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8513 }, 8514 outputs: []outputInfo{ 8515 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8516 }, 8517 }, 8518 }, 8519 { 8520 name: "BSRQ", 8521 argLen: 1, 8522 asm: x86.ABSRQ, 8523 reg: regInfo{ 8524 inputs: []inputInfo{ 8525 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8526 }, 8527 outputs: []outputInfo{ 8528 {1, 0}, 8529 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8530 }, 8531 }, 8532 }, 8533 { 8534 name: "BSRL", 8535 argLen: 1, 8536 clobberFlags: true, 8537 asm: x86.ABSRL, 8538 reg: regInfo{ 8539 inputs: []inputInfo{ 8540 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8541 }, 8542 outputs: []outputInfo{ 8543 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8544 }, 8545 }, 8546 }, 8547 { 8548 name: "CMOVQEQ", 8549 argLen: 3, 8550 resultInArg0: true, 8551 asm: x86.ACMOVQEQ, 8552 reg: regInfo{ 8553 inputs: []inputInfo{ 8554 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8555 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8556 }, 8557 outputs: []outputInfo{ 8558 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8559 }, 8560 }, 8561 }, 8562 { 8563 name: "CMOVQNE", 8564 argLen: 3, 8565 resultInArg0: true, 8566 asm: x86.ACMOVQNE, 8567 reg: regInfo{ 8568 inputs: []inputInfo{ 8569 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8570 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8571 }, 8572 outputs: []outputInfo{ 8573 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8574 }, 8575 }, 8576 }, 8577 { 8578 name: "CMOVQLT", 8579 argLen: 3, 8580 resultInArg0: true, 8581 asm: x86.ACMOVQLT, 8582 reg: regInfo{ 8583 inputs: []inputInfo{ 8584 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8585 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8586 }, 8587 outputs: []outputInfo{ 8588 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8589 }, 8590 }, 8591 }, 8592 { 8593 name: "CMOVQGT", 8594 argLen: 3, 8595 resultInArg0: true, 8596 asm: x86.ACMOVQGT, 8597 reg: regInfo{ 8598 inputs: []inputInfo{ 8599 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8600 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8601 }, 8602 outputs: []outputInfo{ 8603 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8604 }, 8605 }, 8606 }, 8607 { 8608 name: "CMOVQLE", 8609 argLen: 3, 8610 resultInArg0: true, 8611 asm: x86.ACMOVQLE, 8612 reg: regInfo{ 8613 inputs: []inputInfo{ 8614 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8615 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8616 }, 8617 outputs: []outputInfo{ 8618 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8619 }, 8620 }, 8621 }, 8622 { 8623 name: "CMOVQGE", 8624 argLen: 3, 8625 resultInArg0: true, 8626 asm: x86.ACMOVQGE, 8627 reg: regInfo{ 8628 inputs: []inputInfo{ 8629 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8630 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8631 }, 8632 outputs: []outputInfo{ 8633 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8634 }, 8635 }, 8636 }, 8637 { 8638 name: "CMOVQLS", 8639 argLen: 3, 8640 resultInArg0: true, 8641 asm: x86.ACMOVQLS, 8642 reg: regInfo{ 8643 inputs: []inputInfo{ 8644 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8645 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8646 }, 8647 outputs: []outputInfo{ 8648 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8649 }, 8650 }, 8651 }, 8652 { 8653 name: "CMOVQHI", 8654 argLen: 3, 8655 resultInArg0: true, 8656 asm: x86.ACMOVQHI, 8657 reg: regInfo{ 8658 inputs: []inputInfo{ 8659 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8660 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8661 }, 8662 outputs: []outputInfo{ 8663 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8664 }, 8665 }, 8666 }, 8667 { 8668 name: "CMOVQCC", 8669 argLen: 3, 8670 resultInArg0: true, 8671 asm: x86.ACMOVQCC, 8672 reg: regInfo{ 8673 inputs: []inputInfo{ 8674 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8675 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8676 }, 8677 outputs: []outputInfo{ 8678 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8679 }, 8680 }, 8681 }, 8682 { 8683 name: "CMOVQCS", 8684 argLen: 3, 8685 resultInArg0: true, 8686 asm: x86.ACMOVQCS, 8687 reg: regInfo{ 8688 inputs: []inputInfo{ 8689 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8690 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8691 }, 8692 outputs: []outputInfo{ 8693 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8694 }, 8695 }, 8696 }, 8697 { 8698 name: "CMOVLEQ", 8699 argLen: 3, 8700 resultInArg0: true, 8701 asm: x86.ACMOVLEQ, 8702 reg: regInfo{ 8703 inputs: []inputInfo{ 8704 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8705 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8706 }, 8707 outputs: []outputInfo{ 8708 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8709 }, 8710 }, 8711 }, 8712 { 8713 name: "CMOVLNE", 8714 argLen: 3, 8715 resultInArg0: true, 8716 asm: x86.ACMOVLNE, 8717 reg: regInfo{ 8718 inputs: []inputInfo{ 8719 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8720 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8721 }, 8722 outputs: []outputInfo{ 8723 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8724 }, 8725 }, 8726 }, 8727 { 8728 name: "CMOVLLT", 8729 argLen: 3, 8730 resultInArg0: true, 8731 asm: x86.ACMOVLLT, 8732 reg: regInfo{ 8733 inputs: []inputInfo{ 8734 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8735 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8736 }, 8737 outputs: []outputInfo{ 8738 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8739 }, 8740 }, 8741 }, 8742 { 8743 name: "CMOVLGT", 8744 argLen: 3, 8745 resultInArg0: true, 8746 asm: x86.ACMOVLGT, 8747 reg: regInfo{ 8748 inputs: []inputInfo{ 8749 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8750 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8751 }, 8752 outputs: []outputInfo{ 8753 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8754 }, 8755 }, 8756 }, 8757 { 8758 name: "CMOVLLE", 8759 argLen: 3, 8760 resultInArg0: true, 8761 asm: x86.ACMOVLLE, 8762 reg: regInfo{ 8763 inputs: []inputInfo{ 8764 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8765 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8766 }, 8767 outputs: []outputInfo{ 8768 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8769 }, 8770 }, 8771 }, 8772 { 8773 name: "CMOVLGE", 8774 argLen: 3, 8775 resultInArg0: true, 8776 asm: x86.ACMOVLGE, 8777 reg: regInfo{ 8778 inputs: []inputInfo{ 8779 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8780 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8781 }, 8782 outputs: []outputInfo{ 8783 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8784 }, 8785 }, 8786 }, 8787 { 8788 name: "CMOVLLS", 8789 argLen: 3, 8790 resultInArg0: true, 8791 asm: x86.ACMOVLLS, 8792 reg: regInfo{ 8793 inputs: []inputInfo{ 8794 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8795 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8796 }, 8797 outputs: []outputInfo{ 8798 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8799 }, 8800 }, 8801 }, 8802 { 8803 name: "CMOVLHI", 8804 argLen: 3, 8805 resultInArg0: true, 8806 asm: x86.ACMOVLHI, 8807 reg: regInfo{ 8808 inputs: []inputInfo{ 8809 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8810 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8811 }, 8812 outputs: []outputInfo{ 8813 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8814 }, 8815 }, 8816 }, 8817 { 8818 name: "CMOVLCC", 8819 argLen: 3, 8820 resultInArg0: true, 8821 asm: x86.ACMOVLCC, 8822 reg: regInfo{ 8823 inputs: []inputInfo{ 8824 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8825 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8826 }, 8827 outputs: []outputInfo{ 8828 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8829 }, 8830 }, 8831 }, 8832 { 8833 name: "CMOVLCS", 8834 argLen: 3, 8835 resultInArg0: true, 8836 asm: x86.ACMOVLCS, 8837 reg: regInfo{ 8838 inputs: []inputInfo{ 8839 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8840 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8841 }, 8842 outputs: []outputInfo{ 8843 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8844 }, 8845 }, 8846 }, 8847 { 8848 name: "CMOVWEQ", 8849 argLen: 3, 8850 resultInArg0: true, 8851 asm: x86.ACMOVWEQ, 8852 reg: regInfo{ 8853 inputs: []inputInfo{ 8854 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8855 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8856 }, 8857 outputs: []outputInfo{ 8858 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8859 }, 8860 }, 8861 }, 8862 { 8863 name: "CMOVWNE", 8864 argLen: 3, 8865 resultInArg0: true, 8866 asm: x86.ACMOVWNE, 8867 reg: regInfo{ 8868 inputs: []inputInfo{ 8869 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8870 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8871 }, 8872 outputs: []outputInfo{ 8873 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8874 }, 8875 }, 8876 }, 8877 { 8878 name: "CMOVWLT", 8879 argLen: 3, 8880 resultInArg0: true, 8881 asm: x86.ACMOVWLT, 8882 reg: regInfo{ 8883 inputs: []inputInfo{ 8884 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8885 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8886 }, 8887 outputs: []outputInfo{ 8888 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8889 }, 8890 }, 8891 }, 8892 { 8893 name: "CMOVWGT", 8894 argLen: 3, 8895 resultInArg0: true, 8896 asm: x86.ACMOVWGT, 8897 reg: regInfo{ 8898 inputs: []inputInfo{ 8899 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8900 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8901 }, 8902 outputs: []outputInfo{ 8903 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8904 }, 8905 }, 8906 }, 8907 { 8908 name: "CMOVWLE", 8909 argLen: 3, 8910 resultInArg0: true, 8911 asm: x86.ACMOVWLE, 8912 reg: regInfo{ 8913 inputs: []inputInfo{ 8914 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8915 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8916 }, 8917 outputs: []outputInfo{ 8918 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8919 }, 8920 }, 8921 }, 8922 { 8923 name: "CMOVWGE", 8924 argLen: 3, 8925 resultInArg0: true, 8926 asm: x86.ACMOVWGE, 8927 reg: regInfo{ 8928 inputs: []inputInfo{ 8929 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8930 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8931 }, 8932 outputs: []outputInfo{ 8933 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8934 }, 8935 }, 8936 }, 8937 { 8938 name: "CMOVWLS", 8939 argLen: 3, 8940 resultInArg0: true, 8941 asm: x86.ACMOVWLS, 8942 reg: regInfo{ 8943 inputs: []inputInfo{ 8944 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8945 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8946 }, 8947 outputs: []outputInfo{ 8948 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8949 }, 8950 }, 8951 }, 8952 { 8953 name: "CMOVWHI", 8954 argLen: 3, 8955 resultInArg0: true, 8956 asm: x86.ACMOVWHI, 8957 reg: regInfo{ 8958 inputs: []inputInfo{ 8959 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8960 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8961 }, 8962 outputs: []outputInfo{ 8963 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8964 }, 8965 }, 8966 }, 8967 { 8968 name: "CMOVWCC", 8969 argLen: 3, 8970 resultInArg0: true, 8971 asm: x86.ACMOVWCC, 8972 reg: regInfo{ 8973 inputs: []inputInfo{ 8974 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8975 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8976 }, 8977 outputs: []outputInfo{ 8978 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8979 }, 8980 }, 8981 }, 8982 { 8983 name: "CMOVWCS", 8984 argLen: 3, 8985 resultInArg0: true, 8986 asm: x86.ACMOVWCS, 8987 reg: regInfo{ 8988 inputs: []inputInfo{ 8989 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8990 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8991 }, 8992 outputs: []outputInfo{ 8993 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8994 }, 8995 }, 8996 }, 8997 { 8998 name: "CMOVQEQF", 8999 argLen: 3, 9000 resultInArg0: true, 9001 asm: x86.ACMOVQNE, 9002 reg: regInfo{ 9003 inputs: []inputInfo{ 9004 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9005 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9006 }, 9007 clobbers: 1, // AX 9008 outputs: []outputInfo{ 9009 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9010 }, 9011 }, 9012 }, 9013 { 9014 name: "CMOVQNEF", 9015 argLen: 3, 9016 resultInArg0: true, 9017 asm: x86.ACMOVQNE, 9018 reg: regInfo{ 9019 inputs: []inputInfo{ 9020 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9021 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9022 }, 9023 outputs: []outputInfo{ 9024 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9025 }, 9026 }, 9027 }, 9028 { 9029 name: "CMOVQGTF", 9030 argLen: 3, 9031 resultInArg0: true, 9032 asm: x86.ACMOVQHI, 9033 reg: regInfo{ 9034 inputs: []inputInfo{ 9035 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9036 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9037 }, 9038 outputs: []outputInfo{ 9039 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9040 }, 9041 }, 9042 }, 9043 { 9044 name: "CMOVQGEF", 9045 argLen: 3, 9046 resultInArg0: true, 9047 asm: x86.ACMOVQCC, 9048 reg: regInfo{ 9049 inputs: []inputInfo{ 9050 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9051 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9052 }, 9053 outputs: []outputInfo{ 9054 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9055 }, 9056 }, 9057 }, 9058 { 9059 name: "CMOVLEQF", 9060 argLen: 3, 9061 resultInArg0: true, 9062 asm: x86.ACMOVLNE, 9063 reg: regInfo{ 9064 inputs: []inputInfo{ 9065 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9066 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9067 }, 9068 clobbers: 1, // AX 9069 outputs: []outputInfo{ 9070 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9071 }, 9072 }, 9073 }, 9074 { 9075 name: "CMOVLNEF", 9076 argLen: 3, 9077 resultInArg0: true, 9078 asm: x86.ACMOVLNE, 9079 reg: regInfo{ 9080 inputs: []inputInfo{ 9081 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9082 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9083 }, 9084 outputs: []outputInfo{ 9085 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9086 }, 9087 }, 9088 }, 9089 { 9090 name: "CMOVLGTF", 9091 argLen: 3, 9092 resultInArg0: true, 9093 asm: x86.ACMOVLHI, 9094 reg: regInfo{ 9095 inputs: []inputInfo{ 9096 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9097 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9098 }, 9099 outputs: []outputInfo{ 9100 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9101 }, 9102 }, 9103 }, 9104 { 9105 name: "CMOVLGEF", 9106 argLen: 3, 9107 resultInArg0: true, 9108 asm: x86.ACMOVLCC, 9109 reg: regInfo{ 9110 inputs: []inputInfo{ 9111 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9112 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9113 }, 9114 outputs: []outputInfo{ 9115 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9116 }, 9117 }, 9118 }, 9119 { 9120 name: "CMOVWEQF", 9121 argLen: 3, 9122 resultInArg0: true, 9123 asm: x86.ACMOVWNE, 9124 reg: regInfo{ 9125 inputs: []inputInfo{ 9126 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9127 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9128 }, 9129 clobbers: 1, // AX 9130 outputs: []outputInfo{ 9131 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9132 }, 9133 }, 9134 }, 9135 { 9136 name: "CMOVWNEF", 9137 argLen: 3, 9138 resultInArg0: true, 9139 asm: x86.ACMOVWNE, 9140 reg: regInfo{ 9141 inputs: []inputInfo{ 9142 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9143 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9144 }, 9145 outputs: []outputInfo{ 9146 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9147 }, 9148 }, 9149 }, 9150 { 9151 name: "CMOVWGTF", 9152 argLen: 3, 9153 resultInArg0: true, 9154 asm: x86.ACMOVWHI, 9155 reg: regInfo{ 9156 inputs: []inputInfo{ 9157 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9158 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9159 }, 9160 outputs: []outputInfo{ 9161 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9162 }, 9163 }, 9164 }, 9165 { 9166 name: "CMOVWGEF", 9167 argLen: 3, 9168 resultInArg0: true, 9169 asm: x86.ACMOVWCC, 9170 reg: regInfo{ 9171 inputs: []inputInfo{ 9172 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9173 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9174 }, 9175 outputs: []outputInfo{ 9176 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9177 }, 9178 }, 9179 }, 9180 { 9181 name: "BSWAPQ", 9182 argLen: 1, 9183 resultInArg0: true, 9184 clobberFlags: true, 9185 asm: x86.ABSWAPQ, 9186 reg: regInfo{ 9187 inputs: []inputInfo{ 9188 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9189 }, 9190 outputs: []outputInfo{ 9191 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9192 }, 9193 }, 9194 }, 9195 { 9196 name: "BSWAPL", 9197 argLen: 1, 9198 resultInArg0: true, 9199 clobberFlags: true, 9200 asm: x86.ABSWAPL, 9201 reg: regInfo{ 9202 inputs: []inputInfo{ 9203 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9204 }, 9205 outputs: []outputInfo{ 9206 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9207 }, 9208 }, 9209 }, 9210 { 9211 name: "POPCNTQ", 9212 argLen: 1, 9213 clobberFlags: true, 9214 asm: x86.APOPCNTQ, 9215 reg: regInfo{ 9216 inputs: []inputInfo{ 9217 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9218 }, 9219 outputs: []outputInfo{ 9220 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9221 }, 9222 }, 9223 }, 9224 { 9225 name: "POPCNTL", 9226 argLen: 1, 9227 clobberFlags: true, 9228 asm: x86.APOPCNTL, 9229 reg: regInfo{ 9230 inputs: []inputInfo{ 9231 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9232 }, 9233 outputs: []outputInfo{ 9234 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9235 }, 9236 }, 9237 }, 9238 { 9239 name: "SQRTSD", 9240 argLen: 1, 9241 asm: x86.ASQRTSD, 9242 reg: regInfo{ 9243 inputs: []inputInfo{ 9244 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9245 }, 9246 outputs: []outputInfo{ 9247 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9248 }, 9249 }, 9250 }, 9251 { 9252 name: "ROUNDSD", 9253 auxType: auxInt8, 9254 argLen: 1, 9255 asm: x86.AROUNDSD, 9256 reg: regInfo{ 9257 inputs: []inputInfo{ 9258 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9259 }, 9260 outputs: []outputInfo{ 9261 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9262 }, 9263 }, 9264 }, 9265 { 9266 name: "SBBQcarrymask", 9267 argLen: 1, 9268 asm: x86.ASBBQ, 9269 reg: regInfo{ 9270 outputs: []outputInfo{ 9271 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9272 }, 9273 }, 9274 }, 9275 { 9276 name: "SBBLcarrymask", 9277 argLen: 1, 9278 asm: x86.ASBBL, 9279 reg: regInfo{ 9280 outputs: []outputInfo{ 9281 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9282 }, 9283 }, 9284 }, 9285 { 9286 name: "SETEQ", 9287 argLen: 1, 9288 asm: x86.ASETEQ, 9289 reg: regInfo{ 9290 outputs: []outputInfo{ 9291 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9292 }, 9293 }, 9294 }, 9295 { 9296 name: "SETNE", 9297 argLen: 1, 9298 asm: x86.ASETNE, 9299 reg: regInfo{ 9300 outputs: []outputInfo{ 9301 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9302 }, 9303 }, 9304 }, 9305 { 9306 name: "SETL", 9307 argLen: 1, 9308 asm: x86.ASETLT, 9309 reg: regInfo{ 9310 outputs: []outputInfo{ 9311 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9312 }, 9313 }, 9314 }, 9315 { 9316 name: "SETLE", 9317 argLen: 1, 9318 asm: x86.ASETLE, 9319 reg: regInfo{ 9320 outputs: []outputInfo{ 9321 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9322 }, 9323 }, 9324 }, 9325 { 9326 name: "SETG", 9327 argLen: 1, 9328 asm: x86.ASETGT, 9329 reg: regInfo{ 9330 outputs: []outputInfo{ 9331 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9332 }, 9333 }, 9334 }, 9335 { 9336 name: "SETGE", 9337 argLen: 1, 9338 asm: x86.ASETGE, 9339 reg: regInfo{ 9340 outputs: []outputInfo{ 9341 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9342 }, 9343 }, 9344 }, 9345 { 9346 name: "SETB", 9347 argLen: 1, 9348 asm: x86.ASETCS, 9349 reg: regInfo{ 9350 outputs: []outputInfo{ 9351 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9352 }, 9353 }, 9354 }, 9355 { 9356 name: "SETBE", 9357 argLen: 1, 9358 asm: x86.ASETLS, 9359 reg: regInfo{ 9360 outputs: []outputInfo{ 9361 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9362 }, 9363 }, 9364 }, 9365 { 9366 name: "SETA", 9367 argLen: 1, 9368 asm: x86.ASETHI, 9369 reg: regInfo{ 9370 outputs: []outputInfo{ 9371 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9372 }, 9373 }, 9374 }, 9375 { 9376 name: "SETAE", 9377 argLen: 1, 9378 asm: x86.ASETCC, 9379 reg: regInfo{ 9380 outputs: []outputInfo{ 9381 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9382 }, 9383 }, 9384 }, 9385 { 9386 name: "SETO", 9387 argLen: 1, 9388 asm: x86.ASETOS, 9389 reg: regInfo{ 9390 outputs: []outputInfo{ 9391 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9392 }, 9393 }, 9394 }, 9395 { 9396 name: "SETEQstore", 9397 auxType: auxSymOff, 9398 argLen: 3, 9399 faultOnNilArg0: true, 9400 symEffect: SymWrite, 9401 asm: x86.ASETEQ, 9402 reg: regInfo{ 9403 inputs: []inputInfo{ 9404 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9405 }, 9406 }, 9407 }, 9408 { 9409 name: "SETNEstore", 9410 auxType: auxSymOff, 9411 argLen: 3, 9412 faultOnNilArg0: true, 9413 symEffect: SymWrite, 9414 asm: x86.ASETNE, 9415 reg: regInfo{ 9416 inputs: []inputInfo{ 9417 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9418 }, 9419 }, 9420 }, 9421 { 9422 name: "SETLstore", 9423 auxType: auxSymOff, 9424 argLen: 3, 9425 faultOnNilArg0: true, 9426 symEffect: SymWrite, 9427 asm: x86.ASETLT, 9428 reg: regInfo{ 9429 inputs: []inputInfo{ 9430 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9431 }, 9432 }, 9433 }, 9434 { 9435 name: "SETLEstore", 9436 auxType: auxSymOff, 9437 argLen: 3, 9438 faultOnNilArg0: true, 9439 symEffect: SymWrite, 9440 asm: x86.ASETLE, 9441 reg: regInfo{ 9442 inputs: []inputInfo{ 9443 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9444 }, 9445 }, 9446 }, 9447 { 9448 name: "SETGstore", 9449 auxType: auxSymOff, 9450 argLen: 3, 9451 faultOnNilArg0: true, 9452 symEffect: SymWrite, 9453 asm: x86.ASETGT, 9454 reg: regInfo{ 9455 inputs: []inputInfo{ 9456 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9457 }, 9458 }, 9459 }, 9460 { 9461 name: "SETGEstore", 9462 auxType: auxSymOff, 9463 argLen: 3, 9464 faultOnNilArg0: true, 9465 symEffect: SymWrite, 9466 asm: x86.ASETGE, 9467 reg: regInfo{ 9468 inputs: []inputInfo{ 9469 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9470 }, 9471 }, 9472 }, 9473 { 9474 name: "SETBstore", 9475 auxType: auxSymOff, 9476 argLen: 3, 9477 faultOnNilArg0: true, 9478 symEffect: SymWrite, 9479 asm: x86.ASETCS, 9480 reg: regInfo{ 9481 inputs: []inputInfo{ 9482 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9483 }, 9484 }, 9485 }, 9486 { 9487 name: "SETBEstore", 9488 auxType: auxSymOff, 9489 argLen: 3, 9490 faultOnNilArg0: true, 9491 symEffect: SymWrite, 9492 asm: x86.ASETLS, 9493 reg: regInfo{ 9494 inputs: []inputInfo{ 9495 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9496 }, 9497 }, 9498 }, 9499 { 9500 name: "SETAstore", 9501 auxType: auxSymOff, 9502 argLen: 3, 9503 faultOnNilArg0: true, 9504 symEffect: SymWrite, 9505 asm: x86.ASETHI, 9506 reg: regInfo{ 9507 inputs: []inputInfo{ 9508 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9509 }, 9510 }, 9511 }, 9512 { 9513 name: "SETAEstore", 9514 auxType: auxSymOff, 9515 argLen: 3, 9516 faultOnNilArg0: true, 9517 symEffect: SymWrite, 9518 asm: x86.ASETCC, 9519 reg: regInfo{ 9520 inputs: []inputInfo{ 9521 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9522 }, 9523 }, 9524 }, 9525 { 9526 name: "SETEQF", 9527 argLen: 1, 9528 clobberFlags: true, 9529 asm: x86.ASETEQ, 9530 reg: regInfo{ 9531 clobbers: 1, // AX 9532 outputs: []outputInfo{ 9533 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9534 }, 9535 }, 9536 }, 9537 { 9538 name: "SETNEF", 9539 argLen: 1, 9540 clobberFlags: true, 9541 asm: x86.ASETNE, 9542 reg: regInfo{ 9543 clobbers: 1, // AX 9544 outputs: []outputInfo{ 9545 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9546 }, 9547 }, 9548 }, 9549 { 9550 name: "SETORD", 9551 argLen: 1, 9552 asm: x86.ASETPC, 9553 reg: regInfo{ 9554 outputs: []outputInfo{ 9555 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9556 }, 9557 }, 9558 }, 9559 { 9560 name: "SETNAN", 9561 argLen: 1, 9562 asm: x86.ASETPS, 9563 reg: regInfo{ 9564 outputs: []outputInfo{ 9565 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9566 }, 9567 }, 9568 }, 9569 { 9570 name: "SETGF", 9571 argLen: 1, 9572 asm: x86.ASETHI, 9573 reg: regInfo{ 9574 outputs: []outputInfo{ 9575 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9576 }, 9577 }, 9578 }, 9579 { 9580 name: "SETGEF", 9581 argLen: 1, 9582 asm: x86.ASETCC, 9583 reg: regInfo{ 9584 outputs: []outputInfo{ 9585 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9586 }, 9587 }, 9588 }, 9589 { 9590 name: "MOVBQSX", 9591 argLen: 1, 9592 asm: x86.AMOVBQSX, 9593 reg: regInfo{ 9594 inputs: []inputInfo{ 9595 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9596 }, 9597 outputs: []outputInfo{ 9598 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9599 }, 9600 }, 9601 }, 9602 { 9603 name: "MOVBQZX", 9604 argLen: 1, 9605 asm: x86.AMOVBLZX, 9606 reg: regInfo{ 9607 inputs: []inputInfo{ 9608 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9609 }, 9610 outputs: []outputInfo{ 9611 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9612 }, 9613 }, 9614 }, 9615 { 9616 name: "MOVWQSX", 9617 argLen: 1, 9618 asm: x86.AMOVWQSX, 9619 reg: regInfo{ 9620 inputs: []inputInfo{ 9621 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9622 }, 9623 outputs: []outputInfo{ 9624 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9625 }, 9626 }, 9627 }, 9628 { 9629 name: "MOVWQZX", 9630 argLen: 1, 9631 asm: x86.AMOVWLZX, 9632 reg: regInfo{ 9633 inputs: []inputInfo{ 9634 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9635 }, 9636 outputs: []outputInfo{ 9637 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9638 }, 9639 }, 9640 }, 9641 { 9642 name: "MOVLQSX", 9643 argLen: 1, 9644 asm: x86.AMOVLQSX, 9645 reg: regInfo{ 9646 inputs: []inputInfo{ 9647 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9648 }, 9649 outputs: []outputInfo{ 9650 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9651 }, 9652 }, 9653 }, 9654 { 9655 name: "MOVLQZX", 9656 argLen: 1, 9657 asm: x86.AMOVL, 9658 reg: regInfo{ 9659 inputs: []inputInfo{ 9660 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9661 }, 9662 outputs: []outputInfo{ 9663 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9664 }, 9665 }, 9666 }, 9667 { 9668 name: "MOVLconst", 9669 auxType: auxInt32, 9670 argLen: 0, 9671 rematerializeable: true, 9672 asm: x86.AMOVL, 9673 reg: regInfo{ 9674 outputs: []outputInfo{ 9675 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9676 }, 9677 }, 9678 }, 9679 { 9680 name: "MOVQconst", 9681 auxType: auxInt64, 9682 argLen: 0, 9683 rematerializeable: true, 9684 asm: x86.AMOVQ, 9685 reg: regInfo{ 9686 outputs: []outputInfo{ 9687 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9688 }, 9689 }, 9690 }, 9691 { 9692 name: "CVTTSD2SL", 9693 argLen: 1, 9694 asm: x86.ACVTTSD2SL, 9695 reg: regInfo{ 9696 inputs: []inputInfo{ 9697 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9698 }, 9699 outputs: []outputInfo{ 9700 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9701 }, 9702 }, 9703 }, 9704 { 9705 name: "CVTTSD2SQ", 9706 argLen: 1, 9707 asm: x86.ACVTTSD2SQ, 9708 reg: regInfo{ 9709 inputs: []inputInfo{ 9710 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9711 }, 9712 outputs: []outputInfo{ 9713 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9714 }, 9715 }, 9716 }, 9717 { 9718 name: "CVTTSS2SL", 9719 argLen: 1, 9720 asm: x86.ACVTTSS2SL, 9721 reg: regInfo{ 9722 inputs: []inputInfo{ 9723 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9724 }, 9725 outputs: []outputInfo{ 9726 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9727 }, 9728 }, 9729 }, 9730 { 9731 name: "CVTTSS2SQ", 9732 argLen: 1, 9733 asm: x86.ACVTTSS2SQ, 9734 reg: regInfo{ 9735 inputs: []inputInfo{ 9736 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9737 }, 9738 outputs: []outputInfo{ 9739 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9740 }, 9741 }, 9742 }, 9743 { 9744 name: "CVTSL2SS", 9745 argLen: 1, 9746 asm: x86.ACVTSL2SS, 9747 reg: regInfo{ 9748 inputs: []inputInfo{ 9749 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9750 }, 9751 outputs: []outputInfo{ 9752 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9753 }, 9754 }, 9755 }, 9756 { 9757 name: "CVTSL2SD", 9758 argLen: 1, 9759 asm: x86.ACVTSL2SD, 9760 reg: regInfo{ 9761 inputs: []inputInfo{ 9762 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9763 }, 9764 outputs: []outputInfo{ 9765 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9766 }, 9767 }, 9768 }, 9769 { 9770 name: "CVTSQ2SS", 9771 argLen: 1, 9772 asm: x86.ACVTSQ2SS, 9773 reg: regInfo{ 9774 inputs: []inputInfo{ 9775 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9776 }, 9777 outputs: []outputInfo{ 9778 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9779 }, 9780 }, 9781 }, 9782 { 9783 name: "CVTSQ2SD", 9784 argLen: 1, 9785 asm: x86.ACVTSQ2SD, 9786 reg: regInfo{ 9787 inputs: []inputInfo{ 9788 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9789 }, 9790 outputs: []outputInfo{ 9791 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9792 }, 9793 }, 9794 }, 9795 { 9796 name: "CVTSD2SS", 9797 argLen: 1, 9798 asm: x86.ACVTSD2SS, 9799 reg: regInfo{ 9800 inputs: []inputInfo{ 9801 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9802 }, 9803 outputs: []outputInfo{ 9804 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9805 }, 9806 }, 9807 }, 9808 { 9809 name: "CVTSS2SD", 9810 argLen: 1, 9811 asm: x86.ACVTSS2SD, 9812 reg: regInfo{ 9813 inputs: []inputInfo{ 9814 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9815 }, 9816 outputs: []outputInfo{ 9817 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9818 }, 9819 }, 9820 }, 9821 { 9822 name: "MOVQi2f", 9823 argLen: 1, 9824 reg: regInfo{ 9825 inputs: []inputInfo{ 9826 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9827 }, 9828 outputs: []outputInfo{ 9829 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9830 }, 9831 }, 9832 }, 9833 { 9834 name: "MOVQf2i", 9835 argLen: 1, 9836 reg: regInfo{ 9837 inputs: []inputInfo{ 9838 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9839 }, 9840 outputs: []outputInfo{ 9841 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9842 }, 9843 }, 9844 }, 9845 { 9846 name: "MOVLi2f", 9847 argLen: 1, 9848 reg: regInfo{ 9849 inputs: []inputInfo{ 9850 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9851 }, 9852 outputs: []outputInfo{ 9853 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9854 }, 9855 }, 9856 }, 9857 { 9858 name: "MOVLf2i", 9859 argLen: 1, 9860 reg: regInfo{ 9861 inputs: []inputInfo{ 9862 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9863 }, 9864 outputs: []outputInfo{ 9865 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9866 }, 9867 }, 9868 }, 9869 { 9870 name: "PXOR", 9871 argLen: 2, 9872 commutative: true, 9873 resultInArg0: true, 9874 asm: x86.APXOR, 9875 reg: regInfo{ 9876 inputs: []inputInfo{ 9877 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9878 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9879 }, 9880 outputs: []outputInfo{ 9881 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9882 }, 9883 }, 9884 }, 9885 { 9886 name: "LEAQ", 9887 auxType: auxSymOff, 9888 argLen: 1, 9889 rematerializeable: true, 9890 symEffect: SymAddr, 9891 asm: x86.ALEAQ, 9892 reg: regInfo{ 9893 inputs: []inputInfo{ 9894 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9895 }, 9896 outputs: []outputInfo{ 9897 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9898 }, 9899 }, 9900 }, 9901 { 9902 name: "LEAL", 9903 auxType: auxSymOff, 9904 argLen: 1, 9905 rematerializeable: true, 9906 symEffect: SymAddr, 9907 asm: x86.ALEAL, 9908 reg: regInfo{ 9909 inputs: []inputInfo{ 9910 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9911 }, 9912 outputs: []outputInfo{ 9913 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9914 }, 9915 }, 9916 }, 9917 { 9918 name: "LEAW", 9919 auxType: auxSymOff, 9920 argLen: 1, 9921 rematerializeable: true, 9922 symEffect: SymAddr, 9923 asm: x86.ALEAW, 9924 reg: regInfo{ 9925 inputs: []inputInfo{ 9926 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9927 }, 9928 outputs: []outputInfo{ 9929 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9930 }, 9931 }, 9932 }, 9933 { 9934 name: "LEAQ1", 9935 auxType: auxSymOff, 9936 argLen: 2, 9937 commutative: true, 9938 symEffect: SymAddr, 9939 asm: x86.ALEAQ, 9940 reg: regInfo{ 9941 inputs: []inputInfo{ 9942 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9943 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9944 }, 9945 outputs: []outputInfo{ 9946 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9947 }, 9948 }, 9949 }, 9950 { 9951 name: "LEAL1", 9952 auxType: auxSymOff, 9953 argLen: 2, 9954 commutative: true, 9955 symEffect: SymAddr, 9956 asm: x86.ALEAL, 9957 reg: regInfo{ 9958 inputs: []inputInfo{ 9959 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9960 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9961 }, 9962 outputs: []outputInfo{ 9963 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9964 }, 9965 }, 9966 }, 9967 { 9968 name: "LEAW1", 9969 auxType: auxSymOff, 9970 argLen: 2, 9971 commutative: true, 9972 symEffect: SymAddr, 9973 asm: x86.ALEAW, 9974 reg: regInfo{ 9975 inputs: []inputInfo{ 9976 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9977 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9978 }, 9979 outputs: []outputInfo{ 9980 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9981 }, 9982 }, 9983 }, 9984 { 9985 name: "LEAQ2", 9986 auxType: auxSymOff, 9987 argLen: 2, 9988 symEffect: SymAddr, 9989 asm: x86.ALEAQ, 9990 reg: regInfo{ 9991 inputs: []inputInfo{ 9992 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9993 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9994 }, 9995 outputs: []outputInfo{ 9996 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9997 }, 9998 }, 9999 }, 10000 { 10001 name: "LEAL2", 10002 auxType: auxSymOff, 10003 argLen: 2, 10004 symEffect: SymAddr, 10005 asm: x86.ALEAL, 10006 reg: regInfo{ 10007 inputs: []inputInfo{ 10008 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10009 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10010 }, 10011 outputs: []outputInfo{ 10012 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10013 }, 10014 }, 10015 }, 10016 { 10017 name: "LEAW2", 10018 auxType: auxSymOff, 10019 argLen: 2, 10020 symEffect: SymAddr, 10021 asm: x86.ALEAW, 10022 reg: regInfo{ 10023 inputs: []inputInfo{ 10024 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10025 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10026 }, 10027 outputs: []outputInfo{ 10028 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10029 }, 10030 }, 10031 }, 10032 { 10033 name: "LEAQ4", 10034 auxType: auxSymOff, 10035 argLen: 2, 10036 symEffect: SymAddr, 10037 asm: x86.ALEAQ, 10038 reg: regInfo{ 10039 inputs: []inputInfo{ 10040 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10041 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10042 }, 10043 outputs: []outputInfo{ 10044 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10045 }, 10046 }, 10047 }, 10048 { 10049 name: "LEAL4", 10050 auxType: auxSymOff, 10051 argLen: 2, 10052 symEffect: SymAddr, 10053 asm: x86.ALEAL, 10054 reg: regInfo{ 10055 inputs: []inputInfo{ 10056 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10057 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10058 }, 10059 outputs: []outputInfo{ 10060 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10061 }, 10062 }, 10063 }, 10064 { 10065 name: "LEAW4", 10066 auxType: auxSymOff, 10067 argLen: 2, 10068 symEffect: SymAddr, 10069 asm: x86.ALEAW, 10070 reg: regInfo{ 10071 inputs: []inputInfo{ 10072 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10073 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10074 }, 10075 outputs: []outputInfo{ 10076 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10077 }, 10078 }, 10079 }, 10080 { 10081 name: "LEAQ8", 10082 auxType: auxSymOff, 10083 argLen: 2, 10084 symEffect: SymAddr, 10085 asm: x86.ALEAQ, 10086 reg: regInfo{ 10087 inputs: []inputInfo{ 10088 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10089 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10090 }, 10091 outputs: []outputInfo{ 10092 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10093 }, 10094 }, 10095 }, 10096 { 10097 name: "LEAL8", 10098 auxType: auxSymOff, 10099 argLen: 2, 10100 symEffect: SymAddr, 10101 asm: x86.ALEAL, 10102 reg: regInfo{ 10103 inputs: []inputInfo{ 10104 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10105 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10106 }, 10107 outputs: []outputInfo{ 10108 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10109 }, 10110 }, 10111 }, 10112 { 10113 name: "LEAW8", 10114 auxType: auxSymOff, 10115 argLen: 2, 10116 symEffect: SymAddr, 10117 asm: x86.ALEAW, 10118 reg: regInfo{ 10119 inputs: []inputInfo{ 10120 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10121 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10122 }, 10123 outputs: []outputInfo{ 10124 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10125 }, 10126 }, 10127 }, 10128 { 10129 name: "MOVBload", 10130 auxType: auxSymOff, 10131 argLen: 2, 10132 faultOnNilArg0: true, 10133 symEffect: SymRead, 10134 asm: x86.AMOVBLZX, 10135 reg: regInfo{ 10136 inputs: []inputInfo{ 10137 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10138 }, 10139 outputs: []outputInfo{ 10140 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10141 }, 10142 }, 10143 }, 10144 { 10145 name: "MOVBQSXload", 10146 auxType: auxSymOff, 10147 argLen: 2, 10148 faultOnNilArg0: true, 10149 symEffect: SymRead, 10150 asm: x86.AMOVBQSX, 10151 reg: regInfo{ 10152 inputs: []inputInfo{ 10153 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10154 }, 10155 outputs: []outputInfo{ 10156 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10157 }, 10158 }, 10159 }, 10160 { 10161 name: "MOVWload", 10162 auxType: auxSymOff, 10163 argLen: 2, 10164 faultOnNilArg0: true, 10165 symEffect: SymRead, 10166 asm: x86.AMOVWLZX, 10167 reg: regInfo{ 10168 inputs: []inputInfo{ 10169 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10170 }, 10171 outputs: []outputInfo{ 10172 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10173 }, 10174 }, 10175 }, 10176 { 10177 name: "MOVWQSXload", 10178 auxType: auxSymOff, 10179 argLen: 2, 10180 faultOnNilArg0: true, 10181 symEffect: SymRead, 10182 asm: x86.AMOVWQSX, 10183 reg: regInfo{ 10184 inputs: []inputInfo{ 10185 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10186 }, 10187 outputs: []outputInfo{ 10188 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10189 }, 10190 }, 10191 }, 10192 { 10193 name: "MOVLload", 10194 auxType: auxSymOff, 10195 argLen: 2, 10196 faultOnNilArg0: true, 10197 symEffect: SymRead, 10198 asm: x86.AMOVL, 10199 reg: regInfo{ 10200 inputs: []inputInfo{ 10201 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10202 }, 10203 outputs: []outputInfo{ 10204 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10205 }, 10206 }, 10207 }, 10208 { 10209 name: "MOVLQSXload", 10210 auxType: auxSymOff, 10211 argLen: 2, 10212 faultOnNilArg0: true, 10213 symEffect: SymRead, 10214 asm: x86.AMOVLQSX, 10215 reg: regInfo{ 10216 inputs: []inputInfo{ 10217 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10218 }, 10219 outputs: []outputInfo{ 10220 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10221 }, 10222 }, 10223 }, 10224 { 10225 name: "MOVQload", 10226 auxType: auxSymOff, 10227 argLen: 2, 10228 faultOnNilArg0: true, 10229 symEffect: SymRead, 10230 asm: x86.AMOVQ, 10231 reg: regInfo{ 10232 inputs: []inputInfo{ 10233 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10234 }, 10235 outputs: []outputInfo{ 10236 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10237 }, 10238 }, 10239 }, 10240 { 10241 name: "MOVBstore", 10242 auxType: auxSymOff, 10243 argLen: 3, 10244 faultOnNilArg0: true, 10245 symEffect: SymWrite, 10246 asm: x86.AMOVB, 10247 reg: regInfo{ 10248 inputs: []inputInfo{ 10249 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10250 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10251 }, 10252 }, 10253 }, 10254 { 10255 name: "MOVWstore", 10256 auxType: auxSymOff, 10257 argLen: 3, 10258 faultOnNilArg0: true, 10259 symEffect: SymWrite, 10260 asm: x86.AMOVW, 10261 reg: regInfo{ 10262 inputs: []inputInfo{ 10263 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10264 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10265 }, 10266 }, 10267 }, 10268 { 10269 name: "MOVLstore", 10270 auxType: auxSymOff, 10271 argLen: 3, 10272 faultOnNilArg0: true, 10273 symEffect: SymWrite, 10274 asm: x86.AMOVL, 10275 reg: regInfo{ 10276 inputs: []inputInfo{ 10277 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10278 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10279 }, 10280 }, 10281 }, 10282 { 10283 name: "MOVQstore", 10284 auxType: auxSymOff, 10285 argLen: 3, 10286 faultOnNilArg0: true, 10287 symEffect: SymWrite, 10288 asm: x86.AMOVQ, 10289 reg: regInfo{ 10290 inputs: []inputInfo{ 10291 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10292 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10293 }, 10294 }, 10295 }, 10296 { 10297 name: "MOVOload", 10298 auxType: auxSymOff, 10299 argLen: 2, 10300 faultOnNilArg0: true, 10301 symEffect: SymRead, 10302 asm: x86.AMOVUPS, 10303 reg: regInfo{ 10304 inputs: []inputInfo{ 10305 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10306 }, 10307 outputs: []outputInfo{ 10308 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10309 }, 10310 }, 10311 }, 10312 { 10313 name: "MOVOstore", 10314 auxType: auxSymOff, 10315 argLen: 3, 10316 faultOnNilArg0: true, 10317 symEffect: SymWrite, 10318 asm: x86.AMOVUPS, 10319 reg: regInfo{ 10320 inputs: []inputInfo{ 10321 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10322 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10323 }, 10324 }, 10325 }, 10326 { 10327 name: "MOVBloadidx1", 10328 auxType: auxSymOff, 10329 argLen: 3, 10330 commutative: true, 10331 symEffect: SymRead, 10332 asm: x86.AMOVBLZX, 10333 reg: regInfo{ 10334 inputs: []inputInfo{ 10335 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10336 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10337 }, 10338 outputs: []outputInfo{ 10339 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10340 }, 10341 }, 10342 }, 10343 { 10344 name: "MOVWloadidx1", 10345 auxType: auxSymOff, 10346 argLen: 3, 10347 commutative: true, 10348 symEffect: SymRead, 10349 asm: x86.AMOVWLZX, 10350 reg: regInfo{ 10351 inputs: []inputInfo{ 10352 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10353 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10354 }, 10355 outputs: []outputInfo{ 10356 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10357 }, 10358 }, 10359 }, 10360 { 10361 name: "MOVWloadidx2", 10362 auxType: auxSymOff, 10363 argLen: 3, 10364 symEffect: SymRead, 10365 asm: x86.AMOVWLZX, 10366 reg: regInfo{ 10367 inputs: []inputInfo{ 10368 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10369 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10370 }, 10371 outputs: []outputInfo{ 10372 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10373 }, 10374 }, 10375 }, 10376 { 10377 name: "MOVLloadidx1", 10378 auxType: auxSymOff, 10379 argLen: 3, 10380 commutative: true, 10381 symEffect: SymRead, 10382 asm: x86.AMOVL, 10383 reg: regInfo{ 10384 inputs: []inputInfo{ 10385 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10386 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10387 }, 10388 outputs: []outputInfo{ 10389 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10390 }, 10391 }, 10392 }, 10393 { 10394 name: "MOVLloadidx4", 10395 auxType: auxSymOff, 10396 argLen: 3, 10397 symEffect: SymRead, 10398 asm: x86.AMOVL, 10399 reg: regInfo{ 10400 inputs: []inputInfo{ 10401 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10402 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10403 }, 10404 outputs: []outputInfo{ 10405 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10406 }, 10407 }, 10408 }, 10409 { 10410 name: "MOVLloadidx8", 10411 auxType: auxSymOff, 10412 argLen: 3, 10413 symEffect: SymRead, 10414 asm: x86.AMOVL, 10415 reg: regInfo{ 10416 inputs: []inputInfo{ 10417 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10418 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10419 }, 10420 outputs: []outputInfo{ 10421 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10422 }, 10423 }, 10424 }, 10425 { 10426 name: "MOVQloadidx1", 10427 auxType: auxSymOff, 10428 argLen: 3, 10429 commutative: true, 10430 symEffect: SymRead, 10431 asm: x86.AMOVQ, 10432 reg: regInfo{ 10433 inputs: []inputInfo{ 10434 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10435 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10436 }, 10437 outputs: []outputInfo{ 10438 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10439 }, 10440 }, 10441 }, 10442 { 10443 name: "MOVQloadidx8", 10444 auxType: auxSymOff, 10445 argLen: 3, 10446 symEffect: SymRead, 10447 asm: x86.AMOVQ, 10448 reg: regInfo{ 10449 inputs: []inputInfo{ 10450 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10451 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10452 }, 10453 outputs: []outputInfo{ 10454 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10455 }, 10456 }, 10457 }, 10458 { 10459 name: "MOVBstoreidx1", 10460 auxType: auxSymOff, 10461 argLen: 4, 10462 symEffect: SymWrite, 10463 asm: x86.AMOVB, 10464 reg: regInfo{ 10465 inputs: []inputInfo{ 10466 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10467 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10468 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10469 }, 10470 }, 10471 }, 10472 { 10473 name: "MOVWstoreidx1", 10474 auxType: auxSymOff, 10475 argLen: 4, 10476 symEffect: SymWrite, 10477 asm: x86.AMOVW, 10478 reg: regInfo{ 10479 inputs: []inputInfo{ 10480 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10481 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10482 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10483 }, 10484 }, 10485 }, 10486 { 10487 name: "MOVWstoreidx2", 10488 auxType: auxSymOff, 10489 argLen: 4, 10490 symEffect: SymWrite, 10491 asm: x86.AMOVW, 10492 reg: regInfo{ 10493 inputs: []inputInfo{ 10494 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10495 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10496 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10497 }, 10498 }, 10499 }, 10500 { 10501 name: "MOVLstoreidx1", 10502 auxType: auxSymOff, 10503 argLen: 4, 10504 symEffect: SymWrite, 10505 asm: x86.AMOVL, 10506 reg: regInfo{ 10507 inputs: []inputInfo{ 10508 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10509 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10510 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10511 }, 10512 }, 10513 }, 10514 { 10515 name: "MOVLstoreidx4", 10516 auxType: auxSymOff, 10517 argLen: 4, 10518 symEffect: SymWrite, 10519 asm: x86.AMOVL, 10520 reg: regInfo{ 10521 inputs: []inputInfo{ 10522 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10523 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10524 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10525 }, 10526 }, 10527 }, 10528 { 10529 name: "MOVLstoreidx8", 10530 auxType: auxSymOff, 10531 argLen: 4, 10532 symEffect: SymWrite, 10533 asm: x86.AMOVL, 10534 reg: regInfo{ 10535 inputs: []inputInfo{ 10536 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10537 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10538 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10539 }, 10540 }, 10541 }, 10542 { 10543 name: "MOVQstoreidx1", 10544 auxType: auxSymOff, 10545 argLen: 4, 10546 symEffect: SymWrite, 10547 asm: x86.AMOVQ, 10548 reg: regInfo{ 10549 inputs: []inputInfo{ 10550 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10551 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10552 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10553 }, 10554 }, 10555 }, 10556 { 10557 name: "MOVQstoreidx8", 10558 auxType: auxSymOff, 10559 argLen: 4, 10560 symEffect: SymWrite, 10561 asm: x86.AMOVQ, 10562 reg: regInfo{ 10563 inputs: []inputInfo{ 10564 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10565 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10566 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10567 }, 10568 }, 10569 }, 10570 { 10571 name: "MOVBstoreconst", 10572 auxType: auxSymValAndOff, 10573 argLen: 2, 10574 faultOnNilArg0: true, 10575 symEffect: SymWrite, 10576 asm: x86.AMOVB, 10577 reg: regInfo{ 10578 inputs: []inputInfo{ 10579 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10580 }, 10581 }, 10582 }, 10583 { 10584 name: "MOVWstoreconst", 10585 auxType: auxSymValAndOff, 10586 argLen: 2, 10587 faultOnNilArg0: true, 10588 symEffect: SymWrite, 10589 asm: x86.AMOVW, 10590 reg: regInfo{ 10591 inputs: []inputInfo{ 10592 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10593 }, 10594 }, 10595 }, 10596 { 10597 name: "MOVLstoreconst", 10598 auxType: auxSymValAndOff, 10599 argLen: 2, 10600 faultOnNilArg0: true, 10601 symEffect: SymWrite, 10602 asm: x86.AMOVL, 10603 reg: regInfo{ 10604 inputs: []inputInfo{ 10605 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10606 }, 10607 }, 10608 }, 10609 { 10610 name: "MOVQstoreconst", 10611 auxType: auxSymValAndOff, 10612 argLen: 2, 10613 faultOnNilArg0: true, 10614 symEffect: SymWrite, 10615 asm: x86.AMOVQ, 10616 reg: regInfo{ 10617 inputs: []inputInfo{ 10618 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10619 }, 10620 }, 10621 }, 10622 { 10623 name: "MOVBstoreconstidx1", 10624 auxType: auxSymValAndOff, 10625 argLen: 3, 10626 symEffect: SymWrite, 10627 asm: x86.AMOVB, 10628 reg: regInfo{ 10629 inputs: []inputInfo{ 10630 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10631 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10632 }, 10633 }, 10634 }, 10635 { 10636 name: "MOVWstoreconstidx1", 10637 auxType: auxSymValAndOff, 10638 argLen: 3, 10639 symEffect: SymWrite, 10640 asm: x86.AMOVW, 10641 reg: regInfo{ 10642 inputs: []inputInfo{ 10643 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10644 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10645 }, 10646 }, 10647 }, 10648 { 10649 name: "MOVWstoreconstidx2", 10650 auxType: auxSymValAndOff, 10651 argLen: 3, 10652 symEffect: SymWrite, 10653 asm: x86.AMOVW, 10654 reg: regInfo{ 10655 inputs: []inputInfo{ 10656 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10657 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10658 }, 10659 }, 10660 }, 10661 { 10662 name: "MOVLstoreconstidx1", 10663 auxType: auxSymValAndOff, 10664 argLen: 3, 10665 symEffect: SymWrite, 10666 asm: x86.AMOVL, 10667 reg: regInfo{ 10668 inputs: []inputInfo{ 10669 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10670 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10671 }, 10672 }, 10673 }, 10674 { 10675 name: "MOVLstoreconstidx4", 10676 auxType: auxSymValAndOff, 10677 argLen: 3, 10678 symEffect: SymWrite, 10679 asm: x86.AMOVL, 10680 reg: regInfo{ 10681 inputs: []inputInfo{ 10682 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10683 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10684 }, 10685 }, 10686 }, 10687 { 10688 name: "MOVQstoreconstidx1", 10689 auxType: auxSymValAndOff, 10690 argLen: 3, 10691 symEffect: SymWrite, 10692 asm: x86.AMOVQ, 10693 reg: regInfo{ 10694 inputs: []inputInfo{ 10695 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10696 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10697 }, 10698 }, 10699 }, 10700 { 10701 name: "MOVQstoreconstidx8", 10702 auxType: auxSymValAndOff, 10703 argLen: 3, 10704 symEffect: SymWrite, 10705 asm: x86.AMOVQ, 10706 reg: regInfo{ 10707 inputs: []inputInfo{ 10708 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10709 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10710 }, 10711 }, 10712 }, 10713 { 10714 name: "DUFFZERO", 10715 auxType: auxInt64, 10716 argLen: 3, 10717 faultOnNilArg0: true, 10718 reg: regInfo{ 10719 inputs: []inputInfo{ 10720 {0, 128}, // DI 10721 {1, 65536}, // X0 10722 }, 10723 clobbers: 128, // DI 10724 }, 10725 }, 10726 { 10727 name: "MOVOconst", 10728 auxType: auxInt128, 10729 argLen: 0, 10730 rematerializeable: true, 10731 reg: regInfo{ 10732 outputs: []outputInfo{ 10733 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10734 }, 10735 }, 10736 }, 10737 { 10738 name: "REPSTOSQ", 10739 argLen: 4, 10740 faultOnNilArg0: true, 10741 reg: regInfo{ 10742 inputs: []inputInfo{ 10743 {0, 128}, // DI 10744 {1, 2}, // CX 10745 {2, 1}, // AX 10746 }, 10747 clobbers: 130, // CX DI 10748 }, 10749 }, 10750 { 10751 name: "CALLstatic", 10752 auxType: auxSymOff, 10753 argLen: 1, 10754 clobberFlags: true, 10755 call: true, 10756 symEffect: SymNone, 10757 reg: regInfo{ 10758 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10759 }, 10760 }, 10761 { 10762 name: "CALLclosure", 10763 auxType: auxInt64, 10764 argLen: 3, 10765 clobberFlags: true, 10766 call: true, 10767 reg: regInfo{ 10768 inputs: []inputInfo{ 10769 {1, 4}, // DX 10770 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10771 }, 10772 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10773 }, 10774 }, 10775 { 10776 name: "CALLinter", 10777 auxType: auxInt64, 10778 argLen: 2, 10779 clobberFlags: true, 10780 call: true, 10781 reg: regInfo{ 10782 inputs: []inputInfo{ 10783 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10784 }, 10785 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10786 }, 10787 }, 10788 { 10789 name: "DUFFCOPY", 10790 auxType: auxInt64, 10791 argLen: 3, 10792 clobberFlags: true, 10793 faultOnNilArg0: true, 10794 faultOnNilArg1: true, 10795 reg: regInfo{ 10796 inputs: []inputInfo{ 10797 {0, 128}, // DI 10798 {1, 64}, // SI 10799 }, 10800 clobbers: 65728, // SI DI X0 10801 }, 10802 }, 10803 { 10804 name: "REPMOVSQ", 10805 argLen: 4, 10806 faultOnNilArg0: true, 10807 faultOnNilArg1: true, 10808 reg: regInfo{ 10809 inputs: []inputInfo{ 10810 {0, 128}, // DI 10811 {1, 64}, // SI 10812 {2, 2}, // CX 10813 }, 10814 clobbers: 194, // CX SI DI 10815 }, 10816 }, 10817 { 10818 name: "InvertFlags", 10819 argLen: 1, 10820 reg: regInfo{}, 10821 }, 10822 { 10823 name: "LoweredGetG", 10824 argLen: 1, 10825 reg: regInfo{ 10826 outputs: []outputInfo{ 10827 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10828 }, 10829 }, 10830 }, 10831 { 10832 name: "LoweredGetClosurePtr", 10833 argLen: 0, 10834 zeroWidth: true, 10835 reg: regInfo{ 10836 outputs: []outputInfo{ 10837 {0, 4}, // DX 10838 }, 10839 }, 10840 }, 10841 { 10842 name: "LoweredGetCallerPC", 10843 argLen: 0, 10844 rematerializeable: true, 10845 reg: regInfo{ 10846 outputs: []outputInfo{ 10847 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10848 }, 10849 }, 10850 }, 10851 { 10852 name: "LoweredGetCallerSP", 10853 argLen: 0, 10854 rematerializeable: true, 10855 reg: regInfo{ 10856 outputs: []outputInfo{ 10857 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10858 }, 10859 }, 10860 }, 10861 { 10862 name: "LoweredNilCheck", 10863 argLen: 2, 10864 clobberFlags: true, 10865 nilCheck: true, 10866 faultOnNilArg0: true, 10867 reg: regInfo{ 10868 inputs: []inputInfo{ 10869 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10870 }, 10871 }, 10872 }, 10873 { 10874 name: "LoweredWB", 10875 auxType: auxSym, 10876 argLen: 3, 10877 clobberFlags: true, 10878 symEffect: SymNone, 10879 reg: regInfo{ 10880 inputs: []inputInfo{ 10881 {0, 128}, // DI 10882 {1, 1}, // AX 10883 }, 10884 clobbers: 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10885 }, 10886 }, 10887 { 10888 name: "FlagEQ", 10889 argLen: 0, 10890 reg: regInfo{}, 10891 }, 10892 { 10893 name: "FlagLT_ULT", 10894 argLen: 0, 10895 reg: regInfo{}, 10896 }, 10897 { 10898 name: "FlagLT_UGT", 10899 argLen: 0, 10900 reg: regInfo{}, 10901 }, 10902 { 10903 name: "FlagGT_UGT", 10904 argLen: 0, 10905 reg: regInfo{}, 10906 }, 10907 { 10908 name: "FlagGT_ULT", 10909 argLen: 0, 10910 reg: regInfo{}, 10911 }, 10912 { 10913 name: "MOVLatomicload", 10914 auxType: auxSymOff, 10915 argLen: 2, 10916 faultOnNilArg0: true, 10917 symEffect: SymRead, 10918 asm: x86.AMOVL, 10919 reg: regInfo{ 10920 inputs: []inputInfo{ 10921 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10922 }, 10923 outputs: []outputInfo{ 10924 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10925 }, 10926 }, 10927 }, 10928 { 10929 name: "MOVQatomicload", 10930 auxType: auxSymOff, 10931 argLen: 2, 10932 faultOnNilArg0: true, 10933 symEffect: SymRead, 10934 asm: x86.AMOVQ, 10935 reg: regInfo{ 10936 inputs: []inputInfo{ 10937 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10938 }, 10939 outputs: []outputInfo{ 10940 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10941 }, 10942 }, 10943 }, 10944 { 10945 name: "XCHGL", 10946 auxType: auxSymOff, 10947 argLen: 3, 10948 resultInArg0: true, 10949 faultOnNilArg1: true, 10950 hasSideEffects: true, 10951 symEffect: SymRdWr, 10952 asm: x86.AXCHGL, 10953 reg: regInfo{ 10954 inputs: []inputInfo{ 10955 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10956 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10957 }, 10958 outputs: []outputInfo{ 10959 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10960 }, 10961 }, 10962 }, 10963 { 10964 name: "XCHGQ", 10965 auxType: auxSymOff, 10966 argLen: 3, 10967 resultInArg0: true, 10968 faultOnNilArg1: true, 10969 hasSideEffects: true, 10970 symEffect: SymRdWr, 10971 asm: x86.AXCHGQ, 10972 reg: regInfo{ 10973 inputs: []inputInfo{ 10974 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10975 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10976 }, 10977 outputs: []outputInfo{ 10978 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10979 }, 10980 }, 10981 }, 10982 { 10983 name: "XADDLlock", 10984 auxType: auxSymOff, 10985 argLen: 3, 10986 resultInArg0: true, 10987 clobberFlags: true, 10988 faultOnNilArg1: true, 10989 hasSideEffects: true, 10990 symEffect: SymRdWr, 10991 asm: x86.AXADDL, 10992 reg: regInfo{ 10993 inputs: []inputInfo{ 10994 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10995 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10996 }, 10997 outputs: []outputInfo{ 10998 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10999 }, 11000 }, 11001 }, 11002 { 11003 name: "XADDQlock", 11004 auxType: auxSymOff, 11005 argLen: 3, 11006 resultInArg0: true, 11007 clobberFlags: true, 11008 faultOnNilArg1: true, 11009 hasSideEffects: true, 11010 symEffect: SymRdWr, 11011 asm: x86.AXADDQ, 11012 reg: regInfo{ 11013 inputs: []inputInfo{ 11014 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11015 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 11016 }, 11017 outputs: []outputInfo{ 11018 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11019 }, 11020 }, 11021 }, 11022 { 11023 name: "AddTupleFirst32", 11024 argLen: 2, 11025 reg: regInfo{}, 11026 }, 11027 { 11028 name: "AddTupleFirst64", 11029 argLen: 2, 11030 reg: regInfo{}, 11031 }, 11032 { 11033 name: "CMPXCHGLlock", 11034 auxType: auxSymOff, 11035 argLen: 4, 11036 clobberFlags: true, 11037 faultOnNilArg0: true, 11038 hasSideEffects: true, 11039 symEffect: SymRdWr, 11040 asm: x86.ACMPXCHGL, 11041 reg: regInfo{ 11042 inputs: []inputInfo{ 11043 {1, 1}, // AX 11044 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11045 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11046 }, 11047 clobbers: 1, // AX 11048 outputs: []outputInfo{ 11049 {1, 0}, 11050 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11051 }, 11052 }, 11053 }, 11054 { 11055 name: "CMPXCHGQlock", 11056 auxType: auxSymOff, 11057 argLen: 4, 11058 clobberFlags: true, 11059 faultOnNilArg0: true, 11060 hasSideEffects: true, 11061 symEffect: SymRdWr, 11062 asm: x86.ACMPXCHGQ, 11063 reg: regInfo{ 11064 inputs: []inputInfo{ 11065 {1, 1}, // AX 11066 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11067 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11068 }, 11069 clobbers: 1, // AX 11070 outputs: []outputInfo{ 11071 {1, 0}, 11072 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11073 }, 11074 }, 11075 }, 11076 { 11077 name: "ANDBlock", 11078 auxType: auxSymOff, 11079 argLen: 3, 11080 clobberFlags: true, 11081 faultOnNilArg0: true, 11082 hasSideEffects: true, 11083 symEffect: SymRdWr, 11084 asm: x86.AANDB, 11085 reg: regInfo{ 11086 inputs: []inputInfo{ 11087 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11088 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 11089 }, 11090 }, 11091 }, 11092 { 11093 name: "ORBlock", 11094 auxType: auxSymOff, 11095 argLen: 3, 11096 clobberFlags: true, 11097 faultOnNilArg0: true, 11098 hasSideEffects: true, 11099 symEffect: SymRdWr, 11100 asm: x86.AORB, 11101 reg: regInfo{ 11102 inputs: []inputInfo{ 11103 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11104 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 11105 }, 11106 }, 11107 }, 11108 11109 { 11110 name: "ADD", 11111 argLen: 2, 11112 commutative: true, 11113 asm: arm.AADD, 11114 reg: regInfo{ 11115 inputs: []inputInfo{ 11116 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11117 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11118 }, 11119 outputs: []outputInfo{ 11120 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11121 }, 11122 }, 11123 }, 11124 { 11125 name: "ADDconst", 11126 auxType: auxInt32, 11127 argLen: 1, 11128 asm: arm.AADD, 11129 reg: regInfo{ 11130 inputs: []inputInfo{ 11131 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 11132 }, 11133 outputs: []outputInfo{ 11134 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11135 }, 11136 }, 11137 }, 11138 { 11139 name: "SUB", 11140 argLen: 2, 11141 asm: arm.ASUB, 11142 reg: regInfo{ 11143 inputs: []inputInfo{ 11144 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11145 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11146 }, 11147 outputs: []outputInfo{ 11148 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11149 }, 11150 }, 11151 }, 11152 { 11153 name: "SUBconst", 11154 auxType: auxInt32, 11155 argLen: 1, 11156 asm: arm.ASUB, 11157 reg: regInfo{ 11158 inputs: []inputInfo{ 11159 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11160 }, 11161 outputs: []outputInfo{ 11162 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11163 }, 11164 }, 11165 }, 11166 { 11167 name: "RSB", 11168 argLen: 2, 11169 asm: arm.ARSB, 11170 reg: regInfo{ 11171 inputs: []inputInfo{ 11172 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11173 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11174 }, 11175 outputs: []outputInfo{ 11176 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11177 }, 11178 }, 11179 }, 11180 { 11181 name: "RSBconst", 11182 auxType: auxInt32, 11183 argLen: 1, 11184 asm: arm.ARSB, 11185 reg: regInfo{ 11186 inputs: []inputInfo{ 11187 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11188 }, 11189 outputs: []outputInfo{ 11190 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11191 }, 11192 }, 11193 }, 11194 { 11195 name: "MUL", 11196 argLen: 2, 11197 commutative: true, 11198 asm: arm.AMUL, 11199 reg: regInfo{ 11200 inputs: []inputInfo{ 11201 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11202 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11203 }, 11204 outputs: []outputInfo{ 11205 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11206 }, 11207 }, 11208 }, 11209 { 11210 name: "HMUL", 11211 argLen: 2, 11212 commutative: true, 11213 asm: arm.AMULL, 11214 reg: regInfo{ 11215 inputs: []inputInfo{ 11216 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11217 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11218 }, 11219 outputs: []outputInfo{ 11220 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11221 }, 11222 }, 11223 }, 11224 { 11225 name: "HMULU", 11226 argLen: 2, 11227 commutative: true, 11228 asm: arm.AMULLU, 11229 reg: regInfo{ 11230 inputs: []inputInfo{ 11231 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11232 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11233 }, 11234 outputs: []outputInfo{ 11235 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11236 }, 11237 }, 11238 }, 11239 { 11240 name: "CALLudiv", 11241 argLen: 2, 11242 clobberFlags: true, 11243 reg: regInfo{ 11244 inputs: []inputInfo{ 11245 {0, 2}, // R1 11246 {1, 1}, // R0 11247 }, 11248 clobbers: 16396, // R2 R3 R14 11249 outputs: []outputInfo{ 11250 {0, 1}, // R0 11251 {1, 2}, // R1 11252 }, 11253 }, 11254 }, 11255 { 11256 name: "ADDS", 11257 argLen: 2, 11258 commutative: true, 11259 asm: arm.AADD, 11260 reg: regInfo{ 11261 inputs: []inputInfo{ 11262 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11263 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11264 }, 11265 outputs: []outputInfo{ 11266 {1, 0}, 11267 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11268 }, 11269 }, 11270 }, 11271 { 11272 name: "ADDSconst", 11273 auxType: auxInt32, 11274 argLen: 1, 11275 asm: arm.AADD, 11276 reg: regInfo{ 11277 inputs: []inputInfo{ 11278 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11279 }, 11280 outputs: []outputInfo{ 11281 {1, 0}, 11282 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11283 }, 11284 }, 11285 }, 11286 { 11287 name: "ADC", 11288 argLen: 3, 11289 commutative: true, 11290 asm: arm.AADC, 11291 reg: regInfo{ 11292 inputs: []inputInfo{ 11293 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11294 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11295 }, 11296 outputs: []outputInfo{ 11297 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11298 }, 11299 }, 11300 }, 11301 { 11302 name: "ADCconst", 11303 auxType: auxInt32, 11304 argLen: 2, 11305 asm: arm.AADC, 11306 reg: regInfo{ 11307 inputs: []inputInfo{ 11308 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11309 }, 11310 outputs: []outputInfo{ 11311 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11312 }, 11313 }, 11314 }, 11315 { 11316 name: "SUBS", 11317 argLen: 2, 11318 asm: arm.ASUB, 11319 reg: regInfo{ 11320 inputs: []inputInfo{ 11321 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11322 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11323 }, 11324 outputs: []outputInfo{ 11325 {1, 0}, 11326 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11327 }, 11328 }, 11329 }, 11330 { 11331 name: "SUBSconst", 11332 auxType: auxInt32, 11333 argLen: 1, 11334 asm: arm.ASUB, 11335 reg: regInfo{ 11336 inputs: []inputInfo{ 11337 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11338 }, 11339 outputs: []outputInfo{ 11340 {1, 0}, 11341 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11342 }, 11343 }, 11344 }, 11345 { 11346 name: "RSBSconst", 11347 auxType: auxInt32, 11348 argLen: 1, 11349 asm: arm.ARSB, 11350 reg: regInfo{ 11351 inputs: []inputInfo{ 11352 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11353 }, 11354 outputs: []outputInfo{ 11355 {1, 0}, 11356 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11357 }, 11358 }, 11359 }, 11360 { 11361 name: "SBC", 11362 argLen: 3, 11363 asm: arm.ASBC, 11364 reg: regInfo{ 11365 inputs: []inputInfo{ 11366 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11367 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11368 }, 11369 outputs: []outputInfo{ 11370 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11371 }, 11372 }, 11373 }, 11374 { 11375 name: "SBCconst", 11376 auxType: auxInt32, 11377 argLen: 2, 11378 asm: arm.ASBC, 11379 reg: regInfo{ 11380 inputs: []inputInfo{ 11381 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11382 }, 11383 outputs: []outputInfo{ 11384 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11385 }, 11386 }, 11387 }, 11388 { 11389 name: "RSCconst", 11390 auxType: auxInt32, 11391 argLen: 2, 11392 asm: arm.ARSC, 11393 reg: regInfo{ 11394 inputs: []inputInfo{ 11395 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11396 }, 11397 outputs: []outputInfo{ 11398 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11399 }, 11400 }, 11401 }, 11402 { 11403 name: "MULLU", 11404 argLen: 2, 11405 commutative: true, 11406 asm: arm.AMULLU, 11407 reg: regInfo{ 11408 inputs: []inputInfo{ 11409 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11410 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11411 }, 11412 outputs: []outputInfo{ 11413 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11414 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11415 }, 11416 }, 11417 }, 11418 { 11419 name: "MULA", 11420 argLen: 3, 11421 asm: arm.AMULA, 11422 reg: regInfo{ 11423 inputs: []inputInfo{ 11424 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11425 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11426 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11427 }, 11428 outputs: []outputInfo{ 11429 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11430 }, 11431 }, 11432 }, 11433 { 11434 name: "MULS", 11435 argLen: 3, 11436 asm: arm.AMULS, 11437 reg: regInfo{ 11438 inputs: []inputInfo{ 11439 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11440 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11441 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11442 }, 11443 outputs: []outputInfo{ 11444 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11445 }, 11446 }, 11447 }, 11448 { 11449 name: "ADDF", 11450 argLen: 2, 11451 commutative: true, 11452 asm: arm.AADDF, 11453 reg: regInfo{ 11454 inputs: []inputInfo{ 11455 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11456 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11457 }, 11458 outputs: []outputInfo{ 11459 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11460 }, 11461 }, 11462 }, 11463 { 11464 name: "ADDD", 11465 argLen: 2, 11466 commutative: true, 11467 asm: arm.AADDD, 11468 reg: regInfo{ 11469 inputs: []inputInfo{ 11470 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11471 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11472 }, 11473 outputs: []outputInfo{ 11474 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11475 }, 11476 }, 11477 }, 11478 { 11479 name: "SUBF", 11480 argLen: 2, 11481 asm: arm.ASUBF, 11482 reg: regInfo{ 11483 inputs: []inputInfo{ 11484 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11485 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11486 }, 11487 outputs: []outputInfo{ 11488 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11489 }, 11490 }, 11491 }, 11492 { 11493 name: "SUBD", 11494 argLen: 2, 11495 asm: arm.ASUBD, 11496 reg: regInfo{ 11497 inputs: []inputInfo{ 11498 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11499 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11500 }, 11501 outputs: []outputInfo{ 11502 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11503 }, 11504 }, 11505 }, 11506 { 11507 name: "MULF", 11508 argLen: 2, 11509 commutative: true, 11510 asm: arm.AMULF, 11511 reg: regInfo{ 11512 inputs: []inputInfo{ 11513 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11514 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11515 }, 11516 outputs: []outputInfo{ 11517 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11518 }, 11519 }, 11520 }, 11521 { 11522 name: "MULD", 11523 argLen: 2, 11524 commutative: true, 11525 asm: arm.AMULD, 11526 reg: regInfo{ 11527 inputs: []inputInfo{ 11528 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11529 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11530 }, 11531 outputs: []outputInfo{ 11532 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11533 }, 11534 }, 11535 }, 11536 { 11537 name: "NMULF", 11538 argLen: 2, 11539 commutative: true, 11540 asm: arm.ANMULF, 11541 reg: regInfo{ 11542 inputs: []inputInfo{ 11543 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11544 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11545 }, 11546 outputs: []outputInfo{ 11547 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11548 }, 11549 }, 11550 }, 11551 { 11552 name: "NMULD", 11553 argLen: 2, 11554 commutative: true, 11555 asm: arm.ANMULD, 11556 reg: regInfo{ 11557 inputs: []inputInfo{ 11558 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11559 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11560 }, 11561 outputs: []outputInfo{ 11562 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11563 }, 11564 }, 11565 }, 11566 { 11567 name: "DIVF", 11568 argLen: 2, 11569 asm: arm.ADIVF, 11570 reg: regInfo{ 11571 inputs: []inputInfo{ 11572 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11573 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11574 }, 11575 outputs: []outputInfo{ 11576 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11577 }, 11578 }, 11579 }, 11580 { 11581 name: "DIVD", 11582 argLen: 2, 11583 asm: arm.ADIVD, 11584 reg: regInfo{ 11585 inputs: []inputInfo{ 11586 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11587 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11588 }, 11589 outputs: []outputInfo{ 11590 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11591 }, 11592 }, 11593 }, 11594 { 11595 name: "MULAF", 11596 argLen: 3, 11597 resultInArg0: true, 11598 asm: arm.AMULAF, 11599 reg: regInfo{ 11600 inputs: []inputInfo{ 11601 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11602 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11603 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11604 }, 11605 outputs: []outputInfo{ 11606 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11607 }, 11608 }, 11609 }, 11610 { 11611 name: "MULAD", 11612 argLen: 3, 11613 resultInArg0: true, 11614 asm: arm.AMULAD, 11615 reg: regInfo{ 11616 inputs: []inputInfo{ 11617 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11618 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11619 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11620 }, 11621 outputs: []outputInfo{ 11622 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11623 }, 11624 }, 11625 }, 11626 { 11627 name: "MULSF", 11628 argLen: 3, 11629 resultInArg0: true, 11630 asm: arm.AMULSF, 11631 reg: regInfo{ 11632 inputs: []inputInfo{ 11633 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11634 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11635 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11636 }, 11637 outputs: []outputInfo{ 11638 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11639 }, 11640 }, 11641 }, 11642 { 11643 name: "MULSD", 11644 argLen: 3, 11645 resultInArg0: true, 11646 asm: arm.AMULSD, 11647 reg: regInfo{ 11648 inputs: []inputInfo{ 11649 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11650 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11651 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11652 }, 11653 outputs: []outputInfo{ 11654 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11655 }, 11656 }, 11657 }, 11658 { 11659 name: "AND", 11660 argLen: 2, 11661 commutative: true, 11662 asm: arm.AAND, 11663 reg: regInfo{ 11664 inputs: []inputInfo{ 11665 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11666 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11667 }, 11668 outputs: []outputInfo{ 11669 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11670 }, 11671 }, 11672 }, 11673 { 11674 name: "ANDconst", 11675 auxType: auxInt32, 11676 argLen: 1, 11677 asm: arm.AAND, 11678 reg: regInfo{ 11679 inputs: []inputInfo{ 11680 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11681 }, 11682 outputs: []outputInfo{ 11683 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11684 }, 11685 }, 11686 }, 11687 { 11688 name: "OR", 11689 argLen: 2, 11690 commutative: true, 11691 asm: arm.AORR, 11692 reg: regInfo{ 11693 inputs: []inputInfo{ 11694 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11695 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11696 }, 11697 outputs: []outputInfo{ 11698 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11699 }, 11700 }, 11701 }, 11702 { 11703 name: "ORconst", 11704 auxType: auxInt32, 11705 argLen: 1, 11706 asm: arm.AORR, 11707 reg: regInfo{ 11708 inputs: []inputInfo{ 11709 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11710 }, 11711 outputs: []outputInfo{ 11712 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11713 }, 11714 }, 11715 }, 11716 { 11717 name: "XOR", 11718 argLen: 2, 11719 commutative: true, 11720 asm: arm.AEOR, 11721 reg: regInfo{ 11722 inputs: []inputInfo{ 11723 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11724 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11725 }, 11726 outputs: []outputInfo{ 11727 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11728 }, 11729 }, 11730 }, 11731 { 11732 name: "XORconst", 11733 auxType: auxInt32, 11734 argLen: 1, 11735 asm: arm.AEOR, 11736 reg: regInfo{ 11737 inputs: []inputInfo{ 11738 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11739 }, 11740 outputs: []outputInfo{ 11741 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11742 }, 11743 }, 11744 }, 11745 { 11746 name: "BIC", 11747 argLen: 2, 11748 asm: arm.ABIC, 11749 reg: regInfo{ 11750 inputs: []inputInfo{ 11751 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11752 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11753 }, 11754 outputs: []outputInfo{ 11755 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11756 }, 11757 }, 11758 }, 11759 { 11760 name: "BICconst", 11761 auxType: auxInt32, 11762 argLen: 1, 11763 asm: arm.ABIC, 11764 reg: regInfo{ 11765 inputs: []inputInfo{ 11766 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11767 }, 11768 outputs: []outputInfo{ 11769 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11770 }, 11771 }, 11772 }, 11773 { 11774 name: "BFX", 11775 auxType: auxInt32, 11776 argLen: 1, 11777 asm: arm.ABFX, 11778 reg: regInfo{ 11779 inputs: []inputInfo{ 11780 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11781 }, 11782 outputs: []outputInfo{ 11783 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11784 }, 11785 }, 11786 }, 11787 { 11788 name: "BFXU", 11789 auxType: auxInt32, 11790 argLen: 1, 11791 asm: arm.ABFXU, 11792 reg: regInfo{ 11793 inputs: []inputInfo{ 11794 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11795 }, 11796 outputs: []outputInfo{ 11797 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11798 }, 11799 }, 11800 }, 11801 { 11802 name: "MVN", 11803 argLen: 1, 11804 asm: arm.AMVN, 11805 reg: regInfo{ 11806 inputs: []inputInfo{ 11807 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11808 }, 11809 outputs: []outputInfo{ 11810 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11811 }, 11812 }, 11813 }, 11814 { 11815 name: "NEGF", 11816 argLen: 1, 11817 asm: arm.ANEGF, 11818 reg: regInfo{ 11819 inputs: []inputInfo{ 11820 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11821 }, 11822 outputs: []outputInfo{ 11823 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11824 }, 11825 }, 11826 }, 11827 { 11828 name: "NEGD", 11829 argLen: 1, 11830 asm: arm.ANEGD, 11831 reg: regInfo{ 11832 inputs: []inputInfo{ 11833 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11834 }, 11835 outputs: []outputInfo{ 11836 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11837 }, 11838 }, 11839 }, 11840 { 11841 name: "SQRTD", 11842 argLen: 1, 11843 asm: arm.ASQRTD, 11844 reg: regInfo{ 11845 inputs: []inputInfo{ 11846 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11847 }, 11848 outputs: []outputInfo{ 11849 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11850 }, 11851 }, 11852 }, 11853 { 11854 name: "CLZ", 11855 argLen: 1, 11856 asm: arm.ACLZ, 11857 reg: regInfo{ 11858 inputs: []inputInfo{ 11859 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11860 }, 11861 outputs: []outputInfo{ 11862 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11863 }, 11864 }, 11865 }, 11866 { 11867 name: "REV", 11868 argLen: 1, 11869 asm: arm.AREV, 11870 reg: regInfo{ 11871 inputs: []inputInfo{ 11872 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11873 }, 11874 outputs: []outputInfo{ 11875 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11876 }, 11877 }, 11878 }, 11879 { 11880 name: "RBIT", 11881 argLen: 1, 11882 asm: arm.ARBIT, 11883 reg: regInfo{ 11884 inputs: []inputInfo{ 11885 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11886 }, 11887 outputs: []outputInfo{ 11888 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11889 }, 11890 }, 11891 }, 11892 { 11893 name: "SLL", 11894 argLen: 2, 11895 asm: arm.ASLL, 11896 reg: regInfo{ 11897 inputs: []inputInfo{ 11898 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11899 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11900 }, 11901 outputs: []outputInfo{ 11902 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11903 }, 11904 }, 11905 }, 11906 { 11907 name: "SLLconst", 11908 auxType: auxInt32, 11909 argLen: 1, 11910 asm: arm.ASLL, 11911 reg: regInfo{ 11912 inputs: []inputInfo{ 11913 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11914 }, 11915 outputs: []outputInfo{ 11916 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11917 }, 11918 }, 11919 }, 11920 { 11921 name: "SRL", 11922 argLen: 2, 11923 asm: arm.ASRL, 11924 reg: regInfo{ 11925 inputs: []inputInfo{ 11926 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11927 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11928 }, 11929 outputs: []outputInfo{ 11930 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11931 }, 11932 }, 11933 }, 11934 { 11935 name: "SRLconst", 11936 auxType: auxInt32, 11937 argLen: 1, 11938 asm: arm.ASRL, 11939 reg: regInfo{ 11940 inputs: []inputInfo{ 11941 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11942 }, 11943 outputs: []outputInfo{ 11944 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11945 }, 11946 }, 11947 }, 11948 { 11949 name: "SRA", 11950 argLen: 2, 11951 asm: arm.ASRA, 11952 reg: regInfo{ 11953 inputs: []inputInfo{ 11954 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11955 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11956 }, 11957 outputs: []outputInfo{ 11958 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11959 }, 11960 }, 11961 }, 11962 { 11963 name: "SRAconst", 11964 auxType: auxInt32, 11965 argLen: 1, 11966 asm: arm.ASRA, 11967 reg: regInfo{ 11968 inputs: []inputInfo{ 11969 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11970 }, 11971 outputs: []outputInfo{ 11972 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11973 }, 11974 }, 11975 }, 11976 { 11977 name: "SRRconst", 11978 auxType: auxInt32, 11979 argLen: 1, 11980 reg: regInfo{ 11981 inputs: []inputInfo{ 11982 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11983 }, 11984 outputs: []outputInfo{ 11985 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11986 }, 11987 }, 11988 }, 11989 { 11990 name: "ADDshiftLL", 11991 auxType: auxInt32, 11992 argLen: 2, 11993 asm: arm.AADD, 11994 reg: regInfo{ 11995 inputs: []inputInfo{ 11996 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11997 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11998 }, 11999 outputs: []outputInfo{ 12000 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12001 }, 12002 }, 12003 }, 12004 { 12005 name: "ADDshiftRL", 12006 auxType: auxInt32, 12007 argLen: 2, 12008 asm: arm.AADD, 12009 reg: regInfo{ 12010 inputs: []inputInfo{ 12011 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12012 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12013 }, 12014 outputs: []outputInfo{ 12015 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12016 }, 12017 }, 12018 }, 12019 { 12020 name: "ADDshiftRA", 12021 auxType: auxInt32, 12022 argLen: 2, 12023 asm: arm.AADD, 12024 reg: regInfo{ 12025 inputs: []inputInfo{ 12026 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12027 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12028 }, 12029 outputs: []outputInfo{ 12030 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12031 }, 12032 }, 12033 }, 12034 { 12035 name: "SUBshiftLL", 12036 auxType: auxInt32, 12037 argLen: 2, 12038 asm: arm.ASUB, 12039 reg: regInfo{ 12040 inputs: []inputInfo{ 12041 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12042 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12043 }, 12044 outputs: []outputInfo{ 12045 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12046 }, 12047 }, 12048 }, 12049 { 12050 name: "SUBshiftRL", 12051 auxType: auxInt32, 12052 argLen: 2, 12053 asm: arm.ASUB, 12054 reg: regInfo{ 12055 inputs: []inputInfo{ 12056 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12057 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12058 }, 12059 outputs: []outputInfo{ 12060 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12061 }, 12062 }, 12063 }, 12064 { 12065 name: "SUBshiftRA", 12066 auxType: auxInt32, 12067 argLen: 2, 12068 asm: arm.ASUB, 12069 reg: regInfo{ 12070 inputs: []inputInfo{ 12071 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12072 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12073 }, 12074 outputs: []outputInfo{ 12075 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12076 }, 12077 }, 12078 }, 12079 { 12080 name: "RSBshiftLL", 12081 auxType: auxInt32, 12082 argLen: 2, 12083 asm: arm.ARSB, 12084 reg: regInfo{ 12085 inputs: []inputInfo{ 12086 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12087 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12088 }, 12089 outputs: []outputInfo{ 12090 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12091 }, 12092 }, 12093 }, 12094 { 12095 name: "RSBshiftRL", 12096 auxType: auxInt32, 12097 argLen: 2, 12098 asm: arm.ARSB, 12099 reg: regInfo{ 12100 inputs: []inputInfo{ 12101 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12102 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12103 }, 12104 outputs: []outputInfo{ 12105 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12106 }, 12107 }, 12108 }, 12109 { 12110 name: "RSBshiftRA", 12111 auxType: auxInt32, 12112 argLen: 2, 12113 asm: arm.ARSB, 12114 reg: regInfo{ 12115 inputs: []inputInfo{ 12116 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12117 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12118 }, 12119 outputs: []outputInfo{ 12120 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12121 }, 12122 }, 12123 }, 12124 { 12125 name: "ANDshiftLL", 12126 auxType: auxInt32, 12127 argLen: 2, 12128 asm: arm.AAND, 12129 reg: regInfo{ 12130 inputs: []inputInfo{ 12131 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12132 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12133 }, 12134 outputs: []outputInfo{ 12135 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12136 }, 12137 }, 12138 }, 12139 { 12140 name: "ANDshiftRL", 12141 auxType: auxInt32, 12142 argLen: 2, 12143 asm: arm.AAND, 12144 reg: regInfo{ 12145 inputs: []inputInfo{ 12146 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12147 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12148 }, 12149 outputs: []outputInfo{ 12150 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12151 }, 12152 }, 12153 }, 12154 { 12155 name: "ANDshiftRA", 12156 auxType: auxInt32, 12157 argLen: 2, 12158 asm: arm.AAND, 12159 reg: regInfo{ 12160 inputs: []inputInfo{ 12161 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12162 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12163 }, 12164 outputs: []outputInfo{ 12165 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12166 }, 12167 }, 12168 }, 12169 { 12170 name: "ORshiftLL", 12171 auxType: auxInt32, 12172 argLen: 2, 12173 asm: arm.AORR, 12174 reg: regInfo{ 12175 inputs: []inputInfo{ 12176 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12177 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12178 }, 12179 outputs: []outputInfo{ 12180 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12181 }, 12182 }, 12183 }, 12184 { 12185 name: "ORshiftRL", 12186 auxType: auxInt32, 12187 argLen: 2, 12188 asm: arm.AORR, 12189 reg: regInfo{ 12190 inputs: []inputInfo{ 12191 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12192 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12193 }, 12194 outputs: []outputInfo{ 12195 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12196 }, 12197 }, 12198 }, 12199 { 12200 name: "ORshiftRA", 12201 auxType: auxInt32, 12202 argLen: 2, 12203 asm: arm.AORR, 12204 reg: regInfo{ 12205 inputs: []inputInfo{ 12206 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12207 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12208 }, 12209 outputs: []outputInfo{ 12210 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12211 }, 12212 }, 12213 }, 12214 { 12215 name: "XORshiftLL", 12216 auxType: auxInt32, 12217 argLen: 2, 12218 asm: arm.AEOR, 12219 reg: regInfo{ 12220 inputs: []inputInfo{ 12221 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12222 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12223 }, 12224 outputs: []outputInfo{ 12225 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12226 }, 12227 }, 12228 }, 12229 { 12230 name: "XORshiftRL", 12231 auxType: auxInt32, 12232 argLen: 2, 12233 asm: arm.AEOR, 12234 reg: regInfo{ 12235 inputs: []inputInfo{ 12236 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12237 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12238 }, 12239 outputs: []outputInfo{ 12240 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12241 }, 12242 }, 12243 }, 12244 { 12245 name: "XORshiftRA", 12246 auxType: auxInt32, 12247 argLen: 2, 12248 asm: arm.AEOR, 12249 reg: regInfo{ 12250 inputs: []inputInfo{ 12251 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12252 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12253 }, 12254 outputs: []outputInfo{ 12255 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12256 }, 12257 }, 12258 }, 12259 { 12260 name: "XORshiftRR", 12261 auxType: auxInt32, 12262 argLen: 2, 12263 asm: arm.AEOR, 12264 reg: regInfo{ 12265 inputs: []inputInfo{ 12266 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12267 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12268 }, 12269 outputs: []outputInfo{ 12270 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12271 }, 12272 }, 12273 }, 12274 { 12275 name: "BICshiftLL", 12276 auxType: auxInt32, 12277 argLen: 2, 12278 asm: arm.ABIC, 12279 reg: regInfo{ 12280 inputs: []inputInfo{ 12281 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12282 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12283 }, 12284 outputs: []outputInfo{ 12285 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12286 }, 12287 }, 12288 }, 12289 { 12290 name: "BICshiftRL", 12291 auxType: auxInt32, 12292 argLen: 2, 12293 asm: arm.ABIC, 12294 reg: regInfo{ 12295 inputs: []inputInfo{ 12296 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12297 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12298 }, 12299 outputs: []outputInfo{ 12300 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12301 }, 12302 }, 12303 }, 12304 { 12305 name: "BICshiftRA", 12306 auxType: auxInt32, 12307 argLen: 2, 12308 asm: arm.ABIC, 12309 reg: regInfo{ 12310 inputs: []inputInfo{ 12311 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12312 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12313 }, 12314 outputs: []outputInfo{ 12315 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12316 }, 12317 }, 12318 }, 12319 { 12320 name: "MVNshiftLL", 12321 auxType: auxInt32, 12322 argLen: 1, 12323 asm: arm.AMVN, 12324 reg: regInfo{ 12325 inputs: []inputInfo{ 12326 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12327 }, 12328 outputs: []outputInfo{ 12329 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12330 }, 12331 }, 12332 }, 12333 { 12334 name: "MVNshiftRL", 12335 auxType: auxInt32, 12336 argLen: 1, 12337 asm: arm.AMVN, 12338 reg: regInfo{ 12339 inputs: []inputInfo{ 12340 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12341 }, 12342 outputs: []outputInfo{ 12343 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12344 }, 12345 }, 12346 }, 12347 { 12348 name: "MVNshiftRA", 12349 auxType: auxInt32, 12350 argLen: 1, 12351 asm: arm.AMVN, 12352 reg: regInfo{ 12353 inputs: []inputInfo{ 12354 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12355 }, 12356 outputs: []outputInfo{ 12357 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12358 }, 12359 }, 12360 }, 12361 { 12362 name: "ADCshiftLL", 12363 auxType: auxInt32, 12364 argLen: 3, 12365 asm: arm.AADC, 12366 reg: regInfo{ 12367 inputs: []inputInfo{ 12368 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12369 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12370 }, 12371 outputs: []outputInfo{ 12372 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12373 }, 12374 }, 12375 }, 12376 { 12377 name: "ADCshiftRL", 12378 auxType: auxInt32, 12379 argLen: 3, 12380 asm: arm.AADC, 12381 reg: regInfo{ 12382 inputs: []inputInfo{ 12383 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12384 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12385 }, 12386 outputs: []outputInfo{ 12387 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12388 }, 12389 }, 12390 }, 12391 { 12392 name: "ADCshiftRA", 12393 auxType: auxInt32, 12394 argLen: 3, 12395 asm: arm.AADC, 12396 reg: regInfo{ 12397 inputs: []inputInfo{ 12398 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12399 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12400 }, 12401 outputs: []outputInfo{ 12402 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12403 }, 12404 }, 12405 }, 12406 { 12407 name: "SBCshiftLL", 12408 auxType: auxInt32, 12409 argLen: 3, 12410 asm: arm.ASBC, 12411 reg: regInfo{ 12412 inputs: []inputInfo{ 12413 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12414 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12415 }, 12416 outputs: []outputInfo{ 12417 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12418 }, 12419 }, 12420 }, 12421 { 12422 name: "SBCshiftRL", 12423 auxType: auxInt32, 12424 argLen: 3, 12425 asm: arm.ASBC, 12426 reg: regInfo{ 12427 inputs: []inputInfo{ 12428 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12429 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12430 }, 12431 outputs: []outputInfo{ 12432 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12433 }, 12434 }, 12435 }, 12436 { 12437 name: "SBCshiftRA", 12438 auxType: auxInt32, 12439 argLen: 3, 12440 asm: arm.ASBC, 12441 reg: regInfo{ 12442 inputs: []inputInfo{ 12443 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12444 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12445 }, 12446 outputs: []outputInfo{ 12447 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12448 }, 12449 }, 12450 }, 12451 { 12452 name: "RSCshiftLL", 12453 auxType: auxInt32, 12454 argLen: 3, 12455 asm: arm.ARSC, 12456 reg: regInfo{ 12457 inputs: []inputInfo{ 12458 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12459 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12460 }, 12461 outputs: []outputInfo{ 12462 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12463 }, 12464 }, 12465 }, 12466 { 12467 name: "RSCshiftRL", 12468 auxType: auxInt32, 12469 argLen: 3, 12470 asm: arm.ARSC, 12471 reg: regInfo{ 12472 inputs: []inputInfo{ 12473 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12474 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12475 }, 12476 outputs: []outputInfo{ 12477 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12478 }, 12479 }, 12480 }, 12481 { 12482 name: "RSCshiftRA", 12483 auxType: auxInt32, 12484 argLen: 3, 12485 asm: arm.ARSC, 12486 reg: regInfo{ 12487 inputs: []inputInfo{ 12488 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12489 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12490 }, 12491 outputs: []outputInfo{ 12492 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12493 }, 12494 }, 12495 }, 12496 { 12497 name: "ADDSshiftLL", 12498 auxType: auxInt32, 12499 argLen: 2, 12500 asm: arm.AADD, 12501 reg: regInfo{ 12502 inputs: []inputInfo{ 12503 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12504 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12505 }, 12506 outputs: []outputInfo{ 12507 {1, 0}, 12508 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12509 }, 12510 }, 12511 }, 12512 { 12513 name: "ADDSshiftRL", 12514 auxType: auxInt32, 12515 argLen: 2, 12516 asm: arm.AADD, 12517 reg: regInfo{ 12518 inputs: []inputInfo{ 12519 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12520 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12521 }, 12522 outputs: []outputInfo{ 12523 {1, 0}, 12524 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12525 }, 12526 }, 12527 }, 12528 { 12529 name: "ADDSshiftRA", 12530 auxType: auxInt32, 12531 argLen: 2, 12532 asm: arm.AADD, 12533 reg: regInfo{ 12534 inputs: []inputInfo{ 12535 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12536 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12537 }, 12538 outputs: []outputInfo{ 12539 {1, 0}, 12540 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12541 }, 12542 }, 12543 }, 12544 { 12545 name: "SUBSshiftLL", 12546 auxType: auxInt32, 12547 argLen: 2, 12548 asm: arm.ASUB, 12549 reg: regInfo{ 12550 inputs: []inputInfo{ 12551 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12552 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12553 }, 12554 outputs: []outputInfo{ 12555 {1, 0}, 12556 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12557 }, 12558 }, 12559 }, 12560 { 12561 name: "SUBSshiftRL", 12562 auxType: auxInt32, 12563 argLen: 2, 12564 asm: arm.ASUB, 12565 reg: regInfo{ 12566 inputs: []inputInfo{ 12567 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12568 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12569 }, 12570 outputs: []outputInfo{ 12571 {1, 0}, 12572 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12573 }, 12574 }, 12575 }, 12576 { 12577 name: "SUBSshiftRA", 12578 auxType: auxInt32, 12579 argLen: 2, 12580 asm: arm.ASUB, 12581 reg: regInfo{ 12582 inputs: []inputInfo{ 12583 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12584 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12585 }, 12586 outputs: []outputInfo{ 12587 {1, 0}, 12588 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12589 }, 12590 }, 12591 }, 12592 { 12593 name: "RSBSshiftLL", 12594 auxType: auxInt32, 12595 argLen: 2, 12596 asm: arm.ARSB, 12597 reg: regInfo{ 12598 inputs: []inputInfo{ 12599 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12600 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12601 }, 12602 outputs: []outputInfo{ 12603 {1, 0}, 12604 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12605 }, 12606 }, 12607 }, 12608 { 12609 name: "RSBSshiftRL", 12610 auxType: auxInt32, 12611 argLen: 2, 12612 asm: arm.ARSB, 12613 reg: regInfo{ 12614 inputs: []inputInfo{ 12615 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12616 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12617 }, 12618 outputs: []outputInfo{ 12619 {1, 0}, 12620 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12621 }, 12622 }, 12623 }, 12624 { 12625 name: "RSBSshiftRA", 12626 auxType: auxInt32, 12627 argLen: 2, 12628 asm: arm.ARSB, 12629 reg: regInfo{ 12630 inputs: []inputInfo{ 12631 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12632 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12633 }, 12634 outputs: []outputInfo{ 12635 {1, 0}, 12636 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12637 }, 12638 }, 12639 }, 12640 { 12641 name: "ADDshiftLLreg", 12642 argLen: 3, 12643 asm: arm.AADD, 12644 reg: regInfo{ 12645 inputs: []inputInfo{ 12646 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12647 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12648 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12649 }, 12650 outputs: []outputInfo{ 12651 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12652 }, 12653 }, 12654 }, 12655 { 12656 name: "ADDshiftRLreg", 12657 argLen: 3, 12658 asm: arm.AADD, 12659 reg: regInfo{ 12660 inputs: []inputInfo{ 12661 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12662 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12663 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12664 }, 12665 outputs: []outputInfo{ 12666 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12667 }, 12668 }, 12669 }, 12670 { 12671 name: "ADDshiftRAreg", 12672 argLen: 3, 12673 asm: arm.AADD, 12674 reg: regInfo{ 12675 inputs: []inputInfo{ 12676 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12677 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12678 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12679 }, 12680 outputs: []outputInfo{ 12681 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12682 }, 12683 }, 12684 }, 12685 { 12686 name: "SUBshiftLLreg", 12687 argLen: 3, 12688 asm: arm.ASUB, 12689 reg: regInfo{ 12690 inputs: []inputInfo{ 12691 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12692 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12693 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12694 }, 12695 outputs: []outputInfo{ 12696 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12697 }, 12698 }, 12699 }, 12700 { 12701 name: "SUBshiftRLreg", 12702 argLen: 3, 12703 asm: arm.ASUB, 12704 reg: regInfo{ 12705 inputs: []inputInfo{ 12706 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12707 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12708 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12709 }, 12710 outputs: []outputInfo{ 12711 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12712 }, 12713 }, 12714 }, 12715 { 12716 name: "SUBshiftRAreg", 12717 argLen: 3, 12718 asm: arm.ASUB, 12719 reg: regInfo{ 12720 inputs: []inputInfo{ 12721 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12722 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12723 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12724 }, 12725 outputs: []outputInfo{ 12726 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12727 }, 12728 }, 12729 }, 12730 { 12731 name: "RSBshiftLLreg", 12732 argLen: 3, 12733 asm: arm.ARSB, 12734 reg: regInfo{ 12735 inputs: []inputInfo{ 12736 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12737 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12738 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12739 }, 12740 outputs: []outputInfo{ 12741 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12742 }, 12743 }, 12744 }, 12745 { 12746 name: "RSBshiftRLreg", 12747 argLen: 3, 12748 asm: arm.ARSB, 12749 reg: regInfo{ 12750 inputs: []inputInfo{ 12751 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12752 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12753 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12754 }, 12755 outputs: []outputInfo{ 12756 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12757 }, 12758 }, 12759 }, 12760 { 12761 name: "RSBshiftRAreg", 12762 argLen: 3, 12763 asm: arm.ARSB, 12764 reg: regInfo{ 12765 inputs: []inputInfo{ 12766 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12767 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12768 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12769 }, 12770 outputs: []outputInfo{ 12771 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12772 }, 12773 }, 12774 }, 12775 { 12776 name: "ANDshiftLLreg", 12777 argLen: 3, 12778 asm: arm.AAND, 12779 reg: regInfo{ 12780 inputs: []inputInfo{ 12781 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12782 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12783 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12784 }, 12785 outputs: []outputInfo{ 12786 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12787 }, 12788 }, 12789 }, 12790 { 12791 name: "ANDshiftRLreg", 12792 argLen: 3, 12793 asm: arm.AAND, 12794 reg: regInfo{ 12795 inputs: []inputInfo{ 12796 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12797 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12798 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12799 }, 12800 outputs: []outputInfo{ 12801 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12802 }, 12803 }, 12804 }, 12805 { 12806 name: "ANDshiftRAreg", 12807 argLen: 3, 12808 asm: arm.AAND, 12809 reg: regInfo{ 12810 inputs: []inputInfo{ 12811 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12812 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12813 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12814 }, 12815 outputs: []outputInfo{ 12816 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12817 }, 12818 }, 12819 }, 12820 { 12821 name: "ORshiftLLreg", 12822 argLen: 3, 12823 asm: arm.AORR, 12824 reg: regInfo{ 12825 inputs: []inputInfo{ 12826 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12827 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12828 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12829 }, 12830 outputs: []outputInfo{ 12831 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12832 }, 12833 }, 12834 }, 12835 { 12836 name: "ORshiftRLreg", 12837 argLen: 3, 12838 asm: arm.AORR, 12839 reg: regInfo{ 12840 inputs: []inputInfo{ 12841 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12842 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12843 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12844 }, 12845 outputs: []outputInfo{ 12846 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12847 }, 12848 }, 12849 }, 12850 { 12851 name: "ORshiftRAreg", 12852 argLen: 3, 12853 asm: arm.AORR, 12854 reg: regInfo{ 12855 inputs: []inputInfo{ 12856 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12857 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12858 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12859 }, 12860 outputs: []outputInfo{ 12861 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12862 }, 12863 }, 12864 }, 12865 { 12866 name: "XORshiftLLreg", 12867 argLen: 3, 12868 asm: arm.AEOR, 12869 reg: regInfo{ 12870 inputs: []inputInfo{ 12871 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12872 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12873 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12874 }, 12875 outputs: []outputInfo{ 12876 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12877 }, 12878 }, 12879 }, 12880 { 12881 name: "XORshiftRLreg", 12882 argLen: 3, 12883 asm: arm.AEOR, 12884 reg: regInfo{ 12885 inputs: []inputInfo{ 12886 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12887 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12888 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12889 }, 12890 outputs: []outputInfo{ 12891 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12892 }, 12893 }, 12894 }, 12895 { 12896 name: "XORshiftRAreg", 12897 argLen: 3, 12898 asm: arm.AEOR, 12899 reg: regInfo{ 12900 inputs: []inputInfo{ 12901 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12902 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12903 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12904 }, 12905 outputs: []outputInfo{ 12906 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12907 }, 12908 }, 12909 }, 12910 { 12911 name: "BICshiftLLreg", 12912 argLen: 3, 12913 asm: arm.ABIC, 12914 reg: regInfo{ 12915 inputs: []inputInfo{ 12916 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12917 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12918 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12919 }, 12920 outputs: []outputInfo{ 12921 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12922 }, 12923 }, 12924 }, 12925 { 12926 name: "BICshiftRLreg", 12927 argLen: 3, 12928 asm: arm.ABIC, 12929 reg: regInfo{ 12930 inputs: []inputInfo{ 12931 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12932 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12933 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12934 }, 12935 outputs: []outputInfo{ 12936 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12937 }, 12938 }, 12939 }, 12940 { 12941 name: "BICshiftRAreg", 12942 argLen: 3, 12943 asm: arm.ABIC, 12944 reg: regInfo{ 12945 inputs: []inputInfo{ 12946 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12947 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12948 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12949 }, 12950 outputs: []outputInfo{ 12951 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12952 }, 12953 }, 12954 }, 12955 { 12956 name: "MVNshiftLLreg", 12957 argLen: 2, 12958 asm: arm.AMVN, 12959 reg: regInfo{ 12960 inputs: []inputInfo{ 12961 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12962 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12963 }, 12964 outputs: []outputInfo{ 12965 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12966 }, 12967 }, 12968 }, 12969 { 12970 name: "MVNshiftRLreg", 12971 argLen: 2, 12972 asm: arm.AMVN, 12973 reg: regInfo{ 12974 inputs: []inputInfo{ 12975 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12976 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12977 }, 12978 outputs: []outputInfo{ 12979 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12980 }, 12981 }, 12982 }, 12983 { 12984 name: "MVNshiftRAreg", 12985 argLen: 2, 12986 asm: arm.AMVN, 12987 reg: regInfo{ 12988 inputs: []inputInfo{ 12989 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12990 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12991 }, 12992 outputs: []outputInfo{ 12993 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12994 }, 12995 }, 12996 }, 12997 { 12998 name: "ADCshiftLLreg", 12999 argLen: 4, 13000 asm: arm.AADC, 13001 reg: regInfo{ 13002 inputs: []inputInfo{ 13003 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13004 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13005 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13006 }, 13007 outputs: []outputInfo{ 13008 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13009 }, 13010 }, 13011 }, 13012 { 13013 name: "ADCshiftRLreg", 13014 argLen: 4, 13015 asm: arm.AADC, 13016 reg: regInfo{ 13017 inputs: []inputInfo{ 13018 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13019 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13020 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13021 }, 13022 outputs: []outputInfo{ 13023 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13024 }, 13025 }, 13026 }, 13027 { 13028 name: "ADCshiftRAreg", 13029 argLen: 4, 13030 asm: arm.AADC, 13031 reg: regInfo{ 13032 inputs: []inputInfo{ 13033 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13034 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13035 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13036 }, 13037 outputs: []outputInfo{ 13038 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13039 }, 13040 }, 13041 }, 13042 { 13043 name: "SBCshiftLLreg", 13044 argLen: 4, 13045 asm: arm.ASBC, 13046 reg: regInfo{ 13047 inputs: []inputInfo{ 13048 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13049 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13050 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13051 }, 13052 outputs: []outputInfo{ 13053 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13054 }, 13055 }, 13056 }, 13057 { 13058 name: "SBCshiftRLreg", 13059 argLen: 4, 13060 asm: arm.ASBC, 13061 reg: regInfo{ 13062 inputs: []inputInfo{ 13063 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13064 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13065 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13066 }, 13067 outputs: []outputInfo{ 13068 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13069 }, 13070 }, 13071 }, 13072 { 13073 name: "SBCshiftRAreg", 13074 argLen: 4, 13075 asm: arm.ASBC, 13076 reg: regInfo{ 13077 inputs: []inputInfo{ 13078 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13079 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13080 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13081 }, 13082 outputs: []outputInfo{ 13083 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13084 }, 13085 }, 13086 }, 13087 { 13088 name: "RSCshiftLLreg", 13089 argLen: 4, 13090 asm: arm.ARSC, 13091 reg: regInfo{ 13092 inputs: []inputInfo{ 13093 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13094 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13095 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13096 }, 13097 outputs: []outputInfo{ 13098 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13099 }, 13100 }, 13101 }, 13102 { 13103 name: "RSCshiftRLreg", 13104 argLen: 4, 13105 asm: arm.ARSC, 13106 reg: regInfo{ 13107 inputs: []inputInfo{ 13108 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13109 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13110 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13111 }, 13112 outputs: []outputInfo{ 13113 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13114 }, 13115 }, 13116 }, 13117 { 13118 name: "RSCshiftRAreg", 13119 argLen: 4, 13120 asm: arm.ARSC, 13121 reg: regInfo{ 13122 inputs: []inputInfo{ 13123 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13124 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13125 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13126 }, 13127 outputs: []outputInfo{ 13128 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13129 }, 13130 }, 13131 }, 13132 { 13133 name: "ADDSshiftLLreg", 13134 argLen: 3, 13135 asm: arm.AADD, 13136 reg: regInfo{ 13137 inputs: []inputInfo{ 13138 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13139 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13140 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13141 }, 13142 outputs: []outputInfo{ 13143 {1, 0}, 13144 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13145 }, 13146 }, 13147 }, 13148 { 13149 name: "ADDSshiftRLreg", 13150 argLen: 3, 13151 asm: arm.AADD, 13152 reg: regInfo{ 13153 inputs: []inputInfo{ 13154 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13155 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13156 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13157 }, 13158 outputs: []outputInfo{ 13159 {1, 0}, 13160 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13161 }, 13162 }, 13163 }, 13164 { 13165 name: "ADDSshiftRAreg", 13166 argLen: 3, 13167 asm: arm.AADD, 13168 reg: regInfo{ 13169 inputs: []inputInfo{ 13170 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13171 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13172 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13173 }, 13174 outputs: []outputInfo{ 13175 {1, 0}, 13176 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13177 }, 13178 }, 13179 }, 13180 { 13181 name: "SUBSshiftLLreg", 13182 argLen: 3, 13183 asm: arm.ASUB, 13184 reg: regInfo{ 13185 inputs: []inputInfo{ 13186 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13187 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13188 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13189 }, 13190 outputs: []outputInfo{ 13191 {1, 0}, 13192 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13193 }, 13194 }, 13195 }, 13196 { 13197 name: "SUBSshiftRLreg", 13198 argLen: 3, 13199 asm: arm.ASUB, 13200 reg: regInfo{ 13201 inputs: []inputInfo{ 13202 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13203 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13204 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13205 }, 13206 outputs: []outputInfo{ 13207 {1, 0}, 13208 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13209 }, 13210 }, 13211 }, 13212 { 13213 name: "SUBSshiftRAreg", 13214 argLen: 3, 13215 asm: arm.ASUB, 13216 reg: regInfo{ 13217 inputs: []inputInfo{ 13218 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13219 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13220 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13221 }, 13222 outputs: []outputInfo{ 13223 {1, 0}, 13224 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13225 }, 13226 }, 13227 }, 13228 { 13229 name: "RSBSshiftLLreg", 13230 argLen: 3, 13231 asm: arm.ARSB, 13232 reg: regInfo{ 13233 inputs: []inputInfo{ 13234 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13235 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13236 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13237 }, 13238 outputs: []outputInfo{ 13239 {1, 0}, 13240 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13241 }, 13242 }, 13243 }, 13244 { 13245 name: "RSBSshiftRLreg", 13246 argLen: 3, 13247 asm: arm.ARSB, 13248 reg: regInfo{ 13249 inputs: []inputInfo{ 13250 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13251 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13252 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13253 }, 13254 outputs: []outputInfo{ 13255 {1, 0}, 13256 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13257 }, 13258 }, 13259 }, 13260 { 13261 name: "RSBSshiftRAreg", 13262 argLen: 3, 13263 asm: arm.ARSB, 13264 reg: regInfo{ 13265 inputs: []inputInfo{ 13266 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13267 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13268 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13269 }, 13270 outputs: []outputInfo{ 13271 {1, 0}, 13272 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13273 }, 13274 }, 13275 }, 13276 { 13277 name: "CMP", 13278 argLen: 2, 13279 asm: arm.ACMP, 13280 reg: regInfo{ 13281 inputs: []inputInfo{ 13282 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13283 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13284 }, 13285 }, 13286 }, 13287 { 13288 name: "CMPconst", 13289 auxType: auxInt32, 13290 argLen: 1, 13291 asm: arm.ACMP, 13292 reg: regInfo{ 13293 inputs: []inputInfo{ 13294 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13295 }, 13296 }, 13297 }, 13298 { 13299 name: "CMN", 13300 argLen: 2, 13301 commutative: true, 13302 asm: arm.ACMN, 13303 reg: regInfo{ 13304 inputs: []inputInfo{ 13305 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13306 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13307 }, 13308 }, 13309 }, 13310 { 13311 name: "CMNconst", 13312 auxType: auxInt32, 13313 argLen: 1, 13314 asm: arm.ACMN, 13315 reg: regInfo{ 13316 inputs: []inputInfo{ 13317 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13318 }, 13319 }, 13320 }, 13321 { 13322 name: "TST", 13323 argLen: 2, 13324 commutative: true, 13325 asm: arm.ATST, 13326 reg: regInfo{ 13327 inputs: []inputInfo{ 13328 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13329 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13330 }, 13331 }, 13332 }, 13333 { 13334 name: "TSTconst", 13335 auxType: auxInt32, 13336 argLen: 1, 13337 asm: arm.ATST, 13338 reg: regInfo{ 13339 inputs: []inputInfo{ 13340 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13341 }, 13342 }, 13343 }, 13344 { 13345 name: "TEQ", 13346 argLen: 2, 13347 commutative: true, 13348 asm: arm.ATEQ, 13349 reg: regInfo{ 13350 inputs: []inputInfo{ 13351 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13352 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13353 }, 13354 }, 13355 }, 13356 { 13357 name: "TEQconst", 13358 auxType: auxInt32, 13359 argLen: 1, 13360 asm: arm.ATEQ, 13361 reg: regInfo{ 13362 inputs: []inputInfo{ 13363 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13364 }, 13365 }, 13366 }, 13367 { 13368 name: "CMPF", 13369 argLen: 2, 13370 asm: arm.ACMPF, 13371 reg: regInfo{ 13372 inputs: []inputInfo{ 13373 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13374 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13375 }, 13376 }, 13377 }, 13378 { 13379 name: "CMPD", 13380 argLen: 2, 13381 asm: arm.ACMPD, 13382 reg: regInfo{ 13383 inputs: []inputInfo{ 13384 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13385 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13386 }, 13387 }, 13388 }, 13389 { 13390 name: "CMPshiftLL", 13391 auxType: auxInt32, 13392 argLen: 2, 13393 asm: arm.ACMP, 13394 reg: regInfo{ 13395 inputs: []inputInfo{ 13396 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13397 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13398 }, 13399 }, 13400 }, 13401 { 13402 name: "CMPshiftRL", 13403 auxType: auxInt32, 13404 argLen: 2, 13405 asm: arm.ACMP, 13406 reg: regInfo{ 13407 inputs: []inputInfo{ 13408 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13409 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13410 }, 13411 }, 13412 }, 13413 { 13414 name: "CMPshiftRA", 13415 auxType: auxInt32, 13416 argLen: 2, 13417 asm: arm.ACMP, 13418 reg: regInfo{ 13419 inputs: []inputInfo{ 13420 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13421 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13422 }, 13423 }, 13424 }, 13425 { 13426 name: "CMNshiftLL", 13427 auxType: auxInt32, 13428 argLen: 2, 13429 asm: arm.ACMN, 13430 reg: regInfo{ 13431 inputs: []inputInfo{ 13432 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13433 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13434 }, 13435 }, 13436 }, 13437 { 13438 name: "CMNshiftRL", 13439 auxType: auxInt32, 13440 argLen: 2, 13441 asm: arm.ACMN, 13442 reg: regInfo{ 13443 inputs: []inputInfo{ 13444 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13445 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13446 }, 13447 }, 13448 }, 13449 { 13450 name: "CMNshiftRA", 13451 auxType: auxInt32, 13452 argLen: 2, 13453 asm: arm.ACMN, 13454 reg: regInfo{ 13455 inputs: []inputInfo{ 13456 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13457 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13458 }, 13459 }, 13460 }, 13461 { 13462 name: "TSTshiftLL", 13463 auxType: auxInt32, 13464 argLen: 2, 13465 asm: arm.ATST, 13466 reg: regInfo{ 13467 inputs: []inputInfo{ 13468 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13469 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13470 }, 13471 }, 13472 }, 13473 { 13474 name: "TSTshiftRL", 13475 auxType: auxInt32, 13476 argLen: 2, 13477 asm: arm.ATST, 13478 reg: regInfo{ 13479 inputs: []inputInfo{ 13480 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13481 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13482 }, 13483 }, 13484 }, 13485 { 13486 name: "TSTshiftRA", 13487 auxType: auxInt32, 13488 argLen: 2, 13489 asm: arm.ATST, 13490 reg: regInfo{ 13491 inputs: []inputInfo{ 13492 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13493 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13494 }, 13495 }, 13496 }, 13497 { 13498 name: "TEQshiftLL", 13499 auxType: auxInt32, 13500 argLen: 2, 13501 asm: arm.ATEQ, 13502 reg: regInfo{ 13503 inputs: []inputInfo{ 13504 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13505 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13506 }, 13507 }, 13508 }, 13509 { 13510 name: "TEQshiftRL", 13511 auxType: auxInt32, 13512 argLen: 2, 13513 asm: arm.ATEQ, 13514 reg: regInfo{ 13515 inputs: []inputInfo{ 13516 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13517 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13518 }, 13519 }, 13520 }, 13521 { 13522 name: "TEQshiftRA", 13523 auxType: auxInt32, 13524 argLen: 2, 13525 asm: arm.ATEQ, 13526 reg: regInfo{ 13527 inputs: []inputInfo{ 13528 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13529 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13530 }, 13531 }, 13532 }, 13533 { 13534 name: "CMPshiftLLreg", 13535 argLen: 3, 13536 asm: arm.ACMP, 13537 reg: regInfo{ 13538 inputs: []inputInfo{ 13539 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13540 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13541 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13542 }, 13543 }, 13544 }, 13545 { 13546 name: "CMPshiftRLreg", 13547 argLen: 3, 13548 asm: arm.ACMP, 13549 reg: regInfo{ 13550 inputs: []inputInfo{ 13551 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13552 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13553 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13554 }, 13555 }, 13556 }, 13557 { 13558 name: "CMPshiftRAreg", 13559 argLen: 3, 13560 asm: arm.ACMP, 13561 reg: regInfo{ 13562 inputs: []inputInfo{ 13563 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13564 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13565 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13566 }, 13567 }, 13568 }, 13569 { 13570 name: "CMNshiftLLreg", 13571 argLen: 3, 13572 asm: arm.ACMN, 13573 reg: regInfo{ 13574 inputs: []inputInfo{ 13575 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13576 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13577 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13578 }, 13579 }, 13580 }, 13581 { 13582 name: "CMNshiftRLreg", 13583 argLen: 3, 13584 asm: arm.ACMN, 13585 reg: regInfo{ 13586 inputs: []inputInfo{ 13587 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13588 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13589 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13590 }, 13591 }, 13592 }, 13593 { 13594 name: "CMNshiftRAreg", 13595 argLen: 3, 13596 asm: arm.ACMN, 13597 reg: regInfo{ 13598 inputs: []inputInfo{ 13599 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13600 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13601 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13602 }, 13603 }, 13604 }, 13605 { 13606 name: "TSTshiftLLreg", 13607 argLen: 3, 13608 asm: arm.ATST, 13609 reg: regInfo{ 13610 inputs: []inputInfo{ 13611 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13612 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13613 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13614 }, 13615 }, 13616 }, 13617 { 13618 name: "TSTshiftRLreg", 13619 argLen: 3, 13620 asm: arm.ATST, 13621 reg: regInfo{ 13622 inputs: []inputInfo{ 13623 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13624 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13625 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13626 }, 13627 }, 13628 }, 13629 { 13630 name: "TSTshiftRAreg", 13631 argLen: 3, 13632 asm: arm.ATST, 13633 reg: regInfo{ 13634 inputs: []inputInfo{ 13635 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13636 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13637 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13638 }, 13639 }, 13640 }, 13641 { 13642 name: "TEQshiftLLreg", 13643 argLen: 3, 13644 asm: arm.ATEQ, 13645 reg: regInfo{ 13646 inputs: []inputInfo{ 13647 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13648 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13649 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13650 }, 13651 }, 13652 }, 13653 { 13654 name: "TEQshiftRLreg", 13655 argLen: 3, 13656 asm: arm.ATEQ, 13657 reg: regInfo{ 13658 inputs: []inputInfo{ 13659 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13660 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13661 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13662 }, 13663 }, 13664 }, 13665 { 13666 name: "TEQshiftRAreg", 13667 argLen: 3, 13668 asm: arm.ATEQ, 13669 reg: regInfo{ 13670 inputs: []inputInfo{ 13671 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13672 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13673 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13674 }, 13675 }, 13676 }, 13677 { 13678 name: "CMPF0", 13679 argLen: 1, 13680 asm: arm.ACMPF, 13681 reg: regInfo{ 13682 inputs: []inputInfo{ 13683 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13684 }, 13685 }, 13686 }, 13687 { 13688 name: "CMPD0", 13689 argLen: 1, 13690 asm: arm.ACMPD, 13691 reg: regInfo{ 13692 inputs: []inputInfo{ 13693 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13694 }, 13695 }, 13696 }, 13697 { 13698 name: "MOVWconst", 13699 auxType: auxInt32, 13700 argLen: 0, 13701 rematerializeable: true, 13702 asm: arm.AMOVW, 13703 reg: regInfo{ 13704 outputs: []outputInfo{ 13705 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13706 }, 13707 }, 13708 }, 13709 { 13710 name: "MOVFconst", 13711 auxType: auxFloat64, 13712 argLen: 0, 13713 rematerializeable: true, 13714 asm: arm.AMOVF, 13715 reg: regInfo{ 13716 outputs: []outputInfo{ 13717 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13718 }, 13719 }, 13720 }, 13721 { 13722 name: "MOVDconst", 13723 auxType: auxFloat64, 13724 argLen: 0, 13725 rematerializeable: true, 13726 asm: arm.AMOVD, 13727 reg: regInfo{ 13728 outputs: []outputInfo{ 13729 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13730 }, 13731 }, 13732 }, 13733 { 13734 name: "MOVWaddr", 13735 auxType: auxSymOff, 13736 argLen: 1, 13737 rematerializeable: true, 13738 symEffect: SymAddr, 13739 asm: arm.AMOVW, 13740 reg: regInfo{ 13741 inputs: []inputInfo{ 13742 {0, 4294975488}, // SP SB 13743 }, 13744 outputs: []outputInfo{ 13745 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13746 }, 13747 }, 13748 }, 13749 { 13750 name: "MOVBload", 13751 auxType: auxSymOff, 13752 argLen: 2, 13753 faultOnNilArg0: true, 13754 symEffect: SymRead, 13755 asm: arm.AMOVB, 13756 reg: regInfo{ 13757 inputs: []inputInfo{ 13758 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13759 }, 13760 outputs: []outputInfo{ 13761 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13762 }, 13763 }, 13764 }, 13765 { 13766 name: "MOVBUload", 13767 auxType: auxSymOff, 13768 argLen: 2, 13769 faultOnNilArg0: true, 13770 symEffect: SymRead, 13771 asm: arm.AMOVBU, 13772 reg: regInfo{ 13773 inputs: []inputInfo{ 13774 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13775 }, 13776 outputs: []outputInfo{ 13777 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13778 }, 13779 }, 13780 }, 13781 { 13782 name: "MOVHload", 13783 auxType: auxSymOff, 13784 argLen: 2, 13785 faultOnNilArg0: true, 13786 symEffect: SymRead, 13787 asm: arm.AMOVH, 13788 reg: regInfo{ 13789 inputs: []inputInfo{ 13790 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13791 }, 13792 outputs: []outputInfo{ 13793 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13794 }, 13795 }, 13796 }, 13797 { 13798 name: "MOVHUload", 13799 auxType: auxSymOff, 13800 argLen: 2, 13801 faultOnNilArg0: true, 13802 symEffect: SymRead, 13803 asm: arm.AMOVHU, 13804 reg: regInfo{ 13805 inputs: []inputInfo{ 13806 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13807 }, 13808 outputs: []outputInfo{ 13809 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13810 }, 13811 }, 13812 }, 13813 { 13814 name: "MOVWload", 13815 auxType: auxSymOff, 13816 argLen: 2, 13817 faultOnNilArg0: true, 13818 symEffect: SymRead, 13819 asm: arm.AMOVW, 13820 reg: regInfo{ 13821 inputs: []inputInfo{ 13822 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13823 }, 13824 outputs: []outputInfo{ 13825 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13826 }, 13827 }, 13828 }, 13829 { 13830 name: "MOVFload", 13831 auxType: auxSymOff, 13832 argLen: 2, 13833 faultOnNilArg0: true, 13834 symEffect: SymRead, 13835 asm: arm.AMOVF, 13836 reg: regInfo{ 13837 inputs: []inputInfo{ 13838 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13839 }, 13840 outputs: []outputInfo{ 13841 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13842 }, 13843 }, 13844 }, 13845 { 13846 name: "MOVDload", 13847 auxType: auxSymOff, 13848 argLen: 2, 13849 faultOnNilArg0: true, 13850 symEffect: SymRead, 13851 asm: arm.AMOVD, 13852 reg: regInfo{ 13853 inputs: []inputInfo{ 13854 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13855 }, 13856 outputs: []outputInfo{ 13857 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13858 }, 13859 }, 13860 }, 13861 { 13862 name: "MOVBstore", 13863 auxType: auxSymOff, 13864 argLen: 3, 13865 faultOnNilArg0: true, 13866 symEffect: SymWrite, 13867 asm: arm.AMOVB, 13868 reg: regInfo{ 13869 inputs: []inputInfo{ 13870 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13871 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13872 }, 13873 }, 13874 }, 13875 { 13876 name: "MOVHstore", 13877 auxType: auxSymOff, 13878 argLen: 3, 13879 faultOnNilArg0: true, 13880 symEffect: SymWrite, 13881 asm: arm.AMOVH, 13882 reg: regInfo{ 13883 inputs: []inputInfo{ 13884 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13885 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13886 }, 13887 }, 13888 }, 13889 { 13890 name: "MOVWstore", 13891 auxType: auxSymOff, 13892 argLen: 3, 13893 faultOnNilArg0: true, 13894 symEffect: SymWrite, 13895 asm: arm.AMOVW, 13896 reg: regInfo{ 13897 inputs: []inputInfo{ 13898 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13899 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13900 }, 13901 }, 13902 }, 13903 { 13904 name: "MOVFstore", 13905 auxType: auxSymOff, 13906 argLen: 3, 13907 faultOnNilArg0: true, 13908 symEffect: SymWrite, 13909 asm: arm.AMOVF, 13910 reg: regInfo{ 13911 inputs: []inputInfo{ 13912 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13913 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13914 }, 13915 }, 13916 }, 13917 { 13918 name: "MOVDstore", 13919 auxType: auxSymOff, 13920 argLen: 3, 13921 faultOnNilArg0: true, 13922 symEffect: SymWrite, 13923 asm: arm.AMOVD, 13924 reg: regInfo{ 13925 inputs: []inputInfo{ 13926 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13927 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13928 }, 13929 }, 13930 }, 13931 { 13932 name: "MOVWloadidx", 13933 argLen: 3, 13934 asm: arm.AMOVW, 13935 reg: regInfo{ 13936 inputs: []inputInfo{ 13937 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13938 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13939 }, 13940 outputs: []outputInfo{ 13941 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13942 }, 13943 }, 13944 }, 13945 { 13946 name: "MOVWloadshiftLL", 13947 auxType: auxInt32, 13948 argLen: 3, 13949 asm: arm.AMOVW, 13950 reg: regInfo{ 13951 inputs: []inputInfo{ 13952 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13953 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13954 }, 13955 outputs: []outputInfo{ 13956 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13957 }, 13958 }, 13959 }, 13960 { 13961 name: "MOVWloadshiftRL", 13962 auxType: auxInt32, 13963 argLen: 3, 13964 asm: arm.AMOVW, 13965 reg: regInfo{ 13966 inputs: []inputInfo{ 13967 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13968 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13969 }, 13970 outputs: []outputInfo{ 13971 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13972 }, 13973 }, 13974 }, 13975 { 13976 name: "MOVWloadshiftRA", 13977 auxType: auxInt32, 13978 argLen: 3, 13979 asm: arm.AMOVW, 13980 reg: regInfo{ 13981 inputs: []inputInfo{ 13982 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13983 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13984 }, 13985 outputs: []outputInfo{ 13986 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13987 }, 13988 }, 13989 }, 13990 { 13991 name: "MOVBUloadidx", 13992 argLen: 3, 13993 asm: arm.AMOVBU, 13994 reg: regInfo{ 13995 inputs: []inputInfo{ 13996 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13997 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13998 }, 13999 outputs: []outputInfo{ 14000 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14001 }, 14002 }, 14003 }, 14004 { 14005 name: "MOVBloadidx", 14006 argLen: 3, 14007 asm: arm.AMOVB, 14008 reg: regInfo{ 14009 inputs: []inputInfo{ 14010 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14011 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14012 }, 14013 outputs: []outputInfo{ 14014 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14015 }, 14016 }, 14017 }, 14018 { 14019 name: "MOVHUloadidx", 14020 argLen: 3, 14021 asm: arm.AMOVHU, 14022 reg: regInfo{ 14023 inputs: []inputInfo{ 14024 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14025 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14026 }, 14027 outputs: []outputInfo{ 14028 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14029 }, 14030 }, 14031 }, 14032 { 14033 name: "MOVHloadidx", 14034 argLen: 3, 14035 asm: arm.AMOVH, 14036 reg: regInfo{ 14037 inputs: []inputInfo{ 14038 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14039 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14040 }, 14041 outputs: []outputInfo{ 14042 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14043 }, 14044 }, 14045 }, 14046 { 14047 name: "MOVWstoreidx", 14048 argLen: 4, 14049 asm: arm.AMOVW, 14050 reg: regInfo{ 14051 inputs: []inputInfo{ 14052 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14053 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14054 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14055 }, 14056 }, 14057 }, 14058 { 14059 name: "MOVWstoreshiftLL", 14060 auxType: auxInt32, 14061 argLen: 4, 14062 asm: arm.AMOVW, 14063 reg: regInfo{ 14064 inputs: []inputInfo{ 14065 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14066 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14067 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14068 }, 14069 }, 14070 }, 14071 { 14072 name: "MOVWstoreshiftRL", 14073 auxType: auxInt32, 14074 argLen: 4, 14075 asm: arm.AMOVW, 14076 reg: regInfo{ 14077 inputs: []inputInfo{ 14078 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14079 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14080 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14081 }, 14082 }, 14083 }, 14084 { 14085 name: "MOVWstoreshiftRA", 14086 auxType: auxInt32, 14087 argLen: 4, 14088 asm: arm.AMOVW, 14089 reg: regInfo{ 14090 inputs: []inputInfo{ 14091 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14092 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14093 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14094 }, 14095 }, 14096 }, 14097 { 14098 name: "MOVBstoreidx", 14099 argLen: 4, 14100 asm: arm.AMOVB, 14101 reg: regInfo{ 14102 inputs: []inputInfo{ 14103 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14104 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14105 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14106 }, 14107 }, 14108 }, 14109 { 14110 name: "MOVHstoreidx", 14111 argLen: 4, 14112 asm: arm.AMOVH, 14113 reg: regInfo{ 14114 inputs: []inputInfo{ 14115 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14116 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14117 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14118 }, 14119 }, 14120 }, 14121 { 14122 name: "MOVBreg", 14123 argLen: 1, 14124 asm: arm.AMOVBS, 14125 reg: regInfo{ 14126 inputs: []inputInfo{ 14127 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14128 }, 14129 outputs: []outputInfo{ 14130 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14131 }, 14132 }, 14133 }, 14134 { 14135 name: "MOVBUreg", 14136 argLen: 1, 14137 asm: arm.AMOVBU, 14138 reg: regInfo{ 14139 inputs: []inputInfo{ 14140 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14141 }, 14142 outputs: []outputInfo{ 14143 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14144 }, 14145 }, 14146 }, 14147 { 14148 name: "MOVHreg", 14149 argLen: 1, 14150 asm: arm.AMOVHS, 14151 reg: regInfo{ 14152 inputs: []inputInfo{ 14153 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14154 }, 14155 outputs: []outputInfo{ 14156 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14157 }, 14158 }, 14159 }, 14160 { 14161 name: "MOVHUreg", 14162 argLen: 1, 14163 asm: arm.AMOVHU, 14164 reg: regInfo{ 14165 inputs: []inputInfo{ 14166 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14167 }, 14168 outputs: []outputInfo{ 14169 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14170 }, 14171 }, 14172 }, 14173 { 14174 name: "MOVWreg", 14175 argLen: 1, 14176 asm: arm.AMOVW, 14177 reg: regInfo{ 14178 inputs: []inputInfo{ 14179 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14180 }, 14181 outputs: []outputInfo{ 14182 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14183 }, 14184 }, 14185 }, 14186 { 14187 name: "MOVWnop", 14188 argLen: 1, 14189 resultInArg0: true, 14190 reg: regInfo{ 14191 inputs: []inputInfo{ 14192 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14193 }, 14194 outputs: []outputInfo{ 14195 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14196 }, 14197 }, 14198 }, 14199 { 14200 name: "MOVWF", 14201 argLen: 1, 14202 asm: arm.AMOVWF, 14203 reg: regInfo{ 14204 inputs: []inputInfo{ 14205 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14206 }, 14207 clobbers: 2147483648, // F15 14208 outputs: []outputInfo{ 14209 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14210 }, 14211 }, 14212 }, 14213 { 14214 name: "MOVWD", 14215 argLen: 1, 14216 asm: arm.AMOVWD, 14217 reg: regInfo{ 14218 inputs: []inputInfo{ 14219 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14220 }, 14221 clobbers: 2147483648, // F15 14222 outputs: []outputInfo{ 14223 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14224 }, 14225 }, 14226 }, 14227 { 14228 name: "MOVWUF", 14229 argLen: 1, 14230 asm: arm.AMOVWF, 14231 reg: regInfo{ 14232 inputs: []inputInfo{ 14233 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14234 }, 14235 clobbers: 2147483648, // F15 14236 outputs: []outputInfo{ 14237 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14238 }, 14239 }, 14240 }, 14241 { 14242 name: "MOVWUD", 14243 argLen: 1, 14244 asm: arm.AMOVWD, 14245 reg: regInfo{ 14246 inputs: []inputInfo{ 14247 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14248 }, 14249 clobbers: 2147483648, // F15 14250 outputs: []outputInfo{ 14251 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14252 }, 14253 }, 14254 }, 14255 { 14256 name: "MOVFW", 14257 argLen: 1, 14258 asm: arm.AMOVFW, 14259 reg: regInfo{ 14260 inputs: []inputInfo{ 14261 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14262 }, 14263 clobbers: 2147483648, // F15 14264 outputs: []outputInfo{ 14265 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14266 }, 14267 }, 14268 }, 14269 { 14270 name: "MOVDW", 14271 argLen: 1, 14272 asm: arm.AMOVDW, 14273 reg: regInfo{ 14274 inputs: []inputInfo{ 14275 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14276 }, 14277 clobbers: 2147483648, // F15 14278 outputs: []outputInfo{ 14279 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14280 }, 14281 }, 14282 }, 14283 { 14284 name: "MOVFWU", 14285 argLen: 1, 14286 asm: arm.AMOVFW, 14287 reg: regInfo{ 14288 inputs: []inputInfo{ 14289 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14290 }, 14291 clobbers: 2147483648, // F15 14292 outputs: []outputInfo{ 14293 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14294 }, 14295 }, 14296 }, 14297 { 14298 name: "MOVDWU", 14299 argLen: 1, 14300 asm: arm.AMOVDW, 14301 reg: regInfo{ 14302 inputs: []inputInfo{ 14303 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14304 }, 14305 clobbers: 2147483648, // F15 14306 outputs: []outputInfo{ 14307 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14308 }, 14309 }, 14310 }, 14311 { 14312 name: "MOVFD", 14313 argLen: 1, 14314 asm: arm.AMOVFD, 14315 reg: regInfo{ 14316 inputs: []inputInfo{ 14317 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14318 }, 14319 outputs: []outputInfo{ 14320 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14321 }, 14322 }, 14323 }, 14324 { 14325 name: "MOVDF", 14326 argLen: 1, 14327 asm: arm.AMOVDF, 14328 reg: regInfo{ 14329 inputs: []inputInfo{ 14330 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14331 }, 14332 outputs: []outputInfo{ 14333 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14334 }, 14335 }, 14336 }, 14337 { 14338 name: "CMOVWHSconst", 14339 auxType: auxInt32, 14340 argLen: 2, 14341 resultInArg0: true, 14342 asm: arm.AMOVW, 14343 reg: regInfo{ 14344 inputs: []inputInfo{ 14345 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14346 }, 14347 outputs: []outputInfo{ 14348 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14349 }, 14350 }, 14351 }, 14352 { 14353 name: "CMOVWLSconst", 14354 auxType: auxInt32, 14355 argLen: 2, 14356 resultInArg0: true, 14357 asm: arm.AMOVW, 14358 reg: regInfo{ 14359 inputs: []inputInfo{ 14360 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14361 }, 14362 outputs: []outputInfo{ 14363 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14364 }, 14365 }, 14366 }, 14367 { 14368 name: "SRAcond", 14369 argLen: 3, 14370 asm: arm.ASRA, 14371 reg: regInfo{ 14372 inputs: []inputInfo{ 14373 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14374 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14375 }, 14376 outputs: []outputInfo{ 14377 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14378 }, 14379 }, 14380 }, 14381 { 14382 name: "CALLstatic", 14383 auxType: auxSymOff, 14384 argLen: 1, 14385 clobberFlags: true, 14386 call: true, 14387 symEffect: SymNone, 14388 reg: regInfo{ 14389 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14390 }, 14391 }, 14392 { 14393 name: "CALLclosure", 14394 auxType: auxInt64, 14395 argLen: 3, 14396 clobberFlags: true, 14397 call: true, 14398 reg: regInfo{ 14399 inputs: []inputInfo{ 14400 {1, 128}, // R7 14401 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 14402 }, 14403 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14404 }, 14405 }, 14406 { 14407 name: "CALLinter", 14408 auxType: auxInt64, 14409 argLen: 2, 14410 clobberFlags: true, 14411 call: true, 14412 reg: regInfo{ 14413 inputs: []inputInfo{ 14414 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14415 }, 14416 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14417 }, 14418 }, 14419 { 14420 name: "LoweredNilCheck", 14421 argLen: 2, 14422 nilCheck: true, 14423 faultOnNilArg0: true, 14424 reg: regInfo{ 14425 inputs: []inputInfo{ 14426 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14427 }, 14428 }, 14429 }, 14430 { 14431 name: "Equal", 14432 argLen: 1, 14433 reg: regInfo{ 14434 outputs: []outputInfo{ 14435 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14436 }, 14437 }, 14438 }, 14439 { 14440 name: "NotEqual", 14441 argLen: 1, 14442 reg: regInfo{ 14443 outputs: []outputInfo{ 14444 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14445 }, 14446 }, 14447 }, 14448 { 14449 name: "LessThan", 14450 argLen: 1, 14451 reg: regInfo{ 14452 outputs: []outputInfo{ 14453 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14454 }, 14455 }, 14456 }, 14457 { 14458 name: "LessEqual", 14459 argLen: 1, 14460 reg: regInfo{ 14461 outputs: []outputInfo{ 14462 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14463 }, 14464 }, 14465 }, 14466 { 14467 name: "GreaterThan", 14468 argLen: 1, 14469 reg: regInfo{ 14470 outputs: []outputInfo{ 14471 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14472 }, 14473 }, 14474 }, 14475 { 14476 name: "GreaterEqual", 14477 argLen: 1, 14478 reg: regInfo{ 14479 outputs: []outputInfo{ 14480 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14481 }, 14482 }, 14483 }, 14484 { 14485 name: "LessThanU", 14486 argLen: 1, 14487 reg: regInfo{ 14488 outputs: []outputInfo{ 14489 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14490 }, 14491 }, 14492 }, 14493 { 14494 name: "LessEqualU", 14495 argLen: 1, 14496 reg: regInfo{ 14497 outputs: []outputInfo{ 14498 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14499 }, 14500 }, 14501 }, 14502 { 14503 name: "GreaterThanU", 14504 argLen: 1, 14505 reg: regInfo{ 14506 outputs: []outputInfo{ 14507 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14508 }, 14509 }, 14510 }, 14511 { 14512 name: "GreaterEqualU", 14513 argLen: 1, 14514 reg: regInfo{ 14515 outputs: []outputInfo{ 14516 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14517 }, 14518 }, 14519 }, 14520 { 14521 name: "DUFFZERO", 14522 auxType: auxInt64, 14523 argLen: 3, 14524 faultOnNilArg0: true, 14525 reg: regInfo{ 14526 inputs: []inputInfo{ 14527 {0, 2}, // R1 14528 {1, 1}, // R0 14529 }, 14530 clobbers: 16386, // R1 R14 14531 }, 14532 }, 14533 { 14534 name: "DUFFCOPY", 14535 auxType: auxInt64, 14536 argLen: 3, 14537 faultOnNilArg0: true, 14538 faultOnNilArg1: true, 14539 reg: regInfo{ 14540 inputs: []inputInfo{ 14541 {0, 4}, // R2 14542 {1, 2}, // R1 14543 }, 14544 clobbers: 16391, // R0 R1 R2 R14 14545 }, 14546 }, 14547 { 14548 name: "LoweredZero", 14549 auxType: auxInt64, 14550 argLen: 4, 14551 clobberFlags: true, 14552 faultOnNilArg0: true, 14553 reg: regInfo{ 14554 inputs: []inputInfo{ 14555 {0, 2}, // R1 14556 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14557 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14558 }, 14559 clobbers: 2, // R1 14560 }, 14561 }, 14562 { 14563 name: "LoweredMove", 14564 auxType: auxInt64, 14565 argLen: 4, 14566 clobberFlags: true, 14567 faultOnNilArg0: true, 14568 faultOnNilArg1: true, 14569 reg: regInfo{ 14570 inputs: []inputInfo{ 14571 {0, 4}, // R2 14572 {1, 2}, // R1 14573 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14574 }, 14575 clobbers: 6, // R1 R2 14576 }, 14577 }, 14578 { 14579 name: "LoweredGetClosurePtr", 14580 argLen: 0, 14581 zeroWidth: true, 14582 reg: regInfo{ 14583 outputs: []outputInfo{ 14584 {0, 128}, // R7 14585 }, 14586 }, 14587 }, 14588 { 14589 name: "LoweredGetCallerSP", 14590 argLen: 0, 14591 rematerializeable: true, 14592 reg: regInfo{ 14593 outputs: []outputInfo{ 14594 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14595 }, 14596 }, 14597 }, 14598 { 14599 name: "LoweredGetCallerPC", 14600 argLen: 0, 14601 rematerializeable: true, 14602 reg: regInfo{ 14603 outputs: []outputInfo{ 14604 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14605 }, 14606 }, 14607 }, 14608 { 14609 name: "FlagEQ", 14610 argLen: 0, 14611 reg: regInfo{}, 14612 }, 14613 { 14614 name: "FlagLT_ULT", 14615 argLen: 0, 14616 reg: regInfo{}, 14617 }, 14618 { 14619 name: "FlagLT_UGT", 14620 argLen: 0, 14621 reg: regInfo{}, 14622 }, 14623 { 14624 name: "FlagGT_UGT", 14625 argLen: 0, 14626 reg: regInfo{}, 14627 }, 14628 { 14629 name: "FlagGT_ULT", 14630 argLen: 0, 14631 reg: regInfo{}, 14632 }, 14633 { 14634 name: "InvertFlags", 14635 argLen: 1, 14636 reg: regInfo{}, 14637 }, 14638 { 14639 name: "LoweredWB", 14640 auxType: auxSym, 14641 argLen: 3, 14642 clobberFlags: true, 14643 symEffect: SymNone, 14644 reg: regInfo{ 14645 inputs: []inputInfo{ 14646 {0, 4}, // R2 14647 {1, 8}, // R3 14648 }, 14649 clobbers: 4294918144, // R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14650 }, 14651 }, 14652 14653 { 14654 name: "ADD", 14655 argLen: 2, 14656 commutative: true, 14657 asm: arm64.AADD, 14658 reg: regInfo{ 14659 inputs: []inputInfo{ 14660 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14661 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14662 }, 14663 outputs: []outputInfo{ 14664 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14665 }, 14666 }, 14667 }, 14668 { 14669 name: "ADDconst", 14670 auxType: auxInt64, 14671 argLen: 1, 14672 asm: arm64.AADD, 14673 reg: regInfo{ 14674 inputs: []inputInfo{ 14675 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 14676 }, 14677 outputs: []outputInfo{ 14678 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14679 }, 14680 }, 14681 }, 14682 { 14683 name: "SUB", 14684 argLen: 2, 14685 asm: arm64.ASUB, 14686 reg: regInfo{ 14687 inputs: []inputInfo{ 14688 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14689 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14690 }, 14691 outputs: []outputInfo{ 14692 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14693 }, 14694 }, 14695 }, 14696 { 14697 name: "SUBconst", 14698 auxType: auxInt64, 14699 argLen: 1, 14700 asm: arm64.ASUB, 14701 reg: regInfo{ 14702 inputs: []inputInfo{ 14703 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14704 }, 14705 outputs: []outputInfo{ 14706 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14707 }, 14708 }, 14709 }, 14710 { 14711 name: "MUL", 14712 argLen: 2, 14713 commutative: true, 14714 asm: arm64.AMUL, 14715 reg: regInfo{ 14716 inputs: []inputInfo{ 14717 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14718 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14719 }, 14720 outputs: []outputInfo{ 14721 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14722 }, 14723 }, 14724 }, 14725 { 14726 name: "MULW", 14727 argLen: 2, 14728 commutative: true, 14729 asm: arm64.AMULW, 14730 reg: regInfo{ 14731 inputs: []inputInfo{ 14732 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14733 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14734 }, 14735 outputs: []outputInfo{ 14736 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14737 }, 14738 }, 14739 }, 14740 { 14741 name: "MNEG", 14742 argLen: 2, 14743 commutative: true, 14744 asm: arm64.AMNEG, 14745 reg: regInfo{ 14746 inputs: []inputInfo{ 14747 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14748 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14749 }, 14750 outputs: []outputInfo{ 14751 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14752 }, 14753 }, 14754 }, 14755 { 14756 name: "MNEGW", 14757 argLen: 2, 14758 commutative: true, 14759 asm: arm64.AMNEGW, 14760 reg: regInfo{ 14761 inputs: []inputInfo{ 14762 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14763 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14764 }, 14765 outputs: []outputInfo{ 14766 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14767 }, 14768 }, 14769 }, 14770 { 14771 name: "MULH", 14772 argLen: 2, 14773 commutative: true, 14774 asm: arm64.ASMULH, 14775 reg: regInfo{ 14776 inputs: []inputInfo{ 14777 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14778 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14779 }, 14780 outputs: []outputInfo{ 14781 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14782 }, 14783 }, 14784 }, 14785 { 14786 name: "UMULH", 14787 argLen: 2, 14788 commutative: true, 14789 asm: arm64.AUMULH, 14790 reg: regInfo{ 14791 inputs: []inputInfo{ 14792 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14793 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14794 }, 14795 outputs: []outputInfo{ 14796 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14797 }, 14798 }, 14799 }, 14800 { 14801 name: "MULL", 14802 argLen: 2, 14803 commutative: true, 14804 asm: arm64.ASMULL, 14805 reg: regInfo{ 14806 inputs: []inputInfo{ 14807 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14808 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14809 }, 14810 outputs: []outputInfo{ 14811 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14812 }, 14813 }, 14814 }, 14815 { 14816 name: "UMULL", 14817 argLen: 2, 14818 commutative: true, 14819 asm: arm64.AUMULL, 14820 reg: regInfo{ 14821 inputs: []inputInfo{ 14822 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14823 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14824 }, 14825 outputs: []outputInfo{ 14826 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14827 }, 14828 }, 14829 }, 14830 { 14831 name: "DIV", 14832 argLen: 2, 14833 asm: arm64.ASDIV, 14834 reg: regInfo{ 14835 inputs: []inputInfo{ 14836 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14837 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14838 }, 14839 outputs: []outputInfo{ 14840 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14841 }, 14842 }, 14843 }, 14844 { 14845 name: "UDIV", 14846 argLen: 2, 14847 asm: arm64.AUDIV, 14848 reg: regInfo{ 14849 inputs: []inputInfo{ 14850 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14851 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14852 }, 14853 outputs: []outputInfo{ 14854 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14855 }, 14856 }, 14857 }, 14858 { 14859 name: "DIVW", 14860 argLen: 2, 14861 asm: arm64.ASDIVW, 14862 reg: regInfo{ 14863 inputs: []inputInfo{ 14864 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14865 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14866 }, 14867 outputs: []outputInfo{ 14868 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14869 }, 14870 }, 14871 }, 14872 { 14873 name: "UDIVW", 14874 argLen: 2, 14875 asm: arm64.AUDIVW, 14876 reg: regInfo{ 14877 inputs: []inputInfo{ 14878 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14879 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14880 }, 14881 outputs: []outputInfo{ 14882 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14883 }, 14884 }, 14885 }, 14886 { 14887 name: "MOD", 14888 argLen: 2, 14889 asm: arm64.AREM, 14890 reg: regInfo{ 14891 inputs: []inputInfo{ 14892 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14893 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14894 }, 14895 outputs: []outputInfo{ 14896 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14897 }, 14898 }, 14899 }, 14900 { 14901 name: "UMOD", 14902 argLen: 2, 14903 asm: arm64.AUREM, 14904 reg: regInfo{ 14905 inputs: []inputInfo{ 14906 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14907 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14908 }, 14909 outputs: []outputInfo{ 14910 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14911 }, 14912 }, 14913 }, 14914 { 14915 name: "MODW", 14916 argLen: 2, 14917 asm: arm64.AREMW, 14918 reg: regInfo{ 14919 inputs: []inputInfo{ 14920 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14921 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14922 }, 14923 outputs: []outputInfo{ 14924 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14925 }, 14926 }, 14927 }, 14928 { 14929 name: "UMODW", 14930 argLen: 2, 14931 asm: arm64.AUREMW, 14932 reg: regInfo{ 14933 inputs: []inputInfo{ 14934 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14935 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14936 }, 14937 outputs: []outputInfo{ 14938 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14939 }, 14940 }, 14941 }, 14942 { 14943 name: "FADDS", 14944 argLen: 2, 14945 commutative: true, 14946 asm: arm64.AFADDS, 14947 reg: regInfo{ 14948 inputs: []inputInfo{ 14949 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14950 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14951 }, 14952 outputs: []outputInfo{ 14953 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14954 }, 14955 }, 14956 }, 14957 { 14958 name: "FADDD", 14959 argLen: 2, 14960 commutative: true, 14961 asm: arm64.AFADDD, 14962 reg: regInfo{ 14963 inputs: []inputInfo{ 14964 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14965 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14966 }, 14967 outputs: []outputInfo{ 14968 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14969 }, 14970 }, 14971 }, 14972 { 14973 name: "FSUBS", 14974 argLen: 2, 14975 asm: arm64.AFSUBS, 14976 reg: regInfo{ 14977 inputs: []inputInfo{ 14978 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14979 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14980 }, 14981 outputs: []outputInfo{ 14982 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14983 }, 14984 }, 14985 }, 14986 { 14987 name: "FSUBD", 14988 argLen: 2, 14989 asm: arm64.AFSUBD, 14990 reg: regInfo{ 14991 inputs: []inputInfo{ 14992 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14993 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14994 }, 14995 outputs: []outputInfo{ 14996 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14997 }, 14998 }, 14999 }, 15000 { 15001 name: "FMULS", 15002 argLen: 2, 15003 commutative: true, 15004 asm: arm64.AFMULS, 15005 reg: regInfo{ 15006 inputs: []inputInfo{ 15007 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15008 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15009 }, 15010 outputs: []outputInfo{ 15011 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15012 }, 15013 }, 15014 }, 15015 { 15016 name: "FMULD", 15017 argLen: 2, 15018 commutative: true, 15019 asm: arm64.AFMULD, 15020 reg: regInfo{ 15021 inputs: []inputInfo{ 15022 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15023 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15024 }, 15025 outputs: []outputInfo{ 15026 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15027 }, 15028 }, 15029 }, 15030 { 15031 name: "FNMULS", 15032 argLen: 2, 15033 commutative: true, 15034 asm: arm64.AFNMULS, 15035 reg: regInfo{ 15036 inputs: []inputInfo{ 15037 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15038 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15039 }, 15040 outputs: []outputInfo{ 15041 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15042 }, 15043 }, 15044 }, 15045 { 15046 name: "FNMULD", 15047 argLen: 2, 15048 commutative: true, 15049 asm: arm64.AFNMULD, 15050 reg: regInfo{ 15051 inputs: []inputInfo{ 15052 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15053 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15054 }, 15055 outputs: []outputInfo{ 15056 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15057 }, 15058 }, 15059 }, 15060 { 15061 name: "FDIVS", 15062 argLen: 2, 15063 asm: arm64.AFDIVS, 15064 reg: regInfo{ 15065 inputs: []inputInfo{ 15066 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15067 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15068 }, 15069 outputs: []outputInfo{ 15070 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15071 }, 15072 }, 15073 }, 15074 { 15075 name: "FDIVD", 15076 argLen: 2, 15077 asm: arm64.AFDIVD, 15078 reg: regInfo{ 15079 inputs: []inputInfo{ 15080 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15081 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15082 }, 15083 outputs: []outputInfo{ 15084 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15085 }, 15086 }, 15087 }, 15088 { 15089 name: "AND", 15090 argLen: 2, 15091 commutative: true, 15092 asm: arm64.AAND, 15093 reg: regInfo{ 15094 inputs: []inputInfo{ 15095 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15096 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15097 }, 15098 outputs: []outputInfo{ 15099 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15100 }, 15101 }, 15102 }, 15103 { 15104 name: "ANDconst", 15105 auxType: auxInt64, 15106 argLen: 1, 15107 asm: arm64.AAND, 15108 reg: regInfo{ 15109 inputs: []inputInfo{ 15110 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15111 }, 15112 outputs: []outputInfo{ 15113 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15114 }, 15115 }, 15116 }, 15117 { 15118 name: "OR", 15119 argLen: 2, 15120 commutative: true, 15121 asm: arm64.AORR, 15122 reg: regInfo{ 15123 inputs: []inputInfo{ 15124 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15125 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15126 }, 15127 outputs: []outputInfo{ 15128 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15129 }, 15130 }, 15131 }, 15132 { 15133 name: "ORconst", 15134 auxType: auxInt64, 15135 argLen: 1, 15136 asm: arm64.AORR, 15137 reg: regInfo{ 15138 inputs: []inputInfo{ 15139 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15140 }, 15141 outputs: []outputInfo{ 15142 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15143 }, 15144 }, 15145 }, 15146 { 15147 name: "XOR", 15148 argLen: 2, 15149 commutative: true, 15150 asm: arm64.AEOR, 15151 reg: regInfo{ 15152 inputs: []inputInfo{ 15153 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15154 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15155 }, 15156 outputs: []outputInfo{ 15157 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15158 }, 15159 }, 15160 }, 15161 { 15162 name: "XORconst", 15163 auxType: auxInt64, 15164 argLen: 1, 15165 asm: arm64.AEOR, 15166 reg: regInfo{ 15167 inputs: []inputInfo{ 15168 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15169 }, 15170 outputs: []outputInfo{ 15171 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15172 }, 15173 }, 15174 }, 15175 { 15176 name: "BIC", 15177 argLen: 2, 15178 asm: arm64.ABIC, 15179 reg: regInfo{ 15180 inputs: []inputInfo{ 15181 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15182 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15183 }, 15184 outputs: []outputInfo{ 15185 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15186 }, 15187 }, 15188 }, 15189 { 15190 name: "EON", 15191 argLen: 2, 15192 asm: arm64.AEON, 15193 reg: regInfo{ 15194 inputs: []inputInfo{ 15195 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15196 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15197 }, 15198 outputs: []outputInfo{ 15199 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15200 }, 15201 }, 15202 }, 15203 { 15204 name: "ORN", 15205 argLen: 2, 15206 asm: arm64.AORN, 15207 reg: regInfo{ 15208 inputs: []inputInfo{ 15209 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15210 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15211 }, 15212 outputs: []outputInfo{ 15213 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15214 }, 15215 }, 15216 }, 15217 { 15218 name: "LoweredMuluhilo", 15219 argLen: 2, 15220 resultNotInArgs: true, 15221 reg: regInfo{ 15222 inputs: []inputInfo{ 15223 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15224 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15225 }, 15226 outputs: []outputInfo{ 15227 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15228 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15229 }, 15230 }, 15231 }, 15232 { 15233 name: "MVN", 15234 argLen: 1, 15235 asm: arm64.AMVN, 15236 reg: regInfo{ 15237 inputs: []inputInfo{ 15238 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15239 }, 15240 outputs: []outputInfo{ 15241 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15242 }, 15243 }, 15244 }, 15245 { 15246 name: "NEG", 15247 argLen: 1, 15248 asm: arm64.ANEG, 15249 reg: regInfo{ 15250 inputs: []inputInfo{ 15251 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15252 }, 15253 outputs: []outputInfo{ 15254 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15255 }, 15256 }, 15257 }, 15258 { 15259 name: "FABSD", 15260 argLen: 1, 15261 asm: arm64.AFABSD, 15262 reg: regInfo{ 15263 inputs: []inputInfo{ 15264 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15265 }, 15266 outputs: []outputInfo{ 15267 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15268 }, 15269 }, 15270 }, 15271 { 15272 name: "FNEGS", 15273 argLen: 1, 15274 asm: arm64.AFNEGS, 15275 reg: regInfo{ 15276 inputs: []inputInfo{ 15277 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15278 }, 15279 outputs: []outputInfo{ 15280 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15281 }, 15282 }, 15283 }, 15284 { 15285 name: "FNEGD", 15286 argLen: 1, 15287 asm: arm64.AFNEGD, 15288 reg: regInfo{ 15289 inputs: []inputInfo{ 15290 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15291 }, 15292 outputs: []outputInfo{ 15293 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15294 }, 15295 }, 15296 }, 15297 { 15298 name: "FSQRTD", 15299 argLen: 1, 15300 asm: arm64.AFSQRTD, 15301 reg: regInfo{ 15302 inputs: []inputInfo{ 15303 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15304 }, 15305 outputs: []outputInfo{ 15306 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15307 }, 15308 }, 15309 }, 15310 { 15311 name: "REV", 15312 argLen: 1, 15313 asm: arm64.AREV, 15314 reg: regInfo{ 15315 inputs: []inputInfo{ 15316 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15317 }, 15318 outputs: []outputInfo{ 15319 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15320 }, 15321 }, 15322 }, 15323 { 15324 name: "REVW", 15325 argLen: 1, 15326 asm: arm64.AREVW, 15327 reg: regInfo{ 15328 inputs: []inputInfo{ 15329 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15330 }, 15331 outputs: []outputInfo{ 15332 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15333 }, 15334 }, 15335 }, 15336 { 15337 name: "REV16W", 15338 argLen: 1, 15339 asm: arm64.AREV16W, 15340 reg: regInfo{ 15341 inputs: []inputInfo{ 15342 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15343 }, 15344 outputs: []outputInfo{ 15345 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15346 }, 15347 }, 15348 }, 15349 { 15350 name: "RBIT", 15351 argLen: 1, 15352 asm: arm64.ARBIT, 15353 reg: regInfo{ 15354 inputs: []inputInfo{ 15355 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15356 }, 15357 outputs: []outputInfo{ 15358 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15359 }, 15360 }, 15361 }, 15362 { 15363 name: "RBITW", 15364 argLen: 1, 15365 asm: arm64.ARBITW, 15366 reg: regInfo{ 15367 inputs: []inputInfo{ 15368 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15369 }, 15370 outputs: []outputInfo{ 15371 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15372 }, 15373 }, 15374 }, 15375 { 15376 name: "CLZ", 15377 argLen: 1, 15378 asm: arm64.ACLZ, 15379 reg: regInfo{ 15380 inputs: []inputInfo{ 15381 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15382 }, 15383 outputs: []outputInfo{ 15384 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15385 }, 15386 }, 15387 }, 15388 { 15389 name: "CLZW", 15390 argLen: 1, 15391 asm: arm64.ACLZW, 15392 reg: regInfo{ 15393 inputs: []inputInfo{ 15394 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15395 }, 15396 outputs: []outputInfo{ 15397 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15398 }, 15399 }, 15400 }, 15401 { 15402 name: "VCNT", 15403 argLen: 1, 15404 asm: arm64.AVCNT, 15405 reg: regInfo{ 15406 inputs: []inputInfo{ 15407 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15408 }, 15409 outputs: []outputInfo{ 15410 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15411 }, 15412 }, 15413 }, 15414 { 15415 name: "VUADDLV", 15416 argLen: 1, 15417 asm: arm64.AVUADDLV, 15418 reg: regInfo{ 15419 inputs: []inputInfo{ 15420 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15421 }, 15422 outputs: []outputInfo{ 15423 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15424 }, 15425 }, 15426 }, 15427 { 15428 name: "LoweredRound32F", 15429 argLen: 1, 15430 resultInArg0: true, 15431 zeroWidth: true, 15432 reg: regInfo{ 15433 inputs: []inputInfo{ 15434 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15435 }, 15436 outputs: []outputInfo{ 15437 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15438 }, 15439 }, 15440 }, 15441 { 15442 name: "LoweredRound64F", 15443 argLen: 1, 15444 resultInArg0: true, 15445 zeroWidth: true, 15446 reg: regInfo{ 15447 inputs: []inputInfo{ 15448 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15449 }, 15450 outputs: []outputInfo{ 15451 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15452 }, 15453 }, 15454 }, 15455 { 15456 name: "FMADDS", 15457 argLen: 3, 15458 asm: arm64.AFMADDS, 15459 reg: regInfo{ 15460 inputs: []inputInfo{ 15461 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15462 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15463 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15464 }, 15465 outputs: []outputInfo{ 15466 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15467 }, 15468 }, 15469 }, 15470 { 15471 name: "FMADDD", 15472 argLen: 3, 15473 asm: arm64.AFMADDD, 15474 reg: regInfo{ 15475 inputs: []inputInfo{ 15476 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15477 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15478 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15479 }, 15480 outputs: []outputInfo{ 15481 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15482 }, 15483 }, 15484 }, 15485 { 15486 name: "FNMADDS", 15487 argLen: 3, 15488 asm: arm64.AFNMADDS, 15489 reg: regInfo{ 15490 inputs: []inputInfo{ 15491 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15492 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15493 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15494 }, 15495 outputs: []outputInfo{ 15496 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15497 }, 15498 }, 15499 }, 15500 { 15501 name: "FNMADDD", 15502 argLen: 3, 15503 asm: arm64.AFNMADDD, 15504 reg: regInfo{ 15505 inputs: []inputInfo{ 15506 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15507 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15508 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15509 }, 15510 outputs: []outputInfo{ 15511 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15512 }, 15513 }, 15514 }, 15515 { 15516 name: "FMSUBS", 15517 argLen: 3, 15518 asm: arm64.AFMSUBS, 15519 reg: regInfo{ 15520 inputs: []inputInfo{ 15521 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15522 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15523 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15524 }, 15525 outputs: []outputInfo{ 15526 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15527 }, 15528 }, 15529 }, 15530 { 15531 name: "FMSUBD", 15532 argLen: 3, 15533 asm: arm64.AFMSUBD, 15534 reg: regInfo{ 15535 inputs: []inputInfo{ 15536 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15537 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15538 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15539 }, 15540 outputs: []outputInfo{ 15541 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15542 }, 15543 }, 15544 }, 15545 { 15546 name: "FNMSUBS", 15547 argLen: 3, 15548 asm: arm64.AFNMSUBS, 15549 reg: regInfo{ 15550 inputs: []inputInfo{ 15551 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15552 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15553 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15554 }, 15555 outputs: []outputInfo{ 15556 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15557 }, 15558 }, 15559 }, 15560 { 15561 name: "FNMSUBD", 15562 argLen: 3, 15563 asm: arm64.AFNMSUBD, 15564 reg: regInfo{ 15565 inputs: []inputInfo{ 15566 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15567 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15568 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15569 }, 15570 outputs: []outputInfo{ 15571 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15572 }, 15573 }, 15574 }, 15575 { 15576 name: "MADD", 15577 argLen: 3, 15578 asm: arm64.AMADD, 15579 reg: regInfo{ 15580 inputs: []inputInfo{ 15581 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15582 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15583 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15584 }, 15585 outputs: []outputInfo{ 15586 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15587 }, 15588 }, 15589 }, 15590 { 15591 name: "MADDW", 15592 argLen: 3, 15593 asm: arm64.AMADDW, 15594 reg: regInfo{ 15595 inputs: []inputInfo{ 15596 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15597 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15598 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15599 }, 15600 outputs: []outputInfo{ 15601 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15602 }, 15603 }, 15604 }, 15605 { 15606 name: "MSUB", 15607 argLen: 3, 15608 asm: arm64.AMSUB, 15609 reg: regInfo{ 15610 inputs: []inputInfo{ 15611 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15612 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15613 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15614 }, 15615 outputs: []outputInfo{ 15616 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15617 }, 15618 }, 15619 }, 15620 { 15621 name: "MSUBW", 15622 argLen: 3, 15623 asm: arm64.AMSUBW, 15624 reg: regInfo{ 15625 inputs: []inputInfo{ 15626 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15627 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15628 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15629 }, 15630 outputs: []outputInfo{ 15631 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15632 }, 15633 }, 15634 }, 15635 { 15636 name: "SLL", 15637 argLen: 2, 15638 asm: arm64.ALSL, 15639 reg: regInfo{ 15640 inputs: []inputInfo{ 15641 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15642 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15643 }, 15644 outputs: []outputInfo{ 15645 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15646 }, 15647 }, 15648 }, 15649 { 15650 name: "SLLconst", 15651 auxType: auxInt64, 15652 argLen: 1, 15653 asm: arm64.ALSL, 15654 reg: regInfo{ 15655 inputs: []inputInfo{ 15656 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15657 }, 15658 outputs: []outputInfo{ 15659 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15660 }, 15661 }, 15662 }, 15663 { 15664 name: "SRL", 15665 argLen: 2, 15666 asm: arm64.ALSR, 15667 reg: regInfo{ 15668 inputs: []inputInfo{ 15669 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15670 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15671 }, 15672 outputs: []outputInfo{ 15673 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15674 }, 15675 }, 15676 }, 15677 { 15678 name: "SRLconst", 15679 auxType: auxInt64, 15680 argLen: 1, 15681 asm: arm64.ALSR, 15682 reg: regInfo{ 15683 inputs: []inputInfo{ 15684 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15685 }, 15686 outputs: []outputInfo{ 15687 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15688 }, 15689 }, 15690 }, 15691 { 15692 name: "SRA", 15693 argLen: 2, 15694 asm: arm64.AASR, 15695 reg: regInfo{ 15696 inputs: []inputInfo{ 15697 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15698 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15699 }, 15700 outputs: []outputInfo{ 15701 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15702 }, 15703 }, 15704 }, 15705 { 15706 name: "SRAconst", 15707 auxType: auxInt64, 15708 argLen: 1, 15709 asm: arm64.AASR, 15710 reg: regInfo{ 15711 inputs: []inputInfo{ 15712 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15713 }, 15714 outputs: []outputInfo{ 15715 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15716 }, 15717 }, 15718 }, 15719 { 15720 name: "ROR", 15721 argLen: 2, 15722 asm: arm64.AROR, 15723 reg: regInfo{ 15724 inputs: []inputInfo{ 15725 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15726 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15727 }, 15728 outputs: []outputInfo{ 15729 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15730 }, 15731 }, 15732 }, 15733 { 15734 name: "RORW", 15735 argLen: 2, 15736 asm: arm64.ARORW, 15737 reg: regInfo{ 15738 inputs: []inputInfo{ 15739 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15740 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15741 }, 15742 outputs: []outputInfo{ 15743 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15744 }, 15745 }, 15746 }, 15747 { 15748 name: "RORconst", 15749 auxType: auxInt64, 15750 argLen: 1, 15751 asm: arm64.AROR, 15752 reg: regInfo{ 15753 inputs: []inputInfo{ 15754 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15755 }, 15756 outputs: []outputInfo{ 15757 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15758 }, 15759 }, 15760 }, 15761 { 15762 name: "RORWconst", 15763 auxType: auxInt64, 15764 argLen: 1, 15765 asm: arm64.ARORW, 15766 reg: regInfo{ 15767 inputs: []inputInfo{ 15768 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15769 }, 15770 outputs: []outputInfo{ 15771 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15772 }, 15773 }, 15774 }, 15775 { 15776 name: "EXTRconst", 15777 auxType: auxInt64, 15778 argLen: 2, 15779 asm: arm64.AEXTR, 15780 reg: regInfo{ 15781 inputs: []inputInfo{ 15782 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15783 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15784 }, 15785 outputs: []outputInfo{ 15786 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15787 }, 15788 }, 15789 }, 15790 { 15791 name: "EXTRWconst", 15792 auxType: auxInt64, 15793 argLen: 2, 15794 asm: arm64.AEXTRW, 15795 reg: regInfo{ 15796 inputs: []inputInfo{ 15797 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15798 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15799 }, 15800 outputs: []outputInfo{ 15801 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15802 }, 15803 }, 15804 }, 15805 { 15806 name: "CMP", 15807 argLen: 2, 15808 asm: arm64.ACMP, 15809 reg: regInfo{ 15810 inputs: []inputInfo{ 15811 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15812 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15813 }, 15814 }, 15815 }, 15816 { 15817 name: "CMPconst", 15818 auxType: auxInt64, 15819 argLen: 1, 15820 asm: arm64.ACMP, 15821 reg: regInfo{ 15822 inputs: []inputInfo{ 15823 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15824 }, 15825 }, 15826 }, 15827 { 15828 name: "CMPW", 15829 argLen: 2, 15830 asm: arm64.ACMPW, 15831 reg: regInfo{ 15832 inputs: []inputInfo{ 15833 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15834 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15835 }, 15836 }, 15837 }, 15838 { 15839 name: "CMPWconst", 15840 auxType: auxInt32, 15841 argLen: 1, 15842 asm: arm64.ACMPW, 15843 reg: regInfo{ 15844 inputs: []inputInfo{ 15845 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15846 }, 15847 }, 15848 }, 15849 { 15850 name: "CMN", 15851 argLen: 2, 15852 commutative: true, 15853 asm: arm64.ACMN, 15854 reg: regInfo{ 15855 inputs: []inputInfo{ 15856 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15857 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15858 }, 15859 }, 15860 }, 15861 { 15862 name: "CMNconst", 15863 auxType: auxInt64, 15864 argLen: 1, 15865 asm: arm64.ACMN, 15866 reg: regInfo{ 15867 inputs: []inputInfo{ 15868 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15869 }, 15870 }, 15871 }, 15872 { 15873 name: "CMNW", 15874 argLen: 2, 15875 commutative: true, 15876 asm: arm64.ACMNW, 15877 reg: regInfo{ 15878 inputs: []inputInfo{ 15879 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15880 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15881 }, 15882 }, 15883 }, 15884 { 15885 name: "CMNWconst", 15886 auxType: auxInt32, 15887 argLen: 1, 15888 asm: arm64.ACMNW, 15889 reg: regInfo{ 15890 inputs: []inputInfo{ 15891 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15892 }, 15893 }, 15894 }, 15895 { 15896 name: "TST", 15897 argLen: 2, 15898 commutative: true, 15899 asm: arm64.ATST, 15900 reg: regInfo{ 15901 inputs: []inputInfo{ 15902 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15903 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15904 }, 15905 }, 15906 }, 15907 { 15908 name: "TSTconst", 15909 auxType: auxInt64, 15910 argLen: 1, 15911 asm: arm64.ATST, 15912 reg: regInfo{ 15913 inputs: []inputInfo{ 15914 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15915 }, 15916 }, 15917 }, 15918 { 15919 name: "TSTW", 15920 argLen: 2, 15921 commutative: true, 15922 asm: arm64.ATSTW, 15923 reg: regInfo{ 15924 inputs: []inputInfo{ 15925 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15926 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15927 }, 15928 }, 15929 }, 15930 { 15931 name: "TSTWconst", 15932 auxType: auxInt32, 15933 argLen: 1, 15934 asm: arm64.ATSTW, 15935 reg: regInfo{ 15936 inputs: []inputInfo{ 15937 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15938 }, 15939 }, 15940 }, 15941 { 15942 name: "FCMPS", 15943 argLen: 2, 15944 asm: arm64.AFCMPS, 15945 reg: regInfo{ 15946 inputs: []inputInfo{ 15947 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15948 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15949 }, 15950 }, 15951 }, 15952 { 15953 name: "FCMPD", 15954 argLen: 2, 15955 asm: arm64.AFCMPD, 15956 reg: regInfo{ 15957 inputs: []inputInfo{ 15958 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15959 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15960 }, 15961 }, 15962 }, 15963 { 15964 name: "MVNshiftLL", 15965 auxType: auxInt64, 15966 argLen: 1, 15967 asm: arm64.AMVN, 15968 reg: regInfo{ 15969 inputs: []inputInfo{ 15970 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15971 }, 15972 outputs: []outputInfo{ 15973 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15974 }, 15975 }, 15976 }, 15977 { 15978 name: "MVNshiftRL", 15979 auxType: auxInt64, 15980 argLen: 1, 15981 asm: arm64.AMVN, 15982 reg: regInfo{ 15983 inputs: []inputInfo{ 15984 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15985 }, 15986 outputs: []outputInfo{ 15987 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15988 }, 15989 }, 15990 }, 15991 { 15992 name: "MVNshiftRA", 15993 auxType: auxInt64, 15994 argLen: 1, 15995 asm: arm64.AMVN, 15996 reg: regInfo{ 15997 inputs: []inputInfo{ 15998 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15999 }, 16000 outputs: []outputInfo{ 16001 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16002 }, 16003 }, 16004 }, 16005 { 16006 name: "NEGshiftLL", 16007 auxType: auxInt64, 16008 argLen: 1, 16009 asm: arm64.ANEG, 16010 reg: regInfo{ 16011 inputs: []inputInfo{ 16012 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16013 }, 16014 outputs: []outputInfo{ 16015 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16016 }, 16017 }, 16018 }, 16019 { 16020 name: "NEGshiftRL", 16021 auxType: auxInt64, 16022 argLen: 1, 16023 asm: arm64.ANEG, 16024 reg: regInfo{ 16025 inputs: []inputInfo{ 16026 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16027 }, 16028 outputs: []outputInfo{ 16029 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16030 }, 16031 }, 16032 }, 16033 { 16034 name: "NEGshiftRA", 16035 auxType: auxInt64, 16036 argLen: 1, 16037 asm: arm64.ANEG, 16038 reg: regInfo{ 16039 inputs: []inputInfo{ 16040 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16041 }, 16042 outputs: []outputInfo{ 16043 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16044 }, 16045 }, 16046 }, 16047 { 16048 name: "ADDshiftLL", 16049 auxType: auxInt64, 16050 argLen: 2, 16051 asm: arm64.AADD, 16052 reg: regInfo{ 16053 inputs: []inputInfo{ 16054 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16055 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16056 }, 16057 outputs: []outputInfo{ 16058 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16059 }, 16060 }, 16061 }, 16062 { 16063 name: "ADDshiftRL", 16064 auxType: auxInt64, 16065 argLen: 2, 16066 asm: arm64.AADD, 16067 reg: regInfo{ 16068 inputs: []inputInfo{ 16069 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16070 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16071 }, 16072 outputs: []outputInfo{ 16073 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16074 }, 16075 }, 16076 }, 16077 { 16078 name: "ADDshiftRA", 16079 auxType: auxInt64, 16080 argLen: 2, 16081 asm: arm64.AADD, 16082 reg: regInfo{ 16083 inputs: []inputInfo{ 16084 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16085 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16086 }, 16087 outputs: []outputInfo{ 16088 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16089 }, 16090 }, 16091 }, 16092 { 16093 name: "SUBshiftLL", 16094 auxType: auxInt64, 16095 argLen: 2, 16096 asm: arm64.ASUB, 16097 reg: regInfo{ 16098 inputs: []inputInfo{ 16099 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16100 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16101 }, 16102 outputs: []outputInfo{ 16103 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16104 }, 16105 }, 16106 }, 16107 { 16108 name: "SUBshiftRL", 16109 auxType: auxInt64, 16110 argLen: 2, 16111 asm: arm64.ASUB, 16112 reg: regInfo{ 16113 inputs: []inputInfo{ 16114 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16115 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16116 }, 16117 outputs: []outputInfo{ 16118 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16119 }, 16120 }, 16121 }, 16122 { 16123 name: "SUBshiftRA", 16124 auxType: auxInt64, 16125 argLen: 2, 16126 asm: arm64.ASUB, 16127 reg: regInfo{ 16128 inputs: []inputInfo{ 16129 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16130 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16131 }, 16132 outputs: []outputInfo{ 16133 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16134 }, 16135 }, 16136 }, 16137 { 16138 name: "ANDshiftLL", 16139 auxType: auxInt64, 16140 argLen: 2, 16141 asm: arm64.AAND, 16142 reg: regInfo{ 16143 inputs: []inputInfo{ 16144 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16145 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16146 }, 16147 outputs: []outputInfo{ 16148 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16149 }, 16150 }, 16151 }, 16152 { 16153 name: "ANDshiftRL", 16154 auxType: auxInt64, 16155 argLen: 2, 16156 asm: arm64.AAND, 16157 reg: regInfo{ 16158 inputs: []inputInfo{ 16159 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16160 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16161 }, 16162 outputs: []outputInfo{ 16163 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16164 }, 16165 }, 16166 }, 16167 { 16168 name: "ANDshiftRA", 16169 auxType: auxInt64, 16170 argLen: 2, 16171 asm: arm64.AAND, 16172 reg: regInfo{ 16173 inputs: []inputInfo{ 16174 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16175 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16176 }, 16177 outputs: []outputInfo{ 16178 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16179 }, 16180 }, 16181 }, 16182 { 16183 name: "ORshiftLL", 16184 auxType: auxInt64, 16185 argLen: 2, 16186 asm: arm64.AORR, 16187 reg: regInfo{ 16188 inputs: []inputInfo{ 16189 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16190 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16191 }, 16192 outputs: []outputInfo{ 16193 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16194 }, 16195 }, 16196 }, 16197 { 16198 name: "ORshiftRL", 16199 auxType: auxInt64, 16200 argLen: 2, 16201 asm: arm64.AORR, 16202 reg: regInfo{ 16203 inputs: []inputInfo{ 16204 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16205 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16206 }, 16207 outputs: []outputInfo{ 16208 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16209 }, 16210 }, 16211 }, 16212 { 16213 name: "ORshiftRA", 16214 auxType: auxInt64, 16215 argLen: 2, 16216 asm: arm64.AORR, 16217 reg: regInfo{ 16218 inputs: []inputInfo{ 16219 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16220 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16221 }, 16222 outputs: []outputInfo{ 16223 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16224 }, 16225 }, 16226 }, 16227 { 16228 name: "XORshiftLL", 16229 auxType: auxInt64, 16230 argLen: 2, 16231 asm: arm64.AEOR, 16232 reg: regInfo{ 16233 inputs: []inputInfo{ 16234 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16235 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16236 }, 16237 outputs: []outputInfo{ 16238 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16239 }, 16240 }, 16241 }, 16242 { 16243 name: "XORshiftRL", 16244 auxType: auxInt64, 16245 argLen: 2, 16246 asm: arm64.AEOR, 16247 reg: regInfo{ 16248 inputs: []inputInfo{ 16249 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16250 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16251 }, 16252 outputs: []outputInfo{ 16253 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16254 }, 16255 }, 16256 }, 16257 { 16258 name: "XORshiftRA", 16259 auxType: auxInt64, 16260 argLen: 2, 16261 asm: arm64.AEOR, 16262 reg: regInfo{ 16263 inputs: []inputInfo{ 16264 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16265 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16266 }, 16267 outputs: []outputInfo{ 16268 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16269 }, 16270 }, 16271 }, 16272 { 16273 name: "BICshiftLL", 16274 auxType: auxInt64, 16275 argLen: 2, 16276 asm: arm64.ABIC, 16277 reg: regInfo{ 16278 inputs: []inputInfo{ 16279 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16280 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16281 }, 16282 outputs: []outputInfo{ 16283 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16284 }, 16285 }, 16286 }, 16287 { 16288 name: "BICshiftRL", 16289 auxType: auxInt64, 16290 argLen: 2, 16291 asm: arm64.ABIC, 16292 reg: regInfo{ 16293 inputs: []inputInfo{ 16294 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16295 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16296 }, 16297 outputs: []outputInfo{ 16298 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16299 }, 16300 }, 16301 }, 16302 { 16303 name: "BICshiftRA", 16304 auxType: auxInt64, 16305 argLen: 2, 16306 asm: arm64.ABIC, 16307 reg: regInfo{ 16308 inputs: []inputInfo{ 16309 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16310 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16311 }, 16312 outputs: []outputInfo{ 16313 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16314 }, 16315 }, 16316 }, 16317 { 16318 name: "EONshiftLL", 16319 auxType: auxInt64, 16320 argLen: 2, 16321 asm: arm64.AEON, 16322 reg: regInfo{ 16323 inputs: []inputInfo{ 16324 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16325 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16326 }, 16327 outputs: []outputInfo{ 16328 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16329 }, 16330 }, 16331 }, 16332 { 16333 name: "EONshiftRL", 16334 auxType: auxInt64, 16335 argLen: 2, 16336 asm: arm64.AEON, 16337 reg: regInfo{ 16338 inputs: []inputInfo{ 16339 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16340 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16341 }, 16342 outputs: []outputInfo{ 16343 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16344 }, 16345 }, 16346 }, 16347 { 16348 name: "EONshiftRA", 16349 auxType: auxInt64, 16350 argLen: 2, 16351 asm: arm64.AEON, 16352 reg: regInfo{ 16353 inputs: []inputInfo{ 16354 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16355 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16356 }, 16357 outputs: []outputInfo{ 16358 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16359 }, 16360 }, 16361 }, 16362 { 16363 name: "ORNshiftLL", 16364 auxType: auxInt64, 16365 argLen: 2, 16366 asm: arm64.AORN, 16367 reg: regInfo{ 16368 inputs: []inputInfo{ 16369 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16370 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16371 }, 16372 outputs: []outputInfo{ 16373 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16374 }, 16375 }, 16376 }, 16377 { 16378 name: "ORNshiftRL", 16379 auxType: auxInt64, 16380 argLen: 2, 16381 asm: arm64.AORN, 16382 reg: regInfo{ 16383 inputs: []inputInfo{ 16384 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16385 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16386 }, 16387 outputs: []outputInfo{ 16388 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16389 }, 16390 }, 16391 }, 16392 { 16393 name: "ORNshiftRA", 16394 auxType: auxInt64, 16395 argLen: 2, 16396 asm: arm64.AORN, 16397 reg: regInfo{ 16398 inputs: []inputInfo{ 16399 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16400 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16401 }, 16402 outputs: []outputInfo{ 16403 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16404 }, 16405 }, 16406 }, 16407 { 16408 name: "CMPshiftLL", 16409 auxType: auxInt64, 16410 argLen: 2, 16411 asm: arm64.ACMP, 16412 reg: regInfo{ 16413 inputs: []inputInfo{ 16414 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16415 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16416 }, 16417 }, 16418 }, 16419 { 16420 name: "CMPshiftRL", 16421 auxType: auxInt64, 16422 argLen: 2, 16423 asm: arm64.ACMP, 16424 reg: regInfo{ 16425 inputs: []inputInfo{ 16426 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16427 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16428 }, 16429 }, 16430 }, 16431 { 16432 name: "CMPshiftRA", 16433 auxType: auxInt64, 16434 argLen: 2, 16435 asm: arm64.ACMP, 16436 reg: regInfo{ 16437 inputs: []inputInfo{ 16438 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16439 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16440 }, 16441 }, 16442 }, 16443 { 16444 name: "CMNshiftLL", 16445 auxType: auxInt64, 16446 argLen: 2, 16447 asm: arm64.ACMN, 16448 reg: regInfo{ 16449 inputs: []inputInfo{ 16450 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16451 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16452 }, 16453 }, 16454 }, 16455 { 16456 name: "CMNshiftRL", 16457 auxType: auxInt64, 16458 argLen: 2, 16459 asm: arm64.ACMN, 16460 reg: regInfo{ 16461 inputs: []inputInfo{ 16462 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16463 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16464 }, 16465 }, 16466 }, 16467 { 16468 name: "CMNshiftRA", 16469 auxType: auxInt64, 16470 argLen: 2, 16471 asm: arm64.ACMN, 16472 reg: regInfo{ 16473 inputs: []inputInfo{ 16474 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16475 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16476 }, 16477 }, 16478 }, 16479 { 16480 name: "TSTshiftLL", 16481 auxType: auxInt64, 16482 argLen: 2, 16483 asm: arm64.ATST, 16484 reg: regInfo{ 16485 inputs: []inputInfo{ 16486 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16487 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16488 }, 16489 }, 16490 }, 16491 { 16492 name: "TSTshiftRL", 16493 auxType: auxInt64, 16494 argLen: 2, 16495 asm: arm64.ATST, 16496 reg: regInfo{ 16497 inputs: []inputInfo{ 16498 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16499 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16500 }, 16501 }, 16502 }, 16503 { 16504 name: "TSTshiftRA", 16505 auxType: auxInt64, 16506 argLen: 2, 16507 asm: arm64.ATST, 16508 reg: regInfo{ 16509 inputs: []inputInfo{ 16510 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16511 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16512 }, 16513 }, 16514 }, 16515 { 16516 name: "BFI", 16517 auxType: auxInt64, 16518 argLen: 2, 16519 resultInArg0: true, 16520 asm: arm64.ABFI, 16521 reg: regInfo{ 16522 inputs: []inputInfo{ 16523 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16524 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16525 }, 16526 outputs: []outputInfo{ 16527 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16528 }, 16529 }, 16530 }, 16531 { 16532 name: "BFXIL", 16533 auxType: auxInt64, 16534 argLen: 2, 16535 resultInArg0: true, 16536 asm: arm64.ABFXIL, 16537 reg: regInfo{ 16538 inputs: []inputInfo{ 16539 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16540 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16541 }, 16542 outputs: []outputInfo{ 16543 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16544 }, 16545 }, 16546 }, 16547 { 16548 name: "SBFIZ", 16549 auxType: auxInt64, 16550 argLen: 1, 16551 asm: arm64.ASBFIZ, 16552 reg: regInfo{ 16553 inputs: []inputInfo{ 16554 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16555 }, 16556 outputs: []outputInfo{ 16557 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16558 }, 16559 }, 16560 }, 16561 { 16562 name: "SBFX", 16563 auxType: auxInt64, 16564 argLen: 1, 16565 asm: arm64.ASBFX, 16566 reg: regInfo{ 16567 inputs: []inputInfo{ 16568 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16569 }, 16570 outputs: []outputInfo{ 16571 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16572 }, 16573 }, 16574 }, 16575 { 16576 name: "UBFIZ", 16577 auxType: auxInt64, 16578 argLen: 1, 16579 asm: arm64.AUBFIZ, 16580 reg: regInfo{ 16581 inputs: []inputInfo{ 16582 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16583 }, 16584 outputs: []outputInfo{ 16585 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16586 }, 16587 }, 16588 }, 16589 { 16590 name: "UBFX", 16591 auxType: auxInt64, 16592 argLen: 1, 16593 asm: arm64.AUBFX, 16594 reg: regInfo{ 16595 inputs: []inputInfo{ 16596 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16597 }, 16598 outputs: []outputInfo{ 16599 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16600 }, 16601 }, 16602 }, 16603 { 16604 name: "MOVDconst", 16605 auxType: auxInt64, 16606 argLen: 0, 16607 rematerializeable: true, 16608 asm: arm64.AMOVD, 16609 reg: regInfo{ 16610 outputs: []outputInfo{ 16611 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16612 }, 16613 }, 16614 }, 16615 { 16616 name: "FMOVSconst", 16617 auxType: auxFloat64, 16618 argLen: 0, 16619 rematerializeable: true, 16620 asm: arm64.AFMOVS, 16621 reg: regInfo{ 16622 outputs: []outputInfo{ 16623 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16624 }, 16625 }, 16626 }, 16627 { 16628 name: "FMOVDconst", 16629 auxType: auxFloat64, 16630 argLen: 0, 16631 rematerializeable: true, 16632 asm: arm64.AFMOVD, 16633 reg: regInfo{ 16634 outputs: []outputInfo{ 16635 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16636 }, 16637 }, 16638 }, 16639 { 16640 name: "MOVDaddr", 16641 auxType: auxSymOff, 16642 argLen: 1, 16643 rematerializeable: true, 16644 symEffect: SymAddr, 16645 asm: arm64.AMOVD, 16646 reg: regInfo{ 16647 inputs: []inputInfo{ 16648 {0, 9223372037928517632}, // SP SB 16649 }, 16650 outputs: []outputInfo{ 16651 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16652 }, 16653 }, 16654 }, 16655 { 16656 name: "MOVBload", 16657 auxType: auxSymOff, 16658 argLen: 2, 16659 faultOnNilArg0: true, 16660 symEffect: SymRead, 16661 asm: arm64.AMOVB, 16662 reg: regInfo{ 16663 inputs: []inputInfo{ 16664 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16665 }, 16666 outputs: []outputInfo{ 16667 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16668 }, 16669 }, 16670 }, 16671 { 16672 name: "MOVBUload", 16673 auxType: auxSymOff, 16674 argLen: 2, 16675 faultOnNilArg0: true, 16676 symEffect: SymRead, 16677 asm: arm64.AMOVBU, 16678 reg: regInfo{ 16679 inputs: []inputInfo{ 16680 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16681 }, 16682 outputs: []outputInfo{ 16683 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16684 }, 16685 }, 16686 }, 16687 { 16688 name: "MOVHload", 16689 auxType: auxSymOff, 16690 argLen: 2, 16691 faultOnNilArg0: true, 16692 symEffect: SymRead, 16693 asm: arm64.AMOVH, 16694 reg: regInfo{ 16695 inputs: []inputInfo{ 16696 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16697 }, 16698 outputs: []outputInfo{ 16699 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16700 }, 16701 }, 16702 }, 16703 { 16704 name: "MOVHUload", 16705 auxType: auxSymOff, 16706 argLen: 2, 16707 faultOnNilArg0: true, 16708 symEffect: SymRead, 16709 asm: arm64.AMOVHU, 16710 reg: regInfo{ 16711 inputs: []inputInfo{ 16712 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16713 }, 16714 outputs: []outputInfo{ 16715 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16716 }, 16717 }, 16718 }, 16719 { 16720 name: "MOVWload", 16721 auxType: auxSymOff, 16722 argLen: 2, 16723 faultOnNilArg0: true, 16724 symEffect: SymRead, 16725 asm: arm64.AMOVW, 16726 reg: regInfo{ 16727 inputs: []inputInfo{ 16728 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16729 }, 16730 outputs: []outputInfo{ 16731 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16732 }, 16733 }, 16734 }, 16735 { 16736 name: "MOVWUload", 16737 auxType: auxSymOff, 16738 argLen: 2, 16739 faultOnNilArg0: true, 16740 symEffect: SymRead, 16741 asm: arm64.AMOVWU, 16742 reg: regInfo{ 16743 inputs: []inputInfo{ 16744 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16745 }, 16746 outputs: []outputInfo{ 16747 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16748 }, 16749 }, 16750 }, 16751 { 16752 name: "MOVDload", 16753 auxType: auxSymOff, 16754 argLen: 2, 16755 faultOnNilArg0: true, 16756 symEffect: SymRead, 16757 asm: arm64.AMOVD, 16758 reg: regInfo{ 16759 inputs: []inputInfo{ 16760 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16761 }, 16762 outputs: []outputInfo{ 16763 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16764 }, 16765 }, 16766 }, 16767 { 16768 name: "FMOVSload", 16769 auxType: auxSymOff, 16770 argLen: 2, 16771 faultOnNilArg0: true, 16772 symEffect: SymRead, 16773 asm: arm64.AFMOVS, 16774 reg: regInfo{ 16775 inputs: []inputInfo{ 16776 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16777 }, 16778 outputs: []outputInfo{ 16779 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16780 }, 16781 }, 16782 }, 16783 { 16784 name: "FMOVDload", 16785 auxType: auxSymOff, 16786 argLen: 2, 16787 faultOnNilArg0: true, 16788 symEffect: SymRead, 16789 asm: arm64.AFMOVD, 16790 reg: regInfo{ 16791 inputs: []inputInfo{ 16792 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16793 }, 16794 outputs: []outputInfo{ 16795 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16796 }, 16797 }, 16798 }, 16799 { 16800 name: "MOVDloadidx", 16801 argLen: 3, 16802 asm: arm64.AMOVD, 16803 reg: regInfo{ 16804 inputs: []inputInfo{ 16805 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16806 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16807 }, 16808 outputs: []outputInfo{ 16809 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16810 }, 16811 }, 16812 }, 16813 { 16814 name: "MOVWloadidx", 16815 argLen: 3, 16816 asm: arm64.AMOVW, 16817 reg: regInfo{ 16818 inputs: []inputInfo{ 16819 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16820 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16821 }, 16822 outputs: []outputInfo{ 16823 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16824 }, 16825 }, 16826 }, 16827 { 16828 name: "MOVWUloadidx", 16829 argLen: 3, 16830 asm: arm64.AMOVWU, 16831 reg: regInfo{ 16832 inputs: []inputInfo{ 16833 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16834 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16835 }, 16836 outputs: []outputInfo{ 16837 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16838 }, 16839 }, 16840 }, 16841 { 16842 name: "MOVHloadidx", 16843 argLen: 3, 16844 asm: arm64.AMOVH, 16845 reg: regInfo{ 16846 inputs: []inputInfo{ 16847 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16848 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16849 }, 16850 outputs: []outputInfo{ 16851 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16852 }, 16853 }, 16854 }, 16855 { 16856 name: "MOVHUloadidx", 16857 argLen: 3, 16858 asm: arm64.AMOVHU, 16859 reg: regInfo{ 16860 inputs: []inputInfo{ 16861 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16862 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16863 }, 16864 outputs: []outputInfo{ 16865 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16866 }, 16867 }, 16868 }, 16869 { 16870 name: "MOVBloadidx", 16871 argLen: 3, 16872 asm: arm64.AMOVB, 16873 reg: regInfo{ 16874 inputs: []inputInfo{ 16875 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16876 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16877 }, 16878 outputs: []outputInfo{ 16879 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16880 }, 16881 }, 16882 }, 16883 { 16884 name: "MOVBUloadidx", 16885 argLen: 3, 16886 asm: arm64.AMOVBU, 16887 reg: regInfo{ 16888 inputs: []inputInfo{ 16889 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16890 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16891 }, 16892 outputs: []outputInfo{ 16893 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16894 }, 16895 }, 16896 }, 16897 { 16898 name: "FMOVSloadidx", 16899 argLen: 3, 16900 asm: arm64.AFMOVS, 16901 reg: regInfo{ 16902 inputs: []inputInfo{ 16903 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16904 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16905 }, 16906 outputs: []outputInfo{ 16907 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16908 }, 16909 }, 16910 }, 16911 { 16912 name: "FMOVDloadidx", 16913 argLen: 3, 16914 asm: arm64.AFMOVD, 16915 reg: regInfo{ 16916 inputs: []inputInfo{ 16917 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16918 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16919 }, 16920 outputs: []outputInfo{ 16921 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16922 }, 16923 }, 16924 }, 16925 { 16926 name: "MOVHloadidx2", 16927 argLen: 3, 16928 asm: arm64.AMOVH, 16929 reg: regInfo{ 16930 inputs: []inputInfo{ 16931 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16932 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16933 }, 16934 outputs: []outputInfo{ 16935 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16936 }, 16937 }, 16938 }, 16939 { 16940 name: "MOVHUloadidx2", 16941 argLen: 3, 16942 asm: arm64.AMOVHU, 16943 reg: regInfo{ 16944 inputs: []inputInfo{ 16945 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16946 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16947 }, 16948 outputs: []outputInfo{ 16949 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16950 }, 16951 }, 16952 }, 16953 { 16954 name: "MOVWloadidx4", 16955 argLen: 3, 16956 asm: arm64.AMOVW, 16957 reg: regInfo{ 16958 inputs: []inputInfo{ 16959 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16960 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16961 }, 16962 outputs: []outputInfo{ 16963 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16964 }, 16965 }, 16966 }, 16967 { 16968 name: "MOVWUloadidx4", 16969 argLen: 3, 16970 asm: arm64.AMOVWU, 16971 reg: regInfo{ 16972 inputs: []inputInfo{ 16973 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16974 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16975 }, 16976 outputs: []outputInfo{ 16977 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16978 }, 16979 }, 16980 }, 16981 { 16982 name: "MOVDloadidx8", 16983 argLen: 3, 16984 asm: arm64.AMOVD, 16985 reg: regInfo{ 16986 inputs: []inputInfo{ 16987 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16988 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16989 }, 16990 outputs: []outputInfo{ 16991 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16992 }, 16993 }, 16994 }, 16995 { 16996 name: "MOVBstore", 16997 auxType: auxSymOff, 16998 argLen: 3, 16999 faultOnNilArg0: true, 17000 symEffect: SymWrite, 17001 asm: arm64.AMOVB, 17002 reg: regInfo{ 17003 inputs: []inputInfo{ 17004 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17005 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17006 }, 17007 }, 17008 }, 17009 { 17010 name: "MOVHstore", 17011 auxType: auxSymOff, 17012 argLen: 3, 17013 faultOnNilArg0: true, 17014 symEffect: SymWrite, 17015 asm: arm64.AMOVH, 17016 reg: regInfo{ 17017 inputs: []inputInfo{ 17018 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17019 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17020 }, 17021 }, 17022 }, 17023 { 17024 name: "MOVWstore", 17025 auxType: auxSymOff, 17026 argLen: 3, 17027 faultOnNilArg0: true, 17028 symEffect: SymWrite, 17029 asm: arm64.AMOVW, 17030 reg: regInfo{ 17031 inputs: []inputInfo{ 17032 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17033 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17034 }, 17035 }, 17036 }, 17037 { 17038 name: "MOVDstore", 17039 auxType: auxSymOff, 17040 argLen: 3, 17041 faultOnNilArg0: true, 17042 symEffect: SymWrite, 17043 asm: arm64.AMOVD, 17044 reg: regInfo{ 17045 inputs: []inputInfo{ 17046 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17047 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17048 }, 17049 }, 17050 }, 17051 { 17052 name: "STP", 17053 auxType: auxSymOff, 17054 argLen: 4, 17055 faultOnNilArg0: true, 17056 symEffect: SymWrite, 17057 asm: arm64.ASTP, 17058 reg: regInfo{ 17059 inputs: []inputInfo{ 17060 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17061 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17062 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17063 }, 17064 }, 17065 }, 17066 { 17067 name: "FMOVSstore", 17068 auxType: auxSymOff, 17069 argLen: 3, 17070 faultOnNilArg0: true, 17071 symEffect: SymWrite, 17072 asm: arm64.AFMOVS, 17073 reg: regInfo{ 17074 inputs: []inputInfo{ 17075 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17076 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17077 }, 17078 }, 17079 }, 17080 { 17081 name: "FMOVDstore", 17082 auxType: auxSymOff, 17083 argLen: 3, 17084 faultOnNilArg0: true, 17085 symEffect: SymWrite, 17086 asm: arm64.AFMOVD, 17087 reg: regInfo{ 17088 inputs: []inputInfo{ 17089 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17090 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17091 }, 17092 }, 17093 }, 17094 { 17095 name: "MOVBstoreidx", 17096 argLen: 4, 17097 asm: arm64.AMOVB, 17098 reg: regInfo{ 17099 inputs: []inputInfo{ 17100 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17101 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17102 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17103 }, 17104 }, 17105 }, 17106 { 17107 name: "MOVHstoreidx", 17108 argLen: 4, 17109 asm: arm64.AMOVH, 17110 reg: regInfo{ 17111 inputs: []inputInfo{ 17112 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17113 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17114 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17115 }, 17116 }, 17117 }, 17118 { 17119 name: "MOVWstoreidx", 17120 argLen: 4, 17121 asm: arm64.AMOVW, 17122 reg: regInfo{ 17123 inputs: []inputInfo{ 17124 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17125 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17126 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17127 }, 17128 }, 17129 }, 17130 { 17131 name: "MOVDstoreidx", 17132 argLen: 4, 17133 asm: arm64.AMOVD, 17134 reg: regInfo{ 17135 inputs: []inputInfo{ 17136 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17137 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17138 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17139 }, 17140 }, 17141 }, 17142 { 17143 name: "FMOVSstoreidx", 17144 argLen: 4, 17145 asm: arm64.AFMOVS, 17146 reg: regInfo{ 17147 inputs: []inputInfo{ 17148 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17149 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17150 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17151 }, 17152 }, 17153 }, 17154 { 17155 name: "FMOVDstoreidx", 17156 argLen: 4, 17157 asm: arm64.AFMOVD, 17158 reg: regInfo{ 17159 inputs: []inputInfo{ 17160 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17161 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17162 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17163 }, 17164 }, 17165 }, 17166 { 17167 name: "MOVHstoreidx2", 17168 argLen: 4, 17169 asm: arm64.AMOVH, 17170 reg: regInfo{ 17171 inputs: []inputInfo{ 17172 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17173 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17174 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17175 }, 17176 }, 17177 }, 17178 { 17179 name: "MOVWstoreidx4", 17180 argLen: 4, 17181 asm: arm64.AMOVW, 17182 reg: regInfo{ 17183 inputs: []inputInfo{ 17184 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17185 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17186 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17187 }, 17188 }, 17189 }, 17190 { 17191 name: "MOVDstoreidx8", 17192 argLen: 4, 17193 asm: arm64.AMOVD, 17194 reg: regInfo{ 17195 inputs: []inputInfo{ 17196 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17197 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17198 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17199 }, 17200 }, 17201 }, 17202 { 17203 name: "MOVBstorezero", 17204 auxType: auxSymOff, 17205 argLen: 2, 17206 faultOnNilArg0: true, 17207 symEffect: SymWrite, 17208 asm: arm64.AMOVB, 17209 reg: regInfo{ 17210 inputs: []inputInfo{ 17211 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17212 }, 17213 }, 17214 }, 17215 { 17216 name: "MOVHstorezero", 17217 auxType: auxSymOff, 17218 argLen: 2, 17219 faultOnNilArg0: true, 17220 symEffect: SymWrite, 17221 asm: arm64.AMOVH, 17222 reg: regInfo{ 17223 inputs: []inputInfo{ 17224 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17225 }, 17226 }, 17227 }, 17228 { 17229 name: "MOVWstorezero", 17230 auxType: auxSymOff, 17231 argLen: 2, 17232 faultOnNilArg0: true, 17233 symEffect: SymWrite, 17234 asm: arm64.AMOVW, 17235 reg: regInfo{ 17236 inputs: []inputInfo{ 17237 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17238 }, 17239 }, 17240 }, 17241 { 17242 name: "MOVDstorezero", 17243 auxType: auxSymOff, 17244 argLen: 2, 17245 faultOnNilArg0: true, 17246 symEffect: SymWrite, 17247 asm: arm64.AMOVD, 17248 reg: regInfo{ 17249 inputs: []inputInfo{ 17250 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17251 }, 17252 }, 17253 }, 17254 { 17255 name: "MOVQstorezero", 17256 auxType: auxSymOff, 17257 argLen: 2, 17258 faultOnNilArg0: true, 17259 symEffect: SymWrite, 17260 asm: arm64.ASTP, 17261 reg: regInfo{ 17262 inputs: []inputInfo{ 17263 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17264 }, 17265 }, 17266 }, 17267 { 17268 name: "MOVBstorezeroidx", 17269 argLen: 3, 17270 asm: arm64.AMOVB, 17271 reg: regInfo{ 17272 inputs: []inputInfo{ 17273 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17274 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17275 }, 17276 }, 17277 }, 17278 { 17279 name: "MOVHstorezeroidx", 17280 argLen: 3, 17281 asm: arm64.AMOVH, 17282 reg: regInfo{ 17283 inputs: []inputInfo{ 17284 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17285 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17286 }, 17287 }, 17288 }, 17289 { 17290 name: "MOVWstorezeroidx", 17291 argLen: 3, 17292 asm: arm64.AMOVW, 17293 reg: regInfo{ 17294 inputs: []inputInfo{ 17295 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17296 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17297 }, 17298 }, 17299 }, 17300 { 17301 name: "MOVDstorezeroidx", 17302 argLen: 3, 17303 asm: arm64.AMOVD, 17304 reg: regInfo{ 17305 inputs: []inputInfo{ 17306 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17307 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17308 }, 17309 }, 17310 }, 17311 { 17312 name: "MOVHstorezeroidx2", 17313 argLen: 3, 17314 asm: arm64.AMOVH, 17315 reg: regInfo{ 17316 inputs: []inputInfo{ 17317 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17318 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17319 }, 17320 }, 17321 }, 17322 { 17323 name: "MOVWstorezeroidx4", 17324 argLen: 3, 17325 asm: arm64.AMOVW, 17326 reg: regInfo{ 17327 inputs: []inputInfo{ 17328 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17329 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17330 }, 17331 }, 17332 }, 17333 { 17334 name: "MOVDstorezeroidx8", 17335 argLen: 3, 17336 asm: arm64.AMOVD, 17337 reg: regInfo{ 17338 inputs: []inputInfo{ 17339 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17340 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17341 }, 17342 }, 17343 }, 17344 { 17345 name: "FMOVDgpfp", 17346 argLen: 1, 17347 asm: arm64.AFMOVD, 17348 reg: regInfo{ 17349 inputs: []inputInfo{ 17350 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17351 }, 17352 outputs: []outputInfo{ 17353 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17354 }, 17355 }, 17356 }, 17357 { 17358 name: "FMOVDfpgp", 17359 argLen: 1, 17360 asm: arm64.AFMOVD, 17361 reg: regInfo{ 17362 inputs: []inputInfo{ 17363 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17364 }, 17365 outputs: []outputInfo{ 17366 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17367 }, 17368 }, 17369 }, 17370 { 17371 name: "FMOVSgpfp", 17372 argLen: 1, 17373 asm: arm64.AFMOVS, 17374 reg: regInfo{ 17375 inputs: []inputInfo{ 17376 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17377 }, 17378 outputs: []outputInfo{ 17379 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17380 }, 17381 }, 17382 }, 17383 { 17384 name: "FMOVSfpgp", 17385 argLen: 1, 17386 asm: arm64.AFMOVS, 17387 reg: regInfo{ 17388 inputs: []inputInfo{ 17389 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17390 }, 17391 outputs: []outputInfo{ 17392 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17393 }, 17394 }, 17395 }, 17396 { 17397 name: "MOVBreg", 17398 argLen: 1, 17399 asm: arm64.AMOVB, 17400 reg: regInfo{ 17401 inputs: []inputInfo{ 17402 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17403 }, 17404 outputs: []outputInfo{ 17405 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17406 }, 17407 }, 17408 }, 17409 { 17410 name: "MOVBUreg", 17411 argLen: 1, 17412 asm: arm64.AMOVBU, 17413 reg: regInfo{ 17414 inputs: []inputInfo{ 17415 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17416 }, 17417 outputs: []outputInfo{ 17418 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17419 }, 17420 }, 17421 }, 17422 { 17423 name: "MOVHreg", 17424 argLen: 1, 17425 asm: arm64.AMOVH, 17426 reg: regInfo{ 17427 inputs: []inputInfo{ 17428 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17429 }, 17430 outputs: []outputInfo{ 17431 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17432 }, 17433 }, 17434 }, 17435 { 17436 name: "MOVHUreg", 17437 argLen: 1, 17438 asm: arm64.AMOVHU, 17439 reg: regInfo{ 17440 inputs: []inputInfo{ 17441 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17442 }, 17443 outputs: []outputInfo{ 17444 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17445 }, 17446 }, 17447 }, 17448 { 17449 name: "MOVWreg", 17450 argLen: 1, 17451 asm: arm64.AMOVW, 17452 reg: regInfo{ 17453 inputs: []inputInfo{ 17454 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17455 }, 17456 outputs: []outputInfo{ 17457 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17458 }, 17459 }, 17460 }, 17461 { 17462 name: "MOVWUreg", 17463 argLen: 1, 17464 asm: arm64.AMOVWU, 17465 reg: regInfo{ 17466 inputs: []inputInfo{ 17467 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17468 }, 17469 outputs: []outputInfo{ 17470 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17471 }, 17472 }, 17473 }, 17474 { 17475 name: "MOVDreg", 17476 argLen: 1, 17477 asm: arm64.AMOVD, 17478 reg: regInfo{ 17479 inputs: []inputInfo{ 17480 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17481 }, 17482 outputs: []outputInfo{ 17483 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17484 }, 17485 }, 17486 }, 17487 { 17488 name: "MOVDnop", 17489 argLen: 1, 17490 resultInArg0: true, 17491 reg: regInfo{ 17492 inputs: []inputInfo{ 17493 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17494 }, 17495 outputs: []outputInfo{ 17496 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17497 }, 17498 }, 17499 }, 17500 { 17501 name: "SCVTFWS", 17502 argLen: 1, 17503 asm: arm64.ASCVTFWS, 17504 reg: regInfo{ 17505 inputs: []inputInfo{ 17506 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17507 }, 17508 outputs: []outputInfo{ 17509 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17510 }, 17511 }, 17512 }, 17513 { 17514 name: "SCVTFWD", 17515 argLen: 1, 17516 asm: arm64.ASCVTFWD, 17517 reg: regInfo{ 17518 inputs: []inputInfo{ 17519 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17520 }, 17521 outputs: []outputInfo{ 17522 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17523 }, 17524 }, 17525 }, 17526 { 17527 name: "UCVTFWS", 17528 argLen: 1, 17529 asm: arm64.AUCVTFWS, 17530 reg: regInfo{ 17531 inputs: []inputInfo{ 17532 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17533 }, 17534 outputs: []outputInfo{ 17535 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17536 }, 17537 }, 17538 }, 17539 { 17540 name: "UCVTFWD", 17541 argLen: 1, 17542 asm: arm64.AUCVTFWD, 17543 reg: regInfo{ 17544 inputs: []inputInfo{ 17545 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17546 }, 17547 outputs: []outputInfo{ 17548 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17549 }, 17550 }, 17551 }, 17552 { 17553 name: "SCVTFS", 17554 argLen: 1, 17555 asm: arm64.ASCVTFS, 17556 reg: regInfo{ 17557 inputs: []inputInfo{ 17558 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17559 }, 17560 outputs: []outputInfo{ 17561 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17562 }, 17563 }, 17564 }, 17565 { 17566 name: "SCVTFD", 17567 argLen: 1, 17568 asm: arm64.ASCVTFD, 17569 reg: regInfo{ 17570 inputs: []inputInfo{ 17571 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17572 }, 17573 outputs: []outputInfo{ 17574 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17575 }, 17576 }, 17577 }, 17578 { 17579 name: "UCVTFS", 17580 argLen: 1, 17581 asm: arm64.AUCVTFS, 17582 reg: regInfo{ 17583 inputs: []inputInfo{ 17584 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17585 }, 17586 outputs: []outputInfo{ 17587 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17588 }, 17589 }, 17590 }, 17591 { 17592 name: "UCVTFD", 17593 argLen: 1, 17594 asm: arm64.AUCVTFD, 17595 reg: regInfo{ 17596 inputs: []inputInfo{ 17597 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17598 }, 17599 outputs: []outputInfo{ 17600 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17601 }, 17602 }, 17603 }, 17604 { 17605 name: "FCVTZSSW", 17606 argLen: 1, 17607 asm: arm64.AFCVTZSSW, 17608 reg: regInfo{ 17609 inputs: []inputInfo{ 17610 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17611 }, 17612 outputs: []outputInfo{ 17613 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17614 }, 17615 }, 17616 }, 17617 { 17618 name: "FCVTZSDW", 17619 argLen: 1, 17620 asm: arm64.AFCVTZSDW, 17621 reg: regInfo{ 17622 inputs: []inputInfo{ 17623 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17624 }, 17625 outputs: []outputInfo{ 17626 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17627 }, 17628 }, 17629 }, 17630 { 17631 name: "FCVTZUSW", 17632 argLen: 1, 17633 asm: arm64.AFCVTZUSW, 17634 reg: regInfo{ 17635 inputs: []inputInfo{ 17636 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17637 }, 17638 outputs: []outputInfo{ 17639 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17640 }, 17641 }, 17642 }, 17643 { 17644 name: "FCVTZUDW", 17645 argLen: 1, 17646 asm: arm64.AFCVTZUDW, 17647 reg: regInfo{ 17648 inputs: []inputInfo{ 17649 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17650 }, 17651 outputs: []outputInfo{ 17652 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17653 }, 17654 }, 17655 }, 17656 { 17657 name: "FCVTZSS", 17658 argLen: 1, 17659 asm: arm64.AFCVTZSS, 17660 reg: regInfo{ 17661 inputs: []inputInfo{ 17662 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17663 }, 17664 outputs: []outputInfo{ 17665 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17666 }, 17667 }, 17668 }, 17669 { 17670 name: "FCVTZSD", 17671 argLen: 1, 17672 asm: arm64.AFCVTZSD, 17673 reg: regInfo{ 17674 inputs: []inputInfo{ 17675 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17676 }, 17677 outputs: []outputInfo{ 17678 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17679 }, 17680 }, 17681 }, 17682 { 17683 name: "FCVTZUS", 17684 argLen: 1, 17685 asm: arm64.AFCVTZUS, 17686 reg: regInfo{ 17687 inputs: []inputInfo{ 17688 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17689 }, 17690 outputs: []outputInfo{ 17691 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17692 }, 17693 }, 17694 }, 17695 { 17696 name: "FCVTZUD", 17697 argLen: 1, 17698 asm: arm64.AFCVTZUD, 17699 reg: regInfo{ 17700 inputs: []inputInfo{ 17701 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17702 }, 17703 outputs: []outputInfo{ 17704 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17705 }, 17706 }, 17707 }, 17708 { 17709 name: "FCVTSD", 17710 argLen: 1, 17711 asm: arm64.AFCVTSD, 17712 reg: regInfo{ 17713 inputs: []inputInfo{ 17714 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17715 }, 17716 outputs: []outputInfo{ 17717 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17718 }, 17719 }, 17720 }, 17721 { 17722 name: "FCVTDS", 17723 argLen: 1, 17724 asm: arm64.AFCVTDS, 17725 reg: regInfo{ 17726 inputs: []inputInfo{ 17727 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17728 }, 17729 outputs: []outputInfo{ 17730 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17731 }, 17732 }, 17733 }, 17734 { 17735 name: "FRINTAD", 17736 argLen: 1, 17737 asm: arm64.AFRINTAD, 17738 reg: regInfo{ 17739 inputs: []inputInfo{ 17740 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17741 }, 17742 outputs: []outputInfo{ 17743 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17744 }, 17745 }, 17746 }, 17747 { 17748 name: "FRINTMD", 17749 argLen: 1, 17750 asm: arm64.AFRINTMD, 17751 reg: regInfo{ 17752 inputs: []inputInfo{ 17753 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17754 }, 17755 outputs: []outputInfo{ 17756 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17757 }, 17758 }, 17759 }, 17760 { 17761 name: "FRINTND", 17762 argLen: 1, 17763 asm: arm64.AFRINTND, 17764 reg: regInfo{ 17765 inputs: []inputInfo{ 17766 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17767 }, 17768 outputs: []outputInfo{ 17769 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17770 }, 17771 }, 17772 }, 17773 { 17774 name: "FRINTPD", 17775 argLen: 1, 17776 asm: arm64.AFRINTPD, 17777 reg: regInfo{ 17778 inputs: []inputInfo{ 17779 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17780 }, 17781 outputs: []outputInfo{ 17782 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17783 }, 17784 }, 17785 }, 17786 { 17787 name: "FRINTZD", 17788 argLen: 1, 17789 asm: arm64.AFRINTZD, 17790 reg: regInfo{ 17791 inputs: []inputInfo{ 17792 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17793 }, 17794 outputs: []outputInfo{ 17795 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17796 }, 17797 }, 17798 }, 17799 { 17800 name: "CSEL", 17801 auxType: auxCCop, 17802 argLen: 3, 17803 asm: arm64.ACSEL, 17804 reg: regInfo{ 17805 inputs: []inputInfo{ 17806 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17807 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17808 }, 17809 outputs: []outputInfo{ 17810 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17811 }, 17812 }, 17813 }, 17814 { 17815 name: "CSEL0", 17816 auxType: auxCCop, 17817 argLen: 2, 17818 asm: arm64.ACSEL, 17819 reg: regInfo{ 17820 inputs: []inputInfo{ 17821 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17822 }, 17823 outputs: []outputInfo{ 17824 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17825 }, 17826 }, 17827 }, 17828 { 17829 name: "CALLstatic", 17830 auxType: auxSymOff, 17831 argLen: 1, 17832 clobberFlags: true, 17833 call: true, 17834 symEffect: SymNone, 17835 reg: regInfo{ 17836 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17837 }, 17838 }, 17839 { 17840 name: "CALLclosure", 17841 auxType: auxInt64, 17842 argLen: 3, 17843 clobberFlags: true, 17844 call: true, 17845 reg: regInfo{ 17846 inputs: []inputInfo{ 17847 {1, 67108864}, // R26 17848 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 17849 }, 17850 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17851 }, 17852 }, 17853 { 17854 name: "CALLinter", 17855 auxType: auxInt64, 17856 argLen: 2, 17857 clobberFlags: true, 17858 call: true, 17859 reg: regInfo{ 17860 inputs: []inputInfo{ 17861 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17862 }, 17863 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17864 }, 17865 }, 17866 { 17867 name: "LoweredNilCheck", 17868 argLen: 2, 17869 nilCheck: true, 17870 faultOnNilArg0: true, 17871 reg: regInfo{ 17872 inputs: []inputInfo{ 17873 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17874 }, 17875 }, 17876 }, 17877 { 17878 name: "Equal", 17879 argLen: 1, 17880 reg: regInfo{ 17881 outputs: []outputInfo{ 17882 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17883 }, 17884 }, 17885 }, 17886 { 17887 name: "NotEqual", 17888 argLen: 1, 17889 reg: regInfo{ 17890 outputs: []outputInfo{ 17891 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17892 }, 17893 }, 17894 }, 17895 { 17896 name: "LessThan", 17897 argLen: 1, 17898 reg: regInfo{ 17899 outputs: []outputInfo{ 17900 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17901 }, 17902 }, 17903 }, 17904 { 17905 name: "LessEqual", 17906 argLen: 1, 17907 reg: regInfo{ 17908 outputs: []outputInfo{ 17909 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17910 }, 17911 }, 17912 }, 17913 { 17914 name: "GreaterThan", 17915 argLen: 1, 17916 reg: regInfo{ 17917 outputs: []outputInfo{ 17918 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17919 }, 17920 }, 17921 }, 17922 { 17923 name: "GreaterEqual", 17924 argLen: 1, 17925 reg: regInfo{ 17926 outputs: []outputInfo{ 17927 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17928 }, 17929 }, 17930 }, 17931 { 17932 name: "LessThanU", 17933 argLen: 1, 17934 reg: regInfo{ 17935 outputs: []outputInfo{ 17936 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17937 }, 17938 }, 17939 }, 17940 { 17941 name: "LessEqualU", 17942 argLen: 1, 17943 reg: regInfo{ 17944 outputs: []outputInfo{ 17945 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17946 }, 17947 }, 17948 }, 17949 { 17950 name: "GreaterThanU", 17951 argLen: 1, 17952 reg: regInfo{ 17953 outputs: []outputInfo{ 17954 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17955 }, 17956 }, 17957 }, 17958 { 17959 name: "GreaterEqualU", 17960 argLen: 1, 17961 reg: regInfo{ 17962 outputs: []outputInfo{ 17963 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17964 }, 17965 }, 17966 }, 17967 { 17968 name: "DUFFZERO", 17969 auxType: auxInt64, 17970 argLen: 2, 17971 faultOnNilArg0: true, 17972 reg: regInfo{ 17973 inputs: []inputInfo{ 17974 {0, 65536}, // R16 17975 }, 17976 clobbers: 536936448, // R16 R30 17977 }, 17978 }, 17979 { 17980 name: "LoweredZero", 17981 argLen: 3, 17982 clobberFlags: true, 17983 faultOnNilArg0: true, 17984 reg: regInfo{ 17985 inputs: []inputInfo{ 17986 {0, 65536}, // R16 17987 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17988 }, 17989 clobbers: 65536, // R16 17990 }, 17991 }, 17992 { 17993 name: "DUFFCOPY", 17994 auxType: auxInt64, 17995 argLen: 3, 17996 faultOnNilArg0: true, 17997 faultOnNilArg1: true, 17998 reg: regInfo{ 17999 inputs: []inputInfo{ 18000 {0, 131072}, // R17 18001 {1, 65536}, // R16 18002 }, 18003 clobbers: 604176384, // R16 R17 R26 R30 18004 }, 18005 }, 18006 { 18007 name: "LoweredMove", 18008 argLen: 4, 18009 clobberFlags: true, 18010 faultOnNilArg0: true, 18011 faultOnNilArg1: true, 18012 reg: regInfo{ 18013 inputs: []inputInfo{ 18014 {0, 131072}, // R17 18015 {1, 65536}, // R16 18016 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18017 }, 18018 clobbers: 196608, // R16 R17 18019 }, 18020 }, 18021 { 18022 name: "LoweredGetClosurePtr", 18023 argLen: 0, 18024 zeroWidth: true, 18025 reg: regInfo{ 18026 outputs: []outputInfo{ 18027 {0, 67108864}, // R26 18028 }, 18029 }, 18030 }, 18031 { 18032 name: "LoweredGetCallerSP", 18033 argLen: 0, 18034 rematerializeable: true, 18035 reg: regInfo{ 18036 outputs: []outputInfo{ 18037 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18038 }, 18039 }, 18040 }, 18041 { 18042 name: "LoweredGetCallerPC", 18043 argLen: 0, 18044 rematerializeable: true, 18045 reg: regInfo{ 18046 outputs: []outputInfo{ 18047 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18048 }, 18049 }, 18050 }, 18051 { 18052 name: "FlagEQ", 18053 argLen: 0, 18054 reg: regInfo{}, 18055 }, 18056 { 18057 name: "FlagLT_ULT", 18058 argLen: 0, 18059 reg: regInfo{}, 18060 }, 18061 { 18062 name: "FlagLT_UGT", 18063 argLen: 0, 18064 reg: regInfo{}, 18065 }, 18066 { 18067 name: "FlagGT_UGT", 18068 argLen: 0, 18069 reg: regInfo{}, 18070 }, 18071 { 18072 name: "FlagGT_ULT", 18073 argLen: 0, 18074 reg: regInfo{}, 18075 }, 18076 { 18077 name: "InvertFlags", 18078 argLen: 1, 18079 reg: regInfo{}, 18080 }, 18081 { 18082 name: "LDAR", 18083 argLen: 2, 18084 faultOnNilArg0: true, 18085 asm: arm64.ALDAR, 18086 reg: regInfo{ 18087 inputs: []inputInfo{ 18088 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18089 }, 18090 outputs: []outputInfo{ 18091 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18092 }, 18093 }, 18094 }, 18095 { 18096 name: "LDARW", 18097 argLen: 2, 18098 faultOnNilArg0: true, 18099 asm: arm64.ALDARW, 18100 reg: regInfo{ 18101 inputs: []inputInfo{ 18102 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18103 }, 18104 outputs: []outputInfo{ 18105 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18106 }, 18107 }, 18108 }, 18109 { 18110 name: "STLR", 18111 argLen: 3, 18112 faultOnNilArg0: true, 18113 hasSideEffects: true, 18114 asm: arm64.ASTLR, 18115 reg: regInfo{ 18116 inputs: []inputInfo{ 18117 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18118 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18119 }, 18120 }, 18121 }, 18122 { 18123 name: "STLRW", 18124 argLen: 3, 18125 faultOnNilArg0: true, 18126 hasSideEffects: true, 18127 asm: arm64.ASTLRW, 18128 reg: regInfo{ 18129 inputs: []inputInfo{ 18130 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18131 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18132 }, 18133 }, 18134 }, 18135 { 18136 name: "LoweredAtomicExchange64", 18137 argLen: 3, 18138 resultNotInArgs: true, 18139 faultOnNilArg0: true, 18140 hasSideEffects: true, 18141 reg: regInfo{ 18142 inputs: []inputInfo{ 18143 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18144 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18145 }, 18146 outputs: []outputInfo{ 18147 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18148 }, 18149 }, 18150 }, 18151 { 18152 name: "LoweredAtomicExchange32", 18153 argLen: 3, 18154 resultNotInArgs: true, 18155 faultOnNilArg0: true, 18156 hasSideEffects: true, 18157 reg: regInfo{ 18158 inputs: []inputInfo{ 18159 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18160 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18161 }, 18162 outputs: []outputInfo{ 18163 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18164 }, 18165 }, 18166 }, 18167 { 18168 name: "LoweredAtomicAdd64", 18169 argLen: 3, 18170 resultNotInArgs: true, 18171 faultOnNilArg0: true, 18172 hasSideEffects: true, 18173 reg: regInfo{ 18174 inputs: []inputInfo{ 18175 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18176 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18177 }, 18178 outputs: []outputInfo{ 18179 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18180 }, 18181 }, 18182 }, 18183 { 18184 name: "LoweredAtomicAdd32", 18185 argLen: 3, 18186 resultNotInArgs: true, 18187 faultOnNilArg0: true, 18188 hasSideEffects: true, 18189 reg: regInfo{ 18190 inputs: []inputInfo{ 18191 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18192 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18193 }, 18194 outputs: []outputInfo{ 18195 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18196 }, 18197 }, 18198 }, 18199 { 18200 name: "LoweredAtomicAdd64Variant", 18201 argLen: 3, 18202 resultNotInArgs: true, 18203 faultOnNilArg0: true, 18204 hasSideEffects: true, 18205 reg: regInfo{ 18206 inputs: []inputInfo{ 18207 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18208 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18209 }, 18210 outputs: []outputInfo{ 18211 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18212 }, 18213 }, 18214 }, 18215 { 18216 name: "LoweredAtomicAdd32Variant", 18217 argLen: 3, 18218 resultNotInArgs: true, 18219 faultOnNilArg0: true, 18220 hasSideEffects: true, 18221 reg: regInfo{ 18222 inputs: []inputInfo{ 18223 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18224 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18225 }, 18226 outputs: []outputInfo{ 18227 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18228 }, 18229 }, 18230 }, 18231 { 18232 name: "LoweredAtomicCas64", 18233 argLen: 4, 18234 resultNotInArgs: true, 18235 clobberFlags: true, 18236 faultOnNilArg0: true, 18237 hasSideEffects: true, 18238 reg: regInfo{ 18239 inputs: []inputInfo{ 18240 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18241 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18242 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18243 }, 18244 outputs: []outputInfo{ 18245 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18246 }, 18247 }, 18248 }, 18249 { 18250 name: "LoweredAtomicCas32", 18251 argLen: 4, 18252 resultNotInArgs: true, 18253 clobberFlags: true, 18254 faultOnNilArg0: true, 18255 hasSideEffects: true, 18256 reg: regInfo{ 18257 inputs: []inputInfo{ 18258 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18259 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18260 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18261 }, 18262 outputs: []outputInfo{ 18263 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18264 }, 18265 }, 18266 }, 18267 { 18268 name: "LoweredAtomicAnd8", 18269 argLen: 3, 18270 resultNotInArgs: true, 18271 faultOnNilArg0: true, 18272 hasSideEffects: true, 18273 asm: arm64.AAND, 18274 reg: regInfo{ 18275 inputs: []inputInfo{ 18276 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18277 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18278 }, 18279 outputs: []outputInfo{ 18280 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18281 }, 18282 }, 18283 }, 18284 { 18285 name: "LoweredAtomicOr8", 18286 argLen: 3, 18287 resultNotInArgs: true, 18288 faultOnNilArg0: true, 18289 hasSideEffects: true, 18290 asm: arm64.AORR, 18291 reg: regInfo{ 18292 inputs: []inputInfo{ 18293 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18294 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18295 }, 18296 outputs: []outputInfo{ 18297 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18298 }, 18299 }, 18300 }, 18301 { 18302 name: "LoweredWB", 18303 auxType: auxSym, 18304 argLen: 3, 18305 clobberFlags: true, 18306 symEffect: SymNone, 18307 reg: regInfo{ 18308 inputs: []inputInfo{ 18309 {0, 4}, // R2 18310 {1, 8}, // R3 18311 }, 18312 clobbers: 9223372035244163072, // R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18313 }, 18314 }, 18315 18316 { 18317 name: "ADD", 18318 argLen: 2, 18319 commutative: true, 18320 asm: mips.AADDU, 18321 reg: regInfo{ 18322 inputs: []inputInfo{ 18323 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18324 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18325 }, 18326 outputs: []outputInfo{ 18327 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18328 }, 18329 }, 18330 }, 18331 { 18332 name: "ADDconst", 18333 auxType: auxInt32, 18334 argLen: 1, 18335 asm: mips.AADDU, 18336 reg: regInfo{ 18337 inputs: []inputInfo{ 18338 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 18339 }, 18340 outputs: []outputInfo{ 18341 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18342 }, 18343 }, 18344 }, 18345 { 18346 name: "SUB", 18347 argLen: 2, 18348 asm: mips.ASUBU, 18349 reg: regInfo{ 18350 inputs: []inputInfo{ 18351 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18352 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18353 }, 18354 outputs: []outputInfo{ 18355 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18356 }, 18357 }, 18358 }, 18359 { 18360 name: "SUBconst", 18361 auxType: auxInt32, 18362 argLen: 1, 18363 asm: mips.ASUBU, 18364 reg: regInfo{ 18365 inputs: []inputInfo{ 18366 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18367 }, 18368 outputs: []outputInfo{ 18369 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18370 }, 18371 }, 18372 }, 18373 { 18374 name: "MUL", 18375 argLen: 2, 18376 commutative: true, 18377 asm: mips.AMUL, 18378 reg: regInfo{ 18379 inputs: []inputInfo{ 18380 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18381 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18382 }, 18383 clobbers: 105553116266496, // HI LO 18384 outputs: []outputInfo{ 18385 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18386 }, 18387 }, 18388 }, 18389 { 18390 name: "MULT", 18391 argLen: 2, 18392 commutative: true, 18393 asm: mips.AMUL, 18394 reg: regInfo{ 18395 inputs: []inputInfo{ 18396 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18397 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18398 }, 18399 outputs: []outputInfo{ 18400 {0, 35184372088832}, // HI 18401 {1, 70368744177664}, // LO 18402 }, 18403 }, 18404 }, 18405 { 18406 name: "MULTU", 18407 argLen: 2, 18408 commutative: true, 18409 asm: mips.AMULU, 18410 reg: regInfo{ 18411 inputs: []inputInfo{ 18412 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18413 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18414 }, 18415 outputs: []outputInfo{ 18416 {0, 35184372088832}, // HI 18417 {1, 70368744177664}, // LO 18418 }, 18419 }, 18420 }, 18421 { 18422 name: "DIV", 18423 argLen: 2, 18424 asm: mips.ADIV, 18425 reg: regInfo{ 18426 inputs: []inputInfo{ 18427 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18428 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18429 }, 18430 outputs: []outputInfo{ 18431 {0, 35184372088832}, // HI 18432 {1, 70368744177664}, // LO 18433 }, 18434 }, 18435 }, 18436 { 18437 name: "DIVU", 18438 argLen: 2, 18439 asm: mips.ADIVU, 18440 reg: regInfo{ 18441 inputs: []inputInfo{ 18442 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18443 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18444 }, 18445 outputs: []outputInfo{ 18446 {0, 35184372088832}, // HI 18447 {1, 70368744177664}, // LO 18448 }, 18449 }, 18450 }, 18451 { 18452 name: "ADDF", 18453 argLen: 2, 18454 commutative: true, 18455 asm: mips.AADDF, 18456 reg: regInfo{ 18457 inputs: []inputInfo{ 18458 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18459 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18460 }, 18461 outputs: []outputInfo{ 18462 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18463 }, 18464 }, 18465 }, 18466 { 18467 name: "ADDD", 18468 argLen: 2, 18469 commutative: true, 18470 asm: mips.AADDD, 18471 reg: regInfo{ 18472 inputs: []inputInfo{ 18473 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18474 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18475 }, 18476 outputs: []outputInfo{ 18477 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18478 }, 18479 }, 18480 }, 18481 { 18482 name: "SUBF", 18483 argLen: 2, 18484 asm: mips.ASUBF, 18485 reg: regInfo{ 18486 inputs: []inputInfo{ 18487 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18488 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18489 }, 18490 outputs: []outputInfo{ 18491 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18492 }, 18493 }, 18494 }, 18495 { 18496 name: "SUBD", 18497 argLen: 2, 18498 asm: mips.ASUBD, 18499 reg: regInfo{ 18500 inputs: []inputInfo{ 18501 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18502 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18503 }, 18504 outputs: []outputInfo{ 18505 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18506 }, 18507 }, 18508 }, 18509 { 18510 name: "MULF", 18511 argLen: 2, 18512 commutative: true, 18513 asm: mips.AMULF, 18514 reg: regInfo{ 18515 inputs: []inputInfo{ 18516 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18517 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18518 }, 18519 outputs: []outputInfo{ 18520 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18521 }, 18522 }, 18523 }, 18524 { 18525 name: "MULD", 18526 argLen: 2, 18527 commutative: true, 18528 asm: mips.AMULD, 18529 reg: regInfo{ 18530 inputs: []inputInfo{ 18531 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18532 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18533 }, 18534 outputs: []outputInfo{ 18535 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18536 }, 18537 }, 18538 }, 18539 { 18540 name: "DIVF", 18541 argLen: 2, 18542 asm: mips.ADIVF, 18543 reg: regInfo{ 18544 inputs: []inputInfo{ 18545 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18546 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18547 }, 18548 outputs: []outputInfo{ 18549 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18550 }, 18551 }, 18552 }, 18553 { 18554 name: "DIVD", 18555 argLen: 2, 18556 asm: mips.ADIVD, 18557 reg: regInfo{ 18558 inputs: []inputInfo{ 18559 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18560 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18561 }, 18562 outputs: []outputInfo{ 18563 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18564 }, 18565 }, 18566 }, 18567 { 18568 name: "AND", 18569 argLen: 2, 18570 commutative: true, 18571 asm: mips.AAND, 18572 reg: regInfo{ 18573 inputs: []inputInfo{ 18574 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18575 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18576 }, 18577 outputs: []outputInfo{ 18578 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18579 }, 18580 }, 18581 }, 18582 { 18583 name: "ANDconst", 18584 auxType: auxInt32, 18585 argLen: 1, 18586 asm: mips.AAND, 18587 reg: regInfo{ 18588 inputs: []inputInfo{ 18589 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18590 }, 18591 outputs: []outputInfo{ 18592 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18593 }, 18594 }, 18595 }, 18596 { 18597 name: "OR", 18598 argLen: 2, 18599 commutative: true, 18600 asm: mips.AOR, 18601 reg: regInfo{ 18602 inputs: []inputInfo{ 18603 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18604 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18605 }, 18606 outputs: []outputInfo{ 18607 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18608 }, 18609 }, 18610 }, 18611 { 18612 name: "ORconst", 18613 auxType: auxInt32, 18614 argLen: 1, 18615 asm: mips.AOR, 18616 reg: regInfo{ 18617 inputs: []inputInfo{ 18618 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18619 }, 18620 outputs: []outputInfo{ 18621 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18622 }, 18623 }, 18624 }, 18625 { 18626 name: "XOR", 18627 argLen: 2, 18628 commutative: true, 18629 asm: mips.AXOR, 18630 reg: regInfo{ 18631 inputs: []inputInfo{ 18632 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18633 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18634 }, 18635 outputs: []outputInfo{ 18636 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18637 }, 18638 }, 18639 }, 18640 { 18641 name: "XORconst", 18642 auxType: auxInt32, 18643 argLen: 1, 18644 asm: mips.AXOR, 18645 reg: regInfo{ 18646 inputs: []inputInfo{ 18647 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18648 }, 18649 outputs: []outputInfo{ 18650 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18651 }, 18652 }, 18653 }, 18654 { 18655 name: "NOR", 18656 argLen: 2, 18657 commutative: true, 18658 asm: mips.ANOR, 18659 reg: regInfo{ 18660 inputs: []inputInfo{ 18661 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18662 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18663 }, 18664 outputs: []outputInfo{ 18665 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18666 }, 18667 }, 18668 }, 18669 { 18670 name: "NORconst", 18671 auxType: auxInt32, 18672 argLen: 1, 18673 asm: mips.ANOR, 18674 reg: regInfo{ 18675 inputs: []inputInfo{ 18676 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18677 }, 18678 outputs: []outputInfo{ 18679 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18680 }, 18681 }, 18682 }, 18683 { 18684 name: "NEG", 18685 argLen: 1, 18686 reg: regInfo{ 18687 inputs: []inputInfo{ 18688 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18689 }, 18690 outputs: []outputInfo{ 18691 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18692 }, 18693 }, 18694 }, 18695 { 18696 name: "NEGF", 18697 argLen: 1, 18698 asm: mips.ANEGF, 18699 reg: regInfo{ 18700 inputs: []inputInfo{ 18701 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18702 }, 18703 outputs: []outputInfo{ 18704 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18705 }, 18706 }, 18707 }, 18708 { 18709 name: "NEGD", 18710 argLen: 1, 18711 asm: mips.ANEGD, 18712 reg: regInfo{ 18713 inputs: []inputInfo{ 18714 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18715 }, 18716 outputs: []outputInfo{ 18717 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18718 }, 18719 }, 18720 }, 18721 { 18722 name: "SQRTD", 18723 argLen: 1, 18724 asm: mips.ASQRTD, 18725 reg: regInfo{ 18726 inputs: []inputInfo{ 18727 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18728 }, 18729 outputs: []outputInfo{ 18730 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18731 }, 18732 }, 18733 }, 18734 { 18735 name: "SLL", 18736 argLen: 2, 18737 asm: mips.ASLL, 18738 reg: regInfo{ 18739 inputs: []inputInfo{ 18740 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18741 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18742 }, 18743 outputs: []outputInfo{ 18744 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18745 }, 18746 }, 18747 }, 18748 { 18749 name: "SLLconst", 18750 auxType: auxInt32, 18751 argLen: 1, 18752 asm: mips.ASLL, 18753 reg: regInfo{ 18754 inputs: []inputInfo{ 18755 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18756 }, 18757 outputs: []outputInfo{ 18758 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18759 }, 18760 }, 18761 }, 18762 { 18763 name: "SRL", 18764 argLen: 2, 18765 asm: mips.ASRL, 18766 reg: regInfo{ 18767 inputs: []inputInfo{ 18768 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18769 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18770 }, 18771 outputs: []outputInfo{ 18772 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18773 }, 18774 }, 18775 }, 18776 { 18777 name: "SRLconst", 18778 auxType: auxInt32, 18779 argLen: 1, 18780 asm: mips.ASRL, 18781 reg: regInfo{ 18782 inputs: []inputInfo{ 18783 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18784 }, 18785 outputs: []outputInfo{ 18786 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18787 }, 18788 }, 18789 }, 18790 { 18791 name: "SRA", 18792 argLen: 2, 18793 asm: mips.ASRA, 18794 reg: regInfo{ 18795 inputs: []inputInfo{ 18796 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18797 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18798 }, 18799 outputs: []outputInfo{ 18800 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18801 }, 18802 }, 18803 }, 18804 { 18805 name: "SRAconst", 18806 auxType: auxInt32, 18807 argLen: 1, 18808 asm: mips.ASRA, 18809 reg: regInfo{ 18810 inputs: []inputInfo{ 18811 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18812 }, 18813 outputs: []outputInfo{ 18814 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18815 }, 18816 }, 18817 }, 18818 { 18819 name: "CLZ", 18820 argLen: 1, 18821 asm: mips.ACLZ, 18822 reg: regInfo{ 18823 inputs: []inputInfo{ 18824 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18825 }, 18826 outputs: []outputInfo{ 18827 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18828 }, 18829 }, 18830 }, 18831 { 18832 name: "SGT", 18833 argLen: 2, 18834 asm: mips.ASGT, 18835 reg: regInfo{ 18836 inputs: []inputInfo{ 18837 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18838 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18839 }, 18840 outputs: []outputInfo{ 18841 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18842 }, 18843 }, 18844 }, 18845 { 18846 name: "SGTconst", 18847 auxType: auxInt32, 18848 argLen: 1, 18849 asm: mips.ASGT, 18850 reg: regInfo{ 18851 inputs: []inputInfo{ 18852 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18853 }, 18854 outputs: []outputInfo{ 18855 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18856 }, 18857 }, 18858 }, 18859 { 18860 name: "SGTzero", 18861 argLen: 1, 18862 asm: mips.ASGT, 18863 reg: regInfo{ 18864 inputs: []inputInfo{ 18865 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18866 }, 18867 outputs: []outputInfo{ 18868 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18869 }, 18870 }, 18871 }, 18872 { 18873 name: "SGTU", 18874 argLen: 2, 18875 asm: mips.ASGTU, 18876 reg: regInfo{ 18877 inputs: []inputInfo{ 18878 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18879 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18880 }, 18881 outputs: []outputInfo{ 18882 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18883 }, 18884 }, 18885 }, 18886 { 18887 name: "SGTUconst", 18888 auxType: auxInt32, 18889 argLen: 1, 18890 asm: mips.ASGTU, 18891 reg: regInfo{ 18892 inputs: []inputInfo{ 18893 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18894 }, 18895 outputs: []outputInfo{ 18896 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18897 }, 18898 }, 18899 }, 18900 { 18901 name: "SGTUzero", 18902 argLen: 1, 18903 asm: mips.ASGTU, 18904 reg: regInfo{ 18905 inputs: []inputInfo{ 18906 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18907 }, 18908 outputs: []outputInfo{ 18909 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18910 }, 18911 }, 18912 }, 18913 { 18914 name: "CMPEQF", 18915 argLen: 2, 18916 asm: mips.ACMPEQF, 18917 reg: regInfo{ 18918 inputs: []inputInfo{ 18919 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18920 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18921 }, 18922 }, 18923 }, 18924 { 18925 name: "CMPEQD", 18926 argLen: 2, 18927 asm: mips.ACMPEQD, 18928 reg: regInfo{ 18929 inputs: []inputInfo{ 18930 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18931 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18932 }, 18933 }, 18934 }, 18935 { 18936 name: "CMPGEF", 18937 argLen: 2, 18938 asm: mips.ACMPGEF, 18939 reg: regInfo{ 18940 inputs: []inputInfo{ 18941 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18942 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18943 }, 18944 }, 18945 }, 18946 { 18947 name: "CMPGED", 18948 argLen: 2, 18949 asm: mips.ACMPGED, 18950 reg: regInfo{ 18951 inputs: []inputInfo{ 18952 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18953 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18954 }, 18955 }, 18956 }, 18957 { 18958 name: "CMPGTF", 18959 argLen: 2, 18960 asm: mips.ACMPGTF, 18961 reg: regInfo{ 18962 inputs: []inputInfo{ 18963 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18964 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18965 }, 18966 }, 18967 }, 18968 { 18969 name: "CMPGTD", 18970 argLen: 2, 18971 asm: mips.ACMPGTD, 18972 reg: regInfo{ 18973 inputs: []inputInfo{ 18974 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18975 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18976 }, 18977 }, 18978 }, 18979 { 18980 name: "MOVWconst", 18981 auxType: auxInt32, 18982 argLen: 0, 18983 rematerializeable: true, 18984 asm: mips.AMOVW, 18985 reg: regInfo{ 18986 outputs: []outputInfo{ 18987 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18988 }, 18989 }, 18990 }, 18991 { 18992 name: "MOVFconst", 18993 auxType: auxFloat32, 18994 argLen: 0, 18995 rematerializeable: true, 18996 asm: mips.AMOVF, 18997 reg: regInfo{ 18998 outputs: []outputInfo{ 18999 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19000 }, 19001 }, 19002 }, 19003 { 19004 name: "MOVDconst", 19005 auxType: auxFloat64, 19006 argLen: 0, 19007 rematerializeable: true, 19008 asm: mips.AMOVD, 19009 reg: regInfo{ 19010 outputs: []outputInfo{ 19011 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19012 }, 19013 }, 19014 }, 19015 { 19016 name: "MOVWaddr", 19017 auxType: auxSymOff, 19018 argLen: 1, 19019 rematerializeable: true, 19020 symEffect: SymAddr, 19021 asm: mips.AMOVW, 19022 reg: regInfo{ 19023 inputs: []inputInfo{ 19024 {0, 140737555464192}, // SP SB 19025 }, 19026 outputs: []outputInfo{ 19027 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19028 }, 19029 }, 19030 }, 19031 { 19032 name: "MOVBload", 19033 auxType: auxSymOff, 19034 argLen: 2, 19035 faultOnNilArg0: true, 19036 symEffect: SymRead, 19037 asm: mips.AMOVB, 19038 reg: regInfo{ 19039 inputs: []inputInfo{ 19040 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19041 }, 19042 outputs: []outputInfo{ 19043 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19044 }, 19045 }, 19046 }, 19047 { 19048 name: "MOVBUload", 19049 auxType: auxSymOff, 19050 argLen: 2, 19051 faultOnNilArg0: true, 19052 symEffect: SymRead, 19053 asm: mips.AMOVBU, 19054 reg: regInfo{ 19055 inputs: []inputInfo{ 19056 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19057 }, 19058 outputs: []outputInfo{ 19059 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19060 }, 19061 }, 19062 }, 19063 { 19064 name: "MOVHload", 19065 auxType: auxSymOff, 19066 argLen: 2, 19067 faultOnNilArg0: true, 19068 symEffect: SymRead, 19069 asm: mips.AMOVH, 19070 reg: regInfo{ 19071 inputs: []inputInfo{ 19072 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19073 }, 19074 outputs: []outputInfo{ 19075 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19076 }, 19077 }, 19078 }, 19079 { 19080 name: "MOVHUload", 19081 auxType: auxSymOff, 19082 argLen: 2, 19083 faultOnNilArg0: true, 19084 symEffect: SymRead, 19085 asm: mips.AMOVHU, 19086 reg: regInfo{ 19087 inputs: []inputInfo{ 19088 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19089 }, 19090 outputs: []outputInfo{ 19091 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19092 }, 19093 }, 19094 }, 19095 { 19096 name: "MOVWload", 19097 auxType: auxSymOff, 19098 argLen: 2, 19099 faultOnNilArg0: true, 19100 symEffect: SymRead, 19101 asm: mips.AMOVW, 19102 reg: regInfo{ 19103 inputs: []inputInfo{ 19104 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19105 }, 19106 outputs: []outputInfo{ 19107 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19108 }, 19109 }, 19110 }, 19111 { 19112 name: "MOVFload", 19113 auxType: auxSymOff, 19114 argLen: 2, 19115 faultOnNilArg0: true, 19116 symEffect: SymRead, 19117 asm: mips.AMOVF, 19118 reg: regInfo{ 19119 inputs: []inputInfo{ 19120 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19121 }, 19122 outputs: []outputInfo{ 19123 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19124 }, 19125 }, 19126 }, 19127 { 19128 name: "MOVDload", 19129 auxType: auxSymOff, 19130 argLen: 2, 19131 faultOnNilArg0: true, 19132 symEffect: SymRead, 19133 asm: mips.AMOVD, 19134 reg: regInfo{ 19135 inputs: []inputInfo{ 19136 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19137 }, 19138 outputs: []outputInfo{ 19139 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19140 }, 19141 }, 19142 }, 19143 { 19144 name: "MOVBstore", 19145 auxType: auxSymOff, 19146 argLen: 3, 19147 faultOnNilArg0: true, 19148 symEffect: SymWrite, 19149 asm: mips.AMOVB, 19150 reg: regInfo{ 19151 inputs: []inputInfo{ 19152 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19153 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19154 }, 19155 }, 19156 }, 19157 { 19158 name: "MOVHstore", 19159 auxType: auxSymOff, 19160 argLen: 3, 19161 faultOnNilArg0: true, 19162 symEffect: SymWrite, 19163 asm: mips.AMOVH, 19164 reg: regInfo{ 19165 inputs: []inputInfo{ 19166 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19167 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19168 }, 19169 }, 19170 }, 19171 { 19172 name: "MOVWstore", 19173 auxType: auxSymOff, 19174 argLen: 3, 19175 faultOnNilArg0: true, 19176 symEffect: SymWrite, 19177 asm: mips.AMOVW, 19178 reg: regInfo{ 19179 inputs: []inputInfo{ 19180 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19181 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19182 }, 19183 }, 19184 }, 19185 { 19186 name: "MOVFstore", 19187 auxType: auxSymOff, 19188 argLen: 3, 19189 faultOnNilArg0: true, 19190 symEffect: SymWrite, 19191 asm: mips.AMOVF, 19192 reg: regInfo{ 19193 inputs: []inputInfo{ 19194 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19195 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19196 }, 19197 }, 19198 }, 19199 { 19200 name: "MOVDstore", 19201 auxType: auxSymOff, 19202 argLen: 3, 19203 faultOnNilArg0: true, 19204 symEffect: SymWrite, 19205 asm: mips.AMOVD, 19206 reg: regInfo{ 19207 inputs: []inputInfo{ 19208 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19209 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19210 }, 19211 }, 19212 }, 19213 { 19214 name: "MOVBstorezero", 19215 auxType: auxSymOff, 19216 argLen: 2, 19217 faultOnNilArg0: true, 19218 symEffect: SymWrite, 19219 asm: mips.AMOVB, 19220 reg: regInfo{ 19221 inputs: []inputInfo{ 19222 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19223 }, 19224 }, 19225 }, 19226 { 19227 name: "MOVHstorezero", 19228 auxType: auxSymOff, 19229 argLen: 2, 19230 faultOnNilArg0: true, 19231 symEffect: SymWrite, 19232 asm: mips.AMOVH, 19233 reg: regInfo{ 19234 inputs: []inputInfo{ 19235 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19236 }, 19237 }, 19238 }, 19239 { 19240 name: "MOVWstorezero", 19241 auxType: auxSymOff, 19242 argLen: 2, 19243 faultOnNilArg0: true, 19244 symEffect: SymWrite, 19245 asm: mips.AMOVW, 19246 reg: regInfo{ 19247 inputs: []inputInfo{ 19248 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19249 }, 19250 }, 19251 }, 19252 { 19253 name: "MOVBreg", 19254 argLen: 1, 19255 asm: mips.AMOVB, 19256 reg: regInfo{ 19257 inputs: []inputInfo{ 19258 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19259 }, 19260 outputs: []outputInfo{ 19261 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19262 }, 19263 }, 19264 }, 19265 { 19266 name: "MOVBUreg", 19267 argLen: 1, 19268 asm: mips.AMOVBU, 19269 reg: regInfo{ 19270 inputs: []inputInfo{ 19271 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19272 }, 19273 outputs: []outputInfo{ 19274 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19275 }, 19276 }, 19277 }, 19278 { 19279 name: "MOVHreg", 19280 argLen: 1, 19281 asm: mips.AMOVH, 19282 reg: regInfo{ 19283 inputs: []inputInfo{ 19284 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19285 }, 19286 outputs: []outputInfo{ 19287 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19288 }, 19289 }, 19290 }, 19291 { 19292 name: "MOVHUreg", 19293 argLen: 1, 19294 asm: mips.AMOVHU, 19295 reg: regInfo{ 19296 inputs: []inputInfo{ 19297 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19298 }, 19299 outputs: []outputInfo{ 19300 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19301 }, 19302 }, 19303 }, 19304 { 19305 name: "MOVWreg", 19306 argLen: 1, 19307 asm: mips.AMOVW, 19308 reg: regInfo{ 19309 inputs: []inputInfo{ 19310 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19311 }, 19312 outputs: []outputInfo{ 19313 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19314 }, 19315 }, 19316 }, 19317 { 19318 name: "MOVWnop", 19319 argLen: 1, 19320 resultInArg0: true, 19321 reg: regInfo{ 19322 inputs: []inputInfo{ 19323 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19324 }, 19325 outputs: []outputInfo{ 19326 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19327 }, 19328 }, 19329 }, 19330 { 19331 name: "CMOVZ", 19332 argLen: 3, 19333 resultInArg0: true, 19334 asm: mips.ACMOVZ, 19335 reg: regInfo{ 19336 inputs: []inputInfo{ 19337 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19338 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19339 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19340 }, 19341 outputs: []outputInfo{ 19342 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19343 }, 19344 }, 19345 }, 19346 { 19347 name: "CMOVZzero", 19348 argLen: 2, 19349 resultInArg0: true, 19350 asm: mips.ACMOVZ, 19351 reg: regInfo{ 19352 inputs: []inputInfo{ 19353 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19354 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19355 }, 19356 outputs: []outputInfo{ 19357 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19358 }, 19359 }, 19360 }, 19361 { 19362 name: "MOVWF", 19363 argLen: 1, 19364 asm: mips.AMOVWF, 19365 reg: regInfo{ 19366 inputs: []inputInfo{ 19367 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19368 }, 19369 outputs: []outputInfo{ 19370 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19371 }, 19372 }, 19373 }, 19374 { 19375 name: "MOVWD", 19376 argLen: 1, 19377 asm: mips.AMOVWD, 19378 reg: regInfo{ 19379 inputs: []inputInfo{ 19380 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19381 }, 19382 outputs: []outputInfo{ 19383 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19384 }, 19385 }, 19386 }, 19387 { 19388 name: "TRUNCFW", 19389 argLen: 1, 19390 asm: mips.ATRUNCFW, 19391 reg: regInfo{ 19392 inputs: []inputInfo{ 19393 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19394 }, 19395 outputs: []outputInfo{ 19396 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19397 }, 19398 }, 19399 }, 19400 { 19401 name: "TRUNCDW", 19402 argLen: 1, 19403 asm: mips.ATRUNCDW, 19404 reg: regInfo{ 19405 inputs: []inputInfo{ 19406 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19407 }, 19408 outputs: []outputInfo{ 19409 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19410 }, 19411 }, 19412 }, 19413 { 19414 name: "MOVFD", 19415 argLen: 1, 19416 asm: mips.AMOVFD, 19417 reg: regInfo{ 19418 inputs: []inputInfo{ 19419 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19420 }, 19421 outputs: []outputInfo{ 19422 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19423 }, 19424 }, 19425 }, 19426 { 19427 name: "MOVDF", 19428 argLen: 1, 19429 asm: mips.AMOVDF, 19430 reg: regInfo{ 19431 inputs: []inputInfo{ 19432 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19433 }, 19434 outputs: []outputInfo{ 19435 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19436 }, 19437 }, 19438 }, 19439 { 19440 name: "CALLstatic", 19441 auxType: auxSymOff, 19442 argLen: 1, 19443 clobberFlags: true, 19444 call: true, 19445 symEffect: SymNone, 19446 reg: regInfo{ 19447 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 19448 }, 19449 }, 19450 { 19451 name: "CALLclosure", 19452 auxType: auxInt64, 19453 argLen: 3, 19454 clobberFlags: true, 19455 call: true, 19456 reg: regInfo{ 19457 inputs: []inputInfo{ 19458 {1, 4194304}, // R22 19459 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 19460 }, 19461 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 19462 }, 19463 }, 19464 { 19465 name: "CALLinter", 19466 auxType: auxInt64, 19467 argLen: 2, 19468 clobberFlags: true, 19469 call: true, 19470 reg: regInfo{ 19471 inputs: []inputInfo{ 19472 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19473 }, 19474 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 19475 }, 19476 }, 19477 { 19478 name: "LoweredAtomicLoad", 19479 argLen: 2, 19480 faultOnNilArg0: true, 19481 reg: regInfo{ 19482 inputs: []inputInfo{ 19483 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19484 }, 19485 outputs: []outputInfo{ 19486 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19487 }, 19488 }, 19489 }, 19490 { 19491 name: "LoweredAtomicStore", 19492 argLen: 3, 19493 faultOnNilArg0: true, 19494 hasSideEffects: true, 19495 reg: regInfo{ 19496 inputs: []inputInfo{ 19497 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19498 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19499 }, 19500 }, 19501 }, 19502 { 19503 name: "LoweredAtomicStorezero", 19504 argLen: 2, 19505 faultOnNilArg0: true, 19506 hasSideEffects: true, 19507 reg: regInfo{ 19508 inputs: []inputInfo{ 19509 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19510 }, 19511 }, 19512 }, 19513 { 19514 name: "LoweredAtomicExchange", 19515 argLen: 3, 19516 resultNotInArgs: true, 19517 faultOnNilArg0: true, 19518 hasSideEffects: true, 19519 reg: regInfo{ 19520 inputs: []inputInfo{ 19521 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19522 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19523 }, 19524 outputs: []outputInfo{ 19525 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19526 }, 19527 }, 19528 }, 19529 { 19530 name: "LoweredAtomicAdd", 19531 argLen: 3, 19532 resultNotInArgs: true, 19533 faultOnNilArg0: true, 19534 hasSideEffects: true, 19535 reg: regInfo{ 19536 inputs: []inputInfo{ 19537 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19538 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19539 }, 19540 outputs: []outputInfo{ 19541 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19542 }, 19543 }, 19544 }, 19545 { 19546 name: "LoweredAtomicAddconst", 19547 auxType: auxInt32, 19548 argLen: 2, 19549 resultNotInArgs: true, 19550 faultOnNilArg0: true, 19551 hasSideEffects: true, 19552 reg: regInfo{ 19553 inputs: []inputInfo{ 19554 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19555 }, 19556 outputs: []outputInfo{ 19557 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19558 }, 19559 }, 19560 }, 19561 { 19562 name: "LoweredAtomicCas", 19563 argLen: 4, 19564 resultNotInArgs: true, 19565 faultOnNilArg0: true, 19566 hasSideEffects: true, 19567 reg: regInfo{ 19568 inputs: []inputInfo{ 19569 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19570 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19571 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19572 }, 19573 outputs: []outputInfo{ 19574 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19575 }, 19576 }, 19577 }, 19578 { 19579 name: "LoweredAtomicAnd", 19580 argLen: 3, 19581 faultOnNilArg0: true, 19582 hasSideEffects: true, 19583 asm: mips.AAND, 19584 reg: regInfo{ 19585 inputs: []inputInfo{ 19586 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19587 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19588 }, 19589 }, 19590 }, 19591 { 19592 name: "LoweredAtomicOr", 19593 argLen: 3, 19594 faultOnNilArg0: true, 19595 hasSideEffects: true, 19596 asm: mips.AOR, 19597 reg: regInfo{ 19598 inputs: []inputInfo{ 19599 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19600 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19601 }, 19602 }, 19603 }, 19604 { 19605 name: "LoweredZero", 19606 auxType: auxInt32, 19607 argLen: 3, 19608 faultOnNilArg0: true, 19609 reg: regInfo{ 19610 inputs: []inputInfo{ 19611 {0, 2}, // R1 19612 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19613 }, 19614 clobbers: 2, // R1 19615 }, 19616 }, 19617 { 19618 name: "LoweredMove", 19619 auxType: auxInt32, 19620 argLen: 4, 19621 faultOnNilArg0: true, 19622 faultOnNilArg1: true, 19623 reg: regInfo{ 19624 inputs: []inputInfo{ 19625 {0, 4}, // R2 19626 {1, 2}, // R1 19627 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19628 }, 19629 clobbers: 6, // R1 R2 19630 }, 19631 }, 19632 { 19633 name: "LoweredNilCheck", 19634 argLen: 2, 19635 nilCheck: true, 19636 faultOnNilArg0: true, 19637 reg: regInfo{ 19638 inputs: []inputInfo{ 19639 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19640 }, 19641 }, 19642 }, 19643 { 19644 name: "FPFlagTrue", 19645 argLen: 1, 19646 reg: regInfo{ 19647 outputs: []outputInfo{ 19648 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19649 }, 19650 }, 19651 }, 19652 { 19653 name: "FPFlagFalse", 19654 argLen: 1, 19655 reg: regInfo{ 19656 outputs: []outputInfo{ 19657 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19658 }, 19659 }, 19660 }, 19661 { 19662 name: "LoweredGetClosurePtr", 19663 argLen: 0, 19664 zeroWidth: true, 19665 reg: regInfo{ 19666 outputs: []outputInfo{ 19667 {0, 4194304}, // R22 19668 }, 19669 }, 19670 }, 19671 { 19672 name: "LoweredGetCallerSP", 19673 argLen: 0, 19674 rematerializeable: true, 19675 reg: regInfo{ 19676 outputs: []outputInfo{ 19677 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19678 }, 19679 }, 19680 }, 19681 { 19682 name: "LoweredGetCallerPC", 19683 argLen: 0, 19684 rematerializeable: true, 19685 reg: regInfo{ 19686 outputs: []outputInfo{ 19687 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19688 }, 19689 }, 19690 }, 19691 { 19692 name: "LoweredWB", 19693 auxType: auxSym, 19694 argLen: 3, 19695 clobberFlags: true, 19696 symEffect: SymNone, 19697 reg: regInfo{ 19698 inputs: []inputInfo{ 19699 {0, 1048576}, // R20 19700 {1, 2097152}, // R21 19701 }, 19702 clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 19703 }, 19704 }, 19705 19706 { 19707 name: "ADDV", 19708 argLen: 2, 19709 commutative: true, 19710 asm: mips.AADDVU, 19711 reg: regInfo{ 19712 inputs: []inputInfo{ 19713 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19714 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19715 }, 19716 outputs: []outputInfo{ 19717 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 19718 }, 19719 }, 19720 }, 19721 { 19722 name: "ADDVconst", 19723 auxType: auxInt64, 19724 argLen: 1, 19725 asm: mips.AADDVU, 19726 reg: regInfo{ 19727 inputs: []inputInfo{ 19728 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 19729 }, 19730 outputs: []outputInfo{ 19731 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 19732 }, 19733 }, 19734 }, 19735 { 19736 name: "SUBV", 19737 argLen: 2, 19738 asm: mips.ASUBVU, 19739 reg: regInfo{ 19740 inputs: []inputInfo{ 19741 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19742 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19743 }, 19744 outputs: []outputInfo{ 19745 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 19746 }, 19747 }, 19748 }, 19749 { 19750 name: "SUBVconst", 19751 auxType: auxInt64, 19752 argLen: 1, 19753 asm: mips.ASUBVU, 19754 reg: regInfo{ 19755 inputs: []inputInfo{ 19756 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19757 }, 19758 outputs: []outputInfo{ 19759 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 19760 }, 19761 }, 19762 }, 19763 { 19764 name: "MULV", 19765 argLen: 2, 19766 commutative: true, 19767 asm: mips.AMULV, 19768 reg: regInfo{ 19769 inputs: []inputInfo{ 19770 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19771 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19772 }, 19773 outputs: []outputInfo{ 19774 {0, 1152921504606846976}, // HI 19775 {1, 2305843009213693952}, // LO 19776 }, 19777 }, 19778 }, 19779 { 19780 name: "MULVU", 19781 argLen: 2, 19782 commutative: true, 19783 asm: mips.AMULVU, 19784 reg: regInfo{ 19785 inputs: []inputInfo{ 19786 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19787 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19788 }, 19789 outputs: []outputInfo{ 19790 {0, 1152921504606846976}, // HI 19791 {1, 2305843009213693952}, // LO 19792 }, 19793 }, 19794 }, 19795 { 19796 name: "DIVV", 19797 argLen: 2, 19798 asm: mips.ADIVV, 19799 reg: regInfo{ 19800 inputs: []inputInfo{ 19801 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19802 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19803 }, 19804 outputs: []outputInfo{ 19805 {0, 1152921504606846976}, // HI 19806 {1, 2305843009213693952}, // LO 19807 }, 19808 }, 19809 }, 19810 { 19811 name: "DIVVU", 19812 argLen: 2, 19813 asm: mips.ADIVVU, 19814 reg: regInfo{ 19815 inputs: []inputInfo{ 19816 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19817 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19818 }, 19819 outputs: []outputInfo{ 19820 {0, 1152921504606846976}, // HI 19821 {1, 2305843009213693952}, // LO 19822 }, 19823 }, 19824 }, 19825 { 19826 name: "ADDF", 19827 argLen: 2, 19828 commutative: true, 19829 asm: mips.AADDF, 19830 reg: regInfo{ 19831 inputs: []inputInfo{ 19832 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19833 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19834 }, 19835 outputs: []outputInfo{ 19836 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19837 }, 19838 }, 19839 }, 19840 { 19841 name: "ADDD", 19842 argLen: 2, 19843 commutative: true, 19844 asm: mips.AADDD, 19845 reg: regInfo{ 19846 inputs: []inputInfo{ 19847 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19848 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19849 }, 19850 outputs: []outputInfo{ 19851 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19852 }, 19853 }, 19854 }, 19855 { 19856 name: "SUBF", 19857 argLen: 2, 19858 asm: mips.ASUBF, 19859 reg: regInfo{ 19860 inputs: []inputInfo{ 19861 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19862 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19863 }, 19864 outputs: []outputInfo{ 19865 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19866 }, 19867 }, 19868 }, 19869 { 19870 name: "SUBD", 19871 argLen: 2, 19872 asm: mips.ASUBD, 19873 reg: regInfo{ 19874 inputs: []inputInfo{ 19875 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19876 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19877 }, 19878 outputs: []outputInfo{ 19879 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19880 }, 19881 }, 19882 }, 19883 { 19884 name: "MULF", 19885 argLen: 2, 19886 commutative: true, 19887 asm: mips.AMULF, 19888 reg: regInfo{ 19889 inputs: []inputInfo{ 19890 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19891 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19892 }, 19893 outputs: []outputInfo{ 19894 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19895 }, 19896 }, 19897 }, 19898 { 19899 name: "MULD", 19900 argLen: 2, 19901 commutative: true, 19902 asm: mips.AMULD, 19903 reg: regInfo{ 19904 inputs: []inputInfo{ 19905 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19906 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19907 }, 19908 outputs: []outputInfo{ 19909 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19910 }, 19911 }, 19912 }, 19913 { 19914 name: "DIVF", 19915 argLen: 2, 19916 asm: mips.ADIVF, 19917 reg: regInfo{ 19918 inputs: []inputInfo{ 19919 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19920 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19921 }, 19922 outputs: []outputInfo{ 19923 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19924 }, 19925 }, 19926 }, 19927 { 19928 name: "DIVD", 19929 argLen: 2, 19930 asm: mips.ADIVD, 19931 reg: regInfo{ 19932 inputs: []inputInfo{ 19933 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19934 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19935 }, 19936 outputs: []outputInfo{ 19937 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19938 }, 19939 }, 19940 }, 19941 { 19942 name: "AND", 19943 argLen: 2, 19944 commutative: true, 19945 asm: mips.AAND, 19946 reg: regInfo{ 19947 inputs: []inputInfo{ 19948 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19949 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19950 }, 19951 outputs: []outputInfo{ 19952 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 19953 }, 19954 }, 19955 }, 19956 { 19957 name: "ANDconst", 19958 auxType: auxInt64, 19959 argLen: 1, 19960 asm: mips.AAND, 19961 reg: regInfo{ 19962 inputs: []inputInfo{ 19963 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19964 }, 19965 outputs: []outputInfo{ 19966 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 19967 }, 19968 }, 19969 }, 19970 { 19971 name: "OR", 19972 argLen: 2, 19973 commutative: true, 19974 asm: mips.AOR, 19975 reg: regInfo{ 19976 inputs: []inputInfo{ 19977 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19978 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19979 }, 19980 outputs: []outputInfo{ 19981 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 19982 }, 19983 }, 19984 }, 19985 { 19986 name: "ORconst", 19987 auxType: auxInt64, 19988 argLen: 1, 19989 asm: mips.AOR, 19990 reg: regInfo{ 19991 inputs: []inputInfo{ 19992 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19993 }, 19994 outputs: []outputInfo{ 19995 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 19996 }, 19997 }, 19998 }, 19999 { 20000 name: "XOR", 20001 argLen: 2, 20002 commutative: true, 20003 asm: mips.AXOR, 20004 reg: regInfo{ 20005 inputs: []inputInfo{ 20006 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20007 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20008 }, 20009 outputs: []outputInfo{ 20010 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20011 }, 20012 }, 20013 }, 20014 { 20015 name: "XORconst", 20016 auxType: auxInt64, 20017 argLen: 1, 20018 asm: mips.AXOR, 20019 reg: regInfo{ 20020 inputs: []inputInfo{ 20021 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20022 }, 20023 outputs: []outputInfo{ 20024 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20025 }, 20026 }, 20027 }, 20028 { 20029 name: "NOR", 20030 argLen: 2, 20031 commutative: true, 20032 asm: mips.ANOR, 20033 reg: regInfo{ 20034 inputs: []inputInfo{ 20035 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20036 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20037 }, 20038 outputs: []outputInfo{ 20039 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20040 }, 20041 }, 20042 }, 20043 { 20044 name: "NORconst", 20045 auxType: auxInt64, 20046 argLen: 1, 20047 asm: mips.ANOR, 20048 reg: regInfo{ 20049 inputs: []inputInfo{ 20050 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20051 }, 20052 outputs: []outputInfo{ 20053 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20054 }, 20055 }, 20056 }, 20057 { 20058 name: "NEGV", 20059 argLen: 1, 20060 reg: regInfo{ 20061 inputs: []inputInfo{ 20062 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20063 }, 20064 outputs: []outputInfo{ 20065 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20066 }, 20067 }, 20068 }, 20069 { 20070 name: "NEGF", 20071 argLen: 1, 20072 asm: mips.ANEGF, 20073 reg: regInfo{ 20074 inputs: []inputInfo{ 20075 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20076 }, 20077 outputs: []outputInfo{ 20078 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20079 }, 20080 }, 20081 }, 20082 { 20083 name: "NEGD", 20084 argLen: 1, 20085 asm: mips.ANEGD, 20086 reg: regInfo{ 20087 inputs: []inputInfo{ 20088 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20089 }, 20090 outputs: []outputInfo{ 20091 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20092 }, 20093 }, 20094 }, 20095 { 20096 name: "SQRTD", 20097 argLen: 1, 20098 asm: mips.ASQRTD, 20099 reg: regInfo{ 20100 inputs: []inputInfo{ 20101 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20102 }, 20103 outputs: []outputInfo{ 20104 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20105 }, 20106 }, 20107 }, 20108 { 20109 name: "SLLV", 20110 argLen: 2, 20111 asm: mips.ASLLV, 20112 reg: regInfo{ 20113 inputs: []inputInfo{ 20114 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20115 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20116 }, 20117 outputs: []outputInfo{ 20118 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20119 }, 20120 }, 20121 }, 20122 { 20123 name: "SLLVconst", 20124 auxType: auxInt64, 20125 argLen: 1, 20126 asm: mips.ASLLV, 20127 reg: regInfo{ 20128 inputs: []inputInfo{ 20129 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20130 }, 20131 outputs: []outputInfo{ 20132 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20133 }, 20134 }, 20135 }, 20136 { 20137 name: "SRLV", 20138 argLen: 2, 20139 asm: mips.ASRLV, 20140 reg: regInfo{ 20141 inputs: []inputInfo{ 20142 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20143 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20144 }, 20145 outputs: []outputInfo{ 20146 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20147 }, 20148 }, 20149 }, 20150 { 20151 name: "SRLVconst", 20152 auxType: auxInt64, 20153 argLen: 1, 20154 asm: mips.ASRLV, 20155 reg: regInfo{ 20156 inputs: []inputInfo{ 20157 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20158 }, 20159 outputs: []outputInfo{ 20160 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20161 }, 20162 }, 20163 }, 20164 { 20165 name: "SRAV", 20166 argLen: 2, 20167 asm: mips.ASRAV, 20168 reg: regInfo{ 20169 inputs: []inputInfo{ 20170 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20171 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20172 }, 20173 outputs: []outputInfo{ 20174 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20175 }, 20176 }, 20177 }, 20178 { 20179 name: "SRAVconst", 20180 auxType: auxInt64, 20181 argLen: 1, 20182 asm: mips.ASRAV, 20183 reg: regInfo{ 20184 inputs: []inputInfo{ 20185 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20186 }, 20187 outputs: []outputInfo{ 20188 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20189 }, 20190 }, 20191 }, 20192 { 20193 name: "SGT", 20194 argLen: 2, 20195 asm: mips.ASGT, 20196 reg: regInfo{ 20197 inputs: []inputInfo{ 20198 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20199 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20200 }, 20201 outputs: []outputInfo{ 20202 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20203 }, 20204 }, 20205 }, 20206 { 20207 name: "SGTconst", 20208 auxType: auxInt64, 20209 argLen: 1, 20210 asm: mips.ASGT, 20211 reg: regInfo{ 20212 inputs: []inputInfo{ 20213 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20214 }, 20215 outputs: []outputInfo{ 20216 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20217 }, 20218 }, 20219 }, 20220 { 20221 name: "SGTU", 20222 argLen: 2, 20223 asm: mips.ASGTU, 20224 reg: regInfo{ 20225 inputs: []inputInfo{ 20226 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20227 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20228 }, 20229 outputs: []outputInfo{ 20230 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20231 }, 20232 }, 20233 }, 20234 { 20235 name: "SGTUconst", 20236 auxType: auxInt64, 20237 argLen: 1, 20238 asm: mips.ASGTU, 20239 reg: regInfo{ 20240 inputs: []inputInfo{ 20241 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20242 }, 20243 outputs: []outputInfo{ 20244 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20245 }, 20246 }, 20247 }, 20248 { 20249 name: "CMPEQF", 20250 argLen: 2, 20251 asm: mips.ACMPEQF, 20252 reg: regInfo{ 20253 inputs: []inputInfo{ 20254 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20255 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20256 }, 20257 }, 20258 }, 20259 { 20260 name: "CMPEQD", 20261 argLen: 2, 20262 asm: mips.ACMPEQD, 20263 reg: regInfo{ 20264 inputs: []inputInfo{ 20265 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20266 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20267 }, 20268 }, 20269 }, 20270 { 20271 name: "CMPGEF", 20272 argLen: 2, 20273 asm: mips.ACMPGEF, 20274 reg: regInfo{ 20275 inputs: []inputInfo{ 20276 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20277 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20278 }, 20279 }, 20280 }, 20281 { 20282 name: "CMPGED", 20283 argLen: 2, 20284 asm: mips.ACMPGED, 20285 reg: regInfo{ 20286 inputs: []inputInfo{ 20287 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20288 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20289 }, 20290 }, 20291 }, 20292 { 20293 name: "CMPGTF", 20294 argLen: 2, 20295 asm: mips.ACMPGTF, 20296 reg: regInfo{ 20297 inputs: []inputInfo{ 20298 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20299 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20300 }, 20301 }, 20302 }, 20303 { 20304 name: "CMPGTD", 20305 argLen: 2, 20306 asm: mips.ACMPGTD, 20307 reg: regInfo{ 20308 inputs: []inputInfo{ 20309 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20310 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20311 }, 20312 }, 20313 }, 20314 { 20315 name: "MOVVconst", 20316 auxType: auxInt64, 20317 argLen: 0, 20318 rematerializeable: true, 20319 asm: mips.AMOVV, 20320 reg: regInfo{ 20321 outputs: []outputInfo{ 20322 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20323 }, 20324 }, 20325 }, 20326 { 20327 name: "MOVFconst", 20328 auxType: auxFloat64, 20329 argLen: 0, 20330 rematerializeable: true, 20331 asm: mips.AMOVF, 20332 reg: regInfo{ 20333 outputs: []outputInfo{ 20334 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20335 }, 20336 }, 20337 }, 20338 { 20339 name: "MOVDconst", 20340 auxType: auxFloat64, 20341 argLen: 0, 20342 rematerializeable: true, 20343 asm: mips.AMOVD, 20344 reg: regInfo{ 20345 outputs: []outputInfo{ 20346 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20347 }, 20348 }, 20349 }, 20350 { 20351 name: "MOVVaddr", 20352 auxType: auxSymOff, 20353 argLen: 1, 20354 rematerializeable: true, 20355 symEffect: SymAddr, 20356 asm: mips.AMOVV, 20357 reg: regInfo{ 20358 inputs: []inputInfo{ 20359 {0, 4611686018460942336}, // SP SB 20360 }, 20361 outputs: []outputInfo{ 20362 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20363 }, 20364 }, 20365 }, 20366 { 20367 name: "MOVBload", 20368 auxType: auxSymOff, 20369 argLen: 2, 20370 faultOnNilArg0: true, 20371 symEffect: SymRead, 20372 asm: mips.AMOVB, 20373 reg: regInfo{ 20374 inputs: []inputInfo{ 20375 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20376 }, 20377 outputs: []outputInfo{ 20378 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20379 }, 20380 }, 20381 }, 20382 { 20383 name: "MOVBUload", 20384 auxType: auxSymOff, 20385 argLen: 2, 20386 faultOnNilArg0: true, 20387 symEffect: SymRead, 20388 asm: mips.AMOVBU, 20389 reg: regInfo{ 20390 inputs: []inputInfo{ 20391 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20392 }, 20393 outputs: []outputInfo{ 20394 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20395 }, 20396 }, 20397 }, 20398 { 20399 name: "MOVHload", 20400 auxType: auxSymOff, 20401 argLen: 2, 20402 faultOnNilArg0: true, 20403 symEffect: SymRead, 20404 asm: mips.AMOVH, 20405 reg: regInfo{ 20406 inputs: []inputInfo{ 20407 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20408 }, 20409 outputs: []outputInfo{ 20410 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20411 }, 20412 }, 20413 }, 20414 { 20415 name: "MOVHUload", 20416 auxType: auxSymOff, 20417 argLen: 2, 20418 faultOnNilArg0: true, 20419 symEffect: SymRead, 20420 asm: mips.AMOVHU, 20421 reg: regInfo{ 20422 inputs: []inputInfo{ 20423 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20424 }, 20425 outputs: []outputInfo{ 20426 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20427 }, 20428 }, 20429 }, 20430 { 20431 name: "MOVWload", 20432 auxType: auxSymOff, 20433 argLen: 2, 20434 faultOnNilArg0: true, 20435 symEffect: SymRead, 20436 asm: mips.AMOVW, 20437 reg: regInfo{ 20438 inputs: []inputInfo{ 20439 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20440 }, 20441 outputs: []outputInfo{ 20442 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20443 }, 20444 }, 20445 }, 20446 { 20447 name: "MOVWUload", 20448 auxType: auxSymOff, 20449 argLen: 2, 20450 faultOnNilArg0: true, 20451 symEffect: SymRead, 20452 asm: mips.AMOVWU, 20453 reg: regInfo{ 20454 inputs: []inputInfo{ 20455 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20456 }, 20457 outputs: []outputInfo{ 20458 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20459 }, 20460 }, 20461 }, 20462 { 20463 name: "MOVVload", 20464 auxType: auxSymOff, 20465 argLen: 2, 20466 faultOnNilArg0: true, 20467 symEffect: SymRead, 20468 asm: mips.AMOVV, 20469 reg: regInfo{ 20470 inputs: []inputInfo{ 20471 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20472 }, 20473 outputs: []outputInfo{ 20474 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20475 }, 20476 }, 20477 }, 20478 { 20479 name: "MOVFload", 20480 auxType: auxSymOff, 20481 argLen: 2, 20482 faultOnNilArg0: true, 20483 symEffect: SymRead, 20484 asm: mips.AMOVF, 20485 reg: regInfo{ 20486 inputs: []inputInfo{ 20487 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20488 }, 20489 outputs: []outputInfo{ 20490 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20491 }, 20492 }, 20493 }, 20494 { 20495 name: "MOVDload", 20496 auxType: auxSymOff, 20497 argLen: 2, 20498 faultOnNilArg0: true, 20499 symEffect: SymRead, 20500 asm: mips.AMOVD, 20501 reg: regInfo{ 20502 inputs: []inputInfo{ 20503 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20504 }, 20505 outputs: []outputInfo{ 20506 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20507 }, 20508 }, 20509 }, 20510 { 20511 name: "MOVBstore", 20512 auxType: auxSymOff, 20513 argLen: 3, 20514 faultOnNilArg0: true, 20515 symEffect: SymWrite, 20516 asm: mips.AMOVB, 20517 reg: regInfo{ 20518 inputs: []inputInfo{ 20519 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20520 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20521 }, 20522 }, 20523 }, 20524 { 20525 name: "MOVHstore", 20526 auxType: auxSymOff, 20527 argLen: 3, 20528 faultOnNilArg0: true, 20529 symEffect: SymWrite, 20530 asm: mips.AMOVH, 20531 reg: regInfo{ 20532 inputs: []inputInfo{ 20533 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20534 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20535 }, 20536 }, 20537 }, 20538 { 20539 name: "MOVWstore", 20540 auxType: auxSymOff, 20541 argLen: 3, 20542 faultOnNilArg0: true, 20543 symEffect: SymWrite, 20544 asm: mips.AMOVW, 20545 reg: regInfo{ 20546 inputs: []inputInfo{ 20547 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20548 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20549 }, 20550 }, 20551 }, 20552 { 20553 name: "MOVVstore", 20554 auxType: auxSymOff, 20555 argLen: 3, 20556 faultOnNilArg0: true, 20557 symEffect: SymWrite, 20558 asm: mips.AMOVV, 20559 reg: regInfo{ 20560 inputs: []inputInfo{ 20561 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20562 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20563 }, 20564 }, 20565 }, 20566 { 20567 name: "MOVFstore", 20568 auxType: auxSymOff, 20569 argLen: 3, 20570 faultOnNilArg0: true, 20571 symEffect: SymWrite, 20572 asm: mips.AMOVF, 20573 reg: regInfo{ 20574 inputs: []inputInfo{ 20575 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20576 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20577 }, 20578 }, 20579 }, 20580 { 20581 name: "MOVDstore", 20582 auxType: auxSymOff, 20583 argLen: 3, 20584 faultOnNilArg0: true, 20585 symEffect: SymWrite, 20586 asm: mips.AMOVD, 20587 reg: regInfo{ 20588 inputs: []inputInfo{ 20589 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20590 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20591 }, 20592 }, 20593 }, 20594 { 20595 name: "MOVBstorezero", 20596 auxType: auxSymOff, 20597 argLen: 2, 20598 faultOnNilArg0: true, 20599 symEffect: SymWrite, 20600 asm: mips.AMOVB, 20601 reg: regInfo{ 20602 inputs: []inputInfo{ 20603 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20604 }, 20605 }, 20606 }, 20607 { 20608 name: "MOVHstorezero", 20609 auxType: auxSymOff, 20610 argLen: 2, 20611 faultOnNilArg0: true, 20612 symEffect: SymWrite, 20613 asm: mips.AMOVH, 20614 reg: regInfo{ 20615 inputs: []inputInfo{ 20616 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20617 }, 20618 }, 20619 }, 20620 { 20621 name: "MOVWstorezero", 20622 auxType: auxSymOff, 20623 argLen: 2, 20624 faultOnNilArg0: true, 20625 symEffect: SymWrite, 20626 asm: mips.AMOVW, 20627 reg: regInfo{ 20628 inputs: []inputInfo{ 20629 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20630 }, 20631 }, 20632 }, 20633 { 20634 name: "MOVVstorezero", 20635 auxType: auxSymOff, 20636 argLen: 2, 20637 faultOnNilArg0: true, 20638 symEffect: SymWrite, 20639 asm: mips.AMOVV, 20640 reg: regInfo{ 20641 inputs: []inputInfo{ 20642 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20643 }, 20644 }, 20645 }, 20646 { 20647 name: "MOVBreg", 20648 argLen: 1, 20649 asm: mips.AMOVB, 20650 reg: regInfo{ 20651 inputs: []inputInfo{ 20652 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20653 }, 20654 outputs: []outputInfo{ 20655 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20656 }, 20657 }, 20658 }, 20659 { 20660 name: "MOVBUreg", 20661 argLen: 1, 20662 asm: mips.AMOVBU, 20663 reg: regInfo{ 20664 inputs: []inputInfo{ 20665 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20666 }, 20667 outputs: []outputInfo{ 20668 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20669 }, 20670 }, 20671 }, 20672 { 20673 name: "MOVHreg", 20674 argLen: 1, 20675 asm: mips.AMOVH, 20676 reg: regInfo{ 20677 inputs: []inputInfo{ 20678 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20679 }, 20680 outputs: []outputInfo{ 20681 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20682 }, 20683 }, 20684 }, 20685 { 20686 name: "MOVHUreg", 20687 argLen: 1, 20688 asm: mips.AMOVHU, 20689 reg: regInfo{ 20690 inputs: []inputInfo{ 20691 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20692 }, 20693 outputs: []outputInfo{ 20694 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20695 }, 20696 }, 20697 }, 20698 { 20699 name: "MOVWreg", 20700 argLen: 1, 20701 asm: mips.AMOVW, 20702 reg: regInfo{ 20703 inputs: []inputInfo{ 20704 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20705 }, 20706 outputs: []outputInfo{ 20707 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20708 }, 20709 }, 20710 }, 20711 { 20712 name: "MOVWUreg", 20713 argLen: 1, 20714 asm: mips.AMOVWU, 20715 reg: regInfo{ 20716 inputs: []inputInfo{ 20717 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20718 }, 20719 outputs: []outputInfo{ 20720 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20721 }, 20722 }, 20723 }, 20724 { 20725 name: "MOVVreg", 20726 argLen: 1, 20727 asm: mips.AMOVV, 20728 reg: regInfo{ 20729 inputs: []inputInfo{ 20730 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20731 }, 20732 outputs: []outputInfo{ 20733 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20734 }, 20735 }, 20736 }, 20737 { 20738 name: "MOVVnop", 20739 argLen: 1, 20740 resultInArg0: true, 20741 reg: regInfo{ 20742 inputs: []inputInfo{ 20743 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20744 }, 20745 outputs: []outputInfo{ 20746 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20747 }, 20748 }, 20749 }, 20750 { 20751 name: "MOVWF", 20752 argLen: 1, 20753 asm: mips.AMOVWF, 20754 reg: regInfo{ 20755 inputs: []inputInfo{ 20756 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20757 }, 20758 outputs: []outputInfo{ 20759 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20760 }, 20761 }, 20762 }, 20763 { 20764 name: "MOVWD", 20765 argLen: 1, 20766 asm: mips.AMOVWD, 20767 reg: regInfo{ 20768 inputs: []inputInfo{ 20769 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20770 }, 20771 outputs: []outputInfo{ 20772 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20773 }, 20774 }, 20775 }, 20776 { 20777 name: "MOVVF", 20778 argLen: 1, 20779 asm: mips.AMOVVF, 20780 reg: regInfo{ 20781 inputs: []inputInfo{ 20782 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20783 }, 20784 outputs: []outputInfo{ 20785 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20786 }, 20787 }, 20788 }, 20789 { 20790 name: "MOVVD", 20791 argLen: 1, 20792 asm: mips.AMOVVD, 20793 reg: regInfo{ 20794 inputs: []inputInfo{ 20795 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20796 }, 20797 outputs: []outputInfo{ 20798 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20799 }, 20800 }, 20801 }, 20802 { 20803 name: "TRUNCFW", 20804 argLen: 1, 20805 asm: mips.ATRUNCFW, 20806 reg: regInfo{ 20807 inputs: []inputInfo{ 20808 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20809 }, 20810 outputs: []outputInfo{ 20811 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20812 }, 20813 }, 20814 }, 20815 { 20816 name: "TRUNCDW", 20817 argLen: 1, 20818 asm: mips.ATRUNCDW, 20819 reg: regInfo{ 20820 inputs: []inputInfo{ 20821 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20822 }, 20823 outputs: []outputInfo{ 20824 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20825 }, 20826 }, 20827 }, 20828 { 20829 name: "TRUNCFV", 20830 argLen: 1, 20831 asm: mips.ATRUNCFV, 20832 reg: regInfo{ 20833 inputs: []inputInfo{ 20834 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20835 }, 20836 outputs: []outputInfo{ 20837 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20838 }, 20839 }, 20840 }, 20841 { 20842 name: "TRUNCDV", 20843 argLen: 1, 20844 asm: mips.ATRUNCDV, 20845 reg: regInfo{ 20846 inputs: []inputInfo{ 20847 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20848 }, 20849 outputs: []outputInfo{ 20850 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20851 }, 20852 }, 20853 }, 20854 { 20855 name: "MOVFD", 20856 argLen: 1, 20857 asm: mips.AMOVFD, 20858 reg: regInfo{ 20859 inputs: []inputInfo{ 20860 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20861 }, 20862 outputs: []outputInfo{ 20863 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20864 }, 20865 }, 20866 }, 20867 { 20868 name: "MOVDF", 20869 argLen: 1, 20870 asm: mips.AMOVDF, 20871 reg: regInfo{ 20872 inputs: []inputInfo{ 20873 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20874 }, 20875 outputs: []outputInfo{ 20876 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20877 }, 20878 }, 20879 }, 20880 { 20881 name: "CALLstatic", 20882 auxType: auxSymOff, 20883 argLen: 1, 20884 clobberFlags: true, 20885 call: true, 20886 symEffect: SymNone, 20887 reg: regInfo{ 20888 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 20889 }, 20890 }, 20891 { 20892 name: "CALLclosure", 20893 auxType: auxInt64, 20894 argLen: 3, 20895 clobberFlags: true, 20896 call: true, 20897 reg: regInfo{ 20898 inputs: []inputInfo{ 20899 {1, 4194304}, // R22 20900 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 20901 }, 20902 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 20903 }, 20904 }, 20905 { 20906 name: "CALLinter", 20907 auxType: auxInt64, 20908 argLen: 2, 20909 clobberFlags: true, 20910 call: true, 20911 reg: regInfo{ 20912 inputs: []inputInfo{ 20913 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20914 }, 20915 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 20916 }, 20917 }, 20918 { 20919 name: "DUFFZERO", 20920 auxType: auxInt64, 20921 argLen: 2, 20922 faultOnNilArg0: true, 20923 reg: regInfo{ 20924 inputs: []inputInfo{ 20925 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20926 }, 20927 clobbers: 134217730, // R1 R31 20928 }, 20929 }, 20930 { 20931 name: "LoweredZero", 20932 auxType: auxInt64, 20933 argLen: 3, 20934 clobberFlags: true, 20935 faultOnNilArg0: true, 20936 reg: regInfo{ 20937 inputs: []inputInfo{ 20938 {0, 2}, // R1 20939 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20940 }, 20941 clobbers: 2, // R1 20942 }, 20943 }, 20944 { 20945 name: "LoweredMove", 20946 auxType: auxInt64, 20947 argLen: 4, 20948 clobberFlags: true, 20949 faultOnNilArg0: true, 20950 faultOnNilArg1: true, 20951 reg: regInfo{ 20952 inputs: []inputInfo{ 20953 {0, 4}, // R2 20954 {1, 2}, // R1 20955 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20956 }, 20957 clobbers: 6, // R1 R2 20958 }, 20959 }, 20960 { 20961 name: "LoweredAtomicLoad32", 20962 argLen: 2, 20963 faultOnNilArg0: true, 20964 reg: regInfo{ 20965 inputs: []inputInfo{ 20966 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20967 }, 20968 outputs: []outputInfo{ 20969 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20970 }, 20971 }, 20972 }, 20973 { 20974 name: "LoweredAtomicLoad64", 20975 argLen: 2, 20976 faultOnNilArg0: true, 20977 reg: regInfo{ 20978 inputs: []inputInfo{ 20979 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20980 }, 20981 outputs: []outputInfo{ 20982 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20983 }, 20984 }, 20985 }, 20986 { 20987 name: "LoweredAtomicStore32", 20988 argLen: 3, 20989 faultOnNilArg0: true, 20990 hasSideEffects: true, 20991 reg: regInfo{ 20992 inputs: []inputInfo{ 20993 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20994 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20995 }, 20996 }, 20997 }, 20998 { 20999 name: "LoweredAtomicStore64", 21000 argLen: 3, 21001 faultOnNilArg0: true, 21002 hasSideEffects: true, 21003 reg: regInfo{ 21004 inputs: []inputInfo{ 21005 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21006 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21007 }, 21008 }, 21009 }, 21010 { 21011 name: "LoweredAtomicStorezero32", 21012 argLen: 2, 21013 faultOnNilArg0: true, 21014 hasSideEffects: true, 21015 reg: regInfo{ 21016 inputs: []inputInfo{ 21017 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21018 }, 21019 }, 21020 }, 21021 { 21022 name: "LoweredAtomicStorezero64", 21023 argLen: 2, 21024 faultOnNilArg0: true, 21025 hasSideEffects: true, 21026 reg: regInfo{ 21027 inputs: []inputInfo{ 21028 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21029 }, 21030 }, 21031 }, 21032 { 21033 name: "LoweredAtomicExchange32", 21034 argLen: 3, 21035 resultNotInArgs: true, 21036 faultOnNilArg0: true, 21037 hasSideEffects: true, 21038 reg: regInfo{ 21039 inputs: []inputInfo{ 21040 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21041 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21042 }, 21043 outputs: []outputInfo{ 21044 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21045 }, 21046 }, 21047 }, 21048 { 21049 name: "LoweredAtomicExchange64", 21050 argLen: 3, 21051 resultNotInArgs: true, 21052 faultOnNilArg0: true, 21053 hasSideEffects: true, 21054 reg: regInfo{ 21055 inputs: []inputInfo{ 21056 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21057 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21058 }, 21059 outputs: []outputInfo{ 21060 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21061 }, 21062 }, 21063 }, 21064 { 21065 name: "LoweredAtomicAdd32", 21066 argLen: 3, 21067 resultNotInArgs: true, 21068 faultOnNilArg0: true, 21069 hasSideEffects: true, 21070 reg: regInfo{ 21071 inputs: []inputInfo{ 21072 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21073 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21074 }, 21075 outputs: []outputInfo{ 21076 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21077 }, 21078 }, 21079 }, 21080 { 21081 name: "LoweredAtomicAdd64", 21082 argLen: 3, 21083 resultNotInArgs: true, 21084 faultOnNilArg0: true, 21085 hasSideEffects: true, 21086 reg: regInfo{ 21087 inputs: []inputInfo{ 21088 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21089 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21090 }, 21091 outputs: []outputInfo{ 21092 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21093 }, 21094 }, 21095 }, 21096 { 21097 name: "LoweredAtomicAddconst32", 21098 auxType: auxInt32, 21099 argLen: 2, 21100 resultNotInArgs: true, 21101 faultOnNilArg0: true, 21102 hasSideEffects: true, 21103 reg: regInfo{ 21104 inputs: []inputInfo{ 21105 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21106 }, 21107 outputs: []outputInfo{ 21108 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21109 }, 21110 }, 21111 }, 21112 { 21113 name: "LoweredAtomicAddconst64", 21114 auxType: auxInt64, 21115 argLen: 2, 21116 resultNotInArgs: true, 21117 faultOnNilArg0: true, 21118 hasSideEffects: true, 21119 reg: regInfo{ 21120 inputs: []inputInfo{ 21121 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21122 }, 21123 outputs: []outputInfo{ 21124 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21125 }, 21126 }, 21127 }, 21128 { 21129 name: "LoweredAtomicCas32", 21130 argLen: 4, 21131 resultNotInArgs: true, 21132 faultOnNilArg0: true, 21133 hasSideEffects: true, 21134 reg: regInfo{ 21135 inputs: []inputInfo{ 21136 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21137 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21138 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21139 }, 21140 outputs: []outputInfo{ 21141 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21142 }, 21143 }, 21144 }, 21145 { 21146 name: "LoweredAtomicCas64", 21147 argLen: 4, 21148 resultNotInArgs: true, 21149 faultOnNilArg0: true, 21150 hasSideEffects: true, 21151 reg: regInfo{ 21152 inputs: []inputInfo{ 21153 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21154 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21155 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21156 }, 21157 outputs: []outputInfo{ 21158 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21159 }, 21160 }, 21161 }, 21162 { 21163 name: "LoweredNilCheck", 21164 argLen: 2, 21165 nilCheck: true, 21166 faultOnNilArg0: true, 21167 reg: regInfo{ 21168 inputs: []inputInfo{ 21169 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21170 }, 21171 }, 21172 }, 21173 { 21174 name: "FPFlagTrue", 21175 argLen: 1, 21176 reg: regInfo{ 21177 outputs: []outputInfo{ 21178 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21179 }, 21180 }, 21181 }, 21182 { 21183 name: "FPFlagFalse", 21184 argLen: 1, 21185 reg: regInfo{ 21186 outputs: []outputInfo{ 21187 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21188 }, 21189 }, 21190 }, 21191 { 21192 name: "LoweredGetClosurePtr", 21193 argLen: 0, 21194 zeroWidth: true, 21195 reg: regInfo{ 21196 outputs: []outputInfo{ 21197 {0, 4194304}, // R22 21198 }, 21199 }, 21200 }, 21201 { 21202 name: "LoweredGetCallerSP", 21203 argLen: 0, 21204 rematerializeable: true, 21205 reg: regInfo{ 21206 outputs: []outputInfo{ 21207 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21208 }, 21209 }, 21210 }, 21211 { 21212 name: "LoweredGetCallerPC", 21213 argLen: 0, 21214 rematerializeable: true, 21215 reg: regInfo{ 21216 outputs: []outputInfo{ 21217 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21218 }, 21219 }, 21220 }, 21221 { 21222 name: "LoweredWB", 21223 auxType: auxSym, 21224 argLen: 3, 21225 clobberFlags: true, 21226 symEffect: SymNone, 21227 reg: regInfo{ 21228 inputs: []inputInfo{ 21229 {0, 1048576}, // R20 21230 {1, 2097152}, // R21 21231 }, 21232 clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 21233 }, 21234 }, 21235 21236 { 21237 name: "ADD", 21238 argLen: 2, 21239 commutative: true, 21240 asm: ppc64.AADD, 21241 reg: regInfo{ 21242 inputs: []inputInfo{ 21243 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21244 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21245 }, 21246 outputs: []outputInfo{ 21247 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21248 }, 21249 }, 21250 }, 21251 { 21252 name: "ADDconst", 21253 auxType: auxInt64, 21254 argLen: 1, 21255 asm: ppc64.AADD, 21256 reg: regInfo{ 21257 inputs: []inputInfo{ 21258 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21259 }, 21260 outputs: []outputInfo{ 21261 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21262 }, 21263 }, 21264 }, 21265 { 21266 name: "FADD", 21267 argLen: 2, 21268 commutative: true, 21269 asm: ppc64.AFADD, 21270 reg: regInfo{ 21271 inputs: []inputInfo{ 21272 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21273 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21274 }, 21275 outputs: []outputInfo{ 21276 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21277 }, 21278 }, 21279 }, 21280 { 21281 name: "FADDS", 21282 argLen: 2, 21283 commutative: true, 21284 asm: ppc64.AFADDS, 21285 reg: regInfo{ 21286 inputs: []inputInfo{ 21287 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21288 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21289 }, 21290 outputs: []outputInfo{ 21291 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21292 }, 21293 }, 21294 }, 21295 { 21296 name: "SUB", 21297 argLen: 2, 21298 asm: ppc64.ASUB, 21299 reg: regInfo{ 21300 inputs: []inputInfo{ 21301 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21302 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21303 }, 21304 outputs: []outputInfo{ 21305 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21306 }, 21307 }, 21308 }, 21309 { 21310 name: "FSUB", 21311 argLen: 2, 21312 asm: ppc64.AFSUB, 21313 reg: regInfo{ 21314 inputs: []inputInfo{ 21315 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21316 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21317 }, 21318 outputs: []outputInfo{ 21319 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21320 }, 21321 }, 21322 }, 21323 { 21324 name: "FSUBS", 21325 argLen: 2, 21326 asm: ppc64.AFSUBS, 21327 reg: regInfo{ 21328 inputs: []inputInfo{ 21329 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21330 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21331 }, 21332 outputs: []outputInfo{ 21333 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21334 }, 21335 }, 21336 }, 21337 { 21338 name: "MULLD", 21339 argLen: 2, 21340 commutative: true, 21341 asm: ppc64.AMULLD, 21342 reg: regInfo{ 21343 inputs: []inputInfo{ 21344 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21345 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21346 }, 21347 outputs: []outputInfo{ 21348 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21349 }, 21350 }, 21351 }, 21352 { 21353 name: "MULLW", 21354 argLen: 2, 21355 commutative: true, 21356 asm: ppc64.AMULLW, 21357 reg: regInfo{ 21358 inputs: []inputInfo{ 21359 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21360 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21361 }, 21362 outputs: []outputInfo{ 21363 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21364 }, 21365 }, 21366 }, 21367 { 21368 name: "MULHD", 21369 argLen: 2, 21370 commutative: true, 21371 asm: ppc64.AMULHD, 21372 reg: regInfo{ 21373 inputs: []inputInfo{ 21374 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21375 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21376 }, 21377 outputs: []outputInfo{ 21378 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21379 }, 21380 }, 21381 }, 21382 { 21383 name: "MULHW", 21384 argLen: 2, 21385 commutative: true, 21386 asm: ppc64.AMULHW, 21387 reg: regInfo{ 21388 inputs: []inputInfo{ 21389 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21390 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21391 }, 21392 outputs: []outputInfo{ 21393 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21394 }, 21395 }, 21396 }, 21397 { 21398 name: "MULHDU", 21399 argLen: 2, 21400 commutative: true, 21401 asm: ppc64.AMULHDU, 21402 reg: regInfo{ 21403 inputs: []inputInfo{ 21404 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21405 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21406 }, 21407 outputs: []outputInfo{ 21408 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21409 }, 21410 }, 21411 }, 21412 { 21413 name: "MULHWU", 21414 argLen: 2, 21415 commutative: true, 21416 asm: ppc64.AMULHWU, 21417 reg: regInfo{ 21418 inputs: []inputInfo{ 21419 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21420 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21421 }, 21422 outputs: []outputInfo{ 21423 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21424 }, 21425 }, 21426 }, 21427 { 21428 name: "LoweredMuluhilo", 21429 argLen: 2, 21430 resultNotInArgs: true, 21431 reg: regInfo{ 21432 inputs: []inputInfo{ 21433 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21434 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21435 }, 21436 outputs: []outputInfo{ 21437 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21438 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21439 }, 21440 }, 21441 }, 21442 { 21443 name: "FMUL", 21444 argLen: 2, 21445 commutative: true, 21446 asm: ppc64.AFMUL, 21447 reg: regInfo{ 21448 inputs: []inputInfo{ 21449 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21450 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21451 }, 21452 outputs: []outputInfo{ 21453 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21454 }, 21455 }, 21456 }, 21457 { 21458 name: "FMULS", 21459 argLen: 2, 21460 commutative: true, 21461 asm: ppc64.AFMULS, 21462 reg: regInfo{ 21463 inputs: []inputInfo{ 21464 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21465 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21466 }, 21467 outputs: []outputInfo{ 21468 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21469 }, 21470 }, 21471 }, 21472 { 21473 name: "FMADD", 21474 argLen: 3, 21475 asm: ppc64.AFMADD, 21476 reg: regInfo{ 21477 inputs: []inputInfo{ 21478 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21479 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21480 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21481 }, 21482 outputs: []outputInfo{ 21483 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21484 }, 21485 }, 21486 }, 21487 { 21488 name: "FMADDS", 21489 argLen: 3, 21490 asm: ppc64.AFMADDS, 21491 reg: regInfo{ 21492 inputs: []inputInfo{ 21493 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21494 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21495 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21496 }, 21497 outputs: []outputInfo{ 21498 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21499 }, 21500 }, 21501 }, 21502 { 21503 name: "FMSUB", 21504 argLen: 3, 21505 asm: ppc64.AFMSUB, 21506 reg: regInfo{ 21507 inputs: []inputInfo{ 21508 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21509 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21510 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21511 }, 21512 outputs: []outputInfo{ 21513 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21514 }, 21515 }, 21516 }, 21517 { 21518 name: "FMSUBS", 21519 argLen: 3, 21520 asm: ppc64.AFMSUBS, 21521 reg: regInfo{ 21522 inputs: []inputInfo{ 21523 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21524 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21525 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21526 }, 21527 outputs: []outputInfo{ 21528 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21529 }, 21530 }, 21531 }, 21532 { 21533 name: "SRAD", 21534 argLen: 2, 21535 asm: ppc64.ASRAD, 21536 reg: regInfo{ 21537 inputs: []inputInfo{ 21538 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21539 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21540 }, 21541 outputs: []outputInfo{ 21542 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21543 }, 21544 }, 21545 }, 21546 { 21547 name: "SRAW", 21548 argLen: 2, 21549 asm: ppc64.ASRAW, 21550 reg: regInfo{ 21551 inputs: []inputInfo{ 21552 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21553 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21554 }, 21555 outputs: []outputInfo{ 21556 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21557 }, 21558 }, 21559 }, 21560 { 21561 name: "SRD", 21562 argLen: 2, 21563 asm: ppc64.ASRD, 21564 reg: regInfo{ 21565 inputs: []inputInfo{ 21566 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21567 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21568 }, 21569 outputs: []outputInfo{ 21570 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21571 }, 21572 }, 21573 }, 21574 { 21575 name: "SRW", 21576 argLen: 2, 21577 asm: ppc64.ASRW, 21578 reg: regInfo{ 21579 inputs: []inputInfo{ 21580 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21581 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21582 }, 21583 outputs: []outputInfo{ 21584 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21585 }, 21586 }, 21587 }, 21588 { 21589 name: "SLD", 21590 argLen: 2, 21591 asm: ppc64.ASLD, 21592 reg: regInfo{ 21593 inputs: []inputInfo{ 21594 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21595 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21596 }, 21597 outputs: []outputInfo{ 21598 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21599 }, 21600 }, 21601 }, 21602 { 21603 name: "SLW", 21604 argLen: 2, 21605 asm: ppc64.ASLW, 21606 reg: regInfo{ 21607 inputs: []inputInfo{ 21608 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21609 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21610 }, 21611 outputs: []outputInfo{ 21612 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21613 }, 21614 }, 21615 }, 21616 { 21617 name: "ROTL", 21618 argLen: 2, 21619 asm: ppc64.AROTL, 21620 reg: regInfo{ 21621 inputs: []inputInfo{ 21622 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21623 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21624 }, 21625 outputs: []outputInfo{ 21626 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21627 }, 21628 }, 21629 }, 21630 { 21631 name: "ROTLW", 21632 argLen: 2, 21633 asm: ppc64.AROTLW, 21634 reg: regInfo{ 21635 inputs: []inputInfo{ 21636 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21637 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21638 }, 21639 outputs: []outputInfo{ 21640 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21641 }, 21642 }, 21643 }, 21644 { 21645 name: "ADDconstForCarry", 21646 auxType: auxInt16, 21647 argLen: 1, 21648 asm: ppc64.AADDC, 21649 reg: regInfo{ 21650 inputs: []inputInfo{ 21651 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21652 }, 21653 clobbers: 2147483648, // R31 21654 }, 21655 }, 21656 { 21657 name: "MaskIfNotCarry", 21658 argLen: 1, 21659 asm: ppc64.AADDME, 21660 reg: regInfo{ 21661 outputs: []outputInfo{ 21662 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21663 }, 21664 }, 21665 }, 21666 { 21667 name: "SRADconst", 21668 auxType: auxInt64, 21669 argLen: 1, 21670 asm: ppc64.ASRAD, 21671 reg: regInfo{ 21672 inputs: []inputInfo{ 21673 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21674 }, 21675 outputs: []outputInfo{ 21676 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21677 }, 21678 }, 21679 }, 21680 { 21681 name: "SRAWconst", 21682 auxType: auxInt64, 21683 argLen: 1, 21684 asm: ppc64.ASRAW, 21685 reg: regInfo{ 21686 inputs: []inputInfo{ 21687 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21688 }, 21689 outputs: []outputInfo{ 21690 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21691 }, 21692 }, 21693 }, 21694 { 21695 name: "SRDconst", 21696 auxType: auxInt64, 21697 argLen: 1, 21698 asm: ppc64.ASRD, 21699 reg: regInfo{ 21700 inputs: []inputInfo{ 21701 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21702 }, 21703 outputs: []outputInfo{ 21704 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21705 }, 21706 }, 21707 }, 21708 { 21709 name: "SRWconst", 21710 auxType: auxInt64, 21711 argLen: 1, 21712 asm: ppc64.ASRW, 21713 reg: regInfo{ 21714 inputs: []inputInfo{ 21715 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21716 }, 21717 outputs: []outputInfo{ 21718 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21719 }, 21720 }, 21721 }, 21722 { 21723 name: "SLDconst", 21724 auxType: auxInt64, 21725 argLen: 1, 21726 asm: ppc64.ASLD, 21727 reg: regInfo{ 21728 inputs: []inputInfo{ 21729 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21730 }, 21731 outputs: []outputInfo{ 21732 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21733 }, 21734 }, 21735 }, 21736 { 21737 name: "SLWconst", 21738 auxType: auxInt64, 21739 argLen: 1, 21740 asm: ppc64.ASLW, 21741 reg: regInfo{ 21742 inputs: []inputInfo{ 21743 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21744 }, 21745 outputs: []outputInfo{ 21746 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21747 }, 21748 }, 21749 }, 21750 { 21751 name: "ROTLconst", 21752 auxType: auxInt64, 21753 argLen: 1, 21754 asm: ppc64.AROTL, 21755 reg: regInfo{ 21756 inputs: []inputInfo{ 21757 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21758 }, 21759 outputs: []outputInfo{ 21760 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21761 }, 21762 }, 21763 }, 21764 { 21765 name: "ROTLWconst", 21766 auxType: auxInt64, 21767 argLen: 1, 21768 asm: ppc64.AROTLW, 21769 reg: regInfo{ 21770 inputs: []inputInfo{ 21771 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21772 }, 21773 outputs: []outputInfo{ 21774 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21775 }, 21776 }, 21777 }, 21778 { 21779 name: "CNTLZD", 21780 argLen: 1, 21781 clobberFlags: true, 21782 asm: ppc64.ACNTLZD, 21783 reg: regInfo{ 21784 inputs: []inputInfo{ 21785 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21786 }, 21787 outputs: []outputInfo{ 21788 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21789 }, 21790 }, 21791 }, 21792 { 21793 name: "CNTLZW", 21794 argLen: 1, 21795 clobberFlags: true, 21796 asm: ppc64.ACNTLZW, 21797 reg: regInfo{ 21798 inputs: []inputInfo{ 21799 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21800 }, 21801 outputs: []outputInfo{ 21802 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21803 }, 21804 }, 21805 }, 21806 { 21807 name: "POPCNTD", 21808 argLen: 1, 21809 asm: ppc64.APOPCNTD, 21810 reg: regInfo{ 21811 inputs: []inputInfo{ 21812 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21813 }, 21814 outputs: []outputInfo{ 21815 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21816 }, 21817 }, 21818 }, 21819 { 21820 name: "POPCNTW", 21821 argLen: 1, 21822 asm: ppc64.APOPCNTW, 21823 reg: regInfo{ 21824 inputs: []inputInfo{ 21825 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21826 }, 21827 outputs: []outputInfo{ 21828 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21829 }, 21830 }, 21831 }, 21832 { 21833 name: "POPCNTB", 21834 argLen: 1, 21835 asm: ppc64.APOPCNTB, 21836 reg: regInfo{ 21837 inputs: []inputInfo{ 21838 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21839 }, 21840 outputs: []outputInfo{ 21841 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21842 }, 21843 }, 21844 }, 21845 { 21846 name: "FDIV", 21847 argLen: 2, 21848 asm: ppc64.AFDIV, 21849 reg: regInfo{ 21850 inputs: []inputInfo{ 21851 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21852 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21853 }, 21854 outputs: []outputInfo{ 21855 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21856 }, 21857 }, 21858 }, 21859 { 21860 name: "FDIVS", 21861 argLen: 2, 21862 asm: ppc64.AFDIVS, 21863 reg: regInfo{ 21864 inputs: []inputInfo{ 21865 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21866 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21867 }, 21868 outputs: []outputInfo{ 21869 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21870 }, 21871 }, 21872 }, 21873 { 21874 name: "DIVD", 21875 argLen: 2, 21876 asm: ppc64.ADIVD, 21877 reg: regInfo{ 21878 inputs: []inputInfo{ 21879 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21880 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21881 }, 21882 outputs: []outputInfo{ 21883 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21884 }, 21885 }, 21886 }, 21887 { 21888 name: "DIVW", 21889 argLen: 2, 21890 asm: ppc64.ADIVW, 21891 reg: regInfo{ 21892 inputs: []inputInfo{ 21893 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21894 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21895 }, 21896 outputs: []outputInfo{ 21897 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21898 }, 21899 }, 21900 }, 21901 { 21902 name: "DIVDU", 21903 argLen: 2, 21904 asm: ppc64.ADIVDU, 21905 reg: regInfo{ 21906 inputs: []inputInfo{ 21907 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21908 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21909 }, 21910 outputs: []outputInfo{ 21911 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21912 }, 21913 }, 21914 }, 21915 { 21916 name: "DIVWU", 21917 argLen: 2, 21918 asm: ppc64.ADIVWU, 21919 reg: regInfo{ 21920 inputs: []inputInfo{ 21921 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21922 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21923 }, 21924 outputs: []outputInfo{ 21925 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21926 }, 21927 }, 21928 }, 21929 { 21930 name: "FCTIDZ", 21931 argLen: 1, 21932 asm: ppc64.AFCTIDZ, 21933 reg: regInfo{ 21934 inputs: []inputInfo{ 21935 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21936 }, 21937 outputs: []outputInfo{ 21938 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21939 }, 21940 }, 21941 }, 21942 { 21943 name: "FCTIWZ", 21944 argLen: 1, 21945 asm: ppc64.AFCTIWZ, 21946 reg: regInfo{ 21947 inputs: []inputInfo{ 21948 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21949 }, 21950 outputs: []outputInfo{ 21951 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21952 }, 21953 }, 21954 }, 21955 { 21956 name: "FCFID", 21957 argLen: 1, 21958 asm: ppc64.AFCFID, 21959 reg: regInfo{ 21960 inputs: []inputInfo{ 21961 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21962 }, 21963 outputs: []outputInfo{ 21964 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21965 }, 21966 }, 21967 }, 21968 { 21969 name: "FCFIDS", 21970 argLen: 1, 21971 asm: ppc64.AFCFIDS, 21972 reg: regInfo{ 21973 inputs: []inputInfo{ 21974 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21975 }, 21976 outputs: []outputInfo{ 21977 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21978 }, 21979 }, 21980 }, 21981 { 21982 name: "FRSP", 21983 argLen: 1, 21984 asm: ppc64.AFRSP, 21985 reg: regInfo{ 21986 inputs: []inputInfo{ 21987 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21988 }, 21989 outputs: []outputInfo{ 21990 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21991 }, 21992 }, 21993 }, 21994 { 21995 name: "MFVSRD", 21996 argLen: 1, 21997 asm: ppc64.AMFVSRD, 21998 reg: regInfo{ 21999 inputs: []inputInfo{ 22000 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22001 }, 22002 outputs: []outputInfo{ 22003 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22004 }, 22005 }, 22006 }, 22007 { 22008 name: "MTVSRD", 22009 argLen: 1, 22010 asm: ppc64.AMTVSRD, 22011 reg: regInfo{ 22012 inputs: []inputInfo{ 22013 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22014 }, 22015 outputs: []outputInfo{ 22016 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22017 }, 22018 }, 22019 }, 22020 { 22021 name: "AND", 22022 argLen: 2, 22023 commutative: true, 22024 asm: ppc64.AAND, 22025 reg: regInfo{ 22026 inputs: []inputInfo{ 22027 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22028 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22029 }, 22030 outputs: []outputInfo{ 22031 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22032 }, 22033 }, 22034 }, 22035 { 22036 name: "ANDN", 22037 argLen: 2, 22038 asm: ppc64.AANDN, 22039 reg: regInfo{ 22040 inputs: []inputInfo{ 22041 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22042 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22043 }, 22044 outputs: []outputInfo{ 22045 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22046 }, 22047 }, 22048 }, 22049 { 22050 name: "OR", 22051 argLen: 2, 22052 commutative: true, 22053 asm: ppc64.AOR, 22054 reg: regInfo{ 22055 inputs: []inputInfo{ 22056 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22057 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22058 }, 22059 outputs: []outputInfo{ 22060 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22061 }, 22062 }, 22063 }, 22064 { 22065 name: "ORN", 22066 argLen: 2, 22067 asm: ppc64.AORN, 22068 reg: regInfo{ 22069 inputs: []inputInfo{ 22070 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22071 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22072 }, 22073 outputs: []outputInfo{ 22074 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22075 }, 22076 }, 22077 }, 22078 { 22079 name: "NOR", 22080 argLen: 2, 22081 commutative: true, 22082 asm: ppc64.ANOR, 22083 reg: regInfo{ 22084 inputs: []inputInfo{ 22085 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22086 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22087 }, 22088 outputs: []outputInfo{ 22089 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22090 }, 22091 }, 22092 }, 22093 { 22094 name: "XOR", 22095 argLen: 2, 22096 commutative: true, 22097 asm: ppc64.AXOR, 22098 reg: regInfo{ 22099 inputs: []inputInfo{ 22100 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22101 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22102 }, 22103 outputs: []outputInfo{ 22104 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22105 }, 22106 }, 22107 }, 22108 { 22109 name: "EQV", 22110 argLen: 2, 22111 commutative: true, 22112 asm: ppc64.AEQV, 22113 reg: regInfo{ 22114 inputs: []inputInfo{ 22115 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22116 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22117 }, 22118 outputs: []outputInfo{ 22119 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22120 }, 22121 }, 22122 }, 22123 { 22124 name: "NEG", 22125 argLen: 1, 22126 asm: ppc64.ANEG, 22127 reg: regInfo{ 22128 inputs: []inputInfo{ 22129 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22130 }, 22131 outputs: []outputInfo{ 22132 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22133 }, 22134 }, 22135 }, 22136 { 22137 name: "FNEG", 22138 argLen: 1, 22139 asm: ppc64.AFNEG, 22140 reg: regInfo{ 22141 inputs: []inputInfo{ 22142 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22143 }, 22144 outputs: []outputInfo{ 22145 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22146 }, 22147 }, 22148 }, 22149 { 22150 name: "FSQRT", 22151 argLen: 1, 22152 asm: ppc64.AFSQRT, 22153 reg: regInfo{ 22154 inputs: []inputInfo{ 22155 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22156 }, 22157 outputs: []outputInfo{ 22158 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22159 }, 22160 }, 22161 }, 22162 { 22163 name: "FSQRTS", 22164 argLen: 1, 22165 asm: ppc64.AFSQRTS, 22166 reg: regInfo{ 22167 inputs: []inputInfo{ 22168 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22169 }, 22170 outputs: []outputInfo{ 22171 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22172 }, 22173 }, 22174 }, 22175 { 22176 name: "FFLOOR", 22177 argLen: 1, 22178 asm: ppc64.AFRIM, 22179 reg: regInfo{ 22180 inputs: []inputInfo{ 22181 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22182 }, 22183 outputs: []outputInfo{ 22184 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22185 }, 22186 }, 22187 }, 22188 { 22189 name: "FCEIL", 22190 argLen: 1, 22191 asm: ppc64.AFRIP, 22192 reg: regInfo{ 22193 inputs: []inputInfo{ 22194 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22195 }, 22196 outputs: []outputInfo{ 22197 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22198 }, 22199 }, 22200 }, 22201 { 22202 name: "FTRUNC", 22203 argLen: 1, 22204 asm: ppc64.AFRIZ, 22205 reg: regInfo{ 22206 inputs: []inputInfo{ 22207 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22208 }, 22209 outputs: []outputInfo{ 22210 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22211 }, 22212 }, 22213 }, 22214 { 22215 name: "FROUND", 22216 argLen: 1, 22217 asm: ppc64.AFRIN, 22218 reg: regInfo{ 22219 inputs: []inputInfo{ 22220 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22221 }, 22222 outputs: []outputInfo{ 22223 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22224 }, 22225 }, 22226 }, 22227 { 22228 name: "FABS", 22229 argLen: 1, 22230 asm: ppc64.AFABS, 22231 reg: regInfo{ 22232 inputs: []inputInfo{ 22233 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22234 }, 22235 outputs: []outputInfo{ 22236 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22237 }, 22238 }, 22239 }, 22240 { 22241 name: "FNABS", 22242 argLen: 1, 22243 asm: ppc64.AFNABS, 22244 reg: regInfo{ 22245 inputs: []inputInfo{ 22246 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22247 }, 22248 outputs: []outputInfo{ 22249 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22250 }, 22251 }, 22252 }, 22253 { 22254 name: "FCPSGN", 22255 argLen: 2, 22256 asm: ppc64.AFCPSGN, 22257 reg: regInfo{ 22258 inputs: []inputInfo{ 22259 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22260 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22261 }, 22262 outputs: []outputInfo{ 22263 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22264 }, 22265 }, 22266 }, 22267 { 22268 name: "ORconst", 22269 auxType: auxInt64, 22270 argLen: 1, 22271 asm: ppc64.AOR, 22272 reg: regInfo{ 22273 inputs: []inputInfo{ 22274 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22275 }, 22276 outputs: []outputInfo{ 22277 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22278 }, 22279 }, 22280 }, 22281 { 22282 name: "XORconst", 22283 auxType: auxInt64, 22284 argLen: 1, 22285 asm: ppc64.AXOR, 22286 reg: regInfo{ 22287 inputs: []inputInfo{ 22288 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22289 }, 22290 outputs: []outputInfo{ 22291 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22292 }, 22293 }, 22294 }, 22295 { 22296 name: "ANDconst", 22297 auxType: auxInt64, 22298 argLen: 1, 22299 clobberFlags: true, 22300 asm: ppc64.AANDCC, 22301 reg: regInfo{ 22302 inputs: []inputInfo{ 22303 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22304 }, 22305 outputs: []outputInfo{ 22306 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22307 }, 22308 }, 22309 }, 22310 { 22311 name: "ANDCCconst", 22312 auxType: auxInt64, 22313 argLen: 1, 22314 asm: ppc64.AANDCC, 22315 reg: regInfo{ 22316 inputs: []inputInfo{ 22317 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22318 }, 22319 }, 22320 }, 22321 { 22322 name: "MOVBreg", 22323 argLen: 1, 22324 asm: ppc64.AMOVB, 22325 reg: regInfo{ 22326 inputs: []inputInfo{ 22327 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22328 }, 22329 outputs: []outputInfo{ 22330 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22331 }, 22332 }, 22333 }, 22334 { 22335 name: "MOVBZreg", 22336 argLen: 1, 22337 asm: ppc64.AMOVBZ, 22338 reg: regInfo{ 22339 inputs: []inputInfo{ 22340 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22341 }, 22342 outputs: []outputInfo{ 22343 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22344 }, 22345 }, 22346 }, 22347 { 22348 name: "MOVHreg", 22349 argLen: 1, 22350 asm: ppc64.AMOVH, 22351 reg: regInfo{ 22352 inputs: []inputInfo{ 22353 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22354 }, 22355 outputs: []outputInfo{ 22356 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22357 }, 22358 }, 22359 }, 22360 { 22361 name: "MOVHZreg", 22362 argLen: 1, 22363 asm: ppc64.AMOVHZ, 22364 reg: regInfo{ 22365 inputs: []inputInfo{ 22366 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22367 }, 22368 outputs: []outputInfo{ 22369 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22370 }, 22371 }, 22372 }, 22373 { 22374 name: "MOVWreg", 22375 argLen: 1, 22376 asm: ppc64.AMOVW, 22377 reg: regInfo{ 22378 inputs: []inputInfo{ 22379 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22380 }, 22381 outputs: []outputInfo{ 22382 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22383 }, 22384 }, 22385 }, 22386 { 22387 name: "MOVWZreg", 22388 argLen: 1, 22389 asm: ppc64.AMOVWZ, 22390 reg: regInfo{ 22391 inputs: []inputInfo{ 22392 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22393 }, 22394 outputs: []outputInfo{ 22395 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22396 }, 22397 }, 22398 }, 22399 { 22400 name: "MOVBZload", 22401 auxType: auxSymOff, 22402 argLen: 2, 22403 faultOnNilArg0: true, 22404 symEffect: SymRead, 22405 asm: ppc64.AMOVBZ, 22406 reg: regInfo{ 22407 inputs: []inputInfo{ 22408 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22409 }, 22410 outputs: []outputInfo{ 22411 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22412 }, 22413 }, 22414 }, 22415 { 22416 name: "MOVHload", 22417 auxType: auxSymOff, 22418 argLen: 2, 22419 faultOnNilArg0: true, 22420 symEffect: SymRead, 22421 asm: ppc64.AMOVH, 22422 reg: regInfo{ 22423 inputs: []inputInfo{ 22424 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22425 }, 22426 outputs: []outputInfo{ 22427 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22428 }, 22429 }, 22430 }, 22431 { 22432 name: "MOVHZload", 22433 auxType: auxSymOff, 22434 argLen: 2, 22435 faultOnNilArg0: true, 22436 symEffect: SymRead, 22437 asm: ppc64.AMOVHZ, 22438 reg: regInfo{ 22439 inputs: []inputInfo{ 22440 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22441 }, 22442 outputs: []outputInfo{ 22443 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22444 }, 22445 }, 22446 }, 22447 { 22448 name: "MOVWload", 22449 auxType: auxSymOff, 22450 argLen: 2, 22451 faultOnNilArg0: true, 22452 symEffect: SymRead, 22453 asm: ppc64.AMOVW, 22454 reg: regInfo{ 22455 inputs: []inputInfo{ 22456 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22457 }, 22458 outputs: []outputInfo{ 22459 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22460 }, 22461 }, 22462 }, 22463 { 22464 name: "MOVWZload", 22465 auxType: auxSymOff, 22466 argLen: 2, 22467 faultOnNilArg0: true, 22468 symEffect: SymRead, 22469 asm: ppc64.AMOVWZ, 22470 reg: regInfo{ 22471 inputs: []inputInfo{ 22472 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22473 }, 22474 outputs: []outputInfo{ 22475 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22476 }, 22477 }, 22478 }, 22479 { 22480 name: "MOVDload", 22481 auxType: auxSymOff, 22482 argLen: 2, 22483 faultOnNilArg0: true, 22484 symEffect: SymRead, 22485 asm: ppc64.AMOVD, 22486 reg: regInfo{ 22487 inputs: []inputInfo{ 22488 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22489 }, 22490 outputs: []outputInfo{ 22491 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22492 }, 22493 }, 22494 }, 22495 { 22496 name: "MOVDBRload", 22497 auxType: auxSymOff, 22498 argLen: 2, 22499 faultOnNilArg0: true, 22500 symEffect: SymRead, 22501 asm: ppc64.AMOVDBR, 22502 reg: regInfo{ 22503 inputs: []inputInfo{ 22504 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22505 }, 22506 outputs: []outputInfo{ 22507 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22508 }, 22509 }, 22510 }, 22511 { 22512 name: "MOVWBRload", 22513 auxType: auxSymOff, 22514 argLen: 2, 22515 faultOnNilArg0: true, 22516 symEffect: SymRead, 22517 asm: ppc64.AMOVWBR, 22518 reg: regInfo{ 22519 inputs: []inputInfo{ 22520 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22521 }, 22522 outputs: []outputInfo{ 22523 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22524 }, 22525 }, 22526 }, 22527 { 22528 name: "MOVHBRload", 22529 auxType: auxSymOff, 22530 argLen: 2, 22531 faultOnNilArg0: true, 22532 symEffect: SymRead, 22533 asm: ppc64.AMOVHBR, 22534 reg: regInfo{ 22535 inputs: []inputInfo{ 22536 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22537 }, 22538 outputs: []outputInfo{ 22539 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22540 }, 22541 }, 22542 }, 22543 { 22544 name: "MOVBZloadidx", 22545 auxType: auxSymOff, 22546 argLen: 3, 22547 faultOnNilArg0: true, 22548 symEffect: SymRead, 22549 asm: ppc64.AMOVBZ, 22550 reg: regInfo{ 22551 inputs: []inputInfo{ 22552 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22553 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22554 }, 22555 outputs: []outputInfo{ 22556 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22557 }, 22558 }, 22559 }, 22560 { 22561 name: "MOVHloadidx", 22562 auxType: auxSymOff, 22563 argLen: 3, 22564 faultOnNilArg0: true, 22565 symEffect: SymRead, 22566 asm: ppc64.AMOVH, 22567 reg: regInfo{ 22568 inputs: []inputInfo{ 22569 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22570 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22571 }, 22572 outputs: []outputInfo{ 22573 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22574 }, 22575 }, 22576 }, 22577 { 22578 name: "MOVHZloadidx", 22579 auxType: auxSymOff, 22580 argLen: 3, 22581 faultOnNilArg0: true, 22582 symEffect: SymRead, 22583 asm: ppc64.AMOVHZ, 22584 reg: regInfo{ 22585 inputs: []inputInfo{ 22586 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22587 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22588 }, 22589 outputs: []outputInfo{ 22590 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22591 }, 22592 }, 22593 }, 22594 { 22595 name: "MOVWloadidx", 22596 auxType: auxSymOff, 22597 argLen: 3, 22598 faultOnNilArg0: true, 22599 symEffect: SymRead, 22600 asm: ppc64.AMOVW, 22601 reg: regInfo{ 22602 inputs: []inputInfo{ 22603 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22604 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22605 }, 22606 outputs: []outputInfo{ 22607 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22608 }, 22609 }, 22610 }, 22611 { 22612 name: "MOVWZloadidx", 22613 auxType: auxSymOff, 22614 argLen: 3, 22615 faultOnNilArg0: true, 22616 symEffect: SymRead, 22617 asm: ppc64.AMOVWZ, 22618 reg: regInfo{ 22619 inputs: []inputInfo{ 22620 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22621 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22622 }, 22623 outputs: []outputInfo{ 22624 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22625 }, 22626 }, 22627 }, 22628 { 22629 name: "MOVDloadidx", 22630 auxType: auxSymOff, 22631 argLen: 3, 22632 faultOnNilArg0: true, 22633 symEffect: SymRead, 22634 asm: ppc64.AMOVD, 22635 reg: regInfo{ 22636 inputs: []inputInfo{ 22637 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22638 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22639 }, 22640 outputs: []outputInfo{ 22641 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22642 }, 22643 }, 22644 }, 22645 { 22646 name: "MOVHBRloadidx", 22647 auxType: auxSymOff, 22648 argLen: 3, 22649 faultOnNilArg0: true, 22650 symEffect: SymRead, 22651 asm: ppc64.AMOVHBR, 22652 reg: regInfo{ 22653 inputs: []inputInfo{ 22654 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22655 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22656 }, 22657 outputs: []outputInfo{ 22658 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22659 }, 22660 }, 22661 }, 22662 { 22663 name: "MOVWBRloadidx", 22664 auxType: auxSymOff, 22665 argLen: 3, 22666 faultOnNilArg0: true, 22667 symEffect: SymRead, 22668 asm: ppc64.AMOVWBR, 22669 reg: regInfo{ 22670 inputs: []inputInfo{ 22671 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22672 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22673 }, 22674 outputs: []outputInfo{ 22675 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22676 }, 22677 }, 22678 }, 22679 { 22680 name: "MOVDBRloadidx", 22681 auxType: auxSymOff, 22682 argLen: 3, 22683 faultOnNilArg0: true, 22684 symEffect: SymRead, 22685 asm: ppc64.AMOVDBR, 22686 reg: regInfo{ 22687 inputs: []inputInfo{ 22688 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22689 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22690 }, 22691 outputs: []outputInfo{ 22692 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22693 }, 22694 }, 22695 }, 22696 { 22697 name: "FMOVDloadidx", 22698 auxType: auxSymOff, 22699 argLen: 3, 22700 faultOnNilArg0: true, 22701 symEffect: SymRead, 22702 asm: ppc64.AFMOVD, 22703 reg: regInfo{ 22704 inputs: []inputInfo{ 22705 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22706 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22707 }, 22708 outputs: []outputInfo{ 22709 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22710 }, 22711 }, 22712 }, 22713 { 22714 name: "FMOVSloadidx", 22715 auxType: auxSymOff, 22716 argLen: 3, 22717 faultOnNilArg0: true, 22718 symEffect: SymRead, 22719 asm: ppc64.AFMOVS, 22720 reg: regInfo{ 22721 inputs: []inputInfo{ 22722 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22723 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22724 }, 22725 outputs: []outputInfo{ 22726 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22727 }, 22728 }, 22729 }, 22730 { 22731 name: "MOVDBRstore", 22732 auxType: auxSymOff, 22733 argLen: 3, 22734 faultOnNilArg0: true, 22735 symEffect: SymWrite, 22736 asm: ppc64.AMOVDBR, 22737 reg: regInfo{ 22738 inputs: []inputInfo{ 22739 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22740 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22741 }, 22742 }, 22743 }, 22744 { 22745 name: "MOVWBRstore", 22746 auxType: auxSymOff, 22747 argLen: 3, 22748 faultOnNilArg0: true, 22749 symEffect: SymWrite, 22750 asm: ppc64.AMOVWBR, 22751 reg: regInfo{ 22752 inputs: []inputInfo{ 22753 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22754 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22755 }, 22756 }, 22757 }, 22758 { 22759 name: "MOVHBRstore", 22760 auxType: auxSymOff, 22761 argLen: 3, 22762 faultOnNilArg0: true, 22763 symEffect: SymWrite, 22764 asm: ppc64.AMOVHBR, 22765 reg: regInfo{ 22766 inputs: []inputInfo{ 22767 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22768 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22769 }, 22770 }, 22771 }, 22772 { 22773 name: "FMOVDload", 22774 auxType: auxSymOff, 22775 argLen: 2, 22776 faultOnNilArg0: true, 22777 symEffect: SymRead, 22778 asm: ppc64.AFMOVD, 22779 reg: regInfo{ 22780 inputs: []inputInfo{ 22781 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22782 }, 22783 outputs: []outputInfo{ 22784 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22785 }, 22786 }, 22787 }, 22788 { 22789 name: "FMOVSload", 22790 auxType: auxSymOff, 22791 argLen: 2, 22792 faultOnNilArg0: true, 22793 symEffect: SymRead, 22794 asm: ppc64.AFMOVS, 22795 reg: regInfo{ 22796 inputs: []inputInfo{ 22797 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22798 }, 22799 outputs: []outputInfo{ 22800 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22801 }, 22802 }, 22803 }, 22804 { 22805 name: "MOVBstore", 22806 auxType: auxSymOff, 22807 argLen: 3, 22808 faultOnNilArg0: true, 22809 symEffect: SymWrite, 22810 asm: ppc64.AMOVB, 22811 reg: regInfo{ 22812 inputs: []inputInfo{ 22813 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22814 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22815 }, 22816 }, 22817 }, 22818 { 22819 name: "MOVHstore", 22820 auxType: auxSymOff, 22821 argLen: 3, 22822 faultOnNilArg0: true, 22823 symEffect: SymWrite, 22824 asm: ppc64.AMOVH, 22825 reg: regInfo{ 22826 inputs: []inputInfo{ 22827 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22828 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22829 }, 22830 }, 22831 }, 22832 { 22833 name: "MOVWstore", 22834 auxType: auxSymOff, 22835 argLen: 3, 22836 faultOnNilArg0: true, 22837 symEffect: SymWrite, 22838 asm: ppc64.AMOVW, 22839 reg: regInfo{ 22840 inputs: []inputInfo{ 22841 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22842 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22843 }, 22844 }, 22845 }, 22846 { 22847 name: "MOVDstore", 22848 auxType: auxSymOff, 22849 argLen: 3, 22850 faultOnNilArg0: true, 22851 symEffect: SymWrite, 22852 asm: ppc64.AMOVD, 22853 reg: regInfo{ 22854 inputs: []inputInfo{ 22855 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22856 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22857 }, 22858 }, 22859 }, 22860 { 22861 name: "FMOVDstore", 22862 auxType: auxSymOff, 22863 argLen: 3, 22864 faultOnNilArg0: true, 22865 symEffect: SymWrite, 22866 asm: ppc64.AFMOVD, 22867 reg: regInfo{ 22868 inputs: []inputInfo{ 22869 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22870 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22871 }, 22872 }, 22873 }, 22874 { 22875 name: "FMOVSstore", 22876 auxType: auxSymOff, 22877 argLen: 3, 22878 faultOnNilArg0: true, 22879 symEffect: SymWrite, 22880 asm: ppc64.AFMOVS, 22881 reg: regInfo{ 22882 inputs: []inputInfo{ 22883 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22884 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22885 }, 22886 }, 22887 }, 22888 { 22889 name: "MOVBstoreidx", 22890 auxType: auxSymOff, 22891 argLen: 4, 22892 faultOnNilArg0: true, 22893 symEffect: SymWrite, 22894 asm: ppc64.AMOVB, 22895 reg: regInfo{ 22896 inputs: []inputInfo{ 22897 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22898 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22899 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22900 }, 22901 }, 22902 }, 22903 { 22904 name: "MOVHstoreidx", 22905 auxType: auxSymOff, 22906 argLen: 4, 22907 faultOnNilArg0: true, 22908 symEffect: SymWrite, 22909 asm: ppc64.AMOVH, 22910 reg: regInfo{ 22911 inputs: []inputInfo{ 22912 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22913 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22914 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22915 }, 22916 }, 22917 }, 22918 { 22919 name: "MOVWstoreidx", 22920 auxType: auxSymOff, 22921 argLen: 4, 22922 faultOnNilArg0: true, 22923 symEffect: SymWrite, 22924 asm: ppc64.AMOVW, 22925 reg: regInfo{ 22926 inputs: []inputInfo{ 22927 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22928 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22929 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22930 }, 22931 }, 22932 }, 22933 { 22934 name: "MOVDstoreidx", 22935 auxType: auxSymOff, 22936 argLen: 4, 22937 faultOnNilArg0: true, 22938 symEffect: SymWrite, 22939 asm: ppc64.AMOVD, 22940 reg: regInfo{ 22941 inputs: []inputInfo{ 22942 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22943 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22944 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22945 }, 22946 }, 22947 }, 22948 { 22949 name: "FMOVDstoreidx", 22950 auxType: auxSymOff, 22951 argLen: 4, 22952 faultOnNilArg0: true, 22953 symEffect: SymWrite, 22954 asm: ppc64.AFMOVD, 22955 reg: regInfo{ 22956 inputs: []inputInfo{ 22957 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22958 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22959 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22960 }, 22961 }, 22962 }, 22963 { 22964 name: "FMOVSstoreidx", 22965 auxType: auxSymOff, 22966 argLen: 4, 22967 faultOnNilArg0: true, 22968 symEffect: SymWrite, 22969 asm: ppc64.AFMOVS, 22970 reg: regInfo{ 22971 inputs: []inputInfo{ 22972 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22973 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22974 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22975 }, 22976 }, 22977 }, 22978 { 22979 name: "MOVHBRstoreidx", 22980 auxType: auxSymOff, 22981 argLen: 4, 22982 faultOnNilArg0: true, 22983 symEffect: SymWrite, 22984 asm: ppc64.AMOVHBR, 22985 reg: regInfo{ 22986 inputs: []inputInfo{ 22987 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22988 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22989 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22990 }, 22991 }, 22992 }, 22993 { 22994 name: "MOVWBRstoreidx", 22995 auxType: auxSymOff, 22996 argLen: 4, 22997 faultOnNilArg0: true, 22998 symEffect: SymWrite, 22999 asm: ppc64.AMOVWBR, 23000 reg: regInfo{ 23001 inputs: []inputInfo{ 23002 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23003 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23004 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23005 }, 23006 }, 23007 }, 23008 { 23009 name: "MOVDBRstoreidx", 23010 auxType: auxSymOff, 23011 argLen: 4, 23012 faultOnNilArg0: true, 23013 symEffect: SymWrite, 23014 asm: ppc64.AMOVDBR, 23015 reg: regInfo{ 23016 inputs: []inputInfo{ 23017 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23018 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23019 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23020 }, 23021 }, 23022 }, 23023 { 23024 name: "MOVBstorezero", 23025 auxType: auxSymOff, 23026 argLen: 2, 23027 faultOnNilArg0: true, 23028 symEffect: SymWrite, 23029 asm: ppc64.AMOVB, 23030 reg: regInfo{ 23031 inputs: []inputInfo{ 23032 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23033 }, 23034 }, 23035 }, 23036 { 23037 name: "MOVHstorezero", 23038 auxType: auxSymOff, 23039 argLen: 2, 23040 faultOnNilArg0: true, 23041 symEffect: SymWrite, 23042 asm: ppc64.AMOVH, 23043 reg: regInfo{ 23044 inputs: []inputInfo{ 23045 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23046 }, 23047 }, 23048 }, 23049 { 23050 name: "MOVWstorezero", 23051 auxType: auxSymOff, 23052 argLen: 2, 23053 faultOnNilArg0: true, 23054 symEffect: SymWrite, 23055 asm: ppc64.AMOVW, 23056 reg: regInfo{ 23057 inputs: []inputInfo{ 23058 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23059 }, 23060 }, 23061 }, 23062 { 23063 name: "MOVDstorezero", 23064 auxType: auxSymOff, 23065 argLen: 2, 23066 faultOnNilArg0: true, 23067 symEffect: SymWrite, 23068 asm: ppc64.AMOVD, 23069 reg: regInfo{ 23070 inputs: []inputInfo{ 23071 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23072 }, 23073 }, 23074 }, 23075 { 23076 name: "MOVDaddr", 23077 auxType: auxSymOff, 23078 argLen: 1, 23079 rematerializeable: true, 23080 symEffect: SymAddr, 23081 asm: ppc64.AMOVD, 23082 reg: regInfo{ 23083 inputs: []inputInfo{ 23084 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23085 }, 23086 outputs: []outputInfo{ 23087 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23088 }, 23089 }, 23090 }, 23091 { 23092 name: "MOVDconst", 23093 auxType: auxInt64, 23094 argLen: 0, 23095 rematerializeable: true, 23096 asm: ppc64.AMOVD, 23097 reg: regInfo{ 23098 outputs: []outputInfo{ 23099 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23100 }, 23101 }, 23102 }, 23103 { 23104 name: "FMOVDconst", 23105 auxType: auxFloat64, 23106 argLen: 0, 23107 rematerializeable: true, 23108 asm: ppc64.AFMOVD, 23109 reg: regInfo{ 23110 outputs: []outputInfo{ 23111 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23112 }, 23113 }, 23114 }, 23115 { 23116 name: "FMOVSconst", 23117 auxType: auxFloat32, 23118 argLen: 0, 23119 rematerializeable: true, 23120 asm: ppc64.AFMOVS, 23121 reg: regInfo{ 23122 outputs: []outputInfo{ 23123 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23124 }, 23125 }, 23126 }, 23127 { 23128 name: "FCMPU", 23129 argLen: 2, 23130 asm: ppc64.AFCMPU, 23131 reg: regInfo{ 23132 inputs: []inputInfo{ 23133 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23134 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23135 }, 23136 }, 23137 }, 23138 { 23139 name: "CMP", 23140 argLen: 2, 23141 asm: ppc64.ACMP, 23142 reg: regInfo{ 23143 inputs: []inputInfo{ 23144 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23145 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23146 }, 23147 }, 23148 }, 23149 { 23150 name: "CMPU", 23151 argLen: 2, 23152 asm: ppc64.ACMPU, 23153 reg: regInfo{ 23154 inputs: []inputInfo{ 23155 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23156 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23157 }, 23158 }, 23159 }, 23160 { 23161 name: "CMPW", 23162 argLen: 2, 23163 asm: ppc64.ACMPW, 23164 reg: regInfo{ 23165 inputs: []inputInfo{ 23166 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23167 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23168 }, 23169 }, 23170 }, 23171 { 23172 name: "CMPWU", 23173 argLen: 2, 23174 asm: ppc64.ACMPWU, 23175 reg: regInfo{ 23176 inputs: []inputInfo{ 23177 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23178 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23179 }, 23180 }, 23181 }, 23182 { 23183 name: "CMPconst", 23184 auxType: auxInt64, 23185 argLen: 1, 23186 asm: ppc64.ACMP, 23187 reg: regInfo{ 23188 inputs: []inputInfo{ 23189 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23190 }, 23191 }, 23192 }, 23193 { 23194 name: "CMPUconst", 23195 auxType: auxInt64, 23196 argLen: 1, 23197 asm: ppc64.ACMPU, 23198 reg: regInfo{ 23199 inputs: []inputInfo{ 23200 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23201 }, 23202 }, 23203 }, 23204 { 23205 name: "CMPWconst", 23206 auxType: auxInt32, 23207 argLen: 1, 23208 asm: ppc64.ACMPW, 23209 reg: regInfo{ 23210 inputs: []inputInfo{ 23211 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23212 }, 23213 }, 23214 }, 23215 { 23216 name: "CMPWUconst", 23217 auxType: auxInt32, 23218 argLen: 1, 23219 asm: ppc64.ACMPWU, 23220 reg: regInfo{ 23221 inputs: []inputInfo{ 23222 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23223 }, 23224 }, 23225 }, 23226 { 23227 name: "Equal", 23228 argLen: 1, 23229 reg: regInfo{ 23230 outputs: []outputInfo{ 23231 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23232 }, 23233 }, 23234 }, 23235 { 23236 name: "NotEqual", 23237 argLen: 1, 23238 reg: regInfo{ 23239 outputs: []outputInfo{ 23240 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23241 }, 23242 }, 23243 }, 23244 { 23245 name: "LessThan", 23246 argLen: 1, 23247 reg: regInfo{ 23248 outputs: []outputInfo{ 23249 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23250 }, 23251 }, 23252 }, 23253 { 23254 name: "FLessThan", 23255 argLen: 1, 23256 reg: regInfo{ 23257 outputs: []outputInfo{ 23258 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23259 }, 23260 }, 23261 }, 23262 { 23263 name: "LessEqual", 23264 argLen: 1, 23265 reg: regInfo{ 23266 outputs: []outputInfo{ 23267 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23268 }, 23269 }, 23270 }, 23271 { 23272 name: "FLessEqual", 23273 argLen: 1, 23274 reg: regInfo{ 23275 outputs: []outputInfo{ 23276 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23277 }, 23278 }, 23279 }, 23280 { 23281 name: "GreaterThan", 23282 argLen: 1, 23283 reg: regInfo{ 23284 outputs: []outputInfo{ 23285 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23286 }, 23287 }, 23288 }, 23289 { 23290 name: "FGreaterThan", 23291 argLen: 1, 23292 reg: regInfo{ 23293 outputs: []outputInfo{ 23294 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23295 }, 23296 }, 23297 }, 23298 { 23299 name: "GreaterEqual", 23300 argLen: 1, 23301 reg: regInfo{ 23302 outputs: []outputInfo{ 23303 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23304 }, 23305 }, 23306 }, 23307 { 23308 name: "FGreaterEqual", 23309 argLen: 1, 23310 reg: regInfo{ 23311 outputs: []outputInfo{ 23312 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23313 }, 23314 }, 23315 }, 23316 { 23317 name: "LoweredGetClosurePtr", 23318 argLen: 0, 23319 zeroWidth: true, 23320 reg: regInfo{ 23321 outputs: []outputInfo{ 23322 {0, 2048}, // R11 23323 }, 23324 }, 23325 }, 23326 { 23327 name: "LoweredGetCallerSP", 23328 argLen: 0, 23329 rematerializeable: true, 23330 reg: regInfo{ 23331 outputs: []outputInfo{ 23332 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23333 }, 23334 }, 23335 }, 23336 { 23337 name: "LoweredGetCallerPC", 23338 argLen: 0, 23339 rematerializeable: true, 23340 reg: regInfo{ 23341 outputs: []outputInfo{ 23342 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23343 }, 23344 }, 23345 }, 23346 { 23347 name: "LoweredNilCheck", 23348 argLen: 2, 23349 clobberFlags: true, 23350 nilCheck: true, 23351 faultOnNilArg0: true, 23352 reg: regInfo{ 23353 inputs: []inputInfo{ 23354 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23355 }, 23356 clobbers: 2147483648, // R31 23357 }, 23358 }, 23359 { 23360 name: "LoweredRound32F", 23361 argLen: 1, 23362 resultInArg0: true, 23363 zeroWidth: true, 23364 reg: regInfo{ 23365 inputs: []inputInfo{ 23366 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23367 }, 23368 outputs: []outputInfo{ 23369 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23370 }, 23371 }, 23372 }, 23373 { 23374 name: "LoweredRound64F", 23375 argLen: 1, 23376 resultInArg0: true, 23377 zeroWidth: true, 23378 reg: regInfo{ 23379 inputs: []inputInfo{ 23380 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23381 }, 23382 outputs: []outputInfo{ 23383 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23384 }, 23385 }, 23386 }, 23387 { 23388 name: "CALLstatic", 23389 auxType: auxSymOff, 23390 argLen: 1, 23391 clobberFlags: true, 23392 call: true, 23393 symEffect: SymNone, 23394 reg: regInfo{ 23395 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23396 }, 23397 }, 23398 { 23399 name: "CALLclosure", 23400 auxType: auxInt64, 23401 argLen: 3, 23402 clobberFlags: true, 23403 call: true, 23404 reg: regInfo{ 23405 inputs: []inputInfo{ 23406 {0, 4096}, // R12 23407 {1, 2048}, // R11 23408 }, 23409 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23410 }, 23411 }, 23412 { 23413 name: "CALLinter", 23414 auxType: auxInt64, 23415 argLen: 2, 23416 clobberFlags: true, 23417 call: true, 23418 reg: regInfo{ 23419 inputs: []inputInfo{ 23420 {0, 4096}, // R12 23421 }, 23422 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23423 }, 23424 }, 23425 { 23426 name: "LoweredZero", 23427 auxType: auxInt64, 23428 argLen: 2, 23429 clobberFlags: true, 23430 faultOnNilArg0: true, 23431 reg: regInfo{ 23432 inputs: []inputInfo{ 23433 {0, 8}, // R3 23434 }, 23435 clobbers: 8, // R3 23436 }, 23437 }, 23438 { 23439 name: "LoweredMove", 23440 auxType: auxInt64, 23441 argLen: 3, 23442 clobberFlags: true, 23443 faultOnNilArg0: true, 23444 faultOnNilArg1: true, 23445 reg: regInfo{ 23446 inputs: []inputInfo{ 23447 {0, 8}, // R3 23448 {1, 16}, // R4 23449 }, 23450 clobbers: 1944, // R3 R4 R7 R8 R9 R10 23451 }, 23452 }, 23453 { 23454 name: "LoweredAtomicStore32", 23455 auxType: auxInt64, 23456 argLen: 3, 23457 faultOnNilArg0: true, 23458 hasSideEffects: true, 23459 reg: regInfo{ 23460 inputs: []inputInfo{ 23461 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23462 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23463 }, 23464 }, 23465 }, 23466 { 23467 name: "LoweredAtomicStore64", 23468 auxType: auxInt64, 23469 argLen: 3, 23470 faultOnNilArg0: true, 23471 hasSideEffects: true, 23472 reg: regInfo{ 23473 inputs: []inputInfo{ 23474 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23475 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23476 }, 23477 }, 23478 }, 23479 { 23480 name: "LoweredAtomicLoad32", 23481 auxType: auxInt64, 23482 argLen: 2, 23483 clobberFlags: true, 23484 faultOnNilArg0: true, 23485 reg: regInfo{ 23486 inputs: []inputInfo{ 23487 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23488 }, 23489 outputs: []outputInfo{ 23490 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23491 }, 23492 }, 23493 }, 23494 { 23495 name: "LoweredAtomicLoad64", 23496 auxType: auxInt64, 23497 argLen: 2, 23498 clobberFlags: true, 23499 faultOnNilArg0: true, 23500 reg: regInfo{ 23501 inputs: []inputInfo{ 23502 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23503 }, 23504 outputs: []outputInfo{ 23505 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23506 }, 23507 }, 23508 }, 23509 { 23510 name: "LoweredAtomicLoadPtr", 23511 auxType: auxInt64, 23512 argLen: 2, 23513 clobberFlags: true, 23514 faultOnNilArg0: true, 23515 reg: regInfo{ 23516 inputs: []inputInfo{ 23517 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23518 }, 23519 outputs: []outputInfo{ 23520 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23521 }, 23522 }, 23523 }, 23524 { 23525 name: "LoweredAtomicAdd32", 23526 argLen: 3, 23527 resultNotInArgs: true, 23528 clobberFlags: true, 23529 faultOnNilArg0: true, 23530 hasSideEffects: true, 23531 reg: regInfo{ 23532 inputs: []inputInfo{ 23533 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23534 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23535 }, 23536 outputs: []outputInfo{ 23537 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23538 }, 23539 }, 23540 }, 23541 { 23542 name: "LoweredAtomicAdd64", 23543 argLen: 3, 23544 resultNotInArgs: true, 23545 clobberFlags: true, 23546 faultOnNilArg0: true, 23547 hasSideEffects: true, 23548 reg: regInfo{ 23549 inputs: []inputInfo{ 23550 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23551 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23552 }, 23553 outputs: []outputInfo{ 23554 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23555 }, 23556 }, 23557 }, 23558 { 23559 name: "LoweredAtomicExchange32", 23560 argLen: 3, 23561 resultNotInArgs: true, 23562 clobberFlags: true, 23563 faultOnNilArg0: true, 23564 hasSideEffects: true, 23565 reg: regInfo{ 23566 inputs: []inputInfo{ 23567 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23568 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23569 }, 23570 outputs: []outputInfo{ 23571 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23572 }, 23573 }, 23574 }, 23575 { 23576 name: "LoweredAtomicExchange64", 23577 argLen: 3, 23578 resultNotInArgs: true, 23579 clobberFlags: true, 23580 faultOnNilArg0: true, 23581 hasSideEffects: true, 23582 reg: regInfo{ 23583 inputs: []inputInfo{ 23584 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23585 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23586 }, 23587 outputs: []outputInfo{ 23588 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23589 }, 23590 }, 23591 }, 23592 { 23593 name: "LoweredAtomicCas64", 23594 auxType: auxInt64, 23595 argLen: 4, 23596 resultNotInArgs: true, 23597 clobberFlags: true, 23598 faultOnNilArg0: true, 23599 hasSideEffects: true, 23600 reg: regInfo{ 23601 inputs: []inputInfo{ 23602 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23603 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23604 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23605 }, 23606 outputs: []outputInfo{ 23607 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23608 }, 23609 }, 23610 }, 23611 { 23612 name: "LoweredAtomicCas32", 23613 auxType: auxInt64, 23614 argLen: 4, 23615 resultNotInArgs: true, 23616 clobberFlags: true, 23617 faultOnNilArg0: true, 23618 hasSideEffects: true, 23619 reg: regInfo{ 23620 inputs: []inputInfo{ 23621 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23622 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23623 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23624 }, 23625 outputs: []outputInfo{ 23626 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23627 }, 23628 }, 23629 }, 23630 { 23631 name: "LoweredAtomicAnd8", 23632 argLen: 3, 23633 faultOnNilArg0: true, 23634 hasSideEffects: true, 23635 asm: ppc64.AAND, 23636 reg: regInfo{ 23637 inputs: []inputInfo{ 23638 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23639 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23640 }, 23641 }, 23642 }, 23643 { 23644 name: "LoweredAtomicOr8", 23645 argLen: 3, 23646 faultOnNilArg0: true, 23647 hasSideEffects: true, 23648 asm: ppc64.AOR, 23649 reg: regInfo{ 23650 inputs: []inputInfo{ 23651 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23652 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23653 }, 23654 }, 23655 }, 23656 { 23657 name: "LoweredWB", 23658 auxType: auxSym, 23659 argLen: 3, 23660 clobberFlags: true, 23661 symEffect: SymNone, 23662 reg: regInfo{ 23663 inputs: []inputInfo{ 23664 {0, 1048576}, // R20 23665 {1, 2097152}, // R21 23666 }, 23667 clobbers: 576460746931503104, // R16 R17 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23668 }, 23669 }, 23670 { 23671 name: "InvertFlags", 23672 argLen: 1, 23673 reg: regInfo{}, 23674 }, 23675 { 23676 name: "FlagEQ", 23677 argLen: 0, 23678 reg: regInfo{}, 23679 }, 23680 { 23681 name: "FlagLT", 23682 argLen: 0, 23683 reg: regInfo{}, 23684 }, 23685 { 23686 name: "FlagGT", 23687 argLen: 0, 23688 reg: regInfo{}, 23689 }, 23690 23691 { 23692 name: "FADDS", 23693 argLen: 2, 23694 commutative: true, 23695 resultInArg0: true, 23696 clobberFlags: true, 23697 asm: s390x.AFADDS, 23698 reg: regInfo{ 23699 inputs: []inputInfo{ 23700 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23701 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23702 }, 23703 outputs: []outputInfo{ 23704 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23705 }, 23706 }, 23707 }, 23708 { 23709 name: "FADD", 23710 argLen: 2, 23711 commutative: true, 23712 resultInArg0: true, 23713 clobberFlags: true, 23714 asm: s390x.AFADD, 23715 reg: regInfo{ 23716 inputs: []inputInfo{ 23717 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23718 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23719 }, 23720 outputs: []outputInfo{ 23721 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23722 }, 23723 }, 23724 }, 23725 { 23726 name: "FSUBS", 23727 argLen: 2, 23728 resultInArg0: true, 23729 clobberFlags: true, 23730 asm: s390x.AFSUBS, 23731 reg: regInfo{ 23732 inputs: []inputInfo{ 23733 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23734 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23735 }, 23736 outputs: []outputInfo{ 23737 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23738 }, 23739 }, 23740 }, 23741 { 23742 name: "FSUB", 23743 argLen: 2, 23744 resultInArg0: true, 23745 clobberFlags: true, 23746 asm: s390x.AFSUB, 23747 reg: regInfo{ 23748 inputs: []inputInfo{ 23749 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23750 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23751 }, 23752 outputs: []outputInfo{ 23753 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23754 }, 23755 }, 23756 }, 23757 { 23758 name: "FMULS", 23759 argLen: 2, 23760 commutative: true, 23761 resultInArg0: true, 23762 asm: s390x.AFMULS, 23763 reg: regInfo{ 23764 inputs: []inputInfo{ 23765 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23766 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23767 }, 23768 outputs: []outputInfo{ 23769 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23770 }, 23771 }, 23772 }, 23773 { 23774 name: "FMUL", 23775 argLen: 2, 23776 commutative: true, 23777 resultInArg0: true, 23778 asm: s390x.AFMUL, 23779 reg: regInfo{ 23780 inputs: []inputInfo{ 23781 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23782 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23783 }, 23784 outputs: []outputInfo{ 23785 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23786 }, 23787 }, 23788 }, 23789 { 23790 name: "FDIVS", 23791 argLen: 2, 23792 resultInArg0: true, 23793 asm: s390x.AFDIVS, 23794 reg: regInfo{ 23795 inputs: []inputInfo{ 23796 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23797 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23798 }, 23799 outputs: []outputInfo{ 23800 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23801 }, 23802 }, 23803 }, 23804 { 23805 name: "FDIV", 23806 argLen: 2, 23807 resultInArg0: true, 23808 asm: s390x.AFDIV, 23809 reg: regInfo{ 23810 inputs: []inputInfo{ 23811 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23812 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23813 }, 23814 outputs: []outputInfo{ 23815 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23816 }, 23817 }, 23818 }, 23819 { 23820 name: "FNEGS", 23821 argLen: 1, 23822 clobberFlags: true, 23823 asm: s390x.AFNEGS, 23824 reg: regInfo{ 23825 inputs: []inputInfo{ 23826 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23827 }, 23828 outputs: []outputInfo{ 23829 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23830 }, 23831 }, 23832 }, 23833 { 23834 name: "FNEG", 23835 argLen: 1, 23836 clobberFlags: true, 23837 asm: s390x.AFNEG, 23838 reg: regInfo{ 23839 inputs: []inputInfo{ 23840 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23841 }, 23842 outputs: []outputInfo{ 23843 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23844 }, 23845 }, 23846 }, 23847 { 23848 name: "FMADDS", 23849 argLen: 3, 23850 resultInArg0: true, 23851 asm: s390x.AFMADDS, 23852 reg: regInfo{ 23853 inputs: []inputInfo{ 23854 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23855 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23856 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23857 }, 23858 outputs: []outputInfo{ 23859 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23860 }, 23861 }, 23862 }, 23863 { 23864 name: "FMADD", 23865 argLen: 3, 23866 resultInArg0: true, 23867 asm: s390x.AFMADD, 23868 reg: regInfo{ 23869 inputs: []inputInfo{ 23870 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23871 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23872 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23873 }, 23874 outputs: []outputInfo{ 23875 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23876 }, 23877 }, 23878 }, 23879 { 23880 name: "FMSUBS", 23881 argLen: 3, 23882 resultInArg0: true, 23883 asm: s390x.AFMSUBS, 23884 reg: regInfo{ 23885 inputs: []inputInfo{ 23886 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23887 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23888 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23889 }, 23890 outputs: []outputInfo{ 23891 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23892 }, 23893 }, 23894 }, 23895 { 23896 name: "FMSUB", 23897 argLen: 3, 23898 resultInArg0: true, 23899 asm: s390x.AFMSUB, 23900 reg: regInfo{ 23901 inputs: []inputInfo{ 23902 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23903 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23904 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23905 }, 23906 outputs: []outputInfo{ 23907 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23908 }, 23909 }, 23910 }, 23911 { 23912 name: "LPDFR", 23913 argLen: 1, 23914 asm: s390x.ALPDFR, 23915 reg: regInfo{ 23916 inputs: []inputInfo{ 23917 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23918 }, 23919 outputs: []outputInfo{ 23920 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23921 }, 23922 }, 23923 }, 23924 { 23925 name: "LNDFR", 23926 argLen: 1, 23927 asm: s390x.ALNDFR, 23928 reg: regInfo{ 23929 inputs: []inputInfo{ 23930 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23931 }, 23932 outputs: []outputInfo{ 23933 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23934 }, 23935 }, 23936 }, 23937 { 23938 name: "CPSDR", 23939 argLen: 2, 23940 asm: s390x.ACPSDR, 23941 reg: regInfo{ 23942 inputs: []inputInfo{ 23943 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23944 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23945 }, 23946 outputs: []outputInfo{ 23947 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23948 }, 23949 }, 23950 }, 23951 { 23952 name: "FIDBR", 23953 auxType: auxInt8, 23954 argLen: 1, 23955 asm: s390x.AFIDBR, 23956 reg: regInfo{ 23957 inputs: []inputInfo{ 23958 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23959 }, 23960 outputs: []outputInfo{ 23961 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23962 }, 23963 }, 23964 }, 23965 { 23966 name: "FMOVSload", 23967 auxType: auxSymOff, 23968 argLen: 2, 23969 faultOnNilArg0: true, 23970 symEffect: SymRead, 23971 asm: s390x.AFMOVS, 23972 reg: regInfo{ 23973 inputs: []inputInfo{ 23974 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 23975 }, 23976 outputs: []outputInfo{ 23977 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23978 }, 23979 }, 23980 }, 23981 { 23982 name: "FMOVDload", 23983 auxType: auxSymOff, 23984 argLen: 2, 23985 faultOnNilArg0: true, 23986 symEffect: SymRead, 23987 asm: s390x.AFMOVD, 23988 reg: regInfo{ 23989 inputs: []inputInfo{ 23990 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 23991 }, 23992 outputs: []outputInfo{ 23993 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23994 }, 23995 }, 23996 }, 23997 { 23998 name: "FMOVSconst", 23999 auxType: auxFloat32, 24000 argLen: 0, 24001 rematerializeable: true, 24002 asm: s390x.AFMOVS, 24003 reg: regInfo{ 24004 outputs: []outputInfo{ 24005 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24006 }, 24007 }, 24008 }, 24009 { 24010 name: "FMOVDconst", 24011 auxType: auxFloat64, 24012 argLen: 0, 24013 rematerializeable: true, 24014 asm: s390x.AFMOVD, 24015 reg: regInfo{ 24016 outputs: []outputInfo{ 24017 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24018 }, 24019 }, 24020 }, 24021 { 24022 name: "FMOVSloadidx", 24023 auxType: auxSymOff, 24024 argLen: 3, 24025 symEffect: SymRead, 24026 asm: s390x.AFMOVS, 24027 reg: regInfo{ 24028 inputs: []inputInfo{ 24029 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24030 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24031 }, 24032 outputs: []outputInfo{ 24033 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24034 }, 24035 }, 24036 }, 24037 { 24038 name: "FMOVDloadidx", 24039 auxType: auxSymOff, 24040 argLen: 3, 24041 symEffect: SymRead, 24042 asm: s390x.AFMOVD, 24043 reg: regInfo{ 24044 inputs: []inputInfo{ 24045 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24046 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24047 }, 24048 outputs: []outputInfo{ 24049 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24050 }, 24051 }, 24052 }, 24053 { 24054 name: "FMOVSstore", 24055 auxType: auxSymOff, 24056 argLen: 3, 24057 faultOnNilArg0: true, 24058 symEffect: SymWrite, 24059 asm: s390x.AFMOVS, 24060 reg: regInfo{ 24061 inputs: []inputInfo{ 24062 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 24063 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24064 }, 24065 }, 24066 }, 24067 { 24068 name: "FMOVDstore", 24069 auxType: auxSymOff, 24070 argLen: 3, 24071 faultOnNilArg0: true, 24072 symEffect: SymWrite, 24073 asm: s390x.AFMOVD, 24074 reg: regInfo{ 24075 inputs: []inputInfo{ 24076 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 24077 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24078 }, 24079 }, 24080 }, 24081 { 24082 name: "FMOVSstoreidx", 24083 auxType: auxSymOff, 24084 argLen: 4, 24085 symEffect: SymWrite, 24086 asm: s390x.AFMOVS, 24087 reg: regInfo{ 24088 inputs: []inputInfo{ 24089 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24090 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24091 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24092 }, 24093 }, 24094 }, 24095 { 24096 name: "FMOVDstoreidx", 24097 auxType: auxSymOff, 24098 argLen: 4, 24099 symEffect: SymWrite, 24100 asm: s390x.AFMOVD, 24101 reg: regInfo{ 24102 inputs: []inputInfo{ 24103 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24104 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24105 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24106 }, 24107 }, 24108 }, 24109 { 24110 name: "ADD", 24111 argLen: 2, 24112 commutative: true, 24113 clobberFlags: true, 24114 asm: s390x.AADD, 24115 reg: regInfo{ 24116 inputs: []inputInfo{ 24117 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24118 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24119 }, 24120 outputs: []outputInfo{ 24121 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24122 }, 24123 }, 24124 }, 24125 { 24126 name: "ADDW", 24127 argLen: 2, 24128 commutative: true, 24129 clobberFlags: true, 24130 asm: s390x.AADDW, 24131 reg: regInfo{ 24132 inputs: []inputInfo{ 24133 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24134 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24135 }, 24136 outputs: []outputInfo{ 24137 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24138 }, 24139 }, 24140 }, 24141 { 24142 name: "ADDconst", 24143 auxType: auxInt32, 24144 argLen: 1, 24145 clobberFlags: true, 24146 asm: s390x.AADD, 24147 reg: regInfo{ 24148 inputs: []inputInfo{ 24149 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24150 }, 24151 outputs: []outputInfo{ 24152 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24153 }, 24154 }, 24155 }, 24156 { 24157 name: "ADDWconst", 24158 auxType: auxInt32, 24159 argLen: 1, 24160 clobberFlags: true, 24161 asm: s390x.AADDW, 24162 reg: regInfo{ 24163 inputs: []inputInfo{ 24164 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24165 }, 24166 outputs: []outputInfo{ 24167 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24168 }, 24169 }, 24170 }, 24171 { 24172 name: "ADDload", 24173 auxType: auxSymOff, 24174 argLen: 3, 24175 resultInArg0: true, 24176 clobberFlags: true, 24177 faultOnNilArg1: true, 24178 symEffect: SymRead, 24179 asm: s390x.AADD, 24180 reg: regInfo{ 24181 inputs: []inputInfo{ 24182 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24183 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24184 }, 24185 outputs: []outputInfo{ 24186 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24187 }, 24188 }, 24189 }, 24190 { 24191 name: "ADDWload", 24192 auxType: auxSymOff, 24193 argLen: 3, 24194 resultInArg0: true, 24195 clobberFlags: true, 24196 faultOnNilArg1: true, 24197 symEffect: SymRead, 24198 asm: s390x.AADDW, 24199 reg: regInfo{ 24200 inputs: []inputInfo{ 24201 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24202 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24203 }, 24204 outputs: []outputInfo{ 24205 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24206 }, 24207 }, 24208 }, 24209 { 24210 name: "SUB", 24211 argLen: 2, 24212 clobberFlags: true, 24213 asm: s390x.ASUB, 24214 reg: regInfo{ 24215 inputs: []inputInfo{ 24216 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24217 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24218 }, 24219 outputs: []outputInfo{ 24220 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24221 }, 24222 }, 24223 }, 24224 { 24225 name: "SUBW", 24226 argLen: 2, 24227 clobberFlags: true, 24228 asm: s390x.ASUBW, 24229 reg: regInfo{ 24230 inputs: []inputInfo{ 24231 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24232 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24233 }, 24234 outputs: []outputInfo{ 24235 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24236 }, 24237 }, 24238 }, 24239 { 24240 name: "SUBconst", 24241 auxType: auxInt32, 24242 argLen: 1, 24243 resultInArg0: true, 24244 clobberFlags: true, 24245 asm: s390x.ASUB, 24246 reg: regInfo{ 24247 inputs: []inputInfo{ 24248 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24249 }, 24250 outputs: []outputInfo{ 24251 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24252 }, 24253 }, 24254 }, 24255 { 24256 name: "SUBWconst", 24257 auxType: auxInt32, 24258 argLen: 1, 24259 resultInArg0: true, 24260 clobberFlags: true, 24261 asm: s390x.ASUBW, 24262 reg: regInfo{ 24263 inputs: []inputInfo{ 24264 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24265 }, 24266 outputs: []outputInfo{ 24267 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24268 }, 24269 }, 24270 }, 24271 { 24272 name: "SUBload", 24273 auxType: auxSymOff, 24274 argLen: 3, 24275 resultInArg0: true, 24276 clobberFlags: true, 24277 faultOnNilArg1: true, 24278 symEffect: SymRead, 24279 asm: s390x.ASUB, 24280 reg: regInfo{ 24281 inputs: []inputInfo{ 24282 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24283 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24284 }, 24285 outputs: []outputInfo{ 24286 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24287 }, 24288 }, 24289 }, 24290 { 24291 name: "SUBWload", 24292 auxType: auxSymOff, 24293 argLen: 3, 24294 resultInArg0: true, 24295 clobberFlags: true, 24296 faultOnNilArg1: true, 24297 symEffect: SymRead, 24298 asm: s390x.ASUBW, 24299 reg: regInfo{ 24300 inputs: []inputInfo{ 24301 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24302 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24303 }, 24304 outputs: []outputInfo{ 24305 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24306 }, 24307 }, 24308 }, 24309 { 24310 name: "MULLD", 24311 argLen: 2, 24312 commutative: true, 24313 resultInArg0: true, 24314 clobberFlags: true, 24315 asm: s390x.AMULLD, 24316 reg: regInfo{ 24317 inputs: []inputInfo{ 24318 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24319 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24320 }, 24321 outputs: []outputInfo{ 24322 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24323 }, 24324 }, 24325 }, 24326 { 24327 name: "MULLW", 24328 argLen: 2, 24329 commutative: true, 24330 resultInArg0: true, 24331 clobberFlags: true, 24332 asm: s390x.AMULLW, 24333 reg: regInfo{ 24334 inputs: []inputInfo{ 24335 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24336 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24337 }, 24338 outputs: []outputInfo{ 24339 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24340 }, 24341 }, 24342 }, 24343 { 24344 name: "MULLDconst", 24345 auxType: auxInt32, 24346 argLen: 1, 24347 resultInArg0: true, 24348 clobberFlags: true, 24349 asm: s390x.AMULLD, 24350 reg: regInfo{ 24351 inputs: []inputInfo{ 24352 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24353 }, 24354 outputs: []outputInfo{ 24355 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24356 }, 24357 }, 24358 }, 24359 { 24360 name: "MULLWconst", 24361 auxType: auxInt32, 24362 argLen: 1, 24363 resultInArg0: true, 24364 clobberFlags: true, 24365 asm: s390x.AMULLW, 24366 reg: regInfo{ 24367 inputs: []inputInfo{ 24368 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24369 }, 24370 outputs: []outputInfo{ 24371 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24372 }, 24373 }, 24374 }, 24375 { 24376 name: "MULLDload", 24377 auxType: auxSymOff, 24378 argLen: 3, 24379 resultInArg0: true, 24380 clobberFlags: true, 24381 faultOnNilArg1: true, 24382 symEffect: SymRead, 24383 asm: s390x.AMULLD, 24384 reg: regInfo{ 24385 inputs: []inputInfo{ 24386 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24387 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24388 }, 24389 outputs: []outputInfo{ 24390 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24391 }, 24392 }, 24393 }, 24394 { 24395 name: "MULLWload", 24396 auxType: auxSymOff, 24397 argLen: 3, 24398 resultInArg0: true, 24399 clobberFlags: true, 24400 faultOnNilArg1: true, 24401 symEffect: SymRead, 24402 asm: s390x.AMULLW, 24403 reg: regInfo{ 24404 inputs: []inputInfo{ 24405 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24406 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24407 }, 24408 outputs: []outputInfo{ 24409 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24410 }, 24411 }, 24412 }, 24413 { 24414 name: "MULHD", 24415 argLen: 2, 24416 commutative: true, 24417 resultInArg0: true, 24418 clobberFlags: true, 24419 asm: s390x.AMULHD, 24420 reg: regInfo{ 24421 inputs: []inputInfo{ 24422 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24423 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24424 }, 24425 clobbers: 2048, // R11 24426 outputs: []outputInfo{ 24427 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24428 }, 24429 }, 24430 }, 24431 { 24432 name: "MULHDU", 24433 argLen: 2, 24434 commutative: true, 24435 resultInArg0: true, 24436 clobberFlags: true, 24437 asm: s390x.AMULHDU, 24438 reg: regInfo{ 24439 inputs: []inputInfo{ 24440 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24441 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24442 }, 24443 clobbers: 2048, // R11 24444 outputs: []outputInfo{ 24445 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24446 }, 24447 }, 24448 }, 24449 { 24450 name: "DIVD", 24451 argLen: 2, 24452 resultInArg0: true, 24453 clobberFlags: true, 24454 asm: s390x.ADIVD, 24455 reg: regInfo{ 24456 inputs: []inputInfo{ 24457 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24458 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24459 }, 24460 clobbers: 2048, // R11 24461 outputs: []outputInfo{ 24462 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24463 }, 24464 }, 24465 }, 24466 { 24467 name: "DIVW", 24468 argLen: 2, 24469 resultInArg0: true, 24470 clobberFlags: true, 24471 asm: s390x.ADIVW, 24472 reg: regInfo{ 24473 inputs: []inputInfo{ 24474 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24475 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24476 }, 24477 clobbers: 2048, // R11 24478 outputs: []outputInfo{ 24479 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24480 }, 24481 }, 24482 }, 24483 { 24484 name: "DIVDU", 24485 argLen: 2, 24486 resultInArg0: true, 24487 clobberFlags: true, 24488 asm: s390x.ADIVDU, 24489 reg: regInfo{ 24490 inputs: []inputInfo{ 24491 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24492 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24493 }, 24494 clobbers: 2048, // R11 24495 outputs: []outputInfo{ 24496 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24497 }, 24498 }, 24499 }, 24500 { 24501 name: "DIVWU", 24502 argLen: 2, 24503 resultInArg0: true, 24504 clobberFlags: true, 24505 asm: s390x.ADIVWU, 24506 reg: regInfo{ 24507 inputs: []inputInfo{ 24508 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24509 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24510 }, 24511 clobbers: 2048, // R11 24512 outputs: []outputInfo{ 24513 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24514 }, 24515 }, 24516 }, 24517 { 24518 name: "MODD", 24519 argLen: 2, 24520 resultInArg0: true, 24521 clobberFlags: true, 24522 asm: s390x.AMODD, 24523 reg: regInfo{ 24524 inputs: []inputInfo{ 24525 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24526 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24527 }, 24528 clobbers: 2048, // R11 24529 outputs: []outputInfo{ 24530 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24531 }, 24532 }, 24533 }, 24534 { 24535 name: "MODW", 24536 argLen: 2, 24537 resultInArg0: true, 24538 clobberFlags: true, 24539 asm: s390x.AMODW, 24540 reg: regInfo{ 24541 inputs: []inputInfo{ 24542 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24543 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24544 }, 24545 clobbers: 2048, // R11 24546 outputs: []outputInfo{ 24547 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24548 }, 24549 }, 24550 }, 24551 { 24552 name: "MODDU", 24553 argLen: 2, 24554 resultInArg0: true, 24555 clobberFlags: true, 24556 asm: s390x.AMODDU, 24557 reg: regInfo{ 24558 inputs: []inputInfo{ 24559 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24560 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24561 }, 24562 clobbers: 2048, // R11 24563 outputs: []outputInfo{ 24564 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24565 }, 24566 }, 24567 }, 24568 { 24569 name: "MODWU", 24570 argLen: 2, 24571 resultInArg0: true, 24572 clobberFlags: true, 24573 asm: s390x.AMODWU, 24574 reg: regInfo{ 24575 inputs: []inputInfo{ 24576 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24577 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24578 }, 24579 clobbers: 2048, // R11 24580 outputs: []outputInfo{ 24581 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24582 }, 24583 }, 24584 }, 24585 { 24586 name: "AND", 24587 argLen: 2, 24588 commutative: true, 24589 clobberFlags: true, 24590 asm: s390x.AAND, 24591 reg: regInfo{ 24592 inputs: []inputInfo{ 24593 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24594 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24595 }, 24596 outputs: []outputInfo{ 24597 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24598 }, 24599 }, 24600 }, 24601 { 24602 name: "ANDW", 24603 argLen: 2, 24604 commutative: true, 24605 clobberFlags: true, 24606 asm: s390x.AANDW, 24607 reg: regInfo{ 24608 inputs: []inputInfo{ 24609 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24610 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24611 }, 24612 outputs: []outputInfo{ 24613 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24614 }, 24615 }, 24616 }, 24617 { 24618 name: "ANDconst", 24619 auxType: auxInt64, 24620 argLen: 1, 24621 resultInArg0: true, 24622 clobberFlags: true, 24623 asm: s390x.AAND, 24624 reg: regInfo{ 24625 inputs: []inputInfo{ 24626 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24627 }, 24628 outputs: []outputInfo{ 24629 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24630 }, 24631 }, 24632 }, 24633 { 24634 name: "ANDWconst", 24635 auxType: auxInt32, 24636 argLen: 1, 24637 resultInArg0: true, 24638 clobberFlags: true, 24639 asm: s390x.AANDW, 24640 reg: regInfo{ 24641 inputs: []inputInfo{ 24642 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24643 }, 24644 outputs: []outputInfo{ 24645 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24646 }, 24647 }, 24648 }, 24649 { 24650 name: "ANDload", 24651 auxType: auxSymOff, 24652 argLen: 3, 24653 resultInArg0: true, 24654 clobberFlags: true, 24655 faultOnNilArg1: true, 24656 symEffect: SymRead, 24657 asm: s390x.AAND, 24658 reg: regInfo{ 24659 inputs: []inputInfo{ 24660 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24661 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24662 }, 24663 outputs: []outputInfo{ 24664 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24665 }, 24666 }, 24667 }, 24668 { 24669 name: "ANDWload", 24670 auxType: auxSymOff, 24671 argLen: 3, 24672 resultInArg0: true, 24673 clobberFlags: true, 24674 faultOnNilArg1: true, 24675 symEffect: SymRead, 24676 asm: s390x.AANDW, 24677 reg: regInfo{ 24678 inputs: []inputInfo{ 24679 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24680 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24681 }, 24682 outputs: []outputInfo{ 24683 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24684 }, 24685 }, 24686 }, 24687 { 24688 name: "OR", 24689 argLen: 2, 24690 commutative: true, 24691 clobberFlags: true, 24692 asm: s390x.AOR, 24693 reg: regInfo{ 24694 inputs: []inputInfo{ 24695 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24696 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24697 }, 24698 outputs: []outputInfo{ 24699 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24700 }, 24701 }, 24702 }, 24703 { 24704 name: "ORW", 24705 argLen: 2, 24706 commutative: true, 24707 clobberFlags: true, 24708 asm: s390x.AORW, 24709 reg: regInfo{ 24710 inputs: []inputInfo{ 24711 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24712 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24713 }, 24714 outputs: []outputInfo{ 24715 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24716 }, 24717 }, 24718 }, 24719 { 24720 name: "ORconst", 24721 auxType: auxInt64, 24722 argLen: 1, 24723 resultInArg0: true, 24724 clobberFlags: true, 24725 asm: s390x.AOR, 24726 reg: regInfo{ 24727 inputs: []inputInfo{ 24728 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24729 }, 24730 outputs: []outputInfo{ 24731 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24732 }, 24733 }, 24734 }, 24735 { 24736 name: "ORWconst", 24737 auxType: auxInt32, 24738 argLen: 1, 24739 resultInArg0: true, 24740 clobberFlags: true, 24741 asm: s390x.AORW, 24742 reg: regInfo{ 24743 inputs: []inputInfo{ 24744 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24745 }, 24746 outputs: []outputInfo{ 24747 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24748 }, 24749 }, 24750 }, 24751 { 24752 name: "ORload", 24753 auxType: auxSymOff, 24754 argLen: 3, 24755 resultInArg0: true, 24756 clobberFlags: true, 24757 faultOnNilArg1: true, 24758 symEffect: SymRead, 24759 asm: s390x.AOR, 24760 reg: regInfo{ 24761 inputs: []inputInfo{ 24762 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24763 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24764 }, 24765 outputs: []outputInfo{ 24766 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24767 }, 24768 }, 24769 }, 24770 { 24771 name: "ORWload", 24772 auxType: auxSymOff, 24773 argLen: 3, 24774 resultInArg0: true, 24775 clobberFlags: true, 24776 faultOnNilArg1: true, 24777 symEffect: SymRead, 24778 asm: s390x.AORW, 24779 reg: regInfo{ 24780 inputs: []inputInfo{ 24781 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24782 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24783 }, 24784 outputs: []outputInfo{ 24785 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24786 }, 24787 }, 24788 }, 24789 { 24790 name: "XOR", 24791 argLen: 2, 24792 commutative: true, 24793 clobberFlags: true, 24794 asm: s390x.AXOR, 24795 reg: regInfo{ 24796 inputs: []inputInfo{ 24797 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24798 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24799 }, 24800 outputs: []outputInfo{ 24801 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24802 }, 24803 }, 24804 }, 24805 { 24806 name: "XORW", 24807 argLen: 2, 24808 commutative: true, 24809 clobberFlags: true, 24810 asm: s390x.AXORW, 24811 reg: regInfo{ 24812 inputs: []inputInfo{ 24813 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24814 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24815 }, 24816 outputs: []outputInfo{ 24817 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24818 }, 24819 }, 24820 }, 24821 { 24822 name: "XORconst", 24823 auxType: auxInt64, 24824 argLen: 1, 24825 resultInArg0: true, 24826 clobberFlags: true, 24827 asm: s390x.AXOR, 24828 reg: regInfo{ 24829 inputs: []inputInfo{ 24830 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24831 }, 24832 outputs: []outputInfo{ 24833 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24834 }, 24835 }, 24836 }, 24837 { 24838 name: "XORWconst", 24839 auxType: auxInt32, 24840 argLen: 1, 24841 resultInArg0: true, 24842 clobberFlags: true, 24843 asm: s390x.AXORW, 24844 reg: regInfo{ 24845 inputs: []inputInfo{ 24846 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24847 }, 24848 outputs: []outputInfo{ 24849 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24850 }, 24851 }, 24852 }, 24853 { 24854 name: "XORload", 24855 auxType: auxSymOff, 24856 argLen: 3, 24857 resultInArg0: true, 24858 clobberFlags: true, 24859 faultOnNilArg1: true, 24860 symEffect: SymRead, 24861 asm: s390x.AXOR, 24862 reg: regInfo{ 24863 inputs: []inputInfo{ 24864 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24865 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24866 }, 24867 outputs: []outputInfo{ 24868 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24869 }, 24870 }, 24871 }, 24872 { 24873 name: "XORWload", 24874 auxType: auxSymOff, 24875 argLen: 3, 24876 resultInArg0: true, 24877 clobberFlags: true, 24878 faultOnNilArg1: true, 24879 symEffect: SymRead, 24880 asm: s390x.AXORW, 24881 reg: regInfo{ 24882 inputs: []inputInfo{ 24883 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24884 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24885 }, 24886 outputs: []outputInfo{ 24887 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24888 }, 24889 }, 24890 }, 24891 { 24892 name: "CMP", 24893 argLen: 2, 24894 asm: s390x.ACMP, 24895 reg: regInfo{ 24896 inputs: []inputInfo{ 24897 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24898 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24899 }, 24900 }, 24901 }, 24902 { 24903 name: "CMPW", 24904 argLen: 2, 24905 asm: s390x.ACMPW, 24906 reg: regInfo{ 24907 inputs: []inputInfo{ 24908 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24909 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24910 }, 24911 }, 24912 }, 24913 { 24914 name: "CMPU", 24915 argLen: 2, 24916 asm: s390x.ACMPU, 24917 reg: regInfo{ 24918 inputs: []inputInfo{ 24919 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24920 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24921 }, 24922 }, 24923 }, 24924 { 24925 name: "CMPWU", 24926 argLen: 2, 24927 asm: s390x.ACMPWU, 24928 reg: regInfo{ 24929 inputs: []inputInfo{ 24930 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24931 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24932 }, 24933 }, 24934 }, 24935 { 24936 name: "CMPconst", 24937 auxType: auxInt32, 24938 argLen: 1, 24939 asm: s390x.ACMP, 24940 reg: regInfo{ 24941 inputs: []inputInfo{ 24942 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24943 }, 24944 }, 24945 }, 24946 { 24947 name: "CMPWconst", 24948 auxType: auxInt32, 24949 argLen: 1, 24950 asm: s390x.ACMPW, 24951 reg: regInfo{ 24952 inputs: []inputInfo{ 24953 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24954 }, 24955 }, 24956 }, 24957 { 24958 name: "CMPUconst", 24959 auxType: auxInt32, 24960 argLen: 1, 24961 asm: s390x.ACMPU, 24962 reg: regInfo{ 24963 inputs: []inputInfo{ 24964 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24965 }, 24966 }, 24967 }, 24968 { 24969 name: "CMPWUconst", 24970 auxType: auxInt32, 24971 argLen: 1, 24972 asm: s390x.ACMPWU, 24973 reg: regInfo{ 24974 inputs: []inputInfo{ 24975 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24976 }, 24977 }, 24978 }, 24979 { 24980 name: "FCMPS", 24981 argLen: 2, 24982 asm: s390x.ACEBR, 24983 reg: regInfo{ 24984 inputs: []inputInfo{ 24985 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24986 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24987 }, 24988 }, 24989 }, 24990 { 24991 name: "FCMP", 24992 argLen: 2, 24993 asm: s390x.AFCMPU, 24994 reg: regInfo{ 24995 inputs: []inputInfo{ 24996 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24997 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24998 }, 24999 }, 25000 }, 25001 { 25002 name: "SLD", 25003 argLen: 2, 25004 asm: s390x.ASLD, 25005 reg: regInfo{ 25006 inputs: []inputInfo{ 25007 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25008 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25009 }, 25010 outputs: []outputInfo{ 25011 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25012 }, 25013 }, 25014 }, 25015 { 25016 name: "SLW", 25017 argLen: 2, 25018 asm: s390x.ASLW, 25019 reg: regInfo{ 25020 inputs: []inputInfo{ 25021 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25022 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25023 }, 25024 outputs: []outputInfo{ 25025 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25026 }, 25027 }, 25028 }, 25029 { 25030 name: "SLDconst", 25031 auxType: auxInt8, 25032 argLen: 1, 25033 asm: s390x.ASLD, 25034 reg: regInfo{ 25035 inputs: []inputInfo{ 25036 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25037 }, 25038 outputs: []outputInfo{ 25039 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25040 }, 25041 }, 25042 }, 25043 { 25044 name: "SLWconst", 25045 auxType: auxInt8, 25046 argLen: 1, 25047 asm: s390x.ASLW, 25048 reg: regInfo{ 25049 inputs: []inputInfo{ 25050 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25051 }, 25052 outputs: []outputInfo{ 25053 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25054 }, 25055 }, 25056 }, 25057 { 25058 name: "SRD", 25059 argLen: 2, 25060 asm: s390x.ASRD, 25061 reg: regInfo{ 25062 inputs: []inputInfo{ 25063 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25064 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25065 }, 25066 outputs: []outputInfo{ 25067 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25068 }, 25069 }, 25070 }, 25071 { 25072 name: "SRW", 25073 argLen: 2, 25074 asm: s390x.ASRW, 25075 reg: regInfo{ 25076 inputs: []inputInfo{ 25077 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25078 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25079 }, 25080 outputs: []outputInfo{ 25081 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25082 }, 25083 }, 25084 }, 25085 { 25086 name: "SRDconst", 25087 auxType: auxInt8, 25088 argLen: 1, 25089 asm: s390x.ASRD, 25090 reg: regInfo{ 25091 inputs: []inputInfo{ 25092 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25093 }, 25094 outputs: []outputInfo{ 25095 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25096 }, 25097 }, 25098 }, 25099 { 25100 name: "SRWconst", 25101 auxType: auxInt8, 25102 argLen: 1, 25103 asm: s390x.ASRW, 25104 reg: regInfo{ 25105 inputs: []inputInfo{ 25106 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25107 }, 25108 outputs: []outputInfo{ 25109 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25110 }, 25111 }, 25112 }, 25113 { 25114 name: "SRAD", 25115 argLen: 2, 25116 clobberFlags: true, 25117 asm: s390x.ASRAD, 25118 reg: regInfo{ 25119 inputs: []inputInfo{ 25120 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25121 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25122 }, 25123 outputs: []outputInfo{ 25124 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25125 }, 25126 }, 25127 }, 25128 { 25129 name: "SRAW", 25130 argLen: 2, 25131 clobberFlags: true, 25132 asm: s390x.ASRAW, 25133 reg: regInfo{ 25134 inputs: []inputInfo{ 25135 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25136 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25137 }, 25138 outputs: []outputInfo{ 25139 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25140 }, 25141 }, 25142 }, 25143 { 25144 name: "SRADconst", 25145 auxType: auxInt8, 25146 argLen: 1, 25147 clobberFlags: true, 25148 asm: s390x.ASRAD, 25149 reg: regInfo{ 25150 inputs: []inputInfo{ 25151 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25152 }, 25153 outputs: []outputInfo{ 25154 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25155 }, 25156 }, 25157 }, 25158 { 25159 name: "SRAWconst", 25160 auxType: auxInt8, 25161 argLen: 1, 25162 clobberFlags: true, 25163 asm: s390x.ASRAW, 25164 reg: regInfo{ 25165 inputs: []inputInfo{ 25166 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25167 }, 25168 outputs: []outputInfo{ 25169 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25170 }, 25171 }, 25172 }, 25173 { 25174 name: "RLLG", 25175 argLen: 2, 25176 asm: s390x.ARLLG, 25177 reg: regInfo{ 25178 inputs: []inputInfo{ 25179 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25180 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25181 }, 25182 outputs: []outputInfo{ 25183 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25184 }, 25185 }, 25186 }, 25187 { 25188 name: "RLL", 25189 argLen: 2, 25190 asm: s390x.ARLL, 25191 reg: regInfo{ 25192 inputs: []inputInfo{ 25193 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25194 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25195 }, 25196 outputs: []outputInfo{ 25197 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25198 }, 25199 }, 25200 }, 25201 { 25202 name: "RLLGconst", 25203 auxType: auxInt8, 25204 argLen: 1, 25205 asm: s390x.ARLLG, 25206 reg: regInfo{ 25207 inputs: []inputInfo{ 25208 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25209 }, 25210 outputs: []outputInfo{ 25211 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25212 }, 25213 }, 25214 }, 25215 { 25216 name: "RLLconst", 25217 auxType: auxInt8, 25218 argLen: 1, 25219 asm: s390x.ARLL, 25220 reg: regInfo{ 25221 inputs: []inputInfo{ 25222 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25223 }, 25224 outputs: []outputInfo{ 25225 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25226 }, 25227 }, 25228 }, 25229 { 25230 name: "NEG", 25231 argLen: 1, 25232 clobberFlags: true, 25233 asm: s390x.ANEG, 25234 reg: regInfo{ 25235 inputs: []inputInfo{ 25236 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25237 }, 25238 outputs: []outputInfo{ 25239 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25240 }, 25241 }, 25242 }, 25243 { 25244 name: "NEGW", 25245 argLen: 1, 25246 clobberFlags: true, 25247 asm: s390x.ANEGW, 25248 reg: regInfo{ 25249 inputs: []inputInfo{ 25250 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25251 }, 25252 outputs: []outputInfo{ 25253 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25254 }, 25255 }, 25256 }, 25257 { 25258 name: "NOT", 25259 argLen: 1, 25260 resultInArg0: true, 25261 clobberFlags: true, 25262 reg: regInfo{ 25263 inputs: []inputInfo{ 25264 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25265 }, 25266 outputs: []outputInfo{ 25267 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25268 }, 25269 }, 25270 }, 25271 { 25272 name: "NOTW", 25273 argLen: 1, 25274 resultInArg0: true, 25275 clobberFlags: true, 25276 reg: regInfo{ 25277 inputs: []inputInfo{ 25278 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25279 }, 25280 outputs: []outputInfo{ 25281 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25282 }, 25283 }, 25284 }, 25285 { 25286 name: "FSQRT", 25287 argLen: 1, 25288 asm: s390x.AFSQRT, 25289 reg: regInfo{ 25290 inputs: []inputInfo{ 25291 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25292 }, 25293 outputs: []outputInfo{ 25294 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25295 }, 25296 }, 25297 }, 25298 { 25299 name: "MOVDEQ", 25300 argLen: 3, 25301 resultInArg0: true, 25302 asm: s390x.AMOVDEQ, 25303 reg: regInfo{ 25304 inputs: []inputInfo{ 25305 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25306 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25307 }, 25308 outputs: []outputInfo{ 25309 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25310 }, 25311 }, 25312 }, 25313 { 25314 name: "MOVDNE", 25315 argLen: 3, 25316 resultInArg0: true, 25317 asm: s390x.AMOVDNE, 25318 reg: regInfo{ 25319 inputs: []inputInfo{ 25320 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25321 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25322 }, 25323 outputs: []outputInfo{ 25324 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25325 }, 25326 }, 25327 }, 25328 { 25329 name: "MOVDLT", 25330 argLen: 3, 25331 resultInArg0: true, 25332 asm: s390x.AMOVDLT, 25333 reg: regInfo{ 25334 inputs: []inputInfo{ 25335 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25336 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25337 }, 25338 outputs: []outputInfo{ 25339 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25340 }, 25341 }, 25342 }, 25343 { 25344 name: "MOVDLE", 25345 argLen: 3, 25346 resultInArg0: true, 25347 asm: s390x.AMOVDLE, 25348 reg: regInfo{ 25349 inputs: []inputInfo{ 25350 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25351 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25352 }, 25353 outputs: []outputInfo{ 25354 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25355 }, 25356 }, 25357 }, 25358 { 25359 name: "MOVDGT", 25360 argLen: 3, 25361 resultInArg0: true, 25362 asm: s390x.AMOVDGT, 25363 reg: regInfo{ 25364 inputs: []inputInfo{ 25365 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25366 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25367 }, 25368 outputs: []outputInfo{ 25369 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25370 }, 25371 }, 25372 }, 25373 { 25374 name: "MOVDGE", 25375 argLen: 3, 25376 resultInArg0: true, 25377 asm: s390x.AMOVDGE, 25378 reg: regInfo{ 25379 inputs: []inputInfo{ 25380 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25381 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25382 }, 25383 outputs: []outputInfo{ 25384 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25385 }, 25386 }, 25387 }, 25388 { 25389 name: "MOVDGTnoinv", 25390 argLen: 3, 25391 resultInArg0: true, 25392 asm: s390x.AMOVDGT, 25393 reg: regInfo{ 25394 inputs: []inputInfo{ 25395 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25396 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25397 }, 25398 outputs: []outputInfo{ 25399 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25400 }, 25401 }, 25402 }, 25403 { 25404 name: "MOVDGEnoinv", 25405 argLen: 3, 25406 resultInArg0: true, 25407 asm: s390x.AMOVDGE, 25408 reg: regInfo{ 25409 inputs: []inputInfo{ 25410 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25411 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25412 }, 25413 outputs: []outputInfo{ 25414 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25415 }, 25416 }, 25417 }, 25418 { 25419 name: "MOVBreg", 25420 argLen: 1, 25421 asm: s390x.AMOVB, 25422 reg: regInfo{ 25423 inputs: []inputInfo{ 25424 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25425 }, 25426 outputs: []outputInfo{ 25427 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25428 }, 25429 }, 25430 }, 25431 { 25432 name: "MOVBZreg", 25433 argLen: 1, 25434 asm: s390x.AMOVBZ, 25435 reg: regInfo{ 25436 inputs: []inputInfo{ 25437 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25438 }, 25439 outputs: []outputInfo{ 25440 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25441 }, 25442 }, 25443 }, 25444 { 25445 name: "MOVHreg", 25446 argLen: 1, 25447 asm: s390x.AMOVH, 25448 reg: regInfo{ 25449 inputs: []inputInfo{ 25450 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25451 }, 25452 outputs: []outputInfo{ 25453 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25454 }, 25455 }, 25456 }, 25457 { 25458 name: "MOVHZreg", 25459 argLen: 1, 25460 asm: s390x.AMOVHZ, 25461 reg: regInfo{ 25462 inputs: []inputInfo{ 25463 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25464 }, 25465 outputs: []outputInfo{ 25466 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25467 }, 25468 }, 25469 }, 25470 { 25471 name: "MOVWreg", 25472 argLen: 1, 25473 asm: s390x.AMOVW, 25474 reg: regInfo{ 25475 inputs: []inputInfo{ 25476 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25477 }, 25478 outputs: []outputInfo{ 25479 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25480 }, 25481 }, 25482 }, 25483 { 25484 name: "MOVWZreg", 25485 argLen: 1, 25486 asm: s390x.AMOVWZ, 25487 reg: regInfo{ 25488 inputs: []inputInfo{ 25489 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25490 }, 25491 outputs: []outputInfo{ 25492 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25493 }, 25494 }, 25495 }, 25496 { 25497 name: "MOVDreg", 25498 argLen: 1, 25499 asm: s390x.AMOVD, 25500 reg: regInfo{ 25501 inputs: []inputInfo{ 25502 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25503 }, 25504 outputs: []outputInfo{ 25505 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25506 }, 25507 }, 25508 }, 25509 { 25510 name: "MOVDnop", 25511 argLen: 1, 25512 resultInArg0: true, 25513 reg: regInfo{ 25514 inputs: []inputInfo{ 25515 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25516 }, 25517 outputs: []outputInfo{ 25518 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25519 }, 25520 }, 25521 }, 25522 { 25523 name: "MOVDconst", 25524 auxType: auxInt64, 25525 argLen: 0, 25526 rematerializeable: true, 25527 asm: s390x.AMOVD, 25528 reg: regInfo{ 25529 outputs: []outputInfo{ 25530 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25531 }, 25532 }, 25533 }, 25534 { 25535 name: "LDGR", 25536 argLen: 1, 25537 asm: s390x.ALDGR, 25538 reg: regInfo{ 25539 inputs: []inputInfo{ 25540 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25541 }, 25542 outputs: []outputInfo{ 25543 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25544 }, 25545 }, 25546 }, 25547 { 25548 name: "LGDR", 25549 argLen: 1, 25550 asm: s390x.ALGDR, 25551 reg: regInfo{ 25552 inputs: []inputInfo{ 25553 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25554 }, 25555 outputs: []outputInfo{ 25556 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25557 }, 25558 }, 25559 }, 25560 { 25561 name: "CFDBRA", 25562 argLen: 1, 25563 asm: s390x.ACFDBRA, 25564 reg: regInfo{ 25565 inputs: []inputInfo{ 25566 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25567 }, 25568 outputs: []outputInfo{ 25569 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25570 }, 25571 }, 25572 }, 25573 { 25574 name: "CGDBRA", 25575 argLen: 1, 25576 asm: s390x.ACGDBRA, 25577 reg: regInfo{ 25578 inputs: []inputInfo{ 25579 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25580 }, 25581 outputs: []outputInfo{ 25582 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25583 }, 25584 }, 25585 }, 25586 { 25587 name: "CFEBRA", 25588 argLen: 1, 25589 asm: s390x.ACFEBRA, 25590 reg: regInfo{ 25591 inputs: []inputInfo{ 25592 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25593 }, 25594 outputs: []outputInfo{ 25595 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25596 }, 25597 }, 25598 }, 25599 { 25600 name: "CGEBRA", 25601 argLen: 1, 25602 asm: s390x.ACGEBRA, 25603 reg: regInfo{ 25604 inputs: []inputInfo{ 25605 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25606 }, 25607 outputs: []outputInfo{ 25608 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25609 }, 25610 }, 25611 }, 25612 { 25613 name: "CEFBRA", 25614 argLen: 1, 25615 asm: s390x.ACEFBRA, 25616 reg: regInfo{ 25617 inputs: []inputInfo{ 25618 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25619 }, 25620 outputs: []outputInfo{ 25621 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25622 }, 25623 }, 25624 }, 25625 { 25626 name: "CDFBRA", 25627 argLen: 1, 25628 asm: s390x.ACDFBRA, 25629 reg: regInfo{ 25630 inputs: []inputInfo{ 25631 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25632 }, 25633 outputs: []outputInfo{ 25634 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25635 }, 25636 }, 25637 }, 25638 { 25639 name: "CEGBRA", 25640 argLen: 1, 25641 asm: s390x.ACEGBRA, 25642 reg: regInfo{ 25643 inputs: []inputInfo{ 25644 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25645 }, 25646 outputs: []outputInfo{ 25647 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25648 }, 25649 }, 25650 }, 25651 { 25652 name: "CDGBRA", 25653 argLen: 1, 25654 asm: s390x.ACDGBRA, 25655 reg: regInfo{ 25656 inputs: []inputInfo{ 25657 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25658 }, 25659 outputs: []outputInfo{ 25660 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25661 }, 25662 }, 25663 }, 25664 { 25665 name: "LEDBR", 25666 argLen: 1, 25667 asm: s390x.ALEDBR, 25668 reg: regInfo{ 25669 inputs: []inputInfo{ 25670 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25671 }, 25672 outputs: []outputInfo{ 25673 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25674 }, 25675 }, 25676 }, 25677 { 25678 name: "LDEBR", 25679 argLen: 1, 25680 asm: s390x.ALDEBR, 25681 reg: regInfo{ 25682 inputs: []inputInfo{ 25683 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25684 }, 25685 outputs: []outputInfo{ 25686 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25687 }, 25688 }, 25689 }, 25690 { 25691 name: "MOVDaddr", 25692 auxType: auxSymOff, 25693 argLen: 1, 25694 rematerializeable: true, 25695 symEffect: SymRead, 25696 reg: regInfo{ 25697 inputs: []inputInfo{ 25698 {0, 4295000064}, // SP SB 25699 }, 25700 outputs: []outputInfo{ 25701 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25702 }, 25703 }, 25704 }, 25705 { 25706 name: "MOVDaddridx", 25707 auxType: auxSymOff, 25708 argLen: 2, 25709 symEffect: SymRead, 25710 reg: regInfo{ 25711 inputs: []inputInfo{ 25712 {0, 4295000064}, // SP SB 25713 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25714 }, 25715 outputs: []outputInfo{ 25716 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25717 }, 25718 }, 25719 }, 25720 { 25721 name: "MOVBZload", 25722 auxType: auxSymOff, 25723 argLen: 2, 25724 clobberFlags: true, 25725 faultOnNilArg0: true, 25726 symEffect: SymRead, 25727 asm: s390x.AMOVBZ, 25728 reg: regInfo{ 25729 inputs: []inputInfo{ 25730 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25731 }, 25732 outputs: []outputInfo{ 25733 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25734 }, 25735 }, 25736 }, 25737 { 25738 name: "MOVBload", 25739 auxType: auxSymOff, 25740 argLen: 2, 25741 clobberFlags: true, 25742 faultOnNilArg0: true, 25743 symEffect: SymRead, 25744 asm: s390x.AMOVB, 25745 reg: regInfo{ 25746 inputs: []inputInfo{ 25747 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25748 }, 25749 outputs: []outputInfo{ 25750 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25751 }, 25752 }, 25753 }, 25754 { 25755 name: "MOVHZload", 25756 auxType: auxSymOff, 25757 argLen: 2, 25758 clobberFlags: true, 25759 faultOnNilArg0: true, 25760 symEffect: SymRead, 25761 asm: s390x.AMOVHZ, 25762 reg: regInfo{ 25763 inputs: []inputInfo{ 25764 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25765 }, 25766 outputs: []outputInfo{ 25767 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25768 }, 25769 }, 25770 }, 25771 { 25772 name: "MOVHload", 25773 auxType: auxSymOff, 25774 argLen: 2, 25775 clobberFlags: true, 25776 faultOnNilArg0: true, 25777 symEffect: SymRead, 25778 asm: s390x.AMOVH, 25779 reg: regInfo{ 25780 inputs: []inputInfo{ 25781 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25782 }, 25783 outputs: []outputInfo{ 25784 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25785 }, 25786 }, 25787 }, 25788 { 25789 name: "MOVWZload", 25790 auxType: auxSymOff, 25791 argLen: 2, 25792 clobberFlags: true, 25793 faultOnNilArg0: true, 25794 symEffect: SymRead, 25795 asm: s390x.AMOVWZ, 25796 reg: regInfo{ 25797 inputs: []inputInfo{ 25798 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25799 }, 25800 outputs: []outputInfo{ 25801 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25802 }, 25803 }, 25804 }, 25805 { 25806 name: "MOVWload", 25807 auxType: auxSymOff, 25808 argLen: 2, 25809 clobberFlags: true, 25810 faultOnNilArg0: true, 25811 symEffect: SymRead, 25812 asm: s390x.AMOVW, 25813 reg: regInfo{ 25814 inputs: []inputInfo{ 25815 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25816 }, 25817 outputs: []outputInfo{ 25818 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25819 }, 25820 }, 25821 }, 25822 { 25823 name: "MOVDload", 25824 auxType: auxSymOff, 25825 argLen: 2, 25826 clobberFlags: true, 25827 faultOnNilArg0: true, 25828 symEffect: SymRead, 25829 asm: s390x.AMOVD, 25830 reg: regInfo{ 25831 inputs: []inputInfo{ 25832 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25833 }, 25834 outputs: []outputInfo{ 25835 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25836 }, 25837 }, 25838 }, 25839 { 25840 name: "MOVWBR", 25841 argLen: 1, 25842 asm: s390x.AMOVWBR, 25843 reg: regInfo{ 25844 inputs: []inputInfo{ 25845 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25846 }, 25847 outputs: []outputInfo{ 25848 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25849 }, 25850 }, 25851 }, 25852 { 25853 name: "MOVDBR", 25854 argLen: 1, 25855 asm: s390x.AMOVDBR, 25856 reg: regInfo{ 25857 inputs: []inputInfo{ 25858 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25859 }, 25860 outputs: []outputInfo{ 25861 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25862 }, 25863 }, 25864 }, 25865 { 25866 name: "MOVHBRload", 25867 auxType: auxSymOff, 25868 argLen: 2, 25869 clobberFlags: true, 25870 faultOnNilArg0: true, 25871 symEffect: SymRead, 25872 asm: s390x.AMOVHBR, 25873 reg: regInfo{ 25874 inputs: []inputInfo{ 25875 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25876 }, 25877 outputs: []outputInfo{ 25878 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25879 }, 25880 }, 25881 }, 25882 { 25883 name: "MOVWBRload", 25884 auxType: auxSymOff, 25885 argLen: 2, 25886 clobberFlags: true, 25887 faultOnNilArg0: true, 25888 symEffect: SymRead, 25889 asm: s390x.AMOVWBR, 25890 reg: regInfo{ 25891 inputs: []inputInfo{ 25892 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25893 }, 25894 outputs: []outputInfo{ 25895 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25896 }, 25897 }, 25898 }, 25899 { 25900 name: "MOVDBRload", 25901 auxType: auxSymOff, 25902 argLen: 2, 25903 clobberFlags: true, 25904 faultOnNilArg0: true, 25905 symEffect: SymRead, 25906 asm: s390x.AMOVDBR, 25907 reg: regInfo{ 25908 inputs: []inputInfo{ 25909 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25910 }, 25911 outputs: []outputInfo{ 25912 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25913 }, 25914 }, 25915 }, 25916 { 25917 name: "MOVBstore", 25918 auxType: auxSymOff, 25919 argLen: 3, 25920 clobberFlags: true, 25921 faultOnNilArg0: true, 25922 symEffect: SymWrite, 25923 asm: s390x.AMOVB, 25924 reg: regInfo{ 25925 inputs: []inputInfo{ 25926 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25927 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25928 }, 25929 }, 25930 }, 25931 { 25932 name: "MOVHstore", 25933 auxType: auxSymOff, 25934 argLen: 3, 25935 clobberFlags: true, 25936 faultOnNilArg0: true, 25937 symEffect: SymWrite, 25938 asm: s390x.AMOVH, 25939 reg: regInfo{ 25940 inputs: []inputInfo{ 25941 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25942 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25943 }, 25944 }, 25945 }, 25946 { 25947 name: "MOVWstore", 25948 auxType: auxSymOff, 25949 argLen: 3, 25950 clobberFlags: true, 25951 faultOnNilArg0: true, 25952 symEffect: SymWrite, 25953 asm: s390x.AMOVW, 25954 reg: regInfo{ 25955 inputs: []inputInfo{ 25956 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25957 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25958 }, 25959 }, 25960 }, 25961 { 25962 name: "MOVDstore", 25963 auxType: auxSymOff, 25964 argLen: 3, 25965 clobberFlags: true, 25966 faultOnNilArg0: true, 25967 symEffect: SymWrite, 25968 asm: s390x.AMOVD, 25969 reg: regInfo{ 25970 inputs: []inputInfo{ 25971 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25972 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25973 }, 25974 }, 25975 }, 25976 { 25977 name: "MOVHBRstore", 25978 auxType: auxSymOff, 25979 argLen: 3, 25980 clobberFlags: true, 25981 faultOnNilArg0: true, 25982 symEffect: SymWrite, 25983 asm: s390x.AMOVHBR, 25984 reg: regInfo{ 25985 inputs: []inputInfo{ 25986 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25987 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25988 }, 25989 }, 25990 }, 25991 { 25992 name: "MOVWBRstore", 25993 auxType: auxSymOff, 25994 argLen: 3, 25995 clobberFlags: true, 25996 faultOnNilArg0: true, 25997 symEffect: SymWrite, 25998 asm: s390x.AMOVWBR, 25999 reg: regInfo{ 26000 inputs: []inputInfo{ 26001 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26002 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26003 }, 26004 }, 26005 }, 26006 { 26007 name: "MOVDBRstore", 26008 auxType: auxSymOff, 26009 argLen: 3, 26010 clobberFlags: true, 26011 faultOnNilArg0: true, 26012 symEffect: SymWrite, 26013 asm: s390x.AMOVDBR, 26014 reg: regInfo{ 26015 inputs: []inputInfo{ 26016 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26017 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26018 }, 26019 }, 26020 }, 26021 { 26022 name: "MVC", 26023 auxType: auxSymValAndOff, 26024 argLen: 3, 26025 clobberFlags: true, 26026 faultOnNilArg0: true, 26027 faultOnNilArg1: true, 26028 symEffect: SymNone, 26029 asm: s390x.AMVC, 26030 reg: regInfo{ 26031 inputs: []inputInfo{ 26032 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26033 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26034 }, 26035 }, 26036 }, 26037 { 26038 name: "MOVBZloadidx", 26039 auxType: auxSymOff, 26040 argLen: 3, 26041 commutative: true, 26042 clobberFlags: true, 26043 symEffect: SymRead, 26044 asm: s390x.AMOVBZ, 26045 reg: regInfo{ 26046 inputs: []inputInfo{ 26047 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26048 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26049 }, 26050 outputs: []outputInfo{ 26051 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26052 }, 26053 }, 26054 }, 26055 { 26056 name: "MOVBloadidx", 26057 auxType: auxSymOff, 26058 argLen: 3, 26059 commutative: true, 26060 clobberFlags: true, 26061 symEffect: SymRead, 26062 asm: s390x.AMOVB, 26063 reg: regInfo{ 26064 inputs: []inputInfo{ 26065 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26066 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26067 }, 26068 outputs: []outputInfo{ 26069 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26070 }, 26071 }, 26072 }, 26073 { 26074 name: "MOVHZloadidx", 26075 auxType: auxSymOff, 26076 argLen: 3, 26077 commutative: true, 26078 clobberFlags: true, 26079 symEffect: SymRead, 26080 asm: s390x.AMOVHZ, 26081 reg: regInfo{ 26082 inputs: []inputInfo{ 26083 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26084 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26085 }, 26086 outputs: []outputInfo{ 26087 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26088 }, 26089 }, 26090 }, 26091 { 26092 name: "MOVHloadidx", 26093 auxType: auxSymOff, 26094 argLen: 3, 26095 commutative: true, 26096 clobberFlags: true, 26097 symEffect: SymRead, 26098 asm: s390x.AMOVH, 26099 reg: regInfo{ 26100 inputs: []inputInfo{ 26101 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26102 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26103 }, 26104 outputs: []outputInfo{ 26105 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26106 }, 26107 }, 26108 }, 26109 { 26110 name: "MOVWZloadidx", 26111 auxType: auxSymOff, 26112 argLen: 3, 26113 commutative: true, 26114 clobberFlags: true, 26115 symEffect: SymRead, 26116 asm: s390x.AMOVWZ, 26117 reg: regInfo{ 26118 inputs: []inputInfo{ 26119 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26120 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26121 }, 26122 outputs: []outputInfo{ 26123 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26124 }, 26125 }, 26126 }, 26127 { 26128 name: "MOVWloadidx", 26129 auxType: auxSymOff, 26130 argLen: 3, 26131 commutative: true, 26132 clobberFlags: true, 26133 symEffect: SymRead, 26134 asm: s390x.AMOVW, 26135 reg: regInfo{ 26136 inputs: []inputInfo{ 26137 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26138 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26139 }, 26140 outputs: []outputInfo{ 26141 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26142 }, 26143 }, 26144 }, 26145 { 26146 name: "MOVDloadidx", 26147 auxType: auxSymOff, 26148 argLen: 3, 26149 commutative: true, 26150 clobberFlags: true, 26151 symEffect: SymRead, 26152 asm: s390x.AMOVD, 26153 reg: regInfo{ 26154 inputs: []inputInfo{ 26155 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26156 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26157 }, 26158 outputs: []outputInfo{ 26159 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26160 }, 26161 }, 26162 }, 26163 { 26164 name: "MOVHBRloadidx", 26165 auxType: auxSymOff, 26166 argLen: 3, 26167 commutative: true, 26168 clobberFlags: true, 26169 symEffect: SymRead, 26170 asm: s390x.AMOVHBR, 26171 reg: regInfo{ 26172 inputs: []inputInfo{ 26173 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26174 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26175 }, 26176 outputs: []outputInfo{ 26177 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26178 }, 26179 }, 26180 }, 26181 { 26182 name: "MOVWBRloadidx", 26183 auxType: auxSymOff, 26184 argLen: 3, 26185 commutative: true, 26186 clobberFlags: true, 26187 symEffect: SymRead, 26188 asm: s390x.AMOVWBR, 26189 reg: regInfo{ 26190 inputs: []inputInfo{ 26191 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26192 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26193 }, 26194 outputs: []outputInfo{ 26195 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26196 }, 26197 }, 26198 }, 26199 { 26200 name: "MOVDBRloadidx", 26201 auxType: auxSymOff, 26202 argLen: 3, 26203 commutative: true, 26204 clobberFlags: true, 26205 symEffect: SymRead, 26206 asm: s390x.AMOVDBR, 26207 reg: regInfo{ 26208 inputs: []inputInfo{ 26209 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26210 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26211 }, 26212 outputs: []outputInfo{ 26213 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26214 }, 26215 }, 26216 }, 26217 { 26218 name: "MOVBstoreidx", 26219 auxType: auxSymOff, 26220 argLen: 4, 26221 commutative: true, 26222 clobberFlags: true, 26223 symEffect: SymWrite, 26224 asm: s390x.AMOVB, 26225 reg: regInfo{ 26226 inputs: []inputInfo{ 26227 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26228 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26229 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26230 }, 26231 }, 26232 }, 26233 { 26234 name: "MOVHstoreidx", 26235 auxType: auxSymOff, 26236 argLen: 4, 26237 commutative: true, 26238 clobberFlags: true, 26239 symEffect: SymWrite, 26240 asm: s390x.AMOVH, 26241 reg: regInfo{ 26242 inputs: []inputInfo{ 26243 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26244 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26245 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26246 }, 26247 }, 26248 }, 26249 { 26250 name: "MOVWstoreidx", 26251 auxType: auxSymOff, 26252 argLen: 4, 26253 commutative: true, 26254 clobberFlags: true, 26255 symEffect: SymWrite, 26256 asm: s390x.AMOVW, 26257 reg: regInfo{ 26258 inputs: []inputInfo{ 26259 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26260 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26261 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26262 }, 26263 }, 26264 }, 26265 { 26266 name: "MOVDstoreidx", 26267 auxType: auxSymOff, 26268 argLen: 4, 26269 commutative: true, 26270 clobberFlags: true, 26271 symEffect: SymWrite, 26272 asm: s390x.AMOVD, 26273 reg: regInfo{ 26274 inputs: []inputInfo{ 26275 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26276 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26277 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26278 }, 26279 }, 26280 }, 26281 { 26282 name: "MOVHBRstoreidx", 26283 auxType: auxSymOff, 26284 argLen: 4, 26285 commutative: true, 26286 clobberFlags: true, 26287 symEffect: SymWrite, 26288 asm: s390x.AMOVHBR, 26289 reg: regInfo{ 26290 inputs: []inputInfo{ 26291 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26292 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26293 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26294 }, 26295 }, 26296 }, 26297 { 26298 name: "MOVWBRstoreidx", 26299 auxType: auxSymOff, 26300 argLen: 4, 26301 commutative: true, 26302 clobberFlags: true, 26303 symEffect: SymWrite, 26304 asm: s390x.AMOVWBR, 26305 reg: regInfo{ 26306 inputs: []inputInfo{ 26307 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26308 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26309 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26310 }, 26311 }, 26312 }, 26313 { 26314 name: "MOVDBRstoreidx", 26315 auxType: auxSymOff, 26316 argLen: 4, 26317 commutative: true, 26318 clobberFlags: true, 26319 symEffect: SymWrite, 26320 asm: s390x.AMOVDBR, 26321 reg: regInfo{ 26322 inputs: []inputInfo{ 26323 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26324 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26325 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26326 }, 26327 }, 26328 }, 26329 { 26330 name: "MOVBstoreconst", 26331 auxType: auxSymValAndOff, 26332 argLen: 2, 26333 faultOnNilArg0: true, 26334 symEffect: SymWrite, 26335 asm: s390x.AMOVB, 26336 reg: regInfo{ 26337 inputs: []inputInfo{ 26338 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26339 }, 26340 }, 26341 }, 26342 { 26343 name: "MOVHstoreconst", 26344 auxType: auxSymValAndOff, 26345 argLen: 2, 26346 faultOnNilArg0: true, 26347 symEffect: SymWrite, 26348 asm: s390x.AMOVH, 26349 reg: regInfo{ 26350 inputs: []inputInfo{ 26351 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26352 }, 26353 }, 26354 }, 26355 { 26356 name: "MOVWstoreconst", 26357 auxType: auxSymValAndOff, 26358 argLen: 2, 26359 faultOnNilArg0: true, 26360 symEffect: SymWrite, 26361 asm: s390x.AMOVW, 26362 reg: regInfo{ 26363 inputs: []inputInfo{ 26364 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26365 }, 26366 }, 26367 }, 26368 { 26369 name: "MOVDstoreconst", 26370 auxType: auxSymValAndOff, 26371 argLen: 2, 26372 faultOnNilArg0: true, 26373 symEffect: SymWrite, 26374 asm: s390x.AMOVD, 26375 reg: regInfo{ 26376 inputs: []inputInfo{ 26377 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26378 }, 26379 }, 26380 }, 26381 { 26382 name: "CLEAR", 26383 auxType: auxSymValAndOff, 26384 argLen: 2, 26385 clobberFlags: true, 26386 faultOnNilArg0: true, 26387 symEffect: SymWrite, 26388 asm: s390x.ACLEAR, 26389 reg: regInfo{ 26390 inputs: []inputInfo{ 26391 {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26392 }, 26393 }, 26394 }, 26395 { 26396 name: "CALLstatic", 26397 auxType: auxSymOff, 26398 argLen: 1, 26399 clobberFlags: true, 26400 call: true, 26401 symEffect: SymNone, 26402 reg: regInfo{ 26403 clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 26404 }, 26405 }, 26406 { 26407 name: "CALLclosure", 26408 auxType: auxInt64, 26409 argLen: 3, 26410 clobberFlags: true, 26411 call: true, 26412 reg: regInfo{ 26413 inputs: []inputInfo{ 26414 {1, 4096}, // R12 26415 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26416 }, 26417 clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 26418 }, 26419 }, 26420 { 26421 name: "CALLinter", 26422 auxType: auxInt64, 26423 argLen: 2, 26424 clobberFlags: true, 26425 call: true, 26426 reg: regInfo{ 26427 inputs: []inputInfo{ 26428 {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26429 }, 26430 clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 26431 }, 26432 }, 26433 { 26434 name: "InvertFlags", 26435 argLen: 1, 26436 reg: regInfo{}, 26437 }, 26438 { 26439 name: "LoweredGetG", 26440 argLen: 1, 26441 reg: regInfo{ 26442 outputs: []outputInfo{ 26443 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26444 }, 26445 }, 26446 }, 26447 { 26448 name: "LoweredGetClosurePtr", 26449 argLen: 0, 26450 zeroWidth: true, 26451 reg: regInfo{ 26452 outputs: []outputInfo{ 26453 {0, 4096}, // R12 26454 }, 26455 }, 26456 }, 26457 { 26458 name: "LoweredGetCallerSP", 26459 argLen: 0, 26460 rematerializeable: true, 26461 reg: regInfo{ 26462 outputs: []outputInfo{ 26463 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26464 }, 26465 }, 26466 }, 26467 { 26468 name: "LoweredGetCallerPC", 26469 argLen: 0, 26470 rematerializeable: true, 26471 reg: regInfo{ 26472 outputs: []outputInfo{ 26473 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26474 }, 26475 }, 26476 }, 26477 { 26478 name: "LoweredNilCheck", 26479 argLen: 2, 26480 clobberFlags: true, 26481 nilCheck: true, 26482 faultOnNilArg0: true, 26483 reg: regInfo{ 26484 inputs: []inputInfo{ 26485 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26486 }, 26487 }, 26488 }, 26489 { 26490 name: "LoweredRound32F", 26491 argLen: 1, 26492 resultInArg0: true, 26493 zeroWidth: true, 26494 reg: regInfo{ 26495 inputs: []inputInfo{ 26496 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 26497 }, 26498 outputs: []outputInfo{ 26499 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 26500 }, 26501 }, 26502 }, 26503 { 26504 name: "LoweredRound64F", 26505 argLen: 1, 26506 resultInArg0: true, 26507 zeroWidth: true, 26508 reg: regInfo{ 26509 inputs: []inputInfo{ 26510 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 26511 }, 26512 outputs: []outputInfo{ 26513 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 26514 }, 26515 }, 26516 }, 26517 { 26518 name: "LoweredWB", 26519 auxType: auxSym, 26520 argLen: 3, 26521 clobberFlags: true, 26522 symEffect: SymNone, 26523 reg: regInfo{ 26524 inputs: []inputInfo{ 26525 {0, 4}, // R2 26526 {1, 8}, // R3 26527 }, 26528 clobbers: 4294918144, // R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 26529 }, 26530 }, 26531 { 26532 name: "FlagEQ", 26533 argLen: 0, 26534 reg: regInfo{}, 26535 }, 26536 { 26537 name: "FlagLT", 26538 argLen: 0, 26539 reg: regInfo{}, 26540 }, 26541 { 26542 name: "FlagGT", 26543 argLen: 0, 26544 reg: regInfo{}, 26545 }, 26546 { 26547 name: "MOVWZatomicload", 26548 auxType: auxSymOff, 26549 argLen: 2, 26550 faultOnNilArg0: true, 26551 symEffect: SymRead, 26552 asm: s390x.AMOVWZ, 26553 reg: regInfo{ 26554 inputs: []inputInfo{ 26555 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26556 }, 26557 outputs: []outputInfo{ 26558 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26559 }, 26560 }, 26561 }, 26562 { 26563 name: "MOVDatomicload", 26564 auxType: auxSymOff, 26565 argLen: 2, 26566 faultOnNilArg0: true, 26567 symEffect: SymRead, 26568 asm: s390x.AMOVD, 26569 reg: regInfo{ 26570 inputs: []inputInfo{ 26571 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26572 }, 26573 outputs: []outputInfo{ 26574 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26575 }, 26576 }, 26577 }, 26578 { 26579 name: "MOVWatomicstore", 26580 auxType: auxSymOff, 26581 argLen: 3, 26582 clobberFlags: true, 26583 faultOnNilArg0: true, 26584 hasSideEffects: true, 26585 symEffect: SymWrite, 26586 asm: s390x.AMOVW, 26587 reg: regInfo{ 26588 inputs: []inputInfo{ 26589 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26590 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26591 }, 26592 }, 26593 }, 26594 { 26595 name: "MOVDatomicstore", 26596 auxType: auxSymOff, 26597 argLen: 3, 26598 clobberFlags: true, 26599 faultOnNilArg0: true, 26600 hasSideEffects: true, 26601 symEffect: SymWrite, 26602 asm: s390x.AMOVD, 26603 reg: regInfo{ 26604 inputs: []inputInfo{ 26605 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26606 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26607 }, 26608 }, 26609 }, 26610 { 26611 name: "LAA", 26612 auxType: auxSymOff, 26613 argLen: 3, 26614 clobberFlags: true, 26615 faultOnNilArg0: true, 26616 hasSideEffects: true, 26617 symEffect: SymRdWr, 26618 asm: s390x.ALAA, 26619 reg: regInfo{ 26620 inputs: []inputInfo{ 26621 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26622 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26623 }, 26624 outputs: []outputInfo{ 26625 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26626 }, 26627 }, 26628 }, 26629 { 26630 name: "LAAG", 26631 auxType: auxSymOff, 26632 argLen: 3, 26633 clobberFlags: true, 26634 faultOnNilArg0: true, 26635 hasSideEffects: true, 26636 symEffect: SymRdWr, 26637 asm: s390x.ALAAG, 26638 reg: regInfo{ 26639 inputs: []inputInfo{ 26640 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26641 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26642 }, 26643 outputs: []outputInfo{ 26644 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26645 }, 26646 }, 26647 }, 26648 { 26649 name: "AddTupleFirst32", 26650 argLen: 2, 26651 reg: regInfo{}, 26652 }, 26653 { 26654 name: "AddTupleFirst64", 26655 argLen: 2, 26656 reg: regInfo{}, 26657 }, 26658 { 26659 name: "LoweredAtomicCas32", 26660 auxType: auxSymOff, 26661 argLen: 4, 26662 clobberFlags: true, 26663 faultOnNilArg0: true, 26664 hasSideEffects: true, 26665 symEffect: SymRdWr, 26666 asm: s390x.ACS, 26667 reg: regInfo{ 26668 inputs: []inputInfo{ 26669 {1, 1}, // R0 26670 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26671 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26672 }, 26673 clobbers: 1, // R0 26674 outputs: []outputInfo{ 26675 {1, 0}, 26676 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26677 }, 26678 }, 26679 }, 26680 { 26681 name: "LoweredAtomicCas64", 26682 auxType: auxSymOff, 26683 argLen: 4, 26684 clobberFlags: true, 26685 faultOnNilArg0: true, 26686 hasSideEffects: true, 26687 symEffect: SymRdWr, 26688 asm: s390x.ACSG, 26689 reg: regInfo{ 26690 inputs: []inputInfo{ 26691 {1, 1}, // R0 26692 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26693 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26694 }, 26695 clobbers: 1, // R0 26696 outputs: []outputInfo{ 26697 {1, 0}, 26698 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26699 }, 26700 }, 26701 }, 26702 { 26703 name: "LoweredAtomicExchange32", 26704 auxType: auxSymOff, 26705 argLen: 3, 26706 clobberFlags: true, 26707 faultOnNilArg0: true, 26708 hasSideEffects: true, 26709 symEffect: SymRdWr, 26710 asm: s390x.ACS, 26711 reg: regInfo{ 26712 inputs: []inputInfo{ 26713 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26714 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26715 }, 26716 outputs: []outputInfo{ 26717 {1, 0}, 26718 {0, 1}, // R0 26719 }, 26720 }, 26721 }, 26722 { 26723 name: "LoweredAtomicExchange64", 26724 auxType: auxSymOff, 26725 argLen: 3, 26726 clobberFlags: true, 26727 faultOnNilArg0: true, 26728 hasSideEffects: true, 26729 symEffect: SymRdWr, 26730 asm: s390x.ACSG, 26731 reg: regInfo{ 26732 inputs: []inputInfo{ 26733 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26734 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26735 }, 26736 outputs: []outputInfo{ 26737 {1, 0}, 26738 {0, 1}, // R0 26739 }, 26740 }, 26741 }, 26742 { 26743 name: "FLOGR", 26744 argLen: 1, 26745 clobberFlags: true, 26746 asm: s390x.AFLOGR, 26747 reg: regInfo{ 26748 inputs: []inputInfo{ 26749 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26750 }, 26751 clobbers: 2, // R1 26752 outputs: []outputInfo{ 26753 {0, 1}, // R0 26754 }, 26755 }, 26756 }, 26757 { 26758 name: "POPCNT", 26759 argLen: 1, 26760 clobberFlags: true, 26761 asm: s390x.APOPCNT, 26762 reg: regInfo{ 26763 inputs: []inputInfo{ 26764 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26765 }, 26766 outputs: []outputInfo{ 26767 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26768 }, 26769 }, 26770 }, 26771 { 26772 name: "SumBytes2", 26773 argLen: 1, 26774 reg: regInfo{}, 26775 }, 26776 { 26777 name: "SumBytes4", 26778 argLen: 1, 26779 reg: regInfo{}, 26780 }, 26781 { 26782 name: "SumBytes8", 26783 argLen: 1, 26784 reg: regInfo{}, 26785 }, 26786 { 26787 name: "STMG2", 26788 auxType: auxSymOff, 26789 argLen: 4, 26790 faultOnNilArg0: true, 26791 symEffect: SymWrite, 26792 asm: s390x.ASTMG, 26793 reg: regInfo{ 26794 inputs: []inputInfo{ 26795 {1, 2}, // R1 26796 {2, 4}, // R2 26797 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26798 }, 26799 }, 26800 }, 26801 { 26802 name: "STMG3", 26803 auxType: auxSymOff, 26804 argLen: 5, 26805 faultOnNilArg0: true, 26806 symEffect: SymWrite, 26807 asm: s390x.ASTMG, 26808 reg: regInfo{ 26809 inputs: []inputInfo{ 26810 {1, 2}, // R1 26811 {2, 4}, // R2 26812 {3, 8}, // R3 26813 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26814 }, 26815 }, 26816 }, 26817 { 26818 name: "STMG4", 26819 auxType: auxSymOff, 26820 argLen: 6, 26821 faultOnNilArg0: true, 26822 symEffect: SymWrite, 26823 asm: s390x.ASTMG, 26824 reg: regInfo{ 26825 inputs: []inputInfo{ 26826 {1, 2}, // R1 26827 {2, 4}, // R2 26828 {3, 8}, // R3 26829 {4, 16}, // R4 26830 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26831 }, 26832 }, 26833 }, 26834 { 26835 name: "STM2", 26836 auxType: auxSymOff, 26837 argLen: 4, 26838 faultOnNilArg0: true, 26839 symEffect: SymWrite, 26840 asm: s390x.ASTMY, 26841 reg: regInfo{ 26842 inputs: []inputInfo{ 26843 {1, 2}, // R1 26844 {2, 4}, // R2 26845 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26846 }, 26847 }, 26848 }, 26849 { 26850 name: "STM3", 26851 auxType: auxSymOff, 26852 argLen: 5, 26853 faultOnNilArg0: true, 26854 symEffect: SymWrite, 26855 asm: s390x.ASTMY, 26856 reg: regInfo{ 26857 inputs: []inputInfo{ 26858 {1, 2}, // R1 26859 {2, 4}, // R2 26860 {3, 8}, // R3 26861 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26862 }, 26863 }, 26864 }, 26865 { 26866 name: "STM4", 26867 auxType: auxSymOff, 26868 argLen: 6, 26869 faultOnNilArg0: true, 26870 symEffect: SymWrite, 26871 asm: s390x.ASTMY, 26872 reg: regInfo{ 26873 inputs: []inputInfo{ 26874 {1, 2}, // R1 26875 {2, 4}, // R2 26876 {3, 8}, // R3 26877 {4, 16}, // R4 26878 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26879 }, 26880 }, 26881 }, 26882 { 26883 name: "LoweredMove", 26884 auxType: auxInt64, 26885 argLen: 4, 26886 clobberFlags: true, 26887 faultOnNilArg0: true, 26888 faultOnNilArg1: true, 26889 reg: regInfo{ 26890 inputs: []inputInfo{ 26891 {0, 2}, // R1 26892 {1, 4}, // R2 26893 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26894 }, 26895 clobbers: 6, // R1 R2 26896 }, 26897 }, 26898 { 26899 name: "LoweredZero", 26900 auxType: auxInt64, 26901 argLen: 3, 26902 clobberFlags: true, 26903 faultOnNilArg0: true, 26904 reg: regInfo{ 26905 inputs: []inputInfo{ 26906 {0, 2}, // R1 26907 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26908 }, 26909 clobbers: 2, // R1 26910 }, 26911 }, 26912 26913 { 26914 name: "LoweredStaticCall", 26915 auxType: auxSymOff, 26916 argLen: 1, 26917 call: true, 26918 symEffect: SymNone, 26919 reg: regInfo{ 26920 clobbers: 12884901887, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 g 26921 }, 26922 }, 26923 { 26924 name: "LoweredClosureCall", 26925 auxType: auxInt64, 26926 argLen: 3, 26927 call: true, 26928 reg: regInfo{ 26929 inputs: []inputInfo{ 26930 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 26931 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 26932 }, 26933 clobbers: 12884901887, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 g 26934 }, 26935 }, 26936 { 26937 name: "LoweredInterCall", 26938 auxType: auxInt64, 26939 argLen: 2, 26940 call: true, 26941 reg: regInfo{ 26942 inputs: []inputInfo{ 26943 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 26944 }, 26945 clobbers: 12884901887, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 g 26946 }, 26947 }, 26948 { 26949 name: "LoweredAddr", 26950 auxType: auxSymOff, 26951 argLen: 1, 26952 rematerializeable: true, 26953 symEffect: SymAddr, 26954 reg: regInfo{ 26955 inputs: []inputInfo{ 26956 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 26957 }, 26958 outputs: []outputInfo{ 26959 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 26960 }, 26961 }, 26962 }, 26963 { 26964 name: "LoweredMove", 26965 auxType: auxInt64, 26966 argLen: 3, 26967 reg: regInfo{ 26968 inputs: []inputInfo{ 26969 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 26970 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 26971 }, 26972 }, 26973 }, 26974 { 26975 name: "LoweredZero", 26976 auxType: auxInt64, 26977 argLen: 2, 26978 reg: regInfo{ 26979 inputs: []inputInfo{ 26980 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 26981 }, 26982 }, 26983 }, 26984 { 26985 name: "LoweredGetClosurePtr", 26986 argLen: 0, 26987 reg: regInfo{ 26988 outputs: []outputInfo{ 26989 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 26990 }, 26991 }, 26992 }, 26993 { 26994 name: "LoweredGetCallerPC", 26995 argLen: 0, 26996 rematerializeable: true, 26997 reg: regInfo{ 26998 outputs: []outputInfo{ 26999 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27000 }, 27001 }, 27002 }, 27003 { 27004 name: "LoweredGetCallerSP", 27005 argLen: 0, 27006 rematerializeable: true, 27007 reg: regInfo{ 27008 outputs: []outputInfo{ 27009 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27010 }, 27011 }, 27012 }, 27013 { 27014 name: "LoweredNilCheck", 27015 argLen: 2, 27016 nilCheck: true, 27017 faultOnNilArg0: true, 27018 reg: regInfo{ 27019 inputs: []inputInfo{ 27020 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27021 }, 27022 }, 27023 }, 27024 { 27025 name: "LoweredWB", 27026 auxType: auxSym, 27027 argLen: 3, 27028 symEffect: SymNone, 27029 reg: regInfo{ 27030 inputs: []inputInfo{ 27031 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27032 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27033 }, 27034 }, 27035 }, 27036 { 27037 name: "LoweredRound32F", 27038 argLen: 1, 27039 reg: regInfo{ 27040 inputs: []inputInfo{ 27041 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27042 }, 27043 outputs: []outputInfo{ 27044 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27045 }, 27046 }, 27047 }, 27048 { 27049 name: "LoweredConvert", 27050 argLen: 2, 27051 reg: regInfo{ 27052 inputs: []inputInfo{ 27053 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27054 }, 27055 outputs: []outputInfo{ 27056 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27057 }, 27058 }, 27059 }, 27060 { 27061 name: "Select", 27062 argLen: 3, 27063 asm: wasm.ASelect, 27064 reg: regInfo{ 27065 inputs: []inputInfo{ 27066 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27067 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27068 {2, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27069 }, 27070 outputs: []outputInfo{ 27071 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27072 }, 27073 }, 27074 }, 27075 { 27076 name: "I64Load8U", 27077 auxType: auxInt64, 27078 argLen: 2, 27079 asm: wasm.AI64Load8U, 27080 reg: regInfo{ 27081 inputs: []inputInfo{ 27082 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27083 }, 27084 outputs: []outputInfo{ 27085 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27086 }, 27087 }, 27088 }, 27089 { 27090 name: "I64Load8S", 27091 auxType: auxInt64, 27092 argLen: 2, 27093 asm: wasm.AI64Load8S, 27094 reg: regInfo{ 27095 inputs: []inputInfo{ 27096 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27097 }, 27098 outputs: []outputInfo{ 27099 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27100 }, 27101 }, 27102 }, 27103 { 27104 name: "I64Load16U", 27105 auxType: auxInt64, 27106 argLen: 2, 27107 asm: wasm.AI64Load16U, 27108 reg: regInfo{ 27109 inputs: []inputInfo{ 27110 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27111 }, 27112 outputs: []outputInfo{ 27113 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27114 }, 27115 }, 27116 }, 27117 { 27118 name: "I64Load16S", 27119 auxType: auxInt64, 27120 argLen: 2, 27121 asm: wasm.AI64Load16S, 27122 reg: regInfo{ 27123 inputs: []inputInfo{ 27124 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27125 }, 27126 outputs: []outputInfo{ 27127 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27128 }, 27129 }, 27130 }, 27131 { 27132 name: "I64Load32U", 27133 auxType: auxInt64, 27134 argLen: 2, 27135 asm: wasm.AI64Load32U, 27136 reg: regInfo{ 27137 inputs: []inputInfo{ 27138 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27139 }, 27140 outputs: []outputInfo{ 27141 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27142 }, 27143 }, 27144 }, 27145 { 27146 name: "I64Load32S", 27147 auxType: auxInt64, 27148 argLen: 2, 27149 asm: wasm.AI64Load32S, 27150 reg: regInfo{ 27151 inputs: []inputInfo{ 27152 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27153 }, 27154 outputs: []outputInfo{ 27155 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27156 }, 27157 }, 27158 }, 27159 { 27160 name: "I64Load", 27161 auxType: auxInt64, 27162 argLen: 2, 27163 asm: wasm.AI64Load, 27164 reg: regInfo{ 27165 inputs: []inputInfo{ 27166 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27167 }, 27168 outputs: []outputInfo{ 27169 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27170 }, 27171 }, 27172 }, 27173 { 27174 name: "I64Store8", 27175 auxType: auxInt64, 27176 argLen: 3, 27177 asm: wasm.AI64Store8, 27178 reg: regInfo{ 27179 inputs: []inputInfo{ 27180 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27181 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27182 }, 27183 }, 27184 }, 27185 { 27186 name: "I64Store16", 27187 auxType: auxInt64, 27188 argLen: 3, 27189 asm: wasm.AI64Store16, 27190 reg: regInfo{ 27191 inputs: []inputInfo{ 27192 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27193 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27194 }, 27195 }, 27196 }, 27197 { 27198 name: "I64Store32", 27199 auxType: auxInt64, 27200 argLen: 3, 27201 asm: wasm.AI64Store32, 27202 reg: regInfo{ 27203 inputs: []inputInfo{ 27204 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27205 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27206 }, 27207 }, 27208 }, 27209 { 27210 name: "I64Store", 27211 auxType: auxInt64, 27212 argLen: 3, 27213 asm: wasm.AI64Store, 27214 reg: regInfo{ 27215 inputs: []inputInfo{ 27216 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27217 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27218 }, 27219 }, 27220 }, 27221 { 27222 name: "F32Load", 27223 auxType: auxInt64, 27224 argLen: 2, 27225 asm: wasm.AF32Load, 27226 reg: regInfo{ 27227 inputs: []inputInfo{ 27228 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27229 }, 27230 outputs: []outputInfo{ 27231 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27232 }, 27233 }, 27234 }, 27235 { 27236 name: "F64Load", 27237 auxType: auxInt64, 27238 argLen: 2, 27239 asm: wasm.AF64Load, 27240 reg: regInfo{ 27241 inputs: []inputInfo{ 27242 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27243 }, 27244 outputs: []outputInfo{ 27245 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27246 }, 27247 }, 27248 }, 27249 { 27250 name: "F32Store", 27251 auxType: auxInt64, 27252 argLen: 3, 27253 asm: wasm.AF32Store, 27254 reg: regInfo{ 27255 inputs: []inputInfo{ 27256 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27257 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27258 }, 27259 }, 27260 }, 27261 { 27262 name: "F64Store", 27263 auxType: auxInt64, 27264 argLen: 3, 27265 asm: wasm.AF64Store, 27266 reg: regInfo{ 27267 inputs: []inputInfo{ 27268 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27269 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27270 }, 27271 }, 27272 }, 27273 { 27274 name: "I64Const", 27275 auxType: auxInt64, 27276 argLen: 0, 27277 rematerializeable: true, 27278 reg: regInfo{ 27279 outputs: []outputInfo{ 27280 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27281 }, 27282 }, 27283 }, 27284 { 27285 name: "F64Const", 27286 auxType: auxFloat64, 27287 argLen: 0, 27288 rematerializeable: true, 27289 reg: regInfo{ 27290 outputs: []outputInfo{ 27291 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27292 }, 27293 }, 27294 }, 27295 { 27296 name: "I64Eqz", 27297 argLen: 1, 27298 asm: wasm.AI64Eqz, 27299 reg: regInfo{ 27300 inputs: []inputInfo{ 27301 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27302 }, 27303 outputs: []outputInfo{ 27304 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27305 }, 27306 }, 27307 }, 27308 { 27309 name: "I64Eq", 27310 argLen: 2, 27311 asm: wasm.AI64Eq, 27312 reg: regInfo{ 27313 inputs: []inputInfo{ 27314 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27315 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27316 }, 27317 outputs: []outputInfo{ 27318 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27319 }, 27320 }, 27321 }, 27322 { 27323 name: "I64Ne", 27324 argLen: 2, 27325 asm: wasm.AI64Ne, 27326 reg: regInfo{ 27327 inputs: []inputInfo{ 27328 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27329 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27330 }, 27331 outputs: []outputInfo{ 27332 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27333 }, 27334 }, 27335 }, 27336 { 27337 name: "I64LtS", 27338 argLen: 2, 27339 asm: wasm.AI64LtS, 27340 reg: regInfo{ 27341 inputs: []inputInfo{ 27342 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27343 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27344 }, 27345 outputs: []outputInfo{ 27346 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27347 }, 27348 }, 27349 }, 27350 { 27351 name: "I64LtU", 27352 argLen: 2, 27353 asm: wasm.AI64LtU, 27354 reg: regInfo{ 27355 inputs: []inputInfo{ 27356 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27357 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27358 }, 27359 outputs: []outputInfo{ 27360 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27361 }, 27362 }, 27363 }, 27364 { 27365 name: "I64GtS", 27366 argLen: 2, 27367 asm: wasm.AI64GtS, 27368 reg: regInfo{ 27369 inputs: []inputInfo{ 27370 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27371 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27372 }, 27373 outputs: []outputInfo{ 27374 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27375 }, 27376 }, 27377 }, 27378 { 27379 name: "I64GtU", 27380 argLen: 2, 27381 asm: wasm.AI64GtU, 27382 reg: regInfo{ 27383 inputs: []inputInfo{ 27384 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27385 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27386 }, 27387 outputs: []outputInfo{ 27388 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27389 }, 27390 }, 27391 }, 27392 { 27393 name: "I64LeS", 27394 argLen: 2, 27395 asm: wasm.AI64LeS, 27396 reg: regInfo{ 27397 inputs: []inputInfo{ 27398 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27399 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27400 }, 27401 outputs: []outputInfo{ 27402 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27403 }, 27404 }, 27405 }, 27406 { 27407 name: "I64LeU", 27408 argLen: 2, 27409 asm: wasm.AI64LeU, 27410 reg: regInfo{ 27411 inputs: []inputInfo{ 27412 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27413 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27414 }, 27415 outputs: []outputInfo{ 27416 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27417 }, 27418 }, 27419 }, 27420 { 27421 name: "I64GeS", 27422 argLen: 2, 27423 asm: wasm.AI64GeS, 27424 reg: regInfo{ 27425 inputs: []inputInfo{ 27426 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27427 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27428 }, 27429 outputs: []outputInfo{ 27430 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27431 }, 27432 }, 27433 }, 27434 { 27435 name: "I64GeU", 27436 argLen: 2, 27437 asm: wasm.AI64GeU, 27438 reg: regInfo{ 27439 inputs: []inputInfo{ 27440 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27441 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27442 }, 27443 outputs: []outputInfo{ 27444 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27445 }, 27446 }, 27447 }, 27448 { 27449 name: "F64Eq", 27450 argLen: 2, 27451 asm: wasm.AF64Eq, 27452 reg: regInfo{ 27453 inputs: []inputInfo{ 27454 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27455 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27456 }, 27457 outputs: []outputInfo{ 27458 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27459 }, 27460 }, 27461 }, 27462 { 27463 name: "F64Ne", 27464 argLen: 2, 27465 asm: wasm.AF64Ne, 27466 reg: regInfo{ 27467 inputs: []inputInfo{ 27468 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27469 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27470 }, 27471 outputs: []outputInfo{ 27472 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27473 }, 27474 }, 27475 }, 27476 { 27477 name: "F64Lt", 27478 argLen: 2, 27479 asm: wasm.AF64Lt, 27480 reg: regInfo{ 27481 inputs: []inputInfo{ 27482 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27483 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27484 }, 27485 outputs: []outputInfo{ 27486 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27487 }, 27488 }, 27489 }, 27490 { 27491 name: "F64Gt", 27492 argLen: 2, 27493 asm: wasm.AF64Gt, 27494 reg: regInfo{ 27495 inputs: []inputInfo{ 27496 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27497 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27498 }, 27499 outputs: []outputInfo{ 27500 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27501 }, 27502 }, 27503 }, 27504 { 27505 name: "F64Le", 27506 argLen: 2, 27507 asm: wasm.AF64Le, 27508 reg: regInfo{ 27509 inputs: []inputInfo{ 27510 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27511 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27512 }, 27513 outputs: []outputInfo{ 27514 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27515 }, 27516 }, 27517 }, 27518 { 27519 name: "F64Ge", 27520 argLen: 2, 27521 asm: wasm.AF64Ge, 27522 reg: regInfo{ 27523 inputs: []inputInfo{ 27524 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27525 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27526 }, 27527 outputs: []outputInfo{ 27528 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27529 }, 27530 }, 27531 }, 27532 { 27533 name: "I64Add", 27534 argLen: 2, 27535 asm: wasm.AI64Add, 27536 reg: regInfo{ 27537 inputs: []inputInfo{ 27538 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27539 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27540 }, 27541 outputs: []outputInfo{ 27542 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27543 }, 27544 }, 27545 }, 27546 { 27547 name: "I64AddConst", 27548 auxType: auxInt64, 27549 argLen: 1, 27550 asm: wasm.AI64Add, 27551 reg: regInfo{ 27552 inputs: []inputInfo{ 27553 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27554 }, 27555 outputs: []outputInfo{ 27556 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27557 }, 27558 }, 27559 }, 27560 { 27561 name: "I64Sub", 27562 argLen: 2, 27563 asm: wasm.AI64Sub, 27564 reg: regInfo{ 27565 inputs: []inputInfo{ 27566 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27567 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27568 }, 27569 outputs: []outputInfo{ 27570 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27571 }, 27572 }, 27573 }, 27574 { 27575 name: "I64Mul", 27576 argLen: 2, 27577 asm: wasm.AI64Mul, 27578 reg: regInfo{ 27579 inputs: []inputInfo{ 27580 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27581 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27582 }, 27583 outputs: []outputInfo{ 27584 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27585 }, 27586 }, 27587 }, 27588 { 27589 name: "I64DivS", 27590 argLen: 2, 27591 asm: wasm.AI64DivS, 27592 reg: regInfo{ 27593 inputs: []inputInfo{ 27594 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27595 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27596 }, 27597 outputs: []outputInfo{ 27598 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27599 }, 27600 }, 27601 }, 27602 { 27603 name: "I64DivU", 27604 argLen: 2, 27605 asm: wasm.AI64DivU, 27606 reg: regInfo{ 27607 inputs: []inputInfo{ 27608 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27609 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27610 }, 27611 outputs: []outputInfo{ 27612 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27613 }, 27614 }, 27615 }, 27616 { 27617 name: "I64RemS", 27618 argLen: 2, 27619 asm: wasm.AI64RemS, 27620 reg: regInfo{ 27621 inputs: []inputInfo{ 27622 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27623 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27624 }, 27625 outputs: []outputInfo{ 27626 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27627 }, 27628 }, 27629 }, 27630 { 27631 name: "I64RemU", 27632 argLen: 2, 27633 asm: wasm.AI64RemU, 27634 reg: regInfo{ 27635 inputs: []inputInfo{ 27636 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27637 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27638 }, 27639 outputs: []outputInfo{ 27640 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27641 }, 27642 }, 27643 }, 27644 { 27645 name: "I64And", 27646 argLen: 2, 27647 asm: wasm.AI64And, 27648 reg: regInfo{ 27649 inputs: []inputInfo{ 27650 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27651 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27652 }, 27653 outputs: []outputInfo{ 27654 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27655 }, 27656 }, 27657 }, 27658 { 27659 name: "I64Or", 27660 argLen: 2, 27661 asm: wasm.AI64Or, 27662 reg: regInfo{ 27663 inputs: []inputInfo{ 27664 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27665 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27666 }, 27667 outputs: []outputInfo{ 27668 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27669 }, 27670 }, 27671 }, 27672 { 27673 name: "I64Xor", 27674 argLen: 2, 27675 asm: wasm.AI64Xor, 27676 reg: regInfo{ 27677 inputs: []inputInfo{ 27678 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27679 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27680 }, 27681 outputs: []outputInfo{ 27682 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27683 }, 27684 }, 27685 }, 27686 { 27687 name: "I64Shl", 27688 argLen: 2, 27689 asm: wasm.AI64Shl, 27690 reg: regInfo{ 27691 inputs: []inputInfo{ 27692 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27693 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27694 }, 27695 outputs: []outputInfo{ 27696 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27697 }, 27698 }, 27699 }, 27700 { 27701 name: "I64ShrS", 27702 argLen: 2, 27703 asm: wasm.AI64ShrS, 27704 reg: regInfo{ 27705 inputs: []inputInfo{ 27706 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27707 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27708 }, 27709 outputs: []outputInfo{ 27710 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27711 }, 27712 }, 27713 }, 27714 { 27715 name: "I64ShrU", 27716 argLen: 2, 27717 asm: wasm.AI64ShrU, 27718 reg: regInfo{ 27719 inputs: []inputInfo{ 27720 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27721 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27722 }, 27723 outputs: []outputInfo{ 27724 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27725 }, 27726 }, 27727 }, 27728 { 27729 name: "F64Neg", 27730 argLen: 1, 27731 asm: wasm.AF64Neg, 27732 reg: regInfo{ 27733 inputs: []inputInfo{ 27734 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27735 }, 27736 outputs: []outputInfo{ 27737 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27738 }, 27739 }, 27740 }, 27741 { 27742 name: "F64Add", 27743 argLen: 2, 27744 asm: wasm.AF64Add, 27745 reg: regInfo{ 27746 inputs: []inputInfo{ 27747 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27748 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27749 }, 27750 outputs: []outputInfo{ 27751 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27752 }, 27753 }, 27754 }, 27755 { 27756 name: "F64Sub", 27757 argLen: 2, 27758 asm: wasm.AF64Sub, 27759 reg: regInfo{ 27760 inputs: []inputInfo{ 27761 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27762 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27763 }, 27764 outputs: []outputInfo{ 27765 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27766 }, 27767 }, 27768 }, 27769 { 27770 name: "F64Mul", 27771 argLen: 2, 27772 asm: wasm.AF64Mul, 27773 reg: regInfo{ 27774 inputs: []inputInfo{ 27775 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27776 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27777 }, 27778 outputs: []outputInfo{ 27779 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27780 }, 27781 }, 27782 }, 27783 { 27784 name: "F64Div", 27785 argLen: 2, 27786 asm: wasm.AF64Div, 27787 reg: regInfo{ 27788 inputs: []inputInfo{ 27789 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27790 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27791 }, 27792 outputs: []outputInfo{ 27793 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27794 }, 27795 }, 27796 }, 27797 { 27798 name: "I64TruncSF64", 27799 argLen: 1, 27800 asm: wasm.AI64TruncSF64, 27801 reg: regInfo{ 27802 inputs: []inputInfo{ 27803 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27804 }, 27805 outputs: []outputInfo{ 27806 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27807 }, 27808 }, 27809 }, 27810 { 27811 name: "I64TruncUF64", 27812 argLen: 1, 27813 asm: wasm.AI64TruncUF64, 27814 reg: regInfo{ 27815 inputs: []inputInfo{ 27816 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27817 }, 27818 outputs: []outputInfo{ 27819 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27820 }, 27821 }, 27822 }, 27823 { 27824 name: "F64ConvertSI64", 27825 argLen: 1, 27826 asm: wasm.AF64ConvertSI64, 27827 reg: regInfo{ 27828 inputs: []inputInfo{ 27829 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27830 }, 27831 outputs: []outputInfo{ 27832 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27833 }, 27834 }, 27835 }, 27836 { 27837 name: "F64ConvertUI64", 27838 argLen: 1, 27839 asm: wasm.AF64ConvertUI64, 27840 reg: regInfo{ 27841 inputs: []inputInfo{ 27842 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27843 }, 27844 outputs: []outputInfo{ 27845 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27846 }, 27847 }, 27848 }, 27849 27850 { 27851 name: "Add8", 27852 argLen: 2, 27853 commutative: true, 27854 generic: true, 27855 }, 27856 { 27857 name: "Add16", 27858 argLen: 2, 27859 commutative: true, 27860 generic: true, 27861 }, 27862 { 27863 name: "Add32", 27864 argLen: 2, 27865 commutative: true, 27866 generic: true, 27867 }, 27868 { 27869 name: "Add64", 27870 argLen: 2, 27871 commutative: true, 27872 generic: true, 27873 }, 27874 { 27875 name: "AddPtr", 27876 argLen: 2, 27877 generic: true, 27878 }, 27879 { 27880 name: "Add32F", 27881 argLen: 2, 27882 commutative: true, 27883 generic: true, 27884 }, 27885 { 27886 name: "Add64F", 27887 argLen: 2, 27888 commutative: true, 27889 generic: true, 27890 }, 27891 { 27892 name: "Sub8", 27893 argLen: 2, 27894 generic: true, 27895 }, 27896 { 27897 name: "Sub16", 27898 argLen: 2, 27899 generic: true, 27900 }, 27901 { 27902 name: "Sub32", 27903 argLen: 2, 27904 generic: true, 27905 }, 27906 { 27907 name: "Sub64", 27908 argLen: 2, 27909 generic: true, 27910 }, 27911 { 27912 name: "SubPtr", 27913 argLen: 2, 27914 generic: true, 27915 }, 27916 { 27917 name: "Sub32F", 27918 argLen: 2, 27919 generic: true, 27920 }, 27921 { 27922 name: "Sub64F", 27923 argLen: 2, 27924 generic: true, 27925 }, 27926 { 27927 name: "Mul8", 27928 argLen: 2, 27929 commutative: true, 27930 generic: true, 27931 }, 27932 { 27933 name: "Mul16", 27934 argLen: 2, 27935 commutative: true, 27936 generic: true, 27937 }, 27938 { 27939 name: "Mul32", 27940 argLen: 2, 27941 commutative: true, 27942 generic: true, 27943 }, 27944 { 27945 name: "Mul64", 27946 argLen: 2, 27947 commutative: true, 27948 generic: true, 27949 }, 27950 { 27951 name: "Mul32F", 27952 argLen: 2, 27953 commutative: true, 27954 generic: true, 27955 }, 27956 { 27957 name: "Mul64F", 27958 argLen: 2, 27959 commutative: true, 27960 generic: true, 27961 }, 27962 { 27963 name: "Div32F", 27964 argLen: 2, 27965 generic: true, 27966 }, 27967 { 27968 name: "Div64F", 27969 argLen: 2, 27970 generic: true, 27971 }, 27972 { 27973 name: "Hmul32", 27974 argLen: 2, 27975 commutative: true, 27976 generic: true, 27977 }, 27978 { 27979 name: "Hmul32u", 27980 argLen: 2, 27981 commutative: true, 27982 generic: true, 27983 }, 27984 { 27985 name: "Hmul64", 27986 argLen: 2, 27987 commutative: true, 27988 generic: true, 27989 }, 27990 { 27991 name: "Hmul64u", 27992 argLen: 2, 27993 commutative: true, 27994 generic: true, 27995 }, 27996 { 27997 name: "Mul32uhilo", 27998 argLen: 2, 27999 commutative: true, 28000 generic: true, 28001 }, 28002 { 28003 name: "Mul64uhilo", 28004 argLen: 2, 28005 commutative: true, 28006 generic: true, 28007 }, 28008 { 28009 name: "Mul32uover", 28010 argLen: 2, 28011 commutative: true, 28012 generic: true, 28013 }, 28014 { 28015 name: "Mul64uover", 28016 argLen: 2, 28017 commutative: true, 28018 generic: true, 28019 }, 28020 { 28021 name: "Avg32u", 28022 argLen: 2, 28023 generic: true, 28024 }, 28025 { 28026 name: "Avg64u", 28027 argLen: 2, 28028 generic: true, 28029 }, 28030 { 28031 name: "Div8", 28032 argLen: 2, 28033 generic: true, 28034 }, 28035 { 28036 name: "Div8u", 28037 argLen: 2, 28038 generic: true, 28039 }, 28040 { 28041 name: "Div16", 28042 auxType: auxBool, 28043 argLen: 2, 28044 generic: true, 28045 }, 28046 { 28047 name: "Div16u", 28048 argLen: 2, 28049 generic: true, 28050 }, 28051 { 28052 name: "Div32", 28053 auxType: auxBool, 28054 argLen: 2, 28055 generic: true, 28056 }, 28057 { 28058 name: "Div32u", 28059 argLen: 2, 28060 generic: true, 28061 }, 28062 { 28063 name: "Div64", 28064 auxType: auxBool, 28065 argLen: 2, 28066 generic: true, 28067 }, 28068 { 28069 name: "Div64u", 28070 argLen: 2, 28071 generic: true, 28072 }, 28073 { 28074 name: "Div128u", 28075 argLen: 3, 28076 generic: true, 28077 }, 28078 { 28079 name: "Mod8", 28080 argLen: 2, 28081 generic: true, 28082 }, 28083 { 28084 name: "Mod8u", 28085 argLen: 2, 28086 generic: true, 28087 }, 28088 { 28089 name: "Mod16", 28090 auxType: auxBool, 28091 argLen: 2, 28092 generic: true, 28093 }, 28094 { 28095 name: "Mod16u", 28096 argLen: 2, 28097 generic: true, 28098 }, 28099 { 28100 name: "Mod32", 28101 auxType: auxBool, 28102 argLen: 2, 28103 generic: true, 28104 }, 28105 { 28106 name: "Mod32u", 28107 argLen: 2, 28108 generic: true, 28109 }, 28110 { 28111 name: "Mod64", 28112 auxType: auxBool, 28113 argLen: 2, 28114 generic: true, 28115 }, 28116 { 28117 name: "Mod64u", 28118 argLen: 2, 28119 generic: true, 28120 }, 28121 { 28122 name: "And8", 28123 argLen: 2, 28124 commutative: true, 28125 generic: true, 28126 }, 28127 { 28128 name: "And16", 28129 argLen: 2, 28130 commutative: true, 28131 generic: true, 28132 }, 28133 { 28134 name: "And32", 28135 argLen: 2, 28136 commutative: true, 28137 generic: true, 28138 }, 28139 { 28140 name: "And64", 28141 argLen: 2, 28142 commutative: true, 28143 generic: true, 28144 }, 28145 { 28146 name: "Or8", 28147 argLen: 2, 28148 commutative: true, 28149 generic: true, 28150 }, 28151 { 28152 name: "Or16", 28153 argLen: 2, 28154 commutative: true, 28155 generic: true, 28156 }, 28157 { 28158 name: "Or32", 28159 argLen: 2, 28160 commutative: true, 28161 generic: true, 28162 }, 28163 { 28164 name: "Or64", 28165 argLen: 2, 28166 commutative: true, 28167 generic: true, 28168 }, 28169 { 28170 name: "Xor8", 28171 argLen: 2, 28172 commutative: true, 28173 generic: true, 28174 }, 28175 { 28176 name: "Xor16", 28177 argLen: 2, 28178 commutative: true, 28179 generic: true, 28180 }, 28181 { 28182 name: "Xor32", 28183 argLen: 2, 28184 commutative: true, 28185 generic: true, 28186 }, 28187 { 28188 name: "Xor64", 28189 argLen: 2, 28190 commutative: true, 28191 generic: true, 28192 }, 28193 { 28194 name: "Lsh8x8", 28195 auxType: auxBool, 28196 argLen: 2, 28197 generic: true, 28198 }, 28199 { 28200 name: "Lsh8x16", 28201 auxType: auxBool, 28202 argLen: 2, 28203 generic: true, 28204 }, 28205 { 28206 name: "Lsh8x32", 28207 auxType: auxBool, 28208 argLen: 2, 28209 generic: true, 28210 }, 28211 { 28212 name: "Lsh8x64", 28213 auxType: auxBool, 28214 argLen: 2, 28215 generic: true, 28216 }, 28217 { 28218 name: "Lsh16x8", 28219 auxType: auxBool, 28220 argLen: 2, 28221 generic: true, 28222 }, 28223 { 28224 name: "Lsh16x16", 28225 auxType: auxBool, 28226 argLen: 2, 28227 generic: true, 28228 }, 28229 { 28230 name: "Lsh16x32", 28231 auxType: auxBool, 28232 argLen: 2, 28233 generic: true, 28234 }, 28235 { 28236 name: "Lsh16x64", 28237 auxType: auxBool, 28238 argLen: 2, 28239 generic: true, 28240 }, 28241 { 28242 name: "Lsh32x8", 28243 auxType: auxBool, 28244 argLen: 2, 28245 generic: true, 28246 }, 28247 { 28248 name: "Lsh32x16", 28249 auxType: auxBool, 28250 argLen: 2, 28251 generic: true, 28252 }, 28253 { 28254 name: "Lsh32x32", 28255 auxType: auxBool, 28256 argLen: 2, 28257 generic: true, 28258 }, 28259 { 28260 name: "Lsh32x64", 28261 auxType: auxBool, 28262 argLen: 2, 28263 generic: true, 28264 }, 28265 { 28266 name: "Lsh64x8", 28267 auxType: auxBool, 28268 argLen: 2, 28269 generic: true, 28270 }, 28271 { 28272 name: "Lsh64x16", 28273 auxType: auxBool, 28274 argLen: 2, 28275 generic: true, 28276 }, 28277 { 28278 name: "Lsh64x32", 28279 auxType: auxBool, 28280 argLen: 2, 28281 generic: true, 28282 }, 28283 { 28284 name: "Lsh64x64", 28285 auxType: auxBool, 28286 argLen: 2, 28287 generic: true, 28288 }, 28289 { 28290 name: "Rsh8x8", 28291 auxType: auxBool, 28292 argLen: 2, 28293 generic: true, 28294 }, 28295 { 28296 name: "Rsh8x16", 28297 auxType: auxBool, 28298 argLen: 2, 28299 generic: true, 28300 }, 28301 { 28302 name: "Rsh8x32", 28303 auxType: auxBool, 28304 argLen: 2, 28305 generic: true, 28306 }, 28307 { 28308 name: "Rsh8x64", 28309 auxType: auxBool, 28310 argLen: 2, 28311 generic: true, 28312 }, 28313 { 28314 name: "Rsh16x8", 28315 auxType: auxBool, 28316 argLen: 2, 28317 generic: true, 28318 }, 28319 { 28320 name: "Rsh16x16", 28321 auxType: auxBool, 28322 argLen: 2, 28323 generic: true, 28324 }, 28325 { 28326 name: "Rsh16x32", 28327 auxType: auxBool, 28328 argLen: 2, 28329 generic: true, 28330 }, 28331 { 28332 name: "Rsh16x64", 28333 auxType: auxBool, 28334 argLen: 2, 28335 generic: true, 28336 }, 28337 { 28338 name: "Rsh32x8", 28339 auxType: auxBool, 28340 argLen: 2, 28341 generic: true, 28342 }, 28343 { 28344 name: "Rsh32x16", 28345 auxType: auxBool, 28346 argLen: 2, 28347 generic: true, 28348 }, 28349 { 28350 name: "Rsh32x32", 28351 auxType: auxBool, 28352 argLen: 2, 28353 generic: true, 28354 }, 28355 { 28356 name: "Rsh32x64", 28357 auxType: auxBool, 28358 argLen: 2, 28359 generic: true, 28360 }, 28361 { 28362 name: "Rsh64x8", 28363 auxType: auxBool, 28364 argLen: 2, 28365 generic: true, 28366 }, 28367 { 28368 name: "Rsh64x16", 28369 auxType: auxBool, 28370 argLen: 2, 28371 generic: true, 28372 }, 28373 { 28374 name: "Rsh64x32", 28375 auxType: auxBool, 28376 argLen: 2, 28377 generic: true, 28378 }, 28379 { 28380 name: "Rsh64x64", 28381 auxType: auxBool, 28382 argLen: 2, 28383 generic: true, 28384 }, 28385 { 28386 name: "Rsh8Ux8", 28387 auxType: auxBool, 28388 argLen: 2, 28389 generic: true, 28390 }, 28391 { 28392 name: "Rsh8Ux16", 28393 auxType: auxBool, 28394 argLen: 2, 28395 generic: true, 28396 }, 28397 { 28398 name: "Rsh8Ux32", 28399 auxType: auxBool, 28400 argLen: 2, 28401 generic: true, 28402 }, 28403 { 28404 name: "Rsh8Ux64", 28405 auxType: auxBool, 28406 argLen: 2, 28407 generic: true, 28408 }, 28409 { 28410 name: "Rsh16Ux8", 28411 auxType: auxBool, 28412 argLen: 2, 28413 generic: true, 28414 }, 28415 { 28416 name: "Rsh16Ux16", 28417 auxType: auxBool, 28418 argLen: 2, 28419 generic: true, 28420 }, 28421 { 28422 name: "Rsh16Ux32", 28423 auxType: auxBool, 28424 argLen: 2, 28425 generic: true, 28426 }, 28427 { 28428 name: "Rsh16Ux64", 28429 auxType: auxBool, 28430 argLen: 2, 28431 generic: true, 28432 }, 28433 { 28434 name: "Rsh32Ux8", 28435 auxType: auxBool, 28436 argLen: 2, 28437 generic: true, 28438 }, 28439 { 28440 name: "Rsh32Ux16", 28441 auxType: auxBool, 28442 argLen: 2, 28443 generic: true, 28444 }, 28445 { 28446 name: "Rsh32Ux32", 28447 auxType: auxBool, 28448 argLen: 2, 28449 generic: true, 28450 }, 28451 { 28452 name: "Rsh32Ux64", 28453 auxType: auxBool, 28454 argLen: 2, 28455 generic: true, 28456 }, 28457 { 28458 name: "Rsh64Ux8", 28459 auxType: auxBool, 28460 argLen: 2, 28461 generic: true, 28462 }, 28463 { 28464 name: "Rsh64Ux16", 28465 auxType: auxBool, 28466 argLen: 2, 28467 generic: true, 28468 }, 28469 { 28470 name: "Rsh64Ux32", 28471 auxType: auxBool, 28472 argLen: 2, 28473 generic: true, 28474 }, 28475 { 28476 name: "Rsh64Ux64", 28477 auxType: auxBool, 28478 argLen: 2, 28479 generic: true, 28480 }, 28481 { 28482 name: "Eq8", 28483 argLen: 2, 28484 commutative: true, 28485 generic: true, 28486 }, 28487 { 28488 name: "Eq16", 28489 argLen: 2, 28490 commutative: true, 28491 generic: true, 28492 }, 28493 { 28494 name: "Eq32", 28495 argLen: 2, 28496 commutative: true, 28497 generic: true, 28498 }, 28499 { 28500 name: "Eq64", 28501 argLen: 2, 28502 commutative: true, 28503 generic: true, 28504 }, 28505 { 28506 name: "EqPtr", 28507 argLen: 2, 28508 commutative: true, 28509 generic: true, 28510 }, 28511 { 28512 name: "EqInter", 28513 argLen: 2, 28514 generic: true, 28515 }, 28516 { 28517 name: "EqSlice", 28518 argLen: 2, 28519 generic: true, 28520 }, 28521 { 28522 name: "Eq32F", 28523 argLen: 2, 28524 commutative: true, 28525 generic: true, 28526 }, 28527 { 28528 name: "Eq64F", 28529 argLen: 2, 28530 commutative: true, 28531 generic: true, 28532 }, 28533 { 28534 name: "Neq8", 28535 argLen: 2, 28536 commutative: true, 28537 generic: true, 28538 }, 28539 { 28540 name: "Neq16", 28541 argLen: 2, 28542 commutative: true, 28543 generic: true, 28544 }, 28545 { 28546 name: "Neq32", 28547 argLen: 2, 28548 commutative: true, 28549 generic: true, 28550 }, 28551 { 28552 name: "Neq64", 28553 argLen: 2, 28554 commutative: true, 28555 generic: true, 28556 }, 28557 { 28558 name: "NeqPtr", 28559 argLen: 2, 28560 commutative: true, 28561 generic: true, 28562 }, 28563 { 28564 name: "NeqInter", 28565 argLen: 2, 28566 generic: true, 28567 }, 28568 { 28569 name: "NeqSlice", 28570 argLen: 2, 28571 generic: true, 28572 }, 28573 { 28574 name: "Neq32F", 28575 argLen: 2, 28576 commutative: true, 28577 generic: true, 28578 }, 28579 { 28580 name: "Neq64F", 28581 argLen: 2, 28582 commutative: true, 28583 generic: true, 28584 }, 28585 { 28586 name: "Less8", 28587 argLen: 2, 28588 generic: true, 28589 }, 28590 { 28591 name: "Less8U", 28592 argLen: 2, 28593 generic: true, 28594 }, 28595 { 28596 name: "Less16", 28597 argLen: 2, 28598 generic: true, 28599 }, 28600 { 28601 name: "Less16U", 28602 argLen: 2, 28603 generic: true, 28604 }, 28605 { 28606 name: "Less32", 28607 argLen: 2, 28608 generic: true, 28609 }, 28610 { 28611 name: "Less32U", 28612 argLen: 2, 28613 generic: true, 28614 }, 28615 { 28616 name: "Less64", 28617 argLen: 2, 28618 generic: true, 28619 }, 28620 { 28621 name: "Less64U", 28622 argLen: 2, 28623 generic: true, 28624 }, 28625 { 28626 name: "Less32F", 28627 argLen: 2, 28628 generic: true, 28629 }, 28630 { 28631 name: "Less64F", 28632 argLen: 2, 28633 generic: true, 28634 }, 28635 { 28636 name: "Leq8", 28637 argLen: 2, 28638 generic: true, 28639 }, 28640 { 28641 name: "Leq8U", 28642 argLen: 2, 28643 generic: true, 28644 }, 28645 { 28646 name: "Leq16", 28647 argLen: 2, 28648 generic: true, 28649 }, 28650 { 28651 name: "Leq16U", 28652 argLen: 2, 28653 generic: true, 28654 }, 28655 { 28656 name: "Leq32", 28657 argLen: 2, 28658 generic: true, 28659 }, 28660 { 28661 name: "Leq32U", 28662 argLen: 2, 28663 generic: true, 28664 }, 28665 { 28666 name: "Leq64", 28667 argLen: 2, 28668 generic: true, 28669 }, 28670 { 28671 name: "Leq64U", 28672 argLen: 2, 28673 generic: true, 28674 }, 28675 { 28676 name: "Leq32F", 28677 argLen: 2, 28678 generic: true, 28679 }, 28680 { 28681 name: "Leq64F", 28682 argLen: 2, 28683 generic: true, 28684 }, 28685 { 28686 name: "Greater8", 28687 argLen: 2, 28688 generic: true, 28689 }, 28690 { 28691 name: "Greater8U", 28692 argLen: 2, 28693 generic: true, 28694 }, 28695 { 28696 name: "Greater16", 28697 argLen: 2, 28698 generic: true, 28699 }, 28700 { 28701 name: "Greater16U", 28702 argLen: 2, 28703 generic: true, 28704 }, 28705 { 28706 name: "Greater32", 28707 argLen: 2, 28708 generic: true, 28709 }, 28710 { 28711 name: "Greater32U", 28712 argLen: 2, 28713 generic: true, 28714 }, 28715 { 28716 name: "Greater64", 28717 argLen: 2, 28718 generic: true, 28719 }, 28720 { 28721 name: "Greater64U", 28722 argLen: 2, 28723 generic: true, 28724 }, 28725 { 28726 name: "Greater32F", 28727 argLen: 2, 28728 generic: true, 28729 }, 28730 { 28731 name: "Greater64F", 28732 argLen: 2, 28733 generic: true, 28734 }, 28735 { 28736 name: "Geq8", 28737 argLen: 2, 28738 generic: true, 28739 }, 28740 { 28741 name: "Geq8U", 28742 argLen: 2, 28743 generic: true, 28744 }, 28745 { 28746 name: "Geq16", 28747 argLen: 2, 28748 generic: true, 28749 }, 28750 { 28751 name: "Geq16U", 28752 argLen: 2, 28753 generic: true, 28754 }, 28755 { 28756 name: "Geq32", 28757 argLen: 2, 28758 generic: true, 28759 }, 28760 { 28761 name: "Geq32U", 28762 argLen: 2, 28763 generic: true, 28764 }, 28765 { 28766 name: "Geq64", 28767 argLen: 2, 28768 generic: true, 28769 }, 28770 { 28771 name: "Geq64U", 28772 argLen: 2, 28773 generic: true, 28774 }, 28775 { 28776 name: "Geq32F", 28777 argLen: 2, 28778 generic: true, 28779 }, 28780 { 28781 name: "Geq64F", 28782 argLen: 2, 28783 generic: true, 28784 }, 28785 { 28786 name: "CondSelect", 28787 argLen: 3, 28788 generic: true, 28789 }, 28790 { 28791 name: "AndB", 28792 argLen: 2, 28793 commutative: true, 28794 generic: true, 28795 }, 28796 { 28797 name: "OrB", 28798 argLen: 2, 28799 commutative: true, 28800 generic: true, 28801 }, 28802 { 28803 name: "EqB", 28804 argLen: 2, 28805 commutative: true, 28806 generic: true, 28807 }, 28808 { 28809 name: "NeqB", 28810 argLen: 2, 28811 commutative: true, 28812 generic: true, 28813 }, 28814 { 28815 name: "Not", 28816 argLen: 1, 28817 generic: true, 28818 }, 28819 { 28820 name: "Neg8", 28821 argLen: 1, 28822 generic: true, 28823 }, 28824 { 28825 name: "Neg16", 28826 argLen: 1, 28827 generic: true, 28828 }, 28829 { 28830 name: "Neg32", 28831 argLen: 1, 28832 generic: true, 28833 }, 28834 { 28835 name: "Neg64", 28836 argLen: 1, 28837 generic: true, 28838 }, 28839 { 28840 name: "Neg32F", 28841 argLen: 1, 28842 generic: true, 28843 }, 28844 { 28845 name: "Neg64F", 28846 argLen: 1, 28847 generic: true, 28848 }, 28849 { 28850 name: "Com8", 28851 argLen: 1, 28852 generic: true, 28853 }, 28854 { 28855 name: "Com16", 28856 argLen: 1, 28857 generic: true, 28858 }, 28859 { 28860 name: "Com32", 28861 argLen: 1, 28862 generic: true, 28863 }, 28864 { 28865 name: "Com64", 28866 argLen: 1, 28867 generic: true, 28868 }, 28869 { 28870 name: "Ctz8", 28871 argLen: 1, 28872 generic: true, 28873 }, 28874 { 28875 name: "Ctz16", 28876 argLen: 1, 28877 generic: true, 28878 }, 28879 { 28880 name: "Ctz32", 28881 argLen: 1, 28882 generic: true, 28883 }, 28884 { 28885 name: "Ctz64", 28886 argLen: 1, 28887 generic: true, 28888 }, 28889 { 28890 name: "Ctz8NonZero", 28891 argLen: 1, 28892 generic: true, 28893 }, 28894 { 28895 name: "Ctz16NonZero", 28896 argLen: 1, 28897 generic: true, 28898 }, 28899 { 28900 name: "Ctz32NonZero", 28901 argLen: 1, 28902 generic: true, 28903 }, 28904 { 28905 name: "Ctz64NonZero", 28906 argLen: 1, 28907 generic: true, 28908 }, 28909 { 28910 name: "BitLen8", 28911 argLen: 1, 28912 generic: true, 28913 }, 28914 { 28915 name: "BitLen16", 28916 argLen: 1, 28917 generic: true, 28918 }, 28919 { 28920 name: "BitLen32", 28921 argLen: 1, 28922 generic: true, 28923 }, 28924 { 28925 name: "BitLen64", 28926 argLen: 1, 28927 generic: true, 28928 }, 28929 { 28930 name: "Bswap32", 28931 argLen: 1, 28932 generic: true, 28933 }, 28934 { 28935 name: "Bswap64", 28936 argLen: 1, 28937 generic: true, 28938 }, 28939 { 28940 name: "BitRev8", 28941 argLen: 1, 28942 generic: true, 28943 }, 28944 { 28945 name: "BitRev16", 28946 argLen: 1, 28947 generic: true, 28948 }, 28949 { 28950 name: "BitRev32", 28951 argLen: 1, 28952 generic: true, 28953 }, 28954 { 28955 name: "BitRev64", 28956 argLen: 1, 28957 generic: true, 28958 }, 28959 { 28960 name: "PopCount8", 28961 argLen: 1, 28962 generic: true, 28963 }, 28964 { 28965 name: "PopCount16", 28966 argLen: 1, 28967 generic: true, 28968 }, 28969 { 28970 name: "PopCount32", 28971 argLen: 1, 28972 generic: true, 28973 }, 28974 { 28975 name: "PopCount64", 28976 argLen: 1, 28977 generic: true, 28978 }, 28979 { 28980 name: "RotateLeft8", 28981 argLen: 2, 28982 generic: true, 28983 }, 28984 { 28985 name: "RotateLeft16", 28986 argLen: 2, 28987 generic: true, 28988 }, 28989 { 28990 name: "RotateLeft32", 28991 argLen: 2, 28992 generic: true, 28993 }, 28994 { 28995 name: "RotateLeft64", 28996 argLen: 2, 28997 generic: true, 28998 }, 28999 { 29000 name: "Sqrt", 29001 argLen: 1, 29002 generic: true, 29003 }, 29004 { 29005 name: "Floor", 29006 argLen: 1, 29007 generic: true, 29008 }, 29009 { 29010 name: "Ceil", 29011 argLen: 1, 29012 generic: true, 29013 }, 29014 { 29015 name: "Trunc", 29016 argLen: 1, 29017 generic: true, 29018 }, 29019 { 29020 name: "Round", 29021 argLen: 1, 29022 generic: true, 29023 }, 29024 { 29025 name: "RoundToEven", 29026 argLen: 1, 29027 generic: true, 29028 }, 29029 { 29030 name: "Abs", 29031 argLen: 1, 29032 generic: true, 29033 }, 29034 { 29035 name: "Copysign", 29036 argLen: 2, 29037 generic: true, 29038 }, 29039 { 29040 name: "Phi", 29041 argLen: -1, 29042 zeroWidth: true, 29043 generic: true, 29044 }, 29045 { 29046 name: "Copy", 29047 argLen: 1, 29048 generic: true, 29049 }, 29050 { 29051 name: "Convert", 29052 argLen: 2, 29053 resultInArg0: true, 29054 zeroWidth: true, 29055 generic: true, 29056 }, 29057 { 29058 name: "ConstBool", 29059 auxType: auxBool, 29060 argLen: 0, 29061 generic: true, 29062 }, 29063 { 29064 name: "ConstString", 29065 auxType: auxString, 29066 argLen: 0, 29067 generic: true, 29068 }, 29069 { 29070 name: "ConstNil", 29071 argLen: 0, 29072 generic: true, 29073 }, 29074 { 29075 name: "Const8", 29076 auxType: auxInt8, 29077 argLen: 0, 29078 generic: true, 29079 }, 29080 { 29081 name: "Const16", 29082 auxType: auxInt16, 29083 argLen: 0, 29084 generic: true, 29085 }, 29086 { 29087 name: "Const32", 29088 auxType: auxInt32, 29089 argLen: 0, 29090 generic: true, 29091 }, 29092 { 29093 name: "Const64", 29094 auxType: auxInt64, 29095 argLen: 0, 29096 generic: true, 29097 }, 29098 { 29099 name: "Const32F", 29100 auxType: auxFloat32, 29101 argLen: 0, 29102 generic: true, 29103 }, 29104 { 29105 name: "Const64F", 29106 auxType: auxFloat64, 29107 argLen: 0, 29108 generic: true, 29109 }, 29110 { 29111 name: "ConstInterface", 29112 argLen: 0, 29113 generic: true, 29114 }, 29115 { 29116 name: "ConstSlice", 29117 argLen: 0, 29118 generic: true, 29119 }, 29120 { 29121 name: "InitMem", 29122 argLen: 0, 29123 zeroWidth: true, 29124 generic: true, 29125 }, 29126 { 29127 name: "Arg", 29128 auxType: auxSymOff, 29129 argLen: 0, 29130 zeroWidth: true, 29131 symEffect: SymRead, 29132 generic: true, 29133 }, 29134 { 29135 name: "Addr", 29136 auxType: auxSym, 29137 argLen: 1, 29138 symEffect: SymAddr, 29139 generic: true, 29140 }, 29141 { 29142 name: "LocalAddr", 29143 auxType: auxSym, 29144 argLen: 2, 29145 symEffect: SymAddr, 29146 generic: true, 29147 }, 29148 { 29149 name: "SP", 29150 argLen: 0, 29151 zeroWidth: true, 29152 generic: true, 29153 }, 29154 { 29155 name: "SB", 29156 argLen: 0, 29157 zeroWidth: true, 29158 generic: true, 29159 }, 29160 { 29161 name: "Load", 29162 argLen: 2, 29163 generic: true, 29164 }, 29165 { 29166 name: "Store", 29167 auxType: auxTyp, 29168 argLen: 3, 29169 generic: true, 29170 }, 29171 { 29172 name: "Move", 29173 auxType: auxTypSize, 29174 argLen: 3, 29175 generic: true, 29176 }, 29177 { 29178 name: "Zero", 29179 auxType: auxTypSize, 29180 argLen: 2, 29181 generic: true, 29182 }, 29183 { 29184 name: "StoreWB", 29185 auxType: auxTyp, 29186 argLen: 3, 29187 generic: true, 29188 }, 29189 { 29190 name: "MoveWB", 29191 auxType: auxTypSize, 29192 argLen: 3, 29193 generic: true, 29194 }, 29195 { 29196 name: "ZeroWB", 29197 auxType: auxTypSize, 29198 argLen: 2, 29199 generic: true, 29200 }, 29201 { 29202 name: "WB", 29203 auxType: auxSym, 29204 argLen: 3, 29205 symEffect: SymNone, 29206 generic: true, 29207 }, 29208 { 29209 name: "ClosureCall", 29210 auxType: auxInt64, 29211 argLen: 3, 29212 call: true, 29213 generic: true, 29214 }, 29215 { 29216 name: "StaticCall", 29217 auxType: auxSymOff, 29218 argLen: 1, 29219 call: true, 29220 symEffect: SymNone, 29221 generic: true, 29222 }, 29223 { 29224 name: "InterCall", 29225 auxType: auxInt64, 29226 argLen: 2, 29227 call: true, 29228 generic: true, 29229 }, 29230 { 29231 name: "SignExt8to16", 29232 argLen: 1, 29233 generic: true, 29234 }, 29235 { 29236 name: "SignExt8to32", 29237 argLen: 1, 29238 generic: true, 29239 }, 29240 { 29241 name: "SignExt8to64", 29242 argLen: 1, 29243 generic: true, 29244 }, 29245 { 29246 name: "SignExt16to32", 29247 argLen: 1, 29248 generic: true, 29249 }, 29250 { 29251 name: "SignExt16to64", 29252 argLen: 1, 29253 generic: true, 29254 }, 29255 { 29256 name: "SignExt32to64", 29257 argLen: 1, 29258 generic: true, 29259 }, 29260 { 29261 name: "ZeroExt8to16", 29262 argLen: 1, 29263 generic: true, 29264 }, 29265 { 29266 name: "ZeroExt8to32", 29267 argLen: 1, 29268 generic: true, 29269 }, 29270 { 29271 name: "ZeroExt8to64", 29272 argLen: 1, 29273 generic: true, 29274 }, 29275 { 29276 name: "ZeroExt16to32", 29277 argLen: 1, 29278 generic: true, 29279 }, 29280 { 29281 name: "ZeroExt16to64", 29282 argLen: 1, 29283 generic: true, 29284 }, 29285 { 29286 name: "ZeroExt32to64", 29287 argLen: 1, 29288 generic: true, 29289 }, 29290 { 29291 name: "Trunc16to8", 29292 argLen: 1, 29293 generic: true, 29294 }, 29295 { 29296 name: "Trunc32to8", 29297 argLen: 1, 29298 generic: true, 29299 }, 29300 { 29301 name: "Trunc32to16", 29302 argLen: 1, 29303 generic: true, 29304 }, 29305 { 29306 name: "Trunc64to8", 29307 argLen: 1, 29308 generic: true, 29309 }, 29310 { 29311 name: "Trunc64to16", 29312 argLen: 1, 29313 generic: true, 29314 }, 29315 { 29316 name: "Trunc64to32", 29317 argLen: 1, 29318 generic: true, 29319 }, 29320 { 29321 name: "Cvt32to32F", 29322 argLen: 1, 29323 generic: true, 29324 }, 29325 { 29326 name: "Cvt32to64F", 29327 argLen: 1, 29328 generic: true, 29329 }, 29330 { 29331 name: "Cvt64to32F", 29332 argLen: 1, 29333 generic: true, 29334 }, 29335 { 29336 name: "Cvt64to64F", 29337 argLen: 1, 29338 generic: true, 29339 }, 29340 { 29341 name: "Cvt32Fto32", 29342 argLen: 1, 29343 generic: true, 29344 }, 29345 { 29346 name: "Cvt32Fto64", 29347 argLen: 1, 29348 generic: true, 29349 }, 29350 { 29351 name: "Cvt64Fto32", 29352 argLen: 1, 29353 generic: true, 29354 }, 29355 { 29356 name: "Cvt64Fto64", 29357 argLen: 1, 29358 generic: true, 29359 }, 29360 { 29361 name: "Cvt32Fto64F", 29362 argLen: 1, 29363 generic: true, 29364 }, 29365 { 29366 name: "Cvt64Fto32F", 29367 argLen: 1, 29368 generic: true, 29369 }, 29370 { 29371 name: "Round32F", 29372 argLen: 1, 29373 generic: true, 29374 }, 29375 { 29376 name: "Round64F", 29377 argLen: 1, 29378 generic: true, 29379 }, 29380 { 29381 name: "IsNonNil", 29382 argLen: 1, 29383 generic: true, 29384 }, 29385 { 29386 name: "IsInBounds", 29387 argLen: 2, 29388 generic: true, 29389 }, 29390 { 29391 name: "IsSliceInBounds", 29392 argLen: 2, 29393 generic: true, 29394 }, 29395 { 29396 name: "NilCheck", 29397 argLen: 2, 29398 generic: true, 29399 }, 29400 { 29401 name: "GetG", 29402 argLen: 1, 29403 zeroWidth: true, 29404 generic: true, 29405 }, 29406 { 29407 name: "GetClosurePtr", 29408 argLen: 0, 29409 generic: true, 29410 }, 29411 { 29412 name: "GetCallerPC", 29413 argLen: 0, 29414 generic: true, 29415 }, 29416 { 29417 name: "GetCallerSP", 29418 argLen: 0, 29419 generic: true, 29420 }, 29421 { 29422 name: "PtrIndex", 29423 argLen: 2, 29424 generic: true, 29425 }, 29426 { 29427 name: "OffPtr", 29428 auxType: auxInt64, 29429 argLen: 1, 29430 generic: true, 29431 }, 29432 { 29433 name: "SliceMake", 29434 argLen: 3, 29435 generic: true, 29436 }, 29437 { 29438 name: "SlicePtr", 29439 argLen: 1, 29440 generic: true, 29441 }, 29442 { 29443 name: "SliceLen", 29444 argLen: 1, 29445 generic: true, 29446 }, 29447 { 29448 name: "SliceCap", 29449 argLen: 1, 29450 generic: true, 29451 }, 29452 { 29453 name: "ComplexMake", 29454 argLen: 2, 29455 generic: true, 29456 }, 29457 { 29458 name: "ComplexReal", 29459 argLen: 1, 29460 generic: true, 29461 }, 29462 { 29463 name: "ComplexImag", 29464 argLen: 1, 29465 generic: true, 29466 }, 29467 { 29468 name: "StringMake", 29469 argLen: 2, 29470 generic: true, 29471 }, 29472 { 29473 name: "StringPtr", 29474 argLen: 1, 29475 generic: true, 29476 }, 29477 { 29478 name: "StringLen", 29479 argLen: 1, 29480 generic: true, 29481 }, 29482 { 29483 name: "IMake", 29484 argLen: 2, 29485 generic: true, 29486 }, 29487 { 29488 name: "ITab", 29489 argLen: 1, 29490 generic: true, 29491 }, 29492 { 29493 name: "IData", 29494 argLen: 1, 29495 generic: true, 29496 }, 29497 { 29498 name: "StructMake0", 29499 argLen: 0, 29500 generic: true, 29501 }, 29502 { 29503 name: "StructMake1", 29504 argLen: 1, 29505 generic: true, 29506 }, 29507 { 29508 name: "StructMake2", 29509 argLen: 2, 29510 generic: true, 29511 }, 29512 { 29513 name: "StructMake3", 29514 argLen: 3, 29515 generic: true, 29516 }, 29517 { 29518 name: "StructMake4", 29519 argLen: 4, 29520 generic: true, 29521 }, 29522 { 29523 name: "StructSelect", 29524 auxType: auxInt64, 29525 argLen: 1, 29526 generic: true, 29527 }, 29528 { 29529 name: "ArrayMake0", 29530 argLen: 0, 29531 generic: true, 29532 }, 29533 { 29534 name: "ArrayMake1", 29535 argLen: 1, 29536 generic: true, 29537 }, 29538 { 29539 name: "ArraySelect", 29540 auxType: auxInt64, 29541 argLen: 1, 29542 generic: true, 29543 }, 29544 { 29545 name: "StoreReg", 29546 argLen: 1, 29547 generic: true, 29548 }, 29549 { 29550 name: "LoadReg", 29551 argLen: 1, 29552 generic: true, 29553 }, 29554 { 29555 name: "FwdRef", 29556 auxType: auxSym, 29557 argLen: 0, 29558 symEffect: SymNone, 29559 generic: true, 29560 }, 29561 { 29562 name: "Unknown", 29563 argLen: 0, 29564 generic: true, 29565 }, 29566 { 29567 name: "VarDef", 29568 auxType: auxSym, 29569 argLen: 1, 29570 zeroWidth: true, 29571 symEffect: SymNone, 29572 generic: true, 29573 }, 29574 { 29575 name: "VarKill", 29576 auxType: auxSym, 29577 argLen: 1, 29578 symEffect: SymNone, 29579 generic: true, 29580 }, 29581 { 29582 name: "VarLive", 29583 auxType: auxSym, 29584 argLen: 1, 29585 zeroWidth: true, 29586 symEffect: SymRead, 29587 generic: true, 29588 }, 29589 { 29590 name: "KeepAlive", 29591 argLen: 2, 29592 zeroWidth: true, 29593 generic: true, 29594 }, 29595 { 29596 name: "Int64Make", 29597 argLen: 2, 29598 generic: true, 29599 }, 29600 { 29601 name: "Int64Hi", 29602 argLen: 1, 29603 generic: true, 29604 }, 29605 { 29606 name: "Int64Lo", 29607 argLen: 1, 29608 generic: true, 29609 }, 29610 { 29611 name: "Add32carry", 29612 argLen: 2, 29613 commutative: true, 29614 generic: true, 29615 }, 29616 { 29617 name: "Add32withcarry", 29618 argLen: 3, 29619 commutative: true, 29620 generic: true, 29621 }, 29622 { 29623 name: "Sub32carry", 29624 argLen: 2, 29625 generic: true, 29626 }, 29627 { 29628 name: "Sub32withcarry", 29629 argLen: 3, 29630 generic: true, 29631 }, 29632 { 29633 name: "Signmask", 29634 argLen: 1, 29635 generic: true, 29636 }, 29637 { 29638 name: "Zeromask", 29639 argLen: 1, 29640 generic: true, 29641 }, 29642 { 29643 name: "Slicemask", 29644 argLen: 1, 29645 generic: true, 29646 }, 29647 { 29648 name: "Cvt32Uto32F", 29649 argLen: 1, 29650 generic: true, 29651 }, 29652 { 29653 name: "Cvt32Uto64F", 29654 argLen: 1, 29655 generic: true, 29656 }, 29657 { 29658 name: "Cvt32Fto32U", 29659 argLen: 1, 29660 generic: true, 29661 }, 29662 { 29663 name: "Cvt64Fto32U", 29664 argLen: 1, 29665 generic: true, 29666 }, 29667 { 29668 name: "Cvt64Uto32F", 29669 argLen: 1, 29670 generic: true, 29671 }, 29672 { 29673 name: "Cvt64Uto64F", 29674 argLen: 1, 29675 generic: true, 29676 }, 29677 { 29678 name: "Cvt32Fto64U", 29679 argLen: 1, 29680 generic: true, 29681 }, 29682 { 29683 name: "Cvt64Fto64U", 29684 argLen: 1, 29685 generic: true, 29686 }, 29687 { 29688 name: "Select0", 29689 argLen: 1, 29690 zeroWidth: true, 29691 generic: true, 29692 }, 29693 { 29694 name: "Select1", 29695 argLen: 1, 29696 zeroWidth: true, 29697 generic: true, 29698 }, 29699 { 29700 name: "AtomicLoad32", 29701 argLen: 2, 29702 generic: true, 29703 }, 29704 { 29705 name: "AtomicLoad64", 29706 argLen: 2, 29707 generic: true, 29708 }, 29709 { 29710 name: "AtomicLoadPtr", 29711 argLen: 2, 29712 generic: true, 29713 }, 29714 { 29715 name: "AtomicLoadAcq32", 29716 argLen: 2, 29717 generic: true, 29718 }, 29719 { 29720 name: "AtomicStore32", 29721 argLen: 3, 29722 hasSideEffects: true, 29723 generic: true, 29724 }, 29725 { 29726 name: "AtomicStore64", 29727 argLen: 3, 29728 hasSideEffects: true, 29729 generic: true, 29730 }, 29731 { 29732 name: "AtomicStorePtrNoWB", 29733 argLen: 3, 29734 hasSideEffects: true, 29735 generic: true, 29736 }, 29737 { 29738 name: "AtomicStoreRel32", 29739 argLen: 3, 29740 hasSideEffects: true, 29741 generic: true, 29742 }, 29743 { 29744 name: "AtomicExchange32", 29745 argLen: 3, 29746 hasSideEffects: true, 29747 generic: true, 29748 }, 29749 { 29750 name: "AtomicExchange64", 29751 argLen: 3, 29752 hasSideEffects: true, 29753 generic: true, 29754 }, 29755 { 29756 name: "AtomicAdd32", 29757 argLen: 3, 29758 hasSideEffects: true, 29759 generic: true, 29760 }, 29761 { 29762 name: "AtomicAdd64", 29763 argLen: 3, 29764 hasSideEffects: true, 29765 generic: true, 29766 }, 29767 { 29768 name: "AtomicCompareAndSwap32", 29769 argLen: 4, 29770 hasSideEffects: true, 29771 generic: true, 29772 }, 29773 { 29774 name: "AtomicCompareAndSwap64", 29775 argLen: 4, 29776 hasSideEffects: true, 29777 generic: true, 29778 }, 29779 { 29780 name: "AtomicCompareAndSwapRel32", 29781 argLen: 4, 29782 hasSideEffects: true, 29783 generic: true, 29784 }, 29785 { 29786 name: "AtomicAnd8", 29787 argLen: 3, 29788 hasSideEffects: true, 29789 generic: true, 29790 }, 29791 { 29792 name: "AtomicOr8", 29793 argLen: 3, 29794 hasSideEffects: true, 29795 generic: true, 29796 }, 29797 { 29798 name: "AtomicAdd32Variant", 29799 argLen: 3, 29800 hasSideEffects: true, 29801 generic: true, 29802 }, 29803 { 29804 name: "AtomicAdd64Variant", 29805 argLen: 3, 29806 hasSideEffects: true, 29807 generic: true, 29808 }, 29809 { 29810 name: "Clobber", 29811 auxType: auxSymOff, 29812 argLen: 0, 29813 symEffect: SymNone, 29814 generic: true, 29815 }, 29816 } 29817 29818 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 29819 func (o Op) String() string { return opcodeTable[o].name } 29820 func (o Op) UsesScratch() bool { return opcodeTable[o].usesScratch } 29821 func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect } 29822 func (o Op) IsCall() bool { return opcodeTable[o].call } 29823 29824 var registers386 = [...]Register{ 29825 {0, x86.REG_AX, 0, "AX"}, 29826 {1, x86.REG_CX, 1, "CX"}, 29827 {2, x86.REG_DX, 2, "DX"}, 29828 {3, x86.REG_BX, 3, "BX"}, 29829 {4, x86.REGSP, -1, "SP"}, 29830 {5, x86.REG_BP, 4, "BP"}, 29831 {6, x86.REG_SI, 5, "SI"}, 29832 {7, x86.REG_DI, 6, "DI"}, 29833 {8, x86.REG_X0, -1, "X0"}, 29834 {9, x86.REG_X1, -1, "X1"}, 29835 {10, x86.REG_X2, -1, "X2"}, 29836 {11, x86.REG_X3, -1, "X3"}, 29837 {12, x86.REG_X4, -1, "X4"}, 29838 {13, x86.REG_X5, -1, "X5"}, 29839 {14, x86.REG_X6, -1, "X6"}, 29840 {15, x86.REG_X7, -1, "X7"}, 29841 {16, 0, -1, "SB"}, 29842 } 29843 var gpRegMask386 = regMask(239) 29844 var fpRegMask386 = regMask(65280) 29845 var specialRegMask386 = regMask(0) 29846 var framepointerReg386 = int8(5) 29847 var linkReg386 = int8(-1) 29848 var registersAMD64 = [...]Register{ 29849 {0, x86.REG_AX, 0, "AX"}, 29850 {1, x86.REG_CX, 1, "CX"}, 29851 {2, x86.REG_DX, 2, "DX"}, 29852 {3, x86.REG_BX, 3, "BX"}, 29853 {4, x86.REGSP, -1, "SP"}, 29854 {5, x86.REG_BP, 4, "BP"}, 29855 {6, x86.REG_SI, 5, "SI"}, 29856 {7, x86.REG_DI, 6, "DI"}, 29857 {8, x86.REG_R8, 7, "R8"}, 29858 {9, x86.REG_R9, 8, "R9"}, 29859 {10, x86.REG_R10, 9, "R10"}, 29860 {11, x86.REG_R11, 10, "R11"}, 29861 {12, x86.REG_R12, 11, "R12"}, 29862 {13, x86.REG_R13, 12, "R13"}, 29863 {14, x86.REG_R14, 13, "R14"}, 29864 {15, x86.REG_R15, 14, "R15"}, 29865 {16, x86.REG_X0, -1, "X0"}, 29866 {17, x86.REG_X1, -1, "X1"}, 29867 {18, x86.REG_X2, -1, "X2"}, 29868 {19, x86.REG_X3, -1, "X3"}, 29869 {20, x86.REG_X4, -1, "X4"}, 29870 {21, x86.REG_X5, -1, "X5"}, 29871 {22, x86.REG_X6, -1, "X6"}, 29872 {23, x86.REG_X7, -1, "X7"}, 29873 {24, x86.REG_X8, -1, "X8"}, 29874 {25, x86.REG_X9, -1, "X9"}, 29875 {26, x86.REG_X10, -1, "X10"}, 29876 {27, x86.REG_X11, -1, "X11"}, 29877 {28, x86.REG_X12, -1, "X12"}, 29878 {29, x86.REG_X13, -1, "X13"}, 29879 {30, x86.REG_X14, -1, "X14"}, 29880 {31, x86.REG_X15, -1, "X15"}, 29881 {32, 0, -1, "SB"}, 29882 } 29883 var gpRegMaskAMD64 = regMask(65519) 29884 var fpRegMaskAMD64 = regMask(4294901760) 29885 var specialRegMaskAMD64 = regMask(0) 29886 var framepointerRegAMD64 = int8(5) 29887 var linkRegAMD64 = int8(-1) 29888 var registersARM = [...]Register{ 29889 {0, arm.REG_R0, 0, "R0"}, 29890 {1, arm.REG_R1, 1, "R1"}, 29891 {2, arm.REG_R2, 2, "R2"}, 29892 {3, arm.REG_R3, 3, "R3"}, 29893 {4, arm.REG_R4, 4, "R4"}, 29894 {5, arm.REG_R5, 5, "R5"}, 29895 {6, arm.REG_R6, 6, "R6"}, 29896 {7, arm.REG_R7, 7, "R7"}, 29897 {8, arm.REG_R8, 8, "R8"}, 29898 {9, arm.REG_R9, 9, "R9"}, 29899 {10, arm.REGG, -1, "g"}, 29900 {11, arm.REG_R11, -1, "R11"}, 29901 {12, arm.REG_R12, 10, "R12"}, 29902 {13, arm.REGSP, -1, "SP"}, 29903 {14, arm.REG_R14, 11, "R14"}, 29904 {15, arm.REG_R15, -1, "R15"}, 29905 {16, arm.REG_F0, -1, "F0"}, 29906 {17, arm.REG_F1, -1, "F1"}, 29907 {18, arm.REG_F2, -1, "F2"}, 29908 {19, arm.REG_F3, -1, "F3"}, 29909 {20, arm.REG_F4, -1, "F4"}, 29910 {21, arm.REG_F5, -1, "F5"}, 29911 {22, arm.REG_F6, -1, "F6"}, 29912 {23, arm.REG_F7, -1, "F7"}, 29913 {24, arm.REG_F8, -1, "F8"}, 29914 {25, arm.REG_F9, -1, "F9"}, 29915 {26, arm.REG_F10, -1, "F10"}, 29916 {27, arm.REG_F11, -1, "F11"}, 29917 {28, arm.REG_F12, -1, "F12"}, 29918 {29, arm.REG_F13, -1, "F13"}, 29919 {30, arm.REG_F14, -1, "F14"}, 29920 {31, arm.REG_F15, -1, "F15"}, 29921 {32, 0, -1, "SB"}, 29922 } 29923 var gpRegMaskARM = regMask(21503) 29924 var fpRegMaskARM = regMask(4294901760) 29925 var specialRegMaskARM = regMask(0) 29926 var framepointerRegARM = int8(-1) 29927 var linkRegARM = int8(14) 29928 var registersARM64 = [...]Register{ 29929 {0, arm64.REG_R0, 0, "R0"}, 29930 {1, arm64.REG_R1, 1, "R1"}, 29931 {2, arm64.REG_R2, 2, "R2"}, 29932 {3, arm64.REG_R3, 3, "R3"}, 29933 {4, arm64.REG_R4, 4, "R4"}, 29934 {5, arm64.REG_R5, 5, "R5"}, 29935 {6, arm64.REG_R6, 6, "R6"}, 29936 {7, arm64.REG_R7, 7, "R7"}, 29937 {8, arm64.REG_R8, 8, "R8"}, 29938 {9, arm64.REG_R9, 9, "R9"}, 29939 {10, arm64.REG_R10, 10, "R10"}, 29940 {11, arm64.REG_R11, 11, "R11"}, 29941 {12, arm64.REG_R12, 12, "R12"}, 29942 {13, arm64.REG_R13, 13, "R13"}, 29943 {14, arm64.REG_R14, 14, "R14"}, 29944 {15, arm64.REG_R15, 15, "R15"}, 29945 {16, arm64.REG_R16, 16, "R16"}, 29946 {17, arm64.REG_R17, 17, "R17"}, 29947 {18, arm64.REG_R18, -1, "R18"}, 29948 {19, arm64.REG_R19, 18, "R19"}, 29949 {20, arm64.REG_R20, 19, "R20"}, 29950 {21, arm64.REG_R21, 20, "R21"}, 29951 {22, arm64.REG_R22, 21, "R22"}, 29952 {23, arm64.REG_R23, 22, "R23"}, 29953 {24, arm64.REG_R24, 23, "R24"}, 29954 {25, arm64.REG_R25, 24, "R25"}, 29955 {26, arm64.REG_R26, 25, "R26"}, 29956 {27, arm64.REGG, -1, "g"}, 29957 {28, arm64.REG_R29, -1, "R29"}, 29958 {29, arm64.REG_R30, 26, "R30"}, 29959 {30, arm64.REGSP, -1, "SP"}, 29960 {31, arm64.REG_F0, -1, "F0"}, 29961 {32, arm64.REG_F1, -1, "F1"}, 29962 {33, arm64.REG_F2, -1, "F2"}, 29963 {34, arm64.REG_F3, -1, "F3"}, 29964 {35, arm64.REG_F4, -1, "F4"}, 29965 {36, arm64.REG_F5, -1, "F5"}, 29966 {37, arm64.REG_F6, -1, "F6"}, 29967 {38, arm64.REG_F7, -1, "F7"}, 29968 {39, arm64.REG_F8, -1, "F8"}, 29969 {40, arm64.REG_F9, -1, "F9"}, 29970 {41, arm64.REG_F10, -1, "F10"}, 29971 {42, arm64.REG_F11, -1, "F11"}, 29972 {43, arm64.REG_F12, -1, "F12"}, 29973 {44, arm64.REG_F13, -1, "F13"}, 29974 {45, arm64.REG_F14, -1, "F14"}, 29975 {46, arm64.REG_F15, -1, "F15"}, 29976 {47, arm64.REG_F16, -1, "F16"}, 29977 {48, arm64.REG_F17, -1, "F17"}, 29978 {49, arm64.REG_F18, -1, "F18"}, 29979 {50, arm64.REG_F19, -1, "F19"}, 29980 {51, arm64.REG_F20, -1, "F20"}, 29981 {52, arm64.REG_F21, -1, "F21"}, 29982 {53, arm64.REG_F22, -1, "F22"}, 29983 {54, arm64.REG_F23, -1, "F23"}, 29984 {55, arm64.REG_F24, -1, "F24"}, 29985 {56, arm64.REG_F25, -1, "F25"}, 29986 {57, arm64.REG_F26, -1, "F26"}, 29987 {58, arm64.REG_F27, -1, "F27"}, 29988 {59, arm64.REG_F28, -1, "F28"}, 29989 {60, arm64.REG_F29, -1, "F29"}, 29990 {61, arm64.REG_F30, -1, "F30"}, 29991 {62, arm64.REG_F31, -1, "F31"}, 29992 {63, 0, -1, "SB"}, 29993 } 29994 var gpRegMaskARM64 = regMask(670826495) 29995 var fpRegMaskARM64 = regMask(9223372034707292160) 29996 var specialRegMaskARM64 = regMask(0) 29997 var framepointerRegARM64 = int8(-1) 29998 var linkRegARM64 = int8(29) 29999 var registersMIPS = [...]Register{ 30000 {0, mips.REG_R0, -1, "R0"}, 30001 {1, mips.REG_R1, 0, "R1"}, 30002 {2, mips.REG_R2, 1, "R2"}, 30003 {3, mips.REG_R3, 2, "R3"}, 30004 {4, mips.REG_R4, 3, "R4"}, 30005 {5, mips.REG_R5, 4, "R5"}, 30006 {6, mips.REG_R6, 5, "R6"}, 30007 {7, mips.REG_R7, 6, "R7"}, 30008 {8, mips.REG_R8, 7, "R8"}, 30009 {9, mips.REG_R9, 8, "R9"}, 30010 {10, mips.REG_R10, 9, "R10"}, 30011 {11, mips.REG_R11, 10, "R11"}, 30012 {12, mips.REG_R12, 11, "R12"}, 30013 {13, mips.REG_R13, 12, "R13"}, 30014 {14, mips.REG_R14, 13, "R14"}, 30015 {15, mips.REG_R15, 14, "R15"}, 30016 {16, mips.REG_R16, 15, "R16"}, 30017 {17, mips.REG_R17, 16, "R17"}, 30018 {18, mips.REG_R18, 17, "R18"}, 30019 {19, mips.REG_R19, 18, "R19"}, 30020 {20, mips.REG_R20, 19, "R20"}, 30021 {21, mips.REG_R21, 20, "R21"}, 30022 {22, mips.REG_R22, 21, "R22"}, 30023 {23, mips.REG_R24, 22, "R24"}, 30024 {24, mips.REG_R25, 23, "R25"}, 30025 {25, mips.REG_R28, 24, "R28"}, 30026 {26, mips.REGSP, -1, "SP"}, 30027 {27, mips.REGG, -1, "g"}, 30028 {28, mips.REG_R31, 25, "R31"}, 30029 {29, mips.REG_F0, -1, "F0"}, 30030 {30, mips.REG_F2, -1, "F2"}, 30031 {31, mips.REG_F4, -1, "F4"}, 30032 {32, mips.REG_F6, -1, "F6"}, 30033 {33, mips.REG_F8, -1, "F8"}, 30034 {34, mips.REG_F10, -1, "F10"}, 30035 {35, mips.REG_F12, -1, "F12"}, 30036 {36, mips.REG_F14, -1, "F14"}, 30037 {37, mips.REG_F16, -1, "F16"}, 30038 {38, mips.REG_F18, -1, "F18"}, 30039 {39, mips.REG_F20, -1, "F20"}, 30040 {40, mips.REG_F22, -1, "F22"}, 30041 {41, mips.REG_F24, -1, "F24"}, 30042 {42, mips.REG_F26, -1, "F26"}, 30043 {43, mips.REG_F28, -1, "F28"}, 30044 {44, mips.REG_F30, -1, "F30"}, 30045 {45, mips.REG_HI, -1, "HI"}, 30046 {46, mips.REG_LO, -1, "LO"}, 30047 {47, 0, -1, "SB"}, 30048 } 30049 var gpRegMaskMIPS = regMask(335544318) 30050 var fpRegMaskMIPS = regMask(35183835217920) 30051 var specialRegMaskMIPS = regMask(105553116266496) 30052 var framepointerRegMIPS = int8(-1) 30053 var linkRegMIPS = int8(28) 30054 var registersMIPS64 = [...]Register{ 30055 {0, mips.REG_R0, -1, "R0"}, 30056 {1, mips.REG_R1, 0, "R1"}, 30057 {2, mips.REG_R2, 1, "R2"}, 30058 {3, mips.REG_R3, 2, "R3"}, 30059 {4, mips.REG_R4, 3, "R4"}, 30060 {5, mips.REG_R5, 4, "R5"}, 30061 {6, mips.REG_R6, 5, "R6"}, 30062 {7, mips.REG_R7, 6, "R7"}, 30063 {8, mips.REG_R8, 7, "R8"}, 30064 {9, mips.REG_R9, 8, "R9"}, 30065 {10, mips.REG_R10, 9, "R10"}, 30066 {11, mips.REG_R11, 10, "R11"}, 30067 {12, mips.REG_R12, 11, "R12"}, 30068 {13, mips.REG_R13, 12, "R13"}, 30069 {14, mips.REG_R14, 13, "R14"}, 30070 {15, mips.REG_R15, 14, "R15"}, 30071 {16, mips.REG_R16, 15, "R16"}, 30072 {17, mips.REG_R17, 16, "R17"}, 30073 {18, mips.REG_R18, 17, "R18"}, 30074 {19, mips.REG_R19, 18, "R19"}, 30075 {20, mips.REG_R20, 19, "R20"}, 30076 {21, mips.REG_R21, 20, "R21"}, 30077 {22, mips.REG_R22, 21, "R22"}, 30078 {23, mips.REG_R24, 22, "R24"}, 30079 {24, mips.REG_R25, 23, "R25"}, 30080 {25, mips.REGSP, -1, "SP"}, 30081 {26, mips.REGG, -1, "g"}, 30082 {27, mips.REG_R31, 24, "R31"}, 30083 {28, mips.REG_F0, -1, "F0"}, 30084 {29, mips.REG_F1, -1, "F1"}, 30085 {30, mips.REG_F2, -1, "F2"}, 30086 {31, mips.REG_F3, -1, "F3"}, 30087 {32, mips.REG_F4, -1, "F4"}, 30088 {33, mips.REG_F5, -1, "F5"}, 30089 {34, mips.REG_F6, -1, "F6"}, 30090 {35, mips.REG_F7, -1, "F7"}, 30091 {36, mips.REG_F8, -1, "F8"}, 30092 {37, mips.REG_F9, -1, "F9"}, 30093 {38, mips.REG_F10, -1, "F10"}, 30094 {39, mips.REG_F11, -1, "F11"}, 30095 {40, mips.REG_F12, -1, "F12"}, 30096 {41, mips.REG_F13, -1, "F13"}, 30097 {42, mips.REG_F14, -1, "F14"}, 30098 {43, mips.REG_F15, -1, "F15"}, 30099 {44, mips.REG_F16, -1, "F16"}, 30100 {45, mips.REG_F17, -1, "F17"}, 30101 {46, mips.REG_F18, -1, "F18"}, 30102 {47, mips.REG_F19, -1, "F19"}, 30103 {48, mips.REG_F20, -1, "F20"}, 30104 {49, mips.REG_F21, -1, "F21"}, 30105 {50, mips.REG_F22, -1, "F22"}, 30106 {51, mips.REG_F23, -1, "F23"}, 30107 {52, mips.REG_F24, -1, "F24"}, 30108 {53, mips.REG_F25, -1, "F25"}, 30109 {54, mips.REG_F26, -1, "F26"}, 30110 {55, mips.REG_F27, -1, "F27"}, 30111 {56, mips.REG_F28, -1, "F28"}, 30112 {57, mips.REG_F29, -1, "F29"}, 30113 {58, mips.REG_F30, -1, "F30"}, 30114 {59, mips.REG_F31, -1, "F31"}, 30115 {60, mips.REG_HI, -1, "HI"}, 30116 {61, mips.REG_LO, -1, "LO"}, 30117 {62, 0, -1, "SB"}, 30118 } 30119 var gpRegMaskMIPS64 = regMask(167772158) 30120 var fpRegMaskMIPS64 = regMask(1152921504338411520) 30121 var specialRegMaskMIPS64 = regMask(3458764513820540928) 30122 var framepointerRegMIPS64 = int8(-1) 30123 var linkRegMIPS64 = int8(27) 30124 var registersPPC64 = [...]Register{ 30125 {0, ppc64.REG_R0, -1, "R0"}, 30126 {1, ppc64.REGSP, -1, "SP"}, 30127 {2, 0, -1, "SB"}, 30128 {3, ppc64.REG_R3, 0, "R3"}, 30129 {4, ppc64.REG_R4, 1, "R4"}, 30130 {5, ppc64.REG_R5, 2, "R5"}, 30131 {6, ppc64.REG_R6, 3, "R6"}, 30132 {7, ppc64.REG_R7, 4, "R7"}, 30133 {8, ppc64.REG_R8, 5, "R8"}, 30134 {9, ppc64.REG_R9, 6, "R9"}, 30135 {10, ppc64.REG_R10, 7, "R10"}, 30136 {11, ppc64.REG_R11, 8, "R11"}, 30137 {12, ppc64.REG_R12, 9, "R12"}, 30138 {13, ppc64.REG_R13, -1, "R13"}, 30139 {14, ppc64.REG_R14, 10, "R14"}, 30140 {15, ppc64.REG_R15, 11, "R15"}, 30141 {16, ppc64.REG_R16, 12, "R16"}, 30142 {17, ppc64.REG_R17, 13, "R17"}, 30143 {18, ppc64.REG_R18, 14, "R18"}, 30144 {19, ppc64.REG_R19, 15, "R19"}, 30145 {20, ppc64.REG_R20, 16, "R20"}, 30146 {21, ppc64.REG_R21, 17, "R21"}, 30147 {22, ppc64.REG_R22, 18, "R22"}, 30148 {23, ppc64.REG_R23, 19, "R23"}, 30149 {24, ppc64.REG_R24, 20, "R24"}, 30150 {25, ppc64.REG_R25, 21, "R25"}, 30151 {26, ppc64.REG_R26, 22, "R26"}, 30152 {27, ppc64.REG_R27, 23, "R27"}, 30153 {28, ppc64.REG_R28, 24, "R28"}, 30154 {29, ppc64.REG_R29, 25, "R29"}, 30155 {30, ppc64.REGG, -1, "g"}, 30156 {31, ppc64.REG_R31, -1, "R31"}, 30157 {32, ppc64.REG_F0, -1, "F0"}, 30158 {33, ppc64.REG_F1, -1, "F1"}, 30159 {34, ppc64.REG_F2, -1, "F2"}, 30160 {35, ppc64.REG_F3, -1, "F3"}, 30161 {36, ppc64.REG_F4, -1, "F4"}, 30162 {37, ppc64.REG_F5, -1, "F5"}, 30163 {38, ppc64.REG_F6, -1, "F6"}, 30164 {39, ppc64.REG_F7, -1, "F7"}, 30165 {40, ppc64.REG_F8, -1, "F8"}, 30166 {41, ppc64.REG_F9, -1, "F9"}, 30167 {42, ppc64.REG_F10, -1, "F10"}, 30168 {43, ppc64.REG_F11, -1, "F11"}, 30169 {44, ppc64.REG_F12, -1, "F12"}, 30170 {45, ppc64.REG_F13, -1, "F13"}, 30171 {46, ppc64.REG_F14, -1, "F14"}, 30172 {47, ppc64.REG_F15, -1, "F15"}, 30173 {48, ppc64.REG_F16, -1, "F16"}, 30174 {49, ppc64.REG_F17, -1, "F17"}, 30175 {50, ppc64.REG_F18, -1, "F18"}, 30176 {51, ppc64.REG_F19, -1, "F19"}, 30177 {52, ppc64.REG_F20, -1, "F20"}, 30178 {53, ppc64.REG_F21, -1, "F21"}, 30179 {54, ppc64.REG_F22, -1, "F22"}, 30180 {55, ppc64.REG_F23, -1, "F23"}, 30181 {56, ppc64.REG_F24, -1, "F24"}, 30182 {57, ppc64.REG_F25, -1, "F25"}, 30183 {58, ppc64.REG_F26, -1, "F26"}, 30184 {59, ppc64.REG_F27, -1, "F27"}, 30185 {60, ppc64.REG_F28, -1, "F28"}, 30186 {61, ppc64.REG_F29, -1, "F29"}, 30187 {62, ppc64.REG_F30, -1, "F30"}, 30188 {63, ppc64.REG_F31, -1, "F31"}, 30189 } 30190 var gpRegMaskPPC64 = regMask(1073733624) 30191 var fpRegMaskPPC64 = regMask(576460743713488896) 30192 var specialRegMaskPPC64 = regMask(0) 30193 var framepointerRegPPC64 = int8(1) 30194 var linkRegPPC64 = int8(-1) 30195 var registersS390X = [...]Register{ 30196 {0, s390x.REG_R0, 0, "R0"}, 30197 {1, s390x.REG_R1, 1, "R1"}, 30198 {2, s390x.REG_R2, 2, "R2"}, 30199 {3, s390x.REG_R3, 3, "R3"}, 30200 {4, s390x.REG_R4, 4, "R4"}, 30201 {5, s390x.REG_R5, 5, "R5"}, 30202 {6, s390x.REG_R6, 6, "R6"}, 30203 {7, s390x.REG_R7, 7, "R7"}, 30204 {8, s390x.REG_R8, 8, "R8"}, 30205 {9, s390x.REG_R9, 9, "R9"}, 30206 {10, s390x.REG_R10, -1, "R10"}, 30207 {11, s390x.REG_R11, 10, "R11"}, 30208 {12, s390x.REG_R12, 11, "R12"}, 30209 {13, s390x.REGG, -1, "g"}, 30210 {14, s390x.REG_R14, 12, "R14"}, 30211 {15, s390x.REGSP, -1, "SP"}, 30212 {16, s390x.REG_F0, -1, "F0"}, 30213 {17, s390x.REG_F1, -1, "F1"}, 30214 {18, s390x.REG_F2, -1, "F2"}, 30215 {19, s390x.REG_F3, -1, "F3"}, 30216 {20, s390x.REG_F4, -1, "F4"}, 30217 {21, s390x.REG_F5, -1, "F5"}, 30218 {22, s390x.REG_F6, -1, "F6"}, 30219 {23, s390x.REG_F7, -1, "F7"}, 30220 {24, s390x.REG_F8, -1, "F8"}, 30221 {25, s390x.REG_F9, -1, "F9"}, 30222 {26, s390x.REG_F10, -1, "F10"}, 30223 {27, s390x.REG_F11, -1, "F11"}, 30224 {28, s390x.REG_F12, -1, "F12"}, 30225 {29, s390x.REG_F13, -1, "F13"}, 30226 {30, s390x.REG_F14, -1, "F14"}, 30227 {31, s390x.REG_F15, -1, "F15"}, 30228 {32, 0, -1, "SB"}, 30229 } 30230 var gpRegMaskS390X = regMask(23551) 30231 var fpRegMaskS390X = regMask(4294901760) 30232 var specialRegMaskS390X = regMask(0) 30233 var framepointerRegS390X = int8(-1) 30234 var linkRegS390X = int8(14) 30235 var registersWasm = [...]Register{ 30236 {0, wasm.REG_R0, 0, "R0"}, 30237 {1, wasm.REG_R1, 1, "R1"}, 30238 {2, wasm.REG_R2, 2, "R2"}, 30239 {3, wasm.REG_R3, 3, "R3"}, 30240 {4, wasm.REG_R4, 4, "R4"}, 30241 {5, wasm.REG_R5, 5, "R5"}, 30242 {6, wasm.REG_R6, 6, "R6"}, 30243 {7, wasm.REG_R7, 7, "R7"}, 30244 {8, wasm.REG_R8, 8, "R8"}, 30245 {9, wasm.REG_R9, 9, "R9"}, 30246 {10, wasm.REG_R10, 10, "R10"}, 30247 {11, wasm.REG_R11, 11, "R11"}, 30248 {12, wasm.REG_R12, 12, "R12"}, 30249 {13, wasm.REG_R13, 13, "R13"}, 30250 {14, wasm.REG_R14, 14, "R14"}, 30251 {15, wasm.REG_R15, 15, "R15"}, 30252 {16, wasm.REG_F0, -1, "F0"}, 30253 {17, wasm.REG_F1, -1, "F1"}, 30254 {18, wasm.REG_F2, -1, "F2"}, 30255 {19, wasm.REG_F3, -1, "F3"}, 30256 {20, wasm.REG_F4, -1, "F4"}, 30257 {21, wasm.REG_F5, -1, "F5"}, 30258 {22, wasm.REG_F6, -1, "F6"}, 30259 {23, wasm.REG_F7, -1, "F7"}, 30260 {24, wasm.REG_F8, -1, "F8"}, 30261 {25, wasm.REG_F9, -1, "F9"}, 30262 {26, wasm.REG_F10, -1, "F10"}, 30263 {27, wasm.REG_F11, -1, "F11"}, 30264 {28, wasm.REG_F12, -1, "F12"}, 30265 {29, wasm.REG_F13, -1, "F13"}, 30266 {30, wasm.REG_F14, -1, "F14"}, 30267 {31, wasm.REG_F15, -1, "F15"}, 30268 {32, wasm.REGSP, -1, "SP"}, 30269 {33, wasm.REGG, -1, "g"}, 30270 {34, 0, -1, "SB"}, 30271 } 30272 var gpRegMaskWasm = regMask(65535) 30273 var fpRegMaskWasm = regMask(4294901760) 30274 var specialRegMaskWasm = regMask(0) 30275 var framepointerRegWasm = int8(-1) 30276 var linkRegWasm = int8(-1)