github.com/hikaru7719/go@v0.0.0-20181025140707-c8b2ac68906a/src/cmd/internal/obj/arm64/a.out.go (about) 1 // cmd/7c/7.out.h from Vita Nuova. 2 // https://code.google.com/p/ken-cc/source/browse/src/cmd/7c/7.out.h 3 // 4 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 5 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 6 // Portions Copyright © 1997-1999 Vita Nuova Limited 7 // Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com) 8 // Portions Copyright © 2004,2006 Bruce Ellis 9 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 10 // Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others 11 // Portions Copyright © 2009 The Go Authors. All rights reserved. 12 // 13 // Permission is hereby granted, free of charge, to any person obtaining a copy 14 // of this software and associated documentation files (the "Software"), to deal 15 // in the Software without restriction, including without limitation the rights 16 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 // copies of the Software, and to permit persons to whom the Software is 18 // furnished to do so, subject to the following conditions: 19 // 20 // The above copyright notice and this permission notice shall be included in 21 // all copies or substantial portions of the Software. 22 // 23 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 26 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 // THE SOFTWARE. 30 31 package arm64 32 33 import "cmd/internal/obj" 34 35 const ( 36 NSNAME = 8 37 NSYM = 50 38 NREG = 32 /* number of general registers */ 39 NFREG = 32 /* number of floating point registers */ 40 ) 41 42 // General purpose registers, kept in the low bits of Prog.Reg. 43 const ( 44 // integer 45 REG_R0 = obj.RBaseARM64 + iota 46 REG_R1 47 REG_R2 48 REG_R3 49 REG_R4 50 REG_R5 51 REG_R6 52 REG_R7 53 REG_R8 54 REG_R9 55 REG_R10 56 REG_R11 57 REG_R12 58 REG_R13 59 REG_R14 60 REG_R15 61 REG_R16 62 REG_R17 63 REG_R18 64 REG_R19 65 REG_R20 66 REG_R21 67 REG_R22 68 REG_R23 69 REG_R24 70 REG_R25 71 REG_R26 72 REG_R27 73 REG_R28 74 REG_R29 75 REG_R30 76 REG_R31 77 78 // scalar floating point 79 REG_F0 80 REG_F1 81 REG_F2 82 REG_F3 83 REG_F4 84 REG_F5 85 REG_F6 86 REG_F7 87 REG_F8 88 REG_F9 89 REG_F10 90 REG_F11 91 REG_F12 92 REG_F13 93 REG_F14 94 REG_F15 95 REG_F16 96 REG_F17 97 REG_F18 98 REG_F19 99 REG_F20 100 REG_F21 101 REG_F22 102 REG_F23 103 REG_F24 104 REG_F25 105 REG_F26 106 REG_F27 107 REG_F28 108 REG_F29 109 REG_F30 110 REG_F31 111 112 // SIMD 113 REG_V0 114 REG_V1 115 REG_V2 116 REG_V3 117 REG_V4 118 REG_V5 119 REG_V6 120 REG_V7 121 REG_V8 122 REG_V9 123 REG_V10 124 REG_V11 125 REG_V12 126 REG_V13 127 REG_V14 128 REG_V15 129 REG_V16 130 REG_V17 131 REG_V18 132 REG_V19 133 REG_V20 134 REG_V21 135 REG_V22 136 REG_V23 137 REG_V24 138 REG_V25 139 REG_V26 140 REG_V27 141 REG_V28 142 REG_V29 143 REG_V30 144 REG_V31 145 146 // The EQ in 147 // CSET EQ, R0 148 // is encoded as TYPE_REG, even though it's not really a register. 149 COND_EQ 150 COND_NE 151 COND_HS 152 COND_LO 153 COND_MI 154 COND_PL 155 COND_VS 156 COND_VC 157 COND_HI 158 COND_LS 159 COND_GE 160 COND_LT 161 COND_GT 162 COND_LE 163 COND_AL 164 COND_NV 165 166 REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31 167 ) 168 169 // bits 0-4 indicates register: Vn 170 // bits 5-8 indicates arrangement: <T> 171 const ( 172 REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T> 173 REG_ELEM // Vn.<T>[index] 174 REG_ELEM_END 175 ) 176 177 // Not registers, but flags that can be combined with regular register 178 // constants to indicate extended register conversion. When checking, 179 // you should subtract obj.RBaseARM64 first. From this difference, bit 11 180 // indicates extended register, bits 8-10 select the conversion mode. 181 // REG_LSL is the index shift specifier, bit 9 indicates shifted offset register. 182 const REG_LSL = obj.RBaseARM64 + 1<<9 183 const REG_EXT = obj.RBaseARM64 + 1<<11 184 185 const ( 186 REG_UXTB = REG_EXT + iota<<8 187 REG_UXTH 188 REG_UXTW 189 REG_UXTX 190 REG_SXTB 191 REG_SXTH 192 REG_SXTW 193 REG_SXTX 194 ) 195 196 // Special registers, after subtracting obj.RBaseARM64, bit 12 indicates 197 // a special register and the low bits select the register. 198 const ( 199 REG_SPECIAL = obj.RBaseARM64 + 1<<12 + iota 200 REG_DAIF 201 REG_NZCV 202 REG_FPSR 203 REG_FPCR 204 REG_SPSR_EL1 205 REG_ELR_EL1 206 REG_SPSR_EL2 207 REG_ELR_EL2 208 REG_CurrentEL 209 REG_SP_EL0 210 REG_SPSel 211 REG_DAIFSet 212 REG_DAIFClr 213 REG_DCZID_EL0 214 REG_PLDL1KEEP 215 REG_PLDL1STRM 216 REG_PLDL2KEEP 217 REG_PLDL2STRM 218 REG_PLDL3KEEP 219 REG_PLDL3STRM 220 REG_PLIL1KEEP 221 REG_PLIL1STRM 222 REG_PLIL2KEEP 223 REG_PLIL2STRM 224 REG_PLIL3KEEP 225 REG_PLIL3STRM 226 REG_PSTL1KEEP 227 REG_PSTL1STRM 228 REG_PSTL2KEEP 229 REG_PSTL2STRM 230 REG_PSTL3KEEP 231 REG_PSTL3STRM 232 ) 233 234 // Register assignments: 235 // 236 // compiler allocates R0 up as temps 237 // compiler allocates register variables R7-R25 238 // compiler allocates external registers R26 down 239 // 240 // compiler allocates register variables F7-F26 241 // compiler allocates external registers F26 down 242 const ( 243 REGMIN = REG_R7 // register variables allocated from here to REGMAX 244 REGRT1 = REG_R16 // ARM64 IP0, for external linker, runtime, duffzero and duffcopy 245 REGRT2 = REG_R17 // ARM64 IP1, for external linker, runtime, duffcopy 246 REGPR = REG_R18 // ARM64 platform register, unused in the Go toolchain 247 REGMAX = REG_R25 248 249 REGCTXT = REG_R26 // environment for closures 250 REGTMP = REG_R27 // reserved for liblink 251 REGG = REG_R28 // G 252 REGFP = REG_R29 // frame pointer, unused in the Go toolchain 253 REGLINK = REG_R30 254 255 // ARM64 uses R31 as both stack pointer and zero register, 256 // depending on the instruction. To differentiate RSP from ZR, 257 // we use a different numeric value for REGZERO and REGSP. 258 REGZERO = REG_R31 259 REGSP = REG_RSP 260 261 FREGRET = REG_F0 262 FREGMIN = REG_F7 // first register variable 263 FREGMAX = REG_F26 // last register variable for 7g only 264 FREGEXT = REG_F26 // first external register 265 ) 266 267 // http://infocenter.arm.com/help/topic/com.arm.doc.ecm0665627/abi_sve_aadwarf_100985_0000_00_en.pdf 268 var ARM64DWARFRegisters = map[int16]int16{ 269 REG_R0: 0, 270 REG_R1: 1, 271 REG_R2: 2, 272 REG_R3: 3, 273 REG_R4: 4, 274 REG_R5: 5, 275 REG_R6: 6, 276 REG_R7: 7, 277 REG_R8: 8, 278 REG_R9: 9, 279 REG_R10: 10, 280 REG_R11: 11, 281 REG_R12: 12, 282 REG_R13: 13, 283 REG_R14: 14, 284 REG_R15: 15, 285 REG_R16: 16, 286 REG_R17: 17, 287 REG_R18: 18, 288 REG_R19: 19, 289 REG_R20: 20, 290 REG_R21: 21, 291 REG_R22: 22, 292 REG_R23: 23, 293 REG_R24: 24, 294 REG_R25: 25, 295 REG_R26: 26, 296 REG_R27: 27, 297 REG_R28: 28, 298 REG_R29: 29, 299 REG_R30: 30, 300 301 // floating point 302 REG_F0: 64, 303 REG_F1: 65, 304 REG_F2: 66, 305 REG_F3: 67, 306 REG_F4: 68, 307 REG_F5: 69, 308 REG_F6: 70, 309 REG_F7: 71, 310 REG_F8: 72, 311 REG_F9: 73, 312 REG_F10: 74, 313 REG_F11: 75, 314 REG_F12: 76, 315 REG_F13: 77, 316 REG_F14: 78, 317 REG_F15: 79, 318 REG_F16: 80, 319 REG_F17: 81, 320 REG_F18: 82, 321 REG_F19: 83, 322 REG_F20: 84, 323 REG_F21: 85, 324 REG_F22: 86, 325 REG_F23: 87, 326 REG_F24: 88, 327 REG_F25: 89, 328 REG_F26: 90, 329 REG_F27: 91, 330 REG_F28: 92, 331 REG_F29: 93, 332 REG_F30: 94, 333 REG_F31: 95, 334 335 // SIMD 336 REG_V0: 64, 337 REG_V1: 65, 338 REG_V2: 66, 339 REG_V3: 67, 340 REG_V4: 68, 341 REG_V5: 69, 342 REG_V6: 70, 343 REG_V7: 71, 344 REG_V8: 72, 345 REG_V9: 73, 346 REG_V10: 74, 347 REG_V11: 75, 348 REG_V12: 76, 349 REG_V13: 77, 350 REG_V14: 78, 351 REG_V15: 79, 352 REG_V16: 80, 353 REG_V17: 81, 354 REG_V18: 82, 355 REG_V19: 83, 356 REG_V20: 84, 357 REG_V21: 85, 358 REG_V22: 86, 359 REG_V23: 87, 360 REG_V24: 88, 361 REG_V25: 89, 362 REG_V26: 90, 363 REG_V27: 91, 364 REG_V28: 92, 365 REG_V29: 93, 366 REG_V30: 94, 367 REG_V31: 95, 368 } 369 370 const ( 371 BIG = 2048 - 8 372 ) 373 374 const ( 375 /* mark flags */ 376 LABEL = 1 << iota 377 LEAF 378 FLOAT 379 BRANCH 380 LOAD 381 FCMP 382 SYNC 383 LIST 384 FOLL 385 NOSCHED 386 ) 387 388 const ( 389 // optab is sorted based on the order of these constants 390 // and the first match is chosen. 391 // The more specific class needs to come earlier. 392 C_NONE = iota 393 C_REG // R0..R30 394 C_RSP // R0..R30, RSP 395 C_FREG // F0..F31 396 C_VREG // V0..V31 397 C_PAIR // (Rn, Rm) 398 C_SHIFT // Rn<<2 399 C_EXTREG // Rn.UXTB[<<3] 400 C_SPR // REG_NZCV 401 C_COND // EQ, NE, etc 402 C_ARNG // Vn.<T> 403 C_ELEM // Vn.<T>[index] 404 C_LIST // [V1, V2, V3] 405 406 C_ZCON // $0 or ZR 407 C_ABCON0 // could be C_ADDCON0 or C_BITCON 408 C_ADDCON0 // 12-bit unsigned, unshifted 409 C_ABCON // could be C_ADDCON or C_BITCON 410 C_AMCON // could be C_ADDCON or C_MOVCON 411 C_ADDCON // 12-bit unsigned, shifted left by 0 or 12 412 C_MBCON // could be C_MOVCON or C_BITCON 413 C_MOVCON // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16 414 C_BITCON // bitfield and logical immediate masks 415 C_ADDCON2 // 24-bit constant 416 C_LCON // 32-bit constant 417 C_VCON // 64-bit constant 418 C_FCON // floating-point constant 419 C_VCONADDR // 64-bit memory address 420 421 C_AACON // ADDCON offset in auto constant $a(FP) 422 C_LACON // 32-bit offset in auto constant $a(FP) 423 C_AECON // ADDCON offset in extern constant $e(SB) 424 425 // TODO(aram): only one branch class should be enough 426 C_SBRA // for TYPE_BRANCH 427 C_LBRA 428 429 C_ZAUTO // 0(RSP) 430 C_NSAUTO_8 // -256 <= x < 0, 0 mod 8 431 C_NSAUTO_4 // -256 <= x < 0, 0 mod 4 432 C_NSAUTO // -256 <= x < 0 433 C_NPAUTO // -512 <= x < 0, 0 mod 8 434 C_NAUTO4K // -4095 <= x < 0 435 C_PSAUTO_8 // 0 to 255, 0 mod 8 436 C_PSAUTO_4 // 0 to 255, 0 mod 4 437 C_PSAUTO // 0 to 255 438 C_PPAUTO // 0 to 504, 0 mod 8 439 C_UAUTO4K_8 // 0 to 4095, 0 mod 8 440 C_UAUTO4K_4 // 0 to 4095, 0 mod 4 441 C_UAUTO4K_2 // 0 to 4095, 0 mod 2 442 C_UAUTO4K // 0 to 4095 443 C_UAUTO8K_8 // 0 to 8190, 0 mod 8 444 C_UAUTO8K_4 // 0 to 8190, 0 mod 4 445 C_UAUTO8K // 0 to 8190, 0 mod 2 446 C_UAUTO16K_8 // 0 to 16380, 0 mod 8 447 C_UAUTO16K // 0 to 16380, 0 mod 4 448 C_UAUTO32K // 0 to 32760, 0 mod 8 449 C_LAUTO // any other 32-bit constant 450 451 C_SEXT1 // 0 to 4095, direct 452 C_SEXT2 // 0 to 8190 453 C_SEXT4 // 0 to 16380 454 C_SEXT8 // 0 to 32760 455 C_SEXT16 // 0 to 65520 456 C_LEXT 457 458 C_ZOREG // 0(R) 459 C_NSOREG_8 // must mirror C_NSAUTO_8, etc 460 C_NSOREG_4 461 C_NSOREG 462 C_NPOREG 463 C_NOREG4K 464 C_PSOREG_8 465 C_PSOREG_4 466 C_PSOREG 467 C_PPOREG 468 C_UOREG4K_8 469 C_UOREG4K_4 470 C_UOREG4K_2 471 C_UOREG4K 472 C_UOREG8K_8 473 C_UOREG8K_4 474 C_UOREG8K 475 C_UOREG16K_8 476 C_UOREG16K 477 C_UOREG32K 478 C_LOREG 479 480 C_ADDR // TODO(aram): explain difference from C_VCONADDR 481 482 // The GOT slot for a symbol in -dynlink mode. 483 C_GOTADDR 484 485 // TLS "var" in local exec mode: will become a constant offset from 486 // thread local base that is ultimately chosen by the program linker. 487 C_TLS_LE 488 489 // TLS "var" in initial exec mode: will become a memory address (chosen 490 // by the program linker) that the dynamic linker will fill with the 491 // offset from the thread local base. 492 C_TLS_IE 493 494 C_ROFF // register offset (including register extended) 495 496 C_GOK 497 C_TEXTSIZE 498 C_NCLASS // must be last 499 ) 500 501 const ( 502 C_XPRE = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it 503 C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it 504 ) 505 506 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64 507 508 const ( 509 AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota 510 AADCS 511 AADCSW 512 AADCW 513 AADD 514 AADDS 515 AADDSW 516 AADDW 517 AADR 518 AADRP 519 AAND 520 AANDS 521 AANDSW 522 AANDW 523 AASR 524 AASRW 525 AAT 526 ABFI 527 ABFIW 528 ABFM 529 ABFMW 530 ABFXIL 531 ABFXILW 532 ABIC 533 ABICS 534 ABICSW 535 ABICW 536 ABRK 537 ACBNZ 538 ACBNZW 539 ACBZ 540 ACBZW 541 ACCMN 542 ACCMNW 543 ACCMP 544 ACCMPW 545 ACINC 546 ACINCW 547 ACINV 548 ACINVW 549 ACLREX 550 ACLS 551 ACLSW 552 ACLZ 553 ACLZW 554 ACMN 555 ACMNW 556 ACMP 557 ACMPW 558 ACNEG 559 ACNEGW 560 ACRC32B 561 ACRC32CB 562 ACRC32CH 563 ACRC32CW 564 ACRC32CX 565 ACRC32H 566 ACRC32W 567 ACRC32X 568 ACSEL 569 ACSELW 570 ACSET 571 ACSETM 572 ACSETMW 573 ACSETW 574 ACSINC 575 ACSINCW 576 ACSINV 577 ACSINVW 578 ACSNEG 579 ACSNEGW 580 ADC 581 ADCPS1 582 ADCPS2 583 ADCPS3 584 ADMB 585 ADRPS 586 ADSB 587 AEON 588 AEONW 589 AEOR 590 AEORW 591 AERET 592 AEXTR 593 AEXTRW 594 AHINT 595 AHLT 596 AHVC 597 AIC 598 AISB 599 ALDADDALB 600 ALDADDALH 601 ALDADDALW 602 ALDADDALD 603 ALDADDB 604 ALDADDH 605 ALDADDW 606 ALDADDD 607 ALDANDB 608 ALDANDH 609 ALDANDW 610 ALDANDD 611 ALDAR 612 ALDARB 613 ALDARH 614 ALDARW 615 ALDAXP 616 ALDAXPW 617 ALDAXR 618 ALDAXRB 619 ALDAXRH 620 ALDAXRW 621 ALDEORB 622 ALDEORH 623 ALDEORW 624 ALDEORD 625 ALDORB 626 ALDORH 627 ALDORW 628 ALDORD 629 ALDP 630 ALDPW 631 ALDPSW 632 ALDXR 633 ALDXRB 634 ALDXRH 635 ALDXRW 636 ALDXP 637 ALDXPW 638 ALSL 639 ALSLW 640 ALSR 641 ALSRW 642 AMADD 643 AMADDW 644 AMNEG 645 AMNEGW 646 AMOVK 647 AMOVKW 648 AMOVN 649 AMOVNW 650 AMOVZ 651 AMOVZW 652 AMRS 653 AMSR 654 AMSUB 655 AMSUBW 656 AMUL 657 AMULW 658 AMVN 659 AMVNW 660 ANEG 661 ANEGS 662 ANEGSW 663 ANEGW 664 ANGC 665 ANGCS 666 ANGCSW 667 ANGCW 668 AORN 669 AORNW 670 AORR 671 AORRW 672 APRFM 673 APRFUM 674 ARBIT 675 ARBITW 676 AREM 677 AREMW 678 AREV 679 AREV16 680 AREV16W 681 AREV32 682 AREVW 683 AROR 684 ARORW 685 ASBC 686 ASBCS 687 ASBCSW 688 ASBCW 689 ASBFIZ 690 ASBFIZW 691 ASBFM 692 ASBFMW 693 ASBFX 694 ASBFXW 695 ASDIV 696 ASDIVW 697 ASEV 698 ASEVL 699 ASMADDL 700 ASMC 701 ASMNEGL 702 ASMSUBL 703 ASMULH 704 ASMULL 705 ASTXR 706 ASTXRB 707 ASTXRH 708 ASTXP 709 ASTXPW 710 ASTXRW 711 ASTLP 712 ASTLPW 713 ASTLR 714 ASTLRB 715 ASTLRH 716 ASTLRW 717 ASTLXP 718 ASTLXPW 719 ASTLXR 720 ASTLXRB 721 ASTLXRH 722 ASTLXRW 723 ASTP 724 ASTPW 725 ASUB 726 ASUBS 727 ASUBSW 728 ASUBW 729 ASVC 730 ASXTB 731 ASXTBW 732 ASXTH 733 ASXTHW 734 ASXTW 735 ASYS 736 ASYSL 737 ATBNZ 738 ATBZ 739 ATLBI 740 ATST 741 ATSTW 742 AUBFIZ 743 AUBFIZW 744 AUBFM 745 AUBFMW 746 AUBFX 747 AUBFXW 748 AUDIV 749 AUDIVW 750 AUMADDL 751 AUMNEGL 752 AUMSUBL 753 AUMULH 754 AUMULL 755 AUREM 756 AUREMW 757 AUXTB 758 AUXTH 759 AUXTW 760 AUXTBW 761 AUXTHW 762 AWFE 763 AWFI 764 AYIELD 765 AMOVB 766 AMOVBU 767 AMOVH 768 AMOVHU 769 AMOVW 770 AMOVWU 771 AMOVD 772 AMOVNP 773 AMOVNPW 774 AMOVP 775 AMOVPD 776 AMOVPQ 777 AMOVPS 778 AMOVPSW 779 AMOVPW 780 ASWPD 781 ASWPALD 782 ASWPW 783 ASWPALW 784 ASWPH 785 ASWPALH 786 ASWPB 787 ASWPALB 788 ABEQ 789 ABNE 790 ABCS 791 ABHS 792 ABCC 793 ABLO 794 ABMI 795 ABPL 796 ABVS 797 ABVC 798 ABHI 799 ABLS 800 ABGE 801 ABLT 802 ABGT 803 ABLE 804 AFABSD 805 AFABSS 806 AFADDD 807 AFADDS 808 AFCCMPD 809 AFCCMPED 810 AFCCMPS 811 AFCCMPES 812 AFCMPD 813 AFCMPED 814 AFCMPES 815 AFCMPS 816 AFCVTSD 817 AFCVTDS 818 AFCVTZSD 819 AFCVTZSDW 820 AFCVTZSS 821 AFCVTZSSW 822 AFCVTZUD 823 AFCVTZUDW 824 AFCVTZUS 825 AFCVTZUSW 826 AFDIVD 827 AFDIVS 828 AFLDPD 829 AFLDPS 830 AFMOVD 831 AFMOVS 832 AFMULD 833 AFMULS 834 AFNEGD 835 AFNEGS 836 AFSQRTD 837 AFSQRTS 838 AFSTPD 839 AFSTPS 840 AFSUBD 841 AFSUBS 842 ASCVTFD 843 ASCVTFS 844 ASCVTFWD 845 ASCVTFWS 846 AUCVTFD 847 AUCVTFS 848 AUCVTFWD 849 AUCVTFWS 850 AWORD 851 ADWORD 852 AFCSELS 853 AFCSELD 854 AFMAXS 855 AFMINS 856 AFMAXD 857 AFMIND 858 AFMAXNMS 859 AFMAXNMD 860 AFNMULS 861 AFNMULD 862 AFRINTNS 863 AFRINTND 864 AFRINTPS 865 AFRINTPD 866 AFRINTMS 867 AFRINTMD 868 AFRINTZS 869 AFRINTZD 870 AFRINTAS 871 AFRINTAD 872 AFRINTXS 873 AFRINTXD 874 AFRINTIS 875 AFRINTID 876 AFMADDS 877 AFMADDD 878 AFMSUBS 879 AFMSUBD 880 AFNMADDS 881 AFNMADDD 882 AFNMSUBS 883 AFNMSUBD 884 AFMINNMS 885 AFMINNMD 886 AFCVTDH 887 AFCVTHS 888 AFCVTHD 889 AFCVTSH 890 AAESD 891 AAESE 892 AAESIMC 893 AAESMC 894 ASHA1C 895 ASHA1H 896 ASHA1M 897 ASHA1P 898 ASHA1SU0 899 ASHA1SU1 900 ASHA256H 901 ASHA256H2 902 ASHA256SU0 903 ASHA256SU1 904 AVADD 905 AVADDP 906 AVAND 907 AVCMEQ 908 AVCNT 909 AVEOR 910 AVMOV 911 AVLD1 912 AVORR 913 AVREV32 914 AVREV64 915 AVST1 916 AVDUP 917 AVADDV 918 AVMOVI 919 AVUADDLV 920 AVSUB 921 AVFMLA 922 AVFMLS 923 AVPMULL 924 AVPMULL2 925 AVEXT 926 AVRBIT 927 AVUSHR 928 AVSHL 929 AVSRI 930 AVTBL 931 AVZIP1 932 AVZIP2 933 ALAST 934 AB = obj.AJMP 935 ABL = obj.ACALL 936 ) 937 938 const ( 939 // shift types 940 SHIFT_LL = 0 << 22 941 SHIFT_LR = 1 << 22 942 SHIFT_AR = 2 << 22 943 ) 944 945 // Arrangement for ARM64 SIMD instructions 946 const ( 947 // arrangement types 948 ARNG_8B = iota 949 ARNG_16B 950 ARNG_1D 951 ARNG_4H 952 ARNG_8H 953 ARNG_2S 954 ARNG_4S 955 ARNG_2D 956 ARNG_1Q 957 ARNG_B 958 ARNG_H 959 ARNG_S 960 ARNG_D 961 )