github.com/hikaru7719/go@v0.0.0-20181025140707-c8b2ac68906a/src/cmd/internal/obj/ppc64/a.out.go (about) 1 // cmd/9c/9.out.h from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package ppc64 31 32 import "cmd/internal/obj" 33 34 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p ppc64 35 36 /* 37 * powerpc 64 38 */ 39 const ( 40 NSNAME = 8 41 NSYM = 50 42 NREG = 32 /* number of general registers */ 43 NFREG = 32 /* number of floating point registers */ 44 ) 45 46 const ( 47 /* RBasePPC64 = 4096 */ 48 /* R0=4096 ... R31=4127 */ 49 REG_R0 = obj.RBasePPC64 + iota 50 REG_R1 51 REG_R2 52 REG_R3 53 REG_R4 54 REG_R5 55 REG_R6 56 REG_R7 57 REG_R8 58 REG_R9 59 REG_R10 60 REG_R11 61 REG_R12 62 REG_R13 63 REG_R14 64 REG_R15 65 REG_R16 66 REG_R17 67 REG_R18 68 REG_R19 69 REG_R20 70 REG_R21 71 REG_R22 72 REG_R23 73 REG_R24 74 REG_R25 75 REG_R26 76 REG_R27 77 REG_R28 78 REG_R29 79 REG_R30 80 REG_R31 81 82 /* F0=4128 ... F31=4159 */ 83 REG_F0 84 REG_F1 85 REG_F2 86 REG_F3 87 REG_F4 88 REG_F5 89 REG_F6 90 REG_F7 91 REG_F8 92 REG_F9 93 REG_F10 94 REG_F11 95 REG_F12 96 REG_F13 97 REG_F14 98 REG_F15 99 REG_F16 100 REG_F17 101 REG_F18 102 REG_F19 103 REG_F20 104 REG_F21 105 REG_F22 106 REG_F23 107 REG_F24 108 REG_F25 109 REG_F26 110 REG_F27 111 REG_F28 112 REG_F29 113 REG_F30 114 REG_F31 115 116 /* V0=4160 ... V31=4191 */ 117 REG_V0 118 REG_V1 119 REG_V2 120 REG_V3 121 REG_V4 122 REG_V5 123 REG_V6 124 REG_V7 125 REG_V8 126 REG_V9 127 REG_V10 128 REG_V11 129 REG_V12 130 REG_V13 131 REG_V14 132 REG_V15 133 REG_V16 134 REG_V17 135 REG_V18 136 REG_V19 137 REG_V20 138 REG_V21 139 REG_V22 140 REG_V23 141 REG_V24 142 REG_V25 143 REG_V26 144 REG_V27 145 REG_V28 146 REG_V29 147 REG_V30 148 REG_V31 149 150 /* VS0=4192 ... VS63=4255 */ 151 REG_VS0 152 REG_VS1 153 REG_VS2 154 REG_VS3 155 REG_VS4 156 REG_VS5 157 REG_VS6 158 REG_VS7 159 REG_VS8 160 REG_VS9 161 REG_VS10 162 REG_VS11 163 REG_VS12 164 REG_VS13 165 REG_VS14 166 REG_VS15 167 REG_VS16 168 REG_VS17 169 REG_VS18 170 REG_VS19 171 REG_VS20 172 REG_VS21 173 REG_VS22 174 REG_VS23 175 REG_VS24 176 REG_VS25 177 REG_VS26 178 REG_VS27 179 REG_VS28 180 REG_VS29 181 REG_VS30 182 REG_VS31 183 REG_VS32 184 REG_VS33 185 REG_VS34 186 REG_VS35 187 REG_VS36 188 REG_VS37 189 REG_VS38 190 REG_VS39 191 REG_VS40 192 REG_VS41 193 REG_VS42 194 REG_VS43 195 REG_VS44 196 REG_VS45 197 REG_VS46 198 REG_VS47 199 REG_VS48 200 REG_VS49 201 REG_VS50 202 REG_VS51 203 REG_VS52 204 REG_VS53 205 REG_VS54 206 REG_VS55 207 REG_VS56 208 REG_VS57 209 REG_VS58 210 REG_VS59 211 REG_VS60 212 REG_VS61 213 REG_VS62 214 REG_VS63 215 216 REG_CR0 217 REG_CR1 218 REG_CR2 219 REG_CR3 220 REG_CR4 221 REG_CR5 222 REG_CR6 223 REG_CR7 224 225 REG_MSR 226 REG_FPSCR 227 REG_CR 228 229 REG_SPECIAL = REG_CR0 230 231 REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers 232 REG_DCR0 = obj.RBasePPC64 + 2048 // first of 1024 registers 233 234 REG_XER = REG_SPR0 + 1 235 REG_LR = REG_SPR0 + 8 236 REG_CTR = REG_SPR0 + 9 237 238 REGZERO = REG_R0 /* set to zero */ 239 REGSP = REG_R1 240 REGSB = REG_R2 241 REGRET = REG_R3 242 REGARG = -1 /* -1 disables passing the first argument in register */ 243 REGRT1 = REG_R3 /* reserved for runtime, duffzero and duffcopy */ 244 REGRT2 = REG_R4 /* reserved for runtime, duffcopy */ 245 REGMIN = REG_R7 /* register variables allocated from here to REGMAX */ 246 REGCTXT = REG_R11 /* context for closures */ 247 REGTLS = REG_R13 /* C ABI TLS base pointer */ 248 REGMAX = REG_R27 249 REGEXT = REG_R30 /* external registers allocated from here down */ 250 REGG = REG_R30 /* G */ 251 REGTMP = REG_R31 /* used by the linker */ 252 FREGRET = REG_F0 253 FREGMIN = REG_F17 /* first register variable */ 254 FREGMAX = REG_F26 /* last register variable for 9g only */ 255 FREGEXT = REG_F26 /* first external register */ 256 ) 257 258 // OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI 259 // https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture 260 var PPC64DWARFRegisters = map[int16]int16{} 261 262 func init() { 263 // f assigns dwarfregister[from:to] = (base):(to-from+base) 264 f := func(from, to, base int16) { 265 for r := int16(from); r <= to; r++ { 266 PPC64DWARFRegisters[r] = r - from + base 267 } 268 } 269 f(REG_R0, REG_R31, 0) 270 f(REG_F0, REG_F31, 32) 271 f(REG_V0, REG_V31, 77) 272 f(REG_CR0, REG_CR7, 68) 273 274 f(REG_VS0, REG_VS31, 32) // overlaps F0-F31 275 f(REG_VS32, REG_VS63, 77) // overlaps V0-V31 276 PPC64DWARFRegisters[REG_LR] = 65 277 PPC64DWARFRegisters[REG_CTR] = 66 278 PPC64DWARFRegisters[REG_XER] = 76 279 } 280 281 /* 282 * GENERAL: 283 * 284 * compiler allocates R3 up as temps 285 * compiler allocates register variables R7-R27 286 * compiler allocates external registers R30 down 287 * 288 * compiler allocates register variables F17-F26 289 * compiler allocates external registers F26 down 290 */ 291 const ( 292 BIG = 32768 - 8 293 ) 294 295 const ( 296 /* mark flags */ 297 LABEL = 1 << 0 298 LEAF = 1 << 1 299 FLOAT = 1 << 2 300 BRANCH = 1 << 3 301 LOAD = 1 << 4 302 FCMP = 1 << 5 303 SYNC = 1 << 6 304 LIST = 1 << 7 305 FOLL = 1 << 8 306 NOSCHED = 1 << 9 307 ) 308 309 // Values for use in branch instruction BC 310 // BC B0,BI,label 311 // BO is type of branch + likely bits described below 312 // BI is CR value + branch type 313 // ex: BEQ CR2,label is BC 12,10,label 314 // 12 = BO_BCR 315 // 10 = BI_CR2 + BI_EQ 316 317 const ( 318 BI_CR0 = 0 319 BI_CR1 = 4 320 BI_CR2 = 8 321 BI_CR3 = 12 322 BI_CR4 = 16 323 BI_CR5 = 20 324 BI_CR6 = 24 325 BI_CR7 = 28 326 BI_LT = 0 327 BI_GT = 1 328 BI_EQ = 2 329 BI_OVF = 3 330 ) 331 332 // Values for the BO field. Add the branch type to 333 // the likely bits, if a likely setting is known. 334 // If branch likely or unlikely is not known, don't set it. 335 // e.g. branch on cr+likely = 15 336 337 const ( 338 BO_BCTR = 16 // branch on ctr value 339 BO_BCR = 12 // branch on cr value 340 BO_BCRBCTR = 8 // branch on ctr and cr value 341 BO_NOTBCR = 4 // branch on not cr value 342 BO_UNLIKELY = 2 // value for unlikely 343 BO_LIKELY = 3 // value for likely 344 ) 345 346 // Bit settings from the CR 347 348 const ( 349 C_COND_LT = iota // 0 result is negative 350 C_COND_GT // 1 result is positive 351 C_COND_EQ // 2 result is zero 352 C_COND_SO // 3 summary overflow or FP compare w/ NaN 353 ) 354 355 const ( 356 C_NONE = iota 357 C_REG 358 C_FREG 359 C_VREG 360 C_VSREG 361 C_CREG 362 C_SPR /* special processor register */ 363 C_ZCON 364 C_SCON /* 16 bit signed */ 365 C_UCON /* 32 bit signed, low 16 bits 0 */ 366 C_ADDCON /* -0x8000 <= v < 0 */ 367 C_ANDCON /* 0 < v <= 0xFFFF */ 368 C_LCON /* other 32 */ 369 C_DCON /* other 64 (could subdivide further) */ 370 C_SACON /* $n(REG) where n <= int16 */ 371 C_SECON 372 C_LACON /* $n(REG) where int16 < n <= int32 */ 373 C_LECON 374 C_DACON /* $n(REG) where int32 < n */ 375 C_SBRA 376 C_LBRA 377 C_LBRAPIC 378 C_SAUTO 379 C_LAUTO 380 C_SEXT 381 C_LEXT 382 C_ZOREG // conjecture: either (1) register + zeroed offset, or (2) "R0" implies zero or C_REG 383 C_SOREG // register + signed offset 384 C_LOREG 385 C_FPSCR 386 C_MSR 387 C_XER 388 C_LR 389 C_CTR 390 C_ANY 391 C_GOK 392 C_ADDR 393 C_GOTADDR 394 C_TLS_LE 395 C_TLS_IE 396 C_TEXTSIZE 397 398 C_NCLASS /* must be the last */ 399 ) 400 401 const ( 402 AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota 403 AADDCC 404 AADDIS 405 AADDV 406 AADDVCC 407 AADDC 408 AADDCCC 409 AADDCV 410 AADDCVCC 411 AADDME 412 AADDMECC 413 AADDMEVCC 414 AADDMEV 415 AADDE 416 AADDECC 417 AADDEVCC 418 AADDEV 419 AADDZE 420 AADDZECC 421 AADDZEVCC 422 AADDZEV 423 AADDEX 424 AAND 425 AANDCC 426 AANDN 427 AANDNCC 428 AANDISCC 429 ABC 430 ABCL 431 ABEQ 432 ABGE // not LT = G/E/U 433 ABGT 434 ABLE // not GT = L/E/U 435 ABLT 436 ABNE // not EQ = L/G/U 437 ABVC // Unordered-clear 438 ABVS // Unordered-set 439 ACMP 440 ACMPU 441 ACMPEQB 442 ACNTLZW 443 ACNTLZWCC 444 ACRAND 445 ACRANDN 446 ACREQV 447 ACRNAND 448 ACRNOR 449 ACROR 450 ACRORN 451 ACRXOR 452 ADIVW 453 ADIVWCC 454 ADIVWVCC 455 ADIVWV 456 ADIVWU 457 ADIVWUCC 458 ADIVWUVCC 459 ADIVWUV 460 AEQV 461 AEQVCC 462 AEXTSB 463 AEXTSBCC 464 AEXTSH 465 AEXTSHCC 466 AFABS 467 AFABSCC 468 AFADD 469 AFADDCC 470 AFADDS 471 AFADDSCC 472 AFCMPO 473 AFCMPU 474 AFCTIW 475 AFCTIWCC 476 AFCTIWZ 477 AFCTIWZCC 478 AFDIV 479 AFDIVCC 480 AFDIVS 481 AFDIVSCC 482 AFMADD 483 AFMADDCC 484 AFMADDS 485 AFMADDSCC 486 AFMOVD 487 AFMOVDCC 488 AFMOVDU 489 AFMOVS 490 AFMOVSU 491 AFMOVSX 492 AFMOVSZ 493 AFMSUB 494 AFMSUBCC 495 AFMSUBS 496 AFMSUBSCC 497 AFMUL 498 AFMULCC 499 AFMULS 500 AFMULSCC 501 AFNABS 502 AFNABSCC 503 AFNEG 504 AFNEGCC 505 AFNMADD 506 AFNMADDCC 507 AFNMADDS 508 AFNMADDSCC 509 AFNMSUB 510 AFNMSUBCC 511 AFNMSUBS 512 AFNMSUBSCC 513 AFRSP 514 AFRSPCC 515 AFSUB 516 AFSUBCC 517 AFSUBS 518 AFSUBSCC 519 AISEL 520 AMOVMW 521 ALBAR 522 ALHAR 523 ALSW 524 ALWAR 525 ALWSYNC 526 AMOVDBR 527 AMOVWBR 528 AMOVB 529 AMOVBU 530 AMOVBZ 531 AMOVBZU 532 AMOVH 533 AMOVHBR 534 AMOVHU 535 AMOVHZ 536 AMOVHZU 537 AMOVW 538 AMOVWU 539 AMOVFL 540 AMOVCRFS 541 AMTFSB0 542 AMTFSB0CC 543 AMTFSB1 544 AMTFSB1CC 545 AMULHW 546 AMULHWCC 547 AMULHWU 548 AMULHWUCC 549 AMULLW 550 AMULLWCC 551 AMULLWVCC 552 AMULLWV 553 ANAND 554 ANANDCC 555 ANEG 556 ANEGCC 557 ANEGVCC 558 ANEGV 559 ANOR 560 ANORCC 561 AOR 562 AORCC 563 AORN 564 AORNCC 565 AORIS 566 AREM 567 AREMCC 568 AREMV 569 AREMVCC 570 AREMU 571 AREMUCC 572 AREMUV 573 AREMUVCC 574 ARFI 575 ARLWMI 576 ARLWMICC 577 ARLWNM 578 ARLWNMCC 579 ASLW 580 ASLWCC 581 ASRW 582 ASRAW 583 ASRAWCC 584 ASRWCC 585 ASTBCCC 586 ASTSW 587 ASTWCCC 588 ASUB 589 ASUBCC 590 ASUBVCC 591 ASUBC 592 ASUBCCC 593 ASUBCV 594 ASUBCVCC 595 ASUBME 596 ASUBMECC 597 ASUBMEVCC 598 ASUBMEV 599 ASUBV 600 ASUBE 601 ASUBECC 602 ASUBEV 603 ASUBEVCC 604 ASUBZE 605 ASUBZECC 606 ASUBZEVCC 607 ASUBZEV 608 ASYNC 609 AXOR 610 AXORCC 611 AXORIS 612 613 ADCBF 614 ADCBI 615 ADCBST 616 ADCBT 617 ADCBTST 618 ADCBZ 619 AECIWX 620 AECOWX 621 AEIEIO 622 AICBI 623 AISYNC 624 APTESYNC 625 ATLBIE 626 ATLBIEL 627 ATLBSYNC 628 ATW 629 630 ASYSCALL 631 AWORD 632 633 ARFCI 634 635 AFCPSGN 636 AFCPSGNCC 637 /* optional on 32-bit */ 638 AFRES 639 AFRESCC 640 AFRIM 641 AFRIMCC 642 AFRIP 643 AFRIPCC 644 AFRIZ 645 AFRIZCC 646 AFRIN 647 AFRINCC 648 AFRSQRTE 649 AFRSQRTECC 650 AFSEL 651 AFSELCC 652 AFSQRT 653 AFSQRTCC 654 AFSQRTS 655 AFSQRTSCC 656 657 /* 64-bit */ 658 659 ACNTLZD 660 ACNTLZDCC 661 ACMPW /* CMP with L=0 */ 662 ACMPWU 663 ACMPB 664 AFTDIV 665 AFTSQRT 666 ADIVD 667 ADIVDCC 668 ADIVDE 669 ADIVDECC 670 ADIVDEU 671 ADIVDEUCC 672 ADIVDVCC 673 ADIVDV 674 ADIVDU 675 ADIVDUCC 676 ADIVDUVCC 677 ADIVDUV 678 AEXTSW 679 AEXTSWCC 680 /* AFCFIW; AFCFIWCC */ 681 AFCFID 682 AFCFIDCC 683 AFCFIDU 684 AFCFIDUCC 685 AFCFIDS 686 AFCFIDSCC 687 AFCTID 688 AFCTIDCC 689 AFCTIDZ 690 AFCTIDZCC 691 ALDAR 692 AMOVD 693 AMOVDU 694 AMOVWZ 695 AMOVWZU 696 AMULHD 697 AMULHDCC 698 AMULHDU 699 AMULHDUCC 700 AMULLD 701 AMULLDCC 702 AMULLDVCC 703 AMULLDV 704 ARFID 705 ARLDMI 706 ARLDMICC 707 ARLDIMI 708 ARLDIMICC 709 ARLDC 710 ARLDCCC 711 ARLDCR 712 ARLDCRCC 713 ARLDICR 714 ARLDICRCC 715 ARLDCL 716 ARLDCLCC 717 ARLDICL 718 ARLDICLCC 719 AROTL 720 AROTLW 721 ASLBIA 722 ASLBIE 723 ASLBMFEE 724 ASLBMFEV 725 ASLBMTE 726 ASLD 727 ASLDCC 728 ASRD 729 ASRAD 730 ASRADCC 731 ASRDCC 732 ASTDCCC 733 ATD 734 735 /* 64-bit pseudo operation */ 736 ADWORD 737 AREMD 738 AREMDCC 739 AREMDV 740 AREMDVCC 741 AREMDU 742 AREMDUCC 743 AREMDUV 744 AREMDUVCC 745 746 /* more 64-bit operations */ 747 AHRFID 748 APOPCNTD 749 APOPCNTW 750 APOPCNTB 751 ACOPY 752 APASTECC 753 ADARN 754 ALDMX 755 AMADDHD 756 AMADDHDU 757 AMADDLD 758 759 /* Vector */ 760 ALV 761 ALVEBX 762 ALVEHX 763 ALVEWX 764 ALVX 765 ALVXL 766 ALVSL 767 ALVSR 768 ASTV 769 ASTVEBX 770 ASTVEHX 771 ASTVEWX 772 ASTVX 773 ASTVXL 774 AVAND 775 AVANDC 776 AVNAND 777 AVOR 778 AVORC 779 AVNOR 780 AVXOR 781 AVEQV 782 AVADDUM 783 AVADDUBM 784 AVADDUHM 785 AVADDUWM 786 AVADDUDM 787 AVADDUQM 788 AVADDCU 789 AVADDCUQ 790 AVADDCUW 791 AVADDUS 792 AVADDUBS 793 AVADDUHS 794 AVADDUWS 795 AVADDSS 796 AVADDSBS 797 AVADDSHS 798 AVADDSWS 799 AVADDE 800 AVADDEUQM 801 AVADDECUQ 802 AVSUBUM 803 AVSUBUBM 804 AVSUBUHM 805 AVSUBUWM 806 AVSUBUDM 807 AVSUBUQM 808 AVSUBCU 809 AVSUBCUQ 810 AVSUBCUW 811 AVSUBUS 812 AVSUBUBS 813 AVSUBUHS 814 AVSUBUWS 815 AVSUBSS 816 AVSUBSBS 817 AVSUBSHS 818 AVSUBSWS 819 AVSUBE 820 AVSUBEUQM 821 AVSUBECUQ 822 AVMULESB 823 AVMULOSB 824 AVMULEUB 825 AVMULOUB 826 AVMULESH 827 AVMULOSH 828 AVMULEUH 829 AVMULOUH 830 AVMULESW 831 AVMULOSW 832 AVMULEUW 833 AVMULOUW 834 AVMULUWM 835 AVPMSUM 836 AVPMSUMB 837 AVPMSUMH 838 AVPMSUMW 839 AVPMSUMD 840 AVMSUMUDM 841 AVR 842 AVRLB 843 AVRLH 844 AVRLW 845 AVRLD 846 AVS 847 AVSLB 848 AVSLH 849 AVSLW 850 AVSL 851 AVSLO 852 AVSRB 853 AVSRH 854 AVSRW 855 AVSR 856 AVSRO 857 AVSLD 858 AVSRD 859 AVSA 860 AVSRAB 861 AVSRAH 862 AVSRAW 863 AVSRAD 864 AVSOI 865 AVSLDOI 866 AVCLZ 867 AVCLZB 868 AVCLZH 869 AVCLZW 870 AVCLZD 871 AVPOPCNT 872 AVPOPCNTB 873 AVPOPCNTH 874 AVPOPCNTW 875 AVPOPCNTD 876 AVCMPEQ 877 AVCMPEQUB 878 AVCMPEQUBCC 879 AVCMPEQUH 880 AVCMPEQUHCC 881 AVCMPEQUW 882 AVCMPEQUWCC 883 AVCMPEQUD 884 AVCMPEQUDCC 885 AVCMPGT 886 AVCMPGTUB 887 AVCMPGTUBCC 888 AVCMPGTUH 889 AVCMPGTUHCC 890 AVCMPGTUW 891 AVCMPGTUWCC 892 AVCMPGTUD 893 AVCMPGTUDCC 894 AVCMPGTSB 895 AVCMPGTSBCC 896 AVCMPGTSH 897 AVCMPGTSHCC 898 AVCMPGTSW 899 AVCMPGTSWCC 900 AVCMPGTSD 901 AVCMPGTSDCC 902 AVCMPNEZB 903 AVCMPNEZBCC 904 AVPERM 905 AVBPERMQ 906 AVBPERMD 907 AVSEL 908 AVSPLT 909 AVSPLTB 910 AVSPLTH 911 AVSPLTW 912 AVSPLTI 913 AVSPLTISB 914 AVSPLTISH 915 AVSPLTISW 916 AVCIPH 917 AVCIPHER 918 AVCIPHERLAST 919 AVNCIPH 920 AVNCIPHER 921 AVNCIPHERLAST 922 AVSBOX 923 AVSHASIGMA 924 AVSHASIGMAW 925 AVSHASIGMAD 926 927 /* VSX */ 928 ALXV 929 ALXVD2X 930 ALXVDSX 931 ALXVW4X 932 ASTXV 933 ASTXVD2X 934 ASTXVW4X 935 ALXS 936 ALXSDX 937 ASTXS 938 ASTXSDX 939 ALXSI 940 ALXSIWAX 941 ALXSIWZX 942 ASTXSI 943 ASTXSIWX 944 AMFVSR 945 AMFVSRD 946 AMFFPRD 947 AMFVRD 948 AMFVSRWZ 949 AMFVSRLD 950 AMTVSR 951 AMTVSRD 952 AMTFPRD 953 AMTVRD 954 AMTVSRWA 955 AMTVSRWZ 956 AMTVSRDD 957 AMTVSRWS 958 AXXLAND 959 AXXLANDQ 960 AXXLANDC 961 AXXLEQV 962 AXXLNAND 963 AXXLOR 964 AXXLORC 965 AXXLNOR 966 AXXLORQ 967 AXXLXOR 968 AXXSEL 969 AXXMRG 970 AXXMRGHW 971 AXXMRGLW 972 AXXSPLT 973 AXXSPLTW 974 AXXPERM 975 AXXPERMDI 976 AXXSI 977 AXXSLDWI 978 AXSCV 979 AXSCVDPSP 980 AXSCVSPDP 981 AXSCVDPSPN 982 AXSCVSPDPN 983 AXVCV 984 AXVCVDPSP 985 AXVCVSPDP 986 AXSCVX 987 AXSCVDPSXDS 988 AXSCVDPSXWS 989 AXSCVDPUXDS 990 AXSCVDPUXWS 991 AXSCVXP 992 AXSCVSXDDP 993 AXSCVUXDDP 994 AXSCVSXDSP 995 AXSCVUXDSP 996 AXVCVX 997 AXVCVDPSXDS 998 AXVCVDPSXWS 999 AXVCVDPUXDS 1000 AXVCVDPUXWS 1001 AXVCVSPSXDS 1002 AXVCVSPSXWS 1003 AXVCVSPUXDS 1004 AXVCVSPUXWS 1005 AXVCVXP 1006 AXVCVSXDDP 1007 AXVCVSXWDP 1008 AXVCVUXDDP 1009 AXVCVUXWDP 1010 AXVCVSXDSP 1011 AXVCVSXWSP 1012 AXVCVUXDSP 1013 AXVCVUXWSP 1014 1015 ALAST 1016 1017 // aliases 1018 ABR = obj.AJMP 1019 ABL = obj.ACALL 1020 )