github.com/hikaru7719/go@v0.0.0-20181025140707-c8b2ac68906a/src/cmd/internal/obj/s390x/asmz.go (about) 1 // Based on cmd/internal/obj/ppc64/asm9.go. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package s390x 31 32 import ( 33 "cmd/internal/obj" 34 "cmd/internal/objabi" 35 "log" 36 "math" 37 "sort" 38 ) 39 40 // ctxtz holds state while assembling a single function. 41 // Each function gets a fresh ctxtz. 42 // This allows for multiple functions to be safely concurrently assembled. 43 type ctxtz struct { 44 ctxt *obj.Link 45 newprog obj.ProgAlloc 46 cursym *obj.LSym 47 autosize int32 48 instoffset int64 49 pc int64 50 } 51 52 // instruction layout. 53 const ( 54 funcAlign = 16 55 ) 56 57 type Optab struct { 58 as obj.As // opcode 59 a1 uint8 // From 60 a2 uint8 // Reg 61 a3 uint8 // From3 62 a4 uint8 // To 63 type_ int8 64 param int16 // REGSP for auto variables 65 } 66 67 var optab = []Optab{ 68 // instruction, From, Reg, From3, To, type, param 69 Optab{obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0}, 70 Optab{obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0}, 71 72 // move register 73 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 74 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 75 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 76 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 77 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 78 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 1, 0}, 79 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 80 81 // load constant 82 Optab{AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 83 Optab{AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 84 Optab{AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 85 Optab{AMOVD, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 86 Optab{AMOVW, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 87 Optab{AMOVWZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 88 Optab{AMOVB, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 89 Optab{AMOVBZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 90 91 // store constant 92 Optab{AMOVD, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 93 Optab{AMOVD, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 94 Optab{AMOVW, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 95 Optab{AMOVW, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 96 Optab{AMOVWZ, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 97 Optab{AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 98 Optab{AMOVB, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 99 Optab{AMOVB, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 100 Optab{AMOVBZ, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 101 Optab{AMOVBZ, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 102 Optab{AMOVD, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 103 Optab{AMOVD, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 104 Optab{AMOVW, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 105 Optab{AMOVW, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 106 Optab{AMOVWZ, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 107 Optab{AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 108 Optab{AMOVB, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 109 Optab{AMOVB, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 110 Optab{AMOVBZ, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 111 Optab{AMOVBZ, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 112 113 // store 114 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 115 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 116 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 117 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 118 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 119 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 120 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 121 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 122 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 123 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 124 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 125 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 126 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 127 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 128 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 129 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 130 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 131 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 132 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 133 134 // load 135 Optab{AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 136 Optab{AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 137 Optab{AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 138 Optab{AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 139 Optab{AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 140 Optab{AMOVDBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 141 Optab{AMOVHBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 142 Optab{AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 143 Optab{AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 144 Optab{AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 145 Optab{AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 146 Optab{AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 147 Optab{AMOVDBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 148 Optab{AMOVHBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 149 Optab{AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 150 Optab{AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 151 Optab{AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 152 Optab{AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 153 Optab{AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 154 155 // interlocked load and op 156 Optab{ALAAG, C_REG, C_REG, C_NONE, C_LOREG, 99, 0}, 157 158 // integer arithmetic 159 Optab{AADD, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 160 Optab{AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 161 Optab{AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 0}, 162 Optab{AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 0}, 163 Optab{AADD, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 164 Optab{AADD, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 165 Optab{ASUB, C_LCON, C_REG, C_NONE, C_REG, 21, 0}, 166 Optab{ASUB, C_LCON, C_NONE, C_NONE, C_REG, 21, 0}, 167 Optab{ASUB, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 168 Optab{ASUB, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 169 Optab{AMULHD, C_REG, C_NONE, C_NONE, C_REG, 4, 0}, 170 Optab{AMULHD, C_REG, C_REG, C_NONE, C_REG, 4, 0}, 171 Optab{ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 172 Optab{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 173 Optab{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 0}, 174 Optab{ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 0}, 175 Optab{ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 0}, 176 Optab{ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 0}, 177 178 // integer logical 179 Optab{AAND, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 180 Optab{AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 181 Optab{AAND, C_LCON, C_NONE, C_NONE, C_REG, 23, 0}, 182 Optab{AAND, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 183 Optab{AAND, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 184 Optab{AANDW, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 185 Optab{AANDW, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 186 Optab{AANDW, C_LCON, C_NONE, C_NONE, C_REG, 24, 0}, 187 Optab{AANDW, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 188 Optab{AANDW, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 189 Optab{ASLD, C_REG, C_NONE, C_NONE, C_REG, 7, 0}, 190 Optab{ASLD, C_REG, C_REG, C_NONE, C_REG, 7, 0}, 191 Optab{ASLD, C_SCON, C_REG, C_NONE, C_REG, 7, 0}, 192 Optab{ASLD, C_SCON, C_NONE, C_NONE, C_REG, 7, 0}, 193 194 // compare and swap 195 Optab{ACSG, C_REG, C_REG, C_NONE, C_SOREG, 79, 0}, 196 197 // floating point 198 Optab{AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 199 Optab{AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 0}, 200 Optab{AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 0}, 201 Optab{AFMADD, C_FREG, C_FREG, C_NONE, C_FREG, 34, 0}, 202 Optab{AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 203 Optab{AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, REGSP}, 204 Optab{AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 0}, 205 Optab{AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 0}, 206 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 207 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 0}, 208 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 0}, 209 Optab{AFMOVD, C_ZCON, C_NONE, C_NONE, C_FREG, 67, 0}, 210 Optab{ALDGR, C_REG, C_NONE, C_NONE, C_FREG, 81, 0}, 211 Optab{ALGDR, C_FREG, C_NONE, C_NONE, C_REG, 81, 0}, 212 Optab{ACEFBRA, C_REG, C_NONE, C_NONE, C_FREG, 82, 0}, 213 Optab{ACFEBRA, C_FREG, C_NONE, C_NONE, C_REG, 83, 0}, 214 Optab{AFIEBR, C_SCON, C_FREG, C_NONE, C_FREG, 48, 0}, 215 Optab{ACPSDR, C_FREG, C_FREG, C_NONE, C_FREG, 49, 0}, 216 Optab{ALTDBR, C_FREG, C_NONE, C_NONE, C_FREG, 50, 0}, 217 Optab{ATCDB, C_FREG, C_NONE, C_NONE, C_SCON, 51, 0}, 218 219 // load symbol address (plus offset) 220 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_REG, 19, 0}, 221 Optab{AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 93, 0}, 222 Optab{AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 94, 0}, 223 Optab{AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 95, 0}, 224 225 // system call 226 Optab{ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 0}, 227 Optab{ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 0}, 228 229 // branch 230 Optab{ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 0}, 231 Optab{ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 0}, 232 Optab{ABC, C_SCON, C_REG, C_NONE, C_LBRA, 16, 0}, 233 Optab{ABR, C_NONE, C_NONE, C_NONE, C_REG, 18, 0}, 234 Optab{ABR, C_REG, C_NONE, C_NONE, C_REG, 18, 0}, 235 Optab{ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 236 Optab{ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 237 Optab{ACMPBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 238 Optab{ACMPBEQ, C_REG, C_NONE, C_ADDCON, C_SBRA, 90, 0}, 239 Optab{ACMPBEQ, C_REG, C_NONE, C_SCON, C_SBRA, 90, 0}, 240 Optab{ACMPUBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 241 Optab{ACMPUBEQ, C_REG, C_NONE, C_ANDCON, C_SBRA, 90, 0}, 242 243 // move on condition 244 Optab{AMOVDEQ, C_REG, C_NONE, C_NONE, C_REG, 17, 0}, 245 246 // find leftmost one 247 Optab{AFLOGR, C_REG, C_NONE, C_NONE, C_REG, 8, 0}, 248 249 // population count 250 Optab{APOPCNT, C_REG, C_NONE, C_NONE, C_REG, 9, 0}, 251 252 // compare 253 Optab{ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 254 Optab{ACMP, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 255 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 256 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 257 Optab{AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 0}, 258 Optab{AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 0}, 259 260 // test under mask 261 Optab{ATMHH, C_REG, C_NONE, C_NONE, C_ANDCON, 91, 0}, 262 263 // 32-bit access registers 264 Optab{AMOVW, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 265 Optab{AMOVWZ, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 266 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 267 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 268 269 // macros 270 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LOREG, 96, 0}, 271 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LAUTO, 96, REGSP}, 272 273 // load/store multiple 274 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LOREG, 97, 0}, 275 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LAUTO, 97, REGSP}, 276 Optab{ALMG, C_LOREG, C_REG, C_NONE, C_REG, 98, 0}, 277 Optab{ALMG, C_LAUTO, C_REG, C_NONE, C_REG, 98, REGSP}, 278 279 // bytes 280 Optab{ABYTE, C_SCON, C_NONE, C_NONE, C_NONE, 40, 0}, 281 Optab{AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 0}, 282 Optab{ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 0}, 283 Optab{ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 0}, 284 285 // fast synchronization 286 Optab{ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 80, 0}, 287 288 // store clock 289 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SAUTO, 88, REGSP}, 290 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SOREG, 88, 0}, 291 292 // storage and storage 293 Optab{AMVC, C_SCON, C_NONE, C_LOREG, C_LOREG, 84, 0}, 294 Optab{AMVC, C_SCON, C_NONE, C_LOREG, C_LAUTO, 84, REGSP}, 295 Optab{AMVC, C_SCON, C_NONE, C_LAUTO, C_LAUTO, 84, REGSP}, 296 297 // address 298 Optab{ALARL, C_LCON, C_NONE, C_NONE, C_REG, 85, 0}, 299 Optab{ALARL, C_SYMADDR, C_NONE, C_NONE, C_REG, 85, 0}, 300 Optab{ALA, C_SOREG, C_NONE, C_NONE, C_REG, 86, 0}, 301 Optab{ALA, C_SAUTO, C_NONE, C_NONE, C_REG, 86, REGSP}, 302 Optab{AEXRL, C_SYMADDR, C_NONE, C_NONE, C_REG, 87, 0}, 303 304 // misc 305 Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 0}, 306 Optab{obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0}, 307 Optab{obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0}, 308 Optab{obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0}, 309 Optab{obj.ANOP, C_SAUTO, C_NONE, C_NONE, C_NONE, 0, 0}, 310 311 // vector instructions 312 313 // VRX store 314 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SOREG, 100, 0}, 315 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SAUTO, 100, REGSP}, 316 Optab{AVSTEG, C_SCON, C_VREG, C_NONE, C_SOREG, 100, 0}, 317 Optab{AVSTEG, C_SCON, C_VREG, C_NONE, C_SAUTO, 100, REGSP}, 318 319 // VRX load 320 Optab{AVL, C_SOREG, C_NONE, C_NONE, C_VREG, 101, 0}, 321 Optab{AVL, C_SAUTO, C_NONE, C_NONE, C_VREG, 101, REGSP}, 322 Optab{AVLEG, C_SCON, C_NONE, C_SOREG, C_VREG, 101, 0}, 323 Optab{AVLEG, C_SCON, C_NONE, C_SAUTO, C_VREG, 101, REGSP}, 324 325 // VRV scatter 326 Optab{AVSCEG, C_SCON, C_VREG, C_NONE, C_SOREG, 102, 0}, 327 Optab{AVSCEG, C_SCON, C_VREG, C_NONE, C_SAUTO, 102, REGSP}, 328 329 // VRV gather 330 Optab{AVGEG, C_SCON, C_NONE, C_SOREG, C_VREG, 103, 0}, 331 Optab{AVGEG, C_SCON, C_NONE, C_SAUTO, C_VREG, 103, REGSP}, 332 333 // VRS element shift/rotate and load gr to/from vr element 334 Optab{AVESLG, C_SCON, C_VREG, C_NONE, C_VREG, 104, 0}, 335 Optab{AVESLG, C_REG, C_VREG, C_NONE, C_VREG, 104, 0}, 336 Optab{AVESLG, C_SCON, C_NONE, C_NONE, C_VREG, 104, 0}, 337 Optab{AVESLG, C_REG, C_NONE, C_NONE, C_VREG, 104, 0}, 338 Optab{AVLGVG, C_SCON, C_VREG, C_NONE, C_REG, 104, 0}, 339 Optab{AVLGVG, C_REG, C_VREG, C_NONE, C_REG, 104, 0}, 340 Optab{AVLVGG, C_SCON, C_REG, C_NONE, C_VREG, 104, 0}, 341 Optab{AVLVGG, C_REG, C_REG, C_NONE, C_VREG, 104, 0}, 342 343 // VRS store multiple 344 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SOREG, 105, 0}, 345 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SAUTO, 105, REGSP}, 346 347 // VRS load multiple 348 Optab{AVLM, C_SOREG, C_VREG, C_NONE, C_VREG, 106, 0}, 349 Optab{AVLM, C_SAUTO, C_VREG, C_NONE, C_VREG, 106, REGSP}, 350 351 // VRS store with length 352 Optab{AVSTL, C_REG, C_VREG, C_NONE, C_SOREG, 107, 0}, 353 Optab{AVSTL, C_REG, C_VREG, C_NONE, C_SAUTO, 107, REGSP}, 354 355 // VRS load with length 356 Optab{AVLL, C_REG, C_NONE, C_SOREG, C_VREG, 108, 0}, 357 Optab{AVLL, C_REG, C_NONE, C_SAUTO, C_VREG, 108, REGSP}, 358 359 // VRI-a 360 Optab{AVGBM, C_ANDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 361 Optab{AVZERO, C_NONE, C_NONE, C_NONE, C_VREG, 109, 0}, 362 Optab{AVREPIG, C_ADDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 363 Optab{AVREPIG, C_SCON, C_NONE, C_NONE, C_VREG, 109, 0}, 364 Optab{AVLEIG, C_SCON, C_NONE, C_ADDCON, C_VREG, 109, 0}, 365 Optab{AVLEIG, C_SCON, C_NONE, C_SCON, C_VREG, 109, 0}, 366 367 // VRI-b generate mask 368 Optab{AVGMG, C_SCON, C_NONE, C_SCON, C_VREG, 110, 0}, 369 370 // VRI-c replicate 371 Optab{AVREPG, C_UCON, C_VREG, C_NONE, C_VREG, 111, 0}, 372 373 // VRI-d element rotate and insert under mask and 374 // shift left double by byte 375 Optab{AVERIMG, C_SCON, C_VREG, C_VREG, C_VREG, 112, 0}, 376 Optab{AVSLDB, C_SCON, C_VREG, C_VREG, C_VREG, 112, 0}, 377 378 // VRI-d fp test data class immediate 379 Optab{AVFTCIDB, C_SCON, C_VREG, C_NONE, C_VREG, 113, 0}, 380 381 // VRR-a load reg 382 Optab{AVLR, C_VREG, C_NONE, C_NONE, C_VREG, 114, 0}, 383 384 // VRR-a compare 385 Optab{AVECG, C_VREG, C_NONE, C_NONE, C_VREG, 115, 0}, 386 387 // VRR-b 388 Optab{AVCEQG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 389 Optab{AVFAEF, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 390 Optab{AVPKSG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 391 392 // VRR-c 393 Optab{AVAQ, C_VREG, C_VREG, C_NONE, C_VREG, 118, 0}, 394 Optab{AVAQ, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 395 Optab{AVNOT, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 396 Optab{AVPDI, C_SCON, C_VREG, C_VREG, C_VREG, 123, 0}, 397 398 // VRR-c shifts 399 Optab{AVERLLVG, C_VREG, C_VREG, C_NONE, C_VREG, 119, 0}, 400 Optab{AVERLLVG, C_VREG, C_NONE, C_NONE, C_VREG, 119, 0}, 401 402 // VRR-d 403 // 2 3 1 4 404 Optab{AVACQ, C_VREG, C_VREG, C_VREG, C_VREG, 120, 0}, 405 406 // VRR-e 407 Optab{AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 121, 0}, 408 409 // VRR-f 410 Optab{AVLVGP, C_REG, C_REG, C_NONE, C_VREG, 122, 0}, 411 } 412 413 var oprange [ALAST & obj.AMask][]Optab 414 415 var xcmp [C_NCLASS][C_NCLASS]bool 416 417 func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 418 p := cursym.Func.Text 419 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 420 return 421 } 422 423 if oprange[AORW&obj.AMask] == nil { 424 ctxt.Diag("s390x ops not initialized, call s390x.buildop first") 425 } 426 427 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 428 429 buffer := make([]byte, 0) 430 changed := true 431 loop := 0 432 for changed { 433 if loop > 100 { 434 c.ctxt.Diag("stuck in spanz loop") 435 break 436 } 437 changed = false 438 buffer = buffer[:0] 439 c.cursym.R = make([]obj.Reloc, 0) 440 for p := c.cursym.Func.Text; p != nil; p = p.Link { 441 pc := int64(len(buffer)) 442 if pc != p.Pc { 443 changed = true 444 } 445 p.Pc = pc 446 c.pc = p.Pc 447 c.asmout(p, &buffer) 448 if pc == int64(len(buffer)) { 449 switch p.As { 450 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT: 451 // ok 452 default: 453 c.ctxt.Diag("zero-width instruction\n%v", p) 454 } 455 } 456 } 457 loop++ 458 } 459 460 c.cursym.Size = int64(len(buffer)) 461 if c.cursym.Size%funcAlign != 0 { 462 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign) 463 } 464 c.cursym.Grow(c.cursym.Size) 465 copy(c.cursym.P, buffer) 466 } 467 468 func isint32(v int64) bool { 469 return int64(int32(v)) == v 470 } 471 472 func isuint32(v uint64) bool { 473 return uint64(uint32(v)) == v 474 } 475 476 func (c *ctxtz) aclass(a *obj.Addr) int { 477 switch a.Type { 478 case obj.TYPE_NONE: 479 return C_NONE 480 481 case obj.TYPE_REG: 482 if REG_R0 <= a.Reg && a.Reg <= REG_R15 { 483 return C_REG 484 } 485 if REG_F0 <= a.Reg && a.Reg <= REG_F15 { 486 return C_FREG 487 } 488 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 { 489 return C_AREG 490 } 491 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 492 return C_VREG 493 } 494 return C_GOK 495 496 case obj.TYPE_MEM: 497 switch a.Name { 498 case obj.NAME_EXTERN, 499 obj.NAME_STATIC: 500 if a.Sym == nil { 501 // must have a symbol 502 break 503 } 504 c.instoffset = a.Offset 505 if a.Sym.Type == objabi.STLSBSS { 506 if c.ctxt.Flag_shared { 507 return C_TLS_IE // initial exec model 508 } 509 return C_TLS_LE // local exec model 510 } 511 return C_ADDR 512 513 case obj.NAME_GOTREF: 514 return C_GOTADDR 515 516 case obj.NAME_AUTO: 517 if a.Reg == REGSP { 518 // unset base register for better printing, since 519 // a.Offset is still relative to pseudo-SP. 520 a.Reg = obj.REG_NONE 521 } 522 c.instoffset = int64(c.autosize) + a.Offset 523 if c.instoffset >= -BIG && c.instoffset < BIG { 524 return C_SAUTO 525 } 526 return C_LAUTO 527 528 case obj.NAME_PARAM: 529 if a.Reg == REGSP { 530 // unset base register for better printing, since 531 // a.Offset is still relative to pseudo-FP. 532 a.Reg = obj.REG_NONE 533 } 534 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 535 if c.instoffset >= -BIG && c.instoffset < BIG { 536 return C_SAUTO 537 } 538 return C_LAUTO 539 540 case obj.NAME_NONE: 541 c.instoffset = a.Offset 542 if c.instoffset == 0 { 543 return C_ZOREG 544 } 545 if c.instoffset >= -BIG && c.instoffset < BIG { 546 return C_SOREG 547 } 548 return C_LOREG 549 } 550 551 return C_GOK 552 553 case obj.TYPE_TEXTSIZE: 554 return C_TEXTSIZE 555 556 case obj.TYPE_FCONST: 557 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 { 558 return C_ZCON 559 } 560 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val) 561 562 case obj.TYPE_CONST, 563 obj.TYPE_ADDR: 564 switch a.Name { 565 case obj.NAME_NONE: 566 c.instoffset = a.Offset 567 if a.Reg != 0 { 568 if -BIG <= c.instoffset && c.instoffset <= BIG { 569 return C_SACON 570 } 571 if isint32(c.instoffset) { 572 return C_LACON 573 } 574 return C_DACON 575 } 576 577 case obj.NAME_EXTERN, 578 obj.NAME_STATIC: 579 s := a.Sym 580 if s == nil { 581 return C_GOK 582 } 583 c.instoffset = a.Offset 584 585 return C_SYMADDR 586 587 case obj.NAME_AUTO: 588 if a.Reg == REGSP { 589 // unset base register for better printing, since 590 // a.Offset is still relative to pseudo-SP. 591 a.Reg = obj.REG_NONE 592 } 593 c.instoffset = int64(c.autosize) + a.Offset 594 if c.instoffset >= -BIG && c.instoffset < BIG { 595 return C_SACON 596 } 597 return C_LACON 598 599 case obj.NAME_PARAM: 600 if a.Reg == REGSP { 601 // unset base register for better printing, since 602 // a.Offset is still relative to pseudo-FP. 603 a.Reg = obj.REG_NONE 604 } 605 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 606 if c.instoffset >= -BIG && c.instoffset < BIG { 607 return C_SACON 608 } 609 return C_LACON 610 611 default: 612 return C_GOK 613 } 614 615 if c.instoffset == 0 { 616 return C_ZCON 617 } 618 if c.instoffset >= 0 { 619 if c.instoffset <= 0x7fff { 620 return C_SCON 621 } 622 if c.instoffset <= 0xffff { 623 return C_ANDCON 624 } 625 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 626 return C_UCON 627 } 628 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 629 return C_LCON 630 } 631 return C_DCON 632 } 633 634 if c.instoffset >= -0x8000 { 635 return C_ADDCON 636 } 637 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 638 return C_UCON 639 } 640 if isint32(c.instoffset) { 641 return C_LCON 642 } 643 return C_DCON 644 645 case obj.TYPE_BRANCH: 646 return C_SBRA 647 } 648 649 return C_GOK 650 } 651 652 func (c *ctxtz) oplook(p *obj.Prog) *Optab { 653 a1 := int(p.Optab) 654 if a1 != 0 { 655 return &optab[a1-1] 656 } 657 a1 = int(p.From.Class) 658 if a1 == 0 { 659 a1 = c.aclass(&p.From) + 1 660 p.From.Class = int8(a1) 661 } 662 663 a1-- 664 a3 := C_NONE + 1 665 if p.GetFrom3() != nil { 666 a3 = int(p.GetFrom3().Class) 667 if a3 == 0 { 668 a3 = c.aclass(p.GetFrom3()) + 1 669 p.GetFrom3().Class = int8(a3) 670 } 671 } 672 673 a3-- 674 a4 := int(p.To.Class) 675 if a4 == 0 { 676 a4 = c.aclass(&p.To) + 1 677 p.To.Class = int8(a4) 678 } 679 680 a4-- 681 a2 := C_NONE 682 if p.Reg != 0 { 683 if REG_R0 <= p.Reg && p.Reg <= REG_R15 { 684 a2 = C_REG 685 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 686 a2 = C_VREG 687 } else if REG_F0 <= p.Reg && p.Reg <= REG_F15 { 688 a2 = C_FREG 689 } else if REG_AR0 <= p.Reg && p.Reg <= REG_AR15 { 690 a2 = C_AREG 691 } 692 } 693 694 ops := oprange[p.As&obj.AMask] 695 c1 := &xcmp[a1] 696 c2 := &xcmp[a2] 697 c3 := &xcmp[a3] 698 c4 := &xcmp[a4] 699 for i := range ops { 700 op := &ops[i] 701 if (int(op.a2) == a2 || c2[op.a2]) && c4[op.a4] && c1[op.a1] && c3[op.a3] { 702 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 703 return op 704 } 705 } 706 707 // cannot find a case; abort 708 c.ctxt.Diag("illegal combination %v %v %v %v %v\n", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 709 c.ctxt.Diag("prog: %v\n", p) 710 return nil 711 } 712 713 func cmp(a int, b int) bool { 714 if a == b { 715 return true 716 } 717 switch a { 718 case C_DCON: 719 if b == C_LCON { 720 return true 721 } 722 fallthrough 723 case C_LCON: 724 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 725 return true 726 } 727 728 case C_ADDCON: 729 if b == C_ZCON || b == C_SCON { 730 return true 731 } 732 733 case C_ANDCON: 734 if b == C_ZCON || b == C_SCON { 735 return true 736 } 737 738 case C_UCON: 739 if b == C_ZCON || b == C_SCON { 740 return true 741 } 742 743 case C_SCON: 744 if b == C_ZCON { 745 return true 746 } 747 748 case C_LACON: 749 if b == C_SACON { 750 return true 751 } 752 753 case C_LBRA: 754 if b == C_SBRA { 755 return true 756 } 757 758 case C_LAUTO: 759 if b == C_SAUTO { 760 return true 761 } 762 763 case C_LOREG: 764 if b == C_ZOREG || b == C_SOREG { 765 return true 766 } 767 768 case C_SOREG: 769 if b == C_ZOREG { 770 return true 771 } 772 773 case C_ANY: 774 return true 775 } 776 777 return false 778 } 779 780 type ocmp []Optab 781 782 func (x ocmp) Len() int { 783 return len(x) 784 } 785 786 func (x ocmp) Swap(i, j int) { 787 x[i], x[j] = x[j], x[i] 788 } 789 790 func (x ocmp) Less(i, j int) bool { 791 p1 := &x[i] 792 p2 := &x[j] 793 n := int(p1.as) - int(p2.as) 794 if n != 0 { 795 return n < 0 796 } 797 n = int(p1.a1) - int(p2.a1) 798 if n != 0 { 799 return n < 0 800 } 801 n = int(p1.a2) - int(p2.a2) 802 if n != 0 { 803 return n < 0 804 } 805 n = int(p1.a3) - int(p2.a3) 806 if n != 0 { 807 return n < 0 808 } 809 n = int(p1.a4) - int(p2.a4) 810 if n != 0 { 811 return n < 0 812 } 813 return false 814 } 815 func opset(a, b obj.As) { 816 oprange[a&obj.AMask] = oprange[b&obj.AMask] 817 } 818 819 func buildop(ctxt *obj.Link) { 820 if oprange[AORW&obj.AMask] != nil { 821 // Already initialized; stop now. 822 // This happens in the cmd/asm tests, 823 // each of which re-initializes the arch. 824 return 825 } 826 827 for i := 0; i < C_NCLASS; i++ { 828 for n := 0; n < C_NCLASS; n++ { 829 if cmp(n, i) { 830 xcmp[i][n] = true 831 } 832 } 833 } 834 sort.Sort(ocmp(optab)) 835 for i := 0; i < len(optab); i++ { 836 r := optab[i].as 837 start := i 838 for ; i+1 < len(optab); i++ { 839 if optab[i+1].as != r { 840 break 841 } 842 } 843 oprange[r&obj.AMask] = optab[start : i+1] 844 845 // opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array. 846 // oprange[] is used by oplook() to find the Optab entry that applies to a given Prog. 847 switch r { 848 case AADD: 849 opset(AADDC, r) 850 opset(AADDW, r) 851 opset(AMULLD, r) 852 opset(AMULLW, r) 853 case ADIVW: 854 opset(AADDE, r) 855 opset(ADIVD, r) 856 opset(ADIVDU, r) 857 opset(ADIVWU, r) 858 opset(AMODD, r) 859 opset(AMODDU, r) 860 opset(AMODW, r) 861 opset(AMODWU, r) 862 case AMULHD: 863 opset(AMULHDU, r) 864 case AMOVBZ: 865 opset(AMOVH, r) 866 opset(AMOVHZ, r) 867 case ALA: 868 opset(ALAY, r) 869 case AMVC: 870 opset(ACLC, r) 871 opset(AXC, r) 872 opset(AOC, r) 873 opset(ANC, r) 874 case ASTCK: 875 opset(ASTCKC, r) 876 opset(ASTCKE, r) 877 opset(ASTCKF, r) 878 case ALAAG: 879 opset(ALAA, r) 880 opset(ALAAL, r) 881 opset(ALAALG, r) 882 opset(ALAN, r) 883 opset(ALANG, r) 884 opset(ALAX, r) 885 opset(ALAXG, r) 886 opset(ALAO, r) 887 opset(ALAOG, r) 888 case ASTMG: 889 opset(ASTMY, r) 890 case ALMG: 891 opset(ALMY, r) 892 case ABEQ: 893 opset(ABGE, r) 894 opset(ABGT, r) 895 opset(ABLE, r) 896 opset(ABLT, r) 897 opset(ABNE, r) 898 opset(ABVC, r) 899 opset(ABVS, r) 900 opset(ABLEU, r) 901 opset(ABLTU, r) 902 case ABR: 903 opset(ABL, r) 904 case ABC: 905 opset(ABCL, r) 906 case AFABS: 907 opset(AFNABS, r) 908 opset(ALPDFR, r) 909 opset(ALNDFR, r) 910 opset(AFNEG, r) 911 opset(AFNEGS, r) 912 opset(ALEDBR, r) 913 opset(ALDEBR, r) 914 opset(AFSQRT, r) 915 opset(AFSQRTS, r) 916 case AFADD: 917 opset(AFADDS, r) 918 opset(AFDIV, r) 919 opset(AFDIVS, r) 920 opset(AFSUB, r) 921 opset(AFSUBS, r) 922 case AFMADD: 923 opset(AFMADDS, r) 924 opset(AFMSUB, r) 925 opset(AFMSUBS, r) 926 case AFMUL: 927 opset(AFMULS, r) 928 case AFCMPO: 929 opset(AFCMPU, r) 930 opset(ACEBR, r) 931 case AAND: 932 opset(AOR, r) 933 opset(AXOR, r) 934 case AANDW: 935 opset(AORW, r) 936 opset(AXORW, r) 937 case ASLD: 938 opset(ASRD, r) 939 opset(ASLW, r) 940 opset(ASRW, r) 941 opset(ASRAD, r) 942 opset(ASRAW, r) 943 opset(ARLL, r) 944 opset(ARLLG, r) 945 case ACSG: 946 opset(ACS, r) 947 case ASUB: 948 opset(ASUBC, r) 949 opset(ASUBE, r) 950 opset(ASUBW, r) 951 case ANEG: 952 opset(ANEGW, r) 953 case AFMOVD: 954 opset(AFMOVS, r) 955 case AMOVDBR: 956 opset(AMOVWBR, r) 957 case ACMP: 958 opset(ACMPW, r) 959 case ACMPU: 960 opset(ACMPWU, r) 961 case ATMHH: 962 opset(ATMHL, r) 963 opset(ATMLH, r) 964 opset(ATMLL, r) 965 case ACEFBRA: 966 opset(ACDFBRA, r) 967 opset(ACEGBRA, r) 968 opset(ACDGBRA, r) 969 opset(ACELFBR, r) 970 opset(ACDLFBR, r) 971 opset(ACELGBR, r) 972 opset(ACDLGBR, r) 973 case ACFEBRA: 974 opset(ACFDBRA, r) 975 opset(ACGEBRA, r) 976 opset(ACGDBRA, r) 977 opset(ACLFEBR, r) 978 opset(ACLFDBR, r) 979 opset(ACLGEBR, r) 980 opset(ACLGDBR, r) 981 case AFIEBR: 982 opset(AFIDBR, r) 983 case ACMPBEQ: 984 opset(ACMPBGE, r) 985 opset(ACMPBGT, r) 986 opset(ACMPBLE, r) 987 opset(ACMPBLT, r) 988 opset(ACMPBNE, r) 989 case ACMPUBEQ: 990 opset(ACMPUBGE, r) 991 opset(ACMPUBGT, r) 992 opset(ACMPUBLE, r) 993 opset(ACMPUBLT, r) 994 opset(ACMPUBNE, r) 995 case AMOVDEQ: 996 opset(AMOVDGE, r) 997 opset(AMOVDGT, r) 998 opset(AMOVDLE, r) 999 opset(AMOVDLT, r) 1000 opset(AMOVDNE, r) 1001 case ALTDBR: 1002 opset(ALTEBR, r) 1003 case ATCDB: 1004 opset(ATCEB, r) 1005 case AVL: 1006 opset(AVLLEZB, r) 1007 opset(AVLLEZH, r) 1008 opset(AVLLEZF, r) 1009 opset(AVLLEZG, r) 1010 opset(AVLREPB, r) 1011 opset(AVLREPH, r) 1012 opset(AVLREPF, r) 1013 opset(AVLREPG, r) 1014 case AVLEG: 1015 opset(AVLBB, r) 1016 opset(AVLEB, r) 1017 opset(AVLEH, r) 1018 opset(AVLEF, r) 1019 opset(AVLEG, r) 1020 opset(AVLREP, r) 1021 case AVSTEG: 1022 opset(AVSTEB, r) 1023 opset(AVSTEH, r) 1024 opset(AVSTEF, r) 1025 case AVSCEG: 1026 opset(AVSCEF, r) 1027 case AVGEG: 1028 opset(AVGEF, r) 1029 case AVESLG: 1030 opset(AVESLB, r) 1031 opset(AVESLH, r) 1032 opset(AVESLF, r) 1033 opset(AVERLLB, r) 1034 opset(AVERLLH, r) 1035 opset(AVERLLF, r) 1036 opset(AVERLLG, r) 1037 opset(AVESRAB, r) 1038 opset(AVESRAH, r) 1039 opset(AVESRAF, r) 1040 opset(AVESRAG, r) 1041 opset(AVESRLB, r) 1042 opset(AVESRLH, r) 1043 opset(AVESRLF, r) 1044 opset(AVESRLG, r) 1045 case AVLGVG: 1046 opset(AVLGVB, r) 1047 opset(AVLGVH, r) 1048 opset(AVLGVF, r) 1049 case AVLVGG: 1050 opset(AVLVGB, r) 1051 opset(AVLVGH, r) 1052 opset(AVLVGF, r) 1053 case AVZERO: 1054 opset(AVONE, r) 1055 case AVREPIG: 1056 opset(AVREPIB, r) 1057 opset(AVREPIH, r) 1058 opset(AVREPIF, r) 1059 case AVLEIG: 1060 opset(AVLEIB, r) 1061 opset(AVLEIH, r) 1062 opset(AVLEIF, r) 1063 case AVGMG: 1064 opset(AVGMB, r) 1065 opset(AVGMH, r) 1066 opset(AVGMF, r) 1067 case AVREPG: 1068 opset(AVREPB, r) 1069 opset(AVREPH, r) 1070 opset(AVREPF, r) 1071 case AVERIMG: 1072 opset(AVERIMB, r) 1073 opset(AVERIMH, r) 1074 opset(AVERIMF, r) 1075 case AVFTCIDB: 1076 opset(AWFTCIDB, r) 1077 case AVLR: 1078 opset(AVUPHB, r) 1079 opset(AVUPHH, r) 1080 opset(AVUPHF, r) 1081 opset(AVUPLHB, r) 1082 opset(AVUPLHH, r) 1083 opset(AVUPLHF, r) 1084 opset(AVUPLB, r) 1085 opset(AVUPLHW, r) 1086 opset(AVUPLF, r) 1087 opset(AVUPLLB, r) 1088 opset(AVUPLLH, r) 1089 opset(AVUPLLF, r) 1090 opset(AVCLZB, r) 1091 opset(AVCLZH, r) 1092 opset(AVCLZF, r) 1093 opset(AVCLZG, r) 1094 opset(AVCTZB, r) 1095 opset(AVCTZH, r) 1096 opset(AVCTZF, r) 1097 opset(AVCTZG, r) 1098 opset(AVLDEB, r) 1099 opset(AWLDEB, r) 1100 opset(AVFLCDB, r) 1101 opset(AWFLCDB, r) 1102 opset(AVFLNDB, r) 1103 opset(AWFLNDB, r) 1104 opset(AVFLPDB, r) 1105 opset(AWFLPDB, r) 1106 opset(AVFSQDB, r) 1107 opset(AWFSQDB, r) 1108 opset(AVISTRB, r) 1109 opset(AVISTRH, r) 1110 opset(AVISTRF, r) 1111 opset(AVISTRBS, r) 1112 opset(AVISTRHS, r) 1113 opset(AVISTRFS, r) 1114 opset(AVLCB, r) 1115 opset(AVLCH, r) 1116 opset(AVLCF, r) 1117 opset(AVLCG, r) 1118 opset(AVLPB, r) 1119 opset(AVLPH, r) 1120 opset(AVLPF, r) 1121 opset(AVLPG, r) 1122 opset(AVPOPCT, r) 1123 opset(AVSEGB, r) 1124 opset(AVSEGH, r) 1125 opset(AVSEGF, r) 1126 case AVECG: 1127 opset(AVECB, r) 1128 opset(AVECH, r) 1129 opset(AVECF, r) 1130 opset(AVECLB, r) 1131 opset(AVECLH, r) 1132 opset(AVECLF, r) 1133 opset(AVECLG, r) 1134 opset(AWFCDB, r) 1135 opset(AWFKDB, r) 1136 case AVCEQG: 1137 opset(AVCEQB, r) 1138 opset(AVCEQH, r) 1139 opset(AVCEQF, r) 1140 opset(AVCEQBS, r) 1141 opset(AVCEQHS, r) 1142 opset(AVCEQFS, r) 1143 opset(AVCEQGS, r) 1144 opset(AVCHB, r) 1145 opset(AVCHH, r) 1146 opset(AVCHF, r) 1147 opset(AVCHG, r) 1148 opset(AVCHBS, r) 1149 opset(AVCHHS, r) 1150 opset(AVCHFS, r) 1151 opset(AVCHGS, r) 1152 opset(AVCHLB, r) 1153 opset(AVCHLH, r) 1154 opset(AVCHLF, r) 1155 opset(AVCHLG, r) 1156 opset(AVCHLBS, r) 1157 opset(AVCHLHS, r) 1158 opset(AVCHLFS, r) 1159 opset(AVCHLGS, r) 1160 case AVFAEF: 1161 opset(AVFAEB, r) 1162 opset(AVFAEH, r) 1163 opset(AVFAEBS, r) 1164 opset(AVFAEHS, r) 1165 opset(AVFAEFS, r) 1166 opset(AVFAEZB, r) 1167 opset(AVFAEZH, r) 1168 opset(AVFAEZF, r) 1169 opset(AVFAEZBS, r) 1170 opset(AVFAEZHS, r) 1171 opset(AVFAEZFS, r) 1172 opset(AVFEEB, r) 1173 opset(AVFEEH, r) 1174 opset(AVFEEF, r) 1175 opset(AVFEEBS, r) 1176 opset(AVFEEHS, r) 1177 opset(AVFEEFS, r) 1178 opset(AVFEEZB, r) 1179 opset(AVFEEZH, r) 1180 opset(AVFEEZF, r) 1181 opset(AVFEEZBS, r) 1182 opset(AVFEEZHS, r) 1183 opset(AVFEEZFS, r) 1184 opset(AVFENEB, r) 1185 opset(AVFENEH, r) 1186 opset(AVFENEF, r) 1187 opset(AVFENEBS, r) 1188 opset(AVFENEHS, r) 1189 opset(AVFENEFS, r) 1190 opset(AVFENEZB, r) 1191 opset(AVFENEZH, r) 1192 opset(AVFENEZF, r) 1193 opset(AVFENEZBS, r) 1194 opset(AVFENEZHS, r) 1195 opset(AVFENEZFS, r) 1196 case AVPKSG: 1197 opset(AVPKSH, r) 1198 opset(AVPKSF, r) 1199 opset(AVPKSHS, r) 1200 opset(AVPKSFS, r) 1201 opset(AVPKSGS, r) 1202 opset(AVPKLSH, r) 1203 opset(AVPKLSF, r) 1204 opset(AVPKLSG, r) 1205 opset(AVPKLSHS, r) 1206 opset(AVPKLSFS, r) 1207 opset(AVPKLSGS, r) 1208 case AVAQ: 1209 opset(AVAB, r) 1210 opset(AVAH, r) 1211 opset(AVAF, r) 1212 opset(AVAG, r) 1213 opset(AVACCB, r) 1214 opset(AVACCH, r) 1215 opset(AVACCF, r) 1216 opset(AVACCG, r) 1217 opset(AVACCQ, r) 1218 opset(AVN, r) 1219 opset(AVNC, r) 1220 opset(AVAVGB, r) 1221 opset(AVAVGH, r) 1222 opset(AVAVGF, r) 1223 opset(AVAVGG, r) 1224 opset(AVAVGLB, r) 1225 opset(AVAVGLH, r) 1226 opset(AVAVGLF, r) 1227 opset(AVAVGLG, r) 1228 opset(AVCKSM, r) 1229 opset(AVX, r) 1230 opset(AVFADB, r) 1231 opset(AWFADB, r) 1232 opset(AVFCEDB, r) 1233 opset(AVFCEDBS, r) 1234 opset(AWFCEDB, r) 1235 opset(AWFCEDBS, r) 1236 opset(AVFCHDB, r) 1237 opset(AVFCHDBS, r) 1238 opset(AWFCHDB, r) 1239 opset(AWFCHDBS, r) 1240 opset(AVFCHEDB, r) 1241 opset(AVFCHEDBS, r) 1242 opset(AWFCHEDB, r) 1243 opset(AWFCHEDBS, r) 1244 opset(AVFMDB, r) 1245 opset(AWFMDB, r) 1246 opset(AVGFMB, r) 1247 opset(AVGFMH, r) 1248 opset(AVGFMF, r) 1249 opset(AVGFMG, r) 1250 opset(AVMXB, r) 1251 opset(AVMXH, r) 1252 opset(AVMXF, r) 1253 opset(AVMXG, r) 1254 opset(AVMXLB, r) 1255 opset(AVMXLH, r) 1256 opset(AVMXLF, r) 1257 opset(AVMXLG, r) 1258 opset(AVMNB, r) 1259 opset(AVMNH, r) 1260 opset(AVMNF, r) 1261 opset(AVMNG, r) 1262 opset(AVMNLB, r) 1263 opset(AVMNLH, r) 1264 opset(AVMNLF, r) 1265 opset(AVMNLG, r) 1266 opset(AVMRHB, r) 1267 opset(AVMRHH, r) 1268 opset(AVMRHF, r) 1269 opset(AVMRHG, r) 1270 opset(AVMRLB, r) 1271 opset(AVMRLH, r) 1272 opset(AVMRLF, r) 1273 opset(AVMRLG, r) 1274 opset(AVMEB, r) 1275 opset(AVMEH, r) 1276 opset(AVMEF, r) 1277 opset(AVMLEB, r) 1278 opset(AVMLEH, r) 1279 opset(AVMLEF, r) 1280 opset(AVMOB, r) 1281 opset(AVMOH, r) 1282 opset(AVMOF, r) 1283 opset(AVMLOB, r) 1284 opset(AVMLOH, r) 1285 opset(AVMLOF, r) 1286 opset(AVMHB, r) 1287 opset(AVMHH, r) 1288 opset(AVMHF, r) 1289 opset(AVMLHB, r) 1290 opset(AVMLHH, r) 1291 opset(AVMLHF, r) 1292 opset(AVMLH, r) 1293 opset(AVMLHW, r) 1294 opset(AVMLF, r) 1295 opset(AVNO, r) 1296 opset(AVO, r) 1297 opset(AVPKH, r) 1298 opset(AVPKF, r) 1299 opset(AVPKG, r) 1300 opset(AVSUMGH, r) 1301 opset(AVSUMGF, r) 1302 opset(AVSUMQF, r) 1303 opset(AVSUMQG, r) 1304 opset(AVSUMB, r) 1305 opset(AVSUMH, r) 1306 case AVERLLVG: 1307 opset(AVERLLVB, r) 1308 opset(AVERLLVH, r) 1309 opset(AVERLLVF, r) 1310 opset(AVESLVB, r) 1311 opset(AVESLVH, r) 1312 opset(AVESLVF, r) 1313 opset(AVESLVG, r) 1314 opset(AVESRAVB, r) 1315 opset(AVESRAVH, r) 1316 opset(AVESRAVF, r) 1317 opset(AVESRAVG, r) 1318 opset(AVESRLVB, r) 1319 opset(AVESRLVH, r) 1320 opset(AVESRLVF, r) 1321 opset(AVESRLVG, r) 1322 opset(AVFDDB, r) 1323 opset(AWFDDB, r) 1324 opset(AVFSDB, r) 1325 opset(AWFSDB, r) 1326 opset(AVSL, r) 1327 opset(AVSLB, r) 1328 opset(AVSRA, r) 1329 opset(AVSRAB, r) 1330 opset(AVSRL, r) 1331 opset(AVSRLB, r) 1332 opset(AVSF, r) 1333 opset(AVSG, r) 1334 opset(AVSQ, r) 1335 opset(AVSCBIB, r) 1336 opset(AVSCBIH, r) 1337 opset(AVSCBIF, r) 1338 opset(AVSCBIG, r) 1339 opset(AVSCBIQ, r) 1340 case AVACQ: 1341 opset(AVACCCQ, r) 1342 opset(AVGFMAB, r) 1343 opset(AVGFMAH, r) 1344 opset(AVGFMAF, r) 1345 opset(AVGFMAG, r) 1346 opset(AVMALB, r) 1347 opset(AVMALHW, r) 1348 opset(AVMALF, r) 1349 opset(AVMAHB, r) 1350 opset(AVMAHH, r) 1351 opset(AVMAHF, r) 1352 opset(AVMALHB, r) 1353 opset(AVMALHH, r) 1354 opset(AVMALHF, r) 1355 opset(AVMAEB, r) 1356 opset(AVMAEH, r) 1357 opset(AVMAEF, r) 1358 opset(AVMALEB, r) 1359 opset(AVMALEH, r) 1360 opset(AVMALEF, r) 1361 opset(AVMAOB, r) 1362 opset(AVMAOH, r) 1363 opset(AVMAOF, r) 1364 opset(AVMALOB, r) 1365 opset(AVMALOH, r) 1366 opset(AVMALOF, r) 1367 opset(AVSTRCB, r) 1368 opset(AVSTRCH, r) 1369 opset(AVSTRCF, r) 1370 opset(AVSTRCBS, r) 1371 opset(AVSTRCHS, r) 1372 opset(AVSTRCFS, r) 1373 opset(AVSTRCZB, r) 1374 opset(AVSTRCZH, r) 1375 opset(AVSTRCZF, r) 1376 opset(AVSTRCZBS, r) 1377 opset(AVSTRCZHS, r) 1378 opset(AVSTRCZFS, r) 1379 opset(AVSBCBIQ, r) 1380 opset(AVSBIQ, r) 1381 opset(AVMSLG, r) 1382 case AVSEL: 1383 opset(AVFMADB, r) 1384 opset(AWFMADB, r) 1385 opset(AVFMSDB, r) 1386 opset(AWFMSDB, r) 1387 opset(AVPERM, r) 1388 } 1389 } 1390 } 1391 1392 const ( 1393 op_A uint32 = 0x5A00 // FORMAT_RX1 ADD (32) 1394 op_AD uint32 = 0x6A00 // FORMAT_RX1 ADD NORMALIZED (long HFP) 1395 op_ADB uint32 = 0xED1A // FORMAT_RXE ADD (long BFP) 1396 op_ADBR uint32 = 0xB31A // FORMAT_RRE ADD (long BFP) 1397 op_ADR uint32 = 0x2A00 // FORMAT_RR ADD NORMALIZED (long HFP) 1398 op_ADTR uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1399 op_ADTRA uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1400 op_AE uint32 = 0x7A00 // FORMAT_RX1 ADD NORMALIZED (short HFP) 1401 op_AEB uint32 = 0xED0A // FORMAT_RXE ADD (short BFP) 1402 op_AEBR uint32 = 0xB30A // FORMAT_RRE ADD (short BFP) 1403 op_AER uint32 = 0x3A00 // FORMAT_RR ADD NORMALIZED (short HFP) 1404 op_AFI uint32 = 0xC209 // FORMAT_RIL1 ADD IMMEDIATE (32) 1405 op_AG uint32 = 0xE308 // FORMAT_RXY1 ADD (64) 1406 op_AGF uint32 = 0xE318 // FORMAT_RXY1 ADD (64<-32) 1407 op_AGFI uint32 = 0xC208 // FORMAT_RIL1 ADD IMMEDIATE (64<-32) 1408 op_AGFR uint32 = 0xB918 // FORMAT_RRE ADD (64<-32) 1409 op_AGHI uint32 = 0xA70B // FORMAT_RI1 ADD HALFWORD IMMEDIATE (64) 1410 op_AGHIK uint32 = 0xECD9 // FORMAT_RIE4 ADD IMMEDIATE (64<-16) 1411 op_AGR uint32 = 0xB908 // FORMAT_RRE ADD (64) 1412 op_AGRK uint32 = 0xB9E8 // FORMAT_RRF1 ADD (64) 1413 op_AGSI uint32 = 0xEB7A // FORMAT_SIY ADD IMMEDIATE (64<-8) 1414 op_AH uint32 = 0x4A00 // FORMAT_RX1 ADD HALFWORD 1415 op_AHHHR uint32 = 0xB9C8 // FORMAT_RRF1 ADD HIGH (32) 1416 op_AHHLR uint32 = 0xB9D8 // FORMAT_RRF1 ADD HIGH (32) 1417 op_AHI uint32 = 0xA70A // FORMAT_RI1 ADD HALFWORD IMMEDIATE (32) 1418 op_AHIK uint32 = 0xECD8 // FORMAT_RIE4 ADD IMMEDIATE (32<-16) 1419 op_AHY uint32 = 0xE37A // FORMAT_RXY1 ADD HALFWORD 1420 op_AIH uint32 = 0xCC08 // FORMAT_RIL1 ADD IMMEDIATE HIGH (32) 1421 op_AL uint32 = 0x5E00 // FORMAT_RX1 ADD LOGICAL (32) 1422 op_ALC uint32 = 0xE398 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (32) 1423 op_ALCG uint32 = 0xE388 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (64) 1424 op_ALCGR uint32 = 0xB988 // FORMAT_RRE ADD LOGICAL WITH CARRY (64) 1425 op_ALCR uint32 = 0xB998 // FORMAT_RRE ADD LOGICAL WITH CARRY (32) 1426 op_ALFI uint32 = 0xC20B // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (32) 1427 op_ALG uint32 = 0xE30A // FORMAT_RXY1 ADD LOGICAL (64) 1428 op_ALGF uint32 = 0xE31A // FORMAT_RXY1 ADD LOGICAL (64<-32) 1429 op_ALGFI uint32 = 0xC20A // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (64<-32) 1430 op_ALGFR uint32 = 0xB91A // FORMAT_RRE ADD LOGICAL (64<-32) 1431 op_ALGHSIK uint32 = 0xECDB // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16) 1432 op_ALGR uint32 = 0xB90A // FORMAT_RRE ADD LOGICAL (64) 1433 op_ALGRK uint32 = 0xB9EA // FORMAT_RRF1 ADD LOGICAL (64) 1434 op_ALGSI uint32 = 0xEB7E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8) 1435 op_ALHHHR uint32 = 0xB9CA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1436 op_ALHHLR uint32 = 0xB9DA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1437 op_ALHSIK uint32 = 0xECDA // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16) 1438 op_ALR uint32 = 0x1E00 // FORMAT_RR ADD LOGICAL (32) 1439 op_ALRK uint32 = 0xB9FA // FORMAT_RRF1 ADD LOGICAL (32) 1440 op_ALSI uint32 = 0xEB6E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8) 1441 op_ALSIH uint32 = 0xCC0A // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1442 op_ALSIHN uint32 = 0xCC0B // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1443 op_ALY uint32 = 0xE35E // FORMAT_RXY1 ADD LOGICAL (32) 1444 op_AP uint32 = 0xFA00 // FORMAT_SS2 ADD DECIMAL 1445 op_AR uint32 = 0x1A00 // FORMAT_RR ADD (32) 1446 op_ARK uint32 = 0xB9F8 // FORMAT_RRF1 ADD (32) 1447 op_ASI uint32 = 0xEB6A // FORMAT_SIY ADD IMMEDIATE (32<-8) 1448 op_AU uint32 = 0x7E00 // FORMAT_RX1 ADD UNNORMALIZED (short HFP) 1449 op_AUR uint32 = 0x3E00 // FORMAT_RR ADD UNNORMALIZED (short HFP) 1450 op_AW uint32 = 0x6E00 // FORMAT_RX1 ADD UNNORMALIZED (long HFP) 1451 op_AWR uint32 = 0x2E00 // FORMAT_RR ADD UNNORMALIZED (long HFP) 1452 op_AXBR uint32 = 0xB34A // FORMAT_RRE ADD (extended BFP) 1453 op_AXR uint32 = 0x3600 // FORMAT_RR ADD NORMALIZED (extended HFP) 1454 op_AXTR uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1455 op_AXTRA uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1456 op_AY uint32 = 0xE35A // FORMAT_RXY1 ADD (32) 1457 op_BAKR uint32 = 0xB240 // FORMAT_RRE BRANCH AND STACK 1458 op_BAL uint32 = 0x4500 // FORMAT_RX1 BRANCH AND LINK 1459 op_BALR uint32 = 0x0500 // FORMAT_RR BRANCH AND LINK 1460 op_BAS uint32 = 0x4D00 // FORMAT_RX1 BRANCH AND SAVE 1461 op_BASR uint32 = 0x0D00 // FORMAT_RR BRANCH AND SAVE 1462 op_BASSM uint32 = 0x0C00 // FORMAT_RR BRANCH AND SAVE AND SET MODE 1463 op_BC uint32 = 0x4700 // FORMAT_RX2 BRANCH ON CONDITION 1464 op_BCR uint32 = 0x0700 // FORMAT_RR BRANCH ON CONDITION 1465 op_BCT uint32 = 0x4600 // FORMAT_RX1 BRANCH ON COUNT (32) 1466 op_BCTG uint32 = 0xE346 // FORMAT_RXY1 BRANCH ON COUNT (64) 1467 op_BCTGR uint32 = 0xB946 // FORMAT_RRE BRANCH ON COUNT (64) 1468 op_BCTR uint32 = 0x0600 // FORMAT_RR BRANCH ON COUNT (32) 1469 op_BPP uint32 = 0xC700 // FORMAT_SMI BRANCH PREDICTION PRELOAD 1470 op_BPRP uint32 = 0xC500 // FORMAT_MII BRANCH PREDICTION RELATIVE PRELOAD 1471 op_BRAS uint32 = 0xA705 // FORMAT_RI2 BRANCH RELATIVE AND SAVE 1472 op_BRASL uint32 = 0xC005 // FORMAT_RIL2 BRANCH RELATIVE AND SAVE LONG 1473 op_BRC uint32 = 0xA704 // FORMAT_RI3 BRANCH RELATIVE ON CONDITION 1474 op_BRCL uint32 = 0xC004 // FORMAT_RIL3 BRANCH RELATIVE ON CONDITION LONG 1475 op_BRCT uint32 = 0xA706 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (32) 1476 op_BRCTG uint32 = 0xA707 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (64) 1477 op_BRCTH uint32 = 0xCC06 // FORMAT_RIL2 BRANCH RELATIVE ON COUNT HIGH (32) 1478 op_BRXH uint32 = 0x8400 // FORMAT_RSI BRANCH RELATIVE ON INDEX HIGH (32) 1479 op_BRXHG uint32 = 0xEC44 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX HIGH (64) 1480 op_BRXLE uint32 = 0x8500 // FORMAT_RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32) 1481 op_BRXLG uint32 = 0xEC45 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX LOW OR EQ. (64) 1482 op_BSA uint32 = 0xB25A // FORMAT_RRE BRANCH AND SET AUTHORITY 1483 op_BSG uint32 = 0xB258 // FORMAT_RRE BRANCH IN SUBSPACE GROUP 1484 op_BSM uint32 = 0x0B00 // FORMAT_RR BRANCH AND SET MODE 1485 op_BXH uint32 = 0x8600 // FORMAT_RS1 BRANCH ON INDEX HIGH (32) 1486 op_BXHG uint32 = 0xEB44 // FORMAT_RSY1 BRANCH ON INDEX HIGH (64) 1487 op_BXLE uint32 = 0x8700 // FORMAT_RS1 BRANCH ON INDEX LOW OR EQUAL (32) 1488 op_BXLEG uint32 = 0xEB45 // FORMAT_RSY1 BRANCH ON INDEX LOW OR EQUAL (64) 1489 op_C uint32 = 0x5900 // FORMAT_RX1 COMPARE (32) 1490 op_CD uint32 = 0x6900 // FORMAT_RX1 COMPARE (long HFP) 1491 op_CDB uint32 = 0xED19 // FORMAT_RXE COMPARE (long BFP) 1492 op_CDBR uint32 = 0xB319 // FORMAT_RRE COMPARE (long BFP) 1493 op_CDFBR uint32 = 0xB395 // FORMAT_RRE CONVERT FROM FIXED (32 to long BFP) 1494 op_CDFBRA uint32 = 0xB395 // FORMAT_RRF5 CONVERT FROM FIXED (32 to long BFP) 1495 op_CDFR uint32 = 0xB3B5 // FORMAT_RRE CONVERT FROM FIXED (32 to long HFP) 1496 op_CDFTR uint32 = 0xB951 // FORMAT_RRE CONVERT FROM FIXED (32 to long DFP) 1497 op_CDGBR uint32 = 0xB3A5 // FORMAT_RRE CONVERT FROM FIXED (64 to long BFP) 1498 op_CDGBRA uint32 = 0xB3A5 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long BFP) 1499 op_CDGR uint32 = 0xB3C5 // FORMAT_RRE CONVERT FROM FIXED (64 to long HFP) 1500 op_CDGTR uint32 = 0xB3F1 // FORMAT_RRE CONVERT FROM FIXED (64 to long DFP) 1501 op_CDGTRA uint32 = 0xB3F1 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long DFP) 1502 op_CDLFBR uint32 = 0xB391 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long BFP) 1503 op_CDLFTR uint32 = 0xB953 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long DFP) 1504 op_CDLGBR uint32 = 0xB3A1 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long BFP) 1505 op_CDLGTR uint32 = 0xB952 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long DFP) 1506 op_CDR uint32 = 0x2900 // FORMAT_RR COMPARE (long HFP) 1507 op_CDS uint32 = 0xBB00 // FORMAT_RS1 COMPARE DOUBLE AND SWAP (32) 1508 op_CDSG uint32 = 0xEB3E // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (64) 1509 op_CDSTR uint32 = 0xB3F3 // FORMAT_RRE CONVERT FROM SIGNED PACKED (64 to long DFP) 1510 op_CDSY uint32 = 0xEB31 // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (32) 1511 op_CDTR uint32 = 0xB3E4 // FORMAT_RRE COMPARE (long DFP) 1512 op_CDUTR uint32 = 0xB3F2 // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP) 1513 op_CDZT uint32 = 0xEDAA // FORMAT_RSL CONVERT FROM ZONED (to long DFP) 1514 op_CE uint32 = 0x7900 // FORMAT_RX1 COMPARE (short HFP) 1515 op_CEB uint32 = 0xED09 // FORMAT_RXE COMPARE (short BFP) 1516 op_CEBR uint32 = 0xB309 // FORMAT_RRE COMPARE (short BFP) 1517 op_CEDTR uint32 = 0xB3F4 // FORMAT_RRE COMPARE BIASED EXPONENT (long DFP) 1518 op_CEFBR uint32 = 0xB394 // FORMAT_RRE CONVERT FROM FIXED (32 to short BFP) 1519 op_CEFBRA uint32 = 0xB394 // FORMAT_RRF5 CONVERT FROM FIXED (32 to short BFP) 1520 op_CEFR uint32 = 0xB3B4 // FORMAT_RRE CONVERT FROM FIXED (32 to short HFP) 1521 op_CEGBR uint32 = 0xB3A4 // FORMAT_RRE CONVERT FROM FIXED (64 to short BFP) 1522 op_CEGBRA uint32 = 0xB3A4 // FORMAT_RRF5 CONVERT FROM FIXED (64 to short BFP) 1523 op_CEGR uint32 = 0xB3C4 // FORMAT_RRE CONVERT FROM FIXED (64 to short HFP) 1524 op_CELFBR uint32 = 0xB390 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to short BFP) 1525 op_CELGBR uint32 = 0xB3A0 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to short BFP) 1526 op_CER uint32 = 0x3900 // FORMAT_RR COMPARE (short HFP) 1527 op_CEXTR uint32 = 0xB3FC // FORMAT_RRE COMPARE BIASED EXPONENT (extended DFP) 1528 op_CFC uint32 = 0xB21A // FORMAT_S COMPARE AND FORM CODEWORD 1529 op_CFDBR uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1530 op_CFDBRA uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1531 op_CFDR uint32 = 0xB3B9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 32) 1532 op_CFDTR uint32 = 0xB941 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 32) 1533 op_CFEBR uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1534 op_CFEBRA uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1535 op_CFER uint32 = 0xB3B8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 32) 1536 op_CFI uint32 = 0xC20D // FORMAT_RIL1 COMPARE IMMEDIATE (32) 1537 op_CFXBR uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1538 op_CFXBRA uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1539 op_CFXR uint32 = 0xB3BA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 32) 1540 op_CFXTR uint32 = 0xB949 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 32) 1541 op_CG uint32 = 0xE320 // FORMAT_RXY1 COMPARE (64) 1542 op_CGDBR uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1543 op_CGDBRA uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1544 op_CGDR uint32 = 0xB3C9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 64) 1545 op_CGDTR uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1546 op_CGDTRA uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1547 op_CGEBR uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1548 op_CGEBRA uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1549 op_CGER uint32 = 0xB3C8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 64) 1550 op_CGF uint32 = 0xE330 // FORMAT_RXY1 COMPARE (64<-32) 1551 op_CGFI uint32 = 0xC20C // FORMAT_RIL1 COMPARE IMMEDIATE (64<-32) 1552 op_CGFR uint32 = 0xB930 // FORMAT_RRE COMPARE (64<-32) 1553 op_CGFRL uint32 = 0xC60C // FORMAT_RIL2 COMPARE RELATIVE LONG (64<-32) 1554 op_CGH uint32 = 0xE334 // FORMAT_RXY1 COMPARE HALFWORD (64<-16) 1555 op_CGHI uint32 = 0xA70F // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (64<-16) 1556 op_CGHRL uint32 = 0xC604 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (64<-16) 1557 op_CGHSI uint32 = 0xE558 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (64<-16) 1558 op_CGIB uint32 = 0xECFC // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (64<-8) 1559 op_CGIJ uint32 = 0xEC7C // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8) 1560 op_CGIT uint32 = 0xEC70 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (64<-16) 1561 op_CGR uint32 = 0xB920 // FORMAT_RRE COMPARE (64) 1562 op_CGRB uint32 = 0xECE4 // FORMAT_RRS COMPARE AND BRANCH (64) 1563 op_CGRJ uint32 = 0xEC64 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (64) 1564 op_CGRL uint32 = 0xC608 // FORMAT_RIL2 COMPARE RELATIVE LONG (64) 1565 op_CGRT uint32 = 0xB960 // FORMAT_RRF3 COMPARE AND TRAP (64) 1566 op_CGXBR uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1567 op_CGXBRA uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1568 op_CGXR uint32 = 0xB3CA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 64) 1569 op_CGXTR uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1570 op_CGXTRA uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1571 op_CH uint32 = 0x4900 // FORMAT_RX1 COMPARE HALFWORD (32<-16) 1572 op_CHF uint32 = 0xE3CD // FORMAT_RXY1 COMPARE HIGH (32) 1573 op_CHHR uint32 = 0xB9CD // FORMAT_RRE COMPARE HIGH (32) 1574 op_CHHSI uint32 = 0xE554 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (16) 1575 op_CHI uint32 = 0xA70E // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (32<-16) 1576 op_CHLR uint32 = 0xB9DD // FORMAT_RRE COMPARE HIGH (32) 1577 op_CHRL uint32 = 0xC605 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (32<-16) 1578 op_CHSI uint32 = 0xE55C // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (32<-16) 1579 op_CHY uint32 = 0xE379 // FORMAT_RXY1 COMPARE HALFWORD (32<-16) 1580 op_CIB uint32 = 0xECFE // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (32<-8) 1581 op_CIH uint32 = 0xCC0D // FORMAT_RIL1 COMPARE IMMEDIATE HIGH (32) 1582 op_CIJ uint32 = 0xEC7E // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8) 1583 op_CIT uint32 = 0xEC72 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (32<-16) 1584 op_CKSM uint32 = 0xB241 // FORMAT_RRE CHECKSUM 1585 op_CL uint32 = 0x5500 // FORMAT_RX1 COMPARE LOGICAL (32) 1586 op_CLC uint32 = 0xD500 // FORMAT_SS1 COMPARE LOGICAL (character) 1587 op_CLCL uint32 = 0x0F00 // FORMAT_RR COMPARE LOGICAL LONG 1588 op_CLCLE uint32 = 0xA900 // FORMAT_RS1 COMPARE LOGICAL LONG EXTENDED 1589 op_CLCLU uint32 = 0xEB8F // FORMAT_RSY1 COMPARE LOGICAL LONG UNICODE 1590 op_CLFDBR uint32 = 0xB39D // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 32) 1591 op_CLFDTR uint32 = 0xB943 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 32) 1592 op_CLFEBR uint32 = 0xB39C // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 32) 1593 op_CLFHSI uint32 = 0xE55D // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (32<-16) 1594 op_CLFI uint32 = 0xC20F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (32) 1595 op_CLFIT uint32 = 0xEC73 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16) 1596 op_CLFXBR uint32 = 0xB39E // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 32) 1597 op_CLFXTR uint32 = 0xB94B // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 32) 1598 op_CLG uint32 = 0xE321 // FORMAT_RXY1 COMPARE LOGICAL (64) 1599 op_CLGDBR uint32 = 0xB3AD // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 64) 1600 op_CLGDTR uint32 = 0xB942 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 64) 1601 op_CLGEBR uint32 = 0xB3AC // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 64) 1602 op_CLGF uint32 = 0xE331 // FORMAT_RXY1 COMPARE LOGICAL (64<-32) 1603 op_CLGFI uint32 = 0xC20E // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (64<-32) 1604 op_CLGFR uint32 = 0xB931 // FORMAT_RRE COMPARE LOGICAL (64<-32) 1605 op_CLGFRL uint32 = 0xC60E // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-32) 1606 op_CLGHRL uint32 = 0xC606 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-16) 1607 op_CLGHSI uint32 = 0xE559 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (64<-16) 1608 op_CLGIB uint32 = 0xECFD // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8) 1609 op_CLGIJ uint32 = 0xEC7D // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (64<-8) 1610 op_CLGIT uint32 = 0xEC71 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16) 1611 op_CLGR uint32 = 0xB921 // FORMAT_RRE COMPARE LOGICAL (64) 1612 op_CLGRB uint32 = 0xECE5 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (64) 1613 op_CLGRJ uint32 = 0xEC65 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (64) 1614 op_CLGRL uint32 = 0xC60A // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64) 1615 op_CLGRT uint32 = 0xB961 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (64) 1616 op_CLGT uint32 = 0xEB2B // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (64) 1617 op_CLGXBR uint32 = 0xB3AE // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 64) 1618 op_CLGXTR uint32 = 0xB94A // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 64) 1619 op_CLHF uint32 = 0xE3CF // FORMAT_RXY1 COMPARE LOGICAL HIGH (32) 1620 op_CLHHR uint32 = 0xB9CF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1621 op_CLHHSI uint32 = 0xE555 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (16) 1622 op_CLHLR uint32 = 0xB9DF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1623 op_CLHRL uint32 = 0xC607 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32<-16) 1624 op_CLI uint32 = 0x9500 // FORMAT_SI COMPARE LOGICAL (immediate) 1625 op_CLIB uint32 = 0xECFF // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8) 1626 op_CLIH uint32 = 0xCC0F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE HIGH (32) 1627 op_CLIJ uint32 = 0xEC7F // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (32<-8) 1628 op_CLIY uint32 = 0xEB55 // FORMAT_SIY COMPARE LOGICAL (immediate) 1629 op_CLM uint32 = 0xBD00 // FORMAT_RS2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1630 op_CLMH uint32 = 0xEB20 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (high) 1631 op_CLMY uint32 = 0xEB21 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1632 op_CLR uint32 = 0x1500 // FORMAT_RR COMPARE LOGICAL (32) 1633 op_CLRB uint32 = 0xECF7 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (32) 1634 op_CLRJ uint32 = 0xEC77 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (32) 1635 op_CLRL uint32 = 0xC60F // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32) 1636 op_CLRT uint32 = 0xB973 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (32) 1637 op_CLST uint32 = 0xB25D // FORMAT_RRE COMPARE LOGICAL STRING 1638 op_CLT uint32 = 0xEB23 // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (32) 1639 op_CLY uint32 = 0xE355 // FORMAT_RXY1 COMPARE LOGICAL (32) 1640 op_CMPSC uint32 = 0xB263 // FORMAT_RRE COMPRESSION CALL 1641 op_CP uint32 = 0xF900 // FORMAT_SS2 COMPARE DECIMAL 1642 op_CPSDR uint32 = 0xB372 // FORMAT_RRF2 COPY SIGN (long) 1643 op_CPYA uint32 = 0xB24D // FORMAT_RRE COPY ACCESS 1644 op_CR uint32 = 0x1900 // FORMAT_RR COMPARE (32) 1645 op_CRB uint32 = 0xECF6 // FORMAT_RRS COMPARE AND BRANCH (32) 1646 op_CRDTE uint32 = 0xB98F // FORMAT_RRF2 COMPARE AND REPLACE DAT TABLE ENTRY 1647 op_CRJ uint32 = 0xEC76 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (32) 1648 op_CRL uint32 = 0xC60D // FORMAT_RIL2 COMPARE RELATIVE LONG (32) 1649 op_CRT uint32 = 0xB972 // FORMAT_RRF3 COMPARE AND TRAP (32) 1650 op_CS uint32 = 0xBA00 // FORMAT_RS1 COMPARE AND SWAP (32) 1651 op_CSCH uint32 = 0xB230 // FORMAT_S CLEAR SUBCHANNEL 1652 op_CSDTR uint32 = 0xB3E3 // FORMAT_RRF4 CONVERT TO SIGNED PACKED (long DFP to 64) 1653 op_CSG uint32 = 0xEB30 // FORMAT_RSY1 COMPARE AND SWAP (64) 1654 op_CSP uint32 = 0xB250 // FORMAT_RRE COMPARE AND SWAP AND PURGE 1655 op_CSPG uint32 = 0xB98A // FORMAT_RRE COMPARE AND SWAP AND PURGE 1656 op_CSST uint32 = 0xC802 // FORMAT_SSF COMPARE AND SWAP AND STORE 1657 op_CSXTR uint32 = 0xB3EB // FORMAT_RRF4 CONVERT TO SIGNED PACKED (extended DFP to 128) 1658 op_CSY uint32 = 0xEB14 // FORMAT_RSY1 COMPARE AND SWAP (32) 1659 op_CU12 uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-16 1660 op_CU14 uint32 = 0xB9B0 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-32 1661 op_CU21 uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-8 1662 op_CU24 uint32 = 0xB9B1 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-32 1663 op_CU41 uint32 = 0xB9B2 // FORMAT_RRE CONVERT UTF-32 TO UTF-8 1664 op_CU42 uint32 = 0xB9B3 // FORMAT_RRE CONVERT UTF-32 TO UTF-16 1665 op_CUDTR uint32 = 0xB3E2 // FORMAT_RRE CONVERT TO UNSIGNED PACKED (long DFP to 64) 1666 op_CUSE uint32 = 0xB257 // FORMAT_RRE COMPARE UNTIL SUBSTRING EQUAL 1667 op_CUTFU uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UNICODE 1668 op_CUUTF uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UNICODE TO UTF-8 1669 op_CUXTR uint32 = 0xB3EA // FORMAT_RRE CONVERT TO UNSIGNED PACKED (extended DFP to 128) 1670 op_CVB uint32 = 0x4F00 // FORMAT_RX1 CONVERT TO BINARY (32) 1671 op_CVBG uint32 = 0xE30E // FORMAT_RXY1 CONVERT TO BINARY (64) 1672 op_CVBY uint32 = 0xE306 // FORMAT_RXY1 CONVERT TO BINARY (32) 1673 op_CVD uint32 = 0x4E00 // FORMAT_RX1 CONVERT TO DECIMAL (32) 1674 op_CVDG uint32 = 0xE32E // FORMAT_RXY1 CONVERT TO DECIMAL (64) 1675 op_CVDY uint32 = 0xE326 // FORMAT_RXY1 CONVERT TO DECIMAL (32) 1676 op_CXBR uint32 = 0xB349 // FORMAT_RRE COMPARE (extended BFP) 1677 op_CXFBR uint32 = 0xB396 // FORMAT_RRE CONVERT FROM FIXED (32 to extended BFP) 1678 op_CXFBRA uint32 = 0xB396 // FORMAT_RRF5 CONVERT FROM FIXED (32 to extended BFP) 1679 op_CXFR uint32 = 0xB3B6 // FORMAT_RRE CONVERT FROM FIXED (32 to extended HFP) 1680 op_CXFTR uint32 = 0xB959 // FORMAT_RRE CONVERT FROM FIXED (32 to extended DFP) 1681 op_CXGBR uint32 = 0xB3A6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended BFP) 1682 op_CXGBRA uint32 = 0xB3A6 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended BFP) 1683 op_CXGR uint32 = 0xB3C6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended HFP) 1684 op_CXGTR uint32 = 0xB3F9 // FORMAT_RRE CONVERT FROM FIXED (64 to extended DFP) 1685 op_CXGTRA uint32 = 0xB3F9 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended DFP) 1686 op_CXLFBR uint32 = 0xB392 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended BFP) 1687 op_CXLFTR uint32 = 0xB95B // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended DFP) 1688 op_CXLGBR uint32 = 0xB3A2 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended BFP) 1689 op_CXLGTR uint32 = 0xB95A // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended DFP) 1690 op_CXR uint32 = 0xB369 // FORMAT_RRE COMPARE (extended HFP) 1691 op_CXSTR uint32 = 0xB3FB // FORMAT_RRE CONVERT FROM SIGNED PACKED (128 to extended DFP) 1692 op_CXTR uint32 = 0xB3EC // FORMAT_RRE COMPARE (extended DFP) 1693 op_CXUTR uint32 = 0xB3FA // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) 1694 op_CXZT uint32 = 0xEDAB // FORMAT_RSL CONVERT FROM ZONED (to extended DFP) 1695 op_CY uint32 = 0xE359 // FORMAT_RXY1 COMPARE (32) 1696 op_CZDT uint32 = 0xEDA8 // FORMAT_RSL CONVERT TO ZONED (from long DFP) 1697 op_CZXT uint32 = 0xEDA9 // FORMAT_RSL CONVERT TO ZONED (from extended DFP) 1698 op_D uint32 = 0x5D00 // FORMAT_RX1 DIVIDE (32<-64) 1699 op_DD uint32 = 0x6D00 // FORMAT_RX1 DIVIDE (long HFP) 1700 op_DDB uint32 = 0xED1D // FORMAT_RXE DIVIDE (long BFP) 1701 op_DDBR uint32 = 0xB31D // FORMAT_RRE DIVIDE (long BFP) 1702 op_DDR uint32 = 0x2D00 // FORMAT_RR DIVIDE (long HFP) 1703 op_DDTR uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1704 op_DDTRA uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1705 op_DE uint32 = 0x7D00 // FORMAT_RX1 DIVIDE (short HFP) 1706 op_DEB uint32 = 0xED0D // FORMAT_RXE DIVIDE (short BFP) 1707 op_DEBR uint32 = 0xB30D // FORMAT_RRE DIVIDE (short BFP) 1708 op_DER uint32 = 0x3D00 // FORMAT_RR DIVIDE (short HFP) 1709 op_DIDBR uint32 = 0xB35B // FORMAT_RRF2 DIVIDE TO INTEGER (long BFP) 1710 op_DIEBR uint32 = 0xB353 // FORMAT_RRF2 DIVIDE TO INTEGER (short BFP) 1711 op_DL uint32 = 0xE397 // FORMAT_RXY1 DIVIDE LOGICAL (32<-64) 1712 op_DLG uint32 = 0xE387 // FORMAT_RXY1 DIVIDE LOGICAL (64<-128) 1713 op_DLGR uint32 = 0xB987 // FORMAT_RRE DIVIDE LOGICAL (64<-128) 1714 op_DLR uint32 = 0xB997 // FORMAT_RRE DIVIDE LOGICAL (32<-64) 1715 op_DP uint32 = 0xFD00 // FORMAT_SS2 DIVIDE DECIMAL 1716 op_DR uint32 = 0x1D00 // FORMAT_RR DIVIDE (32<-64) 1717 op_DSG uint32 = 0xE30D // FORMAT_RXY1 DIVIDE SINGLE (64) 1718 op_DSGF uint32 = 0xE31D // FORMAT_RXY1 DIVIDE SINGLE (64<-32) 1719 op_DSGFR uint32 = 0xB91D // FORMAT_RRE DIVIDE SINGLE (64<-32) 1720 op_DSGR uint32 = 0xB90D // FORMAT_RRE DIVIDE SINGLE (64) 1721 op_DXBR uint32 = 0xB34D // FORMAT_RRE DIVIDE (extended BFP) 1722 op_DXR uint32 = 0xB22D // FORMAT_RRE DIVIDE (extended HFP) 1723 op_DXTR uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1724 op_DXTRA uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1725 op_EAR uint32 = 0xB24F // FORMAT_RRE EXTRACT ACCESS 1726 op_ECAG uint32 = 0xEB4C // FORMAT_RSY1 EXTRACT CACHE ATTRIBUTE 1727 op_ECTG uint32 = 0xC801 // FORMAT_SSF EXTRACT CPU TIME 1728 op_ED uint32 = 0xDE00 // FORMAT_SS1 EDIT 1729 op_EDMK uint32 = 0xDF00 // FORMAT_SS1 EDIT AND MARK 1730 op_EEDTR uint32 = 0xB3E5 // FORMAT_RRE EXTRACT BIASED EXPONENT (long DFP to 64) 1731 op_EEXTR uint32 = 0xB3ED // FORMAT_RRE EXTRACT BIASED EXPONENT (extended DFP to 64) 1732 op_EFPC uint32 = 0xB38C // FORMAT_RRE EXTRACT FPC 1733 op_EPAIR uint32 = 0xB99A // FORMAT_RRE EXTRACT PRIMARY ASN AND INSTANCE 1734 op_EPAR uint32 = 0xB226 // FORMAT_RRE EXTRACT PRIMARY ASN 1735 op_EPSW uint32 = 0xB98D // FORMAT_RRE EXTRACT PSW 1736 op_EREG uint32 = 0xB249 // FORMAT_RRE EXTRACT STACKED REGISTERS (32) 1737 op_EREGG uint32 = 0xB90E // FORMAT_RRE EXTRACT STACKED REGISTERS (64) 1738 op_ESAIR uint32 = 0xB99B // FORMAT_RRE EXTRACT SECONDARY ASN AND INSTANCE 1739 op_ESAR uint32 = 0xB227 // FORMAT_RRE EXTRACT SECONDARY ASN 1740 op_ESDTR uint32 = 0xB3E7 // FORMAT_RRE EXTRACT SIGNIFICANCE (long DFP) 1741 op_ESEA uint32 = 0xB99D // FORMAT_RRE EXTRACT AND SET EXTENDED AUTHORITY 1742 op_ESTA uint32 = 0xB24A // FORMAT_RRE EXTRACT STACKED STATE 1743 op_ESXTR uint32 = 0xB3EF // FORMAT_RRE EXTRACT SIGNIFICANCE (extended DFP) 1744 op_ETND uint32 = 0xB2EC // FORMAT_RRE EXTRACT TRANSACTION NESTING DEPTH 1745 op_EX uint32 = 0x4400 // FORMAT_RX1 EXECUTE 1746 op_EXRL uint32 = 0xC600 // FORMAT_RIL2 EXECUTE RELATIVE LONG 1747 op_FIDBR uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1748 op_FIDBRA uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1749 op_FIDR uint32 = 0xB37F // FORMAT_RRE LOAD FP INTEGER (long HFP) 1750 op_FIDTR uint32 = 0xB3D7 // FORMAT_RRF5 LOAD FP INTEGER (long DFP) 1751 op_FIEBR uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1752 op_FIEBRA uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1753 op_FIER uint32 = 0xB377 // FORMAT_RRE LOAD FP INTEGER (short HFP) 1754 op_FIXBR uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1755 op_FIXBRA uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1756 op_FIXR uint32 = 0xB367 // FORMAT_RRE LOAD FP INTEGER (extended HFP) 1757 op_FIXTR uint32 = 0xB3DF // FORMAT_RRF5 LOAD FP INTEGER (extended DFP) 1758 op_FLOGR uint32 = 0xB983 // FORMAT_RRE FIND LEFTMOST ONE 1759 op_HDR uint32 = 0x2400 // FORMAT_RR HALVE (long HFP) 1760 op_HER uint32 = 0x3400 // FORMAT_RR HALVE (short HFP) 1761 op_HSCH uint32 = 0xB231 // FORMAT_S HALT SUBCHANNEL 1762 op_IAC uint32 = 0xB224 // FORMAT_RRE INSERT ADDRESS SPACE CONTROL 1763 op_IC uint32 = 0x4300 // FORMAT_RX1 INSERT CHARACTER 1764 op_ICM uint32 = 0xBF00 // FORMAT_RS2 INSERT CHARACTERS UNDER MASK (low) 1765 op_ICMH uint32 = 0xEB80 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (high) 1766 op_ICMY uint32 = 0xEB81 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (low) 1767 op_ICY uint32 = 0xE373 // FORMAT_RXY1 INSERT CHARACTER 1768 op_IDTE uint32 = 0xB98E // FORMAT_RRF2 INVALIDATE DAT TABLE ENTRY 1769 op_IEDTR uint32 = 0xB3F6 // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to long DFP) 1770 op_IEXTR uint32 = 0xB3FE // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to extended DFP) 1771 op_IIHF uint32 = 0xC008 // FORMAT_RIL1 INSERT IMMEDIATE (high) 1772 op_IIHH uint32 = 0xA500 // FORMAT_RI1 INSERT IMMEDIATE (high high) 1773 op_IIHL uint32 = 0xA501 // FORMAT_RI1 INSERT IMMEDIATE (high low) 1774 op_IILF uint32 = 0xC009 // FORMAT_RIL1 INSERT IMMEDIATE (low) 1775 op_IILH uint32 = 0xA502 // FORMAT_RI1 INSERT IMMEDIATE (low high) 1776 op_IILL uint32 = 0xA503 // FORMAT_RI1 INSERT IMMEDIATE (low low) 1777 op_IPK uint32 = 0xB20B // FORMAT_S INSERT PSW KEY 1778 op_IPM uint32 = 0xB222 // FORMAT_RRE INSERT PROGRAM MASK 1779 op_IPTE uint32 = 0xB221 // FORMAT_RRF1 INVALIDATE PAGE TABLE ENTRY 1780 op_ISKE uint32 = 0xB229 // FORMAT_RRE INSERT STORAGE KEY EXTENDED 1781 op_IVSK uint32 = 0xB223 // FORMAT_RRE INSERT VIRTUAL STORAGE KEY 1782 op_KDB uint32 = 0xED18 // FORMAT_RXE COMPARE AND SIGNAL (long BFP) 1783 op_KDBR uint32 = 0xB318 // FORMAT_RRE COMPARE AND SIGNAL (long BFP) 1784 op_KDTR uint32 = 0xB3E0 // FORMAT_RRE COMPARE AND SIGNAL (long DFP) 1785 op_KEB uint32 = 0xED08 // FORMAT_RXE COMPARE AND SIGNAL (short BFP) 1786 op_KEBR uint32 = 0xB308 // FORMAT_RRE COMPARE AND SIGNAL (short BFP) 1787 op_KIMD uint32 = 0xB93E // FORMAT_RRE COMPUTE INTERMEDIATE MESSAGE DIGEST 1788 op_KLMD uint32 = 0xB93F // FORMAT_RRE COMPUTE LAST MESSAGE DIGEST 1789 op_KM uint32 = 0xB92E // FORMAT_RRE CIPHER MESSAGE 1790 op_KMAC uint32 = 0xB91E // FORMAT_RRE COMPUTE MESSAGE AUTHENTICATION CODE 1791 op_KMC uint32 = 0xB92F // FORMAT_RRE CIPHER MESSAGE WITH CHAINING 1792 op_KMCTR uint32 = 0xB92D // FORMAT_RRF2 CIPHER MESSAGE WITH COUNTER 1793 op_KMF uint32 = 0xB92A // FORMAT_RRE CIPHER MESSAGE WITH CFB 1794 op_KMO uint32 = 0xB92B // FORMAT_RRE CIPHER MESSAGE WITH OFB 1795 op_KXBR uint32 = 0xB348 // FORMAT_RRE COMPARE AND SIGNAL (extended BFP) 1796 op_KXTR uint32 = 0xB3E8 // FORMAT_RRE COMPARE AND SIGNAL (extended DFP) 1797 op_L uint32 = 0x5800 // FORMAT_RX1 LOAD (32) 1798 op_LA uint32 = 0x4100 // FORMAT_RX1 LOAD ADDRESS 1799 op_LAA uint32 = 0xEBF8 // FORMAT_RSY1 LOAD AND ADD (32) 1800 op_LAAG uint32 = 0xEBE8 // FORMAT_RSY1 LOAD AND ADD (64) 1801 op_LAAL uint32 = 0xEBFA // FORMAT_RSY1 LOAD AND ADD LOGICAL (32) 1802 op_LAALG uint32 = 0xEBEA // FORMAT_RSY1 LOAD AND ADD LOGICAL (64) 1803 op_LAE uint32 = 0x5100 // FORMAT_RX1 LOAD ADDRESS EXTENDED 1804 op_LAEY uint32 = 0xE375 // FORMAT_RXY1 LOAD ADDRESS EXTENDED 1805 op_LAM uint32 = 0x9A00 // FORMAT_RS1 LOAD ACCESS MULTIPLE 1806 op_LAMY uint32 = 0xEB9A // FORMAT_RSY1 LOAD ACCESS MULTIPLE 1807 op_LAN uint32 = 0xEBF4 // FORMAT_RSY1 LOAD AND AND (32) 1808 op_LANG uint32 = 0xEBE4 // FORMAT_RSY1 LOAD AND AND (64) 1809 op_LAO uint32 = 0xEBF6 // FORMAT_RSY1 LOAD AND OR (32) 1810 op_LAOG uint32 = 0xEBE6 // FORMAT_RSY1 LOAD AND OR (64) 1811 op_LARL uint32 = 0xC000 // FORMAT_RIL2 LOAD ADDRESS RELATIVE LONG 1812 op_LASP uint32 = 0xE500 // FORMAT_SSE LOAD ADDRESS SPACE PARAMETERS 1813 op_LAT uint32 = 0xE39F // FORMAT_RXY1 LOAD AND TRAP (32L<-32) 1814 op_LAX uint32 = 0xEBF7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (32) 1815 op_LAXG uint32 = 0xEBE7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (64) 1816 op_LAY uint32 = 0xE371 // FORMAT_RXY1 LOAD ADDRESS 1817 op_LB uint32 = 0xE376 // FORMAT_RXY1 LOAD BYTE (32) 1818 op_LBH uint32 = 0xE3C0 // FORMAT_RXY1 LOAD BYTE HIGH (32<-8) 1819 op_LBR uint32 = 0xB926 // FORMAT_RRE LOAD BYTE (32) 1820 op_LCDBR uint32 = 0xB313 // FORMAT_RRE LOAD COMPLEMENT (long BFP) 1821 op_LCDFR uint32 = 0xB373 // FORMAT_RRE LOAD COMPLEMENT (long) 1822 op_LCDR uint32 = 0x2300 // FORMAT_RR LOAD COMPLEMENT (long HFP) 1823 op_LCEBR uint32 = 0xB303 // FORMAT_RRE LOAD COMPLEMENT (short BFP) 1824 op_LCER uint32 = 0x3300 // FORMAT_RR LOAD COMPLEMENT (short HFP) 1825 op_LCGFR uint32 = 0xB913 // FORMAT_RRE LOAD COMPLEMENT (64<-32) 1826 op_LCGR uint32 = 0xB903 // FORMAT_RRE LOAD COMPLEMENT (64) 1827 op_LCR uint32 = 0x1300 // FORMAT_RR LOAD COMPLEMENT (32) 1828 op_LCTL uint32 = 0xB700 // FORMAT_RS1 LOAD CONTROL (32) 1829 op_LCTLG uint32 = 0xEB2F // FORMAT_RSY1 LOAD CONTROL (64) 1830 op_LCXBR uint32 = 0xB343 // FORMAT_RRE LOAD COMPLEMENT (extended BFP) 1831 op_LCXR uint32 = 0xB363 // FORMAT_RRE LOAD COMPLEMENT (extended HFP) 1832 op_LD uint32 = 0x6800 // FORMAT_RX1 LOAD (long) 1833 op_LDE uint32 = 0xED24 // FORMAT_RXE LOAD LENGTHENED (short to long HFP) 1834 op_LDEB uint32 = 0xED04 // FORMAT_RXE LOAD LENGTHENED (short to long BFP) 1835 op_LDEBR uint32 = 0xB304 // FORMAT_RRE LOAD LENGTHENED (short to long BFP) 1836 op_LDER uint32 = 0xB324 // FORMAT_RRE LOAD LENGTHENED (short to long HFP) 1837 op_LDETR uint32 = 0xB3D4 // FORMAT_RRF4 LOAD LENGTHENED (short to long DFP) 1838 op_LDGR uint32 = 0xB3C1 // FORMAT_RRE LOAD FPR FROM GR (64 to long) 1839 op_LDR uint32 = 0x2800 // FORMAT_RR LOAD (long) 1840 op_LDXBR uint32 = 0xB345 // FORMAT_RRE LOAD ROUNDED (extended to long BFP) 1841 op_LDXBRA uint32 = 0xB345 // FORMAT_RRF5 LOAD ROUNDED (extended to long BFP) 1842 op_LDXR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1843 op_LDXTR uint32 = 0xB3DD // FORMAT_RRF5 LOAD ROUNDED (extended to long DFP) 1844 op_LDY uint32 = 0xED65 // FORMAT_RXY1 LOAD (long) 1845 op_LE uint32 = 0x7800 // FORMAT_RX1 LOAD (short) 1846 op_LEDBR uint32 = 0xB344 // FORMAT_RRE LOAD ROUNDED (long to short BFP) 1847 op_LEDBRA uint32 = 0xB344 // FORMAT_RRF5 LOAD ROUNDED (long to short BFP) 1848 op_LEDR uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1849 op_LEDTR uint32 = 0xB3D5 // FORMAT_RRF5 LOAD ROUNDED (long to short DFP) 1850 op_LER uint32 = 0x3800 // FORMAT_RR LOAD (short) 1851 op_LEXBR uint32 = 0xB346 // FORMAT_RRE LOAD ROUNDED (extended to short BFP) 1852 op_LEXBRA uint32 = 0xB346 // FORMAT_RRF5 LOAD ROUNDED (extended to short BFP) 1853 op_LEXR uint32 = 0xB366 // FORMAT_RRE LOAD ROUNDED (extended to short HFP) 1854 op_LEY uint32 = 0xED64 // FORMAT_RXY1 LOAD (short) 1855 op_LFAS uint32 = 0xB2BD // FORMAT_S LOAD FPC AND SIGNAL 1856 op_LFH uint32 = 0xE3CA // FORMAT_RXY1 LOAD HIGH (32) 1857 op_LFHAT uint32 = 0xE3C8 // FORMAT_RXY1 LOAD HIGH AND TRAP (32H<-32) 1858 op_LFPC uint32 = 0xB29D // FORMAT_S LOAD FPC 1859 op_LG uint32 = 0xE304 // FORMAT_RXY1 LOAD (64) 1860 op_LGAT uint32 = 0xE385 // FORMAT_RXY1 LOAD AND TRAP (64) 1861 op_LGB uint32 = 0xE377 // FORMAT_RXY1 LOAD BYTE (64) 1862 op_LGBR uint32 = 0xB906 // FORMAT_RRE LOAD BYTE (64) 1863 op_LGDR uint32 = 0xB3CD // FORMAT_RRE LOAD GR FROM FPR (long to 64) 1864 op_LGF uint32 = 0xE314 // FORMAT_RXY1 LOAD (64<-32) 1865 op_LGFI uint32 = 0xC001 // FORMAT_RIL1 LOAD IMMEDIATE (64<-32) 1866 op_LGFR uint32 = 0xB914 // FORMAT_RRE LOAD (64<-32) 1867 op_LGFRL uint32 = 0xC40C // FORMAT_RIL2 LOAD RELATIVE LONG (64<-32) 1868 op_LGH uint32 = 0xE315 // FORMAT_RXY1 LOAD HALFWORD (64) 1869 op_LGHI uint32 = 0xA709 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (64) 1870 op_LGHR uint32 = 0xB907 // FORMAT_RRE LOAD HALFWORD (64) 1871 op_LGHRL uint32 = 0xC404 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (64<-16) 1872 op_LGR uint32 = 0xB904 // FORMAT_RRE LOAD (64) 1873 op_LGRL uint32 = 0xC408 // FORMAT_RIL2 LOAD RELATIVE LONG (64) 1874 op_LH uint32 = 0x4800 // FORMAT_RX1 LOAD HALFWORD (32) 1875 op_LHH uint32 = 0xE3C4 // FORMAT_RXY1 LOAD HALFWORD HIGH (32<-16) 1876 op_LHI uint32 = 0xA708 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (32) 1877 op_LHR uint32 = 0xB927 // FORMAT_RRE LOAD HALFWORD (32) 1878 op_LHRL uint32 = 0xC405 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (32<-16) 1879 op_LHY uint32 = 0xE378 // FORMAT_RXY1 LOAD HALFWORD (32) 1880 op_LLC uint32 = 0xE394 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (32) 1881 op_LLCH uint32 = 0xE3C2 // FORMAT_RXY1 LOAD LOGICAL CHARACTER HIGH (32<-8) 1882 op_LLCR uint32 = 0xB994 // FORMAT_RRE LOAD LOGICAL CHARACTER (32) 1883 op_LLGC uint32 = 0xE390 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (64) 1884 op_LLGCR uint32 = 0xB984 // FORMAT_RRE LOAD LOGICAL CHARACTER (64) 1885 op_LLGF uint32 = 0xE316 // FORMAT_RXY1 LOAD LOGICAL (64<-32) 1886 op_LLGFAT uint32 = 0xE39D // FORMAT_RXY1 LOAD LOGICAL AND TRAP (64<-32) 1887 op_LLGFR uint32 = 0xB916 // FORMAT_RRE LOAD LOGICAL (64<-32) 1888 op_LLGFRL uint32 = 0xC40E // FORMAT_RIL2 LOAD LOGICAL RELATIVE LONG (64<-32) 1889 op_LLGH uint32 = 0xE391 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (64) 1890 op_LLGHR uint32 = 0xB985 // FORMAT_RRE LOAD LOGICAL HALFWORD (64) 1891 op_LLGHRL uint32 = 0xC406 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16) 1892 op_LLGT uint32 = 0xE317 // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS 1893 op_LLGTAT uint32 = 0xE39C // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31) 1894 op_LLGTR uint32 = 0xB917 // FORMAT_RRE LOAD LOGICAL THIRTY ONE BITS 1895 op_LLH uint32 = 0xE395 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (32) 1896 op_LLHH uint32 = 0xE3C6 // FORMAT_RXY1 LOAD LOGICAL HALFWORD HIGH (32<-16) 1897 op_LLHR uint32 = 0xB995 // FORMAT_RRE LOAD LOGICAL HALFWORD (32) 1898 op_LLHRL uint32 = 0xC402 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16) 1899 op_LLIHF uint32 = 0xC00E // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (high) 1900 op_LLIHH uint32 = 0xA50C // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high high) 1901 op_LLIHL uint32 = 0xA50D // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high low) 1902 op_LLILF uint32 = 0xC00F // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (low) 1903 op_LLILH uint32 = 0xA50E // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low high) 1904 op_LLILL uint32 = 0xA50F // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low low) 1905 op_LM uint32 = 0x9800 // FORMAT_RS1 LOAD MULTIPLE (32) 1906 op_LMD uint32 = 0xEF00 // FORMAT_SS5 LOAD MULTIPLE DISJOINT 1907 op_LMG uint32 = 0xEB04 // FORMAT_RSY1 LOAD MULTIPLE (64) 1908 op_LMH uint32 = 0xEB96 // FORMAT_RSY1 LOAD MULTIPLE HIGH 1909 op_LMY uint32 = 0xEB98 // FORMAT_RSY1 LOAD MULTIPLE (32) 1910 op_LNDBR uint32 = 0xB311 // FORMAT_RRE LOAD NEGATIVE (long BFP) 1911 op_LNDFR uint32 = 0xB371 // FORMAT_RRE LOAD NEGATIVE (long) 1912 op_LNDR uint32 = 0x2100 // FORMAT_RR LOAD NEGATIVE (long HFP) 1913 op_LNEBR uint32 = 0xB301 // FORMAT_RRE LOAD NEGATIVE (short BFP) 1914 op_LNER uint32 = 0x3100 // FORMAT_RR LOAD NEGATIVE (short HFP) 1915 op_LNGFR uint32 = 0xB911 // FORMAT_RRE LOAD NEGATIVE (64<-32) 1916 op_LNGR uint32 = 0xB901 // FORMAT_RRE LOAD NEGATIVE (64) 1917 op_LNR uint32 = 0x1100 // FORMAT_RR LOAD NEGATIVE (32) 1918 op_LNXBR uint32 = 0xB341 // FORMAT_RRE LOAD NEGATIVE (extended BFP) 1919 op_LNXR uint32 = 0xB361 // FORMAT_RRE LOAD NEGATIVE (extended HFP) 1920 op_LOC uint32 = 0xEBF2 // FORMAT_RSY2 LOAD ON CONDITION (32) 1921 op_LOCG uint32 = 0xEBE2 // FORMAT_RSY2 LOAD ON CONDITION (64) 1922 op_LOCGR uint32 = 0xB9E2 // FORMAT_RRF3 LOAD ON CONDITION (64) 1923 op_LOCR uint32 = 0xB9F2 // FORMAT_RRF3 LOAD ON CONDITION (32) 1924 op_LPD uint32 = 0xC804 // FORMAT_SSF LOAD PAIR DISJOINT (32) 1925 op_LPDBR uint32 = 0xB310 // FORMAT_RRE LOAD POSITIVE (long BFP) 1926 op_LPDFR uint32 = 0xB370 // FORMAT_RRE LOAD POSITIVE (long) 1927 op_LPDG uint32 = 0xC805 // FORMAT_SSF LOAD PAIR DISJOINT (64) 1928 op_LPDR uint32 = 0x2000 // FORMAT_RR LOAD POSITIVE (long HFP) 1929 op_LPEBR uint32 = 0xB300 // FORMAT_RRE LOAD POSITIVE (short BFP) 1930 op_LPER uint32 = 0x3000 // FORMAT_RR LOAD POSITIVE (short HFP) 1931 op_LPGFR uint32 = 0xB910 // FORMAT_RRE LOAD POSITIVE (64<-32) 1932 op_LPGR uint32 = 0xB900 // FORMAT_RRE LOAD POSITIVE (64) 1933 op_LPQ uint32 = 0xE38F // FORMAT_RXY1 LOAD PAIR FROM QUADWORD 1934 op_LPR uint32 = 0x1000 // FORMAT_RR LOAD POSITIVE (32) 1935 op_LPSW uint32 = 0x8200 // FORMAT_S LOAD PSW 1936 op_LPSWE uint32 = 0xB2B2 // FORMAT_S LOAD PSW EXTENDED 1937 op_LPTEA uint32 = 0xB9AA // FORMAT_RRF2 LOAD PAGE TABLE ENTRY ADDRESS 1938 op_LPXBR uint32 = 0xB340 // FORMAT_RRE LOAD POSITIVE (extended BFP) 1939 op_LPXR uint32 = 0xB360 // FORMAT_RRE LOAD POSITIVE (extended HFP) 1940 op_LR uint32 = 0x1800 // FORMAT_RR LOAD (32) 1941 op_LRA uint32 = 0xB100 // FORMAT_RX1 LOAD REAL ADDRESS (32) 1942 op_LRAG uint32 = 0xE303 // FORMAT_RXY1 LOAD REAL ADDRESS (64) 1943 op_LRAY uint32 = 0xE313 // FORMAT_RXY1 LOAD REAL ADDRESS (32) 1944 op_LRDR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1945 op_LRER uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1946 op_LRL uint32 = 0xC40D // FORMAT_RIL2 LOAD RELATIVE LONG (32) 1947 op_LRV uint32 = 0xE31E // FORMAT_RXY1 LOAD REVERSED (32) 1948 op_LRVG uint32 = 0xE30F // FORMAT_RXY1 LOAD REVERSED (64) 1949 op_LRVGR uint32 = 0xB90F // FORMAT_RRE LOAD REVERSED (64) 1950 op_LRVH uint32 = 0xE31F // FORMAT_RXY1 LOAD REVERSED (16) 1951 op_LRVR uint32 = 0xB91F // FORMAT_RRE LOAD REVERSED (32) 1952 op_LT uint32 = 0xE312 // FORMAT_RXY1 LOAD AND TEST (32) 1953 op_LTDBR uint32 = 0xB312 // FORMAT_RRE LOAD AND TEST (long BFP) 1954 op_LTDR uint32 = 0x2200 // FORMAT_RR LOAD AND TEST (long HFP) 1955 op_LTDTR uint32 = 0xB3D6 // FORMAT_RRE LOAD AND TEST (long DFP) 1956 op_LTEBR uint32 = 0xB302 // FORMAT_RRE LOAD AND TEST (short BFP) 1957 op_LTER uint32 = 0x3200 // FORMAT_RR LOAD AND TEST (short HFP) 1958 op_LTG uint32 = 0xE302 // FORMAT_RXY1 LOAD AND TEST (64) 1959 op_LTGF uint32 = 0xE332 // FORMAT_RXY1 LOAD AND TEST (64<-32) 1960 op_LTGFR uint32 = 0xB912 // FORMAT_RRE LOAD AND TEST (64<-32) 1961 op_LTGR uint32 = 0xB902 // FORMAT_RRE LOAD AND TEST (64) 1962 op_LTR uint32 = 0x1200 // FORMAT_RR LOAD AND TEST (32) 1963 op_LTXBR uint32 = 0xB342 // FORMAT_RRE LOAD AND TEST (extended BFP) 1964 op_LTXR uint32 = 0xB362 // FORMAT_RRE LOAD AND TEST (extended HFP) 1965 op_LTXTR uint32 = 0xB3DE // FORMAT_RRE LOAD AND TEST (extended DFP) 1966 op_LURA uint32 = 0xB24B // FORMAT_RRE LOAD USING REAL ADDRESS (32) 1967 op_LURAG uint32 = 0xB905 // FORMAT_RRE LOAD USING REAL ADDRESS (64) 1968 op_LXD uint32 = 0xED25 // FORMAT_RXE LOAD LENGTHENED (long to extended HFP) 1969 op_LXDB uint32 = 0xED05 // FORMAT_RXE LOAD LENGTHENED (long to extended BFP) 1970 op_LXDBR uint32 = 0xB305 // FORMAT_RRE LOAD LENGTHENED (long to extended BFP) 1971 op_LXDR uint32 = 0xB325 // FORMAT_RRE LOAD LENGTHENED (long to extended HFP) 1972 op_LXDTR uint32 = 0xB3DC // FORMAT_RRF4 LOAD LENGTHENED (long to extended DFP) 1973 op_LXE uint32 = 0xED26 // FORMAT_RXE LOAD LENGTHENED (short to extended HFP) 1974 op_LXEB uint32 = 0xED06 // FORMAT_RXE LOAD LENGTHENED (short to extended BFP) 1975 op_LXEBR uint32 = 0xB306 // FORMAT_RRE LOAD LENGTHENED (short to extended BFP) 1976 op_LXER uint32 = 0xB326 // FORMAT_RRE LOAD LENGTHENED (short to extended HFP) 1977 op_LXR uint32 = 0xB365 // FORMAT_RRE LOAD (extended) 1978 op_LY uint32 = 0xE358 // FORMAT_RXY1 LOAD (32) 1979 op_LZDR uint32 = 0xB375 // FORMAT_RRE LOAD ZERO (long) 1980 op_LZER uint32 = 0xB374 // FORMAT_RRE LOAD ZERO (short) 1981 op_LZXR uint32 = 0xB376 // FORMAT_RRE LOAD ZERO (extended) 1982 op_M uint32 = 0x5C00 // FORMAT_RX1 MULTIPLY (64<-32) 1983 op_MAD uint32 = 0xED3E // FORMAT_RXF MULTIPLY AND ADD (long HFP) 1984 op_MADB uint32 = 0xED1E // FORMAT_RXF MULTIPLY AND ADD (long BFP) 1985 op_MADBR uint32 = 0xB31E // FORMAT_RRD MULTIPLY AND ADD (long BFP) 1986 op_MADR uint32 = 0xB33E // FORMAT_RRD MULTIPLY AND ADD (long HFP) 1987 op_MAE uint32 = 0xED2E // FORMAT_RXF MULTIPLY AND ADD (short HFP) 1988 op_MAEB uint32 = 0xED0E // FORMAT_RXF MULTIPLY AND ADD (short BFP) 1989 op_MAEBR uint32 = 0xB30E // FORMAT_RRD MULTIPLY AND ADD (short BFP) 1990 op_MAER uint32 = 0xB32E // FORMAT_RRD MULTIPLY AND ADD (short HFP) 1991 op_MAY uint32 = 0xED3A // FORMAT_RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1992 op_MAYH uint32 = 0xED3C // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1993 op_MAYHR uint32 = 0xB33C // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1994 op_MAYL uint32 = 0xED38 // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1995 op_MAYLR uint32 = 0xB338 // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1996 op_MAYR uint32 = 0xB33A // FORMAT_RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1997 op_MC uint32 = 0xAF00 // FORMAT_SI MONITOR CALL 1998 op_MD uint32 = 0x6C00 // FORMAT_RX1 MULTIPLY (long HFP) 1999 op_MDB uint32 = 0xED1C // FORMAT_RXE MULTIPLY (long BFP) 2000 op_MDBR uint32 = 0xB31C // FORMAT_RRE MULTIPLY (long BFP) 2001 op_MDE uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 2002 op_MDEB uint32 = 0xED0C // FORMAT_RXE MULTIPLY (short to long BFP) 2003 op_MDEBR uint32 = 0xB30C // FORMAT_RRE MULTIPLY (short to long BFP) 2004 op_MDER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 2005 op_MDR uint32 = 0x2C00 // FORMAT_RR MULTIPLY (long HFP) 2006 op_MDTR uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 2007 op_MDTRA uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 2008 op_ME uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 2009 op_MEE uint32 = 0xED37 // FORMAT_RXE MULTIPLY (short HFP) 2010 op_MEEB uint32 = 0xED17 // FORMAT_RXE MULTIPLY (short BFP) 2011 op_MEEBR uint32 = 0xB317 // FORMAT_RRE MULTIPLY (short BFP) 2012 op_MEER uint32 = 0xB337 // FORMAT_RRE MULTIPLY (short HFP) 2013 op_MER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 2014 op_MFY uint32 = 0xE35C // FORMAT_RXY1 MULTIPLY (64<-32) 2015 op_MGHI uint32 = 0xA70D // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (64) 2016 op_MH uint32 = 0x4C00 // FORMAT_RX1 MULTIPLY HALFWORD (32) 2017 op_MHI uint32 = 0xA70C // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (32) 2018 op_MHY uint32 = 0xE37C // FORMAT_RXY1 MULTIPLY HALFWORD (32) 2019 op_ML uint32 = 0xE396 // FORMAT_RXY1 MULTIPLY LOGICAL (64<-32) 2020 op_MLG uint32 = 0xE386 // FORMAT_RXY1 MULTIPLY LOGICAL (128<-64) 2021 op_MLGR uint32 = 0xB986 // FORMAT_RRE MULTIPLY LOGICAL (128<-64) 2022 op_MLR uint32 = 0xB996 // FORMAT_RRE MULTIPLY LOGICAL (64<-32) 2023 op_MP uint32 = 0xFC00 // FORMAT_SS2 MULTIPLY DECIMAL 2024 op_MR uint32 = 0x1C00 // FORMAT_RR MULTIPLY (64<-32) 2025 op_MS uint32 = 0x7100 // FORMAT_RX1 MULTIPLY SINGLE (32) 2026 op_MSCH uint32 = 0xB232 // FORMAT_S MODIFY SUBCHANNEL 2027 op_MSD uint32 = 0xED3F // FORMAT_RXF MULTIPLY AND SUBTRACT (long HFP) 2028 op_MSDB uint32 = 0xED1F // FORMAT_RXF MULTIPLY AND SUBTRACT (long BFP) 2029 op_MSDBR uint32 = 0xB31F // FORMAT_RRD MULTIPLY AND SUBTRACT (long BFP) 2030 op_MSDR uint32 = 0xB33F // FORMAT_RRD MULTIPLY AND SUBTRACT (long HFP) 2031 op_MSE uint32 = 0xED2F // FORMAT_RXF MULTIPLY AND SUBTRACT (short HFP) 2032 op_MSEB uint32 = 0xED0F // FORMAT_RXF MULTIPLY AND SUBTRACT (short BFP) 2033 op_MSEBR uint32 = 0xB30F // FORMAT_RRD MULTIPLY AND SUBTRACT (short BFP) 2034 op_MSER uint32 = 0xB32F // FORMAT_RRD MULTIPLY AND SUBTRACT (short HFP) 2035 op_MSFI uint32 = 0xC201 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (32) 2036 op_MSG uint32 = 0xE30C // FORMAT_RXY1 MULTIPLY SINGLE (64) 2037 op_MSGF uint32 = 0xE31C // FORMAT_RXY1 MULTIPLY SINGLE (64<-32) 2038 op_MSGFI uint32 = 0xC200 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (64<-32) 2039 op_MSGFR uint32 = 0xB91C // FORMAT_RRE MULTIPLY SINGLE (64<-32) 2040 op_MSGR uint32 = 0xB90C // FORMAT_RRE MULTIPLY SINGLE (64) 2041 op_MSR uint32 = 0xB252 // FORMAT_RRE MULTIPLY SINGLE (32) 2042 op_MSTA uint32 = 0xB247 // FORMAT_RRE MODIFY STACKED STATE 2043 op_MSY uint32 = 0xE351 // FORMAT_RXY1 MULTIPLY SINGLE (32) 2044 op_MVC uint32 = 0xD200 // FORMAT_SS1 MOVE (character) 2045 op_MVCDK uint32 = 0xE50F // FORMAT_SSE MOVE WITH DESTINATION KEY 2046 op_MVCIN uint32 = 0xE800 // FORMAT_SS1 MOVE INVERSE 2047 op_MVCK uint32 = 0xD900 // FORMAT_SS4 MOVE WITH KEY 2048 op_MVCL uint32 = 0x0E00 // FORMAT_RR MOVE LONG 2049 op_MVCLE uint32 = 0xA800 // FORMAT_RS1 MOVE LONG EXTENDED 2050 op_MVCLU uint32 = 0xEB8E // FORMAT_RSY1 MOVE LONG UNICODE 2051 op_MVCOS uint32 = 0xC800 // FORMAT_SSF MOVE WITH OPTIONAL SPECIFICATIONS 2052 op_MVCP uint32 = 0xDA00 // FORMAT_SS4 MOVE TO PRIMARY 2053 op_MVCS uint32 = 0xDB00 // FORMAT_SS4 MOVE TO SECONDARY 2054 op_MVCSK uint32 = 0xE50E // FORMAT_SSE MOVE WITH SOURCE KEY 2055 op_MVGHI uint32 = 0xE548 // FORMAT_SIL MOVE (64<-16) 2056 op_MVHHI uint32 = 0xE544 // FORMAT_SIL MOVE (16<-16) 2057 op_MVHI uint32 = 0xE54C // FORMAT_SIL MOVE (32<-16) 2058 op_MVI uint32 = 0x9200 // FORMAT_SI MOVE (immediate) 2059 op_MVIY uint32 = 0xEB52 // FORMAT_SIY MOVE (immediate) 2060 op_MVN uint32 = 0xD100 // FORMAT_SS1 MOVE NUMERICS 2061 op_MVO uint32 = 0xF100 // FORMAT_SS2 MOVE WITH OFFSET 2062 op_MVPG uint32 = 0xB254 // FORMAT_RRE MOVE PAGE 2063 op_MVST uint32 = 0xB255 // FORMAT_RRE MOVE STRING 2064 op_MVZ uint32 = 0xD300 // FORMAT_SS1 MOVE ZONES 2065 op_MXBR uint32 = 0xB34C // FORMAT_RRE MULTIPLY (extended BFP) 2066 op_MXD uint32 = 0x6700 // FORMAT_RX1 MULTIPLY (long to extended HFP) 2067 op_MXDB uint32 = 0xED07 // FORMAT_RXE MULTIPLY (long to extended BFP) 2068 op_MXDBR uint32 = 0xB307 // FORMAT_RRE MULTIPLY (long to extended BFP) 2069 op_MXDR uint32 = 0x2700 // FORMAT_RR MULTIPLY (long to extended HFP) 2070 op_MXR uint32 = 0x2600 // FORMAT_RR MULTIPLY (extended HFP) 2071 op_MXTR uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2072 op_MXTRA uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2073 op_MY uint32 = 0xED3B // FORMAT_RXF MULTIPLY UNNORMALIZED (long to ext. HFP) 2074 op_MYH uint32 = 0xED3D // FORMAT_RXF MULTIPLY UNNORM. (long to ext. high HFP) 2075 op_MYHR uint32 = 0xB33D // FORMAT_RRD MULTIPLY UNNORM. (long to ext. high HFP) 2076 op_MYL uint32 = 0xED39 // FORMAT_RXF MULTIPLY UNNORM. (long to ext. low HFP) 2077 op_MYLR uint32 = 0xB339 // FORMAT_RRD MULTIPLY UNNORM. (long to ext. low HFP) 2078 op_MYR uint32 = 0xB33B // FORMAT_RRD MULTIPLY UNNORMALIZED (long to ext. HFP) 2079 op_N uint32 = 0x5400 // FORMAT_RX1 AND (32) 2080 op_NC uint32 = 0xD400 // FORMAT_SS1 AND (character) 2081 op_NG uint32 = 0xE380 // FORMAT_RXY1 AND (64) 2082 op_NGR uint32 = 0xB980 // FORMAT_RRE AND (64) 2083 op_NGRK uint32 = 0xB9E4 // FORMAT_RRF1 AND (64) 2084 op_NI uint32 = 0x9400 // FORMAT_SI AND (immediate) 2085 op_NIAI uint32 = 0xB2FA // FORMAT_IE NEXT INSTRUCTION ACCESS INTENT 2086 op_NIHF uint32 = 0xC00A // FORMAT_RIL1 AND IMMEDIATE (high) 2087 op_NIHH uint32 = 0xA504 // FORMAT_RI1 AND IMMEDIATE (high high) 2088 op_NIHL uint32 = 0xA505 // FORMAT_RI1 AND IMMEDIATE (high low) 2089 op_NILF uint32 = 0xC00B // FORMAT_RIL1 AND IMMEDIATE (low) 2090 op_NILH uint32 = 0xA506 // FORMAT_RI1 AND IMMEDIATE (low high) 2091 op_NILL uint32 = 0xA507 // FORMAT_RI1 AND IMMEDIATE (low low) 2092 op_NIY uint32 = 0xEB54 // FORMAT_SIY AND (immediate) 2093 op_NR uint32 = 0x1400 // FORMAT_RR AND (32) 2094 op_NRK uint32 = 0xB9F4 // FORMAT_RRF1 AND (32) 2095 op_NTSTG uint32 = 0xE325 // FORMAT_RXY1 NONTRANSACTIONAL STORE 2096 op_NY uint32 = 0xE354 // FORMAT_RXY1 AND (32) 2097 op_O uint32 = 0x5600 // FORMAT_RX1 OR (32) 2098 op_OC uint32 = 0xD600 // FORMAT_SS1 OR (character) 2099 op_OG uint32 = 0xE381 // FORMAT_RXY1 OR (64) 2100 op_OGR uint32 = 0xB981 // FORMAT_RRE OR (64) 2101 op_OGRK uint32 = 0xB9E6 // FORMAT_RRF1 OR (64) 2102 op_OI uint32 = 0x9600 // FORMAT_SI OR (immediate) 2103 op_OIHF uint32 = 0xC00C // FORMAT_RIL1 OR IMMEDIATE (high) 2104 op_OIHH uint32 = 0xA508 // FORMAT_RI1 OR IMMEDIATE (high high) 2105 op_OIHL uint32 = 0xA509 // FORMAT_RI1 OR IMMEDIATE (high low) 2106 op_OILF uint32 = 0xC00D // FORMAT_RIL1 OR IMMEDIATE (low) 2107 op_OILH uint32 = 0xA50A // FORMAT_RI1 OR IMMEDIATE (low high) 2108 op_OILL uint32 = 0xA50B // FORMAT_RI1 OR IMMEDIATE (low low) 2109 op_OIY uint32 = 0xEB56 // FORMAT_SIY OR (immediate) 2110 op_OR uint32 = 0x1600 // FORMAT_RR OR (32) 2111 op_ORK uint32 = 0xB9F6 // FORMAT_RRF1 OR (32) 2112 op_OY uint32 = 0xE356 // FORMAT_RXY1 OR (32) 2113 op_PACK uint32 = 0xF200 // FORMAT_SS2 PACK 2114 op_PALB uint32 = 0xB248 // FORMAT_RRE PURGE ALB 2115 op_PC uint32 = 0xB218 // FORMAT_S PROGRAM CALL 2116 op_PCC uint32 = 0xB92C // FORMAT_RRE PERFORM CRYPTOGRAPHIC COMPUTATION 2117 op_PCKMO uint32 = 0xB928 // FORMAT_RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS 2118 op_PFD uint32 = 0xE336 // FORMAT_RXY2 PREFETCH DATA 2119 op_PFDRL uint32 = 0xC602 // FORMAT_RIL3 PREFETCH DATA RELATIVE LONG 2120 op_PFMF uint32 = 0xB9AF // FORMAT_RRE PERFORM FRAME MANAGEMENT FUNCTION 2121 op_PFPO uint32 = 0x010A // FORMAT_E PERFORM FLOATING-POINT OPERATION 2122 op_PGIN uint32 = 0xB22E // FORMAT_RRE PAGE IN 2123 op_PGOUT uint32 = 0xB22F // FORMAT_RRE PAGE OUT 2124 op_PKA uint32 = 0xE900 // FORMAT_SS6 PACK ASCII 2125 op_PKU uint32 = 0xE100 // FORMAT_SS6 PACK UNICODE 2126 op_PLO uint32 = 0xEE00 // FORMAT_SS5 PERFORM LOCKED OPERATION 2127 op_POPCNT uint32 = 0xB9E1 // FORMAT_RRE POPULATION COUNT 2128 op_PPA uint32 = 0xB2E8 // FORMAT_RRF3 PERFORM PROCESSOR ASSIST 2129 op_PR uint32 = 0x0101 // FORMAT_E PROGRAM RETURN 2130 op_PT uint32 = 0xB228 // FORMAT_RRE PROGRAM TRANSFER 2131 op_PTF uint32 = 0xB9A2 // FORMAT_RRE PERFORM TOPOLOGY FUNCTION 2132 op_PTFF uint32 = 0x0104 // FORMAT_E PERFORM TIMING FACILITY FUNCTION 2133 op_PTI uint32 = 0xB99E // FORMAT_RRE PROGRAM TRANSFER WITH INSTANCE 2134 op_PTLB uint32 = 0xB20D // FORMAT_S PURGE TLB 2135 op_QADTR uint32 = 0xB3F5 // FORMAT_RRF2 QUANTIZE (long DFP) 2136 op_QAXTR uint32 = 0xB3FD // FORMAT_RRF2 QUANTIZE (extended DFP) 2137 op_RCHP uint32 = 0xB23B // FORMAT_S RESET CHANNEL PATH 2138 op_RISBG uint32 = 0xEC55 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2139 op_RISBGN uint32 = 0xEC59 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2140 op_RISBHG uint32 = 0xEC5D // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS HIGH 2141 op_RISBLG uint32 = 0xEC51 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS LOW 2142 op_RLL uint32 = 0xEB1D // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (32) 2143 op_RLLG uint32 = 0xEB1C // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (64) 2144 op_RNSBG uint32 = 0xEC54 // FORMAT_RIE6 ROTATE THEN AND SELECTED BITS 2145 op_ROSBG uint32 = 0xEC56 // FORMAT_RIE6 ROTATE THEN OR SELECTED BITS 2146 op_RP uint32 = 0xB277 // FORMAT_S RESUME PROGRAM 2147 op_RRBE uint32 = 0xB22A // FORMAT_RRE RESET REFERENCE BIT EXTENDED 2148 op_RRBM uint32 = 0xB9AE // FORMAT_RRE RESET REFERENCE BITS MULTIPLE 2149 op_RRDTR uint32 = 0xB3F7 // FORMAT_RRF2 REROUND (long DFP) 2150 op_RRXTR uint32 = 0xB3FF // FORMAT_RRF2 REROUND (extended DFP) 2151 op_RSCH uint32 = 0xB238 // FORMAT_S RESUME SUBCHANNEL 2152 op_RXSBG uint32 = 0xEC57 // FORMAT_RIE6 ROTATE THEN EXCLUSIVE OR SELECTED BITS 2153 op_S uint32 = 0x5B00 // FORMAT_RX1 SUBTRACT (32) 2154 op_SAC uint32 = 0xB219 // FORMAT_S SET ADDRESS SPACE CONTROL 2155 op_SACF uint32 = 0xB279 // FORMAT_S SET ADDRESS SPACE CONTROL FAST 2156 op_SAL uint32 = 0xB237 // FORMAT_S SET ADDRESS LIMIT 2157 op_SAM24 uint32 = 0x010C // FORMAT_E SET ADDRESSING MODE (24) 2158 op_SAM31 uint32 = 0x010D // FORMAT_E SET ADDRESSING MODE (31) 2159 op_SAM64 uint32 = 0x010E // FORMAT_E SET ADDRESSING MODE (64) 2160 op_SAR uint32 = 0xB24E // FORMAT_RRE SET ACCESS 2161 op_SCHM uint32 = 0xB23C // FORMAT_S SET CHANNEL MONITOR 2162 op_SCK uint32 = 0xB204 // FORMAT_S SET CLOCK 2163 op_SCKC uint32 = 0xB206 // FORMAT_S SET CLOCK COMPARATOR 2164 op_SCKPF uint32 = 0x0107 // FORMAT_E SET CLOCK PROGRAMMABLE FIELD 2165 op_SD uint32 = 0x6B00 // FORMAT_RX1 SUBTRACT NORMALIZED (long HFP) 2166 op_SDB uint32 = 0xED1B // FORMAT_RXE SUBTRACT (long BFP) 2167 op_SDBR uint32 = 0xB31B // FORMAT_RRE SUBTRACT (long BFP) 2168 op_SDR uint32 = 0x2B00 // FORMAT_RR SUBTRACT NORMALIZED (long HFP) 2169 op_SDTR uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2170 op_SDTRA uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2171 op_SE uint32 = 0x7B00 // FORMAT_RX1 SUBTRACT NORMALIZED (short HFP) 2172 op_SEB uint32 = 0xED0B // FORMAT_RXE SUBTRACT (short BFP) 2173 op_SEBR uint32 = 0xB30B // FORMAT_RRE SUBTRACT (short BFP) 2174 op_SER uint32 = 0x3B00 // FORMAT_RR SUBTRACT NORMALIZED (short HFP) 2175 op_SFASR uint32 = 0xB385 // FORMAT_RRE SET FPC AND SIGNAL 2176 op_SFPC uint32 = 0xB384 // FORMAT_RRE SET FPC 2177 op_SG uint32 = 0xE309 // FORMAT_RXY1 SUBTRACT (64) 2178 op_SGF uint32 = 0xE319 // FORMAT_RXY1 SUBTRACT (64<-32) 2179 op_SGFR uint32 = 0xB919 // FORMAT_RRE SUBTRACT (64<-32) 2180 op_SGR uint32 = 0xB909 // FORMAT_RRE SUBTRACT (64) 2181 op_SGRK uint32 = 0xB9E9 // FORMAT_RRF1 SUBTRACT (64) 2182 op_SH uint32 = 0x4B00 // FORMAT_RX1 SUBTRACT HALFWORD 2183 op_SHHHR uint32 = 0xB9C9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2184 op_SHHLR uint32 = 0xB9D9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2185 op_SHY uint32 = 0xE37B // FORMAT_RXY1 SUBTRACT HALFWORD 2186 op_SIGP uint32 = 0xAE00 // FORMAT_RS1 SIGNAL PROCESSOR 2187 op_SL uint32 = 0x5F00 // FORMAT_RX1 SUBTRACT LOGICAL (32) 2188 op_SLA uint32 = 0x8B00 // FORMAT_RS1 SHIFT LEFT SINGLE (32) 2189 op_SLAG uint32 = 0xEB0B // FORMAT_RSY1 SHIFT LEFT SINGLE (64) 2190 op_SLAK uint32 = 0xEBDD // FORMAT_RSY1 SHIFT LEFT SINGLE (32) 2191 op_SLB uint32 = 0xE399 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (32) 2192 op_SLBG uint32 = 0xE389 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (64) 2193 op_SLBGR uint32 = 0xB989 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (64) 2194 op_SLBR uint32 = 0xB999 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (32) 2195 op_SLDA uint32 = 0x8F00 // FORMAT_RS1 SHIFT LEFT DOUBLE 2196 op_SLDL uint32 = 0x8D00 // FORMAT_RS1 SHIFT LEFT DOUBLE LOGICAL 2197 op_SLDT uint32 = 0xED40 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (long DFP) 2198 op_SLFI uint32 = 0xC205 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (32) 2199 op_SLG uint32 = 0xE30B // FORMAT_RXY1 SUBTRACT LOGICAL (64) 2200 op_SLGF uint32 = 0xE31B // FORMAT_RXY1 SUBTRACT LOGICAL (64<-32) 2201 op_SLGFI uint32 = 0xC204 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (64<-32) 2202 op_SLGFR uint32 = 0xB91B // FORMAT_RRE SUBTRACT LOGICAL (64<-32) 2203 op_SLGR uint32 = 0xB90B // FORMAT_RRE SUBTRACT LOGICAL (64) 2204 op_SLGRK uint32 = 0xB9EB // FORMAT_RRF1 SUBTRACT LOGICAL (64) 2205 op_SLHHHR uint32 = 0xB9CB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2206 op_SLHHLR uint32 = 0xB9DB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2207 op_SLL uint32 = 0x8900 // FORMAT_RS1 SHIFT LEFT SINGLE LOGICAL (32) 2208 op_SLLG uint32 = 0xEB0D // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (64) 2209 op_SLLK uint32 = 0xEBDF // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (32) 2210 op_SLR uint32 = 0x1F00 // FORMAT_RR SUBTRACT LOGICAL (32) 2211 op_SLRK uint32 = 0xB9FB // FORMAT_RRF1 SUBTRACT LOGICAL (32) 2212 op_SLXT uint32 = 0xED48 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (extended DFP) 2213 op_SLY uint32 = 0xE35F // FORMAT_RXY1 SUBTRACT LOGICAL (32) 2214 op_SP uint32 = 0xFB00 // FORMAT_SS2 SUBTRACT DECIMAL 2215 op_SPKA uint32 = 0xB20A // FORMAT_S SET PSW KEY FROM ADDRESS 2216 op_SPM uint32 = 0x0400 // FORMAT_RR SET PROGRAM MASK 2217 op_SPT uint32 = 0xB208 // FORMAT_S SET CPU TIMER 2218 op_SPX uint32 = 0xB210 // FORMAT_S SET PREFIX 2219 op_SQD uint32 = 0xED35 // FORMAT_RXE SQUARE ROOT (long HFP) 2220 op_SQDB uint32 = 0xED15 // FORMAT_RXE SQUARE ROOT (long BFP) 2221 op_SQDBR uint32 = 0xB315 // FORMAT_RRE SQUARE ROOT (long BFP) 2222 op_SQDR uint32 = 0xB244 // FORMAT_RRE SQUARE ROOT (long HFP) 2223 op_SQE uint32 = 0xED34 // FORMAT_RXE SQUARE ROOT (short HFP) 2224 op_SQEB uint32 = 0xED14 // FORMAT_RXE SQUARE ROOT (short BFP) 2225 op_SQEBR uint32 = 0xB314 // FORMAT_RRE SQUARE ROOT (short BFP) 2226 op_SQER uint32 = 0xB245 // FORMAT_RRE SQUARE ROOT (short HFP) 2227 op_SQXBR uint32 = 0xB316 // FORMAT_RRE SQUARE ROOT (extended BFP) 2228 op_SQXR uint32 = 0xB336 // FORMAT_RRE SQUARE ROOT (extended HFP) 2229 op_SR uint32 = 0x1B00 // FORMAT_RR SUBTRACT (32) 2230 op_SRA uint32 = 0x8A00 // FORMAT_RS1 SHIFT RIGHT SINGLE (32) 2231 op_SRAG uint32 = 0xEB0A // FORMAT_RSY1 SHIFT RIGHT SINGLE (64) 2232 op_SRAK uint32 = 0xEBDC // FORMAT_RSY1 SHIFT RIGHT SINGLE (32) 2233 op_SRDA uint32 = 0x8E00 // FORMAT_RS1 SHIFT RIGHT DOUBLE 2234 op_SRDL uint32 = 0x8C00 // FORMAT_RS1 SHIFT RIGHT DOUBLE LOGICAL 2235 op_SRDT uint32 = 0xED41 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (long DFP) 2236 op_SRK uint32 = 0xB9F9 // FORMAT_RRF1 SUBTRACT (32) 2237 op_SRL uint32 = 0x8800 // FORMAT_RS1 SHIFT RIGHT SINGLE LOGICAL (32) 2238 op_SRLG uint32 = 0xEB0C // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (64) 2239 op_SRLK uint32 = 0xEBDE // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (32) 2240 op_SRNM uint32 = 0xB299 // FORMAT_S SET BFP ROUNDING MODE (2 bit) 2241 op_SRNMB uint32 = 0xB2B8 // FORMAT_S SET BFP ROUNDING MODE (3 bit) 2242 op_SRNMT uint32 = 0xB2B9 // FORMAT_S SET DFP ROUNDING MODE 2243 op_SRP uint32 = 0xF000 // FORMAT_SS3 SHIFT AND ROUND DECIMAL 2244 op_SRST uint32 = 0xB25E // FORMAT_RRE SEARCH STRING 2245 op_SRSTU uint32 = 0xB9BE // FORMAT_RRE SEARCH STRING UNICODE 2246 op_SRXT uint32 = 0xED49 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (extended DFP) 2247 op_SSAIR uint32 = 0xB99F // FORMAT_RRE SET SECONDARY ASN WITH INSTANCE 2248 op_SSAR uint32 = 0xB225 // FORMAT_RRE SET SECONDARY ASN 2249 op_SSCH uint32 = 0xB233 // FORMAT_S START SUBCHANNEL 2250 op_SSKE uint32 = 0xB22B // FORMAT_RRF3 SET STORAGE KEY EXTENDED 2251 op_SSM uint32 = 0x8000 // FORMAT_S SET SYSTEM MASK 2252 op_ST uint32 = 0x5000 // FORMAT_RX1 STORE (32) 2253 op_STAM uint32 = 0x9B00 // FORMAT_RS1 STORE ACCESS MULTIPLE 2254 op_STAMY uint32 = 0xEB9B // FORMAT_RSY1 STORE ACCESS MULTIPLE 2255 op_STAP uint32 = 0xB212 // FORMAT_S STORE CPU ADDRESS 2256 op_STC uint32 = 0x4200 // FORMAT_RX1 STORE CHARACTER 2257 op_STCH uint32 = 0xE3C3 // FORMAT_RXY1 STORE CHARACTER HIGH (8) 2258 op_STCK uint32 = 0xB205 // FORMAT_S STORE CLOCK 2259 op_STCKC uint32 = 0xB207 // FORMAT_S STORE CLOCK COMPARATOR 2260 op_STCKE uint32 = 0xB278 // FORMAT_S STORE CLOCK EXTENDED 2261 op_STCKF uint32 = 0xB27C // FORMAT_S STORE CLOCK FAST 2262 op_STCM uint32 = 0xBE00 // FORMAT_RS2 STORE CHARACTERS UNDER MASK (low) 2263 op_STCMH uint32 = 0xEB2C // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (high) 2264 op_STCMY uint32 = 0xEB2D // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (low) 2265 op_STCPS uint32 = 0xB23A // FORMAT_S STORE CHANNEL PATH STATUS 2266 op_STCRW uint32 = 0xB239 // FORMAT_S STORE CHANNEL REPORT WORD 2267 op_STCTG uint32 = 0xEB25 // FORMAT_RSY1 STORE CONTROL (64) 2268 op_STCTL uint32 = 0xB600 // FORMAT_RS1 STORE CONTROL (32) 2269 op_STCY uint32 = 0xE372 // FORMAT_RXY1 STORE CHARACTER 2270 op_STD uint32 = 0x6000 // FORMAT_RX1 STORE (long) 2271 op_STDY uint32 = 0xED67 // FORMAT_RXY1 STORE (long) 2272 op_STE uint32 = 0x7000 // FORMAT_RX1 STORE (short) 2273 op_STEY uint32 = 0xED66 // FORMAT_RXY1 STORE (short) 2274 op_STFH uint32 = 0xE3CB // FORMAT_RXY1 STORE HIGH (32) 2275 op_STFL uint32 = 0xB2B1 // FORMAT_S STORE FACILITY LIST 2276 op_STFLE uint32 = 0xB2B0 // FORMAT_S STORE FACILITY LIST EXTENDED 2277 op_STFPC uint32 = 0xB29C // FORMAT_S STORE FPC 2278 op_STG uint32 = 0xE324 // FORMAT_RXY1 STORE (64) 2279 op_STGRL uint32 = 0xC40B // FORMAT_RIL2 STORE RELATIVE LONG (64) 2280 op_STH uint32 = 0x4000 // FORMAT_RX1 STORE HALFWORD 2281 op_STHH uint32 = 0xE3C7 // FORMAT_RXY1 STORE HALFWORD HIGH (16) 2282 op_STHRL uint32 = 0xC407 // FORMAT_RIL2 STORE HALFWORD RELATIVE LONG 2283 op_STHY uint32 = 0xE370 // FORMAT_RXY1 STORE HALFWORD 2284 op_STIDP uint32 = 0xB202 // FORMAT_S STORE CPU ID 2285 op_STM uint32 = 0x9000 // FORMAT_RS1 STORE MULTIPLE (32) 2286 op_STMG uint32 = 0xEB24 // FORMAT_RSY1 STORE MULTIPLE (64) 2287 op_STMH uint32 = 0xEB26 // FORMAT_RSY1 STORE MULTIPLE HIGH 2288 op_STMY uint32 = 0xEB90 // FORMAT_RSY1 STORE MULTIPLE (32) 2289 op_STNSM uint32 = 0xAC00 // FORMAT_SI STORE THEN AND SYSTEM MASK 2290 op_STOC uint32 = 0xEBF3 // FORMAT_RSY2 STORE ON CONDITION (32) 2291 op_STOCG uint32 = 0xEBE3 // FORMAT_RSY2 STORE ON CONDITION (64) 2292 op_STOSM uint32 = 0xAD00 // FORMAT_SI STORE THEN OR SYSTEM MASK 2293 op_STPQ uint32 = 0xE38E // FORMAT_RXY1 STORE PAIR TO QUADWORD 2294 op_STPT uint32 = 0xB209 // FORMAT_S STORE CPU TIMER 2295 op_STPX uint32 = 0xB211 // FORMAT_S STORE PREFIX 2296 op_STRAG uint32 = 0xE502 // FORMAT_SSE STORE REAL ADDRESS 2297 op_STRL uint32 = 0xC40F // FORMAT_RIL2 STORE RELATIVE LONG (32) 2298 op_STRV uint32 = 0xE33E // FORMAT_RXY1 STORE REVERSED (32) 2299 op_STRVG uint32 = 0xE32F // FORMAT_RXY1 STORE REVERSED (64) 2300 op_STRVH uint32 = 0xE33F // FORMAT_RXY1 STORE REVERSED (16) 2301 op_STSCH uint32 = 0xB234 // FORMAT_S STORE SUBCHANNEL 2302 op_STSI uint32 = 0xB27D // FORMAT_S STORE SYSTEM INFORMATION 2303 op_STURA uint32 = 0xB246 // FORMAT_RRE STORE USING REAL ADDRESS (32) 2304 op_STURG uint32 = 0xB925 // FORMAT_RRE STORE USING REAL ADDRESS (64) 2305 op_STY uint32 = 0xE350 // FORMAT_RXY1 STORE (32) 2306 op_SU uint32 = 0x7F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (short HFP) 2307 op_SUR uint32 = 0x3F00 // FORMAT_RR SUBTRACT UNNORMALIZED (short HFP) 2308 op_SVC uint32 = 0x0A00 // FORMAT_I SUPERVISOR CALL 2309 op_SW uint32 = 0x6F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (long HFP) 2310 op_SWR uint32 = 0x2F00 // FORMAT_RR SUBTRACT UNNORMALIZED (long HFP) 2311 op_SXBR uint32 = 0xB34B // FORMAT_RRE SUBTRACT (extended BFP) 2312 op_SXR uint32 = 0x3700 // FORMAT_RR SUBTRACT NORMALIZED (extended HFP) 2313 op_SXTR uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2314 op_SXTRA uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2315 op_SY uint32 = 0xE35B // FORMAT_RXY1 SUBTRACT (32) 2316 op_TABORT uint32 = 0xB2FC // FORMAT_S TRANSACTION ABORT 2317 op_TAM uint32 = 0x010B // FORMAT_E TEST ADDRESSING MODE 2318 op_TAR uint32 = 0xB24C // FORMAT_RRE TEST ACCESS 2319 op_TB uint32 = 0xB22C // FORMAT_RRE TEST BLOCK 2320 op_TBDR uint32 = 0xB351 // FORMAT_RRF5 CONVERT HFP TO BFP (long) 2321 op_TBEDR uint32 = 0xB350 // FORMAT_RRF5 CONVERT HFP TO BFP (long to short) 2322 op_TBEGIN uint32 = 0xE560 // FORMAT_SIL TRANSACTION BEGIN 2323 op_TBEGINC uint32 = 0xE561 // FORMAT_SIL TRANSACTION BEGIN 2324 op_TCDB uint32 = 0xED11 // FORMAT_RXE TEST DATA CLASS (long BFP) 2325 op_TCEB uint32 = 0xED10 // FORMAT_RXE TEST DATA CLASS (short BFP) 2326 op_TCXB uint32 = 0xED12 // FORMAT_RXE TEST DATA CLASS (extended BFP) 2327 op_TDCDT uint32 = 0xED54 // FORMAT_RXE TEST DATA CLASS (long DFP) 2328 op_TDCET uint32 = 0xED50 // FORMAT_RXE TEST DATA CLASS (short DFP) 2329 op_TDCXT uint32 = 0xED58 // FORMAT_RXE TEST DATA CLASS (extended DFP) 2330 op_TDGDT uint32 = 0xED55 // FORMAT_RXE TEST DATA GROUP (long DFP) 2331 op_TDGET uint32 = 0xED51 // FORMAT_RXE TEST DATA GROUP (short DFP) 2332 op_TDGXT uint32 = 0xED59 // FORMAT_RXE TEST DATA GROUP (extended DFP) 2333 op_TEND uint32 = 0xB2F8 // FORMAT_S TRANSACTION END 2334 op_THDER uint32 = 0xB358 // FORMAT_RRE CONVERT BFP TO HFP (short to long) 2335 op_THDR uint32 = 0xB359 // FORMAT_RRE CONVERT BFP TO HFP (long) 2336 op_TM uint32 = 0x9100 // FORMAT_SI TEST UNDER MASK 2337 op_TMH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK HIGH 2338 op_TMHH uint32 = 0xA702 // FORMAT_RI1 TEST UNDER MASK (high high) 2339 op_TMHL uint32 = 0xA703 // FORMAT_RI1 TEST UNDER MASK (high low) 2340 op_TML uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK LOW 2341 op_TMLH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK (low high) 2342 op_TMLL uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK (low low) 2343 op_TMY uint32 = 0xEB51 // FORMAT_SIY TEST UNDER MASK 2344 op_TP uint32 = 0xEBC0 // FORMAT_RSL TEST DECIMAL 2345 op_TPI uint32 = 0xB236 // FORMAT_S TEST PENDING INTERRUPTION 2346 op_TPROT uint32 = 0xE501 // FORMAT_SSE TEST PROTECTION 2347 op_TR uint32 = 0xDC00 // FORMAT_SS1 TRANSLATE 2348 op_TRACE uint32 = 0x9900 // FORMAT_RS1 TRACE (32) 2349 op_TRACG uint32 = 0xEB0F // FORMAT_RSY1 TRACE (64) 2350 op_TRAP2 uint32 = 0x01FF // FORMAT_E TRAP 2351 op_TRAP4 uint32 = 0xB2FF // FORMAT_S TRAP 2352 op_TRE uint32 = 0xB2A5 // FORMAT_RRE TRANSLATE EXTENDED 2353 op_TROO uint32 = 0xB993 // FORMAT_RRF3 TRANSLATE ONE TO ONE 2354 op_TROT uint32 = 0xB992 // FORMAT_RRF3 TRANSLATE ONE TO TWO 2355 op_TRT uint32 = 0xDD00 // FORMAT_SS1 TRANSLATE AND TEST 2356 op_TRTE uint32 = 0xB9BF // FORMAT_RRF3 TRANSLATE AND TEST EXTENDED 2357 op_TRTO uint32 = 0xB991 // FORMAT_RRF3 TRANSLATE TWO TO ONE 2358 op_TRTR uint32 = 0xD000 // FORMAT_SS1 TRANSLATE AND TEST REVERSE 2359 op_TRTRE uint32 = 0xB9BD // FORMAT_RRF3 TRANSLATE AND TEST REVERSE EXTENDED 2360 op_TRTT uint32 = 0xB990 // FORMAT_RRF3 TRANSLATE TWO TO TWO 2361 op_TS uint32 = 0x9300 // FORMAT_S TEST AND SET 2362 op_TSCH uint32 = 0xB235 // FORMAT_S TEST SUBCHANNEL 2363 op_UNPK uint32 = 0xF300 // FORMAT_SS2 UNPACK 2364 op_UNPKA uint32 = 0xEA00 // FORMAT_SS1 UNPACK ASCII 2365 op_UNPKU uint32 = 0xE200 // FORMAT_SS1 UNPACK UNICODE 2366 op_UPT uint32 = 0x0102 // FORMAT_E UPDATE TREE 2367 op_X uint32 = 0x5700 // FORMAT_RX1 EXCLUSIVE OR (32) 2368 op_XC uint32 = 0xD700 // FORMAT_SS1 EXCLUSIVE OR (character) 2369 op_XG uint32 = 0xE382 // FORMAT_RXY1 EXCLUSIVE OR (64) 2370 op_XGR uint32 = 0xB982 // FORMAT_RRE EXCLUSIVE OR (64) 2371 op_XGRK uint32 = 0xB9E7 // FORMAT_RRF1 EXCLUSIVE OR (64) 2372 op_XI uint32 = 0x9700 // FORMAT_SI EXCLUSIVE OR (immediate) 2373 op_XIHF uint32 = 0xC006 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (high) 2374 op_XILF uint32 = 0xC007 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (low) 2375 op_XIY uint32 = 0xEB57 // FORMAT_SIY EXCLUSIVE OR (immediate) 2376 op_XR uint32 = 0x1700 // FORMAT_RR EXCLUSIVE OR (32) 2377 op_XRK uint32 = 0xB9F7 // FORMAT_RRF1 EXCLUSIVE OR (32) 2378 op_XSCH uint32 = 0xB276 // FORMAT_S CANCEL SUBCHANNEL 2379 op_XY uint32 = 0xE357 // FORMAT_RXY1 EXCLUSIVE OR (32) 2380 op_ZAP uint32 = 0xF800 // FORMAT_SS2 ZERO AND ADD 2381 2382 // added in z13 2383 op_CXPT uint32 = 0xEDAF // RSL-b CONVERT FROM PACKED (to extended DFP) 2384 op_CDPT uint32 = 0xEDAE // RSL-b CONVERT FROM PACKED (to long DFP) 2385 op_CPXT uint32 = 0xEDAD // RSL-b CONVERT TO PACKED (from extended DFP) 2386 op_CPDT uint32 = 0xEDAC // RSL-b CONVERT TO PACKED (from long DFP) 2387 op_LZRF uint32 = 0xE33B // RXY-a LOAD AND ZERO RIGHTMOST BYTE (32) 2388 op_LZRG uint32 = 0xE32A // RXY-a LOAD AND ZERO RIGHTMOST BYTE (64) 2389 op_LCCB uint32 = 0xE727 // RXE LOAD COUNT TO BLOCK BOUNDARY 2390 op_LOCHHI uint32 = 0xEC4E // RIE-g LOAD HALFWORD HIGH IMMEDIATE ON CONDITION (32←16) 2391 op_LOCHI uint32 = 0xEC42 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (32←16) 2392 op_LOCGHI uint32 = 0xEC46 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (64←16) 2393 op_LOCFH uint32 = 0xEBE0 // RSY-b LOAD HIGH ON CONDITION (32) 2394 op_LOCFHR uint32 = 0xB9E0 // RRF-c LOAD HIGH ON CONDITION (32) 2395 op_LLZRGF uint32 = 0xE33A // RXY-a LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64←32) 2396 op_STOCFH uint32 = 0xEBE1 // RSY-b STORE HIGH ON CONDITION 2397 op_VA uint32 = 0xE7F3 // VRR-c VECTOR ADD 2398 op_VACC uint32 = 0xE7F1 // VRR-c VECTOR ADD COMPUTE CARRY 2399 op_VAC uint32 = 0xE7BB // VRR-d VECTOR ADD WITH CARRY 2400 op_VACCC uint32 = 0xE7B9 // VRR-d VECTOR ADD WITH CARRY COMPUTE CARRY 2401 op_VN uint32 = 0xE768 // VRR-c VECTOR AND 2402 op_VNC uint32 = 0xE769 // VRR-c VECTOR AND WITH COMPLEMENT 2403 op_VAVG uint32 = 0xE7F2 // VRR-c VECTOR AVERAGE 2404 op_VAVGL uint32 = 0xE7F0 // VRR-c VECTOR AVERAGE LOGICAL 2405 op_VCKSM uint32 = 0xE766 // VRR-c VECTOR CHECKSUM 2406 op_VCEQ uint32 = 0xE7F8 // VRR-b VECTOR COMPARE EQUAL 2407 op_VCH uint32 = 0xE7FB // VRR-b VECTOR COMPARE HIGH 2408 op_VCHL uint32 = 0xE7F9 // VRR-b VECTOR COMPARE HIGH LOGICAL 2409 op_VCLZ uint32 = 0xE753 // VRR-a VECTOR COUNT LEADING ZEROS 2410 op_VCTZ uint32 = 0xE752 // VRR-a VECTOR COUNT TRAILING ZEROS 2411 op_VEC uint32 = 0xE7DB // VRR-a VECTOR ELEMENT COMPARE 2412 op_VECL uint32 = 0xE7D9 // VRR-a VECTOR ELEMENT COMPARE LOGICAL 2413 op_VERIM uint32 = 0xE772 // VRI-d VECTOR ELEMENT ROTATE AND INSERT UNDER MASK 2414 op_VERLL uint32 = 0xE733 // VRS-a VECTOR ELEMENT ROTATE LEFT LOGICAL 2415 op_VERLLV uint32 = 0xE773 // VRR-c VECTOR ELEMENT ROTATE LEFT LOGICAL 2416 op_VESLV uint32 = 0xE770 // VRR-c VECTOR ELEMENT SHIFT LEFT 2417 op_VESL uint32 = 0xE730 // VRS-a VECTOR ELEMENT SHIFT LEFT 2418 op_VESRA uint32 = 0xE73A // VRS-a VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2419 op_VESRAV uint32 = 0xE77A // VRR-c VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2420 op_VESRL uint32 = 0xE738 // VRS-a VECTOR ELEMENT SHIFT RIGHT LOGICAL 2421 op_VESRLV uint32 = 0xE778 // VRR-c VECTOR ELEMENT SHIFT RIGHT LOGICAL 2422 op_VX uint32 = 0xE76D // VRR-c VECTOR EXCLUSIVE OR 2423 op_VFAE uint32 = 0xE782 // VRR-b VECTOR FIND ANY ELEMENT EQUAL 2424 op_VFEE uint32 = 0xE780 // VRR-b VECTOR FIND ELEMENT EQUAL 2425 op_VFENE uint32 = 0xE781 // VRR-b VECTOR FIND ELEMENT NOT EQUAL 2426 op_VFA uint32 = 0xE7E3 // VRR-c VECTOR FP ADD 2427 op_WFK uint32 = 0xE7CA // VRR-a VECTOR FP COMPARE AND SIGNAL SCALAR 2428 op_VFCE uint32 = 0xE7E8 // VRR-c VECTOR FP COMPARE EQUAL 2429 op_VFCH uint32 = 0xE7EB // VRR-c VECTOR FP COMPARE HIGH 2430 op_VFCHE uint32 = 0xE7EA // VRR-c VECTOR FP COMPARE HIGH OR EQUAL 2431 op_WFC uint32 = 0xE7CB // VRR-a VECTOR FP COMPARE SCALAR 2432 op_VCDG uint32 = 0xE7C3 // VRR-a VECTOR FP CONVERT FROM FIXED 64-BIT 2433 op_VCDLG uint32 = 0xE7C1 // VRR-a VECTOR FP CONVERT FROM LOGICAL 64-BIT 2434 op_VCGD uint32 = 0xE7C2 // VRR-a VECTOR FP CONVERT TO FIXED 64-BIT 2435 op_VCLGD uint32 = 0xE7C0 // VRR-a VECTOR FP CONVERT TO LOGICAL 64-BIT 2436 op_VFD uint32 = 0xE7E5 // VRR-c VECTOR FP DIVIDE 2437 op_VLDE uint32 = 0xE7C4 // VRR-a VECTOR FP LOAD LENGTHENED 2438 op_VLED uint32 = 0xE7C5 // VRR-a VECTOR FP LOAD ROUNDED 2439 op_VFM uint32 = 0xE7E7 // VRR-c VECTOR FP MULTIPLY 2440 op_VFMA uint32 = 0xE78F // VRR-e VECTOR FP MULTIPLY AND ADD 2441 op_VFMS uint32 = 0xE78E // VRR-e VECTOR FP MULTIPLY AND SUBTRACT 2442 op_VFPSO uint32 = 0xE7CC // VRR-a VECTOR FP PERFORM SIGN OPERATION 2443 op_VFSQ uint32 = 0xE7CE // VRR-a VECTOR FP SQUARE ROOT 2444 op_VFS uint32 = 0xE7E2 // VRR-c VECTOR FP SUBTRACT 2445 op_VFTCI uint32 = 0xE74A // VRI-e VECTOR FP TEST DATA CLASS IMMEDIATE 2446 op_VGFM uint32 = 0xE7B4 // VRR-c VECTOR GALOIS FIELD MULTIPLY SUM 2447 op_VGFMA uint32 = 0xE7BC // VRR-d VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE 2448 op_VGEF uint32 = 0xE713 // VRV VECTOR GATHER ELEMENT (32) 2449 op_VGEG uint32 = 0xE712 // VRV VECTOR GATHER ELEMENT (64) 2450 op_VGBM uint32 = 0xE744 // VRI-a VECTOR GENERATE BYTE MASK 2451 op_VGM uint32 = 0xE746 // VRI-b VECTOR GENERATE MASK 2452 op_VISTR uint32 = 0xE75C // VRR-a VECTOR ISOLATE STRING 2453 op_VL uint32 = 0xE706 // VRX VECTOR LOAD 2454 op_VLR uint32 = 0xE756 // VRR-a VECTOR LOAD 2455 op_VLREP uint32 = 0xE705 // VRX VECTOR LOAD AND REPLICATE 2456 op_VLC uint32 = 0xE7DE // VRR-a VECTOR LOAD COMPLEMENT 2457 op_VLEH uint32 = 0xE701 // VRX VECTOR LOAD ELEMENT (16) 2458 op_VLEF uint32 = 0xE703 // VRX VECTOR LOAD ELEMENT (32) 2459 op_VLEG uint32 = 0xE702 // VRX VECTOR LOAD ELEMENT (64) 2460 op_VLEB uint32 = 0xE700 // VRX VECTOR LOAD ELEMENT (8) 2461 op_VLEIH uint32 = 0xE741 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (16) 2462 op_VLEIF uint32 = 0xE743 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (32) 2463 op_VLEIG uint32 = 0xE742 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (64) 2464 op_VLEIB uint32 = 0xE740 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (8) 2465 op_VFI uint32 = 0xE7C7 // VRR-a VECTOR LOAD FP INTEGER 2466 op_VLGV uint32 = 0xE721 // VRS-c VECTOR LOAD GR FROM VR ELEMENT 2467 op_VLLEZ uint32 = 0xE704 // VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO 2468 op_VLM uint32 = 0xE736 // VRS-a VECTOR LOAD MULTIPLE 2469 op_VLP uint32 = 0xE7DF // VRR-a VECTOR LOAD POSITIVE 2470 op_VLBB uint32 = 0xE707 // VRX VECTOR LOAD TO BLOCK BOUNDARY 2471 op_VLVG uint32 = 0xE722 // VRS-b VECTOR LOAD VR ELEMENT FROM GR 2472 op_VLVGP uint32 = 0xE762 // VRR-f VECTOR LOAD VR FROM GRS DISJOINT 2473 op_VLL uint32 = 0xE737 // VRS-b VECTOR LOAD WITH LENGTH 2474 op_VMX uint32 = 0xE7FF // VRR-c VECTOR MAXIMUM 2475 op_VMXL uint32 = 0xE7FD // VRR-c VECTOR MAXIMUM LOGICAL 2476 op_VMRH uint32 = 0xE761 // VRR-c VECTOR MERGE HIGH 2477 op_VMRL uint32 = 0xE760 // VRR-c VECTOR MERGE LOW 2478 op_VMN uint32 = 0xE7FE // VRR-c VECTOR MINIMUM 2479 op_VMNL uint32 = 0xE7FC // VRR-c VECTOR MINIMUM LOGICAL 2480 op_VMAE uint32 = 0xE7AE // VRR-d VECTOR MULTIPLY AND ADD EVEN 2481 op_VMAH uint32 = 0xE7AB // VRR-d VECTOR MULTIPLY AND ADD HIGH 2482 op_VMALE uint32 = 0xE7AC // VRR-d VECTOR MULTIPLY AND ADD LOGICAL EVEN 2483 op_VMALH uint32 = 0xE7A9 // VRR-d VECTOR MULTIPLY AND ADD LOGICAL HIGH 2484 op_VMALO uint32 = 0xE7AD // VRR-d VECTOR MULTIPLY AND ADD LOGICAL ODD 2485 op_VMAL uint32 = 0xE7AA // VRR-d VECTOR MULTIPLY AND ADD LOW 2486 op_VMAO uint32 = 0xE7AF // VRR-d VECTOR MULTIPLY AND ADD ODD 2487 op_VME uint32 = 0xE7A6 // VRR-c VECTOR MULTIPLY EVEN 2488 op_VMH uint32 = 0xE7A3 // VRR-c VECTOR MULTIPLY HIGH 2489 op_VMLE uint32 = 0xE7A4 // VRR-c VECTOR MULTIPLY EVEN LOGICAL 2490 op_VMLH uint32 = 0xE7A1 // VRR-c VECTOR MULTIPLY HIGH LOGICAL 2491 op_VMLO uint32 = 0xE7A5 // VRR-c VECTOR MULTIPLY ODD LOGICAL 2492 op_VML uint32 = 0xE7A2 // VRR-c VECTOR MULTIPLY LOW 2493 op_VMO uint32 = 0xE7A7 // VRR-c VECTOR MULTIPLY ODD 2494 op_VNO uint32 = 0xE76B // VRR-c VECTOR NOR 2495 op_VO uint32 = 0xE76A // VRR-c VECTOR OR 2496 op_VPK uint32 = 0xE794 // VRR-c VECTOR PACK 2497 op_VPKLS uint32 = 0xE795 // VRR-b VECTOR PACK LOGICAL SATURATE 2498 op_VPKS uint32 = 0xE797 // VRR-b VECTOR PACK SATURATE 2499 op_VPERM uint32 = 0xE78C // VRR-e VECTOR PERMUTE 2500 op_VPDI uint32 = 0xE784 // VRR-c VECTOR PERMUTE DOUBLEWORD IMMEDIATE 2501 op_VPOPCT uint32 = 0xE750 // VRR-a VECTOR POPULATION COUNT 2502 op_VREP uint32 = 0xE74D // VRI-c VECTOR REPLICATE 2503 op_VREPI uint32 = 0xE745 // VRI-a VECTOR REPLICATE IMMEDIATE 2504 op_VSCEF uint32 = 0xE71B // VRV VECTOR SCATTER ELEMENT (32) 2505 op_VSCEG uint32 = 0xE71A // VRV VECTOR SCATTER ELEMENT (64) 2506 op_VSEL uint32 = 0xE78D // VRR-e VECTOR SELECT 2507 op_VSL uint32 = 0xE774 // VRR-c VECTOR SHIFT LEFT 2508 op_VSLB uint32 = 0xE775 // VRR-c VECTOR SHIFT LEFT BY BYTE 2509 op_VSLDB uint32 = 0xE777 // VRI-d VECTOR SHIFT LEFT DOUBLE BY BYTE 2510 op_VSRA uint32 = 0xE77E // VRR-c VECTOR SHIFT RIGHT ARITHMETIC 2511 op_VSRAB uint32 = 0xE77F // VRR-c VECTOR SHIFT RIGHT ARITHMETIC BY BYTE 2512 op_VSRL uint32 = 0xE77C // VRR-c VECTOR SHIFT RIGHT LOGICAL 2513 op_VSRLB uint32 = 0xE77D // VRR-c VECTOR SHIFT RIGHT LOGICAL BY BYTE 2514 op_VSEG uint32 = 0xE75F // VRR-a VECTOR SIGN EXTEND TO DOUBLEWORD 2515 op_VST uint32 = 0xE70E // VRX VECTOR STORE 2516 op_VSTEH uint32 = 0xE709 // VRX VECTOR STORE ELEMENT (16) 2517 op_VSTEF uint32 = 0xE70B // VRX VECTOR STORE ELEMENT (32) 2518 op_VSTEG uint32 = 0xE70A // VRX VECTOR STORE ELEMENT (64) 2519 op_VSTEB uint32 = 0xE708 // VRX VECTOR STORE ELEMENT (8) 2520 op_VSTM uint32 = 0xE73E // VRS-a VECTOR STORE MULTIPLE 2521 op_VSTL uint32 = 0xE73F // VRS-b VECTOR STORE WITH LENGTH 2522 op_VSTRC uint32 = 0xE78A // VRR-d VECTOR STRING RANGE COMPARE 2523 op_VS uint32 = 0xE7F7 // VRR-c VECTOR SUBTRACT 2524 op_VSCBI uint32 = 0xE7F5 // VRR-c VECTOR SUBTRACT COMPUTE BORROW INDICATION 2525 op_VSBCBI uint32 = 0xE7BD // VRR-d VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION 2526 op_VSBI uint32 = 0xE7BF // VRR-d VECTOR SUBTRACT WITH BORROW INDICATION 2527 op_VSUMG uint32 = 0xE765 // VRR-c VECTOR SUM ACROSS DOUBLEWORD 2528 op_VSUMQ uint32 = 0xE767 // VRR-c VECTOR SUM ACROSS QUADWORD 2529 op_VSUM uint32 = 0xE764 // VRR-c VECTOR SUM ACROSS WORD 2530 op_VTM uint32 = 0xE7D8 // VRR-a VECTOR TEST UNDER MASK 2531 op_VUPH uint32 = 0xE7D7 // VRR-a VECTOR UNPACK HIGH 2532 op_VUPLH uint32 = 0xE7D5 // VRR-a VECTOR UNPACK LOGICAL HIGH 2533 op_VUPLL uint32 = 0xE7D4 // VRR-a VECTOR UNPACK LOGICAL LOW 2534 op_VUPL uint32 = 0xE7D6 // VRR-a VECTOR UNPACK LOW 2535 op_VMSL uint32 = 0xE7B8 // VRR-d VECTOR MULTIPLY SUM LOGICAL 2536 ) 2537 2538 func oclass(a *obj.Addr) int { 2539 return int(a.Class) - 1 2540 } 2541 2542 // Add a relocation for the immediate in a RIL style instruction. 2543 // The addend will be adjusted as required. 2544 func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) *obj.Reloc { 2545 if sym == nil { 2546 c.ctxt.Diag("require symbol to apply relocation") 2547 } 2548 offset := int64(2) // relocation offset from start of instruction 2549 rel := obj.Addrel(c.cursym) 2550 rel.Off = int32(c.pc + offset) 2551 rel.Siz = 4 2552 rel.Sym = sym 2553 rel.Add = add + offset + int64(rel.Siz) 2554 rel.Type = objabi.R_PCRELDBL 2555 return rel 2556 } 2557 2558 func (c *ctxtz) addrilrelocoffset(sym *obj.LSym, add, offset int64) *obj.Reloc { 2559 if sym == nil { 2560 c.ctxt.Diag("require symbol to apply relocation") 2561 } 2562 offset += int64(2) // relocation offset from start of instruction 2563 rel := obj.Addrel(c.cursym) 2564 rel.Off = int32(c.pc + offset) 2565 rel.Siz = 4 2566 rel.Sym = sym 2567 rel.Add = add + offset + int64(rel.Siz) 2568 rel.Type = objabi.R_PCRELDBL 2569 return rel 2570 } 2571 2572 // Add a CALL relocation for the immediate in a RIL style instruction. 2573 // The addend will be adjusted as required. 2574 func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) *obj.Reloc { 2575 if sym == nil { 2576 c.ctxt.Diag("require symbol to apply relocation") 2577 } 2578 offset := int64(2) // relocation offset from start of instruction 2579 rel := obj.Addrel(c.cursym) 2580 rel.Off = int32(c.pc + offset) 2581 rel.Siz = 4 2582 rel.Sym = sym 2583 rel.Add = add + offset + int64(rel.Siz) 2584 rel.Type = objabi.R_CALL 2585 return rel 2586 } 2587 2588 func (c *ctxtz) branchMask(p *obj.Prog) uint32 { 2589 switch p.As { 2590 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ: 2591 return 0x8 2592 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE: 2593 return 0xA 2594 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT: 2595 return 0x2 2596 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE: 2597 return 0xC 2598 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT: 2599 return 0x4 2600 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE: 2601 return 0x7 2602 case ABLEU: // LE or unordered 2603 return 0xD 2604 case ABLTU: // LT or unordered 2605 return 0x5 2606 case ABVC: 2607 return 0x0 // needs extra instruction 2608 case ABVS: 2609 return 0x1 // unordered 2610 } 2611 c.ctxt.Diag("unknown conditional branch %v", p.As) 2612 return 0xF 2613 } 2614 2615 func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) { 2616 o := c.oplook(p) 2617 2618 switch o.type_ { 2619 default: 2620 c.ctxt.Diag("unknown type %d", o.type_) 2621 2622 case 0: // PSEUDO OPS 2623 break 2624 2625 case 1: // mov reg reg 2626 switch p.As { 2627 default: 2628 c.ctxt.Diag("unhandled operation: %v", p.As) 2629 case AMOVD: 2630 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2631 // sign extend 2632 case AMOVW: 2633 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2634 case AMOVH: 2635 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2636 case AMOVB: 2637 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2638 // zero extend 2639 case AMOVWZ: 2640 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2641 case AMOVHZ: 2642 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2643 case AMOVBZ: 2644 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2645 // reverse bytes 2646 case AMOVDBR: 2647 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2648 case AMOVWBR: 2649 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2650 // floating point 2651 case AFMOVD, AFMOVS: 2652 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2653 } 2654 2655 case 2: // arithmetic op reg [reg] reg 2656 r := p.Reg 2657 if r == 0 { 2658 r = p.To.Reg 2659 } 2660 2661 var opcode uint32 2662 2663 switch p.As { 2664 default: 2665 c.ctxt.Diag("invalid opcode") 2666 case AADD: 2667 opcode = op_AGRK 2668 case AADDC: 2669 opcode = op_ALGRK 2670 case AADDE: 2671 opcode = op_ALCGR 2672 case AADDW: 2673 opcode = op_ARK 2674 case AMULLW: 2675 opcode = op_MSGFR 2676 case AMULLD: 2677 opcode = op_MSGR 2678 case ADIVW, AMODW: 2679 opcode = op_DSGFR 2680 case ADIVWU, AMODWU: 2681 opcode = op_DLR 2682 case ADIVD, AMODD: 2683 opcode = op_DSGR 2684 case ADIVDU, AMODDU: 2685 opcode = op_DLGR 2686 } 2687 2688 switch p.As { 2689 default: 2690 2691 case AADD, AADDC, AADDW: 2692 if p.As == AADDW && r == p.To.Reg { 2693 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2694 } else { 2695 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2696 } 2697 2698 case AADDE, AMULLW, AMULLD: 2699 if r == p.To.Reg { 2700 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2701 } else if p.From.Reg == p.To.Reg { 2702 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2703 } else { 2704 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2705 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2706 } 2707 2708 case ADIVW, ADIVWU, ADIVD, ADIVDU: 2709 if p.As == ADIVWU || p.As == ADIVDU { 2710 zRI(op_LGHI, REGTMP, 0, asm) 2711 } 2712 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2713 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2714 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm) 2715 2716 case AMODW, AMODWU, AMODD, AMODDU: 2717 if p.As == AMODWU || p.As == AMODDU { 2718 zRI(op_LGHI, REGTMP, 0, asm) 2719 } 2720 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2721 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2722 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2723 2724 } 2725 2726 case 3: // mov $constant reg 2727 v := c.vregoff(&p.From) 2728 switch p.As { 2729 case AMOVBZ: 2730 v = int64(uint8(v)) 2731 case AMOVHZ: 2732 v = int64(uint16(v)) 2733 case AMOVWZ: 2734 v = int64(uint32(v)) 2735 case AMOVB: 2736 v = int64(int8(v)) 2737 case AMOVH: 2738 v = int64(int16(v)) 2739 case AMOVW: 2740 v = int64(int32(v)) 2741 } 2742 if int64(int16(v)) == v { 2743 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm) 2744 } else if v&0xffff0000 == v { 2745 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm) 2746 } else if v&0xffff00000000 == v { 2747 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm) 2748 } else if uint64(v)&0xffff000000000000 == uint64(v) { 2749 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm) 2750 } else if int64(int32(v)) == v { 2751 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm) 2752 } else if int64(uint32(v)) == v { 2753 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2754 } else if uint64(v)&0xffffffff00000000 == uint64(v) { 2755 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2756 } else { 2757 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2758 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2759 } 2760 2761 case 4: // multiply high (a*b)>>64 2762 r := p.Reg 2763 if r == 0 { 2764 r = p.To.Reg 2765 } 2766 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2767 zRRE(op_MLGR, REGTMP, uint32(p.From.Reg), asm) 2768 switch p.As { 2769 case AMULHDU: 2770 // Unsigned: move result into correct register. 2771 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2772 case AMULHD: 2773 // Signed: need to convert result. 2774 // See Hacker's Delight 8-3. 2775 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm) 2776 zRRE(op_NGR, REGTMP2, uint32(r), asm) 2777 zRRE(op_SGR, REGTMP, REGTMP2, asm) 2778 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm) 2779 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm) 2780 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), REGTMP, asm) 2781 } 2782 2783 case 5: // syscall 2784 zI(op_SVC, 0, asm) 2785 2786 case 6: // logical op reg [reg] reg 2787 var oprr, oprre, oprrf uint32 2788 switch p.As { 2789 case AAND: 2790 oprre = op_NGR 2791 oprrf = op_NGRK 2792 case AANDW: 2793 oprr = op_NR 2794 oprrf = op_NRK 2795 case AOR: 2796 oprre = op_OGR 2797 oprrf = op_OGRK 2798 case AORW: 2799 oprr = op_OR 2800 oprrf = op_ORK 2801 case AXOR: 2802 oprre = op_XGR 2803 oprrf = op_XGRK 2804 case AXORW: 2805 oprr = op_XR 2806 oprrf = op_XRK 2807 } 2808 if p.Reg == 0 { 2809 if oprr != 0 { 2810 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2811 } else { 2812 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2813 } 2814 } else { 2815 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2816 } 2817 2818 case 7: // shift/rotate reg [reg] reg 2819 d2 := c.vregoff(&p.From) 2820 b2 := p.From.Reg 2821 r3 := p.Reg 2822 if r3 == 0 { 2823 r3 = p.To.Reg 2824 } 2825 r1 := p.To.Reg 2826 var opcode uint32 2827 switch p.As { 2828 default: 2829 case ASLD: 2830 opcode = op_SLLG 2831 case ASRD: 2832 opcode = op_SRLG 2833 case ASLW: 2834 opcode = op_SLLK 2835 case ASRW: 2836 opcode = op_SRLK 2837 case ARLL: 2838 opcode = op_RLL 2839 case ARLLG: 2840 opcode = op_RLLG 2841 case ASRAW: 2842 opcode = op_SRAK 2843 case ASRAD: 2844 opcode = op_SRAG 2845 } 2846 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm) 2847 2848 case 8: // find leftmost one 2849 if p.To.Reg&1 != 0 { 2850 c.ctxt.Diag("target must be an even-numbered register") 2851 } 2852 // FLOGR also writes a mask to p.To.Reg+1. 2853 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2854 2855 case 9: // population count 2856 zRRE(op_POPCNT, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2857 2858 case 10: // subtract reg [reg] reg 2859 r := int(p.Reg) 2860 2861 switch p.As { 2862 default: 2863 case ASUB: 2864 if r == 0 { 2865 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2866 } else { 2867 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2868 } 2869 case ASUBC: 2870 if r == 0 { 2871 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2872 } else { 2873 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2874 } 2875 case ASUBE: 2876 if r == 0 { 2877 r = int(p.To.Reg) 2878 } 2879 if r == int(p.To.Reg) { 2880 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2881 } else if p.From.Reg == p.To.Reg { 2882 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 2883 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2884 zRRE(op_SLBGR, uint32(p.To.Reg), REGTMP, asm) 2885 } else { 2886 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2887 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2888 } 2889 case ASUBW: 2890 if r == 0 { 2891 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2892 } else { 2893 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2894 } 2895 } 2896 2897 case 11: // br/bl 2898 v := int32(0) 2899 2900 if p.Pcond != nil { 2901 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2902 } 2903 2904 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v { 2905 zRI(op_BRC, 0xF, uint32(v), asm) 2906 } else { 2907 if p.As == ABL { 2908 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm) 2909 } else { 2910 zRIL(_c, op_BRCL, 0xF, uint32(v), asm) 2911 } 2912 if p.To.Sym != nil { 2913 c.addcallreloc(p.To.Sym, p.To.Offset) 2914 } 2915 } 2916 2917 case 12: 2918 r1 := p.To.Reg 2919 d2 := c.vregoff(&p.From) 2920 b2 := p.From.Reg 2921 if b2 == 0 { 2922 b2 = o.param 2923 } 2924 x2 := p.From.Index 2925 if -DISP20/2 > d2 || d2 >= DISP20/2 { 2926 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 2927 if x2 != 0 { 2928 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 2929 } 2930 x2 = REGTMP 2931 d2 = 0 2932 } 2933 var opx, opxy uint32 2934 switch p.As { 2935 case AADD: 2936 opxy = op_AG 2937 case AADDC: 2938 opxy = op_ALG 2939 case AADDW: 2940 opx = op_A 2941 opxy = op_AY 2942 case AMULLW: 2943 opx = op_MS 2944 opxy = op_MSY 2945 case AMULLD: 2946 opxy = op_MSG 2947 case ASUB: 2948 opxy = op_SG 2949 case ASUBC: 2950 opxy = op_SLG 2951 case ASUBE: 2952 opxy = op_SLBG 2953 case ASUBW: 2954 opx = op_S 2955 opxy = op_SY 2956 case AAND: 2957 opxy = op_NG 2958 case AANDW: 2959 opx = op_N 2960 opxy = op_NY 2961 case AOR: 2962 opxy = op_OG 2963 case AORW: 2964 opx = op_O 2965 opxy = op_OY 2966 case AXOR: 2967 opxy = op_XG 2968 case AXORW: 2969 opx = op_X 2970 opxy = op_XY 2971 } 2972 if opx != 0 && 0 <= d2 && d2 < DISP12 { 2973 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 2974 } else { 2975 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 2976 } 2977 2978 case 15: // br/bl (reg) 2979 r := p.To.Reg 2980 if p.As == ABCL || p.As == ABL { 2981 zRR(op_BASR, uint32(REG_LR), uint32(r), asm) 2982 } else { 2983 zRR(op_BCR, 0xF, uint32(r), asm) 2984 } 2985 2986 case 16: // conditional branch 2987 v := int32(0) 2988 if p.Pcond != nil { 2989 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2990 } 2991 mask := c.branchMask(p) 2992 if p.To.Sym == nil && int32(int16(v)) == v { 2993 zRI(op_BRC, mask, uint32(v), asm) 2994 } else { 2995 zRIL(_c, op_BRCL, mask, uint32(v), asm) 2996 } 2997 if p.To.Sym != nil { 2998 c.addrilreloc(p.To.Sym, p.To.Offset) 2999 } 3000 3001 case 17: // move on condition 3002 m3 := c.branchMask(p) 3003 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3004 3005 case 18: // br/bl reg 3006 if p.As == ABL { 3007 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm) 3008 } else { 3009 zRR(op_BCR, 0xF, uint32(p.To.Reg), asm) 3010 } 3011 3012 case 19: // mov $sym+n(SB) reg 3013 d := c.vregoff(&p.From) 3014 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm) 3015 if d&1 != 0 { 3016 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm) 3017 d -= 1 3018 } 3019 c.addrilreloc(p.From.Sym, d) 3020 3021 case 21: // subtract $constant [reg] reg 3022 v := c.vregoff(&p.From) 3023 r := p.Reg 3024 if r == 0 { 3025 r = p.To.Reg 3026 } 3027 switch p.As { 3028 case ASUB: 3029 zRIL(_a, op_LGFI, uint32(REGTMP), uint32(v), asm) 3030 zRRF(op_SLGRK, uint32(REGTMP), 0, uint32(p.To.Reg), uint32(r), asm) 3031 case ASUBC: 3032 if r != p.To.Reg { 3033 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3034 } 3035 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm) 3036 case ASUBW: 3037 if r != p.To.Reg { 3038 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3039 } 3040 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm) 3041 } 3042 3043 case 22: // add/multiply $constant [reg] reg 3044 v := c.vregoff(&p.From) 3045 r := p.Reg 3046 if r == 0 { 3047 r = p.To.Reg 3048 } 3049 var opri, opril, oprie uint32 3050 switch p.As { 3051 case AADD: 3052 opri = op_AGHI 3053 opril = op_AGFI 3054 oprie = op_AGHIK 3055 case AADDC: 3056 opril = op_ALGFI 3057 oprie = op_ALGHSIK 3058 case AADDW: 3059 opri = op_AHI 3060 opril = op_AFI 3061 oprie = op_AHIK 3062 case AMULLW: 3063 opri = op_MHI 3064 opril = op_MSFI 3065 case AMULLD: 3066 opri = op_MGHI 3067 opril = op_MSGFI 3068 } 3069 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) { 3070 switch p.As { 3071 case AADD, AADDC, AMULLD: 3072 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3073 case AADDW, AMULLW: 3074 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3075 } 3076 r = p.To.Reg 3077 } 3078 if r == p.To.Reg { 3079 if opri != 0 && int64(int16(v)) == v { 3080 zRI(opri, uint32(p.To.Reg), uint32(v), asm) 3081 } else { 3082 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm) 3083 } 3084 } else { 3085 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm) 3086 } 3087 3088 case 23: // 64-bit logical op $constant reg 3089 // TODO(mundaym): merge with case 24. 3090 v := c.vregoff(&p.From) 3091 switch p.As { 3092 default: 3093 c.ctxt.Diag("%v is not supported", p) 3094 case AAND: 3095 if v >= 0 { // needs zero extend 3096 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3097 zRRE(op_NGR, uint32(p.To.Reg), REGTMP, asm) 3098 } else if int64(int16(v)) == v { 3099 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3100 } else { // r.To.Reg & 0xffffffff00000000 & uint32(v) 3101 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3102 } 3103 case AOR: 3104 if int64(uint32(v)) != v { // needs sign extend 3105 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3106 zRRE(op_OGR, uint32(p.To.Reg), REGTMP, asm) 3107 } else if int64(uint16(v)) == v { 3108 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3109 } else { 3110 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3111 } 3112 case AXOR: 3113 if int64(uint32(v)) != v { // needs sign extend 3114 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3115 zRRE(op_XGR, uint32(p.To.Reg), REGTMP, asm) 3116 } else { 3117 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3118 } 3119 } 3120 3121 case 24: // 32-bit logical op $constant reg 3122 v := c.vregoff(&p.From) 3123 switch p.As { 3124 case AANDW: 3125 if uint32(v&0xffff0000) == 0xffff0000 { 3126 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3127 } else if uint32(v&0x0000ffff) == 0x0000ffff { 3128 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3129 } else { 3130 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3131 } 3132 case AORW: 3133 if uint32(v&0xffff0000) == 0 { 3134 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3135 } else if uint32(v&0x0000ffff) == 0 { 3136 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3137 } else { 3138 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3139 } 3140 case AXORW: 3141 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3142 } 3143 3144 case 26: // MOVD $offset(base)(index), reg 3145 v := c.regoff(&p.From) 3146 r := p.From.Reg 3147 if r == 0 { 3148 r = o.param 3149 } 3150 i := p.From.Index 3151 if v >= 0 && v < DISP12 { 3152 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3153 } else if v >= -DISP20/2 && v < DISP20/2 { 3154 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3155 } else { 3156 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3157 zRX(op_LA, uint32(p.To.Reg), uint32(r), REGTMP, uint32(i), asm) 3158 } 3159 3160 case 31: // dword 3161 wd := uint64(c.vregoff(&p.From)) 3162 *asm = append(*asm, 3163 uint8(wd>>56), 3164 uint8(wd>>48), 3165 uint8(wd>>40), 3166 uint8(wd>>32), 3167 uint8(wd>>24), 3168 uint8(wd>>16), 3169 uint8(wd>>8), 3170 uint8(wd)) 3171 3172 case 32: // float op freg freg 3173 var opcode uint32 3174 switch p.As { 3175 default: 3176 c.ctxt.Diag("invalid opcode") 3177 case AFADD: 3178 opcode = op_ADBR 3179 case AFADDS: 3180 opcode = op_AEBR 3181 case AFDIV: 3182 opcode = op_DDBR 3183 case AFDIVS: 3184 opcode = op_DEBR 3185 case AFMUL: 3186 opcode = op_MDBR 3187 case AFMULS: 3188 opcode = op_MEEBR 3189 case AFSUB: 3190 opcode = op_SDBR 3191 case AFSUBS: 3192 opcode = op_SEBR 3193 } 3194 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3195 3196 case 33: // float op [freg] freg 3197 r := p.From.Reg 3198 if oclass(&p.From) == C_NONE { 3199 r = p.To.Reg 3200 } 3201 var opcode uint32 3202 switch p.As { 3203 default: 3204 case AFABS: 3205 opcode = op_LPDBR 3206 case AFNABS: 3207 opcode = op_LNDBR 3208 case ALPDFR: 3209 opcode = op_LPDFR 3210 case ALNDFR: 3211 opcode = op_LNDFR 3212 case AFNEG: 3213 opcode = op_LCDFR 3214 case AFNEGS: 3215 opcode = op_LCEBR 3216 case ALEDBR: 3217 opcode = op_LEDBR 3218 case ALDEBR: 3219 opcode = op_LDEBR 3220 case AFSQRT: 3221 opcode = op_SQDBR 3222 case AFSQRTS: 3223 opcode = op_SQEBR 3224 } 3225 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3226 3227 case 34: // float multiply-add freg freg freg 3228 var opcode uint32 3229 switch p.As { 3230 default: 3231 c.ctxt.Diag("invalid opcode") 3232 case AFMADD: 3233 opcode = op_MADBR 3234 case AFMADDS: 3235 opcode = op_MAEBR 3236 case AFMSUB: 3237 opcode = op_MSDBR 3238 case AFMSUBS: 3239 opcode = op_MSEBR 3240 } 3241 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 3242 3243 case 35: // mov reg mem (no relocation) 3244 d2 := c.regoff(&p.To) 3245 b2 := p.To.Reg 3246 if b2 == 0 { 3247 b2 = o.param 3248 } 3249 x2 := p.To.Index 3250 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3251 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3252 if x2 != 0 { 3253 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3254 } 3255 x2 = REGTMP 3256 d2 = 0 3257 } 3258 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3259 3260 case 36: // mov mem reg (no relocation) 3261 d2 := c.regoff(&p.From) 3262 b2 := p.From.Reg 3263 if b2 == 0 { 3264 b2 = o.param 3265 } 3266 x2 := p.From.Index 3267 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3268 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3269 if x2 != 0 { 3270 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3271 } 3272 x2 = REGTMP 3273 d2 = 0 3274 } 3275 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3276 3277 case 40: // word/byte 3278 wd := uint32(c.regoff(&p.From)) 3279 if p.As == AWORD { //WORD 3280 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd)) 3281 } else { //BYTE 3282 *asm = append(*asm, uint8(wd)) 3283 } 3284 3285 case 47: // negate [reg] reg 3286 r := p.From.Reg 3287 if r == 0 { 3288 r = p.To.Reg 3289 } 3290 switch p.As { 3291 case ANEG: 3292 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm) 3293 case ANEGW: 3294 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm) 3295 } 3296 3297 case 48: // floating-point round to integer 3298 m3 := c.vregoff(&p.From) 3299 if 0 > m3 || m3 > 7 { 3300 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3) 3301 } 3302 var opcode uint32 3303 switch p.As { 3304 case AFIEBR: 3305 opcode = op_FIEBR 3306 case AFIDBR: 3307 opcode = op_FIDBR 3308 } 3309 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3310 3311 case 49: // copysign 3312 zRRF(op_CPSDR, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3313 3314 case 50: // load and test 3315 var opcode uint32 3316 switch p.As { 3317 case ALTEBR: 3318 opcode = op_LTEBR 3319 case ALTDBR: 3320 opcode = op_LTDBR 3321 } 3322 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3323 3324 case 51: // test data class (immediate only) 3325 var opcode uint32 3326 switch p.As { 3327 case ATCEB: 3328 opcode = op_TCEB 3329 case ATCDB: 3330 opcode = op_TCDB 3331 } 3332 d2 := c.regoff(&p.To) 3333 zRXE(opcode, uint32(p.From.Reg), 0, 0, uint32(d2), 0, asm) 3334 3335 case 67: // fmov $0 freg 3336 var opcode uint32 3337 switch p.As { 3338 case AFMOVS: 3339 opcode = op_LZER 3340 case AFMOVD: 3341 opcode = op_LZDR 3342 } 3343 zRRE(opcode, uint32(p.To.Reg), 0, asm) 3344 3345 case 68: // movw areg reg 3346 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm) 3347 3348 case 69: // movw reg areg 3349 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm) 3350 3351 case 70: // cmp reg reg 3352 if p.As == ACMPW || p.As == ACMPWU { 3353 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3354 } else { 3355 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3356 } 3357 3358 case 71: // cmp reg $constant 3359 v := c.vregoff(&p.To) 3360 switch p.As { 3361 case ACMP, ACMPW: 3362 if int64(int32(v)) != v { 3363 c.ctxt.Diag("%v overflows an int32", v) 3364 } 3365 case ACMPU, ACMPWU: 3366 if int64(uint32(v)) != v { 3367 c.ctxt.Diag("%v overflows a uint32", v) 3368 } 3369 } 3370 if p.As == ACMP && int64(int16(v)) == v { 3371 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm) 3372 } else if p.As == ACMPW && int64(int16(v)) == v { 3373 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm) 3374 } else { 3375 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm) 3376 } 3377 3378 case 72: // mov $constant mem 3379 v := c.regoff(&p.From) 3380 d := c.regoff(&p.To) 3381 r := p.To.Reg 3382 if p.To.Index != 0 { 3383 c.ctxt.Diag("cannot use index register") 3384 } 3385 if r == 0 { 3386 r = o.param 3387 } 3388 var opcode uint32 3389 switch p.As { 3390 case AMOVD: 3391 opcode = op_MVGHI 3392 case AMOVW, AMOVWZ: 3393 opcode = op_MVHI 3394 case AMOVH, AMOVHZ: 3395 opcode = op_MVHHI 3396 case AMOVB, AMOVBZ: 3397 opcode = op_MVI 3398 } 3399 if d < 0 || d >= DISP12 { 3400 if r == REGTMP { 3401 c.ctxt.Diag("displacement must be in range [0, 4096) to use %v", r) 3402 } 3403 if d >= -DISP20/2 && d < DISP20/2 { 3404 if opcode == op_MVI { 3405 opcode = op_MVIY 3406 } else { 3407 zRXY(op_LAY, uint32(REGTMP), 0, uint32(r), uint32(d), asm) 3408 r = REGTMP 3409 d = 0 3410 } 3411 } else { 3412 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm) 3413 zRX(op_LA, REGTMP, REGTMP, uint32(r), 0, asm) 3414 r = REGTMP 3415 d = 0 3416 } 3417 } 3418 switch opcode { 3419 case op_MVI: 3420 zSI(opcode, uint32(v), uint32(r), uint32(d), asm) 3421 case op_MVIY: 3422 zSIY(opcode, uint32(v), uint32(r), uint32(d), asm) 3423 default: 3424 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm) 3425 } 3426 3427 case 74: // mov reg addr (including relocation) 3428 i2 := c.regoff(&p.To) 3429 switch p.As { 3430 case AMOVD: 3431 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm) 3432 case AMOVW, AMOVWZ: // The zero extension doesn't affect store instructions 3433 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm) 3434 case AMOVH, AMOVHZ: // The zero extension doesn't affect store instructions 3435 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm) 3436 case AMOVB, AMOVBZ: // The zero extension doesn't affect store instructions 3437 zRIL(_b, op_LARL, REGTMP, 0, asm) 3438 adj := uint32(0) // adjustment needed for odd addresses 3439 if i2&1 != 0 { 3440 i2 -= 1 3441 adj = 1 3442 } 3443 zRX(op_STC, uint32(p.From.Reg), 0, REGTMP, adj, asm) 3444 case AFMOVD: 3445 zRIL(_b, op_LARL, REGTMP, 0, asm) 3446 zRX(op_STD, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3447 case AFMOVS: 3448 zRIL(_b, op_LARL, REGTMP, 0, asm) 3449 zRX(op_STE, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3450 } 3451 c.addrilreloc(p.To.Sym, int64(i2)) 3452 3453 case 75: // mov addr reg (including relocation) 3454 i2 := c.regoff(&p.From) 3455 switch p.As { 3456 case AMOVD: 3457 if i2&1 != 0 { 3458 zRIL(_b, op_LARL, REGTMP, 0, asm) 3459 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 1, asm) 3460 i2 -= 1 3461 } else { 3462 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3463 } 3464 case AMOVW: 3465 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm) 3466 case AMOVWZ: 3467 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm) 3468 case AMOVH: 3469 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm) 3470 case AMOVHZ: 3471 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm) 3472 case AMOVB, AMOVBZ: 3473 zRIL(_b, op_LARL, REGTMP, 0, asm) 3474 adj := uint32(0) // adjustment needed for odd addresses 3475 if i2&1 != 0 { 3476 i2 -= 1 3477 adj = 1 3478 } 3479 switch p.As { 3480 case AMOVB: 3481 zRXY(op_LGB, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3482 case AMOVBZ: 3483 zRXY(op_LLGC, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3484 } 3485 case AFMOVD: 3486 zRIL(_a, op_LARL, REGTMP, 0, asm) 3487 zRX(op_LD, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3488 case AFMOVS: 3489 zRIL(_a, op_LARL, REGTMP, 0, asm) 3490 zRX(op_LE, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3491 } 3492 c.addrilreloc(p.From.Sym, int64(i2)) 3493 3494 case 77: // syscall $constant 3495 if p.From.Offset > 255 || p.From.Offset < 1 { 3496 c.ctxt.Diag("illegal system call; system call number out of range: %v", p) 3497 zE(op_TRAP2, asm) // trap always 3498 } else { 3499 zI(op_SVC, uint32(p.From.Offset), asm) 3500 } 3501 3502 case 78: // undef 3503 // "An instruction consisting entirely of binary 0s is guaranteed 3504 // always to be an illegal instruction." 3505 *asm = append(*asm, 0, 0, 0, 0) 3506 3507 case 79: // compare and swap reg reg reg 3508 v := c.regoff(&p.To) 3509 if v < 0 { 3510 v = 0 3511 } 3512 if p.As == ACS { 3513 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3514 } else if p.As == ACSG { 3515 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3516 } 3517 3518 case 80: // sync 3519 zRR(op_BCR, 0xE, 0, asm) 3520 3521 case 81: // float to fixed and fixed to float moves (no conversion) 3522 switch p.As { 3523 case ALDGR: 3524 zRRE(op_LDGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3525 case ALGDR: 3526 zRRE(op_LGDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3527 } 3528 3529 case 82: // fixed to float conversion 3530 var opcode uint32 3531 switch p.As { 3532 default: 3533 log.Fatalf("unexpected opcode %v", p.As) 3534 case ACEFBRA: 3535 opcode = op_CEFBRA 3536 case ACDFBRA: 3537 opcode = op_CDFBRA 3538 case ACEGBRA: 3539 opcode = op_CEGBRA 3540 case ACDGBRA: 3541 opcode = op_CDGBRA 3542 case ACELFBR: 3543 opcode = op_CELFBR 3544 case ACDLFBR: 3545 opcode = op_CDLFBR 3546 case ACELGBR: 3547 opcode = op_CELGBR 3548 case ACDLGBR: 3549 opcode = op_CDLGBR 3550 } 3551 // set immediate operand M3 to 0 to use the default BFP rounding mode 3552 // (usually round to nearest, ties to even) 3553 // TODO(mundaym): should this be fixed at round to nearest, ties to even? 3554 // M4 is reserved and must be 0 3555 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3556 3557 case 83: // float to fixed conversion 3558 var opcode uint32 3559 switch p.As { 3560 default: 3561 log.Fatalf("unexpected opcode %v", p.As) 3562 case ACFEBRA: 3563 opcode = op_CFEBRA 3564 case ACFDBRA: 3565 opcode = op_CFDBRA 3566 case ACGEBRA: 3567 opcode = op_CGEBRA 3568 case ACGDBRA: 3569 opcode = op_CGDBRA 3570 case ACLFEBR: 3571 opcode = op_CLFEBR 3572 case ACLFDBR: 3573 opcode = op_CLFDBR 3574 case ACLGEBR: 3575 opcode = op_CLGEBR 3576 case ACLGDBR: 3577 opcode = op_CLGDBR 3578 } 3579 // set immediate operand M3 to 5 for rounding toward zero (required by Go spec) 3580 // M4 is reserved and must be 0 3581 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3582 3583 case 84: // storage-and-storage operations $length mem mem 3584 l := c.regoff(&p.From) 3585 if l < 1 || l > 256 { 3586 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l) 3587 } 3588 if p.GetFrom3().Index != 0 || p.To.Index != 0 { 3589 c.ctxt.Diag("cannot use index reg") 3590 } 3591 b1 := p.To.Reg 3592 b2 := p.GetFrom3().Reg 3593 if b1 == 0 { 3594 b1 = o.param 3595 } 3596 if b2 == 0 { 3597 b2 = o.param 3598 } 3599 d1 := c.regoff(&p.To) 3600 d2 := c.regoff(p.GetFrom3()) 3601 if d1 < 0 || d1 >= DISP12 { 3602 if b2 == REGTMP { 3603 c.ctxt.Diag("REGTMP conflict") 3604 } 3605 if b1 != REGTMP { 3606 zRRE(op_LGR, REGTMP, uint32(b1), asm) 3607 } 3608 zRIL(_a, op_AGFI, REGTMP, uint32(d1), asm) 3609 if d1 == d2 && b1 == b2 { 3610 d2 = 0 3611 b2 = REGTMP 3612 } 3613 d1 = 0 3614 b1 = REGTMP 3615 } 3616 if d2 < 0 || d2 >= DISP12 { 3617 if b1 == REGTMP2 { 3618 c.ctxt.Diag("REGTMP2 conflict") 3619 } 3620 if b2 != REGTMP2 { 3621 zRRE(op_LGR, REGTMP2, uint32(b2), asm) 3622 } 3623 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm) 3624 d2 = 0 3625 b2 = REGTMP2 3626 } 3627 var opcode uint32 3628 switch p.As { 3629 default: 3630 c.ctxt.Diag("unexpected opcode %v", p.As) 3631 case AMVC: 3632 opcode = op_MVC 3633 case ACLC: 3634 opcode = op_CLC 3635 // swap operand order for CLC so that it matches CMP 3636 b1, b2 = b2, b1 3637 d1, d2 = d2, d1 3638 case AXC: 3639 opcode = op_XC 3640 case AOC: 3641 opcode = op_OC 3642 case ANC: 3643 opcode = op_NC 3644 } 3645 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm) 3646 3647 case 85: // load address relative long 3648 v := c.regoff(&p.From) 3649 if p.From.Sym == nil { 3650 if (v & 1) != 0 { 3651 c.ctxt.Diag("cannot use LARL with odd offset: %v", v) 3652 } 3653 } else { 3654 c.addrilreloc(p.From.Sym, int64(v)) 3655 v = 0 3656 } 3657 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm) 3658 3659 case 86: // load address 3660 d := c.vregoff(&p.From) 3661 x := p.From.Index 3662 b := p.From.Reg 3663 if b == 0 { 3664 b = o.param 3665 } 3666 switch p.As { 3667 case ALA: 3668 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3669 case ALAY: 3670 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3671 } 3672 3673 case 87: // execute relative long 3674 v := c.vregoff(&p.From) 3675 if p.From.Sym == nil { 3676 if v&1 != 0 { 3677 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v) 3678 } 3679 } else { 3680 c.addrilreloc(p.From.Sym, v) 3681 v = 0 3682 } 3683 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm) 3684 3685 case 88: // store clock 3686 var opcode uint32 3687 switch p.As { 3688 case ASTCK: 3689 opcode = op_STCK 3690 case ASTCKC: 3691 opcode = op_STCKC 3692 case ASTCKE: 3693 opcode = op_STCKE 3694 case ASTCKF: 3695 opcode = op_STCKF 3696 } 3697 v := c.vregoff(&p.To) 3698 r := int(p.To.Reg) 3699 if r == 0 { 3700 r = int(o.param) 3701 } 3702 zS(opcode, uint32(r), uint32(v), asm) 3703 3704 case 89: // compare and branch reg reg 3705 var v int32 3706 if p.Pcond != nil { 3707 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3708 } 3709 var opcode, opcode2 uint32 3710 switch p.As { 3711 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3712 opcode = op_CGRJ 3713 opcode2 = op_CGR 3714 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3715 opcode = op_CLGRJ 3716 opcode2 = op_CLGR 3717 } 3718 mask := c.branchMask(p) 3719 if int32(int16(v)) != v { 3720 zRRE(opcode2, uint32(p.From.Reg), uint32(p.Reg), asm) 3721 zRIL(_c, op_BRCL, mask, uint32(v-sizeRRE/2), asm) 3722 } else { 3723 zRIE(_b, opcode, uint32(p.From.Reg), uint32(p.Reg), uint32(v), 0, 0, mask, 0, asm) 3724 } 3725 3726 case 90: // compare and branch reg $constant 3727 var v int32 3728 if p.Pcond != nil { 3729 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3730 } 3731 var opcode, opcode2 uint32 3732 switch p.As { 3733 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3734 opcode = op_CGIJ 3735 opcode2 = op_CGFI 3736 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3737 opcode = op_CLGIJ 3738 opcode2 = op_CLGFI 3739 } 3740 mask := c.branchMask(p) 3741 if int32(int16(v)) != v { 3742 zRIL(_a, opcode2, uint32(p.From.Reg), uint32(c.regoff(p.GetFrom3())), asm) 3743 zRIL(_c, op_BRCL, mask, uint32(v-sizeRIL/2), asm) 3744 } else { 3745 zRIE(_c, opcode, uint32(p.From.Reg), mask, uint32(v), 0, 0, 0, uint32(c.regoff(p.GetFrom3())), asm) 3746 } 3747 3748 case 91: // test under mask (immediate) 3749 var opcode uint32 3750 switch p.As { 3751 case ATMHH: 3752 opcode = op_TMHH 3753 case ATMHL: 3754 opcode = op_TMHL 3755 case ATMLH: 3756 opcode = op_TMLH 3757 case ATMLL: 3758 opcode = op_TMLL 3759 } 3760 zRI(opcode, uint32(p.From.Reg), uint32(c.vregoff(&p.To)), asm) 3761 3762 case 93: // GOT lookup 3763 v := c.vregoff(&p.To) 3764 if v != 0 { 3765 c.ctxt.Diag("invalid offset against GOT slot %v", p) 3766 } 3767 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3768 rel := obj.Addrel(c.cursym) 3769 rel.Off = int32(c.pc + 2) 3770 rel.Siz = 4 3771 rel.Sym = p.From.Sym 3772 rel.Type = objabi.R_GOTPCREL 3773 rel.Add = 2 + int64(rel.Siz) 3774 3775 case 94: // TLS local exec model 3776 zRIL(_b, op_LARL, REGTMP, (sizeRIL+sizeRXY+sizeRI)>>1, asm) 3777 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3778 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm) 3779 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0) 3780 rel := obj.Addrel(c.cursym) 3781 rel.Off = int32(c.pc + sizeRIL + sizeRXY + sizeRI) 3782 rel.Siz = 8 3783 rel.Sym = p.From.Sym 3784 rel.Type = objabi.R_TLS_LE 3785 rel.Add = 0 3786 3787 case 95: // TLS initial exec model 3788 // Assembly | Relocation symbol | Done Here? 3789 // -------------------------------------------------------------- 3790 // ear %r11, %a0 | | 3791 // sllg %r11, %r11, 32 | | 3792 // ear %r11, %a1 | | 3793 // larl %r10, <var>@indntpoff | R_390_TLS_IEENT | Y 3794 // lg %r10, 0(%r10) | R_390_TLS_LOAD (tag) | Y 3795 // la %r10, 0(%r10, %r11) | | 3796 // -------------------------------------------------------------- 3797 3798 // R_390_TLS_IEENT 3799 zRIL(_b, op_LARL, REGTMP, 0, asm) 3800 ieent := obj.Addrel(c.cursym) 3801 ieent.Off = int32(c.pc + 2) 3802 ieent.Siz = 4 3803 ieent.Sym = p.From.Sym 3804 ieent.Type = objabi.R_TLS_IE 3805 ieent.Add = 2 + int64(ieent.Siz) 3806 3807 // R_390_TLS_LOAD 3808 zRXY(op_LGF, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3809 // TODO(mundaym): add R_390_TLS_LOAD relocation here 3810 // not strictly required but might allow the linker to optimize 3811 3812 case 96: // clear macro 3813 length := c.vregoff(&p.From) 3814 offset := c.vregoff(&p.To) 3815 reg := p.To.Reg 3816 if reg == 0 { 3817 reg = o.param 3818 } 3819 if length <= 0 { 3820 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length) 3821 } 3822 for length > 0 { 3823 if offset < 0 || offset >= DISP12 { 3824 if offset >= -DISP20/2 && offset < DISP20/2 { 3825 zRXY(op_LAY, REGTMP, uint32(reg), 0, uint32(offset), asm) 3826 } else { 3827 if reg != REGTMP { 3828 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3829 } 3830 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3831 } 3832 reg = REGTMP 3833 offset = 0 3834 } 3835 size := length 3836 if size > 256 { 3837 size = 256 3838 } 3839 3840 switch size { 3841 case 1: 3842 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm) 3843 case 2: 3844 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm) 3845 case 4: 3846 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm) 3847 case 8: 3848 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm) 3849 default: 3850 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm) 3851 } 3852 3853 length -= size 3854 offset += size 3855 } 3856 3857 case 97: // store multiple 3858 rstart := p.From.Reg 3859 rend := p.Reg 3860 offset := c.regoff(&p.To) 3861 reg := p.To.Reg 3862 if reg == 0 { 3863 reg = o.param 3864 } 3865 if offset < -DISP20/2 || offset >= DISP20/2 { 3866 if reg != REGTMP { 3867 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3868 } 3869 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3870 reg = REGTMP 3871 offset = 0 3872 } 3873 switch p.As { 3874 case ASTMY: 3875 if offset >= 0 && offset < DISP12 { 3876 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3877 } else { 3878 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3879 } 3880 case ASTMG: 3881 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3882 } 3883 3884 case 98: // load multiple 3885 rstart := p.Reg 3886 rend := p.To.Reg 3887 offset := c.regoff(&p.From) 3888 reg := p.From.Reg 3889 if reg == 0 { 3890 reg = o.param 3891 } 3892 if offset < -DISP20/2 || offset >= DISP20/2 { 3893 if reg != REGTMP { 3894 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3895 } 3896 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3897 reg = REGTMP 3898 offset = 0 3899 } 3900 switch p.As { 3901 case ALMY: 3902 if offset >= 0 && offset < DISP12 { 3903 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3904 } else { 3905 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3906 } 3907 case ALMG: 3908 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3909 } 3910 3911 case 99: // interlocked load and op 3912 if p.To.Index != 0 { 3913 c.ctxt.Diag("cannot use indexed address") 3914 } 3915 offset := c.regoff(&p.To) 3916 if offset < -DISP20/2 || offset >= DISP20/2 { 3917 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset) 3918 } 3919 var opcode uint32 3920 switch p.As { 3921 case ALAA: 3922 opcode = op_LAA 3923 case ALAAG: 3924 opcode = op_LAAG 3925 case ALAAL: 3926 opcode = op_LAAL 3927 case ALAALG: 3928 opcode = op_LAALG 3929 case ALAN: 3930 opcode = op_LAN 3931 case ALANG: 3932 opcode = op_LANG 3933 case ALAX: 3934 opcode = op_LAX 3935 case ALAXG: 3936 opcode = op_LAXG 3937 case ALAO: 3938 opcode = op_LAO 3939 case ALAOG: 3940 opcode = op_LAOG 3941 } 3942 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm) 3943 3944 case 100: // VRX STORE 3945 op, m3, _ := vop(p.As) 3946 v1 := p.From.Reg 3947 if p.Reg != 0 { 3948 m3 = uint32(c.vregoff(&p.From)) 3949 v1 = p.Reg 3950 } 3951 b2 := p.To.Reg 3952 if b2 == 0 { 3953 b2 = o.param 3954 } 3955 d2 := uint32(c.vregoff(&p.To)) 3956 zVRX(op, uint32(v1), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3957 3958 case 101: // VRX LOAD 3959 op, m3, _ := vop(p.As) 3960 src := &p.From 3961 if p.GetFrom3() != nil { 3962 m3 = uint32(c.vregoff(&p.From)) 3963 src = p.GetFrom3() 3964 } 3965 b2 := src.Reg 3966 if b2 == 0 { 3967 b2 = o.param 3968 } 3969 d2 := uint32(c.vregoff(src)) 3970 zVRX(op, uint32(p.To.Reg), uint32(src.Index), uint32(b2), d2, m3, asm) 3971 3972 case 102: // VRV SCATTER 3973 op, _, _ := vop(p.As) 3974 m3 := uint32(c.vregoff(&p.From)) 3975 b2 := p.To.Reg 3976 if b2 == 0 { 3977 b2 = o.param 3978 } 3979 d2 := uint32(c.vregoff(&p.To)) 3980 zVRV(op, uint32(p.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3981 3982 case 103: // VRV GATHER 3983 op, _, _ := vop(p.As) 3984 m3 := uint32(c.vregoff(&p.From)) 3985 b2 := p.GetFrom3().Reg 3986 if b2 == 0 { 3987 b2 = o.param 3988 } 3989 d2 := uint32(c.vregoff(p.GetFrom3())) 3990 zVRV(op, uint32(p.To.Reg), uint32(p.GetFrom3().Index), uint32(b2), d2, m3, asm) 3991 3992 case 104: // VRS SHIFT/ROTATE and LOAD GR FROM VR ELEMENT 3993 op, m4, _ := vop(p.As) 3994 fr := p.Reg 3995 if fr == 0 { 3996 fr = p.To.Reg 3997 } 3998 bits := uint32(c.vregoff(&p.From)) 3999 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm) 4000 4001 case 105: // VRS STORE MULTIPLE 4002 op, _, _ := vop(p.As) 4003 offset := uint32(c.vregoff(&p.To)) 4004 reg := p.To.Reg 4005 if reg == 0 { 4006 reg = o.param 4007 } 4008 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm) 4009 4010 case 106: // VRS LOAD MULTIPLE 4011 op, _, _ := vop(p.As) 4012 offset := uint32(c.vregoff(&p.From)) 4013 reg := p.From.Reg 4014 if reg == 0 { 4015 reg = o.param 4016 } 4017 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm) 4018 4019 case 107: // VRS STORE WITH LENGTH 4020 op, _, _ := vop(p.As) 4021 offset := uint32(c.vregoff(&p.To)) 4022 reg := p.To.Reg 4023 if reg == 0 { 4024 reg = o.param 4025 } 4026 zVRS(op, uint32(p.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 4027 4028 case 108: // VRS LOAD WITH LENGTH 4029 op, _, _ := vop(p.As) 4030 offset := uint32(c.vregoff(p.GetFrom3())) 4031 reg := p.GetFrom3().Reg 4032 if reg == 0 { 4033 reg = o.param 4034 } 4035 zVRS(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 4036 4037 case 109: // VRI-a 4038 op, m3, _ := vop(p.As) 4039 i2 := uint32(c.vregoff(&p.From)) 4040 if p.GetFrom3() != nil { 4041 m3 = uint32(c.vregoff(&p.From)) 4042 i2 = uint32(c.vregoff(p.GetFrom3())) 4043 } 4044 switch p.As { 4045 case AVZERO: 4046 i2 = 0 4047 case AVONE: 4048 i2 = 0xffff 4049 } 4050 zVRIa(op, uint32(p.To.Reg), i2, m3, asm) 4051 4052 case 110: 4053 op, m4, _ := vop(p.As) 4054 i2 := uint32(c.vregoff(&p.From)) 4055 i3 := uint32(c.vregoff(p.GetFrom3())) 4056 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm) 4057 4058 case 111: 4059 op, m4, _ := vop(p.As) 4060 i2 := uint32(c.vregoff(&p.From)) 4061 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm) 4062 4063 case 112: 4064 op, m5, _ := vop(p.As) 4065 i4 := uint32(c.vregoff(&p.From)) 4066 zVRId(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), i4, m5, asm) 4067 4068 case 113: 4069 op, m4, _ := vop(p.As) 4070 m5 := singleElementMask(p.As) 4071 i3 := uint32(c.vregoff(&p.From)) 4072 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm) 4073 4074 case 114: // VRR-a 4075 op, m3, m5 := vop(p.As) 4076 m4 := singleElementMask(p.As) 4077 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm) 4078 4079 case 115: // VRR-a COMPARE 4080 op, m3, m5 := vop(p.As) 4081 m4 := singleElementMask(p.As) 4082 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm) 4083 4084 case 117: // VRR-b 4085 op, m4, m5 := vop(p.As) 4086 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm) 4087 4088 case 118: // VRR-c 4089 op, m4, m6 := vop(p.As) 4090 m5 := singleElementMask(p.As) 4091 v3 := p.Reg 4092 if v3 == 0 { 4093 v3 = p.To.Reg 4094 } 4095 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm) 4096 4097 case 119: // VRR-c SHIFT/ROTATE/DIVIDE/SUB (rhs value on the left, like SLD, DIV etc.) 4098 op, m4, m6 := vop(p.As) 4099 m5 := singleElementMask(p.As) 4100 v2 := p.Reg 4101 if v2 == 0 { 4102 v2 = p.To.Reg 4103 } 4104 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm) 4105 4106 case 120: // VRR-d 4107 op, m6, _ := vop(p.As) 4108 m5 := singleElementMask(p.As) 4109 v1 := uint32(p.To.Reg) 4110 v2 := uint32(p.From.Reg) 4111 v3 := uint32(p.Reg) 4112 v4 := uint32(p.GetFrom3().Reg) 4113 zVRRd(op, v1, v2, v3, m6, m5, v4, asm) 4114 4115 case 121: // VRR-e 4116 op, m6, _ := vop(p.As) 4117 m5 := singleElementMask(p.As) 4118 v1 := uint32(p.To.Reg) 4119 v2 := uint32(p.From.Reg) 4120 v3 := uint32(p.Reg) 4121 v4 := uint32(p.GetFrom3().Reg) 4122 zVRRe(op, v1, v2, v3, m6, m5, v4, asm) 4123 4124 case 122: // VRR-f LOAD VRS FROM GRS DISJOINT 4125 op, _, _ := vop(p.As) 4126 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 4127 4128 case 123: // VPDI $m4, V2, V3, V1 4129 op, _, _ := vop(p.As) 4130 m4 := c.regoff(&p.From) 4131 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), 0, 0, uint32(m4), asm) 4132 } 4133 } 4134 4135 func (c *ctxtz) vregoff(a *obj.Addr) int64 { 4136 c.instoffset = 0 4137 if a != nil { 4138 c.aclass(a) 4139 } 4140 return c.instoffset 4141 } 4142 4143 func (c *ctxtz) regoff(a *obj.Addr) int32 { 4144 return int32(c.vregoff(a)) 4145 } 4146 4147 // zopload returns the RXY op for the given load 4148 func (c *ctxtz) zopload(a obj.As) uint32 { 4149 switch a { 4150 // fixed point load 4151 case AMOVD: 4152 return op_LG 4153 case AMOVW: 4154 return op_LGF 4155 case AMOVWZ: 4156 return op_LLGF 4157 case AMOVH: 4158 return op_LGH 4159 case AMOVHZ: 4160 return op_LLGH 4161 case AMOVB: 4162 return op_LGB 4163 case AMOVBZ: 4164 return op_LLGC 4165 4166 // floating point load 4167 case AFMOVD: 4168 return op_LDY 4169 case AFMOVS: 4170 return op_LEY 4171 4172 // byte reversed load 4173 case AMOVDBR: 4174 return op_LRVG 4175 case AMOVWBR: 4176 return op_LRV 4177 case AMOVHBR: 4178 return op_LRVH 4179 } 4180 4181 c.ctxt.Diag("unknown store opcode %v", a) 4182 return 0 4183 } 4184 4185 // zopstore returns the RXY op for the given store 4186 func (c *ctxtz) zopstore(a obj.As) uint32 { 4187 switch a { 4188 // fixed point store 4189 case AMOVD: 4190 return op_STG 4191 case AMOVW, AMOVWZ: 4192 return op_STY 4193 case AMOVH, AMOVHZ: 4194 return op_STHY 4195 case AMOVB, AMOVBZ: 4196 return op_STCY 4197 4198 // floating point store 4199 case AFMOVD: 4200 return op_STDY 4201 case AFMOVS: 4202 return op_STEY 4203 4204 // byte reversed store 4205 case AMOVDBR: 4206 return op_STRVG 4207 case AMOVWBR: 4208 return op_STRV 4209 case AMOVHBR: 4210 return op_STRVH 4211 } 4212 4213 c.ctxt.Diag("unknown store opcode %v", a) 4214 return 0 4215 } 4216 4217 // zoprre returns the RRE op for the given a 4218 func (c *ctxtz) zoprre(a obj.As) uint32 { 4219 switch a { 4220 case ACMP: 4221 return op_CGR 4222 case ACMPU: 4223 return op_CLGR 4224 case AFCMPO: //ordered 4225 return op_KDBR 4226 case AFCMPU: //unordered 4227 return op_CDBR 4228 case ACEBR: 4229 return op_CEBR 4230 } 4231 c.ctxt.Diag("unknown rre opcode %v", a) 4232 return 0 4233 } 4234 4235 // zoprr returns the RR op for the given a 4236 func (c *ctxtz) zoprr(a obj.As) uint32 { 4237 switch a { 4238 case ACMPW: 4239 return op_CR 4240 case ACMPWU: 4241 return op_CLR 4242 } 4243 c.ctxt.Diag("unknown rr opcode %v", a) 4244 return 0 4245 } 4246 4247 // zopril returns the RIL op for the given a 4248 func (c *ctxtz) zopril(a obj.As) uint32 { 4249 switch a { 4250 case ACMP: 4251 return op_CGFI 4252 case ACMPU: 4253 return op_CLGFI 4254 case ACMPW: 4255 return op_CFI 4256 case ACMPWU: 4257 return op_CLFI 4258 } 4259 c.ctxt.Diag("unknown ril opcode %v", a) 4260 return 0 4261 } 4262 4263 // z instructions sizes 4264 const ( 4265 sizeE = 2 4266 sizeI = 2 4267 sizeIE = 4 4268 sizeMII = 6 4269 sizeRI = 4 4270 sizeRI1 = 4 4271 sizeRI2 = 4 4272 sizeRI3 = 4 4273 sizeRIE = 6 4274 sizeRIE1 = 6 4275 sizeRIE2 = 6 4276 sizeRIE3 = 6 4277 sizeRIE4 = 6 4278 sizeRIE5 = 6 4279 sizeRIE6 = 6 4280 sizeRIL = 6 4281 sizeRIL1 = 6 4282 sizeRIL2 = 6 4283 sizeRIL3 = 6 4284 sizeRIS = 6 4285 sizeRR = 2 4286 sizeRRD = 4 4287 sizeRRE = 4 4288 sizeRRF = 4 4289 sizeRRF1 = 4 4290 sizeRRF2 = 4 4291 sizeRRF3 = 4 4292 sizeRRF4 = 4 4293 sizeRRF5 = 4 4294 sizeRRR = 2 4295 sizeRRS = 6 4296 sizeRS = 4 4297 sizeRS1 = 4 4298 sizeRS2 = 4 4299 sizeRSI = 4 4300 sizeRSL = 6 4301 sizeRSY = 6 4302 sizeRSY1 = 6 4303 sizeRSY2 = 6 4304 sizeRX = 4 4305 sizeRX1 = 4 4306 sizeRX2 = 4 4307 sizeRXE = 6 4308 sizeRXF = 6 4309 sizeRXY = 6 4310 sizeRXY1 = 6 4311 sizeRXY2 = 6 4312 sizeS = 4 4313 sizeSI = 4 4314 sizeSIL = 6 4315 sizeSIY = 6 4316 sizeSMI = 6 4317 sizeSS = 6 4318 sizeSS1 = 6 4319 sizeSS2 = 6 4320 sizeSS3 = 6 4321 sizeSS4 = 6 4322 sizeSS5 = 6 4323 sizeSS6 = 6 4324 sizeSSE = 6 4325 sizeSSF = 6 4326 ) 4327 4328 // instruction format variations 4329 type form int 4330 4331 const ( 4332 _a form = iota 4333 _b 4334 _c 4335 _d 4336 _e 4337 _f 4338 ) 4339 4340 func zE(op uint32, asm *[]byte) { 4341 *asm = append(*asm, uint8(op>>8), uint8(op)) 4342 } 4343 4344 func zI(op, i1 uint32, asm *[]byte) { 4345 *asm = append(*asm, uint8(op>>8), uint8(i1)) 4346 } 4347 4348 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) { 4349 *asm = append(*asm, 4350 uint8(op>>8), 4351 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F), 4352 uint8(ri2), 4353 uint8(ri3>>16), 4354 uint8(ri3>>8), 4355 uint8(ri3)) 4356 } 4357 4358 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4359 *asm = append(*asm, 4360 uint8(op>>8), 4361 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4362 uint8(i2_ri2>>8), 4363 uint8(i2_ri2)) 4364 } 4365 4366 // Expected argument values for the instruction formats. 4367 // 4368 // Format a1 a2 a3 a4 a5 a6 a7 4369 // ------------------------------------ 4370 // a r1, 0, i2, 0, 0, m3, 0 4371 // b r1, r2, ri4, 0, 0, m3, 0 4372 // c r1, m3, ri4, 0, 0, 0, i2 4373 // d r1, r3, i2, 0, 0, 0, 0 4374 // e r1, r3, ri2, 0, 0, 0, 0 4375 // f r1, r2, 0, i3, i4, 0, i5 4376 // g r1, m3, i2, 0, 0, 0, 0 4377 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) { 4378 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F)) 4379 4380 switch f { 4381 default: 4382 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2)) 4383 case _f: 4384 *asm = append(*asm, uint8(i3), uint8(i4)) 4385 } 4386 4387 switch f { 4388 case _a, _b: 4389 *asm = append(*asm, uint8(m3)<<4) 4390 default: 4391 *asm = append(*asm, uint8(i2_i5)) 4392 } 4393 4394 *asm = append(*asm, uint8(op)) 4395 } 4396 4397 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4398 if f == _a || f == _b { 4399 r1_m1 = r1_m1 - obj.RBaseS390X // this is a register base 4400 } 4401 *asm = append(*asm, 4402 uint8(op>>8), 4403 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4404 uint8(i2_ri2>>24), 4405 uint8(i2_ri2>>16), 4406 uint8(i2_ri2>>8), 4407 uint8(i2_ri2)) 4408 } 4409 4410 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) { 4411 *asm = append(*asm, 4412 uint8(op>>8), 4413 (uint8(r1)<<4)|uint8(m3&0x0F), 4414 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F), 4415 uint8(d4), 4416 uint8(i2), 4417 uint8(op)) 4418 } 4419 4420 func zRR(op, r1, r2 uint32, asm *[]byte) { 4421 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F)) 4422 } 4423 4424 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) { 4425 *asm = append(*asm, 4426 uint8(op>>8), 4427 uint8(op), 4428 uint8(r1)<<4, 4429 (uint8(r3)<<4)|uint8(r2&0x0F)) 4430 } 4431 4432 func zRRE(op, r1, r2 uint32, asm *[]byte) { 4433 *asm = append(*asm, 4434 uint8(op>>8), 4435 uint8(op), 4436 0, 4437 (uint8(r1)<<4)|uint8(r2&0x0F)) 4438 } 4439 4440 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) { 4441 *asm = append(*asm, 4442 uint8(op>>8), 4443 uint8(op), 4444 (uint8(r3_m3)<<4)|uint8(m4&0x0F), 4445 (uint8(r1)<<4)|uint8(r2&0x0F)) 4446 } 4447 4448 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) { 4449 *asm = append(*asm, 4450 uint8(op>>8), 4451 (uint8(r1)<<4)|uint8(r2&0x0F), 4452 (uint8(b4)<<4)|uint8((d4>>8)&0x0F), 4453 uint8(d4), 4454 uint8(m3)<<4, 4455 uint8(op)) 4456 } 4457 4458 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4459 *asm = append(*asm, 4460 uint8(op>>8), 4461 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4462 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4463 uint8(d2)) 4464 } 4465 4466 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) { 4467 *asm = append(*asm, 4468 uint8(op>>8), 4469 (uint8(r1)<<4)|uint8(r3&0x0F), 4470 uint8(ri2>>8), 4471 uint8(ri2)) 4472 } 4473 4474 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) { 4475 *asm = append(*asm, 4476 uint8(op>>8), 4477 uint8(l1), 4478 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4479 uint8(d2), 4480 uint8(op)) 4481 } 4482 4483 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4484 dl2 := uint16(d2) & 0x0FFF 4485 *asm = append(*asm, 4486 uint8(op>>8), 4487 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4488 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4489 uint8(dl2), 4490 uint8(d2>>12), 4491 uint8(op)) 4492 } 4493 4494 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4495 *asm = append(*asm, 4496 uint8(op>>8), 4497 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4498 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4499 uint8(d2)) 4500 } 4501 4502 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) { 4503 *asm = append(*asm, 4504 uint8(op>>8), 4505 (uint8(r1)<<4)|uint8(x2&0x0F), 4506 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4507 uint8(d2), 4508 uint8(m3)<<4, 4509 uint8(op)) 4510 } 4511 4512 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) { 4513 *asm = append(*asm, 4514 uint8(op>>8), 4515 (uint8(r3)<<4)|uint8(x2&0x0F), 4516 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4517 uint8(d2), 4518 uint8(m1)<<4, 4519 uint8(op)) 4520 } 4521 4522 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4523 dl2 := uint16(d2) & 0x0FFF 4524 *asm = append(*asm, 4525 uint8(op>>8), 4526 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4527 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4528 uint8(dl2), 4529 uint8(d2>>12), 4530 uint8(op)) 4531 } 4532 4533 func zS(op, b2, d2 uint32, asm *[]byte) { 4534 *asm = append(*asm, 4535 uint8(op>>8), 4536 uint8(op), 4537 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4538 uint8(d2)) 4539 } 4540 4541 func zSI(op, i2, b1, d1 uint32, asm *[]byte) { 4542 *asm = append(*asm, 4543 uint8(op>>8), 4544 uint8(i2), 4545 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4546 uint8(d1)) 4547 } 4548 4549 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) { 4550 *asm = append(*asm, 4551 uint8(op>>8), 4552 uint8(op), 4553 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4554 uint8(d1), 4555 uint8(i2>>8), 4556 uint8(i2)) 4557 } 4558 4559 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) { 4560 dl1 := uint16(d1) & 0x0FFF 4561 *asm = append(*asm, 4562 uint8(op>>8), 4563 uint8(i2), 4564 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F), 4565 uint8(dl1), 4566 uint8(d1>>12), 4567 uint8(op)) 4568 } 4569 4570 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) { 4571 *asm = append(*asm, 4572 uint8(op>>8), 4573 uint8(m1)<<4, 4574 (uint8(b3)<<4)|uint8((d3>>8)&0x0F), 4575 uint8(d3), 4576 uint8(ri2>>8), 4577 uint8(ri2)) 4578 } 4579 4580 // Expected argument values for the instruction formats. 4581 // 4582 // Format a1 a2 a3 a4 a5 a6 4583 // ------------------------------- 4584 // a l1, 0, b1, d1, b2, d2 4585 // b l1, l2, b1, d1, b2, d2 4586 // c l1, i3, b1, d1, b2, d2 4587 // d r1, r3, b1, d1, b2, d2 4588 // e r1, r3, b2, d2, b4, d4 4589 // f 0, l2, b1, d1, b2, d2 4590 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) { 4591 *asm = append(*asm, uint8(op>>8)) 4592 4593 switch f { 4594 case _a: 4595 *asm = append(*asm, uint8(l1_r1)) 4596 case _b, _c, _d, _e: 4597 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F)) 4598 case _f: 4599 *asm = append(*asm, uint8(l2_i3_r3)) 4600 } 4601 4602 *asm = append(*asm, 4603 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F), 4604 uint8(d1_d2), 4605 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F), 4606 uint8(d2_d4)) 4607 } 4608 4609 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) { 4610 *asm = append(*asm, 4611 uint8(op>>8), 4612 uint8(op), 4613 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4614 uint8(d1), 4615 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4616 uint8(d2)) 4617 } 4618 4619 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) { 4620 *asm = append(*asm, 4621 uint8(op>>8), 4622 (uint8(r3)<<4)|(uint8(op)&0x0F), 4623 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4624 uint8(d1), 4625 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4626 uint8(d2)) 4627 } 4628 4629 func rxb(va, vb, vc, vd uint32) uint8 { 4630 mask := uint8(0) 4631 if va >= REG_V16 && va <= REG_V31 { 4632 mask |= 0x8 4633 } 4634 if vb >= REG_V16 && vb <= REG_V31 { 4635 mask |= 0x4 4636 } 4637 if vc >= REG_V16 && vc <= REG_V31 { 4638 mask |= 0x2 4639 } 4640 if vd >= REG_V16 && vd <= REG_V31 { 4641 mask |= 0x1 4642 } 4643 return mask 4644 } 4645 4646 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) { 4647 *asm = append(*asm, 4648 uint8(op>>8), 4649 (uint8(v1)<<4)|(uint8(x2)&0xf), 4650 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4651 uint8(d2), 4652 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4653 uint8(op)) 4654 } 4655 4656 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) { 4657 *asm = append(*asm, 4658 uint8(op>>8), 4659 (uint8(v1)<<4)|(uint8(v2)&0xf), 4660 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4661 uint8(d2), 4662 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4663 uint8(op)) 4664 } 4665 4666 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) { 4667 *asm = append(*asm, 4668 uint8(op>>8), 4669 (uint8(v1)<<4)|(uint8(v3_r3)&0xf), 4670 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4671 uint8(d2), 4672 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0), 4673 uint8(op)) 4674 } 4675 4676 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) { 4677 *asm = append(*asm, 4678 uint8(op>>8), 4679 (uint8(v1)<<4)|(uint8(v2)&0xf), 4680 0, 4681 (uint8(m5)<<4)|(uint8(m4)&0xf), 4682 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4683 uint8(op)) 4684 } 4685 4686 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) { 4687 *asm = append(*asm, 4688 uint8(op>>8), 4689 (uint8(v1)<<4)|(uint8(v2)&0xf), 4690 uint8(v3)<<4, 4691 uint8(m5)<<4, 4692 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4693 uint8(op)) 4694 } 4695 4696 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) { 4697 *asm = append(*asm, 4698 uint8(op>>8), 4699 (uint8(v1)<<4)|(uint8(v2)&0xf), 4700 uint8(v3)<<4, 4701 (uint8(m6)<<4)|(uint8(m5)&0xf), 4702 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4703 uint8(op)) 4704 } 4705 4706 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) { 4707 *asm = append(*asm, 4708 uint8(op>>8), 4709 (uint8(v1)<<4)|(uint8(v2)&0xf), 4710 (uint8(v3)<<4)|(uint8(m5)&0xf), 4711 uint8(m6)<<4, 4712 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4713 uint8(op)) 4714 } 4715 4716 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) { 4717 *asm = append(*asm, 4718 uint8(op>>8), 4719 (uint8(v1)<<4)|(uint8(v2)&0xf), 4720 (uint8(v3)<<4)|(uint8(m6)&0xf), 4721 uint8(m5), 4722 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4723 uint8(op)) 4724 } 4725 4726 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) { 4727 *asm = append(*asm, 4728 uint8(op>>8), 4729 (uint8(v1)<<4)|(uint8(r2)&0xf), 4730 uint8(r3)<<4, 4731 0, 4732 rxb(v1, 0, 0, 0), 4733 uint8(op)) 4734 } 4735 4736 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) { 4737 *asm = append(*asm, 4738 uint8(op>>8), 4739 uint8(v1)<<4, 4740 uint8(i2>>8), 4741 uint8(i2), 4742 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4743 uint8(op)) 4744 } 4745 4746 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) { 4747 *asm = append(*asm, 4748 uint8(op>>8), 4749 uint8(v1)<<4, 4750 uint8(i2), 4751 uint8(i3), 4752 (uint8(m4)<<4)|rxb(v1, 0, 0, 0), 4753 uint8(op)) 4754 } 4755 4756 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) { 4757 *asm = append(*asm, 4758 uint8(op>>8), 4759 (uint8(v1)<<4)|(uint8(v3)&0xf), 4760 uint8(i2>>8), 4761 uint8(i2), 4762 (uint8(m4)<<4)|rxb(v1, v3, 0, 0), 4763 uint8(op)) 4764 } 4765 4766 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) { 4767 *asm = append(*asm, 4768 uint8(op>>8), 4769 (uint8(v1)<<4)|(uint8(v2)&0xf), 4770 uint8(v3)<<4, 4771 uint8(i4), 4772 (uint8(m5)<<4)|rxb(v1, v2, v3, 0), 4773 uint8(op)) 4774 } 4775 4776 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) { 4777 *asm = append(*asm, 4778 uint8(op>>8), 4779 (uint8(v1)<<4)|(uint8(v2)&0xf), 4780 uint8(i3>>4), 4781 (uint8(i3)<<4)|(uint8(m5)&0xf), 4782 (uint8(m4)<<4)|rxb(v1, v2, 0, 0), 4783 uint8(op)) 4784 }