github.com/hlts2/go@v0.0.0-20170904000733-812b34efaed8/src/cmd/compile/internal/ssa/opGen.go (about) 1 // Code generated from gen/*Ops.go; DO NOT EDIT. 2 3 package ssa 4 5 import ( 6 "cmd/internal/obj" 7 "cmd/internal/obj/arm" 8 "cmd/internal/obj/arm64" 9 "cmd/internal/obj/mips" 10 "cmd/internal/obj/ppc64" 11 "cmd/internal/obj/s390x" 12 "cmd/internal/obj/x86" 13 ) 14 15 const ( 16 BlockInvalid BlockKind = iota 17 18 Block386EQ 19 Block386NE 20 Block386LT 21 Block386LE 22 Block386GT 23 Block386GE 24 Block386ULT 25 Block386ULE 26 Block386UGT 27 Block386UGE 28 Block386EQF 29 Block386NEF 30 Block386ORD 31 Block386NAN 32 33 BlockAMD64EQ 34 BlockAMD64NE 35 BlockAMD64LT 36 BlockAMD64LE 37 BlockAMD64GT 38 BlockAMD64GE 39 BlockAMD64ULT 40 BlockAMD64ULE 41 BlockAMD64UGT 42 BlockAMD64UGE 43 BlockAMD64EQF 44 BlockAMD64NEF 45 BlockAMD64ORD 46 BlockAMD64NAN 47 48 BlockARMEQ 49 BlockARMNE 50 BlockARMLT 51 BlockARMLE 52 BlockARMGT 53 BlockARMGE 54 BlockARMULT 55 BlockARMULE 56 BlockARMUGT 57 BlockARMUGE 58 59 BlockARM64EQ 60 BlockARM64NE 61 BlockARM64LT 62 BlockARM64LE 63 BlockARM64GT 64 BlockARM64GE 65 BlockARM64ULT 66 BlockARM64ULE 67 BlockARM64UGT 68 BlockARM64UGE 69 BlockARM64Z 70 BlockARM64NZ 71 BlockARM64ZW 72 BlockARM64NZW 73 BlockARM64TBZ 74 BlockARM64TBNZ 75 76 BlockMIPSEQ 77 BlockMIPSNE 78 BlockMIPSLTZ 79 BlockMIPSLEZ 80 BlockMIPSGTZ 81 BlockMIPSGEZ 82 BlockMIPSFPT 83 BlockMIPSFPF 84 85 BlockMIPS64EQ 86 BlockMIPS64NE 87 BlockMIPS64LTZ 88 BlockMIPS64LEZ 89 BlockMIPS64GTZ 90 BlockMIPS64GEZ 91 BlockMIPS64FPT 92 BlockMIPS64FPF 93 94 BlockPPC64EQ 95 BlockPPC64NE 96 BlockPPC64LT 97 BlockPPC64LE 98 BlockPPC64GT 99 BlockPPC64GE 100 BlockPPC64FLT 101 BlockPPC64FLE 102 BlockPPC64FGT 103 BlockPPC64FGE 104 105 BlockS390XEQ 106 BlockS390XNE 107 BlockS390XLT 108 BlockS390XLE 109 BlockS390XGT 110 BlockS390XGE 111 BlockS390XGTF 112 BlockS390XGEF 113 114 BlockPlain 115 BlockIf 116 BlockDefer 117 BlockRet 118 BlockRetJmp 119 BlockExit 120 BlockFirst 121 ) 122 123 var blockString = [...]string{ 124 BlockInvalid: "BlockInvalid", 125 126 Block386EQ: "EQ", 127 Block386NE: "NE", 128 Block386LT: "LT", 129 Block386LE: "LE", 130 Block386GT: "GT", 131 Block386GE: "GE", 132 Block386ULT: "ULT", 133 Block386ULE: "ULE", 134 Block386UGT: "UGT", 135 Block386UGE: "UGE", 136 Block386EQF: "EQF", 137 Block386NEF: "NEF", 138 Block386ORD: "ORD", 139 Block386NAN: "NAN", 140 141 BlockAMD64EQ: "EQ", 142 BlockAMD64NE: "NE", 143 BlockAMD64LT: "LT", 144 BlockAMD64LE: "LE", 145 BlockAMD64GT: "GT", 146 BlockAMD64GE: "GE", 147 BlockAMD64ULT: "ULT", 148 BlockAMD64ULE: "ULE", 149 BlockAMD64UGT: "UGT", 150 BlockAMD64UGE: "UGE", 151 BlockAMD64EQF: "EQF", 152 BlockAMD64NEF: "NEF", 153 BlockAMD64ORD: "ORD", 154 BlockAMD64NAN: "NAN", 155 156 BlockARMEQ: "EQ", 157 BlockARMNE: "NE", 158 BlockARMLT: "LT", 159 BlockARMLE: "LE", 160 BlockARMGT: "GT", 161 BlockARMGE: "GE", 162 BlockARMULT: "ULT", 163 BlockARMULE: "ULE", 164 BlockARMUGT: "UGT", 165 BlockARMUGE: "UGE", 166 167 BlockARM64EQ: "EQ", 168 BlockARM64NE: "NE", 169 BlockARM64LT: "LT", 170 BlockARM64LE: "LE", 171 BlockARM64GT: "GT", 172 BlockARM64GE: "GE", 173 BlockARM64ULT: "ULT", 174 BlockARM64ULE: "ULE", 175 BlockARM64UGT: "UGT", 176 BlockARM64UGE: "UGE", 177 BlockARM64Z: "Z", 178 BlockARM64NZ: "NZ", 179 BlockARM64ZW: "ZW", 180 BlockARM64NZW: "NZW", 181 BlockARM64TBZ: "TBZ", 182 BlockARM64TBNZ: "TBNZ", 183 184 BlockMIPSEQ: "EQ", 185 BlockMIPSNE: "NE", 186 BlockMIPSLTZ: "LTZ", 187 BlockMIPSLEZ: "LEZ", 188 BlockMIPSGTZ: "GTZ", 189 BlockMIPSGEZ: "GEZ", 190 BlockMIPSFPT: "FPT", 191 BlockMIPSFPF: "FPF", 192 193 BlockMIPS64EQ: "EQ", 194 BlockMIPS64NE: "NE", 195 BlockMIPS64LTZ: "LTZ", 196 BlockMIPS64LEZ: "LEZ", 197 BlockMIPS64GTZ: "GTZ", 198 BlockMIPS64GEZ: "GEZ", 199 BlockMIPS64FPT: "FPT", 200 BlockMIPS64FPF: "FPF", 201 202 BlockPPC64EQ: "EQ", 203 BlockPPC64NE: "NE", 204 BlockPPC64LT: "LT", 205 BlockPPC64LE: "LE", 206 BlockPPC64GT: "GT", 207 BlockPPC64GE: "GE", 208 BlockPPC64FLT: "FLT", 209 BlockPPC64FLE: "FLE", 210 BlockPPC64FGT: "FGT", 211 BlockPPC64FGE: "FGE", 212 213 BlockS390XEQ: "EQ", 214 BlockS390XNE: "NE", 215 BlockS390XLT: "LT", 216 BlockS390XLE: "LE", 217 BlockS390XGT: "GT", 218 BlockS390XGE: "GE", 219 BlockS390XGTF: "GTF", 220 BlockS390XGEF: "GEF", 221 222 BlockPlain: "Plain", 223 BlockIf: "If", 224 BlockDefer: "Defer", 225 BlockRet: "Ret", 226 BlockRetJmp: "RetJmp", 227 BlockExit: "Exit", 228 BlockFirst: "First", 229 } 230 231 func (k BlockKind) String() string { return blockString[k] } 232 233 const ( 234 OpInvalid Op = iota 235 236 Op386ADDSS 237 Op386ADDSD 238 Op386SUBSS 239 Op386SUBSD 240 Op386MULSS 241 Op386MULSD 242 Op386DIVSS 243 Op386DIVSD 244 Op386MOVSSload 245 Op386MOVSDload 246 Op386MOVSSconst 247 Op386MOVSDconst 248 Op386MOVSSloadidx1 249 Op386MOVSSloadidx4 250 Op386MOVSDloadidx1 251 Op386MOVSDloadidx8 252 Op386MOVSSstore 253 Op386MOVSDstore 254 Op386MOVSSstoreidx1 255 Op386MOVSSstoreidx4 256 Op386MOVSDstoreidx1 257 Op386MOVSDstoreidx8 258 Op386ADDL 259 Op386ADDLconst 260 Op386ADDLcarry 261 Op386ADDLconstcarry 262 Op386ADCL 263 Op386ADCLconst 264 Op386SUBL 265 Op386SUBLconst 266 Op386SUBLcarry 267 Op386SUBLconstcarry 268 Op386SBBL 269 Op386SBBLconst 270 Op386MULL 271 Op386MULLconst 272 Op386HMULL 273 Op386HMULLU 274 Op386MULLQU 275 Op386AVGLU 276 Op386DIVL 277 Op386DIVW 278 Op386DIVLU 279 Op386DIVWU 280 Op386MODL 281 Op386MODW 282 Op386MODLU 283 Op386MODWU 284 Op386ANDL 285 Op386ANDLconst 286 Op386ORL 287 Op386ORLconst 288 Op386XORL 289 Op386XORLconst 290 Op386CMPL 291 Op386CMPW 292 Op386CMPB 293 Op386CMPLconst 294 Op386CMPWconst 295 Op386CMPBconst 296 Op386UCOMISS 297 Op386UCOMISD 298 Op386TESTL 299 Op386TESTW 300 Op386TESTB 301 Op386TESTLconst 302 Op386TESTWconst 303 Op386TESTBconst 304 Op386SHLL 305 Op386SHLLconst 306 Op386SHRL 307 Op386SHRW 308 Op386SHRB 309 Op386SHRLconst 310 Op386SHRWconst 311 Op386SHRBconst 312 Op386SARL 313 Op386SARW 314 Op386SARB 315 Op386SARLconst 316 Op386SARWconst 317 Op386SARBconst 318 Op386ROLLconst 319 Op386ROLWconst 320 Op386ROLBconst 321 Op386NEGL 322 Op386NOTL 323 Op386BSFL 324 Op386BSFW 325 Op386BSRL 326 Op386BSRW 327 Op386BSWAPL 328 Op386SQRTSD 329 Op386SBBLcarrymask 330 Op386SETEQ 331 Op386SETNE 332 Op386SETL 333 Op386SETLE 334 Op386SETG 335 Op386SETGE 336 Op386SETB 337 Op386SETBE 338 Op386SETA 339 Op386SETAE 340 Op386SETEQF 341 Op386SETNEF 342 Op386SETORD 343 Op386SETNAN 344 Op386SETGF 345 Op386SETGEF 346 Op386MOVBLSX 347 Op386MOVBLZX 348 Op386MOVWLSX 349 Op386MOVWLZX 350 Op386MOVLconst 351 Op386CVTTSD2SL 352 Op386CVTTSS2SL 353 Op386CVTSL2SS 354 Op386CVTSL2SD 355 Op386CVTSD2SS 356 Op386CVTSS2SD 357 Op386PXOR 358 Op386LEAL 359 Op386LEAL1 360 Op386LEAL2 361 Op386LEAL4 362 Op386LEAL8 363 Op386MOVBload 364 Op386MOVBLSXload 365 Op386MOVWload 366 Op386MOVWLSXload 367 Op386MOVLload 368 Op386MOVBstore 369 Op386MOVWstore 370 Op386MOVLstore 371 Op386MOVBloadidx1 372 Op386MOVWloadidx1 373 Op386MOVWloadidx2 374 Op386MOVLloadidx1 375 Op386MOVLloadidx4 376 Op386MOVBstoreidx1 377 Op386MOVWstoreidx1 378 Op386MOVWstoreidx2 379 Op386MOVLstoreidx1 380 Op386MOVLstoreidx4 381 Op386MOVBstoreconst 382 Op386MOVWstoreconst 383 Op386MOVLstoreconst 384 Op386MOVBstoreconstidx1 385 Op386MOVWstoreconstidx1 386 Op386MOVWstoreconstidx2 387 Op386MOVLstoreconstidx1 388 Op386MOVLstoreconstidx4 389 Op386DUFFZERO 390 Op386REPSTOSL 391 Op386CALLstatic 392 Op386CALLclosure 393 Op386CALLinter 394 Op386DUFFCOPY 395 Op386REPMOVSL 396 Op386InvertFlags 397 Op386LoweredGetG 398 Op386LoweredGetClosurePtr 399 Op386LoweredNilCheck 400 Op386MOVLconvert 401 Op386FlagEQ 402 Op386FlagLT_ULT 403 Op386FlagLT_UGT 404 Op386FlagGT_UGT 405 Op386FlagGT_ULT 406 Op386FCHS 407 Op386MOVSSconst1 408 Op386MOVSDconst1 409 Op386MOVSSconst2 410 Op386MOVSDconst2 411 412 OpAMD64ADDSS 413 OpAMD64ADDSD 414 OpAMD64SUBSS 415 OpAMD64SUBSD 416 OpAMD64MULSS 417 OpAMD64MULSD 418 OpAMD64DIVSS 419 OpAMD64DIVSD 420 OpAMD64MOVSSload 421 OpAMD64MOVSDload 422 OpAMD64MOVSSconst 423 OpAMD64MOVSDconst 424 OpAMD64MOVSSloadidx1 425 OpAMD64MOVSSloadidx4 426 OpAMD64MOVSDloadidx1 427 OpAMD64MOVSDloadidx8 428 OpAMD64MOVSSstore 429 OpAMD64MOVSDstore 430 OpAMD64MOVSSstoreidx1 431 OpAMD64MOVSSstoreidx4 432 OpAMD64MOVSDstoreidx1 433 OpAMD64MOVSDstoreidx8 434 OpAMD64ADDSSmem 435 OpAMD64ADDSDmem 436 OpAMD64SUBSSmem 437 OpAMD64SUBSDmem 438 OpAMD64MULSSmem 439 OpAMD64MULSDmem 440 OpAMD64ADDQ 441 OpAMD64ADDL 442 OpAMD64ADDQconst 443 OpAMD64ADDLconst 444 OpAMD64ADDQconstmem 445 OpAMD64ADDLconstmem 446 OpAMD64SUBQ 447 OpAMD64SUBL 448 OpAMD64SUBQconst 449 OpAMD64SUBLconst 450 OpAMD64MULQ 451 OpAMD64MULL 452 OpAMD64MULQconst 453 OpAMD64MULLconst 454 OpAMD64HMULQ 455 OpAMD64HMULL 456 OpAMD64HMULQU 457 OpAMD64HMULLU 458 OpAMD64AVGQU 459 OpAMD64DIVQ 460 OpAMD64DIVL 461 OpAMD64DIVW 462 OpAMD64DIVQU 463 OpAMD64DIVLU 464 OpAMD64DIVWU 465 OpAMD64MULQU2 466 OpAMD64DIVQU2 467 OpAMD64ANDQ 468 OpAMD64ANDL 469 OpAMD64ANDQconst 470 OpAMD64ANDLconst 471 OpAMD64ORQ 472 OpAMD64ORL 473 OpAMD64ORQconst 474 OpAMD64ORLconst 475 OpAMD64XORQ 476 OpAMD64XORL 477 OpAMD64XORQconst 478 OpAMD64XORLconst 479 OpAMD64CMPQ 480 OpAMD64CMPL 481 OpAMD64CMPW 482 OpAMD64CMPB 483 OpAMD64CMPQconst 484 OpAMD64CMPLconst 485 OpAMD64CMPWconst 486 OpAMD64CMPBconst 487 OpAMD64UCOMISS 488 OpAMD64UCOMISD 489 OpAMD64BTL 490 OpAMD64BTQ 491 OpAMD64BTLconst 492 OpAMD64BTQconst 493 OpAMD64TESTQ 494 OpAMD64TESTL 495 OpAMD64TESTW 496 OpAMD64TESTB 497 OpAMD64TESTQconst 498 OpAMD64TESTLconst 499 OpAMD64TESTWconst 500 OpAMD64TESTBconst 501 OpAMD64SHLQ 502 OpAMD64SHLL 503 OpAMD64SHLQconst 504 OpAMD64SHLLconst 505 OpAMD64SHRQ 506 OpAMD64SHRL 507 OpAMD64SHRW 508 OpAMD64SHRB 509 OpAMD64SHRQconst 510 OpAMD64SHRLconst 511 OpAMD64SHRWconst 512 OpAMD64SHRBconst 513 OpAMD64SARQ 514 OpAMD64SARL 515 OpAMD64SARW 516 OpAMD64SARB 517 OpAMD64SARQconst 518 OpAMD64SARLconst 519 OpAMD64SARWconst 520 OpAMD64SARBconst 521 OpAMD64ROLQ 522 OpAMD64ROLL 523 OpAMD64ROLW 524 OpAMD64ROLB 525 OpAMD64RORQ 526 OpAMD64RORL 527 OpAMD64RORW 528 OpAMD64RORB 529 OpAMD64ROLQconst 530 OpAMD64ROLLconst 531 OpAMD64ROLWconst 532 OpAMD64ROLBconst 533 OpAMD64ADDLmem 534 OpAMD64ADDQmem 535 OpAMD64SUBQmem 536 OpAMD64SUBLmem 537 OpAMD64ANDLmem 538 OpAMD64ANDQmem 539 OpAMD64ORQmem 540 OpAMD64ORLmem 541 OpAMD64XORQmem 542 OpAMD64XORLmem 543 OpAMD64NEGQ 544 OpAMD64NEGL 545 OpAMD64NOTQ 546 OpAMD64NOTL 547 OpAMD64BSFQ 548 OpAMD64BSFL 549 OpAMD64BSRQ 550 OpAMD64BSRL 551 OpAMD64CMOVQEQ 552 OpAMD64CMOVLEQ 553 OpAMD64BSWAPQ 554 OpAMD64BSWAPL 555 OpAMD64POPCNTQ 556 OpAMD64POPCNTL 557 OpAMD64SQRTSD 558 OpAMD64SBBQcarrymask 559 OpAMD64SBBLcarrymask 560 OpAMD64SETEQ 561 OpAMD64SETNE 562 OpAMD64SETL 563 OpAMD64SETLE 564 OpAMD64SETG 565 OpAMD64SETGE 566 OpAMD64SETB 567 OpAMD64SETBE 568 OpAMD64SETA 569 OpAMD64SETAE 570 OpAMD64SETEQF 571 OpAMD64SETNEF 572 OpAMD64SETORD 573 OpAMD64SETNAN 574 OpAMD64SETGF 575 OpAMD64SETGEF 576 OpAMD64MOVBQSX 577 OpAMD64MOVBQZX 578 OpAMD64MOVWQSX 579 OpAMD64MOVWQZX 580 OpAMD64MOVLQSX 581 OpAMD64MOVLQZX 582 OpAMD64MOVLconst 583 OpAMD64MOVQconst 584 OpAMD64CVTTSD2SL 585 OpAMD64CVTTSD2SQ 586 OpAMD64CVTTSS2SL 587 OpAMD64CVTTSS2SQ 588 OpAMD64CVTSL2SS 589 OpAMD64CVTSL2SD 590 OpAMD64CVTSQ2SS 591 OpAMD64CVTSQ2SD 592 OpAMD64CVTSD2SS 593 OpAMD64CVTSS2SD 594 OpAMD64MOVQi2f 595 OpAMD64MOVQf2i 596 OpAMD64MOVLi2f 597 OpAMD64MOVLf2i 598 OpAMD64PXOR 599 OpAMD64LEAQ 600 OpAMD64LEAQ1 601 OpAMD64LEAQ2 602 OpAMD64LEAQ4 603 OpAMD64LEAQ8 604 OpAMD64LEAL 605 OpAMD64MOVBload 606 OpAMD64MOVBQSXload 607 OpAMD64MOVWload 608 OpAMD64MOVWQSXload 609 OpAMD64MOVLload 610 OpAMD64MOVLQSXload 611 OpAMD64MOVQload 612 OpAMD64MOVBstore 613 OpAMD64MOVWstore 614 OpAMD64MOVLstore 615 OpAMD64MOVQstore 616 OpAMD64MOVOload 617 OpAMD64MOVOstore 618 OpAMD64MOVBloadidx1 619 OpAMD64MOVWloadidx1 620 OpAMD64MOVWloadidx2 621 OpAMD64MOVLloadidx1 622 OpAMD64MOVLloadidx4 623 OpAMD64MOVLloadidx8 624 OpAMD64MOVQloadidx1 625 OpAMD64MOVQloadidx8 626 OpAMD64MOVBstoreidx1 627 OpAMD64MOVWstoreidx1 628 OpAMD64MOVWstoreidx2 629 OpAMD64MOVLstoreidx1 630 OpAMD64MOVLstoreidx4 631 OpAMD64MOVLstoreidx8 632 OpAMD64MOVQstoreidx1 633 OpAMD64MOVQstoreidx8 634 OpAMD64MOVBstoreconst 635 OpAMD64MOVWstoreconst 636 OpAMD64MOVLstoreconst 637 OpAMD64MOVQstoreconst 638 OpAMD64MOVBstoreconstidx1 639 OpAMD64MOVWstoreconstidx1 640 OpAMD64MOVWstoreconstidx2 641 OpAMD64MOVLstoreconstidx1 642 OpAMD64MOVLstoreconstidx4 643 OpAMD64MOVQstoreconstidx1 644 OpAMD64MOVQstoreconstidx8 645 OpAMD64DUFFZERO 646 OpAMD64MOVOconst 647 OpAMD64REPSTOSQ 648 OpAMD64CALLstatic 649 OpAMD64CALLclosure 650 OpAMD64CALLinter 651 OpAMD64DUFFCOPY 652 OpAMD64REPMOVSQ 653 OpAMD64InvertFlags 654 OpAMD64LoweredGetG 655 OpAMD64LoweredGetClosurePtr 656 OpAMD64LoweredNilCheck 657 OpAMD64MOVQconvert 658 OpAMD64MOVLconvert 659 OpAMD64FlagEQ 660 OpAMD64FlagLT_ULT 661 OpAMD64FlagLT_UGT 662 OpAMD64FlagGT_UGT 663 OpAMD64FlagGT_ULT 664 OpAMD64MOVLatomicload 665 OpAMD64MOVQatomicload 666 OpAMD64XCHGL 667 OpAMD64XCHGQ 668 OpAMD64XADDLlock 669 OpAMD64XADDQlock 670 OpAMD64AddTupleFirst32 671 OpAMD64AddTupleFirst64 672 OpAMD64CMPXCHGLlock 673 OpAMD64CMPXCHGQlock 674 OpAMD64ANDBlock 675 OpAMD64ORBlock 676 677 OpARMADD 678 OpARMADDconst 679 OpARMSUB 680 OpARMSUBconst 681 OpARMRSB 682 OpARMRSBconst 683 OpARMMUL 684 OpARMHMUL 685 OpARMHMULU 686 OpARMCALLudiv 687 OpARMADDS 688 OpARMADDSconst 689 OpARMADC 690 OpARMADCconst 691 OpARMSUBS 692 OpARMSUBSconst 693 OpARMRSBSconst 694 OpARMSBC 695 OpARMSBCconst 696 OpARMRSCconst 697 OpARMMULLU 698 OpARMMULA 699 OpARMMULS 700 OpARMADDF 701 OpARMADDD 702 OpARMSUBF 703 OpARMSUBD 704 OpARMMULF 705 OpARMMULD 706 OpARMDIVF 707 OpARMDIVD 708 OpARMAND 709 OpARMANDconst 710 OpARMOR 711 OpARMORconst 712 OpARMXOR 713 OpARMXORconst 714 OpARMBIC 715 OpARMBICconst 716 OpARMMVN 717 OpARMNEGF 718 OpARMNEGD 719 OpARMSQRTD 720 OpARMCLZ 721 OpARMREV 722 OpARMRBIT 723 OpARMSLL 724 OpARMSLLconst 725 OpARMSRL 726 OpARMSRLconst 727 OpARMSRA 728 OpARMSRAconst 729 OpARMSRRconst 730 OpARMADDshiftLL 731 OpARMADDshiftRL 732 OpARMADDshiftRA 733 OpARMSUBshiftLL 734 OpARMSUBshiftRL 735 OpARMSUBshiftRA 736 OpARMRSBshiftLL 737 OpARMRSBshiftRL 738 OpARMRSBshiftRA 739 OpARMANDshiftLL 740 OpARMANDshiftRL 741 OpARMANDshiftRA 742 OpARMORshiftLL 743 OpARMORshiftRL 744 OpARMORshiftRA 745 OpARMXORshiftLL 746 OpARMXORshiftRL 747 OpARMXORshiftRA 748 OpARMXORshiftRR 749 OpARMBICshiftLL 750 OpARMBICshiftRL 751 OpARMBICshiftRA 752 OpARMMVNshiftLL 753 OpARMMVNshiftRL 754 OpARMMVNshiftRA 755 OpARMADCshiftLL 756 OpARMADCshiftRL 757 OpARMADCshiftRA 758 OpARMSBCshiftLL 759 OpARMSBCshiftRL 760 OpARMSBCshiftRA 761 OpARMRSCshiftLL 762 OpARMRSCshiftRL 763 OpARMRSCshiftRA 764 OpARMADDSshiftLL 765 OpARMADDSshiftRL 766 OpARMADDSshiftRA 767 OpARMSUBSshiftLL 768 OpARMSUBSshiftRL 769 OpARMSUBSshiftRA 770 OpARMRSBSshiftLL 771 OpARMRSBSshiftRL 772 OpARMRSBSshiftRA 773 OpARMADDshiftLLreg 774 OpARMADDshiftRLreg 775 OpARMADDshiftRAreg 776 OpARMSUBshiftLLreg 777 OpARMSUBshiftRLreg 778 OpARMSUBshiftRAreg 779 OpARMRSBshiftLLreg 780 OpARMRSBshiftRLreg 781 OpARMRSBshiftRAreg 782 OpARMANDshiftLLreg 783 OpARMANDshiftRLreg 784 OpARMANDshiftRAreg 785 OpARMORshiftLLreg 786 OpARMORshiftRLreg 787 OpARMORshiftRAreg 788 OpARMXORshiftLLreg 789 OpARMXORshiftRLreg 790 OpARMXORshiftRAreg 791 OpARMBICshiftLLreg 792 OpARMBICshiftRLreg 793 OpARMBICshiftRAreg 794 OpARMMVNshiftLLreg 795 OpARMMVNshiftRLreg 796 OpARMMVNshiftRAreg 797 OpARMADCshiftLLreg 798 OpARMADCshiftRLreg 799 OpARMADCshiftRAreg 800 OpARMSBCshiftLLreg 801 OpARMSBCshiftRLreg 802 OpARMSBCshiftRAreg 803 OpARMRSCshiftLLreg 804 OpARMRSCshiftRLreg 805 OpARMRSCshiftRAreg 806 OpARMADDSshiftLLreg 807 OpARMADDSshiftRLreg 808 OpARMADDSshiftRAreg 809 OpARMSUBSshiftLLreg 810 OpARMSUBSshiftRLreg 811 OpARMSUBSshiftRAreg 812 OpARMRSBSshiftLLreg 813 OpARMRSBSshiftRLreg 814 OpARMRSBSshiftRAreg 815 OpARMCMP 816 OpARMCMPconst 817 OpARMCMN 818 OpARMCMNconst 819 OpARMTST 820 OpARMTSTconst 821 OpARMTEQ 822 OpARMTEQconst 823 OpARMCMPF 824 OpARMCMPD 825 OpARMCMPshiftLL 826 OpARMCMPshiftRL 827 OpARMCMPshiftRA 828 OpARMCMPshiftLLreg 829 OpARMCMPshiftRLreg 830 OpARMCMPshiftRAreg 831 OpARMCMPF0 832 OpARMCMPD0 833 OpARMMOVWconst 834 OpARMMOVFconst 835 OpARMMOVDconst 836 OpARMMOVWaddr 837 OpARMMOVBload 838 OpARMMOVBUload 839 OpARMMOVHload 840 OpARMMOVHUload 841 OpARMMOVWload 842 OpARMMOVFload 843 OpARMMOVDload 844 OpARMMOVBstore 845 OpARMMOVHstore 846 OpARMMOVWstore 847 OpARMMOVFstore 848 OpARMMOVDstore 849 OpARMMOVWloadidx 850 OpARMMOVWloadshiftLL 851 OpARMMOVWloadshiftRL 852 OpARMMOVWloadshiftRA 853 OpARMMOVBUloadidx 854 OpARMMOVBloadidx 855 OpARMMOVHUloadidx 856 OpARMMOVHloadidx 857 OpARMMOVWstoreidx 858 OpARMMOVWstoreshiftLL 859 OpARMMOVWstoreshiftRL 860 OpARMMOVWstoreshiftRA 861 OpARMMOVBstoreidx 862 OpARMMOVHstoreidx 863 OpARMMOVBreg 864 OpARMMOVBUreg 865 OpARMMOVHreg 866 OpARMMOVHUreg 867 OpARMMOVWreg 868 OpARMMOVWnop 869 OpARMMOVWF 870 OpARMMOVWD 871 OpARMMOVWUF 872 OpARMMOVWUD 873 OpARMMOVFW 874 OpARMMOVDW 875 OpARMMOVFWU 876 OpARMMOVDWU 877 OpARMMOVFD 878 OpARMMOVDF 879 OpARMCMOVWHSconst 880 OpARMCMOVWLSconst 881 OpARMSRAcond 882 OpARMCALLstatic 883 OpARMCALLclosure 884 OpARMCALLinter 885 OpARMLoweredNilCheck 886 OpARMEqual 887 OpARMNotEqual 888 OpARMLessThan 889 OpARMLessEqual 890 OpARMGreaterThan 891 OpARMGreaterEqual 892 OpARMLessThanU 893 OpARMLessEqualU 894 OpARMGreaterThanU 895 OpARMGreaterEqualU 896 OpARMDUFFZERO 897 OpARMDUFFCOPY 898 OpARMLoweredZero 899 OpARMLoweredMove 900 OpARMLoweredGetClosurePtr 901 OpARMMOVWconvert 902 OpARMFlagEQ 903 OpARMFlagLT_ULT 904 OpARMFlagLT_UGT 905 OpARMFlagGT_UGT 906 OpARMFlagGT_ULT 907 OpARMInvertFlags 908 909 OpARM64ADD 910 OpARM64ADDconst 911 OpARM64SUB 912 OpARM64SUBconst 913 OpARM64MUL 914 OpARM64MULW 915 OpARM64MULH 916 OpARM64UMULH 917 OpARM64MULL 918 OpARM64UMULL 919 OpARM64DIV 920 OpARM64UDIV 921 OpARM64DIVW 922 OpARM64UDIVW 923 OpARM64MOD 924 OpARM64UMOD 925 OpARM64MODW 926 OpARM64UMODW 927 OpARM64FADDS 928 OpARM64FADDD 929 OpARM64FSUBS 930 OpARM64FSUBD 931 OpARM64FMULS 932 OpARM64FMULD 933 OpARM64FDIVS 934 OpARM64FDIVD 935 OpARM64AND 936 OpARM64ANDconst 937 OpARM64OR 938 OpARM64ORconst 939 OpARM64XOR 940 OpARM64XORconst 941 OpARM64BIC 942 OpARM64BICconst 943 OpARM64MVN 944 OpARM64NEG 945 OpARM64FNEGS 946 OpARM64FNEGD 947 OpARM64FSQRTD 948 OpARM64REV 949 OpARM64REVW 950 OpARM64REV16W 951 OpARM64RBIT 952 OpARM64RBITW 953 OpARM64CLZ 954 OpARM64CLZW 955 OpARM64SLL 956 OpARM64SLLconst 957 OpARM64SRL 958 OpARM64SRLconst 959 OpARM64SRA 960 OpARM64SRAconst 961 OpARM64RORconst 962 OpARM64RORWconst 963 OpARM64CMP 964 OpARM64CMPconst 965 OpARM64CMPW 966 OpARM64CMPWconst 967 OpARM64CMN 968 OpARM64CMNconst 969 OpARM64CMNW 970 OpARM64CMNWconst 971 OpARM64FCMPS 972 OpARM64FCMPD 973 OpARM64ADDshiftLL 974 OpARM64ADDshiftRL 975 OpARM64ADDshiftRA 976 OpARM64SUBshiftLL 977 OpARM64SUBshiftRL 978 OpARM64SUBshiftRA 979 OpARM64ANDshiftLL 980 OpARM64ANDshiftRL 981 OpARM64ANDshiftRA 982 OpARM64ORshiftLL 983 OpARM64ORshiftRL 984 OpARM64ORshiftRA 985 OpARM64XORshiftLL 986 OpARM64XORshiftRL 987 OpARM64XORshiftRA 988 OpARM64BICshiftLL 989 OpARM64BICshiftRL 990 OpARM64BICshiftRA 991 OpARM64CMPshiftLL 992 OpARM64CMPshiftRL 993 OpARM64CMPshiftRA 994 OpARM64MOVDconst 995 OpARM64FMOVSconst 996 OpARM64FMOVDconst 997 OpARM64MOVDaddr 998 OpARM64MOVBload 999 OpARM64MOVBUload 1000 OpARM64MOVHload 1001 OpARM64MOVHUload 1002 OpARM64MOVWload 1003 OpARM64MOVWUload 1004 OpARM64MOVDload 1005 OpARM64FMOVSload 1006 OpARM64FMOVDload 1007 OpARM64MOVBstore 1008 OpARM64MOVHstore 1009 OpARM64MOVWstore 1010 OpARM64MOVDstore 1011 OpARM64STP 1012 OpARM64FMOVSstore 1013 OpARM64FMOVDstore 1014 OpARM64MOVBstorezero 1015 OpARM64MOVHstorezero 1016 OpARM64MOVWstorezero 1017 OpARM64MOVDstorezero 1018 OpARM64MOVQstorezero 1019 OpARM64MOVBreg 1020 OpARM64MOVBUreg 1021 OpARM64MOVHreg 1022 OpARM64MOVHUreg 1023 OpARM64MOVWreg 1024 OpARM64MOVWUreg 1025 OpARM64MOVDreg 1026 OpARM64MOVDnop 1027 OpARM64SCVTFWS 1028 OpARM64SCVTFWD 1029 OpARM64UCVTFWS 1030 OpARM64UCVTFWD 1031 OpARM64SCVTFS 1032 OpARM64SCVTFD 1033 OpARM64UCVTFS 1034 OpARM64UCVTFD 1035 OpARM64FCVTZSSW 1036 OpARM64FCVTZSDW 1037 OpARM64FCVTZUSW 1038 OpARM64FCVTZUDW 1039 OpARM64FCVTZSS 1040 OpARM64FCVTZSD 1041 OpARM64FCVTZUS 1042 OpARM64FCVTZUD 1043 OpARM64FCVTSD 1044 OpARM64FCVTDS 1045 OpARM64CSELULT 1046 OpARM64CSELULT0 1047 OpARM64CALLstatic 1048 OpARM64CALLclosure 1049 OpARM64CALLinter 1050 OpARM64LoweredNilCheck 1051 OpARM64Equal 1052 OpARM64NotEqual 1053 OpARM64LessThan 1054 OpARM64LessEqual 1055 OpARM64GreaterThan 1056 OpARM64GreaterEqual 1057 OpARM64LessThanU 1058 OpARM64LessEqualU 1059 OpARM64GreaterThanU 1060 OpARM64GreaterEqualU 1061 OpARM64DUFFZERO 1062 OpARM64LoweredZero 1063 OpARM64DUFFCOPY 1064 OpARM64LoweredMove 1065 OpARM64LoweredGetClosurePtr 1066 OpARM64MOVDconvert 1067 OpARM64FlagEQ 1068 OpARM64FlagLT_ULT 1069 OpARM64FlagLT_UGT 1070 OpARM64FlagGT_UGT 1071 OpARM64FlagGT_ULT 1072 OpARM64InvertFlags 1073 OpARM64LDAR 1074 OpARM64LDARW 1075 OpARM64STLR 1076 OpARM64STLRW 1077 OpARM64LoweredAtomicExchange64 1078 OpARM64LoweredAtomicExchange32 1079 OpARM64LoweredAtomicAdd64 1080 OpARM64LoweredAtomicAdd32 1081 OpARM64LoweredAtomicCas64 1082 OpARM64LoweredAtomicCas32 1083 OpARM64LoweredAtomicAnd8 1084 OpARM64LoweredAtomicOr8 1085 1086 OpMIPSADD 1087 OpMIPSADDconst 1088 OpMIPSSUB 1089 OpMIPSSUBconst 1090 OpMIPSMUL 1091 OpMIPSMULT 1092 OpMIPSMULTU 1093 OpMIPSDIV 1094 OpMIPSDIVU 1095 OpMIPSADDF 1096 OpMIPSADDD 1097 OpMIPSSUBF 1098 OpMIPSSUBD 1099 OpMIPSMULF 1100 OpMIPSMULD 1101 OpMIPSDIVF 1102 OpMIPSDIVD 1103 OpMIPSAND 1104 OpMIPSANDconst 1105 OpMIPSOR 1106 OpMIPSORconst 1107 OpMIPSXOR 1108 OpMIPSXORconst 1109 OpMIPSNOR 1110 OpMIPSNORconst 1111 OpMIPSNEG 1112 OpMIPSNEGF 1113 OpMIPSNEGD 1114 OpMIPSSQRTD 1115 OpMIPSSLL 1116 OpMIPSSLLconst 1117 OpMIPSSRL 1118 OpMIPSSRLconst 1119 OpMIPSSRA 1120 OpMIPSSRAconst 1121 OpMIPSCLZ 1122 OpMIPSSGT 1123 OpMIPSSGTconst 1124 OpMIPSSGTzero 1125 OpMIPSSGTU 1126 OpMIPSSGTUconst 1127 OpMIPSSGTUzero 1128 OpMIPSCMPEQF 1129 OpMIPSCMPEQD 1130 OpMIPSCMPGEF 1131 OpMIPSCMPGED 1132 OpMIPSCMPGTF 1133 OpMIPSCMPGTD 1134 OpMIPSMOVWconst 1135 OpMIPSMOVFconst 1136 OpMIPSMOVDconst 1137 OpMIPSMOVWaddr 1138 OpMIPSMOVBload 1139 OpMIPSMOVBUload 1140 OpMIPSMOVHload 1141 OpMIPSMOVHUload 1142 OpMIPSMOVWload 1143 OpMIPSMOVFload 1144 OpMIPSMOVDload 1145 OpMIPSMOVBstore 1146 OpMIPSMOVHstore 1147 OpMIPSMOVWstore 1148 OpMIPSMOVFstore 1149 OpMIPSMOVDstore 1150 OpMIPSMOVBstorezero 1151 OpMIPSMOVHstorezero 1152 OpMIPSMOVWstorezero 1153 OpMIPSMOVBreg 1154 OpMIPSMOVBUreg 1155 OpMIPSMOVHreg 1156 OpMIPSMOVHUreg 1157 OpMIPSMOVWreg 1158 OpMIPSMOVWnop 1159 OpMIPSCMOVZ 1160 OpMIPSCMOVZzero 1161 OpMIPSMOVWF 1162 OpMIPSMOVWD 1163 OpMIPSTRUNCFW 1164 OpMIPSTRUNCDW 1165 OpMIPSMOVFD 1166 OpMIPSMOVDF 1167 OpMIPSCALLstatic 1168 OpMIPSCALLclosure 1169 OpMIPSCALLinter 1170 OpMIPSLoweredAtomicLoad 1171 OpMIPSLoweredAtomicStore 1172 OpMIPSLoweredAtomicStorezero 1173 OpMIPSLoweredAtomicExchange 1174 OpMIPSLoweredAtomicAdd 1175 OpMIPSLoweredAtomicAddconst 1176 OpMIPSLoweredAtomicCas 1177 OpMIPSLoweredAtomicAnd 1178 OpMIPSLoweredAtomicOr 1179 OpMIPSLoweredZero 1180 OpMIPSLoweredMove 1181 OpMIPSLoweredNilCheck 1182 OpMIPSFPFlagTrue 1183 OpMIPSFPFlagFalse 1184 OpMIPSLoweredGetClosurePtr 1185 OpMIPSMOVWconvert 1186 1187 OpMIPS64ADDV 1188 OpMIPS64ADDVconst 1189 OpMIPS64SUBV 1190 OpMIPS64SUBVconst 1191 OpMIPS64MULV 1192 OpMIPS64MULVU 1193 OpMIPS64DIVV 1194 OpMIPS64DIVVU 1195 OpMIPS64ADDF 1196 OpMIPS64ADDD 1197 OpMIPS64SUBF 1198 OpMIPS64SUBD 1199 OpMIPS64MULF 1200 OpMIPS64MULD 1201 OpMIPS64DIVF 1202 OpMIPS64DIVD 1203 OpMIPS64AND 1204 OpMIPS64ANDconst 1205 OpMIPS64OR 1206 OpMIPS64ORconst 1207 OpMIPS64XOR 1208 OpMIPS64XORconst 1209 OpMIPS64NOR 1210 OpMIPS64NORconst 1211 OpMIPS64NEGV 1212 OpMIPS64NEGF 1213 OpMIPS64NEGD 1214 OpMIPS64SLLV 1215 OpMIPS64SLLVconst 1216 OpMIPS64SRLV 1217 OpMIPS64SRLVconst 1218 OpMIPS64SRAV 1219 OpMIPS64SRAVconst 1220 OpMIPS64SGT 1221 OpMIPS64SGTconst 1222 OpMIPS64SGTU 1223 OpMIPS64SGTUconst 1224 OpMIPS64CMPEQF 1225 OpMIPS64CMPEQD 1226 OpMIPS64CMPGEF 1227 OpMIPS64CMPGED 1228 OpMIPS64CMPGTF 1229 OpMIPS64CMPGTD 1230 OpMIPS64MOVVconst 1231 OpMIPS64MOVFconst 1232 OpMIPS64MOVDconst 1233 OpMIPS64MOVVaddr 1234 OpMIPS64MOVBload 1235 OpMIPS64MOVBUload 1236 OpMIPS64MOVHload 1237 OpMIPS64MOVHUload 1238 OpMIPS64MOVWload 1239 OpMIPS64MOVWUload 1240 OpMIPS64MOVVload 1241 OpMIPS64MOVFload 1242 OpMIPS64MOVDload 1243 OpMIPS64MOVBstore 1244 OpMIPS64MOVHstore 1245 OpMIPS64MOVWstore 1246 OpMIPS64MOVVstore 1247 OpMIPS64MOVFstore 1248 OpMIPS64MOVDstore 1249 OpMIPS64MOVBstorezero 1250 OpMIPS64MOVHstorezero 1251 OpMIPS64MOVWstorezero 1252 OpMIPS64MOVVstorezero 1253 OpMIPS64MOVBreg 1254 OpMIPS64MOVBUreg 1255 OpMIPS64MOVHreg 1256 OpMIPS64MOVHUreg 1257 OpMIPS64MOVWreg 1258 OpMIPS64MOVWUreg 1259 OpMIPS64MOVVreg 1260 OpMIPS64MOVVnop 1261 OpMIPS64MOVWF 1262 OpMIPS64MOVWD 1263 OpMIPS64MOVVF 1264 OpMIPS64MOVVD 1265 OpMIPS64TRUNCFW 1266 OpMIPS64TRUNCDW 1267 OpMIPS64TRUNCFV 1268 OpMIPS64TRUNCDV 1269 OpMIPS64MOVFD 1270 OpMIPS64MOVDF 1271 OpMIPS64CALLstatic 1272 OpMIPS64CALLclosure 1273 OpMIPS64CALLinter 1274 OpMIPS64DUFFZERO 1275 OpMIPS64LoweredZero 1276 OpMIPS64LoweredMove 1277 OpMIPS64LoweredNilCheck 1278 OpMIPS64FPFlagTrue 1279 OpMIPS64FPFlagFalse 1280 OpMIPS64LoweredGetClosurePtr 1281 OpMIPS64MOVVconvert 1282 1283 OpPPC64ADD 1284 OpPPC64ADDconst 1285 OpPPC64FADD 1286 OpPPC64FADDS 1287 OpPPC64SUB 1288 OpPPC64FSUB 1289 OpPPC64FSUBS 1290 OpPPC64MULLD 1291 OpPPC64MULLW 1292 OpPPC64MULHD 1293 OpPPC64MULHW 1294 OpPPC64MULHDU 1295 OpPPC64MULHWU 1296 OpPPC64FMUL 1297 OpPPC64FMULS 1298 OpPPC64FMADD 1299 OpPPC64FMADDS 1300 OpPPC64FMSUB 1301 OpPPC64FMSUBS 1302 OpPPC64SRAD 1303 OpPPC64SRAW 1304 OpPPC64SRD 1305 OpPPC64SRW 1306 OpPPC64SLD 1307 OpPPC64SLW 1308 OpPPC64ADDconstForCarry 1309 OpPPC64MaskIfNotCarry 1310 OpPPC64SRADconst 1311 OpPPC64SRAWconst 1312 OpPPC64SRDconst 1313 OpPPC64SRWconst 1314 OpPPC64SLDconst 1315 OpPPC64SLWconst 1316 OpPPC64ROTLconst 1317 OpPPC64ROTLWconst 1318 OpPPC64CNTLZD 1319 OpPPC64CNTLZW 1320 OpPPC64POPCNTD 1321 OpPPC64POPCNTW 1322 OpPPC64POPCNTB 1323 OpPPC64FDIV 1324 OpPPC64FDIVS 1325 OpPPC64DIVD 1326 OpPPC64DIVW 1327 OpPPC64DIVDU 1328 OpPPC64DIVWU 1329 OpPPC64FCTIDZ 1330 OpPPC64FCTIWZ 1331 OpPPC64FCFID 1332 OpPPC64FRSP 1333 OpPPC64Xf2i64 1334 OpPPC64Xi2f64 1335 OpPPC64AND 1336 OpPPC64ANDN 1337 OpPPC64OR 1338 OpPPC64ORN 1339 OpPPC64NOR 1340 OpPPC64XOR 1341 OpPPC64EQV 1342 OpPPC64NEG 1343 OpPPC64FNEG 1344 OpPPC64FSQRT 1345 OpPPC64FSQRTS 1346 OpPPC64FFLOOR 1347 OpPPC64FCEIL 1348 OpPPC64FTRUNC 1349 OpPPC64ORconst 1350 OpPPC64XORconst 1351 OpPPC64ANDconst 1352 OpPPC64ANDCCconst 1353 OpPPC64MOVBreg 1354 OpPPC64MOVBZreg 1355 OpPPC64MOVHreg 1356 OpPPC64MOVHZreg 1357 OpPPC64MOVWreg 1358 OpPPC64MOVWZreg 1359 OpPPC64MOVBZload 1360 OpPPC64MOVHload 1361 OpPPC64MOVHZload 1362 OpPPC64MOVWload 1363 OpPPC64MOVWZload 1364 OpPPC64MOVDload 1365 OpPPC64FMOVDload 1366 OpPPC64FMOVSload 1367 OpPPC64MOVBstore 1368 OpPPC64MOVHstore 1369 OpPPC64MOVWstore 1370 OpPPC64MOVDstore 1371 OpPPC64FMOVDstore 1372 OpPPC64FMOVSstore 1373 OpPPC64MOVBstorezero 1374 OpPPC64MOVHstorezero 1375 OpPPC64MOVWstorezero 1376 OpPPC64MOVDstorezero 1377 OpPPC64MOVDaddr 1378 OpPPC64MOVDconst 1379 OpPPC64FMOVDconst 1380 OpPPC64FMOVSconst 1381 OpPPC64FCMPU 1382 OpPPC64CMP 1383 OpPPC64CMPU 1384 OpPPC64CMPW 1385 OpPPC64CMPWU 1386 OpPPC64CMPconst 1387 OpPPC64CMPUconst 1388 OpPPC64CMPWconst 1389 OpPPC64CMPWUconst 1390 OpPPC64Equal 1391 OpPPC64NotEqual 1392 OpPPC64LessThan 1393 OpPPC64FLessThan 1394 OpPPC64LessEqual 1395 OpPPC64FLessEqual 1396 OpPPC64GreaterThan 1397 OpPPC64FGreaterThan 1398 OpPPC64GreaterEqual 1399 OpPPC64FGreaterEqual 1400 OpPPC64LoweredGetClosurePtr 1401 OpPPC64LoweredNilCheck 1402 OpPPC64LoweredRound32F 1403 OpPPC64LoweredRound64F 1404 OpPPC64MOVDconvert 1405 OpPPC64CALLstatic 1406 OpPPC64CALLclosure 1407 OpPPC64CALLinter 1408 OpPPC64LoweredZero 1409 OpPPC64LoweredMove 1410 OpPPC64LoweredAtomicStore32 1411 OpPPC64LoweredAtomicStore64 1412 OpPPC64LoweredAtomicLoad32 1413 OpPPC64LoweredAtomicLoad64 1414 OpPPC64LoweredAtomicLoadPtr 1415 OpPPC64LoweredAtomicAdd32 1416 OpPPC64LoweredAtomicAdd64 1417 OpPPC64LoweredAtomicExchange32 1418 OpPPC64LoweredAtomicExchange64 1419 OpPPC64LoweredAtomicCas64 1420 OpPPC64LoweredAtomicCas32 1421 OpPPC64LoweredAtomicAnd8 1422 OpPPC64LoweredAtomicOr8 1423 OpPPC64InvertFlags 1424 OpPPC64FlagEQ 1425 OpPPC64FlagLT 1426 OpPPC64FlagGT 1427 1428 OpS390XFADDS 1429 OpS390XFADD 1430 OpS390XFSUBS 1431 OpS390XFSUB 1432 OpS390XFMULS 1433 OpS390XFMUL 1434 OpS390XFDIVS 1435 OpS390XFDIV 1436 OpS390XFNEGS 1437 OpS390XFNEG 1438 OpS390XFMADDS 1439 OpS390XFMADD 1440 OpS390XFMSUBS 1441 OpS390XFMSUB 1442 OpS390XFMOVSload 1443 OpS390XFMOVDload 1444 OpS390XFMOVSconst 1445 OpS390XFMOVDconst 1446 OpS390XFMOVSloadidx 1447 OpS390XFMOVDloadidx 1448 OpS390XFMOVSstore 1449 OpS390XFMOVDstore 1450 OpS390XFMOVSstoreidx 1451 OpS390XFMOVDstoreidx 1452 OpS390XADD 1453 OpS390XADDW 1454 OpS390XADDconst 1455 OpS390XADDWconst 1456 OpS390XADDload 1457 OpS390XADDWload 1458 OpS390XSUB 1459 OpS390XSUBW 1460 OpS390XSUBconst 1461 OpS390XSUBWconst 1462 OpS390XSUBload 1463 OpS390XSUBWload 1464 OpS390XMULLD 1465 OpS390XMULLW 1466 OpS390XMULLDconst 1467 OpS390XMULLWconst 1468 OpS390XMULLDload 1469 OpS390XMULLWload 1470 OpS390XMULHD 1471 OpS390XMULHDU 1472 OpS390XDIVD 1473 OpS390XDIVW 1474 OpS390XDIVDU 1475 OpS390XDIVWU 1476 OpS390XMODD 1477 OpS390XMODW 1478 OpS390XMODDU 1479 OpS390XMODWU 1480 OpS390XAND 1481 OpS390XANDW 1482 OpS390XANDconst 1483 OpS390XANDWconst 1484 OpS390XANDload 1485 OpS390XANDWload 1486 OpS390XOR 1487 OpS390XORW 1488 OpS390XORconst 1489 OpS390XORWconst 1490 OpS390XORload 1491 OpS390XORWload 1492 OpS390XXOR 1493 OpS390XXORW 1494 OpS390XXORconst 1495 OpS390XXORWconst 1496 OpS390XXORload 1497 OpS390XXORWload 1498 OpS390XCMP 1499 OpS390XCMPW 1500 OpS390XCMPU 1501 OpS390XCMPWU 1502 OpS390XCMPconst 1503 OpS390XCMPWconst 1504 OpS390XCMPUconst 1505 OpS390XCMPWUconst 1506 OpS390XFCMPS 1507 OpS390XFCMP 1508 OpS390XSLD 1509 OpS390XSLW 1510 OpS390XSLDconst 1511 OpS390XSLWconst 1512 OpS390XSRD 1513 OpS390XSRW 1514 OpS390XSRDconst 1515 OpS390XSRWconst 1516 OpS390XSRAD 1517 OpS390XSRAW 1518 OpS390XSRADconst 1519 OpS390XSRAWconst 1520 OpS390XRLLGconst 1521 OpS390XRLLconst 1522 OpS390XNEG 1523 OpS390XNEGW 1524 OpS390XNOT 1525 OpS390XNOTW 1526 OpS390XFSQRT 1527 OpS390XSUBEcarrymask 1528 OpS390XSUBEWcarrymask 1529 OpS390XMOVDEQ 1530 OpS390XMOVDNE 1531 OpS390XMOVDLT 1532 OpS390XMOVDLE 1533 OpS390XMOVDGT 1534 OpS390XMOVDGE 1535 OpS390XMOVDGTnoinv 1536 OpS390XMOVDGEnoinv 1537 OpS390XMOVBreg 1538 OpS390XMOVBZreg 1539 OpS390XMOVHreg 1540 OpS390XMOVHZreg 1541 OpS390XMOVWreg 1542 OpS390XMOVWZreg 1543 OpS390XMOVDreg 1544 OpS390XMOVDnop 1545 OpS390XMOVDconst 1546 OpS390XCFDBRA 1547 OpS390XCGDBRA 1548 OpS390XCFEBRA 1549 OpS390XCGEBRA 1550 OpS390XCEFBRA 1551 OpS390XCDFBRA 1552 OpS390XCEGBRA 1553 OpS390XCDGBRA 1554 OpS390XLEDBR 1555 OpS390XLDEBR 1556 OpS390XMOVDaddr 1557 OpS390XMOVDaddridx 1558 OpS390XMOVBZload 1559 OpS390XMOVBload 1560 OpS390XMOVHZload 1561 OpS390XMOVHload 1562 OpS390XMOVWZload 1563 OpS390XMOVWload 1564 OpS390XMOVDload 1565 OpS390XMOVWBR 1566 OpS390XMOVDBR 1567 OpS390XMOVHBRload 1568 OpS390XMOVWBRload 1569 OpS390XMOVDBRload 1570 OpS390XMOVBstore 1571 OpS390XMOVHstore 1572 OpS390XMOVWstore 1573 OpS390XMOVDstore 1574 OpS390XMOVHBRstore 1575 OpS390XMOVWBRstore 1576 OpS390XMOVDBRstore 1577 OpS390XMVC 1578 OpS390XMOVBZloadidx 1579 OpS390XMOVHZloadidx 1580 OpS390XMOVWZloadidx 1581 OpS390XMOVDloadidx 1582 OpS390XMOVHBRloadidx 1583 OpS390XMOVWBRloadidx 1584 OpS390XMOVDBRloadidx 1585 OpS390XMOVBstoreidx 1586 OpS390XMOVHstoreidx 1587 OpS390XMOVWstoreidx 1588 OpS390XMOVDstoreidx 1589 OpS390XMOVHBRstoreidx 1590 OpS390XMOVWBRstoreidx 1591 OpS390XMOVDBRstoreidx 1592 OpS390XMOVBstoreconst 1593 OpS390XMOVHstoreconst 1594 OpS390XMOVWstoreconst 1595 OpS390XMOVDstoreconst 1596 OpS390XCLEAR 1597 OpS390XCALLstatic 1598 OpS390XCALLclosure 1599 OpS390XCALLinter 1600 OpS390XInvertFlags 1601 OpS390XLoweredGetG 1602 OpS390XLoweredGetClosurePtr 1603 OpS390XLoweredNilCheck 1604 OpS390XLoweredRound32F 1605 OpS390XLoweredRound64F 1606 OpS390XMOVDconvert 1607 OpS390XFlagEQ 1608 OpS390XFlagLT 1609 OpS390XFlagGT 1610 OpS390XMOVWZatomicload 1611 OpS390XMOVDatomicload 1612 OpS390XMOVWatomicstore 1613 OpS390XMOVDatomicstore 1614 OpS390XLAA 1615 OpS390XLAAG 1616 OpS390XAddTupleFirst32 1617 OpS390XAddTupleFirst64 1618 OpS390XLoweredAtomicCas32 1619 OpS390XLoweredAtomicCas64 1620 OpS390XLoweredAtomicExchange32 1621 OpS390XLoweredAtomicExchange64 1622 OpS390XFLOGR 1623 OpS390XSTMG2 1624 OpS390XSTMG3 1625 OpS390XSTMG4 1626 OpS390XSTM2 1627 OpS390XSTM3 1628 OpS390XSTM4 1629 OpS390XLoweredMove 1630 OpS390XLoweredZero 1631 1632 OpAdd8 1633 OpAdd16 1634 OpAdd32 1635 OpAdd64 1636 OpAddPtr 1637 OpAdd32F 1638 OpAdd64F 1639 OpSub8 1640 OpSub16 1641 OpSub32 1642 OpSub64 1643 OpSubPtr 1644 OpSub32F 1645 OpSub64F 1646 OpMul8 1647 OpMul16 1648 OpMul32 1649 OpMul64 1650 OpMul32F 1651 OpMul64F 1652 OpDiv32F 1653 OpDiv64F 1654 OpHmul32 1655 OpHmul32u 1656 OpHmul64 1657 OpHmul64u 1658 OpMul32uhilo 1659 OpMul64uhilo 1660 OpAvg32u 1661 OpAvg64u 1662 OpDiv8 1663 OpDiv8u 1664 OpDiv16 1665 OpDiv16u 1666 OpDiv32 1667 OpDiv32u 1668 OpDiv64 1669 OpDiv64u 1670 OpDiv128u 1671 OpMod8 1672 OpMod8u 1673 OpMod16 1674 OpMod16u 1675 OpMod32 1676 OpMod32u 1677 OpMod64 1678 OpMod64u 1679 OpAnd8 1680 OpAnd16 1681 OpAnd32 1682 OpAnd64 1683 OpOr8 1684 OpOr16 1685 OpOr32 1686 OpOr64 1687 OpXor8 1688 OpXor16 1689 OpXor32 1690 OpXor64 1691 OpLsh8x8 1692 OpLsh8x16 1693 OpLsh8x32 1694 OpLsh8x64 1695 OpLsh16x8 1696 OpLsh16x16 1697 OpLsh16x32 1698 OpLsh16x64 1699 OpLsh32x8 1700 OpLsh32x16 1701 OpLsh32x32 1702 OpLsh32x64 1703 OpLsh64x8 1704 OpLsh64x16 1705 OpLsh64x32 1706 OpLsh64x64 1707 OpRsh8x8 1708 OpRsh8x16 1709 OpRsh8x32 1710 OpRsh8x64 1711 OpRsh16x8 1712 OpRsh16x16 1713 OpRsh16x32 1714 OpRsh16x64 1715 OpRsh32x8 1716 OpRsh32x16 1717 OpRsh32x32 1718 OpRsh32x64 1719 OpRsh64x8 1720 OpRsh64x16 1721 OpRsh64x32 1722 OpRsh64x64 1723 OpRsh8Ux8 1724 OpRsh8Ux16 1725 OpRsh8Ux32 1726 OpRsh8Ux64 1727 OpRsh16Ux8 1728 OpRsh16Ux16 1729 OpRsh16Ux32 1730 OpRsh16Ux64 1731 OpRsh32Ux8 1732 OpRsh32Ux16 1733 OpRsh32Ux32 1734 OpRsh32Ux64 1735 OpRsh64Ux8 1736 OpRsh64Ux16 1737 OpRsh64Ux32 1738 OpRsh64Ux64 1739 OpEq8 1740 OpEq16 1741 OpEq32 1742 OpEq64 1743 OpEqPtr 1744 OpEqInter 1745 OpEqSlice 1746 OpEq32F 1747 OpEq64F 1748 OpNeq8 1749 OpNeq16 1750 OpNeq32 1751 OpNeq64 1752 OpNeqPtr 1753 OpNeqInter 1754 OpNeqSlice 1755 OpNeq32F 1756 OpNeq64F 1757 OpLess8 1758 OpLess8U 1759 OpLess16 1760 OpLess16U 1761 OpLess32 1762 OpLess32U 1763 OpLess64 1764 OpLess64U 1765 OpLess32F 1766 OpLess64F 1767 OpLeq8 1768 OpLeq8U 1769 OpLeq16 1770 OpLeq16U 1771 OpLeq32 1772 OpLeq32U 1773 OpLeq64 1774 OpLeq64U 1775 OpLeq32F 1776 OpLeq64F 1777 OpGreater8 1778 OpGreater8U 1779 OpGreater16 1780 OpGreater16U 1781 OpGreater32 1782 OpGreater32U 1783 OpGreater64 1784 OpGreater64U 1785 OpGreater32F 1786 OpGreater64F 1787 OpGeq8 1788 OpGeq8U 1789 OpGeq16 1790 OpGeq16U 1791 OpGeq32 1792 OpGeq32U 1793 OpGeq64 1794 OpGeq64U 1795 OpGeq32F 1796 OpGeq64F 1797 OpAndB 1798 OpOrB 1799 OpEqB 1800 OpNeqB 1801 OpNot 1802 OpNeg8 1803 OpNeg16 1804 OpNeg32 1805 OpNeg64 1806 OpNeg32F 1807 OpNeg64F 1808 OpCom8 1809 OpCom16 1810 OpCom32 1811 OpCom64 1812 OpCtz32 1813 OpCtz64 1814 OpBitLen32 1815 OpBitLen64 1816 OpBswap32 1817 OpBswap64 1818 OpBitRev8 1819 OpBitRev16 1820 OpBitRev32 1821 OpBitRev64 1822 OpPopCount8 1823 OpPopCount16 1824 OpPopCount32 1825 OpPopCount64 1826 OpSqrt 1827 OpFloor 1828 OpCeil 1829 OpTrunc 1830 OpPhi 1831 OpCopy 1832 OpConvert 1833 OpConstBool 1834 OpConstString 1835 OpConstNil 1836 OpConst8 1837 OpConst16 1838 OpConst32 1839 OpConst64 1840 OpConst32F 1841 OpConst64F 1842 OpConstInterface 1843 OpConstSlice 1844 OpInitMem 1845 OpArg 1846 OpAddr 1847 OpSP 1848 OpSB 1849 OpLoad 1850 OpStore 1851 OpMove 1852 OpZero 1853 OpStoreWB 1854 OpMoveWB 1855 OpZeroWB 1856 OpClosureCall 1857 OpStaticCall 1858 OpInterCall 1859 OpSignExt8to16 1860 OpSignExt8to32 1861 OpSignExt8to64 1862 OpSignExt16to32 1863 OpSignExt16to64 1864 OpSignExt32to64 1865 OpZeroExt8to16 1866 OpZeroExt8to32 1867 OpZeroExt8to64 1868 OpZeroExt16to32 1869 OpZeroExt16to64 1870 OpZeroExt32to64 1871 OpTrunc16to8 1872 OpTrunc32to8 1873 OpTrunc32to16 1874 OpTrunc64to8 1875 OpTrunc64to16 1876 OpTrunc64to32 1877 OpCvt32to32F 1878 OpCvt32to64F 1879 OpCvt64to32F 1880 OpCvt64to64F 1881 OpCvt32Fto32 1882 OpCvt32Fto64 1883 OpCvt64Fto32 1884 OpCvt64Fto64 1885 OpCvt32Fto64F 1886 OpCvt64Fto32F 1887 OpRound32F 1888 OpRound64F 1889 OpIsNonNil 1890 OpIsInBounds 1891 OpIsSliceInBounds 1892 OpNilCheck 1893 OpGetG 1894 OpGetClosurePtr 1895 OpPtrIndex 1896 OpOffPtr 1897 OpSliceMake 1898 OpSlicePtr 1899 OpSliceLen 1900 OpSliceCap 1901 OpComplexMake 1902 OpComplexReal 1903 OpComplexImag 1904 OpStringMake 1905 OpStringPtr 1906 OpStringLen 1907 OpIMake 1908 OpITab 1909 OpIData 1910 OpStructMake0 1911 OpStructMake1 1912 OpStructMake2 1913 OpStructMake3 1914 OpStructMake4 1915 OpStructSelect 1916 OpArrayMake0 1917 OpArrayMake1 1918 OpArraySelect 1919 OpStoreReg 1920 OpLoadReg 1921 OpFwdRef 1922 OpUnknown 1923 OpVarDef 1924 OpVarKill 1925 OpVarLive 1926 OpKeepAlive 1927 OpRegKill 1928 OpInt64Make 1929 OpInt64Hi 1930 OpInt64Lo 1931 OpAdd32carry 1932 OpAdd32withcarry 1933 OpSub32carry 1934 OpSub32withcarry 1935 OpSignmask 1936 OpZeromask 1937 OpSlicemask 1938 OpCvt32Uto32F 1939 OpCvt32Uto64F 1940 OpCvt32Fto32U 1941 OpCvt64Fto32U 1942 OpCvt64Uto32F 1943 OpCvt64Uto64F 1944 OpCvt32Fto64U 1945 OpCvt64Fto64U 1946 OpSelect0 1947 OpSelect1 1948 OpAtomicLoad32 1949 OpAtomicLoad64 1950 OpAtomicLoadPtr 1951 OpAtomicStore32 1952 OpAtomicStore64 1953 OpAtomicStorePtrNoWB 1954 OpAtomicExchange32 1955 OpAtomicExchange64 1956 OpAtomicAdd32 1957 OpAtomicAdd64 1958 OpAtomicCompareAndSwap32 1959 OpAtomicCompareAndSwap64 1960 OpAtomicAnd8 1961 OpAtomicOr8 1962 OpClobber 1963 ) 1964 1965 var opcodeTable = [...]opInfo{ 1966 {name: "OpInvalid"}, 1967 1968 { 1969 name: "ADDSS", 1970 argLen: 2, 1971 commutative: true, 1972 resultInArg0: true, 1973 usesScratch: true, 1974 asm: x86.AADDSS, 1975 reg: regInfo{ 1976 inputs: []inputInfo{ 1977 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1978 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1979 }, 1980 outputs: []outputInfo{ 1981 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1982 }, 1983 }, 1984 }, 1985 { 1986 name: "ADDSD", 1987 argLen: 2, 1988 commutative: true, 1989 resultInArg0: true, 1990 asm: x86.AADDSD, 1991 reg: regInfo{ 1992 inputs: []inputInfo{ 1993 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1994 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1995 }, 1996 outputs: []outputInfo{ 1997 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1998 }, 1999 }, 2000 }, 2001 { 2002 name: "SUBSS", 2003 argLen: 2, 2004 resultInArg0: true, 2005 usesScratch: true, 2006 asm: x86.ASUBSS, 2007 reg: regInfo{ 2008 inputs: []inputInfo{ 2009 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2010 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2011 }, 2012 outputs: []outputInfo{ 2013 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2014 }, 2015 }, 2016 }, 2017 { 2018 name: "SUBSD", 2019 argLen: 2, 2020 resultInArg0: true, 2021 asm: x86.ASUBSD, 2022 reg: regInfo{ 2023 inputs: []inputInfo{ 2024 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2025 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2026 }, 2027 outputs: []outputInfo{ 2028 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2029 }, 2030 }, 2031 }, 2032 { 2033 name: "MULSS", 2034 argLen: 2, 2035 commutative: true, 2036 resultInArg0: true, 2037 usesScratch: true, 2038 asm: x86.AMULSS, 2039 reg: regInfo{ 2040 inputs: []inputInfo{ 2041 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2042 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2043 }, 2044 outputs: []outputInfo{ 2045 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2046 }, 2047 }, 2048 }, 2049 { 2050 name: "MULSD", 2051 argLen: 2, 2052 commutative: true, 2053 resultInArg0: true, 2054 asm: x86.AMULSD, 2055 reg: regInfo{ 2056 inputs: []inputInfo{ 2057 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2058 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2059 }, 2060 outputs: []outputInfo{ 2061 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2062 }, 2063 }, 2064 }, 2065 { 2066 name: "DIVSS", 2067 argLen: 2, 2068 resultInArg0: true, 2069 usesScratch: true, 2070 asm: x86.ADIVSS, 2071 reg: regInfo{ 2072 inputs: []inputInfo{ 2073 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2074 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2075 }, 2076 outputs: []outputInfo{ 2077 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2078 }, 2079 }, 2080 }, 2081 { 2082 name: "DIVSD", 2083 argLen: 2, 2084 resultInArg0: true, 2085 asm: x86.ADIVSD, 2086 reg: regInfo{ 2087 inputs: []inputInfo{ 2088 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2089 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2090 }, 2091 outputs: []outputInfo{ 2092 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2093 }, 2094 }, 2095 }, 2096 { 2097 name: "MOVSSload", 2098 auxType: auxSymOff, 2099 argLen: 2, 2100 faultOnNilArg0: true, 2101 symEffect: SymRead, 2102 asm: x86.AMOVSS, 2103 reg: regInfo{ 2104 inputs: []inputInfo{ 2105 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2106 }, 2107 outputs: []outputInfo{ 2108 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2109 }, 2110 }, 2111 }, 2112 { 2113 name: "MOVSDload", 2114 auxType: auxSymOff, 2115 argLen: 2, 2116 faultOnNilArg0: true, 2117 symEffect: SymRead, 2118 asm: x86.AMOVSD, 2119 reg: regInfo{ 2120 inputs: []inputInfo{ 2121 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2122 }, 2123 outputs: []outputInfo{ 2124 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2125 }, 2126 }, 2127 }, 2128 { 2129 name: "MOVSSconst", 2130 auxType: auxFloat32, 2131 argLen: 0, 2132 rematerializeable: true, 2133 asm: x86.AMOVSS, 2134 reg: regInfo{ 2135 outputs: []outputInfo{ 2136 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2137 }, 2138 }, 2139 }, 2140 { 2141 name: "MOVSDconst", 2142 auxType: auxFloat64, 2143 argLen: 0, 2144 rematerializeable: true, 2145 asm: x86.AMOVSD, 2146 reg: regInfo{ 2147 outputs: []outputInfo{ 2148 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2149 }, 2150 }, 2151 }, 2152 { 2153 name: "MOVSSloadidx1", 2154 auxType: auxSymOff, 2155 argLen: 3, 2156 symEffect: SymRead, 2157 asm: x86.AMOVSS, 2158 reg: regInfo{ 2159 inputs: []inputInfo{ 2160 {1, 255}, // AX CX DX BX SP BP SI DI 2161 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2162 }, 2163 outputs: []outputInfo{ 2164 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2165 }, 2166 }, 2167 }, 2168 { 2169 name: "MOVSSloadidx4", 2170 auxType: auxSymOff, 2171 argLen: 3, 2172 symEffect: SymRead, 2173 asm: x86.AMOVSS, 2174 reg: regInfo{ 2175 inputs: []inputInfo{ 2176 {1, 255}, // AX CX DX BX SP BP SI DI 2177 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2178 }, 2179 outputs: []outputInfo{ 2180 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2181 }, 2182 }, 2183 }, 2184 { 2185 name: "MOVSDloadidx1", 2186 auxType: auxSymOff, 2187 argLen: 3, 2188 symEffect: SymRead, 2189 asm: x86.AMOVSD, 2190 reg: regInfo{ 2191 inputs: []inputInfo{ 2192 {1, 255}, // AX CX DX BX SP BP SI DI 2193 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2194 }, 2195 outputs: []outputInfo{ 2196 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2197 }, 2198 }, 2199 }, 2200 { 2201 name: "MOVSDloadidx8", 2202 auxType: auxSymOff, 2203 argLen: 3, 2204 symEffect: SymRead, 2205 asm: x86.AMOVSD, 2206 reg: regInfo{ 2207 inputs: []inputInfo{ 2208 {1, 255}, // AX CX DX BX SP BP SI DI 2209 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2210 }, 2211 outputs: []outputInfo{ 2212 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2213 }, 2214 }, 2215 }, 2216 { 2217 name: "MOVSSstore", 2218 auxType: auxSymOff, 2219 argLen: 3, 2220 faultOnNilArg0: true, 2221 symEffect: SymWrite, 2222 asm: x86.AMOVSS, 2223 reg: regInfo{ 2224 inputs: []inputInfo{ 2225 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2226 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2227 }, 2228 }, 2229 }, 2230 { 2231 name: "MOVSDstore", 2232 auxType: auxSymOff, 2233 argLen: 3, 2234 faultOnNilArg0: true, 2235 symEffect: SymWrite, 2236 asm: x86.AMOVSD, 2237 reg: regInfo{ 2238 inputs: []inputInfo{ 2239 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2240 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2241 }, 2242 }, 2243 }, 2244 { 2245 name: "MOVSSstoreidx1", 2246 auxType: auxSymOff, 2247 argLen: 4, 2248 symEffect: SymWrite, 2249 asm: x86.AMOVSS, 2250 reg: regInfo{ 2251 inputs: []inputInfo{ 2252 {1, 255}, // AX CX DX BX SP BP SI DI 2253 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2254 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2255 }, 2256 }, 2257 }, 2258 { 2259 name: "MOVSSstoreidx4", 2260 auxType: auxSymOff, 2261 argLen: 4, 2262 symEffect: SymWrite, 2263 asm: x86.AMOVSS, 2264 reg: regInfo{ 2265 inputs: []inputInfo{ 2266 {1, 255}, // AX CX DX BX SP BP SI DI 2267 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2268 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2269 }, 2270 }, 2271 }, 2272 { 2273 name: "MOVSDstoreidx1", 2274 auxType: auxSymOff, 2275 argLen: 4, 2276 symEffect: SymWrite, 2277 asm: x86.AMOVSD, 2278 reg: regInfo{ 2279 inputs: []inputInfo{ 2280 {1, 255}, // AX CX DX BX SP BP SI DI 2281 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2282 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2283 }, 2284 }, 2285 }, 2286 { 2287 name: "MOVSDstoreidx8", 2288 auxType: auxSymOff, 2289 argLen: 4, 2290 symEffect: SymWrite, 2291 asm: x86.AMOVSD, 2292 reg: regInfo{ 2293 inputs: []inputInfo{ 2294 {1, 255}, // AX CX DX BX SP BP SI DI 2295 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2296 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2297 }, 2298 }, 2299 }, 2300 { 2301 name: "ADDL", 2302 argLen: 2, 2303 commutative: true, 2304 clobberFlags: true, 2305 asm: x86.AADDL, 2306 reg: regInfo{ 2307 inputs: []inputInfo{ 2308 {1, 239}, // AX CX DX BX BP SI DI 2309 {0, 255}, // AX CX DX BX SP BP SI DI 2310 }, 2311 outputs: []outputInfo{ 2312 {0, 239}, // AX CX DX BX BP SI DI 2313 }, 2314 }, 2315 }, 2316 { 2317 name: "ADDLconst", 2318 auxType: auxInt32, 2319 argLen: 1, 2320 clobberFlags: true, 2321 asm: x86.AADDL, 2322 reg: regInfo{ 2323 inputs: []inputInfo{ 2324 {0, 255}, // AX CX DX BX SP BP SI DI 2325 }, 2326 outputs: []outputInfo{ 2327 {0, 239}, // AX CX DX BX BP SI DI 2328 }, 2329 }, 2330 }, 2331 { 2332 name: "ADDLcarry", 2333 argLen: 2, 2334 commutative: true, 2335 resultInArg0: true, 2336 asm: x86.AADDL, 2337 reg: regInfo{ 2338 inputs: []inputInfo{ 2339 {0, 239}, // AX CX DX BX BP SI DI 2340 {1, 239}, // AX CX DX BX BP SI DI 2341 }, 2342 outputs: []outputInfo{ 2343 {1, 0}, 2344 {0, 239}, // AX CX DX BX BP SI DI 2345 }, 2346 }, 2347 }, 2348 { 2349 name: "ADDLconstcarry", 2350 auxType: auxInt32, 2351 argLen: 1, 2352 resultInArg0: true, 2353 asm: x86.AADDL, 2354 reg: regInfo{ 2355 inputs: []inputInfo{ 2356 {0, 239}, // AX CX DX BX BP SI DI 2357 }, 2358 outputs: []outputInfo{ 2359 {1, 0}, 2360 {0, 239}, // AX CX DX BX BP SI DI 2361 }, 2362 }, 2363 }, 2364 { 2365 name: "ADCL", 2366 argLen: 3, 2367 commutative: true, 2368 resultInArg0: true, 2369 clobberFlags: true, 2370 asm: x86.AADCL, 2371 reg: regInfo{ 2372 inputs: []inputInfo{ 2373 {0, 239}, // AX CX DX BX BP SI DI 2374 {1, 239}, // AX CX DX BX BP SI DI 2375 }, 2376 outputs: []outputInfo{ 2377 {0, 239}, // AX CX DX BX BP SI DI 2378 }, 2379 }, 2380 }, 2381 { 2382 name: "ADCLconst", 2383 auxType: auxInt32, 2384 argLen: 2, 2385 resultInArg0: true, 2386 clobberFlags: true, 2387 asm: x86.AADCL, 2388 reg: regInfo{ 2389 inputs: []inputInfo{ 2390 {0, 239}, // AX CX DX BX BP SI DI 2391 }, 2392 outputs: []outputInfo{ 2393 {0, 239}, // AX CX DX BX BP SI DI 2394 }, 2395 }, 2396 }, 2397 { 2398 name: "SUBL", 2399 argLen: 2, 2400 resultInArg0: true, 2401 clobberFlags: true, 2402 asm: x86.ASUBL, 2403 reg: regInfo{ 2404 inputs: []inputInfo{ 2405 {0, 239}, // AX CX DX BX BP SI DI 2406 {1, 239}, // AX CX DX BX BP SI DI 2407 }, 2408 outputs: []outputInfo{ 2409 {0, 239}, // AX CX DX BX BP SI DI 2410 }, 2411 }, 2412 }, 2413 { 2414 name: "SUBLconst", 2415 auxType: auxInt32, 2416 argLen: 1, 2417 resultInArg0: true, 2418 clobberFlags: true, 2419 asm: x86.ASUBL, 2420 reg: regInfo{ 2421 inputs: []inputInfo{ 2422 {0, 239}, // AX CX DX BX BP SI DI 2423 }, 2424 outputs: []outputInfo{ 2425 {0, 239}, // AX CX DX BX BP SI DI 2426 }, 2427 }, 2428 }, 2429 { 2430 name: "SUBLcarry", 2431 argLen: 2, 2432 resultInArg0: true, 2433 asm: x86.ASUBL, 2434 reg: regInfo{ 2435 inputs: []inputInfo{ 2436 {0, 239}, // AX CX DX BX BP SI DI 2437 {1, 239}, // AX CX DX BX BP SI DI 2438 }, 2439 outputs: []outputInfo{ 2440 {1, 0}, 2441 {0, 239}, // AX CX DX BX BP SI DI 2442 }, 2443 }, 2444 }, 2445 { 2446 name: "SUBLconstcarry", 2447 auxType: auxInt32, 2448 argLen: 1, 2449 resultInArg0: true, 2450 asm: x86.ASUBL, 2451 reg: regInfo{ 2452 inputs: []inputInfo{ 2453 {0, 239}, // AX CX DX BX BP SI DI 2454 }, 2455 outputs: []outputInfo{ 2456 {1, 0}, 2457 {0, 239}, // AX CX DX BX BP SI DI 2458 }, 2459 }, 2460 }, 2461 { 2462 name: "SBBL", 2463 argLen: 3, 2464 resultInArg0: true, 2465 clobberFlags: true, 2466 asm: x86.ASBBL, 2467 reg: regInfo{ 2468 inputs: []inputInfo{ 2469 {0, 239}, // AX CX DX BX BP SI DI 2470 {1, 239}, // AX CX DX BX BP SI DI 2471 }, 2472 outputs: []outputInfo{ 2473 {0, 239}, // AX CX DX BX BP SI DI 2474 }, 2475 }, 2476 }, 2477 { 2478 name: "SBBLconst", 2479 auxType: auxInt32, 2480 argLen: 2, 2481 resultInArg0: true, 2482 clobberFlags: true, 2483 asm: x86.ASBBL, 2484 reg: regInfo{ 2485 inputs: []inputInfo{ 2486 {0, 239}, // AX CX DX BX BP SI DI 2487 }, 2488 outputs: []outputInfo{ 2489 {0, 239}, // AX CX DX BX BP SI DI 2490 }, 2491 }, 2492 }, 2493 { 2494 name: "MULL", 2495 argLen: 2, 2496 commutative: true, 2497 resultInArg0: true, 2498 clobberFlags: true, 2499 asm: x86.AIMULL, 2500 reg: regInfo{ 2501 inputs: []inputInfo{ 2502 {0, 239}, // AX CX DX BX BP SI DI 2503 {1, 239}, // AX CX DX BX BP SI DI 2504 }, 2505 outputs: []outputInfo{ 2506 {0, 239}, // AX CX DX BX BP SI DI 2507 }, 2508 }, 2509 }, 2510 { 2511 name: "MULLconst", 2512 auxType: auxInt32, 2513 argLen: 1, 2514 resultInArg0: true, 2515 clobberFlags: true, 2516 asm: x86.AIMULL, 2517 reg: regInfo{ 2518 inputs: []inputInfo{ 2519 {0, 239}, // AX CX DX BX BP SI DI 2520 }, 2521 outputs: []outputInfo{ 2522 {0, 239}, // AX CX DX BX BP SI DI 2523 }, 2524 }, 2525 }, 2526 { 2527 name: "HMULL", 2528 argLen: 2, 2529 commutative: true, 2530 clobberFlags: true, 2531 asm: x86.AIMULL, 2532 reg: regInfo{ 2533 inputs: []inputInfo{ 2534 {0, 1}, // AX 2535 {1, 255}, // AX CX DX BX SP BP SI DI 2536 }, 2537 clobbers: 1, // AX 2538 outputs: []outputInfo{ 2539 {0, 4}, // DX 2540 }, 2541 }, 2542 }, 2543 { 2544 name: "HMULLU", 2545 argLen: 2, 2546 commutative: true, 2547 clobberFlags: true, 2548 asm: x86.AMULL, 2549 reg: regInfo{ 2550 inputs: []inputInfo{ 2551 {0, 1}, // AX 2552 {1, 255}, // AX CX DX BX SP BP SI DI 2553 }, 2554 clobbers: 1, // AX 2555 outputs: []outputInfo{ 2556 {0, 4}, // DX 2557 }, 2558 }, 2559 }, 2560 { 2561 name: "MULLQU", 2562 argLen: 2, 2563 commutative: true, 2564 clobberFlags: true, 2565 asm: x86.AMULL, 2566 reg: regInfo{ 2567 inputs: []inputInfo{ 2568 {0, 1}, // AX 2569 {1, 255}, // AX CX DX BX SP BP SI DI 2570 }, 2571 outputs: []outputInfo{ 2572 {0, 4}, // DX 2573 {1, 1}, // AX 2574 }, 2575 }, 2576 }, 2577 { 2578 name: "AVGLU", 2579 argLen: 2, 2580 commutative: true, 2581 resultInArg0: true, 2582 clobberFlags: true, 2583 reg: regInfo{ 2584 inputs: []inputInfo{ 2585 {0, 239}, // AX CX DX BX BP SI DI 2586 {1, 239}, // AX CX DX BX BP SI DI 2587 }, 2588 outputs: []outputInfo{ 2589 {0, 239}, // AX CX DX BX BP SI DI 2590 }, 2591 }, 2592 }, 2593 { 2594 name: "DIVL", 2595 argLen: 2, 2596 clobberFlags: true, 2597 asm: x86.AIDIVL, 2598 reg: regInfo{ 2599 inputs: []inputInfo{ 2600 {0, 1}, // AX 2601 {1, 251}, // AX CX BX SP BP SI DI 2602 }, 2603 clobbers: 4, // DX 2604 outputs: []outputInfo{ 2605 {0, 1}, // AX 2606 }, 2607 }, 2608 }, 2609 { 2610 name: "DIVW", 2611 argLen: 2, 2612 clobberFlags: true, 2613 asm: x86.AIDIVW, 2614 reg: regInfo{ 2615 inputs: []inputInfo{ 2616 {0, 1}, // AX 2617 {1, 251}, // AX CX BX SP BP SI DI 2618 }, 2619 clobbers: 4, // DX 2620 outputs: []outputInfo{ 2621 {0, 1}, // AX 2622 }, 2623 }, 2624 }, 2625 { 2626 name: "DIVLU", 2627 argLen: 2, 2628 clobberFlags: true, 2629 asm: x86.ADIVL, 2630 reg: regInfo{ 2631 inputs: []inputInfo{ 2632 {0, 1}, // AX 2633 {1, 251}, // AX CX BX SP BP SI DI 2634 }, 2635 clobbers: 4, // DX 2636 outputs: []outputInfo{ 2637 {0, 1}, // AX 2638 }, 2639 }, 2640 }, 2641 { 2642 name: "DIVWU", 2643 argLen: 2, 2644 clobberFlags: true, 2645 asm: x86.ADIVW, 2646 reg: regInfo{ 2647 inputs: []inputInfo{ 2648 {0, 1}, // AX 2649 {1, 251}, // AX CX BX SP BP SI DI 2650 }, 2651 clobbers: 4, // DX 2652 outputs: []outputInfo{ 2653 {0, 1}, // AX 2654 }, 2655 }, 2656 }, 2657 { 2658 name: "MODL", 2659 argLen: 2, 2660 clobberFlags: true, 2661 asm: x86.AIDIVL, 2662 reg: regInfo{ 2663 inputs: []inputInfo{ 2664 {0, 1}, // AX 2665 {1, 251}, // AX CX BX SP BP SI DI 2666 }, 2667 clobbers: 1, // AX 2668 outputs: []outputInfo{ 2669 {0, 4}, // DX 2670 }, 2671 }, 2672 }, 2673 { 2674 name: "MODW", 2675 argLen: 2, 2676 clobberFlags: true, 2677 asm: x86.AIDIVW, 2678 reg: regInfo{ 2679 inputs: []inputInfo{ 2680 {0, 1}, // AX 2681 {1, 251}, // AX CX BX SP BP SI DI 2682 }, 2683 clobbers: 1, // AX 2684 outputs: []outputInfo{ 2685 {0, 4}, // DX 2686 }, 2687 }, 2688 }, 2689 { 2690 name: "MODLU", 2691 argLen: 2, 2692 clobberFlags: true, 2693 asm: x86.ADIVL, 2694 reg: regInfo{ 2695 inputs: []inputInfo{ 2696 {0, 1}, // AX 2697 {1, 251}, // AX CX BX SP BP SI DI 2698 }, 2699 clobbers: 1, // AX 2700 outputs: []outputInfo{ 2701 {0, 4}, // DX 2702 }, 2703 }, 2704 }, 2705 { 2706 name: "MODWU", 2707 argLen: 2, 2708 clobberFlags: true, 2709 asm: x86.ADIVW, 2710 reg: regInfo{ 2711 inputs: []inputInfo{ 2712 {0, 1}, // AX 2713 {1, 251}, // AX CX BX SP BP SI DI 2714 }, 2715 clobbers: 1, // AX 2716 outputs: []outputInfo{ 2717 {0, 4}, // DX 2718 }, 2719 }, 2720 }, 2721 { 2722 name: "ANDL", 2723 argLen: 2, 2724 commutative: true, 2725 resultInArg0: true, 2726 clobberFlags: true, 2727 asm: x86.AANDL, 2728 reg: regInfo{ 2729 inputs: []inputInfo{ 2730 {0, 239}, // AX CX DX BX BP SI DI 2731 {1, 239}, // AX CX DX BX BP SI DI 2732 }, 2733 outputs: []outputInfo{ 2734 {0, 239}, // AX CX DX BX BP SI DI 2735 }, 2736 }, 2737 }, 2738 { 2739 name: "ANDLconst", 2740 auxType: auxInt32, 2741 argLen: 1, 2742 resultInArg0: true, 2743 clobberFlags: true, 2744 asm: x86.AANDL, 2745 reg: regInfo{ 2746 inputs: []inputInfo{ 2747 {0, 239}, // AX CX DX BX BP SI DI 2748 }, 2749 outputs: []outputInfo{ 2750 {0, 239}, // AX CX DX BX BP SI DI 2751 }, 2752 }, 2753 }, 2754 { 2755 name: "ORL", 2756 argLen: 2, 2757 commutative: true, 2758 resultInArg0: true, 2759 clobberFlags: true, 2760 asm: x86.AORL, 2761 reg: regInfo{ 2762 inputs: []inputInfo{ 2763 {0, 239}, // AX CX DX BX BP SI DI 2764 {1, 239}, // AX CX DX BX BP SI DI 2765 }, 2766 outputs: []outputInfo{ 2767 {0, 239}, // AX CX DX BX BP SI DI 2768 }, 2769 }, 2770 }, 2771 { 2772 name: "ORLconst", 2773 auxType: auxInt32, 2774 argLen: 1, 2775 resultInArg0: true, 2776 clobberFlags: true, 2777 asm: x86.AORL, 2778 reg: regInfo{ 2779 inputs: []inputInfo{ 2780 {0, 239}, // AX CX DX BX BP SI DI 2781 }, 2782 outputs: []outputInfo{ 2783 {0, 239}, // AX CX DX BX BP SI DI 2784 }, 2785 }, 2786 }, 2787 { 2788 name: "XORL", 2789 argLen: 2, 2790 commutative: true, 2791 resultInArg0: true, 2792 clobberFlags: true, 2793 asm: x86.AXORL, 2794 reg: regInfo{ 2795 inputs: []inputInfo{ 2796 {0, 239}, // AX CX DX BX BP SI DI 2797 {1, 239}, // AX CX DX BX BP SI DI 2798 }, 2799 outputs: []outputInfo{ 2800 {0, 239}, // AX CX DX BX BP SI DI 2801 }, 2802 }, 2803 }, 2804 { 2805 name: "XORLconst", 2806 auxType: auxInt32, 2807 argLen: 1, 2808 resultInArg0: true, 2809 clobberFlags: true, 2810 asm: x86.AXORL, 2811 reg: regInfo{ 2812 inputs: []inputInfo{ 2813 {0, 239}, // AX CX DX BX BP SI DI 2814 }, 2815 outputs: []outputInfo{ 2816 {0, 239}, // AX CX DX BX BP SI DI 2817 }, 2818 }, 2819 }, 2820 { 2821 name: "CMPL", 2822 argLen: 2, 2823 asm: x86.ACMPL, 2824 reg: regInfo{ 2825 inputs: []inputInfo{ 2826 {0, 255}, // AX CX DX BX SP BP SI DI 2827 {1, 255}, // AX CX DX BX SP BP SI DI 2828 }, 2829 }, 2830 }, 2831 { 2832 name: "CMPW", 2833 argLen: 2, 2834 asm: x86.ACMPW, 2835 reg: regInfo{ 2836 inputs: []inputInfo{ 2837 {0, 255}, // AX CX DX BX SP BP SI DI 2838 {1, 255}, // AX CX DX BX SP BP SI DI 2839 }, 2840 }, 2841 }, 2842 { 2843 name: "CMPB", 2844 argLen: 2, 2845 asm: x86.ACMPB, 2846 reg: regInfo{ 2847 inputs: []inputInfo{ 2848 {0, 255}, // AX CX DX BX SP BP SI DI 2849 {1, 255}, // AX CX DX BX SP BP SI DI 2850 }, 2851 }, 2852 }, 2853 { 2854 name: "CMPLconst", 2855 auxType: auxInt32, 2856 argLen: 1, 2857 asm: x86.ACMPL, 2858 reg: regInfo{ 2859 inputs: []inputInfo{ 2860 {0, 255}, // AX CX DX BX SP BP SI DI 2861 }, 2862 }, 2863 }, 2864 { 2865 name: "CMPWconst", 2866 auxType: auxInt16, 2867 argLen: 1, 2868 asm: x86.ACMPW, 2869 reg: regInfo{ 2870 inputs: []inputInfo{ 2871 {0, 255}, // AX CX DX BX SP BP SI DI 2872 }, 2873 }, 2874 }, 2875 { 2876 name: "CMPBconst", 2877 auxType: auxInt8, 2878 argLen: 1, 2879 asm: x86.ACMPB, 2880 reg: regInfo{ 2881 inputs: []inputInfo{ 2882 {0, 255}, // AX CX DX BX SP BP SI DI 2883 }, 2884 }, 2885 }, 2886 { 2887 name: "UCOMISS", 2888 argLen: 2, 2889 usesScratch: true, 2890 asm: x86.AUCOMISS, 2891 reg: regInfo{ 2892 inputs: []inputInfo{ 2893 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2894 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2895 }, 2896 }, 2897 }, 2898 { 2899 name: "UCOMISD", 2900 argLen: 2, 2901 usesScratch: true, 2902 asm: x86.AUCOMISD, 2903 reg: regInfo{ 2904 inputs: []inputInfo{ 2905 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2906 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2907 }, 2908 }, 2909 }, 2910 { 2911 name: "TESTL", 2912 argLen: 2, 2913 commutative: true, 2914 asm: x86.ATESTL, 2915 reg: regInfo{ 2916 inputs: []inputInfo{ 2917 {0, 255}, // AX CX DX BX SP BP SI DI 2918 {1, 255}, // AX CX DX BX SP BP SI DI 2919 }, 2920 }, 2921 }, 2922 { 2923 name: "TESTW", 2924 argLen: 2, 2925 commutative: true, 2926 asm: x86.ATESTW, 2927 reg: regInfo{ 2928 inputs: []inputInfo{ 2929 {0, 255}, // AX CX DX BX SP BP SI DI 2930 {1, 255}, // AX CX DX BX SP BP SI DI 2931 }, 2932 }, 2933 }, 2934 { 2935 name: "TESTB", 2936 argLen: 2, 2937 commutative: true, 2938 asm: x86.ATESTB, 2939 reg: regInfo{ 2940 inputs: []inputInfo{ 2941 {0, 255}, // AX CX DX BX SP BP SI DI 2942 {1, 255}, // AX CX DX BX SP BP SI DI 2943 }, 2944 }, 2945 }, 2946 { 2947 name: "TESTLconst", 2948 auxType: auxInt32, 2949 argLen: 1, 2950 asm: x86.ATESTL, 2951 reg: regInfo{ 2952 inputs: []inputInfo{ 2953 {0, 255}, // AX CX DX BX SP BP SI DI 2954 }, 2955 }, 2956 }, 2957 { 2958 name: "TESTWconst", 2959 auxType: auxInt16, 2960 argLen: 1, 2961 asm: x86.ATESTW, 2962 reg: regInfo{ 2963 inputs: []inputInfo{ 2964 {0, 255}, // AX CX DX BX SP BP SI DI 2965 }, 2966 }, 2967 }, 2968 { 2969 name: "TESTBconst", 2970 auxType: auxInt8, 2971 argLen: 1, 2972 asm: x86.ATESTB, 2973 reg: regInfo{ 2974 inputs: []inputInfo{ 2975 {0, 255}, // AX CX DX BX SP BP SI DI 2976 }, 2977 }, 2978 }, 2979 { 2980 name: "SHLL", 2981 argLen: 2, 2982 resultInArg0: true, 2983 clobberFlags: true, 2984 asm: x86.ASHLL, 2985 reg: regInfo{ 2986 inputs: []inputInfo{ 2987 {1, 2}, // CX 2988 {0, 239}, // AX CX DX BX BP SI DI 2989 }, 2990 outputs: []outputInfo{ 2991 {0, 239}, // AX CX DX BX BP SI DI 2992 }, 2993 }, 2994 }, 2995 { 2996 name: "SHLLconst", 2997 auxType: auxInt32, 2998 argLen: 1, 2999 resultInArg0: true, 3000 clobberFlags: true, 3001 asm: x86.ASHLL, 3002 reg: regInfo{ 3003 inputs: []inputInfo{ 3004 {0, 239}, // AX CX DX BX BP SI DI 3005 }, 3006 outputs: []outputInfo{ 3007 {0, 239}, // AX CX DX BX BP SI DI 3008 }, 3009 }, 3010 }, 3011 { 3012 name: "SHRL", 3013 argLen: 2, 3014 resultInArg0: true, 3015 clobberFlags: true, 3016 asm: x86.ASHRL, 3017 reg: regInfo{ 3018 inputs: []inputInfo{ 3019 {1, 2}, // CX 3020 {0, 239}, // AX CX DX BX BP SI DI 3021 }, 3022 outputs: []outputInfo{ 3023 {0, 239}, // AX CX DX BX BP SI DI 3024 }, 3025 }, 3026 }, 3027 { 3028 name: "SHRW", 3029 argLen: 2, 3030 resultInArg0: true, 3031 clobberFlags: true, 3032 asm: x86.ASHRW, 3033 reg: regInfo{ 3034 inputs: []inputInfo{ 3035 {1, 2}, // CX 3036 {0, 239}, // AX CX DX BX BP SI DI 3037 }, 3038 outputs: []outputInfo{ 3039 {0, 239}, // AX CX DX BX BP SI DI 3040 }, 3041 }, 3042 }, 3043 { 3044 name: "SHRB", 3045 argLen: 2, 3046 resultInArg0: true, 3047 clobberFlags: true, 3048 asm: x86.ASHRB, 3049 reg: regInfo{ 3050 inputs: []inputInfo{ 3051 {1, 2}, // CX 3052 {0, 239}, // AX CX DX BX BP SI DI 3053 }, 3054 outputs: []outputInfo{ 3055 {0, 239}, // AX CX DX BX BP SI DI 3056 }, 3057 }, 3058 }, 3059 { 3060 name: "SHRLconst", 3061 auxType: auxInt32, 3062 argLen: 1, 3063 resultInArg0: true, 3064 clobberFlags: true, 3065 asm: x86.ASHRL, 3066 reg: regInfo{ 3067 inputs: []inputInfo{ 3068 {0, 239}, // AX CX DX BX BP SI DI 3069 }, 3070 outputs: []outputInfo{ 3071 {0, 239}, // AX CX DX BX BP SI DI 3072 }, 3073 }, 3074 }, 3075 { 3076 name: "SHRWconst", 3077 auxType: auxInt16, 3078 argLen: 1, 3079 resultInArg0: true, 3080 clobberFlags: true, 3081 asm: x86.ASHRW, 3082 reg: regInfo{ 3083 inputs: []inputInfo{ 3084 {0, 239}, // AX CX DX BX BP SI DI 3085 }, 3086 outputs: []outputInfo{ 3087 {0, 239}, // AX CX DX BX BP SI DI 3088 }, 3089 }, 3090 }, 3091 { 3092 name: "SHRBconst", 3093 auxType: auxInt8, 3094 argLen: 1, 3095 resultInArg0: true, 3096 clobberFlags: true, 3097 asm: x86.ASHRB, 3098 reg: regInfo{ 3099 inputs: []inputInfo{ 3100 {0, 239}, // AX CX DX BX BP SI DI 3101 }, 3102 outputs: []outputInfo{ 3103 {0, 239}, // AX CX DX BX BP SI DI 3104 }, 3105 }, 3106 }, 3107 { 3108 name: "SARL", 3109 argLen: 2, 3110 resultInArg0: true, 3111 clobberFlags: true, 3112 asm: x86.ASARL, 3113 reg: regInfo{ 3114 inputs: []inputInfo{ 3115 {1, 2}, // CX 3116 {0, 239}, // AX CX DX BX BP SI DI 3117 }, 3118 outputs: []outputInfo{ 3119 {0, 239}, // AX CX DX BX BP SI DI 3120 }, 3121 }, 3122 }, 3123 { 3124 name: "SARW", 3125 argLen: 2, 3126 resultInArg0: true, 3127 clobberFlags: true, 3128 asm: x86.ASARW, 3129 reg: regInfo{ 3130 inputs: []inputInfo{ 3131 {1, 2}, // CX 3132 {0, 239}, // AX CX DX BX BP SI DI 3133 }, 3134 outputs: []outputInfo{ 3135 {0, 239}, // AX CX DX BX BP SI DI 3136 }, 3137 }, 3138 }, 3139 { 3140 name: "SARB", 3141 argLen: 2, 3142 resultInArg0: true, 3143 clobberFlags: true, 3144 asm: x86.ASARB, 3145 reg: regInfo{ 3146 inputs: []inputInfo{ 3147 {1, 2}, // CX 3148 {0, 239}, // AX CX DX BX BP SI DI 3149 }, 3150 outputs: []outputInfo{ 3151 {0, 239}, // AX CX DX BX BP SI DI 3152 }, 3153 }, 3154 }, 3155 { 3156 name: "SARLconst", 3157 auxType: auxInt32, 3158 argLen: 1, 3159 resultInArg0: true, 3160 clobberFlags: true, 3161 asm: x86.ASARL, 3162 reg: regInfo{ 3163 inputs: []inputInfo{ 3164 {0, 239}, // AX CX DX BX BP SI DI 3165 }, 3166 outputs: []outputInfo{ 3167 {0, 239}, // AX CX DX BX BP SI DI 3168 }, 3169 }, 3170 }, 3171 { 3172 name: "SARWconst", 3173 auxType: auxInt16, 3174 argLen: 1, 3175 resultInArg0: true, 3176 clobberFlags: true, 3177 asm: x86.ASARW, 3178 reg: regInfo{ 3179 inputs: []inputInfo{ 3180 {0, 239}, // AX CX DX BX BP SI DI 3181 }, 3182 outputs: []outputInfo{ 3183 {0, 239}, // AX CX DX BX BP SI DI 3184 }, 3185 }, 3186 }, 3187 { 3188 name: "SARBconst", 3189 auxType: auxInt8, 3190 argLen: 1, 3191 resultInArg0: true, 3192 clobberFlags: true, 3193 asm: x86.ASARB, 3194 reg: regInfo{ 3195 inputs: []inputInfo{ 3196 {0, 239}, // AX CX DX BX BP SI DI 3197 }, 3198 outputs: []outputInfo{ 3199 {0, 239}, // AX CX DX BX BP SI DI 3200 }, 3201 }, 3202 }, 3203 { 3204 name: "ROLLconst", 3205 auxType: auxInt32, 3206 argLen: 1, 3207 resultInArg0: true, 3208 clobberFlags: true, 3209 asm: x86.AROLL, 3210 reg: regInfo{ 3211 inputs: []inputInfo{ 3212 {0, 239}, // AX CX DX BX BP SI DI 3213 }, 3214 outputs: []outputInfo{ 3215 {0, 239}, // AX CX DX BX BP SI DI 3216 }, 3217 }, 3218 }, 3219 { 3220 name: "ROLWconst", 3221 auxType: auxInt16, 3222 argLen: 1, 3223 resultInArg0: true, 3224 clobberFlags: true, 3225 asm: x86.AROLW, 3226 reg: regInfo{ 3227 inputs: []inputInfo{ 3228 {0, 239}, // AX CX DX BX BP SI DI 3229 }, 3230 outputs: []outputInfo{ 3231 {0, 239}, // AX CX DX BX BP SI DI 3232 }, 3233 }, 3234 }, 3235 { 3236 name: "ROLBconst", 3237 auxType: auxInt8, 3238 argLen: 1, 3239 resultInArg0: true, 3240 clobberFlags: true, 3241 asm: x86.AROLB, 3242 reg: regInfo{ 3243 inputs: []inputInfo{ 3244 {0, 239}, // AX CX DX BX BP SI DI 3245 }, 3246 outputs: []outputInfo{ 3247 {0, 239}, // AX CX DX BX BP SI DI 3248 }, 3249 }, 3250 }, 3251 { 3252 name: "NEGL", 3253 argLen: 1, 3254 resultInArg0: true, 3255 clobberFlags: true, 3256 asm: x86.ANEGL, 3257 reg: regInfo{ 3258 inputs: []inputInfo{ 3259 {0, 239}, // AX CX DX BX BP SI DI 3260 }, 3261 outputs: []outputInfo{ 3262 {0, 239}, // AX CX DX BX BP SI DI 3263 }, 3264 }, 3265 }, 3266 { 3267 name: "NOTL", 3268 argLen: 1, 3269 resultInArg0: true, 3270 clobberFlags: true, 3271 asm: x86.ANOTL, 3272 reg: regInfo{ 3273 inputs: []inputInfo{ 3274 {0, 239}, // AX CX DX BX BP SI DI 3275 }, 3276 outputs: []outputInfo{ 3277 {0, 239}, // AX CX DX BX BP SI DI 3278 }, 3279 }, 3280 }, 3281 { 3282 name: "BSFL", 3283 argLen: 1, 3284 clobberFlags: true, 3285 asm: x86.ABSFL, 3286 reg: regInfo{ 3287 inputs: []inputInfo{ 3288 {0, 239}, // AX CX DX BX BP SI DI 3289 }, 3290 outputs: []outputInfo{ 3291 {0, 239}, // AX CX DX BX BP SI DI 3292 }, 3293 }, 3294 }, 3295 { 3296 name: "BSFW", 3297 argLen: 1, 3298 clobberFlags: true, 3299 asm: x86.ABSFW, 3300 reg: regInfo{ 3301 inputs: []inputInfo{ 3302 {0, 239}, // AX CX DX BX BP SI DI 3303 }, 3304 outputs: []outputInfo{ 3305 {0, 239}, // AX CX DX BX BP SI DI 3306 }, 3307 }, 3308 }, 3309 { 3310 name: "BSRL", 3311 argLen: 1, 3312 clobberFlags: true, 3313 asm: x86.ABSRL, 3314 reg: regInfo{ 3315 inputs: []inputInfo{ 3316 {0, 239}, // AX CX DX BX BP SI DI 3317 }, 3318 outputs: []outputInfo{ 3319 {0, 239}, // AX CX DX BX BP SI DI 3320 }, 3321 }, 3322 }, 3323 { 3324 name: "BSRW", 3325 argLen: 1, 3326 clobberFlags: true, 3327 asm: x86.ABSRW, 3328 reg: regInfo{ 3329 inputs: []inputInfo{ 3330 {0, 239}, // AX CX DX BX BP SI DI 3331 }, 3332 outputs: []outputInfo{ 3333 {0, 239}, // AX CX DX BX BP SI DI 3334 }, 3335 }, 3336 }, 3337 { 3338 name: "BSWAPL", 3339 argLen: 1, 3340 resultInArg0: true, 3341 clobberFlags: true, 3342 asm: x86.ABSWAPL, 3343 reg: regInfo{ 3344 inputs: []inputInfo{ 3345 {0, 239}, // AX CX DX BX BP SI DI 3346 }, 3347 outputs: []outputInfo{ 3348 {0, 239}, // AX CX DX BX BP SI DI 3349 }, 3350 }, 3351 }, 3352 { 3353 name: "SQRTSD", 3354 argLen: 1, 3355 asm: x86.ASQRTSD, 3356 reg: regInfo{ 3357 inputs: []inputInfo{ 3358 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3359 }, 3360 outputs: []outputInfo{ 3361 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3362 }, 3363 }, 3364 }, 3365 { 3366 name: "SBBLcarrymask", 3367 argLen: 1, 3368 asm: x86.ASBBL, 3369 reg: regInfo{ 3370 outputs: []outputInfo{ 3371 {0, 239}, // AX CX DX BX BP SI DI 3372 }, 3373 }, 3374 }, 3375 { 3376 name: "SETEQ", 3377 argLen: 1, 3378 asm: x86.ASETEQ, 3379 reg: regInfo{ 3380 outputs: []outputInfo{ 3381 {0, 239}, // AX CX DX BX BP SI DI 3382 }, 3383 }, 3384 }, 3385 { 3386 name: "SETNE", 3387 argLen: 1, 3388 asm: x86.ASETNE, 3389 reg: regInfo{ 3390 outputs: []outputInfo{ 3391 {0, 239}, // AX CX DX BX BP SI DI 3392 }, 3393 }, 3394 }, 3395 { 3396 name: "SETL", 3397 argLen: 1, 3398 asm: x86.ASETLT, 3399 reg: regInfo{ 3400 outputs: []outputInfo{ 3401 {0, 239}, // AX CX DX BX BP SI DI 3402 }, 3403 }, 3404 }, 3405 { 3406 name: "SETLE", 3407 argLen: 1, 3408 asm: x86.ASETLE, 3409 reg: regInfo{ 3410 outputs: []outputInfo{ 3411 {0, 239}, // AX CX DX BX BP SI DI 3412 }, 3413 }, 3414 }, 3415 { 3416 name: "SETG", 3417 argLen: 1, 3418 asm: x86.ASETGT, 3419 reg: regInfo{ 3420 outputs: []outputInfo{ 3421 {0, 239}, // AX CX DX BX BP SI DI 3422 }, 3423 }, 3424 }, 3425 { 3426 name: "SETGE", 3427 argLen: 1, 3428 asm: x86.ASETGE, 3429 reg: regInfo{ 3430 outputs: []outputInfo{ 3431 {0, 239}, // AX CX DX BX BP SI DI 3432 }, 3433 }, 3434 }, 3435 { 3436 name: "SETB", 3437 argLen: 1, 3438 asm: x86.ASETCS, 3439 reg: regInfo{ 3440 outputs: []outputInfo{ 3441 {0, 239}, // AX CX DX BX BP SI DI 3442 }, 3443 }, 3444 }, 3445 { 3446 name: "SETBE", 3447 argLen: 1, 3448 asm: x86.ASETLS, 3449 reg: regInfo{ 3450 outputs: []outputInfo{ 3451 {0, 239}, // AX CX DX BX BP SI DI 3452 }, 3453 }, 3454 }, 3455 { 3456 name: "SETA", 3457 argLen: 1, 3458 asm: x86.ASETHI, 3459 reg: regInfo{ 3460 outputs: []outputInfo{ 3461 {0, 239}, // AX CX DX BX BP SI DI 3462 }, 3463 }, 3464 }, 3465 { 3466 name: "SETAE", 3467 argLen: 1, 3468 asm: x86.ASETCC, 3469 reg: regInfo{ 3470 outputs: []outputInfo{ 3471 {0, 239}, // AX CX DX BX BP SI DI 3472 }, 3473 }, 3474 }, 3475 { 3476 name: "SETEQF", 3477 argLen: 1, 3478 clobberFlags: true, 3479 asm: x86.ASETEQ, 3480 reg: regInfo{ 3481 clobbers: 1, // AX 3482 outputs: []outputInfo{ 3483 {0, 238}, // CX DX BX BP SI DI 3484 }, 3485 }, 3486 }, 3487 { 3488 name: "SETNEF", 3489 argLen: 1, 3490 clobberFlags: true, 3491 asm: x86.ASETNE, 3492 reg: regInfo{ 3493 clobbers: 1, // AX 3494 outputs: []outputInfo{ 3495 {0, 238}, // CX DX BX BP SI DI 3496 }, 3497 }, 3498 }, 3499 { 3500 name: "SETORD", 3501 argLen: 1, 3502 asm: x86.ASETPC, 3503 reg: regInfo{ 3504 outputs: []outputInfo{ 3505 {0, 239}, // AX CX DX BX BP SI DI 3506 }, 3507 }, 3508 }, 3509 { 3510 name: "SETNAN", 3511 argLen: 1, 3512 asm: x86.ASETPS, 3513 reg: regInfo{ 3514 outputs: []outputInfo{ 3515 {0, 239}, // AX CX DX BX BP SI DI 3516 }, 3517 }, 3518 }, 3519 { 3520 name: "SETGF", 3521 argLen: 1, 3522 asm: x86.ASETHI, 3523 reg: regInfo{ 3524 outputs: []outputInfo{ 3525 {0, 239}, // AX CX DX BX BP SI DI 3526 }, 3527 }, 3528 }, 3529 { 3530 name: "SETGEF", 3531 argLen: 1, 3532 asm: x86.ASETCC, 3533 reg: regInfo{ 3534 outputs: []outputInfo{ 3535 {0, 239}, // AX CX DX BX BP SI DI 3536 }, 3537 }, 3538 }, 3539 { 3540 name: "MOVBLSX", 3541 argLen: 1, 3542 asm: x86.AMOVBLSX, 3543 reg: regInfo{ 3544 inputs: []inputInfo{ 3545 {0, 239}, // AX CX DX BX BP SI DI 3546 }, 3547 outputs: []outputInfo{ 3548 {0, 239}, // AX CX DX BX BP SI DI 3549 }, 3550 }, 3551 }, 3552 { 3553 name: "MOVBLZX", 3554 argLen: 1, 3555 asm: x86.AMOVBLZX, 3556 reg: regInfo{ 3557 inputs: []inputInfo{ 3558 {0, 239}, // AX CX DX BX BP SI DI 3559 }, 3560 outputs: []outputInfo{ 3561 {0, 239}, // AX CX DX BX BP SI DI 3562 }, 3563 }, 3564 }, 3565 { 3566 name: "MOVWLSX", 3567 argLen: 1, 3568 asm: x86.AMOVWLSX, 3569 reg: regInfo{ 3570 inputs: []inputInfo{ 3571 {0, 239}, // AX CX DX BX BP SI DI 3572 }, 3573 outputs: []outputInfo{ 3574 {0, 239}, // AX CX DX BX BP SI DI 3575 }, 3576 }, 3577 }, 3578 { 3579 name: "MOVWLZX", 3580 argLen: 1, 3581 asm: x86.AMOVWLZX, 3582 reg: regInfo{ 3583 inputs: []inputInfo{ 3584 {0, 239}, // AX CX DX BX BP SI DI 3585 }, 3586 outputs: []outputInfo{ 3587 {0, 239}, // AX CX DX BX BP SI DI 3588 }, 3589 }, 3590 }, 3591 { 3592 name: "MOVLconst", 3593 auxType: auxInt32, 3594 argLen: 0, 3595 rematerializeable: true, 3596 asm: x86.AMOVL, 3597 reg: regInfo{ 3598 outputs: []outputInfo{ 3599 {0, 239}, // AX CX DX BX BP SI DI 3600 }, 3601 }, 3602 }, 3603 { 3604 name: "CVTTSD2SL", 3605 argLen: 1, 3606 usesScratch: true, 3607 asm: x86.ACVTTSD2SL, 3608 reg: regInfo{ 3609 inputs: []inputInfo{ 3610 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3611 }, 3612 outputs: []outputInfo{ 3613 {0, 239}, // AX CX DX BX BP SI DI 3614 }, 3615 }, 3616 }, 3617 { 3618 name: "CVTTSS2SL", 3619 argLen: 1, 3620 usesScratch: true, 3621 asm: x86.ACVTTSS2SL, 3622 reg: regInfo{ 3623 inputs: []inputInfo{ 3624 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3625 }, 3626 outputs: []outputInfo{ 3627 {0, 239}, // AX CX DX BX BP SI DI 3628 }, 3629 }, 3630 }, 3631 { 3632 name: "CVTSL2SS", 3633 argLen: 1, 3634 usesScratch: true, 3635 asm: x86.ACVTSL2SS, 3636 reg: regInfo{ 3637 inputs: []inputInfo{ 3638 {0, 239}, // AX CX DX BX BP SI DI 3639 }, 3640 outputs: []outputInfo{ 3641 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3642 }, 3643 }, 3644 }, 3645 { 3646 name: "CVTSL2SD", 3647 argLen: 1, 3648 usesScratch: true, 3649 asm: x86.ACVTSL2SD, 3650 reg: regInfo{ 3651 inputs: []inputInfo{ 3652 {0, 239}, // AX CX DX BX BP SI DI 3653 }, 3654 outputs: []outputInfo{ 3655 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3656 }, 3657 }, 3658 }, 3659 { 3660 name: "CVTSD2SS", 3661 argLen: 1, 3662 usesScratch: true, 3663 asm: x86.ACVTSD2SS, 3664 reg: regInfo{ 3665 inputs: []inputInfo{ 3666 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3667 }, 3668 outputs: []outputInfo{ 3669 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3670 }, 3671 }, 3672 }, 3673 { 3674 name: "CVTSS2SD", 3675 argLen: 1, 3676 asm: x86.ACVTSS2SD, 3677 reg: regInfo{ 3678 inputs: []inputInfo{ 3679 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3680 }, 3681 outputs: []outputInfo{ 3682 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3683 }, 3684 }, 3685 }, 3686 { 3687 name: "PXOR", 3688 argLen: 2, 3689 commutative: true, 3690 resultInArg0: true, 3691 asm: x86.APXOR, 3692 reg: regInfo{ 3693 inputs: []inputInfo{ 3694 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3695 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3696 }, 3697 outputs: []outputInfo{ 3698 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3699 }, 3700 }, 3701 }, 3702 { 3703 name: "LEAL", 3704 auxType: auxSymOff, 3705 argLen: 1, 3706 rematerializeable: true, 3707 symEffect: SymAddr, 3708 reg: regInfo{ 3709 inputs: []inputInfo{ 3710 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3711 }, 3712 outputs: []outputInfo{ 3713 {0, 239}, // AX CX DX BX BP SI DI 3714 }, 3715 }, 3716 }, 3717 { 3718 name: "LEAL1", 3719 auxType: auxSymOff, 3720 argLen: 2, 3721 commutative: true, 3722 symEffect: SymAddr, 3723 reg: regInfo{ 3724 inputs: []inputInfo{ 3725 {1, 255}, // AX CX DX BX SP BP SI DI 3726 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3727 }, 3728 outputs: []outputInfo{ 3729 {0, 239}, // AX CX DX BX BP SI DI 3730 }, 3731 }, 3732 }, 3733 { 3734 name: "LEAL2", 3735 auxType: auxSymOff, 3736 argLen: 2, 3737 symEffect: SymAddr, 3738 reg: regInfo{ 3739 inputs: []inputInfo{ 3740 {1, 255}, // AX CX DX BX SP BP SI DI 3741 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3742 }, 3743 outputs: []outputInfo{ 3744 {0, 239}, // AX CX DX BX BP SI DI 3745 }, 3746 }, 3747 }, 3748 { 3749 name: "LEAL4", 3750 auxType: auxSymOff, 3751 argLen: 2, 3752 symEffect: SymAddr, 3753 reg: regInfo{ 3754 inputs: []inputInfo{ 3755 {1, 255}, // AX CX DX BX SP BP SI DI 3756 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3757 }, 3758 outputs: []outputInfo{ 3759 {0, 239}, // AX CX DX BX BP SI DI 3760 }, 3761 }, 3762 }, 3763 { 3764 name: "LEAL8", 3765 auxType: auxSymOff, 3766 argLen: 2, 3767 symEffect: SymAddr, 3768 reg: regInfo{ 3769 inputs: []inputInfo{ 3770 {1, 255}, // AX CX DX BX SP BP SI DI 3771 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3772 }, 3773 outputs: []outputInfo{ 3774 {0, 239}, // AX CX DX BX BP SI DI 3775 }, 3776 }, 3777 }, 3778 { 3779 name: "MOVBload", 3780 auxType: auxSymOff, 3781 argLen: 2, 3782 faultOnNilArg0: true, 3783 symEffect: SymRead, 3784 asm: x86.AMOVBLZX, 3785 reg: regInfo{ 3786 inputs: []inputInfo{ 3787 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3788 }, 3789 outputs: []outputInfo{ 3790 {0, 239}, // AX CX DX BX BP SI DI 3791 }, 3792 }, 3793 }, 3794 { 3795 name: "MOVBLSXload", 3796 auxType: auxSymOff, 3797 argLen: 2, 3798 faultOnNilArg0: true, 3799 symEffect: SymRead, 3800 asm: x86.AMOVBLSX, 3801 reg: regInfo{ 3802 inputs: []inputInfo{ 3803 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3804 }, 3805 outputs: []outputInfo{ 3806 {0, 239}, // AX CX DX BX BP SI DI 3807 }, 3808 }, 3809 }, 3810 { 3811 name: "MOVWload", 3812 auxType: auxSymOff, 3813 argLen: 2, 3814 faultOnNilArg0: true, 3815 symEffect: SymRead, 3816 asm: x86.AMOVWLZX, 3817 reg: regInfo{ 3818 inputs: []inputInfo{ 3819 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3820 }, 3821 outputs: []outputInfo{ 3822 {0, 239}, // AX CX DX BX BP SI DI 3823 }, 3824 }, 3825 }, 3826 { 3827 name: "MOVWLSXload", 3828 auxType: auxSymOff, 3829 argLen: 2, 3830 faultOnNilArg0: true, 3831 symEffect: SymRead, 3832 asm: x86.AMOVWLSX, 3833 reg: regInfo{ 3834 inputs: []inputInfo{ 3835 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3836 }, 3837 outputs: []outputInfo{ 3838 {0, 239}, // AX CX DX BX BP SI DI 3839 }, 3840 }, 3841 }, 3842 { 3843 name: "MOVLload", 3844 auxType: auxSymOff, 3845 argLen: 2, 3846 faultOnNilArg0: true, 3847 symEffect: SymRead, 3848 asm: x86.AMOVL, 3849 reg: regInfo{ 3850 inputs: []inputInfo{ 3851 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3852 }, 3853 outputs: []outputInfo{ 3854 {0, 239}, // AX CX DX BX BP SI DI 3855 }, 3856 }, 3857 }, 3858 { 3859 name: "MOVBstore", 3860 auxType: auxSymOff, 3861 argLen: 3, 3862 faultOnNilArg0: true, 3863 symEffect: SymWrite, 3864 asm: x86.AMOVB, 3865 reg: regInfo{ 3866 inputs: []inputInfo{ 3867 {1, 255}, // AX CX DX BX SP BP SI DI 3868 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3869 }, 3870 }, 3871 }, 3872 { 3873 name: "MOVWstore", 3874 auxType: auxSymOff, 3875 argLen: 3, 3876 faultOnNilArg0: true, 3877 symEffect: SymWrite, 3878 asm: x86.AMOVW, 3879 reg: regInfo{ 3880 inputs: []inputInfo{ 3881 {1, 255}, // AX CX DX BX SP BP SI DI 3882 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3883 }, 3884 }, 3885 }, 3886 { 3887 name: "MOVLstore", 3888 auxType: auxSymOff, 3889 argLen: 3, 3890 faultOnNilArg0: true, 3891 symEffect: SymWrite, 3892 asm: x86.AMOVL, 3893 reg: regInfo{ 3894 inputs: []inputInfo{ 3895 {1, 255}, // AX CX DX BX SP BP SI DI 3896 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3897 }, 3898 }, 3899 }, 3900 { 3901 name: "MOVBloadidx1", 3902 auxType: auxSymOff, 3903 argLen: 3, 3904 commutative: true, 3905 symEffect: SymRead, 3906 asm: x86.AMOVBLZX, 3907 reg: regInfo{ 3908 inputs: []inputInfo{ 3909 {1, 255}, // AX CX DX BX SP BP SI DI 3910 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3911 }, 3912 outputs: []outputInfo{ 3913 {0, 239}, // AX CX DX BX BP SI DI 3914 }, 3915 }, 3916 }, 3917 { 3918 name: "MOVWloadidx1", 3919 auxType: auxSymOff, 3920 argLen: 3, 3921 commutative: true, 3922 symEffect: SymRead, 3923 asm: x86.AMOVWLZX, 3924 reg: regInfo{ 3925 inputs: []inputInfo{ 3926 {1, 255}, // AX CX DX BX SP BP SI DI 3927 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3928 }, 3929 outputs: []outputInfo{ 3930 {0, 239}, // AX CX DX BX BP SI DI 3931 }, 3932 }, 3933 }, 3934 { 3935 name: "MOVWloadidx2", 3936 auxType: auxSymOff, 3937 argLen: 3, 3938 symEffect: SymRead, 3939 asm: x86.AMOVWLZX, 3940 reg: regInfo{ 3941 inputs: []inputInfo{ 3942 {1, 255}, // AX CX DX BX SP BP SI DI 3943 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3944 }, 3945 outputs: []outputInfo{ 3946 {0, 239}, // AX CX DX BX BP SI DI 3947 }, 3948 }, 3949 }, 3950 { 3951 name: "MOVLloadidx1", 3952 auxType: auxSymOff, 3953 argLen: 3, 3954 commutative: true, 3955 symEffect: SymRead, 3956 asm: x86.AMOVL, 3957 reg: regInfo{ 3958 inputs: []inputInfo{ 3959 {1, 255}, // AX CX DX BX SP BP SI DI 3960 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3961 }, 3962 outputs: []outputInfo{ 3963 {0, 239}, // AX CX DX BX BP SI DI 3964 }, 3965 }, 3966 }, 3967 { 3968 name: "MOVLloadidx4", 3969 auxType: auxSymOff, 3970 argLen: 3, 3971 symEffect: SymRead, 3972 asm: x86.AMOVL, 3973 reg: regInfo{ 3974 inputs: []inputInfo{ 3975 {1, 255}, // AX CX DX BX SP BP SI DI 3976 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3977 }, 3978 outputs: []outputInfo{ 3979 {0, 239}, // AX CX DX BX BP SI DI 3980 }, 3981 }, 3982 }, 3983 { 3984 name: "MOVBstoreidx1", 3985 auxType: auxSymOff, 3986 argLen: 4, 3987 commutative: true, 3988 symEffect: SymWrite, 3989 asm: x86.AMOVB, 3990 reg: regInfo{ 3991 inputs: []inputInfo{ 3992 {1, 255}, // AX CX DX BX SP BP SI DI 3993 {2, 255}, // AX CX DX BX SP BP SI DI 3994 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3995 }, 3996 }, 3997 }, 3998 { 3999 name: "MOVWstoreidx1", 4000 auxType: auxSymOff, 4001 argLen: 4, 4002 commutative: true, 4003 symEffect: SymWrite, 4004 asm: x86.AMOVW, 4005 reg: regInfo{ 4006 inputs: []inputInfo{ 4007 {1, 255}, // AX CX DX BX SP BP SI DI 4008 {2, 255}, // AX CX DX BX SP BP SI DI 4009 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4010 }, 4011 }, 4012 }, 4013 { 4014 name: "MOVWstoreidx2", 4015 auxType: auxSymOff, 4016 argLen: 4, 4017 symEffect: SymWrite, 4018 asm: x86.AMOVW, 4019 reg: regInfo{ 4020 inputs: []inputInfo{ 4021 {1, 255}, // AX CX DX BX SP BP SI DI 4022 {2, 255}, // AX CX DX BX SP BP SI DI 4023 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4024 }, 4025 }, 4026 }, 4027 { 4028 name: "MOVLstoreidx1", 4029 auxType: auxSymOff, 4030 argLen: 4, 4031 commutative: true, 4032 symEffect: SymWrite, 4033 asm: x86.AMOVL, 4034 reg: regInfo{ 4035 inputs: []inputInfo{ 4036 {1, 255}, // AX CX DX BX SP BP SI DI 4037 {2, 255}, // AX CX DX BX SP BP SI DI 4038 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4039 }, 4040 }, 4041 }, 4042 { 4043 name: "MOVLstoreidx4", 4044 auxType: auxSymOff, 4045 argLen: 4, 4046 symEffect: SymWrite, 4047 asm: x86.AMOVL, 4048 reg: regInfo{ 4049 inputs: []inputInfo{ 4050 {1, 255}, // AX CX DX BX SP BP SI DI 4051 {2, 255}, // AX CX DX BX SP BP SI DI 4052 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4053 }, 4054 }, 4055 }, 4056 { 4057 name: "MOVBstoreconst", 4058 auxType: auxSymValAndOff, 4059 argLen: 2, 4060 faultOnNilArg0: true, 4061 symEffect: SymWrite, 4062 asm: x86.AMOVB, 4063 reg: regInfo{ 4064 inputs: []inputInfo{ 4065 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4066 }, 4067 }, 4068 }, 4069 { 4070 name: "MOVWstoreconst", 4071 auxType: auxSymValAndOff, 4072 argLen: 2, 4073 faultOnNilArg0: true, 4074 symEffect: SymWrite, 4075 asm: x86.AMOVW, 4076 reg: regInfo{ 4077 inputs: []inputInfo{ 4078 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4079 }, 4080 }, 4081 }, 4082 { 4083 name: "MOVLstoreconst", 4084 auxType: auxSymValAndOff, 4085 argLen: 2, 4086 faultOnNilArg0: true, 4087 symEffect: SymWrite, 4088 asm: x86.AMOVL, 4089 reg: regInfo{ 4090 inputs: []inputInfo{ 4091 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4092 }, 4093 }, 4094 }, 4095 { 4096 name: "MOVBstoreconstidx1", 4097 auxType: auxSymValAndOff, 4098 argLen: 3, 4099 symEffect: SymWrite, 4100 asm: x86.AMOVB, 4101 reg: regInfo{ 4102 inputs: []inputInfo{ 4103 {1, 255}, // AX CX DX BX SP BP SI DI 4104 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4105 }, 4106 }, 4107 }, 4108 { 4109 name: "MOVWstoreconstidx1", 4110 auxType: auxSymValAndOff, 4111 argLen: 3, 4112 symEffect: SymWrite, 4113 asm: x86.AMOVW, 4114 reg: regInfo{ 4115 inputs: []inputInfo{ 4116 {1, 255}, // AX CX DX BX SP BP SI DI 4117 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4118 }, 4119 }, 4120 }, 4121 { 4122 name: "MOVWstoreconstidx2", 4123 auxType: auxSymValAndOff, 4124 argLen: 3, 4125 symEffect: SymWrite, 4126 asm: x86.AMOVW, 4127 reg: regInfo{ 4128 inputs: []inputInfo{ 4129 {1, 255}, // AX CX DX BX SP BP SI DI 4130 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4131 }, 4132 }, 4133 }, 4134 { 4135 name: "MOVLstoreconstidx1", 4136 auxType: auxSymValAndOff, 4137 argLen: 3, 4138 symEffect: SymWrite, 4139 asm: x86.AMOVL, 4140 reg: regInfo{ 4141 inputs: []inputInfo{ 4142 {1, 255}, // AX CX DX BX SP BP SI DI 4143 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4144 }, 4145 }, 4146 }, 4147 { 4148 name: "MOVLstoreconstidx4", 4149 auxType: auxSymValAndOff, 4150 argLen: 3, 4151 symEffect: SymWrite, 4152 asm: x86.AMOVL, 4153 reg: regInfo{ 4154 inputs: []inputInfo{ 4155 {1, 255}, // AX CX DX BX SP BP SI DI 4156 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4157 }, 4158 }, 4159 }, 4160 { 4161 name: "DUFFZERO", 4162 auxType: auxInt64, 4163 argLen: 3, 4164 faultOnNilArg0: true, 4165 reg: regInfo{ 4166 inputs: []inputInfo{ 4167 {0, 128}, // DI 4168 {1, 1}, // AX 4169 }, 4170 clobbers: 130, // CX DI 4171 }, 4172 }, 4173 { 4174 name: "REPSTOSL", 4175 argLen: 4, 4176 faultOnNilArg0: true, 4177 reg: regInfo{ 4178 inputs: []inputInfo{ 4179 {0, 128}, // DI 4180 {1, 2}, // CX 4181 {2, 1}, // AX 4182 }, 4183 clobbers: 130, // CX DI 4184 }, 4185 }, 4186 { 4187 name: "CALLstatic", 4188 auxType: auxSymOff, 4189 argLen: 1, 4190 clobberFlags: true, 4191 call: true, 4192 symEffect: SymNone, 4193 reg: regInfo{ 4194 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4195 }, 4196 }, 4197 { 4198 name: "CALLclosure", 4199 auxType: auxInt64, 4200 argLen: 3, 4201 clobberFlags: true, 4202 call: true, 4203 reg: regInfo{ 4204 inputs: []inputInfo{ 4205 {1, 4}, // DX 4206 {0, 255}, // AX CX DX BX SP BP SI DI 4207 }, 4208 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4209 }, 4210 }, 4211 { 4212 name: "CALLinter", 4213 auxType: auxInt64, 4214 argLen: 2, 4215 clobberFlags: true, 4216 call: true, 4217 reg: regInfo{ 4218 inputs: []inputInfo{ 4219 {0, 239}, // AX CX DX BX BP SI DI 4220 }, 4221 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4222 }, 4223 }, 4224 { 4225 name: "DUFFCOPY", 4226 auxType: auxInt64, 4227 argLen: 3, 4228 clobberFlags: true, 4229 faultOnNilArg0: true, 4230 faultOnNilArg1: true, 4231 reg: regInfo{ 4232 inputs: []inputInfo{ 4233 {0, 128}, // DI 4234 {1, 64}, // SI 4235 }, 4236 clobbers: 194, // CX SI DI 4237 }, 4238 }, 4239 { 4240 name: "REPMOVSL", 4241 argLen: 4, 4242 faultOnNilArg0: true, 4243 faultOnNilArg1: true, 4244 reg: regInfo{ 4245 inputs: []inputInfo{ 4246 {0, 128}, // DI 4247 {1, 64}, // SI 4248 {2, 2}, // CX 4249 }, 4250 clobbers: 194, // CX SI DI 4251 }, 4252 }, 4253 { 4254 name: "InvertFlags", 4255 argLen: 1, 4256 reg: regInfo{}, 4257 }, 4258 { 4259 name: "LoweredGetG", 4260 argLen: 1, 4261 reg: regInfo{ 4262 outputs: []outputInfo{ 4263 {0, 239}, // AX CX DX BX BP SI DI 4264 }, 4265 }, 4266 }, 4267 { 4268 name: "LoweredGetClosurePtr", 4269 argLen: 0, 4270 reg: regInfo{ 4271 outputs: []outputInfo{ 4272 {0, 4}, // DX 4273 }, 4274 }, 4275 }, 4276 { 4277 name: "LoweredNilCheck", 4278 argLen: 2, 4279 clobberFlags: true, 4280 nilCheck: true, 4281 faultOnNilArg0: true, 4282 reg: regInfo{ 4283 inputs: []inputInfo{ 4284 {0, 255}, // AX CX DX BX SP BP SI DI 4285 }, 4286 }, 4287 }, 4288 { 4289 name: "MOVLconvert", 4290 argLen: 2, 4291 resultInArg0: true, 4292 asm: x86.AMOVL, 4293 reg: regInfo{ 4294 inputs: []inputInfo{ 4295 {0, 239}, // AX CX DX BX BP SI DI 4296 }, 4297 outputs: []outputInfo{ 4298 {0, 239}, // AX CX DX BX BP SI DI 4299 }, 4300 }, 4301 }, 4302 { 4303 name: "FlagEQ", 4304 argLen: 0, 4305 reg: regInfo{}, 4306 }, 4307 { 4308 name: "FlagLT_ULT", 4309 argLen: 0, 4310 reg: regInfo{}, 4311 }, 4312 { 4313 name: "FlagLT_UGT", 4314 argLen: 0, 4315 reg: regInfo{}, 4316 }, 4317 { 4318 name: "FlagGT_UGT", 4319 argLen: 0, 4320 reg: regInfo{}, 4321 }, 4322 { 4323 name: "FlagGT_ULT", 4324 argLen: 0, 4325 reg: regInfo{}, 4326 }, 4327 { 4328 name: "FCHS", 4329 argLen: 1, 4330 reg: regInfo{ 4331 inputs: []inputInfo{ 4332 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4333 }, 4334 outputs: []outputInfo{ 4335 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4336 }, 4337 }, 4338 }, 4339 { 4340 name: "MOVSSconst1", 4341 auxType: auxFloat32, 4342 argLen: 0, 4343 reg: regInfo{ 4344 outputs: []outputInfo{ 4345 {0, 239}, // AX CX DX BX BP SI DI 4346 }, 4347 }, 4348 }, 4349 { 4350 name: "MOVSDconst1", 4351 auxType: auxFloat64, 4352 argLen: 0, 4353 reg: regInfo{ 4354 outputs: []outputInfo{ 4355 {0, 239}, // AX CX DX BX BP SI DI 4356 }, 4357 }, 4358 }, 4359 { 4360 name: "MOVSSconst2", 4361 argLen: 1, 4362 asm: x86.AMOVSS, 4363 reg: regInfo{ 4364 inputs: []inputInfo{ 4365 {0, 239}, // AX CX DX BX BP SI DI 4366 }, 4367 outputs: []outputInfo{ 4368 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4369 }, 4370 }, 4371 }, 4372 { 4373 name: "MOVSDconst2", 4374 argLen: 1, 4375 asm: x86.AMOVSD, 4376 reg: regInfo{ 4377 inputs: []inputInfo{ 4378 {0, 239}, // AX CX DX BX BP SI DI 4379 }, 4380 outputs: []outputInfo{ 4381 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4382 }, 4383 }, 4384 }, 4385 4386 { 4387 name: "ADDSS", 4388 argLen: 2, 4389 commutative: true, 4390 resultInArg0: true, 4391 asm: x86.AADDSS, 4392 reg: regInfo{ 4393 inputs: []inputInfo{ 4394 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4395 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4396 }, 4397 outputs: []outputInfo{ 4398 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4399 }, 4400 }, 4401 }, 4402 { 4403 name: "ADDSD", 4404 argLen: 2, 4405 commutative: true, 4406 resultInArg0: true, 4407 asm: x86.AADDSD, 4408 reg: regInfo{ 4409 inputs: []inputInfo{ 4410 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4411 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4412 }, 4413 outputs: []outputInfo{ 4414 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4415 }, 4416 }, 4417 }, 4418 { 4419 name: "SUBSS", 4420 argLen: 2, 4421 resultInArg0: true, 4422 asm: x86.ASUBSS, 4423 reg: regInfo{ 4424 inputs: []inputInfo{ 4425 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4426 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4427 }, 4428 outputs: []outputInfo{ 4429 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4430 }, 4431 }, 4432 }, 4433 { 4434 name: "SUBSD", 4435 argLen: 2, 4436 resultInArg0: true, 4437 asm: x86.ASUBSD, 4438 reg: regInfo{ 4439 inputs: []inputInfo{ 4440 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4441 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4442 }, 4443 outputs: []outputInfo{ 4444 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4445 }, 4446 }, 4447 }, 4448 { 4449 name: "MULSS", 4450 argLen: 2, 4451 commutative: true, 4452 resultInArg0: true, 4453 asm: x86.AMULSS, 4454 reg: regInfo{ 4455 inputs: []inputInfo{ 4456 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4457 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4458 }, 4459 outputs: []outputInfo{ 4460 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4461 }, 4462 }, 4463 }, 4464 { 4465 name: "MULSD", 4466 argLen: 2, 4467 commutative: true, 4468 resultInArg0: true, 4469 asm: x86.AMULSD, 4470 reg: regInfo{ 4471 inputs: []inputInfo{ 4472 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4473 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4474 }, 4475 outputs: []outputInfo{ 4476 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4477 }, 4478 }, 4479 }, 4480 { 4481 name: "DIVSS", 4482 argLen: 2, 4483 resultInArg0: true, 4484 asm: x86.ADIVSS, 4485 reg: regInfo{ 4486 inputs: []inputInfo{ 4487 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4488 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4489 }, 4490 outputs: []outputInfo{ 4491 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4492 }, 4493 }, 4494 }, 4495 { 4496 name: "DIVSD", 4497 argLen: 2, 4498 resultInArg0: true, 4499 asm: x86.ADIVSD, 4500 reg: regInfo{ 4501 inputs: []inputInfo{ 4502 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4503 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4504 }, 4505 outputs: []outputInfo{ 4506 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4507 }, 4508 }, 4509 }, 4510 { 4511 name: "MOVSSload", 4512 auxType: auxSymOff, 4513 argLen: 2, 4514 faultOnNilArg0: true, 4515 symEffect: SymRead, 4516 asm: x86.AMOVSS, 4517 reg: regInfo{ 4518 inputs: []inputInfo{ 4519 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4520 }, 4521 outputs: []outputInfo{ 4522 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4523 }, 4524 }, 4525 }, 4526 { 4527 name: "MOVSDload", 4528 auxType: auxSymOff, 4529 argLen: 2, 4530 faultOnNilArg0: true, 4531 symEffect: SymRead, 4532 asm: x86.AMOVSD, 4533 reg: regInfo{ 4534 inputs: []inputInfo{ 4535 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4536 }, 4537 outputs: []outputInfo{ 4538 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4539 }, 4540 }, 4541 }, 4542 { 4543 name: "MOVSSconst", 4544 auxType: auxFloat32, 4545 argLen: 0, 4546 rematerializeable: true, 4547 asm: x86.AMOVSS, 4548 reg: regInfo{ 4549 outputs: []outputInfo{ 4550 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4551 }, 4552 }, 4553 }, 4554 { 4555 name: "MOVSDconst", 4556 auxType: auxFloat64, 4557 argLen: 0, 4558 rematerializeable: true, 4559 asm: x86.AMOVSD, 4560 reg: regInfo{ 4561 outputs: []outputInfo{ 4562 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4563 }, 4564 }, 4565 }, 4566 { 4567 name: "MOVSSloadidx1", 4568 auxType: auxSymOff, 4569 argLen: 3, 4570 symEffect: SymRead, 4571 asm: x86.AMOVSS, 4572 reg: regInfo{ 4573 inputs: []inputInfo{ 4574 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4575 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4576 }, 4577 outputs: []outputInfo{ 4578 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4579 }, 4580 }, 4581 }, 4582 { 4583 name: "MOVSSloadidx4", 4584 auxType: auxSymOff, 4585 argLen: 3, 4586 symEffect: SymRead, 4587 asm: x86.AMOVSS, 4588 reg: regInfo{ 4589 inputs: []inputInfo{ 4590 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4591 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4592 }, 4593 outputs: []outputInfo{ 4594 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4595 }, 4596 }, 4597 }, 4598 { 4599 name: "MOVSDloadidx1", 4600 auxType: auxSymOff, 4601 argLen: 3, 4602 symEffect: SymRead, 4603 asm: x86.AMOVSD, 4604 reg: regInfo{ 4605 inputs: []inputInfo{ 4606 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4607 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4608 }, 4609 outputs: []outputInfo{ 4610 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4611 }, 4612 }, 4613 }, 4614 { 4615 name: "MOVSDloadidx8", 4616 auxType: auxSymOff, 4617 argLen: 3, 4618 symEffect: SymRead, 4619 asm: x86.AMOVSD, 4620 reg: regInfo{ 4621 inputs: []inputInfo{ 4622 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4623 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4624 }, 4625 outputs: []outputInfo{ 4626 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4627 }, 4628 }, 4629 }, 4630 { 4631 name: "MOVSSstore", 4632 auxType: auxSymOff, 4633 argLen: 3, 4634 faultOnNilArg0: true, 4635 symEffect: SymWrite, 4636 asm: x86.AMOVSS, 4637 reg: regInfo{ 4638 inputs: []inputInfo{ 4639 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4640 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4641 }, 4642 }, 4643 }, 4644 { 4645 name: "MOVSDstore", 4646 auxType: auxSymOff, 4647 argLen: 3, 4648 faultOnNilArg0: true, 4649 symEffect: SymWrite, 4650 asm: x86.AMOVSD, 4651 reg: regInfo{ 4652 inputs: []inputInfo{ 4653 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4654 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4655 }, 4656 }, 4657 }, 4658 { 4659 name: "MOVSSstoreidx1", 4660 auxType: auxSymOff, 4661 argLen: 4, 4662 symEffect: SymWrite, 4663 asm: x86.AMOVSS, 4664 reg: regInfo{ 4665 inputs: []inputInfo{ 4666 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4667 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4668 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4669 }, 4670 }, 4671 }, 4672 { 4673 name: "MOVSSstoreidx4", 4674 auxType: auxSymOff, 4675 argLen: 4, 4676 symEffect: SymWrite, 4677 asm: x86.AMOVSS, 4678 reg: regInfo{ 4679 inputs: []inputInfo{ 4680 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4681 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4682 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4683 }, 4684 }, 4685 }, 4686 { 4687 name: "MOVSDstoreidx1", 4688 auxType: auxSymOff, 4689 argLen: 4, 4690 symEffect: SymWrite, 4691 asm: x86.AMOVSD, 4692 reg: regInfo{ 4693 inputs: []inputInfo{ 4694 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4695 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4696 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4697 }, 4698 }, 4699 }, 4700 { 4701 name: "MOVSDstoreidx8", 4702 auxType: auxSymOff, 4703 argLen: 4, 4704 symEffect: SymWrite, 4705 asm: x86.AMOVSD, 4706 reg: regInfo{ 4707 inputs: []inputInfo{ 4708 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4709 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4710 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4711 }, 4712 }, 4713 }, 4714 { 4715 name: "ADDSSmem", 4716 auxType: auxSymOff, 4717 argLen: 3, 4718 resultInArg0: true, 4719 faultOnNilArg1: true, 4720 symEffect: SymRead, 4721 asm: x86.AADDSS, 4722 reg: regInfo{ 4723 inputs: []inputInfo{ 4724 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4725 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4726 }, 4727 outputs: []outputInfo{ 4728 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4729 }, 4730 }, 4731 }, 4732 { 4733 name: "ADDSDmem", 4734 auxType: auxSymOff, 4735 argLen: 3, 4736 resultInArg0: true, 4737 faultOnNilArg1: true, 4738 symEffect: SymRead, 4739 asm: x86.AADDSD, 4740 reg: regInfo{ 4741 inputs: []inputInfo{ 4742 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4743 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4744 }, 4745 outputs: []outputInfo{ 4746 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4747 }, 4748 }, 4749 }, 4750 { 4751 name: "SUBSSmem", 4752 auxType: auxSymOff, 4753 argLen: 3, 4754 resultInArg0: true, 4755 faultOnNilArg1: true, 4756 symEffect: SymRead, 4757 asm: x86.ASUBSS, 4758 reg: regInfo{ 4759 inputs: []inputInfo{ 4760 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4761 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4762 }, 4763 outputs: []outputInfo{ 4764 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4765 }, 4766 }, 4767 }, 4768 { 4769 name: "SUBSDmem", 4770 auxType: auxSymOff, 4771 argLen: 3, 4772 resultInArg0: true, 4773 faultOnNilArg1: true, 4774 symEffect: SymRead, 4775 asm: x86.ASUBSD, 4776 reg: regInfo{ 4777 inputs: []inputInfo{ 4778 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4779 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4780 }, 4781 outputs: []outputInfo{ 4782 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4783 }, 4784 }, 4785 }, 4786 { 4787 name: "MULSSmem", 4788 auxType: auxSymOff, 4789 argLen: 3, 4790 resultInArg0: true, 4791 faultOnNilArg1: true, 4792 symEffect: SymRead, 4793 asm: x86.AMULSS, 4794 reg: regInfo{ 4795 inputs: []inputInfo{ 4796 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4797 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4798 }, 4799 outputs: []outputInfo{ 4800 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4801 }, 4802 }, 4803 }, 4804 { 4805 name: "MULSDmem", 4806 auxType: auxSymOff, 4807 argLen: 3, 4808 resultInArg0: true, 4809 faultOnNilArg1: true, 4810 symEffect: SymRead, 4811 asm: x86.AMULSD, 4812 reg: regInfo{ 4813 inputs: []inputInfo{ 4814 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4815 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4816 }, 4817 outputs: []outputInfo{ 4818 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4819 }, 4820 }, 4821 }, 4822 { 4823 name: "ADDQ", 4824 argLen: 2, 4825 commutative: true, 4826 clobberFlags: true, 4827 asm: x86.AADDQ, 4828 reg: regInfo{ 4829 inputs: []inputInfo{ 4830 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4831 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4832 }, 4833 outputs: []outputInfo{ 4834 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4835 }, 4836 }, 4837 }, 4838 { 4839 name: "ADDL", 4840 argLen: 2, 4841 commutative: true, 4842 clobberFlags: true, 4843 asm: x86.AADDL, 4844 reg: regInfo{ 4845 inputs: []inputInfo{ 4846 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4847 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4848 }, 4849 outputs: []outputInfo{ 4850 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4851 }, 4852 }, 4853 }, 4854 { 4855 name: "ADDQconst", 4856 auxType: auxInt32, 4857 argLen: 1, 4858 rematerializeable: true, 4859 clobberFlags: true, 4860 asm: x86.AADDQ, 4861 reg: regInfo{ 4862 inputs: []inputInfo{ 4863 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4864 }, 4865 outputs: []outputInfo{ 4866 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4867 }, 4868 }, 4869 }, 4870 { 4871 name: "ADDLconst", 4872 auxType: auxInt32, 4873 argLen: 1, 4874 rematerializeable: true, 4875 clobberFlags: true, 4876 asm: x86.AADDL, 4877 reg: regInfo{ 4878 inputs: []inputInfo{ 4879 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4880 }, 4881 outputs: []outputInfo{ 4882 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4883 }, 4884 }, 4885 }, 4886 { 4887 name: "ADDQconstmem", 4888 auxType: auxSymValAndOff, 4889 argLen: 2, 4890 clobberFlags: true, 4891 faultOnNilArg0: true, 4892 symEffect: SymWrite, 4893 asm: x86.AADDQ, 4894 reg: regInfo{ 4895 inputs: []inputInfo{ 4896 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4897 }, 4898 }, 4899 }, 4900 { 4901 name: "ADDLconstmem", 4902 auxType: auxSymValAndOff, 4903 argLen: 2, 4904 clobberFlags: true, 4905 faultOnNilArg0: true, 4906 symEffect: SymWrite, 4907 asm: x86.AADDL, 4908 reg: regInfo{ 4909 inputs: []inputInfo{ 4910 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4911 }, 4912 }, 4913 }, 4914 { 4915 name: "SUBQ", 4916 argLen: 2, 4917 resultInArg0: true, 4918 clobberFlags: true, 4919 asm: x86.ASUBQ, 4920 reg: regInfo{ 4921 inputs: []inputInfo{ 4922 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4923 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4924 }, 4925 outputs: []outputInfo{ 4926 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4927 }, 4928 }, 4929 }, 4930 { 4931 name: "SUBL", 4932 argLen: 2, 4933 resultInArg0: true, 4934 clobberFlags: true, 4935 asm: x86.ASUBL, 4936 reg: regInfo{ 4937 inputs: []inputInfo{ 4938 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4939 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4940 }, 4941 outputs: []outputInfo{ 4942 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4943 }, 4944 }, 4945 }, 4946 { 4947 name: "SUBQconst", 4948 auxType: auxInt32, 4949 argLen: 1, 4950 resultInArg0: true, 4951 clobberFlags: true, 4952 asm: x86.ASUBQ, 4953 reg: regInfo{ 4954 inputs: []inputInfo{ 4955 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4956 }, 4957 outputs: []outputInfo{ 4958 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4959 }, 4960 }, 4961 }, 4962 { 4963 name: "SUBLconst", 4964 auxType: auxInt32, 4965 argLen: 1, 4966 resultInArg0: true, 4967 clobberFlags: true, 4968 asm: x86.ASUBL, 4969 reg: regInfo{ 4970 inputs: []inputInfo{ 4971 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4972 }, 4973 outputs: []outputInfo{ 4974 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4975 }, 4976 }, 4977 }, 4978 { 4979 name: "MULQ", 4980 argLen: 2, 4981 commutative: true, 4982 resultInArg0: true, 4983 clobberFlags: true, 4984 asm: x86.AIMULQ, 4985 reg: regInfo{ 4986 inputs: []inputInfo{ 4987 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4988 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4989 }, 4990 outputs: []outputInfo{ 4991 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4992 }, 4993 }, 4994 }, 4995 { 4996 name: "MULL", 4997 argLen: 2, 4998 commutative: true, 4999 resultInArg0: true, 5000 clobberFlags: true, 5001 asm: x86.AIMULL, 5002 reg: regInfo{ 5003 inputs: []inputInfo{ 5004 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5005 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5006 }, 5007 outputs: []outputInfo{ 5008 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5009 }, 5010 }, 5011 }, 5012 { 5013 name: "MULQconst", 5014 auxType: auxInt32, 5015 argLen: 1, 5016 resultInArg0: true, 5017 clobberFlags: true, 5018 asm: x86.AIMULQ, 5019 reg: regInfo{ 5020 inputs: []inputInfo{ 5021 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5022 }, 5023 outputs: []outputInfo{ 5024 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5025 }, 5026 }, 5027 }, 5028 { 5029 name: "MULLconst", 5030 auxType: auxInt32, 5031 argLen: 1, 5032 resultInArg0: true, 5033 clobberFlags: true, 5034 asm: x86.AIMULL, 5035 reg: regInfo{ 5036 inputs: []inputInfo{ 5037 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5038 }, 5039 outputs: []outputInfo{ 5040 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5041 }, 5042 }, 5043 }, 5044 { 5045 name: "HMULQ", 5046 argLen: 2, 5047 commutative: true, 5048 clobberFlags: true, 5049 asm: x86.AIMULQ, 5050 reg: regInfo{ 5051 inputs: []inputInfo{ 5052 {0, 1}, // AX 5053 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5054 }, 5055 clobbers: 1, // AX 5056 outputs: []outputInfo{ 5057 {0, 4}, // DX 5058 }, 5059 }, 5060 }, 5061 { 5062 name: "HMULL", 5063 argLen: 2, 5064 commutative: true, 5065 clobberFlags: true, 5066 asm: x86.AIMULL, 5067 reg: regInfo{ 5068 inputs: []inputInfo{ 5069 {0, 1}, // AX 5070 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5071 }, 5072 clobbers: 1, // AX 5073 outputs: []outputInfo{ 5074 {0, 4}, // DX 5075 }, 5076 }, 5077 }, 5078 { 5079 name: "HMULQU", 5080 argLen: 2, 5081 commutative: true, 5082 clobberFlags: true, 5083 asm: x86.AMULQ, 5084 reg: regInfo{ 5085 inputs: []inputInfo{ 5086 {0, 1}, // AX 5087 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5088 }, 5089 clobbers: 1, // AX 5090 outputs: []outputInfo{ 5091 {0, 4}, // DX 5092 }, 5093 }, 5094 }, 5095 { 5096 name: "HMULLU", 5097 argLen: 2, 5098 commutative: true, 5099 clobberFlags: true, 5100 asm: x86.AMULL, 5101 reg: regInfo{ 5102 inputs: []inputInfo{ 5103 {0, 1}, // AX 5104 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5105 }, 5106 clobbers: 1, // AX 5107 outputs: []outputInfo{ 5108 {0, 4}, // DX 5109 }, 5110 }, 5111 }, 5112 { 5113 name: "AVGQU", 5114 argLen: 2, 5115 commutative: true, 5116 resultInArg0: true, 5117 clobberFlags: true, 5118 reg: regInfo{ 5119 inputs: []inputInfo{ 5120 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5121 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5122 }, 5123 outputs: []outputInfo{ 5124 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5125 }, 5126 }, 5127 }, 5128 { 5129 name: "DIVQ", 5130 argLen: 2, 5131 clobberFlags: true, 5132 asm: x86.AIDIVQ, 5133 reg: regInfo{ 5134 inputs: []inputInfo{ 5135 {0, 1}, // AX 5136 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5137 }, 5138 outputs: []outputInfo{ 5139 {0, 1}, // AX 5140 {1, 4}, // DX 5141 }, 5142 }, 5143 }, 5144 { 5145 name: "DIVL", 5146 argLen: 2, 5147 clobberFlags: true, 5148 asm: x86.AIDIVL, 5149 reg: regInfo{ 5150 inputs: []inputInfo{ 5151 {0, 1}, // AX 5152 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5153 }, 5154 outputs: []outputInfo{ 5155 {0, 1}, // AX 5156 {1, 4}, // DX 5157 }, 5158 }, 5159 }, 5160 { 5161 name: "DIVW", 5162 argLen: 2, 5163 clobberFlags: true, 5164 asm: x86.AIDIVW, 5165 reg: regInfo{ 5166 inputs: []inputInfo{ 5167 {0, 1}, // AX 5168 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5169 }, 5170 outputs: []outputInfo{ 5171 {0, 1}, // AX 5172 {1, 4}, // DX 5173 }, 5174 }, 5175 }, 5176 { 5177 name: "DIVQU", 5178 argLen: 2, 5179 clobberFlags: true, 5180 asm: x86.ADIVQ, 5181 reg: regInfo{ 5182 inputs: []inputInfo{ 5183 {0, 1}, // AX 5184 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5185 }, 5186 outputs: []outputInfo{ 5187 {0, 1}, // AX 5188 {1, 4}, // DX 5189 }, 5190 }, 5191 }, 5192 { 5193 name: "DIVLU", 5194 argLen: 2, 5195 clobberFlags: true, 5196 asm: x86.ADIVL, 5197 reg: regInfo{ 5198 inputs: []inputInfo{ 5199 {0, 1}, // AX 5200 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5201 }, 5202 outputs: []outputInfo{ 5203 {0, 1}, // AX 5204 {1, 4}, // DX 5205 }, 5206 }, 5207 }, 5208 { 5209 name: "DIVWU", 5210 argLen: 2, 5211 clobberFlags: true, 5212 asm: x86.ADIVW, 5213 reg: regInfo{ 5214 inputs: []inputInfo{ 5215 {0, 1}, // AX 5216 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5217 }, 5218 outputs: []outputInfo{ 5219 {0, 1}, // AX 5220 {1, 4}, // DX 5221 }, 5222 }, 5223 }, 5224 { 5225 name: "MULQU2", 5226 argLen: 2, 5227 commutative: true, 5228 clobberFlags: true, 5229 asm: x86.AMULQ, 5230 reg: regInfo{ 5231 inputs: []inputInfo{ 5232 {0, 1}, // AX 5233 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5234 }, 5235 outputs: []outputInfo{ 5236 {0, 4}, // DX 5237 {1, 1}, // AX 5238 }, 5239 }, 5240 }, 5241 { 5242 name: "DIVQU2", 5243 argLen: 3, 5244 clobberFlags: true, 5245 asm: x86.ADIVQ, 5246 reg: regInfo{ 5247 inputs: []inputInfo{ 5248 {0, 4}, // DX 5249 {1, 1}, // AX 5250 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5251 }, 5252 outputs: []outputInfo{ 5253 {0, 1}, // AX 5254 {1, 4}, // DX 5255 }, 5256 }, 5257 }, 5258 { 5259 name: "ANDQ", 5260 argLen: 2, 5261 commutative: true, 5262 resultInArg0: true, 5263 clobberFlags: true, 5264 asm: x86.AANDQ, 5265 reg: regInfo{ 5266 inputs: []inputInfo{ 5267 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5268 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5269 }, 5270 outputs: []outputInfo{ 5271 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5272 }, 5273 }, 5274 }, 5275 { 5276 name: "ANDL", 5277 argLen: 2, 5278 commutative: true, 5279 resultInArg0: true, 5280 clobberFlags: true, 5281 asm: x86.AANDL, 5282 reg: regInfo{ 5283 inputs: []inputInfo{ 5284 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5285 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5286 }, 5287 outputs: []outputInfo{ 5288 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5289 }, 5290 }, 5291 }, 5292 { 5293 name: "ANDQconst", 5294 auxType: auxInt32, 5295 argLen: 1, 5296 resultInArg0: true, 5297 clobberFlags: true, 5298 asm: x86.AANDQ, 5299 reg: regInfo{ 5300 inputs: []inputInfo{ 5301 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5302 }, 5303 outputs: []outputInfo{ 5304 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5305 }, 5306 }, 5307 }, 5308 { 5309 name: "ANDLconst", 5310 auxType: auxInt32, 5311 argLen: 1, 5312 resultInArg0: true, 5313 clobberFlags: true, 5314 asm: x86.AANDL, 5315 reg: regInfo{ 5316 inputs: []inputInfo{ 5317 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5318 }, 5319 outputs: []outputInfo{ 5320 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5321 }, 5322 }, 5323 }, 5324 { 5325 name: "ORQ", 5326 argLen: 2, 5327 commutative: true, 5328 resultInArg0: true, 5329 clobberFlags: true, 5330 asm: x86.AORQ, 5331 reg: regInfo{ 5332 inputs: []inputInfo{ 5333 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5334 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5335 }, 5336 outputs: []outputInfo{ 5337 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5338 }, 5339 }, 5340 }, 5341 { 5342 name: "ORL", 5343 argLen: 2, 5344 commutative: true, 5345 resultInArg0: true, 5346 clobberFlags: true, 5347 asm: x86.AORL, 5348 reg: regInfo{ 5349 inputs: []inputInfo{ 5350 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5351 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5352 }, 5353 outputs: []outputInfo{ 5354 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5355 }, 5356 }, 5357 }, 5358 { 5359 name: "ORQconst", 5360 auxType: auxInt32, 5361 argLen: 1, 5362 resultInArg0: true, 5363 clobberFlags: true, 5364 asm: x86.AORQ, 5365 reg: regInfo{ 5366 inputs: []inputInfo{ 5367 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5368 }, 5369 outputs: []outputInfo{ 5370 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5371 }, 5372 }, 5373 }, 5374 { 5375 name: "ORLconst", 5376 auxType: auxInt32, 5377 argLen: 1, 5378 resultInArg0: true, 5379 clobberFlags: true, 5380 asm: x86.AORL, 5381 reg: regInfo{ 5382 inputs: []inputInfo{ 5383 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5384 }, 5385 outputs: []outputInfo{ 5386 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5387 }, 5388 }, 5389 }, 5390 { 5391 name: "XORQ", 5392 argLen: 2, 5393 commutative: true, 5394 resultInArg0: true, 5395 clobberFlags: true, 5396 asm: x86.AXORQ, 5397 reg: regInfo{ 5398 inputs: []inputInfo{ 5399 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5400 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5401 }, 5402 outputs: []outputInfo{ 5403 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5404 }, 5405 }, 5406 }, 5407 { 5408 name: "XORL", 5409 argLen: 2, 5410 commutative: true, 5411 resultInArg0: true, 5412 clobberFlags: true, 5413 asm: x86.AXORL, 5414 reg: regInfo{ 5415 inputs: []inputInfo{ 5416 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5417 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5418 }, 5419 outputs: []outputInfo{ 5420 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5421 }, 5422 }, 5423 }, 5424 { 5425 name: "XORQconst", 5426 auxType: auxInt32, 5427 argLen: 1, 5428 resultInArg0: true, 5429 clobberFlags: true, 5430 asm: x86.AXORQ, 5431 reg: regInfo{ 5432 inputs: []inputInfo{ 5433 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5434 }, 5435 outputs: []outputInfo{ 5436 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5437 }, 5438 }, 5439 }, 5440 { 5441 name: "XORLconst", 5442 auxType: auxInt32, 5443 argLen: 1, 5444 resultInArg0: true, 5445 clobberFlags: true, 5446 asm: x86.AXORL, 5447 reg: regInfo{ 5448 inputs: []inputInfo{ 5449 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5450 }, 5451 outputs: []outputInfo{ 5452 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5453 }, 5454 }, 5455 }, 5456 { 5457 name: "CMPQ", 5458 argLen: 2, 5459 asm: x86.ACMPQ, 5460 reg: regInfo{ 5461 inputs: []inputInfo{ 5462 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5463 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5464 }, 5465 }, 5466 }, 5467 { 5468 name: "CMPL", 5469 argLen: 2, 5470 asm: x86.ACMPL, 5471 reg: regInfo{ 5472 inputs: []inputInfo{ 5473 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5474 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5475 }, 5476 }, 5477 }, 5478 { 5479 name: "CMPW", 5480 argLen: 2, 5481 asm: x86.ACMPW, 5482 reg: regInfo{ 5483 inputs: []inputInfo{ 5484 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5485 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5486 }, 5487 }, 5488 }, 5489 { 5490 name: "CMPB", 5491 argLen: 2, 5492 asm: x86.ACMPB, 5493 reg: regInfo{ 5494 inputs: []inputInfo{ 5495 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5496 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5497 }, 5498 }, 5499 }, 5500 { 5501 name: "CMPQconst", 5502 auxType: auxInt32, 5503 argLen: 1, 5504 asm: x86.ACMPQ, 5505 reg: regInfo{ 5506 inputs: []inputInfo{ 5507 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5508 }, 5509 }, 5510 }, 5511 { 5512 name: "CMPLconst", 5513 auxType: auxInt32, 5514 argLen: 1, 5515 asm: x86.ACMPL, 5516 reg: regInfo{ 5517 inputs: []inputInfo{ 5518 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5519 }, 5520 }, 5521 }, 5522 { 5523 name: "CMPWconst", 5524 auxType: auxInt16, 5525 argLen: 1, 5526 asm: x86.ACMPW, 5527 reg: regInfo{ 5528 inputs: []inputInfo{ 5529 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5530 }, 5531 }, 5532 }, 5533 { 5534 name: "CMPBconst", 5535 auxType: auxInt8, 5536 argLen: 1, 5537 asm: x86.ACMPB, 5538 reg: regInfo{ 5539 inputs: []inputInfo{ 5540 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5541 }, 5542 }, 5543 }, 5544 { 5545 name: "UCOMISS", 5546 argLen: 2, 5547 asm: x86.AUCOMISS, 5548 reg: regInfo{ 5549 inputs: []inputInfo{ 5550 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5551 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5552 }, 5553 }, 5554 }, 5555 { 5556 name: "UCOMISD", 5557 argLen: 2, 5558 asm: x86.AUCOMISD, 5559 reg: regInfo{ 5560 inputs: []inputInfo{ 5561 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5562 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5563 }, 5564 }, 5565 }, 5566 { 5567 name: "BTL", 5568 argLen: 2, 5569 asm: x86.ABTL, 5570 reg: regInfo{ 5571 inputs: []inputInfo{ 5572 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5573 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5574 }, 5575 }, 5576 }, 5577 { 5578 name: "BTQ", 5579 argLen: 2, 5580 asm: x86.ABTQ, 5581 reg: regInfo{ 5582 inputs: []inputInfo{ 5583 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5584 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5585 }, 5586 }, 5587 }, 5588 { 5589 name: "BTLconst", 5590 auxType: auxInt8, 5591 argLen: 1, 5592 asm: x86.ABTL, 5593 reg: regInfo{ 5594 inputs: []inputInfo{ 5595 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5596 }, 5597 }, 5598 }, 5599 { 5600 name: "BTQconst", 5601 auxType: auxInt8, 5602 argLen: 1, 5603 asm: x86.ABTQ, 5604 reg: regInfo{ 5605 inputs: []inputInfo{ 5606 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5607 }, 5608 }, 5609 }, 5610 { 5611 name: "TESTQ", 5612 argLen: 2, 5613 commutative: true, 5614 asm: x86.ATESTQ, 5615 reg: regInfo{ 5616 inputs: []inputInfo{ 5617 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5618 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5619 }, 5620 }, 5621 }, 5622 { 5623 name: "TESTL", 5624 argLen: 2, 5625 commutative: true, 5626 asm: x86.ATESTL, 5627 reg: regInfo{ 5628 inputs: []inputInfo{ 5629 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5630 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5631 }, 5632 }, 5633 }, 5634 { 5635 name: "TESTW", 5636 argLen: 2, 5637 commutative: true, 5638 asm: x86.ATESTW, 5639 reg: regInfo{ 5640 inputs: []inputInfo{ 5641 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5642 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5643 }, 5644 }, 5645 }, 5646 { 5647 name: "TESTB", 5648 argLen: 2, 5649 commutative: true, 5650 asm: x86.ATESTB, 5651 reg: regInfo{ 5652 inputs: []inputInfo{ 5653 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5654 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5655 }, 5656 }, 5657 }, 5658 { 5659 name: "TESTQconst", 5660 auxType: auxInt32, 5661 argLen: 1, 5662 asm: x86.ATESTQ, 5663 reg: regInfo{ 5664 inputs: []inputInfo{ 5665 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5666 }, 5667 }, 5668 }, 5669 { 5670 name: "TESTLconst", 5671 auxType: auxInt32, 5672 argLen: 1, 5673 asm: x86.ATESTL, 5674 reg: regInfo{ 5675 inputs: []inputInfo{ 5676 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5677 }, 5678 }, 5679 }, 5680 { 5681 name: "TESTWconst", 5682 auxType: auxInt16, 5683 argLen: 1, 5684 asm: x86.ATESTW, 5685 reg: regInfo{ 5686 inputs: []inputInfo{ 5687 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5688 }, 5689 }, 5690 }, 5691 { 5692 name: "TESTBconst", 5693 auxType: auxInt8, 5694 argLen: 1, 5695 asm: x86.ATESTB, 5696 reg: regInfo{ 5697 inputs: []inputInfo{ 5698 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5699 }, 5700 }, 5701 }, 5702 { 5703 name: "SHLQ", 5704 argLen: 2, 5705 resultInArg0: true, 5706 clobberFlags: true, 5707 asm: x86.ASHLQ, 5708 reg: regInfo{ 5709 inputs: []inputInfo{ 5710 {1, 2}, // CX 5711 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5712 }, 5713 outputs: []outputInfo{ 5714 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5715 }, 5716 }, 5717 }, 5718 { 5719 name: "SHLL", 5720 argLen: 2, 5721 resultInArg0: true, 5722 clobberFlags: true, 5723 asm: x86.ASHLL, 5724 reg: regInfo{ 5725 inputs: []inputInfo{ 5726 {1, 2}, // CX 5727 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5728 }, 5729 outputs: []outputInfo{ 5730 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5731 }, 5732 }, 5733 }, 5734 { 5735 name: "SHLQconst", 5736 auxType: auxInt8, 5737 argLen: 1, 5738 resultInArg0: true, 5739 clobberFlags: true, 5740 asm: x86.ASHLQ, 5741 reg: regInfo{ 5742 inputs: []inputInfo{ 5743 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5744 }, 5745 outputs: []outputInfo{ 5746 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5747 }, 5748 }, 5749 }, 5750 { 5751 name: "SHLLconst", 5752 auxType: auxInt8, 5753 argLen: 1, 5754 resultInArg0: true, 5755 clobberFlags: true, 5756 asm: x86.ASHLL, 5757 reg: regInfo{ 5758 inputs: []inputInfo{ 5759 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5760 }, 5761 outputs: []outputInfo{ 5762 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5763 }, 5764 }, 5765 }, 5766 { 5767 name: "SHRQ", 5768 argLen: 2, 5769 resultInArg0: true, 5770 clobberFlags: true, 5771 asm: x86.ASHRQ, 5772 reg: regInfo{ 5773 inputs: []inputInfo{ 5774 {1, 2}, // CX 5775 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5776 }, 5777 outputs: []outputInfo{ 5778 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5779 }, 5780 }, 5781 }, 5782 { 5783 name: "SHRL", 5784 argLen: 2, 5785 resultInArg0: true, 5786 clobberFlags: true, 5787 asm: x86.ASHRL, 5788 reg: regInfo{ 5789 inputs: []inputInfo{ 5790 {1, 2}, // CX 5791 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5792 }, 5793 outputs: []outputInfo{ 5794 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5795 }, 5796 }, 5797 }, 5798 { 5799 name: "SHRW", 5800 argLen: 2, 5801 resultInArg0: true, 5802 clobberFlags: true, 5803 asm: x86.ASHRW, 5804 reg: regInfo{ 5805 inputs: []inputInfo{ 5806 {1, 2}, // CX 5807 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5808 }, 5809 outputs: []outputInfo{ 5810 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5811 }, 5812 }, 5813 }, 5814 { 5815 name: "SHRB", 5816 argLen: 2, 5817 resultInArg0: true, 5818 clobberFlags: true, 5819 asm: x86.ASHRB, 5820 reg: regInfo{ 5821 inputs: []inputInfo{ 5822 {1, 2}, // CX 5823 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5824 }, 5825 outputs: []outputInfo{ 5826 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5827 }, 5828 }, 5829 }, 5830 { 5831 name: "SHRQconst", 5832 auxType: auxInt8, 5833 argLen: 1, 5834 resultInArg0: true, 5835 clobberFlags: true, 5836 asm: x86.ASHRQ, 5837 reg: regInfo{ 5838 inputs: []inputInfo{ 5839 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5840 }, 5841 outputs: []outputInfo{ 5842 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5843 }, 5844 }, 5845 }, 5846 { 5847 name: "SHRLconst", 5848 auxType: auxInt8, 5849 argLen: 1, 5850 resultInArg0: true, 5851 clobberFlags: true, 5852 asm: x86.ASHRL, 5853 reg: regInfo{ 5854 inputs: []inputInfo{ 5855 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5856 }, 5857 outputs: []outputInfo{ 5858 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5859 }, 5860 }, 5861 }, 5862 { 5863 name: "SHRWconst", 5864 auxType: auxInt8, 5865 argLen: 1, 5866 resultInArg0: true, 5867 clobberFlags: true, 5868 asm: x86.ASHRW, 5869 reg: regInfo{ 5870 inputs: []inputInfo{ 5871 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5872 }, 5873 outputs: []outputInfo{ 5874 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5875 }, 5876 }, 5877 }, 5878 { 5879 name: "SHRBconst", 5880 auxType: auxInt8, 5881 argLen: 1, 5882 resultInArg0: true, 5883 clobberFlags: true, 5884 asm: x86.ASHRB, 5885 reg: regInfo{ 5886 inputs: []inputInfo{ 5887 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5888 }, 5889 outputs: []outputInfo{ 5890 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5891 }, 5892 }, 5893 }, 5894 { 5895 name: "SARQ", 5896 argLen: 2, 5897 resultInArg0: true, 5898 clobberFlags: true, 5899 asm: x86.ASARQ, 5900 reg: regInfo{ 5901 inputs: []inputInfo{ 5902 {1, 2}, // CX 5903 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5904 }, 5905 outputs: []outputInfo{ 5906 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5907 }, 5908 }, 5909 }, 5910 { 5911 name: "SARL", 5912 argLen: 2, 5913 resultInArg0: true, 5914 clobberFlags: true, 5915 asm: x86.ASARL, 5916 reg: regInfo{ 5917 inputs: []inputInfo{ 5918 {1, 2}, // CX 5919 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5920 }, 5921 outputs: []outputInfo{ 5922 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5923 }, 5924 }, 5925 }, 5926 { 5927 name: "SARW", 5928 argLen: 2, 5929 resultInArg0: true, 5930 clobberFlags: true, 5931 asm: x86.ASARW, 5932 reg: regInfo{ 5933 inputs: []inputInfo{ 5934 {1, 2}, // CX 5935 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5936 }, 5937 outputs: []outputInfo{ 5938 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5939 }, 5940 }, 5941 }, 5942 { 5943 name: "SARB", 5944 argLen: 2, 5945 resultInArg0: true, 5946 clobberFlags: true, 5947 asm: x86.ASARB, 5948 reg: regInfo{ 5949 inputs: []inputInfo{ 5950 {1, 2}, // CX 5951 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5952 }, 5953 outputs: []outputInfo{ 5954 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5955 }, 5956 }, 5957 }, 5958 { 5959 name: "SARQconst", 5960 auxType: auxInt8, 5961 argLen: 1, 5962 resultInArg0: true, 5963 clobberFlags: true, 5964 asm: x86.ASARQ, 5965 reg: regInfo{ 5966 inputs: []inputInfo{ 5967 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5968 }, 5969 outputs: []outputInfo{ 5970 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5971 }, 5972 }, 5973 }, 5974 { 5975 name: "SARLconst", 5976 auxType: auxInt8, 5977 argLen: 1, 5978 resultInArg0: true, 5979 clobberFlags: true, 5980 asm: x86.ASARL, 5981 reg: regInfo{ 5982 inputs: []inputInfo{ 5983 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5984 }, 5985 outputs: []outputInfo{ 5986 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5987 }, 5988 }, 5989 }, 5990 { 5991 name: "SARWconst", 5992 auxType: auxInt8, 5993 argLen: 1, 5994 resultInArg0: true, 5995 clobberFlags: true, 5996 asm: x86.ASARW, 5997 reg: regInfo{ 5998 inputs: []inputInfo{ 5999 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6000 }, 6001 outputs: []outputInfo{ 6002 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6003 }, 6004 }, 6005 }, 6006 { 6007 name: "SARBconst", 6008 auxType: auxInt8, 6009 argLen: 1, 6010 resultInArg0: true, 6011 clobberFlags: true, 6012 asm: x86.ASARB, 6013 reg: regInfo{ 6014 inputs: []inputInfo{ 6015 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6016 }, 6017 outputs: []outputInfo{ 6018 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6019 }, 6020 }, 6021 }, 6022 { 6023 name: "ROLQ", 6024 argLen: 2, 6025 resultInArg0: true, 6026 clobberFlags: true, 6027 asm: x86.AROLQ, 6028 reg: regInfo{ 6029 inputs: []inputInfo{ 6030 {1, 2}, // CX 6031 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6032 }, 6033 outputs: []outputInfo{ 6034 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6035 }, 6036 }, 6037 }, 6038 { 6039 name: "ROLL", 6040 argLen: 2, 6041 resultInArg0: true, 6042 clobberFlags: true, 6043 asm: x86.AROLL, 6044 reg: regInfo{ 6045 inputs: []inputInfo{ 6046 {1, 2}, // CX 6047 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6048 }, 6049 outputs: []outputInfo{ 6050 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6051 }, 6052 }, 6053 }, 6054 { 6055 name: "ROLW", 6056 argLen: 2, 6057 resultInArg0: true, 6058 clobberFlags: true, 6059 asm: x86.AROLW, 6060 reg: regInfo{ 6061 inputs: []inputInfo{ 6062 {1, 2}, // CX 6063 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6064 }, 6065 outputs: []outputInfo{ 6066 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6067 }, 6068 }, 6069 }, 6070 { 6071 name: "ROLB", 6072 argLen: 2, 6073 resultInArg0: true, 6074 clobberFlags: true, 6075 asm: x86.AROLB, 6076 reg: regInfo{ 6077 inputs: []inputInfo{ 6078 {1, 2}, // CX 6079 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6080 }, 6081 outputs: []outputInfo{ 6082 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6083 }, 6084 }, 6085 }, 6086 { 6087 name: "RORQ", 6088 argLen: 2, 6089 resultInArg0: true, 6090 clobberFlags: true, 6091 asm: x86.ARORQ, 6092 reg: regInfo{ 6093 inputs: []inputInfo{ 6094 {1, 2}, // CX 6095 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6096 }, 6097 outputs: []outputInfo{ 6098 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6099 }, 6100 }, 6101 }, 6102 { 6103 name: "RORL", 6104 argLen: 2, 6105 resultInArg0: true, 6106 clobberFlags: true, 6107 asm: x86.ARORL, 6108 reg: regInfo{ 6109 inputs: []inputInfo{ 6110 {1, 2}, // CX 6111 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6112 }, 6113 outputs: []outputInfo{ 6114 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6115 }, 6116 }, 6117 }, 6118 { 6119 name: "RORW", 6120 argLen: 2, 6121 resultInArg0: true, 6122 clobberFlags: true, 6123 asm: x86.ARORW, 6124 reg: regInfo{ 6125 inputs: []inputInfo{ 6126 {1, 2}, // CX 6127 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6128 }, 6129 outputs: []outputInfo{ 6130 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6131 }, 6132 }, 6133 }, 6134 { 6135 name: "RORB", 6136 argLen: 2, 6137 resultInArg0: true, 6138 clobberFlags: true, 6139 asm: x86.ARORB, 6140 reg: regInfo{ 6141 inputs: []inputInfo{ 6142 {1, 2}, // CX 6143 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6144 }, 6145 outputs: []outputInfo{ 6146 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6147 }, 6148 }, 6149 }, 6150 { 6151 name: "ROLQconst", 6152 auxType: auxInt8, 6153 argLen: 1, 6154 resultInArg0: true, 6155 clobberFlags: true, 6156 asm: x86.AROLQ, 6157 reg: regInfo{ 6158 inputs: []inputInfo{ 6159 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6160 }, 6161 outputs: []outputInfo{ 6162 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6163 }, 6164 }, 6165 }, 6166 { 6167 name: "ROLLconst", 6168 auxType: auxInt8, 6169 argLen: 1, 6170 resultInArg0: true, 6171 clobberFlags: true, 6172 asm: x86.AROLL, 6173 reg: regInfo{ 6174 inputs: []inputInfo{ 6175 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6176 }, 6177 outputs: []outputInfo{ 6178 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6179 }, 6180 }, 6181 }, 6182 { 6183 name: "ROLWconst", 6184 auxType: auxInt8, 6185 argLen: 1, 6186 resultInArg0: true, 6187 clobberFlags: true, 6188 asm: x86.AROLW, 6189 reg: regInfo{ 6190 inputs: []inputInfo{ 6191 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6192 }, 6193 outputs: []outputInfo{ 6194 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6195 }, 6196 }, 6197 }, 6198 { 6199 name: "ROLBconst", 6200 auxType: auxInt8, 6201 argLen: 1, 6202 resultInArg0: true, 6203 clobberFlags: true, 6204 asm: x86.AROLB, 6205 reg: regInfo{ 6206 inputs: []inputInfo{ 6207 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6208 }, 6209 outputs: []outputInfo{ 6210 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6211 }, 6212 }, 6213 }, 6214 { 6215 name: "ADDLmem", 6216 auxType: auxSymOff, 6217 argLen: 3, 6218 resultInArg0: true, 6219 clobberFlags: true, 6220 faultOnNilArg1: true, 6221 symEffect: SymRead, 6222 asm: x86.AADDL, 6223 reg: regInfo{ 6224 inputs: []inputInfo{ 6225 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6226 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6227 }, 6228 outputs: []outputInfo{ 6229 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6230 }, 6231 }, 6232 }, 6233 { 6234 name: "ADDQmem", 6235 auxType: auxSymOff, 6236 argLen: 3, 6237 resultInArg0: true, 6238 clobberFlags: true, 6239 faultOnNilArg1: true, 6240 symEffect: SymRead, 6241 asm: x86.AADDQ, 6242 reg: regInfo{ 6243 inputs: []inputInfo{ 6244 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6245 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6246 }, 6247 outputs: []outputInfo{ 6248 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6249 }, 6250 }, 6251 }, 6252 { 6253 name: "SUBQmem", 6254 auxType: auxSymOff, 6255 argLen: 3, 6256 resultInArg0: true, 6257 clobberFlags: true, 6258 faultOnNilArg1: true, 6259 symEffect: SymRead, 6260 asm: x86.ASUBQ, 6261 reg: regInfo{ 6262 inputs: []inputInfo{ 6263 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6264 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6265 }, 6266 outputs: []outputInfo{ 6267 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6268 }, 6269 }, 6270 }, 6271 { 6272 name: "SUBLmem", 6273 auxType: auxSymOff, 6274 argLen: 3, 6275 resultInArg0: true, 6276 clobberFlags: true, 6277 faultOnNilArg1: true, 6278 symEffect: SymRead, 6279 asm: x86.ASUBL, 6280 reg: regInfo{ 6281 inputs: []inputInfo{ 6282 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6283 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6284 }, 6285 outputs: []outputInfo{ 6286 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6287 }, 6288 }, 6289 }, 6290 { 6291 name: "ANDLmem", 6292 auxType: auxSymOff, 6293 argLen: 3, 6294 resultInArg0: true, 6295 clobberFlags: true, 6296 faultOnNilArg1: true, 6297 symEffect: SymRead, 6298 asm: x86.AANDL, 6299 reg: regInfo{ 6300 inputs: []inputInfo{ 6301 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6302 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6303 }, 6304 outputs: []outputInfo{ 6305 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6306 }, 6307 }, 6308 }, 6309 { 6310 name: "ANDQmem", 6311 auxType: auxSymOff, 6312 argLen: 3, 6313 resultInArg0: true, 6314 clobberFlags: true, 6315 faultOnNilArg1: true, 6316 symEffect: SymRead, 6317 asm: x86.AANDQ, 6318 reg: regInfo{ 6319 inputs: []inputInfo{ 6320 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6321 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6322 }, 6323 outputs: []outputInfo{ 6324 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6325 }, 6326 }, 6327 }, 6328 { 6329 name: "ORQmem", 6330 auxType: auxSymOff, 6331 argLen: 3, 6332 resultInArg0: true, 6333 clobberFlags: true, 6334 faultOnNilArg1: true, 6335 symEffect: SymRead, 6336 asm: x86.AORQ, 6337 reg: regInfo{ 6338 inputs: []inputInfo{ 6339 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6340 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6341 }, 6342 outputs: []outputInfo{ 6343 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6344 }, 6345 }, 6346 }, 6347 { 6348 name: "ORLmem", 6349 auxType: auxSymOff, 6350 argLen: 3, 6351 resultInArg0: true, 6352 clobberFlags: true, 6353 faultOnNilArg1: true, 6354 symEffect: SymRead, 6355 asm: x86.AORL, 6356 reg: regInfo{ 6357 inputs: []inputInfo{ 6358 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6359 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6360 }, 6361 outputs: []outputInfo{ 6362 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6363 }, 6364 }, 6365 }, 6366 { 6367 name: "XORQmem", 6368 auxType: auxSymOff, 6369 argLen: 3, 6370 resultInArg0: true, 6371 clobberFlags: true, 6372 faultOnNilArg1: true, 6373 symEffect: SymRead, 6374 asm: x86.AXORQ, 6375 reg: regInfo{ 6376 inputs: []inputInfo{ 6377 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6378 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6379 }, 6380 outputs: []outputInfo{ 6381 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6382 }, 6383 }, 6384 }, 6385 { 6386 name: "XORLmem", 6387 auxType: auxSymOff, 6388 argLen: 3, 6389 resultInArg0: true, 6390 clobberFlags: true, 6391 faultOnNilArg1: true, 6392 symEffect: SymRead, 6393 asm: x86.AXORL, 6394 reg: regInfo{ 6395 inputs: []inputInfo{ 6396 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6397 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6398 }, 6399 outputs: []outputInfo{ 6400 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6401 }, 6402 }, 6403 }, 6404 { 6405 name: "NEGQ", 6406 argLen: 1, 6407 resultInArg0: true, 6408 clobberFlags: true, 6409 asm: x86.ANEGQ, 6410 reg: regInfo{ 6411 inputs: []inputInfo{ 6412 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6413 }, 6414 outputs: []outputInfo{ 6415 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6416 }, 6417 }, 6418 }, 6419 { 6420 name: "NEGL", 6421 argLen: 1, 6422 resultInArg0: true, 6423 clobberFlags: true, 6424 asm: x86.ANEGL, 6425 reg: regInfo{ 6426 inputs: []inputInfo{ 6427 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6428 }, 6429 outputs: []outputInfo{ 6430 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6431 }, 6432 }, 6433 }, 6434 { 6435 name: "NOTQ", 6436 argLen: 1, 6437 resultInArg0: true, 6438 clobberFlags: true, 6439 asm: x86.ANOTQ, 6440 reg: regInfo{ 6441 inputs: []inputInfo{ 6442 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6443 }, 6444 outputs: []outputInfo{ 6445 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6446 }, 6447 }, 6448 }, 6449 { 6450 name: "NOTL", 6451 argLen: 1, 6452 resultInArg0: true, 6453 clobberFlags: true, 6454 asm: x86.ANOTL, 6455 reg: regInfo{ 6456 inputs: []inputInfo{ 6457 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6458 }, 6459 outputs: []outputInfo{ 6460 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6461 }, 6462 }, 6463 }, 6464 { 6465 name: "BSFQ", 6466 argLen: 1, 6467 asm: x86.ABSFQ, 6468 reg: regInfo{ 6469 inputs: []inputInfo{ 6470 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6471 }, 6472 outputs: []outputInfo{ 6473 {1, 0}, 6474 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6475 }, 6476 }, 6477 }, 6478 { 6479 name: "BSFL", 6480 argLen: 1, 6481 asm: x86.ABSFL, 6482 reg: regInfo{ 6483 inputs: []inputInfo{ 6484 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6485 }, 6486 outputs: []outputInfo{ 6487 {1, 0}, 6488 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6489 }, 6490 }, 6491 }, 6492 { 6493 name: "BSRQ", 6494 argLen: 1, 6495 asm: x86.ABSRQ, 6496 reg: regInfo{ 6497 inputs: []inputInfo{ 6498 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6499 }, 6500 outputs: []outputInfo{ 6501 {1, 0}, 6502 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6503 }, 6504 }, 6505 }, 6506 { 6507 name: "BSRL", 6508 argLen: 1, 6509 asm: x86.ABSRL, 6510 reg: regInfo{ 6511 inputs: []inputInfo{ 6512 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6513 }, 6514 outputs: []outputInfo{ 6515 {1, 0}, 6516 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6517 }, 6518 }, 6519 }, 6520 { 6521 name: "CMOVQEQ", 6522 argLen: 3, 6523 resultInArg0: true, 6524 asm: x86.ACMOVQEQ, 6525 reg: regInfo{ 6526 inputs: []inputInfo{ 6527 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6528 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6529 }, 6530 outputs: []outputInfo{ 6531 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6532 }, 6533 }, 6534 }, 6535 { 6536 name: "CMOVLEQ", 6537 argLen: 3, 6538 resultInArg0: true, 6539 asm: x86.ACMOVLEQ, 6540 reg: regInfo{ 6541 inputs: []inputInfo{ 6542 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6543 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6544 }, 6545 outputs: []outputInfo{ 6546 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6547 }, 6548 }, 6549 }, 6550 { 6551 name: "BSWAPQ", 6552 argLen: 1, 6553 resultInArg0: true, 6554 clobberFlags: true, 6555 asm: x86.ABSWAPQ, 6556 reg: regInfo{ 6557 inputs: []inputInfo{ 6558 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6559 }, 6560 outputs: []outputInfo{ 6561 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6562 }, 6563 }, 6564 }, 6565 { 6566 name: "BSWAPL", 6567 argLen: 1, 6568 resultInArg0: true, 6569 clobberFlags: true, 6570 asm: x86.ABSWAPL, 6571 reg: regInfo{ 6572 inputs: []inputInfo{ 6573 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6574 }, 6575 outputs: []outputInfo{ 6576 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6577 }, 6578 }, 6579 }, 6580 { 6581 name: "POPCNTQ", 6582 argLen: 1, 6583 clobberFlags: true, 6584 asm: x86.APOPCNTQ, 6585 reg: regInfo{ 6586 inputs: []inputInfo{ 6587 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6588 }, 6589 outputs: []outputInfo{ 6590 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6591 }, 6592 }, 6593 }, 6594 { 6595 name: "POPCNTL", 6596 argLen: 1, 6597 clobberFlags: true, 6598 asm: x86.APOPCNTL, 6599 reg: regInfo{ 6600 inputs: []inputInfo{ 6601 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6602 }, 6603 outputs: []outputInfo{ 6604 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6605 }, 6606 }, 6607 }, 6608 { 6609 name: "SQRTSD", 6610 argLen: 1, 6611 asm: x86.ASQRTSD, 6612 reg: regInfo{ 6613 inputs: []inputInfo{ 6614 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6615 }, 6616 outputs: []outputInfo{ 6617 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6618 }, 6619 }, 6620 }, 6621 { 6622 name: "SBBQcarrymask", 6623 argLen: 1, 6624 asm: x86.ASBBQ, 6625 reg: regInfo{ 6626 outputs: []outputInfo{ 6627 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6628 }, 6629 }, 6630 }, 6631 { 6632 name: "SBBLcarrymask", 6633 argLen: 1, 6634 asm: x86.ASBBL, 6635 reg: regInfo{ 6636 outputs: []outputInfo{ 6637 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6638 }, 6639 }, 6640 }, 6641 { 6642 name: "SETEQ", 6643 argLen: 1, 6644 asm: x86.ASETEQ, 6645 reg: regInfo{ 6646 outputs: []outputInfo{ 6647 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6648 }, 6649 }, 6650 }, 6651 { 6652 name: "SETNE", 6653 argLen: 1, 6654 asm: x86.ASETNE, 6655 reg: regInfo{ 6656 outputs: []outputInfo{ 6657 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6658 }, 6659 }, 6660 }, 6661 { 6662 name: "SETL", 6663 argLen: 1, 6664 asm: x86.ASETLT, 6665 reg: regInfo{ 6666 outputs: []outputInfo{ 6667 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6668 }, 6669 }, 6670 }, 6671 { 6672 name: "SETLE", 6673 argLen: 1, 6674 asm: x86.ASETLE, 6675 reg: regInfo{ 6676 outputs: []outputInfo{ 6677 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6678 }, 6679 }, 6680 }, 6681 { 6682 name: "SETG", 6683 argLen: 1, 6684 asm: x86.ASETGT, 6685 reg: regInfo{ 6686 outputs: []outputInfo{ 6687 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6688 }, 6689 }, 6690 }, 6691 { 6692 name: "SETGE", 6693 argLen: 1, 6694 asm: x86.ASETGE, 6695 reg: regInfo{ 6696 outputs: []outputInfo{ 6697 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6698 }, 6699 }, 6700 }, 6701 { 6702 name: "SETB", 6703 argLen: 1, 6704 asm: x86.ASETCS, 6705 reg: regInfo{ 6706 outputs: []outputInfo{ 6707 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6708 }, 6709 }, 6710 }, 6711 { 6712 name: "SETBE", 6713 argLen: 1, 6714 asm: x86.ASETLS, 6715 reg: regInfo{ 6716 outputs: []outputInfo{ 6717 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6718 }, 6719 }, 6720 }, 6721 { 6722 name: "SETA", 6723 argLen: 1, 6724 asm: x86.ASETHI, 6725 reg: regInfo{ 6726 outputs: []outputInfo{ 6727 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6728 }, 6729 }, 6730 }, 6731 { 6732 name: "SETAE", 6733 argLen: 1, 6734 asm: x86.ASETCC, 6735 reg: regInfo{ 6736 outputs: []outputInfo{ 6737 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6738 }, 6739 }, 6740 }, 6741 { 6742 name: "SETEQF", 6743 argLen: 1, 6744 clobberFlags: true, 6745 asm: x86.ASETEQ, 6746 reg: regInfo{ 6747 clobbers: 1, // AX 6748 outputs: []outputInfo{ 6749 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6750 }, 6751 }, 6752 }, 6753 { 6754 name: "SETNEF", 6755 argLen: 1, 6756 clobberFlags: true, 6757 asm: x86.ASETNE, 6758 reg: regInfo{ 6759 clobbers: 1, // AX 6760 outputs: []outputInfo{ 6761 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6762 }, 6763 }, 6764 }, 6765 { 6766 name: "SETORD", 6767 argLen: 1, 6768 asm: x86.ASETPC, 6769 reg: regInfo{ 6770 outputs: []outputInfo{ 6771 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6772 }, 6773 }, 6774 }, 6775 { 6776 name: "SETNAN", 6777 argLen: 1, 6778 asm: x86.ASETPS, 6779 reg: regInfo{ 6780 outputs: []outputInfo{ 6781 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6782 }, 6783 }, 6784 }, 6785 { 6786 name: "SETGF", 6787 argLen: 1, 6788 asm: x86.ASETHI, 6789 reg: regInfo{ 6790 outputs: []outputInfo{ 6791 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6792 }, 6793 }, 6794 }, 6795 { 6796 name: "SETGEF", 6797 argLen: 1, 6798 asm: x86.ASETCC, 6799 reg: regInfo{ 6800 outputs: []outputInfo{ 6801 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6802 }, 6803 }, 6804 }, 6805 { 6806 name: "MOVBQSX", 6807 argLen: 1, 6808 asm: x86.AMOVBQSX, 6809 reg: regInfo{ 6810 inputs: []inputInfo{ 6811 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6812 }, 6813 outputs: []outputInfo{ 6814 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6815 }, 6816 }, 6817 }, 6818 { 6819 name: "MOVBQZX", 6820 argLen: 1, 6821 asm: x86.AMOVBLZX, 6822 reg: regInfo{ 6823 inputs: []inputInfo{ 6824 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6825 }, 6826 outputs: []outputInfo{ 6827 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6828 }, 6829 }, 6830 }, 6831 { 6832 name: "MOVWQSX", 6833 argLen: 1, 6834 asm: x86.AMOVWQSX, 6835 reg: regInfo{ 6836 inputs: []inputInfo{ 6837 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6838 }, 6839 outputs: []outputInfo{ 6840 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6841 }, 6842 }, 6843 }, 6844 { 6845 name: "MOVWQZX", 6846 argLen: 1, 6847 asm: x86.AMOVWLZX, 6848 reg: regInfo{ 6849 inputs: []inputInfo{ 6850 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6851 }, 6852 outputs: []outputInfo{ 6853 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6854 }, 6855 }, 6856 }, 6857 { 6858 name: "MOVLQSX", 6859 argLen: 1, 6860 asm: x86.AMOVLQSX, 6861 reg: regInfo{ 6862 inputs: []inputInfo{ 6863 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6864 }, 6865 outputs: []outputInfo{ 6866 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6867 }, 6868 }, 6869 }, 6870 { 6871 name: "MOVLQZX", 6872 argLen: 1, 6873 asm: x86.AMOVL, 6874 reg: regInfo{ 6875 inputs: []inputInfo{ 6876 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6877 }, 6878 outputs: []outputInfo{ 6879 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6880 }, 6881 }, 6882 }, 6883 { 6884 name: "MOVLconst", 6885 auxType: auxInt32, 6886 argLen: 0, 6887 rematerializeable: true, 6888 asm: x86.AMOVL, 6889 reg: regInfo{ 6890 outputs: []outputInfo{ 6891 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6892 }, 6893 }, 6894 }, 6895 { 6896 name: "MOVQconst", 6897 auxType: auxInt64, 6898 argLen: 0, 6899 rematerializeable: true, 6900 asm: x86.AMOVQ, 6901 reg: regInfo{ 6902 outputs: []outputInfo{ 6903 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6904 }, 6905 }, 6906 }, 6907 { 6908 name: "CVTTSD2SL", 6909 argLen: 1, 6910 asm: x86.ACVTTSD2SL, 6911 reg: regInfo{ 6912 inputs: []inputInfo{ 6913 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6914 }, 6915 outputs: []outputInfo{ 6916 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6917 }, 6918 }, 6919 }, 6920 { 6921 name: "CVTTSD2SQ", 6922 argLen: 1, 6923 asm: x86.ACVTTSD2SQ, 6924 reg: regInfo{ 6925 inputs: []inputInfo{ 6926 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6927 }, 6928 outputs: []outputInfo{ 6929 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6930 }, 6931 }, 6932 }, 6933 { 6934 name: "CVTTSS2SL", 6935 argLen: 1, 6936 asm: x86.ACVTTSS2SL, 6937 reg: regInfo{ 6938 inputs: []inputInfo{ 6939 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6940 }, 6941 outputs: []outputInfo{ 6942 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6943 }, 6944 }, 6945 }, 6946 { 6947 name: "CVTTSS2SQ", 6948 argLen: 1, 6949 asm: x86.ACVTTSS2SQ, 6950 reg: regInfo{ 6951 inputs: []inputInfo{ 6952 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6953 }, 6954 outputs: []outputInfo{ 6955 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6956 }, 6957 }, 6958 }, 6959 { 6960 name: "CVTSL2SS", 6961 argLen: 1, 6962 asm: x86.ACVTSL2SS, 6963 reg: regInfo{ 6964 inputs: []inputInfo{ 6965 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6966 }, 6967 outputs: []outputInfo{ 6968 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6969 }, 6970 }, 6971 }, 6972 { 6973 name: "CVTSL2SD", 6974 argLen: 1, 6975 asm: x86.ACVTSL2SD, 6976 reg: regInfo{ 6977 inputs: []inputInfo{ 6978 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6979 }, 6980 outputs: []outputInfo{ 6981 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6982 }, 6983 }, 6984 }, 6985 { 6986 name: "CVTSQ2SS", 6987 argLen: 1, 6988 asm: x86.ACVTSQ2SS, 6989 reg: regInfo{ 6990 inputs: []inputInfo{ 6991 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6992 }, 6993 outputs: []outputInfo{ 6994 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6995 }, 6996 }, 6997 }, 6998 { 6999 name: "CVTSQ2SD", 7000 argLen: 1, 7001 asm: x86.ACVTSQ2SD, 7002 reg: regInfo{ 7003 inputs: []inputInfo{ 7004 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7005 }, 7006 outputs: []outputInfo{ 7007 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7008 }, 7009 }, 7010 }, 7011 { 7012 name: "CVTSD2SS", 7013 argLen: 1, 7014 asm: x86.ACVTSD2SS, 7015 reg: regInfo{ 7016 inputs: []inputInfo{ 7017 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7018 }, 7019 outputs: []outputInfo{ 7020 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7021 }, 7022 }, 7023 }, 7024 { 7025 name: "CVTSS2SD", 7026 argLen: 1, 7027 asm: x86.ACVTSS2SD, 7028 reg: regInfo{ 7029 inputs: []inputInfo{ 7030 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7031 }, 7032 outputs: []outputInfo{ 7033 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7034 }, 7035 }, 7036 }, 7037 { 7038 name: "MOVQi2f", 7039 argLen: 1, 7040 reg: regInfo{ 7041 inputs: []inputInfo{ 7042 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7043 }, 7044 outputs: []outputInfo{ 7045 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7046 }, 7047 }, 7048 }, 7049 { 7050 name: "MOVQf2i", 7051 argLen: 1, 7052 reg: regInfo{ 7053 inputs: []inputInfo{ 7054 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7055 }, 7056 outputs: []outputInfo{ 7057 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7058 }, 7059 }, 7060 }, 7061 { 7062 name: "MOVLi2f", 7063 argLen: 1, 7064 reg: regInfo{ 7065 inputs: []inputInfo{ 7066 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7067 }, 7068 outputs: []outputInfo{ 7069 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7070 }, 7071 }, 7072 }, 7073 { 7074 name: "MOVLf2i", 7075 argLen: 1, 7076 reg: regInfo{ 7077 inputs: []inputInfo{ 7078 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7079 }, 7080 outputs: []outputInfo{ 7081 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7082 }, 7083 }, 7084 }, 7085 { 7086 name: "PXOR", 7087 argLen: 2, 7088 commutative: true, 7089 resultInArg0: true, 7090 asm: x86.APXOR, 7091 reg: regInfo{ 7092 inputs: []inputInfo{ 7093 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7094 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7095 }, 7096 outputs: []outputInfo{ 7097 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7098 }, 7099 }, 7100 }, 7101 { 7102 name: "LEAQ", 7103 auxType: auxSymOff, 7104 argLen: 1, 7105 rematerializeable: true, 7106 symEffect: SymAddr, 7107 asm: x86.ALEAQ, 7108 reg: regInfo{ 7109 inputs: []inputInfo{ 7110 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7111 }, 7112 outputs: []outputInfo{ 7113 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7114 }, 7115 }, 7116 }, 7117 { 7118 name: "LEAQ1", 7119 auxType: auxSymOff, 7120 argLen: 2, 7121 commutative: true, 7122 symEffect: SymAddr, 7123 reg: regInfo{ 7124 inputs: []inputInfo{ 7125 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7126 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7127 }, 7128 outputs: []outputInfo{ 7129 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7130 }, 7131 }, 7132 }, 7133 { 7134 name: "LEAQ2", 7135 auxType: auxSymOff, 7136 argLen: 2, 7137 symEffect: SymAddr, 7138 reg: regInfo{ 7139 inputs: []inputInfo{ 7140 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7141 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7142 }, 7143 outputs: []outputInfo{ 7144 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7145 }, 7146 }, 7147 }, 7148 { 7149 name: "LEAQ4", 7150 auxType: auxSymOff, 7151 argLen: 2, 7152 symEffect: SymAddr, 7153 reg: regInfo{ 7154 inputs: []inputInfo{ 7155 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7156 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7157 }, 7158 outputs: []outputInfo{ 7159 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7160 }, 7161 }, 7162 }, 7163 { 7164 name: "LEAQ8", 7165 auxType: auxSymOff, 7166 argLen: 2, 7167 symEffect: SymAddr, 7168 reg: regInfo{ 7169 inputs: []inputInfo{ 7170 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7171 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7172 }, 7173 outputs: []outputInfo{ 7174 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7175 }, 7176 }, 7177 }, 7178 { 7179 name: "LEAL", 7180 auxType: auxSymOff, 7181 argLen: 1, 7182 rematerializeable: true, 7183 symEffect: SymAddr, 7184 asm: x86.ALEAL, 7185 reg: regInfo{ 7186 inputs: []inputInfo{ 7187 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7188 }, 7189 outputs: []outputInfo{ 7190 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7191 }, 7192 }, 7193 }, 7194 { 7195 name: "MOVBload", 7196 auxType: auxSymOff, 7197 argLen: 2, 7198 faultOnNilArg0: true, 7199 symEffect: SymRead, 7200 asm: x86.AMOVBLZX, 7201 reg: regInfo{ 7202 inputs: []inputInfo{ 7203 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7204 }, 7205 outputs: []outputInfo{ 7206 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7207 }, 7208 }, 7209 }, 7210 { 7211 name: "MOVBQSXload", 7212 auxType: auxSymOff, 7213 argLen: 2, 7214 faultOnNilArg0: true, 7215 symEffect: SymRead, 7216 asm: x86.AMOVBQSX, 7217 reg: regInfo{ 7218 inputs: []inputInfo{ 7219 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7220 }, 7221 outputs: []outputInfo{ 7222 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7223 }, 7224 }, 7225 }, 7226 { 7227 name: "MOVWload", 7228 auxType: auxSymOff, 7229 argLen: 2, 7230 faultOnNilArg0: true, 7231 symEffect: SymRead, 7232 asm: x86.AMOVWLZX, 7233 reg: regInfo{ 7234 inputs: []inputInfo{ 7235 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7236 }, 7237 outputs: []outputInfo{ 7238 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7239 }, 7240 }, 7241 }, 7242 { 7243 name: "MOVWQSXload", 7244 auxType: auxSymOff, 7245 argLen: 2, 7246 faultOnNilArg0: true, 7247 symEffect: SymRead, 7248 asm: x86.AMOVWQSX, 7249 reg: regInfo{ 7250 inputs: []inputInfo{ 7251 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7252 }, 7253 outputs: []outputInfo{ 7254 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7255 }, 7256 }, 7257 }, 7258 { 7259 name: "MOVLload", 7260 auxType: auxSymOff, 7261 argLen: 2, 7262 faultOnNilArg0: true, 7263 symEffect: SymRead, 7264 asm: x86.AMOVL, 7265 reg: regInfo{ 7266 inputs: []inputInfo{ 7267 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7268 }, 7269 outputs: []outputInfo{ 7270 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7271 }, 7272 }, 7273 }, 7274 { 7275 name: "MOVLQSXload", 7276 auxType: auxSymOff, 7277 argLen: 2, 7278 faultOnNilArg0: true, 7279 symEffect: SymRead, 7280 asm: x86.AMOVLQSX, 7281 reg: regInfo{ 7282 inputs: []inputInfo{ 7283 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7284 }, 7285 outputs: []outputInfo{ 7286 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7287 }, 7288 }, 7289 }, 7290 { 7291 name: "MOVQload", 7292 auxType: auxSymOff, 7293 argLen: 2, 7294 faultOnNilArg0: true, 7295 symEffect: SymRead, 7296 asm: x86.AMOVQ, 7297 reg: regInfo{ 7298 inputs: []inputInfo{ 7299 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7300 }, 7301 outputs: []outputInfo{ 7302 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7303 }, 7304 }, 7305 }, 7306 { 7307 name: "MOVBstore", 7308 auxType: auxSymOff, 7309 argLen: 3, 7310 faultOnNilArg0: true, 7311 symEffect: SymWrite, 7312 asm: x86.AMOVB, 7313 reg: regInfo{ 7314 inputs: []inputInfo{ 7315 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7316 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7317 }, 7318 }, 7319 }, 7320 { 7321 name: "MOVWstore", 7322 auxType: auxSymOff, 7323 argLen: 3, 7324 faultOnNilArg0: true, 7325 symEffect: SymWrite, 7326 asm: x86.AMOVW, 7327 reg: regInfo{ 7328 inputs: []inputInfo{ 7329 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7330 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7331 }, 7332 }, 7333 }, 7334 { 7335 name: "MOVLstore", 7336 auxType: auxSymOff, 7337 argLen: 3, 7338 faultOnNilArg0: true, 7339 symEffect: SymWrite, 7340 asm: x86.AMOVL, 7341 reg: regInfo{ 7342 inputs: []inputInfo{ 7343 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7344 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7345 }, 7346 }, 7347 }, 7348 { 7349 name: "MOVQstore", 7350 auxType: auxSymOff, 7351 argLen: 3, 7352 faultOnNilArg0: true, 7353 symEffect: SymWrite, 7354 asm: x86.AMOVQ, 7355 reg: regInfo{ 7356 inputs: []inputInfo{ 7357 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7358 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7359 }, 7360 }, 7361 }, 7362 { 7363 name: "MOVOload", 7364 auxType: auxSymOff, 7365 argLen: 2, 7366 faultOnNilArg0: true, 7367 symEffect: SymRead, 7368 asm: x86.AMOVUPS, 7369 reg: regInfo{ 7370 inputs: []inputInfo{ 7371 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7372 }, 7373 outputs: []outputInfo{ 7374 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7375 }, 7376 }, 7377 }, 7378 { 7379 name: "MOVOstore", 7380 auxType: auxSymOff, 7381 argLen: 3, 7382 faultOnNilArg0: true, 7383 symEffect: SymWrite, 7384 asm: x86.AMOVUPS, 7385 reg: regInfo{ 7386 inputs: []inputInfo{ 7387 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7388 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7389 }, 7390 }, 7391 }, 7392 { 7393 name: "MOVBloadidx1", 7394 auxType: auxSymOff, 7395 argLen: 3, 7396 commutative: true, 7397 symEffect: SymRead, 7398 asm: x86.AMOVBLZX, 7399 reg: regInfo{ 7400 inputs: []inputInfo{ 7401 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7402 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7403 }, 7404 outputs: []outputInfo{ 7405 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7406 }, 7407 }, 7408 }, 7409 { 7410 name: "MOVWloadidx1", 7411 auxType: auxSymOff, 7412 argLen: 3, 7413 commutative: true, 7414 symEffect: SymRead, 7415 asm: x86.AMOVWLZX, 7416 reg: regInfo{ 7417 inputs: []inputInfo{ 7418 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7419 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7420 }, 7421 outputs: []outputInfo{ 7422 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7423 }, 7424 }, 7425 }, 7426 { 7427 name: "MOVWloadidx2", 7428 auxType: auxSymOff, 7429 argLen: 3, 7430 symEffect: SymRead, 7431 asm: x86.AMOVWLZX, 7432 reg: regInfo{ 7433 inputs: []inputInfo{ 7434 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7435 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7436 }, 7437 outputs: []outputInfo{ 7438 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7439 }, 7440 }, 7441 }, 7442 { 7443 name: "MOVLloadidx1", 7444 auxType: auxSymOff, 7445 argLen: 3, 7446 commutative: true, 7447 symEffect: SymRead, 7448 asm: x86.AMOVL, 7449 reg: regInfo{ 7450 inputs: []inputInfo{ 7451 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7452 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7453 }, 7454 outputs: []outputInfo{ 7455 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7456 }, 7457 }, 7458 }, 7459 { 7460 name: "MOVLloadidx4", 7461 auxType: auxSymOff, 7462 argLen: 3, 7463 symEffect: SymRead, 7464 asm: x86.AMOVL, 7465 reg: regInfo{ 7466 inputs: []inputInfo{ 7467 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7468 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7469 }, 7470 outputs: []outputInfo{ 7471 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7472 }, 7473 }, 7474 }, 7475 { 7476 name: "MOVLloadidx8", 7477 auxType: auxSymOff, 7478 argLen: 3, 7479 symEffect: SymRead, 7480 asm: x86.AMOVL, 7481 reg: regInfo{ 7482 inputs: []inputInfo{ 7483 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7484 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7485 }, 7486 outputs: []outputInfo{ 7487 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7488 }, 7489 }, 7490 }, 7491 { 7492 name: "MOVQloadidx1", 7493 auxType: auxSymOff, 7494 argLen: 3, 7495 commutative: true, 7496 symEffect: SymRead, 7497 asm: x86.AMOVQ, 7498 reg: regInfo{ 7499 inputs: []inputInfo{ 7500 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7501 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7502 }, 7503 outputs: []outputInfo{ 7504 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7505 }, 7506 }, 7507 }, 7508 { 7509 name: "MOVQloadidx8", 7510 auxType: auxSymOff, 7511 argLen: 3, 7512 symEffect: SymRead, 7513 asm: x86.AMOVQ, 7514 reg: regInfo{ 7515 inputs: []inputInfo{ 7516 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7517 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7518 }, 7519 outputs: []outputInfo{ 7520 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7521 }, 7522 }, 7523 }, 7524 { 7525 name: "MOVBstoreidx1", 7526 auxType: auxSymOff, 7527 argLen: 4, 7528 symEffect: SymWrite, 7529 asm: x86.AMOVB, 7530 reg: regInfo{ 7531 inputs: []inputInfo{ 7532 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7533 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7534 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7535 }, 7536 }, 7537 }, 7538 { 7539 name: "MOVWstoreidx1", 7540 auxType: auxSymOff, 7541 argLen: 4, 7542 symEffect: SymWrite, 7543 asm: x86.AMOVW, 7544 reg: regInfo{ 7545 inputs: []inputInfo{ 7546 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7547 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7548 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7549 }, 7550 }, 7551 }, 7552 { 7553 name: "MOVWstoreidx2", 7554 auxType: auxSymOff, 7555 argLen: 4, 7556 symEffect: SymWrite, 7557 asm: x86.AMOVW, 7558 reg: regInfo{ 7559 inputs: []inputInfo{ 7560 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7561 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7562 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7563 }, 7564 }, 7565 }, 7566 { 7567 name: "MOVLstoreidx1", 7568 auxType: auxSymOff, 7569 argLen: 4, 7570 symEffect: SymWrite, 7571 asm: x86.AMOVL, 7572 reg: regInfo{ 7573 inputs: []inputInfo{ 7574 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7575 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7576 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7577 }, 7578 }, 7579 }, 7580 { 7581 name: "MOVLstoreidx4", 7582 auxType: auxSymOff, 7583 argLen: 4, 7584 symEffect: SymWrite, 7585 asm: x86.AMOVL, 7586 reg: regInfo{ 7587 inputs: []inputInfo{ 7588 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7589 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7590 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7591 }, 7592 }, 7593 }, 7594 { 7595 name: "MOVLstoreidx8", 7596 auxType: auxSymOff, 7597 argLen: 4, 7598 symEffect: SymWrite, 7599 asm: x86.AMOVL, 7600 reg: regInfo{ 7601 inputs: []inputInfo{ 7602 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7603 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7604 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7605 }, 7606 }, 7607 }, 7608 { 7609 name: "MOVQstoreidx1", 7610 auxType: auxSymOff, 7611 argLen: 4, 7612 symEffect: SymWrite, 7613 asm: x86.AMOVQ, 7614 reg: regInfo{ 7615 inputs: []inputInfo{ 7616 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7617 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7618 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7619 }, 7620 }, 7621 }, 7622 { 7623 name: "MOVQstoreidx8", 7624 auxType: auxSymOff, 7625 argLen: 4, 7626 symEffect: SymWrite, 7627 asm: x86.AMOVQ, 7628 reg: regInfo{ 7629 inputs: []inputInfo{ 7630 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7631 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7632 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7633 }, 7634 }, 7635 }, 7636 { 7637 name: "MOVBstoreconst", 7638 auxType: auxSymValAndOff, 7639 argLen: 2, 7640 faultOnNilArg0: true, 7641 symEffect: SymWrite, 7642 asm: x86.AMOVB, 7643 reg: regInfo{ 7644 inputs: []inputInfo{ 7645 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7646 }, 7647 }, 7648 }, 7649 { 7650 name: "MOVWstoreconst", 7651 auxType: auxSymValAndOff, 7652 argLen: 2, 7653 faultOnNilArg0: true, 7654 symEffect: SymWrite, 7655 asm: x86.AMOVW, 7656 reg: regInfo{ 7657 inputs: []inputInfo{ 7658 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7659 }, 7660 }, 7661 }, 7662 { 7663 name: "MOVLstoreconst", 7664 auxType: auxSymValAndOff, 7665 argLen: 2, 7666 faultOnNilArg0: true, 7667 symEffect: SymWrite, 7668 asm: x86.AMOVL, 7669 reg: regInfo{ 7670 inputs: []inputInfo{ 7671 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7672 }, 7673 }, 7674 }, 7675 { 7676 name: "MOVQstoreconst", 7677 auxType: auxSymValAndOff, 7678 argLen: 2, 7679 faultOnNilArg0: true, 7680 symEffect: SymWrite, 7681 asm: x86.AMOVQ, 7682 reg: regInfo{ 7683 inputs: []inputInfo{ 7684 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7685 }, 7686 }, 7687 }, 7688 { 7689 name: "MOVBstoreconstidx1", 7690 auxType: auxSymValAndOff, 7691 argLen: 3, 7692 symEffect: SymWrite, 7693 asm: x86.AMOVB, 7694 reg: regInfo{ 7695 inputs: []inputInfo{ 7696 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7697 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7698 }, 7699 }, 7700 }, 7701 { 7702 name: "MOVWstoreconstidx1", 7703 auxType: auxSymValAndOff, 7704 argLen: 3, 7705 symEffect: SymWrite, 7706 asm: x86.AMOVW, 7707 reg: regInfo{ 7708 inputs: []inputInfo{ 7709 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7710 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7711 }, 7712 }, 7713 }, 7714 { 7715 name: "MOVWstoreconstidx2", 7716 auxType: auxSymValAndOff, 7717 argLen: 3, 7718 symEffect: SymWrite, 7719 asm: x86.AMOVW, 7720 reg: regInfo{ 7721 inputs: []inputInfo{ 7722 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7723 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7724 }, 7725 }, 7726 }, 7727 { 7728 name: "MOVLstoreconstidx1", 7729 auxType: auxSymValAndOff, 7730 argLen: 3, 7731 symEffect: SymWrite, 7732 asm: x86.AMOVL, 7733 reg: regInfo{ 7734 inputs: []inputInfo{ 7735 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7736 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7737 }, 7738 }, 7739 }, 7740 { 7741 name: "MOVLstoreconstidx4", 7742 auxType: auxSymValAndOff, 7743 argLen: 3, 7744 symEffect: SymWrite, 7745 asm: x86.AMOVL, 7746 reg: regInfo{ 7747 inputs: []inputInfo{ 7748 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7749 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7750 }, 7751 }, 7752 }, 7753 { 7754 name: "MOVQstoreconstidx1", 7755 auxType: auxSymValAndOff, 7756 argLen: 3, 7757 symEffect: SymWrite, 7758 asm: x86.AMOVQ, 7759 reg: regInfo{ 7760 inputs: []inputInfo{ 7761 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7762 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7763 }, 7764 }, 7765 }, 7766 { 7767 name: "MOVQstoreconstidx8", 7768 auxType: auxSymValAndOff, 7769 argLen: 3, 7770 symEffect: SymWrite, 7771 asm: x86.AMOVQ, 7772 reg: regInfo{ 7773 inputs: []inputInfo{ 7774 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7775 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7776 }, 7777 }, 7778 }, 7779 { 7780 name: "DUFFZERO", 7781 auxType: auxInt64, 7782 argLen: 3, 7783 faultOnNilArg0: true, 7784 reg: regInfo{ 7785 inputs: []inputInfo{ 7786 {0, 128}, // DI 7787 {1, 65536}, // X0 7788 }, 7789 clobbers: 128, // DI 7790 }, 7791 }, 7792 { 7793 name: "MOVOconst", 7794 auxType: auxInt128, 7795 argLen: 0, 7796 rematerializeable: true, 7797 reg: regInfo{ 7798 outputs: []outputInfo{ 7799 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7800 }, 7801 }, 7802 }, 7803 { 7804 name: "REPSTOSQ", 7805 argLen: 4, 7806 faultOnNilArg0: true, 7807 reg: regInfo{ 7808 inputs: []inputInfo{ 7809 {0, 128}, // DI 7810 {1, 2}, // CX 7811 {2, 1}, // AX 7812 }, 7813 clobbers: 130, // CX DI 7814 }, 7815 }, 7816 { 7817 name: "CALLstatic", 7818 auxType: auxSymOff, 7819 argLen: 1, 7820 clobberFlags: true, 7821 call: true, 7822 symEffect: SymNone, 7823 reg: regInfo{ 7824 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7825 }, 7826 }, 7827 { 7828 name: "CALLclosure", 7829 auxType: auxInt64, 7830 argLen: 3, 7831 clobberFlags: true, 7832 call: true, 7833 reg: regInfo{ 7834 inputs: []inputInfo{ 7835 {1, 4}, // DX 7836 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7837 }, 7838 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7839 }, 7840 }, 7841 { 7842 name: "CALLinter", 7843 auxType: auxInt64, 7844 argLen: 2, 7845 clobberFlags: true, 7846 call: true, 7847 reg: regInfo{ 7848 inputs: []inputInfo{ 7849 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7850 }, 7851 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7852 }, 7853 }, 7854 { 7855 name: "DUFFCOPY", 7856 auxType: auxInt64, 7857 argLen: 3, 7858 clobberFlags: true, 7859 faultOnNilArg0: true, 7860 faultOnNilArg1: true, 7861 reg: regInfo{ 7862 inputs: []inputInfo{ 7863 {0, 128}, // DI 7864 {1, 64}, // SI 7865 }, 7866 clobbers: 65728, // SI DI X0 7867 }, 7868 }, 7869 { 7870 name: "REPMOVSQ", 7871 argLen: 4, 7872 faultOnNilArg0: true, 7873 faultOnNilArg1: true, 7874 reg: regInfo{ 7875 inputs: []inputInfo{ 7876 {0, 128}, // DI 7877 {1, 64}, // SI 7878 {2, 2}, // CX 7879 }, 7880 clobbers: 194, // CX SI DI 7881 }, 7882 }, 7883 { 7884 name: "InvertFlags", 7885 argLen: 1, 7886 reg: regInfo{}, 7887 }, 7888 { 7889 name: "LoweredGetG", 7890 argLen: 1, 7891 reg: regInfo{ 7892 outputs: []outputInfo{ 7893 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7894 }, 7895 }, 7896 }, 7897 { 7898 name: "LoweredGetClosurePtr", 7899 argLen: 0, 7900 reg: regInfo{ 7901 outputs: []outputInfo{ 7902 {0, 4}, // DX 7903 }, 7904 }, 7905 }, 7906 { 7907 name: "LoweredNilCheck", 7908 argLen: 2, 7909 clobberFlags: true, 7910 nilCheck: true, 7911 faultOnNilArg0: true, 7912 reg: regInfo{ 7913 inputs: []inputInfo{ 7914 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7915 }, 7916 }, 7917 }, 7918 { 7919 name: "MOVQconvert", 7920 argLen: 2, 7921 resultInArg0: true, 7922 asm: x86.AMOVQ, 7923 reg: regInfo{ 7924 inputs: []inputInfo{ 7925 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7926 }, 7927 outputs: []outputInfo{ 7928 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7929 }, 7930 }, 7931 }, 7932 { 7933 name: "MOVLconvert", 7934 argLen: 2, 7935 resultInArg0: true, 7936 asm: x86.AMOVL, 7937 reg: regInfo{ 7938 inputs: []inputInfo{ 7939 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7940 }, 7941 outputs: []outputInfo{ 7942 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7943 }, 7944 }, 7945 }, 7946 { 7947 name: "FlagEQ", 7948 argLen: 0, 7949 reg: regInfo{}, 7950 }, 7951 { 7952 name: "FlagLT_ULT", 7953 argLen: 0, 7954 reg: regInfo{}, 7955 }, 7956 { 7957 name: "FlagLT_UGT", 7958 argLen: 0, 7959 reg: regInfo{}, 7960 }, 7961 { 7962 name: "FlagGT_UGT", 7963 argLen: 0, 7964 reg: regInfo{}, 7965 }, 7966 { 7967 name: "FlagGT_ULT", 7968 argLen: 0, 7969 reg: regInfo{}, 7970 }, 7971 { 7972 name: "MOVLatomicload", 7973 auxType: auxSymOff, 7974 argLen: 2, 7975 faultOnNilArg0: true, 7976 symEffect: SymRead, 7977 asm: x86.AMOVL, 7978 reg: regInfo{ 7979 inputs: []inputInfo{ 7980 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7981 }, 7982 outputs: []outputInfo{ 7983 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7984 }, 7985 }, 7986 }, 7987 { 7988 name: "MOVQatomicload", 7989 auxType: auxSymOff, 7990 argLen: 2, 7991 faultOnNilArg0: true, 7992 symEffect: SymRead, 7993 asm: x86.AMOVQ, 7994 reg: regInfo{ 7995 inputs: []inputInfo{ 7996 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7997 }, 7998 outputs: []outputInfo{ 7999 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8000 }, 8001 }, 8002 }, 8003 { 8004 name: "XCHGL", 8005 auxType: auxSymOff, 8006 argLen: 3, 8007 resultInArg0: true, 8008 faultOnNilArg1: true, 8009 hasSideEffects: true, 8010 symEffect: SymRdWr, 8011 asm: x86.AXCHGL, 8012 reg: regInfo{ 8013 inputs: []inputInfo{ 8014 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8015 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8016 }, 8017 outputs: []outputInfo{ 8018 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8019 }, 8020 }, 8021 }, 8022 { 8023 name: "XCHGQ", 8024 auxType: auxSymOff, 8025 argLen: 3, 8026 resultInArg0: true, 8027 faultOnNilArg1: true, 8028 hasSideEffects: true, 8029 symEffect: SymRdWr, 8030 asm: x86.AXCHGQ, 8031 reg: regInfo{ 8032 inputs: []inputInfo{ 8033 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8034 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8035 }, 8036 outputs: []outputInfo{ 8037 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8038 }, 8039 }, 8040 }, 8041 { 8042 name: "XADDLlock", 8043 auxType: auxSymOff, 8044 argLen: 3, 8045 resultInArg0: true, 8046 clobberFlags: true, 8047 faultOnNilArg1: true, 8048 hasSideEffects: true, 8049 symEffect: SymRdWr, 8050 asm: x86.AXADDL, 8051 reg: regInfo{ 8052 inputs: []inputInfo{ 8053 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8054 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8055 }, 8056 outputs: []outputInfo{ 8057 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8058 }, 8059 }, 8060 }, 8061 { 8062 name: "XADDQlock", 8063 auxType: auxSymOff, 8064 argLen: 3, 8065 resultInArg0: true, 8066 clobberFlags: true, 8067 faultOnNilArg1: true, 8068 hasSideEffects: true, 8069 symEffect: SymRdWr, 8070 asm: x86.AXADDQ, 8071 reg: regInfo{ 8072 inputs: []inputInfo{ 8073 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8074 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8075 }, 8076 outputs: []outputInfo{ 8077 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8078 }, 8079 }, 8080 }, 8081 { 8082 name: "AddTupleFirst32", 8083 argLen: 2, 8084 reg: regInfo{}, 8085 }, 8086 { 8087 name: "AddTupleFirst64", 8088 argLen: 2, 8089 reg: regInfo{}, 8090 }, 8091 { 8092 name: "CMPXCHGLlock", 8093 auxType: auxSymOff, 8094 argLen: 4, 8095 clobberFlags: true, 8096 faultOnNilArg0: true, 8097 hasSideEffects: true, 8098 symEffect: SymRdWr, 8099 asm: x86.ACMPXCHGL, 8100 reg: regInfo{ 8101 inputs: []inputInfo{ 8102 {1, 1}, // AX 8103 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8104 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8105 }, 8106 clobbers: 1, // AX 8107 outputs: []outputInfo{ 8108 {1, 0}, 8109 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8110 }, 8111 }, 8112 }, 8113 { 8114 name: "CMPXCHGQlock", 8115 auxType: auxSymOff, 8116 argLen: 4, 8117 clobberFlags: true, 8118 faultOnNilArg0: true, 8119 hasSideEffects: true, 8120 symEffect: SymRdWr, 8121 asm: x86.ACMPXCHGQ, 8122 reg: regInfo{ 8123 inputs: []inputInfo{ 8124 {1, 1}, // AX 8125 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8126 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8127 }, 8128 clobbers: 1, // AX 8129 outputs: []outputInfo{ 8130 {1, 0}, 8131 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8132 }, 8133 }, 8134 }, 8135 { 8136 name: "ANDBlock", 8137 auxType: auxSymOff, 8138 argLen: 3, 8139 clobberFlags: true, 8140 faultOnNilArg0: true, 8141 hasSideEffects: true, 8142 symEffect: SymRdWr, 8143 asm: x86.AANDB, 8144 reg: regInfo{ 8145 inputs: []inputInfo{ 8146 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8147 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8148 }, 8149 }, 8150 }, 8151 { 8152 name: "ORBlock", 8153 auxType: auxSymOff, 8154 argLen: 3, 8155 clobberFlags: true, 8156 faultOnNilArg0: true, 8157 hasSideEffects: true, 8158 symEffect: SymRdWr, 8159 asm: x86.AORB, 8160 reg: regInfo{ 8161 inputs: []inputInfo{ 8162 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8163 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8164 }, 8165 }, 8166 }, 8167 8168 { 8169 name: "ADD", 8170 argLen: 2, 8171 commutative: true, 8172 asm: arm.AADD, 8173 reg: regInfo{ 8174 inputs: []inputInfo{ 8175 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8176 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8177 }, 8178 outputs: []outputInfo{ 8179 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8180 }, 8181 }, 8182 }, 8183 { 8184 name: "ADDconst", 8185 auxType: auxInt32, 8186 argLen: 1, 8187 asm: arm.AADD, 8188 reg: regInfo{ 8189 inputs: []inputInfo{ 8190 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 8191 }, 8192 outputs: []outputInfo{ 8193 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8194 }, 8195 }, 8196 }, 8197 { 8198 name: "SUB", 8199 argLen: 2, 8200 asm: arm.ASUB, 8201 reg: regInfo{ 8202 inputs: []inputInfo{ 8203 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8204 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8205 }, 8206 outputs: []outputInfo{ 8207 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8208 }, 8209 }, 8210 }, 8211 { 8212 name: "SUBconst", 8213 auxType: auxInt32, 8214 argLen: 1, 8215 asm: arm.ASUB, 8216 reg: regInfo{ 8217 inputs: []inputInfo{ 8218 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8219 }, 8220 outputs: []outputInfo{ 8221 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8222 }, 8223 }, 8224 }, 8225 { 8226 name: "RSB", 8227 argLen: 2, 8228 asm: arm.ARSB, 8229 reg: regInfo{ 8230 inputs: []inputInfo{ 8231 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8232 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8233 }, 8234 outputs: []outputInfo{ 8235 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8236 }, 8237 }, 8238 }, 8239 { 8240 name: "RSBconst", 8241 auxType: auxInt32, 8242 argLen: 1, 8243 asm: arm.ARSB, 8244 reg: regInfo{ 8245 inputs: []inputInfo{ 8246 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8247 }, 8248 outputs: []outputInfo{ 8249 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8250 }, 8251 }, 8252 }, 8253 { 8254 name: "MUL", 8255 argLen: 2, 8256 commutative: true, 8257 asm: arm.AMUL, 8258 reg: regInfo{ 8259 inputs: []inputInfo{ 8260 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8261 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8262 }, 8263 outputs: []outputInfo{ 8264 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8265 }, 8266 }, 8267 }, 8268 { 8269 name: "HMUL", 8270 argLen: 2, 8271 commutative: true, 8272 asm: arm.AMULL, 8273 reg: regInfo{ 8274 inputs: []inputInfo{ 8275 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8276 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8277 }, 8278 outputs: []outputInfo{ 8279 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8280 }, 8281 }, 8282 }, 8283 { 8284 name: "HMULU", 8285 argLen: 2, 8286 commutative: true, 8287 asm: arm.AMULLU, 8288 reg: regInfo{ 8289 inputs: []inputInfo{ 8290 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8291 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8292 }, 8293 outputs: []outputInfo{ 8294 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8295 }, 8296 }, 8297 }, 8298 { 8299 name: "CALLudiv", 8300 argLen: 2, 8301 clobberFlags: true, 8302 reg: regInfo{ 8303 inputs: []inputInfo{ 8304 {0, 2}, // R1 8305 {1, 1}, // R0 8306 }, 8307 clobbers: 16396, // R2 R3 R14 8308 outputs: []outputInfo{ 8309 {0, 1}, // R0 8310 {1, 2}, // R1 8311 }, 8312 }, 8313 }, 8314 { 8315 name: "ADDS", 8316 argLen: 2, 8317 commutative: true, 8318 asm: arm.AADD, 8319 reg: regInfo{ 8320 inputs: []inputInfo{ 8321 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8322 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8323 }, 8324 outputs: []outputInfo{ 8325 {1, 0}, 8326 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8327 }, 8328 }, 8329 }, 8330 { 8331 name: "ADDSconst", 8332 auxType: auxInt32, 8333 argLen: 1, 8334 asm: arm.AADD, 8335 reg: regInfo{ 8336 inputs: []inputInfo{ 8337 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8338 }, 8339 outputs: []outputInfo{ 8340 {1, 0}, 8341 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8342 }, 8343 }, 8344 }, 8345 { 8346 name: "ADC", 8347 argLen: 3, 8348 commutative: true, 8349 asm: arm.AADC, 8350 reg: regInfo{ 8351 inputs: []inputInfo{ 8352 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8353 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8354 }, 8355 outputs: []outputInfo{ 8356 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8357 }, 8358 }, 8359 }, 8360 { 8361 name: "ADCconst", 8362 auxType: auxInt32, 8363 argLen: 2, 8364 asm: arm.AADC, 8365 reg: regInfo{ 8366 inputs: []inputInfo{ 8367 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8368 }, 8369 outputs: []outputInfo{ 8370 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8371 }, 8372 }, 8373 }, 8374 { 8375 name: "SUBS", 8376 argLen: 2, 8377 asm: arm.ASUB, 8378 reg: regInfo{ 8379 inputs: []inputInfo{ 8380 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8381 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8382 }, 8383 outputs: []outputInfo{ 8384 {1, 0}, 8385 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8386 }, 8387 }, 8388 }, 8389 { 8390 name: "SUBSconst", 8391 auxType: auxInt32, 8392 argLen: 1, 8393 asm: arm.ASUB, 8394 reg: regInfo{ 8395 inputs: []inputInfo{ 8396 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8397 }, 8398 outputs: []outputInfo{ 8399 {1, 0}, 8400 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8401 }, 8402 }, 8403 }, 8404 { 8405 name: "RSBSconst", 8406 auxType: auxInt32, 8407 argLen: 1, 8408 asm: arm.ARSB, 8409 reg: regInfo{ 8410 inputs: []inputInfo{ 8411 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8412 }, 8413 outputs: []outputInfo{ 8414 {1, 0}, 8415 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8416 }, 8417 }, 8418 }, 8419 { 8420 name: "SBC", 8421 argLen: 3, 8422 asm: arm.ASBC, 8423 reg: regInfo{ 8424 inputs: []inputInfo{ 8425 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8426 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8427 }, 8428 outputs: []outputInfo{ 8429 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8430 }, 8431 }, 8432 }, 8433 { 8434 name: "SBCconst", 8435 auxType: auxInt32, 8436 argLen: 2, 8437 asm: arm.ASBC, 8438 reg: regInfo{ 8439 inputs: []inputInfo{ 8440 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8441 }, 8442 outputs: []outputInfo{ 8443 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8444 }, 8445 }, 8446 }, 8447 { 8448 name: "RSCconst", 8449 auxType: auxInt32, 8450 argLen: 2, 8451 asm: arm.ARSC, 8452 reg: regInfo{ 8453 inputs: []inputInfo{ 8454 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8455 }, 8456 outputs: []outputInfo{ 8457 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8458 }, 8459 }, 8460 }, 8461 { 8462 name: "MULLU", 8463 argLen: 2, 8464 commutative: true, 8465 asm: arm.AMULLU, 8466 reg: regInfo{ 8467 inputs: []inputInfo{ 8468 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8469 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8470 }, 8471 outputs: []outputInfo{ 8472 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8473 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8474 }, 8475 }, 8476 }, 8477 { 8478 name: "MULA", 8479 argLen: 3, 8480 asm: arm.AMULA, 8481 reg: regInfo{ 8482 inputs: []inputInfo{ 8483 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8484 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8485 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8486 }, 8487 outputs: []outputInfo{ 8488 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8489 }, 8490 }, 8491 }, 8492 { 8493 name: "MULS", 8494 argLen: 3, 8495 asm: arm.AMULS, 8496 reg: regInfo{ 8497 inputs: []inputInfo{ 8498 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8499 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8500 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8501 }, 8502 outputs: []outputInfo{ 8503 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8504 }, 8505 }, 8506 }, 8507 { 8508 name: "ADDF", 8509 argLen: 2, 8510 commutative: true, 8511 asm: arm.AADDF, 8512 reg: regInfo{ 8513 inputs: []inputInfo{ 8514 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8515 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8516 }, 8517 outputs: []outputInfo{ 8518 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8519 }, 8520 }, 8521 }, 8522 { 8523 name: "ADDD", 8524 argLen: 2, 8525 commutative: true, 8526 asm: arm.AADDD, 8527 reg: regInfo{ 8528 inputs: []inputInfo{ 8529 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8530 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8531 }, 8532 outputs: []outputInfo{ 8533 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8534 }, 8535 }, 8536 }, 8537 { 8538 name: "SUBF", 8539 argLen: 2, 8540 asm: arm.ASUBF, 8541 reg: regInfo{ 8542 inputs: []inputInfo{ 8543 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8544 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8545 }, 8546 outputs: []outputInfo{ 8547 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8548 }, 8549 }, 8550 }, 8551 { 8552 name: "SUBD", 8553 argLen: 2, 8554 asm: arm.ASUBD, 8555 reg: regInfo{ 8556 inputs: []inputInfo{ 8557 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8558 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8559 }, 8560 outputs: []outputInfo{ 8561 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8562 }, 8563 }, 8564 }, 8565 { 8566 name: "MULF", 8567 argLen: 2, 8568 commutative: true, 8569 asm: arm.AMULF, 8570 reg: regInfo{ 8571 inputs: []inputInfo{ 8572 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8573 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8574 }, 8575 outputs: []outputInfo{ 8576 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8577 }, 8578 }, 8579 }, 8580 { 8581 name: "MULD", 8582 argLen: 2, 8583 commutative: true, 8584 asm: arm.AMULD, 8585 reg: regInfo{ 8586 inputs: []inputInfo{ 8587 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8588 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8589 }, 8590 outputs: []outputInfo{ 8591 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8592 }, 8593 }, 8594 }, 8595 { 8596 name: "DIVF", 8597 argLen: 2, 8598 asm: arm.ADIVF, 8599 reg: regInfo{ 8600 inputs: []inputInfo{ 8601 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8602 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8603 }, 8604 outputs: []outputInfo{ 8605 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8606 }, 8607 }, 8608 }, 8609 { 8610 name: "DIVD", 8611 argLen: 2, 8612 asm: arm.ADIVD, 8613 reg: regInfo{ 8614 inputs: []inputInfo{ 8615 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8616 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8617 }, 8618 outputs: []outputInfo{ 8619 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8620 }, 8621 }, 8622 }, 8623 { 8624 name: "AND", 8625 argLen: 2, 8626 commutative: true, 8627 asm: arm.AAND, 8628 reg: regInfo{ 8629 inputs: []inputInfo{ 8630 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8631 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8632 }, 8633 outputs: []outputInfo{ 8634 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8635 }, 8636 }, 8637 }, 8638 { 8639 name: "ANDconst", 8640 auxType: auxInt32, 8641 argLen: 1, 8642 asm: arm.AAND, 8643 reg: regInfo{ 8644 inputs: []inputInfo{ 8645 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8646 }, 8647 outputs: []outputInfo{ 8648 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8649 }, 8650 }, 8651 }, 8652 { 8653 name: "OR", 8654 argLen: 2, 8655 commutative: true, 8656 asm: arm.AORR, 8657 reg: regInfo{ 8658 inputs: []inputInfo{ 8659 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8660 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8661 }, 8662 outputs: []outputInfo{ 8663 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8664 }, 8665 }, 8666 }, 8667 { 8668 name: "ORconst", 8669 auxType: auxInt32, 8670 argLen: 1, 8671 asm: arm.AORR, 8672 reg: regInfo{ 8673 inputs: []inputInfo{ 8674 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8675 }, 8676 outputs: []outputInfo{ 8677 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8678 }, 8679 }, 8680 }, 8681 { 8682 name: "XOR", 8683 argLen: 2, 8684 commutative: true, 8685 asm: arm.AEOR, 8686 reg: regInfo{ 8687 inputs: []inputInfo{ 8688 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8689 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8690 }, 8691 outputs: []outputInfo{ 8692 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8693 }, 8694 }, 8695 }, 8696 { 8697 name: "XORconst", 8698 auxType: auxInt32, 8699 argLen: 1, 8700 asm: arm.AEOR, 8701 reg: regInfo{ 8702 inputs: []inputInfo{ 8703 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8704 }, 8705 outputs: []outputInfo{ 8706 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8707 }, 8708 }, 8709 }, 8710 { 8711 name: "BIC", 8712 argLen: 2, 8713 asm: arm.ABIC, 8714 reg: regInfo{ 8715 inputs: []inputInfo{ 8716 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8717 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8718 }, 8719 outputs: []outputInfo{ 8720 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8721 }, 8722 }, 8723 }, 8724 { 8725 name: "BICconst", 8726 auxType: auxInt32, 8727 argLen: 1, 8728 asm: arm.ABIC, 8729 reg: regInfo{ 8730 inputs: []inputInfo{ 8731 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8732 }, 8733 outputs: []outputInfo{ 8734 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8735 }, 8736 }, 8737 }, 8738 { 8739 name: "MVN", 8740 argLen: 1, 8741 asm: arm.AMVN, 8742 reg: regInfo{ 8743 inputs: []inputInfo{ 8744 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8745 }, 8746 outputs: []outputInfo{ 8747 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8748 }, 8749 }, 8750 }, 8751 { 8752 name: "NEGF", 8753 argLen: 1, 8754 asm: arm.ANEGF, 8755 reg: regInfo{ 8756 inputs: []inputInfo{ 8757 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8758 }, 8759 outputs: []outputInfo{ 8760 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8761 }, 8762 }, 8763 }, 8764 { 8765 name: "NEGD", 8766 argLen: 1, 8767 asm: arm.ANEGD, 8768 reg: regInfo{ 8769 inputs: []inputInfo{ 8770 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8771 }, 8772 outputs: []outputInfo{ 8773 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8774 }, 8775 }, 8776 }, 8777 { 8778 name: "SQRTD", 8779 argLen: 1, 8780 asm: arm.ASQRTD, 8781 reg: regInfo{ 8782 inputs: []inputInfo{ 8783 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8784 }, 8785 outputs: []outputInfo{ 8786 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8787 }, 8788 }, 8789 }, 8790 { 8791 name: "CLZ", 8792 argLen: 1, 8793 asm: arm.ACLZ, 8794 reg: regInfo{ 8795 inputs: []inputInfo{ 8796 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8797 }, 8798 outputs: []outputInfo{ 8799 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8800 }, 8801 }, 8802 }, 8803 { 8804 name: "REV", 8805 argLen: 1, 8806 asm: arm.AREV, 8807 reg: regInfo{ 8808 inputs: []inputInfo{ 8809 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8810 }, 8811 outputs: []outputInfo{ 8812 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8813 }, 8814 }, 8815 }, 8816 { 8817 name: "RBIT", 8818 argLen: 1, 8819 asm: arm.ARBIT, 8820 reg: regInfo{ 8821 inputs: []inputInfo{ 8822 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8823 }, 8824 outputs: []outputInfo{ 8825 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8826 }, 8827 }, 8828 }, 8829 { 8830 name: "SLL", 8831 argLen: 2, 8832 asm: arm.ASLL, 8833 reg: regInfo{ 8834 inputs: []inputInfo{ 8835 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8836 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8837 }, 8838 outputs: []outputInfo{ 8839 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8840 }, 8841 }, 8842 }, 8843 { 8844 name: "SLLconst", 8845 auxType: auxInt32, 8846 argLen: 1, 8847 asm: arm.ASLL, 8848 reg: regInfo{ 8849 inputs: []inputInfo{ 8850 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8851 }, 8852 outputs: []outputInfo{ 8853 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8854 }, 8855 }, 8856 }, 8857 { 8858 name: "SRL", 8859 argLen: 2, 8860 asm: arm.ASRL, 8861 reg: regInfo{ 8862 inputs: []inputInfo{ 8863 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8864 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8865 }, 8866 outputs: []outputInfo{ 8867 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8868 }, 8869 }, 8870 }, 8871 { 8872 name: "SRLconst", 8873 auxType: auxInt32, 8874 argLen: 1, 8875 asm: arm.ASRL, 8876 reg: regInfo{ 8877 inputs: []inputInfo{ 8878 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8879 }, 8880 outputs: []outputInfo{ 8881 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8882 }, 8883 }, 8884 }, 8885 { 8886 name: "SRA", 8887 argLen: 2, 8888 asm: arm.ASRA, 8889 reg: regInfo{ 8890 inputs: []inputInfo{ 8891 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8892 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8893 }, 8894 outputs: []outputInfo{ 8895 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8896 }, 8897 }, 8898 }, 8899 { 8900 name: "SRAconst", 8901 auxType: auxInt32, 8902 argLen: 1, 8903 asm: arm.ASRA, 8904 reg: regInfo{ 8905 inputs: []inputInfo{ 8906 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8907 }, 8908 outputs: []outputInfo{ 8909 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8910 }, 8911 }, 8912 }, 8913 { 8914 name: "SRRconst", 8915 auxType: auxInt32, 8916 argLen: 1, 8917 reg: regInfo{ 8918 inputs: []inputInfo{ 8919 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8920 }, 8921 outputs: []outputInfo{ 8922 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8923 }, 8924 }, 8925 }, 8926 { 8927 name: "ADDshiftLL", 8928 auxType: auxInt32, 8929 argLen: 2, 8930 asm: arm.AADD, 8931 reg: regInfo{ 8932 inputs: []inputInfo{ 8933 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8934 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8935 }, 8936 outputs: []outputInfo{ 8937 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8938 }, 8939 }, 8940 }, 8941 { 8942 name: "ADDshiftRL", 8943 auxType: auxInt32, 8944 argLen: 2, 8945 asm: arm.AADD, 8946 reg: regInfo{ 8947 inputs: []inputInfo{ 8948 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8949 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8950 }, 8951 outputs: []outputInfo{ 8952 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8953 }, 8954 }, 8955 }, 8956 { 8957 name: "ADDshiftRA", 8958 auxType: auxInt32, 8959 argLen: 2, 8960 asm: arm.AADD, 8961 reg: regInfo{ 8962 inputs: []inputInfo{ 8963 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8964 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8965 }, 8966 outputs: []outputInfo{ 8967 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8968 }, 8969 }, 8970 }, 8971 { 8972 name: "SUBshiftLL", 8973 auxType: auxInt32, 8974 argLen: 2, 8975 asm: arm.ASUB, 8976 reg: regInfo{ 8977 inputs: []inputInfo{ 8978 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8979 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8980 }, 8981 outputs: []outputInfo{ 8982 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8983 }, 8984 }, 8985 }, 8986 { 8987 name: "SUBshiftRL", 8988 auxType: auxInt32, 8989 argLen: 2, 8990 asm: arm.ASUB, 8991 reg: regInfo{ 8992 inputs: []inputInfo{ 8993 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8994 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8995 }, 8996 outputs: []outputInfo{ 8997 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8998 }, 8999 }, 9000 }, 9001 { 9002 name: "SUBshiftRA", 9003 auxType: auxInt32, 9004 argLen: 2, 9005 asm: arm.ASUB, 9006 reg: regInfo{ 9007 inputs: []inputInfo{ 9008 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9009 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9010 }, 9011 outputs: []outputInfo{ 9012 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9013 }, 9014 }, 9015 }, 9016 { 9017 name: "RSBshiftLL", 9018 auxType: auxInt32, 9019 argLen: 2, 9020 asm: arm.ARSB, 9021 reg: regInfo{ 9022 inputs: []inputInfo{ 9023 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9024 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9025 }, 9026 outputs: []outputInfo{ 9027 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9028 }, 9029 }, 9030 }, 9031 { 9032 name: "RSBshiftRL", 9033 auxType: auxInt32, 9034 argLen: 2, 9035 asm: arm.ARSB, 9036 reg: regInfo{ 9037 inputs: []inputInfo{ 9038 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9039 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9040 }, 9041 outputs: []outputInfo{ 9042 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9043 }, 9044 }, 9045 }, 9046 { 9047 name: "RSBshiftRA", 9048 auxType: auxInt32, 9049 argLen: 2, 9050 asm: arm.ARSB, 9051 reg: regInfo{ 9052 inputs: []inputInfo{ 9053 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9054 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9055 }, 9056 outputs: []outputInfo{ 9057 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9058 }, 9059 }, 9060 }, 9061 { 9062 name: "ANDshiftLL", 9063 auxType: auxInt32, 9064 argLen: 2, 9065 asm: arm.AAND, 9066 reg: regInfo{ 9067 inputs: []inputInfo{ 9068 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9069 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9070 }, 9071 outputs: []outputInfo{ 9072 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9073 }, 9074 }, 9075 }, 9076 { 9077 name: "ANDshiftRL", 9078 auxType: auxInt32, 9079 argLen: 2, 9080 asm: arm.AAND, 9081 reg: regInfo{ 9082 inputs: []inputInfo{ 9083 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9084 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9085 }, 9086 outputs: []outputInfo{ 9087 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9088 }, 9089 }, 9090 }, 9091 { 9092 name: "ANDshiftRA", 9093 auxType: auxInt32, 9094 argLen: 2, 9095 asm: arm.AAND, 9096 reg: regInfo{ 9097 inputs: []inputInfo{ 9098 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9099 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9100 }, 9101 outputs: []outputInfo{ 9102 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9103 }, 9104 }, 9105 }, 9106 { 9107 name: "ORshiftLL", 9108 auxType: auxInt32, 9109 argLen: 2, 9110 asm: arm.AORR, 9111 reg: regInfo{ 9112 inputs: []inputInfo{ 9113 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9114 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9115 }, 9116 outputs: []outputInfo{ 9117 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9118 }, 9119 }, 9120 }, 9121 { 9122 name: "ORshiftRL", 9123 auxType: auxInt32, 9124 argLen: 2, 9125 asm: arm.AORR, 9126 reg: regInfo{ 9127 inputs: []inputInfo{ 9128 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9129 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9130 }, 9131 outputs: []outputInfo{ 9132 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9133 }, 9134 }, 9135 }, 9136 { 9137 name: "ORshiftRA", 9138 auxType: auxInt32, 9139 argLen: 2, 9140 asm: arm.AORR, 9141 reg: regInfo{ 9142 inputs: []inputInfo{ 9143 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9144 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9145 }, 9146 outputs: []outputInfo{ 9147 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9148 }, 9149 }, 9150 }, 9151 { 9152 name: "XORshiftLL", 9153 auxType: auxInt32, 9154 argLen: 2, 9155 asm: arm.AEOR, 9156 reg: regInfo{ 9157 inputs: []inputInfo{ 9158 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9159 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9160 }, 9161 outputs: []outputInfo{ 9162 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9163 }, 9164 }, 9165 }, 9166 { 9167 name: "XORshiftRL", 9168 auxType: auxInt32, 9169 argLen: 2, 9170 asm: arm.AEOR, 9171 reg: regInfo{ 9172 inputs: []inputInfo{ 9173 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9174 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9175 }, 9176 outputs: []outputInfo{ 9177 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9178 }, 9179 }, 9180 }, 9181 { 9182 name: "XORshiftRA", 9183 auxType: auxInt32, 9184 argLen: 2, 9185 asm: arm.AEOR, 9186 reg: regInfo{ 9187 inputs: []inputInfo{ 9188 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9189 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9190 }, 9191 outputs: []outputInfo{ 9192 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9193 }, 9194 }, 9195 }, 9196 { 9197 name: "XORshiftRR", 9198 auxType: auxInt32, 9199 argLen: 2, 9200 asm: arm.AEOR, 9201 reg: regInfo{ 9202 inputs: []inputInfo{ 9203 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9204 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9205 }, 9206 outputs: []outputInfo{ 9207 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9208 }, 9209 }, 9210 }, 9211 { 9212 name: "BICshiftLL", 9213 auxType: auxInt32, 9214 argLen: 2, 9215 asm: arm.ABIC, 9216 reg: regInfo{ 9217 inputs: []inputInfo{ 9218 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9219 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9220 }, 9221 outputs: []outputInfo{ 9222 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9223 }, 9224 }, 9225 }, 9226 { 9227 name: "BICshiftRL", 9228 auxType: auxInt32, 9229 argLen: 2, 9230 asm: arm.ABIC, 9231 reg: regInfo{ 9232 inputs: []inputInfo{ 9233 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9234 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9235 }, 9236 outputs: []outputInfo{ 9237 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9238 }, 9239 }, 9240 }, 9241 { 9242 name: "BICshiftRA", 9243 auxType: auxInt32, 9244 argLen: 2, 9245 asm: arm.ABIC, 9246 reg: regInfo{ 9247 inputs: []inputInfo{ 9248 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9249 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9250 }, 9251 outputs: []outputInfo{ 9252 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9253 }, 9254 }, 9255 }, 9256 { 9257 name: "MVNshiftLL", 9258 auxType: auxInt32, 9259 argLen: 1, 9260 asm: arm.AMVN, 9261 reg: regInfo{ 9262 inputs: []inputInfo{ 9263 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9264 }, 9265 outputs: []outputInfo{ 9266 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9267 }, 9268 }, 9269 }, 9270 { 9271 name: "MVNshiftRL", 9272 auxType: auxInt32, 9273 argLen: 1, 9274 asm: arm.AMVN, 9275 reg: regInfo{ 9276 inputs: []inputInfo{ 9277 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9278 }, 9279 outputs: []outputInfo{ 9280 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9281 }, 9282 }, 9283 }, 9284 { 9285 name: "MVNshiftRA", 9286 auxType: auxInt32, 9287 argLen: 1, 9288 asm: arm.AMVN, 9289 reg: regInfo{ 9290 inputs: []inputInfo{ 9291 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9292 }, 9293 outputs: []outputInfo{ 9294 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9295 }, 9296 }, 9297 }, 9298 { 9299 name: "ADCshiftLL", 9300 auxType: auxInt32, 9301 argLen: 3, 9302 asm: arm.AADC, 9303 reg: regInfo{ 9304 inputs: []inputInfo{ 9305 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9306 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9307 }, 9308 outputs: []outputInfo{ 9309 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9310 }, 9311 }, 9312 }, 9313 { 9314 name: "ADCshiftRL", 9315 auxType: auxInt32, 9316 argLen: 3, 9317 asm: arm.AADC, 9318 reg: regInfo{ 9319 inputs: []inputInfo{ 9320 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9321 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9322 }, 9323 outputs: []outputInfo{ 9324 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9325 }, 9326 }, 9327 }, 9328 { 9329 name: "ADCshiftRA", 9330 auxType: auxInt32, 9331 argLen: 3, 9332 asm: arm.AADC, 9333 reg: regInfo{ 9334 inputs: []inputInfo{ 9335 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9336 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9337 }, 9338 outputs: []outputInfo{ 9339 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9340 }, 9341 }, 9342 }, 9343 { 9344 name: "SBCshiftLL", 9345 auxType: auxInt32, 9346 argLen: 3, 9347 asm: arm.ASBC, 9348 reg: regInfo{ 9349 inputs: []inputInfo{ 9350 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9351 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9352 }, 9353 outputs: []outputInfo{ 9354 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9355 }, 9356 }, 9357 }, 9358 { 9359 name: "SBCshiftRL", 9360 auxType: auxInt32, 9361 argLen: 3, 9362 asm: arm.ASBC, 9363 reg: regInfo{ 9364 inputs: []inputInfo{ 9365 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9366 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9367 }, 9368 outputs: []outputInfo{ 9369 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9370 }, 9371 }, 9372 }, 9373 { 9374 name: "SBCshiftRA", 9375 auxType: auxInt32, 9376 argLen: 3, 9377 asm: arm.ASBC, 9378 reg: regInfo{ 9379 inputs: []inputInfo{ 9380 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9381 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9382 }, 9383 outputs: []outputInfo{ 9384 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9385 }, 9386 }, 9387 }, 9388 { 9389 name: "RSCshiftLL", 9390 auxType: auxInt32, 9391 argLen: 3, 9392 asm: arm.ARSC, 9393 reg: regInfo{ 9394 inputs: []inputInfo{ 9395 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9396 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9397 }, 9398 outputs: []outputInfo{ 9399 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9400 }, 9401 }, 9402 }, 9403 { 9404 name: "RSCshiftRL", 9405 auxType: auxInt32, 9406 argLen: 3, 9407 asm: arm.ARSC, 9408 reg: regInfo{ 9409 inputs: []inputInfo{ 9410 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9411 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9412 }, 9413 outputs: []outputInfo{ 9414 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9415 }, 9416 }, 9417 }, 9418 { 9419 name: "RSCshiftRA", 9420 auxType: auxInt32, 9421 argLen: 3, 9422 asm: arm.ARSC, 9423 reg: regInfo{ 9424 inputs: []inputInfo{ 9425 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9426 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9427 }, 9428 outputs: []outputInfo{ 9429 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9430 }, 9431 }, 9432 }, 9433 { 9434 name: "ADDSshiftLL", 9435 auxType: auxInt32, 9436 argLen: 2, 9437 asm: arm.AADD, 9438 reg: regInfo{ 9439 inputs: []inputInfo{ 9440 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9441 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9442 }, 9443 outputs: []outputInfo{ 9444 {1, 0}, 9445 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9446 }, 9447 }, 9448 }, 9449 { 9450 name: "ADDSshiftRL", 9451 auxType: auxInt32, 9452 argLen: 2, 9453 asm: arm.AADD, 9454 reg: regInfo{ 9455 inputs: []inputInfo{ 9456 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9457 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9458 }, 9459 outputs: []outputInfo{ 9460 {1, 0}, 9461 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9462 }, 9463 }, 9464 }, 9465 { 9466 name: "ADDSshiftRA", 9467 auxType: auxInt32, 9468 argLen: 2, 9469 asm: arm.AADD, 9470 reg: regInfo{ 9471 inputs: []inputInfo{ 9472 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9473 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9474 }, 9475 outputs: []outputInfo{ 9476 {1, 0}, 9477 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9478 }, 9479 }, 9480 }, 9481 { 9482 name: "SUBSshiftLL", 9483 auxType: auxInt32, 9484 argLen: 2, 9485 asm: arm.ASUB, 9486 reg: regInfo{ 9487 inputs: []inputInfo{ 9488 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9489 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9490 }, 9491 outputs: []outputInfo{ 9492 {1, 0}, 9493 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9494 }, 9495 }, 9496 }, 9497 { 9498 name: "SUBSshiftRL", 9499 auxType: auxInt32, 9500 argLen: 2, 9501 asm: arm.ASUB, 9502 reg: regInfo{ 9503 inputs: []inputInfo{ 9504 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9505 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9506 }, 9507 outputs: []outputInfo{ 9508 {1, 0}, 9509 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9510 }, 9511 }, 9512 }, 9513 { 9514 name: "SUBSshiftRA", 9515 auxType: auxInt32, 9516 argLen: 2, 9517 asm: arm.ASUB, 9518 reg: regInfo{ 9519 inputs: []inputInfo{ 9520 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9521 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9522 }, 9523 outputs: []outputInfo{ 9524 {1, 0}, 9525 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9526 }, 9527 }, 9528 }, 9529 { 9530 name: "RSBSshiftLL", 9531 auxType: auxInt32, 9532 argLen: 2, 9533 asm: arm.ARSB, 9534 reg: regInfo{ 9535 inputs: []inputInfo{ 9536 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9537 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9538 }, 9539 outputs: []outputInfo{ 9540 {1, 0}, 9541 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9542 }, 9543 }, 9544 }, 9545 { 9546 name: "RSBSshiftRL", 9547 auxType: auxInt32, 9548 argLen: 2, 9549 asm: arm.ARSB, 9550 reg: regInfo{ 9551 inputs: []inputInfo{ 9552 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9553 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9554 }, 9555 outputs: []outputInfo{ 9556 {1, 0}, 9557 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9558 }, 9559 }, 9560 }, 9561 { 9562 name: "RSBSshiftRA", 9563 auxType: auxInt32, 9564 argLen: 2, 9565 asm: arm.ARSB, 9566 reg: regInfo{ 9567 inputs: []inputInfo{ 9568 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9569 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9570 }, 9571 outputs: []outputInfo{ 9572 {1, 0}, 9573 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9574 }, 9575 }, 9576 }, 9577 { 9578 name: "ADDshiftLLreg", 9579 argLen: 3, 9580 asm: arm.AADD, 9581 reg: regInfo{ 9582 inputs: []inputInfo{ 9583 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9584 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9585 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9586 }, 9587 outputs: []outputInfo{ 9588 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9589 }, 9590 }, 9591 }, 9592 { 9593 name: "ADDshiftRLreg", 9594 argLen: 3, 9595 asm: arm.AADD, 9596 reg: regInfo{ 9597 inputs: []inputInfo{ 9598 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9599 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9600 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9601 }, 9602 outputs: []outputInfo{ 9603 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9604 }, 9605 }, 9606 }, 9607 { 9608 name: "ADDshiftRAreg", 9609 argLen: 3, 9610 asm: arm.AADD, 9611 reg: regInfo{ 9612 inputs: []inputInfo{ 9613 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9614 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9615 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9616 }, 9617 outputs: []outputInfo{ 9618 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9619 }, 9620 }, 9621 }, 9622 { 9623 name: "SUBshiftLLreg", 9624 argLen: 3, 9625 asm: arm.ASUB, 9626 reg: regInfo{ 9627 inputs: []inputInfo{ 9628 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9629 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9630 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9631 }, 9632 outputs: []outputInfo{ 9633 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9634 }, 9635 }, 9636 }, 9637 { 9638 name: "SUBshiftRLreg", 9639 argLen: 3, 9640 asm: arm.ASUB, 9641 reg: regInfo{ 9642 inputs: []inputInfo{ 9643 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9644 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9645 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9646 }, 9647 outputs: []outputInfo{ 9648 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9649 }, 9650 }, 9651 }, 9652 { 9653 name: "SUBshiftRAreg", 9654 argLen: 3, 9655 asm: arm.ASUB, 9656 reg: regInfo{ 9657 inputs: []inputInfo{ 9658 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9659 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9660 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9661 }, 9662 outputs: []outputInfo{ 9663 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9664 }, 9665 }, 9666 }, 9667 { 9668 name: "RSBshiftLLreg", 9669 argLen: 3, 9670 asm: arm.ARSB, 9671 reg: regInfo{ 9672 inputs: []inputInfo{ 9673 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9674 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9675 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9676 }, 9677 outputs: []outputInfo{ 9678 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9679 }, 9680 }, 9681 }, 9682 { 9683 name: "RSBshiftRLreg", 9684 argLen: 3, 9685 asm: arm.ARSB, 9686 reg: regInfo{ 9687 inputs: []inputInfo{ 9688 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9689 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9690 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9691 }, 9692 outputs: []outputInfo{ 9693 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9694 }, 9695 }, 9696 }, 9697 { 9698 name: "RSBshiftRAreg", 9699 argLen: 3, 9700 asm: arm.ARSB, 9701 reg: regInfo{ 9702 inputs: []inputInfo{ 9703 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9704 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9705 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9706 }, 9707 outputs: []outputInfo{ 9708 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9709 }, 9710 }, 9711 }, 9712 { 9713 name: "ANDshiftLLreg", 9714 argLen: 3, 9715 asm: arm.AAND, 9716 reg: regInfo{ 9717 inputs: []inputInfo{ 9718 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9719 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9720 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9721 }, 9722 outputs: []outputInfo{ 9723 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9724 }, 9725 }, 9726 }, 9727 { 9728 name: "ANDshiftRLreg", 9729 argLen: 3, 9730 asm: arm.AAND, 9731 reg: regInfo{ 9732 inputs: []inputInfo{ 9733 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9734 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9735 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9736 }, 9737 outputs: []outputInfo{ 9738 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9739 }, 9740 }, 9741 }, 9742 { 9743 name: "ANDshiftRAreg", 9744 argLen: 3, 9745 asm: arm.AAND, 9746 reg: regInfo{ 9747 inputs: []inputInfo{ 9748 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9749 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9750 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9751 }, 9752 outputs: []outputInfo{ 9753 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9754 }, 9755 }, 9756 }, 9757 { 9758 name: "ORshiftLLreg", 9759 argLen: 3, 9760 asm: arm.AORR, 9761 reg: regInfo{ 9762 inputs: []inputInfo{ 9763 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9764 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9765 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9766 }, 9767 outputs: []outputInfo{ 9768 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9769 }, 9770 }, 9771 }, 9772 { 9773 name: "ORshiftRLreg", 9774 argLen: 3, 9775 asm: arm.AORR, 9776 reg: regInfo{ 9777 inputs: []inputInfo{ 9778 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9779 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9780 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9781 }, 9782 outputs: []outputInfo{ 9783 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9784 }, 9785 }, 9786 }, 9787 { 9788 name: "ORshiftRAreg", 9789 argLen: 3, 9790 asm: arm.AORR, 9791 reg: regInfo{ 9792 inputs: []inputInfo{ 9793 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9794 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9795 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9796 }, 9797 outputs: []outputInfo{ 9798 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9799 }, 9800 }, 9801 }, 9802 { 9803 name: "XORshiftLLreg", 9804 argLen: 3, 9805 asm: arm.AEOR, 9806 reg: regInfo{ 9807 inputs: []inputInfo{ 9808 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9809 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9810 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9811 }, 9812 outputs: []outputInfo{ 9813 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9814 }, 9815 }, 9816 }, 9817 { 9818 name: "XORshiftRLreg", 9819 argLen: 3, 9820 asm: arm.AEOR, 9821 reg: regInfo{ 9822 inputs: []inputInfo{ 9823 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9824 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9825 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9826 }, 9827 outputs: []outputInfo{ 9828 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9829 }, 9830 }, 9831 }, 9832 { 9833 name: "XORshiftRAreg", 9834 argLen: 3, 9835 asm: arm.AEOR, 9836 reg: regInfo{ 9837 inputs: []inputInfo{ 9838 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9839 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9840 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9841 }, 9842 outputs: []outputInfo{ 9843 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9844 }, 9845 }, 9846 }, 9847 { 9848 name: "BICshiftLLreg", 9849 argLen: 3, 9850 asm: arm.ABIC, 9851 reg: regInfo{ 9852 inputs: []inputInfo{ 9853 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9854 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9855 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9856 }, 9857 outputs: []outputInfo{ 9858 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9859 }, 9860 }, 9861 }, 9862 { 9863 name: "BICshiftRLreg", 9864 argLen: 3, 9865 asm: arm.ABIC, 9866 reg: regInfo{ 9867 inputs: []inputInfo{ 9868 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9869 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9870 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9871 }, 9872 outputs: []outputInfo{ 9873 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9874 }, 9875 }, 9876 }, 9877 { 9878 name: "BICshiftRAreg", 9879 argLen: 3, 9880 asm: arm.ABIC, 9881 reg: regInfo{ 9882 inputs: []inputInfo{ 9883 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9884 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9885 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9886 }, 9887 outputs: []outputInfo{ 9888 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9889 }, 9890 }, 9891 }, 9892 { 9893 name: "MVNshiftLLreg", 9894 argLen: 2, 9895 asm: arm.AMVN, 9896 reg: regInfo{ 9897 inputs: []inputInfo{ 9898 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9899 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9900 }, 9901 outputs: []outputInfo{ 9902 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9903 }, 9904 }, 9905 }, 9906 { 9907 name: "MVNshiftRLreg", 9908 argLen: 2, 9909 asm: arm.AMVN, 9910 reg: regInfo{ 9911 inputs: []inputInfo{ 9912 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9913 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9914 }, 9915 outputs: []outputInfo{ 9916 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9917 }, 9918 }, 9919 }, 9920 { 9921 name: "MVNshiftRAreg", 9922 argLen: 2, 9923 asm: arm.AMVN, 9924 reg: regInfo{ 9925 inputs: []inputInfo{ 9926 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9927 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9928 }, 9929 outputs: []outputInfo{ 9930 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9931 }, 9932 }, 9933 }, 9934 { 9935 name: "ADCshiftLLreg", 9936 argLen: 4, 9937 asm: arm.AADC, 9938 reg: regInfo{ 9939 inputs: []inputInfo{ 9940 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9941 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9942 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9943 }, 9944 outputs: []outputInfo{ 9945 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9946 }, 9947 }, 9948 }, 9949 { 9950 name: "ADCshiftRLreg", 9951 argLen: 4, 9952 asm: arm.AADC, 9953 reg: regInfo{ 9954 inputs: []inputInfo{ 9955 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9956 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9957 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9958 }, 9959 outputs: []outputInfo{ 9960 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9961 }, 9962 }, 9963 }, 9964 { 9965 name: "ADCshiftRAreg", 9966 argLen: 4, 9967 asm: arm.AADC, 9968 reg: regInfo{ 9969 inputs: []inputInfo{ 9970 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9971 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9972 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9973 }, 9974 outputs: []outputInfo{ 9975 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9976 }, 9977 }, 9978 }, 9979 { 9980 name: "SBCshiftLLreg", 9981 argLen: 4, 9982 asm: arm.ASBC, 9983 reg: regInfo{ 9984 inputs: []inputInfo{ 9985 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9986 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9987 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9988 }, 9989 outputs: []outputInfo{ 9990 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9991 }, 9992 }, 9993 }, 9994 { 9995 name: "SBCshiftRLreg", 9996 argLen: 4, 9997 asm: arm.ASBC, 9998 reg: regInfo{ 9999 inputs: []inputInfo{ 10000 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10001 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10002 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10003 }, 10004 outputs: []outputInfo{ 10005 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10006 }, 10007 }, 10008 }, 10009 { 10010 name: "SBCshiftRAreg", 10011 argLen: 4, 10012 asm: arm.ASBC, 10013 reg: regInfo{ 10014 inputs: []inputInfo{ 10015 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10016 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10017 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10018 }, 10019 outputs: []outputInfo{ 10020 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10021 }, 10022 }, 10023 }, 10024 { 10025 name: "RSCshiftLLreg", 10026 argLen: 4, 10027 asm: arm.ARSC, 10028 reg: regInfo{ 10029 inputs: []inputInfo{ 10030 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10031 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10032 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10033 }, 10034 outputs: []outputInfo{ 10035 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10036 }, 10037 }, 10038 }, 10039 { 10040 name: "RSCshiftRLreg", 10041 argLen: 4, 10042 asm: arm.ARSC, 10043 reg: regInfo{ 10044 inputs: []inputInfo{ 10045 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10046 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10047 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10048 }, 10049 outputs: []outputInfo{ 10050 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10051 }, 10052 }, 10053 }, 10054 { 10055 name: "RSCshiftRAreg", 10056 argLen: 4, 10057 asm: arm.ARSC, 10058 reg: regInfo{ 10059 inputs: []inputInfo{ 10060 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10061 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10062 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10063 }, 10064 outputs: []outputInfo{ 10065 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10066 }, 10067 }, 10068 }, 10069 { 10070 name: "ADDSshiftLLreg", 10071 argLen: 3, 10072 asm: arm.AADD, 10073 reg: regInfo{ 10074 inputs: []inputInfo{ 10075 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10076 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10077 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10078 }, 10079 outputs: []outputInfo{ 10080 {1, 0}, 10081 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10082 }, 10083 }, 10084 }, 10085 { 10086 name: "ADDSshiftRLreg", 10087 argLen: 3, 10088 asm: arm.AADD, 10089 reg: regInfo{ 10090 inputs: []inputInfo{ 10091 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10092 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10093 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10094 }, 10095 outputs: []outputInfo{ 10096 {1, 0}, 10097 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10098 }, 10099 }, 10100 }, 10101 { 10102 name: "ADDSshiftRAreg", 10103 argLen: 3, 10104 asm: arm.AADD, 10105 reg: regInfo{ 10106 inputs: []inputInfo{ 10107 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10108 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10109 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10110 }, 10111 outputs: []outputInfo{ 10112 {1, 0}, 10113 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10114 }, 10115 }, 10116 }, 10117 { 10118 name: "SUBSshiftLLreg", 10119 argLen: 3, 10120 asm: arm.ASUB, 10121 reg: regInfo{ 10122 inputs: []inputInfo{ 10123 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10124 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10125 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10126 }, 10127 outputs: []outputInfo{ 10128 {1, 0}, 10129 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10130 }, 10131 }, 10132 }, 10133 { 10134 name: "SUBSshiftRLreg", 10135 argLen: 3, 10136 asm: arm.ASUB, 10137 reg: regInfo{ 10138 inputs: []inputInfo{ 10139 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10140 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10141 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10142 }, 10143 outputs: []outputInfo{ 10144 {1, 0}, 10145 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10146 }, 10147 }, 10148 }, 10149 { 10150 name: "SUBSshiftRAreg", 10151 argLen: 3, 10152 asm: arm.ASUB, 10153 reg: regInfo{ 10154 inputs: []inputInfo{ 10155 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10156 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10157 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10158 }, 10159 outputs: []outputInfo{ 10160 {1, 0}, 10161 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10162 }, 10163 }, 10164 }, 10165 { 10166 name: "RSBSshiftLLreg", 10167 argLen: 3, 10168 asm: arm.ARSB, 10169 reg: regInfo{ 10170 inputs: []inputInfo{ 10171 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10172 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10173 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10174 }, 10175 outputs: []outputInfo{ 10176 {1, 0}, 10177 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10178 }, 10179 }, 10180 }, 10181 { 10182 name: "RSBSshiftRLreg", 10183 argLen: 3, 10184 asm: arm.ARSB, 10185 reg: regInfo{ 10186 inputs: []inputInfo{ 10187 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10188 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10189 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10190 }, 10191 outputs: []outputInfo{ 10192 {1, 0}, 10193 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10194 }, 10195 }, 10196 }, 10197 { 10198 name: "RSBSshiftRAreg", 10199 argLen: 3, 10200 asm: arm.ARSB, 10201 reg: regInfo{ 10202 inputs: []inputInfo{ 10203 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10204 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10205 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10206 }, 10207 outputs: []outputInfo{ 10208 {1, 0}, 10209 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10210 }, 10211 }, 10212 }, 10213 { 10214 name: "CMP", 10215 argLen: 2, 10216 asm: arm.ACMP, 10217 reg: regInfo{ 10218 inputs: []inputInfo{ 10219 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10220 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10221 }, 10222 }, 10223 }, 10224 { 10225 name: "CMPconst", 10226 auxType: auxInt32, 10227 argLen: 1, 10228 asm: arm.ACMP, 10229 reg: regInfo{ 10230 inputs: []inputInfo{ 10231 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10232 }, 10233 }, 10234 }, 10235 { 10236 name: "CMN", 10237 argLen: 2, 10238 asm: arm.ACMN, 10239 reg: regInfo{ 10240 inputs: []inputInfo{ 10241 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10242 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10243 }, 10244 }, 10245 }, 10246 { 10247 name: "CMNconst", 10248 auxType: auxInt32, 10249 argLen: 1, 10250 asm: arm.ACMN, 10251 reg: regInfo{ 10252 inputs: []inputInfo{ 10253 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10254 }, 10255 }, 10256 }, 10257 { 10258 name: "TST", 10259 argLen: 2, 10260 commutative: true, 10261 asm: arm.ATST, 10262 reg: regInfo{ 10263 inputs: []inputInfo{ 10264 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10265 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10266 }, 10267 }, 10268 }, 10269 { 10270 name: "TSTconst", 10271 auxType: auxInt32, 10272 argLen: 1, 10273 asm: arm.ATST, 10274 reg: regInfo{ 10275 inputs: []inputInfo{ 10276 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10277 }, 10278 }, 10279 }, 10280 { 10281 name: "TEQ", 10282 argLen: 2, 10283 commutative: true, 10284 asm: arm.ATEQ, 10285 reg: regInfo{ 10286 inputs: []inputInfo{ 10287 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10288 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10289 }, 10290 }, 10291 }, 10292 { 10293 name: "TEQconst", 10294 auxType: auxInt32, 10295 argLen: 1, 10296 asm: arm.ATEQ, 10297 reg: regInfo{ 10298 inputs: []inputInfo{ 10299 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10300 }, 10301 }, 10302 }, 10303 { 10304 name: "CMPF", 10305 argLen: 2, 10306 asm: arm.ACMPF, 10307 reg: regInfo{ 10308 inputs: []inputInfo{ 10309 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10310 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10311 }, 10312 }, 10313 }, 10314 { 10315 name: "CMPD", 10316 argLen: 2, 10317 asm: arm.ACMPD, 10318 reg: regInfo{ 10319 inputs: []inputInfo{ 10320 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10321 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10322 }, 10323 }, 10324 }, 10325 { 10326 name: "CMPshiftLL", 10327 auxType: auxInt32, 10328 argLen: 2, 10329 asm: arm.ACMP, 10330 reg: regInfo{ 10331 inputs: []inputInfo{ 10332 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10333 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10334 }, 10335 }, 10336 }, 10337 { 10338 name: "CMPshiftRL", 10339 auxType: auxInt32, 10340 argLen: 2, 10341 asm: arm.ACMP, 10342 reg: regInfo{ 10343 inputs: []inputInfo{ 10344 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10345 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10346 }, 10347 }, 10348 }, 10349 { 10350 name: "CMPshiftRA", 10351 auxType: auxInt32, 10352 argLen: 2, 10353 asm: arm.ACMP, 10354 reg: regInfo{ 10355 inputs: []inputInfo{ 10356 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10357 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10358 }, 10359 }, 10360 }, 10361 { 10362 name: "CMPshiftLLreg", 10363 argLen: 3, 10364 asm: arm.ACMP, 10365 reg: regInfo{ 10366 inputs: []inputInfo{ 10367 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10368 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10369 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10370 }, 10371 }, 10372 }, 10373 { 10374 name: "CMPshiftRLreg", 10375 argLen: 3, 10376 asm: arm.ACMP, 10377 reg: regInfo{ 10378 inputs: []inputInfo{ 10379 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10380 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10381 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10382 }, 10383 }, 10384 }, 10385 { 10386 name: "CMPshiftRAreg", 10387 argLen: 3, 10388 asm: arm.ACMP, 10389 reg: regInfo{ 10390 inputs: []inputInfo{ 10391 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10392 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10393 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10394 }, 10395 }, 10396 }, 10397 { 10398 name: "CMPF0", 10399 argLen: 1, 10400 asm: arm.ACMPF, 10401 reg: regInfo{ 10402 inputs: []inputInfo{ 10403 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10404 }, 10405 }, 10406 }, 10407 { 10408 name: "CMPD0", 10409 argLen: 1, 10410 asm: arm.ACMPD, 10411 reg: regInfo{ 10412 inputs: []inputInfo{ 10413 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10414 }, 10415 }, 10416 }, 10417 { 10418 name: "MOVWconst", 10419 auxType: auxInt32, 10420 argLen: 0, 10421 rematerializeable: true, 10422 asm: arm.AMOVW, 10423 reg: regInfo{ 10424 outputs: []outputInfo{ 10425 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10426 }, 10427 }, 10428 }, 10429 { 10430 name: "MOVFconst", 10431 auxType: auxFloat64, 10432 argLen: 0, 10433 rematerializeable: true, 10434 asm: arm.AMOVF, 10435 reg: regInfo{ 10436 outputs: []outputInfo{ 10437 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10438 }, 10439 }, 10440 }, 10441 { 10442 name: "MOVDconst", 10443 auxType: auxFloat64, 10444 argLen: 0, 10445 rematerializeable: true, 10446 asm: arm.AMOVD, 10447 reg: regInfo{ 10448 outputs: []outputInfo{ 10449 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10450 }, 10451 }, 10452 }, 10453 { 10454 name: "MOVWaddr", 10455 auxType: auxSymOff, 10456 argLen: 1, 10457 rematerializeable: true, 10458 symEffect: SymAddr, 10459 asm: arm.AMOVW, 10460 reg: regInfo{ 10461 inputs: []inputInfo{ 10462 {0, 4294975488}, // SP SB 10463 }, 10464 outputs: []outputInfo{ 10465 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10466 }, 10467 }, 10468 }, 10469 { 10470 name: "MOVBload", 10471 auxType: auxSymOff, 10472 argLen: 2, 10473 faultOnNilArg0: true, 10474 symEffect: SymRead, 10475 asm: arm.AMOVB, 10476 reg: regInfo{ 10477 inputs: []inputInfo{ 10478 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10479 }, 10480 outputs: []outputInfo{ 10481 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10482 }, 10483 }, 10484 }, 10485 { 10486 name: "MOVBUload", 10487 auxType: auxSymOff, 10488 argLen: 2, 10489 faultOnNilArg0: true, 10490 symEffect: SymRead, 10491 asm: arm.AMOVBU, 10492 reg: regInfo{ 10493 inputs: []inputInfo{ 10494 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10495 }, 10496 outputs: []outputInfo{ 10497 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10498 }, 10499 }, 10500 }, 10501 { 10502 name: "MOVHload", 10503 auxType: auxSymOff, 10504 argLen: 2, 10505 faultOnNilArg0: true, 10506 symEffect: SymRead, 10507 asm: arm.AMOVH, 10508 reg: regInfo{ 10509 inputs: []inputInfo{ 10510 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10511 }, 10512 outputs: []outputInfo{ 10513 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10514 }, 10515 }, 10516 }, 10517 { 10518 name: "MOVHUload", 10519 auxType: auxSymOff, 10520 argLen: 2, 10521 faultOnNilArg0: true, 10522 symEffect: SymRead, 10523 asm: arm.AMOVHU, 10524 reg: regInfo{ 10525 inputs: []inputInfo{ 10526 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10527 }, 10528 outputs: []outputInfo{ 10529 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10530 }, 10531 }, 10532 }, 10533 { 10534 name: "MOVWload", 10535 auxType: auxSymOff, 10536 argLen: 2, 10537 faultOnNilArg0: true, 10538 symEffect: SymRead, 10539 asm: arm.AMOVW, 10540 reg: regInfo{ 10541 inputs: []inputInfo{ 10542 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10543 }, 10544 outputs: []outputInfo{ 10545 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10546 }, 10547 }, 10548 }, 10549 { 10550 name: "MOVFload", 10551 auxType: auxSymOff, 10552 argLen: 2, 10553 faultOnNilArg0: true, 10554 symEffect: SymRead, 10555 asm: arm.AMOVF, 10556 reg: regInfo{ 10557 inputs: []inputInfo{ 10558 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10559 }, 10560 outputs: []outputInfo{ 10561 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10562 }, 10563 }, 10564 }, 10565 { 10566 name: "MOVDload", 10567 auxType: auxSymOff, 10568 argLen: 2, 10569 faultOnNilArg0: true, 10570 symEffect: SymRead, 10571 asm: arm.AMOVD, 10572 reg: regInfo{ 10573 inputs: []inputInfo{ 10574 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10575 }, 10576 outputs: []outputInfo{ 10577 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10578 }, 10579 }, 10580 }, 10581 { 10582 name: "MOVBstore", 10583 auxType: auxSymOff, 10584 argLen: 3, 10585 faultOnNilArg0: true, 10586 symEffect: SymWrite, 10587 asm: arm.AMOVB, 10588 reg: regInfo{ 10589 inputs: []inputInfo{ 10590 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10591 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10592 }, 10593 }, 10594 }, 10595 { 10596 name: "MOVHstore", 10597 auxType: auxSymOff, 10598 argLen: 3, 10599 faultOnNilArg0: true, 10600 symEffect: SymWrite, 10601 asm: arm.AMOVH, 10602 reg: regInfo{ 10603 inputs: []inputInfo{ 10604 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10605 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10606 }, 10607 }, 10608 }, 10609 { 10610 name: "MOVWstore", 10611 auxType: auxSymOff, 10612 argLen: 3, 10613 faultOnNilArg0: true, 10614 symEffect: SymWrite, 10615 asm: arm.AMOVW, 10616 reg: regInfo{ 10617 inputs: []inputInfo{ 10618 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10619 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10620 }, 10621 }, 10622 }, 10623 { 10624 name: "MOVFstore", 10625 auxType: auxSymOff, 10626 argLen: 3, 10627 faultOnNilArg0: true, 10628 symEffect: SymWrite, 10629 asm: arm.AMOVF, 10630 reg: regInfo{ 10631 inputs: []inputInfo{ 10632 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10633 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10634 }, 10635 }, 10636 }, 10637 { 10638 name: "MOVDstore", 10639 auxType: auxSymOff, 10640 argLen: 3, 10641 faultOnNilArg0: true, 10642 symEffect: SymWrite, 10643 asm: arm.AMOVD, 10644 reg: regInfo{ 10645 inputs: []inputInfo{ 10646 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10647 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10648 }, 10649 }, 10650 }, 10651 { 10652 name: "MOVWloadidx", 10653 argLen: 3, 10654 asm: arm.AMOVW, 10655 reg: regInfo{ 10656 inputs: []inputInfo{ 10657 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10658 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10659 }, 10660 outputs: []outputInfo{ 10661 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10662 }, 10663 }, 10664 }, 10665 { 10666 name: "MOVWloadshiftLL", 10667 auxType: auxInt32, 10668 argLen: 3, 10669 asm: arm.AMOVW, 10670 reg: regInfo{ 10671 inputs: []inputInfo{ 10672 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10673 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10674 }, 10675 outputs: []outputInfo{ 10676 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10677 }, 10678 }, 10679 }, 10680 { 10681 name: "MOVWloadshiftRL", 10682 auxType: auxInt32, 10683 argLen: 3, 10684 asm: arm.AMOVW, 10685 reg: regInfo{ 10686 inputs: []inputInfo{ 10687 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10688 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10689 }, 10690 outputs: []outputInfo{ 10691 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10692 }, 10693 }, 10694 }, 10695 { 10696 name: "MOVWloadshiftRA", 10697 auxType: auxInt32, 10698 argLen: 3, 10699 asm: arm.AMOVW, 10700 reg: regInfo{ 10701 inputs: []inputInfo{ 10702 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10703 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10704 }, 10705 outputs: []outputInfo{ 10706 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10707 }, 10708 }, 10709 }, 10710 { 10711 name: "MOVBUloadidx", 10712 argLen: 3, 10713 asm: arm.AMOVBU, 10714 reg: regInfo{ 10715 inputs: []inputInfo{ 10716 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10717 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10718 }, 10719 outputs: []outputInfo{ 10720 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10721 }, 10722 }, 10723 }, 10724 { 10725 name: "MOVBloadidx", 10726 argLen: 3, 10727 asm: arm.AMOVB, 10728 reg: regInfo{ 10729 inputs: []inputInfo{ 10730 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10731 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10732 }, 10733 outputs: []outputInfo{ 10734 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10735 }, 10736 }, 10737 }, 10738 { 10739 name: "MOVHUloadidx", 10740 argLen: 3, 10741 asm: arm.AMOVHU, 10742 reg: regInfo{ 10743 inputs: []inputInfo{ 10744 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10745 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10746 }, 10747 outputs: []outputInfo{ 10748 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10749 }, 10750 }, 10751 }, 10752 { 10753 name: "MOVHloadidx", 10754 argLen: 3, 10755 asm: arm.AMOVH, 10756 reg: regInfo{ 10757 inputs: []inputInfo{ 10758 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10759 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10760 }, 10761 outputs: []outputInfo{ 10762 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10763 }, 10764 }, 10765 }, 10766 { 10767 name: "MOVWstoreidx", 10768 argLen: 4, 10769 asm: arm.AMOVW, 10770 reg: regInfo{ 10771 inputs: []inputInfo{ 10772 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10773 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10774 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10775 }, 10776 }, 10777 }, 10778 { 10779 name: "MOVWstoreshiftLL", 10780 auxType: auxInt32, 10781 argLen: 4, 10782 asm: arm.AMOVW, 10783 reg: regInfo{ 10784 inputs: []inputInfo{ 10785 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10786 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10787 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10788 }, 10789 }, 10790 }, 10791 { 10792 name: "MOVWstoreshiftRL", 10793 auxType: auxInt32, 10794 argLen: 4, 10795 asm: arm.AMOVW, 10796 reg: regInfo{ 10797 inputs: []inputInfo{ 10798 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10799 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10800 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10801 }, 10802 }, 10803 }, 10804 { 10805 name: "MOVWstoreshiftRA", 10806 auxType: auxInt32, 10807 argLen: 4, 10808 asm: arm.AMOVW, 10809 reg: regInfo{ 10810 inputs: []inputInfo{ 10811 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10812 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10813 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10814 }, 10815 }, 10816 }, 10817 { 10818 name: "MOVBstoreidx", 10819 argLen: 4, 10820 asm: arm.AMOVB, 10821 reg: regInfo{ 10822 inputs: []inputInfo{ 10823 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10824 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10825 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10826 }, 10827 }, 10828 }, 10829 { 10830 name: "MOVHstoreidx", 10831 argLen: 4, 10832 asm: arm.AMOVH, 10833 reg: regInfo{ 10834 inputs: []inputInfo{ 10835 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10836 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10837 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10838 }, 10839 }, 10840 }, 10841 { 10842 name: "MOVBreg", 10843 argLen: 1, 10844 asm: arm.AMOVBS, 10845 reg: regInfo{ 10846 inputs: []inputInfo{ 10847 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10848 }, 10849 outputs: []outputInfo{ 10850 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10851 }, 10852 }, 10853 }, 10854 { 10855 name: "MOVBUreg", 10856 argLen: 1, 10857 asm: arm.AMOVBU, 10858 reg: regInfo{ 10859 inputs: []inputInfo{ 10860 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10861 }, 10862 outputs: []outputInfo{ 10863 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10864 }, 10865 }, 10866 }, 10867 { 10868 name: "MOVHreg", 10869 argLen: 1, 10870 asm: arm.AMOVHS, 10871 reg: regInfo{ 10872 inputs: []inputInfo{ 10873 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10874 }, 10875 outputs: []outputInfo{ 10876 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10877 }, 10878 }, 10879 }, 10880 { 10881 name: "MOVHUreg", 10882 argLen: 1, 10883 asm: arm.AMOVHU, 10884 reg: regInfo{ 10885 inputs: []inputInfo{ 10886 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10887 }, 10888 outputs: []outputInfo{ 10889 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10890 }, 10891 }, 10892 }, 10893 { 10894 name: "MOVWreg", 10895 argLen: 1, 10896 asm: arm.AMOVW, 10897 reg: regInfo{ 10898 inputs: []inputInfo{ 10899 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10900 }, 10901 outputs: []outputInfo{ 10902 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10903 }, 10904 }, 10905 }, 10906 { 10907 name: "MOVWnop", 10908 argLen: 1, 10909 resultInArg0: true, 10910 reg: regInfo{ 10911 inputs: []inputInfo{ 10912 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10913 }, 10914 outputs: []outputInfo{ 10915 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10916 }, 10917 }, 10918 }, 10919 { 10920 name: "MOVWF", 10921 argLen: 1, 10922 asm: arm.AMOVWF, 10923 reg: regInfo{ 10924 inputs: []inputInfo{ 10925 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10926 }, 10927 clobbers: 2147483648, // F15 10928 outputs: []outputInfo{ 10929 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10930 }, 10931 }, 10932 }, 10933 { 10934 name: "MOVWD", 10935 argLen: 1, 10936 asm: arm.AMOVWD, 10937 reg: regInfo{ 10938 inputs: []inputInfo{ 10939 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10940 }, 10941 clobbers: 2147483648, // F15 10942 outputs: []outputInfo{ 10943 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10944 }, 10945 }, 10946 }, 10947 { 10948 name: "MOVWUF", 10949 argLen: 1, 10950 asm: arm.AMOVWF, 10951 reg: regInfo{ 10952 inputs: []inputInfo{ 10953 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10954 }, 10955 clobbers: 2147483648, // F15 10956 outputs: []outputInfo{ 10957 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10958 }, 10959 }, 10960 }, 10961 { 10962 name: "MOVWUD", 10963 argLen: 1, 10964 asm: arm.AMOVWD, 10965 reg: regInfo{ 10966 inputs: []inputInfo{ 10967 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10968 }, 10969 clobbers: 2147483648, // F15 10970 outputs: []outputInfo{ 10971 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10972 }, 10973 }, 10974 }, 10975 { 10976 name: "MOVFW", 10977 argLen: 1, 10978 asm: arm.AMOVFW, 10979 reg: regInfo{ 10980 inputs: []inputInfo{ 10981 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10982 }, 10983 clobbers: 2147483648, // F15 10984 outputs: []outputInfo{ 10985 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10986 }, 10987 }, 10988 }, 10989 { 10990 name: "MOVDW", 10991 argLen: 1, 10992 asm: arm.AMOVDW, 10993 reg: regInfo{ 10994 inputs: []inputInfo{ 10995 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10996 }, 10997 clobbers: 2147483648, // F15 10998 outputs: []outputInfo{ 10999 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11000 }, 11001 }, 11002 }, 11003 { 11004 name: "MOVFWU", 11005 argLen: 1, 11006 asm: arm.AMOVFW, 11007 reg: regInfo{ 11008 inputs: []inputInfo{ 11009 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11010 }, 11011 clobbers: 2147483648, // F15 11012 outputs: []outputInfo{ 11013 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11014 }, 11015 }, 11016 }, 11017 { 11018 name: "MOVDWU", 11019 argLen: 1, 11020 asm: arm.AMOVDW, 11021 reg: regInfo{ 11022 inputs: []inputInfo{ 11023 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11024 }, 11025 clobbers: 2147483648, // F15 11026 outputs: []outputInfo{ 11027 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11028 }, 11029 }, 11030 }, 11031 { 11032 name: "MOVFD", 11033 argLen: 1, 11034 asm: arm.AMOVFD, 11035 reg: regInfo{ 11036 inputs: []inputInfo{ 11037 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11038 }, 11039 outputs: []outputInfo{ 11040 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11041 }, 11042 }, 11043 }, 11044 { 11045 name: "MOVDF", 11046 argLen: 1, 11047 asm: arm.AMOVDF, 11048 reg: regInfo{ 11049 inputs: []inputInfo{ 11050 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11051 }, 11052 outputs: []outputInfo{ 11053 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11054 }, 11055 }, 11056 }, 11057 { 11058 name: "CMOVWHSconst", 11059 auxType: auxInt32, 11060 argLen: 2, 11061 resultInArg0: true, 11062 asm: arm.AMOVW, 11063 reg: regInfo{ 11064 inputs: []inputInfo{ 11065 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11066 }, 11067 outputs: []outputInfo{ 11068 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11069 }, 11070 }, 11071 }, 11072 { 11073 name: "CMOVWLSconst", 11074 auxType: auxInt32, 11075 argLen: 2, 11076 resultInArg0: true, 11077 asm: arm.AMOVW, 11078 reg: regInfo{ 11079 inputs: []inputInfo{ 11080 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11081 }, 11082 outputs: []outputInfo{ 11083 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11084 }, 11085 }, 11086 }, 11087 { 11088 name: "SRAcond", 11089 argLen: 3, 11090 asm: arm.ASRA, 11091 reg: regInfo{ 11092 inputs: []inputInfo{ 11093 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11094 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11095 }, 11096 outputs: []outputInfo{ 11097 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11098 }, 11099 }, 11100 }, 11101 { 11102 name: "CALLstatic", 11103 auxType: auxSymOff, 11104 argLen: 1, 11105 clobberFlags: true, 11106 call: true, 11107 symEffect: SymNone, 11108 reg: regInfo{ 11109 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11110 }, 11111 }, 11112 { 11113 name: "CALLclosure", 11114 auxType: auxInt64, 11115 argLen: 3, 11116 clobberFlags: true, 11117 call: true, 11118 reg: regInfo{ 11119 inputs: []inputInfo{ 11120 {1, 128}, // R7 11121 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 11122 }, 11123 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11124 }, 11125 }, 11126 { 11127 name: "CALLinter", 11128 auxType: auxInt64, 11129 argLen: 2, 11130 clobberFlags: true, 11131 call: true, 11132 reg: regInfo{ 11133 inputs: []inputInfo{ 11134 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11135 }, 11136 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11137 }, 11138 }, 11139 { 11140 name: "LoweredNilCheck", 11141 argLen: 2, 11142 nilCheck: true, 11143 faultOnNilArg0: true, 11144 reg: regInfo{ 11145 inputs: []inputInfo{ 11146 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11147 }, 11148 }, 11149 }, 11150 { 11151 name: "Equal", 11152 argLen: 1, 11153 reg: regInfo{ 11154 outputs: []outputInfo{ 11155 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11156 }, 11157 }, 11158 }, 11159 { 11160 name: "NotEqual", 11161 argLen: 1, 11162 reg: regInfo{ 11163 outputs: []outputInfo{ 11164 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11165 }, 11166 }, 11167 }, 11168 { 11169 name: "LessThan", 11170 argLen: 1, 11171 reg: regInfo{ 11172 outputs: []outputInfo{ 11173 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11174 }, 11175 }, 11176 }, 11177 { 11178 name: "LessEqual", 11179 argLen: 1, 11180 reg: regInfo{ 11181 outputs: []outputInfo{ 11182 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11183 }, 11184 }, 11185 }, 11186 { 11187 name: "GreaterThan", 11188 argLen: 1, 11189 reg: regInfo{ 11190 outputs: []outputInfo{ 11191 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11192 }, 11193 }, 11194 }, 11195 { 11196 name: "GreaterEqual", 11197 argLen: 1, 11198 reg: regInfo{ 11199 outputs: []outputInfo{ 11200 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11201 }, 11202 }, 11203 }, 11204 { 11205 name: "LessThanU", 11206 argLen: 1, 11207 reg: regInfo{ 11208 outputs: []outputInfo{ 11209 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11210 }, 11211 }, 11212 }, 11213 { 11214 name: "LessEqualU", 11215 argLen: 1, 11216 reg: regInfo{ 11217 outputs: []outputInfo{ 11218 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11219 }, 11220 }, 11221 }, 11222 { 11223 name: "GreaterThanU", 11224 argLen: 1, 11225 reg: regInfo{ 11226 outputs: []outputInfo{ 11227 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11228 }, 11229 }, 11230 }, 11231 { 11232 name: "GreaterEqualU", 11233 argLen: 1, 11234 reg: regInfo{ 11235 outputs: []outputInfo{ 11236 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11237 }, 11238 }, 11239 }, 11240 { 11241 name: "DUFFZERO", 11242 auxType: auxInt64, 11243 argLen: 3, 11244 faultOnNilArg0: true, 11245 reg: regInfo{ 11246 inputs: []inputInfo{ 11247 {0, 2}, // R1 11248 {1, 1}, // R0 11249 }, 11250 clobbers: 16386, // R1 R14 11251 }, 11252 }, 11253 { 11254 name: "DUFFCOPY", 11255 auxType: auxInt64, 11256 argLen: 3, 11257 faultOnNilArg0: true, 11258 faultOnNilArg1: true, 11259 reg: regInfo{ 11260 inputs: []inputInfo{ 11261 {0, 4}, // R2 11262 {1, 2}, // R1 11263 }, 11264 clobbers: 16391, // R0 R1 R2 R14 11265 }, 11266 }, 11267 { 11268 name: "LoweredZero", 11269 auxType: auxInt64, 11270 argLen: 4, 11271 clobberFlags: true, 11272 faultOnNilArg0: true, 11273 reg: regInfo{ 11274 inputs: []inputInfo{ 11275 {0, 2}, // R1 11276 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11277 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11278 }, 11279 clobbers: 2, // R1 11280 }, 11281 }, 11282 { 11283 name: "LoweredMove", 11284 auxType: auxInt64, 11285 argLen: 4, 11286 clobberFlags: true, 11287 faultOnNilArg0: true, 11288 faultOnNilArg1: true, 11289 reg: regInfo{ 11290 inputs: []inputInfo{ 11291 {0, 4}, // R2 11292 {1, 2}, // R1 11293 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11294 }, 11295 clobbers: 6, // R1 R2 11296 }, 11297 }, 11298 { 11299 name: "LoweredGetClosurePtr", 11300 argLen: 0, 11301 reg: regInfo{ 11302 outputs: []outputInfo{ 11303 {0, 128}, // R7 11304 }, 11305 }, 11306 }, 11307 { 11308 name: "MOVWconvert", 11309 argLen: 2, 11310 asm: arm.AMOVW, 11311 reg: regInfo{ 11312 inputs: []inputInfo{ 11313 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11314 }, 11315 outputs: []outputInfo{ 11316 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11317 }, 11318 }, 11319 }, 11320 { 11321 name: "FlagEQ", 11322 argLen: 0, 11323 reg: regInfo{}, 11324 }, 11325 { 11326 name: "FlagLT_ULT", 11327 argLen: 0, 11328 reg: regInfo{}, 11329 }, 11330 { 11331 name: "FlagLT_UGT", 11332 argLen: 0, 11333 reg: regInfo{}, 11334 }, 11335 { 11336 name: "FlagGT_UGT", 11337 argLen: 0, 11338 reg: regInfo{}, 11339 }, 11340 { 11341 name: "FlagGT_ULT", 11342 argLen: 0, 11343 reg: regInfo{}, 11344 }, 11345 { 11346 name: "InvertFlags", 11347 argLen: 1, 11348 reg: regInfo{}, 11349 }, 11350 11351 { 11352 name: "ADD", 11353 argLen: 2, 11354 commutative: true, 11355 asm: arm64.AADD, 11356 reg: regInfo{ 11357 inputs: []inputInfo{ 11358 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11359 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11360 }, 11361 outputs: []outputInfo{ 11362 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11363 }, 11364 }, 11365 }, 11366 { 11367 name: "ADDconst", 11368 auxType: auxInt64, 11369 argLen: 1, 11370 asm: arm64.AADD, 11371 reg: regInfo{ 11372 inputs: []inputInfo{ 11373 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 11374 }, 11375 outputs: []outputInfo{ 11376 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11377 }, 11378 }, 11379 }, 11380 { 11381 name: "SUB", 11382 argLen: 2, 11383 asm: arm64.ASUB, 11384 reg: regInfo{ 11385 inputs: []inputInfo{ 11386 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11387 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11388 }, 11389 outputs: []outputInfo{ 11390 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11391 }, 11392 }, 11393 }, 11394 { 11395 name: "SUBconst", 11396 auxType: auxInt64, 11397 argLen: 1, 11398 asm: arm64.ASUB, 11399 reg: regInfo{ 11400 inputs: []inputInfo{ 11401 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11402 }, 11403 outputs: []outputInfo{ 11404 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11405 }, 11406 }, 11407 }, 11408 { 11409 name: "MUL", 11410 argLen: 2, 11411 commutative: true, 11412 asm: arm64.AMUL, 11413 reg: regInfo{ 11414 inputs: []inputInfo{ 11415 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11416 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11417 }, 11418 outputs: []outputInfo{ 11419 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11420 }, 11421 }, 11422 }, 11423 { 11424 name: "MULW", 11425 argLen: 2, 11426 commutative: true, 11427 asm: arm64.AMULW, 11428 reg: regInfo{ 11429 inputs: []inputInfo{ 11430 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11431 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11432 }, 11433 outputs: []outputInfo{ 11434 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11435 }, 11436 }, 11437 }, 11438 { 11439 name: "MULH", 11440 argLen: 2, 11441 commutative: true, 11442 asm: arm64.ASMULH, 11443 reg: regInfo{ 11444 inputs: []inputInfo{ 11445 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11446 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11447 }, 11448 outputs: []outputInfo{ 11449 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11450 }, 11451 }, 11452 }, 11453 { 11454 name: "UMULH", 11455 argLen: 2, 11456 commutative: true, 11457 asm: arm64.AUMULH, 11458 reg: regInfo{ 11459 inputs: []inputInfo{ 11460 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11461 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11462 }, 11463 outputs: []outputInfo{ 11464 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11465 }, 11466 }, 11467 }, 11468 { 11469 name: "MULL", 11470 argLen: 2, 11471 commutative: true, 11472 asm: arm64.ASMULL, 11473 reg: regInfo{ 11474 inputs: []inputInfo{ 11475 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11476 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11477 }, 11478 outputs: []outputInfo{ 11479 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11480 }, 11481 }, 11482 }, 11483 { 11484 name: "UMULL", 11485 argLen: 2, 11486 commutative: true, 11487 asm: arm64.AUMULL, 11488 reg: regInfo{ 11489 inputs: []inputInfo{ 11490 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11491 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11492 }, 11493 outputs: []outputInfo{ 11494 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11495 }, 11496 }, 11497 }, 11498 { 11499 name: "DIV", 11500 argLen: 2, 11501 asm: arm64.ASDIV, 11502 reg: regInfo{ 11503 inputs: []inputInfo{ 11504 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11505 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11506 }, 11507 outputs: []outputInfo{ 11508 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11509 }, 11510 }, 11511 }, 11512 { 11513 name: "UDIV", 11514 argLen: 2, 11515 asm: arm64.AUDIV, 11516 reg: regInfo{ 11517 inputs: []inputInfo{ 11518 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11519 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11520 }, 11521 outputs: []outputInfo{ 11522 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11523 }, 11524 }, 11525 }, 11526 { 11527 name: "DIVW", 11528 argLen: 2, 11529 asm: arm64.ASDIVW, 11530 reg: regInfo{ 11531 inputs: []inputInfo{ 11532 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11533 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11534 }, 11535 outputs: []outputInfo{ 11536 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11537 }, 11538 }, 11539 }, 11540 { 11541 name: "UDIVW", 11542 argLen: 2, 11543 asm: arm64.AUDIVW, 11544 reg: regInfo{ 11545 inputs: []inputInfo{ 11546 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11547 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11548 }, 11549 outputs: []outputInfo{ 11550 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11551 }, 11552 }, 11553 }, 11554 { 11555 name: "MOD", 11556 argLen: 2, 11557 asm: arm64.AREM, 11558 reg: regInfo{ 11559 inputs: []inputInfo{ 11560 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11561 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11562 }, 11563 outputs: []outputInfo{ 11564 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11565 }, 11566 }, 11567 }, 11568 { 11569 name: "UMOD", 11570 argLen: 2, 11571 asm: arm64.AUREM, 11572 reg: regInfo{ 11573 inputs: []inputInfo{ 11574 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11575 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11576 }, 11577 outputs: []outputInfo{ 11578 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11579 }, 11580 }, 11581 }, 11582 { 11583 name: "MODW", 11584 argLen: 2, 11585 asm: arm64.AREMW, 11586 reg: regInfo{ 11587 inputs: []inputInfo{ 11588 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11589 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11590 }, 11591 outputs: []outputInfo{ 11592 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11593 }, 11594 }, 11595 }, 11596 { 11597 name: "UMODW", 11598 argLen: 2, 11599 asm: arm64.AUREMW, 11600 reg: regInfo{ 11601 inputs: []inputInfo{ 11602 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11603 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11604 }, 11605 outputs: []outputInfo{ 11606 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11607 }, 11608 }, 11609 }, 11610 { 11611 name: "FADDS", 11612 argLen: 2, 11613 commutative: true, 11614 asm: arm64.AFADDS, 11615 reg: regInfo{ 11616 inputs: []inputInfo{ 11617 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11618 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11619 }, 11620 outputs: []outputInfo{ 11621 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11622 }, 11623 }, 11624 }, 11625 { 11626 name: "FADDD", 11627 argLen: 2, 11628 commutative: true, 11629 asm: arm64.AFADDD, 11630 reg: regInfo{ 11631 inputs: []inputInfo{ 11632 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11633 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11634 }, 11635 outputs: []outputInfo{ 11636 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11637 }, 11638 }, 11639 }, 11640 { 11641 name: "FSUBS", 11642 argLen: 2, 11643 asm: arm64.AFSUBS, 11644 reg: regInfo{ 11645 inputs: []inputInfo{ 11646 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11647 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11648 }, 11649 outputs: []outputInfo{ 11650 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11651 }, 11652 }, 11653 }, 11654 { 11655 name: "FSUBD", 11656 argLen: 2, 11657 asm: arm64.AFSUBD, 11658 reg: regInfo{ 11659 inputs: []inputInfo{ 11660 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11661 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11662 }, 11663 outputs: []outputInfo{ 11664 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11665 }, 11666 }, 11667 }, 11668 { 11669 name: "FMULS", 11670 argLen: 2, 11671 commutative: true, 11672 asm: arm64.AFMULS, 11673 reg: regInfo{ 11674 inputs: []inputInfo{ 11675 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11676 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11677 }, 11678 outputs: []outputInfo{ 11679 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11680 }, 11681 }, 11682 }, 11683 { 11684 name: "FMULD", 11685 argLen: 2, 11686 commutative: true, 11687 asm: arm64.AFMULD, 11688 reg: regInfo{ 11689 inputs: []inputInfo{ 11690 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11691 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11692 }, 11693 outputs: []outputInfo{ 11694 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11695 }, 11696 }, 11697 }, 11698 { 11699 name: "FDIVS", 11700 argLen: 2, 11701 asm: arm64.AFDIVS, 11702 reg: regInfo{ 11703 inputs: []inputInfo{ 11704 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11705 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11706 }, 11707 outputs: []outputInfo{ 11708 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11709 }, 11710 }, 11711 }, 11712 { 11713 name: "FDIVD", 11714 argLen: 2, 11715 asm: arm64.AFDIVD, 11716 reg: regInfo{ 11717 inputs: []inputInfo{ 11718 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11719 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11720 }, 11721 outputs: []outputInfo{ 11722 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11723 }, 11724 }, 11725 }, 11726 { 11727 name: "AND", 11728 argLen: 2, 11729 commutative: true, 11730 asm: arm64.AAND, 11731 reg: regInfo{ 11732 inputs: []inputInfo{ 11733 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11734 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11735 }, 11736 outputs: []outputInfo{ 11737 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11738 }, 11739 }, 11740 }, 11741 { 11742 name: "ANDconst", 11743 auxType: auxInt64, 11744 argLen: 1, 11745 asm: arm64.AAND, 11746 reg: regInfo{ 11747 inputs: []inputInfo{ 11748 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11749 }, 11750 outputs: []outputInfo{ 11751 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11752 }, 11753 }, 11754 }, 11755 { 11756 name: "OR", 11757 argLen: 2, 11758 commutative: true, 11759 asm: arm64.AORR, 11760 reg: regInfo{ 11761 inputs: []inputInfo{ 11762 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11763 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11764 }, 11765 outputs: []outputInfo{ 11766 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11767 }, 11768 }, 11769 }, 11770 { 11771 name: "ORconst", 11772 auxType: auxInt64, 11773 argLen: 1, 11774 asm: arm64.AORR, 11775 reg: regInfo{ 11776 inputs: []inputInfo{ 11777 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11778 }, 11779 outputs: []outputInfo{ 11780 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11781 }, 11782 }, 11783 }, 11784 { 11785 name: "XOR", 11786 argLen: 2, 11787 commutative: true, 11788 asm: arm64.AEOR, 11789 reg: regInfo{ 11790 inputs: []inputInfo{ 11791 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11792 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11793 }, 11794 outputs: []outputInfo{ 11795 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11796 }, 11797 }, 11798 }, 11799 { 11800 name: "XORconst", 11801 auxType: auxInt64, 11802 argLen: 1, 11803 asm: arm64.AEOR, 11804 reg: regInfo{ 11805 inputs: []inputInfo{ 11806 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11807 }, 11808 outputs: []outputInfo{ 11809 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11810 }, 11811 }, 11812 }, 11813 { 11814 name: "BIC", 11815 argLen: 2, 11816 asm: arm64.ABIC, 11817 reg: regInfo{ 11818 inputs: []inputInfo{ 11819 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11820 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11821 }, 11822 outputs: []outputInfo{ 11823 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11824 }, 11825 }, 11826 }, 11827 { 11828 name: "BICconst", 11829 auxType: auxInt64, 11830 argLen: 1, 11831 asm: arm64.ABIC, 11832 reg: regInfo{ 11833 inputs: []inputInfo{ 11834 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11835 }, 11836 outputs: []outputInfo{ 11837 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11838 }, 11839 }, 11840 }, 11841 { 11842 name: "MVN", 11843 argLen: 1, 11844 asm: arm64.AMVN, 11845 reg: regInfo{ 11846 inputs: []inputInfo{ 11847 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11848 }, 11849 outputs: []outputInfo{ 11850 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11851 }, 11852 }, 11853 }, 11854 { 11855 name: "NEG", 11856 argLen: 1, 11857 asm: arm64.ANEG, 11858 reg: regInfo{ 11859 inputs: []inputInfo{ 11860 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11861 }, 11862 outputs: []outputInfo{ 11863 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11864 }, 11865 }, 11866 }, 11867 { 11868 name: "FNEGS", 11869 argLen: 1, 11870 asm: arm64.AFNEGS, 11871 reg: regInfo{ 11872 inputs: []inputInfo{ 11873 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11874 }, 11875 outputs: []outputInfo{ 11876 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11877 }, 11878 }, 11879 }, 11880 { 11881 name: "FNEGD", 11882 argLen: 1, 11883 asm: arm64.AFNEGD, 11884 reg: regInfo{ 11885 inputs: []inputInfo{ 11886 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11887 }, 11888 outputs: []outputInfo{ 11889 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11890 }, 11891 }, 11892 }, 11893 { 11894 name: "FSQRTD", 11895 argLen: 1, 11896 asm: arm64.AFSQRTD, 11897 reg: regInfo{ 11898 inputs: []inputInfo{ 11899 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11900 }, 11901 outputs: []outputInfo{ 11902 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11903 }, 11904 }, 11905 }, 11906 { 11907 name: "REV", 11908 argLen: 1, 11909 asm: arm64.AREV, 11910 reg: regInfo{ 11911 inputs: []inputInfo{ 11912 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11913 }, 11914 outputs: []outputInfo{ 11915 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11916 }, 11917 }, 11918 }, 11919 { 11920 name: "REVW", 11921 argLen: 1, 11922 asm: arm64.AREVW, 11923 reg: regInfo{ 11924 inputs: []inputInfo{ 11925 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11926 }, 11927 outputs: []outputInfo{ 11928 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11929 }, 11930 }, 11931 }, 11932 { 11933 name: "REV16W", 11934 argLen: 1, 11935 asm: arm64.AREV16W, 11936 reg: regInfo{ 11937 inputs: []inputInfo{ 11938 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11939 }, 11940 outputs: []outputInfo{ 11941 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11942 }, 11943 }, 11944 }, 11945 { 11946 name: "RBIT", 11947 argLen: 1, 11948 asm: arm64.ARBIT, 11949 reg: regInfo{ 11950 inputs: []inputInfo{ 11951 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11952 }, 11953 outputs: []outputInfo{ 11954 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11955 }, 11956 }, 11957 }, 11958 { 11959 name: "RBITW", 11960 argLen: 1, 11961 asm: arm64.ARBITW, 11962 reg: regInfo{ 11963 inputs: []inputInfo{ 11964 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11965 }, 11966 outputs: []outputInfo{ 11967 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11968 }, 11969 }, 11970 }, 11971 { 11972 name: "CLZ", 11973 argLen: 1, 11974 asm: arm64.ACLZ, 11975 reg: regInfo{ 11976 inputs: []inputInfo{ 11977 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11978 }, 11979 outputs: []outputInfo{ 11980 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11981 }, 11982 }, 11983 }, 11984 { 11985 name: "CLZW", 11986 argLen: 1, 11987 asm: arm64.ACLZW, 11988 reg: regInfo{ 11989 inputs: []inputInfo{ 11990 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11991 }, 11992 outputs: []outputInfo{ 11993 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11994 }, 11995 }, 11996 }, 11997 { 11998 name: "SLL", 11999 argLen: 2, 12000 asm: arm64.ALSL, 12001 reg: regInfo{ 12002 inputs: []inputInfo{ 12003 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12004 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12005 }, 12006 outputs: []outputInfo{ 12007 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12008 }, 12009 }, 12010 }, 12011 { 12012 name: "SLLconst", 12013 auxType: auxInt64, 12014 argLen: 1, 12015 asm: arm64.ALSL, 12016 reg: regInfo{ 12017 inputs: []inputInfo{ 12018 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12019 }, 12020 outputs: []outputInfo{ 12021 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12022 }, 12023 }, 12024 }, 12025 { 12026 name: "SRL", 12027 argLen: 2, 12028 asm: arm64.ALSR, 12029 reg: regInfo{ 12030 inputs: []inputInfo{ 12031 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12032 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12033 }, 12034 outputs: []outputInfo{ 12035 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12036 }, 12037 }, 12038 }, 12039 { 12040 name: "SRLconst", 12041 auxType: auxInt64, 12042 argLen: 1, 12043 asm: arm64.ALSR, 12044 reg: regInfo{ 12045 inputs: []inputInfo{ 12046 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12047 }, 12048 outputs: []outputInfo{ 12049 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12050 }, 12051 }, 12052 }, 12053 { 12054 name: "SRA", 12055 argLen: 2, 12056 asm: arm64.AASR, 12057 reg: regInfo{ 12058 inputs: []inputInfo{ 12059 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12060 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12061 }, 12062 outputs: []outputInfo{ 12063 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12064 }, 12065 }, 12066 }, 12067 { 12068 name: "SRAconst", 12069 auxType: auxInt64, 12070 argLen: 1, 12071 asm: arm64.AASR, 12072 reg: regInfo{ 12073 inputs: []inputInfo{ 12074 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12075 }, 12076 outputs: []outputInfo{ 12077 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12078 }, 12079 }, 12080 }, 12081 { 12082 name: "RORconst", 12083 auxType: auxInt64, 12084 argLen: 1, 12085 asm: arm64.AROR, 12086 reg: regInfo{ 12087 inputs: []inputInfo{ 12088 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12089 }, 12090 outputs: []outputInfo{ 12091 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12092 }, 12093 }, 12094 }, 12095 { 12096 name: "RORWconst", 12097 auxType: auxInt64, 12098 argLen: 1, 12099 asm: arm64.ARORW, 12100 reg: regInfo{ 12101 inputs: []inputInfo{ 12102 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12103 }, 12104 outputs: []outputInfo{ 12105 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12106 }, 12107 }, 12108 }, 12109 { 12110 name: "CMP", 12111 argLen: 2, 12112 asm: arm64.ACMP, 12113 reg: regInfo{ 12114 inputs: []inputInfo{ 12115 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12116 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12117 }, 12118 }, 12119 }, 12120 { 12121 name: "CMPconst", 12122 auxType: auxInt64, 12123 argLen: 1, 12124 asm: arm64.ACMP, 12125 reg: regInfo{ 12126 inputs: []inputInfo{ 12127 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12128 }, 12129 }, 12130 }, 12131 { 12132 name: "CMPW", 12133 argLen: 2, 12134 asm: arm64.ACMPW, 12135 reg: regInfo{ 12136 inputs: []inputInfo{ 12137 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12138 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12139 }, 12140 }, 12141 }, 12142 { 12143 name: "CMPWconst", 12144 auxType: auxInt32, 12145 argLen: 1, 12146 asm: arm64.ACMPW, 12147 reg: regInfo{ 12148 inputs: []inputInfo{ 12149 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12150 }, 12151 }, 12152 }, 12153 { 12154 name: "CMN", 12155 argLen: 2, 12156 asm: arm64.ACMN, 12157 reg: regInfo{ 12158 inputs: []inputInfo{ 12159 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12160 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12161 }, 12162 }, 12163 }, 12164 { 12165 name: "CMNconst", 12166 auxType: auxInt64, 12167 argLen: 1, 12168 asm: arm64.ACMN, 12169 reg: regInfo{ 12170 inputs: []inputInfo{ 12171 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12172 }, 12173 }, 12174 }, 12175 { 12176 name: "CMNW", 12177 argLen: 2, 12178 asm: arm64.ACMNW, 12179 reg: regInfo{ 12180 inputs: []inputInfo{ 12181 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12182 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12183 }, 12184 }, 12185 }, 12186 { 12187 name: "CMNWconst", 12188 auxType: auxInt32, 12189 argLen: 1, 12190 asm: arm64.ACMNW, 12191 reg: regInfo{ 12192 inputs: []inputInfo{ 12193 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12194 }, 12195 }, 12196 }, 12197 { 12198 name: "FCMPS", 12199 argLen: 2, 12200 asm: arm64.AFCMPS, 12201 reg: regInfo{ 12202 inputs: []inputInfo{ 12203 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12204 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12205 }, 12206 }, 12207 }, 12208 { 12209 name: "FCMPD", 12210 argLen: 2, 12211 asm: arm64.AFCMPD, 12212 reg: regInfo{ 12213 inputs: []inputInfo{ 12214 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12215 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12216 }, 12217 }, 12218 }, 12219 { 12220 name: "ADDshiftLL", 12221 auxType: auxInt64, 12222 argLen: 2, 12223 asm: arm64.AADD, 12224 reg: regInfo{ 12225 inputs: []inputInfo{ 12226 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12227 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12228 }, 12229 outputs: []outputInfo{ 12230 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12231 }, 12232 }, 12233 }, 12234 { 12235 name: "ADDshiftRL", 12236 auxType: auxInt64, 12237 argLen: 2, 12238 asm: arm64.AADD, 12239 reg: regInfo{ 12240 inputs: []inputInfo{ 12241 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12242 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12243 }, 12244 outputs: []outputInfo{ 12245 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12246 }, 12247 }, 12248 }, 12249 { 12250 name: "ADDshiftRA", 12251 auxType: auxInt64, 12252 argLen: 2, 12253 asm: arm64.AADD, 12254 reg: regInfo{ 12255 inputs: []inputInfo{ 12256 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12257 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12258 }, 12259 outputs: []outputInfo{ 12260 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12261 }, 12262 }, 12263 }, 12264 { 12265 name: "SUBshiftLL", 12266 auxType: auxInt64, 12267 argLen: 2, 12268 asm: arm64.ASUB, 12269 reg: regInfo{ 12270 inputs: []inputInfo{ 12271 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12272 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12273 }, 12274 outputs: []outputInfo{ 12275 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12276 }, 12277 }, 12278 }, 12279 { 12280 name: "SUBshiftRL", 12281 auxType: auxInt64, 12282 argLen: 2, 12283 asm: arm64.ASUB, 12284 reg: regInfo{ 12285 inputs: []inputInfo{ 12286 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12287 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12288 }, 12289 outputs: []outputInfo{ 12290 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12291 }, 12292 }, 12293 }, 12294 { 12295 name: "SUBshiftRA", 12296 auxType: auxInt64, 12297 argLen: 2, 12298 asm: arm64.ASUB, 12299 reg: regInfo{ 12300 inputs: []inputInfo{ 12301 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12302 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12303 }, 12304 outputs: []outputInfo{ 12305 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12306 }, 12307 }, 12308 }, 12309 { 12310 name: "ANDshiftLL", 12311 auxType: auxInt64, 12312 argLen: 2, 12313 asm: arm64.AAND, 12314 reg: regInfo{ 12315 inputs: []inputInfo{ 12316 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12317 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12318 }, 12319 outputs: []outputInfo{ 12320 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12321 }, 12322 }, 12323 }, 12324 { 12325 name: "ANDshiftRL", 12326 auxType: auxInt64, 12327 argLen: 2, 12328 asm: arm64.AAND, 12329 reg: regInfo{ 12330 inputs: []inputInfo{ 12331 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12332 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12333 }, 12334 outputs: []outputInfo{ 12335 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12336 }, 12337 }, 12338 }, 12339 { 12340 name: "ANDshiftRA", 12341 auxType: auxInt64, 12342 argLen: 2, 12343 asm: arm64.AAND, 12344 reg: regInfo{ 12345 inputs: []inputInfo{ 12346 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12347 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12348 }, 12349 outputs: []outputInfo{ 12350 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12351 }, 12352 }, 12353 }, 12354 { 12355 name: "ORshiftLL", 12356 auxType: auxInt64, 12357 argLen: 2, 12358 asm: arm64.AORR, 12359 reg: regInfo{ 12360 inputs: []inputInfo{ 12361 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12362 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12363 }, 12364 outputs: []outputInfo{ 12365 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12366 }, 12367 }, 12368 }, 12369 { 12370 name: "ORshiftRL", 12371 auxType: auxInt64, 12372 argLen: 2, 12373 asm: arm64.AORR, 12374 reg: regInfo{ 12375 inputs: []inputInfo{ 12376 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12377 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12378 }, 12379 outputs: []outputInfo{ 12380 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12381 }, 12382 }, 12383 }, 12384 { 12385 name: "ORshiftRA", 12386 auxType: auxInt64, 12387 argLen: 2, 12388 asm: arm64.AORR, 12389 reg: regInfo{ 12390 inputs: []inputInfo{ 12391 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12392 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12393 }, 12394 outputs: []outputInfo{ 12395 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12396 }, 12397 }, 12398 }, 12399 { 12400 name: "XORshiftLL", 12401 auxType: auxInt64, 12402 argLen: 2, 12403 asm: arm64.AEOR, 12404 reg: regInfo{ 12405 inputs: []inputInfo{ 12406 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12407 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12408 }, 12409 outputs: []outputInfo{ 12410 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12411 }, 12412 }, 12413 }, 12414 { 12415 name: "XORshiftRL", 12416 auxType: auxInt64, 12417 argLen: 2, 12418 asm: arm64.AEOR, 12419 reg: regInfo{ 12420 inputs: []inputInfo{ 12421 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12422 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12423 }, 12424 outputs: []outputInfo{ 12425 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12426 }, 12427 }, 12428 }, 12429 { 12430 name: "XORshiftRA", 12431 auxType: auxInt64, 12432 argLen: 2, 12433 asm: arm64.AEOR, 12434 reg: regInfo{ 12435 inputs: []inputInfo{ 12436 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12437 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12438 }, 12439 outputs: []outputInfo{ 12440 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12441 }, 12442 }, 12443 }, 12444 { 12445 name: "BICshiftLL", 12446 auxType: auxInt64, 12447 argLen: 2, 12448 asm: arm64.ABIC, 12449 reg: regInfo{ 12450 inputs: []inputInfo{ 12451 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12452 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12453 }, 12454 outputs: []outputInfo{ 12455 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12456 }, 12457 }, 12458 }, 12459 { 12460 name: "BICshiftRL", 12461 auxType: auxInt64, 12462 argLen: 2, 12463 asm: arm64.ABIC, 12464 reg: regInfo{ 12465 inputs: []inputInfo{ 12466 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12467 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12468 }, 12469 outputs: []outputInfo{ 12470 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12471 }, 12472 }, 12473 }, 12474 { 12475 name: "BICshiftRA", 12476 auxType: auxInt64, 12477 argLen: 2, 12478 asm: arm64.ABIC, 12479 reg: regInfo{ 12480 inputs: []inputInfo{ 12481 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12482 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12483 }, 12484 outputs: []outputInfo{ 12485 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12486 }, 12487 }, 12488 }, 12489 { 12490 name: "CMPshiftLL", 12491 auxType: auxInt64, 12492 argLen: 2, 12493 asm: arm64.ACMP, 12494 reg: regInfo{ 12495 inputs: []inputInfo{ 12496 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12497 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12498 }, 12499 }, 12500 }, 12501 { 12502 name: "CMPshiftRL", 12503 auxType: auxInt64, 12504 argLen: 2, 12505 asm: arm64.ACMP, 12506 reg: regInfo{ 12507 inputs: []inputInfo{ 12508 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12509 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12510 }, 12511 }, 12512 }, 12513 { 12514 name: "CMPshiftRA", 12515 auxType: auxInt64, 12516 argLen: 2, 12517 asm: arm64.ACMP, 12518 reg: regInfo{ 12519 inputs: []inputInfo{ 12520 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12521 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12522 }, 12523 }, 12524 }, 12525 { 12526 name: "MOVDconst", 12527 auxType: auxInt64, 12528 argLen: 0, 12529 rematerializeable: true, 12530 asm: arm64.AMOVD, 12531 reg: regInfo{ 12532 outputs: []outputInfo{ 12533 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12534 }, 12535 }, 12536 }, 12537 { 12538 name: "FMOVSconst", 12539 auxType: auxFloat64, 12540 argLen: 0, 12541 rematerializeable: true, 12542 asm: arm64.AFMOVS, 12543 reg: regInfo{ 12544 outputs: []outputInfo{ 12545 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12546 }, 12547 }, 12548 }, 12549 { 12550 name: "FMOVDconst", 12551 auxType: auxFloat64, 12552 argLen: 0, 12553 rematerializeable: true, 12554 asm: arm64.AFMOVD, 12555 reg: regInfo{ 12556 outputs: []outputInfo{ 12557 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12558 }, 12559 }, 12560 }, 12561 { 12562 name: "MOVDaddr", 12563 auxType: auxSymOff, 12564 argLen: 1, 12565 rematerializeable: true, 12566 symEffect: SymAddr, 12567 asm: arm64.AMOVD, 12568 reg: regInfo{ 12569 inputs: []inputInfo{ 12570 {0, 9223372037928517632}, // SP SB 12571 }, 12572 outputs: []outputInfo{ 12573 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12574 }, 12575 }, 12576 }, 12577 { 12578 name: "MOVBload", 12579 auxType: auxSymOff, 12580 argLen: 2, 12581 faultOnNilArg0: true, 12582 symEffect: SymRead, 12583 asm: arm64.AMOVB, 12584 reg: regInfo{ 12585 inputs: []inputInfo{ 12586 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12587 }, 12588 outputs: []outputInfo{ 12589 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12590 }, 12591 }, 12592 }, 12593 { 12594 name: "MOVBUload", 12595 auxType: auxSymOff, 12596 argLen: 2, 12597 faultOnNilArg0: true, 12598 symEffect: SymRead, 12599 asm: arm64.AMOVBU, 12600 reg: regInfo{ 12601 inputs: []inputInfo{ 12602 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12603 }, 12604 outputs: []outputInfo{ 12605 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12606 }, 12607 }, 12608 }, 12609 { 12610 name: "MOVHload", 12611 auxType: auxSymOff, 12612 argLen: 2, 12613 faultOnNilArg0: true, 12614 symEffect: SymRead, 12615 asm: arm64.AMOVH, 12616 reg: regInfo{ 12617 inputs: []inputInfo{ 12618 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12619 }, 12620 outputs: []outputInfo{ 12621 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12622 }, 12623 }, 12624 }, 12625 { 12626 name: "MOVHUload", 12627 auxType: auxSymOff, 12628 argLen: 2, 12629 faultOnNilArg0: true, 12630 symEffect: SymRead, 12631 asm: arm64.AMOVHU, 12632 reg: regInfo{ 12633 inputs: []inputInfo{ 12634 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12635 }, 12636 outputs: []outputInfo{ 12637 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12638 }, 12639 }, 12640 }, 12641 { 12642 name: "MOVWload", 12643 auxType: auxSymOff, 12644 argLen: 2, 12645 faultOnNilArg0: true, 12646 symEffect: SymRead, 12647 asm: arm64.AMOVW, 12648 reg: regInfo{ 12649 inputs: []inputInfo{ 12650 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12651 }, 12652 outputs: []outputInfo{ 12653 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12654 }, 12655 }, 12656 }, 12657 { 12658 name: "MOVWUload", 12659 auxType: auxSymOff, 12660 argLen: 2, 12661 faultOnNilArg0: true, 12662 symEffect: SymRead, 12663 asm: arm64.AMOVWU, 12664 reg: regInfo{ 12665 inputs: []inputInfo{ 12666 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12667 }, 12668 outputs: []outputInfo{ 12669 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12670 }, 12671 }, 12672 }, 12673 { 12674 name: "MOVDload", 12675 auxType: auxSymOff, 12676 argLen: 2, 12677 faultOnNilArg0: true, 12678 symEffect: SymRead, 12679 asm: arm64.AMOVD, 12680 reg: regInfo{ 12681 inputs: []inputInfo{ 12682 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12683 }, 12684 outputs: []outputInfo{ 12685 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12686 }, 12687 }, 12688 }, 12689 { 12690 name: "FMOVSload", 12691 auxType: auxSymOff, 12692 argLen: 2, 12693 faultOnNilArg0: true, 12694 symEffect: SymRead, 12695 asm: arm64.AFMOVS, 12696 reg: regInfo{ 12697 inputs: []inputInfo{ 12698 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12699 }, 12700 outputs: []outputInfo{ 12701 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12702 }, 12703 }, 12704 }, 12705 { 12706 name: "FMOVDload", 12707 auxType: auxSymOff, 12708 argLen: 2, 12709 faultOnNilArg0: true, 12710 symEffect: SymRead, 12711 asm: arm64.AFMOVD, 12712 reg: regInfo{ 12713 inputs: []inputInfo{ 12714 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12715 }, 12716 outputs: []outputInfo{ 12717 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12718 }, 12719 }, 12720 }, 12721 { 12722 name: "MOVBstore", 12723 auxType: auxSymOff, 12724 argLen: 3, 12725 faultOnNilArg0: true, 12726 symEffect: SymWrite, 12727 asm: arm64.AMOVB, 12728 reg: regInfo{ 12729 inputs: []inputInfo{ 12730 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12731 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12732 }, 12733 }, 12734 }, 12735 { 12736 name: "MOVHstore", 12737 auxType: auxSymOff, 12738 argLen: 3, 12739 faultOnNilArg0: true, 12740 symEffect: SymWrite, 12741 asm: arm64.AMOVH, 12742 reg: regInfo{ 12743 inputs: []inputInfo{ 12744 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12745 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12746 }, 12747 }, 12748 }, 12749 { 12750 name: "MOVWstore", 12751 auxType: auxSymOff, 12752 argLen: 3, 12753 faultOnNilArg0: true, 12754 symEffect: SymWrite, 12755 asm: arm64.AMOVW, 12756 reg: regInfo{ 12757 inputs: []inputInfo{ 12758 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12759 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12760 }, 12761 }, 12762 }, 12763 { 12764 name: "MOVDstore", 12765 auxType: auxSymOff, 12766 argLen: 3, 12767 faultOnNilArg0: true, 12768 symEffect: SymWrite, 12769 asm: arm64.AMOVD, 12770 reg: regInfo{ 12771 inputs: []inputInfo{ 12772 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12773 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12774 }, 12775 }, 12776 }, 12777 { 12778 name: "STP", 12779 auxType: auxSymOff, 12780 argLen: 4, 12781 faultOnNilArg0: true, 12782 symEffect: SymWrite, 12783 asm: arm64.ASTP, 12784 reg: regInfo{ 12785 inputs: []inputInfo{ 12786 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12787 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12788 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12789 }, 12790 }, 12791 }, 12792 { 12793 name: "FMOVSstore", 12794 auxType: auxSymOff, 12795 argLen: 3, 12796 faultOnNilArg0: true, 12797 symEffect: SymWrite, 12798 asm: arm64.AFMOVS, 12799 reg: regInfo{ 12800 inputs: []inputInfo{ 12801 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12802 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12803 }, 12804 }, 12805 }, 12806 { 12807 name: "FMOVDstore", 12808 auxType: auxSymOff, 12809 argLen: 3, 12810 faultOnNilArg0: true, 12811 symEffect: SymWrite, 12812 asm: arm64.AFMOVD, 12813 reg: regInfo{ 12814 inputs: []inputInfo{ 12815 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12816 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12817 }, 12818 }, 12819 }, 12820 { 12821 name: "MOVBstorezero", 12822 auxType: auxSymOff, 12823 argLen: 2, 12824 faultOnNilArg0: true, 12825 symEffect: SymWrite, 12826 asm: arm64.AMOVB, 12827 reg: regInfo{ 12828 inputs: []inputInfo{ 12829 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12830 }, 12831 }, 12832 }, 12833 { 12834 name: "MOVHstorezero", 12835 auxType: auxSymOff, 12836 argLen: 2, 12837 faultOnNilArg0: true, 12838 symEffect: SymWrite, 12839 asm: arm64.AMOVH, 12840 reg: regInfo{ 12841 inputs: []inputInfo{ 12842 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12843 }, 12844 }, 12845 }, 12846 { 12847 name: "MOVWstorezero", 12848 auxType: auxSymOff, 12849 argLen: 2, 12850 faultOnNilArg0: true, 12851 symEffect: SymWrite, 12852 asm: arm64.AMOVW, 12853 reg: regInfo{ 12854 inputs: []inputInfo{ 12855 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12856 }, 12857 }, 12858 }, 12859 { 12860 name: "MOVDstorezero", 12861 auxType: auxSymOff, 12862 argLen: 2, 12863 faultOnNilArg0: true, 12864 symEffect: SymWrite, 12865 asm: arm64.AMOVD, 12866 reg: regInfo{ 12867 inputs: []inputInfo{ 12868 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12869 }, 12870 }, 12871 }, 12872 { 12873 name: "MOVQstorezero", 12874 auxType: auxSymOff, 12875 argLen: 2, 12876 faultOnNilArg0: true, 12877 symEffect: SymWrite, 12878 asm: arm64.ASTP, 12879 reg: regInfo{ 12880 inputs: []inputInfo{ 12881 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12882 }, 12883 }, 12884 }, 12885 { 12886 name: "MOVBreg", 12887 argLen: 1, 12888 asm: arm64.AMOVB, 12889 reg: regInfo{ 12890 inputs: []inputInfo{ 12891 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12892 }, 12893 outputs: []outputInfo{ 12894 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12895 }, 12896 }, 12897 }, 12898 { 12899 name: "MOVBUreg", 12900 argLen: 1, 12901 asm: arm64.AMOVBU, 12902 reg: regInfo{ 12903 inputs: []inputInfo{ 12904 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12905 }, 12906 outputs: []outputInfo{ 12907 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12908 }, 12909 }, 12910 }, 12911 { 12912 name: "MOVHreg", 12913 argLen: 1, 12914 asm: arm64.AMOVH, 12915 reg: regInfo{ 12916 inputs: []inputInfo{ 12917 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12918 }, 12919 outputs: []outputInfo{ 12920 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12921 }, 12922 }, 12923 }, 12924 { 12925 name: "MOVHUreg", 12926 argLen: 1, 12927 asm: arm64.AMOVHU, 12928 reg: regInfo{ 12929 inputs: []inputInfo{ 12930 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12931 }, 12932 outputs: []outputInfo{ 12933 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12934 }, 12935 }, 12936 }, 12937 { 12938 name: "MOVWreg", 12939 argLen: 1, 12940 asm: arm64.AMOVW, 12941 reg: regInfo{ 12942 inputs: []inputInfo{ 12943 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12944 }, 12945 outputs: []outputInfo{ 12946 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12947 }, 12948 }, 12949 }, 12950 { 12951 name: "MOVWUreg", 12952 argLen: 1, 12953 asm: arm64.AMOVWU, 12954 reg: regInfo{ 12955 inputs: []inputInfo{ 12956 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12957 }, 12958 outputs: []outputInfo{ 12959 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12960 }, 12961 }, 12962 }, 12963 { 12964 name: "MOVDreg", 12965 argLen: 1, 12966 asm: arm64.AMOVD, 12967 reg: regInfo{ 12968 inputs: []inputInfo{ 12969 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12970 }, 12971 outputs: []outputInfo{ 12972 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12973 }, 12974 }, 12975 }, 12976 { 12977 name: "MOVDnop", 12978 argLen: 1, 12979 resultInArg0: true, 12980 reg: regInfo{ 12981 inputs: []inputInfo{ 12982 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12983 }, 12984 outputs: []outputInfo{ 12985 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12986 }, 12987 }, 12988 }, 12989 { 12990 name: "SCVTFWS", 12991 argLen: 1, 12992 asm: arm64.ASCVTFWS, 12993 reg: regInfo{ 12994 inputs: []inputInfo{ 12995 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12996 }, 12997 outputs: []outputInfo{ 12998 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12999 }, 13000 }, 13001 }, 13002 { 13003 name: "SCVTFWD", 13004 argLen: 1, 13005 asm: arm64.ASCVTFWD, 13006 reg: regInfo{ 13007 inputs: []inputInfo{ 13008 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13009 }, 13010 outputs: []outputInfo{ 13011 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13012 }, 13013 }, 13014 }, 13015 { 13016 name: "UCVTFWS", 13017 argLen: 1, 13018 asm: arm64.AUCVTFWS, 13019 reg: regInfo{ 13020 inputs: []inputInfo{ 13021 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13022 }, 13023 outputs: []outputInfo{ 13024 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13025 }, 13026 }, 13027 }, 13028 { 13029 name: "UCVTFWD", 13030 argLen: 1, 13031 asm: arm64.AUCVTFWD, 13032 reg: regInfo{ 13033 inputs: []inputInfo{ 13034 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13035 }, 13036 outputs: []outputInfo{ 13037 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13038 }, 13039 }, 13040 }, 13041 { 13042 name: "SCVTFS", 13043 argLen: 1, 13044 asm: arm64.ASCVTFS, 13045 reg: regInfo{ 13046 inputs: []inputInfo{ 13047 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13048 }, 13049 outputs: []outputInfo{ 13050 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13051 }, 13052 }, 13053 }, 13054 { 13055 name: "SCVTFD", 13056 argLen: 1, 13057 asm: arm64.ASCVTFD, 13058 reg: regInfo{ 13059 inputs: []inputInfo{ 13060 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13061 }, 13062 outputs: []outputInfo{ 13063 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13064 }, 13065 }, 13066 }, 13067 { 13068 name: "UCVTFS", 13069 argLen: 1, 13070 asm: arm64.AUCVTFS, 13071 reg: regInfo{ 13072 inputs: []inputInfo{ 13073 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13074 }, 13075 outputs: []outputInfo{ 13076 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13077 }, 13078 }, 13079 }, 13080 { 13081 name: "UCVTFD", 13082 argLen: 1, 13083 asm: arm64.AUCVTFD, 13084 reg: regInfo{ 13085 inputs: []inputInfo{ 13086 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13087 }, 13088 outputs: []outputInfo{ 13089 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13090 }, 13091 }, 13092 }, 13093 { 13094 name: "FCVTZSSW", 13095 argLen: 1, 13096 asm: arm64.AFCVTZSSW, 13097 reg: regInfo{ 13098 inputs: []inputInfo{ 13099 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13100 }, 13101 outputs: []outputInfo{ 13102 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13103 }, 13104 }, 13105 }, 13106 { 13107 name: "FCVTZSDW", 13108 argLen: 1, 13109 asm: arm64.AFCVTZSDW, 13110 reg: regInfo{ 13111 inputs: []inputInfo{ 13112 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13113 }, 13114 outputs: []outputInfo{ 13115 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13116 }, 13117 }, 13118 }, 13119 { 13120 name: "FCVTZUSW", 13121 argLen: 1, 13122 asm: arm64.AFCVTZUSW, 13123 reg: regInfo{ 13124 inputs: []inputInfo{ 13125 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13126 }, 13127 outputs: []outputInfo{ 13128 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13129 }, 13130 }, 13131 }, 13132 { 13133 name: "FCVTZUDW", 13134 argLen: 1, 13135 asm: arm64.AFCVTZUDW, 13136 reg: regInfo{ 13137 inputs: []inputInfo{ 13138 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13139 }, 13140 outputs: []outputInfo{ 13141 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13142 }, 13143 }, 13144 }, 13145 { 13146 name: "FCVTZSS", 13147 argLen: 1, 13148 asm: arm64.AFCVTZSS, 13149 reg: regInfo{ 13150 inputs: []inputInfo{ 13151 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13152 }, 13153 outputs: []outputInfo{ 13154 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13155 }, 13156 }, 13157 }, 13158 { 13159 name: "FCVTZSD", 13160 argLen: 1, 13161 asm: arm64.AFCVTZSD, 13162 reg: regInfo{ 13163 inputs: []inputInfo{ 13164 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13165 }, 13166 outputs: []outputInfo{ 13167 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13168 }, 13169 }, 13170 }, 13171 { 13172 name: "FCVTZUS", 13173 argLen: 1, 13174 asm: arm64.AFCVTZUS, 13175 reg: regInfo{ 13176 inputs: []inputInfo{ 13177 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13178 }, 13179 outputs: []outputInfo{ 13180 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13181 }, 13182 }, 13183 }, 13184 { 13185 name: "FCVTZUD", 13186 argLen: 1, 13187 asm: arm64.AFCVTZUD, 13188 reg: regInfo{ 13189 inputs: []inputInfo{ 13190 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13191 }, 13192 outputs: []outputInfo{ 13193 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13194 }, 13195 }, 13196 }, 13197 { 13198 name: "FCVTSD", 13199 argLen: 1, 13200 asm: arm64.AFCVTSD, 13201 reg: regInfo{ 13202 inputs: []inputInfo{ 13203 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13204 }, 13205 outputs: []outputInfo{ 13206 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13207 }, 13208 }, 13209 }, 13210 { 13211 name: "FCVTDS", 13212 argLen: 1, 13213 asm: arm64.AFCVTDS, 13214 reg: regInfo{ 13215 inputs: []inputInfo{ 13216 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13217 }, 13218 outputs: []outputInfo{ 13219 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13220 }, 13221 }, 13222 }, 13223 { 13224 name: "CSELULT", 13225 argLen: 3, 13226 asm: arm64.ACSEL, 13227 reg: regInfo{ 13228 inputs: []inputInfo{ 13229 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13230 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13231 }, 13232 outputs: []outputInfo{ 13233 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13234 }, 13235 }, 13236 }, 13237 { 13238 name: "CSELULT0", 13239 argLen: 2, 13240 asm: arm64.ACSEL, 13241 reg: regInfo{ 13242 inputs: []inputInfo{ 13243 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13244 }, 13245 outputs: []outputInfo{ 13246 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13247 }, 13248 }, 13249 }, 13250 { 13251 name: "CALLstatic", 13252 auxType: auxSymOff, 13253 argLen: 1, 13254 clobberFlags: true, 13255 call: true, 13256 symEffect: SymNone, 13257 reg: regInfo{ 13258 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13259 }, 13260 }, 13261 { 13262 name: "CALLclosure", 13263 auxType: auxInt64, 13264 argLen: 3, 13265 clobberFlags: true, 13266 call: true, 13267 reg: regInfo{ 13268 inputs: []inputInfo{ 13269 {1, 67108864}, // R26 13270 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 13271 }, 13272 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13273 }, 13274 }, 13275 { 13276 name: "CALLinter", 13277 auxType: auxInt64, 13278 argLen: 2, 13279 clobberFlags: true, 13280 call: true, 13281 reg: regInfo{ 13282 inputs: []inputInfo{ 13283 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13284 }, 13285 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13286 }, 13287 }, 13288 { 13289 name: "LoweredNilCheck", 13290 argLen: 2, 13291 nilCheck: true, 13292 faultOnNilArg0: true, 13293 reg: regInfo{ 13294 inputs: []inputInfo{ 13295 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13296 }, 13297 }, 13298 }, 13299 { 13300 name: "Equal", 13301 argLen: 1, 13302 reg: regInfo{ 13303 outputs: []outputInfo{ 13304 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13305 }, 13306 }, 13307 }, 13308 { 13309 name: "NotEqual", 13310 argLen: 1, 13311 reg: regInfo{ 13312 outputs: []outputInfo{ 13313 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13314 }, 13315 }, 13316 }, 13317 { 13318 name: "LessThan", 13319 argLen: 1, 13320 reg: regInfo{ 13321 outputs: []outputInfo{ 13322 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13323 }, 13324 }, 13325 }, 13326 { 13327 name: "LessEqual", 13328 argLen: 1, 13329 reg: regInfo{ 13330 outputs: []outputInfo{ 13331 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13332 }, 13333 }, 13334 }, 13335 { 13336 name: "GreaterThan", 13337 argLen: 1, 13338 reg: regInfo{ 13339 outputs: []outputInfo{ 13340 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13341 }, 13342 }, 13343 }, 13344 { 13345 name: "GreaterEqual", 13346 argLen: 1, 13347 reg: regInfo{ 13348 outputs: []outputInfo{ 13349 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13350 }, 13351 }, 13352 }, 13353 { 13354 name: "LessThanU", 13355 argLen: 1, 13356 reg: regInfo{ 13357 outputs: []outputInfo{ 13358 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13359 }, 13360 }, 13361 }, 13362 { 13363 name: "LessEqualU", 13364 argLen: 1, 13365 reg: regInfo{ 13366 outputs: []outputInfo{ 13367 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13368 }, 13369 }, 13370 }, 13371 { 13372 name: "GreaterThanU", 13373 argLen: 1, 13374 reg: regInfo{ 13375 outputs: []outputInfo{ 13376 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13377 }, 13378 }, 13379 }, 13380 { 13381 name: "GreaterEqualU", 13382 argLen: 1, 13383 reg: regInfo{ 13384 outputs: []outputInfo{ 13385 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13386 }, 13387 }, 13388 }, 13389 { 13390 name: "DUFFZERO", 13391 auxType: auxInt64, 13392 argLen: 2, 13393 faultOnNilArg0: true, 13394 reg: regInfo{ 13395 inputs: []inputInfo{ 13396 {0, 65536}, // R16 13397 }, 13398 clobbers: 536936448, // R16 R30 13399 }, 13400 }, 13401 { 13402 name: "LoweredZero", 13403 argLen: 3, 13404 clobberFlags: true, 13405 faultOnNilArg0: true, 13406 reg: regInfo{ 13407 inputs: []inputInfo{ 13408 {0, 65536}, // R16 13409 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13410 }, 13411 clobbers: 65536, // R16 13412 }, 13413 }, 13414 { 13415 name: "DUFFCOPY", 13416 auxType: auxInt64, 13417 argLen: 3, 13418 faultOnNilArg0: true, 13419 faultOnNilArg1: true, 13420 reg: regInfo{ 13421 inputs: []inputInfo{ 13422 {0, 131072}, // R17 13423 {1, 65536}, // R16 13424 }, 13425 clobbers: 537067520, // R16 R17 R30 13426 }, 13427 }, 13428 { 13429 name: "LoweredMove", 13430 argLen: 4, 13431 clobberFlags: true, 13432 faultOnNilArg0: true, 13433 faultOnNilArg1: true, 13434 reg: regInfo{ 13435 inputs: []inputInfo{ 13436 {0, 131072}, // R17 13437 {1, 65536}, // R16 13438 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13439 }, 13440 clobbers: 196608, // R16 R17 13441 }, 13442 }, 13443 { 13444 name: "LoweredGetClosurePtr", 13445 argLen: 0, 13446 reg: regInfo{ 13447 outputs: []outputInfo{ 13448 {0, 67108864}, // R26 13449 }, 13450 }, 13451 }, 13452 { 13453 name: "MOVDconvert", 13454 argLen: 2, 13455 asm: arm64.AMOVD, 13456 reg: regInfo{ 13457 inputs: []inputInfo{ 13458 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13459 }, 13460 outputs: []outputInfo{ 13461 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13462 }, 13463 }, 13464 }, 13465 { 13466 name: "FlagEQ", 13467 argLen: 0, 13468 reg: regInfo{}, 13469 }, 13470 { 13471 name: "FlagLT_ULT", 13472 argLen: 0, 13473 reg: regInfo{}, 13474 }, 13475 { 13476 name: "FlagLT_UGT", 13477 argLen: 0, 13478 reg: regInfo{}, 13479 }, 13480 { 13481 name: "FlagGT_UGT", 13482 argLen: 0, 13483 reg: regInfo{}, 13484 }, 13485 { 13486 name: "FlagGT_ULT", 13487 argLen: 0, 13488 reg: regInfo{}, 13489 }, 13490 { 13491 name: "InvertFlags", 13492 argLen: 1, 13493 reg: regInfo{}, 13494 }, 13495 { 13496 name: "LDAR", 13497 argLen: 2, 13498 faultOnNilArg0: true, 13499 asm: arm64.ALDAR, 13500 reg: regInfo{ 13501 inputs: []inputInfo{ 13502 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13503 }, 13504 outputs: []outputInfo{ 13505 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13506 }, 13507 }, 13508 }, 13509 { 13510 name: "LDARW", 13511 argLen: 2, 13512 faultOnNilArg0: true, 13513 asm: arm64.ALDARW, 13514 reg: regInfo{ 13515 inputs: []inputInfo{ 13516 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13517 }, 13518 outputs: []outputInfo{ 13519 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13520 }, 13521 }, 13522 }, 13523 { 13524 name: "STLR", 13525 argLen: 3, 13526 faultOnNilArg0: true, 13527 hasSideEffects: true, 13528 asm: arm64.ASTLR, 13529 reg: regInfo{ 13530 inputs: []inputInfo{ 13531 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13532 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13533 }, 13534 }, 13535 }, 13536 { 13537 name: "STLRW", 13538 argLen: 3, 13539 faultOnNilArg0: true, 13540 hasSideEffects: true, 13541 asm: arm64.ASTLRW, 13542 reg: regInfo{ 13543 inputs: []inputInfo{ 13544 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13545 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13546 }, 13547 }, 13548 }, 13549 { 13550 name: "LoweredAtomicExchange64", 13551 argLen: 3, 13552 resultNotInArgs: true, 13553 faultOnNilArg0: true, 13554 hasSideEffects: true, 13555 reg: regInfo{ 13556 inputs: []inputInfo{ 13557 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13558 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13559 }, 13560 outputs: []outputInfo{ 13561 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13562 }, 13563 }, 13564 }, 13565 { 13566 name: "LoweredAtomicExchange32", 13567 argLen: 3, 13568 resultNotInArgs: true, 13569 faultOnNilArg0: true, 13570 hasSideEffects: true, 13571 reg: regInfo{ 13572 inputs: []inputInfo{ 13573 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13574 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13575 }, 13576 outputs: []outputInfo{ 13577 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13578 }, 13579 }, 13580 }, 13581 { 13582 name: "LoweredAtomicAdd64", 13583 argLen: 3, 13584 resultNotInArgs: true, 13585 faultOnNilArg0: true, 13586 hasSideEffects: true, 13587 reg: regInfo{ 13588 inputs: []inputInfo{ 13589 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13590 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13591 }, 13592 outputs: []outputInfo{ 13593 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13594 }, 13595 }, 13596 }, 13597 { 13598 name: "LoweredAtomicAdd32", 13599 argLen: 3, 13600 resultNotInArgs: true, 13601 faultOnNilArg0: true, 13602 hasSideEffects: true, 13603 reg: regInfo{ 13604 inputs: []inputInfo{ 13605 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13606 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13607 }, 13608 outputs: []outputInfo{ 13609 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13610 }, 13611 }, 13612 }, 13613 { 13614 name: "LoweredAtomicCas64", 13615 argLen: 4, 13616 resultNotInArgs: true, 13617 clobberFlags: true, 13618 faultOnNilArg0: true, 13619 hasSideEffects: true, 13620 reg: regInfo{ 13621 inputs: []inputInfo{ 13622 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13623 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13624 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13625 }, 13626 outputs: []outputInfo{ 13627 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13628 }, 13629 }, 13630 }, 13631 { 13632 name: "LoweredAtomicCas32", 13633 argLen: 4, 13634 resultNotInArgs: true, 13635 clobberFlags: true, 13636 faultOnNilArg0: true, 13637 hasSideEffects: true, 13638 reg: regInfo{ 13639 inputs: []inputInfo{ 13640 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13641 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13642 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13643 }, 13644 outputs: []outputInfo{ 13645 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13646 }, 13647 }, 13648 }, 13649 { 13650 name: "LoweredAtomicAnd8", 13651 argLen: 3, 13652 faultOnNilArg0: true, 13653 hasSideEffects: true, 13654 asm: arm64.AAND, 13655 reg: regInfo{ 13656 inputs: []inputInfo{ 13657 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13658 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13659 }, 13660 }, 13661 }, 13662 { 13663 name: "LoweredAtomicOr8", 13664 argLen: 3, 13665 faultOnNilArg0: true, 13666 hasSideEffects: true, 13667 asm: arm64.AORR, 13668 reg: regInfo{ 13669 inputs: []inputInfo{ 13670 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13671 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13672 }, 13673 }, 13674 }, 13675 13676 { 13677 name: "ADD", 13678 argLen: 2, 13679 commutative: true, 13680 asm: mips.AADDU, 13681 reg: regInfo{ 13682 inputs: []inputInfo{ 13683 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13684 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13685 }, 13686 outputs: []outputInfo{ 13687 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13688 }, 13689 }, 13690 }, 13691 { 13692 name: "ADDconst", 13693 auxType: auxInt32, 13694 argLen: 1, 13695 asm: mips.AADDU, 13696 reg: regInfo{ 13697 inputs: []inputInfo{ 13698 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 13699 }, 13700 outputs: []outputInfo{ 13701 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13702 }, 13703 }, 13704 }, 13705 { 13706 name: "SUB", 13707 argLen: 2, 13708 asm: mips.ASUBU, 13709 reg: regInfo{ 13710 inputs: []inputInfo{ 13711 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13712 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13713 }, 13714 outputs: []outputInfo{ 13715 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13716 }, 13717 }, 13718 }, 13719 { 13720 name: "SUBconst", 13721 auxType: auxInt32, 13722 argLen: 1, 13723 asm: mips.ASUBU, 13724 reg: regInfo{ 13725 inputs: []inputInfo{ 13726 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13727 }, 13728 outputs: []outputInfo{ 13729 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13730 }, 13731 }, 13732 }, 13733 { 13734 name: "MUL", 13735 argLen: 2, 13736 commutative: true, 13737 asm: mips.AMUL, 13738 reg: regInfo{ 13739 inputs: []inputInfo{ 13740 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13741 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13742 }, 13743 clobbers: 105553116266496, // HI LO 13744 outputs: []outputInfo{ 13745 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13746 }, 13747 }, 13748 }, 13749 { 13750 name: "MULT", 13751 argLen: 2, 13752 commutative: true, 13753 asm: mips.AMUL, 13754 reg: regInfo{ 13755 inputs: []inputInfo{ 13756 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13757 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13758 }, 13759 outputs: []outputInfo{ 13760 {0, 35184372088832}, // HI 13761 {1, 70368744177664}, // LO 13762 }, 13763 }, 13764 }, 13765 { 13766 name: "MULTU", 13767 argLen: 2, 13768 commutative: true, 13769 asm: mips.AMULU, 13770 reg: regInfo{ 13771 inputs: []inputInfo{ 13772 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13773 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13774 }, 13775 outputs: []outputInfo{ 13776 {0, 35184372088832}, // HI 13777 {1, 70368744177664}, // LO 13778 }, 13779 }, 13780 }, 13781 { 13782 name: "DIV", 13783 argLen: 2, 13784 asm: mips.ADIV, 13785 reg: regInfo{ 13786 inputs: []inputInfo{ 13787 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13788 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13789 }, 13790 outputs: []outputInfo{ 13791 {0, 35184372088832}, // HI 13792 {1, 70368744177664}, // LO 13793 }, 13794 }, 13795 }, 13796 { 13797 name: "DIVU", 13798 argLen: 2, 13799 asm: mips.ADIVU, 13800 reg: regInfo{ 13801 inputs: []inputInfo{ 13802 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13803 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13804 }, 13805 outputs: []outputInfo{ 13806 {0, 35184372088832}, // HI 13807 {1, 70368744177664}, // LO 13808 }, 13809 }, 13810 }, 13811 { 13812 name: "ADDF", 13813 argLen: 2, 13814 commutative: true, 13815 asm: mips.AADDF, 13816 reg: regInfo{ 13817 inputs: []inputInfo{ 13818 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13819 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13820 }, 13821 outputs: []outputInfo{ 13822 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13823 }, 13824 }, 13825 }, 13826 { 13827 name: "ADDD", 13828 argLen: 2, 13829 commutative: true, 13830 asm: mips.AADDD, 13831 reg: regInfo{ 13832 inputs: []inputInfo{ 13833 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13834 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13835 }, 13836 outputs: []outputInfo{ 13837 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13838 }, 13839 }, 13840 }, 13841 { 13842 name: "SUBF", 13843 argLen: 2, 13844 asm: mips.ASUBF, 13845 reg: regInfo{ 13846 inputs: []inputInfo{ 13847 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13848 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13849 }, 13850 outputs: []outputInfo{ 13851 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13852 }, 13853 }, 13854 }, 13855 { 13856 name: "SUBD", 13857 argLen: 2, 13858 asm: mips.ASUBD, 13859 reg: regInfo{ 13860 inputs: []inputInfo{ 13861 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13862 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13863 }, 13864 outputs: []outputInfo{ 13865 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13866 }, 13867 }, 13868 }, 13869 { 13870 name: "MULF", 13871 argLen: 2, 13872 commutative: true, 13873 asm: mips.AMULF, 13874 reg: regInfo{ 13875 inputs: []inputInfo{ 13876 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13877 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13878 }, 13879 outputs: []outputInfo{ 13880 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13881 }, 13882 }, 13883 }, 13884 { 13885 name: "MULD", 13886 argLen: 2, 13887 commutative: true, 13888 asm: mips.AMULD, 13889 reg: regInfo{ 13890 inputs: []inputInfo{ 13891 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13892 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13893 }, 13894 outputs: []outputInfo{ 13895 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13896 }, 13897 }, 13898 }, 13899 { 13900 name: "DIVF", 13901 argLen: 2, 13902 asm: mips.ADIVF, 13903 reg: regInfo{ 13904 inputs: []inputInfo{ 13905 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13906 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13907 }, 13908 outputs: []outputInfo{ 13909 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13910 }, 13911 }, 13912 }, 13913 { 13914 name: "DIVD", 13915 argLen: 2, 13916 asm: mips.ADIVD, 13917 reg: regInfo{ 13918 inputs: []inputInfo{ 13919 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13920 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13921 }, 13922 outputs: []outputInfo{ 13923 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13924 }, 13925 }, 13926 }, 13927 { 13928 name: "AND", 13929 argLen: 2, 13930 commutative: true, 13931 asm: mips.AAND, 13932 reg: regInfo{ 13933 inputs: []inputInfo{ 13934 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13935 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13936 }, 13937 outputs: []outputInfo{ 13938 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13939 }, 13940 }, 13941 }, 13942 { 13943 name: "ANDconst", 13944 auxType: auxInt32, 13945 argLen: 1, 13946 asm: mips.AAND, 13947 reg: regInfo{ 13948 inputs: []inputInfo{ 13949 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13950 }, 13951 outputs: []outputInfo{ 13952 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13953 }, 13954 }, 13955 }, 13956 { 13957 name: "OR", 13958 argLen: 2, 13959 commutative: true, 13960 asm: mips.AOR, 13961 reg: regInfo{ 13962 inputs: []inputInfo{ 13963 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13964 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13965 }, 13966 outputs: []outputInfo{ 13967 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13968 }, 13969 }, 13970 }, 13971 { 13972 name: "ORconst", 13973 auxType: auxInt32, 13974 argLen: 1, 13975 asm: mips.AOR, 13976 reg: regInfo{ 13977 inputs: []inputInfo{ 13978 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13979 }, 13980 outputs: []outputInfo{ 13981 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13982 }, 13983 }, 13984 }, 13985 { 13986 name: "XOR", 13987 argLen: 2, 13988 commutative: true, 13989 asm: mips.AXOR, 13990 reg: regInfo{ 13991 inputs: []inputInfo{ 13992 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13993 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13994 }, 13995 outputs: []outputInfo{ 13996 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13997 }, 13998 }, 13999 }, 14000 { 14001 name: "XORconst", 14002 auxType: auxInt32, 14003 argLen: 1, 14004 asm: mips.AXOR, 14005 reg: regInfo{ 14006 inputs: []inputInfo{ 14007 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14008 }, 14009 outputs: []outputInfo{ 14010 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14011 }, 14012 }, 14013 }, 14014 { 14015 name: "NOR", 14016 argLen: 2, 14017 commutative: true, 14018 asm: mips.ANOR, 14019 reg: regInfo{ 14020 inputs: []inputInfo{ 14021 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14022 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14023 }, 14024 outputs: []outputInfo{ 14025 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14026 }, 14027 }, 14028 }, 14029 { 14030 name: "NORconst", 14031 auxType: auxInt32, 14032 argLen: 1, 14033 asm: mips.ANOR, 14034 reg: regInfo{ 14035 inputs: []inputInfo{ 14036 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14037 }, 14038 outputs: []outputInfo{ 14039 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14040 }, 14041 }, 14042 }, 14043 { 14044 name: "NEG", 14045 argLen: 1, 14046 reg: regInfo{ 14047 inputs: []inputInfo{ 14048 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14049 }, 14050 outputs: []outputInfo{ 14051 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14052 }, 14053 }, 14054 }, 14055 { 14056 name: "NEGF", 14057 argLen: 1, 14058 asm: mips.ANEGF, 14059 reg: regInfo{ 14060 inputs: []inputInfo{ 14061 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14062 }, 14063 outputs: []outputInfo{ 14064 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14065 }, 14066 }, 14067 }, 14068 { 14069 name: "NEGD", 14070 argLen: 1, 14071 asm: mips.ANEGD, 14072 reg: regInfo{ 14073 inputs: []inputInfo{ 14074 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14075 }, 14076 outputs: []outputInfo{ 14077 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14078 }, 14079 }, 14080 }, 14081 { 14082 name: "SQRTD", 14083 argLen: 1, 14084 asm: mips.ASQRTD, 14085 reg: regInfo{ 14086 inputs: []inputInfo{ 14087 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14088 }, 14089 outputs: []outputInfo{ 14090 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14091 }, 14092 }, 14093 }, 14094 { 14095 name: "SLL", 14096 argLen: 2, 14097 asm: mips.ASLL, 14098 reg: regInfo{ 14099 inputs: []inputInfo{ 14100 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14101 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14102 }, 14103 outputs: []outputInfo{ 14104 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14105 }, 14106 }, 14107 }, 14108 { 14109 name: "SLLconst", 14110 auxType: auxInt32, 14111 argLen: 1, 14112 asm: mips.ASLL, 14113 reg: regInfo{ 14114 inputs: []inputInfo{ 14115 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14116 }, 14117 outputs: []outputInfo{ 14118 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14119 }, 14120 }, 14121 }, 14122 { 14123 name: "SRL", 14124 argLen: 2, 14125 asm: mips.ASRL, 14126 reg: regInfo{ 14127 inputs: []inputInfo{ 14128 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14129 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14130 }, 14131 outputs: []outputInfo{ 14132 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14133 }, 14134 }, 14135 }, 14136 { 14137 name: "SRLconst", 14138 auxType: auxInt32, 14139 argLen: 1, 14140 asm: mips.ASRL, 14141 reg: regInfo{ 14142 inputs: []inputInfo{ 14143 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14144 }, 14145 outputs: []outputInfo{ 14146 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14147 }, 14148 }, 14149 }, 14150 { 14151 name: "SRA", 14152 argLen: 2, 14153 asm: mips.ASRA, 14154 reg: regInfo{ 14155 inputs: []inputInfo{ 14156 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14157 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14158 }, 14159 outputs: []outputInfo{ 14160 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14161 }, 14162 }, 14163 }, 14164 { 14165 name: "SRAconst", 14166 auxType: auxInt32, 14167 argLen: 1, 14168 asm: mips.ASRA, 14169 reg: regInfo{ 14170 inputs: []inputInfo{ 14171 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14172 }, 14173 outputs: []outputInfo{ 14174 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14175 }, 14176 }, 14177 }, 14178 { 14179 name: "CLZ", 14180 argLen: 1, 14181 asm: mips.ACLZ, 14182 reg: regInfo{ 14183 inputs: []inputInfo{ 14184 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14185 }, 14186 outputs: []outputInfo{ 14187 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14188 }, 14189 }, 14190 }, 14191 { 14192 name: "SGT", 14193 argLen: 2, 14194 asm: mips.ASGT, 14195 reg: regInfo{ 14196 inputs: []inputInfo{ 14197 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14198 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14199 }, 14200 outputs: []outputInfo{ 14201 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14202 }, 14203 }, 14204 }, 14205 { 14206 name: "SGTconst", 14207 auxType: auxInt32, 14208 argLen: 1, 14209 asm: mips.ASGT, 14210 reg: regInfo{ 14211 inputs: []inputInfo{ 14212 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14213 }, 14214 outputs: []outputInfo{ 14215 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14216 }, 14217 }, 14218 }, 14219 { 14220 name: "SGTzero", 14221 argLen: 1, 14222 asm: mips.ASGT, 14223 reg: regInfo{ 14224 inputs: []inputInfo{ 14225 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14226 }, 14227 outputs: []outputInfo{ 14228 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14229 }, 14230 }, 14231 }, 14232 { 14233 name: "SGTU", 14234 argLen: 2, 14235 asm: mips.ASGTU, 14236 reg: regInfo{ 14237 inputs: []inputInfo{ 14238 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14239 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14240 }, 14241 outputs: []outputInfo{ 14242 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14243 }, 14244 }, 14245 }, 14246 { 14247 name: "SGTUconst", 14248 auxType: auxInt32, 14249 argLen: 1, 14250 asm: mips.ASGTU, 14251 reg: regInfo{ 14252 inputs: []inputInfo{ 14253 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14254 }, 14255 outputs: []outputInfo{ 14256 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14257 }, 14258 }, 14259 }, 14260 { 14261 name: "SGTUzero", 14262 argLen: 1, 14263 asm: mips.ASGTU, 14264 reg: regInfo{ 14265 inputs: []inputInfo{ 14266 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14267 }, 14268 outputs: []outputInfo{ 14269 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14270 }, 14271 }, 14272 }, 14273 { 14274 name: "CMPEQF", 14275 argLen: 2, 14276 asm: mips.ACMPEQF, 14277 reg: regInfo{ 14278 inputs: []inputInfo{ 14279 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14280 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14281 }, 14282 }, 14283 }, 14284 { 14285 name: "CMPEQD", 14286 argLen: 2, 14287 asm: mips.ACMPEQD, 14288 reg: regInfo{ 14289 inputs: []inputInfo{ 14290 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14291 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14292 }, 14293 }, 14294 }, 14295 { 14296 name: "CMPGEF", 14297 argLen: 2, 14298 asm: mips.ACMPGEF, 14299 reg: regInfo{ 14300 inputs: []inputInfo{ 14301 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14302 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14303 }, 14304 }, 14305 }, 14306 { 14307 name: "CMPGED", 14308 argLen: 2, 14309 asm: mips.ACMPGED, 14310 reg: regInfo{ 14311 inputs: []inputInfo{ 14312 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14313 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14314 }, 14315 }, 14316 }, 14317 { 14318 name: "CMPGTF", 14319 argLen: 2, 14320 asm: mips.ACMPGTF, 14321 reg: regInfo{ 14322 inputs: []inputInfo{ 14323 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14324 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14325 }, 14326 }, 14327 }, 14328 { 14329 name: "CMPGTD", 14330 argLen: 2, 14331 asm: mips.ACMPGTD, 14332 reg: regInfo{ 14333 inputs: []inputInfo{ 14334 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14335 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14336 }, 14337 }, 14338 }, 14339 { 14340 name: "MOVWconst", 14341 auxType: auxInt32, 14342 argLen: 0, 14343 rematerializeable: true, 14344 asm: mips.AMOVW, 14345 reg: regInfo{ 14346 outputs: []outputInfo{ 14347 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14348 }, 14349 }, 14350 }, 14351 { 14352 name: "MOVFconst", 14353 auxType: auxFloat32, 14354 argLen: 0, 14355 rematerializeable: true, 14356 asm: mips.AMOVF, 14357 reg: regInfo{ 14358 outputs: []outputInfo{ 14359 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14360 }, 14361 }, 14362 }, 14363 { 14364 name: "MOVDconst", 14365 auxType: auxFloat64, 14366 argLen: 0, 14367 rematerializeable: true, 14368 asm: mips.AMOVD, 14369 reg: regInfo{ 14370 outputs: []outputInfo{ 14371 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14372 }, 14373 }, 14374 }, 14375 { 14376 name: "MOVWaddr", 14377 auxType: auxSymOff, 14378 argLen: 1, 14379 rematerializeable: true, 14380 symEffect: SymAddr, 14381 asm: mips.AMOVW, 14382 reg: regInfo{ 14383 inputs: []inputInfo{ 14384 {0, 140737555464192}, // SP SB 14385 }, 14386 outputs: []outputInfo{ 14387 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14388 }, 14389 }, 14390 }, 14391 { 14392 name: "MOVBload", 14393 auxType: auxSymOff, 14394 argLen: 2, 14395 faultOnNilArg0: true, 14396 symEffect: SymRead, 14397 asm: mips.AMOVB, 14398 reg: regInfo{ 14399 inputs: []inputInfo{ 14400 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14401 }, 14402 outputs: []outputInfo{ 14403 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14404 }, 14405 }, 14406 }, 14407 { 14408 name: "MOVBUload", 14409 auxType: auxSymOff, 14410 argLen: 2, 14411 faultOnNilArg0: true, 14412 symEffect: SymRead, 14413 asm: mips.AMOVBU, 14414 reg: regInfo{ 14415 inputs: []inputInfo{ 14416 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14417 }, 14418 outputs: []outputInfo{ 14419 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14420 }, 14421 }, 14422 }, 14423 { 14424 name: "MOVHload", 14425 auxType: auxSymOff, 14426 argLen: 2, 14427 faultOnNilArg0: true, 14428 symEffect: SymRead, 14429 asm: mips.AMOVH, 14430 reg: regInfo{ 14431 inputs: []inputInfo{ 14432 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14433 }, 14434 outputs: []outputInfo{ 14435 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14436 }, 14437 }, 14438 }, 14439 { 14440 name: "MOVHUload", 14441 auxType: auxSymOff, 14442 argLen: 2, 14443 faultOnNilArg0: true, 14444 symEffect: SymRead, 14445 asm: mips.AMOVHU, 14446 reg: regInfo{ 14447 inputs: []inputInfo{ 14448 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14449 }, 14450 outputs: []outputInfo{ 14451 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14452 }, 14453 }, 14454 }, 14455 { 14456 name: "MOVWload", 14457 auxType: auxSymOff, 14458 argLen: 2, 14459 faultOnNilArg0: true, 14460 symEffect: SymRead, 14461 asm: mips.AMOVW, 14462 reg: regInfo{ 14463 inputs: []inputInfo{ 14464 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14465 }, 14466 outputs: []outputInfo{ 14467 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14468 }, 14469 }, 14470 }, 14471 { 14472 name: "MOVFload", 14473 auxType: auxSymOff, 14474 argLen: 2, 14475 faultOnNilArg0: true, 14476 symEffect: SymRead, 14477 asm: mips.AMOVF, 14478 reg: regInfo{ 14479 inputs: []inputInfo{ 14480 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14481 }, 14482 outputs: []outputInfo{ 14483 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14484 }, 14485 }, 14486 }, 14487 { 14488 name: "MOVDload", 14489 auxType: auxSymOff, 14490 argLen: 2, 14491 faultOnNilArg0: true, 14492 symEffect: SymRead, 14493 asm: mips.AMOVD, 14494 reg: regInfo{ 14495 inputs: []inputInfo{ 14496 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14497 }, 14498 outputs: []outputInfo{ 14499 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14500 }, 14501 }, 14502 }, 14503 { 14504 name: "MOVBstore", 14505 auxType: auxSymOff, 14506 argLen: 3, 14507 faultOnNilArg0: true, 14508 symEffect: SymWrite, 14509 asm: mips.AMOVB, 14510 reg: regInfo{ 14511 inputs: []inputInfo{ 14512 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14513 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14514 }, 14515 }, 14516 }, 14517 { 14518 name: "MOVHstore", 14519 auxType: auxSymOff, 14520 argLen: 3, 14521 faultOnNilArg0: true, 14522 symEffect: SymWrite, 14523 asm: mips.AMOVH, 14524 reg: regInfo{ 14525 inputs: []inputInfo{ 14526 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14527 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14528 }, 14529 }, 14530 }, 14531 { 14532 name: "MOVWstore", 14533 auxType: auxSymOff, 14534 argLen: 3, 14535 faultOnNilArg0: true, 14536 symEffect: SymWrite, 14537 asm: mips.AMOVW, 14538 reg: regInfo{ 14539 inputs: []inputInfo{ 14540 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14541 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14542 }, 14543 }, 14544 }, 14545 { 14546 name: "MOVFstore", 14547 auxType: auxSymOff, 14548 argLen: 3, 14549 faultOnNilArg0: true, 14550 symEffect: SymWrite, 14551 asm: mips.AMOVF, 14552 reg: regInfo{ 14553 inputs: []inputInfo{ 14554 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14555 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14556 }, 14557 }, 14558 }, 14559 { 14560 name: "MOVDstore", 14561 auxType: auxSymOff, 14562 argLen: 3, 14563 faultOnNilArg0: true, 14564 symEffect: SymWrite, 14565 asm: mips.AMOVD, 14566 reg: regInfo{ 14567 inputs: []inputInfo{ 14568 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14569 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14570 }, 14571 }, 14572 }, 14573 { 14574 name: "MOVBstorezero", 14575 auxType: auxSymOff, 14576 argLen: 2, 14577 faultOnNilArg0: true, 14578 symEffect: SymWrite, 14579 asm: mips.AMOVB, 14580 reg: regInfo{ 14581 inputs: []inputInfo{ 14582 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14583 }, 14584 }, 14585 }, 14586 { 14587 name: "MOVHstorezero", 14588 auxType: auxSymOff, 14589 argLen: 2, 14590 faultOnNilArg0: true, 14591 symEffect: SymWrite, 14592 asm: mips.AMOVH, 14593 reg: regInfo{ 14594 inputs: []inputInfo{ 14595 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14596 }, 14597 }, 14598 }, 14599 { 14600 name: "MOVWstorezero", 14601 auxType: auxSymOff, 14602 argLen: 2, 14603 faultOnNilArg0: true, 14604 symEffect: SymWrite, 14605 asm: mips.AMOVW, 14606 reg: regInfo{ 14607 inputs: []inputInfo{ 14608 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14609 }, 14610 }, 14611 }, 14612 { 14613 name: "MOVBreg", 14614 argLen: 1, 14615 asm: mips.AMOVB, 14616 reg: regInfo{ 14617 inputs: []inputInfo{ 14618 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14619 }, 14620 outputs: []outputInfo{ 14621 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14622 }, 14623 }, 14624 }, 14625 { 14626 name: "MOVBUreg", 14627 argLen: 1, 14628 asm: mips.AMOVBU, 14629 reg: regInfo{ 14630 inputs: []inputInfo{ 14631 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14632 }, 14633 outputs: []outputInfo{ 14634 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14635 }, 14636 }, 14637 }, 14638 { 14639 name: "MOVHreg", 14640 argLen: 1, 14641 asm: mips.AMOVH, 14642 reg: regInfo{ 14643 inputs: []inputInfo{ 14644 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14645 }, 14646 outputs: []outputInfo{ 14647 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14648 }, 14649 }, 14650 }, 14651 { 14652 name: "MOVHUreg", 14653 argLen: 1, 14654 asm: mips.AMOVHU, 14655 reg: regInfo{ 14656 inputs: []inputInfo{ 14657 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14658 }, 14659 outputs: []outputInfo{ 14660 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14661 }, 14662 }, 14663 }, 14664 { 14665 name: "MOVWreg", 14666 argLen: 1, 14667 asm: mips.AMOVW, 14668 reg: regInfo{ 14669 inputs: []inputInfo{ 14670 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14671 }, 14672 outputs: []outputInfo{ 14673 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14674 }, 14675 }, 14676 }, 14677 { 14678 name: "MOVWnop", 14679 argLen: 1, 14680 resultInArg0: true, 14681 reg: regInfo{ 14682 inputs: []inputInfo{ 14683 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14684 }, 14685 outputs: []outputInfo{ 14686 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14687 }, 14688 }, 14689 }, 14690 { 14691 name: "CMOVZ", 14692 argLen: 3, 14693 resultInArg0: true, 14694 asm: mips.ACMOVZ, 14695 reg: regInfo{ 14696 inputs: []inputInfo{ 14697 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14698 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14699 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14700 }, 14701 outputs: []outputInfo{ 14702 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14703 }, 14704 }, 14705 }, 14706 { 14707 name: "CMOVZzero", 14708 argLen: 2, 14709 resultInArg0: true, 14710 asm: mips.ACMOVZ, 14711 reg: regInfo{ 14712 inputs: []inputInfo{ 14713 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14714 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14715 }, 14716 outputs: []outputInfo{ 14717 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14718 }, 14719 }, 14720 }, 14721 { 14722 name: "MOVWF", 14723 argLen: 1, 14724 asm: mips.AMOVWF, 14725 reg: regInfo{ 14726 inputs: []inputInfo{ 14727 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14728 }, 14729 outputs: []outputInfo{ 14730 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14731 }, 14732 }, 14733 }, 14734 { 14735 name: "MOVWD", 14736 argLen: 1, 14737 asm: mips.AMOVWD, 14738 reg: regInfo{ 14739 inputs: []inputInfo{ 14740 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14741 }, 14742 outputs: []outputInfo{ 14743 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14744 }, 14745 }, 14746 }, 14747 { 14748 name: "TRUNCFW", 14749 argLen: 1, 14750 asm: mips.ATRUNCFW, 14751 reg: regInfo{ 14752 inputs: []inputInfo{ 14753 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14754 }, 14755 outputs: []outputInfo{ 14756 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14757 }, 14758 }, 14759 }, 14760 { 14761 name: "TRUNCDW", 14762 argLen: 1, 14763 asm: mips.ATRUNCDW, 14764 reg: regInfo{ 14765 inputs: []inputInfo{ 14766 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14767 }, 14768 outputs: []outputInfo{ 14769 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14770 }, 14771 }, 14772 }, 14773 { 14774 name: "MOVFD", 14775 argLen: 1, 14776 asm: mips.AMOVFD, 14777 reg: regInfo{ 14778 inputs: []inputInfo{ 14779 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14780 }, 14781 outputs: []outputInfo{ 14782 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14783 }, 14784 }, 14785 }, 14786 { 14787 name: "MOVDF", 14788 argLen: 1, 14789 asm: mips.AMOVDF, 14790 reg: regInfo{ 14791 inputs: []inputInfo{ 14792 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14793 }, 14794 outputs: []outputInfo{ 14795 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14796 }, 14797 }, 14798 }, 14799 { 14800 name: "CALLstatic", 14801 auxType: auxSymOff, 14802 argLen: 1, 14803 clobberFlags: true, 14804 call: true, 14805 symEffect: SymNone, 14806 reg: regInfo{ 14807 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14808 }, 14809 }, 14810 { 14811 name: "CALLclosure", 14812 auxType: auxInt64, 14813 argLen: 3, 14814 clobberFlags: true, 14815 call: true, 14816 reg: regInfo{ 14817 inputs: []inputInfo{ 14818 {1, 4194304}, // R22 14819 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 14820 }, 14821 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14822 }, 14823 }, 14824 { 14825 name: "CALLinter", 14826 auxType: auxInt64, 14827 argLen: 2, 14828 clobberFlags: true, 14829 call: true, 14830 reg: regInfo{ 14831 inputs: []inputInfo{ 14832 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14833 }, 14834 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14835 }, 14836 }, 14837 { 14838 name: "LoweredAtomicLoad", 14839 argLen: 2, 14840 faultOnNilArg0: true, 14841 reg: regInfo{ 14842 inputs: []inputInfo{ 14843 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14844 }, 14845 outputs: []outputInfo{ 14846 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14847 }, 14848 }, 14849 }, 14850 { 14851 name: "LoweredAtomicStore", 14852 argLen: 3, 14853 faultOnNilArg0: true, 14854 hasSideEffects: true, 14855 reg: regInfo{ 14856 inputs: []inputInfo{ 14857 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14858 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14859 }, 14860 }, 14861 }, 14862 { 14863 name: "LoweredAtomicStorezero", 14864 argLen: 2, 14865 faultOnNilArg0: true, 14866 hasSideEffects: true, 14867 reg: regInfo{ 14868 inputs: []inputInfo{ 14869 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14870 }, 14871 }, 14872 }, 14873 { 14874 name: "LoweredAtomicExchange", 14875 argLen: 3, 14876 resultNotInArgs: true, 14877 faultOnNilArg0: true, 14878 hasSideEffects: true, 14879 reg: regInfo{ 14880 inputs: []inputInfo{ 14881 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14882 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14883 }, 14884 outputs: []outputInfo{ 14885 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14886 }, 14887 }, 14888 }, 14889 { 14890 name: "LoweredAtomicAdd", 14891 argLen: 3, 14892 resultNotInArgs: true, 14893 faultOnNilArg0: true, 14894 hasSideEffects: true, 14895 reg: regInfo{ 14896 inputs: []inputInfo{ 14897 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14898 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14899 }, 14900 outputs: []outputInfo{ 14901 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14902 }, 14903 }, 14904 }, 14905 { 14906 name: "LoweredAtomicAddconst", 14907 auxType: auxInt32, 14908 argLen: 2, 14909 resultNotInArgs: true, 14910 faultOnNilArg0: true, 14911 hasSideEffects: true, 14912 reg: regInfo{ 14913 inputs: []inputInfo{ 14914 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14915 }, 14916 outputs: []outputInfo{ 14917 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14918 }, 14919 }, 14920 }, 14921 { 14922 name: "LoweredAtomicCas", 14923 argLen: 4, 14924 resultNotInArgs: true, 14925 faultOnNilArg0: true, 14926 hasSideEffects: true, 14927 reg: regInfo{ 14928 inputs: []inputInfo{ 14929 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14930 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14931 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14932 }, 14933 outputs: []outputInfo{ 14934 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14935 }, 14936 }, 14937 }, 14938 { 14939 name: "LoweredAtomicAnd", 14940 argLen: 3, 14941 faultOnNilArg0: true, 14942 hasSideEffects: true, 14943 asm: mips.AAND, 14944 reg: regInfo{ 14945 inputs: []inputInfo{ 14946 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14947 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14948 }, 14949 }, 14950 }, 14951 { 14952 name: "LoweredAtomicOr", 14953 argLen: 3, 14954 faultOnNilArg0: true, 14955 hasSideEffects: true, 14956 asm: mips.AOR, 14957 reg: regInfo{ 14958 inputs: []inputInfo{ 14959 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14960 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14961 }, 14962 }, 14963 }, 14964 { 14965 name: "LoweredZero", 14966 auxType: auxInt32, 14967 argLen: 3, 14968 faultOnNilArg0: true, 14969 reg: regInfo{ 14970 inputs: []inputInfo{ 14971 {0, 2}, // R1 14972 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14973 }, 14974 clobbers: 2, // R1 14975 }, 14976 }, 14977 { 14978 name: "LoweredMove", 14979 auxType: auxInt32, 14980 argLen: 4, 14981 faultOnNilArg0: true, 14982 faultOnNilArg1: true, 14983 reg: regInfo{ 14984 inputs: []inputInfo{ 14985 {0, 4}, // R2 14986 {1, 2}, // R1 14987 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14988 }, 14989 clobbers: 6, // R1 R2 14990 }, 14991 }, 14992 { 14993 name: "LoweredNilCheck", 14994 argLen: 2, 14995 nilCheck: true, 14996 faultOnNilArg0: true, 14997 reg: regInfo{ 14998 inputs: []inputInfo{ 14999 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15000 }, 15001 }, 15002 }, 15003 { 15004 name: "FPFlagTrue", 15005 argLen: 1, 15006 reg: regInfo{ 15007 outputs: []outputInfo{ 15008 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15009 }, 15010 }, 15011 }, 15012 { 15013 name: "FPFlagFalse", 15014 argLen: 1, 15015 reg: regInfo{ 15016 outputs: []outputInfo{ 15017 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15018 }, 15019 }, 15020 }, 15021 { 15022 name: "LoweredGetClosurePtr", 15023 argLen: 0, 15024 reg: regInfo{ 15025 outputs: []outputInfo{ 15026 {0, 4194304}, // R22 15027 }, 15028 }, 15029 }, 15030 { 15031 name: "MOVWconvert", 15032 argLen: 2, 15033 asm: mips.AMOVW, 15034 reg: regInfo{ 15035 inputs: []inputInfo{ 15036 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15037 }, 15038 outputs: []outputInfo{ 15039 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15040 }, 15041 }, 15042 }, 15043 15044 { 15045 name: "ADDV", 15046 argLen: 2, 15047 commutative: true, 15048 asm: mips.AADDVU, 15049 reg: regInfo{ 15050 inputs: []inputInfo{ 15051 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15052 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15053 }, 15054 outputs: []outputInfo{ 15055 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15056 }, 15057 }, 15058 }, 15059 { 15060 name: "ADDVconst", 15061 auxType: auxInt64, 15062 argLen: 1, 15063 asm: mips.AADDVU, 15064 reg: regInfo{ 15065 inputs: []inputInfo{ 15066 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 15067 }, 15068 outputs: []outputInfo{ 15069 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15070 }, 15071 }, 15072 }, 15073 { 15074 name: "SUBV", 15075 argLen: 2, 15076 asm: mips.ASUBVU, 15077 reg: regInfo{ 15078 inputs: []inputInfo{ 15079 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15080 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15081 }, 15082 outputs: []outputInfo{ 15083 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15084 }, 15085 }, 15086 }, 15087 { 15088 name: "SUBVconst", 15089 auxType: auxInt64, 15090 argLen: 1, 15091 asm: mips.ASUBVU, 15092 reg: regInfo{ 15093 inputs: []inputInfo{ 15094 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15095 }, 15096 outputs: []outputInfo{ 15097 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15098 }, 15099 }, 15100 }, 15101 { 15102 name: "MULV", 15103 argLen: 2, 15104 commutative: true, 15105 asm: mips.AMULV, 15106 reg: regInfo{ 15107 inputs: []inputInfo{ 15108 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15109 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15110 }, 15111 outputs: []outputInfo{ 15112 {0, 1152921504606846976}, // HI 15113 {1, 2305843009213693952}, // LO 15114 }, 15115 }, 15116 }, 15117 { 15118 name: "MULVU", 15119 argLen: 2, 15120 commutative: true, 15121 asm: mips.AMULVU, 15122 reg: regInfo{ 15123 inputs: []inputInfo{ 15124 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15125 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15126 }, 15127 outputs: []outputInfo{ 15128 {0, 1152921504606846976}, // HI 15129 {1, 2305843009213693952}, // LO 15130 }, 15131 }, 15132 }, 15133 { 15134 name: "DIVV", 15135 argLen: 2, 15136 asm: mips.ADIVV, 15137 reg: regInfo{ 15138 inputs: []inputInfo{ 15139 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15140 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15141 }, 15142 outputs: []outputInfo{ 15143 {0, 1152921504606846976}, // HI 15144 {1, 2305843009213693952}, // LO 15145 }, 15146 }, 15147 }, 15148 { 15149 name: "DIVVU", 15150 argLen: 2, 15151 asm: mips.ADIVVU, 15152 reg: regInfo{ 15153 inputs: []inputInfo{ 15154 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15155 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15156 }, 15157 outputs: []outputInfo{ 15158 {0, 1152921504606846976}, // HI 15159 {1, 2305843009213693952}, // LO 15160 }, 15161 }, 15162 }, 15163 { 15164 name: "ADDF", 15165 argLen: 2, 15166 commutative: true, 15167 asm: mips.AADDF, 15168 reg: regInfo{ 15169 inputs: []inputInfo{ 15170 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15171 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15172 }, 15173 outputs: []outputInfo{ 15174 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15175 }, 15176 }, 15177 }, 15178 { 15179 name: "ADDD", 15180 argLen: 2, 15181 commutative: true, 15182 asm: mips.AADDD, 15183 reg: regInfo{ 15184 inputs: []inputInfo{ 15185 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15186 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15187 }, 15188 outputs: []outputInfo{ 15189 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15190 }, 15191 }, 15192 }, 15193 { 15194 name: "SUBF", 15195 argLen: 2, 15196 asm: mips.ASUBF, 15197 reg: regInfo{ 15198 inputs: []inputInfo{ 15199 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15200 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15201 }, 15202 outputs: []outputInfo{ 15203 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15204 }, 15205 }, 15206 }, 15207 { 15208 name: "SUBD", 15209 argLen: 2, 15210 asm: mips.ASUBD, 15211 reg: regInfo{ 15212 inputs: []inputInfo{ 15213 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15214 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15215 }, 15216 outputs: []outputInfo{ 15217 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15218 }, 15219 }, 15220 }, 15221 { 15222 name: "MULF", 15223 argLen: 2, 15224 commutative: true, 15225 asm: mips.AMULF, 15226 reg: regInfo{ 15227 inputs: []inputInfo{ 15228 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15229 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15230 }, 15231 outputs: []outputInfo{ 15232 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15233 }, 15234 }, 15235 }, 15236 { 15237 name: "MULD", 15238 argLen: 2, 15239 commutative: true, 15240 asm: mips.AMULD, 15241 reg: regInfo{ 15242 inputs: []inputInfo{ 15243 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15244 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15245 }, 15246 outputs: []outputInfo{ 15247 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15248 }, 15249 }, 15250 }, 15251 { 15252 name: "DIVF", 15253 argLen: 2, 15254 asm: mips.ADIVF, 15255 reg: regInfo{ 15256 inputs: []inputInfo{ 15257 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15258 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15259 }, 15260 outputs: []outputInfo{ 15261 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15262 }, 15263 }, 15264 }, 15265 { 15266 name: "DIVD", 15267 argLen: 2, 15268 asm: mips.ADIVD, 15269 reg: regInfo{ 15270 inputs: []inputInfo{ 15271 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15272 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15273 }, 15274 outputs: []outputInfo{ 15275 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15276 }, 15277 }, 15278 }, 15279 { 15280 name: "AND", 15281 argLen: 2, 15282 commutative: true, 15283 asm: mips.AAND, 15284 reg: regInfo{ 15285 inputs: []inputInfo{ 15286 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15287 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15288 }, 15289 outputs: []outputInfo{ 15290 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15291 }, 15292 }, 15293 }, 15294 { 15295 name: "ANDconst", 15296 auxType: auxInt64, 15297 argLen: 1, 15298 asm: mips.AAND, 15299 reg: regInfo{ 15300 inputs: []inputInfo{ 15301 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15302 }, 15303 outputs: []outputInfo{ 15304 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15305 }, 15306 }, 15307 }, 15308 { 15309 name: "OR", 15310 argLen: 2, 15311 commutative: true, 15312 asm: mips.AOR, 15313 reg: regInfo{ 15314 inputs: []inputInfo{ 15315 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15316 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15317 }, 15318 outputs: []outputInfo{ 15319 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15320 }, 15321 }, 15322 }, 15323 { 15324 name: "ORconst", 15325 auxType: auxInt64, 15326 argLen: 1, 15327 asm: mips.AOR, 15328 reg: regInfo{ 15329 inputs: []inputInfo{ 15330 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15331 }, 15332 outputs: []outputInfo{ 15333 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15334 }, 15335 }, 15336 }, 15337 { 15338 name: "XOR", 15339 argLen: 2, 15340 commutative: true, 15341 asm: mips.AXOR, 15342 reg: regInfo{ 15343 inputs: []inputInfo{ 15344 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15345 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15346 }, 15347 outputs: []outputInfo{ 15348 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15349 }, 15350 }, 15351 }, 15352 { 15353 name: "XORconst", 15354 auxType: auxInt64, 15355 argLen: 1, 15356 asm: mips.AXOR, 15357 reg: regInfo{ 15358 inputs: []inputInfo{ 15359 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15360 }, 15361 outputs: []outputInfo{ 15362 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15363 }, 15364 }, 15365 }, 15366 { 15367 name: "NOR", 15368 argLen: 2, 15369 commutative: true, 15370 asm: mips.ANOR, 15371 reg: regInfo{ 15372 inputs: []inputInfo{ 15373 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15374 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15375 }, 15376 outputs: []outputInfo{ 15377 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15378 }, 15379 }, 15380 }, 15381 { 15382 name: "NORconst", 15383 auxType: auxInt64, 15384 argLen: 1, 15385 asm: mips.ANOR, 15386 reg: regInfo{ 15387 inputs: []inputInfo{ 15388 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15389 }, 15390 outputs: []outputInfo{ 15391 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15392 }, 15393 }, 15394 }, 15395 { 15396 name: "NEGV", 15397 argLen: 1, 15398 reg: regInfo{ 15399 inputs: []inputInfo{ 15400 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15401 }, 15402 outputs: []outputInfo{ 15403 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15404 }, 15405 }, 15406 }, 15407 { 15408 name: "NEGF", 15409 argLen: 1, 15410 asm: mips.ANEGF, 15411 reg: regInfo{ 15412 inputs: []inputInfo{ 15413 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15414 }, 15415 outputs: []outputInfo{ 15416 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15417 }, 15418 }, 15419 }, 15420 { 15421 name: "NEGD", 15422 argLen: 1, 15423 asm: mips.ANEGD, 15424 reg: regInfo{ 15425 inputs: []inputInfo{ 15426 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15427 }, 15428 outputs: []outputInfo{ 15429 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15430 }, 15431 }, 15432 }, 15433 { 15434 name: "SLLV", 15435 argLen: 2, 15436 asm: mips.ASLLV, 15437 reg: regInfo{ 15438 inputs: []inputInfo{ 15439 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15440 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15441 }, 15442 outputs: []outputInfo{ 15443 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15444 }, 15445 }, 15446 }, 15447 { 15448 name: "SLLVconst", 15449 auxType: auxInt64, 15450 argLen: 1, 15451 asm: mips.ASLLV, 15452 reg: regInfo{ 15453 inputs: []inputInfo{ 15454 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15455 }, 15456 outputs: []outputInfo{ 15457 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15458 }, 15459 }, 15460 }, 15461 { 15462 name: "SRLV", 15463 argLen: 2, 15464 asm: mips.ASRLV, 15465 reg: regInfo{ 15466 inputs: []inputInfo{ 15467 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15468 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15469 }, 15470 outputs: []outputInfo{ 15471 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15472 }, 15473 }, 15474 }, 15475 { 15476 name: "SRLVconst", 15477 auxType: auxInt64, 15478 argLen: 1, 15479 asm: mips.ASRLV, 15480 reg: regInfo{ 15481 inputs: []inputInfo{ 15482 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15483 }, 15484 outputs: []outputInfo{ 15485 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15486 }, 15487 }, 15488 }, 15489 { 15490 name: "SRAV", 15491 argLen: 2, 15492 asm: mips.ASRAV, 15493 reg: regInfo{ 15494 inputs: []inputInfo{ 15495 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15496 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15497 }, 15498 outputs: []outputInfo{ 15499 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15500 }, 15501 }, 15502 }, 15503 { 15504 name: "SRAVconst", 15505 auxType: auxInt64, 15506 argLen: 1, 15507 asm: mips.ASRAV, 15508 reg: regInfo{ 15509 inputs: []inputInfo{ 15510 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15511 }, 15512 outputs: []outputInfo{ 15513 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15514 }, 15515 }, 15516 }, 15517 { 15518 name: "SGT", 15519 argLen: 2, 15520 asm: mips.ASGT, 15521 reg: regInfo{ 15522 inputs: []inputInfo{ 15523 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15524 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15525 }, 15526 outputs: []outputInfo{ 15527 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15528 }, 15529 }, 15530 }, 15531 { 15532 name: "SGTconst", 15533 auxType: auxInt64, 15534 argLen: 1, 15535 asm: mips.ASGT, 15536 reg: regInfo{ 15537 inputs: []inputInfo{ 15538 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15539 }, 15540 outputs: []outputInfo{ 15541 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15542 }, 15543 }, 15544 }, 15545 { 15546 name: "SGTU", 15547 argLen: 2, 15548 asm: mips.ASGTU, 15549 reg: regInfo{ 15550 inputs: []inputInfo{ 15551 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15552 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15553 }, 15554 outputs: []outputInfo{ 15555 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15556 }, 15557 }, 15558 }, 15559 { 15560 name: "SGTUconst", 15561 auxType: auxInt64, 15562 argLen: 1, 15563 asm: mips.ASGTU, 15564 reg: regInfo{ 15565 inputs: []inputInfo{ 15566 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15567 }, 15568 outputs: []outputInfo{ 15569 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15570 }, 15571 }, 15572 }, 15573 { 15574 name: "CMPEQF", 15575 argLen: 2, 15576 asm: mips.ACMPEQF, 15577 reg: regInfo{ 15578 inputs: []inputInfo{ 15579 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15580 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15581 }, 15582 }, 15583 }, 15584 { 15585 name: "CMPEQD", 15586 argLen: 2, 15587 asm: mips.ACMPEQD, 15588 reg: regInfo{ 15589 inputs: []inputInfo{ 15590 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15591 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15592 }, 15593 }, 15594 }, 15595 { 15596 name: "CMPGEF", 15597 argLen: 2, 15598 asm: mips.ACMPGEF, 15599 reg: regInfo{ 15600 inputs: []inputInfo{ 15601 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15602 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15603 }, 15604 }, 15605 }, 15606 { 15607 name: "CMPGED", 15608 argLen: 2, 15609 asm: mips.ACMPGED, 15610 reg: regInfo{ 15611 inputs: []inputInfo{ 15612 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15613 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15614 }, 15615 }, 15616 }, 15617 { 15618 name: "CMPGTF", 15619 argLen: 2, 15620 asm: mips.ACMPGTF, 15621 reg: regInfo{ 15622 inputs: []inputInfo{ 15623 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15624 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15625 }, 15626 }, 15627 }, 15628 { 15629 name: "CMPGTD", 15630 argLen: 2, 15631 asm: mips.ACMPGTD, 15632 reg: regInfo{ 15633 inputs: []inputInfo{ 15634 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15635 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15636 }, 15637 }, 15638 }, 15639 { 15640 name: "MOVVconst", 15641 auxType: auxInt64, 15642 argLen: 0, 15643 rematerializeable: true, 15644 asm: mips.AMOVV, 15645 reg: regInfo{ 15646 outputs: []outputInfo{ 15647 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15648 }, 15649 }, 15650 }, 15651 { 15652 name: "MOVFconst", 15653 auxType: auxFloat64, 15654 argLen: 0, 15655 rematerializeable: true, 15656 asm: mips.AMOVF, 15657 reg: regInfo{ 15658 outputs: []outputInfo{ 15659 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15660 }, 15661 }, 15662 }, 15663 { 15664 name: "MOVDconst", 15665 auxType: auxFloat64, 15666 argLen: 0, 15667 rematerializeable: true, 15668 asm: mips.AMOVD, 15669 reg: regInfo{ 15670 outputs: []outputInfo{ 15671 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15672 }, 15673 }, 15674 }, 15675 { 15676 name: "MOVVaddr", 15677 auxType: auxSymOff, 15678 argLen: 1, 15679 rematerializeable: true, 15680 symEffect: SymAddr, 15681 asm: mips.AMOVV, 15682 reg: regInfo{ 15683 inputs: []inputInfo{ 15684 {0, 4611686018460942336}, // SP SB 15685 }, 15686 outputs: []outputInfo{ 15687 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15688 }, 15689 }, 15690 }, 15691 { 15692 name: "MOVBload", 15693 auxType: auxSymOff, 15694 argLen: 2, 15695 faultOnNilArg0: true, 15696 symEffect: SymRead, 15697 asm: mips.AMOVB, 15698 reg: regInfo{ 15699 inputs: []inputInfo{ 15700 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15701 }, 15702 outputs: []outputInfo{ 15703 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15704 }, 15705 }, 15706 }, 15707 { 15708 name: "MOVBUload", 15709 auxType: auxSymOff, 15710 argLen: 2, 15711 faultOnNilArg0: true, 15712 symEffect: SymRead, 15713 asm: mips.AMOVBU, 15714 reg: regInfo{ 15715 inputs: []inputInfo{ 15716 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15717 }, 15718 outputs: []outputInfo{ 15719 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15720 }, 15721 }, 15722 }, 15723 { 15724 name: "MOVHload", 15725 auxType: auxSymOff, 15726 argLen: 2, 15727 faultOnNilArg0: true, 15728 symEffect: SymRead, 15729 asm: mips.AMOVH, 15730 reg: regInfo{ 15731 inputs: []inputInfo{ 15732 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15733 }, 15734 outputs: []outputInfo{ 15735 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15736 }, 15737 }, 15738 }, 15739 { 15740 name: "MOVHUload", 15741 auxType: auxSymOff, 15742 argLen: 2, 15743 faultOnNilArg0: true, 15744 symEffect: SymRead, 15745 asm: mips.AMOVHU, 15746 reg: regInfo{ 15747 inputs: []inputInfo{ 15748 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15749 }, 15750 outputs: []outputInfo{ 15751 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15752 }, 15753 }, 15754 }, 15755 { 15756 name: "MOVWload", 15757 auxType: auxSymOff, 15758 argLen: 2, 15759 faultOnNilArg0: true, 15760 symEffect: SymRead, 15761 asm: mips.AMOVW, 15762 reg: regInfo{ 15763 inputs: []inputInfo{ 15764 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15765 }, 15766 outputs: []outputInfo{ 15767 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15768 }, 15769 }, 15770 }, 15771 { 15772 name: "MOVWUload", 15773 auxType: auxSymOff, 15774 argLen: 2, 15775 faultOnNilArg0: true, 15776 symEffect: SymRead, 15777 asm: mips.AMOVWU, 15778 reg: regInfo{ 15779 inputs: []inputInfo{ 15780 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15781 }, 15782 outputs: []outputInfo{ 15783 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15784 }, 15785 }, 15786 }, 15787 { 15788 name: "MOVVload", 15789 auxType: auxSymOff, 15790 argLen: 2, 15791 faultOnNilArg0: true, 15792 symEffect: SymRead, 15793 asm: mips.AMOVV, 15794 reg: regInfo{ 15795 inputs: []inputInfo{ 15796 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15797 }, 15798 outputs: []outputInfo{ 15799 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15800 }, 15801 }, 15802 }, 15803 { 15804 name: "MOVFload", 15805 auxType: auxSymOff, 15806 argLen: 2, 15807 faultOnNilArg0: true, 15808 symEffect: SymRead, 15809 asm: mips.AMOVF, 15810 reg: regInfo{ 15811 inputs: []inputInfo{ 15812 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15813 }, 15814 outputs: []outputInfo{ 15815 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15816 }, 15817 }, 15818 }, 15819 { 15820 name: "MOVDload", 15821 auxType: auxSymOff, 15822 argLen: 2, 15823 faultOnNilArg0: true, 15824 symEffect: SymRead, 15825 asm: mips.AMOVD, 15826 reg: regInfo{ 15827 inputs: []inputInfo{ 15828 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15829 }, 15830 outputs: []outputInfo{ 15831 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15832 }, 15833 }, 15834 }, 15835 { 15836 name: "MOVBstore", 15837 auxType: auxSymOff, 15838 argLen: 3, 15839 faultOnNilArg0: true, 15840 symEffect: SymWrite, 15841 asm: mips.AMOVB, 15842 reg: regInfo{ 15843 inputs: []inputInfo{ 15844 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15845 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15846 }, 15847 }, 15848 }, 15849 { 15850 name: "MOVHstore", 15851 auxType: auxSymOff, 15852 argLen: 3, 15853 faultOnNilArg0: true, 15854 symEffect: SymWrite, 15855 asm: mips.AMOVH, 15856 reg: regInfo{ 15857 inputs: []inputInfo{ 15858 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15859 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15860 }, 15861 }, 15862 }, 15863 { 15864 name: "MOVWstore", 15865 auxType: auxSymOff, 15866 argLen: 3, 15867 faultOnNilArg0: true, 15868 symEffect: SymWrite, 15869 asm: mips.AMOVW, 15870 reg: regInfo{ 15871 inputs: []inputInfo{ 15872 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15873 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15874 }, 15875 }, 15876 }, 15877 { 15878 name: "MOVVstore", 15879 auxType: auxSymOff, 15880 argLen: 3, 15881 faultOnNilArg0: true, 15882 symEffect: SymWrite, 15883 asm: mips.AMOVV, 15884 reg: regInfo{ 15885 inputs: []inputInfo{ 15886 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15887 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15888 }, 15889 }, 15890 }, 15891 { 15892 name: "MOVFstore", 15893 auxType: auxSymOff, 15894 argLen: 3, 15895 faultOnNilArg0: true, 15896 symEffect: SymWrite, 15897 asm: mips.AMOVF, 15898 reg: regInfo{ 15899 inputs: []inputInfo{ 15900 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15901 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15902 }, 15903 }, 15904 }, 15905 { 15906 name: "MOVDstore", 15907 auxType: auxSymOff, 15908 argLen: 3, 15909 faultOnNilArg0: true, 15910 symEffect: SymWrite, 15911 asm: mips.AMOVD, 15912 reg: regInfo{ 15913 inputs: []inputInfo{ 15914 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15915 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15916 }, 15917 }, 15918 }, 15919 { 15920 name: "MOVBstorezero", 15921 auxType: auxSymOff, 15922 argLen: 2, 15923 faultOnNilArg0: true, 15924 symEffect: SymWrite, 15925 asm: mips.AMOVB, 15926 reg: regInfo{ 15927 inputs: []inputInfo{ 15928 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15929 }, 15930 }, 15931 }, 15932 { 15933 name: "MOVHstorezero", 15934 auxType: auxSymOff, 15935 argLen: 2, 15936 faultOnNilArg0: true, 15937 symEffect: SymWrite, 15938 asm: mips.AMOVH, 15939 reg: regInfo{ 15940 inputs: []inputInfo{ 15941 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15942 }, 15943 }, 15944 }, 15945 { 15946 name: "MOVWstorezero", 15947 auxType: auxSymOff, 15948 argLen: 2, 15949 faultOnNilArg0: true, 15950 symEffect: SymWrite, 15951 asm: mips.AMOVW, 15952 reg: regInfo{ 15953 inputs: []inputInfo{ 15954 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15955 }, 15956 }, 15957 }, 15958 { 15959 name: "MOVVstorezero", 15960 auxType: auxSymOff, 15961 argLen: 2, 15962 faultOnNilArg0: true, 15963 symEffect: SymWrite, 15964 asm: mips.AMOVV, 15965 reg: regInfo{ 15966 inputs: []inputInfo{ 15967 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15968 }, 15969 }, 15970 }, 15971 { 15972 name: "MOVBreg", 15973 argLen: 1, 15974 asm: mips.AMOVB, 15975 reg: regInfo{ 15976 inputs: []inputInfo{ 15977 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15978 }, 15979 outputs: []outputInfo{ 15980 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15981 }, 15982 }, 15983 }, 15984 { 15985 name: "MOVBUreg", 15986 argLen: 1, 15987 asm: mips.AMOVBU, 15988 reg: regInfo{ 15989 inputs: []inputInfo{ 15990 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15991 }, 15992 outputs: []outputInfo{ 15993 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15994 }, 15995 }, 15996 }, 15997 { 15998 name: "MOVHreg", 15999 argLen: 1, 16000 asm: mips.AMOVH, 16001 reg: regInfo{ 16002 inputs: []inputInfo{ 16003 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16004 }, 16005 outputs: []outputInfo{ 16006 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16007 }, 16008 }, 16009 }, 16010 { 16011 name: "MOVHUreg", 16012 argLen: 1, 16013 asm: mips.AMOVHU, 16014 reg: regInfo{ 16015 inputs: []inputInfo{ 16016 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16017 }, 16018 outputs: []outputInfo{ 16019 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16020 }, 16021 }, 16022 }, 16023 { 16024 name: "MOVWreg", 16025 argLen: 1, 16026 asm: mips.AMOVW, 16027 reg: regInfo{ 16028 inputs: []inputInfo{ 16029 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16030 }, 16031 outputs: []outputInfo{ 16032 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16033 }, 16034 }, 16035 }, 16036 { 16037 name: "MOVWUreg", 16038 argLen: 1, 16039 asm: mips.AMOVWU, 16040 reg: regInfo{ 16041 inputs: []inputInfo{ 16042 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16043 }, 16044 outputs: []outputInfo{ 16045 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16046 }, 16047 }, 16048 }, 16049 { 16050 name: "MOVVreg", 16051 argLen: 1, 16052 asm: mips.AMOVV, 16053 reg: regInfo{ 16054 inputs: []inputInfo{ 16055 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16056 }, 16057 outputs: []outputInfo{ 16058 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16059 }, 16060 }, 16061 }, 16062 { 16063 name: "MOVVnop", 16064 argLen: 1, 16065 resultInArg0: true, 16066 reg: regInfo{ 16067 inputs: []inputInfo{ 16068 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16069 }, 16070 outputs: []outputInfo{ 16071 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16072 }, 16073 }, 16074 }, 16075 { 16076 name: "MOVWF", 16077 argLen: 1, 16078 asm: mips.AMOVWF, 16079 reg: regInfo{ 16080 inputs: []inputInfo{ 16081 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16082 }, 16083 outputs: []outputInfo{ 16084 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16085 }, 16086 }, 16087 }, 16088 { 16089 name: "MOVWD", 16090 argLen: 1, 16091 asm: mips.AMOVWD, 16092 reg: regInfo{ 16093 inputs: []inputInfo{ 16094 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16095 }, 16096 outputs: []outputInfo{ 16097 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16098 }, 16099 }, 16100 }, 16101 { 16102 name: "MOVVF", 16103 argLen: 1, 16104 asm: mips.AMOVVF, 16105 reg: regInfo{ 16106 inputs: []inputInfo{ 16107 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16108 }, 16109 outputs: []outputInfo{ 16110 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16111 }, 16112 }, 16113 }, 16114 { 16115 name: "MOVVD", 16116 argLen: 1, 16117 asm: mips.AMOVVD, 16118 reg: regInfo{ 16119 inputs: []inputInfo{ 16120 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16121 }, 16122 outputs: []outputInfo{ 16123 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16124 }, 16125 }, 16126 }, 16127 { 16128 name: "TRUNCFW", 16129 argLen: 1, 16130 asm: mips.ATRUNCFW, 16131 reg: regInfo{ 16132 inputs: []inputInfo{ 16133 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16134 }, 16135 outputs: []outputInfo{ 16136 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16137 }, 16138 }, 16139 }, 16140 { 16141 name: "TRUNCDW", 16142 argLen: 1, 16143 asm: mips.ATRUNCDW, 16144 reg: regInfo{ 16145 inputs: []inputInfo{ 16146 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16147 }, 16148 outputs: []outputInfo{ 16149 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16150 }, 16151 }, 16152 }, 16153 { 16154 name: "TRUNCFV", 16155 argLen: 1, 16156 asm: mips.ATRUNCFV, 16157 reg: regInfo{ 16158 inputs: []inputInfo{ 16159 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16160 }, 16161 outputs: []outputInfo{ 16162 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16163 }, 16164 }, 16165 }, 16166 { 16167 name: "TRUNCDV", 16168 argLen: 1, 16169 asm: mips.ATRUNCDV, 16170 reg: regInfo{ 16171 inputs: []inputInfo{ 16172 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16173 }, 16174 outputs: []outputInfo{ 16175 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16176 }, 16177 }, 16178 }, 16179 { 16180 name: "MOVFD", 16181 argLen: 1, 16182 asm: mips.AMOVFD, 16183 reg: regInfo{ 16184 inputs: []inputInfo{ 16185 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16186 }, 16187 outputs: []outputInfo{ 16188 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16189 }, 16190 }, 16191 }, 16192 { 16193 name: "MOVDF", 16194 argLen: 1, 16195 asm: mips.AMOVDF, 16196 reg: regInfo{ 16197 inputs: []inputInfo{ 16198 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16199 }, 16200 outputs: []outputInfo{ 16201 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16202 }, 16203 }, 16204 }, 16205 { 16206 name: "CALLstatic", 16207 auxType: auxSymOff, 16208 argLen: 1, 16209 clobberFlags: true, 16210 call: true, 16211 symEffect: SymNone, 16212 reg: regInfo{ 16213 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 16214 }, 16215 }, 16216 { 16217 name: "CALLclosure", 16218 auxType: auxInt64, 16219 argLen: 3, 16220 clobberFlags: true, 16221 call: true, 16222 reg: regInfo{ 16223 inputs: []inputInfo{ 16224 {1, 4194304}, // R22 16225 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 16226 }, 16227 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 16228 }, 16229 }, 16230 { 16231 name: "CALLinter", 16232 auxType: auxInt64, 16233 argLen: 2, 16234 clobberFlags: true, 16235 call: true, 16236 reg: regInfo{ 16237 inputs: []inputInfo{ 16238 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16239 }, 16240 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 16241 }, 16242 }, 16243 { 16244 name: "DUFFZERO", 16245 auxType: auxInt64, 16246 argLen: 2, 16247 faultOnNilArg0: true, 16248 reg: regInfo{ 16249 inputs: []inputInfo{ 16250 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16251 }, 16252 clobbers: 134217730, // R1 R31 16253 }, 16254 }, 16255 { 16256 name: "LoweredZero", 16257 auxType: auxInt64, 16258 argLen: 3, 16259 clobberFlags: true, 16260 faultOnNilArg0: true, 16261 reg: regInfo{ 16262 inputs: []inputInfo{ 16263 {0, 2}, // R1 16264 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16265 }, 16266 clobbers: 2, // R1 16267 }, 16268 }, 16269 { 16270 name: "LoweredMove", 16271 auxType: auxInt64, 16272 argLen: 4, 16273 clobberFlags: true, 16274 faultOnNilArg0: true, 16275 faultOnNilArg1: true, 16276 reg: regInfo{ 16277 inputs: []inputInfo{ 16278 {0, 4}, // R2 16279 {1, 2}, // R1 16280 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16281 }, 16282 clobbers: 6, // R1 R2 16283 }, 16284 }, 16285 { 16286 name: "LoweredNilCheck", 16287 argLen: 2, 16288 nilCheck: true, 16289 faultOnNilArg0: true, 16290 reg: regInfo{ 16291 inputs: []inputInfo{ 16292 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16293 }, 16294 }, 16295 }, 16296 { 16297 name: "FPFlagTrue", 16298 argLen: 1, 16299 reg: regInfo{ 16300 outputs: []outputInfo{ 16301 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16302 }, 16303 }, 16304 }, 16305 { 16306 name: "FPFlagFalse", 16307 argLen: 1, 16308 reg: regInfo{ 16309 outputs: []outputInfo{ 16310 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16311 }, 16312 }, 16313 }, 16314 { 16315 name: "LoweredGetClosurePtr", 16316 argLen: 0, 16317 reg: regInfo{ 16318 outputs: []outputInfo{ 16319 {0, 4194304}, // R22 16320 }, 16321 }, 16322 }, 16323 { 16324 name: "MOVVconvert", 16325 argLen: 2, 16326 asm: mips.AMOVV, 16327 reg: regInfo{ 16328 inputs: []inputInfo{ 16329 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16330 }, 16331 outputs: []outputInfo{ 16332 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16333 }, 16334 }, 16335 }, 16336 16337 { 16338 name: "ADD", 16339 argLen: 2, 16340 commutative: true, 16341 asm: ppc64.AADD, 16342 reg: regInfo{ 16343 inputs: []inputInfo{ 16344 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16345 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16346 }, 16347 outputs: []outputInfo{ 16348 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16349 }, 16350 }, 16351 }, 16352 { 16353 name: "ADDconst", 16354 auxType: auxSymOff, 16355 argLen: 1, 16356 symEffect: SymAddr, 16357 asm: ppc64.AADD, 16358 reg: regInfo{ 16359 inputs: []inputInfo{ 16360 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16361 }, 16362 outputs: []outputInfo{ 16363 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16364 }, 16365 }, 16366 }, 16367 { 16368 name: "FADD", 16369 argLen: 2, 16370 commutative: true, 16371 asm: ppc64.AFADD, 16372 reg: regInfo{ 16373 inputs: []inputInfo{ 16374 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16375 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16376 }, 16377 outputs: []outputInfo{ 16378 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16379 }, 16380 }, 16381 }, 16382 { 16383 name: "FADDS", 16384 argLen: 2, 16385 commutative: true, 16386 asm: ppc64.AFADDS, 16387 reg: regInfo{ 16388 inputs: []inputInfo{ 16389 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16390 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16391 }, 16392 outputs: []outputInfo{ 16393 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16394 }, 16395 }, 16396 }, 16397 { 16398 name: "SUB", 16399 argLen: 2, 16400 asm: ppc64.ASUB, 16401 reg: regInfo{ 16402 inputs: []inputInfo{ 16403 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16404 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16405 }, 16406 outputs: []outputInfo{ 16407 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16408 }, 16409 }, 16410 }, 16411 { 16412 name: "FSUB", 16413 argLen: 2, 16414 asm: ppc64.AFSUB, 16415 reg: regInfo{ 16416 inputs: []inputInfo{ 16417 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16418 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16419 }, 16420 outputs: []outputInfo{ 16421 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16422 }, 16423 }, 16424 }, 16425 { 16426 name: "FSUBS", 16427 argLen: 2, 16428 asm: ppc64.AFSUBS, 16429 reg: regInfo{ 16430 inputs: []inputInfo{ 16431 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16432 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16433 }, 16434 outputs: []outputInfo{ 16435 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16436 }, 16437 }, 16438 }, 16439 { 16440 name: "MULLD", 16441 argLen: 2, 16442 commutative: true, 16443 asm: ppc64.AMULLD, 16444 reg: regInfo{ 16445 inputs: []inputInfo{ 16446 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16447 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16448 }, 16449 outputs: []outputInfo{ 16450 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16451 }, 16452 }, 16453 }, 16454 { 16455 name: "MULLW", 16456 argLen: 2, 16457 commutative: true, 16458 asm: ppc64.AMULLW, 16459 reg: regInfo{ 16460 inputs: []inputInfo{ 16461 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16462 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16463 }, 16464 outputs: []outputInfo{ 16465 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16466 }, 16467 }, 16468 }, 16469 { 16470 name: "MULHD", 16471 argLen: 2, 16472 commutative: true, 16473 asm: ppc64.AMULHD, 16474 reg: regInfo{ 16475 inputs: []inputInfo{ 16476 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16477 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16478 }, 16479 outputs: []outputInfo{ 16480 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16481 }, 16482 }, 16483 }, 16484 { 16485 name: "MULHW", 16486 argLen: 2, 16487 commutative: true, 16488 asm: ppc64.AMULHW, 16489 reg: regInfo{ 16490 inputs: []inputInfo{ 16491 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16492 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16493 }, 16494 outputs: []outputInfo{ 16495 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16496 }, 16497 }, 16498 }, 16499 { 16500 name: "MULHDU", 16501 argLen: 2, 16502 commutative: true, 16503 asm: ppc64.AMULHDU, 16504 reg: regInfo{ 16505 inputs: []inputInfo{ 16506 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16507 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16508 }, 16509 outputs: []outputInfo{ 16510 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16511 }, 16512 }, 16513 }, 16514 { 16515 name: "MULHWU", 16516 argLen: 2, 16517 commutative: true, 16518 asm: ppc64.AMULHWU, 16519 reg: regInfo{ 16520 inputs: []inputInfo{ 16521 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16522 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16523 }, 16524 outputs: []outputInfo{ 16525 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16526 }, 16527 }, 16528 }, 16529 { 16530 name: "FMUL", 16531 argLen: 2, 16532 commutative: true, 16533 asm: ppc64.AFMUL, 16534 reg: regInfo{ 16535 inputs: []inputInfo{ 16536 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16537 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16538 }, 16539 outputs: []outputInfo{ 16540 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16541 }, 16542 }, 16543 }, 16544 { 16545 name: "FMULS", 16546 argLen: 2, 16547 commutative: true, 16548 asm: ppc64.AFMULS, 16549 reg: regInfo{ 16550 inputs: []inputInfo{ 16551 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16552 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16553 }, 16554 outputs: []outputInfo{ 16555 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16556 }, 16557 }, 16558 }, 16559 { 16560 name: "FMADD", 16561 argLen: 3, 16562 asm: ppc64.AFMADD, 16563 reg: regInfo{ 16564 inputs: []inputInfo{ 16565 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16566 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16567 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16568 }, 16569 outputs: []outputInfo{ 16570 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16571 }, 16572 }, 16573 }, 16574 { 16575 name: "FMADDS", 16576 argLen: 3, 16577 asm: ppc64.AFMADDS, 16578 reg: regInfo{ 16579 inputs: []inputInfo{ 16580 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16581 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16582 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16583 }, 16584 outputs: []outputInfo{ 16585 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16586 }, 16587 }, 16588 }, 16589 { 16590 name: "FMSUB", 16591 argLen: 3, 16592 asm: ppc64.AFMSUB, 16593 reg: regInfo{ 16594 inputs: []inputInfo{ 16595 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16596 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16597 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16598 }, 16599 outputs: []outputInfo{ 16600 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16601 }, 16602 }, 16603 }, 16604 { 16605 name: "FMSUBS", 16606 argLen: 3, 16607 asm: ppc64.AFMSUBS, 16608 reg: regInfo{ 16609 inputs: []inputInfo{ 16610 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16611 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16612 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16613 }, 16614 outputs: []outputInfo{ 16615 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16616 }, 16617 }, 16618 }, 16619 { 16620 name: "SRAD", 16621 argLen: 2, 16622 asm: ppc64.ASRAD, 16623 reg: regInfo{ 16624 inputs: []inputInfo{ 16625 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16626 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16627 }, 16628 outputs: []outputInfo{ 16629 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16630 }, 16631 }, 16632 }, 16633 { 16634 name: "SRAW", 16635 argLen: 2, 16636 asm: ppc64.ASRAW, 16637 reg: regInfo{ 16638 inputs: []inputInfo{ 16639 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16640 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16641 }, 16642 outputs: []outputInfo{ 16643 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16644 }, 16645 }, 16646 }, 16647 { 16648 name: "SRD", 16649 argLen: 2, 16650 asm: ppc64.ASRD, 16651 reg: regInfo{ 16652 inputs: []inputInfo{ 16653 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16654 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16655 }, 16656 outputs: []outputInfo{ 16657 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16658 }, 16659 }, 16660 }, 16661 { 16662 name: "SRW", 16663 argLen: 2, 16664 asm: ppc64.ASRW, 16665 reg: regInfo{ 16666 inputs: []inputInfo{ 16667 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16668 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16669 }, 16670 outputs: []outputInfo{ 16671 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16672 }, 16673 }, 16674 }, 16675 { 16676 name: "SLD", 16677 argLen: 2, 16678 asm: ppc64.ASLD, 16679 reg: regInfo{ 16680 inputs: []inputInfo{ 16681 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16682 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16683 }, 16684 outputs: []outputInfo{ 16685 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16686 }, 16687 }, 16688 }, 16689 { 16690 name: "SLW", 16691 argLen: 2, 16692 asm: ppc64.ASLW, 16693 reg: regInfo{ 16694 inputs: []inputInfo{ 16695 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16696 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16697 }, 16698 outputs: []outputInfo{ 16699 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16700 }, 16701 }, 16702 }, 16703 { 16704 name: "ADDconstForCarry", 16705 auxType: auxInt16, 16706 argLen: 1, 16707 asm: ppc64.AADDC, 16708 reg: regInfo{ 16709 inputs: []inputInfo{ 16710 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16711 }, 16712 clobbers: 2147483648, // R31 16713 }, 16714 }, 16715 { 16716 name: "MaskIfNotCarry", 16717 argLen: 1, 16718 asm: ppc64.AADDME, 16719 reg: regInfo{ 16720 outputs: []outputInfo{ 16721 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16722 }, 16723 }, 16724 }, 16725 { 16726 name: "SRADconst", 16727 auxType: auxInt64, 16728 argLen: 1, 16729 asm: ppc64.ASRAD, 16730 reg: regInfo{ 16731 inputs: []inputInfo{ 16732 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16733 }, 16734 outputs: []outputInfo{ 16735 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16736 }, 16737 }, 16738 }, 16739 { 16740 name: "SRAWconst", 16741 auxType: auxInt64, 16742 argLen: 1, 16743 asm: ppc64.ASRAW, 16744 reg: regInfo{ 16745 inputs: []inputInfo{ 16746 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16747 }, 16748 outputs: []outputInfo{ 16749 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16750 }, 16751 }, 16752 }, 16753 { 16754 name: "SRDconst", 16755 auxType: auxInt64, 16756 argLen: 1, 16757 asm: ppc64.ASRD, 16758 reg: regInfo{ 16759 inputs: []inputInfo{ 16760 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16761 }, 16762 outputs: []outputInfo{ 16763 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16764 }, 16765 }, 16766 }, 16767 { 16768 name: "SRWconst", 16769 auxType: auxInt64, 16770 argLen: 1, 16771 asm: ppc64.ASRW, 16772 reg: regInfo{ 16773 inputs: []inputInfo{ 16774 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16775 }, 16776 outputs: []outputInfo{ 16777 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16778 }, 16779 }, 16780 }, 16781 { 16782 name: "SLDconst", 16783 auxType: auxInt64, 16784 argLen: 1, 16785 asm: ppc64.ASLD, 16786 reg: regInfo{ 16787 inputs: []inputInfo{ 16788 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16789 }, 16790 outputs: []outputInfo{ 16791 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16792 }, 16793 }, 16794 }, 16795 { 16796 name: "SLWconst", 16797 auxType: auxInt64, 16798 argLen: 1, 16799 asm: ppc64.ASLW, 16800 reg: regInfo{ 16801 inputs: []inputInfo{ 16802 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16803 }, 16804 outputs: []outputInfo{ 16805 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16806 }, 16807 }, 16808 }, 16809 { 16810 name: "ROTLconst", 16811 auxType: auxInt64, 16812 argLen: 1, 16813 asm: ppc64.AROTL, 16814 reg: regInfo{ 16815 inputs: []inputInfo{ 16816 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16817 }, 16818 outputs: []outputInfo{ 16819 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16820 }, 16821 }, 16822 }, 16823 { 16824 name: "ROTLWconst", 16825 auxType: auxInt64, 16826 argLen: 1, 16827 asm: ppc64.AROTLW, 16828 reg: regInfo{ 16829 inputs: []inputInfo{ 16830 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16831 }, 16832 outputs: []outputInfo{ 16833 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16834 }, 16835 }, 16836 }, 16837 { 16838 name: "CNTLZD", 16839 argLen: 1, 16840 clobberFlags: true, 16841 asm: ppc64.ACNTLZD, 16842 reg: regInfo{ 16843 inputs: []inputInfo{ 16844 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16845 }, 16846 outputs: []outputInfo{ 16847 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16848 }, 16849 }, 16850 }, 16851 { 16852 name: "CNTLZW", 16853 argLen: 1, 16854 clobberFlags: true, 16855 asm: ppc64.ACNTLZW, 16856 reg: regInfo{ 16857 inputs: []inputInfo{ 16858 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16859 }, 16860 outputs: []outputInfo{ 16861 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16862 }, 16863 }, 16864 }, 16865 { 16866 name: "POPCNTD", 16867 argLen: 1, 16868 asm: ppc64.APOPCNTD, 16869 reg: regInfo{ 16870 inputs: []inputInfo{ 16871 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16872 }, 16873 outputs: []outputInfo{ 16874 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16875 }, 16876 }, 16877 }, 16878 { 16879 name: "POPCNTW", 16880 argLen: 1, 16881 asm: ppc64.APOPCNTW, 16882 reg: regInfo{ 16883 inputs: []inputInfo{ 16884 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16885 }, 16886 outputs: []outputInfo{ 16887 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16888 }, 16889 }, 16890 }, 16891 { 16892 name: "POPCNTB", 16893 argLen: 1, 16894 asm: ppc64.APOPCNTB, 16895 reg: regInfo{ 16896 inputs: []inputInfo{ 16897 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16898 }, 16899 outputs: []outputInfo{ 16900 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16901 }, 16902 }, 16903 }, 16904 { 16905 name: "FDIV", 16906 argLen: 2, 16907 asm: ppc64.AFDIV, 16908 reg: regInfo{ 16909 inputs: []inputInfo{ 16910 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16911 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16912 }, 16913 outputs: []outputInfo{ 16914 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16915 }, 16916 }, 16917 }, 16918 { 16919 name: "FDIVS", 16920 argLen: 2, 16921 asm: ppc64.AFDIVS, 16922 reg: regInfo{ 16923 inputs: []inputInfo{ 16924 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16925 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16926 }, 16927 outputs: []outputInfo{ 16928 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16929 }, 16930 }, 16931 }, 16932 { 16933 name: "DIVD", 16934 argLen: 2, 16935 asm: ppc64.ADIVD, 16936 reg: regInfo{ 16937 inputs: []inputInfo{ 16938 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16939 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16940 }, 16941 outputs: []outputInfo{ 16942 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16943 }, 16944 }, 16945 }, 16946 { 16947 name: "DIVW", 16948 argLen: 2, 16949 asm: ppc64.ADIVW, 16950 reg: regInfo{ 16951 inputs: []inputInfo{ 16952 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16953 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16954 }, 16955 outputs: []outputInfo{ 16956 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16957 }, 16958 }, 16959 }, 16960 { 16961 name: "DIVDU", 16962 argLen: 2, 16963 asm: ppc64.ADIVDU, 16964 reg: regInfo{ 16965 inputs: []inputInfo{ 16966 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16967 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16968 }, 16969 outputs: []outputInfo{ 16970 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16971 }, 16972 }, 16973 }, 16974 { 16975 name: "DIVWU", 16976 argLen: 2, 16977 asm: ppc64.ADIVWU, 16978 reg: regInfo{ 16979 inputs: []inputInfo{ 16980 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16981 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16982 }, 16983 outputs: []outputInfo{ 16984 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16985 }, 16986 }, 16987 }, 16988 { 16989 name: "FCTIDZ", 16990 argLen: 1, 16991 asm: ppc64.AFCTIDZ, 16992 reg: regInfo{ 16993 inputs: []inputInfo{ 16994 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16995 }, 16996 outputs: []outputInfo{ 16997 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16998 }, 16999 }, 17000 }, 17001 { 17002 name: "FCTIWZ", 17003 argLen: 1, 17004 asm: ppc64.AFCTIWZ, 17005 reg: regInfo{ 17006 inputs: []inputInfo{ 17007 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17008 }, 17009 outputs: []outputInfo{ 17010 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17011 }, 17012 }, 17013 }, 17014 { 17015 name: "FCFID", 17016 argLen: 1, 17017 asm: ppc64.AFCFID, 17018 reg: regInfo{ 17019 inputs: []inputInfo{ 17020 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17021 }, 17022 outputs: []outputInfo{ 17023 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17024 }, 17025 }, 17026 }, 17027 { 17028 name: "FRSP", 17029 argLen: 1, 17030 asm: ppc64.AFRSP, 17031 reg: regInfo{ 17032 inputs: []inputInfo{ 17033 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17034 }, 17035 outputs: []outputInfo{ 17036 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17037 }, 17038 }, 17039 }, 17040 { 17041 name: "Xf2i64", 17042 argLen: 1, 17043 reg: regInfo{ 17044 inputs: []inputInfo{ 17045 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17046 }, 17047 outputs: []outputInfo{ 17048 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17049 }, 17050 }, 17051 }, 17052 { 17053 name: "Xi2f64", 17054 argLen: 1, 17055 reg: regInfo{ 17056 inputs: []inputInfo{ 17057 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17058 }, 17059 outputs: []outputInfo{ 17060 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17061 }, 17062 }, 17063 }, 17064 { 17065 name: "AND", 17066 argLen: 2, 17067 commutative: true, 17068 asm: ppc64.AAND, 17069 reg: regInfo{ 17070 inputs: []inputInfo{ 17071 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17072 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17073 }, 17074 outputs: []outputInfo{ 17075 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17076 }, 17077 }, 17078 }, 17079 { 17080 name: "ANDN", 17081 argLen: 2, 17082 asm: ppc64.AANDN, 17083 reg: regInfo{ 17084 inputs: []inputInfo{ 17085 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17086 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17087 }, 17088 outputs: []outputInfo{ 17089 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17090 }, 17091 }, 17092 }, 17093 { 17094 name: "OR", 17095 argLen: 2, 17096 commutative: true, 17097 asm: ppc64.AOR, 17098 reg: regInfo{ 17099 inputs: []inputInfo{ 17100 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17101 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17102 }, 17103 outputs: []outputInfo{ 17104 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17105 }, 17106 }, 17107 }, 17108 { 17109 name: "ORN", 17110 argLen: 2, 17111 asm: ppc64.AORN, 17112 reg: regInfo{ 17113 inputs: []inputInfo{ 17114 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17115 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17116 }, 17117 outputs: []outputInfo{ 17118 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17119 }, 17120 }, 17121 }, 17122 { 17123 name: "NOR", 17124 argLen: 2, 17125 commutative: true, 17126 asm: ppc64.ANOR, 17127 reg: regInfo{ 17128 inputs: []inputInfo{ 17129 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17130 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17131 }, 17132 outputs: []outputInfo{ 17133 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17134 }, 17135 }, 17136 }, 17137 { 17138 name: "XOR", 17139 argLen: 2, 17140 commutative: true, 17141 asm: ppc64.AXOR, 17142 reg: regInfo{ 17143 inputs: []inputInfo{ 17144 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17145 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17146 }, 17147 outputs: []outputInfo{ 17148 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17149 }, 17150 }, 17151 }, 17152 { 17153 name: "EQV", 17154 argLen: 2, 17155 commutative: true, 17156 asm: ppc64.AEQV, 17157 reg: regInfo{ 17158 inputs: []inputInfo{ 17159 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17160 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17161 }, 17162 outputs: []outputInfo{ 17163 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17164 }, 17165 }, 17166 }, 17167 { 17168 name: "NEG", 17169 argLen: 1, 17170 asm: ppc64.ANEG, 17171 reg: regInfo{ 17172 inputs: []inputInfo{ 17173 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17174 }, 17175 outputs: []outputInfo{ 17176 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17177 }, 17178 }, 17179 }, 17180 { 17181 name: "FNEG", 17182 argLen: 1, 17183 asm: ppc64.AFNEG, 17184 reg: regInfo{ 17185 inputs: []inputInfo{ 17186 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17187 }, 17188 outputs: []outputInfo{ 17189 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17190 }, 17191 }, 17192 }, 17193 { 17194 name: "FSQRT", 17195 argLen: 1, 17196 asm: ppc64.AFSQRT, 17197 reg: regInfo{ 17198 inputs: []inputInfo{ 17199 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17200 }, 17201 outputs: []outputInfo{ 17202 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17203 }, 17204 }, 17205 }, 17206 { 17207 name: "FSQRTS", 17208 argLen: 1, 17209 asm: ppc64.AFSQRTS, 17210 reg: regInfo{ 17211 inputs: []inputInfo{ 17212 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17213 }, 17214 outputs: []outputInfo{ 17215 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17216 }, 17217 }, 17218 }, 17219 { 17220 name: "FFLOOR", 17221 argLen: 1, 17222 asm: ppc64.AFRIM, 17223 reg: regInfo{ 17224 inputs: []inputInfo{ 17225 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17226 }, 17227 outputs: []outputInfo{ 17228 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17229 }, 17230 }, 17231 }, 17232 { 17233 name: "FCEIL", 17234 argLen: 1, 17235 asm: ppc64.AFRIP, 17236 reg: regInfo{ 17237 inputs: []inputInfo{ 17238 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17239 }, 17240 outputs: []outputInfo{ 17241 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17242 }, 17243 }, 17244 }, 17245 { 17246 name: "FTRUNC", 17247 argLen: 1, 17248 asm: ppc64.AFRIZ, 17249 reg: regInfo{ 17250 inputs: []inputInfo{ 17251 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17252 }, 17253 outputs: []outputInfo{ 17254 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17255 }, 17256 }, 17257 }, 17258 { 17259 name: "ORconst", 17260 auxType: auxInt64, 17261 argLen: 1, 17262 asm: ppc64.AOR, 17263 reg: regInfo{ 17264 inputs: []inputInfo{ 17265 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17266 }, 17267 outputs: []outputInfo{ 17268 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17269 }, 17270 }, 17271 }, 17272 { 17273 name: "XORconst", 17274 auxType: auxInt64, 17275 argLen: 1, 17276 asm: ppc64.AXOR, 17277 reg: regInfo{ 17278 inputs: []inputInfo{ 17279 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17280 }, 17281 outputs: []outputInfo{ 17282 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17283 }, 17284 }, 17285 }, 17286 { 17287 name: "ANDconst", 17288 auxType: auxInt64, 17289 argLen: 1, 17290 clobberFlags: true, 17291 asm: ppc64.AANDCC, 17292 reg: regInfo{ 17293 inputs: []inputInfo{ 17294 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17295 }, 17296 outputs: []outputInfo{ 17297 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17298 }, 17299 }, 17300 }, 17301 { 17302 name: "ANDCCconst", 17303 auxType: auxInt64, 17304 argLen: 1, 17305 asm: ppc64.AANDCC, 17306 reg: regInfo{ 17307 inputs: []inputInfo{ 17308 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17309 }, 17310 }, 17311 }, 17312 { 17313 name: "MOVBreg", 17314 argLen: 1, 17315 asm: ppc64.AMOVB, 17316 reg: regInfo{ 17317 inputs: []inputInfo{ 17318 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17319 }, 17320 outputs: []outputInfo{ 17321 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17322 }, 17323 }, 17324 }, 17325 { 17326 name: "MOVBZreg", 17327 argLen: 1, 17328 asm: ppc64.AMOVBZ, 17329 reg: regInfo{ 17330 inputs: []inputInfo{ 17331 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17332 }, 17333 outputs: []outputInfo{ 17334 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17335 }, 17336 }, 17337 }, 17338 { 17339 name: "MOVHreg", 17340 argLen: 1, 17341 asm: ppc64.AMOVH, 17342 reg: regInfo{ 17343 inputs: []inputInfo{ 17344 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17345 }, 17346 outputs: []outputInfo{ 17347 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17348 }, 17349 }, 17350 }, 17351 { 17352 name: "MOVHZreg", 17353 argLen: 1, 17354 asm: ppc64.AMOVHZ, 17355 reg: regInfo{ 17356 inputs: []inputInfo{ 17357 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17358 }, 17359 outputs: []outputInfo{ 17360 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17361 }, 17362 }, 17363 }, 17364 { 17365 name: "MOVWreg", 17366 argLen: 1, 17367 asm: ppc64.AMOVW, 17368 reg: regInfo{ 17369 inputs: []inputInfo{ 17370 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17371 }, 17372 outputs: []outputInfo{ 17373 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17374 }, 17375 }, 17376 }, 17377 { 17378 name: "MOVWZreg", 17379 argLen: 1, 17380 asm: ppc64.AMOVWZ, 17381 reg: regInfo{ 17382 inputs: []inputInfo{ 17383 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17384 }, 17385 outputs: []outputInfo{ 17386 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17387 }, 17388 }, 17389 }, 17390 { 17391 name: "MOVBZload", 17392 auxType: auxSymOff, 17393 argLen: 2, 17394 faultOnNilArg0: true, 17395 symEffect: SymRead, 17396 asm: ppc64.AMOVBZ, 17397 reg: regInfo{ 17398 inputs: []inputInfo{ 17399 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17400 }, 17401 outputs: []outputInfo{ 17402 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17403 }, 17404 }, 17405 }, 17406 { 17407 name: "MOVHload", 17408 auxType: auxSymOff, 17409 argLen: 2, 17410 faultOnNilArg0: true, 17411 symEffect: SymRead, 17412 asm: ppc64.AMOVH, 17413 reg: regInfo{ 17414 inputs: []inputInfo{ 17415 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17416 }, 17417 outputs: []outputInfo{ 17418 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17419 }, 17420 }, 17421 }, 17422 { 17423 name: "MOVHZload", 17424 auxType: auxSymOff, 17425 argLen: 2, 17426 faultOnNilArg0: true, 17427 symEffect: SymRead, 17428 asm: ppc64.AMOVHZ, 17429 reg: regInfo{ 17430 inputs: []inputInfo{ 17431 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17432 }, 17433 outputs: []outputInfo{ 17434 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17435 }, 17436 }, 17437 }, 17438 { 17439 name: "MOVWload", 17440 auxType: auxSymOff, 17441 argLen: 2, 17442 faultOnNilArg0: true, 17443 symEffect: SymRead, 17444 asm: ppc64.AMOVW, 17445 reg: regInfo{ 17446 inputs: []inputInfo{ 17447 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17448 }, 17449 outputs: []outputInfo{ 17450 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17451 }, 17452 }, 17453 }, 17454 { 17455 name: "MOVWZload", 17456 auxType: auxSymOff, 17457 argLen: 2, 17458 faultOnNilArg0: true, 17459 symEffect: SymRead, 17460 asm: ppc64.AMOVWZ, 17461 reg: regInfo{ 17462 inputs: []inputInfo{ 17463 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17464 }, 17465 outputs: []outputInfo{ 17466 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17467 }, 17468 }, 17469 }, 17470 { 17471 name: "MOVDload", 17472 auxType: auxSymOff, 17473 argLen: 2, 17474 faultOnNilArg0: true, 17475 symEffect: SymRead, 17476 asm: ppc64.AMOVD, 17477 reg: regInfo{ 17478 inputs: []inputInfo{ 17479 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17480 }, 17481 outputs: []outputInfo{ 17482 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17483 }, 17484 }, 17485 }, 17486 { 17487 name: "FMOVDload", 17488 auxType: auxSymOff, 17489 argLen: 2, 17490 faultOnNilArg0: true, 17491 symEffect: SymRead, 17492 asm: ppc64.AFMOVD, 17493 reg: regInfo{ 17494 inputs: []inputInfo{ 17495 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17496 }, 17497 outputs: []outputInfo{ 17498 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17499 }, 17500 }, 17501 }, 17502 { 17503 name: "FMOVSload", 17504 auxType: auxSymOff, 17505 argLen: 2, 17506 faultOnNilArg0: true, 17507 symEffect: SymRead, 17508 asm: ppc64.AFMOVS, 17509 reg: regInfo{ 17510 inputs: []inputInfo{ 17511 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17512 }, 17513 outputs: []outputInfo{ 17514 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17515 }, 17516 }, 17517 }, 17518 { 17519 name: "MOVBstore", 17520 auxType: auxSymOff, 17521 argLen: 3, 17522 faultOnNilArg0: true, 17523 symEffect: SymWrite, 17524 asm: ppc64.AMOVB, 17525 reg: regInfo{ 17526 inputs: []inputInfo{ 17527 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17528 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17529 }, 17530 }, 17531 }, 17532 { 17533 name: "MOVHstore", 17534 auxType: auxSymOff, 17535 argLen: 3, 17536 faultOnNilArg0: true, 17537 symEffect: SymWrite, 17538 asm: ppc64.AMOVH, 17539 reg: regInfo{ 17540 inputs: []inputInfo{ 17541 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17542 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17543 }, 17544 }, 17545 }, 17546 { 17547 name: "MOVWstore", 17548 auxType: auxSymOff, 17549 argLen: 3, 17550 faultOnNilArg0: true, 17551 symEffect: SymWrite, 17552 asm: ppc64.AMOVW, 17553 reg: regInfo{ 17554 inputs: []inputInfo{ 17555 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17556 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17557 }, 17558 }, 17559 }, 17560 { 17561 name: "MOVDstore", 17562 auxType: auxSymOff, 17563 argLen: 3, 17564 faultOnNilArg0: true, 17565 symEffect: SymWrite, 17566 asm: ppc64.AMOVD, 17567 reg: regInfo{ 17568 inputs: []inputInfo{ 17569 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17570 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17571 }, 17572 }, 17573 }, 17574 { 17575 name: "FMOVDstore", 17576 auxType: auxSymOff, 17577 argLen: 3, 17578 faultOnNilArg0: true, 17579 symEffect: SymWrite, 17580 asm: ppc64.AFMOVD, 17581 reg: regInfo{ 17582 inputs: []inputInfo{ 17583 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17584 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17585 }, 17586 }, 17587 }, 17588 { 17589 name: "FMOVSstore", 17590 auxType: auxSymOff, 17591 argLen: 3, 17592 faultOnNilArg0: true, 17593 symEffect: SymWrite, 17594 asm: ppc64.AFMOVS, 17595 reg: regInfo{ 17596 inputs: []inputInfo{ 17597 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17598 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17599 }, 17600 }, 17601 }, 17602 { 17603 name: "MOVBstorezero", 17604 auxType: auxSymOff, 17605 argLen: 2, 17606 faultOnNilArg0: true, 17607 symEffect: SymWrite, 17608 asm: ppc64.AMOVB, 17609 reg: regInfo{ 17610 inputs: []inputInfo{ 17611 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17612 }, 17613 }, 17614 }, 17615 { 17616 name: "MOVHstorezero", 17617 auxType: auxSymOff, 17618 argLen: 2, 17619 faultOnNilArg0: true, 17620 symEffect: SymWrite, 17621 asm: ppc64.AMOVH, 17622 reg: regInfo{ 17623 inputs: []inputInfo{ 17624 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17625 }, 17626 }, 17627 }, 17628 { 17629 name: "MOVWstorezero", 17630 auxType: auxSymOff, 17631 argLen: 2, 17632 faultOnNilArg0: true, 17633 symEffect: SymWrite, 17634 asm: ppc64.AMOVW, 17635 reg: regInfo{ 17636 inputs: []inputInfo{ 17637 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17638 }, 17639 }, 17640 }, 17641 { 17642 name: "MOVDstorezero", 17643 auxType: auxSymOff, 17644 argLen: 2, 17645 faultOnNilArg0: true, 17646 symEffect: SymWrite, 17647 asm: ppc64.AMOVD, 17648 reg: regInfo{ 17649 inputs: []inputInfo{ 17650 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17651 }, 17652 }, 17653 }, 17654 { 17655 name: "MOVDaddr", 17656 auxType: auxSymOff, 17657 argLen: 1, 17658 rematerializeable: true, 17659 symEffect: SymAddr, 17660 asm: ppc64.AMOVD, 17661 reg: regInfo{ 17662 inputs: []inputInfo{ 17663 {0, 6}, // SP SB 17664 }, 17665 outputs: []outputInfo{ 17666 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17667 }, 17668 }, 17669 }, 17670 { 17671 name: "MOVDconst", 17672 auxType: auxInt64, 17673 argLen: 0, 17674 rematerializeable: true, 17675 asm: ppc64.AMOVD, 17676 reg: regInfo{ 17677 outputs: []outputInfo{ 17678 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17679 }, 17680 }, 17681 }, 17682 { 17683 name: "FMOVDconst", 17684 auxType: auxFloat64, 17685 argLen: 0, 17686 rematerializeable: true, 17687 asm: ppc64.AFMOVD, 17688 reg: regInfo{ 17689 outputs: []outputInfo{ 17690 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17691 }, 17692 }, 17693 }, 17694 { 17695 name: "FMOVSconst", 17696 auxType: auxFloat32, 17697 argLen: 0, 17698 rematerializeable: true, 17699 asm: ppc64.AFMOVS, 17700 reg: regInfo{ 17701 outputs: []outputInfo{ 17702 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17703 }, 17704 }, 17705 }, 17706 { 17707 name: "FCMPU", 17708 argLen: 2, 17709 asm: ppc64.AFCMPU, 17710 reg: regInfo{ 17711 inputs: []inputInfo{ 17712 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17713 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17714 }, 17715 }, 17716 }, 17717 { 17718 name: "CMP", 17719 argLen: 2, 17720 asm: ppc64.ACMP, 17721 reg: regInfo{ 17722 inputs: []inputInfo{ 17723 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17724 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17725 }, 17726 }, 17727 }, 17728 { 17729 name: "CMPU", 17730 argLen: 2, 17731 asm: ppc64.ACMPU, 17732 reg: regInfo{ 17733 inputs: []inputInfo{ 17734 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17735 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17736 }, 17737 }, 17738 }, 17739 { 17740 name: "CMPW", 17741 argLen: 2, 17742 asm: ppc64.ACMPW, 17743 reg: regInfo{ 17744 inputs: []inputInfo{ 17745 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17746 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17747 }, 17748 }, 17749 }, 17750 { 17751 name: "CMPWU", 17752 argLen: 2, 17753 asm: ppc64.ACMPWU, 17754 reg: regInfo{ 17755 inputs: []inputInfo{ 17756 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17757 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17758 }, 17759 }, 17760 }, 17761 { 17762 name: "CMPconst", 17763 auxType: auxInt64, 17764 argLen: 1, 17765 asm: ppc64.ACMP, 17766 reg: regInfo{ 17767 inputs: []inputInfo{ 17768 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17769 }, 17770 }, 17771 }, 17772 { 17773 name: "CMPUconst", 17774 auxType: auxInt64, 17775 argLen: 1, 17776 asm: ppc64.ACMPU, 17777 reg: regInfo{ 17778 inputs: []inputInfo{ 17779 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17780 }, 17781 }, 17782 }, 17783 { 17784 name: "CMPWconst", 17785 auxType: auxInt32, 17786 argLen: 1, 17787 asm: ppc64.ACMPW, 17788 reg: regInfo{ 17789 inputs: []inputInfo{ 17790 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17791 }, 17792 }, 17793 }, 17794 { 17795 name: "CMPWUconst", 17796 auxType: auxInt32, 17797 argLen: 1, 17798 asm: ppc64.ACMPWU, 17799 reg: regInfo{ 17800 inputs: []inputInfo{ 17801 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17802 }, 17803 }, 17804 }, 17805 { 17806 name: "Equal", 17807 argLen: 1, 17808 reg: regInfo{ 17809 outputs: []outputInfo{ 17810 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17811 }, 17812 }, 17813 }, 17814 { 17815 name: "NotEqual", 17816 argLen: 1, 17817 reg: regInfo{ 17818 outputs: []outputInfo{ 17819 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17820 }, 17821 }, 17822 }, 17823 { 17824 name: "LessThan", 17825 argLen: 1, 17826 reg: regInfo{ 17827 outputs: []outputInfo{ 17828 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17829 }, 17830 }, 17831 }, 17832 { 17833 name: "FLessThan", 17834 argLen: 1, 17835 reg: regInfo{ 17836 outputs: []outputInfo{ 17837 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17838 }, 17839 }, 17840 }, 17841 { 17842 name: "LessEqual", 17843 argLen: 1, 17844 reg: regInfo{ 17845 outputs: []outputInfo{ 17846 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17847 }, 17848 }, 17849 }, 17850 { 17851 name: "FLessEqual", 17852 argLen: 1, 17853 reg: regInfo{ 17854 outputs: []outputInfo{ 17855 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17856 }, 17857 }, 17858 }, 17859 { 17860 name: "GreaterThan", 17861 argLen: 1, 17862 reg: regInfo{ 17863 outputs: []outputInfo{ 17864 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17865 }, 17866 }, 17867 }, 17868 { 17869 name: "FGreaterThan", 17870 argLen: 1, 17871 reg: regInfo{ 17872 outputs: []outputInfo{ 17873 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17874 }, 17875 }, 17876 }, 17877 { 17878 name: "GreaterEqual", 17879 argLen: 1, 17880 reg: regInfo{ 17881 outputs: []outputInfo{ 17882 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17883 }, 17884 }, 17885 }, 17886 { 17887 name: "FGreaterEqual", 17888 argLen: 1, 17889 reg: regInfo{ 17890 outputs: []outputInfo{ 17891 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17892 }, 17893 }, 17894 }, 17895 { 17896 name: "LoweredGetClosurePtr", 17897 argLen: 0, 17898 reg: regInfo{ 17899 outputs: []outputInfo{ 17900 {0, 2048}, // R11 17901 }, 17902 }, 17903 }, 17904 { 17905 name: "LoweredNilCheck", 17906 argLen: 2, 17907 clobberFlags: true, 17908 nilCheck: true, 17909 faultOnNilArg0: true, 17910 reg: regInfo{ 17911 inputs: []inputInfo{ 17912 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17913 }, 17914 clobbers: 2147483648, // R31 17915 }, 17916 }, 17917 { 17918 name: "LoweredRound32F", 17919 argLen: 1, 17920 resultInArg0: true, 17921 reg: regInfo{ 17922 inputs: []inputInfo{ 17923 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17924 }, 17925 outputs: []outputInfo{ 17926 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17927 }, 17928 }, 17929 }, 17930 { 17931 name: "LoweredRound64F", 17932 argLen: 1, 17933 resultInArg0: true, 17934 reg: regInfo{ 17935 inputs: []inputInfo{ 17936 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17937 }, 17938 outputs: []outputInfo{ 17939 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17940 }, 17941 }, 17942 }, 17943 { 17944 name: "MOVDconvert", 17945 argLen: 2, 17946 asm: ppc64.AMOVD, 17947 reg: regInfo{ 17948 inputs: []inputInfo{ 17949 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17950 }, 17951 outputs: []outputInfo{ 17952 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17953 }, 17954 }, 17955 }, 17956 { 17957 name: "CALLstatic", 17958 auxType: auxSymOff, 17959 argLen: 1, 17960 clobberFlags: true, 17961 call: true, 17962 symEffect: SymNone, 17963 reg: regInfo{ 17964 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17965 }, 17966 }, 17967 { 17968 name: "CALLclosure", 17969 auxType: auxInt64, 17970 argLen: 3, 17971 clobberFlags: true, 17972 call: true, 17973 reg: regInfo{ 17974 inputs: []inputInfo{ 17975 {1, 2048}, // R11 17976 {0, 1073733626}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17977 }, 17978 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17979 }, 17980 }, 17981 { 17982 name: "CALLinter", 17983 auxType: auxInt64, 17984 argLen: 2, 17985 clobberFlags: true, 17986 call: true, 17987 reg: regInfo{ 17988 inputs: []inputInfo{ 17989 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17990 }, 17991 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17992 }, 17993 }, 17994 { 17995 name: "LoweredZero", 17996 auxType: auxInt64, 17997 argLen: 2, 17998 clobberFlags: true, 17999 faultOnNilArg0: true, 18000 reg: regInfo{ 18001 inputs: []inputInfo{ 18002 {0, 8}, // R3 18003 }, 18004 clobbers: 8, // R3 18005 }, 18006 }, 18007 { 18008 name: "LoweredMove", 18009 auxType: auxInt64, 18010 argLen: 3, 18011 clobberFlags: true, 18012 faultOnNilArg0: true, 18013 faultOnNilArg1: true, 18014 reg: regInfo{ 18015 inputs: []inputInfo{ 18016 {0, 8}, // R3 18017 {1, 16}, // R4 18018 }, 18019 clobbers: 1944, // R3 R4 R7 R8 R9 R10 18020 }, 18021 }, 18022 { 18023 name: "LoweredAtomicStore32", 18024 argLen: 3, 18025 faultOnNilArg0: true, 18026 hasSideEffects: true, 18027 reg: regInfo{ 18028 inputs: []inputInfo{ 18029 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18030 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18031 }, 18032 }, 18033 }, 18034 { 18035 name: "LoweredAtomicStore64", 18036 argLen: 3, 18037 faultOnNilArg0: true, 18038 hasSideEffects: true, 18039 reg: regInfo{ 18040 inputs: []inputInfo{ 18041 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18042 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18043 }, 18044 }, 18045 }, 18046 { 18047 name: "LoweredAtomicLoad32", 18048 argLen: 2, 18049 clobberFlags: true, 18050 faultOnNilArg0: true, 18051 reg: regInfo{ 18052 inputs: []inputInfo{ 18053 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18054 }, 18055 outputs: []outputInfo{ 18056 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18057 }, 18058 }, 18059 }, 18060 { 18061 name: "LoweredAtomicLoad64", 18062 argLen: 2, 18063 clobberFlags: true, 18064 faultOnNilArg0: true, 18065 reg: regInfo{ 18066 inputs: []inputInfo{ 18067 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18068 }, 18069 outputs: []outputInfo{ 18070 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18071 }, 18072 }, 18073 }, 18074 { 18075 name: "LoweredAtomicLoadPtr", 18076 argLen: 2, 18077 clobberFlags: true, 18078 faultOnNilArg0: true, 18079 reg: regInfo{ 18080 inputs: []inputInfo{ 18081 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18082 }, 18083 outputs: []outputInfo{ 18084 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18085 }, 18086 }, 18087 }, 18088 { 18089 name: "LoweredAtomicAdd32", 18090 argLen: 3, 18091 resultNotInArgs: true, 18092 clobberFlags: true, 18093 faultOnNilArg0: true, 18094 hasSideEffects: true, 18095 reg: regInfo{ 18096 inputs: []inputInfo{ 18097 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18098 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18099 }, 18100 outputs: []outputInfo{ 18101 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18102 }, 18103 }, 18104 }, 18105 { 18106 name: "LoweredAtomicAdd64", 18107 argLen: 3, 18108 resultNotInArgs: true, 18109 clobberFlags: true, 18110 faultOnNilArg0: true, 18111 hasSideEffects: true, 18112 reg: regInfo{ 18113 inputs: []inputInfo{ 18114 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18115 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18116 }, 18117 outputs: []outputInfo{ 18118 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18119 }, 18120 }, 18121 }, 18122 { 18123 name: "LoweredAtomicExchange32", 18124 argLen: 3, 18125 resultNotInArgs: true, 18126 clobberFlags: true, 18127 faultOnNilArg0: true, 18128 hasSideEffects: true, 18129 reg: regInfo{ 18130 inputs: []inputInfo{ 18131 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18132 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18133 }, 18134 outputs: []outputInfo{ 18135 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18136 }, 18137 }, 18138 }, 18139 { 18140 name: "LoweredAtomicExchange64", 18141 argLen: 3, 18142 resultNotInArgs: true, 18143 clobberFlags: true, 18144 faultOnNilArg0: true, 18145 hasSideEffects: true, 18146 reg: regInfo{ 18147 inputs: []inputInfo{ 18148 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18149 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18150 }, 18151 outputs: []outputInfo{ 18152 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18153 }, 18154 }, 18155 }, 18156 { 18157 name: "LoweredAtomicCas64", 18158 argLen: 4, 18159 resultNotInArgs: true, 18160 clobberFlags: true, 18161 faultOnNilArg0: true, 18162 hasSideEffects: true, 18163 reg: regInfo{ 18164 inputs: []inputInfo{ 18165 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18166 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18167 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18168 }, 18169 outputs: []outputInfo{ 18170 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18171 }, 18172 }, 18173 }, 18174 { 18175 name: "LoweredAtomicCas32", 18176 argLen: 4, 18177 resultNotInArgs: true, 18178 clobberFlags: true, 18179 faultOnNilArg0: true, 18180 hasSideEffects: true, 18181 reg: regInfo{ 18182 inputs: []inputInfo{ 18183 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18184 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18185 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18186 }, 18187 outputs: []outputInfo{ 18188 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18189 }, 18190 }, 18191 }, 18192 { 18193 name: "LoweredAtomicAnd8", 18194 argLen: 3, 18195 faultOnNilArg0: true, 18196 hasSideEffects: true, 18197 asm: ppc64.AAND, 18198 reg: regInfo{ 18199 inputs: []inputInfo{ 18200 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18201 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18202 }, 18203 }, 18204 }, 18205 { 18206 name: "LoweredAtomicOr8", 18207 argLen: 3, 18208 faultOnNilArg0: true, 18209 hasSideEffects: true, 18210 asm: ppc64.AOR, 18211 reg: regInfo{ 18212 inputs: []inputInfo{ 18213 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18214 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18215 }, 18216 }, 18217 }, 18218 { 18219 name: "InvertFlags", 18220 argLen: 1, 18221 reg: regInfo{}, 18222 }, 18223 { 18224 name: "FlagEQ", 18225 argLen: 0, 18226 reg: regInfo{}, 18227 }, 18228 { 18229 name: "FlagLT", 18230 argLen: 0, 18231 reg: regInfo{}, 18232 }, 18233 { 18234 name: "FlagGT", 18235 argLen: 0, 18236 reg: regInfo{}, 18237 }, 18238 18239 { 18240 name: "FADDS", 18241 argLen: 2, 18242 commutative: true, 18243 resultInArg0: true, 18244 clobberFlags: true, 18245 asm: s390x.AFADDS, 18246 reg: regInfo{ 18247 inputs: []inputInfo{ 18248 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18249 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18250 }, 18251 outputs: []outputInfo{ 18252 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18253 }, 18254 }, 18255 }, 18256 { 18257 name: "FADD", 18258 argLen: 2, 18259 commutative: true, 18260 resultInArg0: true, 18261 clobberFlags: true, 18262 asm: s390x.AFADD, 18263 reg: regInfo{ 18264 inputs: []inputInfo{ 18265 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18266 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18267 }, 18268 outputs: []outputInfo{ 18269 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18270 }, 18271 }, 18272 }, 18273 { 18274 name: "FSUBS", 18275 argLen: 2, 18276 resultInArg0: true, 18277 clobberFlags: true, 18278 asm: s390x.AFSUBS, 18279 reg: regInfo{ 18280 inputs: []inputInfo{ 18281 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18282 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18283 }, 18284 outputs: []outputInfo{ 18285 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18286 }, 18287 }, 18288 }, 18289 { 18290 name: "FSUB", 18291 argLen: 2, 18292 resultInArg0: true, 18293 clobberFlags: true, 18294 asm: s390x.AFSUB, 18295 reg: regInfo{ 18296 inputs: []inputInfo{ 18297 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18298 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18299 }, 18300 outputs: []outputInfo{ 18301 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18302 }, 18303 }, 18304 }, 18305 { 18306 name: "FMULS", 18307 argLen: 2, 18308 commutative: true, 18309 resultInArg0: true, 18310 asm: s390x.AFMULS, 18311 reg: regInfo{ 18312 inputs: []inputInfo{ 18313 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18314 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18315 }, 18316 outputs: []outputInfo{ 18317 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18318 }, 18319 }, 18320 }, 18321 { 18322 name: "FMUL", 18323 argLen: 2, 18324 commutative: true, 18325 resultInArg0: true, 18326 asm: s390x.AFMUL, 18327 reg: regInfo{ 18328 inputs: []inputInfo{ 18329 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18330 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18331 }, 18332 outputs: []outputInfo{ 18333 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18334 }, 18335 }, 18336 }, 18337 { 18338 name: "FDIVS", 18339 argLen: 2, 18340 resultInArg0: true, 18341 asm: s390x.AFDIVS, 18342 reg: regInfo{ 18343 inputs: []inputInfo{ 18344 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18345 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18346 }, 18347 outputs: []outputInfo{ 18348 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18349 }, 18350 }, 18351 }, 18352 { 18353 name: "FDIV", 18354 argLen: 2, 18355 resultInArg0: true, 18356 asm: s390x.AFDIV, 18357 reg: regInfo{ 18358 inputs: []inputInfo{ 18359 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18360 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18361 }, 18362 outputs: []outputInfo{ 18363 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18364 }, 18365 }, 18366 }, 18367 { 18368 name: "FNEGS", 18369 argLen: 1, 18370 clobberFlags: true, 18371 asm: s390x.AFNEGS, 18372 reg: regInfo{ 18373 inputs: []inputInfo{ 18374 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18375 }, 18376 outputs: []outputInfo{ 18377 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18378 }, 18379 }, 18380 }, 18381 { 18382 name: "FNEG", 18383 argLen: 1, 18384 clobberFlags: true, 18385 asm: s390x.AFNEG, 18386 reg: regInfo{ 18387 inputs: []inputInfo{ 18388 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18389 }, 18390 outputs: []outputInfo{ 18391 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18392 }, 18393 }, 18394 }, 18395 { 18396 name: "FMADDS", 18397 argLen: 3, 18398 resultInArg0: true, 18399 asm: s390x.AFMADDS, 18400 reg: regInfo{ 18401 inputs: []inputInfo{ 18402 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18403 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18404 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18405 }, 18406 outputs: []outputInfo{ 18407 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18408 }, 18409 }, 18410 }, 18411 { 18412 name: "FMADD", 18413 argLen: 3, 18414 resultInArg0: true, 18415 asm: s390x.AFMADD, 18416 reg: regInfo{ 18417 inputs: []inputInfo{ 18418 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18419 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18420 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18421 }, 18422 outputs: []outputInfo{ 18423 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18424 }, 18425 }, 18426 }, 18427 { 18428 name: "FMSUBS", 18429 argLen: 3, 18430 resultInArg0: true, 18431 asm: s390x.AFMSUBS, 18432 reg: regInfo{ 18433 inputs: []inputInfo{ 18434 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18435 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18436 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18437 }, 18438 outputs: []outputInfo{ 18439 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18440 }, 18441 }, 18442 }, 18443 { 18444 name: "FMSUB", 18445 argLen: 3, 18446 resultInArg0: true, 18447 asm: s390x.AFMSUB, 18448 reg: regInfo{ 18449 inputs: []inputInfo{ 18450 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18451 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18452 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18453 }, 18454 outputs: []outputInfo{ 18455 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18456 }, 18457 }, 18458 }, 18459 { 18460 name: "FMOVSload", 18461 auxType: auxSymOff, 18462 argLen: 2, 18463 faultOnNilArg0: true, 18464 symEffect: SymRead, 18465 asm: s390x.AFMOVS, 18466 reg: regInfo{ 18467 inputs: []inputInfo{ 18468 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18469 }, 18470 outputs: []outputInfo{ 18471 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18472 }, 18473 }, 18474 }, 18475 { 18476 name: "FMOVDload", 18477 auxType: auxSymOff, 18478 argLen: 2, 18479 faultOnNilArg0: true, 18480 symEffect: SymRead, 18481 asm: s390x.AFMOVD, 18482 reg: regInfo{ 18483 inputs: []inputInfo{ 18484 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18485 }, 18486 outputs: []outputInfo{ 18487 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18488 }, 18489 }, 18490 }, 18491 { 18492 name: "FMOVSconst", 18493 auxType: auxFloat32, 18494 argLen: 0, 18495 rematerializeable: true, 18496 asm: s390x.AFMOVS, 18497 reg: regInfo{ 18498 outputs: []outputInfo{ 18499 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18500 }, 18501 }, 18502 }, 18503 { 18504 name: "FMOVDconst", 18505 auxType: auxFloat64, 18506 argLen: 0, 18507 rematerializeable: true, 18508 asm: s390x.AFMOVD, 18509 reg: regInfo{ 18510 outputs: []outputInfo{ 18511 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18512 }, 18513 }, 18514 }, 18515 { 18516 name: "FMOVSloadidx", 18517 auxType: auxSymOff, 18518 argLen: 3, 18519 symEffect: SymRead, 18520 asm: s390x.AFMOVS, 18521 reg: regInfo{ 18522 inputs: []inputInfo{ 18523 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18524 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18525 }, 18526 outputs: []outputInfo{ 18527 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18528 }, 18529 }, 18530 }, 18531 { 18532 name: "FMOVDloadidx", 18533 auxType: auxSymOff, 18534 argLen: 3, 18535 symEffect: SymRead, 18536 asm: s390x.AFMOVD, 18537 reg: regInfo{ 18538 inputs: []inputInfo{ 18539 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18540 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18541 }, 18542 outputs: []outputInfo{ 18543 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18544 }, 18545 }, 18546 }, 18547 { 18548 name: "FMOVSstore", 18549 auxType: auxSymOff, 18550 argLen: 3, 18551 faultOnNilArg0: true, 18552 symEffect: SymWrite, 18553 asm: s390x.AFMOVS, 18554 reg: regInfo{ 18555 inputs: []inputInfo{ 18556 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18557 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18558 }, 18559 }, 18560 }, 18561 { 18562 name: "FMOVDstore", 18563 auxType: auxSymOff, 18564 argLen: 3, 18565 faultOnNilArg0: true, 18566 symEffect: SymWrite, 18567 asm: s390x.AFMOVD, 18568 reg: regInfo{ 18569 inputs: []inputInfo{ 18570 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18571 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18572 }, 18573 }, 18574 }, 18575 { 18576 name: "FMOVSstoreidx", 18577 auxType: auxSymOff, 18578 argLen: 4, 18579 symEffect: SymWrite, 18580 asm: s390x.AFMOVS, 18581 reg: regInfo{ 18582 inputs: []inputInfo{ 18583 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18584 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18585 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18586 }, 18587 }, 18588 }, 18589 { 18590 name: "FMOVDstoreidx", 18591 auxType: auxSymOff, 18592 argLen: 4, 18593 symEffect: SymWrite, 18594 asm: s390x.AFMOVD, 18595 reg: regInfo{ 18596 inputs: []inputInfo{ 18597 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18598 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18599 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18600 }, 18601 }, 18602 }, 18603 { 18604 name: "ADD", 18605 argLen: 2, 18606 commutative: true, 18607 clobberFlags: true, 18608 asm: s390x.AADD, 18609 reg: regInfo{ 18610 inputs: []inputInfo{ 18611 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18612 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18613 }, 18614 outputs: []outputInfo{ 18615 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18616 }, 18617 }, 18618 }, 18619 { 18620 name: "ADDW", 18621 argLen: 2, 18622 commutative: true, 18623 clobberFlags: true, 18624 asm: s390x.AADDW, 18625 reg: regInfo{ 18626 inputs: []inputInfo{ 18627 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18628 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18629 }, 18630 outputs: []outputInfo{ 18631 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18632 }, 18633 }, 18634 }, 18635 { 18636 name: "ADDconst", 18637 auxType: auxInt64, 18638 argLen: 1, 18639 clobberFlags: true, 18640 asm: s390x.AADD, 18641 reg: regInfo{ 18642 inputs: []inputInfo{ 18643 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18644 }, 18645 outputs: []outputInfo{ 18646 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18647 }, 18648 }, 18649 }, 18650 { 18651 name: "ADDWconst", 18652 auxType: auxInt32, 18653 argLen: 1, 18654 clobberFlags: true, 18655 asm: s390x.AADDW, 18656 reg: regInfo{ 18657 inputs: []inputInfo{ 18658 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18659 }, 18660 outputs: []outputInfo{ 18661 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18662 }, 18663 }, 18664 }, 18665 { 18666 name: "ADDload", 18667 auxType: auxSymOff, 18668 argLen: 3, 18669 resultInArg0: true, 18670 clobberFlags: true, 18671 faultOnNilArg1: true, 18672 symEffect: SymRead, 18673 asm: s390x.AADD, 18674 reg: regInfo{ 18675 inputs: []inputInfo{ 18676 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18677 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18678 }, 18679 outputs: []outputInfo{ 18680 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18681 }, 18682 }, 18683 }, 18684 { 18685 name: "ADDWload", 18686 auxType: auxSymOff, 18687 argLen: 3, 18688 resultInArg0: true, 18689 clobberFlags: true, 18690 faultOnNilArg1: true, 18691 symEffect: SymRead, 18692 asm: s390x.AADDW, 18693 reg: regInfo{ 18694 inputs: []inputInfo{ 18695 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18696 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18697 }, 18698 outputs: []outputInfo{ 18699 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18700 }, 18701 }, 18702 }, 18703 { 18704 name: "SUB", 18705 argLen: 2, 18706 clobberFlags: true, 18707 asm: s390x.ASUB, 18708 reg: regInfo{ 18709 inputs: []inputInfo{ 18710 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18711 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18712 }, 18713 outputs: []outputInfo{ 18714 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18715 }, 18716 }, 18717 }, 18718 { 18719 name: "SUBW", 18720 argLen: 2, 18721 clobberFlags: true, 18722 asm: s390x.ASUBW, 18723 reg: regInfo{ 18724 inputs: []inputInfo{ 18725 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18726 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18727 }, 18728 outputs: []outputInfo{ 18729 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18730 }, 18731 }, 18732 }, 18733 { 18734 name: "SUBconst", 18735 auxType: auxInt64, 18736 argLen: 1, 18737 resultInArg0: true, 18738 clobberFlags: true, 18739 asm: s390x.ASUB, 18740 reg: regInfo{ 18741 inputs: []inputInfo{ 18742 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18743 }, 18744 outputs: []outputInfo{ 18745 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18746 }, 18747 }, 18748 }, 18749 { 18750 name: "SUBWconst", 18751 auxType: auxInt32, 18752 argLen: 1, 18753 resultInArg0: true, 18754 clobberFlags: true, 18755 asm: s390x.ASUBW, 18756 reg: regInfo{ 18757 inputs: []inputInfo{ 18758 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18759 }, 18760 outputs: []outputInfo{ 18761 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18762 }, 18763 }, 18764 }, 18765 { 18766 name: "SUBload", 18767 auxType: auxSymOff, 18768 argLen: 3, 18769 resultInArg0: true, 18770 clobberFlags: true, 18771 faultOnNilArg1: true, 18772 symEffect: SymRead, 18773 asm: s390x.ASUB, 18774 reg: regInfo{ 18775 inputs: []inputInfo{ 18776 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18777 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18778 }, 18779 outputs: []outputInfo{ 18780 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18781 }, 18782 }, 18783 }, 18784 { 18785 name: "SUBWload", 18786 auxType: auxSymOff, 18787 argLen: 3, 18788 resultInArg0: true, 18789 clobberFlags: true, 18790 faultOnNilArg1: true, 18791 symEffect: SymRead, 18792 asm: s390x.ASUBW, 18793 reg: regInfo{ 18794 inputs: []inputInfo{ 18795 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18796 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18797 }, 18798 outputs: []outputInfo{ 18799 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18800 }, 18801 }, 18802 }, 18803 { 18804 name: "MULLD", 18805 argLen: 2, 18806 commutative: true, 18807 resultInArg0: true, 18808 clobberFlags: true, 18809 asm: s390x.AMULLD, 18810 reg: regInfo{ 18811 inputs: []inputInfo{ 18812 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18813 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18814 }, 18815 outputs: []outputInfo{ 18816 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18817 }, 18818 }, 18819 }, 18820 { 18821 name: "MULLW", 18822 argLen: 2, 18823 commutative: true, 18824 resultInArg0: true, 18825 clobberFlags: true, 18826 asm: s390x.AMULLW, 18827 reg: regInfo{ 18828 inputs: []inputInfo{ 18829 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18830 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18831 }, 18832 outputs: []outputInfo{ 18833 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18834 }, 18835 }, 18836 }, 18837 { 18838 name: "MULLDconst", 18839 auxType: auxInt64, 18840 argLen: 1, 18841 resultInArg0: true, 18842 clobberFlags: true, 18843 asm: s390x.AMULLD, 18844 reg: regInfo{ 18845 inputs: []inputInfo{ 18846 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18847 }, 18848 outputs: []outputInfo{ 18849 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18850 }, 18851 }, 18852 }, 18853 { 18854 name: "MULLWconst", 18855 auxType: auxInt32, 18856 argLen: 1, 18857 resultInArg0: true, 18858 clobberFlags: true, 18859 asm: s390x.AMULLW, 18860 reg: regInfo{ 18861 inputs: []inputInfo{ 18862 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18863 }, 18864 outputs: []outputInfo{ 18865 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18866 }, 18867 }, 18868 }, 18869 { 18870 name: "MULLDload", 18871 auxType: auxSymOff, 18872 argLen: 3, 18873 resultInArg0: true, 18874 clobberFlags: true, 18875 faultOnNilArg1: true, 18876 symEffect: SymRead, 18877 asm: s390x.AMULLD, 18878 reg: regInfo{ 18879 inputs: []inputInfo{ 18880 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18881 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18882 }, 18883 outputs: []outputInfo{ 18884 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18885 }, 18886 }, 18887 }, 18888 { 18889 name: "MULLWload", 18890 auxType: auxSymOff, 18891 argLen: 3, 18892 resultInArg0: true, 18893 clobberFlags: true, 18894 faultOnNilArg1: true, 18895 symEffect: SymRead, 18896 asm: s390x.AMULLW, 18897 reg: regInfo{ 18898 inputs: []inputInfo{ 18899 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18900 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18901 }, 18902 outputs: []outputInfo{ 18903 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18904 }, 18905 }, 18906 }, 18907 { 18908 name: "MULHD", 18909 argLen: 2, 18910 commutative: true, 18911 resultInArg0: true, 18912 clobberFlags: true, 18913 asm: s390x.AMULHD, 18914 reg: regInfo{ 18915 inputs: []inputInfo{ 18916 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18917 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18918 }, 18919 outputs: []outputInfo{ 18920 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18921 }, 18922 }, 18923 }, 18924 { 18925 name: "MULHDU", 18926 argLen: 2, 18927 commutative: true, 18928 resultInArg0: true, 18929 clobberFlags: true, 18930 asm: s390x.AMULHDU, 18931 reg: regInfo{ 18932 inputs: []inputInfo{ 18933 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18934 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18935 }, 18936 outputs: []outputInfo{ 18937 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18938 }, 18939 }, 18940 }, 18941 { 18942 name: "DIVD", 18943 argLen: 2, 18944 resultInArg0: true, 18945 clobberFlags: true, 18946 asm: s390x.ADIVD, 18947 reg: regInfo{ 18948 inputs: []inputInfo{ 18949 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18950 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18951 }, 18952 outputs: []outputInfo{ 18953 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18954 }, 18955 }, 18956 }, 18957 { 18958 name: "DIVW", 18959 argLen: 2, 18960 resultInArg0: true, 18961 clobberFlags: true, 18962 asm: s390x.ADIVW, 18963 reg: regInfo{ 18964 inputs: []inputInfo{ 18965 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18966 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18967 }, 18968 outputs: []outputInfo{ 18969 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18970 }, 18971 }, 18972 }, 18973 { 18974 name: "DIVDU", 18975 argLen: 2, 18976 resultInArg0: true, 18977 clobberFlags: true, 18978 asm: s390x.ADIVDU, 18979 reg: regInfo{ 18980 inputs: []inputInfo{ 18981 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18982 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18983 }, 18984 outputs: []outputInfo{ 18985 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18986 }, 18987 }, 18988 }, 18989 { 18990 name: "DIVWU", 18991 argLen: 2, 18992 resultInArg0: true, 18993 clobberFlags: true, 18994 asm: s390x.ADIVWU, 18995 reg: regInfo{ 18996 inputs: []inputInfo{ 18997 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18998 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18999 }, 19000 outputs: []outputInfo{ 19001 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19002 }, 19003 }, 19004 }, 19005 { 19006 name: "MODD", 19007 argLen: 2, 19008 resultInArg0: true, 19009 clobberFlags: true, 19010 asm: s390x.AMODD, 19011 reg: regInfo{ 19012 inputs: []inputInfo{ 19013 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19014 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19015 }, 19016 outputs: []outputInfo{ 19017 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19018 }, 19019 }, 19020 }, 19021 { 19022 name: "MODW", 19023 argLen: 2, 19024 resultInArg0: true, 19025 clobberFlags: true, 19026 asm: s390x.AMODW, 19027 reg: regInfo{ 19028 inputs: []inputInfo{ 19029 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19030 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19031 }, 19032 outputs: []outputInfo{ 19033 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19034 }, 19035 }, 19036 }, 19037 { 19038 name: "MODDU", 19039 argLen: 2, 19040 resultInArg0: true, 19041 clobberFlags: true, 19042 asm: s390x.AMODDU, 19043 reg: regInfo{ 19044 inputs: []inputInfo{ 19045 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19046 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19047 }, 19048 outputs: []outputInfo{ 19049 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19050 }, 19051 }, 19052 }, 19053 { 19054 name: "MODWU", 19055 argLen: 2, 19056 resultInArg0: true, 19057 clobberFlags: true, 19058 asm: s390x.AMODWU, 19059 reg: regInfo{ 19060 inputs: []inputInfo{ 19061 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19062 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19063 }, 19064 outputs: []outputInfo{ 19065 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19066 }, 19067 }, 19068 }, 19069 { 19070 name: "AND", 19071 argLen: 2, 19072 commutative: true, 19073 clobberFlags: true, 19074 asm: s390x.AAND, 19075 reg: regInfo{ 19076 inputs: []inputInfo{ 19077 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19078 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19079 }, 19080 outputs: []outputInfo{ 19081 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19082 }, 19083 }, 19084 }, 19085 { 19086 name: "ANDW", 19087 argLen: 2, 19088 commutative: true, 19089 clobberFlags: true, 19090 asm: s390x.AANDW, 19091 reg: regInfo{ 19092 inputs: []inputInfo{ 19093 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19094 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19095 }, 19096 outputs: []outputInfo{ 19097 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19098 }, 19099 }, 19100 }, 19101 { 19102 name: "ANDconst", 19103 auxType: auxInt64, 19104 argLen: 1, 19105 resultInArg0: true, 19106 clobberFlags: true, 19107 asm: s390x.AAND, 19108 reg: regInfo{ 19109 inputs: []inputInfo{ 19110 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19111 }, 19112 outputs: []outputInfo{ 19113 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19114 }, 19115 }, 19116 }, 19117 { 19118 name: "ANDWconst", 19119 auxType: auxInt32, 19120 argLen: 1, 19121 resultInArg0: true, 19122 clobberFlags: true, 19123 asm: s390x.AANDW, 19124 reg: regInfo{ 19125 inputs: []inputInfo{ 19126 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19127 }, 19128 outputs: []outputInfo{ 19129 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19130 }, 19131 }, 19132 }, 19133 { 19134 name: "ANDload", 19135 auxType: auxSymOff, 19136 argLen: 3, 19137 resultInArg0: true, 19138 clobberFlags: true, 19139 faultOnNilArg1: true, 19140 symEffect: SymRead, 19141 asm: s390x.AAND, 19142 reg: regInfo{ 19143 inputs: []inputInfo{ 19144 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19145 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19146 }, 19147 outputs: []outputInfo{ 19148 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19149 }, 19150 }, 19151 }, 19152 { 19153 name: "ANDWload", 19154 auxType: auxSymOff, 19155 argLen: 3, 19156 resultInArg0: true, 19157 clobberFlags: true, 19158 faultOnNilArg1: true, 19159 symEffect: SymRead, 19160 asm: s390x.AANDW, 19161 reg: regInfo{ 19162 inputs: []inputInfo{ 19163 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19164 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19165 }, 19166 outputs: []outputInfo{ 19167 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19168 }, 19169 }, 19170 }, 19171 { 19172 name: "OR", 19173 argLen: 2, 19174 commutative: true, 19175 clobberFlags: true, 19176 asm: s390x.AOR, 19177 reg: regInfo{ 19178 inputs: []inputInfo{ 19179 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19180 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19181 }, 19182 outputs: []outputInfo{ 19183 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19184 }, 19185 }, 19186 }, 19187 { 19188 name: "ORW", 19189 argLen: 2, 19190 commutative: true, 19191 clobberFlags: true, 19192 asm: s390x.AORW, 19193 reg: regInfo{ 19194 inputs: []inputInfo{ 19195 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19196 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19197 }, 19198 outputs: []outputInfo{ 19199 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19200 }, 19201 }, 19202 }, 19203 { 19204 name: "ORconst", 19205 auxType: auxInt64, 19206 argLen: 1, 19207 resultInArg0: true, 19208 clobberFlags: true, 19209 asm: s390x.AOR, 19210 reg: regInfo{ 19211 inputs: []inputInfo{ 19212 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19213 }, 19214 outputs: []outputInfo{ 19215 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19216 }, 19217 }, 19218 }, 19219 { 19220 name: "ORWconst", 19221 auxType: auxInt32, 19222 argLen: 1, 19223 resultInArg0: true, 19224 clobberFlags: true, 19225 asm: s390x.AORW, 19226 reg: regInfo{ 19227 inputs: []inputInfo{ 19228 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19229 }, 19230 outputs: []outputInfo{ 19231 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19232 }, 19233 }, 19234 }, 19235 { 19236 name: "ORload", 19237 auxType: auxSymOff, 19238 argLen: 3, 19239 resultInArg0: true, 19240 clobberFlags: true, 19241 faultOnNilArg1: true, 19242 symEffect: SymRead, 19243 asm: s390x.AOR, 19244 reg: regInfo{ 19245 inputs: []inputInfo{ 19246 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19247 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19248 }, 19249 outputs: []outputInfo{ 19250 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19251 }, 19252 }, 19253 }, 19254 { 19255 name: "ORWload", 19256 auxType: auxSymOff, 19257 argLen: 3, 19258 resultInArg0: true, 19259 clobberFlags: true, 19260 faultOnNilArg1: true, 19261 symEffect: SymRead, 19262 asm: s390x.AORW, 19263 reg: regInfo{ 19264 inputs: []inputInfo{ 19265 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19266 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19267 }, 19268 outputs: []outputInfo{ 19269 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19270 }, 19271 }, 19272 }, 19273 { 19274 name: "XOR", 19275 argLen: 2, 19276 commutative: true, 19277 clobberFlags: true, 19278 asm: s390x.AXOR, 19279 reg: regInfo{ 19280 inputs: []inputInfo{ 19281 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19282 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19283 }, 19284 outputs: []outputInfo{ 19285 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19286 }, 19287 }, 19288 }, 19289 { 19290 name: "XORW", 19291 argLen: 2, 19292 commutative: true, 19293 clobberFlags: true, 19294 asm: s390x.AXORW, 19295 reg: regInfo{ 19296 inputs: []inputInfo{ 19297 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19298 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19299 }, 19300 outputs: []outputInfo{ 19301 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19302 }, 19303 }, 19304 }, 19305 { 19306 name: "XORconst", 19307 auxType: auxInt64, 19308 argLen: 1, 19309 resultInArg0: true, 19310 clobberFlags: true, 19311 asm: s390x.AXOR, 19312 reg: regInfo{ 19313 inputs: []inputInfo{ 19314 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19315 }, 19316 outputs: []outputInfo{ 19317 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19318 }, 19319 }, 19320 }, 19321 { 19322 name: "XORWconst", 19323 auxType: auxInt32, 19324 argLen: 1, 19325 resultInArg0: true, 19326 clobberFlags: true, 19327 asm: s390x.AXORW, 19328 reg: regInfo{ 19329 inputs: []inputInfo{ 19330 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19331 }, 19332 outputs: []outputInfo{ 19333 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19334 }, 19335 }, 19336 }, 19337 { 19338 name: "XORload", 19339 auxType: auxSymOff, 19340 argLen: 3, 19341 resultInArg0: true, 19342 clobberFlags: true, 19343 faultOnNilArg1: true, 19344 symEffect: SymRead, 19345 asm: s390x.AXOR, 19346 reg: regInfo{ 19347 inputs: []inputInfo{ 19348 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19349 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19350 }, 19351 outputs: []outputInfo{ 19352 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19353 }, 19354 }, 19355 }, 19356 { 19357 name: "XORWload", 19358 auxType: auxSymOff, 19359 argLen: 3, 19360 resultInArg0: true, 19361 clobberFlags: true, 19362 faultOnNilArg1: true, 19363 symEffect: SymRead, 19364 asm: s390x.AXORW, 19365 reg: regInfo{ 19366 inputs: []inputInfo{ 19367 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19368 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19369 }, 19370 outputs: []outputInfo{ 19371 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19372 }, 19373 }, 19374 }, 19375 { 19376 name: "CMP", 19377 argLen: 2, 19378 asm: s390x.ACMP, 19379 reg: regInfo{ 19380 inputs: []inputInfo{ 19381 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19382 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19383 }, 19384 }, 19385 }, 19386 { 19387 name: "CMPW", 19388 argLen: 2, 19389 asm: s390x.ACMPW, 19390 reg: regInfo{ 19391 inputs: []inputInfo{ 19392 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19393 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19394 }, 19395 }, 19396 }, 19397 { 19398 name: "CMPU", 19399 argLen: 2, 19400 asm: s390x.ACMPU, 19401 reg: regInfo{ 19402 inputs: []inputInfo{ 19403 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19404 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19405 }, 19406 }, 19407 }, 19408 { 19409 name: "CMPWU", 19410 argLen: 2, 19411 asm: s390x.ACMPWU, 19412 reg: regInfo{ 19413 inputs: []inputInfo{ 19414 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19415 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19416 }, 19417 }, 19418 }, 19419 { 19420 name: "CMPconst", 19421 auxType: auxInt64, 19422 argLen: 1, 19423 asm: s390x.ACMP, 19424 reg: regInfo{ 19425 inputs: []inputInfo{ 19426 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19427 }, 19428 }, 19429 }, 19430 { 19431 name: "CMPWconst", 19432 auxType: auxInt32, 19433 argLen: 1, 19434 asm: s390x.ACMPW, 19435 reg: regInfo{ 19436 inputs: []inputInfo{ 19437 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19438 }, 19439 }, 19440 }, 19441 { 19442 name: "CMPUconst", 19443 auxType: auxInt64, 19444 argLen: 1, 19445 asm: s390x.ACMPU, 19446 reg: regInfo{ 19447 inputs: []inputInfo{ 19448 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19449 }, 19450 }, 19451 }, 19452 { 19453 name: "CMPWUconst", 19454 auxType: auxInt32, 19455 argLen: 1, 19456 asm: s390x.ACMPWU, 19457 reg: regInfo{ 19458 inputs: []inputInfo{ 19459 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19460 }, 19461 }, 19462 }, 19463 { 19464 name: "FCMPS", 19465 argLen: 2, 19466 asm: s390x.ACEBR, 19467 reg: regInfo{ 19468 inputs: []inputInfo{ 19469 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19470 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19471 }, 19472 }, 19473 }, 19474 { 19475 name: "FCMP", 19476 argLen: 2, 19477 asm: s390x.AFCMPU, 19478 reg: regInfo{ 19479 inputs: []inputInfo{ 19480 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19481 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19482 }, 19483 }, 19484 }, 19485 { 19486 name: "SLD", 19487 argLen: 2, 19488 asm: s390x.ASLD, 19489 reg: regInfo{ 19490 inputs: []inputInfo{ 19491 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19492 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19493 }, 19494 outputs: []outputInfo{ 19495 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19496 }, 19497 }, 19498 }, 19499 { 19500 name: "SLW", 19501 argLen: 2, 19502 asm: s390x.ASLW, 19503 reg: regInfo{ 19504 inputs: []inputInfo{ 19505 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19506 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19507 }, 19508 outputs: []outputInfo{ 19509 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19510 }, 19511 }, 19512 }, 19513 { 19514 name: "SLDconst", 19515 auxType: auxInt8, 19516 argLen: 1, 19517 asm: s390x.ASLD, 19518 reg: regInfo{ 19519 inputs: []inputInfo{ 19520 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19521 }, 19522 outputs: []outputInfo{ 19523 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19524 }, 19525 }, 19526 }, 19527 { 19528 name: "SLWconst", 19529 auxType: auxInt8, 19530 argLen: 1, 19531 asm: s390x.ASLW, 19532 reg: regInfo{ 19533 inputs: []inputInfo{ 19534 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19535 }, 19536 outputs: []outputInfo{ 19537 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19538 }, 19539 }, 19540 }, 19541 { 19542 name: "SRD", 19543 argLen: 2, 19544 asm: s390x.ASRD, 19545 reg: regInfo{ 19546 inputs: []inputInfo{ 19547 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19548 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19549 }, 19550 outputs: []outputInfo{ 19551 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19552 }, 19553 }, 19554 }, 19555 { 19556 name: "SRW", 19557 argLen: 2, 19558 asm: s390x.ASRW, 19559 reg: regInfo{ 19560 inputs: []inputInfo{ 19561 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19562 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19563 }, 19564 outputs: []outputInfo{ 19565 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19566 }, 19567 }, 19568 }, 19569 { 19570 name: "SRDconst", 19571 auxType: auxInt8, 19572 argLen: 1, 19573 asm: s390x.ASRD, 19574 reg: regInfo{ 19575 inputs: []inputInfo{ 19576 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19577 }, 19578 outputs: []outputInfo{ 19579 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19580 }, 19581 }, 19582 }, 19583 { 19584 name: "SRWconst", 19585 auxType: auxInt8, 19586 argLen: 1, 19587 asm: s390x.ASRW, 19588 reg: regInfo{ 19589 inputs: []inputInfo{ 19590 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19591 }, 19592 outputs: []outputInfo{ 19593 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19594 }, 19595 }, 19596 }, 19597 { 19598 name: "SRAD", 19599 argLen: 2, 19600 clobberFlags: true, 19601 asm: s390x.ASRAD, 19602 reg: regInfo{ 19603 inputs: []inputInfo{ 19604 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19605 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19606 }, 19607 outputs: []outputInfo{ 19608 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19609 }, 19610 }, 19611 }, 19612 { 19613 name: "SRAW", 19614 argLen: 2, 19615 clobberFlags: true, 19616 asm: s390x.ASRAW, 19617 reg: regInfo{ 19618 inputs: []inputInfo{ 19619 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19620 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19621 }, 19622 outputs: []outputInfo{ 19623 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19624 }, 19625 }, 19626 }, 19627 { 19628 name: "SRADconst", 19629 auxType: auxInt8, 19630 argLen: 1, 19631 clobberFlags: true, 19632 asm: s390x.ASRAD, 19633 reg: regInfo{ 19634 inputs: []inputInfo{ 19635 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19636 }, 19637 outputs: []outputInfo{ 19638 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19639 }, 19640 }, 19641 }, 19642 { 19643 name: "SRAWconst", 19644 auxType: auxInt8, 19645 argLen: 1, 19646 clobberFlags: true, 19647 asm: s390x.ASRAW, 19648 reg: regInfo{ 19649 inputs: []inputInfo{ 19650 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19651 }, 19652 outputs: []outputInfo{ 19653 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19654 }, 19655 }, 19656 }, 19657 { 19658 name: "RLLGconst", 19659 auxType: auxInt8, 19660 argLen: 1, 19661 asm: s390x.ARLLG, 19662 reg: regInfo{ 19663 inputs: []inputInfo{ 19664 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19665 }, 19666 outputs: []outputInfo{ 19667 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19668 }, 19669 }, 19670 }, 19671 { 19672 name: "RLLconst", 19673 auxType: auxInt8, 19674 argLen: 1, 19675 asm: s390x.ARLL, 19676 reg: regInfo{ 19677 inputs: []inputInfo{ 19678 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19679 }, 19680 outputs: []outputInfo{ 19681 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19682 }, 19683 }, 19684 }, 19685 { 19686 name: "NEG", 19687 argLen: 1, 19688 clobberFlags: true, 19689 asm: s390x.ANEG, 19690 reg: regInfo{ 19691 inputs: []inputInfo{ 19692 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19693 }, 19694 outputs: []outputInfo{ 19695 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19696 }, 19697 }, 19698 }, 19699 { 19700 name: "NEGW", 19701 argLen: 1, 19702 clobberFlags: true, 19703 asm: s390x.ANEGW, 19704 reg: regInfo{ 19705 inputs: []inputInfo{ 19706 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19707 }, 19708 outputs: []outputInfo{ 19709 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19710 }, 19711 }, 19712 }, 19713 { 19714 name: "NOT", 19715 argLen: 1, 19716 resultInArg0: true, 19717 clobberFlags: true, 19718 reg: regInfo{ 19719 inputs: []inputInfo{ 19720 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19721 }, 19722 outputs: []outputInfo{ 19723 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19724 }, 19725 }, 19726 }, 19727 { 19728 name: "NOTW", 19729 argLen: 1, 19730 resultInArg0: true, 19731 clobberFlags: true, 19732 reg: regInfo{ 19733 inputs: []inputInfo{ 19734 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19735 }, 19736 outputs: []outputInfo{ 19737 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19738 }, 19739 }, 19740 }, 19741 { 19742 name: "FSQRT", 19743 argLen: 1, 19744 asm: s390x.AFSQRT, 19745 reg: regInfo{ 19746 inputs: []inputInfo{ 19747 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19748 }, 19749 outputs: []outputInfo{ 19750 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19751 }, 19752 }, 19753 }, 19754 { 19755 name: "SUBEcarrymask", 19756 argLen: 1, 19757 asm: s390x.ASUBE, 19758 reg: regInfo{ 19759 outputs: []outputInfo{ 19760 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19761 }, 19762 }, 19763 }, 19764 { 19765 name: "SUBEWcarrymask", 19766 argLen: 1, 19767 asm: s390x.ASUBE, 19768 reg: regInfo{ 19769 outputs: []outputInfo{ 19770 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19771 }, 19772 }, 19773 }, 19774 { 19775 name: "MOVDEQ", 19776 argLen: 3, 19777 resultInArg0: true, 19778 asm: s390x.AMOVDEQ, 19779 reg: regInfo{ 19780 inputs: []inputInfo{ 19781 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19782 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19783 }, 19784 outputs: []outputInfo{ 19785 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19786 }, 19787 }, 19788 }, 19789 { 19790 name: "MOVDNE", 19791 argLen: 3, 19792 resultInArg0: true, 19793 asm: s390x.AMOVDNE, 19794 reg: regInfo{ 19795 inputs: []inputInfo{ 19796 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19797 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19798 }, 19799 outputs: []outputInfo{ 19800 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19801 }, 19802 }, 19803 }, 19804 { 19805 name: "MOVDLT", 19806 argLen: 3, 19807 resultInArg0: true, 19808 asm: s390x.AMOVDLT, 19809 reg: regInfo{ 19810 inputs: []inputInfo{ 19811 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19812 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19813 }, 19814 outputs: []outputInfo{ 19815 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19816 }, 19817 }, 19818 }, 19819 { 19820 name: "MOVDLE", 19821 argLen: 3, 19822 resultInArg0: true, 19823 asm: s390x.AMOVDLE, 19824 reg: regInfo{ 19825 inputs: []inputInfo{ 19826 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19827 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19828 }, 19829 outputs: []outputInfo{ 19830 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19831 }, 19832 }, 19833 }, 19834 { 19835 name: "MOVDGT", 19836 argLen: 3, 19837 resultInArg0: true, 19838 asm: s390x.AMOVDGT, 19839 reg: regInfo{ 19840 inputs: []inputInfo{ 19841 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19842 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19843 }, 19844 outputs: []outputInfo{ 19845 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19846 }, 19847 }, 19848 }, 19849 { 19850 name: "MOVDGE", 19851 argLen: 3, 19852 resultInArg0: true, 19853 asm: s390x.AMOVDGE, 19854 reg: regInfo{ 19855 inputs: []inputInfo{ 19856 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19857 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19858 }, 19859 outputs: []outputInfo{ 19860 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19861 }, 19862 }, 19863 }, 19864 { 19865 name: "MOVDGTnoinv", 19866 argLen: 3, 19867 resultInArg0: true, 19868 asm: s390x.AMOVDGT, 19869 reg: regInfo{ 19870 inputs: []inputInfo{ 19871 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19872 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19873 }, 19874 outputs: []outputInfo{ 19875 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19876 }, 19877 }, 19878 }, 19879 { 19880 name: "MOVDGEnoinv", 19881 argLen: 3, 19882 resultInArg0: true, 19883 asm: s390x.AMOVDGE, 19884 reg: regInfo{ 19885 inputs: []inputInfo{ 19886 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19887 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19888 }, 19889 outputs: []outputInfo{ 19890 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19891 }, 19892 }, 19893 }, 19894 { 19895 name: "MOVBreg", 19896 argLen: 1, 19897 asm: s390x.AMOVB, 19898 reg: regInfo{ 19899 inputs: []inputInfo{ 19900 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19901 }, 19902 outputs: []outputInfo{ 19903 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19904 }, 19905 }, 19906 }, 19907 { 19908 name: "MOVBZreg", 19909 argLen: 1, 19910 asm: s390x.AMOVBZ, 19911 reg: regInfo{ 19912 inputs: []inputInfo{ 19913 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19914 }, 19915 outputs: []outputInfo{ 19916 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19917 }, 19918 }, 19919 }, 19920 { 19921 name: "MOVHreg", 19922 argLen: 1, 19923 asm: s390x.AMOVH, 19924 reg: regInfo{ 19925 inputs: []inputInfo{ 19926 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19927 }, 19928 outputs: []outputInfo{ 19929 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19930 }, 19931 }, 19932 }, 19933 { 19934 name: "MOVHZreg", 19935 argLen: 1, 19936 asm: s390x.AMOVHZ, 19937 reg: regInfo{ 19938 inputs: []inputInfo{ 19939 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19940 }, 19941 outputs: []outputInfo{ 19942 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19943 }, 19944 }, 19945 }, 19946 { 19947 name: "MOVWreg", 19948 argLen: 1, 19949 asm: s390x.AMOVW, 19950 reg: regInfo{ 19951 inputs: []inputInfo{ 19952 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19953 }, 19954 outputs: []outputInfo{ 19955 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19956 }, 19957 }, 19958 }, 19959 { 19960 name: "MOVWZreg", 19961 argLen: 1, 19962 asm: s390x.AMOVWZ, 19963 reg: regInfo{ 19964 inputs: []inputInfo{ 19965 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19966 }, 19967 outputs: []outputInfo{ 19968 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19969 }, 19970 }, 19971 }, 19972 { 19973 name: "MOVDreg", 19974 argLen: 1, 19975 asm: s390x.AMOVD, 19976 reg: regInfo{ 19977 inputs: []inputInfo{ 19978 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19979 }, 19980 outputs: []outputInfo{ 19981 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19982 }, 19983 }, 19984 }, 19985 { 19986 name: "MOVDnop", 19987 argLen: 1, 19988 resultInArg0: true, 19989 reg: regInfo{ 19990 inputs: []inputInfo{ 19991 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19992 }, 19993 outputs: []outputInfo{ 19994 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19995 }, 19996 }, 19997 }, 19998 { 19999 name: "MOVDconst", 20000 auxType: auxInt64, 20001 argLen: 0, 20002 rematerializeable: true, 20003 asm: s390x.AMOVD, 20004 reg: regInfo{ 20005 outputs: []outputInfo{ 20006 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20007 }, 20008 }, 20009 }, 20010 { 20011 name: "CFDBRA", 20012 argLen: 1, 20013 asm: s390x.ACFDBRA, 20014 reg: regInfo{ 20015 inputs: []inputInfo{ 20016 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20017 }, 20018 outputs: []outputInfo{ 20019 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20020 }, 20021 }, 20022 }, 20023 { 20024 name: "CGDBRA", 20025 argLen: 1, 20026 asm: s390x.ACGDBRA, 20027 reg: regInfo{ 20028 inputs: []inputInfo{ 20029 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20030 }, 20031 outputs: []outputInfo{ 20032 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20033 }, 20034 }, 20035 }, 20036 { 20037 name: "CFEBRA", 20038 argLen: 1, 20039 asm: s390x.ACFEBRA, 20040 reg: regInfo{ 20041 inputs: []inputInfo{ 20042 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20043 }, 20044 outputs: []outputInfo{ 20045 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20046 }, 20047 }, 20048 }, 20049 { 20050 name: "CGEBRA", 20051 argLen: 1, 20052 asm: s390x.ACGEBRA, 20053 reg: regInfo{ 20054 inputs: []inputInfo{ 20055 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20056 }, 20057 outputs: []outputInfo{ 20058 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20059 }, 20060 }, 20061 }, 20062 { 20063 name: "CEFBRA", 20064 argLen: 1, 20065 asm: s390x.ACEFBRA, 20066 reg: regInfo{ 20067 inputs: []inputInfo{ 20068 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20069 }, 20070 outputs: []outputInfo{ 20071 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20072 }, 20073 }, 20074 }, 20075 { 20076 name: "CDFBRA", 20077 argLen: 1, 20078 asm: s390x.ACDFBRA, 20079 reg: regInfo{ 20080 inputs: []inputInfo{ 20081 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20082 }, 20083 outputs: []outputInfo{ 20084 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20085 }, 20086 }, 20087 }, 20088 { 20089 name: "CEGBRA", 20090 argLen: 1, 20091 asm: s390x.ACEGBRA, 20092 reg: regInfo{ 20093 inputs: []inputInfo{ 20094 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20095 }, 20096 outputs: []outputInfo{ 20097 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20098 }, 20099 }, 20100 }, 20101 { 20102 name: "CDGBRA", 20103 argLen: 1, 20104 asm: s390x.ACDGBRA, 20105 reg: regInfo{ 20106 inputs: []inputInfo{ 20107 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20108 }, 20109 outputs: []outputInfo{ 20110 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20111 }, 20112 }, 20113 }, 20114 { 20115 name: "LEDBR", 20116 argLen: 1, 20117 asm: s390x.ALEDBR, 20118 reg: regInfo{ 20119 inputs: []inputInfo{ 20120 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20121 }, 20122 outputs: []outputInfo{ 20123 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20124 }, 20125 }, 20126 }, 20127 { 20128 name: "LDEBR", 20129 argLen: 1, 20130 asm: s390x.ALDEBR, 20131 reg: regInfo{ 20132 inputs: []inputInfo{ 20133 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20134 }, 20135 outputs: []outputInfo{ 20136 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20137 }, 20138 }, 20139 }, 20140 { 20141 name: "MOVDaddr", 20142 auxType: auxSymOff, 20143 argLen: 1, 20144 rematerializeable: true, 20145 clobberFlags: true, 20146 symEffect: SymRead, 20147 reg: regInfo{ 20148 inputs: []inputInfo{ 20149 {0, 4295000064}, // SP SB 20150 }, 20151 outputs: []outputInfo{ 20152 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20153 }, 20154 }, 20155 }, 20156 { 20157 name: "MOVDaddridx", 20158 auxType: auxSymOff, 20159 argLen: 2, 20160 clobberFlags: true, 20161 symEffect: SymRead, 20162 reg: regInfo{ 20163 inputs: []inputInfo{ 20164 {0, 4295000064}, // SP SB 20165 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20166 }, 20167 outputs: []outputInfo{ 20168 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20169 }, 20170 }, 20171 }, 20172 { 20173 name: "MOVBZload", 20174 auxType: auxSymOff, 20175 argLen: 2, 20176 clobberFlags: true, 20177 faultOnNilArg0: true, 20178 symEffect: SymRead, 20179 asm: s390x.AMOVBZ, 20180 reg: regInfo{ 20181 inputs: []inputInfo{ 20182 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20183 }, 20184 outputs: []outputInfo{ 20185 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20186 }, 20187 }, 20188 }, 20189 { 20190 name: "MOVBload", 20191 auxType: auxSymOff, 20192 argLen: 2, 20193 clobberFlags: true, 20194 faultOnNilArg0: true, 20195 symEffect: SymRead, 20196 asm: s390x.AMOVB, 20197 reg: regInfo{ 20198 inputs: []inputInfo{ 20199 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20200 }, 20201 outputs: []outputInfo{ 20202 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20203 }, 20204 }, 20205 }, 20206 { 20207 name: "MOVHZload", 20208 auxType: auxSymOff, 20209 argLen: 2, 20210 clobberFlags: true, 20211 faultOnNilArg0: true, 20212 symEffect: SymRead, 20213 asm: s390x.AMOVHZ, 20214 reg: regInfo{ 20215 inputs: []inputInfo{ 20216 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20217 }, 20218 outputs: []outputInfo{ 20219 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20220 }, 20221 }, 20222 }, 20223 { 20224 name: "MOVHload", 20225 auxType: auxSymOff, 20226 argLen: 2, 20227 clobberFlags: true, 20228 faultOnNilArg0: true, 20229 symEffect: SymRead, 20230 asm: s390x.AMOVH, 20231 reg: regInfo{ 20232 inputs: []inputInfo{ 20233 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20234 }, 20235 outputs: []outputInfo{ 20236 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20237 }, 20238 }, 20239 }, 20240 { 20241 name: "MOVWZload", 20242 auxType: auxSymOff, 20243 argLen: 2, 20244 clobberFlags: true, 20245 faultOnNilArg0: true, 20246 symEffect: SymRead, 20247 asm: s390x.AMOVWZ, 20248 reg: regInfo{ 20249 inputs: []inputInfo{ 20250 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20251 }, 20252 outputs: []outputInfo{ 20253 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20254 }, 20255 }, 20256 }, 20257 { 20258 name: "MOVWload", 20259 auxType: auxSymOff, 20260 argLen: 2, 20261 clobberFlags: true, 20262 faultOnNilArg0: true, 20263 symEffect: SymRead, 20264 asm: s390x.AMOVW, 20265 reg: regInfo{ 20266 inputs: []inputInfo{ 20267 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20268 }, 20269 outputs: []outputInfo{ 20270 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20271 }, 20272 }, 20273 }, 20274 { 20275 name: "MOVDload", 20276 auxType: auxSymOff, 20277 argLen: 2, 20278 clobberFlags: true, 20279 faultOnNilArg0: true, 20280 symEffect: SymRead, 20281 asm: s390x.AMOVD, 20282 reg: regInfo{ 20283 inputs: []inputInfo{ 20284 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20285 }, 20286 outputs: []outputInfo{ 20287 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20288 }, 20289 }, 20290 }, 20291 { 20292 name: "MOVWBR", 20293 argLen: 1, 20294 asm: s390x.AMOVWBR, 20295 reg: regInfo{ 20296 inputs: []inputInfo{ 20297 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20298 }, 20299 outputs: []outputInfo{ 20300 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20301 }, 20302 }, 20303 }, 20304 { 20305 name: "MOVDBR", 20306 argLen: 1, 20307 asm: s390x.AMOVDBR, 20308 reg: regInfo{ 20309 inputs: []inputInfo{ 20310 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20311 }, 20312 outputs: []outputInfo{ 20313 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20314 }, 20315 }, 20316 }, 20317 { 20318 name: "MOVHBRload", 20319 auxType: auxSymOff, 20320 argLen: 2, 20321 clobberFlags: true, 20322 faultOnNilArg0: true, 20323 symEffect: SymRead, 20324 asm: s390x.AMOVHBR, 20325 reg: regInfo{ 20326 inputs: []inputInfo{ 20327 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20328 }, 20329 outputs: []outputInfo{ 20330 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20331 }, 20332 }, 20333 }, 20334 { 20335 name: "MOVWBRload", 20336 auxType: auxSymOff, 20337 argLen: 2, 20338 clobberFlags: true, 20339 faultOnNilArg0: true, 20340 symEffect: SymRead, 20341 asm: s390x.AMOVWBR, 20342 reg: regInfo{ 20343 inputs: []inputInfo{ 20344 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20345 }, 20346 outputs: []outputInfo{ 20347 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20348 }, 20349 }, 20350 }, 20351 { 20352 name: "MOVDBRload", 20353 auxType: auxSymOff, 20354 argLen: 2, 20355 clobberFlags: true, 20356 faultOnNilArg0: true, 20357 symEffect: SymRead, 20358 asm: s390x.AMOVDBR, 20359 reg: regInfo{ 20360 inputs: []inputInfo{ 20361 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20362 }, 20363 outputs: []outputInfo{ 20364 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20365 }, 20366 }, 20367 }, 20368 { 20369 name: "MOVBstore", 20370 auxType: auxSymOff, 20371 argLen: 3, 20372 clobberFlags: true, 20373 faultOnNilArg0: true, 20374 symEffect: SymWrite, 20375 asm: s390x.AMOVB, 20376 reg: regInfo{ 20377 inputs: []inputInfo{ 20378 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20379 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20380 }, 20381 }, 20382 }, 20383 { 20384 name: "MOVHstore", 20385 auxType: auxSymOff, 20386 argLen: 3, 20387 clobberFlags: true, 20388 faultOnNilArg0: true, 20389 symEffect: SymWrite, 20390 asm: s390x.AMOVH, 20391 reg: regInfo{ 20392 inputs: []inputInfo{ 20393 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20394 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20395 }, 20396 }, 20397 }, 20398 { 20399 name: "MOVWstore", 20400 auxType: auxSymOff, 20401 argLen: 3, 20402 clobberFlags: true, 20403 faultOnNilArg0: true, 20404 symEffect: SymWrite, 20405 asm: s390x.AMOVW, 20406 reg: regInfo{ 20407 inputs: []inputInfo{ 20408 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20409 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20410 }, 20411 }, 20412 }, 20413 { 20414 name: "MOVDstore", 20415 auxType: auxSymOff, 20416 argLen: 3, 20417 clobberFlags: true, 20418 faultOnNilArg0: true, 20419 symEffect: SymWrite, 20420 asm: s390x.AMOVD, 20421 reg: regInfo{ 20422 inputs: []inputInfo{ 20423 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20424 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20425 }, 20426 }, 20427 }, 20428 { 20429 name: "MOVHBRstore", 20430 auxType: auxSymOff, 20431 argLen: 3, 20432 clobberFlags: true, 20433 faultOnNilArg0: true, 20434 symEffect: SymWrite, 20435 asm: s390x.AMOVHBR, 20436 reg: regInfo{ 20437 inputs: []inputInfo{ 20438 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20439 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20440 }, 20441 }, 20442 }, 20443 { 20444 name: "MOVWBRstore", 20445 auxType: auxSymOff, 20446 argLen: 3, 20447 clobberFlags: true, 20448 faultOnNilArg0: true, 20449 symEffect: SymWrite, 20450 asm: s390x.AMOVWBR, 20451 reg: regInfo{ 20452 inputs: []inputInfo{ 20453 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20454 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20455 }, 20456 }, 20457 }, 20458 { 20459 name: "MOVDBRstore", 20460 auxType: auxSymOff, 20461 argLen: 3, 20462 clobberFlags: true, 20463 faultOnNilArg0: true, 20464 symEffect: SymWrite, 20465 asm: s390x.AMOVDBR, 20466 reg: regInfo{ 20467 inputs: []inputInfo{ 20468 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20469 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20470 }, 20471 }, 20472 }, 20473 { 20474 name: "MVC", 20475 auxType: auxSymValAndOff, 20476 argLen: 3, 20477 clobberFlags: true, 20478 faultOnNilArg0: true, 20479 faultOnNilArg1: true, 20480 symEffect: SymNone, 20481 asm: s390x.AMVC, 20482 reg: regInfo{ 20483 inputs: []inputInfo{ 20484 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20485 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20486 }, 20487 }, 20488 }, 20489 { 20490 name: "MOVBZloadidx", 20491 auxType: auxSymOff, 20492 argLen: 3, 20493 commutative: true, 20494 clobberFlags: true, 20495 symEffect: SymRead, 20496 asm: s390x.AMOVBZ, 20497 reg: regInfo{ 20498 inputs: []inputInfo{ 20499 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20500 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20501 }, 20502 outputs: []outputInfo{ 20503 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20504 }, 20505 }, 20506 }, 20507 { 20508 name: "MOVHZloadidx", 20509 auxType: auxSymOff, 20510 argLen: 3, 20511 commutative: true, 20512 clobberFlags: true, 20513 symEffect: SymRead, 20514 asm: s390x.AMOVHZ, 20515 reg: regInfo{ 20516 inputs: []inputInfo{ 20517 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20518 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20519 }, 20520 outputs: []outputInfo{ 20521 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20522 }, 20523 }, 20524 }, 20525 { 20526 name: "MOVWZloadidx", 20527 auxType: auxSymOff, 20528 argLen: 3, 20529 commutative: true, 20530 clobberFlags: true, 20531 symEffect: SymRead, 20532 asm: s390x.AMOVWZ, 20533 reg: regInfo{ 20534 inputs: []inputInfo{ 20535 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20536 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20537 }, 20538 outputs: []outputInfo{ 20539 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20540 }, 20541 }, 20542 }, 20543 { 20544 name: "MOVDloadidx", 20545 auxType: auxSymOff, 20546 argLen: 3, 20547 commutative: true, 20548 clobberFlags: true, 20549 symEffect: SymRead, 20550 asm: s390x.AMOVD, 20551 reg: regInfo{ 20552 inputs: []inputInfo{ 20553 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20554 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20555 }, 20556 outputs: []outputInfo{ 20557 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20558 }, 20559 }, 20560 }, 20561 { 20562 name: "MOVHBRloadidx", 20563 auxType: auxSymOff, 20564 argLen: 3, 20565 commutative: true, 20566 clobberFlags: true, 20567 symEffect: SymRead, 20568 asm: s390x.AMOVHBR, 20569 reg: regInfo{ 20570 inputs: []inputInfo{ 20571 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20572 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20573 }, 20574 outputs: []outputInfo{ 20575 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20576 }, 20577 }, 20578 }, 20579 { 20580 name: "MOVWBRloadidx", 20581 auxType: auxSymOff, 20582 argLen: 3, 20583 commutative: true, 20584 clobberFlags: true, 20585 symEffect: SymRead, 20586 asm: s390x.AMOVWBR, 20587 reg: regInfo{ 20588 inputs: []inputInfo{ 20589 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20590 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20591 }, 20592 outputs: []outputInfo{ 20593 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20594 }, 20595 }, 20596 }, 20597 { 20598 name: "MOVDBRloadidx", 20599 auxType: auxSymOff, 20600 argLen: 3, 20601 commutative: true, 20602 clobberFlags: true, 20603 symEffect: SymRead, 20604 asm: s390x.AMOVDBR, 20605 reg: regInfo{ 20606 inputs: []inputInfo{ 20607 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20608 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20609 }, 20610 outputs: []outputInfo{ 20611 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20612 }, 20613 }, 20614 }, 20615 { 20616 name: "MOVBstoreidx", 20617 auxType: auxSymOff, 20618 argLen: 4, 20619 commutative: true, 20620 clobberFlags: true, 20621 symEffect: SymWrite, 20622 asm: s390x.AMOVB, 20623 reg: regInfo{ 20624 inputs: []inputInfo{ 20625 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20626 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20627 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20628 }, 20629 }, 20630 }, 20631 { 20632 name: "MOVHstoreidx", 20633 auxType: auxSymOff, 20634 argLen: 4, 20635 commutative: true, 20636 clobberFlags: true, 20637 symEffect: SymWrite, 20638 asm: s390x.AMOVH, 20639 reg: regInfo{ 20640 inputs: []inputInfo{ 20641 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20642 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20643 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20644 }, 20645 }, 20646 }, 20647 { 20648 name: "MOVWstoreidx", 20649 auxType: auxSymOff, 20650 argLen: 4, 20651 commutative: true, 20652 clobberFlags: true, 20653 symEffect: SymWrite, 20654 asm: s390x.AMOVW, 20655 reg: regInfo{ 20656 inputs: []inputInfo{ 20657 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20658 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20659 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20660 }, 20661 }, 20662 }, 20663 { 20664 name: "MOVDstoreidx", 20665 auxType: auxSymOff, 20666 argLen: 4, 20667 commutative: true, 20668 clobberFlags: true, 20669 symEffect: SymWrite, 20670 asm: s390x.AMOVD, 20671 reg: regInfo{ 20672 inputs: []inputInfo{ 20673 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20674 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20675 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20676 }, 20677 }, 20678 }, 20679 { 20680 name: "MOVHBRstoreidx", 20681 auxType: auxSymOff, 20682 argLen: 4, 20683 commutative: true, 20684 clobberFlags: true, 20685 symEffect: SymWrite, 20686 asm: s390x.AMOVHBR, 20687 reg: regInfo{ 20688 inputs: []inputInfo{ 20689 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20690 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20691 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20692 }, 20693 }, 20694 }, 20695 { 20696 name: "MOVWBRstoreidx", 20697 auxType: auxSymOff, 20698 argLen: 4, 20699 commutative: true, 20700 clobberFlags: true, 20701 symEffect: SymWrite, 20702 asm: s390x.AMOVWBR, 20703 reg: regInfo{ 20704 inputs: []inputInfo{ 20705 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20706 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20707 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20708 }, 20709 }, 20710 }, 20711 { 20712 name: "MOVDBRstoreidx", 20713 auxType: auxSymOff, 20714 argLen: 4, 20715 commutative: true, 20716 clobberFlags: true, 20717 symEffect: SymWrite, 20718 asm: s390x.AMOVDBR, 20719 reg: regInfo{ 20720 inputs: []inputInfo{ 20721 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20722 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20723 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20724 }, 20725 }, 20726 }, 20727 { 20728 name: "MOVBstoreconst", 20729 auxType: auxSymValAndOff, 20730 argLen: 2, 20731 faultOnNilArg0: true, 20732 symEffect: SymWrite, 20733 asm: s390x.AMOVB, 20734 reg: regInfo{ 20735 inputs: []inputInfo{ 20736 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20737 }, 20738 }, 20739 }, 20740 { 20741 name: "MOVHstoreconst", 20742 auxType: auxSymValAndOff, 20743 argLen: 2, 20744 faultOnNilArg0: true, 20745 symEffect: SymWrite, 20746 asm: s390x.AMOVH, 20747 reg: regInfo{ 20748 inputs: []inputInfo{ 20749 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20750 }, 20751 }, 20752 }, 20753 { 20754 name: "MOVWstoreconst", 20755 auxType: auxSymValAndOff, 20756 argLen: 2, 20757 faultOnNilArg0: true, 20758 symEffect: SymWrite, 20759 asm: s390x.AMOVW, 20760 reg: regInfo{ 20761 inputs: []inputInfo{ 20762 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20763 }, 20764 }, 20765 }, 20766 { 20767 name: "MOVDstoreconst", 20768 auxType: auxSymValAndOff, 20769 argLen: 2, 20770 faultOnNilArg0: true, 20771 symEffect: SymWrite, 20772 asm: s390x.AMOVD, 20773 reg: regInfo{ 20774 inputs: []inputInfo{ 20775 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20776 }, 20777 }, 20778 }, 20779 { 20780 name: "CLEAR", 20781 auxType: auxSymValAndOff, 20782 argLen: 2, 20783 clobberFlags: true, 20784 faultOnNilArg0: true, 20785 symEffect: SymWrite, 20786 asm: s390x.ACLEAR, 20787 reg: regInfo{ 20788 inputs: []inputInfo{ 20789 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20790 }, 20791 }, 20792 }, 20793 { 20794 name: "CALLstatic", 20795 auxType: auxSymOff, 20796 argLen: 1, 20797 clobberFlags: true, 20798 call: true, 20799 symEffect: SymNone, 20800 reg: regInfo{ 20801 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20802 }, 20803 }, 20804 { 20805 name: "CALLclosure", 20806 auxType: auxInt64, 20807 argLen: 3, 20808 clobberFlags: true, 20809 call: true, 20810 reg: regInfo{ 20811 inputs: []inputInfo{ 20812 {1, 4096}, // R12 20813 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20814 }, 20815 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20816 }, 20817 }, 20818 { 20819 name: "CALLinter", 20820 auxType: auxInt64, 20821 argLen: 2, 20822 clobberFlags: true, 20823 call: true, 20824 reg: regInfo{ 20825 inputs: []inputInfo{ 20826 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20827 }, 20828 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20829 }, 20830 }, 20831 { 20832 name: "InvertFlags", 20833 argLen: 1, 20834 reg: regInfo{}, 20835 }, 20836 { 20837 name: "LoweredGetG", 20838 argLen: 1, 20839 reg: regInfo{ 20840 outputs: []outputInfo{ 20841 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20842 }, 20843 }, 20844 }, 20845 { 20846 name: "LoweredGetClosurePtr", 20847 argLen: 0, 20848 reg: regInfo{ 20849 outputs: []outputInfo{ 20850 {0, 4096}, // R12 20851 }, 20852 }, 20853 }, 20854 { 20855 name: "LoweredNilCheck", 20856 argLen: 2, 20857 clobberFlags: true, 20858 nilCheck: true, 20859 faultOnNilArg0: true, 20860 reg: regInfo{ 20861 inputs: []inputInfo{ 20862 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20863 }, 20864 }, 20865 }, 20866 { 20867 name: "LoweredRound32F", 20868 argLen: 1, 20869 resultInArg0: true, 20870 reg: regInfo{ 20871 inputs: []inputInfo{ 20872 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20873 }, 20874 outputs: []outputInfo{ 20875 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20876 }, 20877 }, 20878 }, 20879 { 20880 name: "LoweredRound64F", 20881 argLen: 1, 20882 resultInArg0: true, 20883 reg: regInfo{ 20884 inputs: []inputInfo{ 20885 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20886 }, 20887 outputs: []outputInfo{ 20888 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20889 }, 20890 }, 20891 }, 20892 { 20893 name: "MOVDconvert", 20894 argLen: 2, 20895 asm: s390x.AMOVD, 20896 reg: regInfo{ 20897 inputs: []inputInfo{ 20898 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20899 }, 20900 outputs: []outputInfo{ 20901 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20902 }, 20903 }, 20904 }, 20905 { 20906 name: "FlagEQ", 20907 argLen: 0, 20908 reg: regInfo{}, 20909 }, 20910 { 20911 name: "FlagLT", 20912 argLen: 0, 20913 reg: regInfo{}, 20914 }, 20915 { 20916 name: "FlagGT", 20917 argLen: 0, 20918 reg: regInfo{}, 20919 }, 20920 { 20921 name: "MOVWZatomicload", 20922 auxType: auxSymOff, 20923 argLen: 2, 20924 faultOnNilArg0: true, 20925 symEffect: SymRead, 20926 asm: s390x.AMOVWZ, 20927 reg: regInfo{ 20928 inputs: []inputInfo{ 20929 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20930 }, 20931 outputs: []outputInfo{ 20932 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20933 }, 20934 }, 20935 }, 20936 { 20937 name: "MOVDatomicload", 20938 auxType: auxSymOff, 20939 argLen: 2, 20940 faultOnNilArg0: true, 20941 symEffect: SymRead, 20942 asm: s390x.AMOVD, 20943 reg: regInfo{ 20944 inputs: []inputInfo{ 20945 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20946 }, 20947 outputs: []outputInfo{ 20948 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20949 }, 20950 }, 20951 }, 20952 { 20953 name: "MOVWatomicstore", 20954 auxType: auxSymOff, 20955 argLen: 3, 20956 clobberFlags: true, 20957 faultOnNilArg0: true, 20958 hasSideEffects: true, 20959 symEffect: SymWrite, 20960 asm: s390x.AMOVW, 20961 reg: regInfo{ 20962 inputs: []inputInfo{ 20963 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20964 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20965 }, 20966 }, 20967 }, 20968 { 20969 name: "MOVDatomicstore", 20970 auxType: auxSymOff, 20971 argLen: 3, 20972 clobberFlags: true, 20973 faultOnNilArg0: true, 20974 hasSideEffects: true, 20975 symEffect: SymWrite, 20976 asm: s390x.AMOVD, 20977 reg: regInfo{ 20978 inputs: []inputInfo{ 20979 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20980 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20981 }, 20982 }, 20983 }, 20984 { 20985 name: "LAA", 20986 auxType: auxSymOff, 20987 argLen: 3, 20988 faultOnNilArg0: true, 20989 hasSideEffects: true, 20990 symEffect: SymRdWr, 20991 asm: s390x.ALAA, 20992 reg: regInfo{ 20993 inputs: []inputInfo{ 20994 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20995 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20996 }, 20997 outputs: []outputInfo{ 20998 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20999 }, 21000 }, 21001 }, 21002 { 21003 name: "LAAG", 21004 auxType: auxSymOff, 21005 argLen: 3, 21006 faultOnNilArg0: true, 21007 hasSideEffects: true, 21008 symEffect: SymRdWr, 21009 asm: s390x.ALAAG, 21010 reg: regInfo{ 21011 inputs: []inputInfo{ 21012 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21013 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21014 }, 21015 outputs: []outputInfo{ 21016 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21017 }, 21018 }, 21019 }, 21020 { 21021 name: "AddTupleFirst32", 21022 argLen: 2, 21023 reg: regInfo{}, 21024 }, 21025 { 21026 name: "AddTupleFirst64", 21027 argLen: 2, 21028 reg: regInfo{}, 21029 }, 21030 { 21031 name: "LoweredAtomicCas32", 21032 auxType: auxSymOff, 21033 argLen: 4, 21034 clobberFlags: true, 21035 faultOnNilArg0: true, 21036 hasSideEffects: true, 21037 symEffect: SymRdWr, 21038 asm: s390x.ACS, 21039 reg: regInfo{ 21040 inputs: []inputInfo{ 21041 {1, 1}, // R0 21042 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21043 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21044 }, 21045 clobbers: 1, // R0 21046 outputs: []outputInfo{ 21047 {1, 0}, 21048 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21049 }, 21050 }, 21051 }, 21052 { 21053 name: "LoweredAtomicCas64", 21054 auxType: auxSymOff, 21055 argLen: 4, 21056 clobberFlags: true, 21057 faultOnNilArg0: true, 21058 hasSideEffects: true, 21059 symEffect: SymRdWr, 21060 asm: s390x.ACSG, 21061 reg: regInfo{ 21062 inputs: []inputInfo{ 21063 {1, 1}, // R0 21064 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21065 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21066 }, 21067 clobbers: 1, // R0 21068 outputs: []outputInfo{ 21069 {1, 0}, 21070 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21071 }, 21072 }, 21073 }, 21074 { 21075 name: "LoweredAtomicExchange32", 21076 auxType: auxSymOff, 21077 argLen: 3, 21078 clobberFlags: true, 21079 faultOnNilArg0: true, 21080 hasSideEffects: true, 21081 symEffect: SymRdWr, 21082 asm: s390x.ACS, 21083 reg: regInfo{ 21084 inputs: []inputInfo{ 21085 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21086 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21087 }, 21088 outputs: []outputInfo{ 21089 {1, 0}, 21090 {0, 1}, // R0 21091 }, 21092 }, 21093 }, 21094 { 21095 name: "LoweredAtomicExchange64", 21096 auxType: auxSymOff, 21097 argLen: 3, 21098 clobberFlags: true, 21099 faultOnNilArg0: true, 21100 hasSideEffects: true, 21101 symEffect: SymRdWr, 21102 asm: s390x.ACSG, 21103 reg: regInfo{ 21104 inputs: []inputInfo{ 21105 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21106 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21107 }, 21108 outputs: []outputInfo{ 21109 {1, 0}, 21110 {0, 1}, // R0 21111 }, 21112 }, 21113 }, 21114 { 21115 name: "FLOGR", 21116 argLen: 1, 21117 clobberFlags: true, 21118 asm: s390x.AFLOGR, 21119 reg: regInfo{ 21120 inputs: []inputInfo{ 21121 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21122 }, 21123 clobbers: 2, // R1 21124 outputs: []outputInfo{ 21125 {0, 1}, // R0 21126 }, 21127 }, 21128 }, 21129 { 21130 name: "STMG2", 21131 auxType: auxSymOff, 21132 argLen: 4, 21133 faultOnNilArg0: true, 21134 symEffect: SymWrite, 21135 asm: s390x.ASTMG, 21136 reg: regInfo{ 21137 inputs: []inputInfo{ 21138 {1, 2}, // R1 21139 {2, 4}, // R2 21140 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21141 }, 21142 }, 21143 }, 21144 { 21145 name: "STMG3", 21146 auxType: auxSymOff, 21147 argLen: 5, 21148 faultOnNilArg0: true, 21149 symEffect: SymWrite, 21150 asm: s390x.ASTMG, 21151 reg: regInfo{ 21152 inputs: []inputInfo{ 21153 {1, 2}, // R1 21154 {2, 4}, // R2 21155 {3, 8}, // R3 21156 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21157 }, 21158 }, 21159 }, 21160 { 21161 name: "STMG4", 21162 auxType: auxSymOff, 21163 argLen: 6, 21164 faultOnNilArg0: true, 21165 symEffect: SymWrite, 21166 asm: s390x.ASTMG, 21167 reg: regInfo{ 21168 inputs: []inputInfo{ 21169 {1, 2}, // R1 21170 {2, 4}, // R2 21171 {3, 8}, // R3 21172 {4, 16}, // R4 21173 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21174 }, 21175 }, 21176 }, 21177 { 21178 name: "STM2", 21179 auxType: auxSymOff, 21180 argLen: 4, 21181 faultOnNilArg0: true, 21182 symEffect: SymWrite, 21183 asm: s390x.ASTMY, 21184 reg: regInfo{ 21185 inputs: []inputInfo{ 21186 {1, 2}, // R1 21187 {2, 4}, // R2 21188 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21189 }, 21190 }, 21191 }, 21192 { 21193 name: "STM3", 21194 auxType: auxSymOff, 21195 argLen: 5, 21196 faultOnNilArg0: true, 21197 symEffect: SymWrite, 21198 asm: s390x.ASTMY, 21199 reg: regInfo{ 21200 inputs: []inputInfo{ 21201 {1, 2}, // R1 21202 {2, 4}, // R2 21203 {3, 8}, // R3 21204 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21205 }, 21206 }, 21207 }, 21208 { 21209 name: "STM4", 21210 auxType: auxSymOff, 21211 argLen: 6, 21212 faultOnNilArg0: true, 21213 symEffect: SymWrite, 21214 asm: s390x.ASTMY, 21215 reg: regInfo{ 21216 inputs: []inputInfo{ 21217 {1, 2}, // R1 21218 {2, 4}, // R2 21219 {3, 8}, // R3 21220 {4, 16}, // R4 21221 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21222 }, 21223 }, 21224 }, 21225 { 21226 name: "LoweredMove", 21227 auxType: auxInt64, 21228 argLen: 4, 21229 clobberFlags: true, 21230 faultOnNilArg0: true, 21231 faultOnNilArg1: true, 21232 reg: regInfo{ 21233 inputs: []inputInfo{ 21234 {0, 2}, // R1 21235 {1, 4}, // R2 21236 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21237 }, 21238 clobbers: 6, // R1 R2 21239 }, 21240 }, 21241 { 21242 name: "LoweredZero", 21243 auxType: auxInt64, 21244 argLen: 3, 21245 clobberFlags: true, 21246 faultOnNilArg0: true, 21247 reg: regInfo{ 21248 inputs: []inputInfo{ 21249 {0, 2}, // R1 21250 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21251 }, 21252 clobbers: 2, // R1 21253 }, 21254 }, 21255 21256 { 21257 name: "Add8", 21258 argLen: 2, 21259 commutative: true, 21260 generic: true, 21261 }, 21262 { 21263 name: "Add16", 21264 argLen: 2, 21265 commutative: true, 21266 generic: true, 21267 }, 21268 { 21269 name: "Add32", 21270 argLen: 2, 21271 commutative: true, 21272 generic: true, 21273 }, 21274 { 21275 name: "Add64", 21276 argLen: 2, 21277 commutative: true, 21278 generic: true, 21279 }, 21280 { 21281 name: "AddPtr", 21282 argLen: 2, 21283 generic: true, 21284 }, 21285 { 21286 name: "Add32F", 21287 argLen: 2, 21288 commutative: true, 21289 generic: true, 21290 }, 21291 { 21292 name: "Add64F", 21293 argLen: 2, 21294 commutative: true, 21295 generic: true, 21296 }, 21297 { 21298 name: "Sub8", 21299 argLen: 2, 21300 generic: true, 21301 }, 21302 { 21303 name: "Sub16", 21304 argLen: 2, 21305 generic: true, 21306 }, 21307 { 21308 name: "Sub32", 21309 argLen: 2, 21310 generic: true, 21311 }, 21312 { 21313 name: "Sub64", 21314 argLen: 2, 21315 generic: true, 21316 }, 21317 { 21318 name: "SubPtr", 21319 argLen: 2, 21320 generic: true, 21321 }, 21322 { 21323 name: "Sub32F", 21324 argLen: 2, 21325 generic: true, 21326 }, 21327 { 21328 name: "Sub64F", 21329 argLen: 2, 21330 generic: true, 21331 }, 21332 { 21333 name: "Mul8", 21334 argLen: 2, 21335 commutative: true, 21336 generic: true, 21337 }, 21338 { 21339 name: "Mul16", 21340 argLen: 2, 21341 commutative: true, 21342 generic: true, 21343 }, 21344 { 21345 name: "Mul32", 21346 argLen: 2, 21347 commutative: true, 21348 generic: true, 21349 }, 21350 { 21351 name: "Mul64", 21352 argLen: 2, 21353 commutative: true, 21354 generic: true, 21355 }, 21356 { 21357 name: "Mul32F", 21358 argLen: 2, 21359 commutative: true, 21360 generic: true, 21361 }, 21362 { 21363 name: "Mul64F", 21364 argLen: 2, 21365 commutative: true, 21366 generic: true, 21367 }, 21368 { 21369 name: "Div32F", 21370 argLen: 2, 21371 generic: true, 21372 }, 21373 { 21374 name: "Div64F", 21375 argLen: 2, 21376 generic: true, 21377 }, 21378 { 21379 name: "Hmul32", 21380 argLen: 2, 21381 commutative: true, 21382 generic: true, 21383 }, 21384 { 21385 name: "Hmul32u", 21386 argLen: 2, 21387 commutative: true, 21388 generic: true, 21389 }, 21390 { 21391 name: "Hmul64", 21392 argLen: 2, 21393 commutative: true, 21394 generic: true, 21395 }, 21396 { 21397 name: "Hmul64u", 21398 argLen: 2, 21399 commutative: true, 21400 generic: true, 21401 }, 21402 { 21403 name: "Mul32uhilo", 21404 argLen: 2, 21405 commutative: true, 21406 generic: true, 21407 }, 21408 { 21409 name: "Mul64uhilo", 21410 argLen: 2, 21411 commutative: true, 21412 generic: true, 21413 }, 21414 { 21415 name: "Avg32u", 21416 argLen: 2, 21417 generic: true, 21418 }, 21419 { 21420 name: "Avg64u", 21421 argLen: 2, 21422 generic: true, 21423 }, 21424 { 21425 name: "Div8", 21426 argLen: 2, 21427 generic: true, 21428 }, 21429 { 21430 name: "Div8u", 21431 argLen: 2, 21432 generic: true, 21433 }, 21434 { 21435 name: "Div16", 21436 argLen: 2, 21437 generic: true, 21438 }, 21439 { 21440 name: "Div16u", 21441 argLen: 2, 21442 generic: true, 21443 }, 21444 { 21445 name: "Div32", 21446 argLen: 2, 21447 generic: true, 21448 }, 21449 { 21450 name: "Div32u", 21451 argLen: 2, 21452 generic: true, 21453 }, 21454 { 21455 name: "Div64", 21456 argLen: 2, 21457 generic: true, 21458 }, 21459 { 21460 name: "Div64u", 21461 argLen: 2, 21462 generic: true, 21463 }, 21464 { 21465 name: "Div128u", 21466 argLen: 3, 21467 generic: true, 21468 }, 21469 { 21470 name: "Mod8", 21471 argLen: 2, 21472 generic: true, 21473 }, 21474 { 21475 name: "Mod8u", 21476 argLen: 2, 21477 generic: true, 21478 }, 21479 { 21480 name: "Mod16", 21481 argLen: 2, 21482 generic: true, 21483 }, 21484 { 21485 name: "Mod16u", 21486 argLen: 2, 21487 generic: true, 21488 }, 21489 { 21490 name: "Mod32", 21491 argLen: 2, 21492 generic: true, 21493 }, 21494 { 21495 name: "Mod32u", 21496 argLen: 2, 21497 generic: true, 21498 }, 21499 { 21500 name: "Mod64", 21501 argLen: 2, 21502 generic: true, 21503 }, 21504 { 21505 name: "Mod64u", 21506 argLen: 2, 21507 generic: true, 21508 }, 21509 { 21510 name: "And8", 21511 argLen: 2, 21512 commutative: true, 21513 generic: true, 21514 }, 21515 { 21516 name: "And16", 21517 argLen: 2, 21518 commutative: true, 21519 generic: true, 21520 }, 21521 { 21522 name: "And32", 21523 argLen: 2, 21524 commutative: true, 21525 generic: true, 21526 }, 21527 { 21528 name: "And64", 21529 argLen: 2, 21530 commutative: true, 21531 generic: true, 21532 }, 21533 { 21534 name: "Or8", 21535 argLen: 2, 21536 commutative: true, 21537 generic: true, 21538 }, 21539 { 21540 name: "Or16", 21541 argLen: 2, 21542 commutative: true, 21543 generic: true, 21544 }, 21545 { 21546 name: "Or32", 21547 argLen: 2, 21548 commutative: true, 21549 generic: true, 21550 }, 21551 { 21552 name: "Or64", 21553 argLen: 2, 21554 commutative: true, 21555 generic: true, 21556 }, 21557 { 21558 name: "Xor8", 21559 argLen: 2, 21560 commutative: true, 21561 generic: true, 21562 }, 21563 { 21564 name: "Xor16", 21565 argLen: 2, 21566 commutative: true, 21567 generic: true, 21568 }, 21569 { 21570 name: "Xor32", 21571 argLen: 2, 21572 commutative: true, 21573 generic: true, 21574 }, 21575 { 21576 name: "Xor64", 21577 argLen: 2, 21578 commutative: true, 21579 generic: true, 21580 }, 21581 { 21582 name: "Lsh8x8", 21583 argLen: 2, 21584 generic: true, 21585 }, 21586 { 21587 name: "Lsh8x16", 21588 argLen: 2, 21589 generic: true, 21590 }, 21591 { 21592 name: "Lsh8x32", 21593 argLen: 2, 21594 generic: true, 21595 }, 21596 { 21597 name: "Lsh8x64", 21598 argLen: 2, 21599 generic: true, 21600 }, 21601 { 21602 name: "Lsh16x8", 21603 argLen: 2, 21604 generic: true, 21605 }, 21606 { 21607 name: "Lsh16x16", 21608 argLen: 2, 21609 generic: true, 21610 }, 21611 { 21612 name: "Lsh16x32", 21613 argLen: 2, 21614 generic: true, 21615 }, 21616 { 21617 name: "Lsh16x64", 21618 argLen: 2, 21619 generic: true, 21620 }, 21621 { 21622 name: "Lsh32x8", 21623 argLen: 2, 21624 generic: true, 21625 }, 21626 { 21627 name: "Lsh32x16", 21628 argLen: 2, 21629 generic: true, 21630 }, 21631 { 21632 name: "Lsh32x32", 21633 argLen: 2, 21634 generic: true, 21635 }, 21636 { 21637 name: "Lsh32x64", 21638 argLen: 2, 21639 generic: true, 21640 }, 21641 { 21642 name: "Lsh64x8", 21643 argLen: 2, 21644 generic: true, 21645 }, 21646 { 21647 name: "Lsh64x16", 21648 argLen: 2, 21649 generic: true, 21650 }, 21651 { 21652 name: "Lsh64x32", 21653 argLen: 2, 21654 generic: true, 21655 }, 21656 { 21657 name: "Lsh64x64", 21658 argLen: 2, 21659 generic: true, 21660 }, 21661 { 21662 name: "Rsh8x8", 21663 argLen: 2, 21664 generic: true, 21665 }, 21666 { 21667 name: "Rsh8x16", 21668 argLen: 2, 21669 generic: true, 21670 }, 21671 { 21672 name: "Rsh8x32", 21673 argLen: 2, 21674 generic: true, 21675 }, 21676 { 21677 name: "Rsh8x64", 21678 argLen: 2, 21679 generic: true, 21680 }, 21681 { 21682 name: "Rsh16x8", 21683 argLen: 2, 21684 generic: true, 21685 }, 21686 { 21687 name: "Rsh16x16", 21688 argLen: 2, 21689 generic: true, 21690 }, 21691 { 21692 name: "Rsh16x32", 21693 argLen: 2, 21694 generic: true, 21695 }, 21696 { 21697 name: "Rsh16x64", 21698 argLen: 2, 21699 generic: true, 21700 }, 21701 { 21702 name: "Rsh32x8", 21703 argLen: 2, 21704 generic: true, 21705 }, 21706 { 21707 name: "Rsh32x16", 21708 argLen: 2, 21709 generic: true, 21710 }, 21711 { 21712 name: "Rsh32x32", 21713 argLen: 2, 21714 generic: true, 21715 }, 21716 { 21717 name: "Rsh32x64", 21718 argLen: 2, 21719 generic: true, 21720 }, 21721 { 21722 name: "Rsh64x8", 21723 argLen: 2, 21724 generic: true, 21725 }, 21726 { 21727 name: "Rsh64x16", 21728 argLen: 2, 21729 generic: true, 21730 }, 21731 { 21732 name: "Rsh64x32", 21733 argLen: 2, 21734 generic: true, 21735 }, 21736 { 21737 name: "Rsh64x64", 21738 argLen: 2, 21739 generic: true, 21740 }, 21741 { 21742 name: "Rsh8Ux8", 21743 argLen: 2, 21744 generic: true, 21745 }, 21746 { 21747 name: "Rsh8Ux16", 21748 argLen: 2, 21749 generic: true, 21750 }, 21751 { 21752 name: "Rsh8Ux32", 21753 argLen: 2, 21754 generic: true, 21755 }, 21756 { 21757 name: "Rsh8Ux64", 21758 argLen: 2, 21759 generic: true, 21760 }, 21761 { 21762 name: "Rsh16Ux8", 21763 argLen: 2, 21764 generic: true, 21765 }, 21766 { 21767 name: "Rsh16Ux16", 21768 argLen: 2, 21769 generic: true, 21770 }, 21771 { 21772 name: "Rsh16Ux32", 21773 argLen: 2, 21774 generic: true, 21775 }, 21776 { 21777 name: "Rsh16Ux64", 21778 argLen: 2, 21779 generic: true, 21780 }, 21781 { 21782 name: "Rsh32Ux8", 21783 argLen: 2, 21784 generic: true, 21785 }, 21786 { 21787 name: "Rsh32Ux16", 21788 argLen: 2, 21789 generic: true, 21790 }, 21791 { 21792 name: "Rsh32Ux32", 21793 argLen: 2, 21794 generic: true, 21795 }, 21796 { 21797 name: "Rsh32Ux64", 21798 argLen: 2, 21799 generic: true, 21800 }, 21801 { 21802 name: "Rsh64Ux8", 21803 argLen: 2, 21804 generic: true, 21805 }, 21806 { 21807 name: "Rsh64Ux16", 21808 argLen: 2, 21809 generic: true, 21810 }, 21811 { 21812 name: "Rsh64Ux32", 21813 argLen: 2, 21814 generic: true, 21815 }, 21816 { 21817 name: "Rsh64Ux64", 21818 argLen: 2, 21819 generic: true, 21820 }, 21821 { 21822 name: "Eq8", 21823 argLen: 2, 21824 commutative: true, 21825 generic: true, 21826 }, 21827 { 21828 name: "Eq16", 21829 argLen: 2, 21830 commutative: true, 21831 generic: true, 21832 }, 21833 { 21834 name: "Eq32", 21835 argLen: 2, 21836 commutative: true, 21837 generic: true, 21838 }, 21839 { 21840 name: "Eq64", 21841 argLen: 2, 21842 commutative: true, 21843 generic: true, 21844 }, 21845 { 21846 name: "EqPtr", 21847 argLen: 2, 21848 commutative: true, 21849 generic: true, 21850 }, 21851 { 21852 name: "EqInter", 21853 argLen: 2, 21854 generic: true, 21855 }, 21856 { 21857 name: "EqSlice", 21858 argLen: 2, 21859 generic: true, 21860 }, 21861 { 21862 name: "Eq32F", 21863 argLen: 2, 21864 commutative: true, 21865 generic: true, 21866 }, 21867 { 21868 name: "Eq64F", 21869 argLen: 2, 21870 commutative: true, 21871 generic: true, 21872 }, 21873 { 21874 name: "Neq8", 21875 argLen: 2, 21876 commutative: true, 21877 generic: true, 21878 }, 21879 { 21880 name: "Neq16", 21881 argLen: 2, 21882 commutative: true, 21883 generic: true, 21884 }, 21885 { 21886 name: "Neq32", 21887 argLen: 2, 21888 commutative: true, 21889 generic: true, 21890 }, 21891 { 21892 name: "Neq64", 21893 argLen: 2, 21894 commutative: true, 21895 generic: true, 21896 }, 21897 { 21898 name: "NeqPtr", 21899 argLen: 2, 21900 commutative: true, 21901 generic: true, 21902 }, 21903 { 21904 name: "NeqInter", 21905 argLen: 2, 21906 generic: true, 21907 }, 21908 { 21909 name: "NeqSlice", 21910 argLen: 2, 21911 generic: true, 21912 }, 21913 { 21914 name: "Neq32F", 21915 argLen: 2, 21916 commutative: true, 21917 generic: true, 21918 }, 21919 { 21920 name: "Neq64F", 21921 argLen: 2, 21922 commutative: true, 21923 generic: true, 21924 }, 21925 { 21926 name: "Less8", 21927 argLen: 2, 21928 generic: true, 21929 }, 21930 { 21931 name: "Less8U", 21932 argLen: 2, 21933 generic: true, 21934 }, 21935 { 21936 name: "Less16", 21937 argLen: 2, 21938 generic: true, 21939 }, 21940 { 21941 name: "Less16U", 21942 argLen: 2, 21943 generic: true, 21944 }, 21945 { 21946 name: "Less32", 21947 argLen: 2, 21948 generic: true, 21949 }, 21950 { 21951 name: "Less32U", 21952 argLen: 2, 21953 generic: true, 21954 }, 21955 { 21956 name: "Less64", 21957 argLen: 2, 21958 generic: true, 21959 }, 21960 { 21961 name: "Less64U", 21962 argLen: 2, 21963 generic: true, 21964 }, 21965 { 21966 name: "Less32F", 21967 argLen: 2, 21968 generic: true, 21969 }, 21970 { 21971 name: "Less64F", 21972 argLen: 2, 21973 generic: true, 21974 }, 21975 { 21976 name: "Leq8", 21977 argLen: 2, 21978 generic: true, 21979 }, 21980 { 21981 name: "Leq8U", 21982 argLen: 2, 21983 generic: true, 21984 }, 21985 { 21986 name: "Leq16", 21987 argLen: 2, 21988 generic: true, 21989 }, 21990 { 21991 name: "Leq16U", 21992 argLen: 2, 21993 generic: true, 21994 }, 21995 { 21996 name: "Leq32", 21997 argLen: 2, 21998 generic: true, 21999 }, 22000 { 22001 name: "Leq32U", 22002 argLen: 2, 22003 generic: true, 22004 }, 22005 { 22006 name: "Leq64", 22007 argLen: 2, 22008 generic: true, 22009 }, 22010 { 22011 name: "Leq64U", 22012 argLen: 2, 22013 generic: true, 22014 }, 22015 { 22016 name: "Leq32F", 22017 argLen: 2, 22018 generic: true, 22019 }, 22020 { 22021 name: "Leq64F", 22022 argLen: 2, 22023 generic: true, 22024 }, 22025 { 22026 name: "Greater8", 22027 argLen: 2, 22028 generic: true, 22029 }, 22030 { 22031 name: "Greater8U", 22032 argLen: 2, 22033 generic: true, 22034 }, 22035 { 22036 name: "Greater16", 22037 argLen: 2, 22038 generic: true, 22039 }, 22040 { 22041 name: "Greater16U", 22042 argLen: 2, 22043 generic: true, 22044 }, 22045 { 22046 name: "Greater32", 22047 argLen: 2, 22048 generic: true, 22049 }, 22050 { 22051 name: "Greater32U", 22052 argLen: 2, 22053 generic: true, 22054 }, 22055 { 22056 name: "Greater64", 22057 argLen: 2, 22058 generic: true, 22059 }, 22060 { 22061 name: "Greater64U", 22062 argLen: 2, 22063 generic: true, 22064 }, 22065 { 22066 name: "Greater32F", 22067 argLen: 2, 22068 generic: true, 22069 }, 22070 { 22071 name: "Greater64F", 22072 argLen: 2, 22073 generic: true, 22074 }, 22075 { 22076 name: "Geq8", 22077 argLen: 2, 22078 generic: true, 22079 }, 22080 { 22081 name: "Geq8U", 22082 argLen: 2, 22083 generic: true, 22084 }, 22085 { 22086 name: "Geq16", 22087 argLen: 2, 22088 generic: true, 22089 }, 22090 { 22091 name: "Geq16U", 22092 argLen: 2, 22093 generic: true, 22094 }, 22095 { 22096 name: "Geq32", 22097 argLen: 2, 22098 generic: true, 22099 }, 22100 { 22101 name: "Geq32U", 22102 argLen: 2, 22103 generic: true, 22104 }, 22105 { 22106 name: "Geq64", 22107 argLen: 2, 22108 generic: true, 22109 }, 22110 { 22111 name: "Geq64U", 22112 argLen: 2, 22113 generic: true, 22114 }, 22115 { 22116 name: "Geq32F", 22117 argLen: 2, 22118 generic: true, 22119 }, 22120 { 22121 name: "Geq64F", 22122 argLen: 2, 22123 generic: true, 22124 }, 22125 { 22126 name: "AndB", 22127 argLen: 2, 22128 commutative: true, 22129 generic: true, 22130 }, 22131 { 22132 name: "OrB", 22133 argLen: 2, 22134 commutative: true, 22135 generic: true, 22136 }, 22137 { 22138 name: "EqB", 22139 argLen: 2, 22140 commutative: true, 22141 generic: true, 22142 }, 22143 { 22144 name: "NeqB", 22145 argLen: 2, 22146 commutative: true, 22147 generic: true, 22148 }, 22149 { 22150 name: "Not", 22151 argLen: 1, 22152 generic: true, 22153 }, 22154 { 22155 name: "Neg8", 22156 argLen: 1, 22157 generic: true, 22158 }, 22159 { 22160 name: "Neg16", 22161 argLen: 1, 22162 generic: true, 22163 }, 22164 { 22165 name: "Neg32", 22166 argLen: 1, 22167 generic: true, 22168 }, 22169 { 22170 name: "Neg64", 22171 argLen: 1, 22172 generic: true, 22173 }, 22174 { 22175 name: "Neg32F", 22176 argLen: 1, 22177 generic: true, 22178 }, 22179 { 22180 name: "Neg64F", 22181 argLen: 1, 22182 generic: true, 22183 }, 22184 { 22185 name: "Com8", 22186 argLen: 1, 22187 generic: true, 22188 }, 22189 { 22190 name: "Com16", 22191 argLen: 1, 22192 generic: true, 22193 }, 22194 { 22195 name: "Com32", 22196 argLen: 1, 22197 generic: true, 22198 }, 22199 { 22200 name: "Com64", 22201 argLen: 1, 22202 generic: true, 22203 }, 22204 { 22205 name: "Ctz32", 22206 argLen: 1, 22207 generic: true, 22208 }, 22209 { 22210 name: "Ctz64", 22211 argLen: 1, 22212 generic: true, 22213 }, 22214 { 22215 name: "BitLen32", 22216 argLen: 1, 22217 generic: true, 22218 }, 22219 { 22220 name: "BitLen64", 22221 argLen: 1, 22222 generic: true, 22223 }, 22224 { 22225 name: "Bswap32", 22226 argLen: 1, 22227 generic: true, 22228 }, 22229 { 22230 name: "Bswap64", 22231 argLen: 1, 22232 generic: true, 22233 }, 22234 { 22235 name: "BitRev8", 22236 argLen: 1, 22237 generic: true, 22238 }, 22239 { 22240 name: "BitRev16", 22241 argLen: 1, 22242 generic: true, 22243 }, 22244 { 22245 name: "BitRev32", 22246 argLen: 1, 22247 generic: true, 22248 }, 22249 { 22250 name: "BitRev64", 22251 argLen: 1, 22252 generic: true, 22253 }, 22254 { 22255 name: "PopCount8", 22256 argLen: 1, 22257 generic: true, 22258 }, 22259 { 22260 name: "PopCount16", 22261 argLen: 1, 22262 generic: true, 22263 }, 22264 { 22265 name: "PopCount32", 22266 argLen: 1, 22267 generic: true, 22268 }, 22269 { 22270 name: "PopCount64", 22271 argLen: 1, 22272 generic: true, 22273 }, 22274 { 22275 name: "Sqrt", 22276 argLen: 1, 22277 generic: true, 22278 }, 22279 { 22280 name: "Floor", 22281 argLen: 1, 22282 generic: true, 22283 }, 22284 { 22285 name: "Ceil", 22286 argLen: 1, 22287 generic: true, 22288 }, 22289 { 22290 name: "Trunc", 22291 argLen: 1, 22292 generic: true, 22293 }, 22294 { 22295 name: "Phi", 22296 argLen: -1, 22297 generic: true, 22298 }, 22299 { 22300 name: "Copy", 22301 argLen: 1, 22302 generic: true, 22303 }, 22304 { 22305 name: "Convert", 22306 argLen: 2, 22307 generic: true, 22308 }, 22309 { 22310 name: "ConstBool", 22311 auxType: auxBool, 22312 argLen: 0, 22313 generic: true, 22314 }, 22315 { 22316 name: "ConstString", 22317 auxType: auxString, 22318 argLen: 0, 22319 generic: true, 22320 }, 22321 { 22322 name: "ConstNil", 22323 argLen: 0, 22324 generic: true, 22325 }, 22326 { 22327 name: "Const8", 22328 auxType: auxInt8, 22329 argLen: 0, 22330 generic: true, 22331 }, 22332 { 22333 name: "Const16", 22334 auxType: auxInt16, 22335 argLen: 0, 22336 generic: true, 22337 }, 22338 { 22339 name: "Const32", 22340 auxType: auxInt32, 22341 argLen: 0, 22342 generic: true, 22343 }, 22344 { 22345 name: "Const64", 22346 auxType: auxInt64, 22347 argLen: 0, 22348 generic: true, 22349 }, 22350 { 22351 name: "Const32F", 22352 auxType: auxFloat32, 22353 argLen: 0, 22354 generic: true, 22355 }, 22356 { 22357 name: "Const64F", 22358 auxType: auxFloat64, 22359 argLen: 0, 22360 generic: true, 22361 }, 22362 { 22363 name: "ConstInterface", 22364 argLen: 0, 22365 generic: true, 22366 }, 22367 { 22368 name: "ConstSlice", 22369 argLen: 0, 22370 generic: true, 22371 }, 22372 { 22373 name: "InitMem", 22374 argLen: 0, 22375 generic: true, 22376 }, 22377 { 22378 name: "Arg", 22379 auxType: auxSymOff, 22380 argLen: 0, 22381 symEffect: SymNone, 22382 generic: true, 22383 }, 22384 { 22385 name: "Addr", 22386 auxType: auxSym, 22387 argLen: 1, 22388 symEffect: SymAddr, 22389 generic: true, 22390 }, 22391 { 22392 name: "SP", 22393 argLen: 0, 22394 generic: true, 22395 }, 22396 { 22397 name: "SB", 22398 argLen: 0, 22399 generic: true, 22400 }, 22401 { 22402 name: "Load", 22403 argLen: 2, 22404 generic: true, 22405 }, 22406 { 22407 name: "Store", 22408 auxType: auxTyp, 22409 argLen: 3, 22410 generic: true, 22411 }, 22412 { 22413 name: "Move", 22414 auxType: auxTypSize, 22415 argLen: 3, 22416 generic: true, 22417 }, 22418 { 22419 name: "Zero", 22420 auxType: auxTypSize, 22421 argLen: 2, 22422 generic: true, 22423 }, 22424 { 22425 name: "StoreWB", 22426 auxType: auxTyp, 22427 argLen: 3, 22428 generic: true, 22429 }, 22430 { 22431 name: "MoveWB", 22432 auxType: auxTypSize, 22433 argLen: 3, 22434 generic: true, 22435 }, 22436 { 22437 name: "ZeroWB", 22438 auxType: auxTypSize, 22439 argLen: 2, 22440 generic: true, 22441 }, 22442 { 22443 name: "ClosureCall", 22444 auxType: auxInt64, 22445 argLen: 3, 22446 call: true, 22447 generic: true, 22448 }, 22449 { 22450 name: "StaticCall", 22451 auxType: auxSymOff, 22452 argLen: 1, 22453 call: true, 22454 symEffect: SymNone, 22455 generic: true, 22456 }, 22457 { 22458 name: "InterCall", 22459 auxType: auxInt64, 22460 argLen: 2, 22461 call: true, 22462 generic: true, 22463 }, 22464 { 22465 name: "SignExt8to16", 22466 argLen: 1, 22467 generic: true, 22468 }, 22469 { 22470 name: "SignExt8to32", 22471 argLen: 1, 22472 generic: true, 22473 }, 22474 { 22475 name: "SignExt8to64", 22476 argLen: 1, 22477 generic: true, 22478 }, 22479 { 22480 name: "SignExt16to32", 22481 argLen: 1, 22482 generic: true, 22483 }, 22484 { 22485 name: "SignExt16to64", 22486 argLen: 1, 22487 generic: true, 22488 }, 22489 { 22490 name: "SignExt32to64", 22491 argLen: 1, 22492 generic: true, 22493 }, 22494 { 22495 name: "ZeroExt8to16", 22496 argLen: 1, 22497 generic: true, 22498 }, 22499 { 22500 name: "ZeroExt8to32", 22501 argLen: 1, 22502 generic: true, 22503 }, 22504 { 22505 name: "ZeroExt8to64", 22506 argLen: 1, 22507 generic: true, 22508 }, 22509 { 22510 name: "ZeroExt16to32", 22511 argLen: 1, 22512 generic: true, 22513 }, 22514 { 22515 name: "ZeroExt16to64", 22516 argLen: 1, 22517 generic: true, 22518 }, 22519 { 22520 name: "ZeroExt32to64", 22521 argLen: 1, 22522 generic: true, 22523 }, 22524 { 22525 name: "Trunc16to8", 22526 argLen: 1, 22527 generic: true, 22528 }, 22529 { 22530 name: "Trunc32to8", 22531 argLen: 1, 22532 generic: true, 22533 }, 22534 { 22535 name: "Trunc32to16", 22536 argLen: 1, 22537 generic: true, 22538 }, 22539 { 22540 name: "Trunc64to8", 22541 argLen: 1, 22542 generic: true, 22543 }, 22544 { 22545 name: "Trunc64to16", 22546 argLen: 1, 22547 generic: true, 22548 }, 22549 { 22550 name: "Trunc64to32", 22551 argLen: 1, 22552 generic: true, 22553 }, 22554 { 22555 name: "Cvt32to32F", 22556 argLen: 1, 22557 generic: true, 22558 }, 22559 { 22560 name: "Cvt32to64F", 22561 argLen: 1, 22562 generic: true, 22563 }, 22564 { 22565 name: "Cvt64to32F", 22566 argLen: 1, 22567 generic: true, 22568 }, 22569 { 22570 name: "Cvt64to64F", 22571 argLen: 1, 22572 generic: true, 22573 }, 22574 { 22575 name: "Cvt32Fto32", 22576 argLen: 1, 22577 generic: true, 22578 }, 22579 { 22580 name: "Cvt32Fto64", 22581 argLen: 1, 22582 generic: true, 22583 }, 22584 { 22585 name: "Cvt64Fto32", 22586 argLen: 1, 22587 generic: true, 22588 }, 22589 { 22590 name: "Cvt64Fto64", 22591 argLen: 1, 22592 generic: true, 22593 }, 22594 { 22595 name: "Cvt32Fto64F", 22596 argLen: 1, 22597 generic: true, 22598 }, 22599 { 22600 name: "Cvt64Fto32F", 22601 argLen: 1, 22602 generic: true, 22603 }, 22604 { 22605 name: "Round32F", 22606 argLen: 1, 22607 generic: true, 22608 }, 22609 { 22610 name: "Round64F", 22611 argLen: 1, 22612 generic: true, 22613 }, 22614 { 22615 name: "IsNonNil", 22616 argLen: 1, 22617 generic: true, 22618 }, 22619 { 22620 name: "IsInBounds", 22621 argLen: 2, 22622 generic: true, 22623 }, 22624 { 22625 name: "IsSliceInBounds", 22626 argLen: 2, 22627 generic: true, 22628 }, 22629 { 22630 name: "NilCheck", 22631 argLen: 2, 22632 generic: true, 22633 }, 22634 { 22635 name: "GetG", 22636 argLen: 1, 22637 generic: true, 22638 }, 22639 { 22640 name: "GetClosurePtr", 22641 argLen: 0, 22642 generic: true, 22643 }, 22644 { 22645 name: "PtrIndex", 22646 argLen: 2, 22647 generic: true, 22648 }, 22649 { 22650 name: "OffPtr", 22651 auxType: auxInt64, 22652 argLen: 1, 22653 generic: true, 22654 }, 22655 { 22656 name: "SliceMake", 22657 argLen: 3, 22658 generic: true, 22659 }, 22660 { 22661 name: "SlicePtr", 22662 argLen: 1, 22663 generic: true, 22664 }, 22665 { 22666 name: "SliceLen", 22667 argLen: 1, 22668 generic: true, 22669 }, 22670 { 22671 name: "SliceCap", 22672 argLen: 1, 22673 generic: true, 22674 }, 22675 { 22676 name: "ComplexMake", 22677 argLen: 2, 22678 generic: true, 22679 }, 22680 { 22681 name: "ComplexReal", 22682 argLen: 1, 22683 generic: true, 22684 }, 22685 { 22686 name: "ComplexImag", 22687 argLen: 1, 22688 generic: true, 22689 }, 22690 { 22691 name: "StringMake", 22692 argLen: 2, 22693 generic: true, 22694 }, 22695 { 22696 name: "StringPtr", 22697 argLen: 1, 22698 generic: true, 22699 }, 22700 { 22701 name: "StringLen", 22702 argLen: 1, 22703 generic: true, 22704 }, 22705 { 22706 name: "IMake", 22707 argLen: 2, 22708 generic: true, 22709 }, 22710 { 22711 name: "ITab", 22712 argLen: 1, 22713 generic: true, 22714 }, 22715 { 22716 name: "IData", 22717 argLen: 1, 22718 generic: true, 22719 }, 22720 { 22721 name: "StructMake0", 22722 argLen: 0, 22723 generic: true, 22724 }, 22725 { 22726 name: "StructMake1", 22727 argLen: 1, 22728 generic: true, 22729 }, 22730 { 22731 name: "StructMake2", 22732 argLen: 2, 22733 generic: true, 22734 }, 22735 { 22736 name: "StructMake3", 22737 argLen: 3, 22738 generic: true, 22739 }, 22740 { 22741 name: "StructMake4", 22742 argLen: 4, 22743 generic: true, 22744 }, 22745 { 22746 name: "StructSelect", 22747 auxType: auxInt64, 22748 argLen: 1, 22749 generic: true, 22750 }, 22751 { 22752 name: "ArrayMake0", 22753 argLen: 0, 22754 generic: true, 22755 }, 22756 { 22757 name: "ArrayMake1", 22758 argLen: 1, 22759 generic: true, 22760 }, 22761 { 22762 name: "ArraySelect", 22763 auxType: auxInt64, 22764 argLen: 1, 22765 generic: true, 22766 }, 22767 { 22768 name: "StoreReg", 22769 argLen: 1, 22770 generic: true, 22771 }, 22772 { 22773 name: "LoadReg", 22774 argLen: 1, 22775 generic: true, 22776 }, 22777 { 22778 name: "FwdRef", 22779 auxType: auxSym, 22780 argLen: 0, 22781 symEffect: SymNone, 22782 generic: true, 22783 }, 22784 { 22785 name: "Unknown", 22786 argLen: 0, 22787 generic: true, 22788 }, 22789 { 22790 name: "VarDef", 22791 auxType: auxSym, 22792 argLen: 1, 22793 symEffect: SymNone, 22794 generic: true, 22795 }, 22796 { 22797 name: "VarKill", 22798 auxType: auxSym, 22799 argLen: 1, 22800 symEffect: SymNone, 22801 generic: true, 22802 }, 22803 { 22804 name: "VarLive", 22805 auxType: auxSym, 22806 argLen: 1, 22807 symEffect: SymNone, 22808 generic: true, 22809 }, 22810 { 22811 name: "KeepAlive", 22812 argLen: 2, 22813 generic: true, 22814 }, 22815 { 22816 name: "RegKill", 22817 argLen: 0, 22818 generic: true, 22819 }, 22820 { 22821 name: "Int64Make", 22822 argLen: 2, 22823 generic: true, 22824 }, 22825 { 22826 name: "Int64Hi", 22827 argLen: 1, 22828 generic: true, 22829 }, 22830 { 22831 name: "Int64Lo", 22832 argLen: 1, 22833 generic: true, 22834 }, 22835 { 22836 name: "Add32carry", 22837 argLen: 2, 22838 commutative: true, 22839 generic: true, 22840 }, 22841 { 22842 name: "Add32withcarry", 22843 argLen: 3, 22844 commutative: true, 22845 generic: true, 22846 }, 22847 { 22848 name: "Sub32carry", 22849 argLen: 2, 22850 generic: true, 22851 }, 22852 { 22853 name: "Sub32withcarry", 22854 argLen: 3, 22855 generic: true, 22856 }, 22857 { 22858 name: "Signmask", 22859 argLen: 1, 22860 generic: true, 22861 }, 22862 { 22863 name: "Zeromask", 22864 argLen: 1, 22865 generic: true, 22866 }, 22867 { 22868 name: "Slicemask", 22869 argLen: 1, 22870 generic: true, 22871 }, 22872 { 22873 name: "Cvt32Uto32F", 22874 argLen: 1, 22875 generic: true, 22876 }, 22877 { 22878 name: "Cvt32Uto64F", 22879 argLen: 1, 22880 generic: true, 22881 }, 22882 { 22883 name: "Cvt32Fto32U", 22884 argLen: 1, 22885 generic: true, 22886 }, 22887 { 22888 name: "Cvt64Fto32U", 22889 argLen: 1, 22890 generic: true, 22891 }, 22892 { 22893 name: "Cvt64Uto32F", 22894 argLen: 1, 22895 generic: true, 22896 }, 22897 { 22898 name: "Cvt64Uto64F", 22899 argLen: 1, 22900 generic: true, 22901 }, 22902 { 22903 name: "Cvt32Fto64U", 22904 argLen: 1, 22905 generic: true, 22906 }, 22907 { 22908 name: "Cvt64Fto64U", 22909 argLen: 1, 22910 generic: true, 22911 }, 22912 { 22913 name: "Select0", 22914 argLen: 1, 22915 generic: true, 22916 }, 22917 { 22918 name: "Select1", 22919 argLen: 1, 22920 generic: true, 22921 }, 22922 { 22923 name: "AtomicLoad32", 22924 argLen: 2, 22925 generic: true, 22926 }, 22927 { 22928 name: "AtomicLoad64", 22929 argLen: 2, 22930 generic: true, 22931 }, 22932 { 22933 name: "AtomicLoadPtr", 22934 argLen: 2, 22935 generic: true, 22936 }, 22937 { 22938 name: "AtomicStore32", 22939 argLen: 3, 22940 hasSideEffects: true, 22941 generic: true, 22942 }, 22943 { 22944 name: "AtomicStore64", 22945 argLen: 3, 22946 hasSideEffects: true, 22947 generic: true, 22948 }, 22949 { 22950 name: "AtomicStorePtrNoWB", 22951 argLen: 3, 22952 hasSideEffects: true, 22953 generic: true, 22954 }, 22955 { 22956 name: "AtomicExchange32", 22957 argLen: 3, 22958 hasSideEffects: true, 22959 generic: true, 22960 }, 22961 { 22962 name: "AtomicExchange64", 22963 argLen: 3, 22964 hasSideEffects: true, 22965 generic: true, 22966 }, 22967 { 22968 name: "AtomicAdd32", 22969 argLen: 3, 22970 hasSideEffects: true, 22971 generic: true, 22972 }, 22973 { 22974 name: "AtomicAdd64", 22975 argLen: 3, 22976 hasSideEffects: true, 22977 generic: true, 22978 }, 22979 { 22980 name: "AtomicCompareAndSwap32", 22981 argLen: 4, 22982 hasSideEffects: true, 22983 generic: true, 22984 }, 22985 { 22986 name: "AtomicCompareAndSwap64", 22987 argLen: 4, 22988 hasSideEffects: true, 22989 generic: true, 22990 }, 22991 { 22992 name: "AtomicAnd8", 22993 argLen: 3, 22994 hasSideEffects: true, 22995 generic: true, 22996 }, 22997 { 22998 name: "AtomicOr8", 22999 argLen: 3, 23000 hasSideEffects: true, 23001 generic: true, 23002 }, 23003 { 23004 name: "Clobber", 23005 auxType: auxSymOff, 23006 argLen: 0, 23007 symEffect: SymNone, 23008 generic: true, 23009 }, 23010 } 23011 23012 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 23013 func (o Op) String() string { return opcodeTable[o].name } 23014 func (o Op) UsesScratch() bool { return opcodeTable[o].usesScratch } 23015 func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect } 23016 func (o Op) IsCall() bool { return opcodeTable[o].call } 23017 23018 var registers386 = [...]Register{ 23019 {0, x86.REG_AX, "AX"}, 23020 {1, x86.REG_CX, "CX"}, 23021 {2, x86.REG_DX, "DX"}, 23022 {3, x86.REG_BX, "BX"}, 23023 {4, x86.REGSP, "SP"}, 23024 {5, x86.REG_BP, "BP"}, 23025 {6, x86.REG_SI, "SI"}, 23026 {7, x86.REG_DI, "DI"}, 23027 {8, x86.REG_X0, "X0"}, 23028 {9, x86.REG_X1, "X1"}, 23029 {10, x86.REG_X2, "X2"}, 23030 {11, x86.REG_X3, "X3"}, 23031 {12, x86.REG_X4, "X4"}, 23032 {13, x86.REG_X5, "X5"}, 23033 {14, x86.REG_X6, "X6"}, 23034 {15, x86.REG_X7, "X7"}, 23035 {16, 0, "SB"}, 23036 } 23037 var gpRegMask386 = regMask(239) 23038 var fpRegMask386 = regMask(65280) 23039 var specialRegMask386 = regMask(0) 23040 var framepointerReg386 = int8(5) 23041 var linkReg386 = int8(-1) 23042 var registersAMD64 = [...]Register{ 23043 {0, x86.REG_AX, "AX"}, 23044 {1, x86.REG_CX, "CX"}, 23045 {2, x86.REG_DX, "DX"}, 23046 {3, x86.REG_BX, "BX"}, 23047 {4, x86.REGSP, "SP"}, 23048 {5, x86.REG_BP, "BP"}, 23049 {6, x86.REG_SI, "SI"}, 23050 {7, x86.REG_DI, "DI"}, 23051 {8, x86.REG_R8, "R8"}, 23052 {9, x86.REG_R9, "R9"}, 23053 {10, x86.REG_R10, "R10"}, 23054 {11, x86.REG_R11, "R11"}, 23055 {12, x86.REG_R12, "R12"}, 23056 {13, x86.REG_R13, "R13"}, 23057 {14, x86.REG_R14, "R14"}, 23058 {15, x86.REG_R15, "R15"}, 23059 {16, x86.REG_X0, "X0"}, 23060 {17, x86.REG_X1, "X1"}, 23061 {18, x86.REG_X2, "X2"}, 23062 {19, x86.REG_X3, "X3"}, 23063 {20, x86.REG_X4, "X4"}, 23064 {21, x86.REG_X5, "X5"}, 23065 {22, x86.REG_X6, "X6"}, 23066 {23, x86.REG_X7, "X7"}, 23067 {24, x86.REG_X8, "X8"}, 23068 {25, x86.REG_X9, "X9"}, 23069 {26, x86.REG_X10, "X10"}, 23070 {27, x86.REG_X11, "X11"}, 23071 {28, x86.REG_X12, "X12"}, 23072 {29, x86.REG_X13, "X13"}, 23073 {30, x86.REG_X14, "X14"}, 23074 {31, x86.REG_X15, "X15"}, 23075 {32, 0, "SB"}, 23076 } 23077 var gpRegMaskAMD64 = regMask(65519) 23078 var fpRegMaskAMD64 = regMask(4294901760) 23079 var specialRegMaskAMD64 = regMask(0) 23080 var framepointerRegAMD64 = int8(5) 23081 var linkRegAMD64 = int8(-1) 23082 var registersARM = [...]Register{ 23083 {0, arm.REG_R0, "R0"}, 23084 {1, arm.REG_R1, "R1"}, 23085 {2, arm.REG_R2, "R2"}, 23086 {3, arm.REG_R3, "R3"}, 23087 {4, arm.REG_R4, "R4"}, 23088 {5, arm.REG_R5, "R5"}, 23089 {6, arm.REG_R6, "R6"}, 23090 {7, arm.REG_R7, "R7"}, 23091 {8, arm.REG_R8, "R8"}, 23092 {9, arm.REG_R9, "R9"}, 23093 {10, arm.REGG, "g"}, 23094 {11, arm.REG_R11, "R11"}, 23095 {12, arm.REG_R12, "R12"}, 23096 {13, arm.REGSP, "SP"}, 23097 {14, arm.REG_R14, "R14"}, 23098 {15, arm.REG_R15, "R15"}, 23099 {16, arm.REG_F0, "F0"}, 23100 {17, arm.REG_F1, "F1"}, 23101 {18, arm.REG_F2, "F2"}, 23102 {19, arm.REG_F3, "F3"}, 23103 {20, arm.REG_F4, "F4"}, 23104 {21, arm.REG_F5, "F5"}, 23105 {22, arm.REG_F6, "F6"}, 23106 {23, arm.REG_F7, "F7"}, 23107 {24, arm.REG_F8, "F8"}, 23108 {25, arm.REG_F9, "F9"}, 23109 {26, arm.REG_F10, "F10"}, 23110 {27, arm.REG_F11, "F11"}, 23111 {28, arm.REG_F12, "F12"}, 23112 {29, arm.REG_F13, "F13"}, 23113 {30, arm.REG_F14, "F14"}, 23114 {31, arm.REG_F15, "F15"}, 23115 {32, 0, "SB"}, 23116 } 23117 var gpRegMaskARM = regMask(21503) 23118 var fpRegMaskARM = regMask(4294901760) 23119 var specialRegMaskARM = regMask(0) 23120 var framepointerRegARM = int8(-1) 23121 var linkRegARM = int8(14) 23122 var registersARM64 = [...]Register{ 23123 {0, arm64.REG_R0, "R0"}, 23124 {1, arm64.REG_R1, "R1"}, 23125 {2, arm64.REG_R2, "R2"}, 23126 {3, arm64.REG_R3, "R3"}, 23127 {4, arm64.REG_R4, "R4"}, 23128 {5, arm64.REG_R5, "R5"}, 23129 {6, arm64.REG_R6, "R6"}, 23130 {7, arm64.REG_R7, "R7"}, 23131 {8, arm64.REG_R8, "R8"}, 23132 {9, arm64.REG_R9, "R9"}, 23133 {10, arm64.REG_R10, "R10"}, 23134 {11, arm64.REG_R11, "R11"}, 23135 {12, arm64.REG_R12, "R12"}, 23136 {13, arm64.REG_R13, "R13"}, 23137 {14, arm64.REG_R14, "R14"}, 23138 {15, arm64.REG_R15, "R15"}, 23139 {16, arm64.REG_R16, "R16"}, 23140 {17, arm64.REG_R17, "R17"}, 23141 {18, arm64.REG_R18, "R18"}, 23142 {19, arm64.REG_R19, "R19"}, 23143 {20, arm64.REG_R20, "R20"}, 23144 {21, arm64.REG_R21, "R21"}, 23145 {22, arm64.REG_R22, "R22"}, 23146 {23, arm64.REG_R23, "R23"}, 23147 {24, arm64.REG_R24, "R24"}, 23148 {25, arm64.REG_R25, "R25"}, 23149 {26, arm64.REG_R26, "R26"}, 23150 {27, arm64.REGG, "g"}, 23151 {28, arm64.REG_R29, "R29"}, 23152 {29, arm64.REG_R30, "R30"}, 23153 {30, arm64.REGSP, "SP"}, 23154 {31, arm64.REG_F0, "F0"}, 23155 {32, arm64.REG_F1, "F1"}, 23156 {33, arm64.REG_F2, "F2"}, 23157 {34, arm64.REG_F3, "F3"}, 23158 {35, arm64.REG_F4, "F4"}, 23159 {36, arm64.REG_F5, "F5"}, 23160 {37, arm64.REG_F6, "F6"}, 23161 {38, arm64.REG_F7, "F7"}, 23162 {39, arm64.REG_F8, "F8"}, 23163 {40, arm64.REG_F9, "F9"}, 23164 {41, arm64.REG_F10, "F10"}, 23165 {42, arm64.REG_F11, "F11"}, 23166 {43, arm64.REG_F12, "F12"}, 23167 {44, arm64.REG_F13, "F13"}, 23168 {45, arm64.REG_F14, "F14"}, 23169 {46, arm64.REG_F15, "F15"}, 23170 {47, arm64.REG_F16, "F16"}, 23171 {48, arm64.REG_F17, "F17"}, 23172 {49, arm64.REG_F18, "F18"}, 23173 {50, arm64.REG_F19, "F19"}, 23174 {51, arm64.REG_F20, "F20"}, 23175 {52, arm64.REG_F21, "F21"}, 23176 {53, arm64.REG_F22, "F22"}, 23177 {54, arm64.REG_F23, "F23"}, 23178 {55, arm64.REG_F24, "F24"}, 23179 {56, arm64.REG_F25, "F25"}, 23180 {57, arm64.REG_F26, "F26"}, 23181 {58, arm64.REG_F27, "F27"}, 23182 {59, arm64.REG_F28, "F28"}, 23183 {60, arm64.REG_F29, "F29"}, 23184 {61, arm64.REG_F30, "F30"}, 23185 {62, arm64.REG_F31, "F31"}, 23186 {63, 0, "SB"}, 23187 } 23188 var gpRegMaskARM64 = regMask(670826495) 23189 var fpRegMaskARM64 = regMask(9223372034707292160) 23190 var specialRegMaskARM64 = regMask(0) 23191 var framepointerRegARM64 = int8(-1) 23192 var linkRegARM64 = int8(29) 23193 var registersMIPS = [...]Register{ 23194 {0, mips.REG_R0, "R0"}, 23195 {1, mips.REG_R1, "R1"}, 23196 {2, mips.REG_R2, "R2"}, 23197 {3, mips.REG_R3, "R3"}, 23198 {4, mips.REG_R4, "R4"}, 23199 {5, mips.REG_R5, "R5"}, 23200 {6, mips.REG_R6, "R6"}, 23201 {7, mips.REG_R7, "R7"}, 23202 {8, mips.REG_R8, "R8"}, 23203 {9, mips.REG_R9, "R9"}, 23204 {10, mips.REG_R10, "R10"}, 23205 {11, mips.REG_R11, "R11"}, 23206 {12, mips.REG_R12, "R12"}, 23207 {13, mips.REG_R13, "R13"}, 23208 {14, mips.REG_R14, "R14"}, 23209 {15, mips.REG_R15, "R15"}, 23210 {16, mips.REG_R16, "R16"}, 23211 {17, mips.REG_R17, "R17"}, 23212 {18, mips.REG_R18, "R18"}, 23213 {19, mips.REG_R19, "R19"}, 23214 {20, mips.REG_R20, "R20"}, 23215 {21, mips.REG_R21, "R21"}, 23216 {22, mips.REG_R22, "R22"}, 23217 {23, mips.REG_R24, "R24"}, 23218 {24, mips.REG_R25, "R25"}, 23219 {25, mips.REG_R28, "R28"}, 23220 {26, mips.REGSP, "SP"}, 23221 {27, mips.REGG, "g"}, 23222 {28, mips.REG_R31, "R31"}, 23223 {29, mips.REG_F0, "F0"}, 23224 {30, mips.REG_F2, "F2"}, 23225 {31, mips.REG_F4, "F4"}, 23226 {32, mips.REG_F6, "F6"}, 23227 {33, mips.REG_F8, "F8"}, 23228 {34, mips.REG_F10, "F10"}, 23229 {35, mips.REG_F12, "F12"}, 23230 {36, mips.REG_F14, "F14"}, 23231 {37, mips.REG_F16, "F16"}, 23232 {38, mips.REG_F18, "F18"}, 23233 {39, mips.REG_F20, "F20"}, 23234 {40, mips.REG_F22, "F22"}, 23235 {41, mips.REG_F24, "F24"}, 23236 {42, mips.REG_F26, "F26"}, 23237 {43, mips.REG_F28, "F28"}, 23238 {44, mips.REG_F30, "F30"}, 23239 {45, mips.REG_HI, "HI"}, 23240 {46, mips.REG_LO, "LO"}, 23241 {47, 0, "SB"}, 23242 } 23243 var gpRegMaskMIPS = regMask(335544318) 23244 var fpRegMaskMIPS = regMask(35183835217920) 23245 var specialRegMaskMIPS = regMask(105553116266496) 23246 var framepointerRegMIPS = int8(-1) 23247 var linkRegMIPS = int8(28) 23248 var registersMIPS64 = [...]Register{ 23249 {0, mips.REG_R0, "R0"}, 23250 {1, mips.REG_R1, "R1"}, 23251 {2, mips.REG_R2, "R2"}, 23252 {3, mips.REG_R3, "R3"}, 23253 {4, mips.REG_R4, "R4"}, 23254 {5, mips.REG_R5, "R5"}, 23255 {6, mips.REG_R6, "R6"}, 23256 {7, mips.REG_R7, "R7"}, 23257 {8, mips.REG_R8, "R8"}, 23258 {9, mips.REG_R9, "R9"}, 23259 {10, mips.REG_R10, "R10"}, 23260 {11, mips.REG_R11, "R11"}, 23261 {12, mips.REG_R12, "R12"}, 23262 {13, mips.REG_R13, "R13"}, 23263 {14, mips.REG_R14, "R14"}, 23264 {15, mips.REG_R15, "R15"}, 23265 {16, mips.REG_R16, "R16"}, 23266 {17, mips.REG_R17, "R17"}, 23267 {18, mips.REG_R18, "R18"}, 23268 {19, mips.REG_R19, "R19"}, 23269 {20, mips.REG_R20, "R20"}, 23270 {21, mips.REG_R21, "R21"}, 23271 {22, mips.REG_R22, "R22"}, 23272 {23, mips.REG_R24, "R24"}, 23273 {24, mips.REG_R25, "R25"}, 23274 {25, mips.REGSP, "SP"}, 23275 {26, mips.REGG, "g"}, 23276 {27, mips.REG_R31, "R31"}, 23277 {28, mips.REG_F0, "F0"}, 23278 {29, mips.REG_F1, "F1"}, 23279 {30, mips.REG_F2, "F2"}, 23280 {31, mips.REG_F3, "F3"}, 23281 {32, mips.REG_F4, "F4"}, 23282 {33, mips.REG_F5, "F5"}, 23283 {34, mips.REG_F6, "F6"}, 23284 {35, mips.REG_F7, "F7"}, 23285 {36, mips.REG_F8, "F8"}, 23286 {37, mips.REG_F9, "F9"}, 23287 {38, mips.REG_F10, "F10"}, 23288 {39, mips.REG_F11, "F11"}, 23289 {40, mips.REG_F12, "F12"}, 23290 {41, mips.REG_F13, "F13"}, 23291 {42, mips.REG_F14, "F14"}, 23292 {43, mips.REG_F15, "F15"}, 23293 {44, mips.REG_F16, "F16"}, 23294 {45, mips.REG_F17, "F17"}, 23295 {46, mips.REG_F18, "F18"}, 23296 {47, mips.REG_F19, "F19"}, 23297 {48, mips.REG_F20, "F20"}, 23298 {49, mips.REG_F21, "F21"}, 23299 {50, mips.REG_F22, "F22"}, 23300 {51, mips.REG_F23, "F23"}, 23301 {52, mips.REG_F24, "F24"}, 23302 {53, mips.REG_F25, "F25"}, 23303 {54, mips.REG_F26, "F26"}, 23304 {55, mips.REG_F27, "F27"}, 23305 {56, mips.REG_F28, "F28"}, 23306 {57, mips.REG_F29, "F29"}, 23307 {58, mips.REG_F30, "F30"}, 23308 {59, mips.REG_F31, "F31"}, 23309 {60, mips.REG_HI, "HI"}, 23310 {61, mips.REG_LO, "LO"}, 23311 {62, 0, "SB"}, 23312 } 23313 var gpRegMaskMIPS64 = regMask(167772158) 23314 var fpRegMaskMIPS64 = regMask(1152921504338411520) 23315 var specialRegMaskMIPS64 = regMask(3458764513820540928) 23316 var framepointerRegMIPS64 = int8(-1) 23317 var linkRegMIPS64 = int8(27) 23318 var registersPPC64 = [...]Register{ 23319 {0, ppc64.REG_R0, "R0"}, 23320 {1, ppc64.REGSP, "SP"}, 23321 {2, 0, "SB"}, 23322 {3, ppc64.REG_R3, "R3"}, 23323 {4, ppc64.REG_R4, "R4"}, 23324 {5, ppc64.REG_R5, "R5"}, 23325 {6, ppc64.REG_R6, "R6"}, 23326 {7, ppc64.REG_R7, "R7"}, 23327 {8, ppc64.REG_R8, "R8"}, 23328 {9, ppc64.REG_R9, "R9"}, 23329 {10, ppc64.REG_R10, "R10"}, 23330 {11, ppc64.REG_R11, "R11"}, 23331 {12, ppc64.REG_R12, "R12"}, 23332 {13, ppc64.REG_R13, "R13"}, 23333 {14, ppc64.REG_R14, "R14"}, 23334 {15, ppc64.REG_R15, "R15"}, 23335 {16, ppc64.REG_R16, "R16"}, 23336 {17, ppc64.REG_R17, "R17"}, 23337 {18, ppc64.REG_R18, "R18"}, 23338 {19, ppc64.REG_R19, "R19"}, 23339 {20, ppc64.REG_R20, "R20"}, 23340 {21, ppc64.REG_R21, "R21"}, 23341 {22, ppc64.REG_R22, "R22"}, 23342 {23, ppc64.REG_R23, "R23"}, 23343 {24, ppc64.REG_R24, "R24"}, 23344 {25, ppc64.REG_R25, "R25"}, 23345 {26, ppc64.REG_R26, "R26"}, 23346 {27, ppc64.REG_R27, "R27"}, 23347 {28, ppc64.REG_R28, "R28"}, 23348 {29, ppc64.REG_R29, "R29"}, 23349 {30, ppc64.REGG, "g"}, 23350 {31, ppc64.REG_R31, "R31"}, 23351 {32, ppc64.REG_F0, "F0"}, 23352 {33, ppc64.REG_F1, "F1"}, 23353 {34, ppc64.REG_F2, "F2"}, 23354 {35, ppc64.REG_F3, "F3"}, 23355 {36, ppc64.REG_F4, "F4"}, 23356 {37, ppc64.REG_F5, "F5"}, 23357 {38, ppc64.REG_F6, "F6"}, 23358 {39, ppc64.REG_F7, "F7"}, 23359 {40, ppc64.REG_F8, "F8"}, 23360 {41, ppc64.REG_F9, "F9"}, 23361 {42, ppc64.REG_F10, "F10"}, 23362 {43, ppc64.REG_F11, "F11"}, 23363 {44, ppc64.REG_F12, "F12"}, 23364 {45, ppc64.REG_F13, "F13"}, 23365 {46, ppc64.REG_F14, "F14"}, 23366 {47, ppc64.REG_F15, "F15"}, 23367 {48, ppc64.REG_F16, "F16"}, 23368 {49, ppc64.REG_F17, "F17"}, 23369 {50, ppc64.REG_F18, "F18"}, 23370 {51, ppc64.REG_F19, "F19"}, 23371 {52, ppc64.REG_F20, "F20"}, 23372 {53, ppc64.REG_F21, "F21"}, 23373 {54, ppc64.REG_F22, "F22"}, 23374 {55, ppc64.REG_F23, "F23"}, 23375 {56, ppc64.REG_F24, "F24"}, 23376 {57, ppc64.REG_F25, "F25"}, 23377 {58, ppc64.REG_F26, "F26"}, 23378 {59, ppc64.REG_F27, "F27"}, 23379 {60, ppc64.REG_F28, "F28"}, 23380 {61, ppc64.REG_F29, "F29"}, 23381 {62, ppc64.REG_F30, "F30"}, 23382 {63, ppc64.REG_F31, "F31"}, 23383 } 23384 var gpRegMaskPPC64 = regMask(1073733624) 23385 var fpRegMaskPPC64 = regMask(576460743713488896) 23386 var specialRegMaskPPC64 = regMask(0) 23387 var framepointerRegPPC64 = int8(1) 23388 var linkRegPPC64 = int8(-1) 23389 var registersS390X = [...]Register{ 23390 {0, s390x.REG_R0, "R0"}, 23391 {1, s390x.REG_R1, "R1"}, 23392 {2, s390x.REG_R2, "R2"}, 23393 {3, s390x.REG_R3, "R3"}, 23394 {4, s390x.REG_R4, "R4"}, 23395 {5, s390x.REG_R5, "R5"}, 23396 {6, s390x.REG_R6, "R6"}, 23397 {7, s390x.REG_R7, "R7"}, 23398 {8, s390x.REG_R8, "R8"}, 23399 {9, s390x.REG_R9, "R9"}, 23400 {10, s390x.REG_R10, "R10"}, 23401 {11, s390x.REG_R11, "R11"}, 23402 {12, s390x.REG_R12, "R12"}, 23403 {13, s390x.REGG, "g"}, 23404 {14, s390x.REG_R14, "R14"}, 23405 {15, s390x.REGSP, "SP"}, 23406 {16, s390x.REG_F0, "F0"}, 23407 {17, s390x.REG_F1, "F1"}, 23408 {18, s390x.REG_F2, "F2"}, 23409 {19, s390x.REG_F3, "F3"}, 23410 {20, s390x.REG_F4, "F4"}, 23411 {21, s390x.REG_F5, "F5"}, 23412 {22, s390x.REG_F6, "F6"}, 23413 {23, s390x.REG_F7, "F7"}, 23414 {24, s390x.REG_F8, "F8"}, 23415 {25, s390x.REG_F9, "F9"}, 23416 {26, s390x.REG_F10, "F10"}, 23417 {27, s390x.REG_F11, "F11"}, 23418 {28, s390x.REG_F12, "F12"}, 23419 {29, s390x.REG_F13, "F13"}, 23420 {30, s390x.REG_F14, "F14"}, 23421 {31, s390x.REG_F15, "F15"}, 23422 {32, 0, "SB"}, 23423 } 23424 var gpRegMaskS390X = regMask(21503) 23425 var fpRegMaskS390X = regMask(4294901760) 23426 var specialRegMaskS390X = regMask(0) 23427 var framepointerRegS390X = int8(-1) 23428 var linkRegS390X = int8(14)