github.com/icexin/eggos@v0.4.2-0.20220216025428-78b167e4f349/kernel/asm_amd64.s (about) 1 #include "textflag.h" 2 3 // copy from go_tls.h 4 #define get_tls(r) MOVL TLS, r 5 #define g(r) 0(r)(TLS*1) 6 7 // rt0 is the entry point of the kernel, which invokes kernel.preinit. 8 TEXT ·rt0(SB), NOSPLIT, $0-0 9 // switch to new stack 10 MOVQ $0x80000, SP 11 XORQ BP, BP 12 13 // DI and SI store multiboot magic and info passed by bootloader 14 SUBQ $0x10, SP 15 MOVQ DI, 0(SP) 16 MOVQ SI, 8(SP) 17 CALL ·preinit(SB) 18 INT $3 19 20 // never return 21 22 // go_entry invokes _rt0_amd64_linux of the Go runtime. 23 TEXT ·go_entry(SB), NOSPLIT, $0 24 SUBQ $256, SP 25 PUSHQ SP 26 CALL ·prepareArgs(SB) 27 ADDQ $8, SP 28 JMP _rt0_amd64_linux(SB) 29 30 // sseInit initializes the SSE instruction set. 31 TEXT ·sseInit(SB), NOSPLIT, $0 32 MOVL CR0, AX 33 ANDW $0xFFFB, AX 34 ORW $0x2, AX 35 MOVL AX, CR0 36 MOVL CR4, AX 37 ORW $3<<9, AX 38 MOVL AX, CR4 39 RET 40 41 // avxInit initializes the AVX instruction set. 42 TEXT ·avxInit(SB), NOSPLIT, $0 43 // enable XGETBV and XSETBV 44 MOVL CR4, AX 45 ORL $1<<18, AX 46 MOVL AX, CR4 47 48 // enable avx 49 XORQ CX, CX 50 XGETBV 51 52 ORQ $7, AX 53 XORQ CX, CX 54 XSETBV 55 RET 56 57 // rdmsr(reg uint32) (ax, dx uint32) - Read from Model Specific Register. 58 TEXT ·rdmsr(SB), NOSPLIT, $0-16 59 MOVL reg+0(FP), CX 60 RDMSR 61 MOVL AX, lo+8(FP) 62 MOVL DX, hi+12(FP) 63 RET 64 65 // wrmsr(reg, lo, hi uint32) - Write to Model Specific Register. 66 TEXT ·wrmsr(SB), NOSPLIT, $0-16 67 MOVL reg+0(FP), CX 68 MOVL lo+8(FP), AX 69 MOVL hi+12(FP), DX 70 WRMSR 71 RET 72 73 // getg() uint64 - returns G from thread local storage of the current thread. 74 TEXT ·getg(SB), NOSPLIT, $0-8 75 get_tls(CX) 76 MOVQ g(CX), BX 77 MOVQ BX, ret+0(FP) 78 RET 79 80 // cpuid(fn, cx uint32) (ax, bx, cx, dx uint32) - CPU Identification. 81 TEXT ·cpuid(SB), NOSPLIT, $0-24 82 MOVL fn+0(FP), AX 83 MOVL cx+4(FP), CX 84 CPUID 85 MOVL AX, eax+8(FP) 86 MOVL BX, ebx+12(FP) 87 MOVL CX, ecx+16(FP) 88 MOVL DX, edx+20(FP) 89 RET