github.com/jlmucb/cloudproxy@v0.0.0-20170830161738-b5aa0b619bc4/cpvmm/common/include/arch/em64t_defs.h (about) 1 /* 2 * Copyright (c) 2013 Intel Corporation 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * Unless required by applicable law or agreed to in writing, software 9 * distributed under the License is distributed on an "AS IS" BASIS, 10 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 11 * See the License for the specific language governing permissions and 12 * limitations under the License. 13 */ 14 15 #ifndef _EM64T_DEFS_H_ 16 #define _EM64T_DEFS_H_ 17 18 #include "msr_defs.h" 19 20 #pragma PACK_ON 21 22 // IA-32 EFLAGS Register 23 typedef union { 24 struct { 25 UINT32 CF:1; // Carry Flag 26 UINT32 Reserved_0:1; // Reserved 27 UINT32 PF:1; // Parity Flag 28 UINT32 Reserved_1:1; // Reserved 29 UINT32 AF:1; // Auxiliary Carry Flag 30 UINT32 Reserved_2:1; // Reserved 31 UINT32 ZF:1; // Zero Flag 32 UINT32 SF:1; // Sign Flag 33 UINT32 TP:1; // Trap Flag 34 UINT32 IFL:1; // Interrupt Enable Flag 35 UINT32 DF:1; // Direction Flag 36 UINT32 OF:1; // Overflow Flag 37 UINT32 IOPL:2; // I/O Privilege Level 38 UINT32 NT:1; // Nexted Task 39 UINT32 Reserved_3:1; // Reserved 40 UINT32 RF:1; // Resume Flag 41 UINT32 VM:1; // Virtual 8086 Mode 42 UINT32 AC:1; // Alignment Check 43 UINT32 VIF:1; // Virtual Interrupt Flag 44 UINT32 VIP:1; // Virtual Interrupt Pending 45 UINT32 ID:1; // ID Flag 46 UINT32 Reserved_4:10; // Reserved 47 UINT32 Reserved_5:32; // Reserved 48 } Bits; 49 UINT64 Uint64; 50 } EM64T_RFLAGS; 51 52 53 // IA-32 Control Register #0 (CR0) 54 #define CR0_PE 0x00000001 55 #define CR0_MP 0x00000002 56 #define CR0_EM 0x00000004 57 #define CR0_TS 0x00000008 58 #define CR0_ET 0x00000010 59 #define CR0_NE 0x00000020 60 #define CR0_WP 0x00010000 61 #define CR0_AM 0x00040000 62 #define CR0_NW 0x20000000 63 #define CR0_CD 0x40000000 64 #define CR0_PG 0x80000000 65 66 typedef union _EM64T_CR0 { 67 struct { 68 UINT32 PE:1; // Protection Enable 69 UINT32 MP:1; // Monitor Coprocessor 70 UINT32 EM:1; // Emulation 71 UINT32 TS:1; // Task Switched 72 UINT32 ET:1; // Extension Type 73 UINT32 NE:1; // Numeric Error 74 UINT32 Reserved_0:10; // Reserved 75 UINT32 WP:1; // Write Protect 76 UINT32 Reserved_1:1; // Reserved 77 UINT32 AM:1; // Alignment Mask 78 UINT32 Reserved_2:10; // Reserved 79 UINT32 NW:1; // Not Write-through 80 UINT32 CD:1; // Cache Disable 81 UINT32 PG:1; // Paging 82 UINT32 Reserved_3:32; // Must be zero 83 } Bits; 84 UINT64 Uint64; 85 } EM64T_CR0; 86 87 #define EM64T_CR1_ReservedBits( Cr1 ) \ 88 ((Cr1).Bits.Reserved_0 && (Cr1).Bits.Reserved_1 && (Cr1).Bits.Reserved_2 && (Cr1).Bits.Reserved_3) 89 90 91 // IA-32 Control Register #3 (CR3) 92 typedef struct _EM64T_CR3 { 93 struct { 94 UINT32 reserved_0_2 :3; 95 UINT32 pwt :1; // Page Write Through 96 UINT32 pcd :1; // Page Cache Disable 97 UINT32 reserved_5_11 :7; 98 UINT32 base_address_lo :20; // bits 31..12 of base address (low bits are zeroes) 99 } lo; 100 struct { 101 UINT32 base_address_hi :20; // bits 51..32 of base address 102 UINT32 zeroes :11; 103 UINT32 no_execute :1; 104 } hi; 105 } EM64T_CR3; 106 107 // IA-32 Control Register #4 (CR4) 108 #define CR4_VME 0x00000001 109 #define CR4_PVI 0x00000002 110 #define CR4_TSD 0x00000004 111 #define CR4_DE 0x00000008 112 #define CR4_PSE 0x00000010 113 #define CR4_PAE 0x00000020 114 #define CR4_MCE 0x00000040 115 #define CR4_PGE 0x00000080 116 #define CR4_PCE 0x00000100 117 #define CR4_OSFXSR 0x00000200 118 #define CR4_OSXMMEXCPT 0x00000400 119 #define CR4_VMXE 0x00002000 120 #define CR4_SMXE 0x00004000 121 #define CR4_OSXSAVE 0x00040000 122 123 typedef union _EM64T_CR4 { 124 struct { 125 UINT32 VME:1; // Virtual-8086 Mode Extensions 126 UINT32 PVI:1; // Protected-Mode Virtual Interrupts 127 UINT32 TSD:1; // Time Stamp Disable 128 UINT32 DE:1; // Debugging Extensions 129 UINT32 PSE:1; // Page Size Extensions 130 UINT32 PAE:1; // Physical Address Extension 131 UINT32 MCE:1; // Machine Check Enable 132 UINT32 PGE:1; // Page Global Enable 133 UINT32 PCE:1; // Performance Monitoring Counter Enable 134 UINT32 OSFXSR:1; // Operating System Support for FXSAVE and FXRSTOR instructions 135 UINT32 OSXMMEXCPT:1; // Operating System Support for Unmasked SIMD Floating Point Exceptions 136 UINT32 Reserved_0:2; // Reserved 137 UINT32 VMXE:1; // VMX Enable 138 UINT32 SMXE:1; // SMX Enable 139 UINT32 Reserved_1:1; // Reseved 140 UINT32 FSGSBASE:1; // Enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, 141 // and WRGSBASE. 142 UINT32 PCIDE:1; // 143 UINT32 OSXSAVE:1; // XSAVE and Processor Extended States-Enable Bit 144 UINT32 Reserved_2:1; // Reseved 145 UINT32 SMEP:1; // Supervisor Mode Execution Prevention 146 UINT32 Reserved_3:11; // Reserved 147 UINT32 Reserved_4:32; // Reserved, must be zero 148 } Bits; 149 UINT64 Uint64; 150 } EM64T_CR4; 151 152 #define EM64T_CR4_ReservedBits( Cr4 ) \ 153 ((Cr4).Bits.Reserved_0 && (Cr4).Bits.Reserved_1 && (Cr4).Bits.Reserved_2) 154 155 // IA-32 Control Register #8 (CR8) 156 typedef union _EM64T_CR8 { 157 struct { 158 UINT32 TPR:4; // Reflect APIC.TPR[7:4] bits 159 UINT32 Reserved_1:28; // Reserved, must be zero 160 UINT32 Reserved_2:32; // Reserved, must be zero 161 } Bits; 162 UINT64 Uint64; 163 } EM64T_CR8; 164 165 #define EM64T_CR8_VALID_BITS_MASK ((UINT64)0x0F) 166 167 // Descriptor for the Global Descriptor Table(GDT) and Interrupt Descriptor Table(IDT) 168 typedef struct _EM64T_GDTR { 169 UINT16 limit; 170 UINT64 base; 171 } PACKED EM64T_GDTR; 172 173 #define EM64T_SEGMENT_IS_UNUSABLE_ATTRUBUTE_VALUE 0x10000 174 175 // Code Segment Entry in Global Descriptor Table(GDT) 176 typedef struct _EM64T_CODE_SEGMENT_DESCRIPTOR { 177 UINT32 reserved; 178 struct { 179 UINT32 reserved_00_07 :8; 180 UINT32 accessed :1; 181 UINT32 readable :1; 182 UINT32 conforming :1; 183 UINT32 mbo_11 :1; // Must Be One 184 UINT32 mbo_12 :1; // Must Be One 185 UINT32 dpl :2; // Descriptor Privilege Level 186 UINT32 present :1; 187 UINT32 reserved_19_16 :4; 188 UINT32 avl :1; // Available to software 189 UINT32 long_mode :1; 190 UINT32 default_size :1; 191 UINT32 granularity :1; 192 UINT32 reserved_31_24 :8; 193 } hi; 194 } EM64T_CODE_SEGMENT_DESCRIPTOR; 195 196 #define CS_SELECTOR_CPL_BIT 0x3 197 198 199 // TSS Entry in Global Descriptor Table(GDT) 200 typedef struct _EM64T_TSS_SEGMENT_DESCRIPTOR { 201 struct { 202 UINT32 segment_limit_00_15 :16; 203 UINT32 base_address_00_15 :16; 204 } q0; 205 struct { 206 UINT32 base_address_23_16 :8; 207 UINT32 type :4; 208 UINT32 mbz_12 :1; 209 UINT32 dpl :2; 210 UINT32 present :1; 211 UINT32 segment_limit_16_19 :4; 212 UINT32 avl :1; 213 UINT32 mbz_21_22 :2; 214 UINT32 granularity :1; 215 UINT32 base_address_31_24 :8; 216 } q1; 217 struct { 218 UINT32 base_address_32_63; 219 } q2; 220 UINT32 q3; // reserved, must be zero 221 } EM64T_TSS_SEGMENT_DESCRIPTOR; 222 223 typedef struct _EM64T_TASK_STATE_SEGMENT { 224 UINT32 reserved_1; 225 UINT64 rsp[3]; 226 UINT64 reserved_2; 227 UINT64 ist[7]; 228 UINT64 reserved_3; 229 UINT16 reserved4; 230 UINT16 io_bitmap_address; // offset inside TSS 231 UINT8 io_bitmap_last_byte; 232 UINT8 pad[7]; 233 } PACKED EM64T_TASK_STATE_SEGMENT; 234 235 236 // Page-Map Level-4 and Ptr Directory Page Table 237 typedef struct _EM64T_PML4 { 238 struct { 239 UINT32 present :1; 240 UINT32 rw :1; 241 UINT32 us :1; // user / supervisor 242 UINT32 pwt :1; // Page Write Through 243 UINT32 pcd :1; // Page Cache Disable 244 UINT32 accessed :1; 245 UINT32 ignored :1; 246 UINT32 zeroes :2; 247 UINT32 avl :3; // available to software 248 UINT32 base_address_lo :20; // bits 31..12 of base address (low bits are zeroes) 249 } lo; 250 struct { 251 UINT32 base_address_hi :20; // bits 51..32 of base address 252 UINT32 available :11; 253 UINT32 no_execute :1; 254 } hi; 255 } EM64T_PML4, EM64T_PDPE; 256 257 258 // Page Table Entry for 2MB pages 259 typedef struct _EM64T_PDE_2MB { 260 struct { 261 UINT32 present :1; 262 UINT32 rw :1; 263 UINT32 us :1; // user / supervisor 264 UINT32 pwt :1; // Page Write Through 265 UINT32 pcd :1; // Page Cache Disable 266 UINT32 accessed :1; 267 UINT32 dirty :1; 268 UINT32 pse :1; // must be set 269 UINT32 global :1; 270 UINT32 avl :3; // available to software 271 UINT32 pat :1; 272 UINT32 zeroes :8; 273 UINT32 base_address_lo :11; // bits 31..21 of base address (low bits are zeroes) 274 } lo; 275 struct { 276 UINT32 base_address_hi :20; // bits 51..32 of base address 277 UINT32 available :11; 278 UINT32 no_execute :1; 279 } hi; 280 } EM64T_PDE_2MB; 281 282 283 // EM64T Interrupt Descriptor Table - Gate Descriptor 284 typedef struct _EM64T_IDT_GATE_DESCRIPTOR { 285 // offset 0 286 UINT32 offset_0_15 :16; // Offset bits 15..0 287 UINT32 css :16; // Command Segment Selector 288 289 // offset 4 290 UINT32 ist :3; // interrupt Stack Table 291 UINT32 reserved_0 :5; // Reserved. must be zeroes 292 UINT32 gate_type :4; // Gate Type. See #defines above 293 UINT32 reserved2_0 :1; // must be zero 294 UINT32 dpl :2; // Descriptor Privilege Level must be zero 295 UINT32 present :1; // Segment Present Flag 296 UINT32 offset_15_31 :16; // Offset bits 31..16 297 298 // offset 8 299 UINT32 offset_32_63; // Offset bits 32..63 300 301 // offset 12 302 UINT32 reserved3; 303 } EM64T_IDT_GATE_DESCRIPTOR; 304 305 typedef EM64T_IDT_GATE_DESCRIPTOR EM64T_IDT_TABLE[256]; 306 307 typedef struct _EM64T_IDT_DESCRIPTOR { 308 UINT16 limit; 309 UINT64 base; 310 } PACKED EM64T_IDT_DESCRIPTOR; 311 312 // IA32_MISC_ENABLE_MSR 313 typedef union _IA32_MISC_ENABLE_MSR { 314 struct { 315 UINT32 FastStringEnable:1; 316 UINT32 Reserved0:1; 317 UINT32 X87FpuFopcodeCompabilityModeEnable:1; 318 UINT32 ThermalMoitor1Enable:1; 319 UINT32 SplitLockDisable:1; 320 UINT32 Reserved1:1; 321 UINT32 ThirdLevelCacheDisable:1; 322 UINT32 PerformanceMonitoringAvailable:1; 323 UINT32 SupressLockEnable:1; 324 UINT32 PrefetchQueueDisable:1; 325 UINT32 FerrInterruptReportingEnable:1; 326 UINT32 BranchTraceStorageUnavailable:1; 327 UINT32 PreciseEventBasedSamplingUnavailable:1; 328 UINT32 Reserved2:6; 329 UINT32 AdjacentCacheLinePrefetchDisable:1; 330 UINT32 Reserved3:4; 331 UINT32 L1DataCacheContextMode:1; 332 UINT32 Reserved4:7; 333 UINT32 Reserved5:32; 334 } Bits; 335 UINT32 Uint32[2]; 336 UINT64 Uint64; 337 } IA32_MISC_ENABLE_MSR; 338 339 // IA-32 MSR Register EFER (0xC0000080) 340 #define EFER_SCE 0x00000001 341 #define EFER_LME 0x00000100 342 #define EFER_LMA 0x00000400 343 #define EFER_NXE 0x00000800 344 345 typedef union _IA32_EFER_S { 346 struct { 347 UINT32 SCE:1; // (00) SysCall Enable/Disable (R/W) 348 UINT32 Reserved_0:7; // 349 UINT32 LME:1; // (08) Long Mode Enable (IA-32e) (R/W) 350 UINT32 Reserved_1:1; // 351 UINT32 LMA:1; // (10) Long Mode Active (IA-32e) (R) 352 UINT32 NXE:1; // (11) Execute Disabled Enable (R/W) 353 UINT32 Reserved_2:20; // 354 UINT32 Reserved_3:32; // 355 } Bits; 356 struct { 357 UINT32 Lower; 358 UINT32 Upper; 359 } Uint32; 360 UINT64 Uint64; 361 } IA32_EFER_S; 362 363 // offset in the VMCS MsrBitmap structure for subset of MSR to force VmExit 364 #define IA32_EFER_WRITE_MSR_VMCS_BITMAP_BYTES_OFFSET 0x80 365 #define IA32_EFER_WRITE_MSR_VMCS_BITMAP_BIT 0x1 366 367 368 #define IA32_SIZE_OF_RDMSR_INST 2 369 #define IA32_SIZE_OF_WRMSR_INST 2 370 371 372 373 // Yonah/Merom specific MSRs 374 //#define IA32_PMG_IO_CAPTURE_INDEX 0xE4 375 376 typedef union _IA32_PMG_IO_CAPTURE_MSR { 377 struct { 378 UINT32 Lvl2BaseAddress:16; 379 UINT32 CstRange:7; 380 UINT32 Reserved_0:9; 381 UINT32 Reserved_1:32; 382 } Bits; 383 UINT64 Uint64; 384 } IA32_PMG_IO_CAPTURE_MSR; 385 386 387 #pragma PACK_OFF 388 389 #endif // _EM64T_DEFS_H_ 390 391