github.com/jlmucb/cloudproxy@v0.0.0-20170830161738-b5aa0b619bc4/cpvmm/common/include/arch/ia32_defs.h (about) 1 /* 2 * Copyright (c) 2013 Intel Corporation 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * Unless required by applicable law or agreed to in writing, software 9 * distributed under the License is distributed on an "AS IS" BASIS, 10 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 11 * See the License for the specific language governing permissions and 12 * limitations under the License. 13 */ 14 15 #ifndef _IA32_DEFS_H_ 16 #define _IA32_DEFS_H_ 17 18 #pragma PACK_ON 19 20 // Segment Selector Definitions 21 22 #define IA32_SELECTOR_INDEX_MASK 0xFFF8 23 24 25 // Note About IA32_SELECTOR 26 // ------------------------ 27 // Although actual selectors are 16-bit fields, the following IA32_SELECTOR 28 // definition is of a 32-bit union. This is done because standard C requires 29 // bit fields to reside within an int-sized variable. 30 31 typedef union 32 { 33 struct 34 { 35 UINT32 rpl : 2; // Bits 1-0 36 UINT32 ti : 1; // Bit 2 37 UINT32 index : 13; // Bits 3-15 38 UINT32 dummy : 16; // Fill up to 32 bits. Actual selector is 16 bits. 39 } bits; 40 UINT16 sel16; 41 UINT32 dummy; 42 } PACKED IA32_SELECTOR; 43 44 45 // Descriptor Definitions 46 typedef struct { 47 UINT16 limit; 48 UINT32 base; 49 } PACKED IA32_GDTR, IA32_IDTR; 50 51 typedef struct { 52 struct { 53 UINT32 limit_15_00 : 16; 54 UINT32 base_address_15_00 : 16; 55 } lo; 56 struct { 57 UINT32 base_address_23_16 : 8; 58 UINT32 accessed : 1; 59 UINT32 writable : 1; 60 UINT32 expansion_direction : 1; 61 UINT32 mbz_11 : 1; // Must Be Zero 62 UINT32 mbo_12 : 1; // Must Be One 63 UINT32 dpl : 2; // Descriptor Privilege Level 64 UINT32 present : 1; 65 UINT32 limit_19_16 : 4; 66 UINT32 avl : 1; // Available to software 67 UINT32 mbz_21 : 1; // Must Be Zero 68 UINT32 big : 1; 69 UINT32 granularity : 1; 70 UINT32 base_address_31_24 : 8; 71 } hi; 72 } PACKED IA32_DATA_SEGMENT_DESCRIPTOR; 73 74 typedef struct { 75 struct { 76 UINT32 limit_15_00 : 16; 77 UINT32 base_address_15_00 : 16; 78 } lo; 79 struct { 80 UINT32 base_address_23_16 : 8; 81 UINT32 accessed : 1; 82 UINT32 readable : 1; 83 UINT32 conforming : 1; 84 UINT32 mbo_11 : 1; // Must Be One 85 UINT32 mbo_12 : 1; // Must Be One 86 UINT32 dpl : 2; // Descriptor Privilege Level 87 UINT32 present : 1; 88 UINT32 limit_19_16 : 4; 89 UINT32 avl : 1; // Available to software 90 UINT32 mbz_21 : 1; // Must Be Zero 91 UINT32 default_size : 1; // 0 = 16-bit segment; 1 = 32-bit segment 92 UINT32 granularity : 1; 93 UINT32 base_address_31_24 : 8; 94 } hi; 95 } PACKED IA32_CODE_SEGMENT_DESCRIPTOR; 96 97 typedef struct { 98 struct { 99 UINT32 limit_15_00 : 16; 100 UINT32 base_address_15_00 : 16; 101 } lo; 102 struct { 103 UINT32 base_address_23_16 : 8; 104 UINT32 type : 4; 105 UINT32 s : 1; // 0 = system; 1 = code or data 106 UINT32 dpl : 2; // Descriptor Privilege Level 107 UINT32 present : 1; 108 UINT32 limit_19_16 : 4; 109 UINT32 avl : 1; // Available to software 110 UINT32 mbz_21 : 1; // Must Be Zero 111 UINT32 default_size : 1; // 0 = 16-bit segment; 1 = 32-bit segment 112 UINT32 granularity : 1; 113 UINT32 base_address_31_24 : 8; 114 } hi; 115 } PACKED IA32_GENERIC_SEGMENT_DESCRIPTOR; 116 117 typedef struct { 118 struct { 119 UINT32 limit_15_00 : 16; 120 UINT32 base_address_15_00 : 16; 121 } lo; 122 struct { 123 UINT32 base_address_23_16 : 8; 124 UINT32 mbo_8 : 1; // Must Be One 125 UINT32 busy : 1; 126 UINT32 mbz_10 : 1; // Must Be Zero 127 UINT32 mbo_11 : 1; // Must Be One 128 UINT32 mbz_12 : 1; // Must Be Zero 129 UINT32 dpl : 2; // Descriptor Privilege Level 130 UINT32 present : 1; 131 UINT32 limit_19_16 : 4; 132 UINT32 avl : 1; // Available to software 133 UINT32 mbz_21 : 1; // Must Be Zero 134 UINT32 mbz_22 : 1; // Must Be Zero 135 UINT32 granularity : 1; 136 UINT32 base_address_31_24 : 8; 137 } hi; 138 } PACKED IA32_STACK_SEGMENT_DESCRIPTOR; 139 140 typedef struct { 141 UINT16 limit_15_00; 142 UINT16 base_address_15_00; 143 UINT8 base_address_23_16; 144 UINT16 attributes; 145 UINT8 base_address_31_24; 146 } PACKED IA32_GENERIC_SEGMENT_DESCRIPTOR_ATTR; 147 148 typedef union 149 { 150 IA32_GENERIC_SEGMENT_DESCRIPTOR gen; 151 IA32_GENERIC_SEGMENT_DESCRIPTOR_ATTR gen_attr; 152 IA32_DATA_SEGMENT_DESCRIPTOR ds; 153 IA32_CODE_SEGMENT_DESCRIPTOR cs; 154 IA32_STACK_SEGMENT_DESCRIPTOR tss; 155 // TODO: add system segment descriptor 156 struct { 157 UINT32 lo; 158 UINT32 hi; 159 } desc32; 160 UINT64 desc64; 161 } PACKED IA32_SEGMENT_DESCRIPTOR; 162 163 // Note About IA32_SEGMENT_DESCRIPTOR_ATTR 164 // --------------------------------------- 165 // Although actual attributes are 16-bit fields, the following 166 // definition is of a 32-bit union. This is done because standard C requires 167 // bit fields to reside within an int-sized variable. 168 169 typedef union 170 { 171 struct { 172 UINT32 type : 4; 173 UINT32 s : 1; // 0 = system; 1 = code or data 174 UINT32 dpl : 2; // Descriptor Privilege Level 175 UINT32 present : 1; 176 UINT32 limit_19_16 : 4; 177 UINT32 avl : 1; // Available to software 178 UINT32 mbz_21 : 1; // Must Be Zero 179 UINT32 default_size : 1; // 0 = 16-bit segment; 1 = 32-bit segment 180 UINT32 granularity : 1; 181 UINT32 dummy : 16; // Fill up to 32 bits. Actual attributes 182 // are 16 bits. 183 } bits; 184 UINT16 attr16; 185 UINT32 dummy; // Fill up to 32 bits. Actual attributes are 16 bits. 186 } PACKED IA32_SEGMENT_DESCRIPTOR_ATTR; 187 188 // ICR Definitions 189 typedef union { 190 struct { 191 UINT32 reserved_1 : 24; 192 UINT32 destination : 8; 193 } bits; 194 UINT32 uint32; 195 } IA32_ICR_HIGH; 196 197 typedef union { 198 struct { 199 UINT32 vector : 8; 200 UINT32 delivery_mode : 3; 201 UINT32 destination_mode : 1; 202 UINT32 delivery_status : 1; 203 UINT32 reserved_1 : 1; 204 UINT32 level : 1; 205 UINT32 trigger_mode : 1; 206 UINT32 reserved_2 : 2; 207 UINT32 destination_shorthand : 2; 208 UINT32 reserved_3 : 12; 209 } bits; 210 UINT32 uint32; 211 } IA32_ICR_LOW; 212 213 typedef struct { 214 IA32_ICR_LOW lo_dword; 215 IA32_ICR_HIGH hi_dword; 216 } IA32_ICR; 217 218 219 // Local APIC Memory Mapped I/O register offsets 220 #define LOCAL_APIC_IDENTIFICATION_OFFSET 0x020 221 #define LOCAL_APIC_IDENTIFICATION_OFFSET_HIGH LOCAL_APIC_IDENTIFICATION_OFFSET + 0x3 222 #define LOCAL_APIC_VERSION_OFFSET 0x030 223 #define LOCAL_APIC_TASK_PRIORITY_OFFSET 0x080 224 #define LOCAL_APIC_ARBITRATION_PRIORITY_OFFSET 0x090 225 #define LOCAL_APIC_PROCESSOR_PRIORITY_OFFSET 0x0A0 226 #define LOCAL_APIC_EOI_OFFSET 0x0B0 227 #define LOCAL_APIC_LOGICAL_DESTINATION_OFFSET 0x0D0 228 #define LOCAL_APIC_DESTINATION_FORMAT_OFFSET 0x0E0 229 #define LOCAL_APIC_SPURRIOUS_INTERRUPT_VECTOR_OFFSET 0x0F0 230 #define LOCAL_APIC_ISR_OFFSET 0x100 231 #define LOCAL_APIC_TMR_OFFSET 0x180 232 #define LOCAL_APIC_IRR_OFFSET 0x200 233 #define LOCAL_APIC_ERROR_STATUS_OFFSET 0x280 234 #define LOCAL_APIC_ICR_OFFSET 0x300 235 #define LOCAL_APIC_ICR_OFFSET_HIGH LOCAL_APIC_ICR_OFFSET + 0x10 236 #define LOCAL_APIC_LVT_TIMER_OFFSET 0x320 237 #define LOCAL_APIC_LVT_THERMAL_SENSOR_OFFSET 0x330 238 #define LOCAL_APIC_LVT_PERFORMANCE_MONITOR_COUNTERS_OFFSET 0x340 239 #define LOCAL_APIC_LVT_LINT0_OFFSET 0x350 240 #define LOCAL_APIC_LVT_LINT1_OFFSET 0x360 241 #define LOCAL_APIC_LVT_ERROR_OFFSET 0x370 242 #define LOCAL_APIC_INITIAL_COUNT_OFFSET 0x380 243 #define LOCAL_APIC_CURRENT_COUNT_OFFSET 0x390 244 #define LOCAL_APIC_DIVIDE_CONFIGURATION_OFFSET 0x3E0 245 #define LOCAL_APIC_MAXIMUM_OFFSET 0x3E4 246 247 #define LOCAL_APIC_ID_LOW_RESERVED_BITS_COUNT 24 248 249 #define LOCAL_APIC_DESTINATION_BROADCAST 0xFF 250 251 #define LOCAL_APIC_DESTINATION_MODE_PHYSICAL 0x0 252 #define LOCAL_APIC_DESTINATION_MODE_LOGICAL 0x1 253 254 #define LOCAL_APIC_DELIVERY_STATUS_IDLE 0x0 255 #define LOCAL_APIC_DELIVERY_STATUS_SEND_PENDING 0x1 256 257 #define LOCAL_APIC_DELIVERY_MODE_FIXED 0x0 258 #define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 0x1 259 #define LOCAL_APIC_DELIVERY_MODE_SMI 0x2 260 #define LOCAL_APIC_DELIVERY_MODE_REMOTE_READ 0x3 261 #define LOCAL_APIC_DELIVERY_MODE_NMI 0x4 262 #define LOCAL_APIC_DELIVERY_MODE_INIT 0x5 263 #define LOCAL_APIC_DELIVERY_MODE_SIPI 0x6 264 #define LOCAL_APIC_DELIVERY_MODE_MAX 0x7 265 266 #define LOCAL_APIC_TRIGGER_MODE_EDGE 0x0 267 #define LOCAL_APIC_TRIGGER_MODE_LEVEL 0x1 268 269 #define LOCAL_APIC_DELIVERY_LEVEL_DEASSERT 0x0 270 #define LOCAL_APIC_DELIVERY_LEVEL_ASSERT 0x1 271 272 #define LOCAL_APIC_BROADCAST_MODE_SPECIFY_CPU 0x0 273 #define LOCAL_APIC_BROADCAST_MODE_SELF 0x1 274 #define LOCAL_APIC_BROADCAST_MODE_ALL_INCLUDING_SELF 0x2 275 #define LOCAL_APIC_BROADCAST_MODE_ALL_EXCLUDING_SELF 0x3 276 277 // get LOCAL_APIC_BASE from IA32_MSR_APIC_BASE_INDEX 278 #define LOCAL_APIC_BASE_MSR_MASK (~0xFFF) 279 280 281 #pragma PACK_OFF 282 283 #endif // _IA32_DEFS_H_ 284