github.com/jlmucb/cloudproxy@v0.0.0-20170830161738-b5aa0b619bc4/cpvmm/common/include/arch/msr_defs.h (about)

     1  /*
     2   * Copyright (c) 2013 Intel Corporation
     3   *
     4   * Licensed under the Apache License, Version 2.0 (the "License");
     5   * you may not use this file except in compliance with the License.
     6   * You may obtain a copy of the License at
     7   *     http://www.apache.org/licenses/LICENSE-2.0
     8   * Unless required by applicable law or agreed to in writing, software
     9   * distributed under the License is distributed on an "AS IS" BASIS,
    10   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    11   * See the License for the specific language governing permissions and
    12   * limitations under the License.
    13   */
    14  
    15  #ifndef _MSR_DEFS_H_
    16  #define _MSR_DEFS_H_
    17  
    18  
    19  // Performance Counter MSR Indexes
    20  #define IA32_MSR_CRU_ESCR1      0x3B9
    21  #define IA32_MSR_IQ_CCCR2       0x36E
    22  #define IA32_MSR_IQ_COUNTER2    0x30E
    23  
    24  // Standard MSR Indexes
    25  #define IA32_INVALID_MSR_INDEX          (UINT32)0xffffffff
    26  #define IA32_MSR_TIME_STAMP_COUNTER     (UINT32)0x010
    27  #define IA32_MSR_APIC_BASE              0x01B
    28  #define IA32_MSR_FEATURE_CONTROL        (UINT32)0x03A
    29  #define IA32_MSR_x2APIC_BASE            (UINT32)0x800
    30  #define IA32_MSR_SYSENTER_CS            (UINT32)0x174
    31  #define IA32_MSR_SYSENTER_ESP           (UINT32)0x175
    32  #define IA32_MSR_SYSENTER_EIP           (UINT32)0x176
    33  #define IA32_MSR_MISC_ENABLE            (UINT32)0x1A0
    34  
    35  #define IA32_MSR_DEBUGCTL               (UINT32)0x1D9
    36      #define IA32_MSR_DEBUGCTL_LBR                   BIT_VALUE64(0)
    37      #define IA32_MSR_DEBUGCTL_BTF                   BIT_VALUE64(1)
    38      #define IA32_MSR_DEBUGCTL_TR                    BIT_VALUE64(6)
    39      #define IA32_MSR_DEBUGCTL_BTS                   BIT_VALUE64(7)
    40      #define IA32_MSR_DEBUGCTL_BTINT                 BIT_VALUE64(8)
    41      #define IA32_MSR_DEBUGCTL_BTS_OFF_OS            BIT_VALUE64(9)
    42      #define IA32_MSR_DEBUGCTL_BTS_OFF_USR           BIT_VALUE64(10)
    43      #define IA32_MSR_DEBUGCTL_FREEZE_LBRS_ON_PMI    BIT_VALUE64(11)
    44      #define IA32_MSR_DEBUGCTL_FREEZE_PERFMON_ON_PMI BIT_VALUE64(12)
    45      #define IA32_MSR_DEBUGCTL_FREEZE_WHILE_SMM_EN   BIT_VALUE64(14)
    46      #define IA32_MSR_DEBUGCTL_RESERVED                                         \
    47         ~( IA32_MSR_DEBUGCTL_LBR                                                \
    48          | IA32_MSR_DEBUGCTL_BTF                                                \
    49          | IA32_MSR_DEBUGCTL_TR                                                 \
    50          | IA32_MSR_DEBUGCTL_BTS                                                \
    51          | IA32_MSR_DEBUGCTL_BTINT                                              \
    52          | IA32_MSR_DEBUGCTL_BTS_OFF_OS                                         \
    53          | IA32_MSR_DEBUGCTL_BTS_OFF_USR                                        \
    54          | IA32_MSR_DEBUGCTL_FREEZE_LBRS_ON_PMI                                 \
    55          | IA32_MSR_DEBUGCTL_FREEZE_PERFMON_ON_PMI                              \
    56          |IA32_MSR_DEBUGCTL_FREEZE_WHILE_SMM_EN)
    57  
    58  #define IA32_MSR_PAT                    (UINT32)0x277
    59  
    60  #define IA32_MSR_PERF_GLOBAL_CTRL       (UINT32)0x38F
    61      #define IA32_MSR_PERF_GLOBAL_CTRL_PMC0          BIT_VALUE64(0)
    62      #define IA32_MSR_PERF_GLOBAL_CTRL_PMC1          BIT_VALUE64(1)
    63      #define IA32_MSR_PERF_GLOBAL_CTRL_FIXED_CTR0    BIT_VALUE64(31)
    64      #define IA32_MSR_PERF_GLOBAL_CTRL_FIXED_CTR1    BIT_VALUE64(32)
    65      #define IA32_MSR_PERF_GLOBAL_CTRL_FIXED_CTR2    BIT_VALUE64(33)
    66      #define IA32_MSR_PERF_GLOBAL_CTRL_RESERVED                                 \
    67          ( IA32_MSR_PERF_GLOBAL_CTRL_PMC0                                       \
    68          | IA32_MSR_PERF_GLOBAL_CTRL_PMC1                                       \
    69          | IA32_MSR_PERF_GLOBAL_CTRL_FIXED_CTR0                                 \
    70          | IA32_MSR_PERF_GLOBAL_CTRL_FIXED_CTR1                                 \
    71          | IA32_MSR_PERF_GLOBAL_CTRL_FIXED_CTR2)
    72  
    73  
    74  #define IA32_MSR_PEBS_ENABLE            (UINT32)0x3F1
    75  #define IA32_MSR_EFER                   (UINT32)0xC0000080
    76  
    77  
    78  #define IA32_MSR_FS_BASE                (UINT32)0xC0000100
    79  #define IA32_MSR_GS_BASE                (UINT32)0xC0000101
    80  
    81  // MTRR MSR Indexes
    82  #define IA32_MSR_MTRRCAP               0xFE
    83  #define IA32_MSR_MTRR_DEF_TYPE         0x2FF
    84  #define IA32_MSR_VARIABLE_MTRR         0x200
    85  #define IA32_MSR_FIXED_MTRR_64K_00000  0x250
    86  #define IA32_MSR_FIXED_MTRR_16K_80000  0x258
    87  #define IA32_MSR_FIXED_MTRR_16K_A0000  0x259
    88  #define IA32_MSR_FIXED_MTRR_4K_C0000   0x268
    89  #define IA32_MSR_FIXED_MTRR_4K_C8000   0x269
    90  #define IA32_MSR_FIXED_MTRR_4K_D0000   0x26A
    91  #define IA32_MSR_FIXED_MTRR_4K_D8000   0x26B
    92  #define IA32_MSR_FIXED_MTRR_4K_E0000   0x26C
    93  #define IA32_MSR_FIXED_MTRR_4K_E8000   0x26D
    94  #define IA32_MSR_FIXED_MTRR_4K_F0000   0x26E
    95  #define IA32_MSR_FIXED_MTRR_4K_F8000   0x26F
    96  
    97  // Microcode Update MSR Indexs
    98  #define IA32_MSR_BIOS_SIGNATURE      0x8B
    99  #define IA32_MSR_BIOS_UPDATE_TRIGGER 0x79
   100  
   101  // Yonah/Merom specific MSRs
   102  #define IA32_MSR_PMG_IO_CAPTURE      0xE4
   103  
   104  
   105  #endif // _MSR_DEFS_H_
   106  
   107