github.com/jlmucb/cloudproxy@v0.0.0-20170830161738-b5aa0b619bc4/cpvmm/vmm/include/hw/pci_configuration.h (about) 1 /* 2 * Copyright (c) 2013 Intel Corporation 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * Unless required by applicable law or agreed to in writing, software 9 * distributed under the License is distributed on an "AS IS" BASIS, 10 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 11 * See the License for the specific language governing permissions and 12 * limitations under the License. 13 */ 14 15 #ifndef _PCI_CONFIGURATION_H 16 #define _PCI_CONFIGURATION_H 17 18 #include "vmm_defs.h" 19 20 #define PCI_CONFIG_SPACE_SIZE 0x100 21 22 // PCI config header fileds 23 #define PCI_CONFIG_VENDOR_ID_OFFSET 0x00 24 #define PCI_CONFIG_DEVICE_ID_OFFSET 0x02 25 #define PCI_CONFIG_COMMAND_OFFSET 0x04 26 #define PCI_CONFIG_REVISION_ID_OFFSET 0x08 27 #define PCI_CONFIG_CLASS_CODE_OFFSET 0x09 28 #define PCI_CONFIG_PROGRAMMING_INTERFACE_OFFSET PCI_CONFIG_CLASS_CODE_OFFSET 29 #define PCI_CONFIG_SUB_CLASS_CODE_OFFSET 0x0A 30 #define PCI_CONFIG_BASE_CLASS_CODE_OFFSET 0x0B 31 #define PCI_CONFIG_CACHE_LINE_SIZE_OFFSET 0x0C 32 #define PCI_CONFIG_LATENCY_TIMER_OFFSET 0x0D 33 #define PCI_CONFIG_HEADER_TYPE_OFFSET 0x0E 34 #define PCI_CONFIG_BIST_OFFSET 0x0F 35 #define PCI_CONFIG_BAR_OFFSET 0x10 36 #define PCI_CONFIG_BAR_LAST_OFFSET 0x24 37 #define PCI_CONFIG_CARD_BUS_CIS_PTR_OFFSET 0x28 38 #define PCI_CONFIG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C 39 #define PCI_CONFIG_SUBSYSTEM_ID_OFFSET 0x2E 40 #define PCI_CONFIG_EXPANSION_ROM_BASE_OFFSET 0x30 41 #define PCI_CONFIG_CAPABILITIES_PTR_OFFSET 0x34 42 #define PCI_CONFIG_INTERRUPT_LINE_OFFSET 0x3C 43 #define PCI_CONFIG_INTERRUPT_PIN_OFFSET 0x3D 44 #define PCI_CONFIG_MIN_GNT_OFFSET 0x3E 45 #define PCI_CONFIG_MAX_LAT_OFFSET 0x3F 46 47 // for PCI config of type '1' (bridge) 48 #define PCI_CONFIG_SECONDARY_BUS_OFFSET 0x19 49 #define PCI_CONFIG_BRIDGE_MEMORY_BASE 0x20 50 #define PCI_CONFIG_BRIDGE_MEMORY_LIMIT 0x22 51 #define PCI_CONFIG_BRIDGE_IO_BASE_LOW 0x1C 52 #define PCI_CONFIG_BRIDGE_IO_LIMIT_LOW 0x1D 53 #define PCI_CONFIG_BRIDGE_IO_BASE_HIGH 0x30 54 #define PCI_CONFIG_BRIDGE_IO_LIMIT_HIGH 0x32 55 56 57 #define PCI_BASE_CLASS_BRIDGE 0x06 58 59 #define PCI_CONFIG_ADDRESS_REGISTER 0xCF8 60 #define PCI_CONFIG_DATA_REGISTER 0xCFC 61 62 #define PCI_INVALID_VENDOR_ID 0xFFFF 63 #define PCI_INVALID_DEVICE_ID PCI_INVALID_VENDOR_ID 64 65 #define PCI_CONFIG_HEADER_TYPE_DEVICE 0x0 66 #define PCI_CONFIG_HEADER_TYPE_PCI2PCI_BRIDGE 0x1 67 #define PCI_CONFIG_HEADER_TYPE_CARDBUS_BRIDGE 0x2 68 69 #define PCI_MAX_NUM_BUSES (UINT16) 256 70 #define PCI_MAX_NUM_DEVICES_ON_BUS (UINT16) 32 71 #define PCI_MAX_NUM_FUNCTIONS_ON_DEVICE (UINT16) 8 72 #define PCI_MAX_NUM_FUNCTIONS (PCI_MAX_NUM_BUSES * PCI_MAX_NUM_DEVICES_ON_BUS * PCI_MAX_NUM_FUNCTIONS_ON_DEVICE) 73 74 #define PCI_MAX_NUM_SUPPORTED_DEVICES 0x100 75 #define PCI_MAX_PATH 16 76 77 #define PCI_IS_ADDRESS_VALID(bus, device, function) (bus < PCI_MAX_NUM_BUSES && device < PCI_MAX_NUM_DEVICES_ON_BUS && function < PCI_MAX_NUM_FUNCTIONS_ON_DEVICE) 78 #define PCI_GET_ADDRESS(bus, device, function) (bus << 8 | device << 3 | function) 79 80 #define PCI_CONFIG_HEADER_BAR_MEMORY_TYPE_MASK (UINT64) 0x1 81 #define PCI_CONFIG_HEADER_BAR_ADDRESS_TYPE_MASK (UINT64) 0x6 82 #define PCI_CONFIG_HEADER_BAR_IO_ENCODING_MASK (UINT64) 0x3 83 #define PCI_CONFIG_HEADER_BAR_MEM_ENCODING_MASK (UINT64) 0xf 84 #define PCI_CONFIG_HEADER_COMMAND_IOSPACE_MASK (UINT64) 0x1 85 #define PCI_CONFIG_HEADER_COMMAND_MEMORY_MASK (UINT64) 0x2 86 #define PCI_CONFIG_HEADER_BAR_SIZING_COMMAND 0xFFFFFFFF 87 #define PCI_BAR_MMIO_REGION (BAR_TYPE)0 88 #define PCI_BAR_IO_REGION (BAR_TYPE)1 89 #define PCI_BAR_UNUSED (BAR_TYPE)-1 90 #define PCI_CONFIG_HEADER_BAR_ADDRESS_MASK_TYPE_MMIO (UINT64) ~(0xf) 91 #define PCI_CONFIG_HEADER_BAR_ADDRESS_MASK_TYPE_IO (UINT64) ~(0x3) 92 #define PCI_CONFIG_HEADER_BAR_ADDRESS_32 0 93 #define PCI_CONFIG_HEADER_BAR_ADDRESS_64 0x2 94 95 #if (PCI_MAX_NUM_SUPPORTED_DEVICES <= 0x100) 96 typedef UINT8 PCI_DEV_INDEX; 97 #elif (PCI_MAX_NUM_SUPPORTED_DEVICES <= 0x10000) 98 typedef UINT16 PCI_DEV_INDEX; 99 #else 100 typedef UINT32 PCI_DEV_INDEX; 101 #endif 102 103 #pragma warning (push) 104 #pragma warning (disable:4214) 105 106 #pragma PACK_ON 107 108 typedef union _PCI_CONFIG_ADDRESS 109 { 110 struct 111 { 112 UINT32 113 Register:8, 114 Function:3, 115 Device:5, 116 Bus:8, 117 Reserved:7, 118 Enable:1; 119 } Bits; 120 UINT32 Uint32; 121 } PCI_CONFIG_ADDRESS; 122 123 typedef UINT16 PCI_DEVICE_ADDRESS; 124 125 #define PCI_BUS_MASK 0xff00 126 #define PCI_DEVICE_MASK 0x00f8 127 #define PCI_FUNCTION_MASK 0x0007 128 129 #define GET_PCI_BUS(addr) (UINT8)(BITMAP_GET((addr), PCI_BUS_MASK) >> 8) 130 #define GET_PCI_DEVICE(addr) (UINT8)(BITMAP_GET((addr), PCI_DEVICE_MASK) >> 3) 131 #define GET_PCI_FUNCTION(addr) (UINT8)(BITMAP_GET((addr), PCI_FUNCTION_MASK)) 132 133 #define SET_PCI_BUS(addr, bus) BITMAP_ASSIGN((addr), PCI_BUS_MASK, (bus) << 8) 134 #define SET_PCI_DEVICE(addr, device) BITMAP_ASSIGN((addr), PCI_DEVICE_MASK, (device) << 3) 135 #define SET_PCI_FUNCTION(addr, function) BITMAP_ASSIGN((addr), PCI_FUNCTION_MASK, (function)) 136 137 #pragma PACK_OFF 138 139 #pragma warning (pop) 140 141 typedef struct _PCI_PATH_ELEMENT 142 { 143 UINT8 device; 144 UINT8 function; 145 } PCI_PATH_ELEMENT; 146 147 typedef struct _PCI_PATH 148 { 149 UINT8 start_bus; 150 PCI_PATH_ELEMENT path[PCI_MAX_PATH]; 151 } PCI_PATH; 152 153 #define PCI_MAX_BAR_NUMBER 6 154 155 typedef enum 156 { 157 BAR_TYPE_IO, 158 BAR_TYPE_MMIO 159 } BAR_TYPE; 160 161 #define PCI_MAX_BAR_NUMBER_IN_BRIDGE 2 162 163 typedef struct _PCI_BASE_ADDRESS_REGISTER 164 { 165 BAR_TYPE type; 166 char padding1[4]; 167 UINT64 addr; 168 UINT64 length; 169 } PCI_BASE_ADDRESS_REGISTER; 170 171 #endif