github.com/jlmucb/cloudproxy@v0.0.0-20170830161738-b5aa0b619bc4/cpvmm/vmm/include/hw/vmx_ctrl_msrs.h (about) 1 /* 2 * Copyright (c) 2013 Intel Corporation 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * Unless required by applicable law or agreed to in writing, software 9 * distributed under the License is distributed on an "AS IS" BASIS, 10 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 11 * See the License for the specific language governing permissions and 12 * limitations under the License. 13 */ 14 15 // IA32 VMX Read Only MSR Definitions 16 #ifndef _VMX_CTRL_MSRS_H_ 17 #define _VMX_CTRL_MSRS_H_ 18 19 #include "vmm_defs.h" 20 #include "em64t_defs.h" 21 22 // VMX Capabilities are declared in bit 5 of ECX retured from CPUID 23 #define IA32_CPUID_ECX_VMX 0x20 24 25 // VMX MSR Indexes 26 #define IA32_MSR_OPT_IN_INDEX 0x3A 27 #define IA32_MSR_MSEG_INDEX 0x9B 28 #define IA32_MSR_VMX_BASIC_INDEX 0x480 29 #define IA32_MSR_PIN_BASED_VM_EXECUTION_CONTROLS_INDEX 0x481 30 #define IA32_MSR_PROCESSOR_BASED_VM_EXECUTION_CONTROLS_INDEX 0x482 31 #define IA32_MSR_PROCESSOR_BASED_VM_EXECUTION_CONTROLS2_INDEX 0x48B 32 #define IA32_MSR_VM_EXIT_CONTROLS_INDEX 0x483 33 #define IA32_MSR_VM_ENTRY_CONTROLS_INDEX 0x484 34 #define IA32_MSR_MISCELLANEOUS_DATA_INDEX 0x485 35 #define IA32_MSR_CR0_ALLOWED_ZERO_INDEX 0x486 36 #define IA32_MSR_CR0_ALLOWED_ONE_INDEX 0x487 37 #define IA32_MSR_CR4_ALLOWED_ZERO_INDEX 0x488 38 #define IA32_MSR_CR4_ALLOWED_ONE_INDEX 0x489 39 #define IA32_MSR_VMX_VMCS_ENUM 0x48A 40 #define IA32_MSR_EPT_VPID_CAP_INDEX 0x48C 41 #define IA32_MSR_TRUE_PINBASED_CTLS_INDEX 0x48D 42 #define IA32_MSR_TRUE_PROCBASED_CTLS_INDEX 0x48E 43 #define IA32_MSR_TRUE_EXIT_CTLS_INDEX 0x48F 44 #define IA32_MSR_TRUE_ENTRY_CTLS_INDEX 0x490 45 #ifdef FAST_VIEW_SWITCH 46 #define IA32_MSR_VMX_VMFUNC_CTRL 0x491 47 #endif 48 49 #define IA32_MSR_VMX_FIRST 0x480 50 #ifdef FAST_VIEW_SWITCH 51 #define IA32_MSR_VMX_LAST 0x491 52 #else 53 #define IA32_MSR_VMX_LAST 0x490 54 #endif 55 56 57 // synonyms 58 #define IA32_MSR_VMCS_REVISION_IDENTIFIER_INDEX IA32_MSR_VMX_BASIC_INDEX 59 60 #pragma PACK_ON 61 62 // VMX MSR Structure - IA32_MSR_OPT_IN_INDEX - Index 0x3A 63 typedef union { 64 struct { 65 UINT32 Lock:1; // 0=Unlocked, 1=Locked 66 UINT32 EnableVmxonInSmx:1; // 0=Disabled, 1=Enabled 67 UINT32 EnableVmxonOutsideSmx:1; // 0=Disabled, 1=Enabled 68 UINT32 Reserved_0:5; 69 UINT32 SenterEnables:8; 70 UINT32 Reserved_1:16; 71 UINT32 Reserved_2:32; 72 } Bits; 73 struct { 74 UINT32 Lower; 75 UINT32 Upper; 76 } Uint32; 77 UINT64 Uint64; 78 } IA32_MSR_OPT_IN; 79 80 // VMX MSR Structure - IA32_MSR_MSEG_INDEX - Index 0x9B 81 typedef union { 82 struct { 83 UINT32 Valid:1; // 0=Invalid, 1=Valid 84 UINT32 Reserved_0:11; 85 UINT32 MsegBaseAddress:20; 86 UINT32 Reserved_1:32; 87 } Bits; 88 UINT64 Uint64; 89 } IA32_MSR_MSEG; 90 91 // VMX MSR Structure - IA32_MSR_VMCS_REVISION_IDENTIFIER_INDEX - Index 0x480 92 typedef union { 93 struct { 94 UINT32 RevisionIdentifier:32; // bits 0-31 95 UINT32 VmcsRegionSize:13; // bits 32-44 96 UINT32 Reserved1_0:3; // bits 45-47 97 UINT32 PhysicalAddressWidth:1; // bit 48 98 UINT32 DualMonitorSystemManagementInterrupts:1; // bit 49 99 UINT32 VmcsMemoryType:4; // bits 50:53 100 UINT32 VmcsInstructionInfoFieldOnIOisValid:1; // bit 54 101 UINT32 Reserved2_0:9; // bits 55-63 102 } Bits; 103 UINT64 Uint64; 104 } IA32_MSR_VMCS_REVISION_IDENTIFIER; 105 106 // VMX MSR Structure - IA32_MSR_PIN_BASED_VM_EXECUTION_CONTROLS_INDEX - Index 0x481 107 typedef union { 108 struct { 109 UINT32 ExternalInterrupt:1; // 0=No VmExit from ext int 110 UINT32 HostInterrupt:1; 111 UINT32 Init:1; 112 UINT32 Nmi:1; 113 UINT32 Sipi:1; 114 UINT32 VirtualNmi:1; 115 UINT32 VmxTimer:1; 116 UINT32 Reserved_1:25; 117 } Bits; 118 UINT32 Uint32; 119 } PIN_BASED_VM_EXECUTION_CONTROLS; 120 121 typedef union { 122 struct { 123 PIN_BASED_VM_EXECUTION_CONTROLS MayBeSetToZero; // Bits, that have 0 values may be set to 0 in VMCS 124 PIN_BASED_VM_EXECUTION_CONTROLS MayBeSetToOne; // Bits, that have 1 values may be set to 1 in VMCS 125 } Bits; 126 UINT64 Uint64; 127 } IA32_MSR_PIN_BASED_VM_EXECUTION_CONTROLS; 128 129 // VMX MSR Structure - IA32_MSR_PROCESSOR_BASED_VM_EXECUTION_CONTROLS_INDEX - Index 0x482 130 typedef union { 131 struct { 132 UINT32 SoftwareInterrupt:1; 133 UINT32 TripleFault:1; 134 UINT32 VirtualInterrupt:1; // InterruptWindow 135 UINT32 UseTscOffsetting:1; 136 UINT32 TaskSwitch:1; 137 UINT32 Cpuid:1; 138 UINT32 GetSec:1; 139 UINT32 Hlt:1; 140 UINT32 Invd:1; 141 UINT32 Invlpg:1; 142 UINT32 Mwait:1; 143 UINT32 Rdpmc:1; 144 UINT32 Rdtsc:1; 145 UINT32 Rsm:1; 146 UINT32 VmInstruction:1; 147 UINT32 Cr3Load:1; 148 UINT32 Cr3Store:1; 149 UINT32 UseCr3Mask:1; 150 UINT32 UseCr3ReadShadow:1; 151 UINT32 Cr8Load:1; 152 UINT32 Cr8Store:1; 153 UINT32 TprShadow:1; 154 UINT32 NmiWindow:1; 155 UINT32 MovDr:1; 156 UINT32 UnconditionalIo:1; 157 UINT32 ActivateIoBitmaps:1; 158 UINT32 MsrProtection:1; 159 UINT32 MonitorTrapFlag:1; 160 UINT32 UseMsrBitmaps:1; 161 UINT32 Monitor:1; 162 UINT32 Pause:1; 163 UINT32 SecondaryControls:1; 164 } Bits; 165 UINT32 Uint32; 166 } PROCESSOR_BASED_VM_EXECUTION_CONTROLS; 167 168 typedef union { 169 struct { 170 PROCESSOR_BASED_VM_EXECUTION_CONTROLS MayBeSetToZero; // Bits, that have 0 values may be set to 0 in VMCS 171 PROCESSOR_BASED_VM_EXECUTION_CONTROLS MayBeSetToOne; // Bits, that have 1 values may be set to 1 in VMCS 172 } Bits; 173 UINT64 Uint64; 174 } IA32_MSR_PROCESSOR_BASED_VM_EXECUTION_CONTROLS; 175 176 // VMX MSR Structure - IA32_MSR_PROCESSOR_BASED_VM_EXECUTION_CONTROLS2_INDEX - Index 0x48B 177 typedef union { 178 struct { 179 UINT32 VirtualizeAPIC:1; 180 UINT32 EnableEPT:1; 181 UINT32 DescriptorTableExiting:1; 182 UINT32 EnableRDTSCP:1; 183 UINT32 ShadowApicMsrs:1; 184 UINT32 EnableVPID:1; 185 UINT32 WBINVD:1; 186 UINT32 UnrestrictedGuest:1; 187 UINT32 Reserved_0:4; 188 UINT32 EnableINVPCID:1; 189 UINT32 Vmfunc:1; // bit 13 190 UINT32 Reserved_1:4; 191 UINT32 VE:1; // bit 18 192 UINT32 Reserved_2:13; 193 } Bits; 194 UINT32 Uint32; 195 } PROCESSOR_BASED_VM_EXECUTION_CONTROLS2; 196 197 typedef union { 198 struct { 199 PROCESSOR_BASED_VM_EXECUTION_CONTROLS2 MayBeSetToZero; // Bits, that have 0 values may be set to 0 in VMCS 200 PROCESSOR_BASED_VM_EXECUTION_CONTROLS2 MayBeSetToOne; // Bits, that have 1 values may be set to 1 in VMCS 201 } Bits; 202 UINT64 Uint64; 203 } IA32_MSR_PROCESSOR_BASED_VM_EXECUTION_CONTROLS2; 204 205 // VMX MSR Structure - IA32_MSR_VM_EXIT_CONTROLS_INDEX - Index 0x483 206 typedef union { 207 struct { 208 UINT32 SaveCr0AndCr4:1; 209 UINT32 SaveCr3:1; 210 UINT32 SaveDebugControls:1; 211 UINT32 SaveSegmentRegisters:1; 212 UINT32 SaveEspEipEflags:1; 213 UINT32 SavePendingDebugExceptions:1; 214 UINT32 SaveInterruptibilityInformation:1; 215 UINT32 SaveActivityState:1; 216 UINT32 SaveWorkingVmcsPointer:1; 217 UINT32 Ia32eModeHost:1; 218 UINT32 LoadCr0AndCr4:1; 219 UINT32 LoadCr3:1; 220 UINT32 Load_IA32_PERF_GLOBAL_CTRL:1; 221 UINT32 LoadSegmentRegisters:1; 222 UINT32 LoadEspEip:1; 223 UINT32 AcknowledgeInterruptOnExit:1; 224 UINT32 SaveSysEnterMsrs:1; 225 UINT32 LoadSysEnterMsrs:1; 226 UINT32 SavePat:1; 227 UINT32 LoadPat:1; 228 UINT32 SaveEfer:1; 229 UINT32 LoadEfer:1; 230 UINT32 SaveVmxTimer:1; 231 UINT32 Reserved_2:9; 232 } Bits; 233 UINT32 Uint32; 234 } VM_EXIT_CONTROLS; 235 236 typedef union { 237 struct { 238 VM_EXIT_CONTROLS MayBeSetToZero; // Bits, that have 0 values may be set to 0 in VMCS 239 VM_EXIT_CONTROLS MayBeSetToOne; // Bits, that have 1 values may be set to 1 in VMCS 240 } Bits; 241 UINT64 Uint64; 242 } IA32_MSR_VM_EXIT_CONTROLS; 243 244 // VMX MSR Structure - IA32_MSR_VM_ENTRY_CONTROLS_INDEX - Index 0x484 245 typedef union { 246 struct { 247 UINT32 LoadCr0AndCr4:1; 248 UINT32 LoadCr3:1; 249 UINT32 LoadDebugControls:1; 250 UINT32 LoadSegmentRegisters:1; 251 UINT32 LoadEspEipEflags:1; 252 UINT32 LoadPendingDebugExceptions:1; 253 UINT32 LoadInterruptibilityInformation:1; 254 UINT32 LoadActivityState:1; 255 UINT32 LoadWorkingVmcsPointer:1; 256 UINT32 Ia32eModeGuest:1; 257 UINT32 EntryToSmm:1; 258 UINT32 TearDownSmmMonitor:1; 259 UINT32 LoadSysEnterMsrs:1; 260 UINT32 Load_IA32_PERF_GLOBAL_CTRL:1; 261 UINT32 LoadPat:1; 262 UINT32 LoadEfer:1; 263 UINT32 Reserved_1:16; 264 } Bits; 265 UINT32 Uint32; 266 } VM_ENTRY_CONTROLS; 267 268 typedef union { 269 struct { 270 VM_ENTRY_CONTROLS MayBeSetToZero; // Bits, that have 0 values may be set to 0 in VMCS 271 VM_ENTRY_CONTROLS MayBeSetToOne; // Bits, that have 1 values may be set to 1 in VMCS 272 } Bits; 273 UINT64 Uint64; 274 } IA32_MSR_VM_ENTRY_CONTROLS; 275 276 277 // VMX MSR Structure - IA32_MSR_MISCELLANEOUS_DATA_INDEX - Index 0x485 278 typedef union { 279 struct { 280 UINT32 PreemptionTimerLength:5; // in TSC ticks 281 UINT32 Reserved_0:1; 282 UINT32 EntryInHaltStateSupported:1; 283 UINT32 EntryInShutdownStateSupported:1; 284 UINT32 EntryInWaitForSipiStateSupported:1; 285 UINT32 Reserved_1:7; 286 UINT32 NumberOfCr3TargetValues:9; 287 UINT32 MsrListsMaxSize:3; // If this value is N, the max supported msr list is 512*(N+1) 288 UINT32 Reserved_2:4; 289 UINT32 MsegRevisionIdentifier:32; 290 } Bits; 291 UINT64 Uint64; 292 } IA32_MSR_MISCELLANEOUS_DATA; 293 294 typedef union { 295 struct { 296 // RWX support 297 UINT32 X_only:1; 298 UINT32 W_only:1; 299 UINT32 W_and_X_only:1; 300 // GAW support 301 UINT32 GAW_21_bit:1; 302 UINT32 GAW_30_bit:1; 303 UINT32 GAW_39_bit:1; 304 UINT32 GAW_48_bit:1; 305 UINT32 GAW_57_bit:1; 306 // EMT support 307 UINT32 UC:1; 308 UINT32 WC:1; 309 UINT32 Reserved0:2; 310 UINT32 WT:1; 311 UINT32 WP:1; 312 UINT32 WB:1; 313 UINT32 Reserved1:1; 314 // SP support 315 UINT32 SP_21_bit:1; 316 UINT32 SP_30_bit:1; 317 UINT32 SP_39_bit:1; 318 UINT32 SP_48_bit:1; 319 320 UINT32 InveptSupported:1; 321 UINT32 Reserved2:3; 322 // INVEPT Support 323 UINT32 InveptIndividualAddress:1; 324 UINT32 InveptContextWide:1; 325 UINT32 InveptAllContexts:1; 326 UINT32 Reserved3:5; 327 328 UINT32 InvvpidSupported:1; 329 UINT32 Reserved4:7; 330 // INVVPID Support 331 UINT32 InvvpidIndividualAddress:1; 332 UINT32 InvvpidContextWide:1; 333 UINT32 InvvpidAllContexts:1; 334 UINT32 InvvpidAllContextsPreservingGlobals:1; 335 UINT32 Reserved5:4; 336 337 UINT32 Reserved6:16; 338 } Bits; 339 UINT64 Uint64; 340 } IA32_VMX_EPT_VPID_CAP; 341 342 // VMX MSR Structure - IA32_MSR_CR0_ALLOWED_ZERO_INDEX, IA32_MSR_CR0_ALLOWED_ONE_INDEX - Index 0x486, 0x487 343 typedef EM64T_CR0 IA32_MSR_CR0; 344 345 346 // VMX MSR Structure - IA32_MSR_CR4_ALLOWED_ZERO_INDEX, IA32_MSR_CR4_ALLOWED_ONE_INDEX - Index 0x488, 0x489 347 typedef EM64T_CR4 IA32_MSR_CR4; 348 349 #ifdef FAST_VIEW_SWITCH 350 // VMX MSR Structure - IA32_MSR_VMFUNC_CTRL - Index 0x491 351 typedef union { 352 struct { 353 UINT32 EptpSwitching:1; 354 UINT32 Reserved_0:31; 355 UINT32 Reserved_1:32; 356 } Bits; 357 UINT64 Uint64; 358 } IA32_MSR_VMFUNC_CTRL; 359 360 typedef enum _VMFUNC_BITS { 361 EPTP_SWITCHING_BIT = 0, 362 } VMFUNC_BITS; 363 #endif 364 #pragma PACK_OFF 365 366 // Structure containing the complete set of VMX MSR Values 367 typedef struct { 368 IA32_MSR_VMCS_REVISION_IDENTIFIER VmcsRevisionIdentifier; 369 IA32_MSR_PIN_BASED_VM_EXECUTION_CONTROLS PinBasedVmExecutionControls; 370 IA32_MSR_PROCESSOR_BASED_VM_EXECUTION_CONTROLS ProcessorBasedVmExecutionControls; 371 IA32_MSR_PROCESSOR_BASED_VM_EXECUTION_CONTROLS2 ProcessorBasedVmExecutionControls2; 372 IA32_MSR_VM_EXIT_CONTROLS VmExitControls; 373 IA32_MSR_VM_ENTRY_CONTROLS VmEntryControls; 374 IA32_MSR_MISCELLANEOUS_DATA MiscellaneousData; 375 IA32_MSR_CR0 Cr0MayBeSetToZero; 376 IA32_MSR_CR0 Cr0MayBeSetToOne; 377 IA32_MSR_CR4 Cr4MayBeSetToZero; 378 IA32_MSR_CR4 Cr4MayBeSetToOne; 379 IA32_VMX_EPT_VPID_CAP EptVpidCapabilities; 380 #ifdef FAST_VIEW_SWITCH 381 IA32_MSR_VMFUNC_CTRL VmFuncControls; 382 #endif 383 } IA32_VMX_CAPABILITIES; 384 385 #endif // _VMX_CTRL_MSRS_H_