github.com/jspc/eggos@v0.5.1-0.20221028160421-556c75c878a5/drivers/e1000/defs.go (about)

     1  package e1000
     2  
     3  const (
     4  	/// Controls the device features and states.
     5  	REG_CTRL = 0x0000
     6  	/// Auto-Speed Detetion Enable.
     7  	CTRL_ASDE = (1 << 5)
     8  	/// Set link up.
     9  	CTRL_SLU = (1 << 6)
    10  	/// Device Reset.
    11  	CTRL_RST = (1 << 26)
    12  
    13  	/// Interrupt Mask Set.
    14  	REG_IMS  = 0x00d0
    15  	IMS_RXT0 = (1 << 7)
    16  
    17  	/// Interrupt Mask Clear.
    18  	REG_IMC = 0x00d8
    19  
    20  	/// Interrupt Cause Read.
    21  	REG_ICR = 0x00c0
    22  	/// Receiver Timer Interrupt.
    23  	ICR_RXT0 = (1 << 7)
    24  
    25  	/// Multicast Table Array.
    26  	REG_MTA_BASE = 0x5200
    27  	/// The lower bits of the Ethernet address.
    28  	REG_RECEIVE_ADDR_LOW = 0x5400
    29  	/// The higher bits of the Ethernet address and some extra bits.
    30  	REG_RECEIVE_ADDR_HIGH = 0x5404
    31  
    32  	/// Receive Control.
    33  	REG_RCTL = 0x0100
    34  	/// Receiver Enable.
    35  	RCTL_EN = (1 << 1)
    36  	/// Strip Ethernet CRC from receiving packet.
    37  	RCTL_SECRC = (1 << 26)
    38  	/// Receive Buffer Size: 2048 bytes (assuming RCTL.BSEX == 0).
    39  	RCTL_BSIZE = 0 << 16
    40  	/// Broadcast Accept Mode.
    41  	RCTL_BAM = (1 << 15)
    42  
    43  	/// Receive Descriptor Base Low.
    44  	REG_RDBAL = 0x2800
    45  	/// Receive Descriptor Base High.
    46  	REG_RDBAH = 0x2804
    47  	/// Length of Receive Descriptors.
    48  	REG_RDLEN = 0x2808
    49  	/// Receive Descriptor Head.
    50  	REG_RDH = 0x2810
    51  	/// Receive Descriptor Tail.
    52  	REG_RDT = 0x2818
    53  
    54  	/// Transmit Control.
    55  	REG_TCTL = 0x0400
    56  	// Transmit Inter Packet Gap
    57  	REG_TIPG = 0x0410
    58  	/// Receiver Enable.
    59  	TCTL_EN = (1 << 1)
    60  	/// Pad Short Packets.
    61  	TCTL_PSP = (1 << 3)
    62  
    63  	/// Transmit Descriptor Base Low.
    64  	REG_TDBAL = 0x3800
    65  	/// Transmit Descriptor Base High.
    66  	REG_TDBAH = 0x3804
    67  	/// Length of Transmit Descriptors.
    68  	REG_TDLEN = 0x3808
    69  	/// Transmit Descriptor Head.
    70  	REG_TDH = 0x3810
    71  	/// Transmit Descriptor Tail.
    72  	REG_TDT = 0x3818
    73  
    74  	/// Insert FCS.
    75  	TX_DESC_IFCS = (1 << 1)
    76  	/// End Of Packet.
    77  	TX_DESC_EOP = (1 << 0)
    78  	// Report Status
    79  	TX_DESC_RS = (1 << 3)
    80  
    81  	// eeprom register
    82  	REG_EEPROM = 0x0014
    83  	REG_RXADDR = 0x5400
    84  
    85  	/// Descriptor Done.
    86  	RX_DESC_DD = (1 << 0)
    87  	/// End Of Packet.
    88  	RX_DESC_EOP = (1 << 1)
    89  )
    90  
    91  const (
    92  	/// The size of buffer to store received/transmtting packets.
    93  	BUFFER_SIZE = 2048
    94  	/// Number of receive descriptors.
    95  	NUM_RX_DESCS = 32
    96  	/// Number of receive descriptors.
    97  	NUM_TX_DESCS = 32
    98  
    99  	TX_BUF_SZ = 1024
   100  )
   101  
   102  type rxdesc struct {
   103  	paddr    uint64
   104  	len      uint16
   105  	checksum uint16
   106  	status   uint8
   107  	errors   uint8
   108  	special  uint16
   109  }
   110  
   111  type txdesc struct {
   112  	paddr   uint64
   113  	len     uint16
   114  	cso     uint8
   115  	cmd     uint8
   116  	status  uint8
   117  	css     uint8
   118  	special uint16
   119  }