github.com/karrick/go@v0.0.0-20170817181416-d5b0ec858b37/src/cmd/compile/internal/ssa/opGen.go (about) 1 // Code generated from gen/*Ops.go; DO NOT EDIT. 2 3 package ssa 4 5 import ( 6 "cmd/internal/obj" 7 "cmd/internal/obj/arm" 8 "cmd/internal/obj/arm64" 9 "cmd/internal/obj/mips" 10 "cmd/internal/obj/ppc64" 11 "cmd/internal/obj/s390x" 12 "cmd/internal/obj/x86" 13 ) 14 15 const ( 16 BlockInvalid BlockKind = iota 17 18 Block386EQ 19 Block386NE 20 Block386LT 21 Block386LE 22 Block386GT 23 Block386GE 24 Block386ULT 25 Block386ULE 26 Block386UGT 27 Block386UGE 28 Block386EQF 29 Block386NEF 30 Block386ORD 31 Block386NAN 32 33 BlockAMD64EQ 34 BlockAMD64NE 35 BlockAMD64LT 36 BlockAMD64LE 37 BlockAMD64GT 38 BlockAMD64GE 39 BlockAMD64ULT 40 BlockAMD64ULE 41 BlockAMD64UGT 42 BlockAMD64UGE 43 BlockAMD64EQF 44 BlockAMD64NEF 45 BlockAMD64ORD 46 BlockAMD64NAN 47 48 BlockARMEQ 49 BlockARMNE 50 BlockARMLT 51 BlockARMLE 52 BlockARMGT 53 BlockARMGE 54 BlockARMULT 55 BlockARMULE 56 BlockARMUGT 57 BlockARMUGE 58 59 BlockARM64EQ 60 BlockARM64NE 61 BlockARM64LT 62 BlockARM64LE 63 BlockARM64GT 64 BlockARM64GE 65 BlockARM64ULT 66 BlockARM64ULE 67 BlockARM64UGT 68 BlockARM64UGE 69 BlockARM64Z 70 BlockARM64NZ 71 BlockARM64ZW 72 BlockARM64NZW 73 BlockARM64TBZ 74 BlockARM64TBNZ 75 76 BlockMIPSEQ 77 BlockMIPSNE 78 BlockMIPSLTZ 79 BlockMIPSLEZ 80 BlockMIPSGTZ 81 BlockMIPSGEZ 82 BlockMIPSFPT 83 BlockMIPSFPF 84 85 BlockMIPS64EQ 86 BlockMIPS64NE 87 BlockMIPS64LTZ 88 BlockMIPS64LEZ 89 BlockMIPS64GTZ 90 BlockMIPS64GEZ 91 BlockMIPS64FPT 92 BlockMIPS64FPF 93 94 BlockPPC64EQ 95 BlockPPC64NE 96 BlockPPC64LT 97 BlockPPC64LE 98 BlockPPC64GT 99 BlockPPC64GE 100 BlockPPC64FLT 101 BlockPPC64FLE 102 BlockPPC64FGT 103 BlockPPC64FGE 104 105 BlockS390XEQ 106 BlockS390XNE 107 BlockS390XLT 108 BlockS390XLE 109 BlockS390XGT 110 BlockS390XGE 111 BlockS390XGTF 112 BlockS390XGEF 113 114 BlockPlain 115 BlockIf 116 BlockDefer 117 BlockRet 118 BlockRetJmp 119 BlockExit 120 BlockFirst 121 ) 122 123 var blockString = [...]string{ 124 BlockInvalid: "BlockInvalid", 125 126 Block386EQ: "EQ", 127 Block386NE: "NE", 128 Block386LT: "LT", 129 Block386LE: "LE", 130 Block386GT: "GT", 131 Block386GE: "GE", 132 Block386ULT: "ULT", 133 Block386ULE: "ULE", 134 Block386UGT: "UGT", 135 Block386UGE: "UGE", 136 Block386EQF: "EQF", 137 Block386NEF: "NEF", 138 Block386ORD: "ORD", 139 Block386NAN: "NAN", 140 141 BlockAMD64EQ: "EQ", 142 BlockAMD64NE: "NE", 143 BlockAMD64LT: "LT", 144 BlockAMD64LE: "LE", 145 BlockAMD64GT: "GT", 146 BlockAMD64GE: "GE", 147 BlockAMD64ULT: "ULT", 148 BlockAMD64ULE: "ULE", 149 BlockAMD64UGT: "UGT", 150 BlockAMD64UGE: "UGE", 151 BlockAMD64EQF: "EQF", 152 BlockAMD64NEF: "NEF", 153 BlockAMD64ORD: "ORD", 154 BlockAMD64NAN: "NAN", 155 156 BlockARMEQ: "EQ", 157 BlockARMNE: "NE", 158 BlockARMLT: "LT", 159 BlockARMLE: "LE", 160 BlockARMGT: "GT", 161 BlockARMGE: "GE", 162 BlockARMULT: "ULT", 163 BlockARMULE: "ULE", 164 BlockARMUGT: "UGT", 165 BlockARMUGE: "UGE", 166 167 BlockARM64EQ: "EQ", 168 BlockARM64NE: "NE", 169 BlockARM64LT: "LT", 170 BlockARM64LE: "LE", 171 BlockARM64GT: "GT", 172 BlockARM64GE: "GE", 173 BlockARM64ULT: "ULT", 174 BlockARM64ULE: "ULE", 175 BlockARM64UGT: "UGT", 176 BlockARM64UGE: "UGE", 177 BlockARM64Z: "Z", 178 BlockARM64NZ: "NZ", 179 BlockARM64ZW: "ZW", 180 BlockARM64NZW: "NZW", 181 BlockARM64TBZ: "TBZ", 182 BlockARM64TBNZ: "TBNZ", 183 184 BlockMIPSEQ: "EQ", 185 BlockMIPSNE: "NE", 186 BlockMIPSLTZ: "LTZ", 187 BlockMIPSLEZ: "LEZ", 188 BlockMIPSGTZ: "GTZ", 189 BlockMIPSGEZ: "GEZ", 190 BlockMIPSFPT: "FPT", 191 BlockMIPSFPF: "FPF", 192 193 BlockMIPS64EQ: "EQ", 194 BlockMIPS64NE: "NE", 195 BlockMIPS64LTZ: "LTZ", 196 BlockMIPS64LEZ: "LEZ", 197 BlockMIPS64GTZ: "GTZ", 198 BlockMIPS64GEZ: "GEZ", 199 BlockMIPS64FPT: "FPT", 200 BlockMIPS64FPF: "FPF", 201 202 BlockPPC64EQ: "EQ", 203 BlockPPC64NE: "NE", 204 BlockPPC64LT: "LT", 205 BlockPPC64LE: "LE", 206 BlockPPC64GT: "GT", 207 BlockPPC64GE: "GE", 208 BlockPPC64FLT: "FLT", 209 BlockPPC64FLE: "FLE", 210 BlockPPC64FGT: "FGT", 211 BlockPPC64FGE: "FGE", 212 213 BlockS390XEQ: "EQ", 214 BlockS390XNE: "NE", 215 BlockS390XLT: "LT", 216 BlockS390XLE: "LE", 217 BlockS390XGT: "GT", 218 BlockS390XGE: "GE", 219 BlockS390XGTF: "GTF", 220 BlockS390XGEF: "GEF", 221 222 BlockPlain: "Plain", 223 BlockIf: "If", 224 BlockDefer: "Defer", 225 BlockRet: "Ret", 226 BlockRetJmp: "RetJmp", 227 BlockExit: "Exit", 228 BlockFirst: "First", 229 } 230 231 func (k BlockKind) String() string { return blockString[k] } 232 233 const ( 234 OpInvalid Op = iota 235 236 Op386ADDSS 237 Op386ADDSD 238 Op386SUBSS 239 Op386SUBSD 240 Op386MULSS 241 Op386MULSD 242 Op386DIVSS 243 Op386DIVSD 244 Op386MOVSSload 245 Op386MOVSDload 246 Op386MOVSSconst 247 Op386MOVSDconst 248 Op386MOVSSloadidx1 249 Op386MOVSSloadidx4 250 Op386MOVSDloadidx1 251 Op386MOVSDloadidx8 252 Op386MOVSSstore 253 Op386MOVSDstore 254 Op386MOVSSstoreidx1 255 Op386MOVSSstoreidx4 256 Op386MOVSDstoreidx1 257 Op386MOVSDstoreidx8 258 Op386ADDL 259 Op386ADDLconst 260 Op386ADDLcarry 261 Op386ADDLconstcarry 262 Op386ADCL 263 Op386ADCLconst 264 Op386SUBL 265 Op386SUBLconst 266 Op386SUBLcarry 267 Op386SUBLconstcarry 268 Op386SBBL 269 Op386SBBLconst 270 Op386MULL 271 Op386MULLconst 272 Op386HMULL 273 Op386HMULLU 274 Op386MULLQU 275 Op386AVGLU 276 Op386DIVL 277 Op386DIVW 278 Op386DIVLU 279 Op386DIVWU 280 Op386MODL 281 Op386MODW 282 Op386MODLU 283 Op386MODWU 284 Op386ANDL 285 Op386ANDLconst 286 Op386ORL 287 Op386ORLconst 288 Op386XORL 289 Op386XORLconst 290 Op386CMPL 291 Op386CMPW 292 Op386CMPB 293 Op386CMPLconst 294 Op386CMPWconst 295 Op386CMPBconst 296 Op386UCOMISS 297 Op386UCOMISD 298 Op386TESTL 299 Op386TESTW 300 Op386TESTB 301 Op386TESTLconst 302 Op386TESTWconst 303 Op386TESTBconst 304 Op386SHLL 305 Op386SHLLconst 306 Op386SHRL 307 Op386SHRW 308 Op386SHRB 309 Op386SHRLconst 310 Op386SHRWconst 311 Op386SHRBconst 312 Op386SARL 313 Op386SARW 314 Op386SARB 315 Op386SARLconst 316 Op386SARWconst 317 Op386SARBconst 318 Op386ROLLconst 319 Op386ROLWconst 320 Op386ROLBconst 321 Op386NEGL 322 Op386NOTL 323 Op386BSFL 324 Op386BSFW 325 Op386BSRL 326 Op386BSRW 327 Op386BSWAPL 328 Op386SQRTSD 329 Op386SBBLcarrymask 330 Op386SETEQ 331 Op386SETNE 332 Op386SETL 333 Op386SETLE 334 Op386SETG 335 Op386SETGE 336 Op386SETB 337 Op386SETBE 338 Op386SETA 339 Op386SETAE 340 Op386SETEQF 341 Op386SETNEF 342 Op386SETORD 343 Op386SETNAN 344 Op386SETGF 345 Op386SETGEF 346 Op386MOVBLSX 347 Op386MOVBLZX 348 Op386MOVWLSX 349 Op386MOVWLZX 350 Op386MOVLconst 351 Op386CVTTSD2SL 352 Op386CVTTSS2SL 353 Op386CVTSL2SS 354 Op386CVTSL2SD 355 Op386CVTSD2SS 356 Op386CVTSS2SD 357 Op386PXOR 358 Op386LEAL 359 Op386LEAL1 360 Op386LEAL2 361 Op386LEAL4 362 Op386LEAL8 363 Op386MOVBload 364 Op386MOVBLSXload 365 Op386MOVWload 366 Op386MOVWLSXload 367 Op386MOVLload 368 Op386MOVBstore 369 Op386MOVWstore 370 Op386MOVLstore 371 Op386MOVBloadidx1 372 Op386MOVWloadidx1 373 Op386MOVWloadidx2 374 Op386MOVLloadidx1 375 Op386MOVLloadidx4 376 Op386MOVBstoreidx1 377 Op386MOVWstoreidx1 378 Op386MOVWstoreidx2 379 Op386MOVLstoreidx1 380 Op386MOVLstoreidx4 381 Op386MOVBstoreconst 382 Op386MOVWstoreconst 383 Op386MOVLstoreconst 384 Op386MOVBstoreconstidx1 385 Op386MOVWstoreconstidx1 386 Op386MOVWstoreconstidx2 387 Op386MOVLstoreconstidx1 388 Op386MOVLstoreconstidx4 389 Op386DUFFZERO 390 Op386REPSTOSL 391 Op386CALLstatic 392 Op386CALLclosure 393 Op386CALLinter 394 Op386DUFFCOPY 395 Op386REPMOVSL 396 Op386InvertFlags 397 Op386LoweredGetG 398 Op386LoweredGetClosurePtr 399 Op386LoweredNilCheck 400 Op386MOVLconvert 401 Op386FlagEQ 402 Op386FlagLT_ULT 403 Op386FlagLT_UGT 404 Op386FlagGT_UGT 405 Op386FlagGT_ULT 406 Op386FCHS 407 Op386MOVSSconst1 408 Op386MOVSDconst1 409 Op386MOVSSconst2 410 Op386MOVSDconst2 411 412 OpAMD64ADDSS 413 OpAMD64ADDSD 414 OpAMD64SUBSS 415 OpAMD64SUBSD 416 OpAMD64MULSS 417 OpAMD64MULSD 418 OpAMD64DIVSS 419 OpAMD64DIVSD 420 OpAMD64MOVSSload 421 OpAMD64MOVSDload 422 OpAMD64MOVSSconst 423 OpAMD64MOVSDconst 424 OpAMD64MOVSSloadidx1 425 OpAMD64MOVSSloadidx4 426 OpAMD64MOVSDloadidx1 427 OpAMD64MOVSDloadidx8 428 OpAMD64MOVSSstore 429 OpAMD64MOVSDstore 430 OpAMD64MOVSSstoreidx1 431 OpAMD64MOVSSstoreidx4 432 OpAMD64MOVSDstoreidx1 433 OpAMD64MOVSDstoreidx8 434 OpAMD64ADDSSmem 435 OpAMD64ADDSDmem 436 OpAMD64SUBSSmem 437 OpAMD64SUBSDmem 438 OpAMD64MULSSmem 439 OpAMD64MULSDmem 440 OpAMD64ADDQ 441 OpAMD64ADDL 442 OpAMD64ADDQconst 443 OpAMD64ADDLconst 444 OpAMD64SUBQ 445 OpAMD64SUBL 446 OpAMD64SUBQconst 447 OpAMD64SUBLconst 448 OpAMD64MULQ 449 OpAMD64MULL 450 OpAMD64MULQconst 451 OpAMD64MULLconst 452 OpAMD64HMULQ 453 OpAMD64HMULL 454 OpAMD64HMULQU 455 OpAMD64HMULLU 456 OpAMD64AVGQU 457 OpAMD64DIVQ 458 OpAMD64DIVL 459 OpAMD64DIVW 460 OpAMD64DIVQU 461 OpAMD64DIVLU 462 OpAMD64DIVWU 463 OpAMD64MULQU2 464 OpAMD64DIVQU2 465 OpAMD64ANDQ 466 OpAMD64ANDL 467 OpAMD64ANDQconst 468 OpAMD64ANDLconst 469 OpAMD64ORQ 470 OpAMD64ORL 471 OpAMD64ORQconst 472 OpAMD64ORLconst 473 OpAMD64XORQ 474 OpAMD64XORL 475 OpAMD64XORQconst 476 OpAMD64XORLconst 477 OpAMD64CMPQ 478 OpAMD64CMPL 479 OpAMD64CMPW 480 OpAMD64CMPB 481 OpAMD64CMPQconst 482 OpAMD64CMPLconst 483 OpAMD64CMPWconst 484 OpAMD64CMPBconst 485 OpAMD64UCOMISS 486 OpAMD64UCOMISD 487 OpAMD64BTL 488 OpAMD64BTQ 489 OpAMD64BTLconst 490 OpAMD64BTQconst 491 OpAMD64TESTQ 492 OpAMD64TESTL 493 OpAMD64TESTW 494 OpAMD64TESTB 495 OpAMD64TESTQconst 496 OpAMD64TESTLconst 497 OpAMD64TESTWconst 498 OpAMD64TESTBconst 499 OpAMD64SHLQ 500 OpAMD64SHLL 501 OpAMD64SHLQconst 502 OpAMD64SHLLconst 503 OpAMD64SHRQ 504 OpAMD64SHRL 505 OpAMD64SHRW 506 OpAMD64SHRB 507 OpAMD64SHRQconst 508 OpAMD64SHRLconst 509 OpAMD64SHRWconst 510 OpAMD64SHRBconst 511 OpAMD64SARQ 512 OpAMD64SARL 513 OpAMD64SARW 514 OpAMD64SARB 515 OpAMD64SARQconst 516 OpAMD64SARLconst 517 OpAMD64SARWconst 518 OpAMD64SARBconst 519 OpAMD64ROLQ 520 OpAMD64ROLL 521 OpAMD64ROLW 522 OpAMD64ROLB 523 OpAMD64RORQ 524 OpAMD64RORL 525 OpAMD64RORW 526 OpAMD64RORB 527 OpAMD64ROLQconst 528 OpAMD64ROLLconst 529 OpAMD64ROLWconst 530 OpAMD64ROLBconst 531 OpAMD64ADDLmem 532 OpAMD64ADDQmem 533 OpAMD64SUBQmem 534 OpAMD64SUBLmem 535 OpAMD64ANDLmem 536 OpAMD64ANDQmem 537 OpAMD64ORQmem 538 OpAMD64ORLmem 539 OpAMD64XORQmem 540 OpAMD64XORLmem 541 OpAMD64NEGQ 542 OpAMD64NEGL 543 OpAMD64NOTQ 544 OpAMD64NOTL 545 OpAMD64BSFQ 546 OpAMD64BSFL 547 OpAMD64BSRQ 548 OpAMD64BSRL 549 OpAMD64CMOVQEQ 550 OpAMD64CMOVLEQ 551 OpAMD64BSWAPQ 552 OpAMD64BSWAPL 553 OpAMD64POPCNTQ 554 OpAMD64POPCNTL 555 OpAMD64SQRTSD 556 OpAMD64SBBQcarrymask 557 OpAMD64SBBLcarrymask 558 OpAMD64SETEQ 559 OpAMD64SETNE 560 OpAMD64SETL 561 OpAMD64SETLE 562 OpAMD64SETG 563 OpAMD64SETGE 564 OpAMD64SETB 565 OpAMD64SETBE 566 OpAMD64SETA 567 OpAMD64SETAE 568 OpAMD64SETEQF 569 OpAMD64SETNEF 570 OpAMD64SETORD 571 OpAMD64SETNAN 572 OpAMD64SETGF 573 OpAMD64SETGEF 574 OpAMD64MOVBQSX 575 OpAMD64MOVBQZX 576 OpAMD64MOVWQSX 577 OpAMD64MOVWQZX 578 OpAMD64MOVLQSX 579 OpAMD64MOVLQZX 580 OpAMD64MOVLconst 581 OpAMD64MOVQconst 582 OpAMD64CVTTSD2SL 583 OpAMD64CVTTSD2SQ 584 OpAMD64CVTTSS2SL 585 OpAMD64CVTTSS2SQ 586 OpAMD64CVTSL2SS 587 OpAMD64CVTSL2SD 588 OpAMD64CVTSQ2SS 589 OpAMD64CVTSQ2SD 590 OpAMD64CVTSD2SS 591 OpAMD64CVTSS2SD 592 OpAMD64PXOR 593 OpAMD64LEAQ 594 OpAMD64LEAQ1 595 OpAMD64LEAQ2 596 OpAMD64LEAQ4 597 OpAMD64LEAQ8 598 OpAMD64LEAL 599 OpAMD64MOVBload 600 OpAMD64MOVBQSXload 601 OpAMD64MOVWload 602 OpAMD64MOVWQSXload 603 OpAMD64MOVLload 604 OpAMD64MOVLQSXload 605 OpAMD64MOVQload 606 OpAMD64MOVBstore 607 OpAMD64MOVWstore 608 OpAMD64MOVLstore 609 OpAMD64MOVQstore 610 OpAMD64MOVOload 611 OpAMD64MOVOstore 612 OpAMD64MOVBloadidx1 613 OpAMD64MOVWloadidx1 614 OpAMD64MOVWloadidx2 615 OpAMD64MOVLloadidx1 616 OpAMD64MOVLloadidx4 617 OpAMD64MOVQloadidx1 618 OpAMD64MOVQloadidx8 619 OpAMD64MOVBstoreidx1 620 OpAMD64MOVWstoreidx1 621 OpAMD64MOVWstoreidx2 622 OpAMD64MOVLstoreidx1 623 OpAMD64MOVLstoreidx4 624 OpAMD64MOVQstoreidx1 625 OpAMD64MOVQstoreidx8 626 OpAMD64MOVBstoreconst 627 OpAMD64MOVWstoreconst 628 OpAMD64MOVLstoreconst 629 OpAMD64MOVQstoreconst 630 OpAMD64MOVBstoreconstidx1 631 OpAMD64MOVWstoreconstidx1 632 OpAMD64MOVWstoreconstidx2 633 OpAMD64MOVLstoreconstidx1 634 OpAMD64MOVLstoreconstidx4 635 OpAMD64MOVQstoreconstidx1 636 OpAMD64MOVQstoreconstidx8 637 OpAMD64DUFFZERO 638 OpAMD64MOVOconst 639 OpAMD64REPSTOSQ 640 OpAMD64CALLstatic 641 OpAMD64CALLclosure 642 OpAMD64CALLinter 643 OpAMD64DUFFCOPY 644 OpAMD64REPMOVSQ 645 OpAMD64InvertFlags 646 OpAMD64LoweredGetG 647 OpAMD64LoweredGetClosurePtr 648 OpAMD64LoweredNilCheck 649 OpAMD64MOVQconvert 650 OpAMD64MOVLconvert 651 OpAMD64FlagEQ 652 OpAMD64FlagLT_ULT 653 OpAMD64FlagLT_UGT 654 OpAMD64FlagGT_UGT 655 OpAMD64FlagGT_ULT 656 OpAMD64MOVLatomicload 657 OpAMD64MOVQatomicload 658 OpAMD64XCHGL 659 OpAMD64XCHGQ 660 OpAMD64XADDLlock 661 OpAMD64XADDQlock 662 OpAMD64AddTupleFirst32 663 OpAMD64AddTupleFirst64 664 OpAMD64CMPXCHGLlock 665 OpAMD64CMPXCHGQlock 666 OpAMD64ANDBlock 667 OpAMD64ORBlock 668 669 OpARMADD 670 OpARMADDconst 671 OpARMSUB 672 OpARMSUBconst 673 OpARMRSB 674 OpARMRSBconst 675 OpARMMUL 676 OpARMHMUL 677 OpARMHMULU 678 OpARMCALLudiv 679 OpARMADDS 680 OpARMADDSconst 681 OpARMADC 682 OpARMADCconst 683 OpARMSUBS 684 OpARMSUBSconst 685 OpARMRSBSconst 686 OpARMSBC 687 OpARMSBCconst 688 OpARMRSCconst 689 OpARMMULLU 690 OpARMMULA 691 OpARMADDF 692 OpARMADDD 693 OpARMSUBF 694 OpARMSUBD 695 OpARMMULF 696 OpARMMULD 697 OpARMDIVF 698 OpARMDIVD 699 OpARMAND 700 OpARMANDconst 701 OpARMOR 702 OpARMORconst 703 OpARMXOR 704 OpARMXORconst 705 OpARMBIC 706 OpARMBICconst 707 OpARMMVN 708 OpARMNEGF 709 OpARMNEGD 710 OpARMSQRTD 711 OpARMCLZ 712 OpARMREV 713 OpARMRBIT 714 OpARMSLL 715 OpARMSLLconst 716 OpARMSRL 717 OpARMSRLconst 718 OpARMSRA 719 OpARMSRAconst 720 OpARMSRRconst 721 OpARMADDshiftLL 722 OpARMADDshiftRL 723 OpARMADDshiftRA 724 OpARMSUBshiftLL 725 OpARMSUBshiftRL 726 OpARMSUBshiftRA 727 OpARMRSBshiftLL 728 OpARMRSBshiftRL 729 OpARMRSBshiftRA 730 OpARMANDshiftLL 731 OpARMANDshiftRL 732 OpARMANDshiftRA 733 OpARMORshiftLL 734 OpARMORshiftRL 735 OpARMORshiftRA 736 OpARMXORshiftLL 737 OpARMXORshiftRL 738 OpARMXORshiftRA 739 OpARMXORshiftRR 740 OpARMBICshiftLL 741 OpARMBICshiftRL 742 OpARMBICshiftRA 743 OpARMMVNshiftLL 744 OpARMMVNshiftRL 745 OpARMMVNshiftRA 746 OpARMADCshiftLL 747 OpARMADCshiftRL 748 OpARMADCshiftRA 749 OpARMSBCshiftLL 750 OpARMSBCshiftRL 751 OpARMSBCshiftRA 752 OpARMRSCshiftLL 753 OpARMRSCshiftRL 754 OpARMRSCshiftRA 755 OpARMADDSshiftLL 756 OpARMADDSshiftRL 757 OpARMADDSshiftRA 758 OpARMSUBSshiftLL 759 OpARMSUBSshiftRL 760 OpARMSUBSshiftRA 761 OpARMRSBSshiftLL 762 OpARMRSBSshiftRL 763 OpARMRSBSshiftRA 764 OpARMADDshiftLLreg 765 OpARMADDshiftRLreg 766 OpARMADDshiftRAreg 767 OpARMSUBshiftLLreg 768 OpARMSUBshiftRLreg 769 OpARMSUBshiftRAreg 770 OpARMRSBshiftLLreg 771 OpARMRSBshiftRLreg 772 OpARMRSBshiftRAreg 773 OpARMANDshiftLLreg 774 OpARMANDshiftRLreg 775 OpARMANDshiftRAreg 776 OpARMORshiftLLreg 777 OpARMORshiftRLreg 778 OpARMORshiftRAreg 779 OpARMXORshiftLLreg 780 OpARMXORshiftRLreg 781 OpARMXORshiftRAreg 782 OpARMBICshiftLLreg 783 OpARMBICshiftRLreg 784 OpARMBICshiftRAreg 785 OpARMMVNshiftLLreg 786 OpARMMVNshiftRLreg 787 OpARMMVNshiftRAreg 788 OpARMADCshiftLLreg 789 OpARMADCshiftRLreg 790 OpARMADCshiftRAreg 791 OpARMSBCshiftLLreg 792 OpARMSBCshiftRLreg 793 OpARMSBCshiftRAreg 794 OpARMRSCshiftLLreg 795 OpARMRSCshiftRLreg 796 OpARMRSCshiftRAreg 797 OpARMADDSshiftLLreg 798 OpARMADDSshiftRLreg 799 OpARMADDSshiftRAreg 800 OpARMSUBSshiftLLreg 801 OpARMSUBSshiftRLreg 802 OpARMSUBSshiftRAreg 803 OpARMRSBSshiftLLreg 804 OpARMRSBSshiftRLreg 805 OpARMRSBSshiftRAreg 806 OpARMCMP 807 OpARMCMPconst 808 OpARMCMN 809 OpARMCMNconst 810 OpARMTST 811 OpARMTSTconst 812 OpARMTEQ 813 OpARMTEQconst 814 OpARMCMPF 815 OpARMCMPD 816 OpARMCMPshiftLL 817 OpARMCMPshiftRL 818 OpARMCMPshiftRA 819 OpARMCMPshiftLLreg 820 OpARMCMPshiftRLreg 821 OpARMCMPshiftRAreg 822 OpARMCMPF0 823 OpARMCMPD0 824 OpARMMOVWconst 825 OpARMMOVFconst 826 OpARMMOVDconst 827 OpARMMOVWaddr 828 OpARMMOVBload 829 OpARMMOVBUload 830 OpARMMOVHload 831 OpARMMOVHUload 832 OpARMMOVWload 833 OpARMMOVFload 834 OpARMMOVDload 835 OpARMMOVBstore 836 OpARMMOVHstore 837 OpARMMOVWstore 838 OpARMMOVFstore 839 OpARMMOVDstore 840 OpARMMOVWloadidx 841 OpARMMOVWloadshiftLL 842 OpARMMOVWloadshiftRL 843 OpARMMOVWloadshiftRA 844 OpARMMOVWstoreidx 845 OpARMMOVWstoreshiftLL 846 OpARMMOVWstoreshiftRL 847 OpARMMOVWstoreshiftRA 848 OpARMMOVBreg 849 OpARMMOVBUreg 850 OpARMMOVHreg 851 OpARMMOVHUreg 852 OpARMMOVWreg 853 OpARMMOVWnop 854 OpARMMOVWF 855 OpARMMOVWD 856 OpARMMOVWUF 857 OpARMMOVWUD 858 OpARMMOVFW 859 OpARMMOVDW 860 OpARMMOVFWU 861 OpARMMOVDWU 862 OpARMMOVFD 863 OpARMMOVDF 864 OpARMCMOVWHSconst 865 OpARMCMOVWLSconst 866 OpARMSRAcond 867 OpARMCALLstatic 868 OpARMCALLclosure 869 OpARMCALLinter 870 OpARMLoweredNilCheck 871 OpARMEqual 872 OpARMNotEqual 873 OpARMLessThan 874 OpARMLessEqual 875 OpARMGreaterThan 876 OpARMGreaterEqual 877 OpARMLessThanU 878 OpARMLessEqualU 879 OpARMGreaterThanU 880 OpARMGreaterEqualU 881 OpARMDUFFZERO 882 OpARMDUFFCOPY 883 OpARMLoweredZero 884 OpARMLoweredMove 885 OpARMLoweredGetClosurePtr 886 OpARMMOVWconvert 887 OpARMFlagEQ 888 OpARMFlagLT_ULT 889 OpARMFlagLT_UGT 890 OpARMFlagGT_UGT 891 OpARMFlagGT_ULT 892 OpARMInvertFlags 893 894 OpARM64ADD 895 OpARM64ADDconst 896 OpARM64SUB 897 OpARM64SUBconst 898 OpARM64MUL 899 OpARM64MULW 900 OpARM64MULH 901 OpARM64UMULH 902 OpARM64MULL 903 OpARM64UMULL 904 OpARM64DIV 905 OpARM64UDIV 906 OpARM64DIVW 907 OpARM64UDIVW 908 OpARM64MOD 909 OpARM64UMOD 910 OpARM64MODW 911 OpARM64UMODW 912 OpARM64FADDS 913 OpARM64FADDD 914 OpARM64FSUBS 915 OpARM64FSUBD 916 OpARM64FMULS 917 OpARM64FMULD 918 OpARM64FDIVS 919 OpARM64FDIVD 920 OpARM64AND 921 OpARM64ANDconst 922 OpARM64OR 923 OpARM64ORconst 924 OpARM64XOR 925 OpARM64XORconst 926 OpARM64BIC 927 OpARM64BICconst 928 OpARM64MVN 929 OpARM64NEG 930 OpARM64FNEGS 931 OpARM64FNEGD 932 OpARM64FSQRTD 933 OpARM64REV 934 OpARM64REVW 935 OpARM64REV16W 936 OpARM64RBIT 937 OpARM64RBITW 938 OpARM64CLZ 939 OpARM64CLZW 940 OpARM64SLL 941 OpARM64SLLconst 942 OpARM64SRL 943 OpARM64SRLconst 944 OpARM64SRA 945 OpARM64SRAconst 946 OpARM64RORconst 947 OpARM64RORWconst 948 OpARM64CMP 949 OpARM64CMPconst 950 OpARM64CMPW 951 OpARM64CMPWconst 952 OpARM64CMN 953 OpARM64CMNconst 954 OpARM64CMNW 955 OpARM64CMNWconst 956 OpARM64FCMPS 957 OpARM64FCMPD 958 OpARM64ADDshiftLL 959 OpARM64ADDshiftRL 960 OpARM64ADDshiftRA 961 OpARM64SUBshiftLL 962 OpARM64SUBshiftRL 963 OpARM64SUBshiftRA 964 OpARM64ANDshiftLL 965 OpARM64ANDshiftRL 966 OpARM64ANDshiftRA 967 OpARM64ORshiftLL 968 OpARM64ORshiftRL 969 OpARM64ORshiftRA 970 OpARM64XORshiftLL 971 OpARM64XORshiftRL 972 OpARM64XORshiftRA 973 OpARM64BICshiftLL 974 OpARM64BICshiftRL 975 OpARM64BICshiftRA 976 OpARM64CMPshiftLL 977 OpARM64CMPshiftRL 978 OpARM64CMPshiftRA 979 OpARM64MOVDconst 980 OpARM64FMOVSconst 981 OpARM64FMOVDconst 982 OpARM64MOVDaddr 983 OpARM64MOVBload 984 OpARM64MOVBUload 985 OpARM64MOVHload 986 OpARM64MOVHUload 987 OpARM64MOVWload 988 OpARM64MOVWUload 989 OpARM64MOVDload 990 OpARM64FMOVSload 991 OpARM64FMOVDload 992 OpARM64MOVBstore 993 OpARM64MOVHstore 994 OpARM64MOVWstore 995 OpARM64MOVDstore 996 OpARM64FMOVSstore 997 OpARM64FMOVDstore 998 OpARM64MOVBstorezero 999 OpARM64MOVHstorezero 1000 OpARM64MOVWstorezero 1001 OpARM64MOVDstorezero 1002 OpARM64MOVBreg 1003 OpARM64MOVBUreg 1004 OpARM64MOVHreg 1005 OpARM64MOVHUreg 1006 OpARM64MOVWreg 1007 OpARM64MOVWUreg 1008 OpARM64MOVDreg 1009 OpARM64MOVDnop 1010 OpARM64SCVTFWS 1011 OpARM64SCVTFWD 1012 OpARM64UCVTFWS 1013 OpARM64UCVTFWD 1014 OpARM64SCVTFS 1015 OpARM64SCVTFD 1016 OpARM64UCVTFS 1017 OpARM64UCVTFD 1018 OpARM64FCVTZSSW 1019 OpARM64FCVTZSDW 1020 OpARM64FCVTZUSW 1021 OpARM64FCVTZUDW 1022 OpARM64FCVTZSS 1023 OpARM64FCVTZSD 1024 OpARM64FCVTZUS 1025 OpARM64FCVTZUD 1026 OpARM64FCVTSD 1027 OpARM64FCVTDS 1028 OpARM64CSELULT 1029 OpARM64CSELULT0 1030 OpARM64CALLstatic 1031 OpARM64CALLclosure 1032 OpARM64CALLinter 1033 OpARM64LoweredNilCheck 1034 OpARM64Equal 1035 OpARM64NotEqual 1036 OpARM64LessThan 1037 OpARM64LessEqual 1038 OpARM64GreaterThan 1039 OpARM64GreaterEqual 1040 OpARM64LessThanU 1041 OpARM64LessEqualU 1042 OpARM64GreaterThanU 1043 OpARM64GreaterEqualU 1044 OpARM64DUFFZERO 1045 OpARM64LoweredZero 1046 OpARM64DUFFCOPY 1047 OpARM64LoweredMove 1048 OpARM64LoweredGetClosurePtr 1049 OpARM64MOVDconvert 1050 OpARM64FlagEQ 1051 OpARM64FlagLT_ULT 1052 OpARM64FlagLT_UGT 1053 OpARM64FlagGT_UGT 1054 OpARM64FlagGT_ULT 1055 OpARM64InvertFlags 1056 OpARM64LDAR 1057 OpARM64LDARW 1058 OpARM64STLR 1059 OpARM64STLRW 1060 OpARM64LoweredAtomicExchange64 1061 OpARM64LoweredAtomicExchange32 1062 OpARM64LoweredAtomicAdd64 1063 OpARM64LoweredAtomicAdd32 1064 OpARM64LoweredAtomicCas64 1065 OpARM64LoweredAtomicCas32 1066 OpARM64LoweredAtomicAnd8 1067 OpARM64LoweredAtomicOr8 1068 1069 OpMIPSADD 1070 OpMIPSADDconst 1071 OpMIPSSUB 1072 OpMIPSSUBconst 1073 OpMIPSMUL 1074 OpMIPSMULT 1075 OpMIPSMULTU 1076 OpMIPSDIV 1077 OpMIPSDIVU 1078 OpMIPSADDF 1079 OpMIPSADDD 1080 OpMIPSSUBF 1081 OpMIPSSUBD 1082 OpMIPSMULF 1083 OpMIPSMULD 1084 OpMIPSDIVF 1085 OpMIPSDIVD 1086 OpMIPSAND 1087 OpMIPSANDconst 1088 OpMIPSOR 1089 OpMIPSORconst 1090 OpMIPSXOR 1091 OpMIPSXORconst 1092 OpMIPSNOR 1093 OpMIPSNORconst 1094 OpMIPSNEG 1095 OpMIPSNEGF 1096 OpMIPSNEGD 1097 OpMIPSSQRTD 1098 OpMIPSSLL 1099 OpMIPSSLLconst 1100 OpMIPSSRL 1101 OpMIPSSRLconst 1102 OpMIPSSRA 1103 OpMIPSSRAconst 1104 OpMIPSCLZ 1105 OpMIPSSGT 1106 OpMIPSSGTconst 1107 OpMIPSSGTzero 1108 OpMIPSSGTU 1109 OpMIPSSGTUconst 1110 OpMIPSSGTUzero 1111 OpMIPSCMPEQF 1112 OpMIPSCMPEQD 1113 OpMIPSCMPGEF 1114 OpMIPSCMPGED 1115 OpMIPSCMPGTF 1116 OpMIPSCMPGTD 1117 OpMIPSMOVWconst 1118 OpMIPSMOVFconst 1119 OpMIPSMOVDconst 1120 OpMIPSMOVWaddr 1121 OpMIPSMOVBload 1122 OpMIPSMOVBUload 1123 OpMIPSMOVHload 1124 OpMIPSMOVHUload 1125 OpMIPSMOVWload 1126 OpMIPSMOVFload 1127 OpMIPSMOVDload 1128 OpMIPSMOVBstore 1129 OpMIPSMOVHstore 1130 OpMIPSMOVWstore 1131 OpMIPSMOVFstore 1132 OpMIPSMOVDstore 1133 OpMIPSMOVBstorezero 1134 OpMIPSMOVHstorezero 1135 OpMIPSMOVWstorezero 1136 OpMIPSMOVBreg 1137 OpMIPSMOVBUreg 1138 OpMIPSMOVHreg 1139 OpMIPSMOVHUreg 1140 OpMIPSMOVWreg 1141 OpMIPSMOVWnop 1142 OpMIPSCMOVZ 1143 OpMIPSCMOVZzero 1144 OpMIPSMOVWF 1145 OpMIPSMOVWD 1146 OpMIPSTRUNCFW 1147 OpMIPSTRUNCDW 1148 OpMIPSMOVFD 1149 OpMIPSMOVDF 1150 OpMIPSCALLstatic 1151 OpMIPSCALLclosure 1152 OpMIPSCALLinter 1153 OpMIPSLoweredAtomicLoad 1154 OpMIPSLoweredAtomicStore 1155 OpMIPSLoweredAtomicStorezero 1156 OpMIPSLoweredAtomicExchange 1157 OpMIPSLoweredAtomicAdd 1158 OpMIPSLoweredAtomicAddconst 1159 OpMIPSLoweredAtomicCas 1160 OpMIPSLoweredAtomicAnd 1161 OpMIPSLoweredAtomicOr 1162 OpMIPSLoweredZero 1163 OpMIPSLoweredMove 1164 OpMIPSLoweredNilCheck 1165 OpMIPSFPFlagTrue 1166 OpMIPSFPFlagFalse 1167 OpMIPSLoweredGetClosurePtr 1168 OpMIPSMOVWconvert 1169 1170 OpMIPS64ADDV 1171 OpMIPS64ADDVconst 1172 OpMIPS64SUBV 1173 OpMIPS64SUBVconst 1174 OpMIPS64MULV 1175 OpMIPS64MULVU 1176 OpMIPS64DIVV 1177 OpMIPS64DIVVU 1178 OpMIPS64ADDF 1179 OpMIPS64ADDD 1180 OpMIPS64SUBF 1181 OpMIPS64SUBD 1182 OpMIPS64MULF 1183 OpMIPS64MULD 1184 OpMIPS64DIVF 1185 OpMIPS64DIVD 1186 OpMIPS64AND 1187 OpMIPS64ANDconst 1188 OpMIPS64OR 1189 OpMIPS64ORconst 1190 OpMIPS64XOR 1191 OpMIPS64XORconst 1192 OpMIPS64NOR 1193 OpMIPS64NORconst 1194 OpMIPS64NEGV 1195 OpMIPS64NEGF 1196 OpMIPS64NEGD 1197 OpMIPS64SLLV 1198 OpMIPS64SLLVconst 1199 OpMIPS64SRLV 1200 OpMIPS64SRLVconst 1201 OpMIPS64SRAV 1202 OpMIPS64SRAVconst 1203 OpMIPS64SGT 1204 OpMIPS64SGTconst 1205 OpMIPS64SGTU 1206 OpMIPS64SGTUconst 1207 OpMIPS64CMPEQF 1208 OpMIPS64CMPEQD 1209 OpMIPS64CMPGEF 1210 OpMIPS64CMPGED 1211 OpMIPS64CMPGTF 1212 OpMIPS64CMPGTD 1213 OpMIPS64MOVVconst 1214 OpMIPS64MOVFconst 1215 OpMIPS64MOVDconst 1216 OpMIPS64MOVVaddr 1217 OpMIPS64MOVBload 1218 OpMIPS64MOVBUload 1219 OpMIPS64MOVHload 1220 OpMIPS64MOVHUload 1221 OpMIPS64MOVWload 1222 OpMIPS64MOVWUload 1223 OpMIPS64MOVVload 1224 OpMIPS64MOVFload 1225 OpMIPS64MOVDload 1226 OpMIPS64MOVBstore 1227 OpMIPS64MOVHstore 1228 OpMIPS64MOVWstore 1229 OpMIPS64MOVVstore 1230 OpMIPS64MOVFstore 1231 OpMIPS64MOVDstore 1232 OpMIPS64MOVBstorezero 1233 OpMIPS64MOVHstorezero 1234 OpMIPS64MOVWstorezero 1235 OpMIPS64MOVVstorezero 1236 OpMIPS64MOVBreg 1237 OpMIPS64MOVBUreg 1238 OpMIPS64MOVHreg 1239 OpMIPS64MOVHUreg 1240 OpMIPS64MOVWreg 1241 OpMIPS64MOVWUreg 1242 OpMIPS64MOVVreg 1243 OpMIPS64MOVVnop 1244 OpMIPS64MOVWF 1245 OpMIPS64MOVWD 1246 OpMIPS64MOVVF 1247 OpMIPS64MOVVD 1248 OpMIPS64TRUNCFW 1249 OpMIPS64TRUNCDW 1250 OpMIPS64TRUNCFV 1251 OpMIPS64TRUNCDV 1252 OpMIPS64MOVFD 1253 OpMIPS64MOVDF 1254 OpMIPS64CALLstatic 1255 OpMIPS64CALLclosure 1256 OpMIPS64CALLinter 1257 OpMIPS64DUFFZERO 1258 OpMIPS64LoweredZero 1259 OpMIPS64LoweredMove 1260 OpMIPS64LoweredNilCheck 1261 OpMIPS64FPFlagTrue 1262 OpMIPS64FPFlagFalse 1263 OpMIPS64LoweredGetClosurePtr 1264 OpMIPS64MOVVconvert 1265 1266 OpPPC64ADD 1267 OpPPC64ADDconst 1268 OpPPC64FADD 1269 OpPPC64FADDS 1270 OpPPC64SUB 1271 OpPPC64FSUB 1272 OpPPC64FSUBS 1273 OpPPC64MULLD 1274 OpPPC64MULLW 1275 OpPPC64MULHD 1276 OpPPC64MULHW 1277 OpPPC64MULHDU 1278 OpPPC64MULHWU 1279 OpPPC64FMUL 1280 OpPPC64FMULS 1281 OpPPC64FMADD 1282 OpPPC64FMADDS 1283 OpPPC64FMSUB 1284 OpPPC64FMSUBS 1285 OpPPC64SRAD 1286 OpPPC64SRAW 1287 OpPPC64SRD 1288 OpPPC64SRW 1289 OpPPC64SLD 1290 OpPPC64SLW 1291 OpPPC64ADDconstForCarry 1292 OpPPC64MaskIfNotCarry 1293 OpPPC64SRADconst 1294 OpPPC64SRAWconst 1295 OpPPC64SRDconst 1296 OpPPC64SRWconst 1297 OpPPC64SLDconst 1298 OpPPC64SLWconst 1299 OpPPC64ROTLconst 1300 OpPPC64ROTLWconst 1301 OpPPC64CNTLZD 1302 OpPPC64CNTLZW 1303 OpPPC64POPCNTD 1304 OpPPC64POPCNTW 1305 OpPPC64POPCNTB 1306 OpPPC64FDIV 1307 OpPPC64FDIVS 1308 OpPPC64DIVD 1309 OpPPC64DIVW 1310 OpPPC64DIVDU 1311 OpPPC64DIVWU 1312 OpPPC64FCTIDZ 1313 OpPPC64FCTIWZ 1314 OpPPC64FCFID 1315 OpPPC64FRSP 1316 OpPPC64Xf2i64 1317 OpPPC64Xi2f64 1318 OpPPC64AND 1319 OpPPC64ANDN 1320 OpPPC64OR 1321 OpPPC64ORN 1322 OpPPC64NOR 1323 OpPPC64XOR 1324 OpPPC64EQV 1325 OpPPC64NEG 1326 OpPPC64FNEG 1327 OpPPC64FSQRT 1328 OpPPC64FSQRTS 1329 OpPPC64FFLOOR 1330 OpPPC64FCEIL 1331 OpPPC64FTRUNC 1332 OpPPC64ORconst 1333 OpPPC64XORconst 1334 OpPPC64ANDconst 1335 OpPPC64ANDCCconst 1336 OpPPC64MOVBreg 1337 OpPPC64MOVBZreg 1338 OpPPC64MOVHreg 1339 OpPPC64MOVHZreg 1340 OpPPC64MOVWreg 1341 OpPPC64MOVWZreg 1342 OpPPC64MOVBZload 1343 OpPPC64MOVHload 1344 OpPPC64MOVHZload 1345 OpPPC64MOVWload 1346 OpPPC64MOVWZload 1347 OpPPC64MOVDload 1348 OpPPC64FMOVDload 1349 OpPPC64FMOVSload 1350 OpPPC64MOVBstore 1351 OpPPC64MOVHstore 1352 OpPPC64MOVWstore 1353 OpPPC64MOVDstore 1354 OpPPC64FMOVDstore 1355 OpPPC64FMOVSstore 1356 OpPPC64MOVBstorezero 1357 OpPPC64MOVHstorezero 1358 OpPPC64MOVWstorezero 1359 OpPPC64MOVDstorezero 1360 OpPPC64MOVDaddr 1361 OpPPC64MOVDconst 1362 OpPPC64FMOVDconst 1363 OpPPC64FMOVSconst 1364 OpPPC64FCMPU 1365 OpPPC64CMP 1366 OpPPC64CMPU 1367 OpPPC64CMPW 1368 OpPPC64CMPWU 1369 OpPPC64CMPconst 1370 OpPPC64CMPUconst 1371 OpPPC64CMPWconst 1372 OpPPC64CMPWUconst 1373 OpPPC64Equal 1374 OpPPC64NotEqual 1375 OpPPC64LessThan 1376 OpPPC64FLessThan 1377 OpPPC64LessEqual 1378 OpPPC64FLessEqual 1379 OpPPC64GreaterThan 1380 OpPPC64FGreaterThan 1381 OpPPC64GreaterEqual 1382 OpPPC64FGreaterEqual 1383 OpPPC64LoweredGetClosurePtr 1384 OpPPC64LoweredNilCheck 1385 OpPPC64LoweredRound32F 1386 OpPPC64LoweredRound64F 1387 OpPPC64MOVDconvert 1388 OpPPC64CALLstatic 1389 OpPPC64CALLclosure 1390 OpPPC64CALLinter 1391 OpPPC64LoweredZero 1392 OpPPC64LoweredMove 1393 OpPPC64LoweredAtomicStore32 1394 OpPPC64LoweredAtomicStore64 1395 OpPPC64LoweredAtomicLoad32 1396 OpPPC64LoweredAtomicLoad64 1397 OpPPC64LoweredAtomicLoadPtr 1398 OpPPC64LoweredAtomicAdd32 1399 OpPPC64LoweredAtomicAdd64 1400 OpPPC64LoweredAtomicExchange32 1401 OpPPC64LoweredAtomicExchange64 1402 OpPPC64LoweredAtomicCas64 1403 OpPPC64LoweredAtomicCas32 1404 OpPPC64LoweredAtomicAnd8 1405 OpPPC64LoweredAtomicOr8 1406 OpPPC64InvertFlags 1407 OpPPC64FlagEQ 1408 OpPPC64FlagLT 1409 OpPPC64FlagGT 1410 1411 OpS390XFADDS 1412 OpS390XFADD 1413 OpS390XFSUBS 1414 OpS390XFSUB 1415 OpS390XFMULS 1416 OpS390XFMUL 1417 OpS390XFDIVS 1418 OpS390XFDIV 1419 OpS390XFNEGS 1420 OpS390XFNEG 1421 OpS390XFMADDS 1422 OpS390XFMADD 1423 OpS390XFMSUBS 1424 OpS390XFMSUB 1425 OpS390XFMOVSload 1426 OpS390XFMOVDload 1427 OpS390XFMOVSconst 1428 OpS390XFMOVDconst 1429 OpS390XFMOVSloadidx 1430 OpS390XFMOVDloadidx 1431 OpS390XFMOVSstore 1432 OpS390XFMOVDstore 1433 OpS390XFMOVSstoreidx 1434 OpS390XFMOVDstoreidx 1435 OpS390XADD 1436 OpS390XADDW 1437 OpS390XADDconst 1438 OpS390XADDWconst 1439 OpS390XADDload 1440 OpS390XADDWload 1441 OpS390XSUB 1442 OpS390XSUBW 1443 OpS390XSUBconst 1444 OpS390XSUBWconst 1445 OpS390XSUBload 1446 OpS390XSUBWload 1447 OpS390XMULLD 1448 OpS390XMULLW 1449 OpS390XMULLDconst 1450 OpS390XMULLWconst 1451 OpS390XMULLDload 1452 OpS390XMULLWload 1453 OpS390XMULHD 1454 OpS390XMULHDU 1455 OpS390XDIVD 1456 OpS390XDIVW 1457 OpS390XDIVDU 1458 OpS390XDIVWU 1459 OpS390XMODD 1460 OpS390XMODW 1461 OpS390XMODDU 1462 OpS390XMODWU 1463 OpS390XAND 1464 OpS390XANDW 1465 OpS390XANDconst 1466 OpS390XANDWconst 1467 OpS390XANDload 1468 OpS390XANDWload 1469 OpS390XOR 1470 OpS390XORW 1471 OpS390XORconst 1472 OpS390XORWconst 1473 OpS390XORload 1474 OpS390XORWload 1475 OpS390XXOR 1476 OpS390XXORW 1477 OpS390XXORconst 1478 OpS390XXORWconst 1479 OpS390XXORload 1480 OpS390XXORWload 1481 OpS390XCMP 1482 OpS390XCMPW 1483 OpS390XCMPU 1484 OpS390XCMPWU 1485 OpS390XCMPconst 1486 OpS390XCMPWconst 1487 OpS390XCMPUconst 1488 OpS390XCMPWUconst 1489 OpS390XFCMPS 1490 OpS390XFCMP 1491 OpS390XSLD 1492 OpS390XSLW 1493 OpS390XSLDconst 1494 OpS390XSLWconst 1495 OpS390XSRD 1496 OpS390XSRW 1497 OpS390XSRDconst 1498 OpS390XSRWconst 1499 OpS390XSRAD 1500 OpS390XSRAW 1501 OpS390XSRADconst 1502 OpS390XSRAWconst 1503 OpS390XRLLGconst 1504 OpS390XRLLconst 1505 OpS390XNEG 1506 OpS390XNEGW 1507 OpS390XNOT 1508 OpS390XNOTW 1509 OpS390XFSQRT 1510 OpS390XSUBEcarrymask 1511 OpS390XSUBEWcarrymask 1512 OpS390XMOVDEQ 1513 OpS390XMOVDNE 1514 OpS390XMOVDLT 1515 OpS390XMOVDLE 1516 OpS390XMOVDGT 1517 OpS390XMOVDGE 1518 OpS390XMOVDGTnoinv 1519 OpS390XMOVDGEnoinv 1520 OpS390XMOVBreg 1521 OpS390XMOVBZreg 1522 OpS390XMOVHreg 1523 OpS390XMOVHZreg 1524 OpS390XMOVWreg 1525 OpS390XMOVWZreg 1526 OpS390XMOVDreg 1527 OpS390XMOVDnop 1528 OpS390XMOVDconst 1529 OpS390XCFDBRA 1530 OpS390XCGDBRA 1531 OpS390XCFEBRA 1532 OpS390XCGEBRA 1533 OpS390XCEFBRA 1534 OpS390XCDFBRA 1535 OpS390XCEGBRA 1536 OpS390XCDGBRA 1537 OpS390XLEDBR 1538 OpS390XLDEBR 1539 OpS390XMOVDaddr 1540 OpS390XMOVDaddridx 1541 OpS390XMOVBZload 1542 OpS390XMOVBload 1543 OpS390XMOVHZload 1544 OpS390XMOVHload 1545 OpS390XMOVWZload 1546 OpS390XMOVWload 1547 OpS390XMOVDload 1548 OpS390XMOVWBR 1549 OpS390XMOVDBR 1550 OpS390XMOVHBRload 1551 OpS390XMOVWBRload 1552 OpS390XMOVDBRload 1553 OpS390XMOVBstore 1554 OpS390XMOVHstore 1555 OpS390XMOVWstore 1556 OpS390XMOVDstore 1557 OpS390XMOVHBRstore 1558 OpS390XMOVWBRstore 1559 OpS390XMOVDBRstore 1560 OpS390XMVC 1561 OpS390XMOVBZloadidx 1562 OpS390XMOVHZloadidx 1563 OpS390XMOVWZloadidx 1564 OpS390XMOVDloadidx 1565 OpS390XMOVHBRloadidx 1566 OpS390XMOVWBRloadidx 1567 OpS390XMOVDBRloadidx 1568 OpS390XMOVBstoreidx 1569 OpS390XMOVHstoreidx 1570 OpS390XMOVWstoreidx 1571 OpS390XMOVDstoreidx 1572 OpS390XMOVHBRstoreidx 1573 OpS390XMOVWBRstoreidx 1574 OpS390XMOVDBRstoreidx 1575 OpS390XMOVBstoreconst 1576 OpS390XMOVHstoreconst 1577 OpS390XMOVWstoreconst 1578 OpS390XMOVDstoreconst 1579 OpS390XCLEAR 1580 OpS390XCALLstatic 1581 OpS390XCALLclosure 1582 OpS390XCALLinter 1583 OpS390XInvertFlags 1584 OpS390XLoweredGetG 1585 OpS390XLoweredGetClosurePtr 1586 OpS390XLoweredNilCheck 1587 OpS390XLoweredRound32F 1588 OpS390XLoweredRound64F 1589 OpS390XMOVDconvert 1590 OpS390XFlagEQ 1591 OpS390XFlagLT 1592 OpS390XFlagGT 1593 OpS390XMOVWZatomicload 1594 OpS390XMOVDatomicload 1595 OpS390XMOVWatomicstore 1596 OpS390XMOVDatomicstore 1597 OpS390XLAA 1598 OpS390XLAAG 1599 OpS390XAddTupleFirst32 1600 OpS390XAddTupleFirst64 1601 OpS390XLoweredAtomicCas32 1602 OpS390XLoweredAtomicCas64 1603 OpS390XLoweredAtomicExchange32 1604 OpS390XLoweredAtomicExchange64 1605 OpS390XFLOGR 1606 OpS390XSTMG2 1607 OpS390XSTMG3 1608 OpS390XSTMG4 1609 OpS390XSTM2 1610 OpS390XSTM3 1611 OpS390XSTM4 1612 OpS390XLoweredMove 1613 OpS390XLoweredZero 1614 1615 OpAdd8 1616 OpAdd16 1617 OpAdd32 1618 OpAdd64 1619 OpAddPtr 1620 OpAdd32F 1621 OpAdd64F 1622 OpSub8 1623 OpSub16 1624 OpSub32 1625 OpSub64 1626 OpSubPtr 1627 OpSub32F 1628 OpSub64F 1629 OpMul8 1630 OpMul16 1631 OpMul32 1632 OpMul64 1633 OpMul32F 1634 OpMul64F 1635 OpDiv32F 1636 OpDiv64F 1637 OpHmul32 1638 OpHmul32u 1639 OpHmul64 1640 OpHmul64u 1641 OpMul32uhilo 1642 OpMul64uhilo 1643 OpAvg32u 1644 OpAvg64u 1645 OpDiv8 1646 OpDiv8u 1647 OpDiv16 1648 OpDiv16u 1649 OpDiv32 1650 OpDiv32u 1651 OpDiv64 1652 OpDiv64u 1653 OpDiv128u 1654 OpMod8 1655 OpMod8u 1656 OpMod16 1657 OpMod16u 1658 OpMod32 1659 OpMod32u 1660 OpMod64 1661 OpMod64u 1662 OpAnd8 1663 OpAnd16 1664 OpAnd32 1665 OpAnd64 1666 OpOr8 1667 OpOr16 1668 OpOr32 1669 OpOr64 1670 OpXor8 1671 OpXor16 1672 OpXor32 1673 OpXor64 1674 OpLsh8x8 1675 OpLsh8x16 1676 OpLsh8x32 1677 OpLsh8x64 1678 OpLsh16x8 1679 OpLsh16x16 1680 OpLsh16x32 1681 OpLsh16x64 1682 OpLsh32x8 1683 OpLsh32x16 1684 OpLsh32x32 1685 OpLsh32x64 1686 OpLsh64x8 1687 OpLsh64x16 1688 OpLsh64x32 1689 OpLsh64x64 1690 OpRsh8x8 1691 OpRsh8x16 1692 OpRsh8x32 1693 OpRsh8x64 1694 OpRsh16x8 1695 OpRsh16x16 1696 OpRsh16x32 1697 OpRsh16x64 1698 OpRsh32x8 1699 OpRsh32x16 1700 OpRsh32x32 1701 OpRsh32x64 1702 OpRsh64x8 1703 OpRsh64x16 1704 OpRsh64x32 1705 OpRsh64x64 1706 OpRsh8Ux8 1707 OpRsh8Ux16 1708 OpRsh8Ux32 1709 OpRsh8Ux64 1710 OpRsh16Ux8 1711 OpRsh16Ux16 1712 OpRsh16Ux32 1713 OpRsh16Ux64 1714 OpRsh32Ux8 1715 OpRsh32Ux16 1716 OpRsh32Ux32 1717 OpRsh32Ux64 1718 OpRsh64Ux8 1719 OpRsh64Ux16 1720 OpRsh64Ux32 1721 OpRsh64Ux64 1722 OpEq8 1723 OpEq16 1724 OpEq32 1725 OpEq64 1726 OpEqPtr 1727 OpEqInter 1728 OpEqSlice 1729 OpEq32F 1730 OpEq64F 1731 OpNeq8 1732 OpNeq16 1733 OpNeq32 1734 OpNeq64 1735 OpNeqPtr 1736 OpNeqInter 1737 OpNeqSlice 1738 OpNeq32F 1739 OpNeq64F 1740 OpLess8 1741 OpLess8U 1742 OpLess16 1743 OpLess16U 1744 OpLess32 1745 OpLess32U 1746 OpLess64 1747 OpLess64U 1748 OpLess32F 1749 OpLess64F 1750 OpLeq8 1751 OpLeq8U 1752 OpLeq16 1753 OpLeq16U 1754 OpLeq32 1755 OpLeq32U 1756 OpLeq64 1757 OpLeq64U 1758 OpLeq32F 1759 OpLeq64F 1760 OpGreater8 1761 OpGreater8U 1762 OpGreater16 1763 OpGreater16U 1764 OpGreater32 1765 OpGreater32U 1766 OpGreater64 1767 OpGreater64U 1768 OpGreater32F 1769 OpGreater64F 1770 OpGeq8 1771 OpGeq8U 1772 OpGeq16 1773 OpGeq16U 1774 OpGeq32 1775 OpGeq32U 1776 OpGeq64 1777 OpGeq64U 1778 OpGeq32F 1779 OpGeq64F 1780 OpAndB 1781 OpOrB 1782 OpEqB 1783 OpNeqB 1784 OpNot 1785 OpNeg8 1786 OpNeg16 1787 OpNeg32 1788 OpNeg64 1789 OpNeg32F 1790 OpNeg64F 1791 OpCom8 1792 OpCom16 1793 OpCom32 1794 OpCom64 1795 OpCtz32 1796 OpCtz64 1797 OpBitLen32 1798 OpBitLen64 1799 OpBswap32 1800 OpBswap64 1801 OpBitRev8 1802 OpBitRev16 1803 OpBitRev32 1804 OpBitRev64 1805 OpPopCount8 1806 OpPopCount16 1807 OpPopCount32 1808 OpPopCount64 1809 OpSqrt 1810 OpFloor 1811 OpCeil 1812 OpTrunc 1813 OpPhi 1814 OpCopy 1815 OpConvert 1816 OpConstBool 1817 OpConstString 1818 OpConstNil 1819 OpConst8 1820 OpConst16 1821 OpConst32 1822 OpConst64 1823 OpConst32F 1824 OpConst64F 1825 OpConstInterface 1826 OpConstSlice 1827 OpInitMem 1828 OpArg 1829 OpAddr 1830 OpSP 1831 OpSB 1832 OpLoad 1833 OpStore 1834 OpMove 1835 OpZero 1836 OpStoreWB 1837 OpMoveWB 1838 OpZeroWB 1839 OpClosureCall 1840 OpStaticCall 1841 OpInterCall 1842 OpSignExt8to16 1843 OpSignExt8to32 1844 OpSignExt8to64 1845 OpSignExt16to32 1846 OpSignExt16to64 1847 OpSignExt32to64 1848 OpZeroExt8to16 1849 OpZeroExt8to32 1850 OpZeroExt8to64 1851 OpZeroExt16to32 1852 OpZeroExt16to64 1853 OpZeroExt32to64 1854 OpTrunc16to8 1855 OpTrunc32to8 1856 OpTrunc32to16 1857 OpTrunc64to8 1858 OpTrunc64to16 1859 OpTrunc64to32 1860 OpCvt32to32F 1861 OpCvt32to64F 1862 OpCvt64to32F 1863 OpCvt64to64F 1864 OpCvt32Fto32 1865 OpCvt32Fto64 1866 OpCvt64Fto32 1867 OpCvt64Fto64 1868 OpCvt32Fto64F 1869 OpCvt64Fto32F 1870 OpRound32F 1871 OpRound64F 1872 OpIsNonNil 1873 OpIsInBounds 1874 OpIsSliceInBounds 1875 OpNilCheck 1876 OpGetG 1877 OpGetClosurePtr 1878 OpPtrIndex 1879 OpOffPtr 1880 OpSliceMake 1881 OpSlicePtr 1882 OpSliceLen 1883 OpSliceCap 1884 OpComplexMake 1885 OpComplexReal 1886 OpComplexImag 1887 OpStringMake 1888 OpStringPtr 1889 OpStringLen 1890 OpIMake 1891 OpITab 1892 OpIData 1893 OpStructMake0 1894 OpStructMake1 1895 OpStructMake2 1896 OpStructMake3 1897 OpStructMake4 1898 OpStructSelect 1899 OpArrayMake0 1900 OpArrayMake1 1901 OpArraySelect 1902 OpStoreReg 1903 OpLoadReg 1904 OpFwdRef 1905 OpUnknown 1906 OpVarDef 1907 OpVarKill 1908 OpVarLive 1909 OpKeepAlive 1910 OpRegKill 1911 OpInt64Make 1912 OpInt64Hi 1913 OpInt64Lo 1914 OpAdd32carry 1915 OpAdd32withcarry 1916 OpSub32carry 1917 OpSub32withcarry 1918 OpSignmask 1919 OpZeromask 1920 OpSlicemask 1921 OpCvt32Uto32F 1922 OpCvt32Uto64F 1923 OpCvt32Fto32U 1924 OpCvt64Fto32U 1925 OpCvt64Uto32F 1926 OpCvt64Uto64F 1927 OpCvt32Fto64U 1928 OpCvt64Fto64U 1929 OpSelect0 1930 OpSelect1 1931 OpAtomicLoad32 1932 OpAtomicLoad64 1933 OpAtomicLoadPtr 1934 OpAtomicStore32 1935 OpAtomicStore64 1936 OpAtomicStorePtrNoWB 1937 OpAtomicExchange32 1938 OpAtomicExchange64 1939 OpAtomicAdd32 1940 OpAtomicAdd64 1941 OpAtomicCompareAndSwap32 1942 OpAtomicCompareAndSwap64 1943 OpAtomicAnd8 1944 OpAtomicOr8 1945 OpClobber 1946 ) 1947 1948 var opcodeTable = [...]opInfo{ 1949 {name: "OpInvalid"}, 1950 1951 { 1952 name: "ADDSS", 1953 argLen: 2, 1954 commutative: true, 1955 resultInArg0: true, 1956 usesScratch: true, 1957 asm: x86.AADDSS, 1958 reg: regInfo{ 1959 inputs: []inputInfo{ 1960 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1961 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1962 }, 1963 outputs: []outputInfo{ 1964 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1965 }, 1966 }, 1967 }, 1968 { 1969 name: "ADDSD", 1970 argLen: 2, 1971 commutative: true, 1972 resultInArg0: true, 1973 asm: x86.AADDSD, 1974 reg: regInfo{ 1975 inputs: []inputInfo{ 1976 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1977 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1978 }, 1979 outputs: []outputInfo{ 1980 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1981 }, 1982 }, 1983 }, 1984 { 1985 name: "SUBSS", 1986 argLen: 2, 1987 resultInArg0: true, 1988 usesScratch: true, 1989 asm: x86.ASUBSS, 1990 reg: regInfo{ 1991 inputs: []inputInfo{ 1992 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1993 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1994 }, 1995 outputs: []outputInfo{ 1996 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1997 }, 1998 }, 1999 }, 2000 { 2001 name: "SUBSD", 2002 argLen: 2, 2003 resultInArg0: true, 2004 asm: x86.ASUBSD, 2005 reg: regInfo{ 2006 inputs: []inputInfo{ 2007 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2008 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2009 }, 2010 outputs: []outputInfo{ 2011 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2012 }, 2013 }, 2014 }, 2015 { 2016 name: "MULSS", 2017 argLen: 2, 2018 commutative: true, 2019 resultInArg0: true, 2020 usesScratch: true, 2021 asm: x86.AMULSS, 2022 reg: regInfo{ 2023 inputs: []inputInfo{ 2024 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2025 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2026 }, 2027 outputs: []outputInfo{ 2028 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2029 }, 2030 }, 2031 }, 2032 { 2033 name: "MULSD", 2034 argLen: 2, 2035 commutative: true, 2036 resultInArg0: true, 2037 asm: x86.AMULSD, 2038 reg: regInfo{ 2039 inputs: []inputInfo{ 2040 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2041 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2042 }, 2043 outputs: []outputInfo{ 2044 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2045 }, 2046 }, 2047 }, 2048 { 2049 name: "DIVSS", 2050 argLen: 2, 2051 resultInArg0: true, 2052 usesScratch: true, 2053 asm: x86.ADIVSS, 2054 reg: regInfo{ 2055 inputs: []inputInfo{ 2056 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2057 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2058 }, 2059 outputs: []outputInfo{ 2060 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2061 }, 2062 }, 2063 }, 2064 { 2065 name: "DIVSD", 2066 argLen: 2, 2067 resultInArg0: true, 2068 asm: x86.ADIVSD, 2069 reg: regInfo{ 2070 inputs: []inputInfo{ 2071 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2072 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2073 }, 2074 outputs: []outputInfo{ 2075 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2076 }, 2077 }, 2078 }, 2079 { 2080 name: "MOVSSload", 2081 auxType: auxSymOff, 2082 argLen: 2, 2083 faultOnNilArg0: true, 2084 symEffect: SymRead, 2085 asm: x86.AMOVSS, 2086 reg: regInfo{ 2087 inputs: []inputInfo{ 2088 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2089 }, 2090 outputs: []outputInfo{ 2091 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2092 }, 2093 }, 2094 }, 2095 { 2096 name: "MOVSDload", 2097 auxType: auxSymOff, 2098 argLen: 2, 2099 faultOnNilArg0: true, 2100 symEffect: SymRead, 2101 asm: x86.AMOVSD, 2102 reg: regInfo{ 2103 inputs: []inputInfo{ 2104 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2105 }, 2106 outputs: []outputInfo{ 2107 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2108 }, 2109 }, 2110 }, 2111 { 2112 name: "MOVSSconst", 2113 auxType: auxFloat32, 2114 argLen: 0, 2115 rematerializeable: true, 2116 asm: x86.AMOVSS, 2117 reg: regInfo{ 2118 outputs: []outputInfo{ 2119 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2120 }, 2121 }, 2122 }, 2123 { 2124 name: "MOVSDconst", 2125 auxType: auxFloat64, 2126 argLen: 0, 2127 rematerializeable: true, 2128 asm: x86.AMOVSD, 2129 reg: regInfo{ 2130 outputs: []outputInfo{ 2131 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2132 }, 2133 }, 2134 }, 2135 { 2136 name: "MOVSSloadidx1", 2137 auxType: auxSymOff, 2138 argLen: 3, 2139 symEffect: SymRead, 2140 asm: x86.AMOVSS, 2141 reg: regInfo{ 2142 inputs: []inputInfo{ 2143 {1, 255}, // AX CX DX BX SP BP SI DI 2144 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2145 }, 2146 outputs: []outputInfo{ 2147 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2148 }, 2149 }, 2150 }, 2151 { 2152 name: "MOVSSloadidx4", 2153 auxType: auxSymOff, 2154 argLen: 3, 2155 symEffect: SymRead, 2156 asm: x86.AMOVSS, 2157 reg: regInfo{ 2158 inputs: []inputInfo{ 2159 {1, 255}, // AX CX DX BX SP BP SI DI 2160 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2161 }, 2162 outputs: []outputInfo{ 2163 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2164 }, 2165 }, 2166 }, 2167 { 2168 name: "MOVSDloadidx1", 2169 auxType: auxSymOff, 2170 argLen: 3, 2171 symEffect: SymRead, 2172 asm: x86.AMOVSD, 2173 reg: regInfo{ 2174 inputs: []inputInfo{ 2175 {1, 255}, // AX CX DX BX SP BP SI DI 2176 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2177 }, 2178 outputs: []outputInfo{ 2179 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2180 }, 2181 }, 2182 }, 2183 { 2184 name: "MOVSDloadidx8", 2185 auxType: auxSymOff, 2186 argLen: 3, 2187 symEffect: SymRead, 2188 asm: x86.AMOVSD, 2189 reg: regInfo{ 2190 inputs: []inputInfo{ 2191 {1, 255}, // AX CX DX BX SP BP SI DI 2192 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2193 }, 2194 outputs: []outputInfo{ 2195 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2196 }, 2197 }, 2198 }, 2199 { 2200 name: "MOVSSstore", 2201 auxType: auxSymOff, 2202 argLen: 3, 2203 faultOnNilArg0: true, 2204 symEffect: SymWrite, 2205 asm: x86.AMOVSS, 2206 reg: regInfo{ 2207 inputs: []inputInfo{ 2208 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2209 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2210 }, 2211 }, 2212 }, 2213 { 2214 name: "MOVSDstore", 2215 auxType: auxSymOff, 2216 argLen: 3, 2217 faultOnNilArg0: true, 2218 symEffect: SymWrite, 2219 asm: x86.AMOVSD, 2220 reg: regInfo{ 2221 inputs: []inputInfo{ 2222 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2223 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2224 }, 2225 }, 2226 }, 2227 { 2228 name: "MOVSSstoreidx1", 2229 auxType: auxSymOff, 2230 argLen: 4, 2231 symEffect: SymWrite, 2232 asm: x86.AMOVSS, 2233 reg: regInfo{ 2234 inputs: []inputInfo{ 2235 {1, 255}, // AX CX DX BX SP BP SI DI 2236 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2237 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2238 }, 2239 }, 2240 }, 2241 { 2242 name: "MOVSSstoreidx4", 2243 auxType: auxSymOff, 2244 argLen: 4, 2245 symEffect: SymWrite, 2246 asm: x86.AMOVSS, 2247 reg: regInfo{ 2248 inputs: []inputInfo{ 2249 {1, 255}, // AX CX DX BX SP BP SI DI 2250 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2251 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2252 }, 2253 }, 2254 }, 2255 { 2256 name: "MOVSDstoreidx1", 2257 auxType: auxSymOff, 2258 argLen: 4, 2259 symEffect: SymWrite, 2260 asm: x86.AMOVSD, 2261 reg: regInfo{ 2262 inputs: []inputInfo{ 2263 {1, 255}, // AX CX DX BX SP BP SI DI 2264 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2265 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2266 }, 2267 }, 2268 }, 2269 { 2270 name: "MOVSDstoreidx8", 2271 auxType: auxSymOff, 2272 argLen: 4, 2273 symEffect: SymWrite, 2274 asm: x86.AMOVSD, 2275 reg: regInfo{ 2276 inputs: []inputInfo{ 2277 {1, 255}, // AX CX DX BX SP BP SI DI 2278 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2279 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2280 }, 2281 }, 2282 }, 2283 { 2284 name: "ADDL", 2285 argLen: 2, 2286 commutative: true, 2287 clobberFlags: true, 2288 asm: x86.AADDL, 2289 reg: regInfo{ 2290 inputs: []inputInfo{ 2291 {1, 239}, // AX CX DX BX BP SI DI 2292 {0, 255}, // AX CX DX BX SP BP SI DI 2293 }, 2294 outputs: []outputInfo{ 2295 {0, 239}, // AX CX DX BX BP SI DI 2296 }, 2297 }, 2298 }, 2299 { 2300 name: "ADDLconst", 2301 auxType: auxInt32, 2302 argLen: 1, 2303 clobberFlags: true, 2304 asm: x86.AADDL, 2305 reg: regInfo{ 2306 inputs: []inputInfo{ 2307 {0, 255}, // AX CX DX BX SP BP SI DI 2308 }, 2309 outputs: []outputInfo{ 2310 {0, 239}, // AX CX DX BX BP SI DI 2311 }, 2312 }, 2313 }, 2314 { 2315 name: "ADDLcarry", 2316 argLen: 2, 2317 commutative: true, 2318 resultInArg0: true, 2319 asm: x86.AADDL, 2320 reg: regInfo{ 2321 inputs: []inputInfo{ 2322 {0, 239}, // AX CX DX BX BP SI DI 2323 {1, 239}, // AX CX DX BX BP SI DI 2324 }, 2325 outputs: []outputInfo{ 2326 {1, 0}, 2327 {0, 239}, // AX CX DX BX BP SI DI 2328 }, 2329 }, 2330 }, 2331 { 2332 name: "ADDLconstcarry", 2333 auxType: auxInt32, 2334 argLen: 1, 2335 resultInArg0: true, 2336 asm: x86.AADDL, 2337 reg: regInfo{ 2338 inputs: []inputInfo{ 2339 {0, 239}, // AX CX DX BX BP SI DI 2340 }, 2341 outputs: []outputInfo{ 2342 {1, 0}, 2343 {0, 239}, // AX CX DX BX BP SI DI 2344 }, 2345 }, 2346 }, 2347 { 2348 name: "ADCL", 2349 argLen: 3, 2350 commutative: true, 2351 resultInArg0: true, 2352 clobberFlags: true, 2353 asm: x86.AADCL, 2354 reg: regInfo{ 2355 inputs: []inputInfo{ 2356 {0, 239}, // AX CX DX BX BP SI DI 2357 {1, 239}, // AX CX DX BX BP SI DI 2358 }, 2359 outputs: []outputInfo{ 2360 {0, 239}, // AX CX DX BX BP SI DI 2361 }, 2362 }, 2363 }, 2364 { 2365 name: "ADCLconst", 2366 auxType: auxInt32, 2367 argLen: 2, 2368 resultInArg0: true, 2369 clobberFlags: true, 2370 asm: x86.AADCL, 2371 reg: regInfo{ 2372 inputs: []inputInfo{ 2373 {0, 239}, // AX CX DX BX BP SI DI 2374 }, 2375 outputs: []outputInfo{ 2376 {0, 239}, // AX CX DX BX BP SI DI 2377 }, 2378 }, 2379 }, 2380 { 2381 name: "SUBL", 2382 argLen: 2, 2383 resultInArg0: true, 2384 clobberFlags: true, 2385 asm: x86.ASUBL, 2386 reg: regInfo{ 2387 inputs: []inputInfo{ 2388 {0, 239}, // AX CX DX BX BP SI DI 2389 {1, 239}, // AX CX DX BX BP SI DI 2390 }, 2391 outputs: []outputInfo{ 2392 {0, 239}, // AX CX DX BX BP SI DI 2393 }, 2394 }, 2395 }, 2396 { 2397 name: "SUBLconst", 2398 auxType: auxInt32, 2399 argLen: 1, 2400 resultInArg0: true, 2401 clobberFlags: true, 2402 asm: x86.ASUBL, 2403 reg: regInfo{ 2404 inputs: []inputInfo{ 2405 {0, 239}, // AX CX DX BX BP SI DI 2406 }, 2407 outputs: []outputInfo{ 2408 {0, 239}, // AX CX DX BX BP SI DI 2409 }, 2410 }, 2411 }, 2412 { 2413 name: "SUBLcarry", 2414 argLen: 2, 2415 resultInArg0: true, 2416 asm: x86.ASUBL, 2417 reg: regInfo{ 2418 inputs: []inputInfo{ 2419 {0, 239}, // AX CX DX BX BP SI DI 2420 {1, 239}, // AX CX DX BX BP SI DI 2421 }, 2422 outputs: []outputInfo{ 2423 {1, 0}, 2424 {0, 239}, // AX CX DX BX BP SI DI 2425 }, 2426 }, 2427 }, 2428 { 2429 name: "SUBLconstcarry", 2430 auxType: auxInt32, 2431 argLen: 1, 2432 resultInArg0: true, 2433 asm: x86.ASUBL, 2434 reg: regInfo{ 2435 inputs: []inputInfo{ 2436 {0, 239}, // AX CX DX BX BP SI DI 2437 }, 2438 outputs: []outputInfo{ 2439 {1, 0}, 2440 {0, 239}, // AX CX DX BX BP SI DI 2441 }, 2442 }, 2443 }, 2444 { 2445 name: "SBBL", 2446 argLen: 3, 2447 resultInArg0: true, 2448 clobberFlags: true, 2449 asm: x86.ASBBL, 2450 reg: regInfo{ 2451 inputs: []inputInfo{ 2452 {0, 239}, // AX CX DX BX BP SI DI 2453 {1, 239}, // AX CX DX BX BP SI DI 2454 }, 2455 outputs: []outputInfo{ 2456 {0, 239}, // AX CX DX BX BP SI DI 2457 }, 2458 }, 2459 }, 2460 { 2461 name: "SBBLconst", 2462 auxType: auxInt32, 2463 argLen: 2, 2464 resultInArg0: true, 2465 clobberFlags: true, 2466 asm: x86.ASBBL, 2467 reg: regInfo{ 2468 inputs: []inputInfo{ 2469 {0, 239}, // AX CX DX BX BP SI DI 2470 }, 2471 outputs: []outputInfo{ 2472 {0, 239}, // AX CX DX BX BP SI DI 2473 }, 2474 }, 2475 }, 2476 { 2477 name: "MULL", 2478 argLen: 2, 2479 commutative: true, 2480 resultInArg0: true, 2481 clobberFlags: true, 2482 asm: x86.AIMULL, 2483 reg: regInfo{ 2484 inputs: []inputInfo{ 2485 {0, 239}, // AX CX DX BX BP SI DI 2486 {1, 239}, // AX CX DX BX BP SI DI 2487 }, 2488 outputs: []outputInfo{ 2489 {0, 239}, // AX CX DX BX BP SI DI 2490 }, 2491 }, 2492 }, 2493 { 2494 name: "MULLconst", 2495 auxType: auxInt32, 2496 argLen: 1, 2497 resultInArg0: true, 2498 clobberFlags: true, 2499 asm: x86.AIMULL, 2500 reg: regInfo{ 2501 inputs: []inputInfo{ 2502 {0, 239}, // AX CX DX BX BP SI DI 2503 }, 2504 outputs: []outputInfo{ 2505 {0, 239}, // AX CX DX BX BP SI DI 2506 }, 2507 }, 2508 }, 2509 { 2510 name: "HMULL", 2511 argLen: 2, 2512 commutative: true, 2513 clobberFlags: true, 2514 asm: x86.AIMULL, 2515 reg: regInfo{ 2516 inputs: []inputInfo{ 2517 {0, 1}, // AX 2518 {1, 255}, // AX CX DX BX SP BP SI DI 2519 }, 2520 clobbers: 1, // AX 2521 outputs: []outputInfo{ 2522 {0, 4}, // DX 2523 }, 2524 }, 2525 }, 2526 { 2527 name: "HMULLU", 2528 argLen: 2, 2529 commutative: true, 2530 clobberFlags: true, 2531 asm: x86.AMULL, 2532 reg: regInfo{ 2533 inputs: []inputInfo{ 2534 {0, 1}, // AX 2535 {1, 255}, // AX CX DX BX SP BP SI DI 2536 }, 2537 clobbers: 1, // AX 2538 outputs: []outputInfo{ 2539 {0, 4}, // DX 2540 }, 2541 }, 2542 }, 2543 { 2544 name: "MULLQU", 2545 argLen: 2, 2546 commutative: true, 2547 clobberFlags: true, 2548 asm: x86.AMULL, 2549 reg: regInfo{ 2550 inputs: []inputInfo{ 2551 {0, 1}, // AX 2552 {1, 255}, // AX CX DX BX SP BP SI DI 2553 }, 2554 outputs: []outputInfo{ 2555 {0, 4}, // DX 2556 {1, 1}, // AX 2557 }, 2558 }, 2559 }, 2560 { 2561 name: "AVGLU", 2562 argLen: 2, 2563 commutative: true, 2564 resultInArg0: true, 2565 clobberFlags: true, 2566 reg: regInfo{ 2567 inputs: []inputInfo{ 2568 {0, 239}, // AX CX DX BX BP SI DI 2569 {1, 239}, // AX CX DX BX BP SI DI 2570 }, 2571 outputs: []outputInfo{ 2572 {0, 239}, // AX CX DX BX BP SI DI 2573 }, 2574 }, 2575 }, 2576 { 2577 name: "DIVL", 2578 argLen: 2, 2579 clobberFlags: true, 2580 asm: x86.AIDIVL, 2581 reg: regInfo{ 2582 inputs: []inputInfo{ 2583 {0, 1}, // AX 2584 {1, 251}, // AX CX BX SP BP SI DI 2585 }, 2586 clobbers: 4, // DX 2587 outputs: []outputInfo{ 2588 {0, 1}, // AX 2589 }, 2590 }, 2591 }, 2592 { 2593 name: "DIVW", 2594 argLen: 2, 2595 clobberFlags: true, 2596 asm: x86.AIDIVW, 2597 reg: regInfo{ 2598 inputs: []inputInfo{ 2599 {0, 1}, // AX 2600 {1, 251}, // AX CX BX SP BP SI DI 2601 }, 2602 clobbers: 4, // DX 2603 outputs: []outputInfo{ 2604 {0, 1}, // AX 2605 }, 2606 }, 2607 }, 2608 { 2609 name: "DIVLU", 2610 argLen: 2, 2611 clobberFlags: true, 2612 asm: x86.ADIVL, 2613 reg: regInfo{ 2614 inputs: []inputInfo{ 2615 {0, 1}, // AX 2616 {1, 251}, // AX CX BX SP BP SI DI 2617 }, 2618 clobbers: 4, // DX 2619 outputs: []outputInfo{ 2620 {0, 1}, // AX 2621 }, 2622 }, 2623 }, 2624 { 2625 name: "DIVWU", 2626 argLen: 2, 2627 clobberFlags: true, 2628 asm: x86.ADIVW, 2629 reg: regInfo{ 2630 inputs: []inputInfo{ 2631 {0, 1}, // AX 2632 {1, 251}, // AX CX BX SP BP SI DI 2633 }, 2634 clobbers: 4, // DX 2635 outputs: []outputInfo{ 2636 {0, 1}, // AX 2637 }, 2638 }, 2639 }, 2640 { 2641 name: "MODL", 2642 argLen: 2, 2643 clobberFlags: true, 2644 asm: x86.AIDIVL, 2645 reg: regInfo{ 2646 inputs: []inputInfo{ 2647 {0, 1}, // AX 2648 {1, 251}, // AX CX BX SP BP SI DI 2649 }, 2650 clobbers: 1, // AX 2651 outputs: []outputInfo{ 2652 {0, 4}, // DX 2653 }, 2654 }, 2655 }, 2656 { 2657 name: "MODW", 2658 argLen: 2, 2659 clobberFlags: true, 2660 asm: x86.AIDIVW, 2661 reg: regInfo{ 2662 inputs: []inputInfo{ 2663 {0, 1}, // AX 2664 {1, 251}, // AX CX BX SP BP SI DI 2665 }, 2666 clobbers: 1, // AX 2667 outputs: []outputInfo{ 2668 {0, 4}, // DX 2669 }, 2670 }, 2671 }, 2672 { 2673 name: "MODLU", 2674 argLen: 2, 2675 clobberFlags: true, 2676 asm: x86.ADIVL, 2677 reg: regInfo{ 2678 inputs: []inputInfo{ 2679 {0, 1}, // AX 2680 {1, 251}, // AX CX BX SP BP SI DI 2681 }, 2682 clobbers: 1, // AX 2683 outputs: []outputInfo{ 2684 {0, 4}, // DX 2685 }, 2686 }, 2687 }, 2688 { 2689 name: "MODWU", 2690 argLen: 2, 2691 clobberFlags: true, 2692 asm: x86.ADIVW, 2693 reg: regInfo{ 2694 inputs: []inputInfo{ 2695 {0, 1}, // AX 2696 {1, 251}, // AX CX BX SP BP SI DI 2697 }, 2698 clobbers: 1, // AX 2699 outputs: []outputInfo{ 2700 {0, 4}, // DX 2701 }, 2702 }, 2703 }, 2704 { 2705 name: "ANDL", 2706 argLen: 2, 2707 commutative: true, 2708 resultInArg0: true, 2709 clobberFlags: true, 2710 asm: x86.AANDL, 2711 reg: regInfo{ 2712 inputs: []inputInfo{ 2713 {0, 239}, // AX CX DX BX BP SI DI 2714 {1, 239}, // AX CX DX BX BP SI DI 2715 }, 2716 outputs: []outputInfo{ 2717 {0, 239}, // AX CX DX BX BP SI DI 2718 }, 2719 }, 2720 }, 2721 { 2722 name: "ANDLconst", 2723 auxType: auxInt32, 2724 argLen: 1, 2725 resultInArg0: true, 2726 clobberFlags: true, 2727 asm: x86.AANDL, 2728 reg: regInfo{ 2729 inputs: []inputInfo{ 2730 {0, 239}, // AX CX DX BX BP SI DI 2731 }, 2732 outputs: []outputInfo{ 2733 {0, 239}, // AX CX DX BX BP SI DI 2734 }, 2735 }, 2736 }, 2737 { 2738 name: "ORL", 2739 argLen: 2, 2740 commutative: true, 2741 resultInArg0: true, 2742 clobberFlags: true, 2743 asm: x86.AORL, 2744 reg: regInfo{ 2745 inputs: []inputInfo{ 2746 {0, 239}, // AX CX DX BX BP SI DI 2747 {1, 239}, // AX CX DX BX BP SI DI 2748 }, 2749 outputs: []outputInfo{ 2750 {0, 239}, // AX CX DX BX BP SI DI 2751 }, 2752 }, 2753 }, 2754 { 2755 name: "ORLconst", 2756 auxType: auxInt32, 2757 argLen: 1, 2758 resultInArg0: true, 2759 clobberFlags: true, 2760 asm: x86.AORL, 2761 reg: regInfo{ 2762 inputs: []inputInfo{ 2763 {0, 239}, // AX CX DX BX BP SI DI 2764 }, 2765 outputs: []outputInfo{ 2766 {0, 239}, // AX CX DX BX BP SI DI 2767 }, 2768 }, 2769 }, 2770 { 2771 name: "XORL", 2772 argLen: 2, 2773 commutative: true, 2774 resultInArg0: true, 2775 clobberFlags: true, 2776 asm: x86.AXORL, 2777 reg: regInfo{ 2778 inputs: []inputInfo{ 2779 {0, 239}, // AX CX DX BX BP SI DI 2780 {1, 239}, // AX CX DX BX BP SI DI 2781 }, 2782 outputs: []outputInfo{ 2783 {0, 239}, // AX CX DX BX BP SI DI 2784 }, 2785 }, 2786 }, 2787 { 2788 name: "XORLconst", 2789 auxType: auxInt32, 2790 argLen: 1, 2791 resultInArg0: true, 2792 clobberFlags: true, 2793 asm: x86.AXORL, 2794 reg: regInfo{ 2795 inputs: []inputInfo{ 2796 {0, 239}, // AX CX DX BX BP SI DI 2797 }, 2798 outputs: []outputInfo{ 2799 {0, 239}, // AX CX DX BX BP SI DI 2800 }, 2801 }, 2802 }, 2803 { 2804 name: "CMPL", 2805 argLen: 2, 2806 asm: x86.ACMPL, 2807 reg: regInfo{ 2808 inputs: []inputInfo{ 2809 {0, 255}, // AX CX DX BX SP BP SI DI 2810 {1, 255}, // AX CX DX BX SP BP SI DI 2811 }, 2812 }, 2813 }, 2814 { 2815 name: "CMPW", 2816 argLen: 2, 2817 asm: x86.ACMPW, 2818 reg: regInfo{ 2819 inputs: []inputInfo{ 2820 {0, 255}, // AX CX DX BX SP BP SI DI 2821 {1, 255}, // AX CX DX BX SP BP SI DI 2822 }, 2823 }, 2824 }, 2825 { 2826 name: "CMPB", 2827 argLen: 2, 2828 asm: x86.ACMPB, 2829 reg: regInfo{ 2830 inputs: []inputInfo{ 2831 {0, 255}, // AX CX DX BX SP BP SI DI 2832 {1, 255}, // AX CX DX BX SP BP SI DI 2833 }, 2834 }, 2835 }, 2836 { 2837 name: "CMPLconst", 2838 auxType: auxInt32, 2839 argLen: 1, 2840 asm: x86.ACMPL, 2841 reg: regInfo{ 2842 inputs: []inputInfo{ 2843 {0, 255}, // AX CX DX BX SP BP SI DI 2844 }, 2845 }, 2846 }, 2847 { 2848 name: "CMPWconst", 2849 auxType: auxInt16, 2850 argLen: 1, 2851 asm: x86.ACMPW, 2852 reg: regInfo{ 2853 inputs: []inputInfo{ 2854 {0, 255}, // AX CX DX BX SP BP SI DI 2855 }, 2856 }, 2857 }, 2858 { 2859 name: "CMPBconst", 2860 auxType: auxInt8, 2861 argLen: 1, 2862 asm: x86.ACMPB, 2863 reg: regInfo{ 2864 inputs: []inputInfo{ 2865 {0, 255}, // AX CX DX BX SP BP SI DI 2866 }, 2867 }, 2868 }, 2869 { 2870 name: "UCOMISS", 2871 argLen: 2, 2872 usesScratch: true, 2873 asm: x86.AUCOMISS, 2874 reg: regInfo{ 2875 inputs: []inputInfo{ 2876 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2877 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2878 }, 2879 }, 2880 }, 2881 { 2882 name: "UCOMISD", 2883 argLen: 2, 2884 usesScratch: true, 2885 asm: x86.AUCOMISD, 2886 reg: regInfo{ 2887 inputs: []inputInfo{ 2888 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2889 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2890 }, 2891 }, 2892 }, 2893 { 2894 name: "TESTL", 2895 argLen: 2, 2896 commutative: true, 2897 asm: x86.ATESTL, 2898 reg: regInfo{ 2899 inputs: []inputInfo{ 2900 {0, 255}, // AX CX DX BX SP BP SI DI 2901 {1, 255}, // AX CX DX BX SP BP SI DI 2902 }, 2903 }, 2904 }, 2905 { 2906 name: "TESTW", 2907 argLen: 2, 2908 commutative: true, 2909 asm: x86.ATESTW, 2910 reg: regInfo{ 2911 inputs: []inputInfo{ 2912 {0, 255}, // AX CX DX BX SP BP SI DI 2913 {1, 255}, // AX CX DX BX SP BP SI DI 2914 }, 2915 }, 2916 }, 2917 { 2918 name: "TESTB", 2919 argLen: 2, 2920 commutative: true, 2921 asm: x86.ATESTB, 2922 reg: regInfo{ 2923 inputs: []inputInfo{ 2924 {0, 255}, // AX CX DX BX SP BP SI DI 2925 {1, 255}, // AX CX DX BX SP BP SI DI 2926 }, 2927 }, 2928 }, 2929 { 2930 name: "TESTLconst", 2931 auxType: auxInt32, 2932 argLen: 1, 2933 asm: x86.ATESTL, 2934 reg: regInfo{ 2935 inputs: []inputInfo{ 2936 {0, 255}, // AX CX DX BX SP BP SI DI 2937 }, 2938 }, 2939 }, 2940 { 2941 name: "TESTWconst", 2942 auxType: auxInt16, 2943 argLen: 1, 2944 asm: x86.ATESTW, 2945 reg: regInfo{ 2946 inputs: []inputInfo{ 2947 {0, 255}, // AX CX DX BX SP BP SI DI 2948 }, 2949 }, 2950 }, 2951 { 2952 name: "TESTBconst", 2953 auxType: auxInt8, 2954 argLen: 1, 2955 asm: x86.ATESTB, 2956 reg: regInfo{ 2957 inputs: []inputInfo{ 2958 {0, 255}, // AX CX DX BX SP BP SI DI 2959 }, 2960 }, 2961 }, 2962 { 2963 name: "SHLL", 2964 argLen: 2, 2965 resultInArg0: true, 2966 clobberFlags: true, 2967 asm: x86.ASHLL, 2968 reg: regInfo{ 2969 inputs: []inputInfo{ 2970 {1, 2}, // CX 2971 {0, 239}, // AX CX DX BX BP SI DI 2972 }, 2973 outputs: []outputInfo{ 2974 {0, 239}, // AX CX DX BX BP SI DI 2975 }, 2976 }, 2977 }, 2978 { 2979 name: "SHLLconst", 2980 auxType: auxInt32, 2981 argLen: 1, 2982 resultInArg0: true, 2983 clobberFlags: true, 2984 asm: x86.ASHLL, 2985 reg: regInfo{ 2986 inputs: []inputInfo{ 2987 {0, 239}, // AX CX DX BX BP SI DI 2988 }, 2989 outputs: []outputInfo{ 2990 {0, 239}, // AX CX DX BX BP SI DI 2991 }, 2992 }, 2993 }, 2994 { 2995 name: "SHRL", 2996 argLen: 2, 2997 resultInArg0: true, 2998 clobberFlags: true, 2999 asm: x86.ASHRL, 3000 reg: regInfo{ 3001 inputs: []inputInfo{ 3002 {1, 2}, // CX 3003 {0, 239}, // AX CX DX BX BP SI DI 3004 }, 3005 outputs: []outputInfo{ 3006 {0, 239}, // AX CX DX BX BP SI DI 3007 }, 3008 }, 3009 }, 3010 { 3011 name: "SHRW", 3012 argLen: 2, 3013 resultInArg0: true, 3014 clobberFlags: true, 3015 asm: x86.ASHRW, 3016 reg: regInfo{ 3017 inputs: []inputInfo{ 3018 {1, 2}, // CX 3019 {0, 239}, // AX CX DX BX BP SI DI 3020 }, 3021 outputs: []outputInfo{ 3022 {0, 239}, // AX CX DX BX BP SI DI 3023 }, 3024 }, 3025 }, 3026 { 3027 name: "SHRB", 3028 argLen: 2, 3029 resultInArg0: true, 3030 clobberFlags: true, 3031 asm: x86.ASHRB, 3032 reg: regInfo{ 3033 inputs: []inputInfo{ 3034 {1, 2}, // CX 3035 {0, 239}, // AX CX DX BX BP SI DI 3036 }, 3037 outputs: []outputInfo{ 3038 {0, 239}, // AX CX DX BX BP SI DI 3039 }, 3040 }, 3041 }, 3042 { 3043 name: "SHRLconst", 3044 auxType: auxInt32, 3045 argLen: 1, 3046 resultInArg0: true, 3047 clobberFlags: true, 3048 asm: x86.ASHRL, 3049 reg: regInfo{ 3050 inputs: []inputInfo{ 3051 {0, 239}, // AX CX DX BX BP SI DI 3052 }, 3053 outputs: []outputInfo{ 3054 {0, 239}, // AX CX DX BX BP SI DI 3055 }, 3056 }, 3057 }, 3058 { 3059 name: "SHRWconst", 3060 auxType: auxInt16, 3061 argLen: 1, 3062 resultInArg0: true, 3063 clobberFlags: true, 3064 asm: x86.ASHRW, 3065 reg: regInfo{ 3066 inputs: []inputInfo{ 3067 {0, 239}, // AX CX DX BX BP SI DI 3068 }, 3069 outputs: []outputInfo{ 3070 {0, 239}, // AX CX DX BX BP SI DI 3071 }, 3072 }, 3073 }, 3074 { 3075 name: "SHRBconst", 3076 auxType: auxInt8, 3077 argLen: 1, 3078 resultInArg0: true, 3079 clobberFlags: true, 3080 asm: x86.ASHRB, 3081 reg: regInfo{ 3082 inputs: []inputInfo{ 3083 {0, 239}, // AX CX DX BX BP SI DI 3084 }, 3085 outputs: []outputInfo{ 3086 {0, 239}, // AX CX DX BX BP SI DI 3087 }, 3088 }, 3089 }, 3090 { 3091 name: "SARL", 3092 argLen: 2, 3093 resultInArg0: true, 3094 clobberFlags: true, 3095 asm: x86.ASARL, 3096 reg: regInfo{ 3097 inputs: []inputInfo{ 3098 {1, 2}, // CX 3099 {0, 239}, // AX CX DX BX BP SI DI 3100 }, 3101 outputs: []outputInfo{ 3102 {0, 239}, // AX CX DX BX BP SI DI 3103 }, 3104 }, 3105 }, 3106 { 3107 name: "SARW", 3108 argLen: 2, 3109 resultInArg0: true, 3110 clobberFlags: true, 3111 asm: x86.ASARW, 3112 reg: regInfo{ 3113 inputs: []inputInfo{ 3114 {1, 2}, // CX 3115 {0, 239}, // AX CX DX BX BP SI DI 3116 }, 3117 outputs: []outputInfo{ 3118 {0, 239}, // AX CX DX BX BP SI DI 3119 }, 3120 }, 3121 }, 3122 { 3123 name: "SARB", 3124 argLen: 2, 3125 resultInArg0: true, 3126 clobberFlags: true, 3127 asm: x86.ASARB, 3128 reg: regInfo{ 3129 inputs: []inputInfo{ 3130 {1, 2}, // CX 3131 {0, 239}, // AX CX DX BX BP SI DI 3132 }, 3133 outputs: []outputInfo{ 3134 {0, 239}, // AX CX DX BX BP SI DI 3135 }, 3136 }, 3137 }, 3138 { 3139 name: "SARLconst", 3140 auxType: auxInt32, 3141 argLen: 1, 3142 resultInArg0: true, 3143 clobberFlags: true, 3144 asm: x86.ASARL, 3145 reg: regInfo{ 3146 inputs: []inputInfo{ 3147 {0, 239}, // AX CX DX BX BP SI DI 3148 }, 3149 outputs: []outputInfo{ 3150 {0, 239}, // AX CX DX BX BP SI DI 3151 }, 3152 }, 3153 }, 3154 { 3155 name: "SARWconst", 3156 auxType: auxInt16, 3157 argLen: 1, 3158 resultInArg0: true, 3159 clobberFlags: true, 3160 asm: x86.ASARW, 3161 reg: regInfo{ 3162 inputs: []inputInfo{ 3163 {0, 239}, // AX CX DX BX BP SI DI 3164 }, 3165 outputs: []outputInfo{ 3166 {0, 239}, // AX CX DX BX BP SI DI 3167 }, 3168 }, 3169 }, 3170 { 3171 name: "SARBconst", 3172 auxType: auxInt8, 3173 argLen: 1, 3174 resultInArg0: true, 3175 clobberFlags: true, 3176 asm: x86.ASARB, 3177 reg: regInfo{ 3178 inputs: []inputInfo{ 3179 {0, 239}, // AX CX DX BX BP SI DI 3180 }, 3181 outputs: []outputInfo{ 3182 {0, 239}, // AX CX DX BX BP SI DI 3183 }, 3184 }, 3185 }, 3186 { 3187 name: "ROLLconst", 3188 auxType: auxInt32, 3189 argLen: 1, 3190 resultInArg0: true, 3191 clobberFlags: true, 3192 asm: x86.AROLL, 3193 reg: regInfo{ 3194 inputs: []inputInfo{ 3195 {0, 239}, // AX CX DX BX BP SI DI 3196 }, 3197 outputs: []outputInfo{ 3198 {0, 239}, // AX CX DX BX BP SI DI 3199 }, 3200 }, 3201 }, 3202 { 3203 name: "ROLWconst", 3204 auxType: auxInt16, 3205 argLen: 1, 3206 resultInArg0: true, 3207 clobberFlags: true, 3208 asm: x86.AROLW, 3209 reg: regInfo{ 3210 inputs: []inputInfo{ 3211 {0, 239}, // AX CX DX BX BP SI DI 3212 }, 3213 outputs: []outputInfo{ 3214 {0, 239}, // AX CX DX BX BP SI DI 3215 }, 3216 }, 3217 }, 3218 { 3219 name: "ROLBconst", 3220 auxType: auxInt8, 3221 argLen: 1, 3222 resultInArg0: true, 3223 clobberFlags: true, 3224 asm: x86.AROLB, 3225 reg: regInfo{ 3226 inputs: []inputInfo{ 3227 {0, 239}, // AX CX DX BX BP SI DI 3228 }, 3229 outputs: []outputInfo{ 3230 {0, 239}, // AX CX DX BX BP SI DI 3231 }, 3232 }, 3233 }, 3234 { 3235 name: "NEGL", 3236 argLen: 1, 3237 resultInArg0: true, 3238 clobberFlags: true, 3239 asm: x86.ANEGL, 3240 reg: regInfo{ 3241 inputs: []inputInfo{ 3242 {0, 239}, // AX CX DX BX BP SI DI 3243 }, 3244 outputs: []outputInfo{ 3245 {0, 239}, // AX CX DX BX BP SI DI 3246 }, 3247 }, 3248 }, 3249 { 3250 name: "NOTL", 3251 argLen: 1, 3252 resultInArg0: true, 3253 clobberFlags: true, 3254 asm: x86.ANOTL, 3255 reg: regInfo{ 3256 inputs: []inputInfo{ 3257 {0, 239}, // AX CX DX BX BP SI DI 3258 }, 3259 outputs: []outputInfo{ 3260 {0, 239}, // AX CX DX BX BP SI DI 3261 }, 3262 }, 3263 }, 3264 { 3265 name: "BSFL", 3266 argLen: 1, 3267 clobberFlags: true, 3268 asm: x86.ABSFL, 3269 reg: regInfo{ 3270 inputs: []inputInfo{ 3271 {0, 239}, // AX CX DX BX BP SI DI 3272 }, 3273 outputs: []outputInfo{ 3274 {0, 239}, // AX CX DX BX BP SI DI 3275 }, 3276 }, 3277 }, 3278 { 3279 name: "BSFW", 3280 argLen: 1, 3281 clobberFlags: true, 3282 asm: x86.ABSFW, 3283 reg: regInfo{ 3284 inputs: []inputInfo{ 3285 {0, 239}, // AX CX DX BX BP SI DI 3286 }, 3287 outputs: []outputInfo{ 3288 {0, 239}, // AX CX DX BX BP SI DI 3289 }, 3290 }, 3291 }, 3292 { 3293 name: "BSRL", 3294 argLen: 1, 3295 clobberFlags: true, 3296 asm: x86.ABSRL, 3297 reg: regInfo{ 3298 inputs: []inputInfo{ 3299 {0, 239}, // AX CX DX BX BP SI DI 3300 }, 3301 outputs: []outputInfo{ 3302 {0, 239}, // AX CX DX BX BP SI DI 3303 }, 3304 }, 3305 }, 3306 { 3307 name: "BSRW", 3308 argLen: 1, 3309 clobberFlags: true, 3310 asm: x86.ABSRW, 3311 reg: regInfo{ 3312 inputs: []inputInfo{ 3313 {0, 239}, // AX CX DX BX BP SI DI 3314 }, 3315 outputs: []outputInfo{ 3316 {0, 239}, // AX CX DX BX BP SI DI 3317 }, 3318 }, 3319 }, 3320 { 3321 name: "BSWAPL", 3322 argLen: 1, 3323 resultInArg0: true, 3324 clobberFlags: true, 3325 asm: x86.ABSWAPL, 3326 reg: regInfo{ 3327 inputs: []inputInfo{ 3328 {0, 239}, // AX CX DX BX BP SI DI 3329 }, 3330 outputs: []outputInfo{ 3331 {0, 239}, // AX CX DX BX BP SI DI 3332 }, 3333 }, 3334 }, 3335 { 3336 name: "SQRTSD", 3337 argLen: 1, 3338 asm: x86.ASQRTSD, 3339 reg: regInfo{ 3340 inputs: []inputInfo{ 3341 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3342 }, 3343 outputs: []outputInfo{ 3344 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3345 }, 3346 }, 3347 }, 3348 { 3349 name: "SBBLcarrymask", 3350 argLen: 1, 3351 asm: x86.ASBBL, 3352 reg: regInfo{ 3353 outputs: []outputInfo{ 3354 {0, 239}, // AX CX DX BX BP SI DI 3355 }, 3356 }, 3357 }, 3358 { 3359 name: "SETEQ", 3360 argLen: 1, 3361 asm: x86.ASETEQ, 3362 reg: regInfo{ 3363 outputs: []outputInfo{ 3364 {0, 239}, // AX CX DX BX BP SI DI 3365 }, 3366 }, 3367 }, 3368 { 3369 name: "SETNE", 3370 argLen: 1, 3371 asm: x86.ASETNE, 3372 reg: regInfo{ 3373 outputs: []outputInfo{ 3374 {0, 239}, // AX CX DX BX BP SI DI 3375 }, 3376 }, 3377 }, 3378 { 3379 name: "SETL", 3380 argLen: 1, 3381 asm: x86.ASETLT, 3382 reg: regInfo{ 3383 outputs: []outputInfo{ 3384 {0, 239}, // AX CX DX BX BP SI DI 3385 }, 3386 }, 3387 }, 3388 { 3389 name: "SETLE", 3390 argLen: 1, 3391 asm: x86.ASETLE, 3392 reg: regInfo{ 3393 outputs: []outputInfo{ 3394 {0, 239}, // AX CX DX BX BP SI DI 3395 }, 3396 }, 3397 }, 3398 { 3399 name: "SETG", 3400 argLen: 1, 3401 asm: x86.ASETGT, 3402 reg: regInfo{ 3403 outputs: []outputInfo{ 3404 {0, 239}, // AX CX DX BX BP SI DI 3405 }, 3406 }, 3407 }, 3408 { 3409 name: "SETGE", 3410 argLen: 1, 3411 asm: x86.ASETGE, 3412 reg: regInfo{ 3413 outputs: []outputInfo{ 3414 {0, 239}, // AX CX DX BX BP SI DI 3415 }, 3416 }, 3417 }, 3418 { 3419 name: "SETB", 3420 argLen: 1, 3421 asm: x86.ASETCS, 3422 reg: regInfo{ 3423 outputs: []outputInfo{ 3424 {0, 239}, // AX CX DX BX BP SI DI 3425 }, 3426 }, 3427 }, 3428 { 3429 name: "SETBE", 3430 argLen: 1, 3431 asm: x86.ASETLS, 3432 reg: regInfo{ 3433 outputs: []outputInfo{ 3434 {0, 239}, // AX CX DX BX BP SI DI 3435 }, 3436 }, 3437 }, 3438 { 3439 name: "SETA", 3440 argLen: 1, 3441 asm: x86.ASETHI, 3442 reg: regInfo{ 3443 outputs: []outputInfo{ 3444 {0, 239}, // AX CX DX BX BP SI DI 3445 }, 3446 }, 3447 }, 3448 { 3449 name: "SETAE", 3450 argLen: 1, 3451 asm: x86.ASETCC, 3452 reg: regInfo{ 3453 outputs: []outputInfo{ 3454 {0, 239}, // AX CX DX BX BP SI DI 3455 }, 3456 }, 3457 }, 3458 { 3459 name: "SETEQF", 3460 argLen: 1, 3461 clobberFlags: true, 3462 asm: x86.ASETEQ, 3463 reg: regInfo{ 3464 clobbers: 1, // AX 3465 outputs: []outputInfo{ 3466 {0, 238}, // CX DX BX BP SI DI 3467 }, 3468 }, 3469 }, 3470 { 3471 name: "SETNEF", 3472 argLen: 1, 3473 clobberFlags: true, 3474 asm: x86.ASETNE, 3475 reg: regInfo{ 3476 clobbers: 1, // AX 3477 outputs: []outputInfo{ 3478 {0, 238}, // CX DX BX BP SI DI 3479 }, 3480 }, 3481 }, 3482 { 3483 name: "SETORD", 3484 argLen: 1, 3485 asm: x86.ASETPC, 3486 reg: regInfo{ 3487 outputs: []outputInfo{ 3488 {0, 239}, // AX CX DX BX BP SI DI 3489 }, 3490 }, 3491 }, 3492 { 3493 name: "SETNAN", 3494 argLen: 1, 3495 asm: x86.ASETPS, 3496 reg: regInfo{ 3497 outputs: []outputInfo{ 3498 {0, 239}, // AX CX DX BX BP SI DI 3499 }, 3500 }, 3501 }, 3502 { 3503 name: "SETGF", 3504 argLen: 1, 3505 asm: x86.ASETHI, 3506 reg: regInfo{ 3507 outputs: []outputInfo{ 3508 {0, 239}, // AX CX DX BX BP SI DI 3509 }, 3510 }, 3511 }, 3512 { 3513 name: "SETGEF", 3514 argLen: 1, 3515 asm: x86.ASETCC, 3516 reg: regInfo{ 3517 outputs: []outputInfo{ 3518 {0, 239}, // AX CX DX BX BP SI DI 3519 }, 3520 }, 3521 }, 3522 { 3523 name: "MOVBLSX", 3524 argLen: 1, 3525 asm: x86.AMOVBLSX, 3526 reg: regInfo{ 3527 inputs: []inputInfo{ 3528 {0, 239}, // AX CX DX BX BP SI DI 3529 }, 3530 outputs: []outputInfo{ 3531 {0, 239}, // AX CX DX BX BP SI DI 3532 }, 3533 }, 3534 }, 3535 { 3536 name: "MOVBLZX", 3537 argLen: 1, 3538 asm: x86.AMOVBLZX, 3539 reg: regInfo{ 3540 inputs: []inputInfo{ 3541 {0, 239}, // AX CX DX BX BP SI DI 3542 }, 3543 outputs: []outputInfo{ 3544 {0, 239}, // AX CX DX BX BP SI DI 3545 }, 3546 }, 3547 }, 3548 { 3549 name: "MOVWLSX", 3550 argLen: 1, 3551 asm: x86.AMOVWLSX, 3552 reg: regInfo{ 3553 inputs: []inputInfo{ 3554 {0, 239}, // AX CX DX BX BP SI DI 3555 }, 3556 outputs: []outputInfo{ 3557 {0, 239}, // AX CX DX BX BP SI DI 3558 }, 3559 }, 3560 }, 3561 { 3562 name: "MOVWLZX", 3563 argLen: 1, 3564 asm: x86.AMOVWLZX, 3565 reg: regInfo{ 3566 inputs: []inputInfo{ 3567 {0, 239}, // AX CX DX BX BP SI DI 3568 }, 3569 outputs: []outputInfo{ 3570 {0, 239}, // AX CX DX BX BP SI DI 3571 }, 3572 }, 3573 }, 3574 { 3575 name: "MOVLconst", 3576 auxType: auxInt32, 3577 argLen: 0, 3578 rematerializeable: true, 3579 asm: x86.AMOVL, 3580 reg: regInfo{ 3581 outputs: []outputInfo{ 3582 {0, 239}, // AX CX DX BX BP SI DI 3583 }, 3584 }, 3585 }, 3586 { 3587 name: "CVTTSD2SL", 3588 argLen: 1, 3589 usesScratch: true, 3590 asm: x86.ACVTTSD2SL, 3591 reg: regInfo{ 3592 inputs: []inputInfo{ 3593 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3594 }, 3595 outputs: []outputInfo{ 3596 {0, 239}, // AX CX DX BX BP SI DI 3597 }, 3598 }, 3599 }, 3600 { 3601 name: "CVTTSS2SL", 3602 argLen: 1, 3603 usesScratch: true, 3604 asm: x86.ACVTTSS2SL, 3605 reg: regInfo{ 3606 inputs: []inputInfo{ 3607 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3608 }, 3609 outputs: []outputInfo{ 3610 {0, 239}, // AX CX DX BX BP SI DI 3611 }, 3612 }, 3613 }, 3614 { 3615 name: "CVTSL2SS", 3616 argLen: 1, 3617 usesScratch: true, 3618 asm: x86.ACVTSL2SS, 3619 reg: regInfo{ 3620 inputs: []inputInfo{ 3621 {0, 239}, // AX CX DX BX BP SI DI 3622 }, 3623 outputs: []outputInfo{ 3624 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3625 }, 3626 }, 3627 }, 3628 { 3629 name: "CVTSL2SD", 3630 argLen: 1, 3631 usesScratch: true, 3632 asm: x86.ACVTSL2SD, 3633 reg: regInfo{ 3634 inputs: []inputInfo{ 3635 {0, 239}, // AX CX DX BX BP SI DI 3636 }, 3637 outputs: []outputInfo{ 3638 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3639 }, 3640 }, 3641 }, 3642 { 3643 name: "CVTSD2SS", 3644 argLen: 1, 3645 usesScratch: true, 3646 asm: x86.ACVTSD2SS, 3647 reg: regInfo{ 3648 inputs: []inputInfo{ 3649 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3650 }, 3651 outputs: []outputInfo{ 3652 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3653 }, 3654 }, 3655 }, 3656 { 3657 name: "CVTSS2SD", 3658 argLen: 1, 3659 asm: x86.ACVTSS2SD, 3660 reg: regInfo{ 3661 inputs: []inputInfo{ 3662 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3663 }, 3664 outputs: []outputInfo{ 3665 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3666 }, 3667 }, 3668 }, 3669 { 3670 name: "PXOR", 3671 argLen: 2, 3672 commutative: true, 3673 resultInArg0: true, 3674 asm: x86.APXOR, 3675 reg: regInfo{ 3676 inputs: []inputInfo{ 3677 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3678 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3679 }, 3680 outputs: []outputInfo{ 3681 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3682 }, 3683 }, 3684 }, 3685 { 3686 name: "LEAL", 3687 auxType: auxSymOff, 3688 argLen: 1, 3689 rematerializeable: true, 3690 symEffect: SymAddr, 3691 reg: regInfo{ 3692 inputs: []inputInfo{ 3693 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3694 }, 3695 outputs: []outputInfo{ 3696 {0, 239}, // AX CX DX BX BP SI DI 3697 }, 3698 }, 3699 }, 3700 { 3701 name: "LEAL1", 3702 auxType: auxSymOff, 3703 argLen: 2, 3704 commutative: true, 3705 symEffect: SymAddr, 3706 reg: regInfo{ 3707 inputs: []inputInfo{ 3708 {1, 255}, // AX CX DX BX SP BP SI DI 3709 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3710 }, 3711 outputs: []outputInfo{ 3712 {0, 239}, // AX CX DX BX BP SI DI 3713 }, 3714 }, 3715 }, 3716 { 3717 name: "LEAL2", 3718 auxType: auxSymOff, 3719 argLen: 2, 3720 symEffect: SymAddr, 3721 reg: regInfo{ 3722 inputs: []inputInfo{ 3723 {1, 255}, // AX CX DX BX SP BP SI DI 3724 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3725 }, 3726 outputs: []outputInfo{ 3727 {0, 239}, // AX CX DX BX BP SI DI 3728 }, 3729 }, 3730 }, 3731 { 3732 name: "LEAL4", 3733 auxType: auxSymOff, 3734 argLen: 2, 3735 symEffect: SymAddr, 3736 reg: regInfo{ 3737 inputs: []inputInfo{ 3738 {1, 255}, // AX CX DX BX SP BP SI DI 3739 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3740 }, 3741 outputs: []outputInfo{ 3742 {0, 239}, // AX CX DX BX BP SI DI 3743 }, 3744 }, 3745 }, 3746 { 3747 name: "LEAL8", 3748 auxType: auxSymOff, 3749 argLen: 2, 3750 symEffect: SymAddr, 3751 reg: regInfo{ 3752 inputs: []inputInfo{ 3753 {1, 255}, // AX CX DX BX SP BP SI DI 3754 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3755 }, 3756 outputs: []outputInfo{ 3757 {0, 239}, // AX CX DX BX BP SI DI 3758 }, 3759 }, 3760 }, 3761 { 3762 name: "MOVBload", 3763 auxType: auxSymOff, 3764 argLen: 2, 3765 faultOnNilArg0: true, 3766 symEffect: SymRead, 3767 asm: x86.AMOVBLZX, 3768 reg: regInfo{ 3769 inputs: []inputInfo{ 3770 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3771 }, 3772 outputs: []outputInfo{ 3773 {0, 239}, // AX CX DX BX BP SI DI 3774 }, 3775 }, 3776 }, 3777 { 3778 name: "MOVBLSXload", 3779 auxType: auxSymOff, 3780 argLen: 2, 3781 faultOnNilArg0: true, 3782 symEffect: SymRead, 3783 asm: x86.AMOVBLSX, 3784 reg: regInfo{ 3785 inputs: []inputInfo{ 3786 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3787 }, 3788 outputs: []outputInfo{ 3789 {0, 239}, // AX CX DX BX BP SI DI 3790 }, 3791 }, 3792 }, 3793 { 3794 name: "MOVWload", 3795 auxType: auxSymOff, 3796 argLen: 2, 3797 faultOnNilArg0: true, 3798 symEffect: SymRead, 3799 asm: x86.AMOVWLZX, 3800 reg: regInfo{ 3801 inputs: []inputInfo{ 3802 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3803 }, 3804 outputs: []outputInfo{ 3805 {0, 239}, // AX CX DX BX BP SI DI 3806 }, 3807 }, 3808 }, 3809 { 3810 name: "MOVWLSXload", 3811 auxType: auxSymOff, 3812 argLen: 2, 3813 faultOnNilArg0: true, 3814 symEffect: SymRead, 3815 asm: x86.AMOVWLSX, 3816 reg: regInfo{ 3817 inputs: []inputInfo{ 3818 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3819 }, 3820 outputs: []outputInfo{ 3821 {0, 239}, // AX CX DX BX BP SI DI 3822 }, 3823 }, 3824 }, 3825 { 3826 name: "MOVLload", 3827 auxType: auxSymOff, 3828 argLen: 2, 3829 faultOnNilArg0: true, 3830 symEffect: SymRead, 3831 asm: x86.AMOVL, 3832 reg: regInfo{ 3833 inputs: []inputInfo{ 3834 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3835 }, 3836 outputs: []outputInfo{ 3837 {0, 239}, // AX CX DX BX BP SI DI 3838 }, 3839 }, 3840 }, 3841 { 3842 name: "MOVBstore", 3843 auxType: auxSymOff, 3844 argLen: 3, 3845 faultOnNilArg0: true, 3846 symEffect: SymWrite, 3847 asm: x86.AMOVB, 3848 reg: regInfo{ 3849 inputs: []inputInfo{ 3850 {1, 255}, // AX CX DX BX SP BP SI DI 3851 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3852 }, 3853 }, 3854 }, 3855 { 3856 name: "MOVWstore", 3857 auxType: auxSymOff, 3858 argLen: 3, 3859 faultOnNilArg0: true, 3860 symEffect: SymWrite, 3861 asm: x86.AMOVW, 3862 reg: regInfo{ 3863 inputs: []inputInfo{ 3864 {1, 255}, // AX CX DX BX SP BP SI DI 3865 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3866 }, 3867 }, 3868 }, 3869 { 3870 name: "MOVLstore", 3871 auxType: auxSymOff, 3872 argLen: 3, 3873 faultOnNilArg0: true, 3874 symEffect: SymWrite, 3875 asm: x86.AMOVL, 3876 reg: regInfo{ 3877 inputs: []inputInfo{ 3878 {1, 255}, // AX CX DX BX SP BP SI DI 3879 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3880 }, 3881 }, 3882 }, 3883 { 3884 name: "MOVBloadidx1", 3885 auxType: auxSymOff, 3886 argLen: 3, 3887 commutative: true, 3888 symEffect: SymRead, 3889 asm: x86.AMOVBLZX, 3890 reg: regInfo{ 3891 inputs: []inputInfo{ 3892 {1, 255}, // AX CX DX BX SP BP SI DI 3893 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3894 }, 3895 outputs: []outputInfo{ 3896 {0, 239}, // AX CX DX BX BP SI DI 3897 }, 3898 }, 3899 }, 3900 { 3901 name: "MOVWloadidx1", 3902 auxType: auxSymOff, 3903 argLen: 3, 3904 commutative: true, 3905 symEffect: SymRead, 3906 asm: x86.AMOVWLZX, 3907 reg: regInfo{ 3908 inputs: []inputInfo{ 3909 {1, 255}, // AX CX DX BX SP BP SI DI 3910 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3911 }, 3912 outputs: []outputInfo{ 3913 {0, 239}, // AX CX DX BX BP SI DI 3914 }, 3915 }, 3916 }, 3917 { 3918 name: "MOVWloadidx2", 3919 auxType: auxSymOff, 3920 argLen: 3, 3921 symEffect: SymRead, 3922 asm: x86.AMOVWLZX, 3923 reg: regInfo{ 3924 inputs: []inputInfo{ 3925 {1, 255}, // AX CX DX BX SP BP SI DI 3926 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3927 }, 3928 outputs: []outputInfo{ 3929 {0, 239}, // AX CX DX BX BP SI DI 3930 }, 3931 }, 3932 }, 3933 { 3934 name: "MOVLloadidx1", 3935 auxType: auxSymOff, 3936 argLen: 3, 3937 commutative: true, 3938 symEffect: SymRead, 3939 asm: x86.AMOVL, 3940 reg: regInfo{ 3941 inputs: []inputInfo{ 3942 {1, 255}, // AX CX DX BX SP BP SI DI 3943 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3944 }, 3945 outputs: []outputInfo{ 3946 {0, 239}, // AX CX DX BX BP SI DI 3947 }, 3948 }, 3949 }, 3950 { 3951 name: "MOVLloadidx4", 3952 auxType: auxSymOff, 3953 argLen: 3, 3954 symEffect: SymRead, 3955 asm: x86.AMOVL, 3956 reg: regInfo{ 3957 inputs: []inputInfo{ 3958 {1, 255}, // AX CX DX BX SP BP SI DI 3959 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3960 }, 3961 outputs: []outputInfo{ 3962 {0, 239}, // AX CX DX BX BP SI DI 3963 }, 3964 }, 3965 }, 3966 { 3967 name: "MOVBstoreidx1", 3968 auxType: auxSymOff, 3969 argLen: 4, 3970 commutative: true, 3971 symEffect: SymWrite, 3972 asm: x86.AMOVB, 3973 reg: regInfo{ 3974 inputs: []inputInfo{ 3975 {1, 255}, // AX CX DX BX SP BP SI DI 3976 {2, 255}, // AX CX DX BX SP BP SI DI 3977 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3978 }, 3979 }, 3980 }, 3981 { 3982 name: "MOVWstoreidx1", 3983 auxType: auxSymOff, 3984 argLen: 4, 3985 commutative: true, 3986 symEffect: SymWrite, 3987 asm: x86.AMOVW, 3988 reg: regInfo{ 3989 inputs: []inputInfo{ 3990 {1, 255}, // AX CX DX BX SP BP SI DI 3991 {2, 255}, // AX CX DX BX SP BP SI DI 3992 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3993 }, 3994 }, 3995 }, 3996 { 3997 name: "MOVWstoreidx2", 3998 auxType: auxSymOff, 3999 argLen: 4, 4000 symEffect: SymWrite, 4001 asm: x86.AMOVW, 4002 reg: regInfo{ 4003 inputs: []inputInfo{ 4004 {1, 255}, // AX CX DX BX SP BP SI DI 4005 {2, 255}, // AX CX DX BX SP BP SI DI 4006 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4007 }, 4008 }, 4009 }, 4010 { 4011 name: "MOVLstoreidx1", 4012 auxType: auxSymOff, 4013 argLen: 4, 4014 commutative: true, 4015 symEffect: SymWrite, 4016 asm: x86.AMOVL, 4017 reg: regInfo{ 4018 inputs: []inputInfo{ 4019 {1, 255}, // AX CX DX BX SP BP SI DI 4020 {2, 255}, // AX CX DX BX SP BP SI DI 4021 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4022 }, 4023 }, 4024 }, 4025 { 4026 name: "MOVLstoreidx4", 4027 auxType: auxSymOff, 4028 argLen: 4, 4029 symEffect: SymWrite, 4030 asm: x86.AMOVL, 4031 reg: regInfo{ 4032 inputs: []inputInfo{ 4033 {1, 255}, // AX CX DX BX SP BP SI DI 4034 {2, 255}, // AX CX DX BX SP BP SI DI 4035 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4036 }, 4037 }, 4038 }, 4039 { 4040 name: "MOVBstoreconst", 4041 auxType: auxSymValAndOff, 4042 argLen: 2, 4043 faultOnNilArg0: true, 4044 symEffect: SymWrite, 4045 asm: x86.AMOVB, 4046 reg: regInfo{ 4047 inputs: []inputInfo{ 4048 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4049 }, 4050 }, 4051 }, 4052 { 4053 name: "MOVWstoreconst", 4054 auxType: auxSymValAndOff, 4055 argLen: 2, 4056 faultOnNilArg0: true, 4057 symEffect: SymWrite, 4058 asm: x86.AMOVW, 4059 reg: regInfo{ 4060 inputs: []inputInfo{ 4061 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4062 }, 4063 }, 4064 }, 4065 { 4066 name: "MOVLstoreconst", 4067 auxType: auxSymValAndOff, 4068 argLen: 2, 4069 faultOnNilArg0: true, 4070 symEffect: SymWrite, 4071 asm: x86.AMOVL, 4072 reg: regInfo{ 4073 inputs: []inputInfo{ 4074 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4075 }, 4076 }, 4077 }, 4078 { 4079 name: "MOVBstoreconstidx1", 4080 auxType: auxSymValAndOff, 4081 argLen: 3, 4082 symEffect: SymWrite, 4083 asm: x86.AMOVB, 4084 reg: regInfo{ 4085 inputs: []inputInfo{ 4086 {1, 255}, // AX CX DX BX SP BP SI DI 4087 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4088 }, 4089 }, 4090 }, 4091 { 4092 name: "MOVWstoreconstidx1", 4093 auxType: auxSymValAndOff, 4094 argLen: 3, 4095 symEffect: SymWrite, 4096 asm: x86.AMOVW, 4097 reg: regInfo{ 4098 inputs: []inputInfo{ 4099 {1, 255}, // AX CX DX BX SP BP SI DI 4100 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4101 }, 4102 }, 4103 }, 4104 { 4105 name: "MOVWstoreconstidx2", 4106 auxType: auxSymValAndOff, 4107 argLen: 3, 4108 symEffect: SymWrite, 4109 asm: x86.AMOVW, 4110 reg: regInfo{ 4111 inputs: []inputInfo{ 4112 {1, 255}, // AX CX DX BX SP BP SI DI 4113 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4114 }, 4115 }, 4116 }, 4117 { 4118 name: "MOVLstoreconstidx1", 4119 auxType: auxSymValAndOff, 4120 argLen: 3, 4121 symEffect: SymWrite, 4122 asm: x86.AMOVL, 4123 reg: regInfo{ 4124 inputs: []inputInfo{ 4125 {1, 255}, // AX CX DX BX SP BP SI DI 4126 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4127 }, 4128 }, 4129 }, 4130 { 4131 name: "MOVLstoreconstidx4", 4132 auxType: auxSymValAndOff, 4133 argLen: 3, 4134 symEffect: SymWrite, 4135 asm: x86.AMOVL, 4136 reg: regInfo{ 4137 inputs: []inputInfo{ 4138 {1, 255}, // AX CX DX BX SP BP SI DI 4139 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4140 }, 4141 }, 4142 }, 4143 { 4144 name: "DUFFZERO", 4145 auxType: auxInt64, 4146 argLen: 3, 4147 faultOnNilArg0: true, 4148 reg: regInfo{ 4149 inputs: []inputInfo{ 4150 {0, 128}, // DI 4151 {1, 1}, // AX 4152 }, 4153 clobbers: 130, // CX DI 4154 }, 4155 }, 4156 { 4157 name: "REPSTOSL", 4158 argLen: 4, 4159 faultOnNilArg0: true, 4160 reg: regInfo{ 4161 inputs: []inputInfo{ 4162 {0, 128}, // DI 4163 {1, 2}, // CX 4164 {2, 1}, // AX 4165 }, 4166 clobbers: 130, // CX DI 4167 }, 4168 }, 4169 { 4170 name: "CALLstatic", 4171 auxType: auxSymOff, 4172 argLen: 1, 4173 clobberFlags: true, 4174 call: true, 4175 symEffect: SymNone, 4176 reg: regInfo{ 4177 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4178 }, 4179 }, 4180 { 4181 name: "CALLclosure", 4182 auxType: auxInt64, 4183 argLen: 3, 4184 clobberFlags: true, 4185 call: true, 4186 reg: regInfo{ 4187 inputs: []inputInfo{ 4188 {1, 4}, // DX 4189 {0, 255}, // AX CX DX BX SP BP SI DI 4190 }, 4191 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4192 }, 4193 }, 4194 { 4195 name: "CALLinter", 4196 auxType: auxInt64, 4197 argLen: 2, 4198 clobberFlags: true, 4199 call: true, 4200 reg: regInfo{ 4201 inputs: []inputInfo{ 4202 {0, 239}, // AX CX DX BX BP SI DI 4203 }, 4204 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4205 }, 4206 }, 4207 { 4208 name: "DUFFCOPY", 4209 auxType: auxInt64, 4210 argLen: 3, 4211 clobberFlags: true, 4212 faultOnNilArg0: true, 4213 faultOnNilArg1: true, 4214 reg: regInfo{ 4215 inputs: []inputInfo{ 4216 {0, 128}, // DI 4217 {1, 64}, // SI 4218 }, 4219 clobbers: 194, // CX SI DI 4220 }, 4221 }, 4222 { 4223 name: "REPMOVSL", 4224 argLen: 4, 4225 faultOnNilArg0: true, 4226 faultOnNilArg1: true, 4227 reg: regInfo{ 4228 inputs: []inputInfo{ 4229 {0, 128}, // DI 4230 {1, 64}, // SI 4231 {2, 2}, // CX 4232 }, 4233 clobbers: 194, // CX SI DI 4234 }, 4235 }, 4236 { 4237 name: "InvertFlags", 4238 argLen: 1, 4239 reg: regInfo{}, 4240 }, 4241 { 4242 name: "LoweredGetG", 4243 argLen: 1, 4244 reg: regInfo{ 4245 outputs: []outputInfo{ 4246 {0, 239}, // AX CX DX BX BP SI DI 4247 }, 4248 }, 4249 }, 4250 { 4251 name: "LoweredGetClosurePtr", 4252 argLen: 0, 4253 reg: regInfo{ 4254 outputs: []outputInfo{ 4255 {0, 4}, // DX 4256 }, 4257 }, 4258 }, 4259 { 4260 name: "LoweredNilCheck", 4261 argLen: 2, 4262 clobberFlags: true, 4263 nilCheck: true, 4264 faultOnNilArg0: true, 4265 reg: regInfo{ 4266 inputs: []inputInfo{ 4267 {0, 255}, // AX CX DX BX SP BP SI DI 4268 }, 4269 }, 4270 }, 4271 { 4272 name: "MOVLconvert", 4273 argLen: 2, 4274 asm: x86.AMOVL, 4275 reg: regInfo{ 4276 inputs: []inputInfo{ 4277 {0, 239}, // AX CX DX BX BP SI DI 4278 }, 4279 outputs: []outputInfo{ 4280 {0, 239}, // AX CX DX BX BP SI DI 4281 }, 4282 }, 4283 }, 4284 { 4285 name: "FlagEQ", 4286 argLen: 0, 4287 reg: regInfo{}, 4288 }, 4289 { 4290 name: "FlagLT_ULT", 4291 argLen: 0, 4292 reg: regInfo{}, 4293 }, 4294 { 4295 name: "FlagLT_UGT", 4296 argLen: 0, 4297 reg: regInfo{}, 4298 }, 4299 { 4300 name: "FlagGT_UGT", 4301 argLen: 0, 4302 reg: regInfo{}, 4303 }, 4304 { 4305 name: "FlagGT_ULT", 4306 argLen: 0, 4307 reg: regInfo{}, 4308 }, 4309 { 4310 name: "FCHS", 4311 argLen: 1, 4312 reg: regInfo{ 4313 inputs: []inputInfo{ 4314 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4315 }, 4316 outputs: []outputInfo{ 4317 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4318 }, 4319 }, 4320 }, 4321 { 4322 name: "MOVSSconst1", 4323 auxType: auxFloat32, 4324 argLen: 0, 4325 reg: regInfo{ 4326 outputs: []outputInfo{ 4327 {0, 239}, // AX CX DX BX BP SI DI 4328 }, 4329 }, 4330 }, 4331 { 4332 name: "MOVSDconst1", 4333 auxType: auxFloat64, 4334 argLen: 0, 4335 reg: regInfo{ 4336 outputs: []outputInfo{ 4337 {0, 239}, // AX CX DX BX BP SI DI 4338 }, 4339 }, 4340 }, 4341 { 4342 name: "MOVSSconst2", 4343 argLen: 1, 4344 asm: x86.AMOVSS, 4345 reg: regInfo{ 4346 inputs: []inputInfo{ 4347 {0, 239}, // AX CX DX BX BP SI DI 4348 }, 4349 outputs: []outputInfo{ 4350 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4351 }, 4352 }, 4353 }, 4354 { 4355 name: "MOVSDconst2", 4356 argLen: 1, 4357 asm: x86.AMOVSD, 4358 reg: regInfo{ 4359 inputs: []inputInfo{ 4360 {0, 239}, // AX CX DX BX BP SI DI 4361 }, 4362 outputs: []outputInfo{ 4363 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4364 }, 4365 }, 4366 }, 4367 4368 { 4369 name: "ADDSS", 4370 argLen: 2, 4371 commutative: true, 4372 resultInArg0: true, 4373 asm: x86.AADDSS, 4374 reg: regInfo{ 4375 inputs: []inputInfo{ 4376 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4377 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4378 }, 4379 outputs: []outputInfo{ 4380 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4381 }, 4382 }, 4383 }, 4384 { 4385 name: "ADDSD", 4386 argLen: 2, 4387 commutative: true, 4388 resultInArg0: true, 4389 asm: x86.AADDSD, 4390 reg: regInfo{ 4391 inputs: []inputInfo{ 4392 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4393 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4394 }, 4395 outputs: []outputInfo{ 4396 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4397 }, 4398 }, 4399 }, 4400 { 4401 name: "SUBSS", 4402 argLen: 2, 4403 resultInArg0: true, 4404 asm: x86.ASUBSS, 4405 reg: regInfo{ 4406 inputs: []inputInfo{ 4407 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4408 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4409 }, 4410 outputs: []outputInfo{ 4411 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4412 }, 4413 }, 4414 }, 4415 { 4416 name: "SUBSD", 4417 argLen: 2, 4418 resultInArg0: true, 4419 asm: x86.ASUBSD, 4420 reg: regInfo{ 4421 inputs: []inputInfo{ 4422 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4423 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4424 }, 4425 outputs: []outputInfo{ 4426 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4427 }, 4428 }, 4429 }, 4430 { 4431 name: "MULSS", 4432 argLen: 2, 4433 commutative: true, 4434 resultInArg0: true, 4435 asm: x86.AMULSS, 4436 reg: regInfo{ 4437 inputs: []inputInfo{ 4438 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4439 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4440 }, 4441 outputs: []outputInfo{ 4442 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4443 }, 4444 }, 4445 }, 4446 { 4447 name: "MULSD", 4448 argLen: 2, 4449 commutative: true, 4450 resultInArg0: true, 4451 asm: x86.AMULSD, 4452 reg: regInfo{ 4453 inputs: []inputInfo{ 4454 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4455 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4456 }, 4457 outputs: []outputInfo{ 4458 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4459 }, 4460 }, 4461 }, 4462 { 4463 name: "DIVSS", 4464 argLen: 2, 4465 resultInArg0: true, 4466 asm: x86.ADIVSS, 4467 reg: regInfo{ 4468 inputs: []inputInfo{ 4469 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4470 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4471 }, 4472 outputs: []outputInfo{ 4473 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4474 }, 4475 }, 4476 }, 4477 { 4478 name: "DIVSD", 4479 argLen: 2, 4480 resultInArg0: true, 4481 asm: x86.ADIVSD, 4482 reg: regInfo{ 4483 inputs: []inputInfo{ 4484 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4485 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4486 }, 4487 outputs: []outputInfo{ 4488 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4489 }, 4490 }, 4491 }, 4492 { 4493 name: "MOVSSload", 4494 auxType: auxSymOff, 4495 argLen: 2, 4496 faultOnNilArg0: true, 4497 symEffect: SymRead, 4498 asm: x86.AMOVSS, 4499 reg: regInfo{ 4500 inputs: []inputInfo{ 4501 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4502 }, 4503 outputs: []outputInfo{ 4504 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4505 }, 4506 }, 4507 }, 4508 { 4509 name: "MOVSDload", 4510 auxType: auxSymOff, 4511 argLen: 2, 4512 faultOnNilArg0: true, 4513 symEffect: SymRead, 4514 asm: x86.AMOVSD, 4515 reg: regInfo{ 4516 inputs: []inputInfo{ 4517 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4518 }, 4519 outputs: []outputInfo{ 4520 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4521 }, 4522 }, 4523 }, 4524 { 4525 name: "MOVSSconst", 4526 auxType: auxFloat32, 4527 argLen: 0, 4528 rematerializeable: true, 4529 asm: x86.AMOVSS, 4530 reg: regInfo{ 4531 outputs: []outputInfo{ 4532 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4533 }, 4534 }, 4535 }, 4536 { 4537 name: "MOVSDconst", 4538 auxType: auxFloat64, 4539 argLen: 0, 4540 rematerializeable: true, 4541 asm: x86.AMOVSD, 4542 reg: regInfo{ 4543 outputs: []outputInfo{ 4544 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4545 }, 4546 }, 4547 }, 4548 { 4549 name: "MOVSSloadidx1", 4550 auxType: auxSymOff, 4551 argLen: 3, 4552 symEffect: SymRead, 4553 asm: x86.AMOVSS, 4554 reg: regInfo{ 4555 inputs: []inputInfo{ 4556 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4557 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4558 }, 4559 outputs: []outputInfo{ 4560 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4561 }, 4562 }, 4563 }, 4564 { 4565 name: "MOVSSloadidx4", 4566 auxType: auxSymOff, 4567 argLen: 3, 4568 symEffect: SymRead, 4569 asm: x86.AMOVSS, 4570 reg: regInfo{ 4571 inputs: []inputInfo{ 4572 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4573 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4574 }, 4575 outputs: []outputInfo{ 4576 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4577 }, 4578 }, 4579 }, 4580 { 4581 name: "MOVSDloadidx1", 4582 auxType: auxSymOff, 4583 argLen: 3, 4584 symEffect: SymRead, 4585 asm: x86.AMOVSD, 4586 reg: regInfo{ 4587 inputs: []inputInfo{ 4588 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4589 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4590 }, 4591 outputs: []outputInfo{ 4592 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4593 }, 4594 }, 4595 }, 4596 { 4597 name: "MOVSDloadidx8", 4598 auxType: auxSymOff, 4599 argLen: 3, 4600 symEffect: SymRead, 4601 asm: x86.AMOVSD, 4602 reg: regInfo{ 4603 inputs: []inputInfo{ 4604 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4605 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4606 }, 4607 outputs: []outputInfo{ 4608 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4609 }, 4610 }, 4611 }, 4612 { 4613 name: "MOVSSstore", 4614 auxType: auxSymOff, 4615 argLen: 3, 4616 faultOnNilArg0: true, 4617 symEffect: SymWrite, 4618 asm: x86.AMOVSS, 4619 reg: regInfo{ 4620 inputs: []inputInfo{ 4621 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4622 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4623 }, 4624 }, 4625 }, 4626 { 4627 name: "MOVSDstore", 4628 auxType: auxSymOff, 4629 argLen: 3, 4630 faultOnNilArg0: true, 4631 symEffect: SymWrite, 4632 asm: x86.AMOVSD, 4633 reg: regInfo{ 4634 inputs: []inputInfo{ 4635 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4636 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4637 }, 4638 }, 4639 }, 4640 { 4641 name: "MOVSSstoreidx1", 4642 auxType: auxSymOff, 4643 argLen: 4, 4644 symEffect: SymWrite, 4645 asm: x86.AMOVSS, 4646 reg: regInfo{ 4647 inputs: []inputInfo{ 4648 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4649 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4650 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4651 }, 4652 }, 4653 }, 4654 { 4655 name: "MOVSSstoreidx4", 4656 auxType: auxSymOff, 4657 argLen: 4, 4658 symEffect: SymWrite, 4659 asm: x86.AMOVSS, 4660 reg: regInfo{ 4661 inputs: []inputInfo{ 4662 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4663 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4664 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4665 }, 4666 }, 4667 }, 4668 { 4669 name: "MOVSDstoreidx1", 4670 auxType: auxSymOff, 4671 argLen: 4, 4672 symEffect: SymWrite, 4673 asm: x86.AMOVSD, 4674 reg: regInfo{ 4675 inputs: []inputInfo{ 4676 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4677 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4678 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4679 }, 4680 }, 4681 }, 4682 { 4683 name: "MOVSDstoreidx8", 4684 auxType: auxSymOff, 4685 argLen: 4, 4686 symEffect: SymWrite, 4687 asm: x86.AMOVSD, 4688 reg: regInfo{ 4689 inputs: []inputInfo{ 4690 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4691 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4692 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4693 }, 4694 }, 4695 }, 4696 { 4697 name: "ADDSSmem", 4698 auxType: auxSymOff, 4699 argLen: 3, 4700 resultInArg0: true, 4701 faultOnNilArg1: true, 4702 symEffect: SymRead, 4703 asm: x86.AADDSS, 4704 reg: regInfo{ 4705 inputs: []inputInfo{ 4706 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4707 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4708 }, 4709 outputs: []outputInfo{ 4710 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4711 }, 4712 }, 4713 }, 4714 { 4715 name: "ADDSDmem", 4716 auxType: auxSymOff, 4717 argLen: 3, 4718 resultInArg0: true, 4719 faultOnNilArg1: true, 4720 symEffect: SymRead, 4721 asm: x86.AADDSD, 4722 reg: regInfo{ 4723 inputs: []inputInfo{ 4724 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4725 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4726 }, 4727 outputs: []outputInfo{ 4728 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4729 }, 4730 }, 4731 }, 4732 { 4733 name: "SUBSSmem", 4734 auxType: auxSymOff, 4735 argLen: 3, 4736 resultInArg0: true, 4737 faultOnNilArg1: true, 4738 symEffect: SymRead, 4739 asm: x86.ASUBSS, 4740 reg: regInfo{ 4741 inputs: []inputInfo{ 4742 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4743 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4744 }, 4745 outputs: []outputInfo{ 4746 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4747 }, 4748 }, 4749 }, 4750 { 4751 name: "SUBSDmem", 4752 auxType: auxSymOff, 4753 argLen: 3, 4754 resultInArg0: true, 4755 faultOnNilArg1: true, 4756 symEffect: SymRead, 4757 asm: x86.ASUBSD, 4758 reg: regInfo{ 4759 inputs: []inputInfo{ 4760 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4761 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4762 }, 4763 outputs: []outputInfo{ 4764 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4765 }, 4766 }, 4767 }, 4768 { 4769 name: "MULSSmem", 4770 auxType: auxSymOff, 4771 argLen: 3, 4772 resultInArg0: true, 4773 faultOnNilArg1: true, 4774 symEffect: SymRead, 4775 asm: x86.AMULSS, 4776 reg: regInfo{ 4777 inputs: []inputInfo{ 4778 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4779 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4780 }, 4781 outputs: []outputInfo{ 4782 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4783 }, 4784 }, 4785 }, 4786 { 4787 name: "MULSDmem", 4788 auxType: auxSymOff, 4789 argLen: 3, 4790 resultInArg0: true, 4791 faultOnNilArg1: true, 4792 symEffect: SymRead, 4793 asm: x86.AMULSD, 4794 reg: regInfo{ 4795 inputs: []inputInfo{ 4796 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4797 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4798 }, 4799 outputs: []outputInfo{ 4800 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4801 }, 4802 }, 4803 }, 4804 { 4805 name: "ADDQ", 4806 argLen: 2, 4807 commutative: true, 4808 clobberFlags: true, 4809 asm: x86.AADDQ, 4810 reg: regInfo{ 4811 inputs: []inputInfo{ 4812 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4813 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4814 }, 4815 outputs: []outputInfo{ 4816 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4817 }, 4818 }, 4819 }, 4820 { 4821 name: "ADDL", 4822 argLen: 2, 4823 commutative: true, 4824 clobberFlags: true, 4825 asm: x86.AADDL, 4826 reg: regInfo{ 4827 inputs: []inputInfo{ 4828 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4829 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4830 }, 4831 outputs: []outputInfo{ 4832 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4833 }, 4834 }, 4835 }, 4836 { 4837 name: "ADDQconst", 4838 auxType: auxInt64, 4839 argLen: 1, 4840 clobberFlags: true, 4841 asm: x86.AADDQ, 4842 reg: regInfo{ 4843 inputs: []inputInfo{ 4844 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4845 }, 4846 outputs: []outputInfo{ 4847 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4848 }, 4849 }, 4850 }, 4851 { 4852 name: "ADDLconst", 4853 auxType: auxInt32, 4854 argLen: 1, 4855 clobberFlags: true, 4856 asm: x86.AADDL, 4857 reg: regInfo{ 4858 inputs: []inputInfo{ 4859 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4860 }, 4861 outputs: []outputInfo{ 4862 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4863 }, 4864 }, 4865 }, 4866 { 4867 name: "SUBQ", 4868 argLen: 2, 4869 resultInArg0: true, 4870 clobberFlags: true, 4871 asm: x86.ASUBQ, 4872 reg: regInfo{ 4873 inputs: []inputInfo{ 4874 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4875 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4876 }, 4877 outputs: []outputInfo{ 4878 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4879 }, 4880 }, 4881 }, 4882 { 4883 name: "SUBL", 4884 argLen: 2, 4885 resultInArg0: true, 4886 clobberFlags: true, 4887 asm: x86.ASUBL, 4888 reg: regInfo{ 4889 inputs: []inputInfo{ 4890 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4891 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4892 }, 4893 outputs: []outputInfo{ 4894 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4895 }, 4896 }, 4897 }, 4898 { 4899 name: "SUBQconst", 4900 auxType: auxInt64, 4901 argLen: 1, 4902 resultInArg0: true, 4903 clobberFlags: true, 4904 asm: x86.ASUBQ, 4905 reg: regInfo{ 4906 inputs: []inputInfo{ 4907 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4908 }, 4909 outputs: []outputInfo{ 4910 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4911 }, 4912 }, 4913 }, 4914 { 4915 name: "SUBLconst", 4916 auxType: auxInt32, 4917 argLen: 1, 4918 resultInArg0: true, 4919 clobberFlags: true, 4920 asm: x86.ASUBL, 4921 reg: regInfo{ 4922 inputs: []inputInfo{ 4923 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4924 }, 4925 outputs: []outputInfo{ 4926 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4927 }, 4928 }, 4929 }, 4930 { 4931 name: "MULQ", 4932 argLen: 2, 4933 commutative: true, 4934 resultInArg0: true, 4935 clobberFlags: true, 4936 asm: x86.AIMULQ, 4937 reg: regInfo{ 4938 inputs: []inputInfo{ 4939 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4940 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4941 }, 4942 outputs: []outputInfo{ 4943 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4944 }, 4945 }, 4946 }, 4947 { 4948 name: "MULL", 4949 argLen: 2, 4950 commutative: true, 4951 resultInArg0: true, 4952 clobberFlags: true, 4953 asm: x86.AIMULL, 4954 reg: regInfo{ 4955 inputs: []inputInfo{ 4956 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4957 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4958 }, 4959 outputs: []outputInfo{ 4960 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4961 }, 4962 }, 4963 }, 4964 { 4965 name: "MULQconst", 4966 auxType: auxInt64, 4967 argLen: 1, 4968 resultInArg0: true, 4969 clobberFlags: true, 4970 asm: x86.AIMULQ, 4971 reg: regInfo{ 4972 inputs: []inputInfo{ 4973 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4974 }, 4975 outputs: []outputInfo{ 4976 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4977 }, 4978 }, 4979 }, 4980 { 4981 name: "MULLconst", 4982 auxType: auxInt32, 4983 argLen: 1, 4984 resultInArg0: true, 4985 clobberFlags: true, 4986 asm: x86.AIMULL, 4987 reg: regInfo{ 4988 inputs: []inputInfo{ 4989 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4990 }, 4991 outputs: []outputInfo{ 4992 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4993 }, 4994 }, 4995 }, 4996 { 4997 name: "HMULQ", 4998 argLen: 2, 4999 commutative: true, 5000 clobberFlags: true, 5001 asm: x86.AIMULQ, 5002 reg: regInfo{ 5003 inputs: []inputInfo{ 5004 {0, 1}, // AX 5005 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5006 }, 5007 clobbers: 1, // AX 5008 outputs: []outputInfo{ 5009 {0, 4}, // DX 5010 }, 5011 }, 5012 }, 5013 { 5014 name: "HMULL", 5015 argLen: 2, 5016 commutative: true, 5017 clobberFlags: true, 5018 asm: x86.AIMULL, 5019 reg: regInfo{ 5020 inputs: []inputInfo{ 5021 {0, 1}, // AX 5022 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5023 }, 5024 clobbers: 1, // AX 5025 outputs: []outputInfo{ 5026 {0, 4}, // DX 5027 }, 5028 }, 5029 }, 5030 { 5031 name: "HMULQU", 5032 argLen: 2, 5033 commutative: true, 5034 clobberFlags: true, 5035 asm: x86.AMULQ, 5036 reg: regInfo{ 5037 inputs: []inputInfo{ 5038 {0, 1}, // AX 5039 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5040 }, 5041 clobbers: 1, // AX 5042 outputs: []outputInfo{ 5043 {0, 4}, // DX 5044 }, 5045 }, 5046 }, 5047 { 5048 name: "HMULLU", 5049 argLen: 2, 5050 commutative: true, 5051 clobberFlags: true, 5052 asm: x86.AMULL, 5053 reg: regInfo{ 5054 inputs: []inputInfo{ 5055 {0, 1}, // AX 5056 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5057 }, 5058 clobbers: 1, // AX 5059 outputs: []outputInfo{ 5060 {0, 4}, // DX 5061 }, 5062 }, 5063 }, 5064 { 5065 name: "AVGQU", 5066 argLen: 2, 5067 commutative: true, 5068 resultInArg0: true, 5069 clobberFlags: true, 5070 reg: regInfo{ 5071 inputs: []inputInfo{ 5072 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5073 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5074 }, 5075 outputs: []outputInfo{ 5076 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5077 }, 5078 }, 5079 }, 5080 { 5081 name: "DIVQ", 5082 argLen: 2, 5083 clobberFlags: true, 5084 asm: x86.AIDIVQ, 5085 reg: regInfo{ 5086 inputs: []inputInfo{ 5087 {0, 1}, // AX 5088 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5089 }, 5090 outputs: []outputInfo{ 5091 {0, 1}, // AX 5092 {1, 4}, // DX 5093 }, 5094 }, 5095 }, 5096 { 5097 name: "DIVL", 5098 argLen: 2, 5099 clobberFlags: true, 5100 asm: x86.AIDIVL, 5101 reg: regInfo{ 5102 inputs: []inputInfo{ 5103 {0, 1}, // AX 5104 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5105 }, 5106 outputs: []outputInfo{ 5107 {0, 1}, // AX 5108 {1, 4}, // DX 5109 }, 5110 }, 5111 }, 5112 { 5113 name: "DIVW", 5114 argLen: 2, 5115 clobberFlags: true, 5116 asm: x86.AIDIVW, 5117 reg: regInfo{ 5118 inputs: []inputInfo{ 5119 {0, 1}, // AX 5120 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5121 }, 5122 outputs: []outputInfo{ 5123 {0, 1}, // AX 5124 {1, 4}, // DX 5125 }, 5126 }, 5127 }, 5128 { 5129 name: "DIVQU", 5130 argLen: 2, 5131 clobberFlags: true, 5132 asm: x86.ADIVQ, 5133 reg: regInfo{ 5134 inputs: []inputInfo{ 5135 {0, 1}, // AX 5136 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5137 }, 5138 outputs: []outputInfo{ 5139 {0, 1}, // AX 5140 {1, 4}, // DX 5141 }, 5142 }, 5143 }, 5144 { 5145 name: "DIVLU", 5146 argLen: 2, 5147 clobberFlags: true, 5148 asm: x86.ADIVL, 5149 reg: regInfo{ 5150 inputs: []inputInfo{ 5151 {0, 1}, // AX 5152 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5153 }, 5154 outputs: []outputInfo{ 5155 {0, 1}, // AX 5156 {1, 4}, // DX 5157 }, 5158 }, 5159 }, 5160 { 5161 name: "DIVWU", 5162 argLen: 2, 5163 clobberFlags: true, 5164 asm: x86.ADIVW, 5165 reg: regInfo{ 5166 inputs: []inputInfo{ 5167 {0, 1}, // AX 5168 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5169 }, 5170 outputs: []outputInfo{ 5171 {0, 1}, // AX 5172 {1, 4}, // DX 5173 }, 5174 }, 5175 }, 5176 { 5177 name: "MULQU2", 5178 argLen: 2, 5179 commutative: true, 5180 clobberFlags: true, 5181 asm: x86.AMULQ, 5182 reg: regInfo{ 5183 inputs: []inputInfo{ 5184 {0, 1}, // AX 5185 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5186 }, 5187 outputs: []outputInfo{ 5188 {0, 4}, // DX 5189 {1, 1}, // AX 5190 }, 5191 }, 5192 }, 5193 { 5194 name: "DIVQU2", 5195 argLen: 3, 5196 clobberFlags: true, 5197 asm: x86.ADIVQ, 5198 reg: regInfo{ 5199 inputs: []inputInfo{ 5200 {0, 4}, // DX 5201 {1, 1}, // AX 5202 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5203 }, 5204 outputs: []outputInfo{ 5205 {0, 1}, // AX 5206 {1, 4}, // DX 5207 }, 5208 }, 5209 }, 5210 { 5211 name: "ANDQ", 5212 argLen: 2, 5213 commutative: true, 5214 resultInArg0: true, 5215 clobberFlags: true, 5216 asm: x86.AANDQ, 5217 reg: regInfo{ 5218 inputs: []inputInfo{ 5219 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5220 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5221 }, 5222 outputs: []outputInfo{ 5223 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5224 }, 5225 }, 5226 }, 5227 { 5228 name: "ANDL", 5229 argLen: 2, 5230 commutative: true, 5231 resultInArg0: true, 5232 clobberFlags: true, 5233 asm: x86.AANDL, 5234 reg: regInfo{ 5235 inputs: []inputInfo{ 5236 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5237 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5238 }, 5239 outputs: []outputInfo{ 5240 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5241 }, 5242 }, 5243 }, 5244 { 5245 name: "ANDQconst", 5246 auxType: auxInt64, 5247 argLen: 1, 5248 resultInArg0: true, 5249 clobberFlags: true, 5250 asm: x86.AANDQ, 5251 reg: regInfo{ 5252 inputs: []inputInfo{ 5253 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5254 }, 5255 outputs: []outputInfo{ 5256 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5257 }, 5258 }, 5259 }, 5260 { 5261 name: "ANDLconst", 5262 auxType: auxInt32, 5263 argLen: 1, 5264 resultInArg0: true, 5265 clobberFlags: true, 5266 asm: x86.AANDL, 5267 reg: regInfo{ 5268 inputs: []inputInfo{ 5269 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5270 }, 5271 outputs: []outputInfo{ 5272 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5273 }, 5274 }, 5275 }, 5276 { 5277 name: "ORQ", 5278 argLen: 2, 5279 commutative: true, 5280 resultInArg0: true, 5281 clobberFlags: true, 5282 asm: x86.AORQ, 5283 reg: regInfo{ 5284 inputs: []inputInfo{ 5285 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5286 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5287 }, 5288 outputs: []outputInfo{ 5289 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5290 }, 5291 }, 5292 }, 5293 { 5294 name: "ORL", 5295 argLen: 2, 5296 commutative: true, 5297 resultInArg0: true, 5298 clobberFlags: true, 5299 asm: x86.AORL, 5300 reg: regInfo{ 5301 inputs: []inputInfo{ 5302 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5303 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5304 }, 5305 outputs: []outputInfo{ 5306 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5307 }, 5308 }, 5309 }, 5310 { 5311 name: "ORQconst", 5312 auxType: auxInt64, 5313 argLen: 1, 5314 resultInArg0: true, 5315 clobberFlags: true, 5316 asm: x86.AORQ, 5317 reg: regInfo{ 5318 inputs: []inputInfo{ 5319 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5320 }, 5321 outputs: []outputInfo{ 5322 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5323 }, 5324 }, 5325 }, 5326 { 5327 name: "ORLconst", 5328 auxType: auxInt32, 5329 argLen: 1, 5330 resultInArg0: true, 5331 clobberFlags: true, 5332 asm: x86.AORL, 5333 reg: regInfo{ 5334 inputs: []inputInfo{ 5335 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5336 }, 5337 outputs: []outputInfo{ 5338 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5339 }, 5340 }, 5341 }, 5342 { 5343 name: "XORQ", 5344 argLen: 2, 5345 commutative: true, 5346 resultInArg0: true, 5347 clobberFlags: true, 5348 asm: x86.AXORQ, 5349 reg: regInfo{ 5350 inputs: []inputInfo{ 5351 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5352 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5353 }, 5354 outputs: []outputInfo{ 5355 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5356 }, 5357 }, 5358 }, 5359 { 5360 name: "XORL", 5361 argLen: 2, 5362 commutative: true, 5363 resultInArg0: true, 5364 clobberFlags: true, 5365 asm: x86.AXORL, 5366 reg: regInfo{ 5367 inputs: []inputInfo{ 5368 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5369 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5370 }, 5371 outputs: []outputInfo{ 5372 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5373 }, 5374 }, 5375 }, 5376 { 5377 name: "XORQconst", 5378 auxType: auxInt64, 5379 argLen: 1, 5380 resultInArg0: true, 5381 clobberFlags: true, 5382 asm: x86.AXORQ, 5383 reg: regInfo{ 5384 inputs: []inputInfo{ 5385 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5386 }, 5387 outputs: []outputInfo{ 5388 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5389 }, 5390 }, 5391 }, 5392 { 5393 name: "XORLconst", 5394 auxType: auxInt32, 5395 argLen: 1, 5396 resultInArg0: true, 5397 clobberFlags: true, 5398 asm: x86.AXORL, 5399 reg: regInfo{ 5400 inputs: []inputInfo{ 5401 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5402 }, 5403 outputs: []outputInfo{ 5404 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5405 }, 5406 }, 5407 }, 5408 { 5409 name: "CMPQ", 5410 argLen: 2, 5411 asm: x86.ACMPQ, 5412 reg: regInfo{ 5413 inputs: []inputInfo{ 5414 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5415 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5416 }, 5417 }, 5418 }, 5419 { 5420 name: "CMPL", 5421 argLen: 2, 5422 asm: x86.ACMPL, 5423 reg: regInfo{ 5424 inputs: []inputInfo{ 5425 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5426 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5427 }, 5428 }, 5429 }, 5430 { 5431 name: "CMPW", 5432 argLen: 2, 5433 asm: x86.ACMPW, 5434 reg: regInfo{ 5435 inputs: []inputInfo{ 5436 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5437 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5438 }, 5439 }, 5440 }, 5441 { 5442 name: "CMPB", 5443 argLen: 2, 5444 asm: x86.ACMPB, 5445 reg: regInfo{ 5446 inputs: []inputInfo{ 5447 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5448 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5449 }, 5450 }, 5451 }, 5452 { 5453 name: "CMPQconst", 5454 auxType: auxInt64, 5455 argLen: 1, 5456 asm: x86.ACMPQ, 5457 reg: regInfo{ 5458 inputs: []inputInfo{ 5459 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5460 }, 5461 }, 5462 }, 5463 { 5464 name: "CMPLconst", 5465 auxType: auxInt32, 5466 argLen: 1, 5467 asm: x86.ACMPL, 5468 reg: regInfo{ 5469 inputs: []inputInfo{ 5470 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5471 }, 5472 }, 5473 }, 5474 { 5475 name: "CMPWconst", 5476 auxType: auxInt16, 5477 argLen: 1, 5478 asm: x86.ACMPW, 5479 reg: regInfo{ 5480 inputs: []inputInfo{ 5481 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5482 }, 5483 }, 5484 }, 5485 { 5486 name: "CMPBconst", 5487 auxType: auxInt8, 5488 argLen: 1, 5489 asm: x86.ACMPB, 5490 reg: regInfo{ 5491 inputs: []inputInfo{ 5492 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5493 }, 5494 }, 5495 }, 5496 { 5497 name: "UCOMISS", 5498 argLen: 2, 5499 asm: x86.AUCOMISS, 5500 reg: regInfo{ 5501 inputs: []inputInfo{ 5502 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5503 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5504 }, 5505 }, 5506 }, 5507 { 5508 name: "UCOMISD", 5509 argLen: 2, 5510 asm: x86.AUCOMISD, 5511 reg: regInfo{ 5512 inputs: []inputInfo{ 5513 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5514 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5515 }, 5516 }, 5517 }, 5518 { 5519 name: "BTL", 5520 argLen: 2, 5521 asm: x86.ABTL, 5522 reg: regInfo{ 5523 inputs: []inputInfo{ 5524 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5525 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5526 }, 5527 }, 5528 }, 5529 { 5530 name: "BTQ", 5531 argLen: 2, 5532 asm: x86.ABTQ, 5533 reg: regInfo{ 5534 inputs: []inputInfo{ 5535 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5536 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5537 }, 5538 }, 5539 }, 5540 { 5541 name: "BTLconst", 5542 auxType: auxInt8, 5543 argLen: 1, 5544 asm: x86.ABTL, 5545 reg: regInfo{ 5546 inputs: []inputInfo{ 5547 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5548 }, 5549 }, 5550 }, 5551 { 5552 name: "BTQconst", 5553 auxType: auxInt8, 5554 argLen: 1, 5555 asm: x86.ABTQ, 5556 reg: regInfo{ 5557 inputs: []inputInfo{ 5558 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5559 }, 5560 }, 5561 }, 5562 { 5563 name: "TESTQ", 5564 argLen: 2, 5565 commutative: true, 5566 asm: x86.ATESTQ, 5567 reg: regInfo{ 5568 inputs: []inputInfo{ 5569 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5570 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5571 }, 5572 }, 5573 }, 5574 { 5575 name: "TESTL", 5576 argLen: 2, 5577 commutative: true, 5578 asm: x86.ATESTL, 5579 reg: regInfo{ 5580 inputs: []inputInfo{ 5581 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5582 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5583 }, 5584 }, 5585 }, 5586 { 5587 name: "TESTW", 5588 argLen: 2, 5589 commutative: true, 5590 asm: x86.ATESTW, 5591 reg: regInfo{ 5592 inputs: []inputInfo{ 5593 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5594 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5595 }, 5596 }, 5597 }, 5598 { 5599 name: "TESTB", 5600 argLen: 2, 5601 commutative: true, 5602 asm: x86.ATESTB, 5603 reg: regInfo{ 5604 inputs: []inputInfo{ 5605 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5606 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5607 }, 5608 }, 5609 }, 5610 { 5611 name: "TESTQconst", 5612 auxType: auxInt64, 5613 argLen: 1, 5614 asm: x86.ATESTQ, 5615 reg: regInfo{ 5616 inputs: []inputInfo{ 5617 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5618 }, 5619 }, 5620 }, 5621 { 5622 name: "TESTLconst", 5623 auxType: auxInt32, 5624 argLen: 1, 5625 asm: x86.ATESTL, 5626 reg: regInfo{ 5627 inputs: []inputInfo{ 5628 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5629 }, 5630 }, 5631 }, 5632 { 5633 name: "TESTWconst", 5634 auxType: auxInt16, 5635 argLen: 1, 5636 asm: x86.ATESTW, 5637 reg: regInfo{ 5638 inputs: []inputInfo{ 5639 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5640 }, 5641 }, 5642 }, 5643 { 5644 name: "TESTBconst", 5645 auxType: auxInt8, 5646 argLen: 1, 5647 asm: x86.ATESTB, 5648 reg: regInfo{ 5649 inputs: []inputInfo{ 5650 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5651 }, 5652 }, 5653 }, 5654 { 5655 name: "SHLQ", 5656 argLen: 2, 5657 resultInArg0: true, 5658 clobberFlags: true, 5659 asm: x86.ASHLQ, 5660 reg: regInfo{ 5661 inputs: []inputInfo{ 5662 {1, 2}, // CX 5663 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5664 }, 5665 outputs: []outputInfo{ 5666 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5667 }, 5668 }, 5669 }, 5670 { 5671 name: "SHLL", 5672 argLen: 2, 5673 resultInArg0: true, 5674 clobberFlags: true, 5675 asm: x86.ASHLL, 5676 reg: regInfo{ 5677 inputs: []inputInfo{ 5678 {1, 2}, // CX 5679 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5680 }, 5681 outputs: []outputInfo{ 5682 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5683 }, 5684 }, 5685 }, 5686 { 5687 name: "SHLQconst", 5688 auxType: auxInt8, 5689 argLen: 1, 5690 resultInArg0: true, 5691 clobberFlags: true, 5692 asm: x86.ASHLQ, 5693 reg: regInfo{ 5694 inputs: []inputInfo{ 5695 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5696 }, 5697 outputs: []outputInfo{ 5698 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5699 }, 5700 }, 5701 }, 5702 { 5703 name: "SHLLconst", 5704 auxType: auxInt8, 5705 argLen: 1, 5706 resultInArg0: true, 5707 clobberFlags: true, 5708 asm: x86.ASHLL, 5709 reg: regInfo{ 5710 inputs: []inputInfo{ 5711 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5712 }, 5713 outputs: []outputInfo{ 5714 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5715 }, 5716 }, 5717 }, 5718 { 5719 name: "SHRQ", 5720 argLen: 2, 5721 resultInArg0: true, 5722 clobberFlags: true, 5723 asm: x86.ASHRQ, 5724 reg: regInfo{ 5725 inputs: []inputInfo{ 5726 {1, 2}, // CX 5727 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5728 }, 5729 outputs: []outputInfo{ 5730 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5731 }, 5732 }, 5733 }, 5734 { 5735 name: "SHRL", 5736 argLen: 2, 5737 resultInArg0: true, 5738 clobberFlags: true, 5739 asm: x86.ASHRL, 5740 reg: regInfo{ 5741 inputs: []inputInfo{ 5742 {1, 2}, // CX 5743 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5744 }, 5745 outputs: []outputInfo{ 5746 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5747 }, 5748 }, 5749 }, 5750 { 5751 name: "SHRW", 5752 argLen: 2, 5753 resultInArg0: true, 5754 clobberFlags: true, 5755 asm: x86.ASHRW, 5756 reg: regInfo{ 5757 inputs: []inputInfo{ 5758 {1, 2}, // CX 5759 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5760 }, 5761 outputs: []outputInfo{ 5762 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5763 }, 5764 }, 5765 }, 5766 { 5767 name: "SHRB", 5768 argLen: 2, 5769 resultInArg0: true, 5770 clobberFlags: true, 5771 asm: x86.ASHRB, 5772 reg: regInfo{ 5773 inputs: []inputInfo{ 5774 {1, 2}, // CX 5775 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5776 }, 5777 outputs: []outputInfo{ 5778 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5779 }, 5780 }, 5781 }, 5782 { 5783 name: "SHRQconst", 5784 auxType: auxInt8, 5785 argLen: 1, 5786 resultInArg0: true, 5787 clobberFlags: true, 5788 asm: x86.ASHRQ, 5789 reg: regInfo{ 5790 inputs: []inputInfo{ 5791 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5792 }, 5793 outputs: []outputInfo{ 5794 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5795 }, 5796 }, 5797 }, 5798 { 5799 name: "SHRLconst", 5800 auxType: auxInt8, 5801 argLen: 1, 5802 resultInArg0: true, 5803 clobberFlags: true, 5804 asm: x86.ASHRL, 5805 reg: regInfo{ 5806 inputs: []inputInfo{ 5807 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5808 }, 5809 outputs: []outputInfo{ 5810 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5811 }, 5812 }, 5813 }, 5814 { 5815 name: "SHRWconst", 5816 auxType: auxInt8, 5817 argLen: 1, 5818 resultInArg0: true, 5819 clobberFlags: true, 5820 asm: x86.ASHRW, 5821 reg: regInfo{ 5822 inputs: []inputInfo{ 5823 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5824 }, 5825 outputs: []outputInfo{ 5826 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5827 }, 5828 }, 5829 }, 5830 { 5831 name: "SHRBconst", 5832 auxType: auxInt8, 5833 argLen: 1, 5834 resultInArg0: true, 5835 clobberFlags: true, 5836 asm: x86.ASHRB, 5837 reg: regInfo{ 5838 inputs: []inputInfo{ 5839 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5840 }, 5841 outputs: []outputInfo{ 5842 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5843 }, 5844 }, 5845 }, 5846 { 5847 name: "SARQ", 5848 argLen: 2, 5849 resultInArg0: true, 5850 clobberFlags: true, 5851 asm: x86.ASARQ, 5852 reg: regInfo{ 5853 inputs: []inputInfo{ 5854 {1, 2}, // CX 5855 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5856 }, 5857 outputs: []outputInfo{ 5858 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5859 }, 5860 }, 5861 }, 5862 { 5863 name: "SARL", 5864 argLen: 2, 5865 resultInArg0: true, 5866 clobberFlags: true, 5867 asm: x86.ASARL, 5868 reg: regInfo{ 5869 inputs: []inputInfo{ 5870 {1, 2}, // CX 5871 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5872 }, 5873 outputs: []outputInfo{ 5874 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5875 }, 5876 }, 5877 }, 5878 { 5879 name: "SARW", 5880 argLen: 2, 5881 resultInArg0: true, 5882 clobberFlags: true, 5883 asm: x86.ASARW, 5884 reg: regInfo{ 5885 inputs: []inputInfo{ 5886 {1, 2}, // CX 5887 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5888 }, 5889 outputs: []outputInfo{ 5890 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5891 }, 5892 }, 5893 }, 5894 { 5895 name: "SARB", 5896 argLen: 2, 5897 resultInArg0: true, 5898 clobberFlags: true, 5899 asm: x86.ASARB, 5900 reg: regInfo{ 5901 inputs: []inputInfo{ 5902 {1, 2}, // CX 5903 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5904 }, 5905 outputs: []outputInfo{ 5906 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5907 }, 5908 }, 5909 }, 5910 { 5911 name: "SARQconst", 5912 auxType: auxInt8, 5913 argLen: 1, 5914 resultInArg0: true, 5915 clobberFlags: true, 5916 asm: x86.ASARQ, 5917 reg: regInfo{ 5918 inputs: []inputInfo{ 5919 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5920 }, 5921 outputs: []outputInfo{ 5922 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5923 }, 5924 }, 5925 }, 5926 { 5927 name: "SARLconst", 5928 auxType: auxInt8, 5929 argLen: 1, 5930 resultInArg0: true, 5931 clobberFlags: true, 5932 asm: x86.ASARL, 5933 reg: regInfo{ 5934 inputs: []inputInfo{ 5935 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5936 }, 5937 outputs: []outputInfo{ 5938 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5939 }, 5940 }, 5941 }, 5942 { 5943 name: "SARWconst", 5944 auxType: auxInt8, 5945 argLen: 1, 5946 resultInArg0: true, 5947 clobberFlags: true, 5948 asm: x86.ASARW, 5949 reg: regInfo{ 5950 inputs: []inputInfo{ 5951 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5952 }, 5953 outputs: []outputInfo{ 5954 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5955 }, 5956 }, 5957 }, 5958 { 5959 name: "SARBconst", 5960 auxType: auxInt8, 5961 argLen: 1, 5962 resultInArg0: true, 5963 clobberFlags: true, 5964 asm: x86.ASARB, 5965 reg: regInfo{ 5966 inputs: []inputInfo{ 5967 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5968 }, 5969 outputs: []outputInfo{ 5970 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5971 }, 5972 }, 5973 }, 5974 { 5975 name: "ROLQ", 5976 argLen: 2, 5977 resultInArg0: true, 5978 clobberFlags: true, 5979 asm: x86.AROLQ, 5980 reg: regInfo{ 5981 inputs: []inputInfo{ 5982 {1, 2}, // CX 5983 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5984 }, 5985 outputs: []outputInfo{ 5986 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5987 }, 5988 }, 5989 }, 5990 { 5991 name: "ROLL", 5992 argLen: 2, 5993 resultInArg0: true, 5994 clobberFlags: true, 5995 asm: x86.AROLL, 5996 reg: regInfo{ 5997 inputs: []inputInfo{ 5998 {1, 2}, // CX 5999 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6000 }, 6001 outputs: []outputInfo{ 6002 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6003 }, 6004 }, 6005 }, 6006 { 6007 name: "ROLW", 6008 argLen: 2, 6009 resultInArg0: true, 6010 clobberFlags: true, 6011 asm: x86.AROLW, 6012 reg: regInfo{ 6013 inputs: []inputInfo{ 6014 {1, 2}, // CX 6015 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6016 }, 6017 outputs: []outputInfo{ 6018 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6019 }, 6020 }, 6021 }, 6022 { 6023 name: "ROLB", 6024 argLen: 2, 6025 resultInArg0: true, 6026 clobberFlags: true, 6027 asm: x86.AROLB, 6028 reg: regInfo{ 6029 inputs: []inputInfo{ 6030 {1, 2}, // CX 6031 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6032 }, 6033 outputs: []outputInfo{ 6034 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6035 }, 6036 }, 6037 }, 6038 { 6039 name: "RORQ", 6040 argLen: 2, 6041 resultInArg0: true, 6042 clobberFlags: true, 6043 asm: x86.ARORQ, 6044 reg: regInfo{ 6045 inputs: []inputInfo{ 6046 {1, 2}, // CX 6047 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6048 }, 6049 outputs: []outputInfo{ 6050 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6051 }, 6052 }, 6053 }, 6054 { 6055 name: "RORL", 6056 argLen: 2, 6057 resultInArg0: true, 6058 clobberFlags: true, 6059 asm: x86.ARORL, 6060 reg: regInfo{ 6061 inputs: []inputInfo{ 6062 {1, 2}, // CX 6063 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6064 }, 6065 outputs: []outputInfo{ 6066 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6067 }, 6068 }, 6069 }, 6070 { 6071 name: "RORW", 6072 argLen: 2, 6073 resultInArg0: true, 6074 clobberFlags: true, 6075 asm: x86.ARORW, 6076 reg: regInfo{ 6077 inputs: []inputInfo{ 6078 {1, 2}, // CX 6079 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6080 }, 6081 outputs: []outputInfo{ 6082 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6083 }, 6084 }, 6085 }, 6086 { 6087 name: "RORB", 6088 argLen: 2, 6089 resultInArg0: true, 6090 clobberFlags: true, 6091 asm: x86.ARORB, 6092 reg: regInfo{ 6093 inputs: []inputInfo{ 6094 {1, 2}, // CX 6095 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6096 }, 6097 outputs: []outputInfo{ 6098 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6099 }, 6100 }, 6101 }, 6102 { 6103 name: "ROLQconst", 6104 auxType: auxInt8, 6105 argLen: 1, 6106 resultInArg0: true, 6107 clobberFlags: true, 6108 asm: x86.AROLQ, 6109 reg: regInfo{ 6110 inputs: []inputInfo{ 6111 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6112 }, 6113 outputs: []outputInfo{ 6114 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6115 }, 6116 }, 6117 }, 6118 { 6119 name: "ROLLconst", 6120 auxType: auxInt8, 6121 argLen: 1, 6122 resultInArg0: true, 6123 clobberFlags: true, 6124 asm: x86.AROLL, 6125 reg: regInfo{ 6126 inputs: []inputInfo{ 6127 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6128 }, 6129 outputs: []outputInfo{ 6130 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6131 }, 6132 }, 6133 }, 6134 { 6135 name: "ROLWconst", 6136 auxType: auxInt8, 6137 argLen: 1, 6138 resultInArg0: true, 6139 clobberFlags: true, 6140 asm: x86.AROLW, 6141 reg: regInfo{ 6142 inputs: []inputInfo{ 6143 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6144 }, 6145 outputs: []outputInfo{ 6146 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6147 }, 6148 }, 6149 }, 6150 { 6151 name: "ROLBconst", 6152 auxType: auxInt8, 6153 argLen: 1, 6154 resultInArg0: true, 6155 clobberFlags: true, 6156 asm: x86.AROLB, 6157 reg: regInfo{ 6158 inputs: []inputInfo{ 6159 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6160 }, 6161 outputs: []outputInfo{ 6162 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6163 }, 6164 }, 6165 }, 6166 { 6167 name: "ADDLmem", 6168 auxType: auxSymOff, 6169 argLen: 3, 6170 resultInArg0: true, 6171 clobberFlags: true, 6172 faultOnNilArg1: true, 6173 symEffect: SymRead, 6174 asm: x86.AADDL, 6175 reg: regInfo{ 6176 inputs: []inputInfo{ 6177 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6178 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6179 }, 6180 outputs: []outputInfo{ 6181 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6182 }, 6183 }, 6184 }, 6185 { 6186 name: "ADDQmem", 6187 auxType: auxSymOff, 6188 argLen: 3, 6189 resultInArg0: true, 6190 clobberFlags: true, 6191 faultOnNilArg1: true, 6192 symEffect: SymRead, 6193 asm: x86.AADDQ, 6194 reg: regInfo{ 6195 inputs: []inputInfo{ 6196 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6197 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6198 }, 6199 outputs: []outputInfo{ 6200 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6201 }, 6202 }, 6203 }, 6204 { 6205 name: "SUBQmem", 6206 auxType: auxSymOff, 6207 argLen: 3, 6208 resultInArg0: true, 6209 clobberFlags: true, 6210 faultOnNilArg1: true, 6211 symEffect: SymRead, 6212 asm: x86.ASUBQ, 6213 reg: regInfo{ 6214 inputs: []inputInfo{ 6215 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6216 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6217 }, 6218 outputs: []outputInfo{ 6219 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6220 }, 6221 }, 6222 }, 6223 { 6224 name: "SUBLmem", 6225 auxType: auxSymOff, 6226 argLen: 3, 6227 resultInArg0: true, 6228 clobberFlags: true, 6229 faultOnNilArg1: true, 6230 symEffect: SymRead, 6231 asm: x86.ASUBL, 6232 reg: regInfo{ 6233 inputs: []inputInfo{ 6234 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6235 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6236 }, 6237 outputs: []outputInfo{ 6238 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6239 }, 6240 }, 6241 }, 6242 { 6243 name: "ANDLmem", 6244 auxType: auxSymOff, 6245 argLen: 3, 6246 resultInArg0: true, 6247 clobberFlags: true, 6248 faultOnNilArg1: true, 6249 symEffect: SymRead, 6250 asm: x86.AANDL, 6251 reg: regInfo{ 6252 inputs: []inputInfo{ 6253 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6254 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6255 }, 6256 outputs: []outputInfo{ 6257 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6258 }, 6259 }, 6260 }, 6261 { 6262 name: "ANDQmem", 6263 auxType: auxSymOff, 6264 argLen: 3, 6265 resultInArg0: true, 6266 clobberFlags: true, 6267 faultOnNilArg1: true, 6268 symEffect: SymRead, 6269 asm: x86.AANDQ, 6270 reg: regInfo{ 6271 inputs: []inputInfo{ 6272 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6273 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6274 }, 6275 outputs: []outputInfo{ 6276 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6277 }, 6278 }, 6279 }, 6280 { 6281 name: "ORQmem", 6282 auxType: auxSymOff, 6283 argLen: 3, 6284 resultInArg0: true, 6285 clobberFlags: true, 6286 faultOnNilArg1: true, 6287 symEffect: SymRead, 6288 asm: x86.AORQ, 6289 reg: regInfo{ 6290 inputs: []inputInfo{ 6291 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6292 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6293 }, 6294 outputs: []outputInfo{ 6295 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6296 }, 6297 }, 6298 }, 6299 { 6300 name: "ORLmem", 6301 auxType: auxSymOff, 6302 argLen: 3, 6303 resultInArg0: true, 6304 clobberFlags: true, 6305 faultOnNilArg1: true, 6306 symEffect: SymRead, 6307 asm: x86.AORL, 6308 reg: regInfo{ 6309 inputs: []inputInfo{ 6310 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6311 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6312 }, 6313 outputs: []outputInfo{ 6314 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6315 }, 6316 }, 6317 }, 6318 { 6319 name: "XORQmem", 6320 auxType: auxSymOff, 6321 argLen: 3, 6322 resultInArg0: true, 6323 clobberFlags: true, 6324 faultOnNilArg1: true, 6325 symEffect: SymRead, 6326 asm: x86.AXORQ, 6327 reg: regInfo{ 6328 inputs: []inputInfo{ 6329 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6330 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6331 }, 6332 outputs: []outputInfo{ 6333 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6334 }, 6335 }, 6336 }, 6337 { 6338 name: "XORLmem", 6339 auxType: auxSymOff, 6340 argLen: 3, 6341 resultInArg0: true, 6342 clobberFlags: true, 6343 faultOnNilArg1: true, 6344 symEffect: SymRead, 6345 asm: x86.AXORL, 6346 reg: regInfo{ 6347 inputs: []inputInfo{ 6348 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6349 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6350 }, 6351 outputs: []outputInfo{ 6352 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6353 }, 6354 }, 6355 }, 6356 { 6357 name: "NEGQ", 6358 argLen: 1, 6359 resultInArg0: true, 6360 clobberFlags: true, 6361 asm: x86.ANEGQ, 6362 reg: regInfo{ 6363 inputs: []inputInfo{ 6364 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6365 }, 6366 outputs: []outputInfo{ 6367 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6368 }, 6369 }, 6370 }, 6371 { 6372 name: "NEGL", 6373 argLen: 1, 6374 resultInArg0: true, 6375 clobberFlags: true, 6376 asm: x86.ANEGL, 6377 reg: regInfo{ 6378 inputs: []inputInfo{ 6379 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6380 }, 6381 outputs: []outputInfo{ 6382 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6383 }, 6384 }, 6385 }, 6386 { 6387 name: "NOTQ", 6388 argLen: 1, 6389 resultInArg0: true, 6390 clobberFlags: true, 6391 asm: x86.ANOTQ, 6392 reg: regInfo{ 6393 inputs: []inputInfo{ 6394 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6395 }, 6396 outputs: []outputInfo{ 6397 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6398 }, 6399 }, 6400 }, 6401 { 6402 name: "NOTL", 6403 argLen: 1, 6404 resultInArg0: true, 6405 clobberFlags: true, 6406 asm: x86.ANOTL, 6407 reg: regInfo{ 6408 inputs: []inputInfo{ 6409 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6410 }, 6411 outputs: []outputInfo{ 6412 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6413 }, 6414 }, 6415 }, 6416 { 6417 name: "BSFQ", 6418 argLen: 1, 6419 asm: x86.ABSFQ, 6420 reg: regInfo{ 6421 inputs: []inputInfo{ 6422 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6423 }, 6424 outputs: []outputInfo{ 6425 {1, 0}, 6426 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6427 }, 6428 }, 6429 }, 6430 { 6431 name: "BSFL", 6432 argLen: 1, 6433 asm: x86.ABSFL, 6434 reg: regInfo{ 6435 inputs: []inputInfo{ 6436 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6437 }, 6438 outputs: []outputInfo{ 6439 {1, 0}, 6440 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6441 }, 6442 }, 6443 }, 6444 { 6445 name: "BSRQ", 6446 argLen: 1, 6447 asm: x86.ABSRQ, 6448 reg: regInfo{ 6449 inputs: []inputInfo{ 6450 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6451 }, 6452 outputs: []outputInfo{ 6453 {1, 0}, 6454 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6455 }, 6456 }, 6457 }, 6458 { 6459 name: "BSRL", 6460 argLen: 1, 6461 asm: x86.ABSRL, 6462 reg: regInfo{ 6463 inputs: []inputInfo{ 6464 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6465 }, 6466 outputs: []outputInfo{ 6467 {1, 0}, 6468 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6469 }, 6470 }, 6471 }, 6472 { 6473 name: "CMOVQEQ", 6474 argLen: 3, 6475 resultInArg0: true, 6476 asm: x86.ACMOVQEQ, 6477 reg: regInfo{ 6478 inputs: []inputInfo{ 6479 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6480 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6481 }, 6482 outputs: []outputInfo{ 6483 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6484 }, 6485 }, 6486 }, 6487 { 6488 name: "CMOVLEQ", 6489 argLen: 3, 6490 resultInArg0: true, 6491 asm: x86.ACMOVLEQ, 6492 reg: regInfo{ 6493 inputs: []inputInfo{ 6494 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6495 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6496 }, 6497 outputs: []outputInfo{ 6498 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6499 }, 6500 }, 6501 }, 6502 { 6503 name: "BSWAPQ", 6504 argLen: 1, 6505 resultInArg0: true, 6506 clobberFlags: true, 6507 asm: x86.ABSWAPQ, 6508 reg: regInfo{ 6509 inputs: []inputInfo{ 6510 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6511 }, 6512 outputs: []outputInfo{ 6513 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6514 }, 6515 }, 6516 }, 6517 { 6518 name: "BSWAPL", 6519 argLen: 1, 6520 resultInArg0: true, 6521 clobberFlags: true, 6522 asm: x86.ABSWAPL, 6523 reg: regInfo{ 6524 inputs: []inputInfo{ 6525 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6526 }, 6527 outputs: []outputInfo{ 6528 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6529 }, 6530 }, 6531 }, 6532 { 6533 name: "POPCNTQ", 6534 argLen: 1, 6535 clobberFlags: true, 6536 asm: x86.APOPCNTQ, 6537 reg: regInfo{ 6538 inputs: []inputInfo{ 6539 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6540 }, 6541 outputs: []outputInfo{ 6542 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6543 }, 6544 }, 6545 }, 6546 { 6547 name: "POPCNTL", 6548 argLen: 1, 6549 clobberFlags: true, 6550 asm: x86.APOPCNTL, 6551 reg: regInfo{ 6552 inputs: []inputInfo{ 6553 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6554 }, 6555 outputs: []outputInfo{ 6556 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6557 }, 6558 }, 6559 }, 6560 { 6561 name: "SQRTSD", 6562 argLen: 1, 6563 asm: x86.ASQRTSD, 6564 reg: regInfo{ 6565 inputs: []inputInfo{ 6566 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6567 }, 6568 outputs: []outputInfo{ 6569 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6570 }, 6571 }, 6572 }, 6573 { 6574 name: "SBBQcarrymask", 6575 argLen: 1, 6576 asm: x86.ASBBQ, 6577 reg: regInfo{ 6578 outputs: []outputInfo{ 6579 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6580 }, 6581 }, 6582 }, 6583 { 6584 name: "SBBLcarrymask", 6585 argLen: 1, 6586 asm: x86.ASBBL, 6587 reg: regInfo{ 6588 outputs: []outputInfo{ 6589 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6590 }, 6591 }, 6592 }, 6593 { 6594 name: "SETEQ", 6595 argLen: 1, 6596 asm: x86.ASETEQ, 6597 reg: regInfo{ 6598 outputs: []outputInfo{ 6599 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6600 }, 6601 }, 6602 }, 6603 { 6604 name: "SETNE", 6605 argLen: 1, 6606 asm: x86.ASETNE, 6607 reg: regInfo{ 6608 outputs: []outputInfo{ 6609 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6610 }, 6611 }, 6612 }, 6613 { 6614 name: "SETL", 6615 argLen: 1, 6616 asm: x86.ASETLT, 6617 reg: regInfo{ 6618 outputs: []outputInfo{ 6619 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6620 }, 6621 }, 6622 }, 6623 { 6624 name: "SETLE", 6625 argLen: 1, 6626 asm: x86.ASETLE, 6627 reg: regInfo{ 6628 outputs: []outputInfo{ 6629 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6630 }, 6631 }, 6632 }, 6633 { 6634 name: "SETG", 6635 argLen: 1, 6636 asm: x86.ASETGT, 6637 reg: regInfo{ 6638 outputs: []outputInfo{ 6639 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6640 }, 6641 }, 6642 }, 6643 { 6644 name: "SETGE", 6645 argLen: 1, 6646 asm: x86.ASETGE, 6647 reg: regInfo{ 6648 outputs: []outputInfo{ 6649 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6650 }, 6651 }, 6652 }, 6653 { 6654 name: "SETB", 6655 argLen: 1, 6656 asm: x86.ASETCS, 6657 reg: regInfo{ 6658 outputs: []outputInfo{ 6659 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6660 }, 6661 }, 6662 }, 6663 { 6664 name: "SETBE", 6665 argLen: 1, 6666 asm: x86.ASETLS, 6667 reg: regInfo{ 6668 outputs: []outputInfo{ 6669 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6670 }, 6671 }, 6672 }, 6673 { 6674 name: "SETA", 6675 argLen: 1, 6676 asm: x86.ASETHI, 6677 reg: regInfo{ 6678 outputs: []outputInfo{ 6679 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6680 }, 6681 }, 6682 }, 6683 { 6684 name: "SETAE", 6685 argLen: 1, 6686 asm: x86.ASETCC, 6687 reg: regInfo{ 6688 outputs: []outputInfo{ 6689 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6690 }, 6691 }, 6692 }, 6693 { 6694 name: "SETEQF", 6695 argLen: 1, 6696 clobberFlags: true, 6697 asm: x86.ASETEQ, 6698 reg: regInfo{ 6699 clobbers: 1, // AX 6700 outputs: []outputInfo{ 6701 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6702 }, 6703 }, 6704 }, 6705 { 6706 name: "SETNEF", 6707 argLen: 1, 6708 clobberFlags: true, 6709 asm: x86.ASETNE, 6710 reg: regInfo{ 6711 clobbers: 1, // AX 6712 outputs: []outputInfo{ 6713 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6714 }, 6715 }, 6716 }, 6717 { 6718 name: "SETORD", 6719 argLen: 1, 6720 asm: x86.ASETPC, 6721 reg: regInfo{ 6722 outputs: []outputInfo{ 6723 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6724 }, 6725 }, 6726 }, 6727 { 6728 name: "SETNAN", 6729 argLen: 1, 6730 asm: x86.ASETPS, 6731 reg: regInfo{ 6732 outputs: []outputInfo{ 6733 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6734 }, 6735 }, 6736 }, 6737 { 6738 name: "SETGF", 6739 argLen: 1, 6740 asm: x86.ASETHI, 6741 reg: regInfo{ 6742 outputs: []outputInfo{ 6743 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6744 }, 6745 }, 6746 }, 6747 { 6748 name: "SETGEF", 6749 argLen: 1, 6750 asm: x86.ASETCC, 6751 reg: regInfo{ 6752 outputs: []outputInfo{ 6753 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6754 }, 6755 }, 6756 }, 6757 { 6758 name: "MOVBQSX", 6759 argLen: 1, 6760 asm: x86.AMOVBQSX, 6761 reg: regInfo{ 6762 inputs: []inputInfo{ 6763 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6764 }, 6765 outputs: []outputInfo{ 6766 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6767 }, 6768 }, 6769 }, 6770 { 6771 name: "MOVBQZX", 6772 argLen: 1, 6773 asm: x86.AMOVBLZX, 6774 reg: regInfo{ 6775 inputs: []inputInfo{ 6776 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6777 }, 6778 outputs: []outputInfo{ 6779 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6780 }, 6781 }, 6782 }, 6783 { 6784 name: "MOVWQSX", 6785 argLen: 1, 6786 asm: x86.AMOVWQSX, 6787 reg: regInfo{ 6788 inputs: []inputInfo{ 6789 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6790 }, 6791 outputs: []outputInfo{ 6792 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6793 }, 6794 }, 6795 }, 6796 { 6797 name: "MOVWQZX", 6798 argLen: 1, 6799 asm: x86.AMOVWLZX, 6800 reg: regInfo{ 6801 inputs: []inputInfo{ 6802 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6803 }, 6804 outputs: []outputInfo{ 6805 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6806 }, 6807 }, 6808 }, 6809 { 6810 name: "MOVLQSX", 6811 argLen: 1, 6812 asm: x86.AMOVLQSX, 6813 reg: regInfo{ 6814 inputs: []inputInfo{ 6815 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6816 }, 6817 outputs: []outputInfo{ 6818 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6819 }, 6820 }, 6821 }, 6822 { 6823 name: "MOVLQZX", 6824 argLen: 1, 6825 asm: x86.AMOVL, 6826 reg: regInfo{ 6827 inputs: []inputInfo{ 6828 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6829 }, 6830 outputs: []outputInfo{ 6831 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6832 }, 6833 }, 6834 }, 6835 { 6836 name: "MOVLconst", 6837 auxType: auxInt32, 6838 argLen: 0, 6839 rematerializeable: true, 6840 asm: x86.AMOVL, 6841 reg: regInfo{ 6842 outputs: []outputInfo{ 6843 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6844 }, 6845 }, 6846 }, 6847 { 6848 name: "MOVQconst", 6849 auxType: auxInt64, 6850 argLen: 0, 6851 rematerializeable: true, 6852 asm: x86.AMOVQ, 6853 reg: regInfo{ 6854 outputs: []outputInfo{ 6855 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6856 }, 6857 }, 6858 }, 6859 { 6860 name: "CVTTSD2SL", 6861 argLen: 1, 6862 asm: x86.ACVTTSD2SL, 6863 reg: regInfo{ 6864 inputs: []inputInfo{ 6865 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6866 }, 6867 outputs: []outputInfo{ 6868 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6869 }, 6870 }, 6871 }, 6872 { 6873 name: "CVTTSD2SQ", 6874 argLen: 1, 6875 asm: x86.ACVTTSD2SQ, 6876 reg: regInfo{ 6877 inputs: []inputInfo{ 6878 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6879 }, 6880 outputs: []outputInfo{ 6881 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6882 }, 6883 }, 6884 }, 6885 { 6886 name: "CVTTSS2SL", 6887 argLen: 1, 6888 asm: x86.ACVTTSS2SL, 6889 reg: regInfo{ 6890 inputs: []inputInfo{ 6891 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6892 }, 6893 outputs: []outputInfo{ 6894 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6895 }, 6896 }, 6897 }, 6898 { 6899 name: "CVTTSS2SQ", 6900 argLen: 1, 6901 asm: x86.ACVTTSS2SQ, 6902 reg: regInfo{ 6903 inputs: []inputInfo{ 6904 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6905 }, 6906 outputs: []outputInfo{ 6907 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6908 }, 6909 }, 6910 }, 6911 { 6912 name: "CVTSL2SS", 6913 argLen: 1, 6914 asm: x86.ACVTSL2SS, 6915 reg: regInfo{ 6916 inputs: []inputInfo{ 6917 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6918 }, 6919 outputs: []outputInfo{ 6920 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6921 }, 6922 }, 6923 }, 6924 { 6925 name: "CVTSL2SD", 6926 argLen: 1, 6927 asm: x86.ACVTSL2SD, 6928 reg: regInfo{ 6929 inputs: []inputInfo{ 6930 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6931 }, 6932 outputs: []outputInfo{ 6933 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6934 }, 6935 }, 6936 }, 6937 { 6938 name: "CVTSQ2SS", 6939 argLen: 1, 6940 asm: x86.ACVTSQ2SS, 6941 reg: regInfo{ 6942 inputs: []inputInfo{ 6943 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6944 }, 6945 outputs: []outputInfo{ 6946 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6947 }, 6948 }, 6949 }, 6950 { 6951 name: "CVTSQ2SD", 6952 argLen: 1, 6953 asm: x86.ACVTSQ2SD, 6954 reg: regInfo{ 6955 inputs: []inputInfo{ 6956 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6957 }, 6958 outputs: []outputInfo{ 6959 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6960 }, 6961 }, 6962 }, 6963 { 6964 name: "CVTSD2SS", 6965 argLen: 1, 6966 asm: x86.ACVTSD2SS, 6967 reg: regInfo{ 6968 inputs: []inputInfo{ 6969 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6970 }, 6971 outputs: []outputInfo{ 6972 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6973 }, 6974 }, 6975 }, 6976 { 6977 name: "CVTSS2SD", 6978 argLen: 1, 6979 asm: x86.ACVTSS2SD, 6980 reg: regInfo{ 6981 inputs: []inputInfo{ 6982 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6983 }, 6984 outputs: []outputInfo{ 6985 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6986 }, 6987 }, 6988 }, 6989 { 6990 name: "PXOR", 6991 argLen: 2, 6992 commutative: true, 6993 resultInArg0: true, 6994 asm: x86.APXOR, 6995 reg: regInfo{ 6996 inputs: []inputInfo{ 6997 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6998 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6999 }, 7000 outputs: []outputInfo{ 7001 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7002 }, 7003 }, 7004 }, 7005 { 7006 name: "LEAQ", 7007 auxType: auxSymOff, 7008 argLen: 1, 7009 rematerializeable: true, 7010 symEffect: SymAddr, 7011 asm: x86.ALEAQ, 7012 reg: regInfo{ 7013 inputs: []inputInfo{ 7014 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7015 }, 7016 outputs: []outputInfo{ 7017 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7018 }, 7019 }, 7020 }, 7021 { 7022 name: "LEAQ1", 7023 auxType: auxSymOff, 7024 argLen: 2, 7025 commutative: true, 7026 symEffect: SymAddr, 7027 reg: regInfo{ 7028 inputs: []inputInfo{ 7029 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7030 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7031 }, 7032 outputs: []outputInfo{ 7033 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7034 }, 7035 }, 7036 }, 7037 { 7038 name: "LEAQ2", 7039 auxType: auxSymOff, 7040 argLen: 2, 7041 symEffect: SymAddr, 7042 reg: regInfo{ 7043 inputs: []inputInfo{ 7044 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7045 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7046 }, 7047 outputs: []outputInfo{ 7048 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7049 }, 7050 }, 7051 }, 7052 { 7053 name: "LEAQ4", 7054 auxType: auxSymOff, 7055 argLen: 2, 7056 symEffect: SymAddr, 7057 reg: regInfo{ 7058 inputs: []inputInfo{ 7059 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7060 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7061 }, 7062 outputs: []outputInfo{ 7063 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7064 }, 7065 }, 7066 }, 7067 { 7068 name: "LEAQ8", 7069 auxType: auxSymOff, 7070 argLen: 2, 7071 symEffect: SymAddr, 7072 reg: regInfo{ 7073 inputs: []inputInfo{ 7074 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7075 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7076 }, 7077 outputs: []outputInfo{ 7078 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7079 }, 7080 }, 7081 }, 7082 { 7083 name: "LEAL", 7084 auxType: auxSymOff, 7085 argLen: 1, 7086 rematerializeable: true, 7087 symEffect: SymAddr, 7088 asm: x86.ALEAL, 7089 reg: regInfo{ 7090 inputs: []inputInfo{ 7091 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7092 }, 7093 outputs: []outputInfo{ 7094 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7095 }, 7096 }, 7097 }, 7098 { 7099 name: "MOVBload", 7100 auxType: auxSymOff, 7101 argLen: 2, 7102 faultOnNilArg0: true, 7103 symEffect: SymRead, 7104 asm: x86.AMOVBLZX, 7105 reg: regInfo{ 7106 inputs: []inputInfo{ 7107 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7108 }, 7109 outputs: []outputInfo{ 7110 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7111 }, 7112 }, 7113 }, 7114 { 7115 name: "MOVBQSXload", 7116 auxType: auxSymOff, 7117 argLen: 2, 7118 faultOnNilArg0: true, 7119 symEffect: SymRead, 7120 asm: x86.AMOVBQSX, 7121 reg: regInfo{ 7122 inputs: []inputInfo{ 7123 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7124 }, 7125 outputs: []outputInfo{ 7126 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7127 }, 7128 }, 7129 }, 7130 { 7131 name: "MOVWload", 7132 auxType: auxSymOff, 7133 argLen: 2, 7134 faultOnNilArg0: true, 7135 symEffect: SymRead, 7136 asm: x86.AMOVWLZX, 7137 reg: regInfo{ 7138 inputs: []inputInfo{ 7139 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7140 }, 7141 outputs: []outputInfo{ 7142 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7143 }, 7144 }, 7145 }, 7146 { 7147 name: "MOVWQSXload", 7148 auxType: auxSymOff, 7149 argLen: 2, 7150 faultOnNilArg0: true, 7151 symEffect: SymRead, 7152 asm: x86.AMOVWQSX, 7153 reg: regInfo{ 7154 inputs: []inputInfo{ 7155 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7156 }, 7157 outputs: []outputInfo{ 7158 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7159 }, 7160 }, 7161 }, 7162 { 7163 name: "MOVLload", 7164 auxType: auxSymOff, 7165 argLen: 2, 7166 faultOnNilArg0: true, 7167 symEffect: SymRead, 7168 asm: x86.AMOVL, 7169 reg: regInfo{ 7170 inputs: []inputInfo{ 7171 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7172 }, 7173 outputs: []outputInfo{ 7174 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7175 }, 7176 }, 7177 }, 7178 { 7179 name: "MOVLQSXload", 7180 auxType: auxSymOff, 7181 argLen: 2, 7182 faultOnNilArg0: true, 7183 symEffect: SymRead, 7184 asm: x86.AMOVLQSX, 7185 reg: regInfo{ 7186 inputs: []inputInfo{ 7187 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7188 }, 7189 outputs: []outputInfo{ 7190 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7191 }, 7192 }, 7193 }, 7194 { 7195 name: "MOVQload", 7196 auxType: auxSymOff, 7197 argLen: 2, 7198 faultOnNilArg0: true, 7199 symEffect: SymRead, 7200 asm: x86.AMOVQ, 7201 reg: regInfo{ 7202 inputs: []inputInfo{ 7203 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7204 }, 7205 outputs: []outputInfo{ 7206 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7207 }, 7208 }, 7209 }, 7210 { 7211 name: "MOVBstore", 7212 auxType: auxSymOff, 7213 argLen: 3, 7214 faultOnNilArg0: true, 7215 symEffect: SymWrite, 7216 asm: x86.AMOVB, 7217 reg: regInfo{ 7218 inputs: []inputInfo{ 7219 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7220 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7221 }, 7222 }, 7223 }, 7224 { 7225 name: "MOVWstore", 7226 auxType: auxSymOff, 7227 argLen: 3, 7228 faultOnNilArg0: true, 7229 symEffect: SymWrite, 7230 asm: x86.AMOVW, 7231 reg: regInfo{ 7232 inputs: []inputInfo{ 7233 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7234 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7235 }, 7236 }, 7237 }, 7238 { 7239 name: "MOVLstore", 7240 auxType: auxSymOff, 7241 argLen: 3, 7242 faultOnNilArg0: true, 7243 symEffect: SymWrite, 7244 asm: x86.AMOVL, 7245 reg: regInfo{ 7246 inputs: []inputInfo{ 7247 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7248 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7249 }, 7250 }, 7251 }, 7252 { 7253 name: "MOVQstore", 7254 auxType: auxSymOff, 7255 argLen: 3, 7256 faultOnNilArg0: true, 7257 symEffect: SymWrite, 7258 asm: x86.AMOVQ, 7259 reg: regInfo{ 7260 inputs: []inputInfo{ 7261 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7262 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7263 }, 7264 }, 7265 }, 7266 { 7267 name: "MOVOload", 7268 auxType: auxSymOff, 7269 argLen: 2, 7270 faultOnNilArg0: true, 7271 symEffect: SymRead, 7272 asm: x86.AMOVUPS, 7273 reg: regInfo{ 7274 inputs: []inputInfo{ 7275 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7276 }, 7277 outputs: []outputInfo{ 7278 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7279 }, 7280 }, 7281 }, 7282 { 7283 name: "MOVOstore", 7284 auxType: auxSymOff, 7285 argLen: 3, 7286 faultOnNilArg0: true, 7287 symEffect: SymWrite, 7288 asm: x86.AMOVUPS, 7289 reg: regInfo{ 7290 inputs: []inputInfo{ 7291 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7292 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7293 }, 7294 }, 7295 }, 7296 { 7297 name: "MOVBloadidx1", 7298 auxType: auxSymOff, 7299 argLen: 3, 7300 commutative: true, 7301 symEffect: SymRead, 7302 asm: x86.AMOVBLZX, 7303 reg: regInfo{ 7304 inputs: []inputInfo{ 7305 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7306 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7307 }, 7308 outputs: []outputInfo{ 7309 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7310 }, 7311 }, 7312 }, 7313 { 7314 name: "MOVWloadidx1", 7315 auxType: auxSymOff, 7316 argLen: 3, 7317 commutative: true, 7318 symEffect: SymRead, 7319 asm: x86.AMOVWLZX, 7320 reg: regInfo{ 7321 inputs: []inputInfo{ 7322 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7323 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7324 }, 7325 outputs: []outputInfo{ 7326 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7327 }, 7328 }, 7329 }, 7330 { 7331 name: "MOVWloadidx2", 7332 auxType: auxSymOff, 7333 argLen: 3, 7334 symEffect: SymRead, 7335 asm: x86.AMOVWLZX, 7336 reg: regInfo{ 7337 inputs: []inputInfo{ 7338 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7339 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7340 }, 7341 outputs: []outputInfo{ 7342 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7343 }, 7344 }, 7345 }, 7346 { 7347 name: "MOVLloadidx1", 7348 auxType: auxSymOff, 7349 argLen: 3, 7350 commutative: true, 7351 symEffect: SymRead, 7352 asm: x86.AMOVL, 7353 reg: regInfo{ 7354 inputs: []inputInfo{ 7355 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7356 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7357 }, 7358 outputs: []outputInfo{ 7359 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7360 }, 7361 }, 7362 }, 7363 { 7364 name: "MOVLloadidx4", 7365 auxType: auxSymOff, 7366 argLen: 3, 7367 symEffect: SymRead, 7368 asm: x86.AMOVL, 7369 reg: regInfo{ 7370 inputs: []inputInfo{ 7371 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7372 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7373 }, 7374 outputs: []outputInfo{ 7375 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7376 }, 7377 }, 7378 }, 7379 { 7380 name: "MOVQloadidx1", 7381 auxType: auxSymOff, 7382 argLen: 3, 7383 commutative: true, 7384 symEffect: SymRead, 7385 asm: x86.AMOVQ, 7386 reg: regInfo{ 7387 inputs: []inputInfo{ 7388 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7389 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7390 }, 7391 outputs: []outputInfo{ 7392 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7393 }, 7394 }, 7395 }, 7396 { 7397 name: "MOVQloadidx8", 7398 auxType: auxSymOff, 7399 argLen: 3, 7400 symEffect: SymRead, 7401 asm: x86.AMOVQ, 7402 reg: regInfo{ 7403 inputs: []inputInfo{ 7404 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7405 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7406 }, 7407 outputs: []outputInfo{ 7408 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7409 }, 7410 }, 7411 }, 7412 { 7413 name: "MOVBstoreidx1", 7414 auxType: auxSymOff, 7415 argLen: 4, 7416 symEffect: SymWrite, 7417 asm: x86.AMOVB, 7418 reg: regInfo{ 7419 inputs: []inputInfo{ 7420 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7421 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7422 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7423 }, 7424 }, 7425 }, 7426 { 7427 name: "MOVWstoreidx1", 7428 auxType: auxSymOff, 7429 argLen: 4, 7430 symEffect: SymWrite, 7431 asm: x86.AMOVW, 7432 reg: regInfo{ 7433 inputs: []inputInfo{ 7434 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7435 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7436 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7437 }, 7438 }, 7439 }, 7440 { 7441 name: "MOVWstoreidx2", 7442 auxType: auxSymOff, 7443 argLen: 4, 7444 symEffect: SymWrite, 7445 asm: x86.AMOVW, 7446 reg: regInfo{ 7447 inputs: []inputInfo{ 7448 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7449 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7450 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7451 }, 7452 }, 7453 }, 7454 { 7455 name: "MOVLstoreidx1", 7456 auxType: auxSymOff, 7457 argLen: 4, 7458 symEffect: SymWrite, 7459 asm: x86.AMOVL, 7460 reg: regInfo{ 7461 inputs: []inputInfo{ 7462 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7463 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7464 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7465 }, 7466 }, 7467 }, 7468 { 7469 name: "MOVLstoreidx4", 7470 auxType: auxSymOff, 7471 argLen: 4, 7472 symEffect: SymWrite, 7473 asm: x86.AMOVL, 7474 reg: regInfo{ 7475 inputs: []inputInfo{ 7476 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7477 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7478 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7479 }, 7480 }, 7481 }, 7482 { 7483 name: "MOVQstoreidx1", 7484 auxType: auxSymOff, 7485 argLen: 4, 7486 symEffect: SymWrite, 7487 asm: x86.AMOVQ, 7488 reg: regInfo{ 7489 inputs: []inputInfo{ 7490 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7491 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7492 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7493 }, 7494 }, 7495 }, 7496 { 7497 name: "MOVQstoreidx8", 7498 auxType: auxSymOff, 7499 argLen: 4, 7500 symEffect: SymWrite, 7501 asm: x86.AMOVQ, 7502 reg: regInfo{ 7503 inputs: []inputInfo{ 7504 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7505 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7506 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7507 }, 7508 }, 7509 }, 7510 { 7511 name: "MOVBstoreconst", 7512 auxType: auxSymValAndOff, 7513 argLen: 2, 7514 faultOnNilArg0: true, 7515 symEffect: SymWrite, 7516 asm: x86.AMOVB, 7517 reg: regInfo{ 7518 inputs: []inputInfo{ 7519 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7520 }, 7521 }, 7522 }, 7523 { 7524 name: "MOVWstoreconst", 7525 auxType: auxSymValAndOff, 7526 argLen: 2, 7527 faultOnNilArg0: true, 7528 symEffect: SymWrite, 7529 asm: x86.AMOVW, 7530 reg: regInfo{ 7531 inputs: []inputInfo{ 7532 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7533 }, 7534 }, 7535 }, 7536 { 7537 name: "MOVLstoreconst", 7538 auxType: auxSymValAndOff, 7539 argLen: 2, 7540 faultOnNilArg0: true, 7541 symEffect: SymWrite, 7542 asm: x86.AMOVL, 7543 reg: regInfo{ 7544 inputs: []inputInfo{ 7545 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7546 }, 7547 }, 7548 }, 7549 { 7550 name: "MOVQstoreconst", 7551 auxType: auxSymValAndOff, 7552 argLen: 2, 7553 faultOnNilArg0: true, 7554 symEffect: SymWrite, 7555 asm: x86.AMOVQ, 7556 reg: regInfo{ 7557 inputs: []inputInfo{ 7558 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7559 }, 7560 }, 7561 }, 7562 { 7563 name: "MOVBstoreconstidx1", 7564 auxType: auxSymValAndOff, 7565 argLen: 3, 7566 symEffect: SymWrite, 7567 asm: x86.AMOVB, 7568 reg: regInfo{ 7569 inputs: []inputInfo{ 7570 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7571 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7572 }, 7573 }, 7574 }, 7575 { 7576 name: "MOVWstoreconstidx1", 7577 auxType: auxSymValAndOff, 7578 argLen: 3, 7579 symEffect: SymWrite, 7580 asm: x86.AMOVW, 7581 reg: regInfo{ 7582 inputs: []inputInfo{ 7583 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7584 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7585 }, 7586 }, 7587 }, 7588 { 7589 name: "MOVWstoreconstidx2", 7590 auxType: auxSymValAndOff, 7591 argLen: 3, 7592 symEffect: SymWrite, 7593 asm: x86.AMOVW, 7594 reg: regInfo{ 7595 inputs: []inputInfo{ 7596 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7597 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7598 }, 7599 }, 7600 }, 7601 { 7602 name: "MOVLstoreconstidx1", 7603 auxType: auxSymValAndOff, 7604 argLen: 3, 7605 symEffect: SymWrite, 7606 asm: x86.AMOVL, 7607 reg: regInfo{ 7608 inputs: []inputInfo{ 7609 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7610 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7611 }, 7612 }, 7613 }, 7614 { 7615 name: "MOVLstoreconstidx4", 7616 auxType: auxSymValAndOff, 7617 argLen: 3, 7618 symEffect: SymWrite, 7619 asm: x86.AMOVL, 7620 reg: regInfo{ 7621 inputs: []inputInfo{ 7622 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7623 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7624 }, 7625 }, 7626 }, 7627 { 7628 name: "MOVQstoreconstidx1", 7629 auxType: auxSymValAndOff, 7630 argLen: 3, 7631 symEffect: SymWrite, 7632 asm: x86.AMOVQ, 7633 reg: regInfo{ 7634 inputs: []inputInfo{ 7635 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7636 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7637 }, 7638 }, 7639 }, 7640 { 7641 name: "MOVQstoreconstidx8", 7642 auxType: auxSymValAndOff, 7643 argLen: 3, 7644 symEffect: SymWrite, 7645 asm: x86.AMOVQ, 7646 reg: regInfo{ 7647 inputs: []inputInfo{ 7648 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7649 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7650 }, 7651 }, 7652 }, 7653 { 7654 name: "DUFFZERO", 7655 auxType: auxInt64, 7656 argLen: 3, 7657 faultOnNilArg0: true, 7658 reg: regInfo{ 7659 inputs: []inputInfo{ 7660 {0, 128}, // DI 7661 {1, 65536}, // X0 7662 }, 7663 clobbers: 128, // DI 7664 }, 7665 }, 7666 { 7667 name: "MOVOconst", 7668 auxType: auxInt128, 7669 argLen: 0, 7670 rematerializeable: true, 7671 reg: regInfo{ 7672 outputs: []outputInfo{ 7673 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7674 }, 7675 }, 7676 }, 7677 { 7678 name: "REPSTOSQ", 7679 argLen: 4, 7680 faultOnNilArg0: true, 7681 reg: regInfo{ 7682 inputs: []inputInfo{ 7683 {0, 128}, // DI 7684 {1, 2}, // CX 7685 {2, 1}, // AX 7686 }, 7687 clobbers: 130, // CX DI 7688 }, 7689 }, 7690 { 7691 name: "CALLstatic", 7692 auxType: auxSymOff, 7693 argLen: 1, 7694 clobberFlags: true, 7695 call: true, 7696 symEffect: SymNone, 7697 reg: regInfo{ 7698 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7699 }, 7700 }, 7701 { 7702 name: "CALLclosure", 7703 auxType: auxInt64, 7704 argLen: 3, 7705 clobberFlags: true, 7706 call: true, 7707 reg: regInfo{ 7708 inputs: []inputInfo{ 7709 {1, 4}, // DX 7710 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7711 }, 7712 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7713 }, 7714 }, 7715 { 7716 name: "CALLinter", 7717 auxType: auxInt64, 7718 argLen: 2, 7719 clobberFlags: true, 7720 call: true, 7721 reg: regInfo{ 7722 inputs: []inputInfo{ 7723 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7724 }, 7725 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7726 }, 7727 }, 7728 { 7729 name: "DUFFCOPY", 7730 auxType: auxInt64, 7731 argLen: 3, 7732 clobberFlags: true, 7733 faultOnNilArg0: true, 7734 faultOnNilArg1: true, 7735 reg: regInfo{ 7736 inputs: []inputInfo{ 7737 {0, 128}, // DI 7738 {1, 64}, // SI 7739 }, 7740 clobbers: 65728, // SI DI X0 7741 }, 7742 }, 7743 { 7744 name: "REPMOVSQ", 7745 argLen: 4, 7746 faultOnNilArg0: true, 7747 faultOnNilArg1: true, 7748 reg: regInfo{ 7749 inputs: []inputInfo{ 7750 {0, 128}, // DI 7751 {1, 64}, // SI 7752 {2, 2}, // CX 7753 }, 7754 clobbers: 194, // CX SI DI 7755 }, 7756 }, 7757 { 7758 name: "InvertFlags", 7759 argLen: 1, 7760 reg: regInfo{}, 7761 }, 7762 { 7763 name: "LoweredGetG", 7764 argLen: 1, 7765 reg: regInfo{ 7766 outputs: []outputInfo{ 7767 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7768 }, 7769 }, 7770 }, 7771 { 7772 name: "LoweredGetClosurePtr", 7773 argLen: 0, 7774 reg: regInfo{ 7775 outputs: []outputInfo{ 7776 {0, 4}, // DX 7777 }, 7778 }, 7779 }, 7780 { 7781 name: "LoweredNilCheck", 7782 argLen: 2, 7783 clobberFlags: true, 7784 nilCheck: true, 7785 faultOnNilArg0: true, 7786 reg: regInfo{ 7787 inputs: []inputInfo{ 7788 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7789 }, 7790 }, 7791 }, 7792 { 7793 name: "MOVQconvert", 7794 argLen: 2, 7795 asm: x86.AMOVQ, 7796 reg: regInfo{ 7797 inputs: []inputInfo{ 7798 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7799 }, 7800 outputs: []outputInfo{ 7801 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7802 }, 7803 }, 7804 }, 7805 { 7806 name: "MOVLconvert", 7807 argLen: 2, 7808 asm: x86.AMOVL, 7809 reg: regInfo{ 7810 inputs: []inputInfo{ 7811 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7812 }, 7813 outputs: []outputInfo{ 7814 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7815 }, 7816 }, 7817 }, 7818 { 7819 name: "FlagEQ", 7820 argLen: 0, 7821 reg: regInfo{}, 7822 }, 7823 { 7824 name: "FlagLT_ULT", 7825 argLen: 0, 7826 reg: regInfo{}, 7827 }, 7828 { 7829 name: "FlagLT_UGT", 7830 argLen: 0, 7831 reg: regInfo{}, 7832 }, 7833 { 7834 name: "FlagGT_UGT", 7835 argLen: 0, 7836 reg: regInfo{}, 7837 }, 7838 { 7839 name: "FlagGT_ULT", 7840 argLen: 0, 7841 reg: regInfo{}, 7842 }, 7843 { 7844 name: "MOVLatomicload", 7845 auxType: auxSymOff, 7846 argLen: 2, 7847 faultOnNilArg0: true, 7848 symEffect: SymRead, 7849 asm: x86.AMOVL, 7850 reg: regInfo{ 7851 inputs: []inputInfo{ 7852 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7853 }, 7854 outputs: []outputInfo{ 7855 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7856 }, 7857 }, 7858 }, 7859 { 7860 name: "MOVQatomicload", 7861 auxType: auxSymOff, 7862 argLen: 2, 7863 faultOnNilArg0: true, 7864 symEffect: SymRead, 7865 asm: x86.AMOVQ, 7866 reg: regInfo{ 7867 inputs: []inputInfo{ 7868 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7869 }, 7870 outputs: []outputInfo{ 7871 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7872 }, 7873 }, 7874 }, 7875 { 7876 name: "XCHGL", 7877 auxType: auxSymOff, 7878 argLen: 3, 7879 resultInArg0: true, 7880 faultOnNilArg1: true, 7881 hasSideEffects: true, 7882 symEffect: SymRdWr, 7883 asm: x86.AXCHGL, 7884 reg: regInfo{ 7885 inputs: []inputInfo{ 7886 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7887 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7888 }, 7889 outputs: []outputInfo{ 7890 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7891 }, 7892 }, 7893 }, 7894 { 7895 name: "XCHGQ", 7896 auxType: auxSymOff, 7897 argLen: 3, 7898 resultInArg0: true, 7899 faultOnNilArg1: true, 7900 hasSideEffects: true, 7901 symEffect: SymRdWr, 7902 asm: x86.AXCHGQ, 7903 reg: regInfo{ 7904 inputs: []inputInfo{ 7905 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7906 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7907 }, 7908 outputs: []outputInfo{ 7909 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7910 }, 7911 }, 7912 }, 7913 { 7914 name: "XADDLlock", 7915 auxType: auxSymOff, 7916 argLen: 3, 7917 resultInArg0: true, 7918 clobberFlags: true, 7919 faultOnNilArg1: true, 7920 hasSideEffects: true, 7921 symEffect: SymRdWr, 7922 asm: x86.AXADDL, 7923 reg: regInfo{ 7924 inputs: []inputInfo{ 7925 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7926 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7927 }, 7928 outputs: []outputInfo{ 7929 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7930 }, 7931 }, 7932 }, 7933 { 7934 name: "XADDQlock", 7935 auxType: auxSymOff, 7936 argLen: 3, 7937 resultInArg0: true, 7938 clobberFlags: true, 7939 faultOnNilArg1: true, 7940 hasSideEffects: true, 7941 symEffect: SymRdWr, 7942 asm: x86.AXADDQ, 7943 reg: regInfo{ 7944 inputs: []inputInfo{ 7945 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7946 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7947 }, 7948 outputs: []outputInfo{ 7949 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7950 }, 7951 }, 7952 }, 7953 { 7954 name: "AddTupleFirst32", 7955 argLen: 2, 7956 reg: regInfo{}, 7957 }, 7958 { 7959 name: "AddTupleFirst64", 7960 argLen: 2, 7961 reg: regInfo{}, 7962 }, 7963 { 7964 name: "CMPXCHGLlock", 7965 auxType: auxSymOff, 7966 argLen: 4, 7967 clobberFlags: true, 7968 faultOnNilArg0: true, 7969 hasSideEffects: true, 7970 symEffect: SymRdWr, 7971 asm: x86.ACMPXCHGL, 7972 reg: regInfo{ 7973 inputs: []inputInfo{ 7974 {1, 1}, // AX 7975 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7976 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7977 }, 7978 clobbers: 1, // AX 7979 outputs: []outputInfo{ 7980 {1, 0}, 7981 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7982 }, 7983 }, 7984 }, 7985 { 7986 name: "CMPXCHGQlock", 7987 auxType: auxSymOff, 7988 argLen: 4, 7989 clobberFlags: true, 7990 faultOnNilArg0: true, 7991 hasSideEffects: true, 7992 symEffect: SymRdWr, 7993 asm: x86.ACMPXCHGQ, 7994 reg: regInfo{ 7995 inputs: []inputInfo{ 7996 {1, 1}, // AX 7997 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7998 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7999 }, 8000 clobbers: 1, // AX 8001 outputs: []outputInfo{ 8002 {1, 0}, 8003 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8004 }, 8005 }, 8006 }, 8007 { 8008 name: "ANDBlock", 8009 auxType: auxSymOff, 8010 argLen: 3, 8011 clobberFlags: true, 8012 faultOnNilArg0: true, 8013 hasSideEffects: true, 8014 symEffect: SymRdWr, 8015 asm: x86.AANDB, 8016 reg: regInfo{ 8017 inputs: []inputInfo{ 8018 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8019 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8020 }, 8021 }, 8022 }, 8023 { 8024 name: "ORBlock", 8025 auxType: auxSymOff, 8026 argLen: 3, 8027 clobberFlags: true, 8028 faultOnNilArg0: true, 8029 hasSideEffects: true, 8030 symEffect: SymRdWr, 8031 asm: x86.AORB, 8032 reg: regInfo{ 8033 inputs: []inputInfo{ 8034 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8035 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8036 }, 8037 }, 8038 }, 8039 8040 { 8041 name: "ADD", 8042 argLen: 2, 8043 commutative: true, 8044 asm: arm.AADD, 8045 reg: regInfo{ 8046 inputs: []inputInfo{ 8047 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8048 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8049 }, 8050 outputs: []outputInfo{ 8051 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8052 }, 8053 }, 8054 }, 8055 { 8056 name: "ADDconst", 8057 auxType: auxInt32, 8058 argLen: 1, 8059 asm: arm.AADD, 8060 reg: regInfo{ 8061 inputs: []inputInfo{ 8062 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 8063 }, 8064 outputs: []outputInfo{ 8065 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8066 }, 8067 }, 8068 }, 8069 { 8070 name: "SUB", 8071 argLen: 2, 8072 asm: arm.ASUB, 8073 reg: regInfo{ 8074 inputs: []inputInfo{ 8075 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8076 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8077 }, 8078 outputs: []outputInfo{ 8079 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8080 }, 8081 }, 8082 }, 8083 { 8084 name: "SUBconst", 8085 auxType: auxInt32, 8086 argLen: 1, 8087 asm: arm.ASUB, 8088 reg: regInfo{ 8089 inputs: []inputInfo{ 8090 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8091 }, 8092 outputs: []outputInfo{ 8093 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8094 }, 8095 }, 8096 }, 8097 { 8098 name: "RSB", 8099 argLen: 2, 8100 asm: arm.ARSB, 8101 reg: regInfo{ 8102 inputs: []inputInfo{ 8103 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8104 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8105 }, 8106 outputs: []outputInfo{ 8107 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8108 }, 8109 }, 8110 }, 8111 { 8112 name: "RSBconst", 8113 auxType: auxInt32, 8114 argLen: 1, 8115 asm: arm.ARSB, 8116 reg: regInfo{ 8117 inputs: []inputInfo{ 8118 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8119 }, 8120 outputs: []outputInfo{ 8121 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8122 }, 8123 }, 8124 }, 8125 { 8126 name: "MUL", 8127 argLen: 2, 8128 commutative: true, 8129 asm: arm.AMUL, 8130 reg: regInfo{ 8131 inputs: []inputInfo{ 8132 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8133 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8134 }, 8135 outputs: []outputInfo{ 8136 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8137 }, 8138 }, 8139 }, 8140 { 8141 name: "HMUL", 8142 argLen: 2, 8143 commutative: true, 8144 asm: arm.AMULL, 8145 reg: regInfo{ 8146 inputs: []inputInfo{ 8147 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8148 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8149 }, 8150 outputs: []outputInfo{ 8151 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8152 }, 8153 }, 8154 }, 8155 { 8156 name: "HMULU", 8157 argLen: 2, 8158 commutative: true, 8159 asm: arm.AMULLU, 8160 reg: regInfo{ 8161 inputs: []inputInfo{ 8162 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8163 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8164 }, 8165 outputs: []outputInfo{ 8166 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8167 }, 8168 }, 8169 }, 8170 { 8171 name: "CALLudiv", 8172 argLen: 2, 8173 clobberFlags: true, 8174 reg: regInfo{ 8175 inputs: []inputInfo{ 8176 {0, 2}, // R1 8177 {1, 1}, // R0 8178 }, 8179 clobbers: 16396, // R2 R3 R14 8180 outputs: []outputInfo{ 8181 {0, 1}, // R0 8182 {1, 2}, // R1 8183 }, 8184 }, 8185 }, 8186 { 8187 name: "ADDS", 8188 argLen: 2, 8189 commutative: true, 8190 asm: arm.AADD, 8191 reg: regInfo{ 8192 inputs: []inputInfo{ 8193 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8194 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8195 }, 8196 outputs: []outputInfo{ 8197 {1, 0}, 8198 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8199 }, 8200 }, 8201 }, 8202 { 8203 name: "ADDSconst", 8204 auxType: auxInt32, 8205 argLen: 1, 8206 asm: arm.AADD, 8207 reg: regInfo{ 8208 inputs: []inputInfo{ 8209 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8210 }, 8211 outputs: []outputInfo{ 8212 {1, 0}, 8213 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8214 }, 8215 }, 8216 }, 8217 { 8218 name: "ADC", 8219 argLen: 3, 8220 commutative: true, 8221 asm: arm.AADC, 8222 reg: regInfo{ 8223 inputs: []inputInfo{ 8224 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8225 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8226 }, 8227 outputs: []outputInfo{ 8228 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8229 }, 8230 }, 8231 }, 8232 { 8233 name: "ADCconst", 8234 auxType: auxInt32, 8235 argLen: 2, 8236 asm: arm.AADC, 8237 reg: regInfo{ 8238 inputs: []inputInfo{ 8239 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8240 }, 8241 outputs: []outputInfo{ 8242 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8243 }, 8244 }, 8245 }, 8246 { 8247 name: "SUBS", 8248 argLen: 2, 8249 asm: arm.ASUB, 8250 reg: regInfo{ 8251 inputs: []inputInfo{ 8252 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8253 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8254 }, 8255 outputs: []outputInfo{ 8256 {1, 0}, 8257 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8258 }, 8259 }, 8260 }, 8261 { 8262 name: "SUBSconst", 8263 auxType: auxInt32, 8264 argLen: 1, 8265 asm: arm.ASUB, 8266 reg: regInfo{ 8267 inputs: []inputInfo{ 8268 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8269 }, 8270 outputs: []outputInfo{ 8271 {1, 0}, 8272 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8273 }, 8274 }, 8275 }, 8276 { 8277 name: "RSBSconst", 8278 auxType: auxInt32, 8279 argLen: 1, 8280 asm: arm.ARSB, 8281 reg: regInfo{ 8282 inputs: []inputInfo{ 8283 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8284 }, 8285 outputs: []outputInfo{ 8286 {1, 0}, 8287 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8288 }, 8289 }, 8290 }, 8291 { 8292 name: "SBC", 8293 argLen: 3, 8294 asm: arm.ASBC, 8295 reg: regInfo{ 8296 inputs: []inputInfo{ 8297 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8298 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8299 }, 8300 outputs: []outputInfo{ 8301 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8302 }, 8303 }, 8304 }, 8305 { 8306 name: "SBCconst", 8307 auxType: auxInt32, 8308 argLen: 2, 8309 asm: arm.ASBC, 8310 reg: regInfo{ 8311 inputs: []inputInfo{ 8312 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8313 }, 8314 outputs: []outputInfo{ 8315 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8316 }, 8317 }, 8318 }, 8319 { 8320 name: "RSCconst", 8321 auxType: auxInt32, 8322 argLen: 2, 8323 asm: arm.ARSC, 8324 reg: regInfo{ 8325 inputs: []inputInfo{ 8326 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8327 }, 8328 outputs: []outputInfo{ 8329 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8330 }, 8331 }, 8332 }, 8333 { 8334 name: "MULLU", 8335 argLen: 2, 8336 commutative: true, 8337 asm: arm.AMULLU, 8338 reg: regInfo{ 8339 inputs: []inputInfo{ 8340 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8341 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8342 }, 8343 outputs: []outputInfo{ 8344 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8345 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8346 }, 8347 }, 8348 }, 8349 { 8350 name: "MULA", 8351 argLen: 3, 8352 asm: arm.AMULA, 8353 reg: regInfo{ 8354 inputs: []inputInfo{ 8355 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8356 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8357 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8358 }, 8359 outputs: []outputInfo{ 8360 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8361 }, 8362 }, 8363 }, 8364 { 8365 name: "ADDF", 8366 argLen: 2, 8367 commutative: true, 8368 asm: arm.AADDF, 8369 reg: regInfo{ 8370 inputs: []inputInfo{ 8371 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8372 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8373 }, 8374 outputs: []outputInfo{ 8375 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8376 }, 8377 }, 8378 }, 8379 { 8380 name: "ADDD", 8381 argLen: 2, 8382 commutative: true, 8383 asm: arm.AADDD, 8384 reg: regInfo{ 8385 inputs: []inputInfo{ 8386 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8387 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8388 }, 8389 outputs: []outputInfo{ 8390 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8391 }, 8392 }, 8393 }, 8394 { 8395 name: "SUBF", 8396 argLen: 2, 8397 asm: arm.ASUBF, 8398 reg: regInfo{ 8399 inputs: []inputInfo{ 8400 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8401 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8402 }, 8403 outputs: []outputInfo{ 8404 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8405 }, 8406 }, 8407 }, 8408 { 8409 name: "SUBD", 8410 argLen: 2, 8411 asm: arm.ASUBD, 8412 reg: regInfo{ 8413 inputs: []inputInfo{ 8414 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8415 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8416 }, 8417 outputs: []outputInfo{ 8418 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8419 }, 8420 }, 8421 }, 8422 { 8423 name: "MULF", 8424 argLen: 2, 8425 commutative: true, 8426 asm: arm.AMULF, 8427 reg: regInfo{ 8428 inputs: []inputInfo{ 8429 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8430 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8431 }, 8432 outputs: []outputInfo{ 8433 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8434 }, 8435 }, 8436 }, 8437 { 8438 name: "MULD", 8439 argLen: 2, 8440 commutative: true, 8441 asm: arm.AMULD, 8442 reg: regInfo{ 8443 inputs: []inputInfo{ 8444 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8445 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8446 }, 8447 outputs: []outputInfo{ 8448 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8449 }, 8450 }, 8451 }, 8452 { 8453 name: "DIVF", 8454 argLen: 2, 8455 asm: arm.ADIVF, 8456 reg: regInfo{ 8457 inputs: []inputInfo{ 8458 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8459 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8460 }, 8461 outputs: []outputInfo{ 8462 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8463 }, 8464 }, 8465 }, 8466 { 8467 name: "DIVD", 8468 argLen: 2, 8469 asm: arm.ADIVD, 8470 reg: regInfo{ 8471 inputs: []inputInfo{ 8472 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8473 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8474 }, 8475 outputs: []outputInfo{ 8476 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8477 }, 8478 }, 8479 }, 8480 { 8481 name: "AND", 8482 argLen: 2, 8483 commutative: true, 8484 asm: arm.AAND, 8485 reg: regInfo{ 8486 inputs: []inputInfo{ 8487 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8488 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8489 }, 8490 outputs: []outputInfo{ 8491 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8492 }, 8493 }, 8494 }, 8495 { 8496 name: "ANDconst", 8497 auxType: auxInt32, 8498 argLen: 1, 8499 asm: arm.AAND, 8500 reg: regInfo{ 8501 inputs: []inputInfo{ 8502 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8503 }, 8504 outputs: []outputInfo{ 8505 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8506 }, 8507 }, 8508 }, 8509 { 8510 name: "OR", 8511 argLen: 2, 8512 commutative: true, 8513 asm: arm.AORR, 8514 reg: regInfo{ 8515 inputs: []inputInfo{ 8516 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8517 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8518 }, 8519 outputs: []outputInfo{ 8520 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8521 }, 8522 }, 8523 }, 8524 { 8525 name: "ORconst", 8526 auxType: auxInt32, 8527 argLen: 1, 8528 asm: arm.AORR, 8529 reg: regInfo{ 8530 inputs: []inputInfo{ 8531 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8532 }, 8533 outputs: []outputInfo{ 8534 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8535 }, 8536 }, 8537 }, 8538 { 8539 name: "XOR", 8540 argLen: 2, 8541 commutative: true, 8542 asm: arm.AEOR, 8543 reg: regInfo{ 8544 inputs: []inputInfo{ 8545 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8546 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8547 }, 8548 outputs: []outputInfo{ 8549 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8550 }, 8551 }, 8552 }, 8553 { 8554 name: "XORconst", 8555 auxType: auxInt32, 8556 argLen: 1, 8557 asm: arm.AEOR, 8558 reg: regInfo{ 8559 inputs: []inputInfo{ 8560 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8561 }, 8562 outputs: []outputInfo{ 8563 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8564 }, 8565 }, 8566 }, 8567 { 8568 name: "BIC", 8569 argLen: 2, 8570 asm: arm.ABIC, 8571 reg: regInfo{ 8572 inputs: []inputInfo{ 8573 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8574 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8575 }, 8576 outputs: []outputInfo{ 8577 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8578 }, 8579 }, 8580 }, 8581 { 8582 name: "BICconst", 8583 auxType: auxInt32, 8584 argLen: 1, 8585 asm: arm.ABIC, 8586 reg: regInfo{ 8587 inputs: []inputInfo{ 8588 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8589 }, 8590 outputs: []outputInfo{ 8591 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8592 }, 8593 }, 8594 }, 8595 { 8596 name: "MVN", 8597 argLen: 1, 8598 asm: arm.AMVN, 8599 reg: regInfo{ 8600 inputs: []inputInfo{ 8601 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8602 }, 8603 outputs: []outputInfo{ 8604 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8605 }, 8606 }, 8607 }, 8608 { 8609 name: "NEGF", 8610 argLen: 1, 8611 asm: arm.ANEGF, 8612 reg: regInfo{ 8613 inputs: []inputInfo{ 8614 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8615 }, 8616 outputs: []outputInfo{ 8617 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8618 }, 8619 }, 8620 }, 8621 { 8622 name: "NEGD", 8623 argLen: 1, 8624 asm: arm.ANEGD, 8625 reg: regInfo{ 8626 inputs: []inputInfo{ 8627 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8628 }, 8629 outputs: []outputInfo{ 8630 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8631 }, 8632 }, 8633 }, 8634 { 8635 name: "SQRTD", 8636 argLen: 1, 8637 asm: arm.ASQRTD, 8638 reg: regInfo{ 8639 inputs: []inputInfo{ 8640 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8641 }, 8642 outputs: []outputInfo{ 8643 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8644 }, 8645 }, 8646 }, 8647 { 8648 name: "CLZ", 8649 argLen: 1, 8650 asm: arm.ACLZ, 8651 reg: regInfo{ 8652 inputs: []inputInfo{ 8653 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8654 }, 8655 outputs: []outputInfo{ 8656 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8657 }, 8658 }, 8659 }, 8660 { 8661 name: "REV", 8662 argLen: 1, 8663 asm: arm.AREV, 8664 reg: regInfo{ 8665 inputs: []inputInfo{ 8666 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8667 }, 8668 outputs: []outputInfo{ 8669 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8670 }, 8671 }, 8672 }, 8673 { 8674 name: "RBIT", 8675 argLen: 1, 8676 asm: arm.ARBIT, 8677 reg: regInfo{ 8678 inputs: []inputInfo{ 8679 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8680 }, 8681 outputs: []outputInfo{ 8682 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8683 }, 8684 }, 8685 }, 8686 { 8687 name: "SLL", 8688 argLen: 2, 8689 asm: arm.ASLL, 8690 reg: regInfo{ 8691 inputs: []inputInfo{ 8692 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8693 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8694 }, 8695 outputs: []outputInfo{ 8696 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8697 }, 8698 }, 8699 }, 8700 { 8701 name: "SLLconst", 8702 auxType: auxInt32, 8703 argLen: 1, 8704 asm: arm.ASLL, 8705 reg: regInfo{ 8706 inputs: []inputInfo{ 8707 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8708 }, 8709 outputs: []outputInfo{ 8710 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8711 }, 8712 }, 8713 }, 8714 { 8715 name: "SRL", 8716 argLen: 2, 8717 asm: arm.ASRL, 8718 reg: regInfo{ 8719 inputs: []inputInfo{ 8720 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8721 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8722 }, 8723 outputs: []outputInfo{ 8724 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8725 }, 8726 }, 8727 }, 8728 { 8729 name: "SRLconst", 8730 auxType: auxInt32, 8731 argLen: 1, 8732 asm: arm.ASRL, 8733 reg: regInfo{ 8734 inputs: []inputInfo{ 8735 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8736 }, 8737 outputs: []outputInfo{ 8738 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8739 }, 8740 }, 8741 }, 8742 { 8743 name: "SRA", 8744 argLen: 2, 8745 asm: arm.ASRA, 8746 reg: regInfo{ 8747 inputs: []inputInfo{ 8748 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8749 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8750 }, 8751 outputs: []outputInfo{ 8752 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8753 }, 8754 }, 8755 }, 8756 { 8757 name: "SRAconst", 8758 auxType: auxInt32, 8759 argLen: 1, 8760 asm: arm.ASRA, 8761 reg: regInfo{ 8762 inputs: []inputInfo{ 8763 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8764 }, 8765 outputs: []outputInfo{ 8766 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8767 }, 8768 }, 8769 }, 8770 { 8771 name: "SRRconst", 8772 auxType: auxInt32, 8773 argLen: 1, 8774 reg: regInfo{ 8775 inputs: []inputInfo{ 8776 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8777 }, 8778 outputs: []outputInfo{ 8779 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8780 }, 8781 }, 8782 }, 8783 { 8784 name: "ADDshiftLL", 8785 auxType: auxInt32, 8786 argLen: 2, 8787 asm: arm.AADD, 8788 reg: regInfo{ 8789 inputs: []inputInfo{ 8790 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8791 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8792 }, 8793 outputs: []outputInfo{ 8794 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8795 }, 8796 }, 8797 }, 8798 { 8799 name: "ADDshiftRL", 8800 auxType: auxInt32, 8801 argLen: 2, 8802 asm: arm.AADD, 8803 reg: regInfo{ 8804 inputs: []inputInfo{ 8805 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8806 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8807 }, 8808 outputs: []outputInfo{ 8809 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8810 }, 8811 }, 8812 }, 8813 { 8814 name: "ADDshiftRA", 8815 auxType: auxInt32, 8816 argLen: 2, 8817 asm: arm.AADD, 8818 reg: regInfo{ 8819 inputs: []inputInfo{ 8820 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8821 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8822 }, 8823 outputs: []outputInfo{ 8824 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8825 }, 8826 }, 8827 }, 8828 { 8829 name: "SUBshiftLL", 8830 auxType: auxInt32, 8831 argLen: 2, 8832 asm: arm.ASUB, 8833 reg: regInfo{ 8834 inputs: []inputInfo{ 8835 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8836 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8837 }, 8838 outputs: []outputInfo{ 8839 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8840 }, 8841 }, 8842 }, 8843 { 8844 name: "SUBshiftRL", 8845 auxType: auxInt32, 8846 argLen: 2, 8847 asm: arm.ASUB, 8848 reg: regInfo{ 8849 inputs: []inputInfo{ 8850 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8851 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8852 }, 8853 outputs: []outputInfo{ 8854 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8855 }, 8856 }, 8857 }, 8858 { 8859 name: "SUBshiftRA", 8860 auxType: auxInt32, 8861 argLen: 2, 8862 asm: arm.ASUB, 8863 reg: regInfo{ 8864 inputs: []inputInfo{ 8865 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8866 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8867 }, 8868 outputs: []outputInfo{ 8869 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8870 }, 8871 }, 8872 }, 8873 { 8874 name: "RSBshiftLL", 8875 auxType: auxInt32, 8876 argLen: 2, 8877 asm: arm.ARSB, 8878 reg: regInfo{ 8879 inputs: []inputInfo{ 8880 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8881 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8882 }, 8883 outputs: []outputInfo{ 8884 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8885 }, 8886 }, 8887 }, 8888 { 8889 name: "RSBshiftRL", 8890 auxType: auxInt32, 8891 argLen: 2, 8892 asm: arm.ARSB, 8893 reg: regInfo{ 8894 inputs: []inputInfo{ 8895 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8896 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8897 }, 8898 outputs: []outputInfo{ 8899 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8900 }, 8901 }, 8902 }, 8903 { 8904 name: "RSBshiftRA", 8905 auxType: auxInt32, 8906 argLen: 2, 8907 asm: arm.ARSB, 8908 reg: regInfo{ 8909 inputs: []inputInfo{ 8910 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8911 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8912 }, 8913 outputs: []outputInfo{ 8914 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8915 }, 8916 }, 8917 }, 8918 { 8919 name: "ANDshiftLL", 8920 auxType: auxInt32, 8921 argLen: 2, 8922 asm: arm.AAND, 8923 reg: regInfo{ 8924 inputs: []inputInfo{ 8925 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8926 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8927 }, 8928 outputs: []outputInfo{ 8929 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8930 }, 8931 }, 8932 }, 8933 { 8934 name: "ANDshiftRL", 8935 auxType: auxInt32, 8936 argLen: 2, 8937 asm: arm.AAND, 8938 reg: regInfo{ 8939 inputs: []inputInfo{ 8940 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8941 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8942 }, 8943 outputs: []outputInfo{ 8944 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8945 }, 8946 }, 8947 }, 8948 { 8949 name: "ANDshiftRA", 8950 auxType: auxInt32, 8951 argLen: 2, 8952 asm: arm.AAND, 8953 reg: regInfo{ 8954 inputs: []inputInfo{ 8955 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8956 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8957 }, 8958 outputs: []outputInfo{ 8959 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8960 }, 8961 }, 8962 }, 8963 { 8964 name: "ORshiftLL", 8965 auxType: auxInt32, 8966 argLen: 2, 8967 asm: arm.AORR, 8968 reg: regInfo{ 8969 inputs: []inputInfo{ 8970 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8971 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8972 }, 8973 outputs: []outputInfo{ 8974 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8975 }, 8976 }, 8977 }, 8978 { 8979 name: "ORshiftRL", 8980 auxType: auxInt32, 8981 argLen: 2, 8982 asm: arm.AORR, 8983 reg: regInfo{ 8984 inputs: []inputInfo{ 8985 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8986 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8987 }, 8988 outputs: []outputInfo{ 8989 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8990 }, 8991 }, 8992 }, 8993 { 8994 name: "ORshiftRA", 8995 auxType: auxInt32, 8996 argLen: 2, 8997 asm: arm.AORR, 8998 reg: regInfo{ 8999 inputs: []inputInfo{ 9000 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9001 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9002 }, 9003 outputs: []outputInfo{ 9004 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9005 }, 9006 }, 9007 }, 9008 { 9009 name: "XORshiftLL", 9010 auxType: auxInt32, 9011 argLen: 2, 9012 asm: arm.AEOR, 9013 reg: regInfo{ 9014 inputs: []inputInfo{ 9015 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9016 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9017 }, 9018 outputs: []outputInfo{ 9019 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9020 }, 9021 }, 9022 }, 9023 { 9024 name: "XORshiftRL", 9025 auxType: auxInt32, 9026 argLen: 2, 9027 asm: arm.AEOR, 9028 reg: regInfo{ 9029 inputs: []inputInfo{ 9030 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9031 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9032 }, 9033 outputs: []outputInfo{ 9034 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9035 }, 9036 }, 9037 }, 9038 { 9039 name: "XORshiftRA", 9040 auxType: auxInt32, 9041 argLen: 2, 9042 asm: arm.AEOR, 9043 reg: regInfo{ 9044 inputs: []inputInfo{ 9045 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9046 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9047 }, 9048 outputs: []outputInfo{ 9049 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9050 }, 9051 }, 9052 }, 9053 { 9054 name: "XORshiftRR", 9055 auxType: auxInt32, 9056 argLen: 2, 9057 asm: arm.AEOR, 9058 reg: regInfo{ 9059 inputs: []inputInfo{ 9060 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9061 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9062 }, 9063 outputs: []outputInfo{ 9064 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9065 }, 9066 }, 9067 }, 9068 { 9069 name: "BICshiftLL", 9070 auxType: auxInt32, 9071 argLen: 2, 9072 asm: arm.ABIC, 9073 reg: regInfo{ 9074 inputs: []inputInfo{ 9075 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9076 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9077 }, 9078 outputs: []outputInfo{ 9079 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9080 }, 9081 }, 9082 }, 9083 { 9084 name: "BICshiftRL", 9085 auxType: auxInt32, 9086 argLen: 2, 9087 asm: arm.ABIC, 9088 reg: regInfo{ 9089 inputs: []inputInfo{ 9090 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9091 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9092 }, 9093 outputs: []outputInfo{ 9094 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9095 }, 9096 }, 9097 }, 9098 { 9099 name: "BICshiftRA", 9100 auxType: auxInt32, 9101 argLen: 2, 9102 asm: arm.ABIC, 9103 reg: regInfo{ 9104 inputs: []inputInfo{ 9105 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9106 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9107 }, 9108 outputs: []outputInfo{ 9109 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9110 }, 9111 }, 9112 }, 9113 { 9114 name: "MVNshiftLL", 9115 auxType: auxInt32, 9116 argLen: 1, 9117 asm: arm.AMVN, 9118 reg: regInfo{ 9119 inputs: []inputInfo{ 9120 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9121 }, 9122 outputs: []outputInfo{ 9123 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9124 }, 9125 }, 9126 }, 9127 { 9128 name: "MVNshiftRL", 9129 auxType: auxInt32, 9130 argLen: 1, 9131 asm: arm.AMVN, 9132 reg: regInfo{ 9133 inputs: []inputInfo{ 9134 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9135 }, 9136 outputs: []outputInfo{ 9137 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9138 }, 9139 }, 9140 }, 9141 { 9142 name: "MVNshiftRA", 9143 auxType: auxInt32, 9144 argLen: 1, 9145 asm: arm.AMVN, 9146 reg: regInfo{ 9147 inputs: []inputInfo{ 9148 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9149 }, 9150 outputs: []outputInfo{ 9151 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9152 }, 9153 }, 9154 }, 9155 { 9156 name: "ADCshiftLL", 9157 auxType: auxInt32, 9158 argLen: 3, 9159 asm: arm.AADC, 9160 reg: regInfo{ 9161 inputs: []inputInfo{ 9162 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9163 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9164 }, 9165 outputs: []outputInfo{ 9166 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9167 }, 9168 }, 9169 }, 9170 { 9171 name: "ADCshiftRL", 9172 auxType: auxInt32, 9173 argLen: 3, 9174 asm: arm.AADC, 9175 reg: regInfo{ 9176 inputs: []inputInfo{ 9177 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9178 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9179 }, 9180 outputs: []outputInfo{ 9181 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9182 }, 9183 }, 9184 }, 9185 { 9186 name: "ADCshiftRA", 9187 auxType: auxInt32, 9188 argLen: 3, 9189 asm: arm.AADC, 9190 reg: regInfo{ 9191 inputs: []inputInfo{ 9192 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9193 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9194 }, 9195 outputs: []outputInfo{ 9196 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9197 }, 9198 }, 9199 }, 9200 { 9201 name: "SBCshiftLL", 9202 auxType: auxInt32, 9203 argLen: 3, 9204 asm: arm.ASBC, 9205 reg: regInfo{ 9206 inputs: []inputInfo{ 9207 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9208 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9209 }, 9210 outputs: []outputInfo{ 9211 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9212 }, 9213 }, 9214 }, 9215 { 9216 name: "SBCshiftRL", 9217 auxType: auxInt32, 9218 argLen: 3, 9219 asm: arm.ASBC, 9220 reg: regInfo{ 9221 inputs: []inputInfo{ 9222 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9223 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9224 }, 9225 outputs: []outputInfo{ 9226 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9227 }, 9228 }, 9229 }, 9230 { 9231 name: "SBCshiftRA", 9232 auxType: auxInt32, 9233 argLen: 3, 9234 asm: arm.ASBC, 9235 reg: regInfo{ 9236 inputs: []inputInfo{ 9237 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9238 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9239 }, 9240 outputs: []outputInfo{ 9241 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9242 }, 9243 }, 9244 }, 9245 { 9246 name: "RSCshiftLL", 9247 auxType: auxInt32, 9248 argLen: 3, 9249 asm: arm.ARSC, 9250 reg: regInfo{ 9251 inputs: []inputInfo{ 9252 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9253 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9254 }, 9255 outputs: []outputInfo{ 9256 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9257 }, 9258 }, 9259 }, 9260 { 9261 name: "RSCshiftRL", 9262 auxType: auxInt32, 9263 argLen: 3, 9264 asm: arm.ARSC, 9265 reg: regInfo{ 9266 inputs: []inputInfo{ 9267 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9268 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9269 }, 9270 outputs: []outputInfo{ 9271 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9272 }, 9273 }, 9274 }, 9275 { 9276 name: "RSCshiftRA", 9277 auxType: auxInt32, 9278 argLen: 3, 9279 asm: arm.ARSC, 9280 reg: regInfo{ 9281 inputs: []inputInfo{ 9282 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9283 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9284 }, 9285 outputs: []outputInfo{ 9286 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9287 }, 9288 }, 9289 }, 9290 { 9291 name: "ADDSshiftLL", 9292 auxType: auxInt32, 9293 argLen: 2, 9294 asm: arm.AADD, 9295 reg: regInfo{ 9296 inputs: []inputInfo{ 9297 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9298 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9299 }, 9300 outputs: []outputInfo{ 9301 {1, 0}, 9302 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9303 }, 9304 }, 9305 }, 9306 { 9307 name: "ADDSshiftRL", 9308 auxType: auxInt32, 9309 argLen: 2, 9310 asm: arm.AADD, 9311 reg: regInfo{ 9312 inputs: []inputInfo{ 9313 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9314 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9315 }, 9316 outputs: []outputInfo{ 9317 {1, 0}, 9318 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9319 }, 9320 }, 9321 }, 9322 { 9323 name: "ADDSshiftRA", 9324 auxType: auxInt32, 9325 argLen: 2, 9326 asm: arm.AADD, 9327 reg: regInfo{ 9328 inputs: []inputInfo{ 9329 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9330 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9331 }, 9332 outputs: []outputInfo{ 9333 {1, 0}, 9334 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9335 }, 9336 }, 9337 }, 9338 { 9339 name: "SUBSshiftLL", 9340 auxType: auxInt32, 9341 argLen: 2, 9342 asm: arm.ASUB, 9343 reg: regInfo{ 9344 inputs: []inputInfo{ 9345 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9346 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9347 }, 9348 outputs: []outputInfo{ 9349 {1, 0}, 9350 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9351 }, 9352 }, 9353 }, 9354 { 9355 name: "SUBSshiftRL", 9356 auxType: auxInt32, 9357 argLen: 2, 9358 asm: arm.ASUB, 9359 reg: regInfo{ 9360 inputs: []inputInfo{ 9361 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9362 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9363 }, 9364 outputs: []outputInfo{ 9365 {1, 0}, 9366 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9367 }, 9368 }, 9369 }, 9370 { 9371 name: "SUBSshiftRA", 9372 auxType: auxInt32, 9373 argLen: 2, 9374 asm: arm.ASUB, 9375 reg: regInfo{ 9376 inputs: []inputInfo{ 9377 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9378 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9379 }, 9380 outputs: []outputInfo{ 9381 {1, 0}, 9382 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9383 }, 9384 }, 9385 }, 9386 { 9387 name: "RSBSshiftLL", 9388 auxType: auxInt32, 9389 argLen: 2, 9390 asm: arm.ARSB, 9391 reg: regInfo{ 9392 inputs: []inputInfo{ 9393 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9394 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9395 }, 9396 outputs: []outputInfo{ 9397 {1, 0}, 9398 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9399 }, 9400 }, 9401 }, 9402 { 9403 name: "RSBSshiftRL", 9404 auxType: auxInt32, 9405 argLen: 2, 9406 asm: arm.ARSB, 9407 reg: regInfo{ 9408 inputs: []inputInfo{ 9409 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9410 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9411 }, 9412 outputs: []outputInfo{ 9413 {1, 0}, 9414 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9415 }, 9416 }, 9417 }, 9418 { 9419 name: "RSBSshiftRA", 9420 auxType: auxInt32, 9421 argLen: 2, 9422 asm: arm.ARSB, 9423 reg: regInfo{ 9424 inputs: []inputInfo{ 9425 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9426 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9427 }, 9428 outputs: []outputInfo{ 9429 {1, 0}, 9430 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9431 }, 9432 }, 9433 }, 9434 { 9435 name: "ADDshiftLLreg", 9436 argLen: 3, 9437 asm: arm.AADD, 9438 reg: regInfo{ 9439 inputs: []inputInfo{ 9440 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9441 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9442 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9443 }, 9444 outputs: []outputInfo{ 9445 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9446 }, 9447 }, 9448 }, 9449 { 9450 name: "ADDshiftRLreg", 9451 argLen: 3, 9452 asm: arm.AADD, 9453 reg: regInfo{ 9454 inputs: []inputInfo{ 9455 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9456 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9457 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9458 }, 9459 outputs: []outputInfo{ 9460 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9461 }, 9462 }, 9463 }, 9464 { 9465 name: "ADDshiftRAreg", 9466 argLen: 3, 9467 asm: arm.AADD, 9468 reg: regInfo{ 9469 inputs: []inputInfo{ 9470 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9471 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9472 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9473 }, 9474 outputs: []outputInfo{ 9475 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9476 }, 9477 }, 9478 }, 9479 { 9480 name: "SUBshiftLLreg", 9481 argLen: 3, 9482 asm: arm.ASUB, 9483 reg: regInfo{ 9484 inputs: []inputInfo{ 9485 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9486 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9487 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9488 }, 9489 outputs: []outputInfo{ 9490 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9491 }, 9492 }, 9493 }, 9494 { 9495 name: "SUBshiftRLreg", 9496 argLen: 3, 9497 asm: arm.ASUB, 9498 reg: regInfo{ 9499 inputs: []inputInfo{ 9500 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9501 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9502 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9503 }, 9504 outputs: []outputInfo{ 9505 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9506 }, 9507 }, 9508 }, 9509 { 9510 name: "SUBshiftRAreg", 9511 argLen: 3, 9512 asm: arm.ASUB, 9513 reg: regInfo{ 9514 inputs: []inputInfo{ 9515 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9516 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9517 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9518 }, 9519 outputs: []outputInfo{ 9520 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9521 }, 9522 }, 9523 }, 9524 { 9525 name: "RSBshiftLLreg", 9526 argLen: 3, 9527 asm: arm.ARSB, 9528 reg: regInfo{ 9529 inputs: []inputInfo{ 9530 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9531 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9532 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9533 }, 9534 outputs: []outputInfo{ 9535 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9536 }, 9537 }, 9538 }, 9539 { 9540 name: "RSBshiftRLreg", 9541 argLen: 3, 9542 asm: arm.ARSB, 9543 reg: regInfo{ 9544 inputs: []inputInfo{ 9545 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9546 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9547 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9548 }, 9549 outputs: []outputInfo{ 9550 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9551 }, 9552 }, 9553 }, 9554 { 9555 name: "RSBshiftRAreg", 9556 argLen: 3, 9557 asm: arm.ARSB, 9558 reg: regInfo{ 9559 inputs: []inputInfo{ 9560 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9561 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9562 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9563 }, 9564 outputs: []outputInfo{ 9565 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9566 }, 9567 }, 9568 }, 9569 { 9570 name: "ANDshiftLLreg", 9571 argLen: 3, 9572 asm: arm.AAND, 9573 reg: regInfo{ 9574 inputs: []inputInfo{ 9575 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9576 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9577 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9578 }, 9579 outputs: []outputInfo{ 9580 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9581 }, 9582 }, 9583 }, 9584 { 9585 name: "ANDshiftRLreg", 9586 argLen: 3, 9587 asm: arm.AAND, 9588 reg: regInfo{ 9589 inputs: []inputInfo{ 9590 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9591 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9592 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9593 }, 9594 outputs: []outputInfo{ 9595 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9596 }, 9597 }, 9598 }, 9599 { 9600 name: "ANDshiftRAreg", 9601 argLen: 3, 9602 asm: arm.AAND, 9603 reg: regInfo{ 9604 inputs: []inputInfo{ 9605 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9606 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9607 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9608 }, 9609 outputs: []outputInfo{ 9610 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9611 }, 9612 }, 9613 }, 9614 { 9615 name: "ORshiftLLreg", 9616 argLen: 3, 9617 asm: arm.AORR, 9618 reg: regInfo{ 9619 inputs: []inputInfo{ 9620 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9621 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9622 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9623 }, 9624 outputs: []outputInfo{ 9625 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9626 }, 9627 }, 9628 }, 9629 { 9630 name: "ORshiftRLreg", 9631 argLen: 3, 9632 asm: arm.AORR, 9633 reg: regInfo{ 9634 inputs: []inputInfo{ 9635 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9636 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9637 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9638 }, 9639 outputs: []outputInfo{ 9640 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9641 }, 9642 }, 9643 }, 9644 { 9645 name: "ORshiftRAreg", 9646 argLen: 3, 9647 asm: arm.AORR, 9648 reg: regInfo{ 9649 inputs: []inputInfo{ 9650 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9651 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9652 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9653 }, 9654 outputs: []outputInfo{ 9655 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9656 }, 9657 }, 9658 }, 9659 { 9660 name: "XORshiftLLreg", 9661 argLen: 3, 9662 asm: arm.AEOR, 9663 reg: regInfo{ 9664 inputs: []inputInfo{ 9665 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9666 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9667 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9668 }, 9669 outputs: []outputInfo{ 9670 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9671 }, 9672 }, 9673 }, 9674 { 9675 name: "XORshiftRLreg", 9676 argLen: 3, 9677 asm: arm.AEOR, 9678 reg: regInfo{ 9679 inputs: []inputInfo{ 9680 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9681 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9682 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9683 }, 9684 outputs: []outputInfo{ 9685 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9686 }, 9687 }, 9688 }, 9689 { 9690 name: "XORshiftRAreg", 9691 argLen: 3, 9692 asm: arm.AEOR, 9693 reg: regInfo{ 9694 inputs: []inputInfo{ 9695 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9696 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9697 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9698 }, 9699 outputs: []outputInfo{ 9700 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9701 }, 9702 }, 9703 }, 9704 { 9705 name: "BICshiftLLreg", 9706 argLen: 3, 9707 asm: arm.ABIC, 9708 reg: regInfo{ 9709 inputs: []inputInfo{ 9710 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9711 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9712 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9713 }, 9714 outputs: []outputInfo{ 9715 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9716 }, 9717 }, 9718 }, 9719 { 9720 name: "BICshiftRLreg", 9721 argLen: 3, 9722 asm: arm.ABIC, 9723 reg: regInfo{ 9724 inputs: []inputInfo{ 9725 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9726 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9727 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9728 }, 9729 outputs: []outputInfo{ 9730 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9731 }, 9732 }, 9733 }, 9734 { 9735 name: "BICshiftRAreg", 9736 argLen: 3, 9737 asm: arm.ABIC, 9738 reg: regInfo{ 9739 inputs: []inputInfo{ 9740 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9741 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9742 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9743 }, 9744 outputs: []outputInfo{ 9745 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9746 }, 9747 }, 9748 }, 9749 { 9750 name: "MVNshiftLLreg", 9751 argLen: 2, 9752 asm: arm.AMVN, 9753 reg: regInfo{ 9754 inputs: []inputInfo{ 9755 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9756 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9757 }, 9758 outputs: []outputInfo{ 9759 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9760 }, 9761 }, 9762 }, 9763 { 9764 name: "MVNshiftRLreg", 9765 argLen: 2, 9766 asm: arm.AMVN, 9767 reg: regInfo{ 9768 inputs: []inputInfo{ 9769 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9770 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9771 }, 9772 outputs: []outputInfo{ 9773 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9774 }, 9775 }, 9776 }, 9777 { 9778 name: "MVNshiftRAreg", 9779 argLen: 2, 9780 asm: arm.AMVN, 9781 reg: regInfo{ 9782 inputs: []inputInfo{ 9783 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9784 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9785 }, 9786 outputs: []outputInfo{ 9787 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9788 }, 9789 }, 9790 }, 9791 { 9792 name: "ADCshiftLLreg", 9793 argLen: 4, 9794 asm: arm.AADC, 9795 reg: regInfo{ 9796 inputs: []inputInfo{ 9797 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9798 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9799 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9800 }, 9801 outputs: []outputInfo{ 9802 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9803 }, 9804 }, 9805 }, 9806 { 9807 name: "ADCshiftRLreg", 9808 argLen: 4, 9809 asm: arm.AADC, 9810 reg: regInfo{ 9811 inputs: []inputInfo{ 9812 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9813 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9814 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9815 }, 9816 outputs: []outputInfo{ 9817 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9818 }, 9819 }, 9820 }, 9821 { 9822 name: "ADCshiftRAreg", 9823 argLen: 4, 9824 asm: arm.AADC, 9825 reg: regInfo{ 9826 inputs: []inputInfo{ 9827 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9828 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9829 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9830 }, 9831 outputs: []outputInfo{ 9832 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9833 }, 9834 }, 9835 }, 9836 { 9837 name: "SBCshiftLLreg", 9838 argLen: 4, 9839 asm: arm.ASBC, 9840 reg: regInfo{ 9841 inputs: []inputInfo{ 9842 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9843 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9844 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9845 }, 9846 outputs: []outputInfo{ 9847 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9848 }, 9849 }, 9850 }, 9851 { 9852 name: "SBCshiftRLreg", 9853 argLen: 4, 9854 asm: arm.ASBC, 9855 reg: regInfo{ 9856 inputs: []inputInfo{ 9857 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9858 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9859 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9860 }, 9861 outputs: []outputInfo{ 9862 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9863 }, 9864 }, 9865 }, 9866 { 9867 name: "SBCshiftRAreg", 9868 argLen: 4, 9869 asm: arm.ASBC, 9870 reg: regInfo{ 9871 inputs: []inputInfo{ 9872 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9873 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9874 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9875 }, 9876 outputs: []outputInfo{ 9877 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9878 }, 9879 }, 9880 }, 9881 { 9882 name: "RSCshiftLLreg", 9883 argLen: 4, 9884 asm: arm.ARSC, 9885 reg: regInfo{ 9886 inputs: []inputInfo{ 9887 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9888 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9889 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9890 }, 9891 outputs: []outputInfo{ 9892 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9893 }, 9894 }, 9895 }, 9896 { 9897 name: "RSCshiftRLreg", 9898 argLen: 4, 9899 asm: arm.ARSC, 9900 reg: regInfo{ 9901 inputs: []inputInfo{ 9902 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9903 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9904 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9905 }, 9906 outputs: []outputInfo{ 9907 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9908 }, 9909 }, 9910 }, 9911 { 9912 name: "RSCshiftRAreg", 9913 argLen: 4, 9914 asm: arm.ARSC, 9915 reg: regInfo{ 9916 inputs: []inputInfo{ 9917 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9918 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9919 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9920 }, 9921 outputs: []outputInfo{ 9922 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9923 }, 9924 }, 9925 }, 9926 { 9927 name: "ADDSshiftLLreg", 9928 argLen: 3, 9929 asm: arm.AADD, 9930 reg: regInfo{ 9931 inputs: []inputInfo{ 9932 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9933 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9934 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9935 }, 9936 outputs: []outputInfo{ 9937 {1, 0}, 9938 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9939 }, 9940 }, 9941 }, 9942 { 9943 name: "ADDSshiftRLreg", 9944 argLen: 3, 9945 asm: arm.AADD, 9946 reg: regInfo{ 9947 inputs: []inputInfo{ 9948 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9949 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9950 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9951 }, 9952 outputs: []outputInfo{ 9953 {1, 0}, 9954 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9955 }, 9956 }, 9957 }, 9958 { 9959 name: "ADDSshiftRAreg", 9960 argLen: 3, 9961 asm: arm.AADD, 9962 reg: regInfo{ 9963 inputs: []inputInfo{ 9964 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9965 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9966 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9967 }, 9968 outputs: []outputInfo{ 9969 {1, 0}, 9970 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9971 }, 9972 }, 9973 }, 9974 { 9975 name: "SUBSshiftLLreg", 9976 argLen: 3, 9977 asm: arm.ASUB, 9978 reg: regInfo{ 9979 inputs: []inputInfo{ 9980 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9981 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9982 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9983 }, 9984 outputs: []outputInfo{ 9985 {1, 0}, 9986 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9987 }, 9988 }, 9989 }, 9990 { 9991 name: "SUBSshiftRLreg", 9992 argLen: 3, 9993 asm: arm.ASUB, 9994 reg: regInfo{ 9995 inputs: []inputInfo{ 9996 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9997 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9998 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9999 }, 10000 outputs: []outputInfo{ 10001 {1, 0}, 10002 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10003 }, 10004 }, 10005 }, 10006 { 10007 name: "SUBSshiftRAreg", 10008 argLen: 3, 10009 asm: arm.ASUB, 10010 reg: regInfo{ 10011 inputs: []inputInfo{ 10012 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10013 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10014 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10015 }, 10016 outputs: []outputInfo{ 10017 {1, 0}, 10018 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10019 }, 10020 }, 10021 }, 10022 { 10023 name: "RSBSshiftLLreg", 10024 argLen: 3, 10025 asm: arm.ARSB, 10026 reg: regInfo{ 10027 inputs: []inputInfo{ 10028 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10029 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10030 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10031 }, 10032 outputs: []outputInfo{ 10033 {1, 0}, 10034 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10035 }, 10036 }, 10037 }, 10038 { 10039 name: "RSBSshiftRLreg", 10040 argLen: 3, 10041 asm: arm.ARSB, 10042 reg: regInfo{ 10043 inputs: []inputInfo{ 10044 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10045 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10046 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10047 }, 10048 outputs: []outputInfo{ 10049 {1, 0}, 10050 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10051 }, 10052 }, 10053 }, 10054 { 10055 name: "RSBSshiftRAreg", 10056 argLen: 3, 10057 asm: arm.ARSB, 10058 reg: regInfo{ 10059 inputs: []inputInfo{ 10060 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10061 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10062 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10063 }, 10064 outputs: []outputInfo{ 10065 {1, 0}, 10066 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10067 }, 10068 }, 10069 }, 10070 { 10071 name: "CMP", 10072 argLen: 2, 10073 asm: arm.ACMP, 10074 reg: regInfo{ 10075 inputs: []inputInfo{ 10076 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10077 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10078 }, 10079 }, 10080 }, 10081 { 10082 name: "CMPconst", 10083 auxType: auxInt32, 10084 argLen: 1, 10085 asm: arm.ACMP, 10086 reg: regInfo{ 10087 inputs: []inputInfo{ 10088 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10089 }, 10090 }, 10091 }, 10092 { 10093 name: "CMN", 10094 argLen: 2, 10095 asm: arm.ACMN, 10096 reg: regInfo{ 10097 inputs: []inputInfo{ 10098 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10099 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10100 }, 10101 }, 10102 }, 10103 { 10104 name: "CMNconst", 10105 auxType: auxInt32, 10106 argLen: 1, 10107 asm: arm.ACMN, 10108 reg: regInfo{ 10109 inputs: []inputInfo{ 10110 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10111 }, 10112 }, 10113 }, 10114 { 10115 name: "TST", 10116 argLen: 2, 10117 commutative: true, 10118 asm: arm.ATST, 10119 reg: regInfo{ 10120 inputs: []inputInfo{ 10121 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10122 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10123 }, 10124 }, 10125 }, 10126 { 10127 name: "TSTconst", 10128 auxType: auxInt32, 10129 argLen: 1, 10130 asm: arm.ATST, 10131 reg: regInfo{ 10132 inputs: []inputInfo{ 10133 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10134 }, 10135 }, 10136 }, 10137 { 10138 name: "TEQ", 10139 argLen: 2, 10140 commutative: true, 10141 asm: arm.ATEQ, 10142 reg: regInfo{ 10143 inputs: []inputInfo{ 10144 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10145 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10146 }, 10147 }, 10148 }, 10149 { 10150 name: "TEQconst", 10151 auxType: auxInt32, 10152 argLen: 1, 10153 asm: arm.ATEQ, 10154 reg: regInfo{ 10155 inputs: []inputInfo{ 10156 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10157 }, 10158 }, 10159 }, 10160 { 10161 name: "CMPF", 10162 argLen: 2, 10163 asm: arm.ACMPF, 10164 reg: regInfo{ 10165 inputs: []inputInfo{ 10166 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10167 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10168 }, 10169 }, 10170 }, 10171 { 10172 name: "CMPD", 10173 argLen: 2, 10174 asm: arm.ACMPD, 10175 reg: regInfo{ 10176 inputs: []inputInfo{ 10177 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10178 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10179 }, 10180 }, 10181 }, 10182 { 10183 name: "CMPshiftLL", 10184 auxType: auxInt32, 10185 argLen: 2, 10186 asm: arm.ACMP, 10187 reg: regInfo{ 10188 inputs: []inputInfo{ 10189 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10190 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10191 }, 10192 }, 10193 }, 10194 { 10195 name: "CMPshiftRL", 10196 auxType: auxInt32, 10197 argLen: 2, 10198 asm: arm.ACMP, 10199 reg: regInfo{ 10200 inputs: []inputInfo{ 10201 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10202 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10203 }, 10204 }, 10205 }, 10206 { 10207 name: "CMPshiftRA", 10208 auxType: auxInt32, 10209 argLen: 2, 10210 asm: arm.ACMP, 10211 reg: regInfo{ 10212 inputs: []inputInfo{ 10213 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10214 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10215 }, 10216 }, 10217 }, 10218 { 10219 name: "CMPshiftLLreg", 10220 argLen: 3, 10221 asm: arm.ACMP, 10222 reg: regInfo{ 10223 inputs: []inputInfo{ 10224 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10225 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10226 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10227 }, 10228 }, 10229 }, 10230 { 10231 name: "CMPshiftRLreg", 10232 argLen: 3, 10233 asm: arm.ACMP, 10234 reg: regInfo{ 10235 inputs: []inputInfo{ 10236 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10237 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10238 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10239 }, 10240 }, 10241 }, 10242 { 10243 name: "CMPshiftRAreg", 10244 argLen: 3, 10245 asm: arm.ACMP, 10246 reg: regInfo{ 10247 inputs: []inputInfo{ 10248 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10249 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10250 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10251 }, 10252 }, 10253 }, 10254 { 10255 name: "CMPF0", 10256 argLen: 1, 10257 asm: arm.ACMPF, 10258 reg: regInfo{ 10259 inputs: []inputInfo{ 10260 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10261 }, 10262 }, 10263 }, 10264 { 10265 name: "CMPD0", 10266 argLen: 1, 10267 asm: arm.ACMPD, 10268 reg: regInfo{ 10269 inputs: []inputInfo{ 10270 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10271 }, 10272 }, 10273 }, 10274 { 10275 name: "MOVWconst", 10276 auxType: auxInt32, 10277 argLen: 0, 10278 rematerializeable: true, 10279 asm: arm.AMOVW, 10280 reg: regInfo{ 10281 outputs: []outputInfo{ 10282 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10283 }, 10284 }, 10285 }, 10286 { 10287 name: "MOVFconst", 10288 auxType: auxFloat64, 10289 argLen: 0, 10290 rematerializeable: true, 10291 asm: arm.AMOVF, 10292 reg: regInfo{ 10293 outputs: []outputInfo{ 10294 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10295 }, 10296 }, 10297 }, 10298 { 10299 name: "MOVDconst", 10300 auxType: auxFloat64, 10301 argLen: 0, 10302 rematerializeable: true, 10303 asm: arm.AMOVD, 10304 reg: regInfo{ 10305 outputs: []outputInfo{ 10306 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10307 }, 10308 }, 10309 }, 10310 { 10311 name: "MOVWaddr", 10312 auxType: auxSymOff, 10313 argLen: 1, 10314 rematerializeable: true, 10315 symEffect: SymAddr, 10316 asm: arm.AMOVW, 10317 reg: regInfo{ 10318 inputs: []inputInfo{ 10319 {0, 4294975488}, // SP SB 10320 }, 10321 outputs: []outputInfo{ 10322 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10323 }, 10324 }, 10325 }, 10326 { 10327 name: "MOVBload", 10328 auxType: auxSymOff, 10329 argLen: 2, 10330 faultOnNilArg0: true, 10331 symEffect: SymRead, 10332 asm: arm.AMOVB, 10333 reg: regInfo{ 10334 inputs: []inputInfo{ 10335 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10336 }, 10337 outputs: []outputInfo{ 10338 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10339 }, 10340 }, 10341 }, 10342 { 10343 name: "MOVBUload", 10344 auxType: auxSymOff, 10345 argLen: 2, 10346 faultOnNilArg0: true, 10347 symEffect: SymRead, 10348 asm: arm.AMOVBU, 10349 reg: regInfo{ 10350 inputs: []inputInfo{ 10351 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10352 }, 10353 outputs: []outputInfo{ 10354 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10355 }, 10356 }, 10357 }, 10358 { 10359 name: "MOVHload", 10360 auxType: auxSymOff, 10361 argLen: 2, 10362 faultOnNilArg0: true, 10363 symEffect: SymRead, 10364 asm: arm.AMOVH, 10365 reg: regInfo{ 10366 inputs: []inputInfo{ 10367 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10368 }, 10369 outputs: []outputInfo{ 10370 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10371 }, 10372 }, 10373 }, 10374 { 10375 name: "MOVHUload", 10376 auxType: auxSymOff, 10377 argLen: 2, 10378 faultOnNilArg0: true, 10379 symEffect: SymRead, 10380 asm: arm.AMOVHU, 10381 reg: regInfo{ 10382 inputs: []inputInfo{ 10383 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10384 }, 10385 outputs: []outputInfo{ 10386 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10387 }, 10388 }, 10389 }, 10390 { 10391 name: "MOVWload", 10392 auxType: auxSymOff, 10393 argLen: 2, 10394 faultOnNilArg0: true, 10395 symEffect: SymRead, 10396 asm: arm.AMOVW, 10397 reg: regInfo{ 10398 inputs: []inputInfo{ 10399 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10400 }, 10401 outputs: []outputInfo{ 10402 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10403 }, 10404 }, 10405 }, 10406 { 10407 name: "MOVFload", 10408 auxType: auxSymOff, 10409 argLen: 2, 10410 faultOnNilArg0: true, 10411 symEffect: SymRead, 10412 asm: arm.AMOVF, 10413 reg: regInfo{ 10414 inputs: []inputInfo{ 10415 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10416 }, 10417 outputs: []outputInfo{ 10418 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10419 }, 10420 }, 10421 }, 10422 { 10423 name: "MOVDload", 10424 auxType: auxSymOff, 10425 argLen: 2, 10426 faultOnNilArg0: true, 10427 symEffect: SymRead, 10428 asm: arm.AMOVD, 10429 reg: regInfo{ 10430 inputs: []inputInfo{ 10431 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10432 }, 10433 outputs: []outputInfo{ 10434 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10435 }, 10436 }, 10437 }, 10438 { 10439 name: "MOVBstore", 10440 auxType: auxSymOff, 10441 argLen: 3, 10442 faultOnNilArg0: true, 10443 symEffect: SymWrite, 10444 asm: arm.AMOVB, 10445 reg: regInfo{ 10446 inputs: []inputInfo{ 10447 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10448 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10449 }, 10450 }, 10451 }, 10452 { 10453 name: "MOVHstore", 10454 auxType: auxSymOff, 10455 argLen: 3, 10456 faultOnNilArg0: true, 10457 symEffect: SymWrite, 10458 asm: arm.AMOVH, 10459 reg: regInfo{ 10460 inputs: []inputInfo{ 10461 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10462 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10463 }, 10464 }, 10465 }, 10466 { 10467 name: "MOVWstore", 10468 auxType: auxSymOff, 10469 argLen: 3, 10470 faultOnNilArg0: true, 10471 symEffect: SymWrite, 10472 asm: arm.AMOVW, 10473 reg: regInfo{ 10474 inputs: []inputInfo{ 10475 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10476 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10477 }, 10478 }, 10479 }, 10480 { 10481 name: "MOVFstore", 10482 auxType: auxSymOff, 10483 argLen: 3, 10484 faultOnNilArg0: true, 10485 symEffect: SymWrite, 10486 asm: arm.AMOVF, 10487 reg: regInfo{ 10488 inputs: []inputInfo{ 10489 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10490 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10491 }, 10492 }, 10493 }, 10494 { 10495 name: "MOVDstore", 10496 auxType: auxSymOff, 10497 argLen: 3, 10498 faultOnNilArg0: true, 10499 symEffect: SymWrite, 10500 asm: arm.AMOVD, 10501 reg: regInfo{ 10502 inputs: []inputInfo{ 10503 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10504 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10505 }, 10506 }, 10507 }, 10508 { 10509 name: "MOVWloadidx", 10510 argLen: 3, 10511 asm: arm.AMOVW, 10512 reg: regInfo{ 10513 inputs: []inputInfo{ 10514 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10515 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10516 }, 10517 outputs: []outputInfo{ 10518 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10519 }, 10520 }, 10521 }, 10522 { 10523 name: "MOVWloadshiftLL", 10524 auxType: auxInt32, 10525 argLen: 3, 10526 asm: arm.AMOVW, 10527 reg: regInfo{ 10528 inputs: []inputInfo{ 10529 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10530 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10531 }, 10532 outputs: []outputInfo{ 10533 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10534 }, 10535 }, 10536 }, 10537 { 10538 name: "MOVWloadshiftRL", 10539 auxType: auxInt32, 10540 argLen: 3, 10541 asm: arm.AMOVW, 10542 reg: regInfo{ 10543 inputs: []inputInfo{ 10544 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10545 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10546 }, 10547 outputs: []outputInfo{ 10548 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10549 }, 10550 }, 10551 }, 10552 { 10553 name: "MOVWloadshiftRA", 10554 auxType: auxInt32, 10555 argLen: 3, 10556 asm: arm.AMOVW, 10557 reg: regInfo{ 10558 inputs: []inputInfo{ 10559 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10560 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10561 }, 10562 outputs: []outputInfo{ 10563 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10564 }, 10565 }, 10566 }, 10567 { 10568 name: "MOVWstoreidx", 10569 argLen: 4, 10570 asm: arm.AMOVW, 10571 reg: regInfo{ 10572 inputs: []inputInfo{ 10573 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10574 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10575 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10576 }, 10577 }, 10578 }, 10579 { 10580 name: "MOVWstoreshiftLL", 10581 auxType: auxInt32, 10582 argLen: 4, 10583 asm: arm.AMOVW, 10584 reg: regInfo{ 10585 inputs: []inputInfo{ 10586 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10587 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10588 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10589 }, 10590 }, 10591 }, 10592 { 10593 name: "MOVWstoreshiftRL", 10594 auxType: auxInt32, 10595 argLen: 4, 10596 asm: arm.AMOVW, 10597 reg: regInfo{ 10598 inputs: []inputInfo{ 10599 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10600 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10601 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10602 }, 10603 }, 10604 }, 10605 { 10606 name: "MOVWstoreshiftRA", 10607 auxType: auxInt32, 10608 argLen: 4, 10609 asm: arm.AMOVW, 10610 reg: regInfo{ 10611 inputs: []inputInfo{ 10612 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10613 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10614 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10615 }, 10616 }, 10617 }, 10618 { 10619 name: "MOVBreg", 10620 argLen: 1, 10621 asm: arm.AMOVBS, 10622 reg: regInfo{ 10623 inputs: []inputInfo{ 10624 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10625 }, 10626 outputs: []outputInfo{ 10627 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10628 }, 10629 }, 10630 }, 10631 { 10632 name: "MOVBUreg", 10633 argLen: 1, 10634 asm: arm.AMOVBU, 10635 reg: regInfo{ 10636 inputs: []inputInfo{ 10637 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10638 }, 10639 outputs: []outputInfo{ 10640 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10641 }, 10642 }, 10643 }, 10644 { 10645 name: "MOVHreg", 10646 argLen: 1, 10647 asm: arm.AMOVHS, 10648 reg: regInfo{ 10649 inputs: []inputInfo{ 10650 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10651 }, 10652 outputs: []outputInfo{ 10653 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10654 }, 10655 }, 10656 }, 10657 { 10658 name: "MOVHUreg", 10659 argLen: 1, 10660 asm: arm.AMOVHU, 10661 reg: regInfo{ 10662 inputs: []inputInfo{ 10663 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10664 }, 10665 outputs: []outputInfo{ 10666 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10667 }, 10668 }, 10669 }, 10670 { 10671 name: "MOVWreg", 10672 argLen: 1, 10673 asm: arm.AMOVW, 10674 reg: regInfo{ 10675 inputs: []inputInfo{ 10676 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10677 }, 10678 outputs: []outputInfo{ 10679 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10680 }, 10681 }, 10682 }, 10683 { 10684 name: "MOVWnop", 10685 argLen: 1, 10686 resultInArg0: true, 10687 reg: regInfo{ 10688 inputs: []inputInfo{ 10689 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10690 }, 10691 outputs: []outputInfo{ 10692 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10693 }, 10694 }, 10695 }, 10696 { 10697 name: "MOVWF", 10698 argLen: 1, 10699 asm: arm.AMOVWF, 10700 reg: regInfo{ 10701 inputs: []inputInfo{ 10702 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10703 }, 10704 clobbers: 2147483648, // F15 10705 outputs: []outputInfo{ 10706 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10707 }, 10708 }, 10709 }, 10710 { 10711 name: "MOVWD", 10712 argLen: 1, 10713 asm: arm.AMOVWD, 10714 reg: regInfo{ 10715 inputs: []inputInfo{ 10716 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10717 }, 10718 clobbers: 2147483648, // F15 10719 outputs: []outputInfo{ 10720 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10721 }, 10722 }, 10723 }, 10724 { 10725 name: "MOVWUF", 10726 argLen: 1, 10727 asm: arm.AMOVWF, 10728 reg: regInfo{ 10729 inputs: []inputInfo{ 10730 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10731 }, 10732 clobbers: 2147483648, // F15 10733 outputs: []outputInfo{ 10734 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10735 }, 10736 }, 10737 }, 10738 { 10739 name: "MOVWUD", 10740 argLen: 1, 10741 asm: arm.AMOVWD, 10742 reg: regInfo{ 10743 inputs: []inputInfo{ 10744 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10745 }, 10746 clobbers: 2147483648, // F15 10747 outputs: []outputInfo{ 10748 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10749 }, 10750 }, 10751 }, 10752 { 10753 name: "MOVFW", 10754 argLen: 1, 10755 asm: arm.AMOVFW, 10756 reg: regInfo{ 10757 inputs: []inputInfo{ 10758 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10759 }, 10760 clobbers: 2147483648, // F15 10761 outputs: []outputInfo{ 10762 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10763 }, 10764 }, 10765 }, 10766 { 10767 name: "MOVDW", 10768 argLen: 1, 10769 asm: arm.AMOVDW, 10770 reg: regInfo{ 10771 inputs: []inputInfo{ 10772 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10773 }, 10774 clobbers: 2147483648, // F15 10775 outputs: []outputInfo{ 10776 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10777 }, 10778 }, 10779 }, 10780 { 10781 name: "MOVFWU", 10782 argLen: 1, 10783 asm: arm.AMOVFW, 10784 reg: regInfo{ 10785 inputs: []inputInfo{ 10786 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10787 }, 10788 clobbers: 2147483648, // F15 10789 outputs: []outputInfo{ 10790 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10791 }, 10792 }, 10793 }, 10794 { 10795 name: "MOVDWU", 10796 argLen: 1, 10797 asm: arm.AMOVDW, 10798 reg: regInfo{ 10799 inputs: []inputInfo{ 10800 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10801 }, 10802 clobbers: 2147483648, // F15 10803 outputs: []outputInfo{ 10804 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10805 }, 10806 }, 10807 }, 10808 { 10809 name: "MOVFD", 10810 argLen: 1, 10811 asm: arm.AMOVFD, 10812 reg: regInfo{ 10813 inputs: []inputInfo{ 10814 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10815 }, 10816 outputs: []outputInfo{ 10817 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10818 }, 10819 }, 10820 }, 10821 { 10822 name: "MOVDF", 10823 argLen: 1, 10824 asm: arm.AMOVDF, 10825 reg: regInfo{ 10826 inputs: []inputInfo{ 10827 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10828 }, 10829 outputs: []outputInfo{ 10830 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10831 }, 10832 }, 10833 }, 10834 { 10835 name: "CMOVWHSconst", 10836 auxType: auxInt32, 10837 argLen: 2, 10838 resultInArg0: true, 10839 asm: arm.AMOVW, 10840 reg: regInfo{ 10841 inputs: []inputInfo{ 10842 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10843 }, 10844 outputs: []outputInfo{ 10845 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10846 }, 10847 }, 10848 }, 10849 { 10850 name: "CMOVWLSconst", 10851 auxType: auxInt32, 10852 argLen: 2, 10853 resultInArg0: true, 10854 asm: arm.AMOVW, 10855 reg: regInfo{ 10856 inputs: []inputInfo{ 10857 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10858 }, 10859 outputs: []outputInfo{ 10860 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10861 }, 10862 }, 10863 }, 10864 { 10865 name: "SRAcond", 10866 argLen: 3, 10867 asm: arm.ASRA, 10868 reg: regInfo{ 10869 inputs: []inputInfo{ 10870 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10871 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10872 }, 10873 outputs: []outputInfo{ 10874 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10875 }, 10876 }, 10877 }, 10878 { 10879 name: "CALLstatic", 10880 auxType: auxSymOff, 10881 argLen: 1, 10882 clobberFlags: true, 10883 call: true, 10884 symEffect: SymNone, 10885 reg: regInfo{ 10886 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10887 }, 10888 }, 10889 { 10890 name: "CALLclosure", 10891 auxType: auxInt64, 10892 argLen: 3, 10893 clobberFlags: true, 10894 call: true, 10895 reg: regInfo{ 10896 inputs: []inputInfo{ 10897 {1, 128}, // R7 10898 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 10899 }, 10900 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10901 }, 10902 }, 10903 { 10904 name: "CALLinter", 10905 auxType: auxInt64, 10906 argLen: 2, 10907 clobberFlags: true, 10908 call: true, 10909 reg: regInfo{ 10910 inputs: []inputInfo{ 10911 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10912 }, 10913 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10914 }, 10915 }, 10916 { 10917 name: "LoweredNilCheck", 10918 argLen: 2, 10919 nilCheck: true, 10920 faultOnNilArg0: true, 10921 reg: regInfo{ 10922 inputs: []inputInfo{ 10923 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10924 }, 10925 }, 10926 }, 10927 { 10928 name: "Equal", 10929 argLen: 1, 10930 reg: regInfo{ 10931 outputs: []outputInfo{ 10932 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10933 }, 10934 }, 10935 }, 10936 { 10937 name: "NotEqual", 10938 argLen: 1, 10939 reg: regInfo{ 10940 outputs: []outputInfo{ 10941 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10942 }, 10943 }, 10944 }, 10945 { 10946 name: "LessThan", 10947 argLen: 1, 10948 reg: regInfo{ 10949 outputs: []outputInfo{ 10950 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10951 }, 10952 }, 10953 }, 10954 { 10955 name: "LessEqual", 10956 argLen: 1, 10957 reg: regInfo{ 10958 outputs: []outputInfo{ 10959 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10960 }, 10961 }, 10962 }, 10963 { 10964 name: "GreaterThan", 10965 argLen: 1, 10966 reg: regInfo{ 10967 outputs: []outputInfo{ 10968 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10969 }, 10970 }, 10971 }, 10972 { 10973 name: "GreaterEqual", 10974 argLen: 1, 10975 reg: regInfo{ 10976 outputs: []outputInfo{ 10977 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10978 }, 10979 }, 10980 }, 10981 { 10982 name: "LessThanU", 10983 argLen: 1, 10984 reg: regInfo{ 10985 outputs: []outputInfo{ 10986 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10987 }, 10988 }, 10989 }, 10990 { 10991 name: "LessEqualU", 10992 argLen: 1, 10993 reg: regInfo{ 10994 outputs: []outputInfo{ 10995 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10996 }, 10997 }, 10998 }, 10999 { 11000 name: "GreaterThanU", 11001 argLen: 1, 11002 reg: regInfo{ 11003 outputs: []outputInfo{ 11004 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11005 }, 11006 }, 11007 }, 11008 { 11009 name: "GreaterEqualU", 11010 argLen: 1, 11011 reg: regInfo{ 11012 outputs: []outputInfo{ 11013 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11014 }, 11015 }, 11016 }, 11017 { 11018 name: "DUFFZERO", 11019 auxType: auxInt64, 11020 argLen: 3, 11021 faultOnNilArg0: true, 11022 reg: regInfo{ 11023 inputs: []inputInfo{ 11024 {0, 2}, // R1 11025 {1, 1}, // R0 11026 }, 11027 clobbers: 16386, // R1 R14 11028 }, 11029 }, 11030 { 11031 name: "DUFFCOPY", 11032 auxType: auxInt64, 11033 argLen: 3, 11034 faultOnNilArg0: true, 11035 faultOnNilArg1: true, 11036 reg: regInfo{ 11037 inputs: []inputInfo{ 11038 {0, 4}, // R2 11039 {1, 2}, // R1 11040 }, 11041 clobbers: 16391, // R0 R1 R2 R14 11042 }, 11043 }, 11044 { 11045 name: "LoweredZero", 11046 auxType: auxInt64, 11047 argLen: 4, 11048 clobberFlags: true, 11049 faultOnNilArg0: true, 11050 reg: regInfo{ 11051 inputs: []inputInfo{ 11052 {0, 2}, // R1 11053 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11054 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11055 }, 11056 clobbers: 2, // R1 11057 }, 11058 }, 11059 { 11060 name: "LoweredMove", 11061 auxType: auxInt64, 11062 argLen: 4, 11063 clobberFlags: true, 11064 faultOnNilArg0: true, 11065 faultOnNilArg1: true, 11066 reg: regInfo{ 11067 inputs: []inputInfo{ 11068 {0, 4}, // R2 11069 {1, 2}, // R1 11070 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11071 }, 11072 clobbers: 6, // R1 R2 11073 }, 11074 }, 11075 { 11076 name: "LoweredGetClosurePtr", 11077 argLen: 0, 11078 reg: regInfo{ 11079 outputs: []outputInfo{ 11080 {0, 128}, // R7 11081 }, 11082 }, 11083 }, 11084 { 11085 name: "MOVWconvert", 11086 argLen: 2, 11087 asm: arm.AMOVW, 11088 reg: regInfo{ 11089 inputs: []inputInfo{ 11090 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11091 }, 11092 outputs: []outputInfo{ 11093 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11094 }, 11095 }, 11096 }, 11097 { 11098 name: "FlagEQ", 11099 argLen: 0, 11100 reg: regInfo{}, 11101 }, 11102 { 11103 name: "FlagLT_ULT", 11104 argLen: 0, 11105 reg: regInfo{}, 11106 }, 11107 { 11108 name: "FlagLT_UGT", 11109 argLen: 0, 11110 reg: regInfo{}, 11111 }, 11112 { 11113 name: "FlagGT_UGT", 11114 argLen: 0, 11115 reg: regInfo{}, 11116 }, 11117 { 11118 name: "FlagGT_ULT", 11119 argLen: 0, 11120 reg: regInfo{}, 11121 }, 11122 { 11123 name: "InvertFlags", 11124 argLen: 1, 11125 reg: regInfo{}, 11126 }, 11127 11128 { 11129 name: "ADD", 11130 argLen: 2, 11131 commutative: true, 11132 asm: arm64.AADD, 11133 reg: regInfo{ 11134 inputs: []inputInfo{ 11135 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11136 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11137 }, 11138 outputs: []outputInfo{ 11139 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11140 }, 11141 }, 11142 }, 11143 { 11144 name: "ADDconst", 11145 auxType: auxInt64, 11146 argLen: 1, 11147 asm: arm64.AADD, 11148 reg: regInfo{ 11149 inputs: []inputInfo{ 11150 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 11151 }, 11152 outputs: []outputInfo{ 11153 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11154 }, 11155 }, 11156 }, 11157 { 11158 name: "SUB", 11159 argLen: 2, 11160 asm: arm64.ASUB, 11161 reg: regInfo{ 11162 inputs: []inputInfo{ 11163 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11164 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11165 }, 11166 outputs: []outputInfo{ 11167 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11168 }, 11169 }, 11170 }, 11171 { 11172 name: "SUBconst", 11173 auxType: auxInt64, 11174 argLen: 1, 11175 asm: arm64.ASUB, 11176 reg: regInfo{ 11177 inputs: []inputInfo{ 11178 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11179 }, 11180 outputs: []outputInfo{ 11181 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11182 }, 11183 }, 11184 }, 11185 { 11186 name: "MUL", 11187 argLen: 2, 11188 commutative: true, 11189 asm: arm64.AMUL, 11190 reg: regInfo{ 11191 inputs: []inputInfo{ 11192 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11193 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11194 }, 11195 outputs: []outputInfo{ 11196 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11197 }, 11198 }, 11199 }, 11200 { 11201 name: "MULW", 11202 argLen: 2, 11203 commutative: true, 11204 asm: arm64.AMULW, 11205 reg: regInfo{ 11206 inputs: []inputInfo{ 11207 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11208 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11209 }, 11210 outputs: []outputInfo{ 11211 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11212 }, 11213 }, 11214 }, 11215 { 11216 name: "MULH", 11217 argLen: 2, 11218 commutative: true, 11219 asm: arm64.ASMULH, 11220 reg: regInfo{ 11221 inputs: []inputInfo{ 11222 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11223 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11224 }, 11225 outputs: []outputInfo{ 11226 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11227 }, 11228 }, 11229 }, 11230 { 11231 name: "UMULH", 11232 argLen: 2, 11233 commutative: true, 11234 asm: arm64.AUMULH, 11235 reg: regInfo{ 11236 inputs: []inputInfo{ 11237 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11238 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11239 }, 11240 outputs: []outputInfo{ 11241 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11242 }, 11243 }, 11244 }, 11245 { 11246 name: "MULL", 11247 argLen: 2, 11248 commutative: true, 11249 asm: arm64.ASMULL, 11250 reg: regInfo{ 11251 inputs: []inputInfo{ 11252 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11253 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11254 }, 11255 outputs: []outputInfo{ 11256 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11257 }, 11258 }, 11259 }, 11260 { 11261 name: "UMULL", 11262 argLen: 2, 11263 commutative: true, 11264 asm: arm64.AUMULL, 11265 reg: regInfo{ 11266 inputs: []inputInfo{ 11267 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11268 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11269 }, 11270 outputs: []outputInfo{ 11271 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11272 }, 11273 }, 11274 }, 11275 { 11276 name: "DIV", 11277 argLen: 2, 11278 asm: arm64.ASDIV, 11279 reg: regInfo{ 11280 inputs: []inputInfo{ 11281 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11282 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11283 }, 11284 outputs: []outputInfo{ 11285 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11286 }, 11287 }, 11288 }, 11289 { 11290 name: "UDIV", 11291 argLen: 2, 11292 asm: arm64.AUDIV, 11293 reg: regInfo{ 11294 inputs: []inputInfo{ 11295 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11296 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11297 }, 11298 outputs: []outputInfo{ 11299 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11300 }, 11301 }, 11302 }, 11303 { 11304 name: "DIVW", 11305 argLen: 2, 11306 asm: arm64.ASDIVW, 11307 reg: regInfo{ 11308 inputs: []inputInfo{ 11309 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11310 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11311 }, 11312 outputs: []outputInfo{ 11313 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11314 }, 11315 }, 11316 }, 11317 { 11318 name: "UDIVW", 11319 argLen: 2, 11320 asm: arm64.AUDIVW, 11321 reg: regInfo{ 11322 inputs: []inputInfo{ 11323 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11324 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11325 }, 11326 outputs: []outputInfo{ 11327 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11328 }, 11329 }, 11330 }, 11331 { 11332 name: "MOD", 11333 argLen: 2, 11334 asm: arm64.AREM, 11335 reg: regInfo{ 11336 inputs: []inputInfo{ 11337 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11338 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11339 }, 11340 outputs: []outputInfo{ 11341 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11342 }, 11343 }, 11344 }, 11345 { 11346 name: "UMOD", 11347 argLen: 2, 11348 asm: arm64.AUREM, 11349 reg: regInfo{ 11350 inputs: []inputInfo{ 11351 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11352 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11353 }, 11354 outputs: []outputInfo{ 11355 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11356 }, 11357 }, 11358 }, 11359 { 11360 name: "MODW", 11361 argLen: 2, 11362 asm: arm64.AREMW, 11363 reg: regInfo{ 11364 inputs: []inputInfo{ 11365 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11366 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11367 }, 11368 outputs: []outputInfo{ 11369 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11370 }, 11371 }, 11372 }, 11373 { 11374 name: "UMODW", 11375 argLen: 2, 11376 asm: arm64.AUREMW, 11377 reg: regInfo{ 11378 inputs: []inputInfo{ 11379 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11380 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11381 }, 11382 outputs: []outputInfo{ 11383 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11384 }, 11385 }, 11386 }, 11387 { 11388 name: "FADDS", 11389 argLen: 2, 11390 commutative: true, 11391 asm: arm64.AFADDS, 11392 reg: regInfo{ 11393 inputs: []inputInfo{ 11394 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11395 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11396 }, 11397 outputs: []outputInfo{ 11398 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11399 }, 11400 }, 11401 }, 11402 { 11403 name: "FADDD", 11404 argLen: 2, 11405 commutative: true, 11406 asm: arm64.AFADDD, 11407 reg: regInfo{ 11408 inputs: []inputInfo{ 11409 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11410 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11411 }, 11412 outputs: []outputInfo{ 11413 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11414 }, 11415 }, 11416 }, 11417 { 11418 name: "FSUBS", 11419 argLen: 2, 11420 asm: arm64.AFSUBS, 11421 reg: regInfo{ 11422 inputs: []inputInfo{ 11423 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11424 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11425 }, 11426 outputs: []outputInfo{ 11427 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11428 }, 11429 }, 11430 }, 11431 { 11432 name: "FSUBD", 11433 argLen: 2, 11434 asm: arm64.AFSUBD, 11435 reg: regInfo{ 11436 inputs: []inputInfo{ 11437 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11438 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11439 }, 11440 outputs: []outputInfo{ 11441 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11442 }, 11443 }, 11444 }, 11445 { 11446 name: "FMULS", 11447 argLen: 2, 11448 commutative: true, 11449 asm: arm64.AFMULS, 11450 reg: regInfo{ 11451 inputs: []inputInfo{ 11452 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11453 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11454 }, 11455 outputs: []outputInfo{ 11456 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11457 }, 11458 }, 11459 }, 11460 { 11461 name: "FMULD", 11462 argLen: 2, 11463 commutative: true, 11464 asm: arm64.AFMULD, 11465 reg: regInfo{ 11466 inputs: []inputInfo{ 11467 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11468 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11469 }, 11470 outputs: []outputInfo{ 11471 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11472 }, 11473 }, 11474 }, 11475 { 11476 name: "FDIVS", 11477 argLen: 2, 11478 asm: arm64.AFDIVS, 11479 reg: regInfo{ 11480 inputs: []inputInfo{ 11481 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11482 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11483 }, 11484 outputs: []outputInfo{ 11485 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11486 }, 11487 }, 11488 }, 11489 { 11490 name: "FDIVD", 11491 argLen: 2, 11492 asm: arm64.AFDIVD, 11493 reg: regInfo{ 11494 inputs: []inputInfo{ 11495 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11496 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11497 }, 11498 outputs: []outputInfo{ 11499 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11500 }, 11501 }, 11502 }, 11503 { 11504 name: "AND", 11505 argLen: 2, 11506 commutative: true, 11507 asm: arm64.AAND, 11508 reg: regInfo{ 11509 inputs: []inputInfo{ 11510 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11511 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11512 }, 11513 outputs: []outputInfo{ 11514 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11515 }, 11516 }, 11517 }, 11518 { 11519 name: "ANDconst", 11520 auxType: auxInt64, 11521 argLen: 1, 11522 asm: arm64.AAND, 11523 reg: regInfo{ 11524 inputs: []inputInfo{ 11525 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11526 }, 11527 outputs: []outputInfo{ 11528 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11529 }, 11530 }, 11531 }, 11532 { 11533 name: "OR", 11534 argLen: 2, 11535 commutative: true, 11536 asm: arm64.AORR, 11537 reg: regInfo{ 11538 inputs: []inputInfo{ 11539 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11540 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11541 }, 11542 outputs: []outputInfo{ 11543 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11544 }, 11545 }, 11546 }, 11547 { 11548 name: "ORconst", 11549 auxType: auxInt64, 11550 argLen: 1, 11551 asm: arm64.AORR, 11552 reg: regInfo{ 11553 inputs: []inputInfo{ 11554 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11555 }, 11556 outputs: []outputInfo{ 11557 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11558 }, 11559 }, 11560 }, 11561 { 11562 name: "XOR", 11563 argLen: 2, 11564 commutative: true, 11565 asm: arm64.AEOR, 11566 reg: regInfo{ 11567 inputs: []inputInfo{ 11568 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11569 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11570 }, 11571 outputs: []outputInfo{ 11572 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11573 }, 11574 }, 11575 }, 11576 { 11577 name: "XORconst", 11578 auxType: auxInt64, 11579 argLen: 1, 11580 asm: arm64.AEOR, 11581 reg: regInfo{ 11582 inputs: []inputInfo{ 11583 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11584 }, 11585 outputs: []outputInfo{ 11586 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11587 }, 11588 }, 11589 }, 11590 { 11591 name: "BIC", 11592 argLen: 2, 11593 asm: arm64.ABIC, 11594 reg: regInfo{ 11595 inputs: []inputInfo{ 11596 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11597 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11598 }, 11599 outputs: []outputInfo{ 11600 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11601 }, 11602 }, 11603 }, 11604 { 11605 name: "BICconst", 11606 auxType: auxInt64, 11607 argLen: 1, 11608 asm: arm64.ABIC, 11609 reg: regInfo{ 11610 inputs: []inputInfo{ 11611 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11612 }, 11613 outputs: []outputInfo{ 11614 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11615 }, 11616 }, 11617 }, 11618 { 11619 name: "MVN", 11620 argLen: 1, 11621 asm: arm64.AMVN, 11622 reg: regInfo{ 11623 inputs: []inputInfo{ 11624 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11625 }, 11626 outputs: []outputInfo{ 11627 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11628 }, 11629 }, 11630 }, 11631 { 11632 name: "NEG", 11633 argLen: 1, 11634 asm: arm64.ANEG, 11635 reg: regInfo{ 11636 inputs: []inputInfo{ 11637 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11638 }, 11639 outputs: []outputInfo{ 11640 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11641 }, 11642 }, 11643 }, 11644 { 11645 name: "FNEGS", 11646 argLen: 1, 11647 asm: arm64.AFNEGS, 11648 reg: regInfo{ 11649 inputs: []inputInfo{ 11650 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11651 }, 11652 outputs: []outputInfo{ 11653 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11654 }, 11655 }, 11656 }, 11657 { 11658 name: "FNEGD", 11659 argLen: 1, 11660 asm: arm64.AFNEGD, 11661 reg: regInfo{ 11662 inputs: []inputInfo{ 11663 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11664 }, 11665 outputs: []outputInfo{ 11666 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11667 }, 11668 }, 11669 }, 11670 { 11671 name: "FSQRTD", 11672 argLen: 1, 11673 asm: arm64.AFSQRTD, 11674 reg: regInfo{ 11675 inputs: []inputInfo{ 11676 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11677 }, 11678 outputs: []outputInfo{ 11679 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11680 }, 11681 }, 11682 }, 11683 { 11684 name: "REV", 11685 argLen: 1, 11686 asm: arm64.AREV, 11687 reg: regInfo{ 11688 inputs: []inputInfo{ 11689 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11690 }, 11691 outputs: []outputInfo{ 11692 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11693 }, 11694 }, 11695 }, 11696 { 11697 name: "REVW", 11698 argLen: 1, 11699 asm: arm64.AREVW, 11700 reg: regInfo{ 11701 inputs: []inputInfo{ 11702 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11703 }, 11704 outputs: []outputInfo{ 11705 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11706 }, 11707 }, 11708 }, 11709 { 11710 name: "REV16W", 11711 argLen: 1, 11712 asm: arm64.AREV16W, 11713 reg: regInfo{ 11714 inputs: []inputInfo{ 11715 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11716 }, 11717 outputs: []outputInfo{ 11718 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11719 }, 11720 }, 11721 }, 11722 { 11723 name: "RBIT", 11724 argLen: 1, 11725 asm: arm64.ARBIT, 11726 reg: regInfo{ 11727 inputs: []inputInfo{ 11728 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11729 }, 11730 outputs: []outputInfo{ 11731 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11732 }, 11733 }, 11734 }, 11735 { 11736 name: "RBITW", 11737 argLen: 1, 11738 asm: arm64.ARBITW, 11739 reg: regInfo{ 11740 inputs: []inputInfo{ 11741 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11742 }, 11743 outputs: []outputInfo{ 11744 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11745 }, 11746 }, 11747 }, 11748 { 11749 name: "CLZ", 11750 argLen: 1, 11751 asm: arm64.ACLZ, 11752 reg: regInfo{ 11753 inputs: []inputInfo{ 11754 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11755 }, 11756 outputs: []outputInfo{ 11757 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11758 }, 11759 }, 11760 }, 11761 { 11762 name: "CLZW", 11763 argLen: 1, 11764 asm: arm64.ACLZW, 11765 reg: regInfo{ 11766 inputs: []inputInfo{ 11767 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11768 }, 11769 outputs: []outputInfo{ 11770 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11771 }, 11772 }, 11773 }, 11774 { 11775 name: "SLL", 11776 argLen: 2, 11777 asm: arm64.ALSL, 11778 reg: regInfo{ 11779 inputs: []inputInfo{ 11780 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11781 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11782 }, 11783 outputs: []outputInfo{ 11784 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11785 }, 11786 }, 11787 }, 11788 { 11789 name: "SLLconst", 11790 auxType: auxInt64, 11791 argLen: 1, 11792 asm: arm64.ALSL, 11793 reg: regInfo{ 11794 inputs: []inputInfo{ 11795 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11796 }, 11797 outputs: []outputInfo{ 11798 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11799 }, 11800 }, 11801 }, 11802 { 11803 name: "SRL", 11804 argLen: 2, 11805 asm: arm64.ALSR, 11806 reg: regInfo{ 11807 inputs: []inputInfo{ 11808 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11809 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11810 }, 11811 outputs: []outputInfo{ 11812 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11813 }, 11814 }, 11815 }, 11816 { 11817 name: "SRLconst", 11818 auxType: auxInt64, 11819 argLen: 1, 11820 asm: arm64.ALSR, 11821 reg: regInfo{ 11822 inputs: []inputInfo{ 11823 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11824 }, 11825 outputs: []outputInfo{ 11826 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11827 }, 11828 }, 11829 }, 11830 { 11831 name: "SRA", 11832 argLen: 2, 11833 asm: arm64.AASR, 11834 reg: regInfo{ 11835 inputs: []inputInfo{ 11836 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11837 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11838 }, 11839 outputs: []outputInfo{ 11840 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11841 }, 11842 }, 11843 }, 11844 { 11845 name: "SRAconst", 11846 auxType: auxInt64, 11847 argLen: 1, 11848 asm: arm64.AASR, 11849 reg: regInfo{ 11850 inputs: []inputInfo{ 11851 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11852 }, 11853 outputs: []outputInfo{ 11854 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11855 }, 11856 }, 11857 }, 11858 { 11859 name: "RORconst", 11860 auxType: auxInt64, 11861 argLen: 1, 11862 asm: arm64.AROR, 11863 reg: regInfo{ 11864 inputs: []inputInfo{ 11865 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11866 }, 11867 outputs: []outputInfo{ 11868 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11869 }, 11870 }, 11871 }, 11872 { 11873 name: "RORWconst", 11874 auxType: auxInt64, 11875 argLen: 1, 11876 asm: arm64.ARORW, 11877 reg: regInfo{ 11878 inputs: []inputInfo{ 11879 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11880 }, 11881 outputs: []outputInfo{ 11882 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11883 }, 11884 }, 11885 }, 11886 { 11887 name: "CMP", 11888 argLen: 2, 11889 asm: arm64.ACMP, 11890 reg: regInfo{ 11891 inputs: []inputInfo{ 11892 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11893 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11894 }, 11895 }, 11896 }, 11897 { 11898 name: "CMPconst", 11899 auxType: auxInt64, 11900 argLen: 1, 11901 asm: arm64.ACMP, 11902 reg: regInfo{ 11903 inputs: []inputInfo{ 11904 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11905 }, 11906 }, 11907 }, 11908 { 11909 name: "CMPW", 11910 argLen: 2, 11911 asm: arm64.ACMPW, 11912 reg: regInfo{ 11913 inputs: []inputInfo{ 11914 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11915 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11916 }, 11917 }, 11918 }, 11919 { 11920 name: "CMPWconst", 11921 auxType: auxInt32, 11922 argLen: 1, 11923 asm: arm64.ACMPW, 11924 reg: regInfo{ 11925 inputs: []inputInfo{ 11926 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11927 }, 11928 }, 11929 }, 11930 { 11931 name: "CMN", 11932 argLen: 2, 11933 asm: arm64.ACMN, 11934 reg: regInfo{ 11935 inputs: []inputInfo{ 11936 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11937 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11938 }, 11939 }, 11940 }, 11941 { 11942 name: "CMNconst", 11943 auxType: auxInt64, 11944 argLen: 1, 11945 asm: arm64.ACMN, 11946 reg: regInfo{ 11947 inputs: []inputInfo{ 11948 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11949 }, 11950 }, 11951 }, 11952 { 11953 name: "CMNW", 11954 argLen: 2, 11955 asm: arm64.ACMNW, 11956 reg: regInfo{ 11957 inputs: []inputInfo{ 11958 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11959 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11960 }, 11961 }, 11962 }, 11963 { 11964 name: "CMNWconst", 11965 auxType: auxInt32, 11966 argLen: 1, 11967 asm: arm64.ACMNW, 11968 reg: regInfo{ 11969 inputs: []inputInfo{ 11970 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11971 }, 11972 }, 11973 }, 11974 { 11975 name: "FCMPS", 11976 argLen: 2, 11977 asm: arm64.AFCMPS, 11978 reg: regInfo{ 11979 inputs: []inputInfo{ 11980 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11981 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11982 }, 11983 }, 11984 }, 11985 { 11986 name: "FCMPD", 11987 argLen: 2, 11988 asm: arm64.AFCMPD, 11989 reg: regInfo{ 11990 inputs: []inputInfo{ 11991 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11992 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11993 }, 11994 }, 11995 }, 11996 { 11997 name: "ADDshiftLL", 11998 auxType: auxInt64, 11999 argLen: 2, 12000 asm: arm64.AADD, 12001 reg: regInfo{ 12002 inputs: []inputInfo{ 12003 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12004 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12005 }, 12006 outputs: []outputInfo{ 12007 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12008 }, 12009 }, 12010 }, 12011 { 12012 name: "ADDshiftRL", 12013 auxType: auxInt64, 12014 argLen: 2, 12015 asm: arm64.AADD, 12016 reg: regInfo{ 12017 inputs: []inputInfo{ 12018 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12019 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12020 }, 12021 outputs: []outputInfo{ 12022 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12023 }, 12024 }, 12025 }, 12026 { 12027 name: "ADDshiftRA", 12028 auxType: auxInt64, 12029 argLen: 2, 12030 asm: arm64.AADD, 12031 reg: regInfo{ 12032 inputs: []inputInfo{ 12033 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12034 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12035 }, 12036 outputs: []outputInfo{ 12037 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12038 }, 12039 }, 12040 }, 12041 { 12042 name: "SUBshiftLL", 12043 auxType: auxInt64, 12044 argLen: 2, 12045 asm: arm64.ASUB, 12046 reg: regInfo{ 12047 inputs: []inputInfo{ 12048 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12049 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12050 }, 12051 outputs: []outputInfo{ 12052 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12053 }, 12054 }, 12055 }, 12056 { 12057 name: "SUBshiftRL", 12058 auxType: auxInt64, 12059 argLen: 2, 12060 asm: arm64.ASUB, 12061 reg: regInfo{ 12062 inputs: []inputInfo{ 12063 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12064 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12065 }, 12066 outputs: []outputInfo{ 12067 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12068 }, 12069 }, 12070 }, 12071 { 12072 name: "SUBshiftRA", 12073 auxType: auxInt64, 12074 argLen: 2, 12075 asm: arm64.ASUB, 12076 reg: regInfo{ 12077 inputs: []inputInfo{ 12078 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12079 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12080 }, 12081 outputs: []outputInfo{ 12082 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12083 }, 12084 }, 12085 }, 12086 { 12087 name: "ANDshiftLL", 12088 auxType: auxInt64, 12089 argLen: 2, 12090 asm: arm64.AAND, 12091 reg: regInfo{ 12092 inputs: []inputInfo{ 12093 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12094 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12095 }, 12096 outputs: []outputInfo{ 12097 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12098 }, 12099 }, 12100 }, 12101 { 12102 name: "ANDshiftRL", 12103 auxType: auxInt64, 12104 argLen: 2, 12105 asm: arm64.AAND, 12106 reg: regInfo{ 12107 inputs: []inputInfo{ 12108 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12109 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12110 }, 12111 outputs: []outputInfo{ 12112 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12113 }, 12114 }, 12115 }, 12116 { 12117 name: "ANDshiftRA", 12118 auxType: auxInt64, 12119 argLen: 2, 12120 asm: arm64.AAND, 12121 reg: regInfo{ 12122 inputs: []inputInfo{ 12123 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12124 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12125 }, 12126 outputs: []outputInfo{ 12127 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12128 }, 12129 }, 12130 }, 12131 { 12132 name: "ORshiftLL", 12133 auxType: auxInt64, 12134 argLen: 2, 12135 asm: arm64.AORR, 12136 reg: regInfo{ 12137 inputs: []inputInfo{ 12138 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12139 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12140 }, 12141 outputs: []outputInfo{ 12142 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12143 }, 12144 }, 12145 }, 12146 { 12147 name: "ORshiftRL", 12148 auxType: auxInt64, 12149 argLen: 2, 12150 asm: arm64.AORR, 12151 reg: regInfo{ 12152 inputs: []inputInfo{ 12153 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12154 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12155 }, 12156 outputs: []outputInfo{ 12157 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12158 }, 12159 }, 12160 }, 12161 { 12162 name: "ORshiftRA", 12163 auxType: auxInt64, 12164 argLen: 2, 12165 asm: arm64.AORR, 12166 reg: regInfo{ 12167 inputs: []inputInfo{ 12168 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12169 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12170 }, 12171 outputs: []outputInfo{ 12172 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12173 }, 12174 }, 12175 }, 12176 { 12177 name: "XORshiftLL", 12178 auxType: auxInt64, 12179 argLen: 2, 12180 asm: arm64.AEOR, 12181 reg: regInfo{ 12182 inputs: []inputInfo{ 12183 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12184 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12185 }, 12186 outputs: []outputInfo{ 12187 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12188 }, 12189 }, 12190 }, 12191 { 12192 name: "XORshiftRL", 12193 auxType: auxInt64, 12194 argLen: 2, 12195 asm: arm64.AEOR, 12196 reg: regInfo{ 12197 inputs: []inputInfo{ 12198 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12199 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12200 }, 12201 outputs: []outputInfo{ 12202 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12203 }, 12204 }, 12205 }, 12206 { 12207 name: "XORshiftRA", 12208 auxType: auxInt64, 12209 argLen: 2, 12210 asm: arm64.AEOR, 12211 reg: regInfo{ 12212 inputs: []inputInfo{ 12213 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12214 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12215 }, 12216 outputs: []outputInfo{ 12217 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12218 }, 12219 }, 12220 }, 12221 { 12222 name: "BICshiftLL", 12223 auxType: auxInt64, 12224 argLen: 2, 12225 asm: arm64.ABIC, 12226 reg: regInfo{ 12227 inputs: []inputInfo{ 12228 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12229 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12230 }, 12231 outputs: []outputInfo{ 12232 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12233 }, 12234 }, 12235 }, 12236 { 12237 name: "BICshiftRL", 12238 auxType: auxInt64, 12239 argLen: 2, 12240 asm: arm64.ABIC, 12241 reg: regInfo{ 12242 inputs: []inputInfo{ 12243 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12244 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12245 }, 12246 outputs: []outputInfo{ 12247 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12248 }, 12249 }, 12250 }, 12251 { 12252 name: "BICshiftRA", 12253 auxType: auxInt64, 12254 argLen: 2, 12255 asm: arm64.ABIC, 12256 reg: regInfo{ 12257 inputs: []inputInfo{ 12258 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12259 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12260 }, 12261 outputs: []outputInfo{ 12262 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12263 }, 12264 }, 12265 }, 12266 { 12267 name: "CMPshiftLL", 12268 auxType: auxInt64, 12269 argLen: 2, 12270 asm: arm64.ACMP, 12271 reg: regInfo{ 12272 inputs: []inputInfo{ 12273 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12274 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12275 }, 12276 }, 12277 }, 12278 { 12279 name: "CMPshiftRL", 12280 auxType: auxInt64, 12281 argLen: 2, 12282 asm: arm64.ACMP, 12283 reg: regInfo{ 12284 inputs: []inputInfo{ 12285 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12286 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12287 }, 12288 }, 12289 }, 12290 { 12291 name: "CMPshiftRA", 12292 auxType: auxInt64, 12293 argLen: 2, 12294 asm: arm64.ACMP, 12295 reg: regInfo{ 12296 inputs: []inputInfo{ 12297 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12298 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12299 }, 12300 }, 12301 }, 12302 { 12303 name: "MOVDconst", 12304 auxType: auxInt64, 12305 argLen: 0, 12306 rematerializeable: true, 12307 asm: arm64.AMOVD, 12308 reg: regInfo{ 12309 outputs: []outputInfo{ 12310 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12311 }, 12312 }, 12313 }, 12314 { 12315 name: "FMOVSconst", 12316 auxType: auxFloat64, 12317 argLen: 0, 12318 rematerializeable: true, 12319 asm: arm64.AFMOVS, 12320 reg: regInfo{ 12321 outputs: []outputInfo{ 12322 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12323 }, 12324 }, 12325 }, 12326 { 12327 name: "FMOVDconst", 12328 auxType: auxFloat64, 12329 argLen: 0, 12330 rematerializeable: true, 12331 asm: arm64.AFMOVD, 12332 reg: regInfo{ 12333 outputs: []outputInfo{ 12334 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12335 }, 12336 }, 12337 }, 12338 { 12339 name: "MOVDaddr", 12340 auxType: auxSymOff, 12341 argLen: 1, 12342 rematerializeable: true, 12343 symEffect: SymAddr, 12344 asm: arm64.AMOVD, 12345 reg: regInfo{ 12346 inputs: []inputInfo{ 12347 {0, 9223372037928517632}, // SP SB 12348 }, 12349 outputs: []outputInfo{ 12350 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12351 }, 12352 }, 12353 }, 12354 { 12355 name: "MOVBload", 12356 auxType: auxSymOff, 12357 argLen: 2, 12358 faultOnNilArg0: true, 12359 symEffect: SymRead, 12360 asm: arm64.AMOVB, 12361 reg: regInfo{ 12362 inputs: []inputInfo{ 12363 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12364 }, 12365 outputs: []outputInfo{ 12366 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12367 }, 12368 }, 12369 }, 12370 { 12371 name: "MOVBUload", 12372 auxType: auxSymOff, 12373 argLen: 2, 12374 faultOnNilArg0: true, 12375 symEffect: SymRead, 12376 asm: arm64.AMOVBU, 12377 reg: regInfo{ 12378 inputs: []inputInfo{ 12379 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12380 }, 12381 outputs: []outputInfo{ 12382 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12383 }, 12384 }, 12385 }, 12386 { 12387 name: "MOVHload", 12388 auxType: auxSymOff, 12389 argLen: 2, 12390 faultOnNilArg0: true, 12391 symEffect: SymRead, 12392 asm: arm64.AMOVH, 12393 reg: regInfo{ 12394 inputs: []inputInfo{ 12395 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12396 }, 12397 outputs: []outputInfo{ 12398 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12399 }, 12400 }, 12401 }, 12402 { 12403 name: "MOVHUload", 12404 auxType: auxSymOff, 12405 argLen: 2, 12406 faultOnNilArg0: true, 12407 symEffect: SymRead, 12408 asm: arm64.AMOVHU, 12409 reg: regInfo{ 12410 inputs: []inputInfo{ 12411 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12412 }, 12413 outputs: []outputInfo{ 12414 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12415 }, 12416 }, 12417 }, 12418 { 12419 name: "MOVWload", 12420 auxType: auxSymOff, 12421 argLen: 2, 12422 faultOnNilArg0: true, 12423 symEffect: SymRead, 12424 asm: arm64.AMOVW, 12425 reg: regInfo{ 12426 inputs: []inputInfo{ 12427 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12428 }, 12429 outputs: []outputInfo{ 12430 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12431 }, 12432 }, 12433 }, 12434 { 12435 name: "MOVWUload", 12436 auxType: auxSymOff, 12437 argLen: 2, 12438 faultOnNilArg0: true, 12439 symEffect: SymRead, 12440 asm: arm64.AMOVWU, 12441 reg: regInfo{ 12442 inputs: []inputInfo{ 12443 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12444 }, 12445 outputs: []outputInfo{ 12446 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12447 }, 12448 }, 12449 }, 12450 { 12451 name: "MOVDload", 12452 auxType: auxSymOff, 12453 argLen: 2, 12454 faultOnNilArg0: true, 12455 symEffect: SymRead, 12456 asm: arm64.AMOVD, 12457 reg: regInfo{ 12458 inputs: []inputInfo{ 12459 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12460 }, 12461 outputs: []outputInfo{ 12462 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12463 }, 12464 }, 12465 }, 12466 { 12467 name: "FMOVSload", 12468 auxType: auxSymOff, 12469 argLen: 2, 12470 faultOnNilArg0: true, 12471 symEffect: SymRead, 12472 asm: arm64.AFMOVS, 12473 reg: regInfo{ 12474 inputs: []inputInfo{ 12475 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12476 }, 12477 outputs: []outputInfo{ 12478 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12479 }, 12480 }, 12481 }, 12482 { 12483 name: "FMOVDload", 12484 auxType: auxSymOff, 12485 argLen: 2, 12486 faultOnNilArg0: true, 12487 symEffect: SymRead, 12488 asm: arm64.AFMOVD, 12489 reg: regInfo{ 12490 inputs: []inputInfo{ 12491 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12492 }, 12493 outputs: []outputInfo{ 12494 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12495 }, 12496 }, 12497 }, 12498 { 12499 name: "MOVBstore", 12500 auxType: auxSymOff, 12501 argLen: 3, 12502 faultOnNilArg0: true, 12503 symEffect: SymWrite, 12504 asm: arm64.AMOVB, 12505 reg: regInfo{ 12506 inputs: []inputInfo{ 12507 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12508 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12509 }, 12510 }, 12511 }, 12512 { 12513 name: "MOVHstore", 12514 auxType: auxSymOff, 12515 argLen: 3, 12516 faultOnNilArg0: true, 12517 symEffect: SymWrite, 12518 asm: arm64.AMOVH, 12519 reg: regInfo{ 12520 inputs: []inputInfo{ 12521 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12522 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12523 }, 12524 }, 12525 }, 12526 { 12527 name: "MOVWstore", 12528 auxType: auxSymOff, 12529 argLen: 3, 12530 faultOnNilArg0: true, 12531 symEffect: SymWrite, 12532 asm: arm64.AMOVW, 12533 reg: regInfo{ 12534 inputs: []inputInfo{ 12535 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12536 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12537 }, 12538 }, 12539 }, 12540 { 12541 name: "MOVDstore", 12542 auxType: auxSymOff, 12543 argLen: 3, 12544 faultOnNilArg0: true, 12545 symEffect: SymWrite, 12546 asm: arm64.AMOVD, 12547 reg: regInfo{ 12548 inputs: []inputInfo{ 12549 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12550 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12551 }, 12552 }, 12553 }, 12554 { 12555 name: "FMOVSstore", 12556 auxType: auxSymOff, 12557 argLen: 3, 12558 faultOnNilArg0: true, 12559 symEffect: SymWrite, 12560 asm: arm64.AFMOVS, 12561 reg: regInfo{ 12562 inputs: []inputInfo{ 12563 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12564 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12565 }, 12566 }, 12567 }, 12568 { 12569 name: "FMOVDstore", 12570 auxType: auxSymOff, 12571 argLen: 3, 12572 faultOnNilArg0: true, 12573 symEffect: SymWrite, 12574 asm: arm64.AFMOVD, 12575 reg: regInfo{ 12576 inputs: []inputInfo{ 12577 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12578 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12579 }, 12580 }, 12581 }, 12582 { 12583 name: "MOVBstorezero", 12584 auxType: auxSymOff, 12585 argLen: 2, 12586 faultOnNilArg0: true, 12587 symEffect: SymWrite, 12588 asm: arm64.AMOVB, 12589 reg: regInfo{ 12590 inputs: []inputInfo{ 12591 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12592 }, 12593 }, 12594 }, 12595 { 12596 name: "MOVHstorezero", 12597 auxType: auxSymOff, 12598 argLen: 2, 12599 faultOnNilArg0: true, 12600 symEffect: SymWrite, 12601 asm: arm64.AMOVH, 12602 reg: regInfo{ 12603 inputs: []inputInfo{ 12604 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12605 }, 12606 }, 12607 }, 12608 { 12609 name: "MOVWstorezero", 12610 auxType: auxSymOff, 12611 argLen: 2, 12612 faultOnNilArg0: true, 12613 symEffect: SymWrite, 12614 asm: arm64.AMOVW, 12615 reg: regInfo{ 12616 inputs: []inputInfo{ 12617 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12618 }, 12619 }, 12620 }, 12621 { 12622 name: "MOVDstorezero", 12623 auxType: auxSymOff, 12624 argLen: 2, 12625 faultOnNilArg0: true, 12626 symEffect: SymWrite, 12627 asm: arm64.AMOVD, 12628 reg: regInfo{ 12629 inputs: []inputInfo{ 12630 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12631 }, 12632 }, 12633 }, 12634 { 12635 name: "MOVBreg", 12636 argLen: 1, 12637 asm: arm64.AMOVB, 12638 reg: regInfo{ 12639 inputs: []inputInfo{ 12640 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12641 }, 12642 outputs: []outputInfo{ 12643 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12644 }, 12645 }, 12646 }, 12647 { 12648 name: "MOVBUreg", 12649 argLen: 1, 12650 asm: arm64.AMOVBU, 12651 reg: regInfo{ 12652 inputs: []inputInfo{ 12653 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12654 }, 12655 outputs: []outputInfo{ 12656 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12657 }, 12658 }, 12659 }, 12660 { 12661 name: "MOVHreg", 12662 argLen: 1, 12663 asm: arm64.AMOVH, 12664 reg: regInfo{ 12665 inputs: []inputInfo{ 12666 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12667 }, 12668 outputs: []outputInfo{ 12669 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12670 }, 12671 }, 12672 }, 12673 { 12674 name: "MOVHUreg", 12675 argLen: 1, 12676 asm: arm64.AMOVHU, 12677 reg: regInfo{ 12678 inputs: []inputInfo{ 12679 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12680 }, 12681 outputs: []outputInfo{ 12682 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12683 }, 12684 }, 12685 }, 12686 { 12687 name: "MOVWreg", 12688 argLen: 1, 12689 asm: arm64.AMOVW, 12690 reg: regInfo{ 12691 inputs: []inputInfo{ 12692 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12693 }, 12694 outputs: []outputInfo{ 12695 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12696 }, 12697 }, 12698 }, 12699 { 12700 name: "MOVWUreg", 12701 argLen: 1, 12702 asm: arm64.AMOVWU, 12703 reg: regInfo{ 12704 inputs: []inputInfo{ 12705 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12706 }, 12707 outputs: []outputInfo{ 12708 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12709 }, 12710 }, 12711 }, 12712 { 12713 name: "MOVDreg", 12714 argLen: 1, 12715 asm: arm64.AMOVD, 12716 reg: regInfo{ 12717 inputs: []inputInfo{ 12718 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12719 }, 12720 outputs: []outputInfo{ 12721 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12722 }, 12723 }, 12724 }, 12725 { 12726 name: "MOVDnop", 12727 argLen: 1, 12728 resultInArg0: true, 12729 reg: regInfo{ 12730 inputs: []inputInfo{ 12731 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12732 }, 12733 outputs: []outputInfo{ 12734 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12735 }, 12736 }, 12737 }, 12738 { 12739 name: "SCVTFWS", 12740 argLen: 1, 12741 asm: arm64.ASCVTFWS, 12742 reg: regInfo{ 12743 inputs: []inputInfo{ 12744 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12745 }, 12746 outputs: []outputInfo{ 12747 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12748 }, 12749 }, 12750 }, 12751 { 12752 name: "SCVTFWD", 12753 argLen: 1, 12754 asm: arm64.ASCVTFWD, 12755 reg: regInfo{ 12756 inputs: []inputInfo{ 12757 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12758 }, 12759 outputs: []outputInfo{ 12760 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12761 }, 12762 }, 12763 }, 12764 { 12765 name: "UCVTFWS", 12766 argLen: 1, 12767 asm: arm64.AUCVTFWS, 12768 reg: regInfo{ 12769 inputs: []inputInfo{ 12770 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12771 }, 12772 outputs: []outputInfo{ 12773 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12774 }, 12775 }, 12776 }, 12777 { 12778 name: "UCVTFWD", 12779 argLen: 1, 12780 asm: arm64.AUCVTFWD, 12781 reg: regInfo{ 12782 inputs: []inputInfo{ 12783 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12784 }, 12785 outputs: []outputInfo{ 12786 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12787 }, 12788 }, 12789 }, 12790 { 12791 name: "SCVTFS", 12792 argLen: 1, 12793 asm: arm64.ASCVTFS, 12794 reg: regInfo{ 12795 inputs: []inputInfo{ 12796 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12797 }, 12798 outputs: []outputInfo{ 12799 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12800 }, 12801 }, 12802 }, 12803 { 12804 name: "SCVTFD", 12805 argLen: 1, 12806 asm: arm64.ASCVTFD, 12807 reg: regInfo{ 12808 inputs: []inputInfo{ 12809 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12810 }, 12811 outputs: []outputInfo{ 12812 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12813 }, 12814 }, 12815 }, 12816 { 12817 name: "UCVTFS", 12818 argLen: 1, 12819 asm: arm64.AUCVTFS, 12820 reg: regInfo{ 12821 inputs: []inputInfo{ 12822 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12823 }, 12824 outputs: []outputInfo{ 12825 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12826 }, 12827 }, 12828 }, 12829 { 12830 name: "UCVTFD", 12831 argLen: 1, 12832 asm: arm64.AUCVTFD, 12833 reg: regInfo{ 12834 inputs: []inputInfo{ 12835 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12836 }, 12837 outputs: []outputInfo{ 12838 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12839 }, 12840 }, 12841 }, 12842 { 12843 name: "FCVTZSSW", 12844 argLen: 1, 12845 asm: arm64.AFCVTZSSW, 12846 reg: regInfo{ 12847 inputs: []inputInfo{ 12848 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12849 }, 12850 outputs: []outputInfo{ 12851 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12852 }, 12853 }, 12854 }, 12855 { 12856 name: "FCVTZSDW", 12857 argLen: 1, 12858 asm: arm64.AFCVTZSDW, 12859 reg: regInfo{ 12860 inputs: []inputInfo{ 12861 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12862 }, 12863 outputs: []outputInfo{ 12864 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12865 }, 12866 }, 12867 }, 12868 { 12869 name: "FCVTZUSW", 12870 argLen: 1, 12871 asm: arm64.AFCVTZUSW, 12872 reg: regInfo{ 12873 inputs: []inputInfo{ 12874 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12875 }, 12876 outputs: []outputInfo{ 12877 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12878 }, 12879 }, 12880 }, 12881 { 12882 name: "FCVTZUDW", 12883 argLen: 1, 12884 asm: arm64.AFCVTZUDW, 12885 reg: regInfo{ 12886 inputs: []inputInfo{ 12887 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12888 }, 12889 outputs: []outputInfo{ 12890 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12891 }, 12892 }, 12893 }, 12894 { 12895 name: "FCVTZSS", 12896 argLen: 1, 12897 asm: arm64.AFCVTZSS, 12898 reg: regInfo{ 12899 inputs: []inputInfo{ 12900 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12901 }, 12902 outputs: []outputInfo{ 12903 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12904 }, 12905 }, 12906 }, 12907 { 12908 name: "FCVTZSD", 12909 argLen: 1, 12910 asm: arm64.AFCVTZSD, 12911 reg: regInfo{ 12912 inputs: []inputInfo{ 12913 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12914 }, 12915 outputs: []outputInfo{ 12916 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12917 }, 12918 }, 12919 }, 12920 { 12921 name: "FCVTZUS", 12922 argLen: 1, 12923 asm: arm64.AFCVTZUS, 12924 reg: regInfo{ 12925 inputs: []inputInfo{ 12926 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12927 }, 12928 outputs: []outputInfo{ 12929 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12930 }, 12931 }, 12932 }, 12933 { 12934 name: "FCVTZUD", 12935 argLen: 1, 12936 asm: arm64.AFCVTZUD, 12937 reg: regInfo{ 12938 inputs: []inputInfo{ 12939 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12940 }, 12941 outputs: []outputInfo{ 12942 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12943 }, 12944 }, 12945 }, 12946 { 12947 name: "FCVTSD", 12948 argLen: 1, 12949 asm: arm64.AFCVTSD, 12950 reg: regInfo{ 12951 inputs: []inputInfo{ 12952 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12953 }, 12954 outputs: []outputInfo{ 12955 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12956 }, 12957 }, 12958 }, 12959 { 12960 name: "FCVTDS", 12961 argLen: 1, 12962 asm: arm64.AFCVTDS, 12963 reg: regInfo{ 12964 inputs: []inputInfo{ 12965 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12966 }, 12967 outputs: []outputInfo{ 12968 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12969 }, 12970 }, 12971 }, 12972 { 12973 name: "CSELULT", 12974 argLen: 3, 12975 asm: arm64.ACSEL, 12976 reg: regInfo{ 12977 inputs: []inputInfo{ 12978 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12979 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12980 }, 12981 outputs: []outputInfo{ 12982 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12983 }, 12984 }, 12985 }, 12986 { 12987 name: "CSELULT0", 12988 argLen: 2, 12989 asm: arm64.ACSEL, 12990 reg: regInfo{ 12991 inputs: []inputInfo{ 12992 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12993 }, 12994 outputs: []outputInfo{ 12995 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12996 }, 12997 }, 12998 }, 12999 { 13000 name: "CALLstatic", 13001 auxType: auxSymOff, 13002 argLen: 1, 13003 clobberFlags: true, 13004 call: true, 13005 symEffect: SymNone, 13006 reg: regInfo{ 13007 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13008 }, 13009 }, 13010 { 13011 name: "CALLclosure", 13012 auxType: auxInt64, 13013 argLen: 3, 13014 clobberFlags: true, 13015 call: true, 13016 reg: regInfo{ 13017 inputs: []inputInfo{ 13018 {1, 67108864}, // R26 13019 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 13020 }, 13021 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13022 }, 13023 }, 13024 { 13025 name: "CALLinter", 13026 auxType: auxInt64, 13027 argLen: 2, 13028 clobberFlags: true, 13029 call: true, 13030 reg: regInfo{ 13031 inputs: []inputInfo{ 13032 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13033 }, 13034 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13035 }, 13036 }, 13037 { 13038 name: "LoweredNilCheck", 13039 argLen: 2, 13040 nilCheck: true, 13041 faultOnNilArg0: true, 13042 reg: regInfo{ 13043 inputs: []inputInfo{ 13044 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13045 }, 13046 }, 13047 }, 13048 { 13049 name: "Equal", 13050 argLen: 1, 13051 reg: regInfo{ 13052 outputs: []outputInfo{ 13053 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13054 }, 13055 }, 13056 }, 13057 { 13058 name: "NotEqual", 13059 argLen: 1, 13060 reg: regInfo{ 13061 outputs: []outputInfo{ 13062 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13063 }, 13064 }, 13065 }, 13066 { 13067 name: "LessThan", 13068 argLen: 1, 13069 reg: regInfo{ 13070 outputs: []outputInfo{ 13071 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13072 }, 13073 }, 13074 }, 13075 { 13076 name: "LessEqual", 13077 argLen: 1, 13078 reg: regInfo{ 13079 outputs: []outputInfo{ 13080 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13081 }, 13082 }, 13083 }, 13084 { 13085 name: "GreaterThan", 13086 argLen: 1, 13087 reg: regInfo{ 13088 outputs: []outputInfo{ 13089 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13090 }, 13091 }, 13092 }, 13093 { 13094 name: "GreaterEqual", 13095 argLen: 1, 13096 reg: regInfo{ 13097 outputs: []outputInfo{ 13098 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13099 }, 13100 }, 13101 }, 13102 { 13103 name: "LessThanU", 13104 argLen: 1, 13105 reg: regInfo{ 13106 outputs: []outputInfo{ 13107 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13108 }, 13109 }, 13110 }, 13111 { 13112 name: "LessEqualU", 13113 argLen: 1, 13114 reg: regInfo{ 13115 outputs: []outputInfo{ 13116 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13117 }, 13118 }, 13119 }, 13120 { 13121 name: "GreaterThanU", 13122 argLen: 1, 13123 reg: regInfo{ 13124 outputs: []outputInfo{ 13125 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13126 }, 13127 }, 13128 }, 13129 { 13130 name: "GreaterEqualU", 13131 argLen: 1, 13132 reg: regInfo{ 13133 outputs: []outputInfo{ 13134 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13135 }, 13136 }, 13137 }, 13138 { 13139 name: "DUFFZERO", 13140 auxType: auxInt64, 13141 argLen: 2, 13142 faultOnNilArg0: true, 13143 reg: regInfo{ 13144 inputs: []inputInfo{ 13145 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13146 }, 13147 clobbers: 536936448, // R16 R30 13148 }, 13149 }, 13150 { 13151 name: "LoweredZero", 13152 argLen: 3, 13153 clobberFlags: true, 13154 faultOnNilArg0: true, 13155 reg: regInfo{ 13156 inputs: []inputInfo{ 13157 {0, 65536}, // R16 13158 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13159 }, 13160 clobbers: 65536, // R16 13161 }, 13162 }, 13163 { 13164 name: "DUFFCOPY", 13165 auxType: auxInt64, 13166 argLen: 3, 13167 faultOnNilArg0: true, 13168 faultOnNilArg1: true, 13169 reg: regInfo{ 13170 inputs: []inputInfo{ 13171 {0, 131072}, // R17 13172 {1, 65536}, // R16 13173 }, 13174 clobbers: 537067520, // R16 R17 R30 13175 }, 13176 }, 13177 { 13178 name: "LoweredMove", 13179 argLen: 4, 13180 clobberFlags: true, 13181 faultOnNilArg0: true, 13182 faultOnNilArg1: true, 13183 reg: regInfo{ 13184 inputs: []inputInfo{ 13185 {0, 131072}, // R17 13186 {1, 65536}, // R16 13187 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13188 }, 13189 clobbers: 196608, // R16 R17 13190 }, 13191 }, 13192 { 13193 name: "LoweredGetClosurePtr", 13194 argLen: 0, 13195 reg: regInfo{ 13196 outputs: []outputInfo{ 13197 {0, 67108864}, // R26 13198 }, 13199 }, 13200 }, 13201 { 13202 name: "MOVDconvert", 13203 argLen: 2, 13204 asm: arm64.AMOVD, 13205 reg: regInfo{ 13206 inputs: []inputInfo{ 13207 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13208 }, 13209 outputs: []outputInfo{ 13210 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13211 }, 13212 }, 13213 }, 13214 { 13215 name: "FlagEQ", 13216 argLen: 0, 13217 reg: regInfo{}, 13218 }, 13219 { 13220 name: "FlagLT_ULT", 13221 argLen: 0, 13222 reg: regInfo{}, 13223 }, 13224 { 13225 name: "FlagLT_UGT", 13226 argLen: 0, 13227 reg: regInfo{}, 13228 }, 13229 { 13230 name: "FlagGT_UGT", 13231 argLen: 0, 13232 reg: regInfo{}, 13233 }, 13234 { 13235 name: "FlagGT_ULT", 13236 argLen: 0, 13237 reg: regInfo{}, 13238 }, 13239 { 13240 name: "InvertFlags", 13241 argLen: 1, 13242 reg: regInfo{}, 13243 }, 13244 { 13245 name: "LDAR", 13246 argLen: 2, 13247 faultOnNilArg0: true, 13248 asm: arm64.ALDAR, 13249 reg: regInfo{ 13250 inputs: []inputInfo{ 13251 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13252 }, 13253 outputs: []outputInfo{ 13254 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13255 }, 13256 }, 13257 }, 13258 { 13259 name: "LDARW", 13260 argLen: 2, 13261 faultOnNilArg0: true, 13262 asm: arm64.ALDARW, 13263 reg: regInfo{ 13264 inputs: []inputInfo{ 13265 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13266 }, 13267 outputs: []outputInfo{ 13268 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13269 }, 13270 }, 13271 }, 13272 { 13273 name: "STLR", 13274 argLen: 3, 13275 faultOnNilArg0: true, 13276 hasSideEffects: true, 13277 asm: arm64.ASTLR, 13278 reg: regInfo{ 13279 inputs: []inputInfo{ 13280 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13281 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13282 }, 13283 }, 13284 }, 13285 { 13286 name: "STLRW", 13287 argLen: 3, 13288 faultOnNilArg0: true, 13289 hasSideEffects: true, 13290 asm: arm64.ASTLRW, 13291 reg: regInfo{ 13292 inputs: []inputInfo{ 13293 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13294 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13295 }, 13296 }, 13297 }, 13298 { 13299 name: "LoweredAtomicExchange64", 13300 argLen: 3, 13301 resultNotInArgs: true, 13302 faultOnNilArg0: true, 13303 hasSideEffects: true, 13304 reg: regInfo{ 13305 inputs: []inputInfo{ 13306 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13307 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13308 }, 13309 outputs: []outputInfo{ 13310 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13311 }, 13312 }, 13313 }, 13314 { 13315 name: "LoweredAtomicExchange32", 13316 argLen: 3, 13317 resultNotInArgs: true, 13318 faultOnNilArg0: true, 13319 hasSideEffects: true, 13320 reg: regInfo{ 13321 inputs: []inputInfo{ 13322 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13323 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13324 }, 13325 outputs: []outputInfo{ 13326 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13327 }, 13328 }, 13329 }, 13330 { 13331 name: "LoweredAtomicAdd64", 13332 argLen: 3, 13333 resultNotInArgs: true, 13334 faultOnNilArg0: true, 13335 hasSideEffects: true, 13336 reg: regInfo{ 13337 inputs: []inputInfo{ 13338 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13339 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13340 }, 13341 outputs: []outputInfo{ 13342 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13343 }, 13344 }, 13345 }, 13346 { 13347 name: "LoweredAtomicAdd32", 13348 argLen: 3, 13349 resultNotInArgs: true, 13350 faultOnNilArg0: true, 13351 hasSideEffects: true, 13352 reg: regInfo{ 13353 inputs: []inputInfo{ 13354 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13355 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13356 }, 13357 outputs: []outputInfo{ 13358 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13359 }, 13360 }, 13361 }, 13362 { 13363 name: "LoweredAtomicCas64", 13364 argLen: 4, 13365 resultNotInArgs: true, 13366 clobberFlags: true, 13367 faultOnNilArg0: true, 13368 hasSideEffects: true, 13369 reg: regInfo{ 13370 inputs: []inputInfo{ 13371 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13372 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13373 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13374 }, 13375 outputs: []outputInfo{ 13376 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13377 }, 13378 }, 13379 }, 13380 { 13381 name: "LoweredAtomicCas32", 13382 argLen: 4, 13383 resultNotInArgs: true, 13384 clobberFlags: true, 13385 faultOnNilArg0: true, 13386 hasSideEffects: true, 13387 reg: regInfo{ 13388 inputs: []inputInfo{ 13389 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13390 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13391 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13392 }, 13393 outputs: []outputInfo{ 13394 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13395 }, 13396 }, 13397 }, 13398 { 13399 name: "LoweredAtomicAnd8", 13400 argLen: 3, 13401 faultOnNilArg0: true, 13402 hasSideEffects: true, 13403 asm: arm64.AAND, 13404 reg: regInfo{ 13405 inputs: []inputInfo{ 13406 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13407 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13408 }, 13409 }, 13410 }, 13411 { 13412 name: "LoweredAtomicOr8", 13413 argLen: 3, 13414 faultOnNilArg0: true, 13415 hasSideEffects: true, 13416 asm: arm64.AORR, 13417 reg: regInfo{ 13418 inputs: []inputInfo{ 13419 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13420 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13421 }, 13422 }, 13423 }, 13424 13425 { 13426 name: "ADD", 13427 argLen: 2, 13428 commutative: true, 13429 asm: mips.AADDU, 13430 reg: regInfo{ 13431 inputs: []inputInfo{ 13432 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13433 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13434 }, 13435 outputs: []outputInfo{ 13436 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13437 }, 13438 }, 13439 }, 13440 { 13441 name: "ADDconst", 13442 auxType: auxInt32, 13443 argLen: 1, 13444 asm: mips.AADDU, 13445 reg: regInfo{ 13446 inputs: []inputInfo{ 13447 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 13448 }, 13449 outputs: []outputInfo{ 13450 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13451 }, 13452 }, 13453 }, 13454 { 13455 name: "SUB", 13456 argLen: 2, 13457 asm: mips.ASUBU, 13458 reg: regInfo{ 13459 inputs: []inputInfo{ 13460 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13461 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13462 }, 13463 outputs: []outputInfo{ 13464 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13465 }, 13466 }, 13467 }, 13468 { 13469 name: "SUBconst", 13470 auxType: auxInt32, 13471 argLen: 1, 13472 asm: mips.ASUBU, 13473 reg: regInfo{ 13474 inputs: []inputInfo{ 13475 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13476 }, 13477 outputs: []outputInfo{ 13478 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13479 }, 13480 }, 13481 }, 13482 { 13483 name: "MUL", 13484 argLen: 2, 13485 commutative: true, 13486 asm: mips.AMUL, 13487 reg: regInfo{ 13488 inputs: []inputInfo{ 13489 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13490 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13491 }, 13492 clobbers: 105553116266496, // HI LO 13493 outputs: []outputInfo{ 13494 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13495 }, 13496 }, 13497 }, 13498 { 13499 name: "MULT", 13500 argLen: 2, 13501 commutative: true, 13502 asm: mips.AMUL, 13503 reg: regInfo{ 13504 inputs: []inputInfo{ 13505 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13506 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13507 }, 13508 outputs: []outputInfo{ 13509 {0, 35184372088832}, // HI 13510 {1, 70368744177664}, // LO 13511 }, 13512 }, 13513 }, 13514 { 13515 name: "MULTU", 13516 argLen: 2, 13517 commutative: true, 13518 asm: mips.AMULU, 13519 reg: regInfo{ 13520 inputs: []inputInfo{ 13521 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13522 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13523 }, 13524 outputs: []outputInfo{ 13525 {0, 35184372088832}, // HI 13526 {1, 70368744177664}, // LO 13527 }, 13528 }, 13529 }, 13530 { 13531 name: "DIV", 13532 argLen: 2, 13533 asm: mips.ADIV, 13534 reg: regInfo{ 13535 inputs: []inputInfo{ 13536 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13537 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13538 }, 13539 outputs: []outputInfo{ 13540 {0, 35184372088832}, // HI 13541 {1, 70368744177664}, // LO 13542 }, 13543 }, 13544 }, 13545 { 13546 name: "DIVU", 13547 argLen: 2, 13548 asm: mips.ADIVU, 13549 reg: regInfo{ 13550 inputs: []inputInfo{ 13551 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13552 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13553 }, 13554 outputs: []outputInfo{ 13555 {0, 35184372088832}, // HI 13556 {1, 70368744177664}, // LO 13557 }, 13558 }, 13559 }, 13560 { 13561 name: "ADDF", 13562 argLen: 2, 13563 commutative: true, 13564 asm: mips.AADDF, 13565 reg: regInfo{ 13566 inputs: []inputInfo{ 13567 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13568 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13569 }, 13570 outputs: []outputInfo{ 13571 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13572 }, 13573 }, 13574 }, 13575 { 13576 name: "ADDD", 13577 argLen: 2, 13578 commutative: true, 13579 asm: mips.AADDD, 13580 reg: regInfo{ 13581 inputs: []inputInfo{ 13582 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13583 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13584 }, 13585 outputs: []outputInfo{ 13586 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13587 }, 13588 }, 13589 }, 13590 { 13591 name: "SUBF", 13592 argLen: 2, 13593 asm: mips.ASUBF, 13594 reg: regInfo{ 13595 inputs: []inputInfo{ 13596 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13597 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13598 }, 13599 outputs: []outputInfo{ 13600 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13601 }, 13602 }, 13603 }, 13604 { 13605 name: "SUBD", 13606 argLen: 2, 13607 asm: mips.ASUBD, 13608 reg: regInfo{ 13609 inputs: []inputInfo{ 13610 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13611 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13612 }, 13613 outputs: []outputInfo{ 13614 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13615 }, 13616 }, 13617 }, 13618 { 13619 name: "MULF", 13620 argLen: 2, 13621 commutative: true, 13622 asm: mips.AMULF, 13623 reg: regInfo{ 13624 inputs: []inputInfo{ 13625 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13626 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13627 }, 13628 outputs: []outputInfo{ 13629 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13630 }, 13631 }, 13632 }, 13633 { 13634 name: "MULD", 13635 argLen: 2, 13636 commutative: true, 13637 asm: mips.AMULD, 13638 reg: regInfo{ 13639 inputs: []inputInfo{ 13640 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13641 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13642 }, 13643 outputs: []outputInfo{ 13644 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13645 }, 13646 }, 13647 }, 13648 { 13649 name: "DIVF", 13650 argLen: 2, 13651 asm: mips.ADIVF, 13652 reg: regInfo{ 13653 inputs: []inputInfo{ 13654 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13655 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13656 }, 13657 outputs: []outputInfo{ 13658 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13659 }, 13660 }, 13661 }, 13662 { 13663 name: "DIVD", 13664 argLen: 2, 13665 asm: mips.ADIVD, 13666 reg: regInfo{ 13667 inputs: []inputInfo{ 13668 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13669 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13670 }, 13671 outputs: []outputInfo{ 13672 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13673 }, 13674 }, 13675 }, 13676 { 13677 name: "AND", 13678 argLen: 2, 13679 commutative: true, 13680 asm: mips.AAND, 13681 reg: regInfo{ 13682 inputs: []inputInfo{ 13683 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13684 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13685 }, 13686 outputs: []outputInfo{ 13687 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13688 }, 13689 }, 13690 }, 13691 { 13692 name: "ANDconst", 13693 auxType: auxInt32, 13694 argLen: 1, 13695 asm: mips.AAND, 13696 reg: regInfo{ 13697 inputs: []inputInfo{ 13698 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13699 }, 13700 outputs: []outputInfo{ 13701 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13702 }, 13703 }, 13704 }, 13705 { 13706 name: "OR", 13707 argLen: 2, 13708 commutative: true, 13709 asm: mips.AOR, 13710 reg: regInfo{ 13711 inputs: []inputInfo{ 13712 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13713 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13714 }, 13715 outputs: []outputInfo{ 13716 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13717 }, 13718 }, 13719 }, 13720 { 13721 name: "ORconst", 13722 auxType: auxInt32, 13723 argLen: 1, 13724 asm: mips.AOR, 13725 reg: regInfo{ 13726 inputs: []inputInfo{ 13727 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13728 }, 13729 outputs: []outputInfo{ 13730 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13731 }, 13732 }, 13733 }, 13734 { 13735 name: "XOR", 13736 argLen: 2, 13737 commutative: true, 13738 asm: mips.AXOR, 13739 reg: regInfo{ 13740 inputs: []inputInfo{ 13741 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13742 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13743 }, 13744 outputs: []outputInfo{ 13745 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13746 }, 13747 }, 13748 }, 13749 { 13750 name: "XORconst", 13751 auxType: auxInt32, 13752 argLen: 1, 13753 asm: mips.AXOR, 13754 reg: regInfo{ 13755 inputs: []inputInfo{ 13756 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13757 }, 13758 outputs: []outputInfo{ 13759 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13760 }, 13761 }, 13762 }, 13763 { 13764 name: "NOR", 13765 argLen: 2, 13766 commutative: true, 13767 asm: mips.ANOR, 13768 reg: regInfo{ 13769 inputs: []inputInfo{ 13770 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13771 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13772 }, 13773 outputs: []outputInfo{ 13774 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13775 }, 13776 }, 13777 }, 13778 { 13779 name: "NORconst", 13780 auxType: auxInt32, 13781 argLen: 1, 13782 asm: mips.ANOR, 13783 reg: regInfo{ 13784 inputs: []inputInfo{ 13785 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13786 }, 13787 outputs: []outputInfo{ 13788 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13789 }, 13790 }, 13791 }, 13792 { 13793 name: "NEG", 13794 argLen: 1, 13795 reg: regInfo{ 13796 inputs: []inputInfo{ 13797 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13798 }, 13799 outputs: []outputInfo{ 13800 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13801 }, 13802 }, 13803 }, 13804 { 13805 name: "NEGF", 13806 argLen: 1, 13807 asm: mips.ANEGF, 13808 reg: regInfo{ 13809 inputs: []inputInfo{ 13810 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13811 }, 13812 outputs: []outputInfo{ 13813 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13814 }, 13815 }, 13816 }, 13817 { 13818 name: "NEGD", 13819 argLen: 1, 13820 asm: mips.ANEGD, 13821 reg: regInfo{ 13822 inputs: []inputInfo{ 13823 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13824 }, 13825 outputs: []outputInfo{ 13826 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13827 }, 13828 }, 13829 }, 13830 { 13831 name: "SQRTD", 13832 argLen: 1, 13833 asm: mips.ASQRTD, 13834 reg: regInfo{ 13835 inputs: []inputInfo{ 13836 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13837 }, 13838 outputs: []outputInfo{ 13839 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13840 }, 13841 }, 13842 }, 13843 { 13844 name: "SLL", 13845 argLen: 2, 13846 asm: mips.ASLL, 13847 reg: regInfo{ 13848 inputs: []inputInfo{ 13849 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13850 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13851 }, 13852 outputs: []outputInfo{ 13853 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13854 }, 13855 }, 13856 }, 13857 { 13858 name: "SLLconst", 13859 auxType: auxInt32, 13860 argLen: 1, 13861 asm: mips.ASLL, 13862 reg: regInfo{ 13863 inputs: []inputInfo{ 13864 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13865 }, 13866 outputs: []outputInfo{ 13867 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13868 }, 13869 }, 13870 }, 13871 { 13872 name: "SRL", 13873 argLen: 2, 13874 asm: mips.ASRL, 13875 reg: regInfo{ 13876 inputs: []inputInfo{ 13877 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13878 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13879 }, 13880 outputs: []outputInfo{ 13881 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13882 }, 13883 }, 13884 }, 13885 { 13886 name: "SRLconst", 13887 auxType: auxInt32, 13888 argLen: 1, 13889 asm: mips.ASRL, 13890 reg: regInfo{ 13891 inputs: []inputInfo{ 13892 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13893 }, 13894 outputs: []outputInfo{ 13895 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13896 }, 13897 }, 13898 }, 13899 { 13900 name: "SRA", 13901 argLen: 2, 13902 asm: mips.ASRA, 13903 reg: regInfo{ 13904 inputs: []inputInfo{ 13905 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13906 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13907 }, 13908 outputs: []outputInfo{ 13909 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13910 }, 13911 }, 13912 }, 13913 { 13914 name: "SRAconst", 13915 auxType: auxInt32, 13916 argLen: 1, 13917 asm: mips.ASRA, 13918 reg: regInfo{ 13919 inputs: []inputInfo{ 13920 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13921 }, 13922 outputs: []outputInfo{ 13923 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13924 }, 13925 }, 13926 }, 13927 { 13928 name: "CLZ", 13929 argLen: 1, 13930 asm: mips.ACLZ, 13931 reg: regInfo{ 13932 inputs: []inputInfo{ 13933 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13934 }, 13935 outputs: []outputInfo{ 13936 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13937 }, 13938 }, 13939 }, 13940 { 13941 name: "SGT", 13942 argLen: 2, 13943 asm: mips.ASGT, 13944 reg: regInfo{ 13945 inputs: []inputInfo{ 13946 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13947 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13948 }, 13949 outputs: []outputInfo{ 13950 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13951 }, 13952 }, 13953 }, 13954 { 13955 name: "SGTconst", 13956 auxType: auxInt32, 13957 argLen: 1, 13958 asm: mips.ASGT, 13959 reg: regInfo{ 13960 inputs: []inputInfo{ 13961 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13962 }, 13963 outputs: []outputInfo{ 13964 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13965 }, 13966 }, 13967 }, 13968 { 13969 name: "SGTzero", 13970 argLen: 1, 13971 asm: mips.ASGT, 13972 reg: regInfo{ 13973 inputs: []inputInfo{ 13974 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13975 }, 13976 outputs: []outputInfo{ 13977 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13978 }, 13979 }, 13980 }, 13981 { 13982 name: "SGTU", 13983 argLen: 2, 13984 asm: mips.ASGTU, 13985 reg: regInfo{ 13986 inputs: []inputInfo{ 13987 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13988 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13989 }, 13990 outputs: []outputInfo{ 13991 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13992 }, 13993 }, 13994 }, 13995 { 13996 name: "SGTUconst", 13997 auxType: auxInt32, 13998 argLen: 1, 13999 asm: mips.ASGTU, 14000 reg: regInfo{ 14001 inputs: []inputInfo{ 14002 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14003 }, 14004 outputs: []outputInfo{ 14005 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14006 }, 14007 }, 14008 }, 14009 { 14010 name: "SGTUzero", 14011 argLen: 1, 14012 asm: mips.ASGTU, 14013 reg: regInfo{ 14014 inputs: []inputInfo{ 14015 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14016 }, 14017 outputs: []outputInfo{ 14018 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14019 }, 14020 }, 14021 }, 14022 { 14023 name: "CMPEQF", 14024 argLen: 2, 14025 asm: mips.ACMPEQF, 14026 reg: regInfo{ 14027 inputs: []inputInfo{ 14028 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14029 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14030 }, 14031 }, 14032 }, 14033 { 14034 name: "CMPEQD", 14035 argLen: 2, 14036 asm: mips.ACMPEQD, 14037 reg: regInfo{ 14038 inputs: []inputInfo{ 14039 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14040 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14041 }, 14042 }, 14043 }, 14044 { 14045 name: "CMPGEF", 14046 argLen: 2, 14047 asm: mips.ACMPGEF, 14048 reg: regInfo{ 14049 inputs: []inputInfo{ 14050 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14051 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14052 }, 14053 }, 14054 }, 14055 { 14056 name: "CMPGED", 14057 argLen: 2, 14058 asm: mips.ACMPGED, 14059 reg: regInfo{ 14060 inputs: []inputInfo{ 14061 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14062 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14063 }, 14064 }, 14065 }, 14066 { 14067 name: "CMPGTF", 14068 argLen: 2, 14069 asm: mips.ACMPGTF, 14070 reg: regInfo{ 14071 inputs: []inputInfo{ 14072 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14073 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14074 }, 14075 }, 14076 }, 14077 { 14078 name: "CMPGTD", 14079 argLen: 2, 14080 asm: mips.ACMPGTD, 14081 reg: regInfo{ 14082 inputs: []inputInfo{ 14083 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14084 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14085 }, 14086 }, 14087 }, 14088 { 14089 name: "MOVWconst", 14090 auxType: auxInt32, 14091 argLen: 0, 14092 rematerializeable: true, 14093 asm: mips.AMOVW, 14094 reg: regInfo{ 14095 outputs: []outputInfo{ 14096 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14097 }, 14098 }, 14099 }, 14100 { 14101 name: "MOVFconst", 14102 auxType: auxFloat32, 14103 argLen: 0, 14104 rematerializeable: true, 14105 asm: mips.AMOVF, 14106 reg: regInfo{ 14107 outputs: []outputInfo{ 14108 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14109 }, 14110 }, 14111 }, 14112 { 14113 name: "MOVDconst", 14114 auxType: auxFloat64, 14115 argLen: 0, 14116 rematerializeable: true, 14117 asm: mips.AMOVD, 14118 reg: regInfo{ 14119 outputs: []outputInfo{ 14120 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14121 }, 14122 }, 14123 }, 14124 { 14125 name: "MOVWaddr", 14126 auxType: auxSymOff, 14127 argLen: 1, 14128 rematerializeable: true, 14129 symEffect: SymAddr, 14130 asm: mips.AMOVW, 14131 reg: regInfo{ 14132 inputs: []inputInfo{ 14133 {0, 140737555464192}, // SP SB 14134 }, 14135 outputs: []outputInfo{ 14136 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14137 }, 14138 }, 14139 }, 14140 { 14141 name: "MOVBload", 14142 auxType: auxSymOff, 14143 argLen: 2, 14144 faultOnNilArg0: true, 14145 symEffect: SymRead, 14146 asm: mips.AMOVB, 14147 reg: regInfo{ 14148 inputs: []inputInfo{ 14149 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14150 }, 14151 outputs: []outputInfo{ 14152 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14153 }, 14154 }, 14155 }, 14156 { 14157 name: "MOVBUload", 14158 auxType: auxSymOff, 14159 argLen: 2, 14160 faultOnNilArg0: true, 14161 symEffect: SymRead, 14162 asm: mips.AMOVBU, 14163 reg: regInfo{ 14164 inputs: []inputInfo{ 14165 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14166 }, 14167 outputs: []outputInfo{ 14168 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14169 }, 14170 }, 14171 }, 14172 { 14173 name: "MOVHload", 14174 auxType: auxSymOff, 14175 argLen: 2, 14176 faultOnNilArg0: true, 14177 symEffect: SymRead, 14178 asm: mips.AMOVH, 14179 reg: regInfo{ 14180 inputs: []inputInfo{ 14181 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14182 }, 14183 outputs: []outputInfo{ 14184 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14185 }, 14186 }, 14187 }, 14188 { 14189 name: "MOVHUload", 14190 auxType: auxSymOff, 14191 argLen: 2, 14192 faultOnNilArg0: true, 14193 symEffect: SymRead, 14194 asm: mips.AMOVHU, 14195 reg: regInfo{ 14196 inputs: []inputInfo{ 14197 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14198 }, 14199 outputs: []outputInfo{ 14200 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14201 }, 14202 }, 14203 }, 14204 { 14205 name: "MOVWload", 14206 auxType: auxSymOff, 14207 argLen: 2, 14208 faultOnNilArg0: true, 14209 symEffect: SymRead, 14210 asm: mips.AMOVW, 14211 reg: regInfo{ 14212 inputs: []inputInfo{ 14213 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14214 }, 14215 outputs: []outputInfo{ 14216 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14217 }, 14218 }, 14219 }, 14220 { 14221 name: "MOVFload", 14222 auxType: auxSymOff, 14223 argLen: 2, 14224 faultOnNilArg0: true, 14225 symEffect: SymRead, 14226 asm: mips.AMOVF, 14227 reg: regInfo{ 14228 inputs: []inputInfo{ 14229 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14230 }, 14231 outputs: []outputInfo{ 14232 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14233 }, 14234 }, 14235 }, 14236 { 14237 name: "MOVDload", 14238 auxType: auxSymOff, 14239 argLen: 2, 14240 faultOnNilArg0: true, 14241 symEffect: SymRead, 14242 asm: mips.AMOVD, 14243 reg: regInfo{ 14244 inputs: []inputInfo{ 14245 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14246 }, 14247 outputs: []outputInfo{ 14248 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14249 }, 14250 }, 14251 }, 14252 { 14253 name: "MOVBstore", 14254 auxType: auxSymOff, 14255 argLen: 3, 14256 faultOnNilArg0: true, 14257 symEffect: SymWrite, 14258 asm: mips.AMOVB, 14259 reg: regInfo{ 14260 inputs: []inputInfo{ 14261 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14262 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14263 }, 14264 }, 14265 }, 14266 { 14267 name: "MOVHstore", 14268 auxType: auxSymOff, 14269 argLen: 3, 14270 faultOnNilArg0: true, 14271 symEffect: SymWrite, 14272 asm: mips.AMOVH, 14273 reg: regInfo{ 14274 inputs: []inputInfo{ 14275 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14276 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14277 }, 14278 }, 14279 }, 14280 { 14281 name: "MOVWstore", 14282 auxType: auxSymOff, 14283 argLen: 3, 14284 faultOnNilArg0: true, 14285 symEffect: SymWrite, 14286 asm: mips.AMOVW, 14287 reg: regInfo{ 14288 inputs: []inputInfo{ 14289 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14290 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14291 }, 14292 }, 14293 }, 14294 { 14295 name: "MOVFstore", 14296 auxType: auxSymOff, 14297 argLen: 3, 14298 faultOnNilArg0: true, 14299 symEffect: SymWrite, 14300 asm: mips.AMOVF, 14301 reg: regInfo{ 14302 inputs: []inputInfo{ 14303 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14304 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14305 }, 14306 }, 14307 }, 14308 { 14309 name: "MOVDstore", 14310 auxType: auxSymOff, 14311 argLen: 3, 14312 faultOnNilArg0: true, 14313 symEffect: SymWrite, 14314 asm: mips.AMOVD, 14315 reg: regInfo{ 14316 inputs: []inputInfo{ 14317 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14318 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14319 }, 14320 }, 14321 }, 14322 { 14323 name: "MOVBstorezero", 14324 auxType: auxSymOff, 14325 argLen: 2, 14326 faultOnNilArg0: true, 14327 symEffect: SymWrite, 14328 asm: mips.AMOVB, 14329 reg: regInfo{ 14330 inputs: []inputInfo{ 14331 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14332 }, 14333 }, 14334 }, 14335 { 14336 name: "MOVHstorezero", 14337 auxType: auxSymOff, 14338 argLen: 2, 14339 faultOnNilArg0: true, 14340 symEffect: SymWrite, 14341 asm: mips.AMOVH, 14342 reg: regInfo{ 14343 inputs: []inputInfo{ 14344 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14345 }, 14346 }, 14347 }, 14348 { 14349 name: "MOVWstorezero", 14350 auxType: auxSymOff, 14351 argLen: 2, 14352 faultOnNilArg0: true, 14353 symEffect: SymWrite, 14354 asm: mips.AMOVW, 14355 reg: regInfo{ 14356 inputs: []inputInfo{ 14357 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14358 }, 14359 }, 14360 }, 14361 { 14362 name: "MOVBreg", 14363 argLen: 1, 14364 asm: mips.AMOVB, 14365 reg: regInfo{ 14366 inputs: []inputInfo{ 14367 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14368 }, 14369 outputs: []outputInfo{ 14370 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14371 }, 14372 }, 14373 }, 14374 { 14375 name: "MOVBUreg", 14376 argLen: 1, 14377 asm: mips.AMOVBU, 14378 reg: regInfo{ 14379 inputs: []inputInfo{ 14380 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14381 }, 14382 outputs: []outputInfo{ 14383 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14384 }, 14385 }, 14386 }, 14387 { 14388 name: "MOVHreg", 14389 argLen: 1, 14390 asm: mips.AMOVH, 14391 reg: regInfo{ 14392 inputs: []inputInfo{ 14393 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14394 }, 14395 outputs: []outputInfo{ 14396 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14397 }, 14398 }, 14399 }, 14400 { 14401 name: "MOVHUreg", 14402 argLen: 1, 14403 asm: mips.AMOVHU, 14404 reg: regInfo{ 14405 inputs: []inputInfo{ 14406 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14407 }, 14408 outputs: []outputInfo{ 14409 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14410 }, 14411 }, 14412 }, 14413 { 14414 name: "MOVWreg", 14415 argLen: 1, 14416 asm: mips.AMOVW, 14417 reg: regInfo{ 14418 inputs: []inputInfo{ 14419 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14420 }, 14421 outputs: []outputInfo{ 14422 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14423 }, 14424 }, 14425 }, 14426 { 14427 name: "MOVWnop", 14428 argLen: 1, 14429 resultInArg0: true, 14430 reg: regInfo{ 14431 inputs: []inputInfo{ 14432 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14433 }, 14434 outputs: []outputInfo{ 14435 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14436 }, 14437 }, 14438 }, 14439 { 14440 name: "CMOVZ", 14441 argLen: 3, 14442 resultInArg0: true, 14443 asm: mips.ACMOVZ, 14444 reg: regInfo{ 14445 inputs: []inputInfo{ 14446 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14447 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14448 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14449 }, 14450 outputs: []outputInfo{ 14451 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14452 }, 14453 }, 14454 }, 14455 { 14456 name: "CMOVZzero", 14457 argLen: 2, 14458 resultInArg0: true, 14459 asm: mips.ACMOVZ, 14460 reg: regInfo{ 14461 inputs: []inputInfo{ 14462 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14463 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14464 }, 14465 outputs: []outputInfo{ 14466 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14467 }, 14468 }, 14469 }, 14470 { 14471 name: "MOVWF", 14472 argLen: 1, 14473 asm: mips.AMOVWF, 14474 reg: regInfo{ 14475 inputs: []inputInfo{ 14476 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14477 }, 14478 outputs: []outputInfo{ 14479 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14480 }, 14481 }, 14482 }, 14483 { 14484 name: "MOVWD", 14485 argLen: 1, 14486 asm: mips.AMOVWD, 14487 reg: regInfo{ 14488 inputs: []inputInfo{ 14489 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14490 }, 14491 outputs: []outputInfo{ 14492 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14493 }, 14494 }, 14495 }, 14496 { 14497 name: "TRUNCFW", 14498 argLen: 1, 14499 asm: mips.ATRUNCFW, 14500 reg: regInfo{ 14501 inputs: []inputInfo{ 14502 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14503 }, 14504 outputs: []outputInfo{ 14505 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14506 }, 14507 }, 14508 }, 14509 { 14510 name: "TRUNCDW", 14511 argLen: 1, 14512 asm: mips.ATRUNCDW, 14513 reg: regInfo{ 14514 inputs: []inputInfo{ 14515 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14516 }, 14517 outputs: []outputInfo{ 14518 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14519 }, 14520 }, 14521 }, 14522 { 14523 name: "MOVFD", 14524 argLen: 1, 14525 asm: mips.AMOVFD, 14526 reg: regInfo{ 14527 inputs: []inputInfo{ 14528 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14529 }, 14530 outputs: []outputInfo{ 14531 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14532 }, 14533 }, 14534 }, 14535 { 14536 name: "MOVDF", 14537 argLen: 1, 14538 asm: mips.AMOVDF, 14539 reg: regInfo{ 14540 inputs: []inputInfo{ 14541 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14542 }, 14543 outputs: []outputInfo{ 14544 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14545 }, 14546 }, 14547 }, 14548 { 14549 name: "CALLstatic", 14550 auxType: auxSymOff, 14551 argLen: 1, 14552 clobberFlags: true, 14553 call: true, 14554 symEffect: SymNone, 14555 reg: regInfo{ 14556 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14557 }, 14558 }, 14559 { 14560 name: "CALLclosure", 14561 auxType: auxInt64, 14562 argLen: 3, 14563 clobberFlags: true, 14564 call: true, 14565 reg: regInfo{ 14566 inputs: []inputInfo{ 14567 {1, 4194304}, // R22 14568 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 14569 }, 14570 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14571 }, 14572 }, 14573 { 14574 name: "CALLinter", 14575 auxType: auxInt64, 14576 argLen: 2, 14577 clobberFlags: true, 14578 call: true, 14579 reg: regInfo{ 14580 inputs: []inputInfo{ 14581 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14582 }, 14583 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14584 }, 14585 }, 14586 { 14587 name: "LoweredAtomicLoad", 14588 argLen: 2, 14589 faultOnNilArg0: true, 14590 reg: regInfo{ 14591 inputs: []inputInfo{ 14592 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14593 }, 14594 outputs: []outputInfo{ 14595 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14596 }, 14597 }, 14598 }, 14599 { 14600 name: "LoweredAtomicStore", 14601 argLen: 3, 14602 faultOnNilArg0: true, 14603 hasSideEffects: true, 14604 reg: regInfo{ 14605 inputs: []inputInfo{ 14606 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14607 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14608 }, 14609 }, 14610 }, 14611 { 14612 name: "LoweredAtomicStorezero", 14613 argLen: 2, 14614 faultOnNilArg0: true, 14615 hasSideEffects: true, 14616 reg: regInfo{ 14617 inputs: []inputInfo{ 14618 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14619 }, 14620 }, 14621 }, 14622 { 14623 name: "LoweredAtomicExchange", 14624 argLen: 3, 14625 resultNotInArgs: true, 14626 faultOnNilArg0: true, 14627 hasSideEffects: true, 14628 reg: regInfo{ 14629 inputs: []inputInfo{ 14630 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14631 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14632 }, 14633 outputs: []outputInfo{ 14634 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14635 }, 14636 }, 14637 }, 14638 { 14639 name: "LoweredAtomicAdd", 14640 argLen: 3, 14641 resultNotInArgs: true, 14642 faultOnNilArg0: true, 14643 hasSideEffects: true, 14644 reg: regInfo{ 14645 inputs: []inputInfo{ 14646 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14647 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14648 }, 14649 outputs: []outputInfo{ 14650 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14651 }, 14652 }, 14653 }, 14654 { 14655 name: "LoweredAtomicAddconst", 14656 auxType: auxInt32, 14657 argLen: 2, 14658 resultNotInArgs: true, 14659 faultOnNilArg0: true, 14660 hasSideEffects: true, 14661 reg: regInfo{ 14662 inputs: []inputInfo{ 14663 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14664 }, 14665 outputs: []outputInfo{ 14666 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14667 }, 14668 }, 14669 }, 14670 { 14671 name: "LoweredAtomicCas", 14672 argLen: 4, 14673 resultNotInArgs: true, 14674 faultOnNilArg0: true, 14675 hasSideEffects: true, 14676 reg: regInfo{ 14677 inputs: []inputInfo{ 14678 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14679 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14680 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14681 }, 14682 outputs: []outputInfo{ 14683 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14684 }, 14685 }, 14686 }, 14687 { 14688 name: "LoweredAtomicAnd", 14689 argLen: 3, 14690 faultOnNilArg0: true, 14691 hasSideEffects: true, 14692 asm: mips.AAND, 14693 reg: regInfo{ 14694 inputs: []inputInfo{ 14695 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14696 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14697 }, 14698 }, 14699 }, 14700 { 14701 name: "LoweredAtomicOr", 14702 argLen: 3, 14703 faultOnNilArg0: true, 14704 hasSideEffects: true, 14705 asm: mips.AOR, 14706 reg: regInfo{ 14707 inputs: []inputInfo{ 14708 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14709 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14710 }, 14711 }, 14712 }, 14713 { 14714 name: "LoweredZero", 14715 auxType: auxInt32, 14716 argLen: 3, 14717 faultOnNilArg0: true, 14718 reg: regInfo{ 14719 inputs: []inputInfo{ 14720 {0, 2}, // R1 14721 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14722 }, 14723 clobbers: 2, // R1 14724 }, 14725 }, 14726 { 14727 name: "LoweredMove", 14728 auxType: auxInt32, 14729 argLen: 4, 14730 faultOnNilArg0: true, 14731 faultOnNilArg1: true, 14732 reg: regInfo{ 14733 inputs: []inputInfo{ 14734 {0, 4}, // R2 14735 {1, 2}, // R1 14736 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14737 }, 14738 clobbers: 6, // R1 R2 14739 }, 14740 }, 14741 { 14742 name: "LoweredNilCheck", 14743 argLen: 2, 14744 nilCheck: true, 14745 faultOnNilArg0: true, 14746 reg: regInfo{ 14747 inputs: []inputInfo{ 14748 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14749 }, 14750 }, 14751 }, 14752 { 14753 name: "FPFlagTrue", 14754 argLen: 1, 14755 reg: regInfo{ 14756 outputs: []outputInfo{ 14757 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14758 }, 14759 }, 14760 }, 14761 { 14762 name: "FPFlagFalse", 14763 argLen: 1, 14764 reg: regInfo{ 14765 outputs: []outputInfo{ 14766 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14767 }, 14768 }, 14769 }, 14770 { 14771 name: "LoweredGetClosurePtr", 14772 argLen: 0, 14773 reg: regInfo{ 14774 outputs: []outputInfo{ 14775 {0, 4194304}, // R22 14776 }, 14777 }, 14778 }, 14779 { 14780 name: "MOVWconvert", 14781 argLen: 2, 14782 asm: mips.AMOVW, 14783 reg: regInfo{ 14784 inputs: []inputInfo{ 14785 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14786 }, 14787 outputs: []outputInfo{ 14788 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14789 }, 14790 }, 14791 }, 14792 14793 { 14794 name: "ADDV", 14795 argLen: 2, 14796 commutative: true, 14797 asm: mips.AADDVU, 14798 reg: regInfo{ 14799 inputs: []inputInfo{ 14800 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14801 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14802 }, 14803 outputs: []outputInfo{ 14804 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14805 }, 14806 }, 14807 }, 14808 { 14809 name: "ADDVconst", 14810 auxType: auxInt64, 14811 argLen: 1, 14812 asm: mips.AADDVU, 14813 reg: regInfo{ 14814 inputs: []inputInfo{ 14815 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 14816 }, 14817 outputs: []outputInfo{ 14818 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14819 }, 14820 }, 14821 }, 14822 { 14823 name: "SUBV", 14824 argLen: 2, 14825 asm: mips.ASUBVU, 14826 reg: regInfo{ 14827 inputs: []inputInfo{ 14828 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14829 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14830 }, 14831 outputs: []outputInfo{ 14832 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14833 }, 14834 }, 14835 }, 14836 { 14837 name: "SUBVconst", 14838 auxType: auxInt64, 14839 argLen: 1, 14840 asm: mips.ASUBVU, 14841 reg: regInfo{ 14842 inputs: []inputInfo{ 14843 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14844 }, 14845 outputs: []outputInfo{ 14846 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14847 }, 14848 }, 14849 }, 14850 { 14851 name: "MULV", 14852 argLen: 2, 14853 commutative: true, 14854 asm: mips.AMULV, 14855 reg: regInfo{ 14856 inputs: []inputInfo{ 14857 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14858 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14859 }, 14860 outputs: []outputInfo{ 14861 {0, 1152921504606846976}, // HI 14862 {1, 2305843009213693952}, // LO 14863 }, 14864 }, 14865 }, 14866 { 14867 name: "MULVU", 14868 argLen: 2, 14869 commutative: true, 14870 asm: mips.AMULVU, 14871 reg: regInfo{ 14872 inputs: []inputInfo{ 14873 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14874 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14875 }, 14876 outputs: []outputInfo{ 14877 {0, 1152921504606846976}, // HI 14878 {1, 2305843009213693952}, // LO 14879 }, 14880 }, 14881 }, 14882 { 14883 name: "DIVV", 14884 argLen: 2, 14885 asm: mips.ADIVV, 14886 reg: regInfo{ 14887 inputs: []inputInfo{ 14888 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14889 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14890 }, 14891 outputs: []outputInfo{ 14892 {0, 1152921504606846976}, // HI 14893 {1, 2305843009213693952}, // LO 14894 }, 14895 }, 14896 }, 14897 { 14898 name: "DIVVU", 14899 argLen: 2, 14900 asm: mips.ADIVVU, 14901 reg: regInfo{ 14902 inputs: []inputInfo{ 14903 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14904 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14905 }, 14906 outputs: []outputInfo{ 14907 {0, 1152921504606846976}, // HI 14908 {1, 2305843009213693952}, // LO 14909 }, 14910 }, 14911 }, 14912 { 14913 name: "ADDF", 14914 argLen: 2, 14915 commutative: true, 14916 asm: mips.AADDF, 14917 reg: regInfo{ 14918 inputs: []inputInfo{ 14919 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14920 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14921 }, 14922 outputs: []outputInfo{ 14923 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14924 }, 14925 }, 14926 }, 14927 { 14928 name: "ADDD", 14929 argLen: 2, 14930 commutative: true, 14931 asm: mips.AADDD, 14932 reg: regInfo{ 14933 inputs: []inputInfo{ 14934 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14935 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14936 }, 14937 outputs: []outputInfo{ 14938 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14939 }, 14940 }, 14941 }, 14942 { 14943 name: "SUBF", 14944 argLen: 2, 14945 asm: mips.ASUBF, 14946 reg: regInfo{ 14947 inputs: []inputInfo{ 14948 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14949 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14950 }, 14951 outputs: []outputInfo{ 14952 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14953 }, 14954 }, 14955 }, 14956 { 14957 name: "SUBD", 14958 argLen: 2, 14959 asm: mips.ASUBD, 14960 reg: regInfo{ 14961 inputs: []inputInfo{ 14962 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14963 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14964 }, 14965 outputs: []outputInfo{ 14966 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14967 }, 14968 }, 14969 }, 14970 { 14971 name: "MULF", 14972 argLen: 2, 14973 commutative: true, 14974 asm: mips.AMULF, 14975 reg: regInfo{ 14976 inputs: []inputInfo{ 14977 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14978 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14979 }, 14980 outputs: []outputInfo{ 14981 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14982 }, 14983 }, 14984 }, 14985 { 14986 name: "MULD", 14987 argLen: 2, 14988 commutative: true, 14989 asm: mips.AMULD, 14990 reg: regInfo{ 14991 inputs: []inputInfo{ 14992 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14993 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14994 }, 14995 outputs: []outputInfo{ 14996 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14997 }, 14998 }, 14999 }, 15000 { 15001 name: "DIVF", 15002 argLen: 2, 15003 asm: mips.ADIVF, 15004 reg: regInfo{ 15005 inputs: []inputInfo{ 15006 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15007 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15008 }, 15009 outputs: []outputInfo{ 15010 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15011 }, 15012 }, 15013 }, 15014 { 15015 name: "DIVD", 15016 argLen: 2, 15017 asm: mips.ADIVD, 15018 reg: regInfo{ 15019 inputs: []inputInfo{ 15020 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15021 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15022 }, 15023 outputs: []outputInfo{ 15024 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15025 }, 15026 }, 15027 }, 15028 { 15029 name: "AND", 15030 argLen: 2, 15031 commutative: true, 15032 asm: mips.AAND, 15033 reg: regInfo{ 15034 inputs: []inputInfo{ 15035 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15036 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15037 }, 15038 outputs: []outputInfo{ 15039 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15040 }, 15041 }, 15042 }, 15043 { 15044 name: "ANDconst", 15045 auxType: auxInt64, 15046 argLen: 1, 15047 asm: mips.AAND, 15048 reg: regInfo{ 15049 inputs: []inputInfo{ 15050 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15051 }, 15052 outputs: []outputInfo{ 15053 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15054 }, 15055 }, 15056 }, 15057 { 15058 name: "OR", 15059 argLen: 2, 15060 commutative: true, 15061 asm: mips.AOR, 15062 reg: regInfo{ 15063 inputs: []inputInfo{ 15064 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15065 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15066 }, 15067 outputs: []outputInfo{ 15068 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15069 }, 15070 }, 15071 }, 15072 { 15073 name: "ORconst", 15074 auxType: auxInt64, 15075 argLen: 1, 15076 asm: mips.AOR, 15077 reg: regInfo{ 15078 inputs: []inputInfo{ 15079 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15080 }, 15081 outputs: []outputInfo{ 15082 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15083 }, 15084 }, 15085 }, 15086 { 15087 name: "XOR", 15088 argLen: 2, 15089 commutative: true, 15090 asm: mips.AXOR, 15091 reg: regInfo{ 15092 inputs: []inputInfo{ 15093 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15094 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15095 }, 15096 outputs: []outputInfo{ 15097 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15098 }, 15099 }, 15100 }, 15101 { 15102 name: "XORconst", 15103 auxType: auxInt64, 15104 argLen: 1, 15105 asm: mips.AXOR, 15106 reg: regInfo{ 15107 inputs: []inputInfo{ 15108 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15109 }, 15110 outputs: []outputInfo{ 15111 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15112 }, 15113 }, 15114 }, 15115 { 15116 name: "NOR", 15117 argLen: 2, 15118 commutative: true, 15119 asm: mips.ANOR, 15120 reg: regInfo{ 15121 inputs: []inputInfo{ 15122 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15123 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15124 }, 15125 outputs: []outputInfo{ 15126 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15127 }, 15128 }, 15129 }, 15130 { 15131 name: "NORconst", 15132 auxType: auxInt64, 15133 argLen: 1, 15134 asm: mips.ANOR, 15135 reg: regInfo{ 15136 inputs: []inputInfo{ 15137 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15138 }, 15139 outputs: []outputInfo{ 15140 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15141 }, 15142 }, 15143 }, 15144 { 15145 name: "NEGV", 15146 argLen: 1, 15147 reg: regInfo{ 15148 inputs: []inputInfo{ 15149 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15150 }, 15151 outputs: []outputInfo{ 15152 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15153 }, 15154 }, 15155 }, 15156 { 15157 name: "NEGF", 15158 argLen: 1, 15159 asm: mips.ANEGF, 15160 reg: regInfo{ 15161 inputs: []inputInfo{ 15162 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15163 }, 15164 outputs: []outputInfo{ 15165 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15166 }, 15167 }, 15168 }, 15169 { 15170 name: "NEGD", 15171 argLen: 1, 15172 asm: mips.ANEGD, 15173 reg: regInfo{ 15174 inputs: []inputInfo{ 15175 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15176 }, 15177 outputs: []outputInfo{ 15178 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15179 }, 15180 }, 15181 }, 15182 { 15183 name: "SLLV", 15184 argLen: 2, 15185 asm: mips.ASLLV, 15186 reg: regInfo{ 15187 inputs: []inputInfo{ 15188 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15189 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15190 }, 15191 outputs: []outputInfo{ 15192 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15193 }, 15194 }, 15195 }, 15196 { 15197 name: "SLLVconst", 15198 auxType: auxInt64, 15199 argLen: 1, 15200 asm: mips.ASLLV, 15201 reg: regInfo{ 15202 inputs: []inputInfo{ 15203 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15204 }, 15205 outputs: []outputInfo{ 15206 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15207 }, 15208 }, 15209 }, 15210 { 15211 name: "SRLV", 15212 argLen: 2, 15213 asm: mips.ASRLV, 15214 reg: regInfo{ 15215 inputs: []inputInfo{ 15216 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15217 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15218 }, 15219 outputs: []outputInfo{ 15220 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15221 }, 15222 }, 15223 }, 15224 { 15225 name: "SRLVconst", 15226 auxType: auxInt64, 15227 argLen: 1, 15228 asm: mips.ASRLV, 15229 reg: regInfo{ 15230 inputs: []inputInfo{ 15231 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15232 }, 15233 outputs: []outputInfo{ 15234 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15235 }, 15236 }, 15237 }, 15238 { 15239 name: "SRAV", 15240 argLen: 2, 15241 asm: mips.ASRAV, 15242 reg: regInfo{ 15243 inputs: []inputInfo{ 15244 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15245 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15246 }, 15247 outputs: []outputInfo{ 15248 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15249 }, 15250 }, 15251 }, 15252 { 15253 name: "SRAVconst", 15254 auxType: auxInt64, 15255 argLen: 1, 15256 asm: mips.ASRAV, 15257 reg: regInfo{ 15258 inputs: []inputInfo{ 15259 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15260 }, 15261 outputs: []outputInfo{ 15262 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15263 }, 15264 }, 15265 }, 15266 { 15267 name: "SGT", 15268 argLen: 2, 15269 asm: mips.ASGT, 15270 reg: regInfo{ 15271 inputs: []inputInfo{ 15272 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15273 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15274 }, 15275 outputs: []outputInfo{ 15276 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15277 }, 15278 }, 15279 }, 15280 { 15281 name: "SGTconst", 15282 auxType: auxInt64, 15283 argLen: 1, 15284 asm: mips.ASGT, 15285 reg: regInfo{ 15286 inputs: []inputInfo{ 15287 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15288 }, 15289 outputs: []outputInfo{ 15290 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15291 }, 15292 }, 15293 }, 15294 { 15295 name: "SGTU", 15296 argLen: 2, 15297 asm: mips.ASGTU, 15298 reg: regInfo{ 15299 inputs: []inputInfo{ 15300 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15301 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15302 }, 15303 outputs: []outputInfo{ 15304 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15305 }, 15306 }, 15307 }, 15308 { 15309 name: "SGTUconst", 15310 auxType: auxInt64, 15311 argLen: 1, 15312 asm: mips.ASGTU, 15313 reg: regInfo{ 15314 inputs: []inputInfo{ 15315 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15316 }, 15317 outputs: []outputInfo{ 15318 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15319 }, 15320 }, 15321 }, 15322 { 15323 name: "CMPEQF", 15324 argLen: 2, 15325 asm: mips.ACMPEQF, 15326 reg: regInfo{ 15327 inputs: []inputInfo{ 15328 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15329 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15330 }, 15331 }, 15332 }, 15333 { 15334 name: "CMPEQD", 15335 argLen: 2, 15336 asm: mips.ACMPEQD, 15337 reg: regInfo{ 15338 inputs: []inputInfo{ 15339 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15340 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15341 }, 15342 }, 15343 }, 15344 { 15345 name: "CMPGEF", 15346 argLen: 2, 15347 asm: mips.ACMPGEF, 15348 reg: regInfo{ 15349 inputs: []inputInfo{ 15350 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15351 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15352 }, 15353 }, 15354 }, 15355 { 15356 name: "CMPGED", 15357 argLen: 2, 15358 asm: mips.ACMPGED, 15359 reg: regInfo{ 15360 inputs: []inputInfo{ 15361 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15362 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15363 }, 15364 }, 15365 }, 15366 { 15367 name: "CMPGTF", 15368 argLen: 2, 15369 asm: mips.ACMPGTF, 15370 reg: regInfo{ 15371 inputs: []inputInfo{ 15372 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15373 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15374 }, 15375 }, 15376 }, 15377 { 15378 name: "CMPGTD", 15379 argLen: 2, 15380 asm: mips.ACMPGTD, 15381 reg: regInfo{ 15382 inputs: []inputInfo{ 15383 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15384 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15385 }, 15386 }, 15387 }, 15388 { 15389 name: "MOVVconst", 15390 auxType: auxInt64, 15391 argLen: 0, 15392 rematerializeable: true, 15393 asm: mips.AMOVV, 15394 reg: regInfo{ 15395 outputs: []outputInfo{ 15396 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15397 }, 15398 }, 15399 }, 15400 { 15401 name: "MOVFconst", 15402 auxType: auxFloat64, 15403 argLen: 0, 15404 rematerializeable: true, 15405 asm: mips.AMOVF, 15406 reg: regInfo{ 15407 outputs: []outputInfo{ 15408 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15409 }, 15410 }, 15411 }, 15412 { 15413 name: "MOVDconst", 15414 auxType: auxFloat64, 15415 argLen: 0, 15416 rematerializeable: true, 15417 asm: mips.AMOVD, 15418 reg: regInfo{ 15419 outputs: []outputInfo{ 15420 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15421 }, 15422 }, 15423 }, 15424 { 15425 name: "MOVVaddr", 15426 auxType: auxSymOff, 15427 argLen: 1, 15428 rematerializeable: true, 15429 symEffect: SymAddr, 15430 asm: mips.AMOVV, 15431 reg: regInfo{ 15432 inputs: []inputInfo{ 15433 {0, 4611686018460942336}, // SP SB 15434 }, 15435 outputs: []outputInfo{ 15436 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15437 }, 15438 }, 15439 }, 15440 { 15441 name: "MOVBload", 15442 auxType: auxSymOff, 15443 argLen: 2, 15444 faultOnNilArg0: true, 15445 symEffect: SymRead, 15446 asm: mips.AMOVB, 15447 reg: regInfo{ 15448 inputs: []inputInfo{ 15449 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15450 }, 15451 outputs: []outputInfo{ 15452 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15453 }, 15454 }, 15455 }, 15456 { 15457 name: "MOVBUload", 15458 auxType: auxSymOff, 15459 argLen: 2, 15460 faultOnNilArg0: true, 15461 symEffect: SymRead, 15462 asm: mips.AMOVBU, 15463 reg: regInfo{ 15464 inputs: []inputInfo{ 15465 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15466 }, 15467 outputs: []outputInfo{ 15468 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15469 }, 15470 }, 15471 }, 15472 { 15473 name: "MOVHload", 15474 auxType: auxSymOff, 15475 argLen: 2, 15476 faultOnNilArg0: true, 15477 symEffect: SymRead, 15478 asm: mips.AMOVH, 15479 reg: regInfo{ 15480 inputs: []inputInfo{ 15481 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15482 }, 15483 outputs: []outputInfo{ 15484 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15485 }, 15486 }, 15487 }, 15488 { 15489 name: "MOVHUload", 15490 auxType: auxSymOff, 15491 argLen: 2, 15492 faultOnNilArg0: true, 15493 symEffect: SymRead, 15494 asm: mips.AMOVHU, 15495 reg: regInfo{ 15496 inputs: []inputInfo{ 15497 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15498 }, 15499 outputs: []outputInfo{ 15500 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15501 }, 15502 }, 15503 }, 15504 { 15505 name: "MOVWload", 15506 auxType: auxSymOff, 15507 argLen: 2, 15508 faultOnNilArg0: true, 15509 symEffect: SymRead, 15510 asm: mips.AMOVW, 15511 reg: regInfo{ 15512 inputs: []inputInfo{ 15513 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15514 }, 15515 outputs: []outputInfo{ 15516 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15517 }, 15518 }, 15519 }, 15520 { 15521 name: "MOVWUload", 15522 auxType: auxSymOff, 15523 argLen: 2, 15524 faultOnNilArg0: true, 15525 symEffect: SymRead, 15526 asm: mips.AMOVWU, 15527 reg: regInfo{ 15528 inputs: []inputInfo{ 15529 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15530 }, 15531 outputs: []outputInfo{ 15532 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15533 }, 15534 }, 15535 }, 15536 { 15537 name: "MOVVload", 15538 auxType: auxSymOff, 15539 argLen: 2, 15540 faultOnNilArg0: true, 15541 symEffect: SymRead, 15542 asm: mips.AMOVV, 15543 reg: regInfo{ 15544 inputs: []inputInfo{ 15545 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15546 }, 15547 outputs: []outputInfo{ 15548 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15549 }, 15550 }, 15551 }, 15552 { 15553 name: "MOVFload", 15554 auxType: auxSymOff, 15555 argLen: 2, 15556 faultOnNilArg0: true, 15557 symEffect: SymRead, 15558 asm: mips.AMOVF, 15559 reg: regInfo{ 15560 inputs: []inputInfo{ 15561 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15562 }, 15563 outputs: []outputInfo{ 15564 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15565 }, 15566 }, 15567 }, 15568 { 15569 name: "MOVDload", 15570 auxType: auxSymOff, 15571 argLen: 2, 15572 faultOnNilArg0: true, 15573 symEffect: SymRead, 15574 asm: mips.AMOVD, 15575 reg: regInfo{ 15576 inputs: []inputInfo{ 15577 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15578 }, 15579 outputs: []outputInfo{ 15580 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15581 }, 15582 }, 15583 }, 15584 { 15585 name: "MOVBstore", 15586 auxType: auxSymOff, 15587 argLen: 3, 15588 faultOnNilArg0: true, 15589 symEffect: SymWrite, 15590 asm: mips.AMOVB, 15591 reg: regInfo{ 15592 inputs: []inputInfo{ 15593 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15594 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15595 }, 15596 }, 15597 }, 15598 { 15599 name: "MOVHstore", 15600 auxType: auxSymOff, 15601 argLen: 3, 15602 faultOnNilArg0: true, 15603 symEffect: SymWrite, 15604 asm: mips.AMOVH, 15605 reg: regInfo{ 15606 inputs: []inputInfo{ 15607 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15608 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15609 }, 15610 }, 15611 }, 15612 { 15613 name: "MOVWstore", 15614 auxType: auxSymOff, 15615 argLen: 3, 15616 faultOnNilArg0: true, 15617 symEffect: SymWrite, 15618 asm: mips.AMOVW, 15619 reg: regInfo{ 15620 inputs: []inputInfo{ 15621 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15622 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15623 }, 15624 }, 15625 }, 15626 { 15627 name: "MOVVstore", 15628 auxType: auxSymOff, 15629 argLen: 3, 15630 faultOnNilArg0: true, 15631 symEffect: SymWrite, 15632 asm: mips.AMOVV, 15633 reg: regInfo{ 15634 inputs: []inputInfo{ 15635 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15636 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15637 }, 15638 }, 15639 }, 15640 { 15641 name: "MOVFstore", 15642 auxType: auxSymOff, 15643 argLen: 3, 15644 faultOnNilArg0: true, 15645 symEffect: SymWrite, 15646 asm: mips.AMOVF, 15647 reg: regInfo{ 15648 inputs: []inputInfo{ 15649 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15650 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15651 }, 15652 }, 15653 }, 15654 { 15655 name: "MOVDstore", 15656 auxType: auxSymOff, 15657 argLen: 3, 15658 faultOnNilArg0: true, 15659 symEffect: SymWrite, 15660 asm: mips.AMOVD, 15661 reg: regInfo{ 15662 inputs: []inputInfo{ 15663 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15664 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15665 }, 15666 }, 15667 }, 15668 { 15669 name: "MOVBstorezero", 15670 auxType: auxSymOff, 15671 argLen: 2, 15672 faultOnNilArg0: true, 15673 symEffect: SymWrite, 15674 asm: mips.AMOVB, 15675 reg: regInfo{ 15676 inputs: []inputInfo{ 15677 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15678 }, 15679 }, 15680 }, 15681 { 15682 name: "MOVHstorezero", 15683 auxType: auxSymOff, 15684 argLen: 2, 15685 faultOnNilArg0: true, 15686 symEffect: SymWrite, 15687 asm: mips.AMOVH, 15688 reg: regInfo{ 15689 inputs: []inputInfo{ 15690 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15691 }, 15692 }, 15693 }, 15694 { 15695 name: "MOVWstorezero", 15696 auxType: auxSymOff, 15697 argLen: 2, 15698 faultOnNilArg0: true, 15699 symEffect: SymWrite, 15700 asm: mips.AMOVW, 15701 reg: regInfo{ 15702 inputs: []inputInfo{ 15703 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15704 }, 15705 }, 15706 }, 15707 { 15708 name: "MOVVstorezero", 15709 auxType: auxSymOff, 15710 argLen: 2, 15711 faultOnNilArg0: true, 15712 symEffect: SymWrite, 15713 asm: mips.AMOVV, 15714 reg: regInfo{ 15715 inputs: []inputInfo{ 15716 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15717 }, 15718 }, 15719 }, 15720 { 15721 name: "MOVBreg", 15722 argLen: 1, 15723 asm: mips.AMOVB, 15724 reg: regInfo{ 15725 inputs: []inputInfo{ 15726 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15727 }, 15728 outputs: []outputInfo{ 15729 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15730 }, 15731 }, 15732 }, 15733 { 15734 name: "MOVBUreg", 15735 argLen: 1, 15736 asm: mips.AMOVBU, 15737 reg: regInfo{ 15738 inputs: []inputInfo{ 15739 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15740 }, 15741 outputs: []outputInfo{ 15742 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15743 }, 15744 }, 15745 }, 15746 { 15747 name: "MOVHreg", 15748 argLen: 1, 15749 asm: mips.AMOVH, 15750 reg: regInfo{ 15751 inputs: []inputInfo{ 15752 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15753 }, 15754 outputs: []outputInfo{ 15755 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15756 }, 15757 }, 15758 }, 15759 { 15760 name: "MOVHUreg", 15761 argLen: 1, 15762 asm: mips.AMOVHU, 15763 reg: regInfo{ 15764 inputs: []inputInfo{ 15765 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15766 }, 15767 outputs: []outputInfo{ 15768 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15769 }, 15770 }, 15771 }, 15772 { 15773 name: "MOVWreg", 15774 argLen: 1, 15775 asm: mips.AMOVW, 15776 reg: regInfo{ 15777 inputs: []inputInfo{ 15778 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15779 }, 15780 outputs: []outputInfo{ 15781 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15782 }, 15783 }, 15784 }, 15785 { 15786 name: "MOVWUreg", 15787 argLen: 1, 15788 asm: mips.AMOVWU, 15789 reg: regInfo{ 15790 inputs: []inputInfo{ 15791 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15792 }, 15793 outputs: []outputInfo{ 15794 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15795 }, 15796 }, 15797 }, 15798 { 15799 name: "MOVVreg", 15800 argLen: 1, 15801 asm: mips.AMOVV, 15802 reg: regInfo{ 15803 inputs: []inputInfo{ 15804 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15805 }, 15806 outputs: []outputInfo{ 15807 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15808 }, 15809 }, 15810 }, 15811 { 15812 name: "MOVVnop", 15813 argLen: 1, 15814 resultInArg0: true, 15815 reg: regInfo{ 15816 inputs: []inputInfo{ 15817 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15818 }, 15819 outputs: []outputInfo{ 15820 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15821 }, 15822 }, 15823 }, 15824 { 15825 name: "MOVWF", 15826 argLen: 1, 15827 asm: mips.AMOVWF, 15828 reg: regInfo{ 15829 inputs: []inputInfo{ 15830 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15831 }, 15832 outputs: []outputInfo{ 15833 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15834 }, 15835 }, 15836 }, 15837 { 15838 name: "MOVWD", 15839 argLen: 1, 15840 asm: mips.AMOVWD, 15841 reg: regInfo{ 15842 inputs: []inputInfo{ 15843 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15844 }, 15845 outputs: []outputInfo{ 15846 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15847 }, 15848 }, 15849 }, 15850 { 15851 name: "MOVVF", 15852 argLen: 1, 15853 asm: mips.AMOVVF, 15854 reg: regInfo{ 15855 inputs: []inputInfo{ 15856 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15857 }, 15858 outputs: []outputInfo{ 15859 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15860 }, 15861 }, 15862 }, 15863 { 15864 name: "MOVVD", 15865 argLen: 1, 15866 asm: mips.AMOVVD, 15867 reg: regInfo{ 15868 inputs: []inputInfo{ 15869 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15870 }, 15871 outputs: []outputInfo{ 15872 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15873 }, 15874 }, 15875 }, 15876 { 15877 name: "TRUNCFW", 15878 argLen: 1, 15879 asm: mips.ATRUNCFW, 15880 reg: regInfo{ 15881 inputs: []inputInfo{ 15882 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15883 }, 15884 outputs: []outputInfo{ 15885 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15886 }, 15887 }, 15888 }, 15889 { 15890 name: "TRUNCDW", 15891 argLen: 1, 15892 asm: mips.ATRUNCDW, 15893 reg: regInfo{ 15894 inputs: []inputInfo{ 15895 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15896 }, 15897 outputs: []outputInfo{ 15898 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15899 }, 15900 }, 15901 }, 15902 { 15903 name: "TRUNCFV", 15904 argLen: 1, 15905 asm: mips.ATRUNCFV, 15906 reg: regInfo{ 15907 inputs: []inputInfo{ 15908 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15909 }, 15910 outputs: []outputInfo{ 15911 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15912 }, 15913 }, 15914 }, 15915 { 15916 name: "TRUNCDV", 15917 argLen: 1, 15918 asm: mips.ATRUNCDV, 15919 reg: regInfo{ 15920 inputs: []inputInfo{ 15921 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15922 }, 15923 outputs: []outputInfo{ 15924 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15925 }, 15926 }, 15927 }, 15928 { 15929 name: "MOVFD", 15930 argLen: 1, 15931 asm: mips.AMOVFD, 15932 reg: regInfo{ 15933 inputs: []inputInfo{ 15934 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15935 }, 15936 outputs: []outputInfo{ 15937 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15938 }, 15939 }, 15940 }, 15941 { 15942 name: "MOVDF", 15943 argLen: 1, 15944 asm: mips.AMOVDF, 15945 reg: regInfo{ 15946 inputs: []inputInfo{ 15947 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15948 }, 15949 outputs: []outputInfo{ 15950 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15951 }, 15952 }, 15953 }, 15954 { 15955 name: "CALLstatic", 15956 auxType: auxSymOff, 15957 argLen: 1, 15958 clobberFlags: true, 15959 call: true, 15960 symEffect: SymNone, 15961 reg: regInfo{ 15962 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15963 }, 15964 }, 15965 { 15966 name: "CALLclosure", 15967 auxType: auxInt64, 15968 argLen: 3, 15969 clobberFlags: true, 15970 call: true, 15971 reg: regInfo{ 15972 inputs: []inputInfo{ 15973 {1, 4194304}, // R22 15974 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 15975 }, 15976 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15977 }, 15978 }, 15979 { 15980 name: "CALLinter", 15981 auxType: auxInt64, 15982 argLen: 2, 15983 clobberFlags: true, 15984 call: true, 15985 reg: regInfo{ 15986 inputs: []inputInfo{ 15987 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15988 }, 15989 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15990 }, 15991 }, 15992 { 15993 name: "DUFFZERO", 15994 auxType: auxInt64, 15995 argLen: 2, 15996 faultOnNilArg0: true, 15997 reg: regInfo{ 15998 inputs: []inputInfo{ 15999 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16000 }, 16001 clobbers: 134217730, // R1 R31 16002 }, 16003 }, 16004 { 16005 name: "LoweredZero", 16006 auxType: auxInt64, 16007 argLen: 3, 16008 clobberFlags: true, 16009 faultOnNilArg0: true, 16010 reg: regInfo{ 16011 inputs: []inputInfo{ 16012 {0, 2}, // R1 16013 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16014 }, 16015 clobbers: 2, // R1 16016 }, 16017 }, 16018 { 16019 name: "LoweredMove", 16020 auxType: auxInt64, 16021 argLen: 4, 16022 clobberFlags: true, 16023 faultOnNilArg0: true, 16024 faultOnNilArg1: true, 16025 reg: regInfo{ 16026 inputs: []inputInfo{ 16027 {0, 4}, // R2 16028 {1, 2}, // R1 16029 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16030 }, 16031 clobbers: 6, // R1 R2 16032 }, 16033 }, 16034 { 16035 name: "LoweredNilCheck", 16036 argLen: 2, 16037 nilCheck: true, 16038 faultOnNilArg0: true, 16039 reg: regInfo{ 16040 inputs: []inputInfo{ 16041 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16042 }, 16043 }, 16044 }, 16045 { 16046 name: "FPFlagTrue", 16047 argLen: 1, 16048 reg: regInfo{ 16049 outputs: []outputInfo{ 16050 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16051 }, 16052 }, 16053 }, 16054 { 16055 name: "FPFlagFalse", 16056 argLen: 1, 16057 reg: regInfo{ 16058 outputs: []outputInfo{ 16059 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16060 }, 16061 }, 16062 }, 16063 { 16064 name: "LoweredGetClosurePtr", 16065 argLen: 0, 16066 reg: regInfo{ 16067 outputs: []outputInfo{ 16068 {0, 4194304}, // R22 16069 }, 16070 }, 16071 }, 16072 { 16073 name: "MOVVconvert", 16074 argLen: 2, 16075 asm: mips.AMOVV, 16076 reg: regInfo{ 16077 inputs: []inputInfo{ 16078 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16079 }, 16080 outputs: []outputInfo{ 16081 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16082 }, 16083 }, 16084 }, 16085 16086 { 16087 name: "ADD", 16088 argLen: 2, 16089 commutative: true, 16090 asm: ppc64.AADD, 16091 reg: regInfo{ 16092 inputs: []inputInfo{ 16093 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16094 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16095 }, 16096 outputs: []outputInfo{ 16097 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16098 }, 16099 }, 16100 }, 16101 { 16102 name: "ADDconst", 16103 auxType: auxSymOff, 16104 argLen: 1, 16105 symEffect: SymAddr, 16106 asm: ppc64.AADD, 16107 reg: regInfo{ 16108 inputs: []inputInfo{ 16109 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16110 }, 16111 outputs: []outputInfo{ 16112 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16113 }, 16114 }, 16115 }, 16116 { 16117 name: "FADD", 16118 argLen: 2, 16119 commutative: true, 16120 asm: ppc64.AFADD, 16121 reg: regInfo{ 16122 inputs: []inputInfo{ 16123 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16124 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16125 }, 16126 outputs: []outputInfo{ 16127 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16128 }, 16129 }, 16130 }, 16131 { 16132 name: "FADDS", 16133 argLen: 2, 16134 commutative: true, 16135 asm: ppc64.AFADDS, 16136 reg: regInfo{ 16137 inputs: []inputInfo{ 16138 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16139 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16140 }, 16141 outputs: []outputInfo{ 16142 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16143 }, 16144 }, 16145 }, 16146 { 16147 name: "SUB", 16148 argLen: 2, 16149 asm: ppc64.ASUB, 16150 reg: regInfo{ 16151 inputs: []inputInfo{ 16152 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16153 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16154 }, 16155 outputs: []outputInfo{ 16156 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16157 }, 16158 }, 16159 }, 16160 { 16161 name: "FSUB", 16162 argLen: 2, 16163 asm: ppc64.AFSUB, 16164 reg: regInfo{ 16165 inputs: []inputInfo{ 16166 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16167 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16168 }, 16169 outputs: []outputInfo{ 16170 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16171 }, 16172 }, 16173 }, 16174 { 16175 name: "FSUBS", 16176 argLen: 2, 16177 asm: ppc64.AFSUBS, 16178 reg: regInfo{ 16179 inputs: []inputInfo{ 16180 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16181 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16182 }, 16183 outputs: []outputInfo{ 16184 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16185 }, 16186 }, 16187 }, 16188 { 16189 name: "MULLD", 16190 argLen: 2, 16191 commutative: true, 16192 asm: ppc64.AMULLD, 16193 reg: regInfo{ 16194 inputs: []inputInfo{ 16195 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16196 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16197 }, 16198 outputs: []outputInfo{ 16199 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16200 }, 16201 }, 16202 }, 16203 { 16204 name: "MULLW", 16205 argLen: 2, 16206 commutative: true, 16207 asm: ppc64.AMULLW, 16208 reg: regInfo{ 16209 inputs: []inputInfo{ 16210 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16211 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16212 }, 16213 outputs: []outputInfo{ 16214 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16215 }, 16216 }, 16217 }, 16218 { 16219 name: "MULHD", 16220 argLen: 2, 16221 commutative: true, 16222 asm: ppc64.AMULHD, 16223 reg: regInfo{ 16224 inputs: []inputInfo{ 16225 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16226 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16227 }, 16228 outputs: []outputInfo{ 16229 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16230 }, 16231 }, 16232 }, 16233 { 16234 name: "MULHW", 16235 argLen: 2, 16236 commutative: true, 16237 asm: ppc64.AMULHW, 16238 reg: regInfo{ 16239 inputs: []inputInfo{ 16240 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16241 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16242 }, 16243 outputs: []outputInfo{ 16244 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16245 }, 16246 }, 16247 }, 16248 { 16249 name: "MULHDU", 16250 argLen: 2, 16251 commutative: true, 16252 asm: ppc64.AMULHDU, 16253 reg: regInfo{ 16254 inputs: []inputInfo{ 16255 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16256 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16257 }, 16258 outputs: []outputInfo{ 16259 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16260 }, 16261 }, 16262 }, 16263 { 16264 name: "MULHWU", 16265 argLen: 2, 16266 commutative: true, 16267 asm: ppc64.AMULHWU, 16268 reg: regInfo{ 16269 inputs: []inputInfo{ 16270 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16271 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16272 }, 16273 outputs: []outputInfo{ 16274 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16275 }, 16276 }, 16277 }, 16278 { 16279 name: "FMUL", 16280 argLen: 2, 16281 commutative: true, 16282 asm: ppc64.AFMUL, 16283 reg: regInfo{ 16284 inputs: []inputInfo{ 16285 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16286 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16287 }, 16288 outputs: []outputInfo{ 16289 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16290 }, 16291 }, 16292 }, 16293 { 16294 name: "FMULS", 16295 argLen: 2, 16296 commutative: true, 16297 asm: ppc64.AFMULS, 16298 reg: regInfo{ 16299 inputs: []inputInfo{ 16300 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16301 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16302 }, 16303 outputs: []outputInfo{ 16304 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16305 }, 16306 }, 16307 }, 16308 { 16309 name: "FMADD", 16310 argLen: 3, 16311 asm: ppc64.AFMADD, 16312 reg: regInfo{ 16313 inputs: []inputInfo{ 16314 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16315 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16316 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16317 }, 16318 outputs: []outputInfo{ 16319 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16320 }, 16321 }, 16322 }, 16323 { 16324 name: "FMADDS", 16325 argLen: 3, 16326 asm: ppc64.AFMADDS, 16327 reg: regInfo{ 16328 inputs: []inputInfo{ 16329 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16330 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16331 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16332 }, 16333 outputs: []outputInfo{ 16334 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16335 }, 16336 }, 16337 }, 16338 { 16339 name: "FMSUB", 16340 argLen: 3, 16341 asm: ppc64.AFMSUB, 16342 reg: regInfo{ 16343 inputs: []inputInfo{ 16344 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16345 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16346 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16347 }, 16348 outputs: []outputInfo{ 16349 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16350 }, 16351 }, 16352 }, 16353 { 16354 name: "FMSUBS", 16355 argLen: 3, 16356 asm: ppc64.AFMSUBS, 16357 reg: regInfo{ 16358 inputs: []inputInfo{ 16359 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16360 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16361 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16362 }, 16363 outputs: []outputInfo{ 16364 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16365 }, 16366 }, 16367 }, 16368 { 16369 name: "SRAD", 16370 argLen: 2, 16371 asm: ppc64.ASRAD, 16372 reg: regInfo{ 16373 inputs: []inputInfo{ 16374 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16375 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16376 }, 16377 outputs: []outputInfo{ 16378 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16379 }, 16380 }, 16381 }, 16382 { 16383 name: "SRAW", 16384 argLen: 2, 16385 asm: ppc64.ASRAW, 16386 reg: regInfo{ 16387 inputs: []inputInfo{ 16388 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16389 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16390 }, 16391 outputs: []outputInfo{ 16392 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16393 }, 16394 }, 16395 }, 16396 { 16397 name: "SRD", 16398 argLen: 2, 16399 asm: ppc64.ASRD, 16400 reg: regInfo{ 16401 inputs: []inputInfo{ 16402 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16403 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16404 }, 16405 outputs: []outputInfo{ 16406 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16407 }, 16408 }, 16409 }, 16410 { 16411 name: "SRW", 16412 argLen: 2, 16413 asm: ppc64.ASRW, 16414 reg: regInfo{ 16415 inputs: []inputInfo{ 16416 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16417 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16418 }, 16419 outputs: []outputInfo{ 16420 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16421 }, 16422 }, 16423 }, 16424 { 16425 name: "SLD", 16426 argLen: 2, 16427 asm: ppc64.ASLD, 16428 reg: regInfo{ 16429 inputs: []inputInfo{ 16430 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16431 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16432 }, 16433 outputs: []outputInfo{ 16434 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16435 }, 16436 }, 16437 }, 16438 { 16439 name: "SLW", 16440 argLen: 2, 16441 asm: ppc64.ASLW, 16442 reg: regInfo{ 16443 inputs: []inputInfo{ 16444 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16445 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16446 }, 16447 outputs: []outputInfo{ 16448 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16449 }, 16450 }, 16451 }, 16452 { 16453 name: "ADDconstForCarry", 16454 auxType: auxInt16, 16455 argLen: 1, 16456 asm: ppc64.AADDC, 16457 reg: regInfo{ 16458 inputs: []inputInfo{ 16459 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16460 }, 16461 clobbers: 2147483648, // R31 16462 }, 16463 }, 16464 { 16465 name: "MaskIfNotCarry", 16466 argLen: 1, 16467 asm: ppc64.AADDME, 16468 reg: regInfo{ 16469 outputs: []outputInfo{ 16470 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16471 }, 16472 }, 16473 }, 16474 { 16475 name: "SRADconst", 16476 auxType: auxInt64, 16477 argLen: 1, 16478 asm: ppc64.ASRAD, 16479 reg: regInfo{ 16480 inputs: []inputInfo{ 16481 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16482 }, 16483 outputs: []outputInfo{ 16484 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16485 }, 16486 }, 16487 }, 16488 { 16489 name: "SRAWconst", 16490 auxType: auxInt64, 16491 argLen: 1, 16492 asm: ppc64.ASRAW, 16493 reg: regInfo{ 16494 inputs: []inputInfo{ 16495 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16496 }, 16497 outputs: []outputInfo{ 16498 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16499 }, 16500 }, 16501 }, 16502 { 16503 name: "SRDconst", 16504 auxType: auxInt64, 16505 argLen: 1, 16506 asm: ppc64.ASRD, 16507 reg: regInfo{ 16508 inputs: []inputInfo{ 16509 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16510 }, 16511 outputs: []outputInfo{ 16512 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16513 }, 16514 }, 16515 }, 16516 { 16517 name: "SRWconst", 16518 auxType: auxInt64, 16519 argLen: 1, 16520 asm: ppc64.ASRW, 16521 reg: regInfo{ 16522 inputs: []inputInfo{ 16523 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16524 }, 16525 outputs: []outputInfo{ 16526 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16527 }, 16528 }, 16529 }, 16530 { 16531 name: "SLDconst", 16532 auxType: auxInt64, 16533 argLen: 1, 16534 asm: ppc64.ASLD, 16535 reg: regInfo{ 16536 inputs: []inputInfo{ 16537 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16538 }, 16539 outputs: []outputInfo{ 16540 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16541 }, 16542 }, 16543 }, 16544 { 16545 name: "SLWconst", 16546 auxType: auxInt64, 16547 argLen: 1, 16548 asm: ppc64.ASLW, 16549 reg: regInfo{ 16550 inputs: []inputInfo{ 16551 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16552 }, 16553 outputs: []outputInfo{ 16554 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16555 }, 16556 }, 16557 }, 16558 { 16559 name: "ROTLconst", 16560 auxType: auxInt64, 16561 argLen: 1, 16562 asm: ppc64.AROTL, 16563 reg: regInfo{ 16564 inputs: []inputInfo{ 16565 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16566 }, 16567 outputs: []outputInfo{ 16568 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16569 }, 16570 }, 16571 }, 16572 { 16573 name: "ROTLWconst", 16574 auxType: auxInt64, 16575 argLen: 1, 16576 asm: ppc64.AROTLW, 16577 reg: regInfo{ 16578 inputs: []inputInfo{ 16579 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16580 }, 16581 outputs: []outputInfo{ 16582 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16583 }, 16584 }, 16585 }, 16586 { 16587 name: "CNTLZD", 16588 argLen: 1, 16589 clobberFlags: true, 16590 asm: ppc64.ACNTLZD, 16591 reg: regInfo{ 16592 inputs: []inputInfo{ 16593 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16594 }, 16595 outputs: []outputInfo{ 16596 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16597 }, 16598 }, 16599 }, 16600 { 16601 name: "CNTLZW", 16602 argLen: 1, 16603 clobberFlags: true, 16604 asm: ppc64.ACNTLZW, 16605 reg: regInfo{ 16606 inputs: []inputInfo{ 16607 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16608 }, 16609 outputs: []outputInfo{ 16610 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16611 }, 16612 }, 16613 }, 16614 { 16615 name: "POPCNTD", 16616 argLen: 1, 16617 asm: ppc64.APOPCNTD, 16618 reg: regInfo{ 16619 inputs: []inputInfo{ 16620 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16621 }, 16622 outputs: []outputInfo{ 16623 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16624 }, 16625 }, 16626 }, 16627 { 16628 name: "POPCNTW", 16629 argLen: 1, 16630 asm: ppc64.APOPCNTW, 16631 reg: regInfo{ 16632 inputs: []inputInfo{ 16633 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16634 }, 16635 outputs: []outputInfo{ 16636 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16637 }, 16638 }, 16639 }, 16640 { 16641 name: "POPCNTB", 16642 argLen: 1, 16643 asm: ppc64.APOPCNTB, 16644 reg: regInfo{ 16645 inputs: []inputInfo{ 16646 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16647 }, 16648 outputs: []outputInfo{ 16649 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16650 }, 16651 }, 16652 }, 16653 { 16654 name: "FDIV", 16655 argLen: 2, 16656 asm: ppc64.AFDIV, 16657 reg: regInfo{ 16658 inputs: []inputInfo{ 16659 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16660 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16661 }, 16662 outputs: []outputInfo{ 16663 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16664 }, 16665 }, 16666 }, 16667 { 16668 name: "FDIVS", 16669 argLen: 2, 16670 asm: ppc64.AFDIVS, 16671 reg: regInfo{ 16672 inputs: []inputInfo{ 16673 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16674 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16675 }, 16676 outputs: []outputInfo{ 16677 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16678 }, 16679 }, 16680 }, 16681 { 16682 name: "DIVD", 16683 argLen: 2, 16684 asm: ppc64.ADIVD, 16685 reg: regInfo{ 16686 inputs: []inputInfo{ 16687 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16688 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16689 }, 16690 outputs: []outputInfo{ 16691 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16692 }, 16693 }, 16694 }, 16695 { 16696 name: "DIVW", 16697 argLen: 2, 16698 asm: ppc64.ADIVW, 16699 reg: regInfo{ 16700 inputs: []inputInfo{ 16701 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16702 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16703 }, 16704 outputs: []outputInfo{ 16705 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16706 }, 16707 }, 16708 }, 16709 { 16710 name: "DIVDU", 16711 argLen: 2, 16712 asm: ppc64.ADIVDU, 16713 reg: regInfo{ 16714 inputs: []inputInfo{ 16715 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16716 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16717 }, 16718 outputs: []outputInfo{ 16719 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16720 }, 16721 }, 16722 }, 16723 { 16724 name: "DIVWU", 16725 argLen: 2, 16726 asm: ppc64.ADIVWU, 16727 reg: regInfo{ 16728 inputs: []inputInfo{ 16729 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16730 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16731 }, 16732 outputs: []outputInfo{ 16733 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16734 }, 16735 }, 16736 }, 16737 { 16738 name: "FCTIDZ", 16739 argLen: 1, 16740 asm: ppc64.AFCTIDZ, 16741 reg: regInfo{ 16742 inputs: []inputInfo{ 16743 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16744 }, 16745 outputs: []outputInfo{ 16746 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16747 }, 16748 }, 16749 }, 16750 { 16751 name: "FCTIWZ", 16752 argLen: 1, 16753 asm: ppc64.AFCTIWZ, 16754 reg: regInfo{ 16755 inputs: []inputInfo{ 16756 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16757 }, 16758 outputs: []outputInfo{ 16759 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16760 }, 16761 }, 16762 }, 16763 { 16764 name: "FCFID", 16765 argLen: 1, 16766 asm: ppc64.AFCFID, 16767 reg: regInfo{ 16768 inputs: []inputInfo{ 16769 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16770 }, 16771 outputs: []outputInfo{ 16772 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16773 }, 16774 }, 16775 }, 16776 { 16777 name: "FRSP", 16778 argLen: 1, 16779 asm: ppc64.AFRSP, 16780 reg: regInfo{ 16781 inputs: []inputInfo{ 16782 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16783 }, 16784 outputs: []outputInfo{ 16785 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16786 }, 16787 }, 16788 }, 16789 { 16790 name: "Xf2i64", 16791 argLen: 1, 16792 reg: regInfo{ 16793 inputs: []inputInfo{ 16794 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16795 }, 16796 outputs: []outputInfo{ 16797 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16798 }, 16799 }, 16800 }, 16801 { 16802 name: "Xi2f64", 16803 argLen: 1, 16804 reg: regInfo{ 16805 inputs: []inputInfo{ 16806 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16807 }, 16808 outputs: []outputInfo{ 16809 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16810 }, 16811 }, 16812 }, 16813 { 16814 name: "AND", 16815 argLen: 2, 16816 commutative: true, 16817 asm: ppc64.AAND, 16818 reg: regInfo{ 16819 inputs: []inputInfo{ 16820 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16821 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16822 }, 16823 outputs: []outputInfo{ 16824 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16825 }, 16826 }, 16827 }, 16828 { 16829 name: "ANDN", 16830 argLen: 2, 16831 asm: ppc64.AANDN, 16832 reg: regInfo{ 16833 inputs: []inputInfo{ 16834 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16835 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16836 }, 16837 outputs: []outputInfo{ 16838 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16839 }, 16840 }, 16841 }, 16842 { 16843 name: "OR", 16844 argLen: 2, 16845 commutative: true, 16846 asm: ppc64.AOR, 16847 reg: regInfo{ 16848 inputs: []inputInfo{ 16849 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16850 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16851 }, 16852 outputs: []outputInfo{ 16853 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16854 }, 16855 }, 16856 }, 16857 { 16858 name: "ORN", 16859 argLen: 2, 16860 asm: ppc64.AORN, 16861 reg: regInfo{ 16862 inputs: []inputInfo{ 16863 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16864 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16865 }, 16866 outputs: []outputInfo{ 16867 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16868 }, 16869 }, 16870 }, 16871 { 16872 name: "NOR", 16873 argLen: 2, 16874 commutative: true, 16875 asm: ppc64.ANOR, 16876 reg: regInfo{ 16877 inputs: []inputInfo{ 16878 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16879 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16880 }, 16881 outputs: []outputInfo{ 16882 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16883 }, 16884 }, 16885 }, 16886 { 16887 name: "XOR", 16888 argLen: 2, 16889 commutative: true, 16890 asm: ppc64.AXOR, 16891 reg: regInfo{ 16892 inputs: []inputInfo{ 16893 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16894 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16895 }, 16896 outputs: []outputInfo{ 16897 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16898 }, 16899 }, 16900 }, 16901 { 16902 name: "EQV", 16903 argLen: 2, 16904 commutative: true, 16905 asm: ppc64.AEQV, 16906 reg: regInfo{ 16907 inputs: []inputInfo{ 16908 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16909 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16910 }, 16911 outputs: []outputInfo{ 16912 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16913 }, 16914 }, 16915 }, 16916 { 16917 name: "NEG", 16918 argLen: 1, 16919 asm: ppc64.ANEG, 16920 reg: regInfo{ 16921 inputs: []inputInfo{ 16922 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16923 }, 16924 outputs: []outputInfo{ 16925 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16926 }, 16927 }, 16928 }, 16929 { 16930 name: "FNEG", 16931 argLen: 1, 16932 asm: ppc64.AFNEG, 16933 reg: regInfo{ 16934 inputs: []inputInfo{ 16935 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16936 }, 16937 outputs: []outputInfo{ 16938 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16939 }, 16940 }, 16941 }, 16942 { 16943 name: "FSQRT", 16944 argLen: 1, 16945 asm: ppc64.AFSQRT, 16946 reg: regInfo{ 16947 inputs: []inputInfo{ 16948 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16949 }, 16950 outputs: []outputInfo{ 16951 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16952 }, 16953 }, 16954 }, 16955 { 16956 name: "FSQRTS", 16957 argLen: 1, 16958 asm: ppc64.AFSQRTS, 16959 reg: regInfo{ 16960 inputs: []inputInfo{ 16961 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16962 }, 16963 outputs: []outputInfo{ 16964 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16965 }, 16966 }, 16967 }, 16968 { 16969 name: "FFLOOR", 16970 argLen: 1, 16971 asm: ppc64.AFRIM, 16972 reg: regInfo{ 16973 inputs: []inputInfo{ 16974 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16975 }, 16976 outputs: []outputInfo{ 16977 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16978 }, 16979 }, 16980 }, 16981 { 16982 name: "FCEIL", 16983 argLen: 1, 16984 asm: ppc64.AFRIP, 16985 reg: regInfo{ 16986 inputs: []inputInfo{ 16987 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16988 }, 16989 outputs: []outputInfo{ 16990 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16991 }, 16992 }, 16993 }, 16994 { 16995 name: "FTRUNC", 16996 argLen: 1, 16997 asm: ppc64.AFRIZ, 16998 reg: regInfo{ 16999 inputs: []inputInfo{ 17000 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17001 }, 17002 outputs: []outputInfo{ 17003 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17004 }, 17005 }, 17006 }, 17007 { 17008 name: "ORconst", 17009 auxType: auxInt64, 17010 argLen: 1, 17011 asm: ppc64.AOR, 17012 reg: regInfo{ 17013 inputs: []inputInfo{ 17014 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17015 }, 17016 outputs: []outputInfo{ 17017 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17018 }, 17019 }, 17020 }, 17021 { 17022 name: "XORconst", 17023 auxType: auxInt64, 17024 argLen: 1, 17025 asm: ppc64.AXOR, 17026 reg: regInfo{ 17027 inputs: []inputInfo{ 17028 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17029 }, 17030 outputs: []outputInfo{ 17031 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17032 }, 17033 }, 17034 }, 17035 { 17036 name: "ANDconst", 17037 auxType: auxInt64, 17038 argLen: 1, 17039 clobberFlags: true, 17040 asm: ppc64.AANDCC, 17041 reg: regInfo{ 17042 inputs: []inputInfo{ 17043 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17044 }, 17045 outputs: []outputInfo{ 17046 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17047 }, 17048 }, 17049 }, 17050 { 17051 name: "ANDCCconst", 17052 auxType: auxInt64, 17053 argLen: 1, 17054 asm: ppc64.AANDCC, 17055 reg: regInfo{ 17056 inputs: []inputInfo{ 17057 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17058 }, 17059 }, 17060 }, 17061 { 17062 name: "MOVBreg", 17063 argLen: 1, 17064 asm: ppc64.AMOVB, 17065 reg: regInfo{ 17066 inputs: []inputInfo{ 17067 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17068 }, 17069 outputs: []outputInfo{ 17070 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17071 }, 17072 }, 17073 }, 17074 { 17075 name: "MOVBZreg", 17076 argLen: 1, 17077 asm: ppc64.AMOVBZ, 17078 reg: regInfo{ 17079 inputs: []inputInfo{ 17080 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17081 }, 17082 outputs: []outputInfo{ 17083 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17084 }, 17085 }, 17086 }, 17087 { 17088 name: "MOVHreg", 17089 argLen: 1, 17090 asm: ppc64.AMOVH, 17091 reg: regInfo{ 17092 inputs: []inputInfo{ 17093 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17094 }, 17095 outputs: []outputInfo{ 17096 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17097 }, 17098 }, 17099 }, 17100 { 17101 name: "MOVHZreg", 17102 argLen: 1, 17103 asm: ppc64.AMOVHZ, 17104 reg: regInfo{ 17105 inputs: []inputInfo{ 17106 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17107 }, 17108 outputs: []outputInfo{ 17109 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17110 }, 17111 }, 17112 }, 17113 { 17114 name: "MOVWreg", 17115 argLen: 1, 17116 asm: ppc64.AMOVW, 17117 reg: regInfo{ 17118 inputs: []inputInfo{ 17119 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17120 }, 17121 outputs: []outputInfo{ 17122 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17123 }, 17124 }, 17125 }, 17126 { 17127 name: "MOVWZreg", 17128 argLen: 1, 17129 asm: ppc64.AMOVWZ, 17130 reg: regInfo{ 17131 inputs: []inputInfo{ 17132 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17133 }, 17134 outputs: []outputInfo{ 17135 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17136 }, 17137 }, 17138 }, 17139 { 17140 name: "MOVBZload", 17141 auxType: auxSymOff, 17142 argLen: 2, 17143 faultOnNilArg0: true, 17144 symEffect: SymRead, 17145 asm: ppc64.AMOVBZ, 17146 reg: regInfo{ 17147 inputs: []inputInfo{ 17148 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17149 }, 17150 outputs: []outputInfo{ 17151 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17152 }, 17153 }, 17154 }, 17155 { 17156 name: "MOVHload", 17157 auxType: auxSymOff, 17158 argLen: 2, 17159 faultOnNilArg0: true, 17160 symEffect: SymRead, 17161 asm: ppc64.AMOVH, 17162 reg: regInfo{ 17163 inputs: []inputInfo{ 17164 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17165 }, 17166 outputs: []outputInfo{ 17167 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17168 }, 17169 }, 17170 }, 17171 { 17172 name: "MOVHZload", 17173 auxType: auxSymOff, 17174 argLen: 2, 17175 faultOnNilArg0: true, 17176 symEffect: SymRead, 17177 asm: ppc64.AMOVHZ, 17178 reg: regInfo{ 17179 inputs: []inputInfo{ 17180 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17181 }, 17182 outputs: []outputInfo{ 17183 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17184 }, 17185 }, 17186 }, 17187 { 17188 name: "MOVWload", 17189 auxType: auxSymOff, 17190 argLen: 2, 17191 faultOnNilArg0: true, 17192 symEffect: SymRead, 17193 asm: ppc64.AMOVW, 17194 reg: regInfo{ 17195 inputs: []inputInfo{ 17196 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17197 }, 17198 outputs: []outputInfo{ 17199 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17200 }, 17201 }, 17202 }, 17203 { 17204 name: "MOVWZload", 17205 auxType: auxSymOff, 17206 argLen: 2, 17207 faultOnNilArg0: true, 17208 symEffect: SymRead, 17209 asm: ppc64.AMOVWZ, 17210 reg: regInfo{ 17211 inputs: []inputInfo{ 17212 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17213 }, 17214 outputs: []outputInfo{ 17215 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17216 }, 17217 }, 17218 }, 17219 { 17220 name: "MOVDload", 17221 auxType: auxSymOff, 17222 argLen: 2, 17223 faultOnNilArg0: true, 17224 symEffect: SymRead, 17225 asm: ppc64.AMOVD, 17226 reg: regInfo{ 17227 inputs: []inputInfo{ 17228 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17229 }, 17230 outputs: []outputInfo{ 17231 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17232 }, 17233 }, 17234 }, 17235 { 17236 name: "FMOVDload", 17237 auxType: auxSymOff, 17238 argLen: 2, 17239 faultOnNilArg0: true, 17240 symEffect: SymRead, 17241 asm: ppc64.AFMOVD, 17242 reg: regInfo{ 17243 inputs: []inputInfo{ 17244 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17245 }, 17246 outputs: []outputInfo{ 17247 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17248 }, 17249 }, 17250 }, 17251 { 17252 name: "FMOVSload", 17253 auxType: auxSymOff, 17254 argLen: 2, 17255 faultOnNilArg0: true, 17256 symEffect: SymRead, 17257 asm: ppc64.AFMOVS, 17258 reg: regInfo{ 17259 inputs: []inputInfo{ 17260 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17261 }, 17262 outputs: []outputInfo{ 17263 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17264 }, 17265 }, 17266 }, 17267 { 17268 name: "MOVBstore", 17269 auxType: auxSymOff, 17270 argLen: 3, 17271 faultOnNilArg0: true, 17272 symEffect: SymWrite, 17273 asm: ppc64.AMOVB, 17274 reg: regInfo{ 17275 inputs: []inputInfo{ 17276 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17277 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17278 }, 17279 }, 17280 }, 17281 { 17282 name: "MOVHstore", 17283 auxType: auxSymOff, 17284 argLen: 3, 17285 faultOnNilArg0: true, 17286 symEffect: SymWrite, 17287 asm: ppc64.AMOVH, 17288 reg: regInfo{ 17289 inputs: []inputInfo{ 17290 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17291 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17292 }, 17293 }, 17294 }, 17295 { 17296 name: "MOVWstore", 17297 auxType: auxSymOff, 17298 argLen: 3, 17299 faultOnNilArg0: true, 17300 symEffect: SymWrite, 17301 asm: ppc64.AMOVW, 17302 reg: regInfo{ 17303 inputs: []inputInfo{ 17304 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17305 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17306 }, 17307 }, 17308 }, 17309 { 17310 name: "MOVDstore", 17311 auxType: auxSymOff, 17312 argLen: 3, 17313 faultOnNilArg0: true, 17314 symEffect: SymWrite, 17315 asm: ppc64.AMOVD, 17316 reg: regInfo{ 17317 inputs: []inputInfo{ 17318 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17319 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17320 }, 17321 }, 17322 }, 17323 { 17324 name: "FMOVDstore", 17325 auxType: auxSymOff, 17326 argLen: 3, 17327 faultOnNilArg0: true, 17328 symEffect: SymWrite, 17329 asm: ppc64.AFMOVD, 17330 reg: regInfo{ 17331 inputs: []inputInfo{ 17332 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17333 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17334 }, 17335 }, 17336 }, 17337 { 17338 name: "FMOVSstore", 17339 auxType: auxSymOff, 17340 argLen: 3, 17341 faultOnNilArg0: true, 17342 symEffect: SymWrite, 17343 asm: ppc64.AFMOVS, 17344 reg: regInfo{ 17345 inputs: []inputInfo{ 17346 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17347 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17348 }, 17349 }, 17350 }, 17351 { 17352 name: "MOVBstorezero", 17353 auxType: auxSymOff, 17354 argLen: 2, 17355 faultOnNilArg0: true, 17356 symEffect: SymWrite, 17357 asm: ppc64.AMOVB, 17358 reg: regInfo{ 17359 inputs: []inputInfo{ 17360 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17361 }, 17362 }, 17363 }, 17364 { 17365 name: "MOVHstorezero", 17366 auxType: auxSymOff, 17367 argLen: 2, 17368 faultOnNilArg0: true, 17369 symEffect: SymWrite, 17370 asm: ppc64.AMOVH, 17371 reg: regInfo{ 17372 inputs: []inputInfo{ 17373 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17374 }, 17375 }, 17376 }, 17377 { 17378 name: "MOVWstorezero", 17379 auxType: auxSymOff, 17380 argLen: 2, 17381 faultOnNilArg0: true, 17382 symEffect: SymWrite, 17383 asm: ppc64.AMOVW, 17384 reg: regInfo{ 17385 inputs: []inputInfo{ 17386 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17387 }, 17388 }, 17389 }, 17390 { 17391 name: "MOVDstorezero", 17392 auxType: auxSymOff, 17393 argLen: 2, 17394 faultOnNilArg0: true, 17395 symEffect: SymWrite, 17396 asm: ppc64.AMOVD, 17397 reg: regInfo{ 17398 inputs: []inputInfo{ 17399 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17400 }, 17401 }, 17402 }, 17403 { 17404 name: "MOVDaddr", 17405 auxType: auxSymOff, 17406 argLen: 1, 17407 rematerializeable: true, 17408 symEffect: SymAddr, 17409 asm: ppc64.AMOVD, 17410 reg: regInfo{ 17411 inputs: []inputInfo{ 17412 {0, 6}, // SP SB 17413 }, 17414 outputs: []outputInfo{ 17415 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17416 }, 17417 }, 17418 }, 17419 { 17420 name: "MOVDconst", 17421 auxType: auxInt64, 17422 argLen: 0, 17423 rematerializeable: true, 17424 asm: ppc64.AMOVD, 17425 reg: regInfo{ 17426 outputs: []outputInfo{ 17427 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17428 }, 17429 }, 17430 }, 17431 { 17432 name: "FMOVDconst", 17433 auxType: auxFloat64, 17434 argLen: 0, 17435 rematerializeable: true, 17436 asm: ppc64.AFMOVD, 17437 reg: regInfo{ 17438 outputs: []outputInfo{ 17439 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17440 }, 17441 }, 17442 }, 17443 { 17444 name: "FMOVSconst", 17445 auxType: auxFloat32, 17446 argLen: 0, 17447 rematerializeable: true, 17448 asm: ppc64.AFMOVS, 17449 reg: regInfo{ 17450 outputs: []outputInfo{ 17451 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17452 }, 17453 }, 17454 }, 17455 { 17456 name: "FCMPU", 17457 argLen: 2, 17458 asm: ppc64.AFCMPU, 17459 reg: regInfo{ 17460 inputs: []inputInfo{ 17461 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17462 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17463 }, 17464 }, 17465 }, 17466 { 17467 name: "CMP", 17468 argLen: 2, 17469 asm: ppc64.ACMP, 17470 reg: regInfo{ 17471 inputs: []inputInfo{ 17472 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17473 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17474 }, 17475 }, 17476 }, 17477 { 17478 name: "CMPU", 17479 argLen: 2, 17480 asm: ppc64.ACMPU, 17481 reg: regInfo{ 17482 inputs: []inputInfo{ 17483 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17484 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17485 }, 17486 }, 17487 }, 17488 { 17489 name: "CMPW", 17490 argLen: 2, 17491 asm: ppc64.ACMPW, 17492 reg: regInfo{ 17493 inputs: []inputInfo{ 17494 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17495 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17496 }, 17497 }, 17498 }, 17499 { 17500 name: "CMPWU", 17501 argLen: 2, 17502 asm: ppc64.ACMPWU, 17503 reg: regInfo{ 17504 inputs: []inputInfo{ 17505 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17506 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17507 }, 17508 }, 17509 }, 17510 { 17511 name: "CMPconst", 17512 auxType: auxInt64, 17513 argLen: 1, 17514 asm: ppc64.ACMP, 17515 reg: regInfo{ 17516 inputs: []inputInfo{ 17517 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17518 }, 17519 }, 17520 }, 17521 { 17522 name: "CMPUconst", 17523 auxType: auxInt64, 17524 argLen: 1, 17525 asm: ppc64.ACMPU, 17526 reg: regInfo{ 17527 inputs: []inputInfo{ 17528 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17529 }, 17530 }, 17531 }, 17532 { 17533 name: "CMPWconst", 17534 auxType: auxInt32, 17535 argLen: 1, 17536 asm: ppc64.ACMPW, 17537 reg: regInfo{ 17538 inputs: []inputInfo{ 17539 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17540 }, 17541 }, 17542 }, 17543 { 17544 name: "CMPWUconst", 17545 auxType: auxInt32, 17546 argLen: 1, 17547 asm: ppc64.ACMPWU, 17548 reg: regInfo{ 17549 inputs: []inputInfo{ 17550 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17551 }, 17552 }, 17553 }, 17554 { 17555 name: "Equal", 17556 argLen: 1, 17557 reg: regInfo{ 17558 outputs: []outputInfo{ 17559 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17560 }, 17561 }, 17562 }, 17563 { 17564 name: "NotEqual", 17565 argLen: 1, 17566 reg: regInfo{ 17567 outputs: []outputInfo{ 17568 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17569 }, 17570 }, 17571 }, 17572 { 17573 name: "LessThan", 17574 argLen: 1, 17575 reg: regInfo{ 17576 outputs: []outputInfo{ 17577 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17578 }, 17579 }, 17580 }, 17581 { 17582 name: "FLessThan", 17583 argLen: 1, 17584 reg: regInfo{ 17585 outputs: []outputInfo{ 17586 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17587 }, 17588 }, 17589 }, 17590 { 17591 name: "LessEqual", 17592 argLen: 1, 17593 reg: regInfo{ 17594 outputs: []outputInfo{ 17595 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17596 }, 17597 }, 17598 }, 17599 { 17600 name: "FLessEqual", 17601 argLen: 1, 17602 reg: regInfo{ 17603 outputs: []outputInfo{ 17604 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17605 }, 17606 }, 17607 }, 17608 { 17609 name: "GreaterThan", 17610 argLen: 1, 17611 reg: regInfo{ 17612 outputs: []outputInfo{ 17613 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17614 }, 17615 }, 17616 }, 17617 { 17618 name: "FGreaterThan", 17619 argLen: 1, 17620 reg: regInfo{ 17621 outputs: []outputInfo{ 17622 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17623 }, 17624 }, 17625 }, 17626 { 17627 name: "GreaterEqual", 17628 argLen: 1, 17629 reg: regInfo{ 17630 outputs: []outputInfo{ 17631 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17632 }, 17633 }, 17634 }, 17635 { 17636 name: "FGreaterEqual", 17637 argLen: 1, 17638 reg: regInfo{ 17639 outputs: []outputInfo{ 17640 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17641 }, 17642 }, 17643 }, 17644 { 17645 name: "LoweredGetClosurePtr", 17646 argLen: 0, 17647 reg: regInfo{ 17648 outputs: []outputInfo{ 17649 {0, 2048}, // R11 17650 }, 17651 }, 17652 }, 17653 { 17654 name: "LoweredNilCheck", 17655 argLen: 2, 17656 clobberFlags: true, 17657 nilCheck: true, 17658 faultOnNilArg0: true, 17659 reg: regInfo{ 17660 inputs: []inputInfo{ 17661 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17662 }, 17663 clobbers: 2147483648, // R31 17664 }, 17665 }, 17666 { 17667 name: "LoweredRound32F", 17668 argLen: 1, 17669 resultInArg0: true, 17670 reg: regInfo{ 17671 inputs: []inputInfo{ 17672 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17673 }, 17674 outputs: []outputInfo{ 17675 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17676 }, 17677 }, 17678 }, 17679 { 17680 name: "LoweredRound64F", 17681 argLen: 1, 17682 resultInArg0: true, 17683 reg: regInfo{ 17684 inputs: []inputInfo{ 17685 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17686 }, 17687 outputs: []outputInfo{ 17688 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17689 }, 17690 }, 17691 }, 17692 { 17693 name: "MOVDconvert", 17694 argLen: 2, 17695 asm: ppc64.AMOVD, 17696 reg: regInfo{ 17697 inputs: []inputInfo{ 17698 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17699 }, 17700 outputs: []outputInfo{ 17701 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17702 }, 17703 }, 17704 }, 17705 { 17706 name: "CALLstatic", 17707 auxType: auxSymOff, 17708 argLen: 1, 17709 clobberFlags: true, 17710 call: true, 17711 symEffect: SymNone, 17712 reg: regInfo{ 17713 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17714 }, 17715 }, 17716 { 17717 name: "CALLclosure", 17718 auxType: auxInt64, 17719 argLen: 3, 17720 clobberFlags: true, 17721 call: true, 17722 reg: regInfo{ 17723 inputs: []inputInfo{ 17724 {1, 2048}, // R11 17725 {0, 1073733626}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17726 }, 17727 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17728 }, 17729 }, 17730 { 17731 name: "CALLinter", 17732 auxType: auxInt64, 17733 argLen: 2, 17734 clobberFlags: true, 17735 call: true, 17736 reg: regInfo{ 17737 inputs: []inputInfo{ 17738 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17739 }, 17740 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17741 }, 17742 }, 17743 { 17744 name: "LoweredZero", 17745 auxType: auxInt64, 17746 argLen: 2, 17747 clobberFlags: true, 17748 faultOnNilArg0: true, 17749 reg: regInfo{ 17750 inputs: []inputInfo{ 17751 {0, 8}, // R3 17752 }, 17753 clobbers: 8, // R3 17754 }, 17755 }, 17756 { 17757 name: "LoweredMove", 17758 auxType: auxInt64, 17759 argLen: 3, 17760 clobberFlags: true, 17761 faultOnNilArg0: true, 17762 faultOnNilArg1: true, 17763 reg: regInfo{ 17764 inputs: []inputInfo{ 17765 {0, 8}, // R3 17766 {1, 16}, // R4 17767 }, 17768 clobbers: 1944, // R3 R4 R7 R8 R9 R10 17769 }, 17770 }, 17771 { 17772 name: "LoweredAtomicStore32", 17773 argLen: 3, 17774 faultOnNilArg0: true, 17775 hasSideEffects: true, 17776 reg: regInfo{ 17777 inputs: []inputInfo{ 17778 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17779 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17780 }, 17781 }, 17782 }, 17783 { 17784 name: "LoweredAtomicStore64", 17785 argLen: 3, 17786 faultOnNilArg0: true, 17787 hasSideEffects: true, 17788 reg: regInfo{ 17789 inputs: []inputInfo{ 17790 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17791 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17792 }, 17793 }, 17794 }, 17795 { 17796 name: "LoweredAtomicLoad32", 17797 argLen: 2, 17798 clobberFlags: true, 17799 faultOnNilArg0: true, 17800 reg: regInfo{ 17801 inputs: []inputInfo{ 17802 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17803 }, 17804 outputs: []outputInfo{ 17805 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17806 }, 17807 }, 17808 }, 17809 { 17810 name: "LoweredAtomicLoad64", 17811 argLen: 2, 17812 clobberFlags: true, 17813 faultOnNilArg0: true, 17814 reg: regInfo{ 17815 inputs: []inputInfo{ 17816 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17817 }, 17818 outputs: []outputInfo{ 17819 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17820 }, 17821 }, 17822 }, 17823 { 17824 name: "LoweredAtomicLoadPtr", 17825 argLen: 2, 17826 clobberFlags: true, 17827 faultOnNilArg0: true, 17828 reg: regInfo{ 17829 inputs: []inputInfo{ 17830 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17831 }, 17832 outputs: []outputInfo{ 17833 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17834 }, 17835 }, 17836 }, 17837 { 17838 name: "LoweredAtomicAdd32", 17839 argLen: 3, 17840 resultNotInArgs: true, 17841 clobberFlags: true, 17842 faultOnNilArg0: true, 17843 hasSideEffects: true, 17844 reg: regInfo{ 17845 inputs: []inputInfo{ 17846 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17847 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17848 }, 17849 outputs: []outputInfo{ 17850 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17851 }, 17852 }, 17853 }, 17854 { 17855 name: "LoweredAtomicAdd64", 17856 argLen: 3, 17857 resultNotInArgs: true, 17858 clobberFlags: true, 17859 faultOnNilArg0: true, 17860 hasSideEffects: true, 17861 reg: regInfo{ 17862 inputs: []inputInfo{ 17863 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17864 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17865 }, 17866 outputs: []outputInfo{ 17867 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17868 }, 17869 }, 17870 }, 17871 { 17872 name: "LoweredAtomicExchange32", 17873 argLen: 3, 17874 resultNotInArgs: true, 17875 clobberFlags: true, 17876 faultOnNilArg0: true, 17877 hasSideEffects: true, 17878 reg: regInfo{ 17879 inputs: []inputInfo{ 17880 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17881 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17882 }, 17883 outputs: []outputInfo{ 17884 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17885 }, 17886 }, 17887 }, 17888 { 17889 name: "LoweredAtomicExchange64", 17890 argLen: 3, 17891 resultNotInArgs: true, 17892 clobberFlags: true, 17893 faultOnNilArg0: true, 17894 hasSideEffects: true, 17895 reg: regInfo{ 17896 inputs: []inputInfo{ 17897 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17898 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17899 }, 17900 outputs: []outputInfo{ 17901 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17902 }, 17903 }, 17904 }, 17905 { 17906 name: "LoweredAtomicCas64", 17907 argLen: 4, 17908 resultNotInArgs: true, 17909 clobberFlags: true, 17910 faultOnNilArg0: true, 17911 hasSideEffects: true, 17912 reg: regInfo{ 17913 inputs: []inputInfo{ 17914 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17915 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17916 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17917 }, 17918 outputs: []outputInfo{ 17919 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17920 }, 17921 }, 17922 }, 17923 { 17924 name: "LoweredAtomicCas32", 17925 argLen: 4, 17926 resultNotInArgs: true, 17927 clobberFlags: true, 17928 faultOnNilArg0: true, 17929 hasSideEffects: true, 17930 reg: regInfo{ 17931 inputs: []inputInfo{ 17932 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17933 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17934 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17935 }, 17936 outputs: []outputInfo{ 17937 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17938 }, 17939 }, 17940 }, 17941 { 17942 name: "LoweredAtomicAnd8", 17943 argLen: 3, 17944 faultOnNilArg0: true, 17945 hasSideEffects: true, 17946 asm: ppc64.AAND, 17947 reg: regInfo{ 17948 inputs: []inputInfo{ 17949 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17950 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17951 }, 17952 }, 17953 }, 17954 { 17955 name: "LoweredAtomicOr8", 17956 argLen: 3, 17957 faultOnNilArg0: true, 17958 hasSideEffects: true, 17959 asm: ppc64.AOR, 17960 reg: regInfo{ 17961 inputs: []inputInfo{ 17962 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17963 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17964 }, 17965 }, 17966 }, 17967 { 17968 name: "InvertFlags", 17969 argLen: 1, 17970 reg: regInfo{}, 17971 }, 17972 { 17973 name: "FlagEQ", 17974 argLen: 0, 17975 reg: regInfo{}, 17976 }, 17977 { 17978 name: "FlagLT", 17979 argLen: 0, 17980 reg: regInfo{}, 17981 }, 17982 { 17983 name: "FlagGT", 17984 argLen: 0, 17985 reg: regInfo{}, 17986 }, 17987 17988 { 17989 name: "FADDS", 17990 argLen: 2, 17991 commutative: true, 17992 resultInArg0: true, 17993 clobberFlags: true, 17994 asm: s390x.AFADDS, 17995 reg: regInfo{ 17996 inputs: []inputInfo{ 17997 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17998 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17999 }, 18000 outputs: []outputInfo{ 18001 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18002 }, 18003 }, 18004 }, 18005 { 18006 name: "FADD", 18007 argLen: 2, 18008 commutative: true, 18009 resultInArg0: true, 18010 clobberFlags: true, 18011 asm: s390x.AFADD, 18012 reg: regInfo{ 18013 inputs: []inputInfo{ 18014 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18015 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18016 }, 18017 outputs: []outputInfo{ 18018 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18019 }, 18020 }, 18021 }, 18022 { 18023 name: "FSUBS", 18024 argLen: 2, 18025 resultInArg0: true, 18026 clobberFlags: true, 18027 asm: s390x.AFSUBS, 18028 reg: regInfo{ 18029 inputs: []inputInfo{ 18030 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18031 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18032 }, 18033 outputs: []outputInfo{ 18034 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18035 }, 18036 }, 18037 }, 18038 { 18039 name: "FSUB", 18040 argLen: 2, 18041 resultInArg0: true, 18042 clobberFlags: true, 18043 asm: s390x.AFSUB, 18044 reg: regInfo{ 18045 inputs: []inputInfo{ 18046 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18047 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18048 }, 18049 outputs: []outputInfo{ 18050 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18051 }, 18052 }, 18053 }, 18054 { 18055 name: "FMULS", 18056 argLen: 2, 18057 commutative: true, 18058 resultInArg0: true, 18059 asm: s390x.AFMULS, 18060 reg: regInfo{ 18061 inputs: []inputInfo{ 18062 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18063 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18064 }, 18065 outputs: []outputInfo{ 18066 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18067 }, 18068 }, 18069 }, 18070 { 18071 name: "FMUL", 18072 argLen: 2, 18073 commutative: true, 18074 resultInArg0: true, 18075 asm: s390x.AFMUL, 18076 reg: regInfo{ 18077 inputs: []inputInfo{ 18078 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18079 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18080 }, 18081 outputs: []outputInfo{ 18082 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18083 }, 18084 }, 18085 }, 18086 { 18087 name: "FDIVS", 18088 argLen: 2, 18089 resultInArg0: true, 18090 asm: s390x.AFDIVS, 18091 reg: regInfo{ 18092 inputs: []inputInfo{ 18093 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18094 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18095 }, 18096 outputs: []outputInfo{ 18097 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18098 }, 18099 }, 18100 }, 18101 { 18102 name: "FDIV", 18103 argLen: 2, 18104 resultInArg0: true, 18105 asm: s390x.AFDIV, 18106 reg: regInfo{ 18107 inputs: []inputInfo{ 18108 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18109 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18110 }, 18111 outputs: []outputInfo{ 18112 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18113 }, 18114 }, 18115 }, 18116 { 18117 name: "FNEGS", 18118 argLen: 1, 18119 clobberFlags: true, 18120 asm: s390x.AFNEGS, 18121 reg: regInfo{ 18122 inputs: []inputInfo{ 18123 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18124 }, 18125 outputs: []outputInfo{ 18126 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18127 }, 18128 }, 18129 }, 18130 { 18131 name: "FNEG", 18132 argLen: 1, 18133 clobberFlags: true, 18134 asm: s390x.AFNEG, 18135 reg: regInfo{ 18136 inputs: []inputInfo{ 18137 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18138 }, 18139 outputs: []outputInfo{ 18140 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18141 }, 18142 }, 18143 }, 18144 { 18145 name: "FMADDS", 18146 argLen: 3, 18147 resultInArg0: true, 18148 asm: s390x.AFMADDS, 18149 reg: regInfo{ 18150 inputs: []inputInfo{ 18151 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18152 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18153 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18154 }, 18155 outputs: []outputInfo{ 18156 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18157 }, 18158 }, 18159 }, 18160 { 18161 name: "FMADD", 18162 argLen: 3, 18163 resultInArg0: true, 18164 asm: s390x.AFMADD, 18165 reg: regInfo{ 18166 inputs: []inputInfo{ 18167 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18168 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18169 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18170 }, 18171 outputs: []outputInfo{ 18172 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18173 }, 18174 }, 18175 }, 18176 { 18177 name: "FMSUBS", 18178 argLen: 3, 18179 resultInArg0: true, 18180 asm: s390x.AFMSUBS, 18181 reg: regInfo{ 18182 inputs: []inputInfo{ 18183 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18184 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18185 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18186 }, 18187 outputs: []outputInfo{ 18188 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18189 }, 18190 }, 18191 }, 18192 { 18193 name: "FMSUB", 18194 argLen: 3, 18195 resultInArg0: true, 18196 asm: s390x.AFMSUB, 18197 reg: regInfo{ 18198 inputs: []inputInfo{ 18199 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18200 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18201 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18202 }, 18203 outputs: []outputInfo{ 18204 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18205 }, 18206 }, 18207 }, 18208 { 18209 name: "FMOVSload", 18210 auxType: auxSymOff, 18211 argLen: 2, 18212 faultOnNilArg0: true, 18213 symEffect: SymRead, 18214 asm: s390x.AFMOVS, 18215 reg: regInfo{ 18216 inputs: []inputInfo{ 18217 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18218 }, 18219 outputs: []outputInfo{ 18220 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18221 }, 18222 }, 18223 }, 18224 { 18225 name: "FMOVDload", 18226 auxType: auxSymOff, 18227 argLen: 2, 18228 faultOnNilArg0: true, 18229 symEffect: SymRead, 18230 asm: s390x.AFMOVD, 18231 reg: regInfo{ 18232 inputs: []inputInfo{ 18233 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18234 }, 18235 outputs: []outputInfo{ 18236 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18237 }, 18238 }, 18239 }, 18240 { 18241 name: "FMOVSconst", 18242 auxType: auxFloat32, 18243 argLen: 0, 18244 rematerializeable: true, 18245 asm: s390x.AFMOVS, 18246 reg: regInfo{ 18247 outputs: []outputInfo{ 18248 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18249 }, 18250 }, 18251 }, 18252 { 18253 name: "FMOVDconst", 18254 auxType: auxFloat64, 18255 argLen: 0, 18256 rematerializeable: true, 18257 asm: s390x.AFMOVD, 18258 reg: regInfo{ 18259 outputs: []outputInfo{ 18260 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18261 }, 18262 }, 18263 }, 18264 { 18265 name: "FMOVSloadidx", 18266 auxType: auxSymOff, 18267 argLen: 3, 18268 symEffect: SymRead, 18269 asm: s390x.AFMOVS, 18270 reg: regInfo{ 18271 inputs: []inputInfo{ 18272 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18273 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18274 }, 18275 outputs: []outputInfo{ 18276 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18277 }, 18278 }, 18279 }, 18280 { 18281 name: "FMOVDloadidx", 18282 auxType: auxSymOff, 18283 argLen: 3, 18284 symEffect: SymRead, 18285 asm: s390x.AFMOVD, 18286 reg: regInfo{ 18287 inputs: []inputInfo{ 18288 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18289 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18290 }, 18291 outputs: []outputInfo{ 18292 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18293 }, 18294 }, 18295 }, 18296 { 18297 name: "FMOVSstore", 18298 auxType: auxSymOff, 18299 argLen: 3, 18300 faultOnNilArg0: true, 18301 symEffect: SymWrite, 18302 asm: s390x.AFMOVS, 18303 reg: regInfo{ 18304 inputs: []inputInfo{ 18305 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18306 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18307 }, 18308 }, 18309 }, 18310 { 18311 name: "FMOVDstore", 18312 auxType: auxSymOff, 18313 argLen: 3, 18314 faultOnNilArg0: true, 18315 symEffect: SymWrite, 18316 asm: s390x.AFMOVD, 18317 reg: regInfo{ 18318 inputs: []inputInfo{ 18319 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18320 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18321 }, 18322 }, 18323 }, 18324 { 18325 name: "FMOVSstoreidx", 18326 auxType: auxSymOff, 18327 argLen: 4, 18328 symEffect: SymWrite, 18329 asm: s390x.AFMOVS, 18330 reg: regInfo{ 18331 inputs: []inputInfo{ 18332 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18333 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18334 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18335 }, 18336 }, 18337 }, 18338 { 18339 name: "FMOVDstoreidx", 18340 auxType: auxSymOff, 18341 argLen: 4, 18342 symEffect: SymWrite, 18343 asm: s390x.AFMOVD, 18344 reg: regInfo{ 18345 inputs: []inputInfo{ 18346 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18347 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18348 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18349 }, 18350 }, 18351 }, 18352 { 18353 name: "ADD", 18354 argLen: 2, 18355 commutative: true, 18356 clobberFlags: true, 18357 asm: s390x.AADD, 18358 reg: regInfo{ 18359 inputs: []inputInfo{ 18360 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18361 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18362 }, 18363 outputs: []outputInfo{ 18364 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18365 }, 18366 }, 18367 }, 18368 { 18369 name: "ADDW", 18370 argLen: 2, 18371 commutative: true, 18372 clobberFlags: true, 18373 asm: s390x.AADDW, 18374 reg: regInfo{ 18375 inputs: []inputInfo{ 18376 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18377 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18378 }, 18379 outputs: []outputInfo{ 18380 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18381 }, 18382 }, 18383 }, 18384 { 18385 name: "ADDconst", 18386 auxType: auxInt64, 18387 argLen: 1, 18388 clobberFlags: true, 18389 asm: s390x.AADD, 18390 reg: regInfo{ 18391 inputs: []inputInfo{ 18392 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18393 }, 18394 outputs: []outputInfo{ 18395 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18396 }, 18397 }, 18398 }, 18399 { 18400 name: "ADDWconst", 18401 auxType: auxInt32, 18402 argLen: 1, 18403 clobberFlags: true, 18404 asm: s390x.AADDW, 18405 reg: regInfo{ 18406 inputs: []inputInfo{ 18407 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18408 }, 18409 outputs: []outputInfo{ 18410 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18411 }, 18412 }, 18413 }, 18414 { 18415 name: "ADDload", 18416 auxType: auxSymOff, 18417 argLen: 3, 18418 resultInArg0: true, 18419 clobberFlags: true, 18420 faultOnNilArg1: true, 18421 symEffect: SymRead, 18422 asm: s390x.AADD, 18423 reg: regInfo{ 18424 inputs: []inputInfo{ 18425 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18426 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18427 }, 18428 outputs: []outputInfo{ 18429 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18430 }, 18431 }, 18432 }, 18433 { 18434 name: "ADDWload", 18435 auxType: auxSymOff, 18436 argLen: 3, 18437 resultInArg0: true, 18438 clobberFlags: true, 18439 faultOnNilArg1: true, 18440 symEffect: SymRead, 18441 asm: s390x.AADDW, 18442 reg: regInfo{ 18443 inputs: []inputInfo{ 18444 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18445 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18446 }, 18447 outputs: []outputInfo{ 18448 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18449 }, 18450 }, 18451 }, 18452 { 18453 name: "SUB", 18454 argLen: 2, 18455 clobberFlags: true, 18456 asm: s390x.ASUB, 18457 reg: regInfo{ 18458 inputs: []inputInfo{ 18459 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18460 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18461 }, 18462 outputs: []outputInfo{ 18463 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18464 }, 18465 }, 18466 }, 18467 { 18468 name: "SUBW", 18469 argLen: 2, 18470 clobberFlags: true, 18471 asm: s390x.ASUBW, 18472 reg: regInfo{ 18473 inputs: []inputInfo{ 18474 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18475 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18476 }, 18477 outputs: []outputInfo{ 18478 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18479 }, 18480 }, 18481 }, 18482 { 18483 name: "SUBconst", 18484 auxType: auxInt64, 18485 argLen: 1, 18486 resultInArg0: true, 18487 clobberFlags: true, 18488 asm: s390x.ASUB, 18489 reg: regInfo{ 18490 inputs: []inputInfo{ 18491 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18492 }, 18493 outputs: []outputInfo{ 18494 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18495 }, 18496 }, 18497 }, 18498 { 18499 name: "SUBWconst", 18500 auxType: auxInt32, 18501 argLen: 1, 18502 resultInArg0: true, 18503 clobberFlags: true, 18504 asm: s390x.ASUBW, 18505 reg: regInfo{ 18506 inputs: []inputInfo{ 18507 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18508 }, 18509 outputs: []outputInfo{ 18510 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18511 }, 18512 }, 18513 }, 18514 { 18515 name: "SUBload", 18516 auxType: auxSymOff, 18517 argLen: 3, 18518 resultInArg0: true, 18519 clobberFlags: true, 18520 faultOnNilArg1: true, 18521 symEffect: SymRead, 18522 asm: s390x.ASUB, 18523 reg: regInfo{ 18524 inputs: []inputInfo{ 18525 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18526 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18527 }, 18528 outputs: []outputInfo{ 18529 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18530 }, 18531 }, 18532 }, 18533 { 18534 name: "SUBWload", 18535 auxType: auxSymOff, 18536 argLen: 3, 18537 resultInArg0: true, 18538 clobberFlags: true, 18539 faultOnNilArg1: true, 18540 symEffect: SymRead, 18541 asm: s390x.ASUBW, 18542 reg: regInfo{ 18543 inputs: []inputInfo{ 18544 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18545 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18546 }, 18547 outputs: []outputInfo{ 18548 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18549 }, 18550 }, 18551 }, 18552 { 18553 name: "MULLD", 18554 argLen: 2, 18555 commutative: true, 18556 resultInArg0: true, 18557 clobberFlags: true, 18558 asm: s390x.AMULLD, 18559 reg: regInfo{ 18560 inputs: []inputInfo{ 18561 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18562 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18563 }, 18564 outputs: []outputInfo{ 18565 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18566 }, 18567 }, 18568 }, 18569 { 18570 name: "MULLW", 18571 argLen: 2, 18572 commutative: true, 18573 resultInArg0: true, 18574 clobberFlags: true, 18575 asm: s390x.AMULLW, 18576 reg: regInfo{ 18577 inputs: []inputInfo{ 18578 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18579 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18580 }, 18581 outputs: []outputInfo{ 18582 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18583 }, 18584 }, 18585 }, 18586 { 18587 name: "MULLDconst", 18588 auxType: auxInt64, 18589 argLen: 1, 18590 resultInArg0: true, 18591 clobberFlags: true, 18592 asm: s390x.AMULLD, 18593 reg: regInfo{ 18594 inputs: []inputInfo{ 18595 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18596 }, 18597 outputs: []outputInfo{ 18598 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18599 }, 18600 }, 18601 }, 18602 { 18603 name: "MULLWconst", 18604 auxType: auxInt32, 18605 argLen: 1, 18606 resultInArg0: true, 18607 clobberFlags: true, 18608 asm: s390x.AMULLW, 18609 reg: regInfo{ 18610 inputs: []inputInfo{ 18611 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18612 }, 18613 outputs: []outputInfo{ 18614 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18615 }, 18616 }, 18617 }, 18618 { 18619 name: "MULLDload", 18620 auxType: auxSymOff, 18621 argLen: 3, 18622 resultInArg0: true, 18623 clobberFlags: true, 18624 faultOnNilArg1: true, 18625 symEffect: SymRead, 18626 asm: s390x.AMULLD, 18627 reg: regInfo{ 18628 inputs: []inputInfo{ 18629 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18630 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18631 }, 18632 outputs: []outputInfo{ 18633 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18634 }, 18635 }, 18636 }, 18637 { 18638 name: "MULLWload", 18639 auxType: auxSymOff, 18640 argLen: 3, 18641 resultInArg0: true, 18642 clobberFlags: true, 18643 faultOnNilArg1: true, 18644 symEffect: SymRead, 18645 asm: s390x.AMULLW, 18646 reg: regInfo{ 18647 inputs: []inputInfo{ 18648 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18649 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18650 }, 18651 outputs: []outputInfo{ 18652 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18653 }, 18654 }, 18655 }, 18656 { 18657 name: "MULHD", 18658 argLen: 2, 18659 commutative: true, 18660 resultInArg0: true, 18661 clobberFlags: true, 18662 asm: s390x.AMULHD, 18663 reg: regInfo{ 18664 inputs: []inputInfo{ 18665 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18666 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18667 }, 18668 outputs: []outputInfo{ 18669 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18670 }, 18671 }, 18672 }, 18673 { 18674 name: "MULHDU", 18675 argLen: 2, 18676 commutative: true, 18677 resultInArg0: true, 18678 clobberFlags: true, 18679 asm: s390x.AMULHDU, 18680 reg: regInfo{ 18681 inputs: []inputInfo{ 18682 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18683 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18684 }, 18685 outputs: []outputInfo{ 18686 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18687 }, 18688 }, 18689 }, 18690 { 18691 name: "DIVD", 18692 argLen: 2, 18693 resultInArg0: true, 18694 clobberFlags: true, 18695 asm: s390x.ADIVD, 18696 reg: regInfo{ 18697 inputs: []inputInfo{ 18698 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18699 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18700 }, 18701 outputs: []outputInfo{ 18702 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18703 }, 18704 }, 18705 }, 18706 { 18707 name: "DIVW", 18708 argLen: 2, 18709 resultInArg0: true, 18710 clobberFlags: true, 18711 asm: s390x.ADIVW, 18712 reg: regInfo{ 18713 inputs: []inputInfo{ 18714 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18715 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18716 }, 18717 outputs: []outputInfo{ 18718 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18719 }, 18720 }, 18721 }, 18722 { 18723 name: "DIVDU", 18724 argLen: 2, 18725 resultInArg0: true, 18726 clobberFlags: true, 18727 asm: s390x.ADIVDU, 18728 reg: regInfo{ 18729 inputs: []inputInfo{ 18730 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18731 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18732 }, 18733 outputs: []outputInfo{ 18734 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18735 }, 18736 }, 18737 }, 18738 { 18739 name: "DIVWU", 18740 argLen: 2, 18741 resultInArg0: true, 18742 clobberFlags: true, 18743 asm: s390x.ADIVWU, 18744 reg: regInfo{ 18745 inputs: []inputInfo{ 18746 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18747 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18748 }, 18749 outputs: []outputInfo{ 18750 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18751 }, 18752 }, 18753 }, 18754 { 18755 name: "MODD", 18756 argLen: 2, 18757 resultInArg0: true, 18758 clobberFlags: true, 18759 asm: s390x.AMODD, 18760 reg: regInfo{ 18761 inputs: []inputInfo{ 18762 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18763 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18764 }, 18765 outputs: []outputInfo{ 18766 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18767 }, 18768 }, 18769 }, 18770 { 18771 name: "MODW", 18772 argLen: 2, 18773 resultInArg0: true, 18774 clobberFlags: true, 18775 asm: s390x.AMODW, 18776 reg: regInfo{ 18777 inputs: []inputInfo{ 18778 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18779 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18780 }, 18781 outputs: []outputInfo{ 18782 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18783 }, 18784 }, 18785 }, 18786 { 18787 name: "MODDU", 18788 argLen: 2, 18789 resultInArg0: true, 18790 clobberFlags: true, 18791 asm: s390x.AMODDU, 18792 reg: regInfo{ 18793 inputs: []inputInfo{ 18794 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18795 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18796 }, 18797 outputs: []outputInfo{ 18798 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18799 }, 18800 }, 18801 }, 18802 { 18803 name: "MODWU", 18804 argLen: 2, 18805 resultInArg0: true, 18806 clobberFlags: true, 18807 asm: s390x.AMODWU, 18808 reg: regInfo{ 18809 inputs: []inputInfo{ 18810 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18811 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18812 }, 18813 outputs: []outputInfo{ 18814 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18815 }, 18816 }, 18817 }, 18818 { 18819 name: "AND", 18820 argLen: 2, 18821 commutative: true, 18822 clobberFlags: true, 18823 asm: s390x.AAND, 18824 reg: regInfo{ 18825 inputs: []inputInfo{ 18826 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18827 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18828 }, 18829 outputs: []outputInfo{ 18830 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18831 }, 18832 }, 18833 }, 18834 { 18835 name: "ANDW", 18836 argLen: 2, 18837 commutative: true, 18838 clobberFlags: true, 18839 asm: s390x.AANDW, 18840 reg: regInfo{ 18841 inputs: []inputInfo{ 18842 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18843 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18844 }, 18845 outputs: []outputInfo{ 18846 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18847 }, 18848 }, 18849 }, 18850 { 18851 name: "ANDconst", 18852 auxType: auxInt64, 18853 argLen: 1, 18854 resultInArg0: true, 18855 clobberFlags: true, 18856 asm: s390x.AAND, 18857 reg: regInfo{ 18858 inputs: []inputInfo{ 18859 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18860 }, 18861 outputs: []outputInfo{ 18862 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18863 }, 18864 }, 18865 }, 18866 { 18867 name: "ANDWconst", 18868 auxType: auxInt32, 18869 argLen: 1, 18870 resultInArg0: true, 18871 clobberFlags: true, 18872 asm: s390x.AANDW, 18873 reg: regInfo{ 18874 inputs: []inputInfo{ 18875 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18876 }, 18877 outputs: []outputInfo{ 18878 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18879 }, 18880 }, 18881 }, 18882 { 18883 name: "ANDload", 18884 auxType: auxSymOff, 18885 argLen: 3, 18886 resultInArg0: true, 18887 clobberFlags: true, 18888 faultOnNilArg1: true, 18889 symEffect: SymRead, 18890 asm: s390x.AAND, 18891 reg: regInfo{ 18892 inputs: []inputInfo{ 18893 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18894 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18895 }, 18896 outputs: []outputInfo{ 18897 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18898 }, 18899 }, 18900 }, 18901 { 18902 name: "ANDWload", 18903 auxType: auxSymOff, 18904 argLen: 3, 18905 resultInArg0: true, 18906 clobberFlags: true, 18907 faultOnNilArg1: true, 18908 symEffect: SymRead, 18909 asm: s390x.AANDW, 18910 reg: regInfo{ 18911 inputs: []inputInfo{ 18912 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18913 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18914 }, 18915 outputs: []outputInfo{ 18916 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18917 }, 18918 }, 18919 }, 18920 { 18921 name: "OR", 18922 argLen: 2, 18923 commutative: true, 18924 clobberFlags: true, 18925 asm: s390x.AOR, 18926 reg: regInfo{ 18927 inputs: []inputInfo{ 18928 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18929 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18930 }, 18931 outputs: []outputInfo{ 18932 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18933 }, 18934 }, 18935 }, 18936 { 18937 name: "ORW", 18938 argLen: 2, 18939 commutative: true, 18940 clobberFlags: true, 18941 asm: s390x.AORW, 18942 reg: regInfo{ 18943 inputs: []inputInfo{ 18944 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18945 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18946 }, 18947 outputs: []outputInfo{ 18948 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18949 }, 18950 }, 18951 }, 18952 { 18953 name: "ORconst", 18954 auxType: auxInt64, 18955 argLen: 1, 18956 resultInArg0: true, 18957 clobberFlags: true, 18958 asm: s390x.AOR, 18959 reg: regInfo{ 18960 inputs: []inputInfo{ 18961 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18962 }, 18963 outputs: []outputInfo{ 18964 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18965 }, 18966 }, 18967 }, 18968 { 18969 name: "ORWconst", 18970 auxType: auxInt32, 18971 argLen: 1, 18972 resultInArg0: true, 18973 clobberFlags: true, 18974 asm: s390x.AORW, 18975 reg: regInfo{ 18976 inputs: []inputInfo{ 18977 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18978 }, 18979 outputs: []outputInfo{ 18980 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18981 }, 18982 }, 18983 }, 18984 { 18985 name: "ORload", 18986 auxType: auxSymOff, 18987 argLen: 3, 18988 resultInArg0: true, 18989 clobberFlags: true, 18990 faultOnNilArg1: true, 18991 symEffect: SymRead, 18992 asm: s390x.AOR, 18993 reg: regInfo{ 18994 inputs: []inputInfo{ 18995 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18996 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18997 }, 18998 outputs: []outputInfo{ 18999 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19000 }, 19001 }, 19002 }, 19003 { 19004 name: "ORWload", 19005 auxType: auxSymOff, 19006 argLen: 3, 19007 resultInArg0: true, 19008 clobberFlags: true, 19009 faultOnNilArg1: true, 19010 symEffect: SymRead, 19011 asm: s390x.AORW, 19012 reg: regInfo{ 19013 inputs: []inputInfo{ 19014 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19015 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19016 }, 19017 outputs: []outputInfo{ 19018 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19019 }, 19020 }, 19021 }, 19022 { 19023 name: "XOR", 19024 argLen: 2, 19025 commutative: true, 19026 clobberFlags: true, 19027 asm: s390x.AXOR, 19028 reg: regInfo{ 19029 inputs: []inputInfo{ 19030 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19031 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19032 }, 19033 outputs: []outputInfo{ 19034 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19035 }, 19036 }, 19037 }, 19038 { 19039 name: "XORW", 19040 argLen: 2, 19041 commutative: true, 19042 clobberFlags: true, 19043 asm: s390x.AXORW, 19044 reg: regInfo{ 19045 inputs: []inputInfo{ 19046 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19047 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19048 }, 19049 outputs: []outputInfo{ 19050 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19051 }, 19052 }, 19053 }, 19054 { 19055 name: "XORconst", 19056 auxType: auxInt64, 19057 argLen: 1, 19058 resultInArg0: true, 19059 clobberFlags: true, 19060 asm: s390x.AXOR, 19061 reg: regInfo{ 19062 inputs: []inputInfo{ 19063 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19064 }, 19065 outputs: []outputInfo{ 19066 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19067 }, 19068 }, 19069 }, 19070 { 19071 name: "XORWconst", 19072 auxType: auxInt32, 19073 argLen: 1, 19074 resultInArg0: true, 19075 clobberFlags: true, 19076 asm: s390x.AXORW, 19077 reg: regInfo{ 19078 inputs: []inputInfo{ 19079 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19080 }, 19081 outputs: []outputInfo{ 19082 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19083 }, 19084 }, 19085 }, 19086 { 19087 name: "XORload", 19088 auxType: auxSymOff, 19089 argLen: 3, 19090 resultInArg0: true, 19091 clobberFlags: true, 19092 faultOnNilArg1: true, 19093 symEffect: SymRead, 19094 asm: s390x.AXOR, 19095 reg: regInfo{ 19096 inputs: []inputInfo{ 19097 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19098 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19099 }, 19100 outputs: []outputInfo{ 19101 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19102 }, 19103 }, 19104 }, 19105 { 19106 name: "XORWload", 19107 auxType: auxSymOff, 19108 argLen: 3, 19109 resultInArg0: true, 19110 clobberFlags: true, 19111 faultOnNilArg1: true, 19112 symEffect: SymRead, 19113 asm: s390x.AXORW, 19114 reg: regInfo{ 19115 inputs: []inputInfo{ 19116 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19117 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19118 }, 19119 outputs: []outputInfo{ 19120 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19121 }, 19122 }, 19123 }, 19124 { 19125 name: "CMP", 19126 argLen: 2, 19127 asm: s390x.ACMP, 19128 reg: regInfo{ 19129 inputs: []inputInfo{ 19130 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19131 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19132 }, 19133 }, 19134 }, 19135 { 19136 name: "CMPW", 19137 argLen: 2, 19138 asm: s390x.ACMPW, 19139 reg: regInfo{ 19140 inputs: []inputInfo{ 19141 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19142 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19143 }, 19144 }, 19145 }, 19146 { 19147 name: "CMPU", 19148 argLen: 2, 19149 asm: s390x.ACMPU, 19150 reg: regInfo{ 19151 inputs: []inputInfo{ 19152 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19153 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19154 }, 19155 }, 19156 }, 19157 { 19158 name: "CMPWU", 19159 argLen: 2, 19160 asm: s390x.ACMPWU, 19161 reg: regInfo{ 19162 inputs: []inputInfo{ 19163 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19164 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19165 }, 19166 }, 19167 }, 19168 { 19169 name: "CMPconst", 19170 auxType: auxInt64, 19171 argLen: 1, 19172 asm: s390x.ACMP, 19173 reg: regInfo{ 19174 inputs: []inputInfo{ 19175 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19176 }, 19177 }, 19178 }, 19179 { 19180 name: "CMPWconst", 19181 auxType: auxInt32, 19182 argLen: 1, 19183 asm: s390x.ACMPW, 19184 reg: regInfo{ 19185 inputs: []inputInfo{ 19186 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19187 }, 19188 }, 19189 }, 19190 { 19191 name: "CMPUconst", 19192 auxType: auxInt64, 19193 argLen: 1, 19194 asm: s390x.ACMPU, 19195 reg: regInfo{ 19196 inputs: []inputInfo{ 19197 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19198 }, 19199 }, 19200 }, 19201 { 19202 name: "CMPWUconst", 19203 auxType: auxInt32, 19204 argLen: 1, 19205 asm: s390x.ACMPWU, 19206 reg: regInfo{ 19207 inputs: []inputInfo{ 19208 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19209 }, 19210 }, 19211 }, 19212 { 19213 name: "FCMPS", 19214 argLen: 2, 19215 asm: s390x.ACEBR, 19216 reg: regInfo{ 19217 inputs: []inputInfo{ 19218 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19219 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19220 }, 19221 }, 19222 }, 19223 { 19224 name: "FCMP", 19225 argLen: 2, 19226 asm: s390x.AFCMPU, 19227 reg: regInfo{ 19228 inputs: []inputInfo{ 19229 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19230 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19231 }, 19232 }, 19233 }, 19234 { 19235 name: "SLD", 19236 argLen: 2, 19237 asm: s390x.ASLD, 19238 reg: regInfo{ 19239 inputs: []inputInfo{ 19240 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19241 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19242 }, 19243 outputs: []outputInfo{ 19244 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19245 }, 19246 }, 19247 }, 19248 { 19249 name: "SLW", 19250 argLen: 2, 19251 asm: s390x.ASLW, 19252 reg: regInfo{ 19253 inputs: []inputInfo{ 19254 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19255 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19256 }, 19257 outputs: []outputInfo{ 19258 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19259 }, 19260 }, 19261 }, 19262 { 19263 name: "SLDconst", 19264 auxType: auxInt8, 19265 argLen: 1, 19266 asm: s390x.ASLD, 19267 reg: regInfo{ 19268 inputs: []inputInfo{ 19269 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19270 }, 19271 outputs: []outputInfo{ 19272 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19273 }, 19274 }, 19275 }, 19276 { 19277 name: "SLWconst", 19278 auxType: auxInt8, 19279 argLen: 1, 19280 asm: s390x.ASLW, 19281 reg: regInfo{ 19282 inputs: []inputInfo{ 19283 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19284 }, 19285 outputs: []outputInfo{ 19286 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19287 }, 19288 }, 19289 }, 19290 { 19291 name: "SRD", 19292 argLen: 2, 19293 asm: s390x.ASRD, 19294 reg: regInfo{ 19295 inputs: []inputInfo{ 19296 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19297 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19298 }, 19299 outputs: []outputInfo{ 19300 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19301 }, 19302 }, 19303 }, 19304 { 19305 name: "SRW", 19306 argLen: 2, 19307 asm: s390x.ASRW, 19308 reg: regInfo{ 19309 inputs: []inputInfo{ 19310 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19311 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19312 }, 19313 outputs: []outputInfo{ 19314 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19315 }, 19316 }, 19317 }, 19318 { 19319 name: "SRDconst", 19320 auxType: auxInt8, 19321 argLen: 1, 19322 asm: s390x.ASRD, 19323 reg: regInfo{ 19324 inputs: []inputInfo{ 19325 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19326 }, 19327 outputs: []outputInfo{ 19328 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19329 }, 19330 }, 19331 }, 19332 { 19333 name: "SRWconst", 19334 auxType: auxInt8, 19335 argLen: 1, 19336 asm: s390x.ASRW, 19337 reg: regInfo{ 19338 inputs: []inputInfo{ 19339 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19340 }, 19341 outputs: []outputInfo{ 19342 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19343 }, 19344 }, 19345 }, 19346 { 19347 name: "SRAD", 19348 argLen: 2, 19349 clobberFlags: true, 19350 asm: s390x.ASRAD, 19351 reg: regInfo{ 19352 inputs: []inputInfo{ 19353 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19354 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19355 }, 19356 outputs: []outputInfo{ 19357 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19358 }, 19359 }, 19360 }, 19361 { 19362 name: "SRAW", 19363 argLen: 2, 19364 clobberFlags: true, 19365 asm: s390x.ASRAW, 19366 reg: regInfo{ 19367 inputs: []inputInfo{ 19368 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19369 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19370 }, 19371 outputs: []outputInfo{ 19372 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19373 }, 19374 }, 19375 }, 19376 { 19377 name: "SRADconst", 19378 auxType: auxInt8, 19379 argLen: 1, 19380 clobberFlags: true, 19381 asm: s390x.ASRAD, 19382 reg: regInfo{ 19383 inputs: []inputInfo{ 19384 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19385 }, 19386 outputs: []outputInfo{ 19387 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19388 }, 19389 }, 19390 }, 19391 { 19392 name: "SRAWconst", 19393 auxType: auxInt8, 19394 argLen: 1, 19395 clobberFlags: true, 19396 asm: s390x.ASRAW, 19397 reg: regInfo{ 19398 inputs: []inputInfo{ 19399 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19400 }, 19401 outputs: []outputInfo{ 19402 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19403 }, 19404 }, 19405 }, 19406 { 19407 name: "RLLGconst", 19408 auxType: auxInt8, 19409 argLen: 1, 19410 asm: s390x.ARLLG, 19411 reg: regInfo{ 19412 inputs: []inputInfo{ 19413 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19414 }, 19415 outputs: []outputInfo{ 19416 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19417 }, 19418 }, 19419 }, 19420 { 19421 name: "RLLconst", 19422 auxType: auxInt8, 19423 argLen: 1, 19424 asm: s390x.ARLL, 19425 reg: regInfo{ 19426 inputs: []inputInfo{ 19427 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19428 }, 19429 outputs: []outputInfo{ 19430 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19431 }, 19432 }, 19433 }, 19434 { 19435 name: "NEG", 19436 argLen: 1, 19437 clobberFlags: true, 19438 asm: s390x.ANEG, 19439 reg: regInfo{ 19440 inputs: []inputInfo{ 19441 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19442 }, 19443 outputs: []outputInfo{ 19444 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19445 }, 19446 }, 19447 }, 19448 { 19449 name: "NEGW", 19450 argLen: 1, 19451 clobberFlags: true, 19452 asm: s390x.ANEGW, 19453 reg: regInfo{ 19454 inputs: []inputInfo{ 19455 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19456 }, 19457 outputs: []outputInfo{ 19458 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19459 }, 19460 }, 19461 }, 19462 { 19463 name: "NOT", 19464 argLen: 1, 19465 resultInArg0: true, 19466 clobberFlags: true, 19467 reg: regInfo{ 19468 inputs: []inputInfo{ 19469 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19470 }, 19471 outputs: []outputInfo{ 19472 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19473 }, 19474 }, 19475 }, 19476 { 19477 name: "NOTW", 19478 argLen: 1, 19479 resultInArg0: true, 19480 clobberFlags: true, 19481 reg: regInfo{ 19482 inputs: []inputInfo{ 19483 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19484 }, 19485 outputs: []outputInfo{ 19486 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19487 }, 19488 }, 19489 }, 19490 { 19491 name: "FSQRT", 19492 argLen: 1, 19493 asm: s390x.AFSQRT, 19494 reg: regInfo{ 19495 inputs: []inputInfo{ 19496 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19497 }, 19498 outputs: []outputInfo{ 19499 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19500 }, 19501 }, 19502 }, 19503 { 19504 name: "SUBEcarrymask", 19505 argLen: 1, 19506 asm: s390x.ASUBE, 19507 reg: regInfo{ 19508 outputs: []outputInfo{ 19509 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19510 }, 19511 }, 19512 }, 19513 { 19514 name: "SUBEWcarrymask", 19515 argLen: 1, 19516 asm: s390x.ASUBE, 19517 reg: regInfo{ 19518 outputs: []outputInfo{ 19519 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19520 }, 19521 }, 19522 }, 19523 { 19524 name: "MOVDEQ", 19525 argLen: 3, 19526 resultInArg0: true, 19527 asm: s390x.AMOVDEQ, 19528 reg: regInfo{ 19529 inputs: []inputInfo{ 19530 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19531 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19532 }, 19533 outputs: []outputInfo{ 19534 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19535 }, 19536 }, 19537 }, 19538 { 19539 name: "MOVDNE", 19540 argLen: 3, 19541 resultInArg0: true, 19542 asm: s390x.AMOVDNE, 19543 reg: regInfo{ 19544 inputs: []inputInfo{ 19545 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19546 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19547 }, 19548 outputs: []outputInfo{ 19549 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19550 }, 19551 }, 19552 }, 19553 { 19554 name: "MOVDLT", 19555 argLen: 3, 19556 resultInArg0: true, 19557 asm: s390x.AMOVDLT, 19558 reg: regInfo{ 19559 inputs: []inputInfo{ 19560 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19561 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19562 }, 19563 outputs: []outputInfo{ 19564 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19565 }, 19566 }, 19567 }, 19568 { 19569 name: "MOVDLE", 19570 argLen: 3, 19571 resultInArg0: true, 19572 asm: s390x.AMOVDLE, 19573 reg: regInfo{ 19574 inputs: []inputInfo{ 19575 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19576 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19577 }, 19578 outputs: []outputInfo{ 19579 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19580 }, 19581 }, 19582 }, 19583 { 19584 name: "MOVDGT", 19585 argLen: 3, 19586 resultInArg0: true, 19587 asm: s390x.AMOVDGT, 19588 reg: regInfo{ 19589 inputs: []inputInfo{ 19590 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19591 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19592 }, 19593 outputs: []outputInfo{ 19594 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19595 }, 19596 }, 19597 }, 19598 { 19599 name: "MOVDGE", 19600 argLen: 3, 19601 resultInArg0: true, 19602 asm: s390x.AMOVDGE, 19603 reg: regInfo{ 19604 inputs: []inputInfo{ 19605 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19606 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19607 }, 19608 outputs: []outputInfo{ 19609 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19610 }, 19611 }, 19612 }, 19613 { 19614 name: "MOVDGTnoinv", 19615 argLen: 3, 19616 resultInArg0: true, 19617 asm: s390x.AMOVDGT, 19618 reg: regInfo{ 19619 inputs: []inputInfo{ 19620 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19621 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19622 }, 19623 outputs: []outputInfo{ 19624 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19625 }, 19626 }, 19627 }, 19628 { 19629 name: "MOVDGEnoinv", 19630 argLen: 3, 19631 resultInArg0: true, 19632 asm: s390x.AMOVDGE, 19633 reg: regInfo{ 19634 inputs: []inputInfo{ 19635 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19636 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19637 }, 19638 outputs: []outputInfo{ 19639 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19640 }, 19641 }, 19642 }, 19643 { 19644 name: "MOVBreg", 19645 argLen: 1, 19646 asm: s390x.AMOVB, 19647 reg: regInfo{ 19648 inputs: []inputInfo{ 19649 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19650 }, 19651 outputs: []outputInfo{ 19652 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19653 }, 19654 }, 19655 }, 19656 { 19657 name: "MOVBZreg", 19658 argLen: 1, 19659 asm: s390x.AMOVBZ, 19660 reg: regInfo{ 19661 inputs: []inputInfo{ 19662 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19663 }, 19664 outputs: []outputInfo{ 19665 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19666 }, 19667 }, 19668 }, 19669 { 19670 name: "MOVHreg", 19671 argLen: 1, 19672 asm: s390x.AMOVH, 19673 reg: regInfo{ 19674 inputs: []inputInfo{ 19675 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19676 }, 19677 outputs: []outputInfo{ 19678 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19679 }, 19680 }, 19681 }, 19682 { 19683 name: "MOVHZreg", 19684 argLen: 1, 19685 asm: s390x.AMOVHZ, 19686 reg: regInfo{ 19687 inputs: []inputInfo{ 19688 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19689 }, 19690 outputs: []outputInfo{ 19691 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19692 }, 19693 }, 19694 }, 19695 { 19696 name: "MOVWreg", 19697 argLen: 1, 19698 asm: s390x.AMOVW, 19699 reg: regInfo{ 19700 inputs: []inputInfo{ 19701 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19702 }, 19703 outputs: []outputInfo{ 19704 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19705 }, 19706 }, 19707 }, 19708 { 19709 name: "MOVWZreg", 19710 argLen: 1, 19711 asm: s390x.AMOVWZ, 19712 reg: regInfo{ 19713 inputs: []inputInfo{ 19714 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19715 }, 19716 outputs: []outputInfo{ 19717 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19718 }, 19719 }, 19720 }, 19721 { 19722 name: "MOVDreg", 19723 argLen: 1, 19724 asm: s390x.AMOVD, 19725 reg: regInfo{ 19726 inputs: []inputInfo{ 19727 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19728 }, 19729 outputs: []outputInfo{ 19730 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19731 }, 19732 }, 19733 }, 19734 { 19735 name: "MOVDnop", 19736 argLen: 1, 19737 resultInArg0: true, 19738 reg: regInfo{ 19739 inputs: []inputInfo{ 19740 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19741 }, 19742 outputs: []outputInfo{ 19743 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19744 }, 19745 }, 19746 }, 19747 { 19748 name: "MOVDconst", 19749 auxType: auxInt64, 19750 argLen: 0, 19751 rematerializeable: true, 19752 asm: s390x.AMOVD, 19753 reg: regInfo{ 19754 outputs: []outputInfo{ 19755 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19756 }, 19757 }, 19758 }, 19759 { 19760 name: "CFDBRA", 19761 argLen: 1, 19762 asm: s390x.ACFDBRA, 19763 reg: regInfo{ 19764 inputs: []inputInfo{ 19765 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19766 }, 19767 outputs: []outputInfo{ 19768 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19769 }, 19770 }, 19771 }, 19772 { 19773 name: "CGDBRA", 19774 argLen: 1, 19775 asm: s390x.ACGDBRA, 19776 reg: regInfo{ 19777 inputs: []inputInfo{ 19778 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19779 }, 19780 outputs: []outputInfo{ 19781 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19782 }, 19783 }, 19784 }, 19785 { 19786 name: "CFEBRA", 19787 argLen: 1, 19788 asm: s390x.ACFEBRA, 19789 reg: regInfo{ 19790 inputs: []inputInfo{ 19791 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19792 }, 19793 outputs: []outputInfo{ 19794 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19795 }, 19796 }, 19797 }, 19798 { 19799 name: "CGEBRA", 19800 argLen: 1, 19801 asm: s390x.ACGEBRA, 19802 reg: regInfo{ 19803 inputs: []inputInfo{ 19804 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19805 }, 19806 outputs: []outputInfo{ 19807 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19808 }, 19809 }, 19810 }, 19811 { 19812 name: "CEFBRA", 19813 argLen: 1, 19814 asm: s390x.ACEFBRA, 19815 reg: regInfo{ 19816 inputs: []inputInfo{ 19817 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19818 }, 19819 outputs: []outputInfo{ 19820 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19821 }, 19822 }, 19823 }, 19824 { 19825 name: "CDFBRA", 19826 argLen: 1, 19827 asm: s390x.ACDFBRA, 19828 reg: regInfo{ 19829 inputs: []inputInfo{ 19830 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19831 }, 19832 outputs: []outputInfo{ 19833 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19834 }, 19835 }, 19836 }, 19837 { 19838 name: "CEGBRA", 19839 argLen: 1, 19840 asm: s390x.ACEGBRA, 19841 reg: regInfo{ 19842 inputs: []inputInfo{ 19843 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19844 }, 19845 outputs: []outputInfo{ 19846 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19847 }, 19848 }, 19849 }, 19850 { 19851 name: "CDGBRA", 19852 argLen: 1, 19853 asm: s390x.ACDGBRA, 19854 reg: regInfo{ 19855 inputs: []inputInfo{ 19856 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19857 }, 19858 outputs: []outputInfo{ 19859 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19860 }, 19861 }, 19862 }, 19863 { 19864 name: "LEDBR", 19865 argLen: 1, 19866 asm: s390x.ALEDBR, 19867 reg: regInfo{ 19868 inputs: []inputInfo{ 19869 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19870 }, 19871 outputs: []outputInfo{ 19872 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19873 }, 19874 }, 19875 }, 19876 { 19877 name: "LDEBR", 19878 argLen: 1, 19879 asm: s390x.ALDEBR, 19880 reg: regInfo{ 19881 inputs: []inputInfo{ 19882 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19883 }, 19884 outputs: []outputInfo{ 19885 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19886 }, 19887 }, 19888 }, 19889 { 19890 name: "MOVDaddr", 19891 auxType: auxSymOff, 19892 argLen: 1, 19893 rematerializeable: true, 19894 clobberFlags: true, 19895 symEffect: SymRead, 19896 reg: regInfo{ 19897 inputs: []inputInfo{ 19898 {0, 4295000064}, // SP SB 19899 }, 19900 outputs: []outputInfo{ 19901 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19902 }, 19903 }, 19904 }, 19905 { 19906 name: "MOVDaddridx", 19907 auxType: auxSymOff, 19908 argLen: 2, 19909 clobberFlags: true, 19910 symEffect: SymRead, 19911 reg: regInfo{ 19912 inputs: []inputInfo{ 19913 {0, 4295000064}, // SP SB 19914 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19915 }, 19916 outputs: []outputInfo{ 19917 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19918 }, 19919 }, 19920 }, 19921 { 19922 name: "MOVBZload", 19923 auxType: auxSymOff, 19924 argLen: 2, 19925 clobberFlags: true, 19926 faultOnNilArg0: true, 19927 symEffect: SymRead, 19928 asm: s390x.AMOVBZ, 19929 reg: regInfo{ 19930 inputs: []inputInfo{ 19931 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19932 }, 19933 outputs: []outputInfo{ 19934 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19935 }, 19936 }, 19937 }, 19938 { 19939 name: "MOVBload", 19940 auxType: auxSymOff, 19941 argLen: 2, 19942 clobberFlags: true, 19943 faultOnNilArg0: true, 19944 symEffect: SymRead, 19945 asm: s390x.AMOVB, 19946 reg: regInfo{ 19947 inputs: []inputInfo{ 19948 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19949 }, 19950 outputs: []outputInfo{ 19951 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19952 }, 19953 }, 19954 }, 19955 { 19956 name: "MOVHZload", 19957 auxType: auxSymOff, 19958 argLen: 2, 19959 clobberFlags: true, 19960 faultOnNilArg0: true, 19961 symEffect: SymRead, 19962 asm: s390x.AMOVHZ, 19963 reg: regInfo{ 19964 inputs: []inputInfo{ 19965 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19966 }, 19967 outputs: []outputInfo{ 19968 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19969 }, 19970 }, 19971 }, 19972 { 19973 name: "MOVHload", 19974 auxType: auxSymOff, 19975 argLen: 2, 19976 clobberFlags: true, 19977 faultOnNilArg0: true, 19978 symEffect: SymRead, 19979 asm: s390x.AMOVH, 19980 reg: regInfo{ 19981 inputs: []inputInfo{ 19982 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19983 }, 19984 outputs: []outputInfo{ 19985 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19986 }, 19987 }, 19988 }, 19989 { 19990 name: "MOVWZload", 19991 auxType: auxSymOff, 19992 argLen: 2, 19993 clobberFlags: true, 19994 faultOnNilArg0: true, 19995 symEffect: SymRead, 19996 asm: s390x.AMOVWZ, 19997 reg: regInfo{ 19998 inputs: []inputInfo{ 19999 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20000 }, 20001 outputs: []outputInfo{ 20002 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20003 }, 20004 }, 20005 }, 20006 { 20007 name: "MOVWload", 20008 auxType: auxSymOff, 20009 argLen: 2, 20010 clobberFlags: true, 20011 faultOnNilArg0: true, 20012 symEffect: SymRead, 20013 asm: s390x.AMOVW, 20014 reg: regInfo{ 20015 inputs: []inputInfo{ 20016 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20017 }, 20018 outputs: []outputInfo{ 20019 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20020 }, 20021 }, 20022 }, 20023 { 20024 name: "MOVDload", 20025 auxType: auxSymOff, 20026 argLen: 2, 20027 clobberFlags: true, 20028 faultOnNilArg0: true, 20029 symEffect: SymRead, 20030 asm: s390x.AMOVD, 20031 reg: regInfo{ 20032 inputs: []inputInfo{ 20033 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20034 }, 20035 outputs: []outputInfo{ 20036 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20037 }, 20038 }, 20039 }, 20040 { 20041 name: "MOVWBR", 20042 argLen: 1, 20043 asm: s390x.AMOVWBR, 20044 reg: regInfo{ 20045 inputs: []inputInfo{ 20046 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20047 }, 20048 outputs: []outputInfo{ 20049 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20050 }, 20051 }, 20052 }, 20053 { 20054 name: "MOVDBR", 20055 argLen: 1, 20056 asm: s390x.AMOVDBR, 20057 reg: regInfo{ 20058 inputs: []inputInfo{ 20059 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20060 }, 20061 outputs: []outputInfo{ 20062 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20063 }, 20064 }, 20065 }, 20066 { 20067 name: "MOVHBRload", 20068 auxType: auxSymOff, 20069 argLen: 2, 20070 clobberFlags: true, 20071 faultOnNilArg0: true, 20072 symEffect: SymRead, 20073 asm: s390x.AMOVHBR, 20074 reg: regInfo{ 20075 inputs: []inputInfo{ 20076 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20077 }, 20078 outputs: []outputInfo{ 20079 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20080 }, 20081 }, 20082 }, 20083 { 20084 name: "MOVWBRload", 20085 auxType: auxSymOff, 20086 argLen: 2, 20087 clobberFlags: true, 20088 faultOnNilArg0: true, 20089 symEffect: SymRead, 20090 asm: s390x.AMOVWBR, 20091 reg: regInfo{ 20092 inputs: []inputInfo{ 20093 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20094 }, 20095 outputs: []outputInfo{ 20096 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20097 }, 20098 }, 20099 }, 20100 { 20101 name: "MOVDBRload", 20102 auxType: auxSymOff, 20103 argLen: 2, 20104 clobberFlags: true, 20105 faultOnNilArg0: true, 20106 symEffect: SymRead, 20107 asm: s390x.AMOVDBR, 20108 reg: regInfo{ 20109 inputs: []inputInfo{ 20110 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20111 }, 20112 outputs: []outputInfo{ 20113 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20114 }, 20115 }, 20116 }, 20117 { 20118 name: "MOVBstore", 20119 auxType: auxSymOff, 20120 argLen: 3, 20121 clobberFlags: true, 20122 faultOnNilArg0: true, 20123 symEffect: SymWrite, 20124 asm: s390x.AMOVB, 20125 reg: regInfo{ 20126 inputs: []inputInfo{ 20127 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20128 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20129 }, 20130 }, 20131 }, 20132 { 20133 name: "MOVHstore", 20134 auxType: auxSymOff, 20135 argLen: 3, 20136 clobberFlags: true, 20137 faultOnNilArg0: true, 20138 symEffect: SymWrite, 20139 asm: s390x.AMOVH, 20140 reg: regInfo{ 20141 inputs: []inputInfo{ 20142 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20143 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20144 }, 20145 }, 20146 }, 20147 { 20148 name: "MOVWstore", 20149 auxType: auxSymOff, 20150 argLen: 3, 20151 clobberFlags: true, 20152 faultOnNilArg0: true, 20153 symEffect: SymWrite, 20154 asm: s390x.AMOVW, 20155 reg: regInfo{ 20156 inputs: []inputInfo{ 20157 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20158 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20159 }, 20160 }, 20161 }, 20162 { 20163 name: "MOVDstore", 20164 auxType: auxSymOff, 20165 argLen: 3, 20166 clobberFlags: true, 20167 faultOnNilArg0: true, 20168 symEffect: SymWrite, 20169 asm: s390x.AMOVD, 20170 reg: regInfo{ 20171 inputs: []inputInfo{ 20172 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20173 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20174 }, 20175 }, 20176 }, 20177 { 20178 name: "MOVHBRstore", 20179 auxType: auxSymOff, 20180 argLen: 3, 20181 clobberFlags: true, 20182 faultOnNilArg0: true, 20183 symEffect: SymWrite, 20184 asm: s390x.AMOVHBR, 20185 reg: regInfo{ 20186 inputs: []inputInfo{ 20187 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20188 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20189 }, 20190 }, 20191 }, 20192 { 20193 name: "MOVWBRstore", 20194 auxType: auxSymOff, 20195 argLen: 3, 20196 clobberFlags: true, 20197 faultOnNilArg0: true, 20198 symEffect: SymWrite, 20199 asm: s390x.AMOVWBR, 20200 reg: regInfo{ 20201 inputs: []inputInfo{ 20202 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20203 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20204 }, 20205 }, 20206 }, 20207 { 20208 name: "MOVDBRstore", 20209 auxType: auxSymOff, 20210 argLen: 3, 20211 clobberFlags: true, 20212 faultOnNilArg0: true, 20213 symEffect: SymWrite, 20214 asm: s390x.AMOVDBR, 20215 reg: regInfo{ 20216 inputs: []inputInfo{ 20217 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20218 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20219 }, 20220 }, 20221 }, 20222 { 20223 name: "MVC", 20224 auxType: auxSymValAndOff, 20225 argLen: 3, 20226 clobberFlags: true, 20227 faultOnNilArg0: true, 20228 faultOnNilArg1: true, 20229 symEffect: SymNone, 20230 asm: s390x.AMVC, 20231 reg: regInfo{ 20232 inputs: []inputInfo{ 20233 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20234 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20235 }, 20236 }, 20237 }, 20238 { 20239 name: "MOVBZloadidx", 20240 auxType: auxSymOff, 20241 argLen: 3, 20242 commutative: true, 20243 clobberFlags: true, 20244 symEffect: SymRead, 20245 asm: s390x.AMOVBZ, 20246 reg: regInfo{ 20247 inputs: []inputInfo{ 20248 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20249 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20250 }, 20251 outputs: []outputInfo{ 20252 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20253 }, 20254 }, 20255 }, 20256 { 20257 name: "MOVHZloadidx", 20258 auxType: auxSymOff, 20259 argLen: 3, 20260 commutative: true, 20261 clobberFlags: true, 20262 symEffect: SymRead, 20263 asm: s390x.AMOVHZ, 20264 reg: regInfo{ 20265 inputs: []inputInfo{ 20266 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20267 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20268 }, 20269 outputs: []outputInfo{ 20270 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20271 }, 20272 }, 20273 }, 20274 { 20275 name: "MOVWZloadidx", 20276 auxType: auxSymOff, 20277 argLen: 3, 20278 commutative: true, 20279 clobberFlags: true, 20280 symEffect: SymRead, 20281 asm: s390x.AMOVWZ, 20282 reg: regInfo{ 20283 inputs: []inputInfo{ 20284 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20285 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20286 }, 20287 outputs: []outputInfo{ 20288 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20289 }, 20290 }, 20291 }, 20292 { 20293 name: "MOVDloadidx", 20294 auxType: auxSymOff, 20295 argLen: 3, 20296 commutative: true, 20297 clobberFlags: true, 20298 symEffect: SymRead, 20299 asm: s390x.AMOVD, 20300 reg: regInfo{ 20301 inputs: []inputInfo{ 20302 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20303 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20304 }, 20305 outputs: []outputInfo{ 20306 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20307 }, 20308 }, 20309 }, 20310 { 20311 name: "MOVHBRloadidx", 20312 auxType: auxSymOff, 20313 argLen: 3, 20314 commutative: true, 20315 clobberFlags: true, 20316 symEffect: SymRead, 20317 asm: s390x.AMOVHBR, 20318 reg: regInfo{ 20319 inputs: []inputInfo{ 20320 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20321 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20322 }, 20323 outputs: []outputInfo{ 20324 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20325 }, 20326 }, 20327 }, 20328 { 20329 name: "MOVWBRloadidx", 20330 auxType: auxSymOff, 20331 argLen: 3, 20332 commutative: true, 20333 clobberFlags: true, 20334 symEffect: SymRead, 20335 asm: s390x.AMOVWBR, 20336 reg: regInfo{ 20337 inputs: []inputInfo{ 20338 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20339 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20340 }, 20341 outputs: []outputInfo{ 20342 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20343 }, 20344 }, 20345 }, 20346 { 20347 name: "MOVDBRloadidx", 20348 auxType: auxSymOff, 20349 argLen: 3, 20350 commutative: true, 20351 clobberFlags: true, 20352 symEffect: SymRead, 20353 asm: s390x.AMOVDBR, 20354 reg: regInfo{ 20355 inputs: []inputInfo{ 20356 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20357 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20358 }, 20359 outputs: []outputInfo{ 20360 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20361 }, 20362 }, 20363 }, 20364 { 20365 name: "MOVBstoreidx", 20366 auxType: auxSymOff, 20367 argLen: 4, 20368 commutative: true, 20369 clobberFlags: true, 20370 symEffect: SymWrite, 20371 asm: s390x.AMOVB, 20372 reg: regInfo{ 20373 inputs: []inputInfo{ 20374 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20375 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20376 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20377 }, 20378 }, 20379 }, 20380 { 20381 name: "MOVHstoreidx", 20382 auxType: auxSymOff, 20383 argLen: 4, 20384 commutative: true, 20385 clobberFlags: true, 20386 symEffect: SymWrite, 20387 asm: s390x.AMOVH, 20388 reg: regInfo{ 20389 inputs: []inputInfo{ 20390 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20391 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20392 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20393 }, 20394 }, 20395 }, 20396 { 20397 name: "MOVWstoreidx", 20398 auxType: auxSymOff, 20399 argLen: 4, 20400 commutative: true, 20401 clobberFlags: true, 20402 symEffect: SymWrite, 20403 asm: s390x.AMOVW, 20404 reg: regInfo{ 20405 inputs: []inputInfo{ 20406 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20407 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20408 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20409 }, 20410 }, 20411 }, 20412 { 20413 name: "MOVDstoreidx", 20414 auxType: auxSymOff, 20415 argLen: 4, 20416 commutative: true, 20417 clobberFlags: true, 20418 symEffect: SymWrite, 20419 asm: s390x.AMOVD, 20420 reg: regInfo{ 20421 inputs: []inputInfo{ 20422 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20423 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20424 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20425 }, 20426 }, 20427 }, 20428 { 20429 name: "MOVHBRstoreidx", 20430 auxType: auxSymOff, 20431 argLen: 4, 20432 commutative: true, 20433 clobberFlags: true, 20434 symEffect: SymWrite, 20435 asm: s390x.AMOVHBR, 20436 reg: regInfo{ 20437 inputs: []inputInfo{ 20438 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20439 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20440 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20441 }, 20442 }, 20443 }, 20444 { 20445 name: "MOVWBRstoreidx", 20446 auxType: auxSymOff, 20447 argLen: 4, 20448 commutative: true, 20449 clobberFlags: true, 20450 symEffect: SymWrite, 20451 asm: s390x.AMOVWBR, 20452 reg: regInfo{ 20453 inputs: []inputInfo{ 20454 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20455 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20456 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20457 }, 20458 }, 20459 }, 20460 { 20461 name: "MOVDBRstoreidx", 20462 auxType: auxSymOff, 20463 argLen: 4, 20464 commutative: true, 20465 clobberFlags: true, 20466 symEffect: SymWrite, 20467 asm: s390x.AMOVDBR, 20468 reg: regInfo{ 20469 inputs: []inputInfo{ 20470 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20471 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20472 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20473 }, 20474 }, 20475 }, 20476 { 20477 name: "MOVBstoreconst", 20478 auxType: auxSymValAndOff, 20479 argLen: 2, 20480 faultOnNilArg0: true, 20481 symEffect: SymWrite, 20482 asm: s390x.AMOVB, 20483 reg: regInfo{ 20484 inputs: []inputInfo{ 20485 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20486 }, 20487 }, 20488 }, 20489 { 20490 name: "MOVHstoreconst", 20491 auxType: auxSymValAndOff, 20492 argLen: 2, 20493 faultOnNilArg0: true, 20494 symEffect: SymWrite, 20495 asm: s390x.AMOVH, 20496 reg: regInfo{ 20497 inputs: []inputInfo{ 20498 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20499 }, 20500 }, 20501 }, 20502 { 20503 name: "MOVWstoreconst", 20504 auxType: auxSymValAndOff, 20505 argLen: 2, 20506 faultOnNilArg0: true, 20507 symEffect: SymWrite, 20508 asm: s390x.AMOVW, 20509 reg: regInfo{ 20510 inputs: []inputInfo{ 20511 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20512 }, 20513 }, 20514 }, 20515 { 20516 name: "MOVDstoreconst", 20517 auxType: auxSymValAndOff, 20518 argLen: 2, 20519 faultOnNilArg0: true, 20520 symEffect: SymWrite, 20521 asm: s390x.AMOVD, 20522 reg: regInfo{ 20523 inputs: []inputInfo{ 20524 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20525 }, 20526 }, 20527 }, 20528 { 20529 name: "CLEAR", 20530 auxType: auxSymValAndOff, 20531 argLen: 2, 20532 clobberFlags: true, 20533 faultOnNilArg0: true, 20534 symEffect: SymWrite, 20535 asm: s390x.ACLEAR, 20536 reg: regInfo{ 20537 inputs: []inputInfo{ 20538 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20539 }, 20540 }, 20541 }, 20542 { 20543 name: "CALLstatic", 20544 auxType: auxSymOff, 20545 argLen: 1, 20546 clobberFlags: true, 20547 call: true, 20548 symEffect: SymNone, 20549 reg: regInfo{ 20550 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20551 }, 20552 }, 20553 { 20554 name: "CALLclosure", 20555 auxType: auxInt64, 20556 argLen: 3, 20557 clobberFlags: true, 20558 call: true, 20559 reg: regInfo{ 20560 inputs: []inputInfo{ 20561 {1, 4096}, // R12 20562 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20563 }, 20564 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20565 }, 20566 }, 20567 { 20568 name: "CALLinter", 20569 auxType: auxInt64, 20570 argLen: 2, 20571 clobberFlags: true, 20572 call: true, 20573 reg: regInfo{ 20574 inputs: []inputInfo{ 20575 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20576 }, 20577 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20578 }, 20579 }, 20580 { 20581 name: "InvertFlags", 20582 argLen: 1, 20583 reg: regInfo{}, 20584 }, 20585 { 20586 name: "LoweredGetG", 20587 argLen: 1, 20588 reg: regInfo{ 20589 outputs: []outputInfo{ 20590 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20591 }, 20592 }, 20593 }, 20594 { 20595 name: "LoweredGetClosurePtr", 20596 argLen: 0, 20597 reg: regInfo{ 20598 outputs: []outputInfo{ 20599 {0, 4096}, // R12 20600 }, 20601 }, 20602 }, 20603 { 20604 name: "LoweredNilCheck", 20605 argLen: 2, 20606 clobberFlags: true, 20607 nilCheck: true, 20608 faultOnNilArg0: true, 20609 reg: regInfo{ 20610 inputs: []inputInfo{ 20611 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20612 }, 20613 }, 20614 }, 20615 { 20616 name: "LoweredRound32F", 20617 argLen: 1, 20618 resultInArg0: true, 20619 reg: regInfo{ 20620 inputs: []inputInfo{ 20621 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20622 }, 20623 outputs: []outputInfo{ 20624 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20625 }, 20626 }, 20627 }, 20628 { 20629 name: "LoweredRound64F", 20630 argLen: 1, 20631 resultInArg0: true, 20632 reg: regInfo{ 20633 inputs: []inputInfo{ 20634 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20635 }, 20636 outputs: []outputInfo{ 20637 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20638 }, 20639 }, 20640 }, 20641 { 20642 name: "MOVDconvert", 20643 argLen: 2, 20644 asm: s390x.AMOVD, 20645 reg: regInfo{ 20646 inputs: []inputInfo{ 20647 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20648 }, 20649 outputs: []outputInfo{ 20650 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20651 }, 20652 }, 20653 }, 20654 { 20655 name: "FlagEQ", 20656 argLen: 0, 20657 reg: regInfo{}, 20658 }, 20659 { 20660 name: "FlagLT", 20661 argLen: 0, 20662 reg: regInfo{}, 20663 }, 20664 { 20665 name: "FlagGT", 20666 argLen: 0, 20667 reg: regInfo{}, 20668 }, 20669 { 20670 name: "MOVWZatomicload", 20671 auxType: auxSymOff, 20672 argLen: 2, 20673 faultOnNilArg0: true, 20674 symEffect: SymRead, 20675 asm: s390x.AMOVWZ, 20676 reg: regInfo{ 20677 inputs: []inputInfo{ 20678 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20679 }, 20680 outputs: []outputInfo{ 20681 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20682 }, 20683 }, 20684 }, 20685 { 20686 name: "MOVDatomicload", 20687 auxType: auxSymOff, 20688 argLen: 2, 20689 faultOnNilArg0: true, 20690 symEffect: SymRead, 20691 asm: s390x.AMOVD, 20692 reg: regInfo{ 20693 inputs: []inputInfo{ 20694 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20695 }, 20696 outputs: []outputInfo{ 20697 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20698 }, 20699 }, 20700 }, 20701 { 20702 name: "MOVWatomicstore", 20703 auxType: auxSymOff, 20704 argLen: 3, 20705 clobberFlags: true, 20706 faultOnNilArg0: true, 20707 hasSideEffects: true, 20708 symEffect: SymWrite, 20709 asm: s390x.AMOVW, 20710 reg: regInfo{ 20711 inputs: []inputInfo{ 20712 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20713 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20714 }, 20715 }, 20716 }, 20717 { 20718 name: "MOVDatomicstore", 20719 auxType: auxSymOff, 20720 argLen: 3, 20721 clobberFlags: true, 20722 faultOnNilArg0: true, 20723 hasSideEffects: true, 20724 symEffect: SymWrite, 20725 asm: s390x.AMOVD, 20726 reg: regInfo{ 20727 inputs: []inputInfo{ 20728 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20729 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20730 }, 20731 }, 20732 }, 20733 { 20734 name: "LAA", 20735 auxType: auxSymOff, 20736 argLen: 3, 20737 faultOnNilArg0: true, 20738 hasSideEffects: true, 20739 symEffect: SymRdWr, 20740 asm: s390x.ALAA, 20741 reg: regInfo{ 20742 inputs: []inputInfo{ 20743 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20744 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20745 }, 20746 outputs: []outputInfo{ 20747 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20748 }, 20749 }, 20750 }, 20751 { 20752 name: "LAAG", 20753 auxType: auxSymOff, 20754 argLen: 3, 20755 faultOnNilArg0: true, 20756 hasSideEffects: true, 20757 symEffect: SymRdWr, 20758 asm: s390x.ALAAG, 20759 reg: regInfo{ 20760 inputs: []inputInfo{ 20761 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20762 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20763 }, 20764 outputs: []outputInfo{ 20765 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20766 }, 20767 }, 20768 }, 20769 { 20770 name: "AddTupleFirst32", 20771 argLen: 2, 20772 reg: regInfo{}, 20773 }, 20774 { 20775 name: "AddTupleFirst64", 20776 argLen: 2, 20777 reg: regInfo{}, 20778 }, 20779 { 20780 name: "LoweredAtomicCas32", 20781 auxType: auxSymOff, 20782 argLen: 4, 20783 clobberFlags: true, 20784 faultOnNilArg0: true, 20785 hasSideEffects: true, 20786 symEffect: SymRdWr, 20787 asm: s390x.ACS, 20788 reg: regInfo{ 20789 inputs: []inputInfo{ 20790 {1, 1}, // R0 20791 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20792 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20793 }, 20794 clobbers: 1, // R0 20795 outputs: []outputInfo{ 20796 {1, 0}, 20797 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20798 }, 20799 }, 20800 }, 20801 { 20802 name: "LoweredAtomicCas64", 20803 auxType: auxSymOff, 20804 argLen: 4, 20805 clobberFlags: true, 20806 faultOnNilArg0: true, 20807 hasSideEffects: true, 20808 symEffect: SymRdWr, 20809 asm: s390x.ACSG, 20810 reg: regInfo{ 20811 inputs: []inputInfo{ 20812 {1, 1}, // R0 20813 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20814 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20815 }, 20816 clobbers: 1, // R0 20817 outputs: []outputInfo{ 20818 {1, 0}, 20819 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20820 }, 20821 }, 20822 }, 20823 { 20824 name: "LoweredAtomicExchange32", 20825 auxType: auxSymOff, 20826 argLen: 3, 20827 clobberFlags: true, 20828 faultOnNilArg0: true, 20829 hasSideEffects: true, 20830 symEffect: SymRdWr, 20831 asm: s390x.ACS, 20832 reg: regInfo{ 20833 inputs: []inputInfo{ 20834 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20835 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20836 }, 20837 outputs: []outputInfo{ 20838 {1, 0}, 20839 {0, 1}, // R0 20840 }, 20841 }, 20842 }, 20843 { 20844 name: "LoweredAtomicExchange64", 20845 auxType: auxSymOff, 20846 argLen: 3, 20847 clobberFlags: true, 20848 faultOnNilArg0: true, 20849 hasSideEffects: true, 20850 symEffect: SymRdWr, 20851 asm: s390x.ACSG, 20852 reg: regInfo{ 20853 inputs: []inputInfo{ 20854 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20855 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20856 }, 20857 outputs: []outputInfo{ 20858 {1, 0}, 20859 {0, 1}, // R0 20860 }, 20861 }, 20862 }, 20863 { 20864 name: "FLOGR", 20865 argLen: 1, 20866 clobberFlags: true, 20867 asm: s390x.AFLOGR, 20868 reg: regInfo{ 20869 inputs: []inputInfo{ 20870 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20871 }, 20872 clobbers: 2, // R1 20873 outputs: []outputInfo{ 20874 {0, 1}, // R0 20875 }, 20876 }, 20877 }, 20878 { 20879 name: "STMG2", 20880 auxType: auxSymOff, 20881 argLen: 4, 20882 faultOnNilArg0: true, 20883 symEffect: SymWrite, 20884 asm: s390x.ASTMG, 20885 reg: regInfo{ 20886 inputs: []inputInfo{ 20887 {1, 2}, // R1 20888 {2, 4}, // R2 20889 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20890 }, 20891 }, 20892 }, 20893 { 20894 name: "STMG3", 20895 auxType: auxSymOff, 20896 argLen: 5, 20897 faultOnNilArg0: true, 20898 symEffect: SymWrite, 20899 asm: s390x.ASTMG, 20900 reg: regInfo{ 20901 inputs: []inputInfo{ 20902 {1, 2}, // R1 20903 {2, 4}, // R2 20904 {3, 8}, // R3 20905 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20906 }, 20907 }, 20908 }, 20909 { 20910 name: "STMG4", 20911 auxType: auxSymOff, 20912 argLen: 6, 20913 faultOnNilArg0: true, 20914 symEffect: SymWrite, 20915 asm: s390x.ASTMG, 20916 reg: regInfo{ 20917 inputs: []inputInfo{ 20918 {1, 2}, // R1 20919 {2, 4}, // R2 20920 {3, 8}, // R3 20921 {4, 16}, // R4 20922 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20923 }, 20924 }, 20925 }, 20926 { 20927 name: "STM2", 20928 auxType: auxSymOff, 20929 argLen: 4, 20930 faultOnNilArg0: true, 20931 symEffect: SymWrite, 20932 asm: s390x.ASTMY, 20933 reg: regInfo{ 20934 inputs: []inputInfo{ 20935 {1, 2}, // R1 20936 {2, 4}, // R2 20937 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20938 }, 20939 }, 20940 }, 20941 { 20942 name: "STM3", 20943 auxType: auxSymOff, 20944 argLen: 5, 20945 faultOnNilArg0: true, 20946 symEffect: SymWrite, 20947 asm: s390x.ASTMY, 20948 reg: regInfo{ 20949 inputs: []inputInfo{ 20950 {1, 2}, // R1 20951 {2, 4}, // R2 20952 {3, 8}, // R3 20953 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20954 }, 20955 }, 20956 }, 20957 { 20958 name: "STM4", 20959 auxType: auxSymOff, 20960 argLen: 6, 20961 faultOnNilArg0: true, 20962 symEffect: SymWrite, 20963 asm: s390x.ASTMY, 20964 reg: regInfo{ 20965 inputs: []inputInfo{ 20966 {1, 2}, // R1 20967 {2, 4}, // R2 20968 {3, 8}, // R3 20969 {4, 16}, // R4 20970 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20971 }, 20972 }, 20973 }, 20974 { 20975 name: "LoweredMove", 20976 auxType: auxInt64, 20977 argLen: 4, 20978 clobberFlags: true, 20979 faultOnNilArg0: true, 20980 faultOnNilArg1: true, 20981 reg: regInfo{ 20982 inputs: []inputInfo{ 20983 {0, 2}, // R1 20984 {1, 4}, // R2 20985 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20986 }, 20987 clobbers: 6, // R1 R2 20988 }, 20989 }, 20990 { 20991 name: "LoweredZero", 20992 auxType: auxInt64, 20993 argLen: 3, 20994 clobberFlags: true, 20995 faultOnNilArg0: true, 20996 reg: regInfo{ 20997 inputs: []inputInfo{ 20998 {0, 2}, // R1 20999 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21000 }, 21001 clobbers: 2, // R1 21002 }, 21003 }, 21004 21005 { 21006 name: "Add8", 21007 argLen: 2, 21008 commutative: true, 21009 generic: true, 21010 }, 21011 { 21012 name: "Add16", 21013 argLen: 2, 21014 commutative: true, 21015 generic: true, 21016 }, 21017 { 21018 name: "Add32", 21019 argLen: 2, 21020 commutative: true, 21021 generic: true, 21022 }, 21023 { 21024 name: "Add64", 21025 argLen: 2, 21026 commutative: true, 21027 generic: true, 21028 }, 21029 { 21030 name: "AddPtr", 21031 argLen: 2, 21032 generic: true, 21033 }, 21034 { 21035 name: "Add32F", 21036 argLen: 2, 21037 commutative: true, 21038 generic: true, 21039 }, 21040 { 21041 name: "Add64F", 21042 argLen: 2, 21043 commutative: true, 21044 generic: true, 21045 }, 21046 { 21047 name: "Sub8", 21048 argLen: 2, 21049 generic: true, 21050 }, 21051 { 21052 name: "Sub16", 21053 argLen: 2, 21054 generic: true, 21055 }, 21056 { 21057 name: "Sub32", 21058 argLen: 2, 21059 generic: true, 21060 }, 21061 { 21062 name: "Sub64", 21063 argLen: 2, 21064 generic: true, 21065 }, 21066 { 21067 name: "SubPtr", 21068 argLen: 2, 21069 generic: true, 21070 }, 21071 { 21072 name: "Sub32F", 21073 argLen: 2, 21074 generic: true, 21075 }, 21076 { 21077 name: "Sub64F", 21078 argLen: 2, 21079 generic: true, 21080 }, 21081 { 21082 name: "Mul8", 21083 argLen: 2, 21084 commutative: true, 21085 generic: true, 21086 }, 21087 { 21088 name: "Mul16", 21089 argLen: 2, 21090 commutative: true, 21091 generic: true, 21092 }, 21093 { 21094 name: "Mul32", 21095 argLen: 2, 21096 commutative: true, 21097 generic: true, 21098 }, 21099 { 21100 name: "Mul64", 21101 argLen: 2, 21102 commutative: true, 21103 generic: true, 21104 }, 21105 { 21106 name: "Mul32F", 21107 argLen: 2, 21108 commutative: true, 21109 generic: true, 21110 }, 21111 { 21112 name: "Mul64F", 21113 argLen: 2, 21114 commutative: true, 21115 generic: true, 21116 }, 21117 { 21118 name: "Div32F", 21119 argLen: 2, 21120 generic: true, 21121 }, 21122 { 21123 name: "Div64F", 21124 argLen: 2, 21125 generic: true, 21126 }, 21127 { 21128 name: "Hmul32", 21129 argLen: 2, 21130 commutative: true, 21131 generic: true, 21132 }, 21133 { 21134 name: "Hmul32u", 21135 argLen: 2, 21136 commutative: true, 21137 generic: true, 21138 }, 21139 { 21140 name: "Hmul64", 21141 argLen: 2, 21142 commutative: true, 21143 generic: true, 21144 }, 21145 { 21146 name: "Hmul64u", 21147 argLen: 2, 21148 commutative: true, 21149 generic: true, 21150 }, 21151 { 21152 name: "Mul32uhilo", 21153 argLen: 2, 21154 commutative: true, 21155 generic: true, 21156 }, 21157 { 21158 name: "Mul64uhilo", 21159 argLen: 2, 21160 commutative: true, 21161 generic: true, 21162 }, 21163 { 21164 name: "Avg32u", 21165 argLen: 2, 21166 generic: true, 21167 }, 21168 { 21169 name: "Avg64u", 21170 argLen: 2, 21171 generic: true, 21172 }, 21173 { 21174 name: "Div8", 21175 argLen: 2, 21176 generic: true, 21177 }, 21178 { 21179 name: "Div8u", 21180 argLen: 2, 21181 generic: true, 21182 }, 21183 { 21184 name: "Div16", 21185 argLen: 2, 21186 generic: true, 21187 }, 21188 { 21189 name: "Div16u", 21190 argLen: 2, 21191 generic: true, 21192 }, 21193 { 21194 name: "Div32", 21195 argLen: 2, 21196 generic: true, 21197 }, 21198 { 21199 name: "Div32u", 21200 argLen: 2, 21201 generic: true, 21202 }, 21203 { 21204 name: "Div64", 21205 argLen: 2, 21206 generic: true, 21207 }, 21208 { 21209 name: "Div64u", 21210 argLen: 2, 21211 generic: true, 21212 }, 21213 { 21214 name: "Div128u", 21215 argLen: 3, 21216 generic: true, 21217 }, 21218 { 21219 name: "Mod8", 21220 argLen: 2, 21221 generic: true, 21222 }, 21223 { 21224 name: "Mod8u", 21225 argLen: 2, 21226 generic: true, 21227 }, 21228 { 21229 name: "Mod16", 21230 argLen: 2, 21231 generic: true, 21232 }, 21233 { 21234 name: "Mod16u", 21235 argLen: 2, 21236 generic: true, 21237 }, 21238 { 21239 name: "Mod32", 21240 argLen: 2, 21241 generic: true, 21242 }, 21243 { 21244 name: "Mod32u", 21245 argLen: 2, 21246 generic: true, 21247 }, 21248 { 21249 name: "Mod64", 21250 argLen: 2, 21251 generic: true, 21252 }, 21253 { 21254 name: "Mod64u", 21255 argLen: 2, 21256 generic: true, 21257 }, 21258 { 21259 name: "And8", 21260 argLen: 2, 21261 commutative: true, 21262 generic: true, 21263 }, 21264 { 21265 name: "And16", 21266 argLen: 2, 21267 commutative: true, 21268 generic: true, 21269 }, 21270 { 21271 name: "And32", 21272 argLen: 2, 21273 commutative: true, 21274 generic: true, 21275 }, 21276 { 21277 name: "And64", 21278 argLen: 2, 21279 commutative: true, 21280 generic: true, 21281 }, 21282 { 21283 name: "Or8", 21284 argLen: 2, 21285 commutative: true, 21286 generic: true, 21287 }, 21288 { 21289 name: "Or16", 21290 argLen: 2, 21291 commutative: true, 21292 generic: true, 21293 }, 21294 { 21295 name: "Or32", 21296 argLen: 2, 21297 commutative: true, 21298 generic: true, 21299 }, 21300 { 21301 name: "Or64", 21302 argLen: 2, 21303 commutative: true, 21304 generic: true, 21305 }, 21306 { 21307 name: "Xor8", 21308 argLen: 2, 21309 commutative: true, 21310 generic: true, 21311 }, 21312 { 21313 name: "Xor16", 21314 argLen: 2, 21315 commutative: true, 21316 generic: true, 21317 }, 21318 { 21319 name: "Xor32", 21320 argLen: 2, 21321 commutative: true, 21322 generic: true, 21323 }, 21324 { 21325 name: "Xor64", 21326 argLen: 2, 21327 commutative: true, 21328 generic: true, 21329 }, 21330 { 21331 name: "Lsh8x8", 21332 argLen: 2, 21333 generic: true, 21334 }, 21335 { 21336 name: "Lsh8x16", 21337 argLen: 2, 21338 generic: true, 21339 }, 21340 { 21341 name: "Lsh8x32", 21342 argLen: 2, 21343 generic: true, 21344 }, 21345 { 21346 name: "Lsh8x64", 21347 argLen: 2, 21348 generic: true, 21349 }, 21350 { 21351 name: "Lsh16x8", 21352 argLen: 2, 21353 generic: true, 21354 }, 21355 { 21356 name: "Lsh16x16", 21357 argLen: 2, 21358 generic: true, 21359 }, 21360 { 21361 name: "Lsh16x32", 21362 argLen: 2, 21363 generic: true, 21364 }, 21365 { 21366 name: "Lsh16x64", 21367 argLen: 2, 21368 generic: true, 21369 }, 21370 { 21371 name: "Lsh32x8", 21372 argLen: 2, 21373 generic: true, 21374 }, 21375 { 21376 name: "Lsh32x16", 21377 argLen: 2, 21378 generic: true, 21379 }, 21380 { 21381 name: "Lsh32x32", 21382 argLen: 2, 21383 generic: true, 21384 }, 21385 { 21386 name: "Lsh32x64", 21387 argLen: 2, 21388 generic: true, 21389 }, 21390 { 21391 name: "Lsh64x8", 21392 argLen: 2, 21393 generic: true, 21394 }, 21395 { 21396 name: "Lsh64x16", 21397 argLen: 2, 21398 generic: true, 21399 }, 21400 { 21401 name: "Lsh64x32", 21402 argLen: 2, 21403 generic: true, 21404 }, 21405 { 21406 name: "Lsh64x64", 21407 argLen: 2, 21408 generic: true, 21409 }, 21410 { 21411 name: "Rsh8x8", 21412 argLen: 2, 21413 generic: true, 21414 }, 21415 { 21416 name: "Rsh8x16", 21417 argLen: 2, 21418 generic: true, 21419 }, 21420 { 21421 name: "Rsh8x32", 21422 argLen: 2, 21423 generic: true, 21424 }, 21425 { 21426 name: "Rsh8x64", 21427 argLen: 2, 21428 generic: true, 21429 }, 21430 { 21431 name: "Rsh16x8", 21432 argLen: 2, 21433 generic: true, 21434 }, 21435 { 21436 name: "Rsh16x16", 21437 argLen: 2, 21438 generic: true, 21439 }, 21440 { 21441 name: "Rsh16x32", 21442 argLen: 2, 21443 generic: true, 21444 }, 21445 { 21446 name: "Rsh16x64", 21447 argLen: 2, 21448 generic: true, 21449 }, 21450 { 21451 name: "Rsh32x8", 21452 argLen: 2, 21453 generic: true, 21454 }, 21455 { 21456 name: "Rsh32x16", 21457 argLen: 2, 21458 generic: true, 21459 }, 21460 { 21461 name: "Rsh32x32", 21462 argLen: 2, 21463 generic: true, 21464 }, 21465 { 21466 name: "Rsh32x64", 21467 argLen: 2, 21468 generic: true, 21469 }, 21470 { 21471 name: "Rsh64x8", 21472 argLen: 2, 21473 generic: true, 21474 }, 21475 { 21476 name: "Rsh64x16", 21477 argLen: 2, 21478 generic: true, 21479 }, 21480 { 21481 name: "Rsh64x32", 21482 argLen: 2, 21483 generic: true, 21484 }, 21485 { 21486 name: "Rsh64x64", 21487 argLen: 2, 21488 generic: true, 21489 }, 21490 { 21491 name: "Rsh8Ux8", 21492 argLen: 2, 21493 generic: true, 21494 }, 21495 { 21496 name: "Rsh8Ux16", 21497 argLen: 2, 21498 generic: true, 21499 }, 21500 { 21501 name: "Rsh8Ux32", 21502 argLen: 2, 21503 generic: true, 21504 }, 21505 { 21506 name: "Rsh8Ux64", 21507 argLen: 2, 21508 generic: true, 21509 }, 21510 { 21511 name: "Rsh16Ux8", 21512 argLen: 2, 21513 generic: true, 21514 }, 21515 { 21516 name: "Rsh16Ux16", 21517 argLen: 2, 21518 generic: true, 21519 }, 21520 { 21521 name: "Rsh16Ux32", 21522 argLen: 2, 21523 generic: true, 21524 }, 21525 { 21526 name: "Rsh16Ux64", 21527 argLen: 2, 21528 generic: true, 21529 }, 21530 { 21531 name: "Rsh32Ux8", 21532 argLen: 2, 21533 generic: true, 21534 }, 21535 { 21536 name: "Rsh32Ux16", 21537 argLen: 2, 21538 generic: true, 21539 }, 21540 { 21541 name: "Rsh32Ux32", 21542 argLen: 2, 21543 generic: true, 21544 }, 21545 { 21546 name: "Rsh32Ux64", 21547 argLen: 2, 21548 generic: true, 21549 }, 21550 { 21551 name: "Rsh64Ux8", 21552 argLen: 2, 21553 generic: true, 21554 }, 21555 { 21556 name: "Rsh64Ux16", 21557 argLen: 2, 21558 generic: true, 21559 }, 21560 { 21561 name: "Rsh64Ux32", 21562 argLen: 2, 21563 generic: true, 21564 }, 21565 { 21566 name: "Rsh64Ux64", 21567 argLen: 2, 21568 generic: true, 21569 }, 21570 { 21571 name: "Eq8", 21572 argLen: 2, 21573 commutative: true, 21574 generic: true, 21575 }, 21576 { 21577 name: "Eq16", 21578 argLen: 2, 21579 commutative: true, 21580 generic: true, 21581 }, 21582 { 21583 name: "Eq32", 21584 argLen: 2, 21585 commutative: true, 21586 generic: true, 21587 }, 21588 { 21589 name: "Eq64", 21590 argLen: 2, 21591 commutative: true, 21592 generic: true, 21593 }, 21594 { 21595 name: "EqPtr", 21596 argLen: 2, 21597 commutative: true, 21598 generic: true, 21599 }, 21600 { 21601 name: "EqInter", 21602 argLen: 2, 21603 generic: true, 21604 }, 21605 { 21606 name: "EqSlice", 21607 argLen: 2, 21608 generic: true, 21609 }, 21610 { 21611 name: "Eq32F", 21612 argLen: 2, 21613 commutative: true, 21614 generic: true, 21615 }, 21616 { 21617 name: "Eq64F", 21618 argLen: 2, 21619 commutative: true, 21620 generic: true, 21621 }, 21622 { 21623 name: "Neq8", 21624 argLen: 2, 21625 commutative: true, 21626 generic: true, 21627 }, 21628 { 21629 name: "Neq16", 21630 argLen: 2, 21631 commutative: true, 21632 generic: true, 21633 }, 21634 { 21635 name: "Neq32", 21636 argLen: 2, 21637 commutative: true, 21638 generic: true, 21639 }, 21640 { 21641 name: "Neq64", 21642 argLen: 2, 21643 commutative: true, 21644 generic: true, 21645 }, 21646 { 21647 name: "NeqPtr", 21648 argLen: 2, 21649 commutative: true, 21650 generic: true, 21651 }, 21652 { 21653 name: "NeqInter", 21654 argLen: 2, 21655 generic: true, 21656 }, 21657 { 21658 name: "NeqSlice", 21659 argLen: 2, 21660 generic: true, 21661 }, 21662 { 21663 name: "Neq32F", 21664 argLen: 2, 21665 commutative: true, 21666 generic: true, 21667 }, 21668 { 21669 name: "Neq64F", 21670 argLen: 2, 21671 commutative: true, 21672 generic: true, 21673 }, 21674 { 21675 name: "Less8", 21676 argLen: 2, 21677 generic: true, 21678 }, 21679 { 21680 name: "Less8U", 21681 argLen: 2, 21682 generic: true, 21683 }, 21684 { 21685 name: "Less16", 21686 argLen: 2, 21687 generic: true, 21688 }, 21689 { 21690 name: "Less16U", 21691 argLen: 2, 21692 generic: true, 21693 }, 21694 { 21695 name: "Less32", 21696 argLen: 2, 21697 generic: true, 21698 }, 21699 { 21700 name: "Less32U", 21701 argLen: 2, 21702 generic: true, 21703 }, 21704 { 21705 name: "Less64", 21706 argLen: 2, 21707 generic: true, 21708 }, 21709 { 21710 name: "Less64U", 21711 argLen: 2, 21712 generic: true, 21713 }, 21714 { 21715 name: "Less32F", 21716 argLen: 2, 21717 generic: true, 21718 }, 21719 { 21720 name: "Less64F", 21721 argLen: 2, 21722 generic: true, 21723 }, 21724 { 21725 name: "Leq8", 21726 argLen: 2, 21727 generic: true, 21728 }, 21729 { 21730 name: "Leq8U", 21731 argLen: 2, 21732 generic: true, 21733 }, 21734 { 21735 name: "Leq16", 21736 argLen: 2, 21737 generic: true, 21738 }, 21739 { 21740 name: "Leq16U", 21741 argLen: 2, 21742 generic: true, 21743 }, 21744 { 21745 name: "Leq32", 21746 argLen: 2, 21747 generic: true, 21748 }, 21749 { 21750 name: "Leq32U", 21751 argLen: 2, 21752 generic: true, 21753 }, 21754 { 21755 name: "Leq64", 21756 argLen: 2, 21757 generic: true, 21758 }, 21759 { 21760 name: "Leq64U", 21761 argLen: 2, 21762 generic: true, 21763 }, 21764 { 21765 name: "Leq32F", 21766 argLen: 2, 21767 generic: true, 21768 }, 21769 { 21770 name: "Leq64F", 21771 argLen: 2, 21772 generic: true, 21773 }, 21774 { 21775 name: "Greater8", 21776 argLen: 2, 21777 generic: true, 21778 }, 21779 { 21780 name: "Greater8U", 21781 argLen: 2, 21782 generic: true, 21783 }, 21784 { 21785 name: "Greater16", 21786 argLen: 2, 21787 generic: true, 21788 }, 21789 { 21790 name: "Greater16U", 21791 argLen: 2, 21792 generic: true, 21793 }, 21794 { 21795 name: "Greater32", 21796 argLen: 2, 21797 generic: true, 21798 }, 21799 { 21800 name: "Greater32U", 21801 argLen: 2, 21802 generic: true, 21803 }, 21804 { 21805 name: "Greater64", 21806 argLen: 2, 21807 generic: true, 21808 }, 21809 { 21810 name: "Greater64U", 21811 argLen: 2, 21812 generic: true, 21813 }, 21814 { 21815 name: "Greater32F", 21816 argLen: 2, 21817 generic: true, 21818 }, 21819 { 21820 name: "Greater64F", 21821 argLen: 2, 21822 generic: true, 21823 }, 21824 { 21825 name: "Geq8", 21826 argLen: 2, 21827 generic: true, 21828 }, 21829 { 21830 name: "Geq8U", 21831 argLen: 2, 21832 generic: true, 21833 }, 21834 { 21835 name: "Geq16", 21836 argLen: 2, 21837 generic: true, 21838 }, 21839 { 21840 name: "Geq16U", 21841 argLen: 2, 21842 generic: true, 21843 }, 21844 { 21845 name: "Geq32", 21846 argLen: 2, 21847 generic: true, 21848 }, 21849 { 21850 name: "Geq32U", 21851 argLen: 2, 21852 generic: true, 21853 }, 21854 { 21855 name: "Geq64", 21856 argLen: 2, 21857 generic: true, 21858 }, 21859 { 21860 name: "Geq64U", 21861 argLen: 2, 21862 generic: true, 21863 }, 21864 { 21865 name: "Geq32F", 21866 argLen: 2, 21867 generic: true, 21868 }, 21869 { 21870 name: "Geq64F", 21871 argLen: 2, 21872 generic: true, 21873 }, 21874 { 21875 name: "AndB", 21876 argLen: 2, 21877 commutative: true, 21878 generic: true, 21879 }, 21880 { 21881 name: "OrB", 21882 argLen: 2, 21883 commutative: true, 21884 generic: true, 21885 }, 21886 { 21887 name: "EqB", 21888 argLen: 2, 21889 commutative: true, 21890 generic: true, 21891 }, 21892 { 21893 name: "NeqB", 21894 argLen: 2, 21895 commutative: true, 21896 generic: true, 21897 }, 21898 { 21899 name: "Not", 21900 argLen: 1, 21901 generic: true, 21902 }, 21903 { 21904 name: "Neg8", 21905 argLen: 1, 21906 generic: true, 21907 }, 21908 { 21909 name: "Neg16", 21910 argLen: 1, 21911 generic: true, 21912 }, 21913 { 21914 name: "Neg32", 21915 argLen: 1, 21916 generic: true, 21917 }, 21918 { 21919 name: "Neg64", 21920 argLen: 1, 21921 generic: true, 21922 }, 21923 { 21924 name: "Neg32F", 21925 argLen: 1, 21926 generic: true, 21927 }, 21928 { 21929 name: "Neg64F", 21930 argLen: 1, 21931 generic: true, 21932 }, 21933 { 21934 name: "Com8", 21935 argLen: 1, 21936 generic: true, 21937 }, 21938 { 21939 name: "Com16", 21940 argLen: 1, 21941 generic: true, 21942 }, 21943 { 21944 name: "Com32", 21945 argLen: 1, 21946 generic: true, 21947 }, 21948 { 21949 name: "Com64", 21950 argLen: 1, 21951 generic: true, 21952 }, 21953 { 21954 name: "Ctz32", 21955 argLen: 1, 21956 generic: true, 21957 }, 21958 { 21959 name: "Ctz64", 21960 argLen: 1, 21961 generic: true, 21962 }, 21963 { 21964 name: "BitLen32", 21965 argLen: 1, 21966 generic: true, 21967 }, 21968 { 21969 name: "BitLen64", 21970 argLen: 1, 21971 generic: true, 21972 }, 21973 { 21974 name: "Bswap32", 21975 argLen: 1, 21976 generic: true, 21977 }, 21978 { 21979 name: "Bswap64", 21980 argLen: 1, 21981 generic: true, 21982 }, 21983 { 21984 name: "BitRev8", 21985 argLen: 1, 21986 generic: true, 21987 }, 21988 { 21989 name: "BitRev16", 21990 argLen: 1, 21991 generic: true, 21992 }, 21993 { 21994 name: "BitRev32", 21995 argLen: 1, 21996 generic: true, 21997 }, 21998 { 21999 name: "BitRev64", 22000 argLen: 1, 22001 generic: true, 22002 }, 22003 { 22004 name: "PopCount8", 22005 argLen: 1, 22006 generic: true, 22007 }, 22008 { 22009 name: "PopCount16", 22010 argLen: 1, 22011 generic: true, 22012 }, 22013 { 22014 name: "PopCount32", 22015 argLen: 1, 22016 generic: true, 22017 }, 22018 { 22019 name: "PopCount64", 22020 argLen: 1, 22021 generic: true, 22022 }, 22023 { 22024 name: "Sqrt", 22025 argLen: 1, 22026 generic: true, 22027 }, 22028 { 22029 name: "Floor", 22030 argLen: 1, 22031 generic: true, 22032 }, 22033 { 22034 name: "Ceil", 22035 argLen: 1, 22036 generic: true, 22037 }, 22038 { 22039 name: "Trunc", 22040 argLen: 1, 22041 generic: true, 22042 }, 22043 { 22044 name: "Phi", 22045 argLen: -1, 22046 generic: true, 22047 }, 22048 { 22049 name: "Copy", 22050 argLen: 1, 22051 generic: true, 22052 }, 22053 { 22054 name: "Convert", 22055 argLen: 2, 22056 generic: true, 22057 }, 22058 { 22059 name: "ConstBool", 22060 auxType: auxBool, 22061 argLen: 0, 22062 generic: true, 22063 }, 22064 { 22065 name: "ConstString", 22066 auxType: auxString, 22067 argLen: 0, 22068 generic: true, 22069 }, 22070 { 22071 name: "ConstNil", 22072 argLen: 0, 22073 generic: true, 22074 }, 22075 { 22076 name: "Const8", 22077 auxType: auxInt8, 22078 argLen: 0, 22079 generic: true, 22080 }, 22081 { 22082 name: "Const16", 22083 auxType: auxInt16, 22084 argLen: 0, 22085 generic: true, 22086 }, 22087 { 22088 name: "Const32", 22089 auxType: auxInt32, 22090 argLen: 0, 22091 generic: true, 22092 }, 22093 { 22094 name: "Const64", 22095 auxType: auxInt64, 22096 argLen: 0, 22097 generic: true, 22098 }, 22099 { 22100 name: "Const32F", 22101 auxType: auxFloat32, 22102 argLen: 0, 22103 generic: true, 22104 }, 22105 { 22106 name: "Const64F", 22107 auxType: auxFloat64, 22108 argLen: 0, 22109 generic: true, 22110 }, 22111 { 22112 name: "ConstInterface", 22113 argLen: 0, 22114 generic: true, 22115 }, 22116 { 22117 name: "ConstSlice", 22118 argLen: 0, 22119 generic: true, 22120 }, 22121 { 22122 name: "InitMem", 22123 argLen: 0, 22124 generic: true, 22125 }, 22126 { 22127 name: "Arg", 22128 auxType: auxSymOff, 22129 argLen: 0, 22130 symEffect: SymNone, 22131 generic: true, 22132 }, 22133 { 22134 name: "Addr", 22135 auxType: auxSym, 22136 argLen: 1, 22137 symEffect: SymAddr, 22138 generic: true, 22139 }, 22140 { 22141 name: "SP", 22142 argLen: 0, 22143 generic: true, 22144 }, 22145 { 22146 name: "SB", 22147 argLen: 0, 22148 generic: true, 22149 }, 22150 { 22151 name: "Load", 22152 argLen: 2, 22153 generic: true, 22154 }, 22155 { 22156 name: "Store", 22157 auxType: auxTyp, 22158 argLen: 3, 22159 generic: true, 22160 }, 22161 { 22162 name: "Move", 22163 auxType: auxTypSize, 22164 argLen: 3, 22165 generic: true, 22166 }, 22167 { 22168 name: "Zero", 22169 auxType: auxTypSize, 22170 argLen: 2, 22171 generic: true, 22172 }, 22173 { 22174 name: "StoreWB", 22175 auxType: auxTyp, 22176 argLen: 3, 22177 generic: true, 22178 }, 22179 { 22180 name: "MoveWB", 22181 auxType: auxTypSize, 22182 argLen: 3, 22183 generic: true, 22184 }, 22185 { 22186 name: "ZeroWB", 22187 auxType: auxTypSize, 22188 argLen: 2, 22189 generic: true, 22190 }, 22191 { 22192 name: "ClosureCall", 22193 auxType: auxInt64, 22194 argLen: 3, 22195 call: true, 22196 generic: true, 22197 }, 22198 { 22199 name: "StaticCall", 22200 auxType: auxSymOff, 22201 argLen: 1, 22202 call: true, 22203 symEffect: SymNone, 22204 generic: true, 22205 }, 22206 { 22207 name: "InterCall", 22208 auxType: auxInt64, 22209 argLen: 2, 22210 call: true, 22211 generic: true, 22212 }, 22213 { 22214 name: "SignExt8to16", 22215 argLen: 1, 22216 generic: true, 22217 }, 22218 { 22219 name: "SignExt8to32", 22220 argLen: 1, 22221 generic: true, 22222 }, 22223 { 22224 name: "SignExt8to64", 22225 argLen: 1, 22226 generic: true, 22227 }, 22228 { 22229 name: "SignExt16to32", 22230 argLen: 1, 22231 generic: true, 22232 }, 22233 { 22234 name: "SignExt16to64", 22235 argLen: 1, 22236 generic: true, 22237 }, 22238 { 22239 name: "SignExt32to64", 22240 argLen: 1, 22241 generic: true, 22242 }, 22243 { 22244 name: "ZeroExt8to16", 22245 argLen: 1, 22246 generic: true, 22247 }, 22248 { 22249 name: "ZeroExt8to32", 22250 argLen: 1, 22251 generic: true, 22252 }, 22253 { 22254 name: "ZeroExt8to64", 22255 argLen: 1, 22256 generic: true, 22257 }, 22258 { 22259 name: "ZeroExt16to32", 22260 argLen: 1, 22261 generic: true, 22262 }, 22263 { 22264 name: "ZeroExt16to64", 22265 argLen: 1, 22266 generic: true, 22267 }, 22268 { 22269 name: "ZeroExt32to64", 22270 argLen: 1, 22271 generic: true, 22272 }, 22273 { 22274 name: "Trunc16to8", 22275 argLen: 1, 22276 generic: true, 22277 }, 22278 { 22279 name: "Trunc32to8", 22280 argLen: 1, 22281 generic: true, 22282 }, 22283 { 22284 name: "Trunc32to16", 22285 argLen: 1, 22286 generic: true, 22287 }, 22288 { 22289 name: "Trunc64to8", 22290 argLen: 1, 22291 generic: true, 22292 }, 22293 { 22294 name: "Trunc64to16", 22295 argLen: 1, 22296 generic: true, 22297 }, 22298 { 22299 name: "Trunc64to32", 22300 argLen: 1, 22301 generic: true, 22302 }, 22303 { 22304 name: "Cvt32to32F", 22305 argLen: 1, 22306 generic: true, 22307 }, 22308 { 22309 name: "Cvt32to64F", 22310 argLen: 1, 22311 generic: true, 22312 }, 22313 { 22314 name: "Cvt64to32F", 22315 argLen: 1, 22316 generic: true, 22317 }, 22318 { 22319 name: "Cvt64to64F", 22320 argLen: 1, 22321 generic: true, 22322 }, 22323 { 22324 name: "Cvt32Fto32", 22325 argLen: 1, 22326 generic: true, 22327 }, 22328 { 22329 name: "Cvt32Fto64", 22330 argLen: 1, 22331 generic: true, 22332 }, 22333 { 22334 name: "Cvt64Fto32", 22335 argLen: 1, 22336 generic: true, 22337 }, 22338 { 22339 name: "Cvt64Fto64", 22340 argLen: 1, 22341 generic: true, 22342 }, 22343 { 22344 name: "Cvt32Fto64F", 22345 argLen: 1, 22346 generic: true, 22347 }, 22348 { 22349 name: "Cvt64Fto32F", 22350 argLen: 1, 22351 generic: true, 22352 }, 22353 { 22354 name: "Round32F", 22355 argLen: 1, 22356 generic: true, 22357 }, 22358 { 22359 name: "Round64F", 22360 argLen: 1, 22361 generic: true, 22362 }, 22363 { 22364 name: "IsNonNil", 22365 argLen: 1, 22366 generic: true, 22367 }, 22368 { 22369 name: "IsInBounds", 22370 argLen: 2, 22371 generic: true, 22372 }, 22373 { 22374 name: "IsSliceInBounds", 22375 argLen: 2, 22376 generic: true, 22377 }, 22378 { 22379 name: "NilCheck", 22380 argLen: 2, 22381 generic: true, 22382 }, 22383 { 22384 name: "GetG", 22385 argLen: 1, 22386 generic: true, 22387 }, 22388 { 22389 name: "GetClosurePtr", 22390 argLen: 0, 22391 generic: true, 22392 }, 22393 { 22394 name: "PtrIndex", 22395 argLen: 2, 22396 generic: true, 22397 }, 22398 { 22399 name: "OffPtr", 22400 auxType: auxInt64, 22401 argLen: 1, 22402 generic: true, 22403 }, 22404 { 22405 name: "SliceMake", 22406 argLen: 3, 22407 generic: true, 22408 }, 22409 { 22410 name: "SlicePtr", 22411 argLen: 1, 22412 generic: true, 22413 }, 22414 { 22415 name: "SliceLen", 22416 argLen: 1, 22417 generic: true, 22418 }, 22419 { 22420 name: "SliceCap", 22421 argLen: 1, 22422 generic: true, 22423 }, 22424 { 22425 name: "ComplexMake", 22426 argLen: 2, 22427 generic: true, 22428 }, 22429 { 22430 name: "ComplexReal", 22431 argLen: 1, 22432 generic: true, 22433 }, 22434 { 22435 name: "ComplexImag", 22436 argLen: 1, 22437 generic: true, 22438 }, 22439 { 22440 name: "StringMake", 22441 argLen: 2, 22442 generic: true, 22443 }, 22444 { 22445 name: "StringPtr", 22446 argLen: 1, 22447 generic: true, 22448 }, 22449 { 22450 name: "StringLen", 22451 argLen: 1, 22452 generic: true, 22453 }, 22454 { 22455 name: "IMake", 22456 argLen: 2, 22457 generic: true, 22458 }, 22459 { 22460 name: "ITab", 22461 argLen: 1, 22462 generic: true, 22463 }, 22464 { 22465 name: "IData", 22466 argLen: 1, 22467 generic: true, 22468 }, 22469 { 22470 name: "StructMake0", 22471 argLen: 0, 22472 generic: true, 22473 }, 22474 { 22475 name: "StructMake1", 22476 argLen: 1, 22477 generic: true, 22478 }, 22479 { 22480 name: "StructMake2", 22481 argLen: 2, 22482 generic: true, 22483 }, 22484 { 22485 name: "StructMake3", 22486 argLen: 3, 22487 generic: true, 22488 }, 22489 { 22490 name: "StructMake4", 22491 argLen: 4, 22492 generic: true, 22493 }, 22494 { 22495 name: "StructSelect", 22496 auxType: auxInt64, 22497 argLen: 1, 22498 generic: true, 22499 }, 22500 { 22501 name: "ArrayMake0", 22502 argLen: 0, 22503 generic: true, 22504 }, 22505 { 22506 name: "ArrayMake1", 22507 argLen: 1, 22508 generic: true, 22509 }, 22510 { 22511 name: "ArraySelect", 22512 auxType: auxInt64, 22513 argLen: 1, 22514 generic: true, 22515 }, 22516 { 22517 name: "StoreReg", 22518 argLen: 1, 22519 generic: true, 22520 }, 22521 { 22522 name: "LoadReg", 22523 argLen: 1, 22524 generic: true, 22525 }, 22526 { 22527 name: "FwdRef", 22528 auxType: auxSym, 22529 argLen: 0, 22530 symEffect: SymNone, 22531 generic: true, 22532 }, 22533 { 22534 name: "Unknown", 22535 argLen: 0, 22536 generic: true, 22537 }, 22538 { 22539 name: "VarDef", 22540 auxType: auxSym, 22541 argLen: 1, 22542 symEffect: SymNone, 22543 generic: true, 22544 }, 22545 { 22546 name: "VarKill", 22547 auxType: auxSym, 22548 argLen: 1, 22549 symEffect: SymNone, 22550 generic: true, 22551 }, 22552 { 22553 name: "VarLive", 22554 auxType: auxSym, 22555 argLen: 1, 22556 symEffect: SymNone, 22557 generic: true, 22558 }, 22559 { 22560 name: "KeepAlive", 22561 argLen: 2, 22562 generic: true, 22563 }, 22564 { 22565 name: "RegKill", 22566 argLen: 0, 22567 generic: true, 22568 }, 22569 { 22570 name: "Int64Make", 22571 argLen: 2, 22572 generic: true, 22573 }, 22574 { 22575 name: "Int64Hi", 22576 argLen: 1, 22577 generic: true, 22578 }, 22579 { 22580 name: "Int64Lo", 22581 argLen: 1, 22582 generic: true, 22583 }, 22584 { 22585 name: "Add32carry", 22586 argLen: 2, 22587 commutative: true, 22588 generic: true, 22589 }, 22590 { 22591 name: "Add32withcarry", 22592 argLen: 3, 22593 commutative: true, 22594 generic: true, 22595 }, 22596 { 22597 name: "Sub32carry", 22598 argLen: 2, 22599 generic: true, 22600 }, 22601 { 22602 name: "Sub32withcarry", 22603 argLen: 3, 22604 generic: true, 22605 }, 22606 { 22607 name: "Signmask", 22608 argLen: 1, 22609 generic: true, 22610 }, 22611 { 22612 name: "Zeromask", 22613 argLen: 1, 22614 generic: true, 22615 }, 22616 { 22617 name: "Slicemask", 22618 argLen: 1, 22619 generic: true, 22620 }, 22621 { 22622 name: "Cvt32Uto32F", 22623 argLen: 1, 22624 generic: true, 22625 }, 22626 { 22627 name: "Cvt32Uto64F", 22628 argLen: 1, 22629 generic: true, 22630 }, 22631 { 22632 name: "Cvt32Fto32U", 22633 argLen: 1, 22634 generic: true, 22635 }, 22636 { 22637 name: "Cvt64Fto32U", 22638 argLen: 1, 22639 generic: true, 22640 }, 22641 { 22642 name: "Cvt64Uto32F", 22643 argLen: 1, 22644 generic: true, 22645 }, 22646 { 22647 name: "Cvt64Uto64F", 22648 argLen: 1, 22649 generic: true, 22650 }, 22651 { 22652 name: "Cvt32Fto64U", 22653 argLen: 1, 22654 generic: true, 22655 }, 22656 { 22657 name: "Cvt64Fto64U", 22658 argLen: 1, 22659 generic: true, 22660 }, 22661 { 22662 name: "Select0", 22663 argLen: 1, 22664 generic: true, 22665 }, 22666 { 22667 name: "Select1", 22668 argLen: 1, 22669 generic: true, 22670 }, 22671 { 22672 name: "AtomicLoad32", 22673 argLen: 2, 22674 generic: true, 22675 }, 22676 { 22677 name: "AtomicLoad64", 22678 argLen: 2, 22679 generic: true, 22680 }, 22681 { 22682 name: "AtomicLoadPtr", 22683 argLen: 2, 22684 generic: true, 22685 }, 22686 { 22687 name: "AtomicStore32", 22688 argLen: 3, 22689 hasSideEffects: true, 22690 generic: true, 22691 }, 22692 { 22693 name: "AtomicStore64", 22694 argLen: 3, 22695 hasSideEffects: true, 22696 generic: true, 22697 }, 22698 { 22699 name: "AtomicStorePtrNoWB", 22700 argLen: 3, 22701 hasSideEffects: true, 22702 generic: true, 22703 }, 22704 { 22705 name: "AtomicExchange32", 22706 argLen: 3, 22707 hasSideEffects: true, 22708 generic: true, 22709 }, 22710 { 22711 name: "AtomicExchange64", 22712 argLen: 3, 22713 hasSideEffects: true, 22714 generic: true, 22715 }, 22716 { 22717 name: "AtomicAdd32", 22718 argLen: 3, 22719 hasSideEffects: true, 22720 generic: true, 22721 }, 22722 { 22723 name: "AtomicAdd64", 22724 argLen: 3, 22725 hasSideEffects: true, 22726 generic: true, 22727 }, 22728 { 22729 name: "AtomicCompareAndSwap32", 22730 argLen: 4, 22731 hasSideEffects: true, 22732 generic: true, 22733 }, 22734 { 22735 name: "AtomicCompareAndSwap64", 22736 argLen: 4, 22737 hasSideEffects: true, 22738 generic: true, 22739 }, 22740 { 22741 name: "AtomicAnd8", 22742 argLen: 3, 22743 hasSideEffects: true, 22744 generic: true, 22745 }, 22746 { 22747 name: "AtomicOr8", 22748 argLen: 3, 22749 hasSideEffects: true, 22750 generic: true, 22751 }, 22752 { 22753 name: "Clobber", 22754 auxType: auxSymOff, 22755 argLen: 0, 22756 symEffect: SymNone, 22757 generic: true, 22758 }, 22759 } 22760 22761 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 22762 func (o Op) String() string { return opcodeTable[o].name } 22763 func (o Op) UsesScratch() bool { return opcodeTable[o].usesScratch } 22764 func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect } 22765 func (o Op) IsCall() bool { return opcodeTable[o].call } 22766 22767 var registers386 = [...]Register{ 22768 {0, x86.REG_AX, "AX"}, 22769 {1, x86.REG_CX, "CX"}, 22770 {2, x86.REG_DX, "DX"}, 22771 {3, x86.REG_BX, "BX"}, 22772 {4, x86.REGSP, "SP"}, 22773 {5, x86.REG_BP, "BP"}, 22774 {6, x86.REG_SI, "SI"}, 22775 {7, x86.REG_DI, "DI"}, 22776 {8, x86.REG_X0, "X0"}, 22777 {9, x86.REG_X1, "X1"}, 22778 {10, x86.REG_X2, "X2"}, 22779 {11, x86.REG_X3, "X3"}, 22780 {12, x86.REG_X4, "X4"}, 22781 {13, x86.REG_X5, "X5"}, 22782 {14, x86.REG_X6, "X6"}, 22783 {15, x86.REG_X7, "X7"}, 22784 {16, 0, "SB"}, 22785 } 22786 var gpRegMask386 = regMask(239) 22787 var fpRegMask386 = regMask(65280) 22788 var specialRegMask386 = regMask(0) 22789 var framepointerReg386 = int8(5) 22790 var linkReg386 = int8(-1) 22791 var registersAMD64 = [...]Register{ 22792 {0, x86.REG_AX, "AX"}, 22793 {1, x86.REG_CX, "CX"}, 22794 {2, x86.REG_DX, "DX"}, 22795 {3, x86.REG_BX, "BX"}, 22796 {4, x86.REGSP, "SP"}, 22797 {5, x86.REG_BP, "BP"}, 22798 {6, x86.REG_SI, "SI"}, 22799 {7, x86.REG_DI, "DI"}, 22800 {8, x86.REG_R8, "R8"}, 22801 {9, x86.REG_R9, "R9"}, 22802 {10, x86.REG_R10, "R10"}, 22803 {11, x86.REG_R11, "R11"}, 22804 {12, x86.REG_R12, "R12"}, 22805 {13, x86.REG_R13, "R13"}, 22806 {14, x86.REG_R14, "R14"}, 22807 {15, x86.REG_R15, "R15"}, 22808 {16, x86.REG_X0, "X0"}, 22809 {17, x86.REG_X1, "X1"}, 22810 {18, x86.REG_X2, "X2"}, 22811 {19, x86.REG_X3, "X3"}, 22812 {20, x86.REG_X4, "X4"}, 22813 {21, x86.REG_X5, "X5"}, 22814 {22, x86.REG_X6, "X6"}, 22815 {23, x86.REG_X7, "X7"}, 22816 {24, x86.REG_X8, "X8"}, 22817 {25, x86.REG_X9, "X9"}, 22818 {26, x86.REG_X10, "X10"}, 22819 {27, x86.REG_X11, "X11"}, 22820 {28, x86.REG_X12, "X12"}, 22821 {29, x86.REG_X13, "X13"}, 22822 {30, x86.REG_X14, "X14"}, 22823 {31, x86.REG_X15, "X15"}, 22824 {32, 0, "SB"}, 22825 } 22826 var gpRegMaskAMD64 = regMask(65519) 22827 var fpRegMaskAMD64 = regMask(4294901760) 22828 var specialRegMaskAMD64 = regMask(0) 22829 var framepointerRegAMD64 = int8(5) 22830 var linkRegAMD64 = int8(-1) 22831 var registersARM = [...]Register{ 22832 {0, arm.REG_R0, "R0"}, 22833 {1, arm.REG_R1, "R1"}, 22834 {2, arm.REG_R2, "R2"}, 22835 {3, arm.REG_R3, "R3"}, 22836 {4, arm.REG_R4, "R4"}, 22837 {5, arm.REG_R5, "R5"}, 22838 {6, arm.REG_R6, "R6"}, 22839 {7, arm.REG_R7, "R7"}, 22840 {8, arm.REG_R8, "R8"}, 22841 {9, arm.REG_R9, "R9"}, 22842 {10, arm.REGG, "g"}, 22843 {11, arm.REG_R11, "R11"}, 22844 {12, arm.REG_R12, "R12"}, 22845 {13, arm.REGSP, "SP"}, 22846 {14, arm.REG_R14, "R14"}, 22847 {15, arm.REG_R15, "R15"}, 22848 {16, arm.REG_F0, "F0"}, 22849 {17, arm.REG_F1, "F1"}, 22850 {18, arm.REG_F2, "F2"}, 22851 {19, arm.REG_F3, "F3"}, 22852 {20, arm.REG_F4, "F4"}, 22853 {21, arm.REG_F5, "F5"}, 22854 {22, arm.REG_F6, "F6"}, 22855 {23, arm.REG_F7, "F7"}, 22856 {24, arm.REG_F8, "F8"}, 22857 {25, arm.REG_F9, "F9"}, 22858 {26, arm.REG_F10, "F10"}, 22859 {27, arm.REG_F11, "F11"}, 22860 {28, arm.REG_F12, "F12"}, 22861 {29, arm.REG_F13, "F13"}, 22862 {30, arm.REG_F14, "F14"}, 22863 {31, arm.REG_F15, "F15"}, 22864 {32, 0, "SB"}, 22865 } 22866 var gpRegMaskARM = regMask(21503) 22867 var fpRegMaskARM = regMask(4294901760) 22868 var specialRegMaskARM = regMask(0) 22869 var framepointerRegARM = int8(-1) 22870 var linkRegARM = int8(14) 22871 var registersARM64 = [...]Register{ 22872 {0, arm64.REG_R0, "R0"}, 22873 {1, arm64.REG_R1, "R1"}, 22874 {2, arm64.REG_R2, "R2"}, 22875 {3, arm64.REG_R3, "R3"}, 22876 {4, arm64.REG_R4, "R4"}, 22877 {5, arm64.REG_R5, "R5"}, 22878 {6, arm64.REG_R6, "R6"}, 22879 {7, arm64.REG_R7, "R7"}, 22880 {8, arm64.REG_R8, "R8"}, 22881 {9, arm64.REG_R9, "R9"}, 22882 {10, arm64.REG_R10, "R10"}, 22883 {11, arm64.REG_R11, "R11"}, 22884 {12, arm64.REG_R12, "R12"}, 22885 {13, arm64.REG_R13, "R13"}, 22886 {14, arm64.REG_R14, "R14"}, 22887 {15, arm64.REG_R15, "R15"}, 22888 {16, arm64.REG_R16, "R16"}, 22889 {17, arm64.REG_R17, "R17"}, 22890 {18, arm64.REG_R18, "R18"}, 22891 {19, arm64.REG_R19, "R19"}, 22892 {20, arm64.REG_R20, "R20"}, 22893 {21, arm64.REG_R21, "R21"}, 22894 {22, arm64.REG_R22, "R22"}, 22895 {23, arm64.REG_R23, "R23"}, 22896 {24, arm64.REG_R24, "R24"}, 22897 {25, arm64.REG_R25, "R25"}, 22898 {26, arm64.REG_R26, "R26"}, 22899 {27, arm64.REGG, "g"}, 22900 {28, arm64.REG_R29, "R29"}, 22901 {29, arm64.REG_R30, "R30"}, 22902 {30, arm64.REGSP, "SP"}, 22903 {31, arm64.REG_F0, "F0"}, 22904 {32, arm64.REG_F1, "F1"}, 22905 {33, arm64.REG_F2, "F2"}, 22906 {34, arm64.REG_F3, "F3"}, 22907 {35, arm64.REG_F4, "F4"}, 22908 {36, arm64.REG_F5, "F5"}, 22909 {37, arm64.REG_F6, "F6"}, 22910 {38, arm64.REG_F7, "F7"}, 22911 {39, arm64.REG_F8, "F8"}, 22912 {40, arm64.REG_F9, "F9"}, 22913 {41, arm64.REG_F10, "F10"}, 22914 {42, arm64.REG_F11, "F11"}, 22915 {43, arm64.REG_F12, "F12"}, 22916 {44, arm64.REG_F13, "F13"}, 22917 {45, arm64.REG_F14, "F14"}, 22918 {46, arm64.REG_F15, "F15"}, 22919 {47, arm64.REG_F16, "F16"}, 22920 {48, arm64.REG_F17, "F17"}, 22921 {49, arm64.REG_F18, "F18"}, 22922 {50, arm64.REG_F19, "F19"}, 22923 {51, arm64.REG_F20, "F20"}, 22924 {52, arm64.REG_F21, "F21"}, 22925 {53, arm64.REG_F22, "F22"}, 22926 {54, arm64.REG_F23, "F23"}, 22927 {55, arm64.REG_F24, "F24"}, 22928 {56, arm64.REG_F25, "F25"}, 22929 {57, arm64.REG_F26, "F26"}, 22930 {58, arm64.REG_F27, "F27"}, 22931 {59, arm64.REG_F28, "F28"}, 22932 {60, arm64.REG_F29, "F29"}, 22933 {61, arm64.REG_F30, "F30"}, 22934 {62, arm64.REG_F31, "F31"}, 22935 {63, 0, "SB"}, 22936 } 22937 var gpRegMaskARM64 = regMask(670826495) 22938 var fpRegMaskARM64 = regMask(9223372034707292160) 22939 var specialRegMaskARM64 = regMask(0) 22940 var framepointerRegARM64 = int8(-1) 22941 var linkRegARM64 = int8(29) 22942 var registersMIPS = [...]Register{ 22943 {0, mips.REG_R0, "R0"}, 22944 {1, mips.REG_R1, "R1"}, 22945 {2, mips.REG_R2, "R2"}, 22946 {3, mips.REG_R3, "R3"}, 22947 {4, mips.REG_R4, "R4"}, 22948 {5, mips.REG_R5, "R5"}, 22949 {6, mips.REG_R6, "R6"}, 22950 {7, mips.REG_R7, "R7"}, 22951 {8, mips.REG_R8, "R8"}, 22952 {9, mips.REG_R9, "R9"}, 22953 {10, mips.REG_R10, "R10"}, 22954 {11, mips.REG_R11, "R11"}, 22955 {12, mips.REG_R12, "R12"}, 22956 {13, mips.REG_R13, "R13"}, 22957 {14, mips.REG_R14, "R14"}, 22958 {15, mips.REG_R15, "R15"}, 22959 {16, mips.REG_R16, "R16"}, 22960 {17, mips.REG_R17, "R17"}, 22961 {18, mips.REG_R18, "R18"}, 22962 {19, mips.REG_R19, "R19"}, 22963 {20, mips.REG_R20, "R20"}, 22964 {21, mips.REG_R21, "R21"}, 22965 {22, mips.REG_R22, "R22"}, 22966 {23, mips.REG_R24, "R24"}, 22967 {24, mips.REG_R25, "R25"}, 22968 {25, mips.REG_R28, "R28"}, 22969 {26, mips.REGSP, "SP"}, 22970 {27, mips.REGG, "g"}, 22971 {28, mips.REG_R31, "R31"}, 22972 {29, mips.REG_F0, "F0"}, 22973 {30, mips.REG_F2, "F2"}, 22974 {31, mips.REG_F4, "F4"}, 22975 {32, mips.REG_F6, "F6"}, 22976 {33, mips.REG_F8, "F8"}, 22977 {34, mips.REG_F10, "F10"}, 22978 {35, mips.REG_F12, "F12"}, 22979 {36, mips.REG_F14, "F14"}, 22980 {37, mips.REG_F16, "F16"}, 22981 {38, mips.REG_F18, "F18"}, 22982 {39, mips.REG_F20, "F20"}, 22983 {40, mips.REG_F22, "F22"}, 22984 {41, mips.REG_F24, "F24"}, 22985 {42, mips.REG_F26, "F26"}, 22986 {43, mips.REG_F28, "F28"}, 22987 {44, mips.REG_F30, "F30"}, 22988 {45, mips.REG_HI, "HI"}, 22989 {46, mips.REG_LO, "LO"}, 22990 {47, 0, "SB"}, 22991 } 22992 var gpRegMaskMIPS = regMask(335544318) 22993 var fpRegMaskMIPS = regMask(35183835217920) 22994 var specialRegMaskMIPS = regMask(105553116266496) 22995 var framepointerRegMIPS = int8(-1) 22996 var linkRegMIPS = int8(28) 22997 var registersMIPS64 = [...]Register{ 22998 {0, mips.REG_R0, "R0"}, 22999 {1, mips.REG_R1, "R1"}, 23000 {2, mips.REG_R2, "R2"}, 23001 {3, mips.REG_R3, "R3"}, 23002 {4, mips.REG_R4, "R4"}, 23003 {5, mips.REG_R5, "R5"}, 23004 {6, mips.REG_R6, "R6"}, 23005 {7, mips.REG_R7, "R7"}, 23006 {8, mips.REG_R8, "R8"}, 23007 {9, mips.REG_R9, "R9"}, 23008 {10, mips.REG_R10, "R10"}, 23009 {11, mips.REG_R11, "R11"}, 23010 {12, mips.REG_R12, "R12"}, 23011 {13, mips.REG_R13, "R13"}, 23012 {14, mips.REG_R14, "R14"}, 23013 {15, mips.REG_R15, "R15"}, 23014 {16, mips.REG_R16, "R16"}, 23015 {17, mips.REG_R17, "R17"}, 23016 {18, mips.REG_R18, "R18"}, 23017 {19, mips.REG_R19, "R19"}, 23018 {20, mips.REG_R20, "R20"}, 23019 {21, mips.REG_R21, "R21"}, 23020 {22, mips.REG_R22, "R22"}, 23021 {23, mips.REG_R24, "R24"}, 23022 {24, mips.REG_R25, "R25"}, 23023 {25, mips.REGSP, "SP"}, 23024 {26, mips.REGG, "g"}, 23025 {27, mips.REG_R31, "R31"}, 23026 {28, mips.REG_F0, "F0"}, 23027 {29, mips.REG_F1, "F1"}, 23028 {30, mips.REG_F2, "F2"}, 23029 {31, mips.REG_F3, "F3"}, 23030 {32, mips.REG_F4, "F4"}, 23031 {33, mips.REG_F5, "F5"}, 23032 {34, mips.REG_F6, "F6"}, 23033 {35, mips.REG_F7, "F7"}, 23034 {36, mips.REG_F8, "F8"}, 23035 {37, mips.REG_F9, "F9"}, 23036 {38, mips.REG_F10, "F10"}, 23037 {39, mips.REG_F11, "F11"}, 23038 {40, mips.REG_F12, "F12"}, 23039 {41, mips.REG_F13, "F13"}, 23040 {42, mips.REG_F14, "F14"}, 23041 {43, mips.REG_F15, "F15"}, 23042 {44, mips.REG_F16, "F16"}, 23043 {45, mips.REG_F17, "F17"}, 23044 {46, mips.REG_F18, "F18"}, 23045 {47, mips.REG_F19, "F19"}, 23046 {48, mips.REG_F20, "F20"}, 23047 {49, mips.REG_F21, "F21"}, 23048 {50, mips.REG_F22, "F22"}, 23049 {51, mips.REG_F23, "F23"}, 23050 {52, mips.REG_F24, "F24"}, 23051 {53, mips.REG_F25, "F25"}, 23052 {54, mips.REG_F26, "F26"}, 23053 {55, mips.REG_F27, "F27"}, 23054 {56, mips.REG_F28, "F28"}, 23055 {57, mips.REG_F29, "F29"}, 23056 {58, mips.REG_F30, "F30"}, 23057 {59, mips.REG_F31, "F31"}, 23058 {60, mips.REG_HI, "HI"}, 23059 {61, mips.REG_LO, "LO"}, 23060 {62, 0, "SB"}, 23061 } 23062 var gpRegMaskMIPS64 = regMask(167772158) 23063 var fpRegMaskMIPS64 = regMask(1152921504338411520) 23064 var specialRegMaskMIPS64 = regMask(3458764513820540928) 23065 var framepointerRegMIPS64 = int8(-1) 23066 var linkRegMIPS64 = int8(27) 23067 var registersPPC64 = [...]Register{ 23068 {0, ppc64.REG_R0, "R0"}, 23069 {1, ppc64.REGSP, "SP"}, 23070 {2, 0, "SB"}, 23071 {3, ppc64.REG_R3, "R3"}, 23072 {4, ppc64.REG_R4, "R4"}, 23073 {5, ppc64.REG_R5, "R5"}, 23074 {6, ppc64.REG_R6, "R6"}, 23075 {7, ppc64.REG_R7, "R7"}, 23076 {8, ppc64.REG_R8, "R8"}, 23077 {9, ppc64.REG_R9, "R9"}, 23078 {10, ppc64.REG_R10, "R10"}, 23079 {11, ppc64.REG_R11, "R11"}, 23080 {12, ppc64.REG_R12, "R12"}, 23081 {13, ppc64.REG_R13, "R13"}, 23082 {14, ppc64.REG_R14, "R14"}, 23083 {15, ppc64.REG_R15, "R15"}, 23084 {16, ppc64.REG_R16, "R16"}, 23085 {17, ppc64.REG_R17, "R17"}, 23086 {18, ppc64.REG_R18, "R18"}, 23087 {19, ppc64.REG_R19, "R19"}, 23088 {20, ppc64.REG_R20, "R20"}, 23089 {21, ppc64.REG_R21, "R21"}, 23090 {22, ppc64.REG_R22, "R22"}, 23091 {23, ppc64.REG_R23, "R23"}, 23092 {24, ppc64.REG_R24, "R24"}, 23093 {25, ppc64.REG_R25, "R25"}, 23094 {26, ppc64.REG_R26, "R26"}, 23095 {27, ppc64.REG_R27, "R27"}, 23096 {28, ppc64.REG_R28, "R28"}, 23097 {29, ppc64.REG_R29, "R29"}, 23098 {30, ppc64.REGG, "g"}, 23099 {31, ppc64.REG_R31, "R31"}, 23100 {32, ppc64.REG_F0, "F0"}, 23101 {33, ppc64.REG_F1, "F1"}, 23102 {34, ppc64.REG_F2, "F2"}, 23103 {35, ppc64.REG_F3, "F3"}, 23104 {36, ppc64.REG_F4, "F4"}, 23105 {37, ppc64.REG_F5, "F5"}, 23106 {38, ppc64.REG_F6, "F6"}, 23107 {39, ppc64.REG_F7, "F7"}, 23108 {40, ppc64.REG_F8, "F8"}, 23109 {41, ppc64.REG_F9, "F9"}, 23110 {42, ppc64.REG_F10, "F10"}, 23111 {43, ppc64.REG_F11, "F11"}, 23112 {44, ppc64.REG_F12, "F12"}, 23113 {45, ppc64.REG_F13, "F13"}, 23114 {46, ppc64.REG_F14, "F14"}, 23115 {47, ppc64.REG_F15, "F15"}, 23116 {48, ppc64.REG_F16, "F16"}, 23117 {49, ppc64.REG_F17, "F17"}, 23118 {50, ppc64.REG_F18, "F18"}, 23119 {51, ppc64.REG_F19, "F19"}, 23120 {52, ppc64.REG_F20, "F20"}, 23121 {53, ppc64.REG_F21, "F21"}, 23122 {54, ppc64.REG_F22, "F22"}, 23123 {55, ppc64.REG_F23, "F23"}, 23124 {56, ppc64.REG_F24, "F24"}, 23125 {57, ppc64.REG_F25, "F25"}, 23126 {58, ppc64.REG_F26, "F26"}, 23127 {59, ppc64.REG_F27, "F27"}, 23128 {60, ppc64.REG_F28, "F28"}, 23129 {61, ppc64.REG_F29, "F29"}, 23130 {62, ppc64.REG_F30, "F30"}, 23131 {63, ppc64.REG_F31, "F31"}, 23132 } 23133 var gpRegMaskPPC64 = regMask(1073733624) 23134 var fpRegMaskPPC64 = regMask(576460743713488896) 23135 var specialRegMaskPPC64 = regMask(0) 23136 var framepointerRegPPC64 = int8(1) 23137 var linkRegPPC64 = int8(-1) 23138 var registersS390X = [...]Register{ 23139 {0, s390x.REG_R0, "R0"}, 23140 {1, s390x.REG_R1, "R1"}, 23141 {2, s390x.REG_R2, "R2"}, 23142 {3, s390x.REG_R3, "R3"}, 23143 {4, s390x.REG_R4, "R4"}, 23144 {5, s390x.REG_R5, "R5"}, 23145 {6, s390x.REG_R6, "R6"}, 23146 {7, s390x.REG_R7, "R7"}, 23147 {8, s390x.REG_R8, "R8"}, 23148 {9, s390x.REG_R9, "R9"}, 23149 {10, s390x.REG_R10, "R10"}, 23150 {11, s390x.REG_R11, "R11"}, 23151 {12, s390x.REG_R12, "R12"}, 23152 {13, s390x.REGG, "g"}, 23153 {14, s390x.REG_R14, "R14"}, 23154 {15, s390x.REGSP, "SP"}, 23155 {16, s390x.REG_F0, "F0"}, 23156 {17, s390x.REG_F1, "F1"}, 23157 {18, s390x.REG_F2, "F2"}, 23158 {19, s390x.REG_F3, "F3"}, 23159 {20, s390x.REG_F4, "F4"}, 23160 {21, s390x.REG_F5, "F5"}, 23161 {22, s390x.REG_F6, "F6"}, 23162 {23, s390x.REG_F7, "F7"}, 23163 {24, s390x.REG_F8, "F8"}, 23164 {25, s390x.REG_F9, "F9"}, 23165 {26, s390x.REG_F10, "F10"}, 23166 {27, s390x.REG_F11, "F11"}, 23167 {28, s390x.REG_F12, "F12"}, 23168 {29, s390x.REG_F13, "F13"}, 23169 {30, s390x.REG_F14, "F14"}, 23170 {31, s390x.REG_F15, "F15"}, 23171 {32, 0, "SB"}, 23172 } 23173 var gpRegMaskS390X = regMask(21503) 23174 var fpRegMaskS390X = regMask(4294901760) 23175 var specialRegMaskS390X = regMask(0) 23176 var framepointerRegS390X = int8(-1) 23177 var linkRegS390X = int8(14)