github.com/kdevb0x/go@v0.0.0-20180115030120-39687051e9e7/src/cmd/internal/obj/x86/a.out.go (about) 1 // Inferno utils/6c/6.out.h 2 // https://bitbucket.org/inferno-os/inferno-os/src/default/utils/6c/6.out.h 3 // 4 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 5 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 6 // Portions Copyright © 1997-1999 Vita Nuova Limited 7 // Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com) 8 // Portions Copyright © 2004,2006 Bruce Ellis 9 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 10 // Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others 11 // Portions Copyright © 2009 The Go Authors. All rights reserved. 12 // 13 // Permission is hereby granted, free of charge, to any person obtaining a copy 14 // of this software and associated documentation files (the "Software"), to deal 15 // in the Software without restriction, including without limitation the rights 16 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 // copies of the Software, and to permit persons to whom the Software is 18 // furnished to do so, subject to the following conditions: 19 // 20 // The above copyright notice and this permission notice shall be included in 21 // all copies or substantial portions of the Software. 22 // 23 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 26 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 // THE SOFTWARE. 30 31 package x86 32 33 import "cmd/internal/obj" 34 35 const ( 36 /* mark flags */ 37 DONE = 1 << iota 38 ) 39 40 const ( 41 REG_NONE = 0 42 ) 43 44 const ( 45 REG_AL = obj.RBaseAMD64 + iota 46 REG_CL 47 REG_DL 48 REG_BL 49 REG_SPB 50 REG_BPB 51 REG_SIB 52 REG_DIB 53 REG_R8B 54 REG_R9B 55 REG_R10B 56 REG_R11B 57 REG_R12B 58 REG_R13B 59 REG_R14B 60 REG_R15B 61 62 REG_AX 63 REG_CX 64 REG_DX 65 REG_BX 66 REG_SP 67 REG_BP 68 REG_SI 69 REG_DI 70 REG_R8 71 REG_R9 72 REG_R10 73 REG_R11 74 REG_R12 75 REG_R13 76 REG_R14 77 REG_R15 78 79 REG_AH 80 REG_CH 81 REG_DH 82 REG_BH 83 84 REG_F0 85 REG_F1 86 REG_F2 87 REG_F3 88 REG_F4 89 REG_F5 90 REG_F6 91 REG_F7 92 93 REG_M0 94 REG_M1 95 REG_M2 96 REG_M3 97 REG_M4 98 REG_M5 99 REG_M6 100 REG_M7 101 102 REG_X0 103 REG_X1 104 REG_X2 105 REG_X3 106 REG_X4 107 REG_X5 108 REG_X6 109 REG_X7 110 REG_X8 111 REG_X9 112 REG_X10 113 REG_X11 114 REG_X12 115 REG_X13 116 REG_X14 117 REG_X15 118 119 REG_Y0 120 REG_Y1 121 REG_Y2 122 REG_Y3 123 REG_Y4 124 REG_Y5 125 REG_Y6 126 REG_Y7 127 REG_Y8 128 REG_Y9 129 REG_Y10 130 REG_Y11 131 REG_Y12 132 REG_Y13 133 REG_Y14 134 REG_Y15 135 136 REG_CS 137 REG_SS 138 REG_DS 139 REG_ES 140 REG_FS 141 REG_GS 142 143 REG_GDTR /* global descriptor table register */ 144 REG_IDTR /* interrupt descriptor table register */ 145 REG_LDTR /* local descriptor table register */ 146 REG_MSW /* machine status word */ 147 REG_TASK /* task register */ 148 149 REG_CR0 150 REG_CR1 151 REG_CR2 152 REG_CR3 153 REG_CR4 154 REG_CR5 155 REG_CR6 156 REG_CR7 157 REG_CR8 158 REG_CR9 159 REG_CR10 160 REG_CR11 161 REG_CR12 162 REG_CR13 163 REG_CR14 164 REG_CR15 165 166 REG_DR0 167 REG_DR1 168 REG_DR2 169 REG_DR3 170 REG_DR4 171 REG_DR5 172 REG_DR6 173 REG_DR7 174 175 REG_TR0 176 REG_TR1 177 REG_TR2 178 REG_TR3 179 REG_TR4 180 REG_TR5 181 REG_TR6 182 REG_TR7 183 184 REG_TLS 185 186 MAXREG 187 188 REG_CR = REG_CR0 189 REG_DR = REG_DR0 190 REG_TR = REG_TR0 191 192 REGARG = -1 193 REGRET = REG_AX 194 FREGRET = REG_X0 195 REGSP = REG_SP 196 REGCTXT = REG_DX 197 REGEXT = REG_R15 /* compiler allocates external registers R15 down */ 198 FREGMIN = REG_X0 + 5 /* first register variable */ 199 FREGEXT = REG_X0 + 15 /* first external register */ 200 T_TYPE = 1 << 0 201 T_INDEX = 1 << 1 202 T_OFFSET = 1 << 2 203 T_FCONST = 1 << 3 204 T_SYM = 1 << 4 205 T_SCONST = 1 << 5 206 T_64 = 1 << 6 207 T_GOTYPE = 1 << 7 208 ) 209 210 // https://www.uclibc.org/docs/psABI-x86_64.pdf, figure 3.36 211 var AMD64DWARFRegisters = map[int16]int16{ 212 REG_AX: 0, 213 REG_DX: 1, 214 REG_CX: 2, 215 REG_BX: 3, 216 REG_SI: 4, 217 REG_DI: 5, 218 REG_BP: 6, 219 REG_SP: 7, 220 REG_R8: 8, 221 REG_R9: 9, 222 REG_R10: 10, 223 REG_R11: 11, 224 REG_R12: 12, 225 REG_R13: 13, 226 REG_R14: 14, 227 REG_R15: 15, 228 // 16 is "Return Address RA", whatever that is. 229 // XMM registers. %xmmN => XN. 230 REG_X0: 17, 231 REG_X1: 18, 232 REG_X2: 19, 233 REG_X3: 20, 234 REG_X4: 21, 235 REG_X5: 22, 236 REG_X6: 23, 237 REG_X7: 24, 238 REG_X8: 25, 239 REG_X9: 26, 240 REG_X10: 27, 241 REG_X11: 28, 242 REG_X12: 29, 243 REG_X13: 30, 244 REG_X14: 31, 245 REG_X15: 32, 246 // ST registers. %stN => FN. 247 REG_F0: 33, 248 REG_F1: 34, 249 REG_F2: 35, 250 REG_F3: 36, 251 REG_F4: 37, 252 REG_F5: 38, 253 REG_F6: 39, 254 REG_F7: 40, 255 // MMX registers. %mmN => MN. 256 REG_M0: 41, 257 REG_M1: 42, 258 REG_M2: 43, 259 REG_M3: 44, 260 REG_M4: 45, 261 REG_M5: 46, 262 REG_M6: 47, 263 REG_M7: 48, 264 // 48 is flags, which doesn't have a name. 265 REG_ES: 50, 266 REG_CS: 51, 267 REG_SS: 52, 268 REG_DS: 53, 269 REG_FS: 54, 270 REG_GS: 55, 271 // 58 and 59 are {fs,gs}base, which don't have names. 272 REG_TR: 62, 273 REG_LDTR: 63, 274 // 64-66 are mxcsr, fcw, fsw, which don't have names. 275 } 276 277 // https://www.uclibc.org/docs/psABI-i386.pdf, table 2.14 278 var X86DWARFRegisters = map[int16]int16{ 279 REG_AX: 0, 280 REG_CX: 1, 281 REG_DX: 2, 282 REG_BX: 3, 283 REG_SP: 4, 284 REG_BP: 5, 285 REG_SI: 6, 286 REG_DI: 7, 287 // 8 is "Return Address RA", whatever that is. 288 // 9 is flags, which doesn't have a name. 289 // ST registers. %stN => FN. 290 REG_F0: 11, 291 REG_F1: 12, 292 REG_F2: 13, 293 REG_F3: 14, 294 REG_F4: 15, 295 REG_F5: 16, 296 REG_F6: 17, 297 REG_F7: 18, 298 // XMM registers. %xmmN => XN. 299 REG_X0: 21, 300 REG_X1: 22, 301 REG_X2: 23, 302 REG_X3: 24, 303 REG_X4: 25, 304 REG_X5: 26, 305 REG_X6: 27, 306 REG_X7: 28, 307 // MMX registers. %mmN => MN. 308 REG_M0: 29, 309 REG_M1: 30, 310 REG_M2: 31, 311 REG_M3: 32, 312 REG_M4: 33, 313 REG_M5: 34, 314 REG_M6: 35, 315 REG_M7: 36, 316 // 39 is mxcsr, which doesn't have a name. 317 REG_ES: 40, 318 REG_CS: 41, 319 REG_SS: 42, 320 REG_DS: 43, 321 REG_FS: 44, 322 REG_GS: 45, 323 REG_TR: 48, 324 REG_LDTR: 49, 325 }