github.com/ltltlt/go-source-code@v0.0.0-20190830023027-95be009773aa/cmd/internal/obj/ppc64/a.out.go (about) 1 // cmd/9c/9.out.h from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package ppc64 31 32 import "cmd/internal/obj" 33 34 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p ppc64 35 36 /* 37 * powerpc 64 38 */ 39 const ( 40 NSNAME = 8 41 NSYM = 50 42 NREG = 32 /* number of general registers */ 43 NFREG = 32 /* number of floating point registers */ 44 ) 45 46 const ( 47 /* RBasePPC64 = 4096 */ 48 /* R0=4096 ... R31=4127 */ 49 REG_R0 = obj.RBasePPC64 + iota 50 REG_R1 51 REG_R2 52 REG_R3 53 REG_R4 54 REG_R5 55 REG_R6 56 REG_R7 57 REG_R8 58 REG_R9 59 REG_R10 60 REG_R11 61 REG_R12 62 REG_R13 63 REG_R14 64 REG_R15 65 REG_R16 66 REG_R17 67 REG_R18 68 REG_R19 69 REG_R20 70 REG_R21 71 REG_R22 72 REG_R23 73 REG_R24 74 REG_R25 75 REG_R26 76 REG_R27 77 REG_R28 78 REG_R29 79 REG_R30 80 REG_R31 81 82 /* F0=4128 ... F31=4159 */ 83 REG_F0 84 REG_F1 85 REG_F2 86 REG_F3 87 REG_F4 88 REG_F5 89 REG_F6 90 REG_F7 91 REG_F8 92 REG_F9 93 REG_F10 94 REG_F11 95 REG_F12 96 REG_F13 97 REG_F14 98 REG_F15 99 REG_F16 100 REG_F17 101 REG_F18 102 REG_F19 103 REG_F20 104 REG_F21 105 REG_F22 106 REG_F23 107 REG_F24 108 REG_F25 109 REG_F26 110 REG_F27 111 REG_F28 112 REG_F29 113 REG_F30 114 REG_F31 115 116 /* V0=4160 ... V31=4191 */ 117 REG_V0 118 REG_V1 119 REG_V2 120 REG_V3 121 REG_V4 122 REG_V5 123 REG_V6 124 REG_V7 125 REG_V8 126 REG_V9 127 REG_V10 128 REG_V11 129 REG_V12 130 REG_V13 131 REG_V14 132 REG_V15 133 REG_V16 134 REG_V17 135 REG_V18 136 REG_V19 137 REG_V20 138 REG_V21 139 REG_V22 140 REG_V23 141 REG_V24 142 REG_V25 143 REG_V26 144 REG_V27 145 REG_V28 146 REG_V29 147 REG_V30 148 REG_V31 149 150 /* VS0=4192 ... VS63=4255 */ 151 REG_VS0 152 REG_VS1 153 REG_VS2 154 REG_VS3 155 REG_VS4 156 REG_VS5 157 REG_VS6 158 REG_VS7 159 REG_VS8 160 REG_VS9 161 REG_VS10 162 REG_VS11 163 REG_VS12 164 REG_VS13 165 REG_VS14 166 REG_VS15 167 REG_VS16 168 REG_VS17 169 REG_VS18 170 REG_VS19 171 REG_VS20 172 REG_VS21 173 REG_VS22 174 REG_VS23 175 REG_VS24 176 REG_VS25 177 REG_VS26 178 REG_VS27 179 REG_VS28 180 REG_VS29 181 REG_VS30 182 REG_VS31 183 REG_VS32 184 REG_VS33 185 REG_VS34 186 REG_VS35 187 REG_VS36 188 REG_VS37 189 REG_VS38 190 REG_VS39 191 REG_VS40 192 REG_VS41 193 REG_VS42 194 REG_VS43 195 REG_VS44 196 REG_VS45 197 REG_VS46 198 REG_VS47 199 REG_VS48 200 REG_VS49 201 REG_VS50 202 REG_VS51 203 REG_VS52 204 REG_VS53 205 REG_VS54 206 REG_VS55 207 REG_VS56 208 REG_VS57 209 REG_VS58 210 REG_VS59 211 REG_VS60 212 REG_VS61 213 REG_VS62 214 REG_VS63 215 216 REG_CR0 217 REG_CR1 218 REG_CR2 219 REG_CR3 220 REG_CR4 221 REG_CR5 222 REG_CR6 223 REG_CR7 224 225 REG_MSR 226 REG_FPSCR 227 REG_CR 228 229 REG_SPECIAL = REG_CR0 230 231 REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers 232 REG_DCR0 = obj.RBasePPC64 + 2048 // first of 1024 registers 233 234 REG_XER = REG_SPR0 + 1 235 REG_LR = REG_SPR0 + 8 236 REG_CTR = REG_SPR0 + 9 237 238 REGZERO = REG_R0 /* set to zero */ 239 REGSP = REG_R1 240 REGSB = REG_R2 241 REGRET = REG_R3 242 REGARG = -1 /* -1 disables passing the first argument in register */ 243 REGRT1 = REG_R3 /* reserved for runtime, duffzero and duffcopy */ 244 REGRT2 = REG_R4 /* reserved for runtime, duffcopy */ 245 REGMIN = REG_R7 /* register variables allocated from here to REGMAX */ 246 REGCTXT = REG_R11 /* context for closures */ 247 REGTLS = REG_R13 /* C ABI TLS base pointer */ 248 REGMAX = REG_R27 249 REGEXT = REG_R30 /* external registers allocated from here down */ 250 REGG = REG_R30 /* G */ 251 REGTMP = REG_R31 /* used by the linker */ 252 FREGRET = REG_F0 253 FREGMIN = REG_F17 /* first register variable */ 254 FREGMAX = REG_F26 /* last register variable for 9g only */ 255 FREGEXT = REG_F26 /* first external register */ 256 ) 257 258 /* 259 * GENERAL: 260 * 261 * compiler allocates R3 up as temps 262 * compiler allocates register variables R7-R27 263 * compiler allocates external registers R30 down 264 * 265 * compiler allocates register variables F17-F26 266 * compiler allocates external registers F26 down 267 */ 268 const ( 269 BIG = 32768 - 8 270 ) 271 272 const ( 273 /* mark flags */ 274 LABEL = 1 << 0 275 LEAF = 1 << 1 276 FLOAT = 1 << 2 277 BRANCH = 1 << 3 278 LOAD = 1 << 4 279 FCMP = 1 << 5 280 SYNC = 1 << 6 281 LIST = 1 << 7 282 FOLL = 1 << 8 283 NOSCHED = 1 << 9 284 ) 285 286 // Values for use in branch instruction BC 287 // BC B0,BI,label 288 // BO is type of branch + likely bits described below 289 // BI is CR value + branch type 290 // ex: BEQ CR2,label is BC 12,10,label 291 // 12 = BO_BCR 292 // 10 = BI_CR2 + BI_EQ 293 294 const ( 295 BI_CR0 = 0 296 BI_CR1 = 4 297 BI_CR2 = 8 298 BI_CR3 = 12 299 BI_CR4 = 16 300 BI_CR5 = 20 301 BI_CR6 = 24 302 BI_CR7 = 28 303 BI_LT = 0 304 BI_GT = 1 305 BI_EQ = 2 306 BI_OVF = 3 307 ) 308 309 // Values for the BO field. Add the branch type to 310 // the likely bits, if a likely setting is known. 311 // If branch likely or unlikely is not known, don't set it. 312 // e.g. branch on cr+likely = 15 313 314 const ( 315 BO_BCTR = 16 // branch on ctr value 316 BO_BCR = 12 // branch on cr value 317 BO_BCRBCTR = 8 // branch on ctr and cr value 318 BO_NOTBCR = 4 // branch on not cr value 319 BO_UNLIKELY = 2 // value for unlikely 320 BO_LIKELY = 3 // value for likely 321 ) 322 323 // Bit settings from the CR 324 325 const ( 326 C_COND_LT = iota // 0 result is negative 327 C_COND_GT // 1 result is positive 328 C_COND_EQ // 2 result is zero 329 C_COND_SO // 3 summary overflow or FP compare w/ NaN 330 ) 331 332 const ( 333 C_NONE = iota 334 C_REG 335 C_FREG 336 C_VREG 337 C_VSREG 338 C_CREG 339 C_SPR /* special processor register */ 340 C_ZCON 341 C_SCON /* 16 bit signed */ 342 C_UCON /* 32 bit signed, low 16 bits 0 */ 343 C_ADDCON /* -0x8000 <= v < 0 */ 344 C_ANDCON /* 0 < v <= 0xFFFF */ 345 C_LCON /* other 32 */ 346 C_DCON /* other 64 (could subdivide further) */ 347 C_SACON /* $n(REG) where n <= int16 */ 348 C_SECON 349 C_LACON /* $n(REG) where int16 < n <= int32 */ 350 C_LECON 351 C_DACON /* $n(REG) where int32 < n */ 352 C_SBRA 353 C_LBRA 354 C_LBRAPIC 355 C_SAUTO 356 C_LAUTO 357 C_SEXT 358 C_LEXT 359 C_ZOREG // conjecture: either (1) register + zeroed offset, or (2) "R0" implies zero or C_REG 360 C_SOREG // register + signed offset 361 C_LOREG 362 C_FPSCR 363 C_MSR 364 C_XER 365 C_LR 366 C_CTR 367 C_ANY 368 C_GOK 369 C_ADDR 370 C_GOTADDR 371 C_TLS_LE 372 C_TLS_IE 373 C_TEXTSIZE 374 375 C_NCLASS /* must be the last */ 376 ) 377 378 const ( 379 AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota 380 AADDCC 381 AADDV 382 AADDVCC 383 AADDC 384 AADDCCC 385 AADDCV 386 AADDCVCC 387 AADDME 388 AADDMECC 389 AADDMEVCC 390 AADDMEV 391 AADDE 392 AADDECC 393 AADDEVCC 394 AADDEV 395 AADDZE 396 AADDZECC 397 AADDZEVCC 398 AADDZEV 399 AADDEX 400 AAND 401 AANDCC 402 AANDN 403 AANDNCC 404 ABC 405 ABCL 406 ABEQ 407 ABGE // not LT = G/E/U 408 ABGT 409 ABLE // not GT = L/E/U 410 ABLT 411 ABNE // not EQ = L/G/U 412 ABVC // Unordered-clear 413 ABVS // Unordered-set 414 ACMP 415 ACMPU 416 ACMPEQB 417 ACNTLZW 418 ACNTLZWCC 419 ACRAND 420 ACRANDN 421 ACREQV 422 ACRNAND 423 ACRNOR 424 ACROR 425 ACRORN 426 ACRXOR 427 ADIVW 428 ADIVWCC 429 ADIVWVCC 430 ADIVWV 431 ADIVWU 432 ADIVWUCC 433 ADIVWUVCC 434 ADIVWUV 435 AEQV 436 AEQVCC 437 AEXTSB 438 AEXTSBCC 439 AEXTSH 440 AEXTSHCC 441 AFABS 442 AFABSCC 443 AFADD 444 AFADDCC 445 AFADDS 446 AFADDSCC 447 AFCMPO 448 AFCMPU 449 AFCTIW 450 AFCTIWCC 451 AFCTIWZ 452 AFCTIWZCC 453 AFDIV 454 AFDIVCC 455 AFDIVS 456 AFDIVSCC 457 AFMADD 458 AFMADDCC 459 AFMADDS 460 AFMADDSCC 461 AFMOVD 462 AFMOVDCC 463 AFMOVDU 464 AFMOVS 465 AFMOVSU 466 AFMOVSX 467 AFMOVSZ 468 AFMSUB 469 AFMSUBCC 470 AFMSUBS 471 AFMSUBSCC 472 AFMUL 473 AFMULCC 474 AFMULS 475 AFMULSCC 476 AFNABS 477 AFNABSCC 478 AFNEG 479 AFNEGCC 480 AFNMADD 481 AFNMADDCC 482 AFNMADDS 483 AFNMADDSCC 484 AFNMSUB 485 AFNMSUBCC 486 AFNMSUBS 487 AFNMSUBSCC 488 AFRSP 489 AFRSPCC 490 AFSUB 491 AFSUBCC 492 AFSUBS 493 AFSUBSCC 494 AISEL 495 AMOVMW 496 ALBAR 497 ALSW 498 ALWAR 499 ALWSYNC 500 AMOVDBR 501 AMOVWBR 502 AMOVB 503 AMOVBU 504 AMOVBZ 505 AMOVBZU 506 AMOVH 507 AMOVHBR 508 AMOVHU 509 AMOVHZ 510 AMOVHZU 511 AMOVW 512 AMOVWU 513 AMOVFL 514 AMOVCRFS 515 AMTFSB0 516 AMTFSB0CC 517 AMTFSB1 518 AMTFSB1CC 519 AMULHW 520 AMULHWCC 521 AMULHWU 522 AMULHWUCC 523 AMULLW 524 AMULLWCC 525 AMULLWVCC 526 AMULLWV 527 ANAND 528 ANANDCC 529 ANEG 530 ANEGCC 531 ANEGVCC 532 ANEGV 533 ANOR 534 ANORCC 535 AOR 536 AORCC 537 AORN 538 AORNCC 539 AREM 540 AREMCC 541 AREMV 542 AREMVCC 543 AREMU 544 AREMUCC 545 AREMUV 546 AREMUVCC 547 ARFI 548 ARLWMI 549 ARLWMICC 550 ARLWNM 551 ARLWNMCC 552 ASLW 553 ASLWCC 554 ASRW 555 ASRAW 556 ASRAWCC 557 ASRWCC 558 ASTBCCC 559 ASTSW 560 ASTWCCC 561 ASUB 562 ASUBCC 563 ASUBVCC 564 ASUBC 565 ASUBCCC 566 ASUBCV 567 ASUBCVCC 568 ASUBME 569 ASUBMECC 570 ASUBMEVCC 571 ASUBMEV 572 ASUBV 573 ASUBE 574 ASUBECC 575 ASUBEV 576 ASUBEVCC 577 ASUBZE 578 ASUBZECC 579 ASUBZEVCC 580 ASUBZEV 581 ASYNC 582 AXOR 583 AXORCC 584 585 ADCBF 586 ADCBI 587 ADCBST 588 ADCBT 589 ADCBTST 590 ADCBZ 591 AECIWX 592 AECOWX 593 AEIEIO 594 AICBI 595 AISYNC 596 APTESYNC 597 ATLBIE 598 ATLBIEL 599 ATLBSYNC 600 ATW 601 602 ASYSCALL 603 AWORD 604 605 ARFCI 606 607 AFCPSGN 608 AFCPSGNCC 609 /* optional on 32-bit */ 610 AFRES 611 AFRESCC 612 AFRIM 613 AFRIMCC 614 AFRIP 615 AFRIPCC 616 AFRIZ 617 AFRIZCC 618 AFRSQRTE 619 AFRSQRTECC 620 AFSEL 621 AFSELCC 622 AFSQRT 623 AFSQRTCC 624 AFSQRTS 625 AFSQRTSCC 626 627 /* 64-bit */ 628 629 ACNTLZD 630 ACNTLZDCC 631 ACMPW /* CMP with L=0 */ 632 ACMPWU 633 ACMPB 634 AFTDIV 635 AFTSQRT 636 ADIVD 637 ADIVDCC 638 ADIVDE 639 ADIVDECC 640 ADIVDEU 641 ADIVDEUCC 642 ADIVDVCC 643 ADIVDV 644 ADIVDU 645 ADIVDUCC 646 ADIVDUVCC 647 ADIVDUV 648 AEXTSW 649 AEXTSWCC 650 /* AFCFIW; AFCFIWCC */ 651 AFCFID 652 AFCFIDCC 653 AFCFIDU 654 AFCFIDUCC 655 AFCFIDS 656 AFCFIDSCC 657 AFCTID 658 AFCTIDCC 659 AFCTIDZ 660 AFCTIDZCC 661 ALDAR 662 AMOVD 663 AMOVDU 664 AMOVWZ 665 AMOVWZU 666 AMULHD 667 AMULHDCC 668 AMULHDU 669 AMULHDUCC 670 AMULLD 671 AMULLDCC 672 AMULLDVCC 673 AMULLDV 674 ARFID 675 ARLDMI 676 ARLDMICC 677 ARLDIMI 678 ARLDIMICC 679 ARLDC 680 ARLDCCC 681 ARLDCR 682 ARLDCRCC 683 ARLDICR 684 ARLDICRCC 685 ARLDCL 686 ARLDCLCC 687 ARLDICL 688 ARLDICLCC 689 AROTL 690 AROTLW 691 ASLBIA 692 ASLBIE 693 ASLBMFEE 694 ASLBMFEV 695 ASLBMTE 696 ASLD 697 ASLDCC 698 ASRD 699 ASRAD 700 ASRADCC 701 ASRDCC 702 ASTDCCC 703 ATD 704 705 /* 64-bit pseudo operation */ 706 ADWORD 707 AREMD 708 AREMDCC 709 AREMDV 710 AREMDVCC 711 AREMDU 712 AREMDUCC 713 AREMDUV 714 AREMDUVCC 715 716 /* more 64-bit operations */ 717 AHRFID 718 APOPCNTD 719 APOPCNTW 720 APOPCNTB 721 ACOPY 722 APASTECC 723 ADARN 724 ALDMX 725 AMADDHD 726 AMADDHDU 727 AMADDLD 728 729 /* Vector */ 730 ALV 731 ALVEBX 732 ALVEHX 733 ALVEWX 734 ALVX 735 ALVXL 736 ALVSL 737 ALVSR 738 ASTV 739 ASTVEBX 740 ASTVEHX 741 ASTVEWX 742 ASTVX 743 ASTVXL 744 AVAND 745 AVANDC 746 AVNAND 747 AVOR 748 AVORC 749 AVNOR 750 AVXOR 751 AVEQV 752 AVADDUM 753 AVADDUBM 754 AVADDUHM 755 AVADDUWM 756 AVADDUDM 757 AVADDUQM 758 AVADDCU 759 AVADDCUQ 760 AVADDCUW 761 AVADDUS 762 AVADDUBS 763 AVADDUHS 764 AVADDUWS 765 AVADDSS 766 AVADDSBS 767 AVADDSHS 768 AVADDSWS 769 AVADDE 770 AVADDEUQM 771 AVADDECUQ 772 AVSUBUM 773 AVSUBUBM 774 AVSUBUHM 775 AVSUBUWM 776 AVSUBUDM 777 AVSUBUQM 778 AVSUBCU 779 AVSUBCUQ 780 AVSUBCUW 781 AVSUBUS 782 AVSUBUBS 783 AVSUBUHS 784 AVSUBUWS 785 AVSUBSS 786 AVSUBSBS 787 AVSUBSHS 788 AVSUBSWS 789 AVSUBE 790 AVSUBEUQM 791 AVSUBECUQ 792 AVPMSUM 793 AVPMSUMB 794 AVPMSUMH 795 AVPMSUMW 796 AVPMSUMD 797 AVMSUMUDM 798 AVR 799 AVRLB 800 AVRLH 801 AVRLW 802 AVRLD 803 AVS 804 AVSLB 805 AVSLH 806 AVSLW 807 AVSL 808 AVSLO 809 AVSRB 810 AVSRH 811 AVSRW 812 AVSR 813 AVSRO 814 AVSLD 815 AVSRD 816 AVSA 817 AVSRAB 818 AVSRAH 819 AVSRAW 820 AVSRAD 821 AVSOI 822 AVSLDOI 823 AVCLZ 824 AVCLZB 825 AVCLZH 826 AVCLZW 827 AVCLZD 828 AVPOPCNT 829 AVPOPCNTB 830 AVPOPCNTH 831 AVPOPCNTW 832 AVPOPCNTD 833 AVCMPEQ 834 AVCMPEQUB 835 AVCMPEQUBCC 836 AVCMPEQUH 837 AVCMPEQUHCC 838 AVCMPEQUW 839 AVCMPEQUWCC 840 AVCMPEQUD 841 AVCMPEQUDCC 842 AVCMPGT 843 AVCMPGTUB 844 AVCMPGTUBCC 845 AVCMPGTUH 846 AVCMPGTUHCC 847 AVCMPGTUW 848 AVCMPGTUWCC 849 AVCMPGTUD 850 AVCMPGTUDCC 851 AVCMPGTSB 852 AVCMPGTSBCC 853 AVCMPGTSH 854 AVCMPGTSHCC 855 AVCMPGTSW 856 AVCMPGTSWCC 857 AVCMPGTSD 858 AVCMPGTSDCC 859 AVCMPNEZB 860 AVCMPNEZBCC 861 AVPERM 862 AVBPERMQ 863 AVBPERMD 864 AVSEL 865 AVSPLT 866 AVSPLTB 867 AVSPLTH 868 AVSPLTW 869 AVSPLTI 870 AVSPLTISB 871 AVSPLTISH 872 AVSPLTISW 873 AVCIPH 874 AVCIPHER 875 AVCIPHERLAST 876 AVNCIPH 877 AVNCIPHER 878 AVNCIPHERLAST 879 AVSBOX 880 AVSHASIGMA 881 AVSHASIGMAW 882 AVSHASIGMAD 883 884 /* VSX */ 885 ALXV 886 ALXVD2X 887 ALXVDSX 888 ALXVW4X 889 ASTXV 890 ASTXVD2X 891 ASTXVW4X 892 ALXS 893 ALXSDX 894 ASTXS 895 ASTXSDX 896 ALXSI 897 ALXSIWAX 898 ALXSIWZX 899 ASTXSI 900 ASTXSIWX 901 AMFVSR 902 AMFVSRD 903 AMFFPRD 904 AMFVRD 905 AMFVSRWZ 906 AMFVSRLD 907 AMTVSR 908 AMTVSRD 909 AMTFPRD 910 AMTVRD 911 AMTVSRWA 912 AMTVSRWZ 913 AMTVSRDD 914 AMTVSRWS 915 AXXLAND 916 AXXLANDQ 917 AXXLANDC 918 AXXLEQV 919 AXXLNAND 920 AXXLOR 921 AXXLORC 922 AXXLNOR 923 AXXLORQ 924 AXXLXOR 925 AXXSEL 926 AXXMRG 927 AXXMRGHW 928 AXXMRGLW 929 AXXSPLT 930 AXXSPLTW 931 AXXPERM 932 AXXPERMDI 933 AXXSI 934 AXXSLDWI 935 AXSCV 936 AXSCVDPSP 937 AXSCVSPDP 938 AXSCVDPSPN 939 AXSCVSPDPN 940 AXVCV 941 AXVCVDPSP 942 AXVCVSPDP 943 AXSCVX 944 AXSCVDPSXDS 945 AXSCVDPSXWS 946 AXSCVDPUXDS 947 AXSCVDPUXWS 948 AXSCVXP 949 AXSCVSXDDP 950 AXSCVUXDDP 951 AXSCVSXDSP 952 AXSCVUXDSP 953 AXVCVX 954 AXVCVDPSXDS 955 AXVCVDPSXWS 956 AXVCVDPUXDS 957 AXVCVDPUXWS 958 AXVCVSPSXDS 959 AXVCVSPSXWS 960 AXVCVSPUXDS 961 AXVCVSPUXWS 962 AXVCVXP 963 AXVCVSXDDP 964 AXVCVSXWDP 965 AXVCVUXDDP 966 AXVCVUXWDP 967 AXVCVSXDSP 968 AXVCVSXWSP 969 AXVCVUXDSP 970 AXVCVUXWSP 971 972 ALAST 973 974 // aliases 975 ABR = obj.AJMP 976 ABL = obj.ACALL 977 )