github.com/matrixorigin/matrixone@v1.2.0/pkg/sql/colexec/intersectall/intersectall_test.go (about) 1 // Copyright 2022 Matrix Origin 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 package intersectall 16 17 import ( 18 "context" 19 "testing" 20 21 "github.com/matrixorigin/matrixone/pkg/container/batch" 22 "github.com/matrixorigin/matrixone/pkg/container/types" 23 "github.com/matrixorigin/matrixone/pkg/container/vector" 24 "github.com/matrixorigin/matrixone/pkg/testutil" 25 "github.com/matrixorigin/matrixone/pkg/vm" 26 "github.com/matrixorigin/matrixone/pkg/vm/process" 27 "github.com/stretchr/testify/require" 28 ) 29 30 type intersectAllTestCase struct { 31 proc *process.Process 32 arg *Argument 33 cancel context.CancelFunc 34 } 35 36 func TestIntersectAll(t *testing.T) { 37 proc := testutil.NewProcess() 38 // [2 rows + 2 row, 3 columns] minus [1 row + 2 rows, 3 columns] 39 /* 40 {1, 2, 3} {1, 2, 3} {1, 2, 3} 41 {1, 2, 3} intersect all {4, 5, 6} ==> {1, 2, 3} 42 {3, 4, 5} {1, 2, 3} 43 {3, 4, 5} 44 */ 45 c := newIntersectAllTestCase( 46 proc, 47 []*batch.Batch{ 48 testutil.NewBatchWithVectors( 49 []*vector.Vector{ 50 testutil.NewVector(2, types.T_int64.ToType(), proc.Mp(), false, []int64{1, 1}), 51 testutil.NewVector(2, types.T_int64.ToType(), proc.Mp(), false, []int64{2, 2}), 52 testutil.NewVector(2, types.T_int64.ToType(), proc.Mp(), false, []int64{3, 3}), 53 }, nil), 54 testutil.NewBatchWithVectors( 55 []*vector.Vector{ 56 testutil.NewVector(2, types.T_int64.ToType(), proc.Mp(), false, []int64{3, 3}), 57 testutil.NewVector(2, types.T_int64.ToType(), proc.Mp(), false, []int64{4, 4}), 58 testutil.NewVector(2, types.T_int64.ToType(), proc.Mp(), false, []int64{5, 5}), 59 }, nil), 60 }, 61 []*batch.Batch{ 62 testutil.NewBatchWithVectors( 63 []*vector.Vector{ 64 testutil.NewVector(1, types.T_int64.ToType(), proc.Mp(), false, []int64{1, 1}), 65 testutil.NewVector(1, types.T_int64.ToType(), proc.Mp(), false, []int64{2, 2}), 66 testutil.NewVector(1, types.T_int64.ToType(), proc.Mp(), false, []int64{3, 3}), 67 }, nil), 68 testutil.NewBatchWithVectors( 69 []*vector.Vector{ 70 testutil.NewVector(1, types.T_int64.ToType(), proc.Mp(), false, []int64{4}), 71 testutil.NewVector(1, types.T_int64.ToType(), proc.Mp(), false, []int64{5}), 72 testutil.NewVector(1, types.T_int64.ToType(), proc.Mp(), false, []int64{6}), 73 }, nil), 74 }, 75 ) 76 err := c.arg.Prepare(c.proc) 77 require.NoError(t, err) 78 cnt := 0 79 var end vm.CallResult 80 81 for { 82 end, err = c.arg.Call(c.proc) 83 require.NoError(t, err) 84 result := end.Batch 85 if result != nil && !result.IsEmpty() { 86 cnt += result.RowCount() 87 require.Equal(t, 3, len(result.Vecs)) 88 } else { 89 break 90 } 91 } 92 93 require.Equal(t, 2, cnt) // 1 row 94 c.proc.Reg.MergeReceivers[0].Ch <- nil 95 c.proc.Reg.MergeReceivers[1].Ch <- nil 96 c.arg.Free(c.proc, false, nil) 97 c.proc.FreeVectors() 98 require.Equal(t, int64(0), c.proc.Mp().CurrNB()) 99 } 100 101 func newIntersectAllTestCase(proc *process.Process, leftBatches, rightBatches []*batch.Batch) intersectAllTestCase { 102 ctx, cancel := context.WithCancel(context.Background()) 103 proc.Reg.MergeReceivers = make([]*process.WaitRegister, 2) 104 { 105 c := make(chan *batch.Batch, len(leftBatches)+1) 106 for i := range leftBatches { 107 c <- leftBatches[i] 108 } 109 c <- nil 110 proc.Reg.MergeReceivers[0] = &process.WaitRegister{ 111 Ctx: ctx, 112 Ch: c, 113 } 114 } 115 { 116 c := make(chan *batch.Batch, len(rightBatches)+1) 117 for i := range rightBatches { 118 c <- rightBatches[i] 119 } 120 c <- nil 121 proc.Reg.MergeReceivers[1] = &process.WaitRegister{ 122 Ctx: ctx, 123 Ch: c, 124 } 125 } 126 arg := new(Argument) 127 arg.OperatorBase.OperatorInfo = vm.OperatorInfo{ 128 Idx: 0, 129 IsFirst: false, 130 IsLast: false, 131 } 132 return intersectAllTestCase{ 133 proc: proc, 134 arg: arg, 135 cancel: cancel, 136 } 137 }