github.com/mattn/go@v0.0.0-20171011075504-07f7db3ea99f/src/cmd/compile/internal/ssa/opGen.go (about) 1 // Code generated from gen/*Ops.go; DO NOT EDIT. 2 3 package ssa 4 5 import ( 6 "cmd/internal/obj" 7 "cmd/internal/obj/arm" 8 "cmd/internal/obj/arm64" 9 "cmd/internal/obj/mips" 10 "cmd/internal/obj/ppc64" 11 "cmd/internal/obj/s390x" 12 "cmd/internal/obj/x86" 13 ) 14 15 const ( 16 BlockInvalid BlockKind = iota 17 18 Block386EQ 19 Block386NE 20 Block386LT 21 Block386LE 22 Block386GT 23 Block386GE 24 Block386ULT 25 Block386ULE 26 Block386UGT 27 Block386UGE 28 Block386EQF 29 Block386NEF 30 Block386ORD 31 Block386NAN 32 33 BlockAMD64EQ 34 BlockAMD64NE 35 BlockAMD64LT 36 BlockAMD64LE 37 BlockAMD64GT 38 BlockAMD64GE 39 BlockAMD64ULT 40 BlockAMD64ULE 41 BlockAMD64UGT 42 BlockAMD64UGE 43 BlockAMD64EQF 44 BlockAMD64NEF 45 BlockAMD64ORD 46 BlockAMD64NAN 47 48 BlockARMEQ 49 BlockARMNE 50 BlockARMLT 51 BlockARMLE 52 BlockARMGT 53 BlockARMGE 54 BlockARMULT 55 BlockARMULE 56 BlockARMUGT 57 BlockARMUGE 58 59 BlockARM64EQ 60 BlockARM64NE 61 BlockARM64LT 62 BlockARM64LE 63 BlockARM64GT 64 BlockARM64GE 65 BlockARM64ULT 66 BlockARM64ULE 67 BlockARM64UGT 68 BlockARM64UGE 69 BlockARM64Z 70 BlockARM64NZ 71 BlockARM64ZW 72 BlockARM64NZW 73 BlockARM64TBZ 74 BlockARM64TBNZ 75 76 BlockMIPSEQ 77 BlockMIPSNE 78 BlockMIPSLTZ 79 BlockMIPSLEZ 80 BlockMIPSGTZ 81 BlockMIPSGEZ 82 BlockMIPSFPT 83 BlockMIPSFPF 84 85 BlockMIPS64EQ 86 BlockMIPS64NE 87 BlockMIPS64LTZ 88 BlockMIPS64LEZ 89 BlockMIPS64GTZ 90 BlockMIPS64GEZ 91 BlockMIPS64FPT 92 BlockMIPS64FPF 93 94 BlockPPC64EQ 95 BlockPPC64NE 96 BlockPPC64LT 97 BlockPPC64LE 98 BlockPPC64GT 99 BlockPPC64GE 100 BlockPPC64FLT 101 BlockPPC64FLE 102 BlockPPC64FGT 103 BlockPPC64FGE 104 105 BlockS390XEQ 106 BlockS390XNE 107 BlockS390XLT 108 BlockS390XLE 109 BlockS390XGT 110 BlockS390XGE 111 BlockS390XGTF 112 BlockS390XGEF 113 114 BlockPlain 115 BlockIf 116 BlockDefer 117 BlockRet 118 BlockRetJmp 119 BlockExit 120 BlockFirst 121 ) 122 123 var blockString = [...]string{ 124 BlockInvalid: "BlockInvalid", 125 126 Block386EQ: "EQ", 127 Block386NE: "NE", 128 Block386LT: "LT", 129 Block386LE: "LE", 130 Block386GT: "GT", 131 Block386GE: "GE", 132 Block386ULT: "ULT", 133 Block386ULE: "ULE", 134 Block386UGT: "UGT", 135 Block386UGE: "UGE", 136 Block386EQF: "EQF", 137 Block386NEF: "NEF", 138 Block386ORD: "ORD", 139 Block386NAN: "NAN", 140 141 BlockAMD64EQ: "EQ", 142 BlockAMD64NE: "NE", 143 BlockAMD64LT: "LT", 144 BlockAMD64LE: "LE", 145 BlockAMD64GT: "GT", 146 BlockAMD64GE: "GE", 147 BlockAMD64ULT: "ULT", 148 BlockAMD64ULE: "ULE", 149 BlockAMD64UGT: "UGT", 150 BlockAMD64UGE: "UGE", 151 BlockAMD64EQF: "EQF", 152 BlockAMD64NEF: "NEF", 153 BlockAMD64ORD: "ORD", 154 BlockAMD64NAN: "NAN", 155 156 BlockARMEQ: "EQ", 157 BlockARMNE: "NE", 158 BlockARMLT: "LT", 159 BlockARMLE: "LE", 160 BlockARMGT: "GT", 161 BlockARMGE: "GE", 162 BlockARMULT: "ULT", 163 BlockARMULE: "ULE", 164 BlockARMUGT: "UGT", 165 BlockARMUGE: "UGE", 166 167 BlockARM64EQ: "EQ", 168 BlockARM64NE: "NE", 169 BlockARM64LT: "LT", 170 BlockARM64LE: "LE", 171 BlockARM64GT: "GT", 172 BlockARM64GE: "GE", 173 BlockARM64ULT: "ULT", 174 BlockARM64ULE: "ULE", 175 BlockARM64UGT: "UGT", 176 BlockARM64UGE: "UGE", 177 BlockARM64Z: "Z", 178 BlockARM64NZ: "NZ", 179 BlockARM64ZW: "ZW", 180 BlockARM64NZW: "NZW", 181 BlockARM64TBZ: "TBZ", 182 BlockARM64TBNZ: "TBNZ", 183 184 BlockMIPSEQ: "EQ", 185 BlockMIPSNE: "NE", 186 BlockMIPSLTZ: "LTZ", 187 BlockMIPSLEZ: "LEZ", 188 BlockMIPSGTZ: "GTZ", 189 BlockMIPSGEZ: "GEZ", 190 BlockMIPSFPT: "FPT", 191 BlockMIPSFPF: "FPF", 192 193 BlockMIPS64EQ: "EQ", 194 BlockMIPS64NE: "NE", 195 BlockMIPS64LTZ: "LTZ", 196 BlockMIPS64LEZ: "LEZ", 197 BlockMIPS64GTZ: "GTZ", 198 BlockMIPS64GEZ: "GEZ", 199 BlockMIPS64FPT: "FPT", 200 BlockMIPS64FPF: "FPF", 201 202 BlockPPC64EQ: "EQ", 203 BlockPPC64NE: "NE", 204 BlockPPC64LT: "LT", 205 BlockPPC64LE: "LE", 206 BlockPPC64GT: "GT", 207 BlockPPC64GE: "GE", 208 BlockPPC64FLT: "FLT", 209 BlockPPC64FLE: "FLE", 210 BlockPPC64FGT: "FGT", 211 BlockPPC64FGE: "FGE", 212 213 BlockS390XEQ: "EQ", 214 BlockS390XNE: "NE", 215 BlockS390XLT: "LT", 216 BlockS390XLE: "LE", 217 BlockS390XGT: "GT", 218 BlockS390XGE: "GE", 219 BlockS390XGTF: "GTF", 220 BlockS390XGEF: "GEF", 221 222 BlockPlain: "Plain", 223 BlockIf: "If", 224 BlockDefer: "Defer", 225 BlockRet: "Ret", 226 BlockRetJmp: "RetJmp", 227 BlockExit: "Exit", 228 BlockFirst: "First", 229 } 230 231 func (k BlockKind) String() string { return blockString[k] } 232 233 const ( 234 OpInvalid Op = iota 235 236 Op386ADDSS 237 Op386ADDSD 238 Op386SUBSS 239 Op386SUBSD 240 Op386MULSS 241 Op386MULSD 242 Op386DIVSS 243 Op386DIVSD 244 Op386MOVSSload 245 Op386MOVSDload 246 Op386MOVSSconst 247 Op386MOVSDconst 248 Op386MOVSSloadidx1 249 Op386MOVSSloadidx4 250 Op386MOVSDloadidx1 251 Op386MOVSDloadidx8 252 Op386MOVSSstore 253 Op386MOVSDstore 254 Op386MOVSSstoreidx1 255 Op386MOVSSstoreidx4 256 Op386MOVSDstoreidx1 257 Op386MOVSDstoreidx8 258 Op386ADDL 259 Op386ADDLconst 260 Op386ADDLcarry 261 Op386ADDLconstcarry 262 Op386ADCL 263 Op386ADCLconst 264 Op386SUBL 265 Op386SUBLconst 266 Op386SUBLcarry 267 Op386SUBLconstcarry 268 Op386SBBL 269 Op386SBBLconst 270 Op386MULL 271 Op386MULLconst 272 Op386HMULL 273 Op386HMULLU 274 Op386MULLQU 275 Op386AVGLU 276 Op386DIVL 277 Op386DIVW 278 Op386DIVLU 279 Op386DIVWU 280 Op386MODL 281 Op386MODW 282 Op386MODLU 283 Op386MODWU 284 Op386ANDL 285 Op386ANDLconst 286 Op386ORL 287 Op386ORLconst 288 Op386XORL 289 Op386XORLconst 290 Op386CMPL 291 Op386CMPW 292 Op386CMPB 293 Op386CMPLconst 294 Op386CMPWconst 295 Op386CMPBconst 296 Op386UCOMISS 297 Op386UCOMISD 298 Op386TESTL 299 Op386TESTW 300 Op386TESTB 301 Op386TESTLconst 302 Op386TESTWconst 303 Op386TESTBconst 304 Op386SHLL 305 Op386SHLLconst 306 Op386SHRL 307 Op386SHRW 308 Op386SHRB 309 Op386SHRLconst 310 Op386SHRWconst 311 Op386SHRBconst 312 Op386SARL 313 Op386SARW 314 Op386SARB 315 Op386SARLconst 316 Op386SARWconst 317 Op386SARBconst 318 Op386ROLLconst 319 Op386ROLWconst 320 Op386ROLBconst 321 Op386NEGL 322 Op386NOTL 323 Op386BSFL 324 Op386BSFW 325 Op386BSRL 326 Op386BSRW 327 Op386BSWAPL 328 Op386SQRTSD 329 Op386SBBLcarrymask 330 Op386SETEQ 331 Op386SETNE 332 Op386SETL 333 Op386SETLE 334 Op386SETG 335 Op386SETGE 336 Op386SETB 337 Op386SETBE 338 Op386SETA 339 Op386SETAE 340 Op386SETEQF 341 Op386SETNEF 342 Op386SETORD 343 Op386SETNAN 344 Op386SETGF 345 Op386SETGEF 346 Op386MOVBLSX 347 Op386MOVBLZX 348 Op386MOVWLSX 349 Op386MOVWLZX 350 Op386MOVLconst 351 Op386CVTTSD2SL 352 Op386CVTTSS2SL 353 Op386CVTSL2SS 354 Op386CVTSL2SD 355 Op386CVTSD2SS 356 Op386CVTSS2SD 357 Op386PXOR 358 Op386LEAL 359 Op386LEAL1 360 Op386LEAL2 361 Op386LEAL4 362 Op386LEAL8 363 Op386MOVBload 364 Op386MOVBLSXload 365 Op386MOVWload 366 Op386MOVWLSXload 367 Op386MOVLload 368 Op386MOVBstore 369 Op386MOVWstore 370 Op386MOVLstore 371 Op386MOVBloadidx1 372 Op386MOVWloadidx1 373 Op386MOVWloadidx2 374 Op386MOVLloadidx1 375 Op386MOVLloadidx4 376 Op386MOVBstoreidx1 377 Op386MOVWstoreidx1 378 Op386MOVWstoreidx2 379 Op386MOVLstoreidx1 380 Op386MOVLstoreidx4 381 Op386MOVBstoreconst 382 Op386MOVWstoreconst 383 Op386MOVLstoreconst 384 Op386MOVBstoreconstidx1 385 Op386MOVWstoreconstidx1 386 Op386MOVWstoreconstidx2 387 Op386MOVLstoreconstidx1 388 Op386MOVLstoreconstidx4 389 Op386DUFFZERO 390 Op386REPSTOSL 391 Op386CALLstatic 392 Op386CALLclosure 393 Op386CALLinter 394 Op386DUFFCOPY 395 Op386REPMOVSL 396 Op386InvertFlags 397 Op386LoweredGetG 398 Op386LoweredGetClosurePtr 399 Op386LoweredGetCallerPC 400 Op386LoweredGetCallerSP 401 Op386LoweredNilCheck 402 Op386MOVLconvert 403 Op386FlagEQ 404 Op386FlagLT_ULT 405 Op386FlagLT_UGT 406 Op386FlagGT_UGT 407 Op386FlagGT_ULT 408 Op386FCHS 409 Op386MOVSSconst1 410 Op386MOVSDconst1 411 Op386MOVSSconst2 412 Op386MOVSDconst2 413 414 OpAMD64ADDSS 415 OpAMD64ADDSD 416 OpAMD64SUBSS 417 OpAMD64SUBSD 418 OpAMD64MULSS 419 OpAMD64MULSD 420 OpAMD64DIVSS 421 OpAMD64DIVSD 422 OpAMD64MOVSSload 423 OpAMD64MOVSDload 424 OpAMD64MOVSSconst 425 OpAMD64MOVSDconst 426 OpAMD64MOVSSloadidx1 427 OpAMD64MOVSSloadidx4 428 OpAMD64MOVSDloadidx1 429 OpAMD64MOVSDloadidx8 430 OpAMD64MOVSSstore 431 OpAMD64MOVSDstore 432 OpAMD64MOVSSstoreidx1 433 OpAMD64MOVSSstoreidx4 434 OpAMD64MOVSDstoreidx1 435 OpAMD64MOVSDstoreidx8 436 OpAMD64ADDSSmem 437 OpAMD64ADDSDmem 438 OpAMD64SUBSSmem 439 OpAMD64SUBSDmem 440 OpAMD64MULSSmem 441 OpAMD64MULSDmem 442 OpAMD64ADDQ 443 OpAMD64ADDL 444 OpAMD64ADDQconst 445 OpAMD64ADDLconst 446 OpAMD64ADDQconstmem 447 OpAMD64ADDLconstmem 448 OpAMD64SUBQ 449 OpAMD64SUBL 450 OpAMD64SUBQconst 451 OpAMD64SUBLconst 452 OpAMD64MULQ 453 OpAMD64MULL 454 OpAMD64MULQconst 455 OpAMD64MULLconst 456 OpAMD64HMULQ 457 OpAMD64HMULL 458 OpAMD64HMULQU 459 OpAMD64HMULLU 460 OpAMD64AVGQU 461 OpAMD64DIVQ 462 OpAMD64DIVL 463 OpAMD64DIVW 464 OpAMD64DIVQU 465 OpAMD64DIVLU 466 OpAMD64DIVWU 467 OpAMD64MULQU2 468 OpAMD64DIVQU2 469 OpAMD64ANDQ 470 OpAMD64ANDL 471 OpAMD64ANDQconst 472 OpAMD64ANDLconst 473 OpAMD64ORQ 474 OpAMD64ORL 475 OpAMD64ORQconst 476 OpAMD64ORLconst 477 OpAMD64XORQ 478 OpAMD64XORL 479 OpAMD64XORQconst 480 OpAMD64XORLconst 481 OpAMD64CMPQ 482 OpAMD64CMPL 483 OpAMD64CMPW 484 OpAMD64CMPB 485 OpAMD64CMPQconst 486 OpAMD64CMPLconst 487 OpAMD64CMPWconst 488 OpAMD64CMPBconst 489 OpAMD64UCOMISS 490 OpAMD64UCOMISD 491 OpAMD64BTL 492 OpAMD64BTQ 493 OpAMD64BTLconst 494 OpAMD64BTQconst 495 OpAMD64TESTQ 496 OpAMD64TESTL 497 OpAMD64TESTW 498 OpAMD64TESTB 499 OpAMD64TESTQconst 500 OpAMD64TESTLconst 501 OpAMD64TESTWconst 502 OpAMD64TESTBconst 503 OpAMD64SHLQ 504 OpAMD64SHLL 505 OpAMD64SHLQconst 506 OpAMD64SHLLconst 507 OpAMD64SHRQ 508 OpAMD64SHRL 509 OpAMD64SHRW 510 OpAMD64SHRB 511 OpAMD64SHRQconst 512 OpAMD64SHRLconst 513 OpAMD64SHRWconst 514 OpAMD64SHRBconst 515 OpAMD64SARQ 516 OpAMD64SARL 517 OpAMD64SARW 518 OpAMD64SARB 519 OpAMD64SARQconst 520 OpAMD64SARLconst 521 OpAMD64SARWconst 522 OpAMD64SARBconst 523 OpAMD64ROLQ 524 OpAMD64ROLL 525 OpAMD64ROLW 526 OpAMD64ROLB 527 OpAMD64RORQ 528 OpAMD64RORL 529 OpAMD64RORW 530 OpAMD64RORB 531 OpAMD64ROLQconst 532 OpAMD64ROLLconst 533 OpAMD64ROLWconst 534 OpAMD64ROLBconst 535 OpAMD64ADDLmem 536 OpAMD64ADDQmem 537 OpAMD64SUBQmem 538 OpAMD64SUBLmem 539 OpAMD64ANDLmem 540 OpAMD64ANDQmem 541 OpAMD64ORQmem 542 OpAMD64ORLmem 543 OpAMD64XORQmem 544 OpAMD64XORLmem 545 OpAMD64NEGQ 546 OpAMD64NEGL 547 OpAMD64NOTQ 548 OpAMD64NOTL 549 OpAMD64BSFQ 550 OpAMD64BSFL 551 OpAMD64BSRQ 552 OpAMD64BSRL 553 OpAMD64CMOVQEQ 554 OpAMD64CMOVLEQ 555 OpAMD64BSWAPQ 556 OpAMD64BSWAPL 557 OpAMD64POPCNTQ 558 OpAMD64POPCNTL 559 OpAMD64SQRTSD 560 OpAMD64SBBQcarrymask 561 OpAMD64SBBLcarrymask 562 OpAMD64SETEQ 563 OpAMD64SETNE 564 OpAMD64SETL 565 OpAMD64SETLE 566 OpAMD64SETG 567 OpAMD64SETGE 568 OpAMD64SETB 569 OpAMD64SETBE 570 OpAMD64SETA 571 OpAMD64SETAE 572 OpAMD64SETEQmem 573 OpAMD64SETNEmem 574 OpAMD64SETLmem 575 OpAMD64SETLEmem 576 OpAMD64SETGmem 577 OpAMD64SETGEmem 578 OpAMD64SETBmem 579 OpAMD64SETBEmem 580 OpAMD64SETAmem 581 OpAMD64SETAEmem 582 OpAMD64SETEQF 583 OpAMD64SETNEF 584 OpAMD64SETORD 585 OpAMD64SETNAN 586 OpAMD64SETGF 587 OpAMD64SETGEF 588 OpAMD64MOVBQSX 589 OpAMD64MOVBQZX 590 OpAMD64MOVWQSX 591 OpAMD64MOVWQZX 592 OpAMD64MOVLQSX 593 OpAMD64MOVLQZX 594 OpAMD64MOVLconst 595 OpAMD64MOVQconst 596 OpAMD64CVTTSD2SL 597 OpAMD64CVTTSD2SQ 598 OpAMD64CVTTSS2SL 599 OpAMD64CVTTSS2SQ 600 OpAMD64CVTSL2SS 601 OpAMD64CVTSL2SD 602 OpAMD64CVTSQ2SS 603 OpAMD64CVTSQ2SD 604 OpAMD64CVTSD2SS 605 OpAMD64CVTSS2SD 606 OpAMD64MOVQi2f 607 OpAMD64MOVQf2i 608 OpAMD64MOVLi2f 609 OpAMD64MOVLf2i 610 OpAMD64PXOR 611 OpAMD64LEAQ 612 OpAMD64LEAQ1 613 OpAMD64LEAQ2 614 OpAMD64LEAQ4 615 OpAMD64LEAQ8 616 OpAMD64LEAL 617 OpAMD64MOVBload 618 OpAMD64MOVBQSXload 619 OpAMD64MOVWload 620 OpAMD64MOVWQSXload 621 OpAMD64MOVLload 622 OpAMD64MOVLQSXload 623 OpAMD64MOVQload 624 OpAMD64MOVBstore 625 OpAMD64MOVWstore 626 OpAMD64MOVLstore 627 OpAMD64MOVQstore 628 OpAMD64MOVOload 629 OpAMD64MOVOstore 630 OpAMD64MOVBloadidx1 631 OpAMD64MOVWloadidx1 632 OpAMD64MOVWloadidx2 633 OpAMD64MOVLloadidx1 634 OpAMD64MOVLloadidx4 635 OpAMD64MOVLloadidx8 636 OpAMD64MOVQloadidx1 637 OpAMD64MOVQloadidx8 638 OpAMD64MOVBstoreidx1 639 OpAMD64MOVWstoreidx1 640 OpAMD64MOVWstoreidx2 641 OpAMD64MOVLstoreidx1 642 OpAMD64MOVLstoreidx4 643 OpAMD64MOVLstoreidx8 644 OpAMD64MOVQstoreidx1 645 OpAMD64MOVQstoreidx8 646 OpAMD64MOVBstoreconst 647 OpAMD64MOVWstoreconst 648 OpAMD64MOVLstoreconst 649 OpAMD64MOVQstoreconst 650 OpAMD64MOVBstoreconstidx1 651 OpAMD64MOVWstoreconstidx1 652 OpAMD64MOVWstoreconstidx2 653 OpAMD64MOVLstoreconstidx1 654 OpAMD64MOVLstoreconstidx4 655 OpAMD64MOVQstoreconstidx1 656 OpAMD64MOVQstoreconstidx8 657 OpAMD64DUFFZERO 658 OpAMD64MOVOconst 659 OpAMD64REPSTOSQ 660 OpAMD64CALLstatic 661 OpAMD64CALLclosure 662 OpAMD64CALLinter 663 OpAMD64DUFFCOPY 664 OpAMD64REPMOVSQ 665 OpAMD64InvertFlags 666 OpAMD64LoweredGetG 667 OpAMD64LoweredGetClosurePtr 668 OpAMD64LoweredGetCallerPC 669 OpAMD64LoweredGetCallerSP 670 OpAMD64LoweredNilCheck 671 OpAMD64MOVQconvert 672 OpAMD64MOVLconvert 673 OpAMD64FlagEQ 674 OpAMD64FlagLT_ULT 675 OpAMD64FlagLT_UGT 676 OpAMD64FlagGT_UGT 677 OpAMD64FlagGT_ULT 678 OpAMD64MOVLatomicload 679 OpAMD64MOVQatomicload 680 OpAMD64XCHGL 681 OpAMD64XCHGQ 682 OpAMD64XADDLlock 683 OpAMD64XADDQlock 684 OpAMD64AddTupleFirst32 685 OpAMD64AddTupleFirst64 686 OpAMD64CMPXCHGLlock 687 OpAMD64CMPXCHGQlock 688 OpAMD64ANDBlock 689 OpAMD64ORBlock 690 691 OpARMADD 692 OpARMADDconst 693 OpARMSUB 694 OpARMSUBconst 695 OpARMRSB 696 OpARMRSBconst 697 OpARMMUL 698 OpARMHMUL 699 OpARMHMULU 700 OpARMCALLudiv 701 OpARMADDS 702 OpARMADDSconst 703 OpARMADC 704 OpARMADCconst 705 OpARMSUBS 706 OpARMSUBSconst 707 OpARMRSBSconst 708 OpARMSBC 709 OpARMSBCconst 710 OpARMRSCconst 711 OpARMMULLU 712 OpARMMULA 713 OpARMMULS 714 OpARMADDF 715 OpARMADDD 716 OpARMSUBF 717 OpARMSUBD 718 OpARMMULF 719 OpARMMULD 720 OpARMNMULF 721 OpARMNMULD 722 OpARMDIVF 723 OpARMDIVD 724 OpARMMULAF 725 OpARMMULAD 726 OpARMMULSF 727 OpARMMULSD 728 OpARMAND 729 OpARMANDconst 730 OpARMOR 731 OpARMORconst 732 OpARMXOR 733 OpARMXORconst 734 OpARMBIC 735 OpARMBICconst 736 OpARMBFX 737 OpARMBFXU 738 OpARMMVN 739 OpARMNEGF 740 OpARMNEGD 741 OpARMSQRTD 742 OpARMCLZ 743 OpARMREV 744 OpARMRBIT 745 OpARMSLL 746 OpARMSLLconst 747 OpARMSRL 748 OpARMSRLconst 749 OpARMSRA 750 OpARMSRAconst 751 OpARMSRRconst 752 OpARMADDshiftLL 753 OpARMADDshiftRL 754 OpARMADDshiftRA 755 OpARMSUBshiftLL 756 OpARMSUBshiftRL 757 OpARMSUBshiftRA 758 OpARMRSBshiftLL 759 OpARMRSBshiftRL 760 OpARMRSBshiftRA 761 OpARMANDshiftLL 762 OpARMANDshiftRL 763 OpARMANDshiftRA 764 OpARMORshiftLL 765 OpARMORshiftRL 766 OpARMORshiftRA 767 OpARMXORshiftLL 768 OpARMXORshiftRL 769 OpARMXORshiftRA 770 OpARMXORshiftRR 771 OpARMBICshiftLL 772 OpARMBICshiftRL 773 OpARMBICshiftRA 774 OpARMMVNshiftLL 775 OpARMMVNshiftRL 776 OpARMMVNshiftRA 777 OpARMADCshiftLL 778 OpARMADCshiftRL 779 OpARMADCshiftRA 780 OpARMSBCshiftLL 781 OpARMSBCshiftRL 782 OpARMSBCshiftRA 783 OpARMRSCshiftLL 784 OpARMRSCshiftRL 785 OpARMRSCshiftRA 786 OpARMADDSshiftLL 787 OpARMADDSshiftRL 788 OpARMADDSshiftRA 789 OpARMSUBSshiftLL 790 OpARMSUBSshiftRL 791 OpARMSUBSshiftRA 792 OpARMRSBSshiftLL 793 OpARMRSBSshiftRL 794 OpARMRSBSshiftRA 795 OpARMADDshiftLLreg 796 OpARMADDshiftRLreg 797 OpARMADDshiftRAreg 798 OpARMSUBshiftLLreg 799 OpARMSUBshiftRLreg 800 OpARMSUBshiftRAreg 801 OpARMRSBshiftLLreg 802 OpARMRSBshiftRLreg 803 OpARMRSBshiftRAreg 804 OpARMANDshiftLLreg 805 OpARMANDshiftRLreg 806 OpARMANDshiftRAreg 807 OpARMORshiftLLreg 808 OpARMORshiftRLreg 809 OpARMORshiftRAreg 810 OpARMXORshiftLLreg 811 OpARMXORshiftRLreg 812 OpARMXORshiftRAreg 813 OpARMBICshiftLLreg 814 OpARMBICshiftRLreg 815 OpARMBICshiftRAreg 816 OpARMMVNshiftLLreg 817 OpARMMVNshiftRLreg 818 OpARMMVNshiftRAreg 819 OpARMADCshiftLLreg 820 OpARMADCshiftRLreg 821 OpARMADCshiftRAreg 822 OpARMSBCshiftLLreg 823 OpARMSBCshiftRLreg 824 OpARMSBCshiftRAreg 825 OpARMRSCshiftLLreg 826 OpARMRSCshiftRLreg 827 OpARMRSCshiftRAreg 828 OpARMADDSshiftLLreg 829 OpARMADDSshiftRLreg 830 OpARMADDSshiftRAreg 831 OpARMSUBSshiftLLreg 832 OpARMSUBSshiftRLreg 833 OpARMSUBSshiftRAreg 834 OpARMRSBSshiftLLreg 835 OpARMRSBSshiftRLreg 836 OpARMRSBSshiftRAreg 837 OpARMCMP 838 OpARMCMPconst 839 OpARMCMN 840 OpARMCMNconst 841 OpARMTST 842 OpARMTSTconst 843 OpARMTEQ 844 OpARMTEQconst 845 OpARMCMPF 846 OpARMCMPD 847 OpARMCMPshiftLL 848 OpARMCMPshiftRL 849 OpARMCMPshiftRA 850 OpARMCMPshiftLLreg 851 OpARMCMPshiftRLreg 852 OpARMCMPshiftRAreg 853 OpARMCMPF0 854 OpARMCMPD0 855 OpARMMOVWconst 856 OpARMMOVFconst 857 OpARMMOVDconst 858 OpARMMOVWaddr 859 OpARMMOVBload 860 OpARMMOVBUload 861 OpARMMOVHload 862 OpARMMOVHUload 863 OpARMMOVWload 864 OpARMMOVFload 865 OpARMMOVDload 866 OpARMMOVBstore 867 OpARMMOVHstore 868 OpARMMOVWstore 869 OpARMMOVFstore 870 OpARMMOVDstore 871 OpARMMOVWloadidx 872 OpARMMOVWloadshiftLL 873 OpARMMOVWloadshiftRL 874 OpARMMOVWloadshiftRA 875 OpARMMOVBUloadidx 876 OpARMMOVBloadidx 877 OpARMMOVHUloadidx 878 OpARMMOVHloadidx 879 OpARMMOVWstoreidx 880 OpARMMOVWstoreshiftLL 881 OpARMMOVWstoreshiftRL 882 OpARMMOVWstoreshiftRA 883 OpARMMOVBstoreidx 884 OpARMMOVHstoreidx 885 OpARMMOVBreg 886 OpARMMOVBUreg 887 OpARMMOVHreg 888 OpARMMOVHUreg 889 OpARMMOVWreg 890 OpARMMOVWnop 891 OpARMMOVWF 892 OpARMMOVWD 893 OpARMMOVWUF 894 OpARMMOVWUD 895 OpARMMOVFW 896 OpARMMOVDW 897 OpARMMOVFWU 898 OpARMMOVDWU 899 OpARMMOVFD 900 OpARMMOVDF 901 OpARMCMOVWHSconst 902 OpARMCMOVWLSconst 903 OpARMSRAcond 904 OpARMCALLstatic 905 OpARMCALLclosure 906 OpARMCALLinter 907 OpARMLoweredNilCheck 908 OpARMEqual 909 OpARMNotEqual 910 OpARMLessThan 911 OpARMLessEqual 912 OpARMGreaterThan 913 OpARMGreaterEqual 914 OpARMLessThanU 915 OpARMLessEqualU 916 OpARMGreaterThanU 917 OpARMGreaterEqualU 918 OpARMDUFFZERO 919 OpARMDUFFCOPY 920 OpARMLoweredZero 921 OpARMLoweredMove 922 OpARMLoweredGetClosurePtr 923 OpARMLoweredGetCallerSP 924 OpARMMOVWconvert 925 OpARMFlagEQ 926 OpARMFlagLT_ULT 927 OpARMFlagLT_UGT 928 OpARMFlagGT_UGT 929 OpARMFlagGT_ULT 930 OpARMInvertFlags 931 932 OpARM64ADD 933 OpARM64ADDconst 934 OpARM64SUB 935 OpARM64SUBconst 936 OpARM64MUL 937 OpARM64MULW 938 OpARM64MULH 939 OpARM64UMULH 940 OpARM64MULL 941 OpARM64UMULL 942 OpARM64DIV 943 OpARM64UDIV 944 OpARM64DIVW 945 OpARM64UDIVW 946 OpARM64MOD 947 OpARM64UMOD 948 OpARM64MODW 949 OpARM64UMODW 950 OpARM64FADDS 951 OpARM64FADDD 952 OpARM64FSUBS 953 OpARM64FSUBD 954 OpARM64FMULS 955 OpARM64FMULD 956 OpARM64FDIVS 957 OpARM64FDIVD 958 OpARM64AND 959 OpARM64ANDconst 960 OpARM64OR 961 OpARM64ORconst 962 OpARM64XOR 963 OpARM64XORconst 964 OpARM64BIC 965 OpARM64BICconst 966 OpARM64MVN 967 OpARM64NEG 968 OpARM64FNEGS 969 OpARM64FNEGD 970 OpARM64FSQRTD 971 OpARM64REV 972 OpARM64REVW 973 OpARM64REV16W 974 OpARM64RBIT 975 OpARM64RBITW 976 OpARM64CLZ 977 OpARM64CLZW 978 OpARM64SLL 979 OpARM64SLLconst 980 OpARM64SRL 981 OpARM64SRLconst 982 OpARM64SRA 983 OpARM64SRAconst 984 OpARM64RORconst 985 OpARM64RORWconst 986 OpARM64CMP 987 OpARM64CMPconst 988 OpARM64CMPW 989 OpARM64CMPWconst 990 OpARM64CMN 991 OpARM64CMNconst 992 OpARM64CMNW 993 OpARM64CMNWconst 994 OpARM64FCMPS 995 OpARM64FCMPD 996 OpARM64ADDshiftLL 997 OpARM64ADDshiftRL 998 OpARM64ADDshiftRA 999 OpARM64SUBshiftLL 1000 OpARM64SUBshiftRL 1001 OpARM64SUBshiftRA 1002 OpARM64ANDshiftLL 1003 OpARM64ANDshiftRL 1004 OpARM64ANDshiftRA 1005 OpARM64ORshiftLL 1006 OpARM64ORshiftRL 1007 OpARM64ORshiftRA 1008 OpARM64XORshiftLL 1009 OpARM64XORshiftRL 1010 OpARM64XORshiftRA 1011 OpARM64BICshiftLL 1012 OpARM64BICshiftRL 1013 OpARM64BICshiftRA 1014 OpARM64CMPshiftLL 1015 OpARM64CMPshiftRL 1016 OpARM64CMPshiftRA 1017 OpARM64MOVDconst 1018 OpARM64FMOVSconst 1019 OpARM64FMOVDconst 1020 OpARM64MOVDaddr 1021 OpARM64MOVBload 1022 OpARM64MOVBUload 1023 OpARM64MOVHload 1024 OpARM64MOVHUload 1025 OpARM64MOVWload 1026 OpARM64MOVWUload 1027 OpARM64MOVDload 1028 OpARM64FMOVSload 1029 OpARM64FMOVDload 1030 OpARM64MOVBstore 1031 OpARM64MOVHstore 1032 OpARM64MOVWstore 1033 OpARM64MOVDstore 1034 OpARM64STP 1035 OpARM64FMOVSstore 1036 OpARM64FMOVDstore 1037 OpARM64MOVBstorezero 1038 OpARM64MOVHstorezero 1039 OpARM64MOVWstorezero 1040 OpARM64MOVDstorezero 1041 OpARM64MOVQstorezero 1042 OpARM64MOVBreg 1043 OpARM64MOVBUreg 1044 OpARM64MOVHreg 1045 OpARM64MOVHUreg 1046 OpARM64MOVWreg 1047 OpARM64MOVWUreg 1048 OpARM64MOVDreg 1049 OpARM64MOVDnop 1050 OpARM64SCVTFWS 1051 OpARM64SCVTFWD 1052 OpARM64UCVTFWS 1053 OpARM64UCVTFWD 1054 OpARM64SCVTFS 1055 OpARM64SCVTFD 1056 OpARM64UCVTFS 1057 OpARM64UCVTFD 1058 OpARM64FCVTZSSW 1059 OpARM64FCVTZSDW 1060 OpARM64FCVTZUSW 1061 OpARM64FCVTZUDW 1062 OpARM64FCVTZSS 1063 OpARM64FCVTZSD 1064 OpARM64FCVTZUS 1065 OpARM64FCVTZUD 1066 OpARM64FCVTSD 1067 OpARM64FCVTDS 1068 OpARM64CSELULT 1069 OpARM64CSELULT0 1070 OpARM64CALLstatic 1071 OpARM64CALLclosure 1072 OpARM64CALLinter 1073 OpARM64LoweredNilCheck 1074 OpARM64Equal 1075 OpARM64NotEqual 1076 OpARM64LessThan 1077 OpARM64LessEqual 1078 OpARM64GreaterThan 1079 OpARM64GreaterEqual 1080 OpARM64LessThanU 1081 OpARM64LessEqualU 1082 OpARM64GreaterThanU 1083 OpARM64GreaterEqualU 1084 OpARM64DUFFZERO 1085 OpARM64LoweredZero 1086 OpARM64DUFFCOPY 1087 OpARM64LoweredMove 1088 OpARM64LoweredGetClosurePtr 1089 OpARM64LoweredGetCallerSP 1090 OpARM64MOVDconvert 1091 OpARM64FlagEQ 1092 OpARM64FlagLT_ULT 1093 OpARM64FlagLT_UGT 1094 OpARM64FlagGT_UGT 1095 OpARM64FlagGT_ULT 1096 OpARM64InvertFlags 1097 OpARM64LDAR 1098 OpARM64LDARW 1099 OpARM64STLR 1100 OpARM64STLRW 1101 OpARM64LoweredAtomicExchange64 1102 OpARM64LoweredAtomicExchange32 1103 OpARM64LoweredAtomicAdd64 1104 OpARM64LoweredAtomicAdd32 1105 OpARM64LoweredAtomicCas64 1106 OpARM64LoweredAtomicCas32 1107 OpARM64LoweredAtomicAnd8 1108 OpARM64LoweredAtomicOr8 1109 1110 OpMIPSADD 1111 OpMIPSADDconst 1112 OpMIPSSUB 1113 OpMIPSSUBconst 1114 OpMIPSMUL 1115 OpMIPSMULT 1116 OpMIPSMULTU 1117 OpMIPSDIV 1118 OpMIPSDIVU 1119 OpMIPSADDF 1120 OpMIPSADDD 1121 OpMIPSSUBF 1122 OpMIPSSUBD 1123 OpMIPSMULF 1124 OpMIPSMULD 1125 OpMIPSDIVF 1126 OpMIPSDIVD 1127 OpMIPSAND 1128 OpMIPSANDconst 1129 OpMIPSOR 1130 OpMIPSORconst 1131 OpMIPSXOR 1132 OpMIPSXORconst 1133 OpMIPSNOR 1134 OpMIPSNORconst 1135 OpMIPSNEG 1136 OpMIPSNEGF 1137 OpMIPSNEGD 1138 OpMIPSSQRTD 1139 OpMIPSSLL 1140 OpMIPSSLLconst 1141 OpMIPSSRL 1142 OpMIPSSRLconst 1143 OpMIPSSRA 1144 OpMIPSSRAconst 1145 OpMIPSCLZ 1146 OpMIPSSGT 1147 OpMIPSSGTconst 1148 OpMIPSSGTzero 1149 OpMIPSSGTU 1150 OpMIPSSGTUconst 1151 OpMIPSSGTUzero 1152 OpMIPSCMPEQF 1153 OpMIPSCMPEQD 1154 OpMIPSCMPGEF 1155 OpMIPSCMPGED 1156 OpMIPSCMPGTF 1157 OpMIPSCMPGTD 1158 OpMIPSMOVWconst 1159 OpMIPSMOVFconst 1160 OpMIPSMOVDconst 1161 OpMIPSMOVWaddr 1162 OpMIPSMOVBload 1163 OpMIPSMOVBUload 1164 OpMIPSMOVHload 1165 OpMIPSMOVHUload 1166 OpMIPSMOVWload 1167 OpMIPSMOVFload 1168 OpMIPSMOVDload 1169 OpMIPSMOVBstore 1170 OpMIPSMOVHstore 1171 OpMIPSMOVWstore 1172 OpMIPSMOVFstore 1173 OpMIPSMOVDstore 1174 OpMIPSMOVBstorezero 1175 OpMIPSMOVHstorezero 1176 OpMIPSMOVWstorezero 1177 OpMIPSMOVBreg 1178 OpMIPSMOVBUreg 1179 OpMIPSMOVHreg 1180 OpMIPSMOVHUreg 1181 OpMIPSMOVWreg 1182 OpMIPSMOVWnop 1183 OpMIPSCMOVZ 1184 OpMIPSCMOVZzero 1185 OpMIPSMOVWF 1186 OpMIPSMOVWD 1187 OpMIPSTRUNCFW 1188 OpMIPSTRUNCDW 1189 OpMIPSMOVFD 1190 OpMIPSMOVDF 1191 OpMIPSCALLstatic 1192 OpMIPSCALLclosure 1193 OpMIPSCALLinter 1194 OpMIPSLoweredAtomicLoad 1195 OpMIPSLoweredAtomicStore 1196 OpMIPSLoweredAtomicStorezero 1197 OpMIPSLoweredAtomicExchange 1198 OpMIPSLoweredAtomicAdd 1199 OpMIPSLoweredAtomicAddconst 1200 OpMIPSLoweredAtomicCas 1201 OpMIPSLoweredAtomicAnd 1202 OpMIPSLoweredAtomicOr 1203 OpMIPSLoweredZero 1204 OpMIPSLoweredMove 1205 OpMIPSLoweredNilCheck 1206 OpMIPSFPFlagTrue 1207 OpMIPSFPFlagFalse 1208 OpMIPSLoweredGetClosurePtr 1209 OpMIPSLoweredGetCallerSP 1210 OpMIPSMOVWconvert 1211 1212 OpMIPS64ADDV 1213 OpMIPS64ADDVconst 1214 OpMIPS64SUBV 1215 OpMIPS64SUBVconst 1216 OpMIPS64MULV 1217 OpMIPS64MULVU 1218 OpMIPS64DIVV 1219 OpMIPS64DIVVU 1220 OpMIPS64ADDF 1221 OpMIPS64ADDD 1222 OpMIPS64SUBF 1223 OpMIPS64SUBD 1224 OpMIPS64MULF 1225 OpMIPS64MULD 1226 OpMIPS64DIVF 1227 OpMIPS64DIVD 1228 OpMIPS64AND 1229 OpMIPS64ANDconst 1230 OpMIPS64OR 1231 OpMIPS64ORconst 1232 OpMIPS64XOR 1233 OpMIPS64XORconst 1234 OpMIPS64NOR 1235 OpMIPS64NORconst 1236 OpMIPS64NEGV 1237 OpMIPS64NEGF 1238 OpMIPS64NEGD 1239 OpMIPS64SLLV 1240 OpMIPS64SLLVconst 1241 OpMIPS64SRLV 1242 OpMIPS64SRLVconst 1243 OpMIPS64SRAV 1244 OpMIPS64SRAVconst 1245 OpMIPS64SGT 1246 OpMIPS64SGTconst 1247 OpMIPS64SGTU 1248 OpMIPS64SGTUconst 1249 OpMIPS64CMPEQF 1250 OpMIPS64CMPEQD 1251 OpMIPS64CMPGEF 1252 OpMIPS64CMPGED 1253 OpMIPS64CMPGTF 1254 OpMIPS64CMPGTD 1255 OpMIPS64MOVVconst 1256 OpMIPS64MOVFconst 1257 OpMIPS64MOVDconst 1258 OpMIPS64MOVVaddr 1259 OpMIPS64MOVBload 1260 OpMIPS64MOVBUload 1261 OpMIPS64MOVHload 1262 OpMIPS64MOVHUload 1263 OpMIPS64MOVWload 1264 OpMIPS64MOVWUload 1265 OpMIPS64MOVVload 1266 OpMIPS64MOVFload 1267 OpMIPS64MOVDload 1268 OpMIPS64MOVBstore 1269 OpMIPS64MOVHstore 1270 OpMIPS64MOVWstore 1271 OpMIPS64MOVVstore 1272 OpMIPS64MOVFstore 1273 OpMIPS64MOVDstore 1274 OpMIPS64MOVBstorezero 1275 OpMIPS64MOVHstorezero 1276 OpMIPS64MOVWstorezero 1277 OpMIPS64MOVVstorezero 1278 OpMIPS64MOVBreg 1279 OpMIPS64MOVBUreg 1280 OpMIPS64MOVHreg 1281 OpMIPS64MOVHUreg 1282 OpMIPS64MOVWreg 1283 OpMIPS64MOVWUreg 1284 OpMIPS64MOVVreg 1285 OpMIPS64MOVVnop 1286 OpMIPS64MOVWF 1287 OpMIPS64MOVWD 1288 OpMIPS64MOVVF 1289 OpMIPS64MOVVD 1290 OpMIPS64TRUNCFW 1291 OpMIPS64TRUNCDW 1292 OpMIPS64TRUNCFV 1293 OpMIPS64TRUNCDV 1294 OpMIPS64MOVFD 1295 OpMIPS64MOVDF 1296 OpMIPS64CALLstatic 1297 OpMIPS64CALLclosure 1298 OpMIPS64CALLinter 1299 OpMIPS64DUFFZERO 1300 OpMIPS64LoweredZero 1301 OpMIPS64LoweredMove 1302 OpMIPS64LoweredAtomicLoad32 1303 OpMIPS64LoweredAtomicLoad64 1304 OpMIPS64LoweredAtomicStore32 1305 OpMIPS64LoweredAtomicStore64 1306 OpMIPS64LoweredAtomicStorezero32 1307 OpMIPS64LoweredAtomicStorezero64 1308 OpMIPS64LoweredAtomicExchange32 1309 OpMIPS64LoweredAtomicExchange64 1310 OpMIPS64LoweredAtomicAdd32 1311 OpMIPS64LoweredAtomicAdd64 1312 OpMIPS64LoweredAtomicAddconst32 1313 OpMIPS64LoweredAtomicAddconst64 1314 OpMIPS64LoweredAtomicCas32 1315 OpMIPS64LoweredAtomicCas64 1316 OpMIPS64LoweredNilCheck 1317 OpMIPS64FPFlagTrue 1318 OpMIPS64FPFlagFalse 1319 OpMIPS64LoweredGetClosurePtr 1320 OpMIPS64LoweredGetCallerSP 1321 OpMIPS64MOVVconvert 1322 1323 OpPPC64ADD 1324 OpPPC64ADDconst 1325 OpPPC64FADD 1326 OpPPC64FADDS 1327 OpPPC64SUB 1328 OpPPC64FSUB 1329 OpPPC64FSUBS 1330 OpPPC64MULLD 1331 OpPPC64MULLW 1332 OpPPC64MULHD 1333 OpPPC64MULHW 1334 OpPPC64MULHDU 1335 OpPPC64MULHWU 1336 OpPPC64FMUL 1337 OpPPC64FMULS 1338 OpPPC64FMADD 1339 OpPPC64FMADDS 1340 OpPPC64FMSUB 1341 OpPPC64FMSUBS 1342 OpPPC64SRAD 1343 OpPPC64SRAW 1344 OpPPC64SRD 1345 OpPPC64SRW 1346 OpPPC64SLD 1347 OpPPC64SLW 1348 OpPPC64ROTL 1349 OpPPC64ROTLW 1350 OpPPC64ADDconstForCarry 1351 OpPPC64MaskIfNotCarry 1352 OpPPC64SRADconst 1353 OpPPC64SRAWconst 1354 OpPPC64SRDconst 1355 OpPPC64SRWconst 1356 OpPPC64SLDconst 1357 OpPPC64SLWconst 1358 OpPPC64ROTLconst 1359 OpPPC64ROTLWconst 1360 OpPPC64CNTLZD 1361 OpPPC64CNTLZW 1362 OpPPC64POPCNTD 1363 OpPPC64POPCNTW 1364 OpPPC64POPCNTB 1365 OpPPC64FDIV 1366 OpPPC64FDIVS 1367 OpPPC64DIVD 1368 OpPPC64DIVW 1369 OpPPC64DIVDU 1370 OpPPC64DIVWU 1371 OpPPC64FCTIDZ 1372 OpPPC64FCTIWZ 1373 OpPPC64FCFID 1374 OpPPC64FCFIDS 1375 OpPPC64FRSP 1376 OpPPC64MFVSRD 1377 OpPPC64MTVSRD 1378 OpPPC64AND 1379 OpPPC64ANDN 1380 OpPPC64OR 1381 OpPPC64ORN 1382 OpPPC64NOR 1383 OpPPC64XOR 1384 OpPPC64EQV 1385 OpPPC64NEG 1386 OpPPC64FNEG 1387 OpPPC64FSQRT 1388 OpPPC64FSQRTS 1389 OpPPC64FFLOOR 1390 OpPPC64FCEIL 1391 OpPPC64FTRUNC 1392 OpPPC64ORconst 1393 OpPPC64XORconst 1394 OpPPC64ANDconst 1395 OpPPC64ANDCCconst 1396 OpPPC64MOVBreg 1397 OpPPC64MOVBZreg 1398 OpPPC64MOVHreg 1399 OpPPC64MOVHZreg 1400 OpPPC64MOVWreg 1401 OpPPC64MOVWZreg 1402 OpPPC64MOVBZload 1403 OpPPC64MOVHload 1404 OpPPC64MOVHZload 1405 OpPPC64MOVWload 1406 OpPPC64MOVWZload 1407 OpPPC64MOVDload 1408 OpPPC64FMOVDload 1409 OpPPC64FMOVSload 1410 OpPPC64MOVBstore 1411 OpPPC64MOVHstore 1412 OpPPC64MOVWstore 1413 OpPPC64MOVDstore 1414 OpPPC64FMOVDstore 1415 OpPPC64FMOVSstore 1416 OpPPC64MOVBstorezero 1417 OpPPC64MOVHstorezero 1418 OpPPC64MOVWstorezero 1419 OpPPC64MOVDstorezero 1420 OpPPC64MOVDaddr 1421 OpPPC64MOVDconst 1422 OpPPC64FMOVDconst 1423 OpPPC64FMOVSconst 1424 OpPPC64FCMPU 1425 OpPPC64CMP 1426 OpPPC64CMPU 1427 OpPPC64CMPW 1428 OpPPC64CMPWU 1429 OpPPC64CMPconst 1430 OpPPC64CMPUconst 1431 OpPPC64CMPWconst 1432 OpPPC64CMPWUconst 1433 OpPPC64Equal 1434 OpPPC64NotEqual 1435 OpPPC64LessThan 1436 OpPPC64FLessThan 1437 OpPPC64LessEqual 1438 OpPPC64FLessEqual 1439 OpPPC64GreaterThan 1440 OpPPC64FGreaterThan 1441 OpPPC64GreaterEqual 1442 OpPPC64FGreaterEqual 1443 OpPPC64LoweredGetClosurePtr 1444 OpPPC64LoweredGetCallerSP 1445 OpPPC64LoweredNilCheck 1446 OpPPC64LoweredRound32F 1447 OpPPC64LoweredRound64F 1448 OpPPC64MOVDconvert 1449 OpPPC64CALLstatic 1450 OpPPC64CALLclosure 1451 OpPPC64CALLinter 1452 OpPPC64LoweredZero 1453 OpPPC64LoweredMove 1454 OpPPC64LoweredAtomicStore32 1455 OpPPC64LoweredAtomicStore64 1456 OpPPC64LoweredAtomicLoad32 1457 OpPPC64LoweredAtomicLoad64 1458 OpPPC64LoweredAtomicLoadPtr 1459 OpPPC64LoweredAtomicAdd32 1460 OpPPC64LoweredAtomicAdd64 1461 OpPPC64LoweredAtomicExchange32 1462 OpPPC64LoweredAtomicExchange64 1463 OpPPC64LoweredAtomicCas64 1464 OpPPC64LoweredAtomicCas32 1465 OpPPC64LoweredAtomicAnd8 1466 OpPPC64LoweredAtomicOr8 1467 OpPPC64InvertFlags 1468 OpPPC64FlagEQ 1469 OpPPC64FlagLT 1470 OpPPC64FlagGT 1471 1472 OpS390XFADDS 1473 OpS390XFADD 1474 OpS390XFSUBS 1475 OpS390XFSUB 1476 OpS390XFMULS 1477 OpS390XFMUL 1478 OpS390XFDIVS 1479 OpS390XFDIV 1480 OpS390XFNEGS 1481 OpS390XFNEG 1482 OpS390XFMADDS 1483 OpS390XFMADD 1484 OpS390XFMSUBS 1485 OpS390XFMSUB 1486 OpS390XFIDBR 1487 OpS390XFMOVSload 1488 OpS390XFMOVDload 1489 OpS390XFMOVSconst 1490 OpS390XFMOVDconst 1491 OpS390XFMOVSloadidx 1492 OpS390XFMOVDloadidx 1493 OpS390XFMOVSstore 1494 OpS390XFMOVDstore 1495 OpS390XFMOVSstoreidx 1496 OpS390XFMOVDstoreidx 1497 OpS390XADD 1498 OpS390XADDW 1499 OpS390XADDconst 1500 OpS390XADDWconst 1501 OpS390XADDload 1502 OpS390XADDWload 1503 OpS390XSUB 1504 OpS390XSUBW 1505 OpS390XSUBconst 1506 OpS390XSUBWconst 1507 OpS390XSUBload 1508 OpS390XSUBWload 1509 OpS390XMULLD 1510 OpS390XMULLW 1511 OpS390XMULLDconst 1512 OpS390XMULLWconst 1513 OpS390XMULLDload 1514 OpS390XMULLWload 1515 OpS390XMULHD 1516 OpS390XMULHDU 1517 OpS390XDIVD 1518 OpS390XDIVW 1519 OpS390XDIVDU 1520 OpS390XDIVWU 1521 OpS390XMODD 1522 OpS390XMODW 1523 OpS390XMODDU 1524 OpS390XMODWU 1525 OpS390XAND 1526 OpS390XANDW 1527 OpS390XANDconst 1528 OpS390XANDWconst 1529 OpS390XANDload 1530 OpS390XANDWload 1531 OpS390XOR 1532 OpS390XORW 1533 OpS390XORconst 1534 OpS390XORWconst 1535 OpS390XORload 1536 OpS390XORWload 1537 OpS390XXOR 1538 OpS390XXORW 1539 OpS390XXORconst 1540 OpS390XXORWconst 1541 OpS390XXORload 1542 OpS390XXORWload 1543 OpS390XCMP 1544 OpS390XCMPW 1545 OpS390XCMPU 1546 OpS390XCMPWU 1547 OpS390XCMPconst 1548 OpS390XCMPWconst 1549 OpS390XCMPUconst 1550 OpS390XCMPWUconst 1551 OpS390XFCMPS 1552 OpS390XFCMP 1553 OpS390XSLD 1554 OpS390XSLW 1555 OpS390XSLDconst 1556 OpS390XSLWconst 1557 OpS390XSRD 1558 OpS390XSRW 1559 OpS390XSRDconst 1560 OpS390XSRWconst 1561 OpS390XSRAD 1562 OpS390XSRAW 1563 OpS390XSRADconst 1564 OpS390XSRAWconst 1565 OpS390XRLLGconst 1566 OpS390XRLLconst 1567 OpS390XNEG 1568 OpS390XNEGW 1569 OpS390XNOT 1570 OpS390XNOTW 1571 OpS390XFSQRT 1572 OpS390XSUBEcarrymask 1573 OpS390XSUBEWcarrymask 1574 OpS390XMOVDEQ 1575 OpS390XMOVDNE 1576 OpS390XMOVDLT 1577 OpS390XMOVDLE 1578 OpS390XMOVDGT 1579 OpS390XMOVDGE 1580 OpS390XMOVDGTnoinv 1581 OpS390XMOVDGEnoinv 1582 OpS390XMOVBreg 1583 OpS390XMOVBZreg 1584 OpS390XMOVHreg 1585 OpS390XMOVHZreg 1586 OpS390XMOVWreg 1587 OpS390XMOVWZreg 1588 OpS390XMOVDreg 1589 OpS390XMOVDnop 1590 OpS390XMOVDconst 1591 OpS390XCFDBRA 1592 OpS390XCGDBRA 1593 OpS390XCFEBRA 1594 OpS390XCGEBRA 1595 OpS390XCEFBRA 1596 OpS390XCDFBRA 1597 OpS390XCEGBRA 1598 OpS390XCDGBRA 1599 OpS390XLEDBR 1600 OpS390XLDEBR 1601 OpS390XMOVDaddr 1602 OpS390XMOVDaddridx 1603 OpS390XMOVBZload 1604 OpS390XMOVBload 1605 OpS390XMOVHZload 1606 OpS390XMOVHload 1607 OpS390XMOVWZload 1608 OpS390XMOVWload 1609 OpS390XMOVDload 1610 OpS390XMOVWBR 1611 OpS390XMOVDBR 1612 OpS390XMOVHBRload 1613 OpS390XMOVWBRload 1614 OpS390XMOVDBRload 1615 OpS390XMOVBstore 1616 OpS390XMOVHstore 1617 OpS390XMOVWstore 1618 OpS390XMOVDstore 1619 OpS390XMOVHBRstore 1620 OpS390XMOVWBRstore 1621 OpS390XMOVDBRstore 1622 OpS390XMVC 1623 OpS390XMOVBZloadidx 1624 OpS390XMOVHZloadidx 1625 OpS390XMOVWZloadidx 1626 OpS390XMOVDloadidx 1627 OpS390XMOVHBRloadidx 1628 OpS390XMOVWBRloadidx 1629 OpS390XMOVDBRloadidx 1630 OpS390XMOVBstoreidx 1631 OpS390XMOVHstoreidx 1632 OpS390XMOVWstoreidx 1633 OpS390XMOVDstoreidx 1634 OpS390XMOVHBRstoreidx 1635 OpS390XMOVWBRstoreidx 1636 OpS390XMOVDBRstoreidx 1637 OpS390XMOVBstoreconst 1638 OpS390XMOVHstoreconst 1639 OpS390XMOVWstoreconst 1640 OpS390XMOVDstoreconst 1641 OpS390XCLEAR 1642 OpS390XCALLstatic 1643 OpS390XCALLclosure 1644 OpS390XCALLinter 1645 OpS390XInvertFlags 1646 OpS390XLoweredGetG 1647 OpS390XLoweredGetClosurePtr 1648 OpS390XLoweredGetCallerSP 1649 OpS390XLoweredNilCheck 1650 OpS390XLoweredRound32F 1651 OpS390XLoweredRound64F 1652 OpS390XMOVDconvert 1653 OpS390XFlagEQ 1654 OpS390XFlagLT 1655 OpS390XFlagGT 1656 OpS390XMOVWZatomicload 1657 OpS390XMOVDatomicload 1658 OpS390XMOVWatomicstore 1659 OpS390XMOVDatomicstore 1660 OpS390XLAA 1661 OpS390XLAAG 1662 OpS390XAddTupleFirst32 1663 OpS390XAddTupleFirst64 1664 OpS390XLoweredAtomicCas32 1665 OpS390XLoweredAtomicCas64 1666 OpS390XLoweredAtomicExchange32 1667 OpS390XLoweredAtomicExchange64 1668 OpS390XFLOGR 1669 OpS390XSTMG2 1670 OpS390XSTMG3 1671 OpS390XSTMG4 1672 OpS390XSTM2 1673 OpS390XSTM3 1674 OpS390XSTM4 1675 OpS390XLoweredMove 1676 OpS390XLoweredZero 1677 1678 OpAdd8 1679 OpAdd16 1680 OpAdd32 1681 OpAdd64 1682 OpAddPtr 1683 OpAdd32F 1684 OpAdd64F 1685 OpSub8 1686 OpSub16 1687 OpSub32 1688 OpSub64 1689 OpSubPtr 1690 OpSub32F 1691 OpSub64F 1692 OpMul8 1693 OpMul16 1694 OpMul32 1695 OpMul64 1696 OpMul32F 1697 OpMul64F 1698 OpDiv32F 1699 OpDiv64F 1700 OpHmul32 1701 OpHmul32u 1702 OpHmul64 1703 OpHmul64u 1704 OpMul32uhilo 1705 OpMul64uhilo 1706 OpAvg32u 1707 OpAvg64u 1708 OpDiv8 1709 OpDiv8u 1710 OpDiv16 1711 OpDiv16u 1712 OpDiv32 1713 OpDiv32u 1714 OpDiv64 1715 OpDiv64u 1716 OpDiv128u 1717 OpMod8 1718 OpMod8u 1719 OpMod16 1720 OpMod16u 1721 OpMod32 1722 OpMod32u 1723 OpMod64 1724 OpMod64u 1725 OpAnd8 1726 OpAnd16 1727 OpAnd32 1728 OpAnd64 1729 OpOr8 1730 OpOr16 1731 OpOr32 1732 OpOr64 1733 OpXor8 1734 OpXor16 1735 OpXor32 1736 OpXor64 1737 OpLsh8x8 1738 OpLsh8x16 1739 OpLsh8x32 1740 OpLsh8x64 1741 OpLsh16x8 1742 OpLsh16x16 1743 OpLsh16x32 1744 OpLsh16x64 1745 OpLsh32x8 1746 OpLsh32x16 1747 OpLsh32x32 1748 OpLsh32x64 1749 OpLsh64x8 1750 OpLsh64x16 1751 OpLsh64x32 1752 OpLsh64x64 1753 OpRsh8x8 1754 OpRsh8x16 1755 OpRsh8x32 1756 OpRsh8x64 1757 OpRsh16x8 1758 OpRsh16x16 1759 OpRsh16x32 1760 OpRsh16x64 1761 OpRsh32x8 1762 OpRsh32x16 1763 OpRsh32x32 1764 OpRsh32x64 1765 OpRsh64x8 1766 OpRsh64x16 1767 OpRsh64x32 1768 OpRsh64x64 1769 OpRsh8Ux8 1770 OpRsh8Ux16 1771 OpRsh8Ux32 1772 OpRsh8Ux64 1773 OpRsh16Ux8 1774 OpRsh16Ux16 1775 OpRsh16Ux32 1776 OpRsh16Ux64 1777 OpRsh32Ux8 1778 OpRsh32Ux16 1779 OpRsh32Ux32 1780 OpRsh32Ux64 1781 OpRsh64Ux8 1782 OpRsh64Ux16 1783 OpRsh64Ux32 1784 OpRsh64Ux64 1785 OpEq8 1786 OpEq16 1787 OpEq32 1788 OpEq64 1789 OpEqPtr 1790 OpEqInter 1791 OpEqSlice 1792 OpEq32F 1793 OpEq64F 1794 OpNeq8 1795 OpNeq16 1796 OpNeq32 1797 OpNeq64 1798 OpNeqPtr 1799 OpNeqInter 1800 OpNeqSlice 1801 OpNeq32F 1802 OpNeq64F 1803 OpLess8 1804 OpLess8U 1805 OpLess16 1806 OpLess16U 1807 OpLess32 1808 OpLess32U 1809 OpLess64 1810 OpLess64U 1811 OpLess32F 1812 OpLess64F 1813 OpLeq8 1814 OpLeq8U 1815 OpLeq16 1816 OpLeq16U 1817 OpLeq32 1818 OpLeq32U 1819 OpLeq64 1820 OpLeq64U 1821 OpLeq32F 1822 OpLeq64F 1823 OpGreater8 1824 OpGreater8U 1825 OpGreater16 1826 OpGreater16U 1827 OpGreater32 1828 OpGreater32U 1829 OpGreater64 1830 OpGreater64U 1831 OpGreater32F 1832 OpGreater64F 1833 OpGeq8 1834 OpGeq8U 1835 OpGeq16 1836 OpGeq16U 1837 OpGeq32 1838 OpGeq32U 1839 OpGeq64 1840 OpGeq64U 1841 OpGeq32F 1842 OpGeq64F 1843 OpAndB 1844 OpOrB 1845 OpEqB 1846 OpNeqB 1847 OpNot 1848 OpNeg8 1849 OpNeg16 1850 OpNeg32 1851 OpNeg64 1852 OpNeg32F 1853 OpNeg64F 1854 OpCom8 1855 OpCom16 1856 OpCom32 1857 OpCom64 1858 OpCtz32 1859 OpCtz64 1860 OpBitLen32 1861 OpBitLen64 1862 OpBswap32 1863 OpBswap64 1864 OpBitRev8 1865 OpBitRev16 1866 OpBitRev32 1867 OpBitRev64 1868 OpPopCount8 1869 OpPopCount16 1870 OpPopCount32 1871 OpPopCount64 1872 OpSqrt 1873 OpFloor 1874 OpCeil 1875 OpTrunc 1876 OpRound 1877 OpPhi 1878 OpCopy 1879 OpConvert 1880 OpConstBool 1881 OpConstString 1882 OpConstNil 1883 OpConst8 1884 OpConst16 1885 OpConst32 1886 OpConst64 1887 OpConst32F 1888 OpConst64F 1889 OpConstInterface 1890 OpConstSlice 1891 OpInitMem 1892 OpArg 1893 OpAddr 1894 OpSP 1895 OpSB 1896 OpLoad 1897 OpStore 1898 OpMove 1899 OpZero 1900 OpStoreWB 1901 OpMoveWB 1902 OpZeroWB 1903 OpClosureCall 1904 OpStaticCall 1905 OpInterCall 1906 OpSignExt8to16 1907 OpSignExt8to32 1908 OpSignExt8to64 1909 OpSignExt16to32 1910 OpSignExt16to64 1911 OpSignExt32to64 1912 OpZeroExt8to16 1913 OpZeroExt8to32 1914 OpZeroExt8to64 1915 OpZeroExt16to32 1916 OpZeroExt16to64 1917 OpZeroExt32to64 1918 OpTrunc16to8 1919 OpTrunc32to8 1920 OpTrunc32to16 1921 OpTrunc64to8 1922 OpTrunc64to16 1923 OpTrunc64to32 1924 OpCvt32to32F 1925 OpCvt32to64F 1926 OpCvt64to32F 1927 OpCvt64to64F 1928 OpCvt32Fto32 1929 OpCvt32Fto64 1930 OpCvt64Fto32 1931 OpCvt64Fto64 1932 OpCvt32Fto64F 1933 OpCvt64Fto32F 1934 OpRound32F 1935 OpRound64F 1936 OpIsNonNil 1937 OpIsInBounds 1938 OpIsSliceInBounds 1939 OpNilCheck 1940 OpGetG 1941 OpGetClosurePtr 1942 OpGetCallerPC 1943 OpGetCallerSP 1944 OpPtrIndex 1945 OpOffPtr 1946 OpSliceMake 1947 OpSlicePtr 1948 OpSliceLen 1949 OpSliceCap 1950 OpComplexMake 1951 OpComplexReal 1952 OpComplexImag 1953 OpStringMake 1954 OpStringPtr 1955 OpStringLen 1956 OpIMake 1957 OpITab 1958 OpIData 1959 OpStructMake0 1960 OpStructMake1 1961 OpStructMake2 1962 OpStructMake3 1963 OpStructMake4 1964 OpStructSelect 1965 OpArrayMake0 1966 OpArrayMake1 1967 OpArraySelect 1968 OpStoreReg 1969 OpLoadReg 1970 OpFwdRef 1971 OpUnknown 1972 OpVarDef 1973 OpVarKill 1974 OpVarLive 1975 OpKeepAlive 1976 OpRegKill 1977 OpInt64Make 1978 OpInt64Hi 1979 OpInt64Lo 1980 OpAdd32carry 1981 OpAdd32withcarry 1982 OpSub32carry 1983 OpSub32withcarry 1984 OpSignmask 1985 OpZeromask 1986 OpSlicemask 1987 OpCvt32Uto32F 1988 OpCvt32Uto64F 1989 OpCvt32Fto32U 1990 OpCvt64Fto32U 1991 OpCvt64Uto32F 1992 OpCvt64Uto64F 1993 OpCvt32Fto64U 1994 OpCvt64Fto64U 1995 OpSelect0 1996 OpSelect1 1997 OpAtomicLoad32 1998 OpAtomicLoad64 1999 OpAtomicLoadPtr 2000 OpAtomicStore32 2001 OpAtomicStore64 2002 OpAtomicStorePtrNoWB 2003 OpAtomicExchange32 2004 OpAtomicExchange64 2005 OpAtomicAdd32 2006 OpAtomicAdd64 2007 OpAtomicCompareAndSwap32 2008 OpAtomicCompareAndSwap64 2009 OpAtomicAnd8 2010 OpAtomicOr8 2011 OpClobber 2012 ) 2013 2014 var opcodeTable = [...]opInfo{ 2015 {name: "OpInvalid"}, 2016 2017 { 2018 name: "ADDSS", 2019 argLen: 2, 2020 commutative: true, 2021 resultInArg0: true, 2022 usesScratch: true, 2023 asm: x86.AADDSS, 2024 reg: regInfo{ 2025 inputs: []inputInfo{ 2026 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2027 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2028 }, 2029 outputs: []outputInfo{ 2030 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2031 }, 2032 }, 2033 }, 2034 { 2035 name: "ADDSD", 2036 argLen: 2, 2037 commutative: true, 2038 resultInArg0: true, 2039 asm: x86.AADDSD, 2040 reg: regInfo{ 2041 inputs: []inputInfo{ 2042 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2043 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2044 }, 2045 outputs: []outputInfo{ 2046 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2047 }, 2048 }, 2049 }, 2050 { 2051 name: "SUBSS", 2052 argLen: 2, 2053 resultInArg0: true, 2054 usesScratch: true, 2055 asm: x86.ASUBSS, 2056 reg: regInfo{ 2057 inputs: []inputInfo{ 2058 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2059 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2060 }, 2061 outputs: []outputInfo{ 2062 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2063 }, 2064 }, 2065 }, 2066 { 2067 name: "SUBSD", 2068 argLen: 2, 2069 resultInArg0: true, 2070 asm: x86.ASUBSD, 2071 reg: regInfo{ 2072 inputs: []inputInfo{ 2073 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2074 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2075 }, 2076 outputs: []outputInfo{ 2077 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2078 }, 2079 }, 2080 }, 2081 { 2082 name: "MULSS", 2083 argLen: 2, 2084 commutative: true, 2085 resultInArg0: true, 2086 usesScratch: true, 2087 asm: x86.AMULSS, 2088 reg: regInfo{ 2089 inputs: []inputInfo{ 2090 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2091 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2092 }, 2093 outputs: []outputInfo{ 2094 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2095 }, 2096 }, 2097 }, 2098 { 2099 name: "MULSD", 2100 argLen: 2, 2101 commutative: true, 2102 resultInArg0: true, 2103 asm: x86.AMULSD, 2104 reg: regInfo{ 2105 inputs: []inputInfo{ 2106 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2107 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2108 }, 2109 outputs: []outputInfo{ 2110 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2111 }, 2112 }, 2113 }, 2114 { 2115 name: "DIVSS", 2116 argLen: 2, 2117 resultInArg0: true, 2118 usesScratch: true, 2119 asm: x86.ADIVSS, 2120 reg: regInfo{ 2121 inputs: []inputInfo{ 2122 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2123 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2124 }, 2125 outputs: []outputInfo{ 2126 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2127 }, 2128 }, 2129 }, 2130 { 2131 name: "DIVSD", 2132 argLen: 2, 2133 resultInArg0: true, 2134 asm: x86.ADIVSD, 2135 reg: regInfo{ 2136 inputs: []inputInfo{ 2137 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2138 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2139 }, 2140 outputs: []outputInfo{ 2141 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2142 }, 2143 }, 2144 }, 2145 { 2146 name: "MOVSSload", 2147 auxType: auxSymOff, 2148 argLen: 2, 2149 faultOnNilArg0: true, 2150 symEffect: SymRead, 2151 asm: x86.AMOVSS, 2152 reg: regInfo{ 2153 inputs: []inputInfo{ 2154 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2155 }, 2156 outputs: []outputInfo{ 2157 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2158 }, 2159 }, 2160 }, 2161 { 2162 name: "MOVSDload", 2163 auxType: auxSymOff, 2164 argLen: 2, 2165 faultOnNilArg0: true, 2166 symEffect: SymRead, 2167 asm: x86.AMOVSD, 2168 reg: regInfo{ 2169 inputs: []inputInfo{ 2170 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2171 }, 2172 outputs: []outputInfo{ 2173 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2174 }, 2175 }, 2176 }, 2177 { 2178 name: "MOVSSconst", 2179 auxType: auxFloat32, 2180 argLen: 0, 2181 rematerializeable: true, 2182 asm: x86.AMOVSS, 2183 reg: regInfo{ 2184 outputs: []outputInfo{ 2185 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2186 }, 2187 }, 2188 }, 2189 { 2190 name: "MOVSDconst", 2191 auxType: auxFloat64, 2192 argLen: 0, 2193 rematerializeable: true, 2194 asm: x86.AMOVSD, 2195 reg: regInfo{ 2196 outputs: []outputInfo{ 2197 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2198 }, 2199 }, 2200 }, 2201 { 2202 name: "MOVSSloadidx1", 2203 auxType: auxSymOff, 2204 argLen: 3, 2205 symEffect: SymRead, 2206 asm: x86.AMOVSS, 2207 reg: regInfo{ 2208 inputs: []inputInfo{ 2209 {1, 255}, // AX CX DX BX SP BP SI DI 2210 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2211 }, 2212 outputs: []outputInfo{ 2213 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2214 }, 2215 }, 2216 }, 2217 { 2218 name: "MOVSSloadidx4", 2219 auxType: auxSymOff, 2220 argLen: 3, 2221 symEffect: SymRead, 2222 asm: x86.AMOVSS, 2223 reg: regInfo{ 2224 inputs: []inputInfo{ 2225 {1, 255}, // AX CX DX BX SP BP SI DI 2226 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2227 }, 2228 outputs: []outputInfo{ 2229 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2230 }, 2231 }, 2232 }, 2233 { 2234 name: "MOVSDloadidx1", 2235 auxType: auxSymOff, 2236 argLen: 3, 2237 symEffect: SymRead, 2238 asm: x86.AMOVSD, 2239 reg: regInfo{ 2240 inputs: []inputInfo{ 2241 {1, 255}, // AX CX DX BX SP BP SI DI 2242 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2243 }, 2244 outputs: []outputInfo{ 2245 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2246 }, 2247 }, 2248 }, 2249 { 2250 name: "MOVSDloadidx8", 2251 auxType: auxSymOff, 2252 argLen: 3, 2253 symEffect: SymRead, 2254 asm: x86.AMOVSD, 2255 reg: regInfo{ 2256 inputs: []inputInfo{ 2257 {1, 255}, // AX CX DX BX SP BP SI DI 2258 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2259 }, 2260 outputs: []outputInfo{ 2261 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2262 }, 2263 }, 2264 }, 2265 { 2266 name: "MOVSSstore", 2267 auxType: auxSymOff, 2268 argLen: 3, 2269 faultOnNilArg0: true, 2270 symEffect: SymWrite, 2271 asm: x86.AMOVSS, 2272 reg: regInfo{ 2273 inputs: []inputInfo{ 2274 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2275 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2276 }, 2277 }, 2278 }, 2279 { 2280 name: "MOVSDstore", 2281 auxType: auxSymOff, 2282 argLen: 3, 2283 faultOnNilArg0: true, 2284 symEffect: SymWrite, 2285 asm: x86.AMOVSD, 2286 reg: regInfo{ 2287 inputs: []inputInfo{ 2288 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2289 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2290 }, 2291 }, 2292 }, 2293 { 2294 name: "MOVSSstoreidx1", 2295 auxType: auxSymOff, 2296 argLen: 4, 2297 symEffect: SymWrite, 2298 asm: x86.AMOVSS, 2299 reg: regInfo{ 2300 inputs: []inputInfo{ 2301 {1, 255}, // AX CX DX BX SP BP SI DI 2302 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2303 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2304 }, 2305 }, 2306 }, 2307 { 2308 name: "MOVSSstoreidx4", 2309 auxType: auxSymOff, 2310 argLen: 4, 2311 symEffect: SymWrite, 2312 asm: x86.AMOVSS, 2313 reg: regInfo{ 2314 inputs: []inputInfo{ 2315 {1, 255}, // AX CX DX BX SP BP SI DI 2316 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2317 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2318 }, 2319 }, 2320 }, 2321 { 2322 name: "MOVSDstoreidx1", 2323 auxType: auxSymOff, 2324 argLen: 4, 2325 symEffect: SymWrite, 2326 asm: x86.AMOVSD, 2327 reg: regInfo{ 2328 inputs: []inputInfo{ 2329 {1, 255}, // AX CX DX BX SP BP SI DI 2330 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2331 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2332 }, 2333 }, 2334 }, 2335 { 2336 name: "MOVSDstoreidx8", 2337 auxType: auxSymOff, 2338 argLen: 4, 2339 symEffect: SymWrite, 2340 asm: x86.AMOVSD, 2341 reg: regInfo{ 2342 inputs: []inputInfo{ 2343 {1, 255}, // AX CX DX BX SP BP SI DI 2344 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2345 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2346 }, 2347 }, 2348 }, 2349 { 2350 name: "ADDL", 2351 argLen: 2, 2352 commutative: true, 2353 clobberFlags: true, 2354 asm: x86.AADDL, 2355 reg: regInfo{ 2356 inputs: []inputInfo{ 2357 {1, 239}, // AX CX DX BX BP SI DI 2358 {0, 255}, // AX CX DX BX SP BP SI DI 2359 }, 2360 outputs: []outputInfo{ 2361 {0, 239}, // AX CX DX BX BP SI DI 2362 }, 2363 }, 2364 }, 2365 { 2366 name: "ADDLconst", 2367 auxType: auxInt32, 2368 argLen: 1, 2369 clobberFlags: true, 2370 asm: x86.AADDL, 2371 reg: regInfo{ 2372 inputs: []inputInfo{ 2373 {0, 255}, // AX CX DX BX SP BP SI DI 2374 }, 2375 outputs: []outputInfo{ 2376 {0, 239}, // AX CX DX BX BP SI DI 2377 }, 2378 }, 2379 }, 2380 { 2381 name: "ADDLcarry", 2382 argLen: 2, 2383 commutative: true, 2384 resultInArg0: true, 2385 asm: x86.AADDL, 2386 reg: regInfo{ 2387 inputs: []inputInfo{ 2388 {0, 239}, // AX CX DX BX BP SI DI 2389 {1, 239}, // AX CX DX BX BP SI DI 2390 }, 2391 outputs: []outputInfo{ 2392 {1, 0}, 2393 {0, 239}, // AX CX DX BX BP SI DI 2394 }, 2395 }, 2396 }, 2397 { 2398 name: "ADDLconstcarry", 2399 auxType: auxInt32, 2400 argLen: 1, 2401 resultInArg0: true, 2402 asm: x86.AADDL, 2403 reg: regInfo{ 2404 inputs: []inputInfo{ 2405 {0, 239}, // AX CX DX BX BP SI DI 2406 }, 2407 outputs: []outputInfo{ 2408 {1, 0}, 2409 {0, 239}, // AX CX DX BX BP SI DI 2410 }, 2411 }, 2412 }, 2413 { 2414 name: "ADCL", 2415 argLen: 3, 2416 commutative: true, 2417 resultInArg0: true, 2418 clobberFlags: true, 2419 asm: x86.AADCL, 2420 reg: regInfo{ 2421 inputs: []inputInfo{ 2422 {0, 239}, // AX CX DX BX BP SI DI 2423 {1, 239}, // AX CX DX BX BP SI DI 2424 }, 2425 outputs: []outputInfo{ 2426 {0, 239}, // AX CX DX BX BP SI DI 2427 }, 2428 }, 2429 }, 2430 { 2431 name: "ADCLconst", 2432 auxType: auxInt32, 2433 argLen: 2, 2434 resultInArg0: true, 2435 clobberFlags: true, 2436 asm: x86.AADCL, 2437 reg: regInfo{ 2438 inputs: []inputInfo{ 2439 {0, 239}, // AX CX DX BX BP SI DI 2440 }, 2441 outputs: []outputInfo{ 2442 {0, 239}, // AX CX DX BX BP SI DI 2443 }, 2444 }, 2445 }, 2446 { 2447 name: "SUBL", 2448 argLen: 2, 2449 resultInArg0: true, 2450 clobberFlags: true, 2451 asm: x86.ASUBL, 2452 reg: regInfo{ 2453 inputs: []inputInfo{ 2454 {0, 239}, // AX CX DX BX BP SI DI 2455 {1, 239}, // AX CX DX BX BP SI DI 2456 }, 2457 outputs: []outputInfo{ 2458 {0, 239}, // AX CX DX BX BP SI DI 2459 }, 2460 }, 2461 }, 2462 { 2463 name: "SUBLconst", 2464 auxType: auxInt32, 2465 argLen: 1, 2466 resultInArg0: true, 2467 clobberFlags: true, 2468 asm: x86.ASUBL, 2469 reg: regInfo{ 2470 inputs: []inputInfo{ 2471 {0, 239}, // AX CX DX BX BP SI DI 2472 }, 2473 outputs: []outputInfo{ 2474 {0, 239}, // AX CX DX BX BP SI DI 2475 }, 2476 }, 2477 }, 2478 { 2479 name: "SUBLcarry", 2480 argLen: 2, 2481 resultInArg0: true, 2482 asm: x86.ASUBL, 2483 reg: regInfo{ 2484 inputs: []inputInfo{ 2485 {0, 239}, // AX CX DX BX BP SI DI 2486 {1, 239}, // AX CX DX BX BP SI DI 2487 }, 2488 outputs: []outputInfo{ 2489 {1, 0}, 2490 {0, 239}, // AX CX DX BX BP SI DI 2491 }, 2492 }, 2493 }, 2494 { 2495 name: "SUBLconstcarry", 2496 auxType: auxInt32, 2497 argLen: 1, 2498 resultInArg0: true, 2499 asm: x86.ASUBL, 2500 reg: regInfo{ 2501 inputs: []inputInfo{ 2502 {0, 239}, // AX CX DX BX BP SI DI 2503 }, 2504 outputs: []outputInfo{ 2505 {1, 0}, 2506 {0, 239}, // AX CX DX BX BP SI DI 2507 }, 2508 }, 2509 }, 2510 { 2511 name: "SBBL", 2512 argLen: 3, 2513 resultInArg0: true, 2514 clobberFlags: true, 2515 asm: x86.ASBBL, 2516 reg: regInfo{ 2517 inputs: []inputInfo{ 2518 {0, 239}, // AX CX DX BX BP SI DI 2519 {1, 239}, // AX CX DX BX BP SI DI 2520 }, 2521 outputs: []outputInfo{ 2522 {0, 239}, // AX CX DX BX BP SI DI 2523 }, 2524 }, 2525 }, 2526 { 2527 name: "SBBLconst", 2528 auxType: auxInt32, 2529 argLen: 2, 2530 resultInArg0: true, 2531 clobberFlags: true, 2532 asm: x86.ASBBL, 2533 reg: regInfo{ 2534 inputs: []inputInfo{ 2535 {0, 239}, // AX CX DX BX BP SI DI 2536 }, 2537 outputs: []outputInfo{ 2538 {0, 239}, // AX CX DX BX BP SI DI 2539 }, 2540 }, 2541 }, 2542 { 2543 name: "MULL", 2544 argLen: 2, 2545 commutative: true, 2546 resultInArg0: true, 2547 clobberFlags: true, 2548 asm: x86.AIMULL, 2549 reg: regInfo{ 2550 inputs: []inputInfo{ 2551 {0, 239}, // AX CX DX BX BP SI DI 2552 {1, 239}, // AX CX DX BX BP SI DI 2553 }, 2554 outputs: []outputInfo{ 2555 {0, 239}, // AX CX DX BX BP SI DI 2556 }, 2557 }, 2558 }, 2559 { 2560 name: "MULLconst", 2561 auxType: auxInt32, 2562 argLen: 1, 2563 resultInArg0: true, 2564 clobberFlags: true, 2565 asm: x86.AIMULL, 2566 reg: regInfo{ 2567 inputs: []inputInfo{ 2568 {0, 239}, // AX CX DX BX BP SI DI 2569 }, 2570 outputs: []outputInfo{ 2571 {0, 239}, // AX CX DX BX BP SI DI 2572 }, 2573 }, 2574 }, 2575 { 2576 name: "HMULL", 2577 argLen: 2, 2578 commutative: true, 2579 clobberFlags: true, 2580 asm: x86.AIMULL, 2581 reg: regInfo{ 2582 inputs: []inputInfo{ 2583 {0, 1}, // AX 2584 {1, 255}, // AX CX DX BX SP BP SI DI 2585 }, 2586 clobbers: 1, // AX 2587 outputs: []outputInfo{ 2588 {0, 4}, // DX 2589 }, 2590 }, 2591 }, 2592 { 2593 name: "HMULLU", 2594 argLen: 2, 2595 commutative: true, 2596 clobberFlags: true, 2597 asm: x86.AMULL, 2598 reg: regInfo{ 2599 inputs: []inputInfo{ 2600 {0, 1}, // AX 2601 {1, 255}, // AX CX DX BX SP BP SI DI 2602 }, 2603 clobbers: 1, // AX 2604 outputs: []outputInfo{ 2605 {0, 4}, // DX 2606 }, 2607 }, 2608 }, 2609 { 2610 name: "MULLQU", 2611 argLen: 2, 2612 commutative: true, 2613 clobberFlags: true, 2614 asm: x86.AMULL, 2615 reg: regInfo{ 2616 inputs: []inputInfo{ 2617 {0, 1}, // AX 2618 {1, 255}, // AX CX DX BX SP BP SI DI 2619 }, 2620 outputs: []outputInfo{ 2621 {0, 4}, // DX 2622 {1, 1}, // AX 2623 }, 2624 }, 2625 }, 2626 { 2627 name: "AVGLU", 2628 argLen: 2, 2629 commutative: true, 2630 resultInArg0: true, 2631 clobberFlags: true, 2632 reg: regInfo{ 2633 inputs: []inputInfo{ 2634 {0, 239}, // AX CX DX BX BP SI DI 2635 {1, 239}, // AX CX DX BX BP SI DI 2636 }, 2637 outputs: []outputInfo{ 2638 {0, 239}, // AX CX DX BX BP SI DI 2639 }, 2640 }, 2641 }, 2642 { 2643 name: "DIVL", 2644 argLen: 2, 2645 clobberFlags: true, 2646 asm: x86.AIDIVL, 2647 reg: regInfo{ 2648 inputs: []inputInfo{ 2649 {0, 1}, // AX 2650 {1, 251}, // AX CX BX SP BP SI DI 2651 }, 2652 clobbers: 4, // DX 2653 outputs: []outputInfo{ 2654 {0, 1}, // AX 2655 }, 2656 }, 2657 }, 2658 { 2659 name: "DIVW", 2660 argLen: 2, 2661 clobberFlags: true, 2662 asm: x86.AIDIVW, 2663 reg: regInfo{ 2664 inputs: []inputInfo{ 2665 {0, 1}, // AX 2666 {1, 251}, // AX CX BX SP BP SI DI 2667 }, 2668 clobbers: 4, // DX 2669 outputs: []outputInfo{ 2670 {0, 1}, // AX 2671 }, 2672 }, 2673 }, 2674 { 2675 name: "DIVLU", 2676 argLen: 2, 2677 clobberFlags: true, 2678 asm: x86.ADIVL, 2679 reg: regInfo{ 2680 inputs: []inputInfo{ 2681 {0, 1}, // AX 2682 {1, 251}, // AX CX BX SP BP SI DI 2683 }, 2684 clobbers: 4, // DX 2685 outputs: []outputInfo{ 2686 {0, 1}, // AX 2687 }, 2688 }, 2689 }, 2690 { 2691 name: "DIVWU", 2692 argLen: 2, 2693 clobberFlags: true, 2694 asm: x86.ADIVW, 2695 reg: regInfo{ 2696 inputs: []inputInfo{ 2697 {0, 1}, // AX 2698 {1, 251}, // AX CX BX SP BP SI DI 2699 }, 2700 clobbers: 4, // DX 2701 outputs: []outputInfo{ 2702 {0, 1}, // AX 2703 }, 2704 }, 2705 }, 2706 { 2707 name: "MODL", 2708 argLen: 2, 2709 clobberFlags: true, 2710 asm: x86.AIDIVL, 2711 reg: regInfo{ 2712 inputs: []inputInfo{ 2713 {0, 1}, // AX 2714 {1, 251}, // AX CX BX SP BP SI DI 2715 }, 2716 clobbers: 1, // AX 2717 outputs: []outputInfo{ 2718 {0, 4}, // DX 2719 }, 2720 }, 2721 }, 2722 { 2723 name: "MODW", 2724 argLen: 2, 2725 clobberFlags: true, 2726 asm: x86.AIDIVW, 2727 reg: regInfo{ 2728 inputs: []inputInfo{ 2729 {0, 1}, // AX 2730 {1, 251}, // AX CX BX SP BP SI DI 2731 }, 2732 clobbers: 1, // AX 2733 outputs: []outputInfo{ 2734 {0, 4}, // DX 2735 }, 2736 }, 2737 }, 2738 { 2739 name: "MODLU", 2740 argLen: 2, 2741 clobberFlags: true, 2742 asm: x86.ADIVL, 2743 reg: regInfo{ 2744 inputs: []inputInfo{ 2745 {0, 1}, // AX 2746 {1, 251}, // AX CX BX SP BP SI DI 2747 }, 2748 clobbers: 1, // AX 2749 outputs: []outputInfo{ 2750 {0, 4}, // DX 2751 }, 2752 }, 2753 }, 2754 { 2755 name: "MODWU", 2756 argLen: 2, 2757 clobberFlags: true, 2758 asm: x86.ADIVW, 2759 reg: regInfo{ 2760 inputs: []inputInfo{ 2761 {0, 1}, // AX 2762 {1, 251}, // AX CX BX SP BP SI DI 2763 }, 2764 clobbers: 1, // AX 2765 outputs: []outputInfo{ 2766 {0, 4}, // DX 2767 }, 2768 }, 2769 }, 2770 { 2771 name: "ANDL", 2772 argLen: 2, 2773 commutative: true, 2774 resultInArg0: true, 2775 clobberFlags: true, 2776 asm: x86.AANDL, 2777 reg: regInfo{ 2778 inputs: []inputInfo{ 2779 {0, 239}, // AX CX DX BX BP SI DI 2780 {1, 239}, // AX CX DX BX BP SI DI 2781 }, 2782 outputs: []outputInfo{ 2783 {0, 239}, // AX CX DX BX BP SI DI 2784 }, 2785 }, 2786 }, 2787 { 2788 name: "ANDLconst", 2789 auxType: auxInt32, 2790 argLen: 1, 2791 resultInArg0: true, 2792 clobberFlags: true, 2793 asm: x86.AANDL, 2794 reg: regInfo{ 2795 inputs: []inputInfo{ 2796 {0, 239}, // AX CX DX BX BP SI DI 2797 }, 2798 outputs: []outputInfo{ 2799 {0, 239}, // AX CX DX BX BP SI DI 2800 }, 2801 }, 2802 }, 2803 { 2804 name: "ORL", 2805 argLen: 2, 2806 commutative: true, 2807 resultInArg0: true, 2808 clobberFlags: true, 2809 asm: x86.AORL, 2810 reg: regInfo{ 2811 inputs: []inputInfo{ 2812 {0, 239}, // AX CX DX BX BP SI DI 2813 {1, 239}, // AX CX DX BX BP SI DI 2814 }, 2815 outputs: []outputInfo{ 2816 {0, 239}, // AX CX DX BX BP SI DI 2817 }, 2818 }, 2819 }, 2820 { 2821 name: "ORLconst", 2822 auxType: auxInt32, 2823 argLen: 1, 2824 resultInArg0: true, 2825 clobberFlags: true, 2826 asm: x86.AORL, 2827 reg: regInfo{ 2828 inputs: []inputInfo{ 2829 {0, 239}, // AX CX DX BX BP SI DI 2830 }, 2831 outputs: []outputInfo{ 2832 {0, 239}, // AX CX DX BX BP SI DI 2833 }, 2834 }, 2835 }, 2836 { 2837 name: "XORL", 2838 argLen: 2, 2839 commutative: true, 2840 resultInArg0: true, 2841 clobberFlags: true, 2842 asm: x86.AXORL, 2843 reg: regInfo{ 2844 inputs: []inputInfo{ 2845 {0, 239}, // AX CX DX BX BP SI DI 2846 {1, 239}, // AX CX DX BX BP SI DI 2847 }, 2848 outputs: []outputInfo{ 2849 {0, 239}, // AX CX DX BX BP SI DI 2850 }, 2851 }, 2852 }, 2853 { 2854 name: "XORLconst", 2855 auxType: auxInt32, 2856 argLen: 1, 2857 resultInArg0: true, 2858 clobberFlags: true, 2859 asm: x86.AXORL, 2860 reg: regInfo{ 2861 inputs: []inputInfo{ 2862 {0, 239}, // AX CX DX BX BP SI DI 2863 }, 2864 outputs: []outputInfo{ 2865 {0, 239}, // AX CX DX BX BP SI DI 2866 }, 2867 }, 2868 }, 2869 { 2870 name: "CMPL", 2871 argLen: 2, 2872 asm: x86.ACMPL, 2873 reg: regInfo{ 2874 inputs: []inputInfo{ 2875 {0, 255}, // AX CX DX BX SP BP SI DI 2876 {1, 255}, // AX CX DX BX SP BP SI DI 2877 }, 2878 }, 2879 }, 2880 { 2881 name: "CMPW", 2882 argLen: 2, 2883 asm: x86.ACMPW, 2884 reg: regInfo{ 2885 inputs: []inputInfo{ 2886 {0, 255}, // AX CX DX BX SP BP SI DI 2887 {1, 255}, // AX CX DX BX SP BP SI DI 2888 }, 2889 }, 2890 }, 2891 { 2892 name: "CMPB", 2893 argLen: 2, 2894 asm: x86.ACMPB, 2895 reg: regInfo{ 2896 inputs: []inputInfo{ 2897 {0, 255}, // AX CX DX BX SP BP SI DI 2898 {1, 255}, // AX CX DX BX SP BP SI DI 2899 }, 2900 }, 2901 }, 2902 { 2903 name: "CMPLconst", 2904 auxType: auxInt32, 2905 argLen: 1, 2906 asm: x86.ACMPL, 2907 reg: regInfo{ 2908 inputs: []inputInfo{ 2909 {0, 255}, // AX CX DX BX SP BP SI DI 2910 }, 2911 }, 2912 }, 2913 { 2914 name: "CMPWconst", 2915 auxType: auxInt16, 2916 argLen: 1, 2917 asm: x86.ACMPW, 2918 reg: regInfo{ 2919 inputs: []inputInfo{ 2920 {0, 255}, // AX CX DX BX SP BP SI DI 2921 }, 2922 }, 2923 }, 2924 { 2925 name: "CMPBconst", 2926 auxType: auxInt8, 2927 argLen: 1, 2928 asm: x86.ACMPB, 2929 reg: regInfo{ 2930 inputs: []inputInfo{ 2931 {0, 255}, // AX CX DX BX SP BP SI DI 2932 }, 2933 }, 2934 }, 2935 { 2936 name: "UCOMISS", 2937 argLen: 2, 2938 usesScratch: true, 2939 asm: x86.AUCOMISS, 2940 reg: regInfo{ 2941 inputs: []inputInfo{ 2942 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2943 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2944 }, 2945 }, 2946 }, 2947 { 2948 name: "UCOMISD", 2949 argLen: 2, 2950 usesScratch: true, 2951 asm: x86.AUCOMISD, 2952 reg: regInfo{ 2953 inputs: []inputInfo{ 2954 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2955 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2956 }, 2957 }, 2958 }, 2959 { 2960 name: "TESTL", 2961 argLen: 2, 2962 commutative: true, 2963 asm: x86.ATESTL, 2964 reg: regInfo{ 2965 inputs: []inputInfo{ 2966 {0, 255}, // AX CX DX BX SP BP SI DI 2967 {1, 255}, // AX CX DX BX SP BP SI DI 2968 }, 2969 }, 2970 }, 2971 { 2972 name: "TESTW", 2973 argLen: 2, 2974 commutative: true, 2975 asm: x86.ATESTW, 2976 reg: regInfo{ 2977 inputs: []inputInfo{ 2978 {0, 255}, // AX CX DX BX SP BP SI DI 2979 {1, 255}, // AX CX DX BX SP BP SI DI 2980 }, 2981 }, 2982 }, 2983 { 2984 name: "TESTB", 2985 argLen: 2, 2986 commutative: true, 2987 asm: x86.ATESTB, 2988 reg: regInfo{ 2989 inputs: []inputInfo{ 2990 {0, 255}, // AX CX DX BX SP BP SI DI 2991 {1, 255}, // AX CX DX BX SP BP SI DI 2992 }, 2993 }, 2994 }, 2995 { 2996 name: "TESTLconst", 2997 auxType: auxInt32, 2998 argLen: 1, 2999 asm: x86.ATESTL, 3000 reg: regInfo{ 3001 inputs: []inputInfo{ 3002 {0, 255}, // AX CX DX BX SP BP SI DI 3003 }, 3004 }, 3005 }, 3006 { 3007 name: "TESTWconst", 3008 auxType: auxInt16, 3009 argLen: 1, 3010 asm: x86.ATESTW, 3011 reg: regInfo{ 3012 inputs: []inputInfo{ 3013 {0, 255}, // AX CX DX BX SP BP SI DI 3014 }, 3015 }, 3016 }, 3017 { 3018 name: "TESTBconst", 3019 auxType: auxInt8, 3020 argLen: 1, 3021 asm: x86.ATESTB, 3022 reg: regInfo{ 3023 inputs: []inputInfo{ 3024 {0, 255}, // AX CX DX BX SP BP SI DI 3025 }, 3026 }, 3027 }, 3028 { 3029 name: "SHLL", 3030 argLen: 2, 3031 resultInArg0: true, 3032 clobberFlags: true, 3033 asm: x86.ASHLL, 3034 reg: regInfo{ 3035 inputs: []inputInfo{ 3036 {1, 2}, // CX 3037 {0, 239}, // AX CX DX BX BP SI DI 3038 }, 3039 outputs: []outputInfo{ 3040 {0, 239}, // AX CX DX BX BP SI DI 3041 }, 3042 }, 3043 }, 3044 { 3045 name: "SHLLconst", 3046 auxType: auxInt32, 3047 argLen: 1, 3048 resultInArg0: true, 3049 clobberFlags: true, 3050 asm: x86.ASHLL, 3051 reg: regInfo{ 3052 inputs: []inputInfo{ 3053 {0, 239}, // AX CX DX BX BP SI DI 3054 }, 3055 outputs: []outputInfo{ 3056 {0, 239}, // AX CX DX BX BP SI DI 3057 }, 3058 }, 3059 }, 3060 { 3061 name: "SHRL", 3062 argLen: 2, 3063 resultInArg0: true, 3064 clobberFlags: true, 3065 asm: x86.ASHRL, 3066 reg: regInfo{ 3067 inputs: []inputInfo{ 3068 {1, 2}, // CX 3069 {0, 239}, // AX CX DX BX BP SI DI 3070 }, 3071 outputs: []outputInfo{ 3072 {0, 239}, // AX CX DX BX BP SI DI 3073 }, 3074 }, 3075 }, 3076 { 3077 name: "SHRW", 3078 argLen: 2, 3079 resultInArg0: true, 3080 clobberFlags: true, 3081 asm: x86.ASHRW, 3082 reg: regInfo{ 3083 inputs: []inputInfo{ 3084 {1, 2}, // CX 3085 {0, 239}, // AX CX DX BX BP SI DI 3086 }, 3087 outputs: []outputInfo{ 3088 {0, 239}, // AX CX DX BX BP SI DI 3089 }, 3090 }, 3091 }, 3092 { 3093 name: "SHRB", 3094 argLen: 2, 3095 resultInArg0: true, 3096 clobberFlags: true, 3097 asm: x86.ASHRB, 3098 reg: regInfo{ 3099 inputs: []inputInfo{ 3100 {1, 2}, // CX 3101 {0, 239}, // AX CX DX BX BP SI DI 3102 }, 3103 outputs: []outputInfo{ 3104 {0, 239}, // AX CX DX BX BP SI DI 3105 }, 3106 }, 3107 }, 3108 { 3109 name: "SHRLconst", 3110 auxType: auxInt32, 3111 argLen: 1, 3112 resultInArg0: true, 3113 clobberFlags: true, 3114 asm: x86.ASHRL, 3115 reg: regInfo{ 3116 inputs: []inputInfo{ 3117 {0, 239}, // AX CX DX BX BP SI DI 3118 }, 3119 outputs: []outputInfo{ 3120 {0, 239}, // AX CX DX BX BP SI DI 3121 }, 3122 }, 3123 }, 3124 { 3125 name: "SHRWconst", 3126 auxType: auxInt16, 3127 argLen: 1, 3128 resultInArg0: true, 3129 clobberFlags: true, 3130 asm: x86.ASHRW, 3131 reg: regInfo{ 3132 inputs: []inputInfo{ 3133 {0, 239}, // AX CX DX BX BP SI DI 3134 }, 3135 outputs: []outputInfo{ 3136 {0, 239}, // AX CX DX BX BP SI DI 3137 }, 3138 }, 3139 }, 3140 { 3141 name: "SHRBconst", 3142 auxType: auxInt8, 3143 argLen: 1, 3144 resultInArg0: true, 3145 clobberFlags: true, 3146 asm: x86.ASHRB, 3147 reg: regInfo{ 3148 inputs: []inputInfo{ 3149 {0, 239}, // AX CX DX BX BP SI DI 3150 }, 3151 outputs: []outputInfo{ 3152 {0, 239}, // AX CX DX BX BP SI DI 3153 }, 3154 }, 3155 }, 3156 { 3157 name: "SARL", 3158 argLen: 2, 3159 resultInArg0: true, 3160 clobberFlags: true, 3161 asm: x86.ASARL, 3162 reg: regInfo{ 3163 inputs: []inputInfo{ 3164 {1, 2}, // CX 3165 {0, 239}, // AX CX DX BX BP SI DI 3166 }, 3167 outputs: []outputInfo{ 3168 {0, 239}, // AX CX DX BX BP SI DI 3169 }, 3170 }, 3171 }, 3172 { 3173 name: "SARW", 3174 argLen: 2, 3175 resultInArg0: true, 3176 clobberFlags: true, 3177 asm: x86.ASARW, 3178 reg: regInfo{ 3179 inputs: []inputInfo{ 3180 {1, 2}, // CX 3181 {0, 239}, // AX CX DX BX BP SI DI 3182 }, 3183 outputs: []outputInfo{ 3184 {0, 239}, // AX CX DX BX BP SI DI 3185 }, 3186 }, 3187 }, 3188 { 3189 name: "SARB", 3190 argLen: 2, 3191 resultInArg0: true, 3192 clobberFlags: true, 3193 asm: x86.ASARB, 3194 reg: regInfo{ 3195 inputs: []inputInfo{ 3196 {1, 2}, // CX 3197 {0, 239}, // AX CX DX BX BP SI DI 3198 }, 3199 outputs: []outputInfo{ 3200 {0, 239}, // AX CX DX BX BP SI DI 3201 }, 3202 }, 3203 }, 3204 { 3205 name: "SARLconst", 3206 auxType: auxInt32, 3207 argLen: 1, 3208 resultInArg0: true, 3209 clobberFlags: true, 3210 asm: x86.ASARL, 3211 reg: regInfo{ 3212 inputs: []inputInfo{ 3213 {0, 239}, // AX CX DX BX BP SI DI 3214 }, 3215 outputs: []outputInfo{ 3216 {0, 239}, // AX CX DX BX BP SI DI 3217 }, 3218 }, 3219 }, 3220 { 3221 name: "SARWconst", 3222 auxType: auxInt16, 3223 argLen: 1, 3224 resultInArg0: true, 3225 clobberFlags: true, 3226 asm: x86.ASARW, 3227 reg: regInfo{ 3228 inputs: []inputInfo{ 3229 {0, 239}, // AX CX DX BX BP SI DI 3230 }, 3231 outputs: []outputInfo{ 3232 {0, 239}, // AX CX DX BX BP SI DI 3233 }, 3234 }, 3235 }, 3236 { 3237 name: "SARBconst", 3238 auxType: auxInt8, 3239 argLen: 1, 3240 resultInArg0: true, 3241 clobberFlags: true, 3242 asm: x86.ASARB, 3243 reg: regInfo{ 3244 inputs: []inputInfo{ 3245 {0, 239}, // AX CX DX BX BP SI DI 3246 }, 3247 outputs: []outputInfo{ 3248 {0, 239}, // AX CX DX BX BP SI DI 3249 }, 3250 }, 3251 }, 3252 { 3253 name: "ROLLconst", 3254 auxType: auxInt32, 3255 argLen: 1, 3256 resultInArg0: true, 3257 clobberFlags: true, 3258 asm: x86.AROLL, 3259 reg: regInfo{ 3260 inputs: []inputInfo{ 3261 {0, 239}, // AX CX DX BX BP SI DI 3262 }, 3263 outputs: []outputInfo{ 3264 {0, 239}, // AX CX DX BX BP SI DI 3265 }, 3266 }, 3267 }, 3268 { 3269 name: "ROLWconst", 3270 auxType: auxInt16, 3271 argLen: 1, 3272 resultInArg0: true, 3273 clobberFlags: true, 3274 asm: x86.AROLW, 3275 reg: regInfo{ 3276 inputs: []inputInfo{ 3277 {0, 239}, // AX CX DX BX BP SI DI 3278 }, 3279 outputs: []outputInfo{ 3280 {0, 239}, // AX CX DX BX BP SI DI 3281 }, 3282 }, 3283 }, 3284 { 3285 name: "ROLBconst", 3286 auxType: auxInt8, 3287 argLen: 1, 3288 resultInArg0: true, 3289 clobberFlags: true, 3290 asm: x86.AROLB, 3291 reg: regInfo{ 3292 inputs: []inputInfo{ 3293 {0, 239}, // AX CX DX BX BP SI DI 3294 }, 3295 outputs: []outputInfo{ 3296 {0, 239}, // AX CX DX BX BP SI DI 3297 }, 3298 }, 3299 }, 3300 { 3301 name: "NEGL", 3302 argLen: 1, 3303 resultInArg0: true, 3304 clobberFlags: true, 3305 asm: x86.ANEGL, 3306 reg: regInfo{ 3307 inputs: []inputInfo{ 3308 {0, 239}, // AX CX DX BX BP SI DI 3309 }, 3310 outputs: []outputInfo{ 3311 {0, 239}, // AX CX DX BX BP SI DI 3312 }, 3313 }, 3314 }, 3315 { 3316 name: "NOTL", 3317 argLen: 1, 3318 resultInArg0: true, 3319 clobberFlags: true, 3320 asm: x86.ANOTL, 3321 reg: regInfo{ 3322 inputs: []inputInfo{ 3323 {0, 239}, // AX CX DX BX BP SI DI 3324 }, 3325 outputs: []outputInfo{ 3326 {0, 239}, // AX CX DX BX BP SI DI 3327 }, 3328 }, 3329 }, 3330 { 3331 name: "BSFL", 3332 argLen: 1, 3333 clobberFlags: true, 3334 asm: x86.ABSFL, 3335 reg: regInfo{ 3336 inputs: []inputInfo{ 3337 {0, 239}, // AX CX DX BX BP SI DI 3338 }, 3339 outputs: []outputInfo{ 3340 {0, 239}, // AX CX DX BX BP SI DI 3341 }, 3342 }, 3343 }, 3344 { 3345 name: "BSFW", 3346 argLen: 1, 3347 clobberFlags: true, 3348 asm: x86.ABSFW, 3349 reg: regInfo{ 3350 inputs: []inputInfo{ 3351 {0, 239}, // AX CX DX BX BP SI DI 3352 }, 3353 outputs: []outputInfo{ 3354 {0, 239}, // AX CX DX BX BP SI DI 3355 }, 3356 }, 3357 }, 3358 { 3359 name: "BSRL", 3360 argLen: 1, 3361 clobberFlags: true, 3362 asm: x86.ABSRL, 3363 reg: regInfo{ 3364 inputs: []inputInfo{ 3365 {0, 239}, // AX CX DX BX BP SI DI 3366 }, 3367 outputs: []outputInfo{ 3368 {0, 239}, // AX CX DX BX BP SI DI 3369 }, 3370 }, 3371 }, 3372 { 3373 name: "BSRW", 3374 argLen: 1, 3375 clobberFlags: true, 3376 asm: x86.ABSRW, 3377 reg: regInfo{ 3378 inputs: []inputInfo{ 3379 {0, 239}, // AX CX DX BX BP SI DI 3380 }, 3381 outputs: []outputInfo{ 3382 {0, 239}, // AX CX DX BX BP SI DI 3383 }, 3384 }, 3385 }, 3386 { 3387 name: "BSWAPL", 3388 argLen: 1, 3389 resultInArg0: true, 3390 clobberFlags: true, 3391 asm: x86.ABSWAPL, 3392 reg: regInfo{ 3393 inputs: []inputInfo{ 3394 {0, 239}, // AX CX DX BX BP SI DI 3395 }, 3396 outputs: []outputInfo{ 3397 {0, 239}, // AX CX DX BX BP SI DI 3398 }, 3399 }, 3400 }, 3401 { 3402 name: "SQRTSD", 3403 argLen: 1, 3404 asm: x86.ASQRTSD, 3405 reg: regInfo{ 3406 inputs: []inputInfo{ 3407 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3408 }, 3409 outputs: []outputInfo{ 3410 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3411 }, 3412 }, 3413 }, 3414 { 3415 name: "SBBLcarrymask", 3416 argLen: 1, 3417 asm: x86.ASBBL, 3418 reg: regInfo{ 3419 outputs: []outputInfo{ 3420 {0, 239}, // AX CX DX BX BP SI DI 3421 }, 3422 }, 3423 }, 3424 { 3425 name: "SETEQ", 3426 argLen: 1, 3427 asm: x86.ASETEQ, 3428 reg: regInfo{ 3429 outputs: []outputInfo{ 3430 {0, 239}, // AX CX DX BX BP SI DI 3431 }, 3432 }, 3433 }, 3434 { 3435 name: "SETNE", 3436 argLen: 1, 3437 asm: x86.ASETNE, 3438 reg: regInfo{ 3439 outputs: []outputInfo{ 3440 {0, 239}, // AX CX DX BX BP SI DI 3441 }, 3442 }, 3443 }, 3444 { 3445 name: "SETL", 3446 argLen: 1, 3447 asm: x86.ASETLT, 3448 reg: regInfo{ 3449 outputs: []outputInfo{ 3450 {0, 239}, // AX CX DX BX BP SI DI 3451 }, 3452 }, 3453 }, 3454 { 3455 name: "SETLE", 3456 argLen: 1, 3457 asm: x86.ASETLE, 3458 reg: regInfo{ 3459 outputs: []outputInfo{ 3460 {0, 239}, // AX CX DX BX BP SI DI 3461 }, 3462 }, 3463 }, 3464 { 3465 name: "SETG", 3466 argLen: 1, 3467 asm: x86.ASETGT, 3468 reg: regInfo{ 3469 outputs: []outputInfo{ 3470 {0, 239}, // AX CX DX BX BP SI DI 3471 }, 3472 }, 3473 }, 3474 { 3475 name: "SETGE", 3476 argLen: 1, 3477 asm: x86.ASETGE, 3478 reg: regInfo{ 3479 outputs: []outputInfo{ 3480 {0, 239}, // AX CX DX BX BP SI DI 3481 }, 3482 }, 3483 }, 3484 { 3485 name: "SETB", 3486 argLen: 1, 3487 asm: x86.ASETCS, 3488 reg: regInfo{ 3489 outputs: []outputInfo{ 3490 {0, 239}, // AX CX DX BX BP SI DI 3491 }, 3492 }, 3493 }, 3494 { 3495 name: "SETBE", 3496 argLen: 1, 3497 asm: x86.ASETLS, 3498 reg: regInfo{ 3499 outputs: []outputInfo{ 3500 {0, 239}, // AX CX DX BX BP SI DI 3501 }, 3502 }, 3503 }, 3504 { 3505 name: "SETA", 3506 argLen: 1, 3507 asm: x86.ASETHI, 3508 reg: regInfo{ 3509 outputs: []outputInfo{ 3510 {0, 239}, // AX CX DX BX BP SI DI 3511 }, 3512 }, 3513 }, 3514 { 3515 name: "SETAE", 3516 argLen: 1, 3517 asm: x86.ASETCC, 3518 reg: regInfo{ 3519 outputs: []outputInfo{ 3520 {0, 239}, // AX CX DX BX BP SI DI 3521 }, 3522 }, 3523 }, 3524 { 3525 name: "SETEQF", 3526 argLen: 1, 3527 clobberFlags: true, 3528 asm: x86.ASETEQ, 3529 reg: regInfo{ 3530 clobbers: 1, // AX 3531 outputs: []outputInfo{ 3532 {0, 238}, // CX DX BX BP SI DI 3533 }, 3534 }, 3535 }, 3536 { 3537 name: "SETNEF", 3538 argLen: 1, 3539 clobberFlags: true, 3540 asm: x86.ASETNE, 3541 reg: regInfo{ 3542 clobbers: 1, // AX 3543 outputs: []outputInfo{ 3544 {0, 238}, // CX DX BX BP SI DI 3545 }, 3546 }, 3547 }, 3548 { 3549 name: "SETORD", 3550 argLen: 1, 3551 asm: x86.ASETPC, 3552 reg: regInfo{ 3553 outputs: []outputInfo{ 3554 {0, 239}, // AX CX DX BX BP SI DI 3555 }, 3556 }, 3557 }, 3558 { 3559 name: "SETNAN", 3560 argLen: 1, 3561 asm: x86.ASETPS, 3562 reg: regInfo{ 3563 outputs: []outputInfo{ 3564 {0, 239}, // AX CX DX BX BP SI DI 3565 }, 3566 }, 3567 }, 3568 { 3569 name: "SETGF", 3570 argLen: 1, 3571 asm: x86.ASETHI, 3572 reg: regInfo{ 3573 outputs: []outputInfo{ 3574 {0, 239}, // AX CX DX BX BP SI DI 3575 }, 3576 }, 3577 }, 3578 { 3579 name: "SETGEF", 3580 argLen: 1, 3581 asm: x86.ASETCC, 3582 reg: regInfo{ 3583 outputs: []outputInfo{ 3584 {0, 239}, // AX CX DX BX BP SI DI 3585 }, 3586 }, 3587 }, 3588 { 3589 name: "MOVBLSX", 3590 argLen: 1, 3591 asm: x86.AMOVBLSX, 3592 reg: regInfo{ 3593 inputs: []inputInfo{ 3594 {0, 239}, // AX CX DX BX BP SI DI 3595 }, 3596 outputs: []outputInfo{ 3597 {0, 239}, // AX CX DX BX BP SI DI 3598 }, 3599 }, 3600 }, 3601 { 3602 name: "MOVBLZX", 3603 argLen: 1, 3604 asm: x86.AMOVBLZX, 3605 reg: regInfo{ 3606 inputs: []inputInfo{ 3607 {0, 239}, // AX CX DX BX BP SI DI 3608 }, 3609 outputs: []outputInfo{ 3610 {0, 239}, // AX CX DX BX BP SI DI 3611 }, 3612 }, 3613 }, 3614 { 3615 name: "MOVWLSX", 3616 argLen: 1, 3617 asm: x86.AMOVWLSX, 3618 reg: regInfo{ 3619 inputs: []inputInfo{ 3620 {0, 239}, // AX CX DX BX BP SI DI 3621 }, 3622 outputs: []outputInfo{ 3623 {0, 239}, // AX CX DX BX BP SI DI 3624 }, 3625 }, 3626 }, 3627 { 3628 name: "MOVWLZX", 3629 argLen: 1, 3630 asm: x86.AMOVWLZX, 3631 reg: regInfo{ 3632 inputs: []inputInfo{ 3633 {0, 239}, // AX CX DX BX BP SI DI 3634 }, 3635 outputs: []outputInfo{ 3636 {0, 239}, // AX CX DX BX BP SI DI 3637 }, 3638 }, 3639 }, 3640 { 3641 name: "MOVLconst", 3642 auxType: auxInt32, 3643 argLen: 0, 3644 rematerializeable: true, 3645 asm: x86.AMOVL, 3646 reg: regInfo{ 3647 outputs: []outputInfo{ 3648 {0, 239}, // AX CX DX BX BP SI DI 3649 }, 3650 }, 3651 }, 3652 { 3653 name: "CVTTSD2SL", 3654 argLen: 1, 3655 usesScratch: true, 3656 asm: x86.ACVTTSD2SL, 3657 reg: regInfo{ 3658 inputs: []inputInfo{ 3659 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3660 }, 3661 outputs: []outputInfo{ 3662 {0, 239}, // AX CX DX BX BP SI DI 3663 }, 3664 }, 3665 }, 3666 { 3667 name: "CVTTSS2SL", 3668 argLen: 1, 3669 usesScratch: true, 3670 asm: x86.ACVTTSS2SL, 3671 reg: regInfo{ 3672 inputs: []inputInfo{ 3673 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3674 }, 3675 outputs: []outputInfo{ 3676 {0, 239}, // AX CX DX BX BP SI DI 3677 }, 3678 }, 3679 }, 3680 { 3681 name: "CVTSL2SS", 3682 argLen: 1, 3683 usesScratch: true, 3684 asm: x86.ACVTSL2SS, 3685 reg: regInfo{ 3686 inputs: []inputInfo{ 3687 {0, 239}, // AX CX DX BX BP SI DI 3688 }, 3689 outputs: []outputInfo{ 3690 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3691 }, 3692 }, 3693 }, 3694 { 3695 name: "CVTSL2SD", 3696 argLen: 1, 3697 usesScratch: true, 3698 asm: x86.ACVTSL2SD, 3699 reg: regInfo{ 3700 inputs: []inputInfo{ 3701 {0, 239}, // AX CX DX BX BP SI DI 3702 }, 3703 outputs: []outputInfo{ 3704 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3705 }, 3706 }, 3707 }, 3708 { 3709 name: "CVTSD2SS", 3710 argLen: 1, 3711 usesScratch: true, 3712 asm: x86.ACVTSD2SS, 3713 reg: regInfo{ 3714 inputs: []inputInfo{ 3715 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3716 }, 3717 outputs: []outputInfo{ 3718 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3719 }, 3720 }, 3721 }, 3722 { 3723 name: "CVTSS2SD", 3724 argLen: 1, 3725 asm: x86.ACVTSS2SD, 3726 reg: regInfo{ 3727 inputs: []inputInfo{ 3728 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3729 }, 3730 outputs: []outputInfo{ 3731 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3732 }, 3733 }, 3734 }, 3735 { 3736 name: "PXOR", 3737 argLen: 2, 3738 commutative: true, 3739 resultInArg0: true, 3740 asm: x86.APXOR, 3741 reg: regInfo{ 3742 inputs: []inputInfo{ 3743 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3744 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3745 }, 3746 outputs: []outputInfo{ 3747 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3748 }, 3749 }, 3750 }, 3751 { 3752 name: "LEAL", 3753 auxType: auxSymOff, 3754 argLen: 1, 3755 rematerializeable: true, 3756 symEffect: SymAddr, 3757 reg: regInfo{ 3758 inputs: []inputInfo{ 3759 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3760 }, 3761 outputs: []outputInfo{ 3762 {0, 239}, // AX CX DX BX BP SI DI 3763 }, 3764 }, 3765 }, 3766 { 3767 name: "LEAL1", 3768 auxType: auxSymOff, 3769 argLen: 2, 3770 commutative: true, 3771 symEffect: SymAddr, 3772 reg: regInfo{ 3773 inputs: []inputInfo{ 3774 {1, 255}, // AX CX DX BX SP BP SI DI 3775 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3776 }, 3777 outputs: []outputInfo{ 3778 {0, 239}, // AX CX DX BX BP SI DI 3779 }, 3780 }, 3781 }, 3782 { 3783 name: "LEAL2", 3784 auxType: auxSymOff, 3785 argLen: 2, 3786 symEffect: SymAddr, 3787 reg: regInfo{ 3788 inputs: []inputInfo{ 3789 {1, 255}, // AX CX DX BX SP BP SI DI 3790 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3791 }, 3792 outputs: []outputInfo{ 3793 {0, 239}, // AX CX DX BX BP SI DI 3794 }, 3795 }, 3796 }, 3797 { 3798 name: "LEAL4", 3799 auxType: auxSymOff, 3800 argLen: 2, 3801 symEffect: SymAddr, 3802 reg: regInfo{ 3803 inputs: []inputInfo{ 3804 {1, 255}, // AX CX DX BX SP BP SI DI 3805 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3806 }, 3807 outputs: []outputInfo{ 3808 {0, 239}, // AX CX DX BX BP SI DI 3809 }, 3810 }, 3811 }, 3812 { 3813 name: "LEAL8", 3814 auxType: auxSymOff, 3815 argLen: 2, 3816 symEffect: SymAddr, 3817 reg: regInfo{ 3818 inputs: []inputInfo{ 3819 {1, 255}, // AX CX DX BX SP BP SI DI 3820 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3821 }, 3822 outputs: []outputInfo{ 3823 {0, 239}, // AX CX DX BX BP SI DI 3824 }, 3825 }, 3826 }, 3827 { 3828 name: "MOVBload", 3829 auxType: auxSymOff, 3830 argLen: 2, 3831 faultOnNilArg0: true, 3832 symEffect: SymRead, 3833 asm: x86.AMOVBLZX, 3834 reg: regInfo{ 3835 inputs: []inputInfo{ 3836 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3837 }, 3838 outputs: []outputInfo{ 3839 {0, 239}, // AX CX DX BX BP SI DI 3840 }, 3841 }, 3842 }, 3843 { 3844 name: "MOVBLSXload", 3845 auxType: auxSymOff, 3846 argLen: 2, 3847 faultOnNilArg0: true, 3848 symEffect: SymRead, 3849 asm: x86.AMOVBLSX, 3850 reg: regInfo{ 3851 inputs: []inputInfo{ 3852 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3853 }, 3854 outputs: []outputInfo{ 3855 {0, 239}, // AX CX DX BX BP SI DI 3856 }, 3857 }, 3858 }, 3859 { 3860 name: "MOVWload", 3861 auxType: auxSymOff, 3862 argLen: 2, 3863 faultOnNilArg0: true, 3864 symEffect: SymRead, 3865 asm: x86.AMOVWLZX, 3866 reg: regInfo{ 3867 inputs: []inputInfo{ 3868 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3869 }, 3870 outputs: []outputInfo{ 3871 {0, 239}, // AX CX DX BX BP SI DI 3872 }, 3873 }, 3874 }, 3875 { 3876 name: "MOVWLSXload", 3877 auxType: auxSymOff, 3878 argLen: 2, 3879 faultOnNilArg0: true, 3880 symEffect: SymRead, 3881 asm: x86.AMOVWLSX, 3882 reg: regInfo{ 3883 inputs: []inputInfo{ 3884 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3885 }, 3886 outputs: []outputInfo{ 3887 {0, 239}, // AX CX DX BX BP SI DI 3888 }, 3889 }, 3890 }, 3891 { 3892 name: "MOVLload", 3893 auxType: auxSymOff, 3894 argLen: 2, 3895 faultOnNilArg0: true, 3896 symEffect: SymRead, 3897 asm: x86.AMOVL, 3898 reg: regInfo{ 3899 inputs: []inputInfo{ 3900 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3901 }, 3902 outputs: []outputInfo{ 3903 {0, 239}, // AX CX DX BX BP SI DI 3904 }, 3905 }, 3906 }, 3907 { 3908 name: "MOVBstore", 3909 auxType: auxSymOff, 3910 argLen: 3, 3911 faultOnNilArg0: true, 3912 symEffect: SymWrite, 3913 asm: x86.AMOVB, 3914 reg: regInfo{ 3915 inputs: []inputInfo{ 3916 {1, 255}, // AX CX DX BX SP BP SI DI 3917 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3918 }, 3919 }, 3920 }, 3921 { 3922 name: "MOVWstore", 3923 auxType: auxSymOff, 3924 argLen: 3, 3925 faultOnNilArg0: true, 3926 symEffect: SymWrite, 3927 asm: x86.AMOVW, 3928 reg: regInfo{ 3929 inputs: []inputInfo{ 3930 {1, 255}, // AX CX DX BX SP BP SI DI 3931 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3932 }, 3933 }, 3934 }, 3935 { 3936 name: "MOVLstore", 3937 auxType: auxSymOff, 3938 argLen: 3, 3939 faultOnNilArg0: true, 3940 symEffect: SymWrite, 3941 asm: x86.AMOVL, 3942 reg: regInfo{ 3943 inputs: []inputInfo{ 3944 {1, 255}, // AX CX DX BX SP BP SI DI 3945 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3946 }, 3947 }, 3948 }, 3949 { 3950 name: "MOVBloadidx1", 3951 auxType: auxSymOff, 3952 argLen: 3, 3953 commutative: true, 3954 symEffect: SymRead, 3955 asm: x86.AMOVBLZX, 3956 reg: regInfo{ 3957 inputs: []inputInfo{ 3958 {1, 255}, // AX CX DX BX SP BP SI DI 3959 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3960 }, 3961 outputs: []outputInfo{ 3962 {0, 239}, // AX CX DX BX BP SI DI 3963 }, 3964 }, 3965 }, 3966 { 3967 name: "MOVWloadidx1", 3968 auxType: auxSymOff, 3969 argLen: 3, 3970 commutative: true, 3971 symEffect: SymRead, 3972 asm: x86.AMOVWLZX, 3973 reg: regInfo{ 3974 inputs: []inputInfo{ 3975 {1, 255}, // AX CX DX BX SP BP SI DI 3976 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3977 }, 3978 outputs: []outputInfo{ 3979 {0, 239}, // AX CX DX BX BP SI DI 3980 }, 3981 }, 3982 }, 3983 { 3984 name: "MOVWloadidx2", 3985 auxType: auxSymOff, 3986 argLen: 3, 3987 symEffect: SymRead, 3988 asm: x86.AMOVWLZX, 3989 reg: regInfo{ 3990 inputs: []inputInfo{ 3991 {1, 255}, // AX CX DX BX SP BP SI DI 3992 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3993 }, 3994 outputs: []outputInfo{ 3995 {0, 239}, // AX CX DX BX BP SI DI 3996 }, 3997 }, 3998 }, 3999 { 4000 name: "MOVLloadidx1", 4001 auxType: auxSymOff, 4002 argLen: 3, 4003 commutative: true, 4004 symEffect: SymRead, 4005 asm: x86.AMOVL, 4006 reg: regInfo{ 4007 inputs: []inputInfo{ 4008 {1, 255}, // AX CX DX BX SP BP SI DI 4009 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4010 }, 4011 outputs: []outputInfo{ 4012 {0, 239}, // AX CX DX BX BP SI DI 4013 }, 4014 }, 4015 }, 4016 { 4017 name: "MOVLloadidx4", 4018 auxType: auxSymOff, 4019 argLen: 3, 4020 symEffect: SymRead, 4021 asm: x86.AMOVL, 4022 reg: regInfo{ 4023 inputs: []inputInfo{ 4024 {1, 255}, // AX CX DX BX SP BP SI DI 4025 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4026 }, 4027 outputs: []outputInfo{ 4028 {0, 239}, // AX CX DX BX BP SI DI 4029 }, 4030 }, 4031 }, 4032 { 4033 name: "MOVBstoreidx1", 4034 auxType: auxSymOff, 4035 argLen: 4, 4036 commutative: true, 4037 symEffect: SymWrite, 4038 asm: x86.AMOVB, 4039 reg: regInfo{ 4040 inputs: []inputInfo{ 4041 {1, 255}, // AX CX DX BX SP BP SI DI 4042 {2, 255}, // AX CX DX BX SP BP SI DI 4043 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4044 }, 4045 }, 4046 }, 4047 { 4048 name: "MOVWstoreidx1", 4049 auxType: auxSymOff, 4050 argLen: 4, 4051 commutative: true, 4052 symEffect: SymWrite, 4053 asm: x86.AMOVW, 4054 reg: regInfo{ 4055 inputs: []inputInfo{ 4056 {1, 255}, // AX CX DX BX SP BP SI DI 4057 {2, 255}, // AX CX DX BX SP BP SI DI 4058 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4059 }, 4060 }, 4061 }, 4062 { 4063 name: "MOVWstoreidx2", 4064 auxType: auxSymOff, 4065 argLen: 4, 4066 symEffect: SymWrite, 4067 asm: x86.AMOVW, 4068 reg: regInfo{ 4069 inputs: []inputInfo{ 4070 {1, 255}, // AX CX DX BX SP BP SI DI 4071 {2, 255}, // AX CX DX BX SP BP SI DI 4072 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4073 }, 4074 }, 4075 }, 4076 { 4077 name: "MOVLstoreidx1", 4078 auxType: auxSymOff, 4079 argLen: 4, 4080 commutative: true, 4081 symEffect: SymWrite, 4082 asm: x86.AMOVL, 4083 reg: regInfo{ 4084 inputs: []inputInfo{ 4085 {1, 255}, // AX CX DX BX SP BP SI DI 4086 {2, 255}, // AX CX DX BX SP BP SI DI 4087 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4088 }, 4089 }, 4090 }, 4091 { 4092 name: "MOVLstoreidx4", 4093 auxType: auxSymOff, 4094 argLen: 4, 4095 symEffect: SymWrite, 4096 asm: x86.AMOVL, 4097 reg: regInfo{ 4098 inputs: []inputInfo{ 4099 {1, 255}, // AX CX DX BX SP BP SI DI 4100 {2, 255}, // AX CX DX BX SP BP SI DI 4101 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4102 }, 4103 }, 4104 }, 4105 { 4106 name: "MOVBstoreconst", 4107 auxType: auxSymValAndOff, 4108 argLen: 2, 4109 faultOnNilArg0: true, 4110 symEffect: SymWrite, 4111 asm: x86.AMOVB, 4112 reg: regInfo{ 4113 inputs: []inputInfo{ 4114 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4115 }, 4116 }, 4117 }, 4118 { 4119 name: "MOVWstoreconst", 4120 auxType: auxSymValAndOff, 4121 argLen: 2, 4122 faultOnNilArg0: true, 4123 symEffect: SymWrite, 4124 asm: x86.AMOVW, 4125 reg: regInfo{ 4126 inputs: []inputInfo{ 4127 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4128 }, 4129 }, 4130 }, 4131 { 4132 name: "MOVLstoreconst", 4133 auxType: auxSymValAndOff, 4134 argLen: 2, 4135 faultOnNilArg0: true, 4136 symEffect: SymWrite, 4137 asm: x86.AMOVL, 4138 reg: regInfo{ 4139 inputs: []inputInfo{ 4140 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4141 }, 4142 }, 4143 }, 4144 { 4145 name: "MOVBstoreconstidx1", 4146 auxType: auxSymValAndOff, 4147 argLen: 3, 4148 symEffect: SymWrite, 4149 asm: x86.AMOVB, 4150 reg: regInfo{ 4151 inputs: []inputInfo{ 4152 {1, 255}, // AX CX DX BX SP BP SI DI 4153 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4154 }, 4155 }, 4156 }, 4157 { 4158 name: "MOVWstoreconstidx1", 4159 auxType: auxSymValAndOff, 4160 argLen: 3, 4161 symEffect: SymWrite, 4162 asm: x86.AMOVW, 4163 reg: regInfo{ 4164 inputs: []inputInfo{ 4165 {1, 255}, // AX CX DX BX SP BP SI DI 4166 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4167 }, 4168 }, 4169 }, 4170 { 4171 name: "MOVWstoreconstidx2", 4172 auxType: auxSymValAndOff, 4173 argLen: 3, 4174 symEffect: SymWrite, 4175 asm: x86.AMOVW, 4176 reg: regInfo{ 4177 inputs: []inputInfo{ 4178 {1, 255}, // AX CX DX BX SP BP SI DI 4179 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4180 }, 4181 }, 4182 }, 4183 { 4184 name: "MOVLstoreconstidx1", 4185 auxType: auxSymValAndOff, 4186 argLen: 3, 4187 symEffect: SymWrite, 4188 asm: x86.AMOVL, 4189 reg: regInfo{ 4190 inputs: []inputInfo{ 4191 {1, 255}, // AX CX DX BX SP BP SI DI 4192 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4193 }, 4194 }, 4195 }, 4196 { 4197 name: "MOVLstoreconstidx4", 4198 auxType: auxSymValAndOff, 4199 argLen: 3, 4200 symEffect: SymWrite, 4201 asm: x86.AMOVL, 4202 reg: regInfo{ 4203 inputs: []inputInfo{ 4204 {1, 255}, // AX CX DX BX SP BP SI DI 4205 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4206 }, 4207 }, 4208 }, 4209 { 4210 name: "DUFFZERO", 4211 auxType: auxInt64, 4212 argLen: 3, 4213 faultOnNilArg0: true, 4214 reg: regInfo{ 4215 inputs: []inputInfo{ 4216 {0, 128}, // DI 4217 {1, 1}, // AX 4218 }, 4219 clobbers: 130, // CX DI 4220 }, 4221 }, 4222 { 4223 name: "REPSTOSL", 4224 argLen: 4, 4225 faultOnNilArg0: true, 4226 reg: regInfo{ 4227 inputs: []inputInfo{ 4228 {0, 128}, // DI 4229 {1, 2}, // CX 4230 {2, 1}, // AX 4231 }, 4232 clobbers: 130, // CX DI 4233 }, 4234 }, 4235 { 4236 name: "CALLstatic", 4237 auxType: auxSymOff, 4238 argLen: 1, 4239 clobberFlags: true, 4240 call: true, 4241 symEffect: SymNone, 4242 reg: regInfo{ 4243 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4244 }, 4245 }, 4246 { 4247 name: "CALLclosure", 4248 auxType: auxInt64, 4249 argLen: 3, 4250 clobberFlags: true, 4251 call: true, 4252 reg: regInfo{ 4253 inputs: []inputInfo{ 4254 {1, 4}, // DX 4255 {0, 255}, // AX CX DX BX SP BP SI DI 4256 }, 4257 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4258 }, 4259 }, 4260 { 4261 name: "CALLinter", 4262 auxType: auxInt64, 4263 argLen: 2, 4264 clobberFlags: true, 4265 call: true, 4266 reg: regInfo{ 4267 inputs: []inputInfo{ 4268 {0, 239}, // AX CX DX BX BP SI DI 4269 }, 4270 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4271 }, 4272 }, 4273 { 4274 name: "DUFFCOPY", 4275 auxType: auxInt64, 4276 argLen: 3, 4277 clobberFlags: true, 4278 faultOnNilArg0: true, 4279 faultOnNilArg1: true, 4280 reg: regInfo{ 4281 inputs: []inputInfo{ 4282 {0, 128}, // DI 4283 {1, 64}, // SI 4284 }, 4285 clobbers: 194, // CX SI DI 4286 }, 4287 }, 4288 { 4289 name: "REPMOVSL", 4290 argLen: 4, 4291 faultOnNilArg0: true, 4292 faultOnNilArg1: true, 4293 reg: regInfo{ 4294 inputs: []inputInfo{ 4295 {0, 128}, // DI 4296 {1, 64}, // SI 4297 {2, 2}, // CX 4298 }, 4299 clobbers: 194, // CX SI DI 4300 }, 4301 }, 4302 { 4303 name: "InvertFlags", 4304 argLen: 1, 4305 reg: regInfo{}, 4306 }, 4307 { 4308 name: "LoweredGetG", 4309 argLen: 1, 4310 reg: regInfo{ 4311 outputs: []outputInfo{ 4312 {0, 239}, // AX CX DX BX BP SI DI 4313 }, 4314 }, 4315 }, 4316 { 4317 name: "LoweredGetClosurePtr", 4318 argLen: 0, 4319 reg: regInfo{ 4320 outputs: []outputInfo{ 4321 {0, 4}, // DX 4322 }, 4323 }, 4324 }, 4325 { 4326 name: "LoweredGetCallerPC", 4327 argLen: 0, 4328 reg: regInfo{ 4329 outputs: []outputInfo{ 4330 {0, 239}, // AX CX DX BX BP SI DI 4331 }, 4332 }, 4333 }, 4334 { 4335 name: "LoweredGetCallerSP", 4336 argLen: 0, 4337 rematerializeable: true, 4338 reg: regInfo{ 4339 outputs: []outputInfo{ 4340 {0, 239}, // AX CX DX BX BP SI DI 4341 }, 4342 }, 4343 }, 4344 { 4345 name: "LoweredNilCheck", 4346 argLen: 2, 4347 clobberFlags: true, 4348 nilCheck: true, 4349 faultOnNilArg0: true, 4350 reg: regInfo{ 4351 inputs: []inputInfo{ 4352 {0, 255}, // AX CX DX BX SP BP SI DI 4353 }, 4354 }, 4355 }, 4356 { 4357 name: "MOVLconvert", 4358 argLen: 2, 4359 resultInArg0: true, 4360 asm: x86.AMOVL, 4361 reg: regInfo{ 4362 inputs: []inputInfo{ 4363 {0, 239}, // AX CX DX BX BP SI DI 4364 }, 4365 outputs: []outputInfo{ 4366 {0, 239}, // AX CX DX BX BP SI DI 4367 }, 4368 }, 4369 }, 4370 { 4371 name: "FlagEQ", 4372 argLen: 0, 4373 reg: regInfo{}, 4374 }, 4375 { 4376 name: "FlagLT_ULT", 4377 argLen: 0, 4378 reg: regInfo{}, 4379 }, 4380 { 4381 name: "FlagLT_UGT", 4382 argLen: 0, 4383 reg: regInfo{}, 4384 }, 4385 { 4386 name: "FlagGT_UGT", 4387 argLen: 0, 4388 reg: regInfo{}, 4389 }, 4390 { 4391 name: "FlagGT_ULT", 4392 argLen: 0, 4393 reg: regInfo{}, 4394 }, 4395 { 4396 name: "FCHS", 4397 argLen: 1, 4398 reg: regInfo{ 4399 inputs: []inputInfo{ 4400 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4401 }, 4402 outputs: []outputInfo{ 4403 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4404 }, 4405 }, 4406 }, 4407 { 4408 name: "MOVSSconst1", 4409 auxType: auxFloat32, 4410 argLen: 0, 4411 reg: regInfo{ 4412 outputs: []outputInfo{ 4413 {0, 239}, // AX CX DX BX BP SI DI 4414 }, 4415 }, 4416 }, 4417 { 4418 name: "MOVSDconst1", 4419 auxType: auxFloat64, 4420 argLen: 0, 4421 reg: regInfo{ 4422 outputs: []outputInfo{ 4423 {0, 239}, // AX CX DX BX BP SI DI 4424 }, 4425 }, 4426 }, 4427 { 4428 name: "MOVSSconst2", 4429 argLen: 1, 4430 asm: x86.AMOVSS, 4431 reg: regInfo{ 4432 inputs: []inputInfo{ 4433 {0, 239}, // AX CX DX BX BP SI DI 4434 }, 4435 outputs: []outputInfo{ 4436 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4437 }, 4438 }, 4439 }, 4440 { 4441 name: "MOVSDconst2", 4442 argLen: 1, 4443 asm: x86.AMOVSD, 4444 reg: regInfo{ 4445 inputs: []inputInfo{ 4446 {0, 239}, // AX CX DX BX BP SI DI 4447 }, 4448 outputs: []outputInfo{ 4449 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4450 }, 4451 }, 4452 }, 4453 4454 { 4455 name: "ADDSS", 4456 argLen: 2, 4457 commutative: true, 4458 resultInArg0: true, 4459 asm: x86.AADDSS, 4460 reg: regInfo{ 4461 inputs: []inputInfo{ 4462 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4463 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4464 }, 4465 outputs: []outputInfo{ 4466 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4467 }, 4468 }, 4469 }, 4470 { 4471 name: "ADDSD", 4472 argLen: 2, 4473 commutative: true, 4474 resultInArg0: true, 4475 asm: x86.AADDSD, 4476 reg: regInfo{ 4477 inputs: []inputInfo{ 4478 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4479 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4480 }, 4481 outputs: []outputInfo{ 4482 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4483 }, 4484 }, 4485 }, 4486 { 4487 name: "SUBSS", 4488 argLen: 2, 4489 resultInArg0: true, 4490 asm: x86.ASUBSS, 4491 reg: regInfo{ 4492 inputs: []inputInfo{ 4493 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4494 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4495 }, 4496 outputs: []outputInfo{ 4497 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4498 }, 4499 }, 4500 }, 4501 { 4502 name: "SUBSD", 4503 argLen: 2, 4504 resultInArg0: true, 4505 asm: x86.ASUBSD, 4506 reg: regInfo{ 4507 inputs: []inputInfo{ 4508 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4509 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4510 }, 4511 outputs: []outputInfo{ 4512 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4513 }, 4514 }, 4515 }, 4516 { 4517 name: "MULSS", 4518 argLen: 2, 4519 commutative: true, 4520 resultInArg0: true, 4521 asm: x86.AMULSS, 4522 reg: regInfo{ 4523 inputs: []inputInfo{ 4524 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4525 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4526 }, 4527 outputs: []outputInfo{ 4528 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4529 }, 4530 }, 4531 }, 4532 { 4533 name: "MULSD", 4534 argLen: 2, 4535 commutative: true, 4536 resultInArg0: true, 4537 asm: x86.AMULSD, 4538 reg: regInfo{ 4539 inputs: []inputInfo{ 4540 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4541 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4542 }, 4543 outputs: []outputInfo{ 4544 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4545 }, 4546 }, 4547 }, 4548 { 4549 name: "DIVSS", 4550 argLen: 2, 4551 resultInArg0: true, 4552 asm: x86.ADIVSS, 4553 reg: regInfo{ 4554 inputs: []inputInfo{ 4555 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4556 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4557 }, 4558 outputs: []outputInfo{ 4559 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4560 }, 4561 }, 4562 }, 4563 { 4564 name: "DIVSD", 4565 argLen: 2, 4566 resultInArg0: true, 4567 asm: x86.ADIVSD, 4568 reg: regInfo{ 4569 inputs: []inputInfo{ 4570 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4571 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4572 }, 4573 outputs: []outputInfo{ 4574 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4575 }, 4576 }, 4577 }, 4578 { 4579 name: "MOVSSload", 4580 auxType: auxSymOff, 4581 argLen: 2, 4582 faultOnNilArg0: true, 4583 symEffect: SymRead, 4584 asm: x86.AMOVSS, 4585 reg: regInfo{ 4586 inputs: []inputInfo{ 4587 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4588 }, 4589 outputs: []outputInfo{ 4590 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4591 }, 4592 }, 4593 }, 4594 { 4595 name: "MOVSDload", 4596 auxType: auxSymOff, 4597 argLen: 2, 4598 faultOnNilArg0: true, 4599 symEffect: SymRead, 4600 asm: x86.AMOVSD, 4601 reg: regInfo{ 4602 inputs: []inputInfo{ 4603 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4604 }, 4605 outputs: []outputInfo{ 4606 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4607 }, 4608 }, 4609 }, 4610 { 4611 name: "MOVSSconst", 4612 auxType: auxFloat32, 4613 argLen: 0, 4614 rematerializeable: true, 4615 asm: x86.AMOVSS, 4616 reg: regInfo{ 4617 outputs: []outputInfo{ 4618 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4619 }, 4620 }, 4621 }, 4622 { 4623 name: "MOVSDconst", 4624 auxType: auxFloat64, 4625 argLen: 0, 4626 rematerializeable: true, 4627 asm: x86.AMOVSD, 4628 reg: regInfo{ 4629 outputs: []outputInfo{ 4630 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4631 }, 4632 }, 4633 }, 4634 { 4635 name: "MOVSSloadidx1", 4636 auxType: auxSymOff, 4637 argLen: 3, 4638 symEffect: SymRead, 4639 asm: x86.AMOVSS, 4640 reg: regInfo{ 4641 inputs: []inputInfo{ 4642 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4643 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4644 }, 4645 outputs: []outputInfo{ 4646 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4647 }, 4648 }, 4649 }, 4650 { 4651 name: "MOVSSloadidx4", 4652 auxType: auxSymOff, 4653 argLen: 3, 4654 symEffect: SymRead, 4655 asm: x86.AMOVSS, 4656 reg: regInfo{ 4657 inputs: []inputInfo{ 4658 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4659 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4660 }, 4661 outputs: []outputInfo{ 4662 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4663 }, 4664 }, 4665 }, 4666 { 4667 name: "MOVSDloadidx1", 4668 auxType: auxSymOff, 4669 argLen: 3, 4670 symEffect: SymRead, 4671 asm: x86.AMOVSD, 4672 reg: regInfo{ 4673 inputs: []inputInfo{ 4674 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4675 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4676 }, 4677 outputs: []outputInfo{ 4678 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4679 }, 4680 }, 4681 }, 4682 { 4683 name: "MOVSDloadidx8", 4684 auxType: auxSymOff, 4685 argLen: 3, 4686 symEffect: SymRead, 4687 asm: x86.AMOVSD, 4688 reg: regInfo{ 4689 inputs: []inputInfo{ 4690 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4691 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4692 }, 4693 outputs: []outputInfo{ 4694 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4695 }, 4696 }, 4697 }, 4698 { 4699 name: "MOVSSstore", 4700 auxType: auxSymOff, 4701 argLen: 3, 4702 faultOnNilArg0: true, 4703 symEffect: SymWrite, 4704 asm: x86.AMOVSS, 4705 reg: regInfo{ 4706 inputs: []inputInfo{ 4707 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4708 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4709 }, 4710 }, 4711 }, 4712 { 4713 name: "MOVSDstore", 4714 auxType: auxSymOff, 4715 argLen: 3, 4716 faultOnNilArg0: true, 4717 symEffect: SymWrite, 4718 asm: x86.AMOVSD, 4719 reg: regInfo{ 4720 inputs: []inputInfo{ 4721 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4722 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4723 }, 4724 }, 4725 }, 4726 { 4727 name: "MOVSSstoreidx1", 4728 auxType: auxSymOff, 4729 argLen: 4, 4730 symEffect: SymWrite, 4731 asm: x86.AMOVSS, 4732 reg: regInfo{ 4733 inputs: []inputInfo{ 4734 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4735 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4736 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4737 }, 4738 }, 4739 }, 4740 { 4741 name: "MOVSSstoreidx4", 4742 auxType: auxSymOff, 4743 argLen: 4, 4744 symEffect: SymWrite, 4745 asm: x86.AMOVSS, 4746 reg: regInfo{ 4747 inputs: []inputInfo{ 4748 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4749 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4750 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4751 }, 4752 }, 4753 }, 4754 { 4755 name: "MOVSDstoreidx1", 4756 auxType: auxSymOff, 4757 argLen: 4, 4758 symEffect: SymWrite, 4759 asm: x86.AMOVSD, 4760 reg: regInfo{ 4761 inputs: []inputInfo{ 4762 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4763 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4764 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4765 }, 4766 }, 4767 }, 4768 { 4769 name: "MOVSDstoreidx8", 4770 auxType: auxSymOff, 4771 argLen: 4, 4772 symEffect: SymWrite, 4773 asm: x86.AMOVSD, 4774 reg: regInfo{ 4775 inputs: []inputInfo{ 4776 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4777 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4778 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4779 }, 4780 }, 4781 }, 4782 { 4783 name: "ADDSSmem", 4784 auxType: auxSymOff, 4785 argLen: 3, 4786 resultInArg0: true, 4787 faultOnNilArg1: true, 4788 symEffect: SymRead, 4789 asm: x86.AADDSS, 4790 reg: regInfo{ 4791 inputs: []inputInfo{ 4792 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4793 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4794 }, 4795 outputs: []outputInfo{ 4796 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4797 }, 4798 }, 4799 }, 4800 { 4801 name: "ADDSDmem", 4802 auxType: auxSymOff, 4803 argLen: 3, 4804 resultInArg0: true, 4805 faultOnNilArg1: true, 4806 symEffect: SymRead, 4807 asm: x86.AADDSD, 4808 reg: regInfo{ 4809 inputs: []inputInfo{ 4810 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4811 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4812 }, 4813 outputs: []outputInfo{ 4814 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4815 }, 4816 }, 4817 }, 4818 { 4819 name: "SUBSSmem", 4820 auxType: auxSymOff, 4821 argLen: 3, 4822 resultInArg0: true, 4823 faultOnNilArg1: true, 4824 symEffect: SymRead, 4825 asm: x86.ASUBSS, 4826 reg: regInfo{ 4827 inputs: []inputInfo{ 4828 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4829 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4830 }, 4831 outputs: []outputInfo{ 4832 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4833 }, 4834 }, 4835 }, 4836 { 4837 name: "SUBSDmem", 4838 auxType: auxSymOff, 4839 argLen: 3, 4840 resultInArg0: true, 4841 faultOnNilArg1: true, 4842 symEffect: SymRead, 4843 asm: x86.ASUBSD, 4844 reg: regInfo{ 4845 inputs: []inputInfo{ 4846 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4847 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4848 }, 4849 outputs: []outputInfo{ 4850 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4851 }, 4852 }, 4853 }, 4854 { 4855 name: "MULSSmem", 4856 auxType: auxSymOff, 4857 argLen: 3, 4858 resultInArg0: true, 4859 faultOnNilArg1: true, 4860 symEffect: SymRead, 4861 asm: x86.AMULSS, 4862 reg: regInfo{ 4863 inputs: []inputInfo{ 4864 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4865 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4866 }, 4867 outputs: []outputInfo{ 4868 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4869 }, 4870 }, 4871 }, 4872 { 4873 name: "MULSDmem", 4874 auxType: auxSymOff, 4875 argLen: 3, 4876 resultInArg0: true, 4877 faultOnNilArg1: true, 4878 symEffect: SymRead, 4879 asm: x86.AMULSD, 4880 reg: regInfo{ 4881 inputs: []inputInfo{ 4882 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4883 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4884 }, 4885 outputs: []outputInfo{ 4886 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4887 }, 4888 }, 4889 }, 4890 { 4891 name: "ADDQ", 4892 argLen: 2, 4893 commutative: true, 4894 clobberFlags: true, 4895 asm: x86.AADDQ, 4896 reg: regInfo{ 4897 inputs: []inputInfo{ 4898 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4899 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4900 }, 4901 outputs: []outputInfo{ 4902 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4903 }, 4904 }, 4905 }, 4906 { 4907 name: "ADDL", 4908 argLen: 2, 4909 commutative: true, 4910 clobberFlags: true, 4911 asm: x86.AADDL, 4912 reg: regInfo{ 4913 inputs: []inputInfo{ 4914 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4915 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4916 }, 4917 outputs: []outputInfo{ 4918 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4919 }, 4920 }, 4921 }, 4922 { 4923 name: "ADDQconst", 4924 auxType: auxInt32, 4925 argLen: 1, 4926 clobberFlags: true, 4927 asm: x86.AADDQ, 4928 reg: regInfo{ 4929 inputs: []inputInfo{ 4930 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4931 }, 4932 outputs: []outputInfo{ 4933 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4934 }, 4935 }, 4936 }, 4937 { 4938 name: "ADDLconst", 4939 auxType: auxInt32, 4940 argLen: 1, 4941 clobberFlags: true, 4942 asm: x86.AADDL, 4943 reg: regInfo{ 4944 inputs: []inputInfo{ 4945 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4946 }, 4947 outputs: []outputInfo{ 4948 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4949 }, 4950 }, 4951 }, 4952 { 4953 name: "ADDQconstmem", 4954 auxType: auxSymValAndOff, 4955 argLen: 2, 4956 clobberFlags: true, 4957 faultOnNilArg0: true, 4958 symEffect: SymWrite, 4959 asm: x86.AADDQ, 4960 reg: regInfo{ 4961 inputs: []inputInfo{ 4962 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4963 }, 4964 }, 4965 }, 4966 { 4967 name: "ADDLconstmem", 4968 auxType: auxSymValAndOff, 4969 argLen: 2, 4970 clobberFlags: true, 4971 faultOnNilArg0: true, 4972 symEffect: SymWrite, 4973 asm: x86.AADDL, 4974 reg: regInfo{ 4975 inputs: []inputInfo{ 4976 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4977 }, 4978 }, 4979 }, 4980 { 4981 name: "SUBQ", 4982 argLen: 2, 4983 resultInArg0: true, 4984 clobberFlags: true, 4985 asm: x86.ASUBQ, 4986 reg: regInfo{ 4987 inputs: []inputInfo{ 4988 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4989 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4990 }, 4991 outputs: []outputInfo{ 4992 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4993 }, 4994 }, 4995 }, 4996 { 4997 name: "SUBL", 4998 argLen: 2, 4999 resultInArg0: true, 5000 clobberFlags: true, 5001 asm: x86.ASUBL, 5002 reg: regInfo{ 5003 inputs: []inputInfo{ 5004 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5005 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5006 }, 5007 outputs: []outputInfo{ 5008 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5009 }, 5010 }, 5011 }, 5012 { 5013 name: "SUBQconst", 5014 auxType: auxInt32, 5015 argLen: 1, 5016 resultInArg0: true, 5017 clobberFlags: true, 5018 asm: x86.ASUBQ, 5019 reg: regInfo{ 5020 inputs: []inputInfo{ 5021 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5022 }, 5023 outputs: []outputInfo{ 5024 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5025 }, 5026 }, 5027 }, 5028 { 5029 name: "SUBLconst", 5030 auxType: auxInt32, 5031 argLen: 1, 5032 resultInArg0: true, 5033 clobberFlags: true, 5034 asm: x86.ASUBL, 5035 reg: regInfo{ 5036 inputs: []inputInfo{ 5037 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5038 }, 5039 outputs: []outputInfo{ 5040 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5041 }, 5042 }, 5043 }, 5044 { 5045 name: "MULQ", 5046 argLen: 2, 5047 commutative: true, 5048 resultInArg0: true, 5049 clobberFlags: true, 5050 asm: x86.AIMULQ, 5051 reg: regInfo{ 5052 inputs: []inputInfo{ 5053 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5054 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5055 }, 5056 outputs: []outputInfo{ 5057 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5058 }, 5059 }, 5060 }, 5061 { 5062 name: "MULL", 5063 argLen: 2, 5064 commutative: true, 5065 resultInArg0: true, 5066 clobberFlags: true, 5067 asm: x86.AIMULL, 5068 reg: regInfo{ 5069 inputs: []inputInfo{ 5070 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5071 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5072 }, 5073 outputs: []outputInfo{ 5074 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5075 }, 5076 }, 5077 }, 5078 { 5079 name: "MULQconst", 5080 auxType: auxInt32, 5081 argLen: 1, 5082 resultInArg0: true, 5083 clobberFlags: true, 5084 asm: x86.AIMULQ, 5085 reg: regInfo{ 5086 inputs: []inputInfo{ 5087 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5088 }, 5089 outputs: []outputInfo{ 5090 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5091 }, 5092 }, 5093 }, 5094 { 5095 name: "MULLconst", 5096 auxType: auxInt32, 5097 argLen: 1, 5098 resultInArg0: true, 5099 clobberFlags: true, 5100 asm: x86.AIMULL, 5101 reg: regInfo{ 5102 inputs: []inputInfo{ 5103 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5104 }, 5105 outputs: []outputInfo{ 5106 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5107 }, 5108 }, 5109 }, 5110 { 5111 name: "HMULQ", 5112 argLen: 2, 5113 commutative: true, 5114 clobberFlags: true, 5115 asm: x86.AIMULQ, 5116 reg: regInfo{ 5117 inputs: []inputInfo{ 5118 {0, 1}, // AX 5119 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5120 }, 5121 clobbers: 1, // AX 5122 outputs: []outputInfo{ 5123 {0, 4}, // DX 5124 }, 5125 }, 5126 }, 5127 { 5128 name: "HMULL", 5129 argLen: 2, 5130 commutative: true, 5131 clobberFlags: true, 5132 asm: x86.AIMULL, 5133 reg: regInfo{ 5134 inputs: []inputInfo{ 5135 {0, 1}, // AX 5136 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5137 }, 5138 clobbers: 1, // AX 5139 outputs: []outputInfo{ 5140 {0, 4}, // DX 5141 }, 5142 }, 5143 }, 5144 { 5145 name: "HMULQU", 5146 argLen: 2, 5147 commutative: true, 5148 clobberFlags: true, 5149 asm: x86.AMULQ, 5150 reg: regInfo{ 5151 inputs: []inputInfo{ 5152 {0, 1}, // AX 5153 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5154 }, 5155 clobbers: 1, // AX 5156 outputs: []outputInfo{ 5157 {0, 4}, // DX 5158 }, 5159 }, 5160 }, 5161 { 5162 name: "HMULLU", 5163 argLen: 2, 5164 commutative: true, 5165 clobberFlags: true, 5166 asm: x86.AMULL, 5167 reg: regInfo{ 5168 inputs: []inputInfo{ 5169 {0, 1}, // AX 5170 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5171 }, 5172 clobbers: 1, // AX 5173 outputs: []outputInfo{ 5174 {0, 4}, // DX 5175 }, 5176 }, 5177 }, 5178 { 5179 name: "AVGQU", 5180 argLen: 2, 5181 commutative: true, 5182 resultInArg0: true, 5183 clobberFlags: true, 5184 reg: regInfo{ 5185 inputs: []inputInfo{ 5186 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5187 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5188 }, 5189 outputs: []outputInfo{ 5190 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5191 }, 5192 }, 5193 }, 5194 { 5195 name: "DIVQ", 5196 argLen: 2, 5197 clobberFlags: true, 5198 asm: x86.AIDIVQ, 5199 reg: regInfo{ 5200 inputs: []inputInfo{ 5201 {0, 1}, // AX 5202 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5203 }, 5204 outputs: []outputInfo{ 5205 {0, 1}, // AX 5206 {1, 4}, // DX 5207 }, 5208 }, 5209 }, 5210 { 5211 name: "DIVL", 5212 argLen: 2, 5213 clobberFlags: true, 5214 asm: x86.AIDIVL, 5215 reg: regInfo{ 5216 inputs: []inputInfo{ 5217 {0, 1}, // AX 5218 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5219 }, 5220 outputs: []outputInfo{ 5221 {0, 1}, // AX 5222 {1, 4}, // DX 5223 }, 5224 }, 5225 }, 5226 { 5227 name: "DIVW", 5228 argLen: 2, 5229 clobberFlags: true, 5230 asm: x86.AIDIVW, 5231 reg: regInfo{ 5232 inputs: []inputInfo{ 5233 {0, 1}, // AX 5234 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5235 }, 5236 outputs: []outputInfo{ 5237 {0, 1}, // AX 5238 {1, 4}, // DX 5239 }, 5240 }, 5241 }, 5242 { 5243 name: "DIVQU", 5244 argLen: 2, 5245 clobberFlags: true, 5246 asm: x86.ADIVQ, 5247 reg: regInfo{ 5248 inputs: []inputInfo{ 5249 {0, 1}, // AX 5250 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5251 }, 5252 outputs: []outputInfo{ 5253 {0, 1}, // AX 5254 {1, 4}, // DX 5255 }, 5256 }, 5257 }, 5258 { 5259 name: "DIVLU", 5260 argLen: 2, 5261 clobberFlags: true, 5262 asm: x86.ADIVL, 5263 reg: regInfo{ 5264 inputs: []inputInfo{ 5265 {0, 1}, // AX 5266 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5267 }, 5268 outputs: []outputInfo{ 5269 {0, 1}, // AX 5270 {1, 4}, // DX 5271 }, 5272 }, 5273 }, 5274 { 5275 name: "DIVWU", 5276 argLen: 2, 5277 clobberFlags: true, 5278 asm: x86.ADIVW, 5279 reg: regInfo{ 5280 inputs: []inputInfo{ 5281 {0, 1}, // AX 5282 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5283 }, 5284 outputs: []outputInfo{ 5285 {0, 1}, // AX 5286 {1, 4}, // DX 5287 }, 5288 }, 5289 }, 5290 { 5291 name: "MULQU2", 5292 argLen: 2, 5293 commutative: true, 5294 clobberFlags: true, 5295 asm: x86.AMULQ, 5296 reg: regInfo{ 5297 inputs: []inputInfo{ 5298 {0, 1}, // AX 5299 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5300 }, 5301 outputs: []outputInfo{ 5302 {0, 4}, // DX 5303 {1, 1}, // AX 5304 }, 5305 }, 5306 }, 5307 { 5308 name: "DIVQU2", 5309 argLen: 3, 5310 clobberFlags: true, 5311 asm: x86.ADIVQ, 5312 reg: regInfo{ 5313 inputs: []inputInfo{ 5314 {0, 4}, // DX 5315 {1, 1}, // AX 5316 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5317 }, 5318 outputs: []outputInfo{ 5319 {0, 1}, // AX 5320 {1, 4}, // DX 5321 }, 5322 }, 5323 }, 5324 { 5325 name: "ANDQ", 5326 argLen: 2, 5327 commutative: true, 5328 resultInArg0: true, 5329 clobberFlags: true, 5330 asm: x86.AANDQ, 5331 reg: regInfo{ 5332 inputs: []inputInfo{ 5333 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5334 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5335 }, 5336 outputs: []outputInfo{ 5337 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5338 }, 5339 }, 5340 }, 5341 { 5342 name: "ANDL", 5343 argLen: 2, 5344 commutative: true, 5345 resultInArg0: true, 5346 clobberFlags: true, 5347 asm: x86.AANDL, 5348 reg: regInfo{ 5349 inputs: []inputInfo{ 5350 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5351 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5352 }, 5353 outputs: []outputInfo{ 5354 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5355 }, 5356 }, 5357 }, 5358 { 5359 name: "ANDQconst", 5360 auxType: auxInt32, 5361 argLen: 1, 5362 resultInArg0: true, 5363 clobberFlags: true, 5364 asm: x86.AANDQ, 5365 reg: regInfo{ 5366 inputs: []inputInfo{ 5367 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5368 }, 5369 outputs: []outputInfo{ 5370 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5371 }, 5372 }, 5373 }, 5374 { 5375 name: "ANDLconst", 5376 auxType: auxInt32, 5377 argLen: 1, 5378 resultInArg0: true, 5379 clobberFlags: true, 5380 asm: x86.AANDL, 5381 reg: regInfo{ 5382 inputs: []inputInfo{ 5383 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5384 }, 5385 outputs: []outputInfo{ 5386 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5387 }, 5388 }, 5389 }, 5390 { 5391 name: "ORQ", 5392 argLen: 2, 5393 commutative: true, 5394 resultInArg0: true, 5395 clobberFlags: true, 5396 asm: x86.AORQ, 5397 reg: regInfo{ 5398 inputs: []inputInfo{ 5399 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5400 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5401 }, 5402 outputs: []outputInfo{ 5403 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5404 }, 5405 }, 5406 }, 5407 { 5408 name: "ORL", 5409 argLen: 2, 5410 commutative: true, 5411 resultInArg0: true, 5412 clobberFlags: true, 5413 asm: x86.AORL, 5414 reg: regInfo{ 5415 inputs: []inputInfo{ 5416 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5417 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5418 }, 5419 outputs: []outputInfo{ 5420 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5421 }, 5422 }, 5423 }, 5424 { 5425 name: "ORQconst", 5426 auxType: auxInt32, 5427 argLen: 1, 5428 resultInArg0: true, 5429 clobberFlags: true, 5430 asm: x86.AORQ, 5431 reg: regInfo{ 5432 inputs: []inputInfo{ 5433 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5434 }, 5435 outputs: []outputInfo{ 5436 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5437 }, 5438 }, 5439 }, 5440 { 5441 name: "ORLconst", 5442 auxType: auxInt32, 5443 argLen: 1, 5444 resultInArg0: true, 5445 clobberFlags: true, 5446 asm: x86.AORL, 5447 reg: regInfo{ 5448 inputs: []inputInfo{ 5449 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5450 }, 5451 outputs: []outputInfo{ 5452 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5453 }, 5454 }, 5455 }, 5456 { 5457 name: "XORQ", 5458 argLen: 2, 5459 commutative: true, 5460 resultInArg0: true, 5461 clobberFlags: true, 5462 asm: x86.AXORQ, 5463 reg: regInfo{ 5464 inputs: []inputInfo{ 5465 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5466 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5467 }, 5468 outputs: []outputInfo{ 5469 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5470 }, 5471 }, 5472 }, 5473 { 5474 name: "XORL", 5475 argLen: 2, 5476 commutative: true, 5477 resultInArg0: true, 5478 clobberFlags: true, 5479 asm: x86.AXORL, 5480 reg: regInfo{ 5481 inputs: []inputInfo{ 5482 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5483 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5484 }, 5485 outputs: []outputInfo{ 5486 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5487 }, 5488 }, 5489 }, 5490 { 5491 name: "XORQconst", 5492 auxType: auxInt32, 5493 argLen: 1, 5494 resultInArg0: true, 5495 clobberFlags: true, 5496 asm: x86.AXORQ, 5497 reg: regInfo{ 5498 inputs: []inputInfo{ 5499 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5500 }, 5501 outputs: []outputInfo{ 5502 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5503 }, 5504 }, 5505 }, 5506 { 5507 name: "XORLconst", 5508 auxType: auxInt32, 5509 argLen: 1, 5510 resultInArg0: true, 5511 clobberFlags: true, 5512 asm: x86.AXORL, 5513 reg: regInfo{ 5514 inputs: []inputInfo{ 5515 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5516 }, 5517 outputs: []outputInfo{ 5518 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5519 }, 5520 }, 5521 }, 5522 { 5523 name: "CMPQ", 5524 argLen: 2, 5525 asm: x86.ACMPQ, 5526 reg: regInfo{ 5527 inputs: []inputInfo{ 5528 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5529 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5530 }, 5531 }, 5532 }, 5533 { 5534 name: "CMPL", 5535 argLen: 2, 5536 asm: x86.ACMPL, 5537 reg: regInfo{ 5538 inputs: []inputInfo{ 5539 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5540 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5541 }, 5542 }, 5543 }, 5544 { 5545 name: "CMPW", 5546 argLen: 2, 5547 asm: x86.ACMPW, 5548 reg: regInfo{ 5549 inputs: []inputInfo{ 5550 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5551 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5552 }, 5553 }, 5554 }, 5555 { 5556 name: "CMPB", 5557 argLen: 2, 5558 asm: x86.ACMPB, 5559 reg: regInfo{ 5560 inputs: []inputInfo{ 5561 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5562 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5563 }, 5564 }, 5565 }, 5566 { 5567 name: "CMPQconst", 5568 auxType: auxInt32, 5569 argLen: 1, 5570 asm: x86.ACMPQ, 5571 reg: regInfo{ 5572 inputs: []inputInfo{ 5573 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5574 }, 5575 }, 5576 }, 5577 { 5578 name: "CMPLconst", 5579 auxType: auxInt32, 5580 argLen: 1, 5581 asm: x86.ACMPL, 5582 reg: regInfo{ 5583 inputs: []inputInfo{ 5584 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5585 }, 5586 }, 5587 }, 5588 { 5589 name: "CMPWconst", 5590 auxType: auxInt16, 5591 argLen: 1, 5592 asm: x86.ACMPW, 5593 reg: regInfo{ 5594 inputs: []inputInfo{ 5595 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5596 }, 5597 }, 5598 }, 5599 { 5600 name: "CMPBconst", 5601 auxType: auxInt8, 5602 argLen: 1, 5603 asm: x86.ACMPB, 5604 reg: regInfo{ 5605 inputs: []inputInfo{ 5606 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5607 }, 5608 }, 5609 }, 5610 { 5611 name: "UCOMISS", 5612 argLen: 2, 5613 asm: x86.AUCOMISS, 5614 reg: regInfo{ 5615 inputs: []inputInfo{ 5616 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5617 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5618 }, 5619 }, 5620 }, 5621 { 5622 name: "UCOMISD", 5623 argLen: 2, 5624 asm: x86.AUCOMISD, 5625 reg: regInfo{ 5626 inputs: []inputInfo{ 5627 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5628 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5629 }, 5630 }, 5631 }, 5632 { 5633 name: "BTL", 5634 argLen: 2, 5635 asm: x86.ABTL, 5636 reg: regInfo{ 5637 inputs: []inputInfo{ 5638 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5639 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5640 }, 5641 }, 5642 }, 5643 { 5644 name: "BTQ", 5645 argLen: 2, 5646 asm: x86.ABTQ, 5647 reg: regInfo{ 5648 inputs: []inputInfo{ 5649 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5650 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5651 }, 5652 }, 5653 }, 5654 { 5655 name: "BTLconst", 5656 auxType: auxInt8, 5657 argLen: 1, 5658 asm: x86.ABTL, 5659 reg: regInfo{ 5660 inputs: []inputInfo{ 5661 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5662 }, 5663 }, 5664 }, 5665 { 5666 name: "BTQconst", 5667 auxType: auxInt8, 5668 argLen: 1, 5669 asm: x86.ABTQ, 5670 reg: regInfo{ 5671 inputs: []inputInfo{ 5672 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5673 }, 5674 }, 5675 }, 5676 { 5677 name: "TESTQ", 5678 argLen: 2, 5679 commutative: true, 5680 asm: x86.ATESTQ, 5681 reg: regInfo{ 5682 inputs: []inputInfo{ 5683 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5684 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5685 }, 5686 }, 5687 }, 5688 { 5689 name: "TESTL", 5690 argLen: 2, 5691 commutative: true, 5692 asm: x86.ATESTL, 5693 reg: regInfo{ 5694 inputs: []inputInfo{ 5695 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5696 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5697 }, 5698 }, 5699 }, 5700 { 5701 name: "TESTW", 5702 argLen: 2, 5703 commutative: true, 5704 asm: x86.ATESTW, 5705 reg: regInfo{ 5706 inputs: []inputInfo{ 5707 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5708 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5709 }, 5710 }, 5711 }, 5712 { 5713 name: "TESTB", 5714 argLen: 2, 5715 commutative: true, 5716 asm: x86.ATESTB, 5717 reg: regInfo{ 5718 inputs: []inputInfo{ 5719 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5720 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5721 }, 5722 }, 5723 }, 5724 { 5725 name: "TESTQconst", 5726 auxType: auxInt32, 5727 argLen: 1, 5728 asm: x86.ATESTQ, 5729 reg: regInfo{ 5730 inputs: []inputInfo{ 5731 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5732 }, 5733 }, 5734 }, 5735 { 5736 name: "TESTLconst", 5737 auxType: auxInt32, 5738 argLen: 1, 5739 asm: x86.ATESTL, 5740 reg: regInfo{ 5741 inputs: []inputInfo{ 5742 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5743 }, 5744 }, 5745 }, 5746 { 5747 name: "TESTWconst", 5748 auxType: auxInt16, 5749 argLen: 1, 5750 asm: x86.ATESTW, 5751 reg: regInfo{ 5752 inputs: []inputInfo{ 5753 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5754 }, 5755 }, 5756 }, 5757 { 5758 name: "TESTBconst", 5759 auxType: auxInt8, 5760 argLen: 1, 5761 asm: x86.ATESTB, 5762 reg: regInfo{ 5763 inputs: []inputInfo{ 5764 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5765 }, 5766 }, 5767 }, 5768 { 5769 name: "SHLQ", 5770 argLen: 2, 5771 resultInArg0: true, 5772 clobberFlags: true, 5773 asm: x86.ASHLQ, 5774 reg: regInfo{ 5775 inputs: []inputInfo{ 5776 {1, 2}, // CX 5777 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5778 }, 5779 outputs: []outputInfo{ 5780 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5781 }, 5782 }, 5783 }, 5784 { 5785 name: "SHLL", 5786 argLen: 2, 5787 resultInArg0: true, 5788 clobberFlags: true, 5789 asm: x86.ASHLL, 5790 reg: regInfo{ 5791 inputs: []inputInfo{ 5792 {1, 2}, // CX 5793 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5794 }, 5795 outputs: []outputInfo{ 5796 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5797 }, 5798 }, 5799 }, 5800 { 5801 name: "SHLQconst", 5802 auxType: auxInt8, 5803 argLen: 1, 5804 resultInArg0: true, 5805 clobberFlags: true, 5806 asm: x86.ASHLQ, 5807 reg: regInfo{ 5808 inputs: []inputInfo{ 5809 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5810 }, 5811 outputs: []outputInfo{ 5812 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5813 }, 5814 }, 5815 }, 5816 { 5817 name: "SHLLconst", 5818 auxType: auxInt8, 5819 argLen: 1, 5820 resultInArg0: true, 5821 clobberFlags: true, 5822 asm: x86.ASHLL, 5823 reg: regInfo{ 5824 inputs: []inputInfo{ 5825 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5826 }, 5827 outputs: []outputInfo{ 5828 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5829 }, 5830 }, 5831 }, 5832 { 5833 name: "SHRQ", 5834 argLen: 2, 5835 resultInArg0: true, 5836 clobberFlags: true, 5837 asm: x86.ASHRQ, 5838 reg: regInfo{ 5839 inputs: []inputInfo{ 5840 {1, 2}, // CX 5841 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5842 }, 5843 outputs: []outputInfo{ 5844 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5845 }, 5846 }, 5847 }, 5848 { 5849 name: "SHRL", 5850 argLen: 2, 5851 resultInArg0: true, 5852 clobberFlags: true, 5853 asm: x86.ASHRL, 5854 reg: regInfo{ 5855 inputs: []inputInfo{ 5856 {1, 2}, // CX 5857 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5858 }, 5859 outputs: []outputInfo{ 5860 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5861 }, 5862 }, 5863 }, 5864 { 5865 name: "SHRW", 5866 argLen: 2, 5867 resultInArg0: true, 5868 clobberFlags: true, 5869 asm: x86.ASHRW, 5870 reg: regInfo{ 5871 inputs: []inputInfo{ 5872 {1, 2}, // CX 5873 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5874 }, 5875 outputs: []outputInfo{ 5876 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5877 }, 5878 }, 5879 }, 5880 { 5881 name: "SHRB", 5882 argLen: 2, 5883 resultInArg0: true, 5884 clobberFlags: true, 5885 asm: x86.ASHRB, 5886 reg: regInfo{ 5887 inputs: []inputInfo{ 5888 {1, 2}, // CX 5889 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5890 }, 5891 outputs: []outputInfo{ 5892 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5893 }, 5894 }, 5895 }, 5896 { 5897 name: "SHRQconst", 5898 auxType: auxInt8, 5899 argLen: 1, 5900 resultInArg0: true, 5901 clobberFlags: true, 5902 asm: x86.ASHRQ, 5903 reg: regInfo{ 5904 inputs: []inputInfo{ 5905 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5906 }, 5907 outputs: []outputInfo{ 5908 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5909 }, 5910 }, 5911 }, 5912 { 5913 name: "SHRLconst", 5914 auxType: auxInt8, 5915 argLen: 1, 5916 resultInArg0: true, 5917 clobberFlags: true, 5918 asm: x86.ASHRL, 5919 reg: regInfo{ 5920 inputs: []inputInfo{ 5921 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5922 }, 5923 outputs: []outputInfo{ 5924 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5925 }, 5926 }, 5927 }, 5928 { 5929 name: "SHRWconst", 5930 auxType: auxInt8, 5931 argLen: 1, 5932 resultInArg0: true, 5933 clobberFlags: true, 5934 asm: x86.ASHRW, 5935 reg: regInfo{ 5936 inputs: []inputInfo{ 5937 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5938 }, 5939 outputs: []outputInfo{ 5940 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5941 }, 5942 }, 5943 }, 5944 { 5945 name: "SHRBconst", 5946 auxType: auxInt8, 5947 argLen: 1, 5948 resultInArg0: true, 5949 clobberFlags: true, 5950 asm: x86.ASHRB, 5951 reg: regInfo{ 5952 inputs: []inputInfo{ 5953 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5954 }, 5955 outputs: []outputInfo{ 5956 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5957 }, 5958 }, 5959 }, 5960 { 5961 name: "SARQ", 5962 argLen: 2, 5963 resultInArg0: true, 5964 clobberFlags: true, 5965 asm: x86.ASARQ, 5966 reg: regInfo{ 5967 inputs: []inputInfo{ 5968 {1, 2}, // CX 5969 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5970 }, 5971 outputs: []outputInfo{ 5972 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5973 }, 5974 }, 5975 }, 5976 { 5977 name: "SARL", 5978 argLen: 2, 5979 resultInArg0: true, 5980 clobberFlags: true, 5981 asm: x86.ASARL, 5982 reg: regInfo{ 5983 inputs: []inputInfo{ 5984 {1, 2}, // CX 5985 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5986 }, 5987 outputs: []outputInfo{ 5988 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5989 }, 5990 }, 5991 }, 5992 { 5993 name: "SARW", 5994 argLen: 2, 5995 resultInArg0: true, 5996 clobberFlags: true, 5997 asm: x86.ASARW, 5998 reg: regInfo{ 5999 inputs: []inputInfo{ 6000 {1, 2}, // CX 6001 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6002 }, 6003 outputs: []outputInfo{ 6004 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6005 }, 6006 }, 6007 }, 6008 { 6009 name: "SARB", 6010 argLen: 2, 6011 resultInArg0: true, 6012 clobberFlags: true, 6013 asm: x86.ASARB, 6014 reg: regInfo{ 6015 inputs: []inputInfo{ 6016 {1, 2}, // CX 6017 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6018 }, 6019 outputs: []outputInfo{ 6020 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6021 }, 6022 }, 6023 }, 6024 { 6025 name: "SARQconst", 6026 auxType: auxInt8, 6027 argLen: 1, 6028 resultInArg0: true, 6029 clobberFlags: true, 6030 asm: x86.ASARQ, 6031 reg: regInfo{ 6032 inputs: []inputInfo{ 6033 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6034 }, 6035 outputs: []outputInfo{ 6036 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6037 }, 6038 }, 6039 }, 6040 { 6041 name: "SARLconst", 6042 auxType: auxInt8, 6043 argLen: 1, 6044 resultInArg0: true, 6045 clobberFlags: true, 6046 asm: x86.ASARL, 6047 reg: regInfo{ 6048 inputs: []inputInfo{ 6049 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6050 }, 6051 outputs: []outputInfo{ 6052 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6053 }, 6054 }, 6055 }, 6056 { 6057 name: "SARWconst", 6058 auxType: auxInt8, 6059 argLen: 1, 6060 resultInArg0: true, 6061 clobberFlags: true, 6062 asm: x86.ASARW, 6063 reg: regInfo{ 6064 inputs: []inputInfo{ 6065 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6066 }, 6067 outputs: []outputInfo{ 6068 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6069 }, 6070 }, 6071 }, 6072 { 6073 name: "SARBconst", 6074 auxType: auxInt8, 6075 argLen: 1, 6076 resultInArg0: true, 6077 clobberFlags: true, 6078 asm: x86.ASARB, 6079 reg: regInfo{ 6080 inputs: []inputInfo{ 6081 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6082 }, 6083 outputs: []outputInfo{ 6084 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6085 }, 6086 }, 6087 }, 6088 { 6089 name: "ROLQ", 6090 argLen: 2, 6091 resultInArg0: true, 6092 clobberFlags: true, 6093 asm: x86.AROLQ, 6094 reg: regInfo{ 6095 inputs: []inputInfo{ 6096 {1, 2}, // CX 6097 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6098 }, 6099 outputs: []outputInfo{ 6100 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6101 }, 6102 }, 6103 }, 6104 { 6105 name: "ROLL", 6106 argLen: 2, 6107 resultInArg0: true, 6108 clobberFlags: true, 6109 asm: x86.AROLL, 6110 reg: regInfo{ 6111 inputs: []inputInfo{ 6112 {1, 2}, // CX 6113 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6114 }, 6115 outputs: []outputInfo{ 6116 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6117 }, 6118 }, 6119 }, 6120 { 6121 name: "ROLW", 6122 argLen: 2, 6123 resultInArg0: true, 6124 clobberFlags: true, 6125 asm: x86.AROLW, 6126 reg: regInfo{ 6127 inputs: []inputInfo{ 6128 {1, 2}, // CX 6129 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6130 }, 6131 outputs: []outputInfo{ 6132 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6133 }, 6134 }, 6135 }, 6136 { 6137 name: "ROLB", 6138 argLen: 2, 6139 resultInArg0: true, 6140 clobberFlags: true, 6141 asm: x86.AROLB, 6142 reg: regInfo{ 6143 inputs: []inputInfo{ 6144 {1, 2}, // CX 6145 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6146 }, 6147 outputs: []outputInfo{ 6148 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6149 }, 6150 }, 6151 }, 6152 { 6153 name: "RORQ", 6154 argLen: 2, 6155 resultInArg0: true, 6156 clobberFlags: true, 6157 asm: x86.ARORQ, 6158 reg: regInfo{ 6159 inputs: []inputInfo{ 6160 {1, 2}, // CX 6161 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6162 }, 6163 outputs: []outputInfo{ 6164 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6165 }, 6166 }, 6167 }, 6168 { 6169 name: "RORL", 6170 argLen: 2, 6171 resultInArg0: true, 6172 clobberFlags: true, 6173 asm: x86.ARORL, 6174 reg: regInfo{ 6175 inputs: []inputInfo{ 6176 {1, 2}, // CX 6177 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6178 }, 6179 outputs: []outputInfo{ 6180 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6181 }, 6182 }, 6183 }, 6184 { 6185 name: "RORW", 6186 argLen: 2, 6187 resultInArg0: true, 6188 clobberFlags: true, 6189 asm: x86.ARORW, 6190 reg: regInfo{ 6191 inputs: []inputInfo{ 6192 {1, 2}, // CX 6193 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6194 }, 6195 outputs: []outputInfo{ 6196 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6197 }, 6198 }, 6199 }, 6200 { 6201 name: "RORB", 6202 argLen: 2, 6203 resultInArg0: true, 6204 clobberFlags: true, 6205 asm: x86.ARORB, 6206 reg: regInfo{ 6207 inputs: []inputInfo{ 6208 {1, 2}, // CX 6209 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6210 }, 6211 outputs: []outputInfo{ 6212 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6213 }, 6214 }, 6215 }, 6216 { 6217 name: "ROLQconst", 6218 auxType: auxInt8, 6219 argLen: 1, 6220 resultInArg0: true, 6221 clobberFlags: true, 6222 asm: x86.AROLQ, 6223 reg: regInfo{ 6224 inputs: []inputInfo{ 6225 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6226 }, 6227 outputs: []outputInfo{ 6228 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6229 }, 6230 }, 6231 }, 6232 { 6233 name: "ROLLconst", 6234 auxType: auxInt8, 6235 argLen: 1, 6236 resultInArg0: true, 6237 clobberFlags: true, 6238 asm: x86.AROLL, 6239 reg: regInfo{ 6240 inputs: []inputInfo{ 6241 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6242 }, 6243 outputs: []outputInfo{ 6244 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6245 }, 6246 }, 6247 }, 6248 { 6249 name: "ROLWconst", 6250 auxType: auxInt8, 6251 argLen: 1, 6252 resultInArg0: true, 6253 clobberFlags: true, 6254 asm: x86.AROLW, 6255 reg: regInfo{ 6256 inputs: []inputInfo{ 6257 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6258 }, 6259 outputs: []outputInfo{ 6260 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6261 }, 6262 }, 6263 }, 6264 { 6265 name: "ROLBconst", 6266 auxType: auxInt8, 6267 argLen: 1, 6268 resultInArg0: true, 6269 clobberFlags: true, 6270 asm: x86.AROLB, 6271 reg: regInfo{ 6272 inputs: []inputInfo{ 6273 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6274 }, 6275 outputs: []outputInfo{ 6276 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6277 }, 6278 }, 6279 }, 6280 { 6281 name: "ADDLmem", 6282 auxType: auxSymOff, 6283 argLen: 3, 6284 resultInArg0: true, 6285 clobberFlags: true, 6286 faultOnNilArg1: true, 6287 symEffect: SymRead, 6288 asm: x86.AADDL, 6289 reg: regInfo{ 6290 inputs: []inputInfo{ 6291 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6292 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6293 }, 6294 outputs: []outputInfo{ 6295 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6296 }, 6297 }, 6298 }, 6299 { 6300 name: "ADDQmem", 6301 auxType: auxSymOff, 6302 argLen: 3, 6303 resultInArg0: true, 6304 clobberFlags: true, 6305 faultOnNilArg1: true, 6306 symEffect: SymRead, 6307 asm: x86.AADDQ, 6308 reg: regInfo{ 6309 inputs: []inputInfo{ 6310 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6311 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6312 }, 6313 outputs: []outputInfo{ 6314 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6315 }, 6316 }, 6317 }, 6318 { 6319 name: "SUBQmem", 6320 auxType: auxSymOff, 6321 argLen: 3, 6322 resultInArg0: true, 6323 clobberFlags: true, 6324 faultOnNilArg1: true, 6325 symEffect: SymRead, 6326 asm: x86.ASUBQ, 6327 reg: regInfo{ 6328 inputs: []inputInfo{ 6329 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6330 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6331 }, 6332 outputs: []outputInfo{ 6333 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6334 }, 6335 }, 6336 }, 6337 { 6338 name: "SUBLmem", 6339 auxType: auxSymOff, 6340 argLen: 3, 6341 resultInArg0: true, 6342 clobberFlags: true, 6343 faultOnNilArg1: true, 6344 symEffect: SymRead, 6345 asm: x86.ASUBL, 6346 reg: regInfo{ 6347 inputs: []inputInfo{ 6348 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6349 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6350 }, 6351 outputs: []outputInfo{ 6352 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6353 }, 6354 }, 6355 }, 6356 { 6357 name: "ANDLmem", 6358 auxType: auxSymOff, 6359 argLen: 3, 6360 resultInArg0: true, 6361 clobberFlags: true, 6362 faultOnNilArg1: true, 6363 symEffect: SymRead, 6364 asm: x86.AANDL, 6365 reg: regInfo{ 6366 inputs: []inputInfo{ 6367 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6368 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6369 }, 6370 outputs: []outputInfo{ 6371 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6372 }, 6373 }, 6374 }, 6375 { 6376 name: "ANDQmem", 6377 auxType: auxSymOff, 6378 argLen: 3, 6379 resultInArg0: true, 6380 clobberFlags: true, 6381 faultOnNilArg1: true, 6382 symEffect: SymRead, 6383 asm: x86.AANDQ, 6384 reg: regInfo{ 6385 inputs: []inputInfo{ 6386 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6387 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6388 }, 6389 outputs: []outputInfo{ 6390 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6391 }, 6392 }, 6393 }, 6394 { 6395 name: "ORQmem", 6396 auxType: auxSymOff, 6397 argLen: 3, 6398 resultInArg0: true, 6399 clobberFlags: true, 6400 faultOnNilArg1: true, 6401 symEffect: SymRead, 6402 asm: x86.AORQ, 6403 reg: regInfo{ 6404 inputs: []inputInfo{ 6405 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6406 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6407 }, 6408 outputs: []outputInfo{ 6409 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6410 }, 6411 }, 6412 }, 6413 { 6414 name: "ORLmem", 6415 auxType: auxSymOff, 6416 argLen: 3, 6417 resultInArg0: true, 6418 clobberFlags: true, 6419 faultOnNilArg1: true, 6420 symEffect: SymRead, 6421 asm: x86.AORL, 6422 reg: regInfo{ 6423 inputs: []inputInfo{ 6424 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6425 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6426 }, 6427 outputs: []outputInfo{ 6428 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6429 }, 6430 }, 6431 }, 6432 { 6433 name: "XORQmem", 6434 auxType: auxSymOff, 6435 argLen: 3, 6436 resultInArg0: true, 6437 clobberFlags: true, 6438 faultOnNilArg1: true, 6439 symEffect: SymRead, 6440 asm: x86.AXORQ, 6441 reg: regInfo{ 6442 inputs: []inputInfo{ 6443 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6444 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6445 }, 6446 outputs: []outputInfo{ 6447 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6448 }, 6449 }, 6450 }, 6451 { 6452 name: "XORLmem", 6453 auxType: auxSymOff, 6454 argLen: 3, 6455 resultInArg0: true, 6456 clobberFlags: true, 6457 faultOnNilArg1: true, 6458 symEffect: SymRead, 6459 asm: x86.AXORL, 6460 reg: regInfo{ 6461 inputs: []inputInfo{ 6462 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6463 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6464 }, 6465 outputs: []outputInfo{ 6466 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6467 }, 6468 }, 6469 }, 6470 { 6471 name: "NEGQ", 6472 argLen: 1, 6473 resultInArg0: true, 6474 clobberFlags: true, 6475 asm: x86.ANEGQ, 6476 reg: regInfo{ 6477 inputs: []inputInfo{ 6478 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6479 }, 6480 outputs: []outputInfo{ 6481 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6482 }, 6483 }, 6484 }, 6485 { 6486 name: "NEGL", 6487 argLen: 1, 6488 resultInArg0: true, 6489 clobberFlags: true, 6490 asm: x86.ANEGL, 6491 reg: regInfo{ 6492 inputs: []inputInfo{ 6493 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6494 }, 6495 outputs: []outputInfo{ 6496 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6497 }, 6498 }, 6499 }, 6500 { 6501 name: "NOTQ", 6502 argLen: 1, 6503 resultInArg0: true, 6504 clobberFlags: true, 6505 asm: x86.ANOTQ, 6506 reg: regInfo{ 6507 inputs: []inputInfo{ 6508 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6509 }, 6510 outputs: []outputInfo{ 6511 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6512 }, 6513 }, 6514 }, 6515 { 6516 name: "NOTL", 6517 argLen: 1, 6518 resultInArg0: true, 6519 clobberFlags: true, 6520 asm: x86.ANOTL, 6521 reg: regInfo{ 6522 inputs: []inputInfo{ 6523 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6524 }, 6525 outputs: []outputInfo{ 6526 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6527 }, 6528 }, 6529 }, 6530 { 6531 name: "BSFQ", 6532 argLen: 1, 6533 asm: x86.ABSFQ, 6534 reg: regInfo{ 6535 inputs: []inputInfo{ 6536 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6537 }, 6538 outputs: []outputInfo{ 6539 {1, 0}, 6540 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6541 }, 6542 }, 6543 }, 6544 { 6545 name: "BSFL", 6546 argLen: 1, 6547 asm: x86.ABSFL, 6548 reg: regInfo{ 6549 inputs: []inputInfo{ 6550 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6551 }, 6552 outputs: []outputInfo{ 6553 {1, 0}, 6554 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6555 }, 6556 }, 6557 }, 6558 { 6559 name: "BSRQ", 6560 argLen: 1, 6561 asm: x86.ABSRQ, 6562 reg: regInfo{ 6563 inputs: []inputInfo{ 6564 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6565 }, 6566 outputs: []outputInfo{ 6567 {1, 0}, 6568 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6569 }, 6570 }, 6571 }, 6572 { 6573 name: "BSRL", 6574 argLen: 1, 6575 asm: x86.ABSRL, 6576 reg: regInfo{ 6577 inputs: []inputInfo{ 6578 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6579 }, 6580 outputs: []outputInfo{ 6581 {1, 0}, 6582 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6583 }, 6584 }, 6585 }, 6586 { 6587 name: "CMOVQEQ", 6588 argLen: 3, 6589 resultInArg0: true, 6590 asm: x86.ACMOVQEQ, 6591 reg: regInfo{ 6592 inputs: []inputInfo{ 6593 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6594 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6595 }, 6596 outputs: []outputInfo{ 6597 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6598 }, 6599 }, 6600 }, 6601 { 6602 name: "CMOVLEQ", 6603 argLen: 3, 6604 resultInArg0: true, 6605 asm: x86.ACMOVLEQ, 6606 reg: regInfo{ 6607 inputs: []inputInfo{ 6608 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6609 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6610 }, 6611 outputs: []outputInfo{ 6612 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6613 }, 6614 }, 6615 }, 6616 { 6617 name: "BSWAPQ", 6618 argLen: 1, 6619 resultInArg0: true, 6620 clobberFlags: true, 6621 asm: x86.ABSWAPQ, 6622 reg: regInfo{ 6623 inputs: []inputInfo{ 6624 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6625 }, 6626 outputs: []outputInfo{ 6627 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6628 }, 6629 }, 6630 }, 6631 { 6632 name: "BSWAPL", 6633 argLen: 1, 6634 resultInArg0: true, 6635 clobberFlags: true, 6636 asm: x86.ABSWAPL, 6637 reg: regInfo{ 6638 inputs: []inputInfo{ 6639 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6640 }, 6641 outputs: []outputInfo{ 6642 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6643 }, 6644 }, 6645 }, 6646 { 6647 name: "POPCNTQ", 6648 argLen: 1, 6649 clobberFlags: true, 6650 asm: x86.APOPCNTQ, 6651 reg: regInfo{ 6652 inputs: []inputInfo{ 6653 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6654 }, 6655 outputs: []outputInfo{ 6656 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6657 }, 6658 }, 6659 }, 6660 { 6661 name: "POPCNTL", 6662 argLen: 1, 6663 clobberFlags: true, 6664 asm: x86.APOPCNTL, 6665 reg: regInfo{ 6666 inputs: []inputInfo{ 6667 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6668 }, 6669 outputs: []outputInfo{ 6670 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6671 }, 6672 }, 6673 }, 6674 { 6675 name: "SQRTSD", 6676 argLen: 1, 6677 asm: x86.ASQRTSD, 6678 reg: regInfo{ 6679 inputs: []inputInfo{ 6680 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6681 }, 6682 outputs: []outputInfo{ 6683 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6684 }, 6685 }, 6686 }, 6687 { 6688 name: "SBBQcarrymask", 6689 argLen: 1, 6690 asm: x86.ASBBQ, 6691 reg: regInfo{ 6692 outputs: []outputInfo{ 6693 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6694 }, 6695 }, 6696 }, 6697 { 6698 name: "SBBLcarrymask", 6699 argLen: 1, 6700 asm: x86.ASBBL, 6701 reg: regInfo{ 6702 outputs: []outputInfo{ 6703 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6704 }, 6705 }, 6706 }, 6707 { 6708 name: "SETEQ", 6709 argLen: 1, 6710 asm: x86.ASETEQ, 6711 reg: regInfo{ 6712 outputs: []outputInfo{ 6713 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6714 }, 6715 }, 6716 }, 6717 { 6718 name: "SETNE", 6719 argLen: 1, 6720 asm: x86.ASETNE, 6721 reg: regInfo{ 6722 outputs: []outputInfo{ 6723 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6724 }, 6725 }, 6726 }, 6727 { 6728 name: "SETL", 6729 argLen: 1, 6730 asm: x86.ASETLT, 6731 reg: regInfo{ 6732 outputs: []outputInfo{ 6733 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6734 }, 6735 }, 6736 }, 6737 { 6738 name: "SETLE", 6739 argLen: 1, 6740 asm: x86.ASETLE, 6741 reg: regInfo{ 6742 outputs: []outputInfo{ 6743 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6744 }, 6745 }, 6746 }, 6747 { 6748 name: "SETG", 6749 argLen: 1, 6750 asm: x86.ASETGT, 6751 reg: regInfo{ 6752 outputs: []outputInfo{ 6753 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6754 }, 6755 }, 6756 }, 6757 { 6758 name: "SETGE", 6759 argLen: 1, 6760 asm: x86.ASETGE, 6761 reg: regInfo{ 6762 outputs: []outputInfo{ 6763 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6764 }, 6765 }, 6766 }, 6767 { 6768 name: "SETB", 6769 argLen: 1, 6770 asm: x86.ASETCS, 6771 reg: regInfo{ 6772 outputs: []outputInfo{ 6773 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6774 }, 6775 }, 6776 }, 6777 { 6778 name: "SETBE", 6779 argLen: 1, 6780 asm: x86.ASETLS, 6781 reg: regInfo{ 6782 outputs: []outputInfo{ 6783 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6784 }, 6785 }, 6786 }, 6787 { 6788 name: "SETA", 6789 argLen: 1, 6790 asm: x86.ASETHI, 6791 reg: regInfo{ 6792 outputs: []outputInfo{ 6793 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6794 }, 6795 }, 6796 }, 6797 { 6798 name: "SETAE", 6799 argLen: 1, 6800 asm: x86.ASETCC, 6801 reg: regInfo{ 6802 outputs: []outputInfo{ 6803 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6804 }, 6805 }, 6806 }, 6807 { 6808 name: "SETEQmem", 6809 auxType: auxSymOff, 6810 argLen: 3, 6811 faultOnNilArg0: true, 6812 symEffect: SymWrite, 6813 asm: x86.ASETEQ, 6814 reg: regInfo{ 6815 inputs: []inputInfo{ 6816 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6817 }, 6818 }, 6819 }, 6820 { 6821 name: "SETNEmem", 6822 auxType: auxSymOff, 6823 argLen: 3, 6824 faultOnNilArg0: true, 6825 symEffect: SymWrite, 6826 asm: x86.ASETNE, 6827 reg: regInfo{ 6828 inputs: []inputInfo{ 6829 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6830 }, 6831 }, 6832 }, 6833 { 6834 name: "SETLmem", 6835 auxType: auxSymOff, 6836 argLen: 3, 6837 faultOnNilArg0: true, 6838 symEffect: SymWrite, 6839 asm: x86.ASETLT, 6840 reg: regInfo{ 6841 inputs: []inputInfo{ 6842 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6843 }, 6844 }, 6845 }, 6846 { 6847 name: "SETLEmem", 6848 auxType: auxSymOff, 6849 argLen: 3, 6850 faultOnNilArg0: true, 6851 symEffect: SymWrite, 6852 asm: x86.ASETLE, 6853 reg: regInfo{ 6854 inputs: []inputInfo{ 6855 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6856 }, 6857 }, 6858 }, 6859 { 6860 name: "SETGmem", 6861 auxType: auxSymOff, 6862 argLen: 3, 6863 faultOnNilArg0: true, 6864 symEffect: SymWrite, 6865 asm: x86.ASETGT, 6866 reg: regInfo{ 6867 inputs: []inputInfo{ 6868 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6869 }, 6870 }, 6871 }, 6872 { 6873 name: "SETGEmem", 6874 auxType: auxSymOff, 6875 argLen: 3, 6876 faultOnNilArg0: true, 6877 symEffect: SymWrite, 6878 asm: x86.ASETGE, 6879 reg: regInfo{ 6880 inputs: []inputInfo{ 6881 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6882 }, 6883 }, 6884 }, 6885 { 6886 name: "SETBmem", 6887 auxType: auxSymOff, 6888 argLen: 3, 6889 faultOnNilArg0: true, 6890 symEffect: SymWrite, 6891 asm: x86.ASETCS, 6892 reg: regInfo{ 6893 inputs: []inputInfo{ 6894 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6895 }, 6896 }, 6897 }, 6898 { 6899 name: "SETBEmem", 6900 auxType: auxSymOff, 6901 argLen: 3, 6902 faultOnNilArg0: true, 6903 symEffect: SymWrite, 6904 asm: x86.ASETLS, 6905 reg: regInfo{ 6906 inputs: []inputInfo{ 6907 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6908 }, 6909 }, 6910 }, 6911 { 6912 name: "SETAmem", 6913 auxType: auxSymOff, 6914 argLen: 3, 6915 faultOnNilArg0: true, 6916 symEffect: SymWrite, 6917 asm: x86.ASETHI, 6918 reg: regInfo{ 6919 inputs: []inputInfo{ 6920 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6921 }, 6922 }, 6923 }, 6924 { 6925 name: "SETAEmem", 6926 auxType: auxSymOff, 6927 argLen: 3, 6928 faultOnNilArg0: true, 6929 symEffect: SymWrite, 6930 asm: x86.ASETCC, 6931 reg: regInfo{ 6932 inputs: []inputInfo{ 6933 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6934 }, 6935 }, 6936 }, 6937 { 6938 name: "SETEQF", 6939 argLen: 1, 6940 clobberFlags: true, 6941 asm: x86.ASETEQ, 6942 reg: regInfo{ 6943 clobbers: 1, // AX 6944 outputs: []outputInfo{ 6945 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6946 }, 6947 }, 6948 }, 6949 { 6950 name: "SETNEF", 6951 argLen: 1, 6952 clobberFlags: true, 6953 asm: x86.ASETNE, 6954 reg: regInfo{ 6955 clobbers: 1, // AX 6956 outputs: []outputInfo{ 6957 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6958 }, 6959 }, 6960 }, 6961 { 6962 name: "SETORD", 6963 argLen: 1, 6964 asm: x86.ASETPC, 6965 reg: regInfo{ 6966 outputs: []outputInfo{ 6967 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6968 }, 6969 }, 6970 }, 6971 { 6972 name: "SETNAN", 6973 argLen: 1, 6974 asm: x86.ASETPS, 6975 reg: regInfo{ 6976 outputs: []outputInfo{ 6977 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6978 }, 6979 }, 6980 }, 6981 { 6982 name: "SETGF", 6983 argLen: 1, 6984 asm: x86.ASETHI, 6985 reg: regInfo{ 6986 outputs: []outputInfo{ 6987 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6988 }, 6989 }, 6990 }, 6991 { 6992 name: "SETGEF", 6993 argLen: 1, 6994 asm: x86.ASETCC, 6995 reg: regInfo{ 6996 outputs: []outputInfo{ 6997 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6998 }, 6999 }, 7000 }, 7001 { 7002 name: "MOVBQSX", 7003 argLen: 1, 7004 asm: x86.AMOVBQSX, 7005 reg: regInfo{ 7006 inputs: []inputInfo{ 7007 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7008 }, 7009 outputs: []outputInfo{ 7010 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7011 }, 7012 }, 7013 }, 7014 { 7015 name: "MOVBQZX", 7016 argLen: 1, 7017 asm: x86.AMOVBLZX, 7018 reg: regInfo{ 7019 inputs: []inputInfo{ 7020 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7021 }, 7022 outputs: []outputInfo{ 7023 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7024 }, 7025 }, 7026 }, 7027 { 7028 name: "MOVWQSX", 7029 argLen: 1, 7030 asm: x86.AMOVWQSX, 7031 reg: regInfo{ 7032 inputs: []inputInfo{ 7033 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7034 }, 7035 outputs: []outputInfo{ 7036 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7037 }, 7038 }, 7039 }, 7040 { 7041 name: "MOVWQZX", 7042 argLen: 1, 7043 asm: x86.AMOVWLZX, 7044 reg: regInfo{ 7045 inputs: []inputInfo{ 7046 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7047 }, 7048 outputs: []outputInfo{ 7049 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7050 }, 7051 }, 7052 }, 7053 { 7054 name: "MOVLQSX", 7055 argLen: 1, 7056 asm: x86.AMOVLQSX, 7057 reg: regInfo{ 7058 inputs: []inputInfo{ 7059 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7060 }, 7061 outputs: []outputInfo{ 7062 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7063 }, 7064 }, 7065 }, 7066 { 7067 name: "MOVLQZX", 7068 argLen: 1, 7069 asm: x86.AMOVL, 7070 reg: regInfo{ 7071 inputs: []inputInfo{ 7072 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7073 }, 7074 outputs: []outputInfo{ 7075 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7076 }, 7077 }, 7078 }, 7079 { 7080 name: "MOVLconst", 7081 auxType: auxInt32, 7082 argLen: 0, 7083 rematerializeable: true, 7084 asm: x86.AMOVL, 7085 reg: regInfo{ 7086 outputs: []outputInfo{ 7087 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7088 }, 7089 }, 7090 }, 7091 { 7092 name: "MOVQconst", 7093 auxType: auxInt64, 7094 argLen: 0, 7095 rematerializeable: true, 7096 asm: x86.AMOVQ, 7097 reg: regInfo{ 7098 outputs: []outputInfo{ 7099 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7100 }, 7101 }, 7102 }, 7103 { 7104 name: "CVTTSD2SL", 7105 argLen: 1, 7106 asm: x86.ACVTTSD2SL, 7107 reg: regInfo{ 7108 inputs: []inputInfo{ 7109 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7110 }, 7111 outputs: []outputInfo{ 7112 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7113 }, 7114 }, 7115 }, 7116 { 7117 name: "CVTTSD2SQ", 7118 argLen: 1, 7119 asm: x86.ACVTTSD2SQ, 7120 reg: regInfo{ 7121 inputs: []inputInfo{ 7122 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7123 }, 7124 outputs: []outputInfo{ 7125 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7126 }, 7127 }, 7128 }, 7129 { 7130 name: "CVTTSS2SL", 7131 argLen: 1, 7132 asm: x86.ACVTTSS2SL, 7133 reg: regInfo{ 7134 inputs: []inputInfo{ 7135 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7136 }, 7137 outputs: []outputInfo{ 7138 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7139 }, 7140 }, 7141 }, 7142 { 7143 name: "CVTTSS2SQ", 7144 argLen: 1, 7145 asm: x86.ACVTTSS2SQ, 7146 reg: regInfo{ 7147 inputs: []inputInfo{ 7148 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7149 }, 7150 outputs: []outputInfo{ 7151 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7152 }, 7153 }, 7154 }, 7155 { 7156 name: "CVTSL2SS", 7157 argLen: 1, 7158 asm: x86.ACVTSL2SS, 7159 reg: regInfo{ 7160 inputs: []inputInfo{ 7161 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7162 }, 7163 outputs: []outputInfo{ 7164 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7165 }, 7166 }, 7167 }, 7168 { 7169 name: "CVTSL2SD", 7170 argLen: 1, 7171 asm: x86.ACVTSL2SD, 7172 reg: regInfo{ 7173 inputs: []inputInfo{ 7174 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7175 }, 7176 outputs: []outputInfo{ 7177 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7178 }, 7179 }, 7180 }, 7181 { 7182 name: "CVTSQ2SS", 7183 argLen: 1, 7184 asm: x86.ACVTSQ2SS, 7185 reg: regInfo{ 7186 inputs: []inputInfo{ 7187 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7188 }, 7189 outputs: []outputInfo{ 7190 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7191 }, 7192 }, 7193 }, 7194 { 7195 name: "CVTSQ2SD", 7196 argLen: 1, 7197 asm: x86.ACVTSQ2SD, 7198 reg: regInfo{ 7199 inputs: []inputInfo{ 7200 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7201 }, 7202 outputs: []outputInfo{ 7203 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7204 }, 7205 }, 7206 }, 7207 { 7208 name: "CVTSD2SS", 7209 argLen: 1, 7210 asm: x86.ACVTSD2SS, 7211 reg: regInfo{ 7212 inputs: []inputInfo{ 7213 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7214 }, 7215 outputs: []outputInfo{ 7216 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7217 }, 7218 }, 7219 }, 7220 { 7221 name: "CVTSS2SD", 7222 argLen: 1, 7223 asm: x86.ACVTSS2SD, 7224 reg: regInfo{ 7225 inputs: []inputInfo{ 7226 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7227 }, 7228 outputs: []outputInfo{ 7229 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7230 }, 7231 }, 7232 }, 7233 { 7234 name: "MOVQi2f", 7235 argLen: 1, 7236 reg: regInfo{ 7237 inputs: []inputInfo{ 7238 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7239 }, 7240 outputs: []outputInfo{ 7241 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7242 }, 7243 }, 7244 }, 7245 { 7246 name: "MOVQf2i", 7247 argLen: 1, 7248 reg: regInfo{ 7249 inputs: []inputInfo{ 7250 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7251 }, 7252 outputs: []outputInfo{ 7253 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7254 }, 7255 }, 7256 }, 7257 { 7258 name: "MOVLi2f", 7259 argLen: 1, 7260 reg: regInfo{ 7261 inputs: []inputInfo{ 7262 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7263 }, 7264 outputs: []outputInfo{ 7265 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7266 }, 7267 }, 7268 }, 7269 { 7270 name: "MOVLf2i", 7271 argLen: 1, 7272 reg: regInfo{ 7273 inputs: []inputInfo{ 7274 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7275 }, 7276 outputs: []outputInfo{ 7277 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7278 }, 7279 }, 7280 }, 7281 { 7282 name: "PXOR", 7283 argLen: 2, 7284 commutative: true, 7285 resultInArg0: true, 7286 asm: x86.APXOR, 7287 reg: regInfo{ 7288 inputs: []inputInfo{ 7289 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7290 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7291 }, 7292 outputs: []outputInfo{ 7293 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7294 }, 7295 }, 7296 }, 7297 { 7298 name: "LEAQ", 7299 auxType: auxSymOff, 7300 argLen: 1, 7301 rematerializeable: true, 7302 symEffect: SymAddr, 7303 asm: x86.ALEAQ, 7304 reg: regInfo{ 7305 inputs: []inputInfo{ 7306 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7307 }, 7308 outputs: []outputInfo{ 7309 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7310 }, 7311 }, 7312 }, 7313 { 7314 name: "LEAQ1", 7315 auxType: auxSymOff, 7316 argLen: 2, 7317 commutative: true, 7318 symEffect: SymAddr, 7319 reg: regInfo{ 7320 inputs: []inputInfo{ 7321 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7322 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7323 }, 7324 outputs: []outputInfo{ 7325 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7326 }, 7327 }, 7328 }, 7329 { 7330 name: "LEAQ2", 7331 auxType: auxSymOff, 7332 argLen: 2, 7333 symEffect: SymAddr, 7334 reg: regInfo{ 7335 inputs: []inputInfo{ 7336 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7337 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7338 }, 7339 outputs: []outputInfo{ 7340 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7341 }, 7342 }, 7343 }, 7344 { 7345 name: "LEAQ4", 7346 auxType: auxSymOff, 7347 argLen: 2, 7348 symEffect: SymAddr, 7349 reg: regInfo{ 7350 inputs: []inputInfo{ 7351 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7352 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7353 }, 7354 outputs: []outputInfo{ 7355 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7356 }, 7357 }, 7358 }, 7359 { 7360 name: "LEAQ8", 7361 auxType: auxSymOff, 7362 argLen: 2, 7363 symEffect: SymAddr, 7364 reg: regInfo{ 7365 inputs: []inputInfo{ 7366 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7367 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7368 }, 7369 outputs: []outputInfo{ 7370 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7371 }, 7372 }, 7373 }, 7374 { 7375 name: "LEAL", 7376 auxType: auxSymOff, 7377 argLen: 1, 7378 rematerializeable: true, 7379 symEffect: SymAddr, 7380 asm: x86.ALEAL, 7381 reg: regInfo{ 7382 inputs: []inputInfo{ 7383 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7384 }, 7385 outputs: []outputInfo{ 7386 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7387 }, 7388 }, 7389 }, 7390 { 7391 name: "MOVBload", 7392 auxType: auxSymOff, 7393 argLen: 2, 7394 faultOnNilArg0: true, 7395 symEffect: SymRead, 7396 asm: x86.AMOVBLZX, 7397 reg: regInfo{ 7398 inputs: []inputInfo{ 7399 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7400 }, 7401 outputs: []outputInfo{ 7402 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7403 }, 7404 }, 7405 }, 7406 { 7407 name: "MOVBQSXload", 7408 auxType: auxSymOff, 7409 argLen: 2, 7410 faultOnNilArg0: true, 7411 symEffect: SymRead, 7412 asm: x86.AMOVBQSX, 7413 reg: regInfo{ 7414 inputs: []inputInfo{ 7415 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7416 }, 7417 outputs: []outputInfo{ 7418 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7419 }, 7420 }, 7421 }, 7422 { 7423 name: "MOVWload", 7424 auxType: auxSymOff, 7425 argLen: 2, 7426 faultOnNilArg0: true, 7427 symEffect: SymRead, 7428 asm: x86.AMOVWLZX, 7429 reg: regInfo{ 7430 inputs: []inputInfo{ 7431 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7432 }, 7433 outputs: []outputInfo{ 7434 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7435 }, 7436 }, 7437 }, 7438 { 7439 name: "MOVWQSXload", 7440 auxType: auxSymOff, 7441 argLen: 2, 7442 faultOnNilArg0: true, 7443 symEffect: SymRead, 7444 asm: x86.AMOVWQSX, 7445 reg: regInfo{ 7446 inputs: []inputInfo{ 7447 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7448 }, 7449 outputs: []outputInfo{ 7450 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7451 }, 7452 }, 7453 }, 7454 { 7455 name: "MOVLload", 7456 auxType: auxSymOff, 7457 argLen: 2, 7458 faultOnNilArg0: true, 7459 symEffect: SymRead, 7460 asm: x86.AMOVL, 7461 reg: regInfo{ 7462 inputs: []inputInfo{ 7463 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7464 }, 7465 outputs: []outputInfo{ 7466 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7467 }, 7468 }, 7469 }, 7470 { 7471 name: "MOVLQSXload", 7472 auxType: auxSymOff, 7473 argLen: 2, 7474 faultOnNilArg0: true, 7475 symEffect: SymRead, 7476 asm: x86.AMOVLQSX, 7477 reg: regInfo{ 7478 inputs: []inputInfo{ 7479 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7480 }, 7481 outputs: []outputInfo{ 7482 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7483 }, 7484 }, 7485 }, 7486 { 7487 name: "MOVQload", 7488 auxType: auxSymOff, 7489 argLen: 2, 7490 faultOnNilArg0: true, 7491 symEffect: SymRead, 7492 asm: x86.AMOVQ, 7493 reg: regInfo{ 7494 inputs: []inputInfo{ 7495 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7496 }, 7497 outputs: []outputInfo{ 7498 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7499 }, 7500 }, 7501 }, 7502 { 7503 name: "MOVBstore", 7504 auxType: auxSymOff, 7505 argLen: 3, 7506 faultOnNilArg0: true, 7507 symEffect: SymWrite, 7508 asm: x86.AMOVB, 7509 reg: regInfo{ 7510 inputs: []inputInfo{ 7511 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7512 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7513 }, 7514 }, 7515 }, 7516 { 7517 name: "MOVWstore", 7518 auxType: auxSymOff, 7519 argLen: 3, 7520 faultOnNilArg0: true, 7521 symEffect: SymWrite, 7522 asm: x86.AMOVW, 7523 reg: regInfo{ 7524 inputs: []inputInfo{ 7525 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7526 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7527 }, 7528 }, 7529 }, 7530 { 7531 name: "MOVLstore", 7532 auxType: auxSymOff, 7533 argLen: 3, 7534 faultOnNilArg0: true, 7535 symEffect: SymWrite, 7536 asm: x86.AMOVL, 7537 reg: regInfo{ 7538 inputs: []inputInfo{ 7539 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7540 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7541 }, 7542 }, 7543 }, 7544 { 7545 name: "MOVQstore", 7546 auxType: auxSymOff, 7547 argLen: 3, 7548 faultOnNilArg0: true, 7549 symEffect: SymWrite, 7550 asm: x86.AMOVQ, 7551 reg: regInfo{ 7552 inputs: []inputInfo{ 7553 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7554 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7555 }, 7556 }, 7557 }, 7558 { 7559 name: "MOVOload", 7560 auxType: auxSymOff, 7561 argLen: 2, 7562 faultOnNilArg0: true, 7563 symEffect: SymRead, 7564 asm: x86.AMOVUPS, 7565 reg: regInfo{ 7566 inputs: []inputInfo{ 7567 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7568 }, 7569 outputs: []outputInfo{ 7570 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7571 }, 7572 }, 7573 }, 7574 { 7575 name: "MOVOstore", 7576 auxType: auxSymOff, 7577 argLen: 3, 7578 faultOnNilArg0: true, 7579 symEffect: SymWrite, 7580 asm: x86.AMOVUPS, 7581 reg: regInfo{ 7582 inputs: []inputInfo{ 7583 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7584 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7585 }, 7586 }, 7587 }, 7588 { 7589 name: "MOVBloadidx1", 7590 auxType: auxSymOff, 7591 argLen: 3, 7592 commutative: true, 7593 symEffect: SymRead, 7594 asm: x86.AMOVBLZX, 7595 reg: regInfo{ 7596 inputs: []inputInfo{ 7597 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7598 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7599 }, 7600 outputs: []outputInfo{ 7601 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7602 }, 7603 }, 7604 }, 7605 { 7606 name: "MOVWloadidx1", 7607 auxType: auxSymOff, 7608 argLen: 3, 7609 commutative: true, 7610 symEffect: SymRead, 7611 asm: x86.AMOVWLZX, 7612 reg: regInfo{ 7613 inputs: []inputInfo{ 7614 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7615 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7616 }, 7617 outputs: []outputInfo{ 7618 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7619 }, 7620 }, 7621 }, 7622 { 7623 name: "MOVWloadidx2", 7624 auxType: auxSymOff, 7625 argLen: 3, 7626 symEffect: SymRead, 7627 asm: x86.AMOVWLZX, 7628 reg: regInfo{ 7629 inputs: []inputInfo{ 7630 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7631 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7632 }, 7633 outputs: []outputInfo{ 7634 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7635 }, 7636 }, 7637 }, 7638 { 7639 name: "MOVLloadidx1", 7640 auxType: auxSymOff, 7641 argLen: 3, 7642 commutative: true, 7643 symEffect: SymRead, 7644 asm: x86.AMOVL, 7645 reg: regInfo{ 7646 inputs: []inputInfo{ 7647 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7648 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7649 }, 7650 outputs: []outputInfo{ 7651 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7652 }, 7653 }, 7654 }, 7655 { 7656 name: "MOVLloadidx4", 7657 auxType: auxSymOff, 7658 argLen: 3, 7659 symEffect: SymRead, 7660 asm: x86.AMOVL, 7661 reg: regInfo{ 7662 inputs: []inputInfo{ 7663 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7664 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7665 }, 7666 outputs: []outputInfo{ 7667 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7668 }, 7669 }, 7670 }, 7671 { 7672 name: "MOVLloadidx8", 7673 auxType: auxSymOff, 7674 argLen: 3, 7675 symEffect: SymRead, 7676 asm: x86.AMOVL, 7677 reg: regInfo{ 7678 inputs: []inputInfo{ 7679 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7680 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7681 }, 7682 outputs: []outputInfo{ 7683 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7684 }, 7685 }, 7686 }, 7687 { 7688 name: "MOVQloadidx1", 7689 auxType: auxSymOff, 7690 argLen: 3, 7691 commutative: true, 7692 symEffect: SymRead, 7693 asm: x86.AMOVQ, 7694 reg: regInfo{ 7695 inputs: []inputInfo{ 7696 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7697 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7698 }, 7699 outputs: []outputInfo{ 7700 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7701 }, 7702 }, 7703 }, 7704 { 7705 name: "MOVQloadidx8", 7706 auxType: auxSymOff, 7707 argLen: 3, 7708 symEffect: SymRead, 7709 asm: x86.AMOVQ, 7710 reg: regInfo{ 7711 inputs: []inputInfo{ 7712 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7713 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7714 }, 7715 outputs: []outputInfo{ 7716 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7717 }, 7718 }, 7719 }, 7720 { 7721 name: "MOVBstoreidx1", 7722 auxType: auxSymOff, 7723 argLen: 4, 7724 symEffect: SymWrite, 7725 asm: x86.AMOVB, 7726 reg: regInfo{ 7727 inputs: []inputInfo{ 7728 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7729 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7730 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7731 }, 7732 }, 7733 }, 7734 { 7735 name: "MOVWstoreidx1", 7736 auxType: auxSymOff, 7737 argLen: 4, 7738 symEffect: SymWrite, 7739 asm: x86.AMOVW, 7740 reg: regInfo{ 7741 inputs: []inputInfo{ 7742 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7743 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7744 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7745 }, 7746 }, 7747 }, 7748 { 7749 name: "MOVWstoreidx2", 7750 auxType: auxSymOff, 7751 argLen: 4, 7752 symEffect: SymWrite, 7753 asm: x86.AMOVW, 7754 reg: regInfo{ 7755 inputs: []inputInfo{ 7756 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7757 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7758 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7759 }, 7760 }, 7761 }, 7762 { 7763 name: "MOVLstoreidx1", 7764 auxType: auxSymOff, 7765 argLen: 4, 7766 symEffect: SymWrite, 7767 asm: x86.AMOVL, 7768 reg: regInfo{ 7769 inputs: []inputInfo{ 7770 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7771 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7772 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7773 }, 7774 }, 7775 }, 7776 { 7777 name: "MOVLstoreidx4", 7778 auxType: auxSymOff, 7779 argLen: 4, 7780 symEffect: SymWrite, 7781 asm: x86.AMOVL, 7782 reg: regInfo{ 7783 inputs: []inputInfo{ 7784 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7785 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7786 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7787 }, 7788 }, 7789 }, 7790 { 7791 name: "MOVLstoreidx8", 7792 auxType: auxSymOff, 7793 argLen: 4, 7794 symEffect: SymWrite, 7795 asm: x86.AMOVL, 7796 reg: regInfo{ 7797 inputs: []inputInfo{ 7798 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7799 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7800 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7801 }, 7802 }, 7803 }, 7804 { 7805 name: "MOVQstoreidx1", 7806 auxType: auxSymOff, 7807 argLen: 4, 7808 symEffect: SymWrite, 7809 asm: x86.AMOVQ, 7810 reg: regInfo{ 7811 inputs: []inputInfo{ 7812 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7813 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7814 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7815 }, 7816 }, 7817 }, 7818 { 7819 name: "MOVQstoreidx8", 7820 auxType: auxSymOff, 7821 argLen: 4, 7822 symEffect: SymWrite, 7823 asm: x86.AMOVQ, 7824 reg: regInfo{ 7825 inputs: []inputInfo{ 7826 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7827 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7828 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7829 }, 7830 }, 7831 }, 7832 { 7833 name: "MOVBstoreconst", 7834 auxType: auxSymValAndOff, 7835 argLen: 2, 7836 faultOnNilArg0: true, 7837 symEffect: SymWrite, 7838 asm: x86.AMOVB, 7839 reg: regInfo{ 7840 inputs: []inputInfo{ 7841 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7842 }, 7843 }, 7844 }, 7845 { 7846 name: "MOVWstoreconst", 7847 auxType: auxSymValAndOff, 7848 argLen: 2, 7849 faultOnNilArg0: true, 7850 symEffect: SymWrite, 7851 asm: x86.AMOVW, 7852 reg: regInfo{ 7853 inputs: []inputInfo{ 7854 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7855 }, 7856 }, 7857 }, 7858 { 7859 name: "MOVLstoreconst", 7860 auxType: auxSymValAndOff, 7861 argLen: 2, 7862 faultOnNilArg0: true, 7863 symEffect: SymWrite, 7864 asm: x86.AMOVL, 7865 reg: regInfo{ 7866 inputs: []inputInfo{ 7867 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7868 }, 7869 }, 7870 }, 7871 { 7872 name: "MOVQstoreconst", 7873 auxType: auxSymValAndOff, 7874 argLen: 2, 7875 faultOnNilArg0: true, 7876 symEffect: SymWrite, 7877 asm: x86.AMOVQ, 7878 reg: regInfo{ 7879 inputs: []inputInfo{ 7880 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7881 }, 7882 }, 7883 }, 7884 { 7885 name: "MOVBstoreconstidx1", 7886 auxType: auxSymValAndOff, 7887 argLen: 3, 7888 symEffect: SymWrite, 7889 asm: x86.AMOVB, 7890 reg: regInfo{ 7891 inputs: []inputInfo{ 7892 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7893 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7894 }, 7895 }, 7896 }, 7897 { 7898 name: "MOVWstoreconstidx1", 7899 auxType: auxSymValAndOff, 7900 argLen: 3, 7901 symEffect: SymWrite, 7902 asm: x86.AMOVW, 7903 reg: regInfo{ 7904 inputs: []inputInfo{ 7905 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7906 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7907 }, 7908 }, 7909 }, 7910 { 7911 name: "MOVWstoreconstidx2", 7912 auxType: auxSymValAndOff, 7913 argLen: 3, 7914 symEffect: SymWrite, 7915 asm: x86.AMOVW, 7916 reg: regInfo{ 7917 inputs: []inputInfo{ 7918 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7919 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7920 }, 7921 }, 7922 }, 7923 { 7924 name: "MOVLstoreconstidx1", 7925 auxType: auxSymValAndOff, 7926 argLen: 3, 7927 symEffect: SymWrite, 7928 asm: x86.AMOVL, 7929 reg: regInfo{ 7930 inputs: []inputInfo{ 7931 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7932 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7933 }, 7934 }, 7935 }, 7936 { 7937 name: "MOVLstoreconstidx4", 7938 auxType: auxSymValAndOff, 7939 argLen: 3, 7940 symEffect: SymWrite, 7941 asm: x86.AMOVL, 7942 reg: regInfo{ 7943 inputs: []inputInfo{ 7944 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7945 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7946 }, 7947 }, 7948 }, 7949 { 7950 name: "MOVQstoreconstidx1", 7951 auxType: auxSymValAndOff, 7952 argLen: 3, 7953 symEffect: SymWrite, 7954 asm: x86.AMOVQ, 7955 reg: regInfo{ 7956 inputs: []inputInfo{ 7957 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7958 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7959 }, 7960 }, 7961 }, 7962 { 7963 name: "MOVQstoreconstidx8", 7964 auxType: auxSymValAndOff, 7965 argLen: 3, 7966 symEffect: SymWrite, 7967 asm: x86.AMOVQ, 7968 reg: regInfo{ 7969 inputs: []inputInfo{ 7970 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7971 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7972 }, 7973 }, 7974 }, 7975 { 7976 name: "DUFFZERO", 7977 auxType: auxInt64, 7978 argLen: 3, 7979 faultOnNilArg0: true, 7980 reg: regInfo{ 7981 inputs: []inputInfo{ 7982 {0, 128}, // DI 7983 {1, 65536}, // X0 7984 }, 7985 clobbers: 128, // DI 7986 }, 7987 }, 7988 { 7989 name: "MOVOconst", 7990 auxType: auxInt128, 7991 argLen: 0, 7992 rematerializeable: true, 7993 reg: regInfo{ 7994 outputs: []outputInfo{ 7995 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7996 }, 7997 }, 7998 }, 7999 { 8000 name: "REPSTOSQ", 8001 argLen: 4, 8002 faultOnNilArg0: true, 8003 reg: regInfo{ 8004 inputs: []inputInfo{ 8005 {0, 128}, // DI 8006 {1, 2}, // CX 8007 {2, 1}, // AX 8008 }, 8009 clobbers: 130, // CX DI 8010 }, 8011 }, 8012 { 8013 name: "CALLstatic", 8014 auxType: auxSymOff, 8015 argLen: 1, 8016 clobberFlags: true, 8017 call: true, 8018 symEffect: SymNone, 8019 reg: regInfo{ 8020 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 8021 }, 8022 }, 8023 { 8024 name: "CALLclosure", 8025 auxType: auxInt64, 8026 argLen: 3, 8027 clobberFlags: true, 8028 call: true, 8029 reg: regInfo{ 8030 inputs: []inputInfo{ 8031 {1, 4}, // DX 8032 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8033 }, 8034 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 8035 }, 8036 }, 8037 { 8038 name: "CALLinter", 8039 auxType: auxInt64, 8040 argLen: 2, 8041 clobberFlags: true, 8042 call: true, 8043 reg: regInfo{ 8044 inputs: []inputInfo{ 8045 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8046 }, 8047 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 8048 }, 8049 }, 8050 { 8051 name: "DUFFCOPY", 8052 auxType: auxInt64, 8053 argLen: 3, 8054 clobberFlags: true, 8055 faultOnNilArg0: true, 8056 faultOnNilArg1: true, 8057 reg: regInfo{ 8058 inputs: []inputInfo{ 8059 {0, 128}, // DI 8060 {1, 64}, // SI 8061 }, 8062 clobbers: 65728, // SI DI X0 8063 }, 8064 }, 8065 { 8066 name: "REPMOVSQ", 8067 argLen: 4, 8068 faultOnNilArg0: true, 8069 faultOnNilArg1: true, 8070 reg: regInfo{ 8071 inputs: []inputInfo{ 8072 {0, 128}, // DI 8073 {1, 64}, // SI 8074 {2, 2}, // CX 8075 }, 8076 clobbers: 194, // CX SI DI 8077 }, 8078 }, 8079 { 8080 name: "InvertFlags", 8081 argLen: 1, 8082 reg: regInfo{}, 8083 }, 8084 { 8085 name: "LoweredGetG", 8086 argLen: 1, 8087 reg: regInfo{ 8088 outputs: []outputInfo{ 8089 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8090 }, 8091 }, 8092 }, 8093 { 8094 name: "LoweredGetClosurePtr", 8095 argLen: 0, 8096 reg: regInfo{ 8097 outputs: []outputInfo{ 8098 {0, 4}, // DX 8099 }, 8100 }, 8101 }, 8102 { 8103 name: "LoweredGetCallerPC", 8104 argLen: 0, 8105 reg: regInfo{ 8106 outputs: []outputInfo{ 8107 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8108 }, 8109 }, 8110 }, 8111 { 8112 name: "LoweredGetCallerSP", 8113 argLen: 0, 8114 rematerializeable: true, 8115 reg: regInfo{ 8116 outputs: []outputInfo{ 8117 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8118 }, 8119 }, 8120 }, 8121 { 8122 name: "LoweredNilCheck", 8123 argLen: 2, 8124 clobberFlags: true, 8125 nilCheck: true, 8126 faultOnNilArg0: true, 8127 reg: regInfo{ 8128 inputs: []inputInfo{ 8129 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8130 }, 8131 }, 8132 }, 8133 { 8134 name: "MOVQconvert", 8135 argLen: 2, 8136 resultInArg0: true, 8137 asm: x86.AMOVQ, 8138 reg: regInfo{ 8139 inputs: []inputInfo{ 8140 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8141 }, 8142 outputs: []outputInfo{ 8143 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8144 }, 8145 }, 8146 }, 8147 { 8148 name: "MOVLconvert", 8149 argLen: 2, 8150 resultInArg0: true, 8151 asm: x86.AMOVL, 8152 reg: regInfo{ 8153 inputs: []inputInfo{ 8154 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8155 }, 8156 outputs: []outputInfo{ 8157 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8158 }, 8159 }, 8160 }, 8161 { 8162 name: "FlagEQ", 8163 argLen: 0, 8164 reg: regInfo{}, 8165 }, 8166 { 8167 name: "FlagLT_ULT", 8168 argLen: 0, 8169 reg: regInfo{}, 8170 }, 8171 { 8172 name: "FlagLT_UGT", 8173 argLen: 0, 8174 reg: regInfo{}, 8175 }, 8176 { 8177 name: "FlagGT_UGT", 8178 argLen: 0, 8179 reg: regInfo{}, 8180 }, 8181 { 8182 name: "FlagGT_ULT", 8183 argLen: 0, 8184 reg: regInfo{}, 8185 }, 8186 { 8187 name: "MOVLatomicload", 8188 auxType: auxSymOff, 8189 argLen: 2, 8190 faultOnNilArg0: true, 8191 symEffect: SymRead, 8192 asm: x86.AMOVL, 8193 reg: regInfo{ 8194 inputs: []inputInfo{ 8195 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8196 }, 8197 outputs: []outputInfo{ 8198 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8199 }, 8200 }, 8201 }, 8202 { 8203 name: "MOVQatomicload", 8204 auxType: auxSymOff, 8205 argLen: 2, 8206 faultOnNilArg0: true, 8207 symEffect: SymRead, 8208 asm: x86.AMOVQ, 8209 reg: regInfo{ 8210 inputs: []inputInfo{ 8211 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8212 }, 8213 outputs: []outputInfo{ 8214 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8215 }, 8216 }, 8217 }, 8218 { 8219 name: "XCHGL", 8220 auxType: auxSymOff, 8221 argLen: 3, 8222 resultInArg0: true, 8223 faultOnNilArg1: true, 8224 hasSideEffects: true, 8225 symEffect: SymRdWr, 8226 asm: x86.AXCHGL, 8227 reg: regInfo{ 8228 inputs: []inputInfo{ 8229 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8230 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8231 }, 8232 outputs: []outputInfo{ 8233 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8234 }, 8235 }, 8236 }, 8237 { 8238 name: "XCHGQ", 8239 auxType: auxSymOff, 8240 argLen: 3, 8241 resultInArg0: true, 8242 faultOnNilArg1: true, 8243 hasSideEffects: true, 8244 symEffect: SymRdWr, 8245 asm: x86.AXCHGQ, 8246 reg: regInfo{ 8247 inputs: []inputInfo{ 8248 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8249 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8250 }, 8251 outputs: []outputInfo{ 8252 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8253 }, 8254 }, 8255 }, 8256 { 8257 name: "XADDLlock", 8258 auxType: auxSymOff, 8259 argLen: 3, 8260 resultInArg0: true, 8261 clobberFlags: true, 8262 faultOnNilArg1: true, 8263 hasSideEffects: true, 8264 symEffect: SymRdWr, 8265 asm: x86.AXADDL, 8266 reg: regInfo{ 8267 inputs: []inputInfo{ 8268 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8269 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8270 }, 8271 outputs: []outputInfo{ 8272 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8273 }, 8274 }, 8275 }, 8276 { 8277 name: "XADDQlock", 8278 auxType: auxSymOff, 8279 argLen: 3, 8280 resultInArg0: true, 8281 clobberFlags: true, 8282 faultOnNilArg1: true, 8283 hasSideEffects: true, 8284 symEffect: SymRdWr, 8285 asm: x86.AXADDQ, 8286 reg: regInfo{ 8287 inputs: []inputInfo{ 8288 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8289 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8290 }, 8291 outputs: []outputInfo{ 8292 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8293 }, 8294 }, 8295 }, 8296 { 8297 name: "AddTupleFirst32", 8298 argLen: 2, 8299 reg: regInfo{}, 8300 }, 8301 { 8302 name: "AddTupleFirst64", 8303 argLen: 2, 8304 reg: regInfo{}, 8305 }, 8306 { 8307 name: "CMPXCHGLlock", 8308 auxType: auxSymOff, 8309 argLen: 4, 8310 clobberFlags: true, 8311 faultOnNilArg0: true, 8312 hasSideEffects: true, 8313 symEffect: SymRdWr, 8314 asm: x86.ACMPXCHGL, 8315 reg: regInfo{ 8316 inputs: []inputInfo{ 8317 {1, 1}, // AX 8318 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8319 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8320 }, 8321 clobbers: 1, // AX 8322 outputs: []outputInfo{ 8323 {1, 0}, 8324 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8325 }, 8326 }, 8327 }, 8328 { 8329 name: "CMPXCHGQlock", 8330 auxType: auxSymOff, 8331 argLen: 4, 8332 clobberFlags: true, 8333 faultOnNilArg0: true, 8334 hasSideEffects: true, 8335 symEffect: SymRdWr, 8336 asm: x86.ACMPXCHGQ, 8337 reg: regInfo{ 8338 inputs: []inputInfo{ 8339 {1, 1}, // AX 8340 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8341 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8342 }, 8343 clobbers: 1, // AX 8344 outputs: []outputInfo{ 8345 {1, 0}, 8346 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8347 }, 8348 }, 8349 }, 8350 { 8351 name: "ANDBlock", 8352 auxType: auxSymOff, 8353 argLen: 3, 8354 clobberFlags: true, 8355 faultOnNilArg0: true, 8356 hasSideEffects: true, 8357 symEffect: SymRdWr, 8358 asm: x86.AANDB, 8359 reg: regInfo{ 8360 inputs: []inputInfo{ 8361 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8362 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8363 }, 8364 }, 8365 }, 8366 { 8367 name: "ORBlock", 8368 auxType: auxSymOff, 8369 argLen: 3, 8370 clobberFlags: true, 8371 faultOnNilArg0: true, 8372 hasSideEffects: true, 8373 symEffect: SymRdWr, 8374 asm: x86.AORB, 8375 reg: regInfo{ 8376 inputs: []inputInfo{ 8377 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8378 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8379 }, 8380 }, 8381 }, 8382 8383 { 8384 name: "ADD", 8385 argLen: 2, 8386 commutative: true, 8387 asm: arm.AADD, 8388 reg: regInfo{ 8389 inputs: []inputInfo{ 8390 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8391 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8392 }, 8393 outputs: []outputInfo{ 8394 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8395 }, 8396 }, 8397 }, 8398 { 8399 name: "ADDconst", 8400 auxType: auxInt32, 8401 argLen: 1, 8402 asm: arm.AADD, 8403 reg: regInfo{ 8404 inputs: []inputInfo{ 8405 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 8406 }, 8407 outputs: []outputInfo{ 8408 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8409 }, 8410 }, 8411 }, 8412 { 8413 name: "SUB", 8414 argLen: 2, 8415 asm: arm.ASUB, 8416 reg: regInfo{ 8417 inputs: []inputInfo{ 8418 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8419 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8420 }, 8421 outputs: []outputInfo{ 8422 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8423 }, 8424 }, 8425 }, 8426 { 8427 name: "SUBconst", 8428 auxType: auxInt32, 8429 argLen: 1, 8430 asm: arm.ASUB, 8431 reg: regInfo{ 8432 inputs: []inputInfo{ 8433 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8434 }, 8435 outputs: []outputInfo{ 8436 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8437 }, 8438 }, 8439 }, 8440 { 8441 name: "RSB", 8442 argLen: 2, 8443 asm: arm.ARSB, 8444 reg: regInfo{ 8445 inputs: []inputInfo{ 8446 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8447 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8448 }, 8449 outputs: []outputInfo{ 8450 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8451 }, 8452 }, 8453 }, 8454 { 8455 name: "RSBconst", 8456 auxType: auxInt32, 8457 argLen: 1, 8458 asm: arm.ARSB, 8459 reg: regInfo{ 8460 inputs: []inputInfo{ 8461 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8462 }, 8463 outputs: []outputInfo{ 8464 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8465 }, 8466 }, 8467 }, 8468 { 8469 name: "MUL", 8470 argLen: 2, 8471 commutative: true, 8472 asm: arm.AMUL, 8473 reg: regInfo{ 8474 inputs: []inputInfo{ 8475 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8476 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8477 }, 8478 outputs: []outputInfo{ 8479 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8480 }, 8481 }, 8482 }, 8483 { 8484 name: "HMUL", 8485 argLen: 2, 8486 commutative: true, 8487 asm: arm.AMULL, 8488 reg: regInfo{ 8489 inputs: []inputInfo{ 8490 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8491 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8492 }, 8493 outputs: []outputInfo{ 8494 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8495 }, 8496 }, 8497 }, 8498 { 8499 name: "HMULU", 8500 argLen: 2, 8501 commutative: true, 8502 asm: arm.AMULLU, 8503 reg: regInfo{ 8504 inputs: []inputInfo{ 8505 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8506 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8507 }, 8508 outputs: []outputInfo{ 8509 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8510 }, 8511 }, 8512 }, 8513 { 8514 name: "CALLudiv", 8515 argLen: 2, 8516 clobberFlags: true, 8517 reg: regInfo{ 8518 inputs: []inputInfo{ 8519 {0, 2}, // R1 8520 {1, 1}, // R0 8521 }, 8522 clobbers: 16396, // R2 R3 R14 8523 outputs: []outputInfo{ 8524 {0, 1}, // R0 8525 {1, 2}, // R1 8526 }, 8527 }, 8528 }, 8529 { 8530 name: "ADDS", 8531 argLen: 2, 8532 commutative: true, 8533 asm: arm.AADD, 8534 reg: regInfo{ 8535 inputs: []inputInfo{ 8536 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8537 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8538 }, 8539 outputs: []outputInfo{ 8540 {1, 0}, 8541 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8542 }, 8543 }, 8544 }, 8545 { 8546 name: "ADDSconst", 8547 auxType: auxInt32, 8548 argLen: 1, 8549 asm: arm.AADD, 8550 reg: regInfo{ 8551 inputs: []inputInfo{ 8552 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8553 }, 8554 outputs: []outputInfo{ 8555 {1, 0}, 8556 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8557 }, 8558 }, 8559 }, 8560 { 8561 name: "ADC", 8562 argLen: 3, 8563 commutative: true, 8564 asm: arm.AADC, 8565 reg: regInfo{ 8566 inputs: []inputInfo{ 8567 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8568 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8569 }, 8570 outputs: []outputInfo{ 8571 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8572 }, 8573 }, 8574 }, 8575 { 8576 name: "ADCconst", 8577 auxType: auxInt32, 8578 argLen: 2, 8579 asm: arm.AADC, 8580 reg: regInfo{ 8581 inputs: []inputInfo{ 8582 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8583 }, 8584 outputs: []outputInfo{ 8585 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8586 }, 8587 }, 8588 }, 8589 { 8590 name: "SUBS", 8591 argLen: 2, 8592 asm: arm.ASUB, 8593 reg: regInfo{ 8594 inputs: []inputInfo{ 8595 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8596 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8597 }, 8598 outputs: []outputInfo{ 8599 {1, 0}, 8600 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8601 }, 8602 }, 8603 }, 8604 { 8605 name: "SUBSconst", 8606 auxType: auxInt32, 8607 argLen: 1, 8608 asm: arm.ASUB, 8609 reg: regInfo{ 8610 inputs: []inputInfo{ 8611 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8612 }, 8613 outputs: []outputInfo{ 8614 {1, 0}, 8615 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8616 }, 8617 }, 8618 }, 8619 { 8620 name: "RSBSconst", 8621 auxType: auxInt32, 8622 argLen: 1, 8623 asm: arm.ARSB, 8624 reg: regInfo{ 8625 inputs: []inputInfo{ 8626 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8627 }, 8628 outputs: []outputInfo{ 8629 {1, 0}, 8630 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8631 }, 8632 }, 8633 }, 8634 { 8635 name: "SBC", 8636 argLen: 3, 8637 asm: arm.ASBC, 8638 reg: regInfo{ 8639 inputs: []inputInfo{ 8640 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8641 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8642 }, 8643 outputs: []outputInfo{ 8644 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8645 }, 8646 }, 8647 }, 8648 { 8649 name: "SBCconst", 8650 auxType: auxInt32, 8651 argLen: 2, 8652 asm: arm.ASBC, 8653 reg: regInfo{ 8654 inputs: []inputInfo{ 8655 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8656 }, 8657 outputs: []outputInfo{ 8658 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8659 }, 8660 }, 8661 }, 8662 { 8663 name: "RSCconst", 8664 auxType: auxInt32, 8665 argLen: 2, 8666 asm: arm.ARSC, 8667 reg: regInfo{ 8668 inputs: []inputInfo{ 8669 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8670 }, 8671 outputs: []outputInfo{ 8672 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8673 }, 8674 }, 8675 }, 8676 { 8677 name: "MULLU", 8678 argLen: 2, 8679 commutative: true, 8680 asm: arm.AMULLU, 8681 reg: regInfo{ 8682 inputs: []inputInfo{ 8683 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8684 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8685 }, 8686 outputs: []outputInfo{ 8687 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8688 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8689 }, 8690 }, 8691 }, 8692 { 8693 name: "MULA", 8694 argLen: 3, 8695 asm: arm.AMULA, 8696 reg: regInfo{ 8697 inputs: []inputInfo{ 8698 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8699 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8700 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8701 }, 8702 outputs: []outputInfo{ 8703 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8704 }, 8705 }, 8706 }, 8707 { 8708 name: "MULS", 8709 argLen: 3, 8710 asm: arm.AMULS, 8711 reg: regInfo{ 8712 inputs: []inputInfo{ 8713 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8714 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8715 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8716 }, 8717 outputs: []outputInfo{ 8718 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8719 }, 8720 }, 8721 }, 8722 { 8723 name: "ADDF", 8724 argLen: 2, 8725 commutative: true, 8726 asm: arm.AADDF, 8727 reg: regInfo{ 8728 inputs: []inputInfo{ 8729 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8730 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8731 }, 8732 outputs: []outputInfo{ 8733 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8734 }, 8735 }, 8736 }, 8737 { 8738 name: "ADDD", 8739 argLen: 2, 8740 commutative: true, 8741 asm: arm.AADDD, 8742 reg: regInfo{ 8743 inputs: []inputInfo{ 8744 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8745 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8746 }, 8747 outputs: []outputInfo{ 8748 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8749 }, 8750 }, 8751 }, 8752 { 8753 name: "SUBF", 8754 argLen: 2, 8755 asm: arm.ASUBF, 8756 reg: regInfo{ 8757 inputs: []inputInfo{ 8758 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8759 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8760 }, 8761 outputs: []outputInfo{ 8762 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8763 }, 8764 }, 8765 }, 8766 { 8767 name: "SUBD", 8768 argLen: 2, 8769 asm: arm.ASUBD, 8770 reg: regInfo{ 8771 inputs: []inputInfo{ 8772 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8773 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8774 }, 8775 outputs: []outputInfo{ 8776 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8777 }, 8778 }, 8779 }, 8780 { 8781 name: "MULF", 8782 argLen: 2, 8783 commutative: true, 8784 asm: arm.AMULF, 8785 reg: regInfo{ 8786 inputs: []inputInfo{ 8787 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8788 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8789 }, 8790 outputs: []outputInfo{ 8791 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8792 }, 8793 }, 8794 }, 8795 { 8796 name: "MULD", 8797 argLen: 2, 8798 commutative: true, 8799 asm: arm.AMULD, 8800 reg: regInfo{ 8801 inputs: []inputInfo{ 8802 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8803 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8804 }, 8805 outputs: []outputInfo{ 8806 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8807 }, 8808 }, 8809 }, 8810 { 8811 name: "NMULF", 8812 argLen: 2, 8813 commutative: true, 8814 asm: arm.ANMULF, 8815 reg: regInfo{ 8816 inputs: []inputInfo{ 8817 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8818 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8819 }, 8820 outputs: []outputInfo{ 8821 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8822 }, 8823 }, 8824 }, 8825 { 8826 name: "NMULD", 8827 argLen: 2, 8828 commutative: true, 8829 asm: arm.ANMULD, 8830 reg: regInfo{ 8831 inputs: []inputInfo{ 8832 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8833 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8834 }, 8835 outputs: []outputInfo{ 8836 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8837 }, 8838 }, 8839 }, 8840 { 8841 name: "DIVF", 8842 argLen: 2, 8843 asm: arm.ADIVF, 8844 reg: regInfo{ 8845 inputs: []inputInfo{ 8846 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8847 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8848 }, 8849 outputs: []outputInfo{ 8850 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8851 }, 8852 }, 8853 }, 8854 { 8855 name: "DIVD", 8856 argLen: 2, 8857 asm: arm.ADIVD, 8858 reg: regInfo{ 8859 inputs: []inputInfo{ 8860 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8861 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8862 }, 8863 outputs: []outputInfo{ 8864 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8865 }, 8866 }, 8867 }, 8868 { 8869 name: "MULAF", 8870 argLen: 3, 8871 resultInArg0: true, 8872 asm: arm.AMULAF, 8873 reg: regInfo{ 8874 inputs: []inputInfo{ 8875 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8876 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8877 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8878 }, 8879 outputs: []outputInfo{ 8880 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8881 }, 8882 }, 8883 }, 8884 { 8885 name: "MULAD", 8886 argLen: 3, 8887 resultInArg0: true, 8888 asm: arm.AMULAD, 8889 reg: regInfo{ 8890 inputs: []inputInfo{ 8891 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8892 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8893 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8894 }, 8895 outputs: []outputInfo{ 8896 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8897 }, 8898 }, 8899 }, 8900 { 8901 name: "MULSF", 8902 argLen: 3, 8903 resultInArg0: true, 8904 asm: arm.AMULSF, 8905 reg: regInfo{ 8906 inputs: []inputInfo{ 8907 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8908 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8909 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8910 }, 8911 outputs: []outputInfo{ 8912 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8913 }, 8914 }, 8915 }, 8916 { 8917 name: "MULSD", 8918 argLen: 3, 8919 resultInArg0: true, 8920 asm: arm.AMULSD, 8921 reg: regInfo{ 8922 inputs: []inputInfo{ 8923 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8924 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8925 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8926 }, 8927 outputs: []outputInfo{ 8928 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8929 }, 8930 }, 8931 }, 8932 { 8933 name: "AND", 8934 argLen: 2, 8935 commutative: true, 8936 asm: arm.AAND, 8937 reg: regInfo{ 8938 inputs: []inputInfo{ 8939 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8940 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8941 }, 8942 outputs: []outputInfo{ 8943 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8944 }, 8945 }, 8946 }, 8947 { 8948 name: "ANDconst", 8949 auxType: auxInt32, 8950 argLen: 1, 8951 asm: arm.AAND, 8952 reg: regInfo{ 8953 inputs: []inputInfo{ 8954 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8955 }, 8956 outputs: []outputInfo{ 8957 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8958 }, 8959 }, 8960 }, 8961 { 8962 name: "OR", 8963 argLen: 2, 8964 commutative: true, 8965 asm: arm.AORR, 8966 reg: regInfo{ 8967 inputs: []inputInfo{ 8968 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8969 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8970 }, 8971 outputs: []outputInfo{ 8972 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8973 }, 8974 }, 8975 }, 8976 { 8977 name: "ORconst", 8978 auxType: auxInt32, 8979 argLen: 1, 8980 asm: arm.AORR, 8981 reg: regInfo{ 8982 inputs: []inputInfo{ 8983 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8984 }, 8985 outputs: []outputInfo{ 8986 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8987 }, 8988 }, 8989 }, 8990 { 8991 name: "XOR", 8992 argLen: 2, 8993 commutative: true, 8994 asm: arm.AEOR, 8995 reg: regInfo{ 8996 inputs: []inputInfo{ 8997 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8998 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8999 }, 9000 outputs: []outputInfo{ 9001 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9002 }, 9003 }, 9004 }, 9005 { 9006 name: "XORconst", 9007 auxType: auxInt32, 9008 argLen: 1, 9009 asm: arm.AEOR, 9010 reg: regInfo{ 9011 inputs: []inputInfo{ 9012 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9013 }, 9014 outputs: []outputInfo{ 9015 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9016 }, 9017 }, 9018 }, 9019 { 9020 name: "BIC", 9021 argLen: 2, 9022 asm: arm.ABIC, 9023 reg: regInfo{ 9024 inputs: []inputInfo{ 9025 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9026 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9027 }, 9028 outputs: []outputInfo{ 9029 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9030 }, 9031 }, 9032 }, 9033 { 9034 name: "BICconst", 9035 auxType: auxInt32, 9036 argLen: 1, 9037 asm: arm.ABIC, 9038 reg: regInfo{ 9039 inputs: []inputInfo{ 9040 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9041 }, 9042 outputs: []outputInfo{ 9043 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9044 }, 9045 }, 9046 }, 9047 { 9048 name: "BFX", 9049 auxType: auxInt32, 9050 argLen: 1, 9051 asm: arm.ABFX, 9052 reg: regInfo{ 9053 inputs: []inputInfo{ 9054 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9055 }, 9056 outputs: []outputInfo{ 9057 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9058 }, 9059 }, 9060 }, 9061 { 9062 name: "BFXU", 9063 auxType: auxInt32, 9064 argLen: 1, 9065 asm: arm.ABFXU, 9066 reg: regInfo{ 9067 inputs: []inputInfo{ 9068 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9069 }, 9070 outputs: []outputInfo{ 9071 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9072 }, 9073 }, 9074 }, 9075 { 9076 name: "MVN", 9077 argLen: 1, 9078 asm: arm.AMVN, 9079 reg: regInfo{ 9080 inputs: []inputInfo{ 9081 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9082 }, 9083 outputs: []outputInfo{ 9084 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9085 }, 9086 }, 9087 }, 9088 { 9089 name: "NEGF", 9090 argLen: 1, 9091 asm: arm.ANEGF, 9092 reg: regInfo{ 9093 inputs: []inputInfo{ 9094 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9095 }, 9096 outputs: []outputInfo{ 9097 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9098 }, 9099 }, 9100 }, 9101 { 9102 name: "NEGD", 9103 argLen: 1, 9104 asm: arm.ANEGD, 9105 reg: regInfo{ 9106 inputs: []inputInfo{ 9107 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9108 }, 9109 outputs: []outputInfo{ 9110 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9111 }, 9112 }, 9113 }, 9114 { 9115 name: "SQRTD", 9116 argLen: 1, 9117 asm: arm.ASQRTD, 9118 reg: regInfo{ 9119 inputs: []inputInfo{ 9120 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9121 }, 9122 outputs: []outputInfo{ 9123 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9124 }, 9125 }, 9126 }, 9127 { 9128 name: "CLZ", 9129 argLen: 1, 9130 asm: arm.ACLZ, 9131 reg: regInfo{ 9132 inputs: []inputInfo{ 9133 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9134 }, 9135 outputs: []outputInfo{ 9136 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9137 }, 9138 }, 9139 }, 9140 { 9141 name: "REV", 9142 argLen: 1, 9143 asm: arm.AREV, 9144 reg: regInfo{ 9145 inputs: []inputInfo{ 9146 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9147 }, 9148 outputs: []outputInfo{ 9149 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9150 }, 9151 }, 9152 }, 9153 { 9154 name: "RBIT", 9155 argLen: 1, 9156 asm: arm.ARBIT, 9157 reg: regInfo{ 9158 inputs: []inputInfo{ 9159 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9160 }, 9161 outputs: []outputInfo{ 9162 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9163 }, 9164 }, 9165 }, 9166 { 9167 name: "SLL", 9168 argLen: 2, 9169 asm: arm.ASLL, 9170 reg: regInfo{ 9171 inputs: []inputInfo{ 9172 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9173 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9174 }, 9175 outputs: []outputInfo{ 9176 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9177 }, 9178 }, 9179 }, 9180 { 9181 name: "SLLconst", 9182 auxType: auxInt32, 9183 argLen: 1, 9184 asm: arm.ASLL, 9185 reg: regInfo{ 9186 inputs: []inputInfo{ 9187 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9188 }, 9189 outputs: []outputInfo{ 9190 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9191 }, 9192 }, 9193 }, 9194 { 9195 name: "SRL", 9196 argLen: 2, 9197 asm: arm.ASRL, 9198 reg: regInfo{ 9199 inputs: []inputInfo{ 9200 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9201 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9202 }, 9203 outputs: []outputInfo{ 9204 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9205 }, 9206 }, 9207 }, 9208 { 9209 name: "SRLconst", 9210 auxType: auxInt32, 9211 argLen: 1, 9212 asm: arm.ASRL, 9213 reg: regInfo{ 9214 inputs: []inputInfo{ 9215 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9216 }, 9217 outputs: []outputInfo{ 9218 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9219 }, 9220 }, 9221 }, 9222 { 9223 name: "SRA", 9224 argLen: 2, 9225 asm: arm.ASRA, 9226 reg: regInfo{ 9227 inputs: []inputInfo{ 9228 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9229 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9230 }, 9231 outputs: []outputInfo{ 9232 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9233 }, 9234 }, 9235 }, 9236 { 9237 name: "SRAconst", 9238 auxType: auxInt32, 9239 argLen: 1, 9240 asm: arm.ASRA, 9241 reg: regInfo{ 9242 inputs: []inputInfo{ 9243 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9244 }, 9245 outputs: []outputInfo{ 9246 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9247 }, 9248 }, 9249 }, 9250 { 9251 name: "SRRconst", 9252 auxType: auxInt32, 9253 argLen: 1, 9254 reg: regInfo{ 9255 inputs: []inputInfo{ 9256 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9257 }, 9258 outputs: []outputInfo{ 9259 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9260 }, 9261 }, 9262 }, 9263 { 9264 name: "ADDshiftLL", 9265 auxType: auxInt32, 9266 argLen: 2, 9267 asm: arm.AADD, 9268 reg: regInfo{ 9269 inputs: []inputInfo{ 9270 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9271 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9272 }, 9273 outputs: []outputInfo{ 9274 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9275 }, 9276 }, 9277 }, 9278 { 9279 name: "ADDshiftRL", 9280 auxType: auxInt32, 9281 argLen: 2, 9282 asm: arm.AADD, 9283 reg: regInfo{ 9284 inputs: []inputInfo{ 9285 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9286 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9287 }, 9288 outputs: []outputInfo{ 9289 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9290 }, 9291 }, 9292 }, 9293 { 9294 name: "ADDshiftRA", 9295 auxType: auxInt32, 9296 argLen: 2, 9297 asm: arm.AADD, 9298 reg: regInfo{ 9299 inputs: []inputInfo{ 9300 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9301 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9302 }, 9303 outputs: []outputInfo{ 9304 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9305 }, 9306 }, 9307 }, 9308 { 9309 name: "SUBshiftLL", 9310 auxType: auxInt32, 9311 argLen: 2, 9312 asm: arm.ASUB, 9313 reg: regInfo{ 9314 inputs: []inputInfo{ 9315 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9316 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9317 }, 9318 outputs: []outputInfo{ 9319 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9320 }, 9321 }, 9322 }, 9323 { 9324 name: "SUBshiftRL", 9325 auxType: auxInt32, 9326 argLen: 2, 9327 asm: arm.ASUB, 9328 reg: regInfo{ 9329 inputs: []inputInfo{ 9330 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9331 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9332 }, 9333 outputs: []outputInfo{ 9334 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9335 }, 9336 }, 9337 }, 9338 { 9339 name: "SUBshiftRA", 9340 auxType: auxInt32, 9341 argLen: 2, 9342 asm: arm.ASUB, 9343 reg: regInfo{ 9344 inputs: []inputInfo{ 9345 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9346 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9347 }, 9348 outputs: []outputInfo{ 9349 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9350 }, 9351 }, 9352 }, 9353 { 9354 name: "RSBshiftLL", 9355 auxType: auxInt32, 9356 argLen: 2, 9357 asm: arm.ARSB, 9358 reg: regInfo{ 9359 inputs: []inputInfo{ 9360 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9361 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9362 }, 9363 outputs: []outputInfo{ 9364 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9365 }, 9366 }, 9367 }, 9368 { 9369 name: "RSBshiftRL", 9370 auxType: auxInt32, 9371 argLen: 2, 9372 asm: arm.ARSB, 9373 reg: regInfo{ 9374 inputs: []inputInfo{ 9375 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9376 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9377 }, 9378 outputs: []outputInfo{ 9379 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9380 }, 9381 }, 9382 }, 9383 { 9384 name: "RSBshiftRA", 9385 auxType: auxInt32, 9386 argLen: 2, 9387 asm: arm.ARSB, 9388 reg: regInfo{ 9389 inputs: []inputInfo{ 9390 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9391 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9392 }, 9393 outputs: []outputInfo{ 9394 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9395 }, 9396 }, 9397 }, 9398 { 9399 name: "ANDshiftLL", 9400 auxType: auxInt32, 9401 argLen: 2, 9402 asm: arm.AAND, 9403 reg: regInfo{ 9404 inputs: []inputInfo{ 9405 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9406 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9407 }, 9408 outputs: []outputInfo{ 9409 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9410 }, 9411 }, 9412 }, 9413 { 9414 name: "ANDshiftRL", 9415 auxType: auxInt32, 9416 argLen: 2, 9417 asm: arm.AAND, 9418 reg: regInfo{ 9419 inputs: []inputInfo{ 9420 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9421 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9422 }, 9423 outputs: []outputInfo{ 9424 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9425 }, 9426 }, 9427 }, 9428 { 9429 name: "ANDshiftRA", 9430 auxType: auxInt32, 9431 argLen: 2, 9432 asm: arm.AAND, 9433 reg: regInfo{ 9434 inputs: []inputInfo{ 9435 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9436 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9437 }, 9438 outputs: []outputInfo{ 9439 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9440 }, 9441 }, 9442 }, 9443 { 9444 name: "ORshiftLL", 9445 auxType: auxInt32, 9446 argLen: 2, 9447 asm: arm.AORR, 9448 reg: regInfo{ 9449 inputs: []inputInfo{ 9450 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9451 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9452 }, 9453 outputs: []outputInfo{ 9454 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9455 }, 9456 }, 9457 }, 9458 { 9459 name: "ORshiftRL", 9460 auxType: auxInt32, 9461 argLen: 2, 9462 asm: arm.AORR, 9463 reg: regInfo{ 9464 inputs: []inputInfo{ 9465 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9466 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9467 }, 9468 outputs: []outputInfo{ 9469 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9470 }, 9471 }, 9472 }, 9473 { 9474 name: "ORshiftRA", 9475 auxType: auxInt32, 9476 argLen: 2, 9477 asm: arm.AORR, 9478 reg: regInfo{ 9479 inputs: []inputInfo{ 9480 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9481 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9482 }, 9483 outputs: []outputInfo{ 9484 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9485 }, 9486 }, 9487 }, 9488 { 9489 name: "XORshiftLL", 9490 auxType: auxInt32, 9491 argLen: 2, 9492 asm: arm.AEOR, 9493 reg: regInfo{ 9494 inputs: []inputInfo{ 9495 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9496 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9497 }, 9498 outputs: []outputInfo{ 9499 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9500 }, 9501 }, 9502 }, 9503 { 9504 name: "XORshiftRL", 9505 auxType: auxInt32, 9506 argLen: 2, 9507 asm: arm.AEOR, 9508 reg: regInfo{ 9509 inputs: []inputInfo{ 9510 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9511 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9512 }, 9513 outputs: []outputInfo{ 9514 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9515 }, 9516 }, 9517 }, 9518 { 9519 name: "XORshiftRA", 9520 auxType: auxInt32, 9521 argLen: 2, 9522 asm: arm.AEOR, 9523 reg: regInfo{ 9524 inputs: []inputInfo{ 9525 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9526 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9527 }, 9528 outputs: []outputInfo{ 9529 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9530 }, 9531 }, 9532 }, 9533 { 9534 name: "XORshiftRR", 9535 auxType: auxInt32, 9536 argLen: 2, 9537 asm: arm.AEOR, 9538 reg: regInfo{ 9539 inputs: []inputInfo{ 9540 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9541 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9542 }, 9543 outputs: []outputInfo{ 9544 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9545 }, 9546 }, 9547 }, 9548 { 9549 name: "BICshiftLL", 9550 auxType: auxInt32, 9551 argLen: 2, 9552 asm: arm.ABIC, 9553 reg: regInfo{ 9554 inputs: []inputInfo{ 9555 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9556 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9557 }, 9558 outputs: []outputInfo{ 9559 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9560 }, 9561 }, 9562 }, 9563 { 9564 name: "BICshiftRL", 9565 auxType: auxInt32, 9566 argLen: 2, 9567 asm: arm.ABIC, 9568 reg: regInfo{ 9569 inputs: []inputInfo{ 9570 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9571 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9572 }, 9573 outputs: []outputInfo{ 9574 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9575 }, 9576 }, 9577 }, 9578 { 9579 name: "BICshiftRA", 9580 auxType: auxInt32, 9581 argLen: 2, 9582 asm: arm.ABIC, 9583 reg: regInfo{ 9584 inputs: []inputInfo{ 9585 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9586 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9587 }, 9588 outputs: []outputInfo{ 9589 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9590 }, 9591 }, 9592 }, 9593 { 9594 name: "MVNshiftLL", 9595 auxType: auxInt32, 9596 argLen: 1, 9597 asm: arm.AMVN, 9598 reg: regInfo{ 9599 inputs: []inputInfo{ 9600 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9601 }, 9602 outputs: []outputInfo{ 9603 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9604 }, 9605 }, 9606 }, 9607 { 9608 name: "MVNshiftRL", 9609 auxType: auxInt32, 9610 argLen: 1, 9611 asm: arm.AMVN, 9612 reg: regInfo{ 9613 inputs: []inputInfo{ 9614 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9615 }, 9616 outputs: []outputInfo{ 9617 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9618 }, 9619 }, 9620 }, 9621 { 9622 name: "MVNshiftRA", 9623 auxType: auxInt32, 9624 argLen: 1, 9625 asm: arm.AMVN, 9626 reg: regInfo{ 9627 inputs: []inputInfo{ 9628 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9629 }, 9630 outputs: []outputInfo{ 9631 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9632 }, 9633 }, 9634 }, 9635 { 9636 name: "ADCshiftLL", 9637 auxType: auxInt32, 9638 argLen: 3, 9639 asm: arm.AADC, 9640 reg: regInfo{ 9641 inputs: []inputInfo{ 9642 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9643 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9644 }, 9645 outputs: []outputInfo{ 9646 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9647 }, 9648 }, 9649 }, 9650 { 9651 name: "ADCshiftRL", 9652 auxType: auxInt32, 9653 argLen: 3, 9654 asm: arm.AADC, 9655 reg: regInfo{ 9656 inputs: []inputInfo{ 9657 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9658 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9659 }, 9660 outputs: []outputInfo{ 9661 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9662 }, 9663 }, 9664 }, 9665 { 9666 name: "ADCshiftRA", 9667 auxType: auxInt32, 9668 argLen: 3, 9669 asm: arm.AADC, 9670 reg: regInfo{ 9671 inputs: []inputInfo{ 9672 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9673 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9674 }, 9675 outputs: []outputInfo{ 9676 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9677 }, 9678 }, 9679 }, 9680 { 9681 name: "SBCshiftLL", 9682 auxType: auxInt32, 9683 argLen: 3, 9684 asm: arm.ASBC, 9685 reg: regInfo{ 9686 inputs: []inputInfo{ 9687 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9688 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9689 }, 9690 outputs: []outputInfo{ 9691 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9692 }, 9693 }, 9694 }, 9695 { 9696 name: "SBCshiftRL", 9697 auxType: auxInt32, 9698 argLen: 3, 9699 asm: arm.ASBC, 9700 reg: regInfo{ 9701 inputs: []inputInfo{ 9702 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9703 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9704 }, 9705 outputs: []outputInfo{ 9706 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9707 }, 9708 }, 9709 }, 9710 { 9711 name: "SBCshiftRA", 9712 auxType: auxInt32, 9713 argLen: 3, 9714 asm: arm.ASBC, 9715 reg: regInfo{ 9716 inputs: []inputInfo{ 9717 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9718 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9719 }, 9720 outputs: []outputInfo{ 9721 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9722 }, 9723 }, 9724 }, 9725 { 9726 name: "RSCshiftLL", 9727 auxType: auxInt32, 9728 argLen: 3, 9729 asm: arm.ARSC, 9730 reg: regInfo{ 9731 inputs: []inputInfo{ 9732 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9733 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9734 }, 9735 outputs: []outputInfo{ 9736 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9737 }, 9738 }, 9739 }, 9740 { 9741 name: "RSCshiftRL", 9742 auxType: auxInt32, 9743 argLen: 3, 9744 asm: arm.ARSC, 9745 reg: regInfo{ 9746 inputs: []inputInfo{ 9747 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9748 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9749 }, 9750 outputs: []outputInfo{ 9751 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9752 }, 9753 }, 9754 }, 9755 { 9756 name: "RSCshiftRA", 9757 auxType: auxInt32, 9758 argLen: 3, 9759 asm: arm.ARSC, 9760 reg: regInfo{ 9761 inputs: []inputInfo{ 9762 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9763 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9764 }, 9765 outputs: []outputInfo{ 9766 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9767 }, 9768 }, 9769 }, 9770 { 9771 name: "ADDSshiftLL", 9772 auxType: auxInt32, 9773 argLen: 2, 9774 asm: arm.AADD, 9775 reg: regInfo{ 9776 inputs: []inputInfo{ 9777 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9778 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9779 }, 9780 outputs: []outputInfo{ 9781 {1, 0}, 9782 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9783 }, 9784 }, 9785 }, 9786 { 9787 name: "ADDSshiftRL", 9788 auxType: auxInt32, 9789 argLen: 2, 9790 asm: arm.AADD, 9791 reg: regInfo{ 9792 inputs: []inputInfo{ 9793 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9794 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9795 }, 9796 outputs: []outputInfo{ 9797 {1, 0}, 9798 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9799 }, 9800 }, 9801 }, 9802 { 9803 name: "ADDSshiftRA", 9804 auxType: auxInt32, 9805 argLen: 2, 9806 asm: arm.AADD, 9807 reg: regInfo{ 9808 inputs: []inputInfo{ 9809 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9810 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9811 }, 9812 outputs: []outputInfo{ 9813 {1, 0}, 9814 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9815 }, 9816 }, 9817 }, 9818 { 9819 name: "SUBSshiftLL", 9820 auxType: auxInt32, 9821 argLen: 2, 9822 asm: arm.ASUB, 9823 reg: regInfo{ 9824 inputs: []inputInfo{ 9825 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9826 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9827 }, 9828 outputs: []outputInfo{ 9829 {1, 0}, 9830 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9831 }, 9832 }, 9833 }, 9834 { 9835 name: "SUBSshiftRL", 9836 auxType: auxInt32, 9837 argLen: 2, 9838 asm: arm.ASUB, 9839 reg: regInfo{ 9840 inputs: []inputInfo{ 9841 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9842 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9843 }, 9844 outputs: []outputInfo{ 9845 {1, 0}, 9846 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9847 }, 9848 }, 9849 }, 9850 { 9851 name: "SUBSshiftRA", 9852 auxType: auxInt32, 9853 argLen: 2, 9854 asm: arm.ASUB, 9855 reg: regInfo{ 9856 inputs: []inputInfo{ 9857 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9858 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9859 }, 9860 outputs: []outputInfo{ 9861 {1, 0}, 9862 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9863 }, 9864 }, 9865 }, 9866 { 9867 name: "RSBSshiftLL", 9868 auxType: auxInt32, 9869 argLen: 2, 9870 asm: arm.ARSB, 9871 reg: regInfo{ 9872 inputs: []inputInfo{ 9873 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9874 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9875 }, 9876 outputs: []outputInfo{ 9877 {1, 0}, 9878 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9879 }, 9880 }, 9881 }, 9882 { 9883 name: "RSBSshiftRL", 9884 auxType: auxInt32, 9885 argLen: 2, 9886 asm: arm.ARSB, 9887 reg: regInfo{ 9888 inputs: []inputInfo{ 9889 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9890 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9891 }, 9892 outputs: []outputInfo{ 9893 {1, 0}, 9894 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9895 }, 9896 }, 9897 }, 9898 { 9899 name: "RSBSshiftRA", 9900 auxType: auxInt32, 9901 argLen: 2, 9902 asm: arm.ARSB, 9903 reg: regInfo{ 9904 inputs: []inputInfo{ 9905 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9906 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9907 }, 9908 outputs: []outputInfo{ 9909 {1, 0}, 9910 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9911 }, 9912 }, 9913 }, 9914 { 9915 name: "ADDshiftLLreg", 9916 argLen: 3, 9917 asm: arm.AADD, 9918 reg: regInfo{ 9919 inputs: []inputInfo{ 9920 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9921 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9922 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9923 }, 9924 outputs: []outputInfo{ 9925 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9926 }, 9927 }, 9928 }, 9929 { 9930 name: "ADDshiftRLreg", 9931 argLen: 3, 9932 asm: arm.AADD, 9933 reg: regInfo{ 9934 inputs: []inputInfo{ 9935 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9936 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9937 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9938 }, 9939 outputs: []outputInfo{ 9940 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9941 }, 9942 }, 9943 }, 9944 { 9945 name: "ADDshiftRAreg", 9946 argLen: 3, 9947 asm: arm.AADD, 9948 reg: regInfo{ 9949 inputs: []inputInfo{ 9950 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9951 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9952 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9953 }, 9954 outputs: []outputInfo{ 9955 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9956 }, 9957 }, 9958 }, 9959 { 9960 name: "SUBshiftLLreg", 9961 argLen: 3, 9962 asm: arm.ASUB, 9963 reg: regInfo{ 9964 inputs: []inputInfo{ 9965 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9966 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9967 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9968 }, 9969 outputs: []outputInfo{ 9970 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9971 }, 9972 }, 9973 }, 9974 { 9975 name: "SUBshiftRLreg", 9976 argLen: 3, 9977 asm: arm.ASUB, 9978 reg: regInfo{ 9979 inputs: []inputInfo{ 9980 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9981 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9982 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9983 }, 9984 outputs: []outputInfo{ 9985 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9986 }, 9987 }, 9988 }, 9989 { 9990 name: "SUBshiftRAreg", 9991 argLen: 3, 9992 asm: arm.ASUB, 9993 reg: regInfo{ 9994 inputs: []inputInfo{ 9995 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9996 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9997 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9998 }, 9999 outputs: []outputInfo{ 10000 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10001 }, 10002 }, 10003 }, 10004 { 10005 name: "RSBshiftLLreg", 10006 argLen: 3, 10007 asm: arm.ARSB, 10008 reg: regInfo{ 10009 inputs: []inputInfo{ 10010 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10011 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10012 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10013 }, 10014 outputs: []outputInfo{ 10015 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10016 }, 10017 }, 10018 }, 10019 { 10020 name: "RSBshiftRLreg", 10021 argLen: 3, 10022 asm: arm.ARSB, 10023 reg: regInfo{ 10024 inputs: []inputInfo{ 10025 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10026 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10027 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10028 }, 10029 outputs: []outputInfo{ 10030 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10031 }, 10032 }, 10033 }, 10034 { 10035 name: "RSBshiftRAreg", 10036 argLen: 3, 10037 asm: arm.ARSB, 10038 reg: regInfo{ 10039 inputs: []inputInfo{ 10040 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10041 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10042 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10043 }, 10044 outputs: []outputInfo{ 10045 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10046 }, 10047 }, 10048 }, 10049 { 10050 name: "ANDshiftLLreg", 10051 argLen: 3, 10052 asm: arm.AAND, 10053 reg: regInfo{ 10054 inputs: []inputInfo{ 10055 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10056 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10057 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10058 }, 10059 outputs: []outputInfo{ 10060 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10061 }, 10062 }, 10063 }, 10064 { 10065 name: "ANDshiftRLreg", 10066 argLen: 3, 10067 asm: arm.AAND, 10068 reg: regInfo{ 10069 inputs: []inputInfo{ 10070 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10071 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10072 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10073 }, 10074 outputs: []outputInfo{ 10075 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10076 }, 10077 }, 10078 }, 10079 { 10080 name: "ANDshiftRAreg", 10081 argLen: 3, 10082 asm: arm.AAND, 10083 reg: regInfo{ 10084 inputs: []inputInfo{ 10085 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10086 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10087 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10088 }, 10089 outputs: []outputInfo{ 10090 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10091 }, 10092 }, 10093 }, 10094 { 10095 name: "ORshiftLLreg", 10096 argLen: 3, 10097 asm: arm.AORR, 10098 reg: regInfo{ 10099 inputs: []inputInfo{ 10100 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10101 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10102 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10103 }, 10104 outputs: []outputInfo{ 10105 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10106 }, 10107 }, 10108 }, 10109 { 10110 name: "ORshiftRLreg", 10111 argLen: 3, 10112 asm: arm.AORR, 10113 reg: regInfo{ 10114 inputs: []inputInfo{ 10115 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10116 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10117 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10118 }, 10119 outputs: []outputInfo{ 10120 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10121 }, 10122 }, 10123 }, 10124 { 10125 name: "ORshiftRAreg", 10126 argLen: 3, 10127 asm: arm.AORR, 10128 reg: regInfo{ 10129 inputs: []inputInfo{ 10130 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10131 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10132 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10133 }, 10134 outputs: []outputInfo{ 10135 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10136 }, 10137 }, 10138 }, 10139 { 10140 name: "XORshiftLLreg", 10141 argLen: 3, 10142 asm: arm.AEOR, 10143 reg: regInfo{ 10144 inputs: []inputInfo{ 10145 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10146 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10147 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10148 }, 10149 outputs: []outputInfo{ 10150 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10151 }, 10152 }, 10153 }, 10154 { 10155 name: "XORshiftRLreg", 10156 argLen: 3, 10157 asm: arm.AEOR, 10158 reg: regInfo{ 10159 inputs: []inputInfo{ 10160 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10161 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10162 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10163 }, 10164 outputs: []outputInfo{ 10165 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10166 }, 10167 }, 10168 }, 10169 { 10170 name: "XORshiftRAreg", 10171 argLen: 3, 10172 asm: arm.AEOR, 10173 reg: regInfo{ 10174 inputs: []inputInfo{ 10175 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10176 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10177 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10178 }, 10179 outputs: []outputInfo{ 10180 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10181 }, 10182 }, 10183 }, 10184 { 10185 name: "BICshiftLLreg", 10186 argLen: 3, 10187 asm: arm.ABIC, 10188 reg: regInfo{ 10189 inputs: []inputInfo{ 10190 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10191 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10192 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10193 }, 10194 outputs: []outputInfo{ 10195 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10196 }, 10197 }, 10198 }, 10199 { 10200 name: "BICshiftRLreg", 10201 argLen: 3, 10202 asm: arm.ABIC, 10203 reg: regInfo{ 10204 inputs: []inputInfo{ 10205 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10206 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10207 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10208 }, 10209 outputs: []outputInfo{ 10210 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10211 }, 10212 }, 10213 }, 10214 { 10215 name: "BICshiftRAreg", 10216 argLen: 3, 10217 asm: arm.ABIC, 10218 reg: regInfo{ 10219 inputs: []inputInfo{ 10220 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10221 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10222 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10223 }, 10224 outputs: []outputInfo{ 10225 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10226 }, 10227 }, 10228 }, 10229 { 10230 name: "MVNshiftLLreg", 10231 argLen: 2, 10232 asm: arm.AMVN, 10233 reg: regInfo{ 10234 inputs: []inputInfo{ 10235 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10236 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10237 }, 10238 outputs: []outputInfo{ 10239 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10240 }, 10241 }, 10242 }, 10243 { 10244 name: "MVNshiftRLreg", 10245 argLen: 2, 10246 asm: arm.AMVN, 10247 reg: regInfo{ 10248 inputs: []inputInfo{ 10249 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10250 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10251 }, 10252 outputs: []outputInfo{ 10253 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10254 }, 10255 }, 10256 }, 10257 { 10258 name: "MVNshiftRAreg", 10259 argLen: 2, 10260 asm: arm.AMVN, 10261 reg: regInfo{ 10262 inputs: []inputInfo{ 10263 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10264 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10265 }, 10266 outputs: []outputInfo{ 10267 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10268 }, 10269 }, 10270 }, 10271 { 10272 name: "ADCshiftLLreg", 10273 argLen: 4, 10274 asm: arm.AADC, 10275 reg: regInfo{ 10276 inputs: []inputInfo{ 10277 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10278 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10279 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10280 }, 10281 outputs: []outputInfo{ 10282 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10283 }, 10284 }, 10285 }, 10286 { 10287 name: "ADCshiftRLreg", 10288 argLen: 4, 10289 asm: arm.AADC, 10290 reg: regInfo{ 10291 inputs: []inputInfo{ 10292 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10293 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10294 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10295 }, 10296 outputs: []outputInfo{ 10297 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10298 }, 10299 }, 10300 }, 10301 { 10302 name: "ADCshiftRAreg", 10303 argLen: 4, 10304 asm: arm.AADC, 10305 reg: regInfo{ 10306 inputs: []inputInfo{ 10307 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10308 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10309 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10310 }, 10311 outputs: []outputInfo{ 10312 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10313 }, 10314 }, 10315 }, 10316 { 10317 name: "SBCshiftLLreg", 10318 argLen: 4, 10319 asm: arm.ASBC, 10320 reg: regInfo{ 10321 inputs: []inputInfo{ 10322 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10323 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10324 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10325 }, 10326 outputs: []outputInfo{ 10327 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10328 }, 10329 }, 10330 }, 10331 { 10332 name: "SBCshiftRLreg", 10333 argLen: 4, 10334 asm: arm.ASBC, 10335 reg: regInfo{ 10336 inputs: []inputInfo{ 10337 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10338 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10339 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10340 }, 10341 outputs: []outputInfo{ 10342 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10343 }, 10344 }, 10345 }, 10346 { 10347 name: "SBCshiftRAreg", 10348 argLen: 4, 10349 asm: arm.ASBC, 10350 reg: regInfo{ 10351 inputs: []inputInfo{ 10352 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10353 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10354 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10355 }, 10356 outputs: []outputInfo{ 10357 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10358 }, 10359 }, 10360 }, 10361 { 10362 name: "RSCshiftLLreg", 10363 argLen: 4, 10364 asm: arm.ARSC, 10365 reg: regInfo{ 10366 inputs: []inputInfo{ 10367 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10368 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10369 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10370 }, 10371 outputs: []outputInfo{ 10372 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10373 }, 10374 }, 10375 }, 10376 { 10377 name: "RSCshiftRLreg", 10378 argLen: 4, 10379 asm: arm.ARSC, 10380 reg: regInfo{ 10381 inputs: []inputInfo{ 10382 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10383 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10384 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10385 }, 10386 outputs: []outputInfo{ 10387 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10388 }, 10389 }, 10390 }, 10391 { 10392 name: "RSCshiftRAreg", 10393 argLen: 4, 10394 asm: arm.ARSC, 10395 reg: regInfo{ 10396 inputs: []inputInfo{ 10397 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10398 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10399 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10400 }, 10401 outputs: []outputInfo{ 10402 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10403 }, 10404 }, 10405 }, 10406 { 10407 name: "ADDSshiftLLreg", 10408 argLen: 3, 10409 asm: arm.AADD, 10410 reg: regInfo{ 10411 inputs: []inputInfo{ 10412 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10413 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10414 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10415 }, 10416 outputs: []outputInfo{ 10417 {1, 0}, 10418 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10419 }, 10420 }, 10421 }, 10422 { 10423 name: "ADDSshiftRLreg", 10424 argLen: 3, 10425 asm: arm.AADD, 10426 reg: regInfo{ 10427 inputs: []inputInfo{ 10428 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10429 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10430 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10431 }, 10432 outputs: []outputInfo{ 10433 {1, 0}, 10434 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10435 }, 10436 }, 10437 }, 10438 { 10439 name: "ADDSshiftRAreg", 10440 argLen: 3, 10441 asm: arm.AADD, 10442 reg: regInfo{ 10443 inputs: []inputInfo{ 10444 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10445 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10446 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10447 }, 10448 outputs: []outputInfo{ 10449 {1, 0}, 10450 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10451 }, 10452 }, 10453 }, 10454 { 10455 name: "SUBSshiftLLreg", 10456 argLen: 3, 10457 asm: arm.ASUB, 10458 reg: regInfo{ 10459 inputs: []inputInfo{ 10460 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10461 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10462 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10463 }, 10464 outputs: []outputInfo{ 10465 {1, 0}, 10466 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10467 }, 10468 }, 10469 }, 10470 { 10471 name: "SUBSshiftRLreg", 10472 argLen: 3, 10473 asm: arm.ASUB, 10474 reg: regInfo{ 10475 inputs: []inputInfo{ 10476 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10477 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10478 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10479 }, 10480 outputs: []outputInfo{ 10481 {1, 0}, 10482 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10483 }, 10484 }, 10485 }, 10486 { 10487 name: "SUBSshiftRAreg", 10488 argLen: 3, 10489 asm: arm.ASUB, 10490 reg: regInfo{ 10491 inputs: []inputInfo{ 10492 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10493 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10494 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10495 }, 10496 outputs: []outputInfo{ 10497 {1, 0}, 10498 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10499 }, 10500 }, 10501 }, 10502 { 10503 name: "RSBSshiftLLreg", 10504 argLen: 3, 10505 asm: arm.ARSB, 10506 reg: regInfo{ 10507 inputs: []inputInfo{ 10508 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10509 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10510 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10511 }, 10512 outputs: []outputInfo{ 10513 {1, 0}, 10514 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10515 }, 10516 }, 10517 }, 10518 { 10519 name: "RSBSshiftRLreg", 10520 argLen: 3, 10521 asm: arm.ARSB, 10522 reg: regInfo{ 10523 inputs: []inputInfo{ 10524 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10525 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10526 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10527 }, 10528 outputs: []outputInfo{ 10529 {1, 0}, 10530 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10531 }, 10532 }, 10533 }, 10534 { 10535 name: "RSBSshiftRAreg", 10536 argLen: 3, 10537 asm: arm.ARSB, 10538 reg: regInfo{ 10539 inputs: []inputInfo{ 10540 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10541 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10542 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10543 }, 10544 outputs: []outputInfo{ 10545 {1, 0}, 10546 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10547 }, 10548 }, 10549 }, 10550 { 10551 name: "CMP", 10552 argLen: 2, 10553 asm: arm.ACMP, 10554 reg: regInfo{ 10555 inputs: []inputInfo{ 10556 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10557 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10558 }, 10559 }, 10560 }, 10561 { 10562 name: "CMPconst", 10563 auxType: auxInt32, 10564 argLen: 1, 10565 asm: arm.ACMP, 10566 reg: regInfo{ 10567 inputs: []inputInfo{ 10568 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10569 }, 10570 }, 10571 }, 10572 { 10573 name: "CMN", 10574 argLen: 2, 10575 asm: arm.ACMN, 10576 reg: regInfo{ 10577 inputs: []inputInfo{ 10578 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10579 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10580 }, 10581 }, 10582 }, 10583 { 10584 name: "CMNconst", 10585 auxType: auxInt32, 10586 argLen: 1, 10587 asm: arm.ACMN, 10588 reg: regInfo{ 10589 inputs: []inputInfo{ 10590 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10591 }, 10592 }, 10593 }, 10594 { 10595 name: "TST", 10596 argLen: 2, 10597 commutative: true, 10598 asm: arm.ATST, 10599 reg: regInfo{ 10600 inputs: []inputInfo{ 10601 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10602 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10603 }, 10604 }, 10605 }, 10606 { 10607 name: "TSTconst", 10608 auxType: auxInt32, 10609 argLen: 1, 10610 asm: arm.ATST, 10611 reg: regInfo{ 10612 inputs: []inputInfo{ 10613 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10614 }, 10615 }, 10616 }, 10617 { 10618 name: "TEQ", 10619 argLen: 2, 10620 commutative: true, 10621 asm: arm.ATEQ, 10622 reg: regInfo{ 10623 inputs: []inputInfo{ 10624 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10625 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10626 }, 10627 }, 10628 }, 10629 { 10630 name: "TEQconst", 10631 auxType: auxInt32, 10632 argLen: 1, 10633 asm: arm.ATEQ, 10634 reg: regInfo{ 10635 inputs: []inputInfo{ 10636 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10637 }, 10638 }, 10639 }, 10640 { 10641 name: "CMPF", 10642 argLen: 2, 10643 asm: arm.ACMPF, 10644 reg: regInfo{ 10645 inputs: []inputInfo{ 10646 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10647 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10648 }, 10649 }, 10650 }, 10651 { 10652 name: "CMPD", 10653 argLen: 2, 10654 asm: arm.ACMPD, 10655 reg: regInfo{ 10656 inputs: []inputInfo{ 10657 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10658 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10659 }, 10660 }, 10661 }, 10662 { 10663 name: "CMPshiftLL", 10664 auxType: auxInt32, 10665 argLen: 2, 10666 asm: arm.ACMP, 10667 reg: regInfo{ 10668 inputs: []inputInfo{ 10669 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10670 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10671 }, 10672 }, 10673 }, 10674 { 10675 name: "CMPshiftRL", 10676 auxType: auxInt32, 10677 argLen: 2, 10678 asm: arm.ACMP, 10679 reg: regInfo{ 10680 inputs: []inputInfo{ 10681 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10682 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10683 }, 10684 }, 10685 }, 10686 { 10687 name: "CMPshiftRA", 10688 auxType: auxInt32, 10689 argLen: 2, 10690 asm: arm.ACMP, 10691 reg: regInfo{ 10692 inputs: []inputInfo{ 10693 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10694 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10695 }, 10696 }, 10697 }, 10698 { 10699 name: "CMPshiftLLreg", 10700 argLen: 3, 10701 asm: arm.ACMP, 10702 reg: regInfo{ 10703 inputs: []inputInfo{ 10704 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10705 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10706 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10707 }, 10708 }, 10709 }, 10710 { 10711 name: "CMPshiftRLreg", 10712 argLen: 3, 10713 asm: arm.ACMP, 10714 reg: regInfo{ 10715 inputs: []inputInfo{ 10716 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10717 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10718 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10719 }, 10720 }, 10721 }, 10722 { 10723 name: "CMPshiftRAreg", 10724 argLen: 3, 10725 asm: arm.ACMP, 10726 reg: regInfo{ 10727 inputs: []inputInfo{ 10728 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10729 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10730 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10731 }, 10732 }, 10733 }, 10734 { 10735 name: "CMPF0", 10736 argLen: 1, 10737 asm: arm.ACMPF, 10738 reg: regInfo{ 10739 inputs: []inputInfo{ 10740 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10741 }, 10742 }, 10743 }, 10744 { 10745 name: "CMPD0", 10746 argLen: 1, 10747 asm: arm.ACMPD, 10748 reg: regInfo{ 10749 inputs: []inputInfo{ 10750 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10751 }, 10752 }, 10753 }, 10754 { 10755 name: "MOVWconst", 10756 auxType: auxInt32, 10757 argLen: 0, 10758 rematerializeable: true, 10759 asm: arm.AMOVW, 10760 reg: regInfo{ 10761 outputs: []outputInfo{ 10762 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10763 }, 10764 }, 10765 }, 10766 { 10767 name: "MOVFconst", 10768 auxType: auxFloat64, 10769 argLen: 0, 10770 rematerializeable: true, 10771 asm: arm.AMOVF, 10772 reg: regInfo{ 10773 outputs: []outputInfo{ 10774 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10775 }, 10776 }, 10777 }, 10778 { 10779 name: "MOVDconst", 10780 auxType: auxFloat64, 10781 argLen: 0, 10782 rematerializeable: true, 10783 asm: arm.AMOVD, 10784 reg: regInfo{ 10785 outputs: []outputInfo{ 10786 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10787 }, 10788 }, 10789 }, 10790 { 10791 name: "MOVWaddr", 10792 auxType: auxSymOff, 10793 argLen: 1, 10794 rematerializeable: true, 10795 symEffect: SymAddr, 10796 asm: arm.AMOVW, 10797 reg: regInfo{ 10798 inputs: []inputInfo{ 10799 {0, 4294975488}, // SP SB 10800 }, 10801 outputs: []outputInfo{ 10802 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10803 }, 10804 }, 10805 }, 10806 { 10807 name: "MOVBload", 10808 auxType: auxSymOff, 10809 argLen: 2, 10810 faultOnNilArg0: true, 10811 symEffect: SymRead, 10812 asm: arm.AMOVB, 10813 reg: regInfo{ 10814 inputs: []inputInfo{ 10815 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10816 }, 10817 outputs: []outputInfo{ 10818 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10819 }, 10820 }, 10821 }, 10822 { 10823 name: "MOVBUload", 10824 auxType: auxSymOff, 10825 argLen: 2, 10826 faultOnNilArg0: true, 10827 symEffect: SymRead, 10828 asm: arm.AMOVBU, 10829 reg: regInfo{ 10830 inputs: []inputInfo{ 10831 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10832 }, 10833 outputs: []outputInfo{ 10834 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10835 }, 10836 }, 10837 }, 10838 { 10839 name: "MOVHload", 10840 auxType: auxSymOff, 10841 argLen: 2, 10842 faultOnNilArg0: true, 10843 symEffect: SymRead, 10844 asm: arm.AMOVH, 10845 reg: regInfo{ 10846 inputs: []inputInfo{ 10847 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10848 }, 10849 outputs: []outputInfo{ 10850 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10851 }, 10852 }, 10853 }, 10854 { 10855 name: "MOVHUload", 10856 auxType: auxSymOff, 10857 argLen: 2, 10858 faultOnNilArg0: true, 10859 symEffect: SymRead, 10860 asm: arm.AMOVHU, 10861 reg: regInfo{ 10862 inputs: []inputInfo{ 10863 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10864 }, 10865 outputs: []outputInfo{ 10866 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10867 }, 10868 }, 10869 }, 10870 { 10871 name: "MOVWload", 10872 auxType: auxSymOff, 10873 argLen: 2, 10874 faultOnNilArg0: true, 10875 symEffect: SymRead, 10876 asm: arm.AMOVW, 10877 reg: regInfo{ 10878 inputs: []inputInfo{ 10879 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10880 }, 10881 outputs: []outputInfo{ 10882 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10883 }, 10884 }, 10885 }, 10886 { 10887 name: "MOVFload", 10888 auxType: auxSymOff, 10889 argLen: 2, 10890 faultOnNilArg0: true, 10891 symEffect: SymRead, 10892 asm: arm.AMOVF, 10893 reg: regInfo{ 10894 inputs: []inputInfo{ 10895 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10896 }, 10897 outputs: []outputInfo{ 10898 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10899 }, 10900 }, 10901 }, 10902 { 10903 name: "MOVDload", 10904 auxType: auxSymOff, 10905 argLen: 2, 10906 faultOnNilArg0: true, 10907 symEffect: SymRead, 10908 asm: arm.AMOVD, 10909 reg: regInfo{ 10910 inputs: []inputInfo{ 10911 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10912 }, 10913 outputs: []outputInfo{ 10914 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10915 }, 10916 }, 10917 }, 10918 { 10919 name: "MOVBstore", 10920 auxType: auxSymOff, 10921 argLen: 3, 10922 faultOnNilArg0: true, 10923 symEffect: SymWrite, 10924 asm: arm.AMOVB, 10925 reg: regInfo{ 10926 inputs: []inputInfo{ 10927 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10928 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10929 }, 10930 }, 10931 }, 10932 { 10933 name: "MOVHstore", 10934 auxType: auxSymOff, 10935 argLen: 3, 10936 faultOnNilArg0: true, 10937 symEffect: SymWrite, 10938 asm: arm.AMOVH, 10939 reg: regInfo{ 10940 inputs: []inputInfo{ 10941 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10942 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10943 }, 10944 }, 10945 }, 10946 { 10947 name: "MOVWstore", 10948 auxType: auxSymOff, 10949 argLen: 3, 10950 faultOnNilArg0: true, 10951 symEffect: SymWrite, 10952 asm: arm.AMOVW, 10953 reg: regInfo{ 10954 inputs: []inputInfo{ 10955 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10956 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10957 }, 10958 }, 10959 }, 10960 { 10961 name: "MOVFstore", 10962 auxType: auxSymOff, 10963 argLen: 3, 10964 faultOnNilArg0: true, 10965 symEffect: SymWrite, 10966 asm: arm.AMOVF, 10967 reg: regInfo{ 10968 inputs: []inputInfo{ 10969 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10970 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10971 }, 10972 }, 10973 }, 10974 { 10975 name: "MOVDstore", 10976 auxType: auxSymOff, 10977 argLen: 3, 10978 faultOnNilArg0: true, 10979 symEffect: SymWrite, 10980 asm: arm.AMOVD, 10981 reg: regInfo{ 10982 inputs: []inputInfo{ 10983 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10984 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10985 }, 10986 }, 10987 }, 10988 { 10989 name: "MOVWloadidx", 10990 argLen: 3, 10991 asm: arm.AMOVW, 10992 reg: regInfo{ 10993 inputs: []inputInfo{ 10994 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10995 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10996 }, 10997 outputs: []outputInfo{ 10998 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10999 }, 11000 }, 11001 }, 11002 { 11003 name: "MOVWloadshiftLL", 11004 auxType: auxInt32, 11005 argLen: 3, 11006 asm: arm.AMOVW, 11007 reg: regInfo{ 11008 inputs: []inputInfo{ 11009 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11010 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11011 }, 11012 outputs: []outputInfo{ 11013 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11014 }, 11015 }, 11016 }, 11017 { 11018 name: "MOVWloadshiftRL", 11019 auxType: auxInt32, 11020 argLen: 3, 11021 asm: arm.AMOVW, 11022 reg: regInfo{ 11023 inputs: []inputInfo{ 11024 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11025 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11026 }, 11027 outputs: []outputInfo{ 11028 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11029 }, 11030 }, 11031 }, 11032 { 11033 name: "MOVWloadshiftRA", 11034 auxType: auxInt32, 11035 argLen: 3, 11036 asm: arm.AMOVW, 11037 reg: regInfo{ 11038 inputs: []inputInfo{ 11039 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11040 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11041 }, 11042 outputs: []outputInfo{ 11043 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11044 }, 11045 }, 11046 }, 11047 { 11048 name: "MOVBUloadidx", 11049 argLen: 3, 11050 asm: arm.AMOVBU, 11051 reg: regInfo{ 11052 inputs: []inputInfo{ 11053 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11054 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11055 }, 11056 outputs: []outputInfo{ 11057 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11058 }, 11059 }, 11060 }, 11061 { 11062 name: "MOVBloadidx", 11063 argLen: 3, 11064 asm: arm.AMOVB, 11065 reg: regInfo{ 11066 inputs: []inputInfo{ 11067 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11068 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11069 }, 11070 outputs: []outputInfo{ 11071 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11072 }, 11073 }, 11074 }, 11075 { 11076 name: "MOVHUloadidx", 11077 argLen: 3, 11078 asm: arm.AMOVHU, 11079 reg: regInfo{ 11080 inputs: []inputInfo{ 11081 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11082 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11083 }, 11084 outputs: []outputInfo{ 11085 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11086 }, 11087 }, 11088 }, 11089 { 11090 name: "MOVHloadidx", 11091 argLen: 3, 11092 asm: arm.AMOVH, 11093 reg: regInfo{ 11094 inputs: []inputInfo{ 11095 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11096 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11097 }, 11098 outputs: []outputInfo{ 11099 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11100 }, 11101 }, 11102 }, 11103 { 11104 name: "MOVWstoreidx", 11105 argLen: 4, 11106 asm: arm.AMOVW, 11107 reg: regInfo{ 11108 inputs: []inputInfo{ 11109 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11110 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11111 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11112 }, 11113 }, 11114 }, 11115 { 11116 name: "MOVWstoreshiftLL", 11117 auxType: auxInt32, 11118 argLen: 4, 11119 asm: arm.AMOVW, 11120 reg: regInfo{ 11121 inputs: []inputInfo{ 11122 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11123 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11124 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11125 }, 11126 }, 11127 }, 11128 { 11129 name: "MOVWstoreshiftRL", 11130 auxType: auxInt32, 11131 argLen: 4, 11132 asm: arm.AMOVW, 11133 reg: regInfo{ 11134 inputs: []inputInfo{ 11135 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11136 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11137 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11138 }, 11139 }, 11140 }, 11141 { 11142 name: "MOVWstoreshiftRA", 11143 auxType: auxInt32, 11144 argLen: 4, 11145 asm: arm.AMOVW, 11146 reg: regInfo{ 11147 inputs: []inputInfo{ 11148 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11149 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11150 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11151 }, 11152 }, 11153 }, 11154 { 11155 name: "MOVBstoreidx", 11156 argLen: 4, 11157 asm: arm.AMOVB, 11158 reg: regInfo{ 11159 inputs: []inputInfo{ 11160 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11161 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11162 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11163 }, 11164 }, 11165 }, 11166 { 11167 name: "MOVHstoreidx", 11168 argLen: 4, 11169 asm: arm.AMOVH, 11170 reg: regInfo{ 11171 inputs: []inputInfo{ 11172 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11173 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11174 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11175 }, 11176 }, 11177 }, 11178 { 11179 name: "MOVBreg", 11180 argLen: 1, 11181 asm: arm.AMOVBS, 11182 reg: regInfo{ 11183 inputs: []inputInfo{ 11184 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11185 }, 11186 outputs: []outputInfo{ 11187 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11188 }, 11189 }, 11190 }, 11191 { 11192 name: "MOVBUreg", 11193 argLen: 1, 11194 asm: arm.AMOVBU, 11195 reg: regInfo{ 11196 inputs: []inputInfo{ 11197 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11198 }, 11199 outputs: []outputInfo{ 11200 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11201 }, 11202 }, 11203 }, 11204 { 11205 name: "MOVHreg", 11206 argLen: 1, 11207 asm: arm.AMOVHS, 11208 reg: regInfo{ 11209 inputs: []inputInfo{ 11210 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11211 }, 11212 outputs: []outputInfo{ 11213 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11214 }, 11215 }, 11216 }, 11217 { 11218 name: "MOVHUreg", 11219 argLen: 1, 11220 asm: arm.AMOVHU, 11221 reg: regInfo{ 11222 inputs: []inputInfo{ 11223 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11224 }, 11225 outputs: []outputInfo{ 11226 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11227 }, 11228 }, 11229 }, 11230 { 11231 name: "MOVWreg", 11232 argLen: 1, 11233 asm: arm.AMOVW, 11234 reg: regInfo{ 11235 inputs: []inputInfo{ 11236 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11237 }, 11238 outputs: []outputInfo{ 11239 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11240 }, 11241 }, 11242 }, 11243 { 11244 name: "MOVWnop", 11245 argLen: 1, 11246 resultInArg0: true, 11247 reg: regInfo{ 11248 inputs: []inputInfo{ 11249 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11250 }, 11251 outputs: []outputInfo{ 11252 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11253 }, 11254 }, 11255 }, 11256 { 11257 name: "MOVWF", 11258 argLen: 1, 11259 asm: arm.AMOVWF, 11260 reg: regInfo{ 11261 inputs: []inputInfo{ 11262 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11263 }, 11264 clobbers: 2147483648, // F15 11265 outputs: []outputInfo{ 11266 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11267 }, 11268 }, 11269 }, 11270 { 11271 name: "MOVWD", 11272 argLen: 1, 11273 asm: arm.AMOVWD, 11274 reg: regInfo{ 11275 inputs: []inputInfo{ 11276 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11277 }, 11278 clobbers: 2147483648, // F15 11279 outputs: []outputInfo{ 11280 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11281 }, 11282 }, 11283 }, 11284 { 11285 name: "MOVWUF", 11286 argLen: 1, 11287 asm: arm.AMOVWF, 11288 reg: regInfo{ 11289 inputs: []inputInfo{ 11290 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11291 }, 11292 clobbers: 2147483648, // F15 11293 outputs: []outputInfo{ 11294 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11295 }, 11296 }, 11297 }, 11298 { 11299 name: "MOVWUD", 11300 argLen: 1, 11301 asm: arm.AMOVWD, 11302 reg: regInfo{ 11303 inputs: []inputInfo{ 11304 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11305 }, 11306 clobbers: 2147483648, // F15 11307 outputs: []outputInfo{ 11308 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11309 }, 11310 }, 11311 }, 11312 { 11313 name: "MOVFW", 11314 argLen: 1, 11315 asm: arm.AMOVFW, 11316 reg: regInfo{ 11317 inputs: []inputInfo{ 11318 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11319 }, 11320 clobbers: 2147483648, // F15 11321 outputs: []outputInfo{ 11322 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11323 }, 11324 }, 11325 }, 11326 { 11327 name: "MOVDW", 11328 argLen: 1, 11329 asm: arm.AMOVDW, 11330 reg: regInfo{ 11331 inputs: []inputInfo{ 11332 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11333 }, 11334 clobbers: 2147483648, // F15 11335 outputs: []outputInfo{ 11336 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11337 }, 11338 }, 11339 }, 11340 { 11341 name: "MOVFWU", 11342 argLen: 1, 11343 asm: arm.AMOVFW, 11344 reg: regInfo{ 11345 inputs: []inputInfo{ 11346 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11347 }, 11348 clobbers: 2147483648, // F15 11349 outputs: []outputInfo{ 11350 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11351 }, 11352 }, 11353 }, 11354 { 11355 name: "MOVDWU", 11356 argLen: 1, 11357 asm: arm.AMOVDW, 11358 reg: regInfo{ 11359 inputs: []inputInfo{ 11360 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11361 }, 11362 clobbers: 2147483648, // F15 11363 outputs: []outputInfo{ 11364 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11365 }, 11366 }, 11367 }, 11368 { 11369 name: "MOVFD", 11370 argLen: 1, 11371 asm: arm.AMOVFD, 11372 reg: regInfo{ 11373 inputs: []inputInfo{ 11374 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11375 }, 11376 outputs: []outputInfo{ 11377 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11378 }, 11379 }, 11380 }, 11381 { 11382 name: "MOVDF", 11383 argLen: 1, 11384 asm: arm.AMOVDF, 11385 reg: regInfo{ 11386 inputs: []inputInfo{ 11387 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11388 }, 11389 outputs: []outputInfo{ 11390 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11391 }, 11392 }, 11393 }, 11394 { 11395 name: "CMOVWHSconst", 11396 auxType: auxInt32, 11397 argLen: 2, 11398 resultInArg0: true, 11399 asm: arm.AMOVW, 11400 reg: regInfo{ 11401 inputs: []inputInfo{ 11402 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11403 }, 11404 outputs: []outputInfo{ 11405 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11406 }, 11407 }, 11408 }, 11409 { 11410 name: "CMOVWLSconst", 11411 auxType: auxInt32, 11412 argLen: 2, 11413 resultInArg0: true, 11414 asm: arm.AMOVW, 11415 reg: regInfo{ 11416 inputs: []inputInfo{ 11417 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11418 }, 11419 outputs: []outputInfo{ 11420 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11421 }, 11422 }, 11423 }, 11424 { 11425 name: "SRAcond", 11426 argLen: 3, 11427 asm: arm.ASRA, 11428 reg: regInfo{ 11429 inputs: []inputInfo{ 11430 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11431 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11432 }, 11433 outputs: []outputInfo{ 11434 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11435 }, 11436 }, 11437 }, 11438 { 11439 name: "CALLstatic", 11440 auxType: auxSymOff, 11441 argLen: 1, 11442 clobberFlags: true, 11443 call: true, 11444 symEffect: SymNone, 11445 reg: regInfo{ 11446 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11447 }, 11448 }, 11449 { 11450 name: "CALLclosure", 11451 auxType: auxInt64, 11452 argLen: 3, 11453 clobberFlags: true, 11454 call: true, 11455 reg: regInfo{ 11456 inputs: []inputInfo{ 11457 {1, 128}, // R7 11458 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 11459 }, 11460 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11461 }, 11462 }, 11463 { 11464 name: "CALLinter", 11465 auxType: auxInt64, 11466 argLen: 2, 11467 clobberFlags: true, 11468 call: true, 11469 reg: regInfo{ 11470 inputs: []inputInfo{ 11471 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11472 }, 11473 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11474 }, 11475 }, 11476 { 11477 name: "LoweredNilCheck", 11478 argLen: 2, 11479 nilCheck: true, 11480 faultOnNilArg0: true, 11481 reg: regInfo{ 11482 inputs: []inputInfo{ 11483 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11484 }, 11485 }, 11486 }, 11487 { 11488 name: "Equal", 11489 argLen: 1, 11490 reg: regInfo{ 11491 outputs: []outputInfo{ 11492 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11493 }, 11494 }, 11495 }, 11496 { 11497 name: "NotEqual", 11498 argLen: 1, 11499 reg: regInfo{ 11500 outputs: []outputInfo{ 11501 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11502 }, 11503 }, 11504 }, 11505 { 11506 name: "LessThan", 11507 argLen: 1, 11508 reg: regInfo{ 11509 outputs: []outputInfo{ 11510 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11511 }, 11512 }, 11513 }, 11514 { 11515 name: "LessEqual", 11516 argLen: 1, 11517 reg: regInfo{ 11518 outputs: []outputInfo{ 11519 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11520 }, 11521 }, 11522 }, 11523 { 11524 name: "GreaterThan", 11525 argLen: 1, 11526 reg: regInfo{ 11527 outputs: []outputInfo{ 11528 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11529 }, 11530 }, 11531 }, 11532 { 11533 name: "GreaterEqual", 11534 argLen: 1, 11535 reg: regInfo{ 11536 outputs: []outputInfo{ 11537 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11538 }, 11539 }, 11540 }, 11541 { 11542 name: "LessThanU", 11543 argLen: 1, 11544 reg: regInfo{ 11545 outputs: []outputInfo{ 11546 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11547 }, 11548 }, 11549 }, 11550 { 11551 name: "LessEqualU", 11552 argLen: 1, 11553 reg: regInfo{ 11554 outputs: []outputInfo{ 11555 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11556 }, 11557 }, 11558 }, 11559 { 11560 name: "GreaterThanU", 11561 argLen: 1, 11562 reg: regInfo{ 11563 outputs: []outputInfo{ 11564 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11565 }, 11566 }, 11567 }, 11568 { 11569 name: "GreaterEqualU", 11570 argLen: 1, 11571 reg: regInfo{ 11572 outputs: []outputInfo{ 11573 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11574 }, 11575 }, 11576 }, 11577 { 11578 name: "DUFFZERO", 11579 auxType: auxInt64, 11580 argLen: 3, 11581 faultOnNilArg0: true, 11582 reg: regInfo{ 11583 inputs: []inputInfo{ 11584 {0, 2}, // R1 11585 {1, 1}, // R0 11586 }, 11587 clobbers: 16386, // R1 R14 11588 }, 11589 }, 11590 { 11591 name: "DUFFCOPY", 11592 auxType: auxInt64, 11593 argLen: 3, 11594 faultOnNilArg0: true, 11595 faultOnNilArg1: true, 11596 reg: regInfo{ 11597 inputs: []inputInfo{ 11598 {0, 4}, // R2 11599 {1, 2}, // R1 11600 }, 11601 clobbers: 16391, // R0 R1 R2 R14 11602 }, 11603 }, 11604 { 11605 name: "LoweredZero", 11606 auxType: auxInt64, 11607 argLen: 4, 11608 clobberFlags: true, 11609 faultOnNilArg0: true, 11610 reg: regInfo{ 11611 inputs: []inputInfo{ 11612 {0, 2}, // R1 11613 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11614 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11615 }, 11616 clobbers: 2, // R1 11617 }, 11618 }, 11619 { 11620 name: "LoweredMove", 11621 auxType: auxInt64, 11622 argLen: 4, 11623 clobberFlags: true, 11624 faultOnNilArg0: true, 11625 faultOnNilArg1: true, 11626 reg: regInfo{ 11627 inputs: []inputInfo{ 11628 {0, 4}, // R2 11629 {1, 2}, // R1 11630 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11631 }, 11632 clobbers: 6, // R1 R2 11633 }, 11634 }, 11635 { 11636 name: "LoweredGetClosurePtr", 11637 argLen: 0, 11638 reg: regInfo{ 11639 outputs: []outputInfo{ 11640 {0, 128}, // R7 11641 }, 11642 }, 11643 }, 11644 { 11645 name: "LoweredGetCallerSP", 11646 argLen: 0, 11647 rematerializeable: true, 11648 reg: regInfo{ 11649 outputs: []outputInfo{ 11650 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11651 }, 11652 }, 11653 }, 11654 { 11655 name: "MOVWconvert", 11656 argLen: 2, 11657 asm: arm.AMOVW, 11658 reg: regInfo{ 11659 inputs: []inputInfo{ 11660 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11661 }, 11662 outputs: []outputInfo{ 11663 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11664 }, 11665 }, 11666 }, 11667 { 11668 name: "FlagEQ", 11669 argLen: 0, 11670 reg: regInfo{}, 11671 }, 11672 { 11673 name: "FlagLT_ULT", 11674 argLen: 0, 11675 reg: regInfo{}, 11676 }, 11677 { 11678 name: "FlagLT_UGT", 11679 argLen: 0, 11680 reg: regInfo{}, 11681 }, 11682 { 11683 name: "FlagGT_UGT", 11684 argLen: 0, 11685 reg: regInfo{}, 11686 }, 11687 { 11688 name: "FlagGT_ULT", 11689 argLen: 0, 11690 reg: regInfo{}, 11691 }, 11692 { 11693 name: "InvertFlags", 11694 argLen: 1, 11695 reg: regInfo{}, 11696 }, 11697 11698 { 11699 name: "ADD", 11700 argLen: 2, 11701 commutative: true, 11702 asm: arm64.AADD, 11703 reg: regInfo{ 11704 inputs: []inputInfo{ 11705 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11706 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11707 }, 11708 outputs: []outputInfo{ 11709 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11710 }, 11711 }, 11712 }, 11713 { 11714 name: "ADDconst", 11715 auxType: auxInt64, 11716 argLen: 1, 11717 asm: arm64.AADD, 11718 reg: regInfo{ 11719 inputs: []inputInfo{ 11720 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 11721 }, 11722 outputs: []outputInfo{ 11723 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11724 }, 11725 }, 11726 }, 11727 { 11728 name: "SUB", 11729 argLen: 2, 11730 asm: arm64.ASUB, 11731 reg: regInfo{ 11732 inputs: []inputInfo{ 11733 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11734 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11735 }, 11736 outputs: []outputInfo{ 11737 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11738 }, 11739 }, 11740 }, 11741 { 11742 name: "SUBconst", 11743 auxType: auxInt64, 11744 argLen: 1, 11745 asm: arm64.ASUB, 11746 reg: regInfo{ 11747 inputs: []inputInfo{ 11748 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11749 }, 11750 outputs: []outputInfo{ 11751 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11752 }, 11753 }, 11754 }, 11755 { 11756 name: "MUL", 11757 argLen: 2, 11758 commutative: true, 11759 asm: arm64.AMUL, 11760 reg: regInfo{ 11761 inputs: []inputInfo{ 11762 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11763 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11764 }, 11765 outputs: []outputInfo{ 11766 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11767 }, 11768 }, 11769 }, 11770 { 11771 name: "MULW", 11772 argLen: 2, 11773 commutative: true, 11774 asm: arm64.AMULW, 11775 reg: regInfo{ 11776 inputs: []inputInfo{ 11777 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11778 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11779 }, 11780 outputs: []outputInfo{ 11781 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11782 }, 11783 }, 11784 }, 11785 { 11786 name: "MULH", 11787 argLen: 2, 11788 commutative: true, 11789 asm: arm64.ASMULH, 11790 reg: regInfo{ 11791 inputs: []inputInfo{ 11792 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11793 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11794 }, 11795 outputs: []outputInfo{ 11796 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11797 }, 11798 }, 11799 }, 11800 { 11801 name: "UMULH", 11802 argLen: 2, 11803 commutative: true, 11804 asm: arm64.AUMULH, 11805 reg: regInfo{ 11806 inputs: []inputInfo{ 11807 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11808 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11809 }, 11810 outputs: []outputInfo{ 11811 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11812 }, 11813 }, 11814 }, 11815 { 11816 name: "MULL", 11817 argLen: 2, 11818 commutative: true, 11819 asm: arm64.ASMULL, 11820 reg: regInfo{ 11821 inputs: []inputInfo{ 11822 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11823 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11824 }, 11825 outputs: []outputInfo{ 11826 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11827 }, 11828 }, 11829 }, 11830 { 11831 name: "UMULL", 11832 argLen: 2, 11833 commutative: true, 11834 asm: arm64.AUMULL, 11835 reg: regInfo{ 11836 inputs: []inputInfo{ 11837 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11838 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11839 }, 11840 outputs: []outputInfo{ 11841 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11842 }, 11843 }, 11844 }, 11845 { 11846 name: "DIV", 11847 argLen: 2, 11848 asm: arm64.ASDIV, 11849 reg: regInfo{ 11850 inputs: []inputInfo{ 11851 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11852 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11853 }, 11854 outputs: []outputInfo{ 11855 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11856 }, 11857 }, 11858 }, 11859 { 11860 name: "UDIV", 11861 argLen: 2, 11862 asm: arm64.AUDIV, 11863 reg: regInfo{ 11864 inputs: []inputInfo{ 11865 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11866 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11867 }, 11868 outputs: []outputInfo{ 11869 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11870 }, 11871 }, 11872 }, 11873 { 11874 name: "DIVW", 11875 argLen: 2, 11876 asm: arm64.ASDIVW, 11877 reg: regInfo{ 11878 inputs: []inputInfo{ 11879 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11880 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11881 }, 11882 outputs: []outputInfo{ 11883 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11884 }, 11885 }, 11886 }, 11887 { 11888 name: "UDIVW", 11889 argLen: 2, 11890 asm: arm64.AUDIVW, 11891 reg: regInfo{ 11892 inputs: []inputInfo{ 11893 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11894 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11895 }, 11896 outputs: []outputInfo{ 11897 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11898 }, 11899 }, 11900 }, 11901 { 11902 name: "MOD", 11903 argLen: 2, 11904 asm: arm64.AREM, 11905 reg: regInfo{ 11906 inputs: []inputInfo{ 11907 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11908 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11909 }, 11910 outputs: []outputInfo{ 11911 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11912 }, 11913 }, 11914 }, 11915 { 11916 name: "UMOD", 11917 argLen: 2, 11918 asm: arm64.AUREM, 11919 reg: regInfo{ 11920 inputs: []inputInfo{ 11921 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11922 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11923 }, 11924 outputs: []outputInfo{ 11925 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11926 }, 11927 }, 11928 }, 11929 { 11930 name: "MODW", 11931 argLen: 2, 11932 asm: arm64.AREMW, 11933 reg: regInfo{ 11934 inputs: []inputInfo{ 11935 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11936 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11937 }, 11938 outputs: []outputInfo{ 11939 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11940 }, 11941 }, 11942 }, 11943 { 11944 name: "UMODW", 11945 argLen: 2, 11946 asm: arm64.AUREMW, 11947 reg: regInfo{ 11948 inputs: []inputInfo{ 11949 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11950 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11951 }, 11952 outputs: []outputInfo{ 11953 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11954 }, 11955 }, 11956 }, 11957 { 11958 name: "FADDS", 11959 argLen: 2, 11960 commutative: true, 11961 asm: arm64.AFADDS, 11962 reg: regInfo{ 11963 inputs: []inputInfo{ 11964 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11965 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11966 }, 11967 outputs: []outputInfo{ 11968 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11969 }, 11970 }, 11971 }, 11972 { 11973 name: "FADDD", 11974 argLen: 2, 11975 commutative: true, 11976 asm: arm64.AFADDD, 11977 reg: regInfo{ 11978 inputs: []inputInfo{ 11979 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11980 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11981 }, 11982 outputs: []outputInfo{ 11983 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11984 }, 11985 }, 11986 }, 11987 { 11988 name: "FSUBS", 11989 argLen: 2, 11990 asm: arm64.AFSUBS, 11991 reg: regInfo{ 11992 inputs: []inputInfo{ 11993 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11994 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11995 }, 11996 outputs: []outputInfo{ 11997 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11998 }, 11999 }, 12000 }, 12001 { 12002 name: "FSUBD", 12003 argLen: 2, 12004 asm: arm64.AFSUBD, 12005 reg: regInfo{ 12006 inputs: []inputInfo{ 12007 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12008 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12009 }, 12010 outputs: []outputInfo{ 12011 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12012 }, 12013 }, 12014 }, 12015 { 12016 name: "FMULS", 12017 argLen: 2, 12018 commutative: true, 12019 asm: arm64.AFMULS, 12020 reg: regInfo{ 12021 inputs: []inputInfo{ 12022 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12023 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12024 }, 12025 outputs: []outputInfo{ 12026 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12027 }, 12028 }, 12029 }, 12030 { 12031 name: "FMULD", 12032 argLen: 2, 12033 commutative: true, 12034 asm: arm64.AFMULD, 12035 reg: regInfo{ 12036 inputs: []inputInfo{ 12037 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12038 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12039 }, 12040 outputs: []outputInfo{ 12041 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12042 }, 12043 }, 12044 }, 12045 { 12046 name: "FDIVS", 12047 argLen: 2, 12048 asm: arm64.AFDIVS, 12049 reg: regInfo{ 12050 inputs: []inputInfo{ 12051 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12052 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12053 }, 12054 outputs: []outputInfo{ 12055 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12056 }, 12057 }, 12058 }, 12059 { 12060 name: "FDIVD", 12061 argLen: 2, 12062 asm: arm64.AFDIVD, 12063 reg: regInfo{ 12064 inputs: []inputInfo{ 12065 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12066 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12067 }, 12068 outputs: []outputInfo{ 12069 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12070 }, 12071 }, 12072 }, 12073 { 12074 name: "AND", 12075 argLen: 2, 12076 commutative: true, 12077 asm: arm64.AAND, 12078 reg: regInfo{ 12079 inputs: []inputInfo{ 12080 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12081 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12082 }, 12083 outputs: []outputInfo{ 12084 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12085 }, 12086 }, 12087 }, 12088 { 12089 name: "ANDconst", 12090 auxType: auxInt64, 12091 argLen: 1, 12092 asm: arm64.AAND, 12093 reg: regInfo{ 12094 inputs: []inputInfo{ 12095 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12096 }, 12097 outputs: []outputInfo{ 12098 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12099 }, 12100 }, 12101 }, 12102 { 12103 name: "OR", 12104 argLen: 2, 12105 commutative: true, 12106 asm: arm64.AORR, 12107 reg: regInfo{ 12108 inputs: []inputInfo{ 12109 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12110 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12111 }, 12112 outputs: []outputInfo{ 12113 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12114 }, 12115 }, 12116 }, 12117 { 12118 name: "ORconst", 12119 auxType: auxInt64, 12120 argLen: 1, 12121 asm: arm64.AORR, 12122 reg: regInfo{ 12123 inputs: []inputInfo{ 12124 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12125 }, 12126 outputs: []outputInfo{ 12127 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12128 }, 12129 }, 12130 }, 12131 { 12132 name: "XOR", 12133 argLen: 2, 12134 commutative: true, 12135 asm: arm64.AEOR, 12136 reg: regInfo{ 12137 inputs: []inputInfo{ 12138 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12139 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12140 }, 12141 outputs: []outputInfo{ 12142 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12143 }, 12144 }, 12145 }, 12146 { 12147 name: "XORconst", 12148 auxType: auxInt64, 12149 argLen: 1, 12150 asm: arm64.AEOR, 12151 reg: regInfo{ 12152 inputs: []inputInfo{ 12153 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12154 }, 12155 outputs: []outputInfo{ 12156 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12157 }, 12158 }, 12159 }, 12160 { 12161 name: "BIC", 12162 argLen: 2, 12163 asm: arm64.ABIC, 12164 reg: regInfo{ 12165 inputs: []inputInfo{ 12166 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12167 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12168 }, 12169 outputs: []outputInfo{ 12170 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12171 }, 12172 }, 12173 }, 12174 { 12175 name: "BICconst", 12176 auxType: auxInt64, 12177 argLen: 1, 12178 asm: arm64.ABIC, 12179 reg: regInfo{ 12180 inputs: []inputInfo{ 12181 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12182 }, 12183 outputs: []outputInfo{ 12184 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12185 }, 12186 }, 12187 }, 12188 { 12189 name: "MVN", 12190 argLen: 1, 12191 asm: arm64.AMVN, 12192 reg: regInfo{ 12193 inputs: []inputInfo{ 12194 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12195 }, 12196 outputs: []outputInfo{ 12197 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12198 }, 12199 }, 12200 }, 12201 { 12202 name: "NEG", 12203 argLen: 1, 12204 asm: arm64.ANEG, 12205 reg: regInfo{ 12206 inputs: []inputInfo{ 12207 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12208 }, 12209 outputs: []outputInfo{ 12210 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12211 }, 12212 }, 12213 }, 12214 { 12215 name: "FNEGS", 12216 argLen: 1, 12217 asm: arm64.AFNEGS, 12218 reg: regInfo{ 12219 inputs: []inputInfo{ 12220 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12221 }, 12222 outputs: []outputInfo{ 12223 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12224 }, 12225 }, 12226 }, 12227 { 12228 name: "FNEGD", 12229 argLen: 1, 12230 asm: arm64.AFNEGD, 12231 reg: regInfo{ 12232 inputs: []inputInfo{ 12233 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12234 }, 12235 outputs: []outputInfo{ 12236 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12237 }, 12238 }, 12239 }, 12240 { 12241 name: "FSQRTD", 12242 argLen: 1, 12243 asm: arm64.AFSQRTD, 12244 reg: regInfo{ 12245 inputs: []inputInfo{ 12246 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12247 }, 12248 outputs: []outputInfo{ 12249 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12250 }, 12251 }, 12252 }, 12253 { 12254 name: "REV", 12255 argLen: 1, 12256 asm: arm64.AREV, 12257 reg: regInfo{ 12258 inputs: []inputInfo{ 12259 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12260 }, 12261 outputs: []outputInfo{ 12262 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12263 }, 12264 }, 12265 }, 12266 { 12267 name: "REVW", 12268 argLen: 1, 12269 asm: arm64.AREVW, 12270 reg: regInfo{ 12271 inputs: []inputInfo{ 12272 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12273 }, 12274 outputs: []outputInfo{ 12275 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12276 }, 12277 }, 12278 }, 12279 { 12280 name: "REV16W", 12281 argLen: 1, 12282 asm: arm64.AREV16W, 12283 reg: regInfo{ 12284 inputs: []inputInfo{ 12285 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12286 }, 12287 outputs: []outputInfo{ 12288 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12289 }, 12290 }, 12291 }, 12292 { 12293 name: "RBIT", 12294 argLen: 1, 12295 asm: arm64.ARBIT, 12296 reg: regInfo{ 12297 inputs: []inputInfo{ 12298 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12299 }, 12300 outputs: []outputInfo{ 12301 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12302 }, 12303 }, 12304 }, 12305 { 12306 name: "RBITW", 12307 argLen: 1, 12308 asm: arm64.ARBITW, 12309 reg: regInfo{ 12310 inputs: []inputInfo{ 12311 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12312 }, 12313 outputs: []outputInfo{ 12314 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12315 }, 12316 }, 12317 }, 12318 { 12319 name: "CLZ", 12320 argLen: 1, 12321 asm: arm64.ACLZ, 12322 reg: regInfo{ 12323 inputs: []inputInfo{ 12324 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12325 }, 12326 outputs: []outputInfo{ 12327 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12328 }, 12329 }, 12330 }, 12331 { 12332 name: "CLZW", 12333 argLen: 1, 12334 asm: arm64.ACLZW, 12335 reg: regInfo{ 12336 inputs: []inputInfo{ 12337 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12338 }, 12339 outputs: []outputInfo{ 12340 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12341 }, 12342 }, 12343 }, 12344 { 12345 name: "SLL", 12346 argLen: 2, 12347 asm: arm64.ALSL, 12348 reg: regInfo{ 12349 inputs: []inputInfo{ 12350 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12351 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12352 }, 12353 outputs: []outputInfo{ 12354 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12355 }, 12356 }, 12357 }, 12358 { 12359 name: "SLLconst", 12360 auxType: auxInt64, 12361 argLen: 1, 12362 asm: arm64.ALSL, 12363 reg: regInfo{ 12364 inputs: []inputInfo{ 12365 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12366 }, 12367 outputs: []outputInfo{ 12368 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12369 }, 12370 }, 12371 }, 12372 { 12373 name: "SRL", 12374 argLen: 2, 12375 asm: arm64.ALSR, 12376 reg: regInfo{ 12377 inputs: []inputInfo{ 12378 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12379 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12380 }, 12381 outputs: []outputInfo{ 12382 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12383 }, 12384 }, 12385 }, 12386 { 12387 name: "SRLconst", 12388 auxType: auxInt64, 12389 argLen: 1, 12390 asm: arm64.ALSR, 12391 reg: regInfo{ 12392 inputs: []inputInfo{ 12393 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12394 }, 12395 outputs: []outputInfo{ 12396 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12397 }, 12398 }, 12399 }, 12400 { 12401 name: "SRA", 12402 argLen: 2, 12403 asm: arm64.AASR, 12404 reg: regInfo{ 12405 inputs: []inputInfo{ 12406 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12407 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12408 }, 12409 outputs: []outputInfo{ 12410 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12411 }, 12412 }, 12413 }, 12414 { 12415 name: "SRAconst", 12416 auxType: auxInt64, 12417 argLen: 1, 12418 asm: arm64.AASR, 12419 reg: regInfo{ 12420 inputs: []inputInfo{ 12421 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12422 }, 12423 outputs: []outputInfo{ 12424 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12425 }, 12426 }, 12427 }, 12428 { 12429 name: "RORconst", 12430 auxType: auxInt64, 12431 argLen: 1, 12432 asm: arm64.AROR, 12433 reg: regInfo{ 12434 inputs: []inputInfo{ 12435 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12436 }, 12437 outputs: []outputInfo{ 12438 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12439 }, 12440 }, 12441 }, 12442 { 12443 name: "RORWconst", 12444 auxType: auxInt64, 12445 argLen: 1, 12446 asm: arm64.ARORW, 12447 reg: regInfo{ 12448 inputs: []inputInfo{ 12449 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12450 }, 12451 outputs: []outputInfo{ 12452 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12453 }, 12454 }, 12455 }, 12456 { 12457 name: "CMP", 12458 argLen: 2, 12459 asm: arm64.ACMP, 12460 reg: regInfo{ 12461 inputs: []inputInfo{ 12462 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12463 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12464 }, 12465 }, 12466 }, 12467 { 12468 name: "CMPconst", 12469 auxType: auxInt64, 12470 argLen: 1, 12471 asm: arm64.ACMP, 12472 reg: regInfo{ 12473 inputs: []inputInfo{ 12474 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12475 }, 12476 }, 12477 }, 12478 { 12479 name: "CMPW", 12480 argLen: 2, 12481 asm: arm64.ACMPW, 12482 reg: regInfo{ 12483 inputs: []inputInfo{ 12484 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12485 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12486 }, 12487 }, 12488 }, 12489 { 12490 name: "CMPWconst", 12491 auxType: auxInt32, 12492 argLen: 1, 12493 asm: arm64.ACMPW, 12494 reg: regInfo{ 12495 inputs: []inputInfo{ 12496 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12497 }, 12498 }, 12499 }, 12500 { 12501 name: "CMN", 12502 argLen: 2, 12503 asm: arm64.ACMN, 12504 reg: regInfo{ 12505 inputs: []inputInfo{ 12506 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12507 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12508 }, 12509 }, 12510 }, 12511 { 12512 name: "CMNconst", 12513 auxType: auxInt64, 12514 argLen: 1, 12515 asm: arm64.ACMN, 12516 reg: regInfo{ 12517 inputs: []inputInfo{ 12518 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12519 }, 12520 }, 12521 }, 12522 { 12523 name: "CMNW", 12524 argLen: 2, 12525 asm: arm64.ACMNW, 12526 reg: regInfo{ 12527 inputs: []inputInfo{ 12528 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12529 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12530 }, 12531 }, 12532 }, 12533 { 12534 name: "CMNWconst", 12535 auxType: auxInt32, 12536 argLen: 1, 12537 asm: arm64.ACMNW, 12538 reg: regInfo{ 12539 inputs: []inputInfo{ 12540 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12541 }, 12542 }, 12543 }, 12544 { 12545 name: "FCMPS", 12546 argLen: 2, 12547 asm: arm64.AFCMPS, 12548 reg: regInfo{ 12549 inputs: []inputInfo{ 12550 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12551 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12552 }, 12553 }, 12554 }, 12555 { 12556 name: "FCMPD", 12557 argLen: 2, 12558 asm: arm64.AFCMPD, 12559 reg: regInfo{ 12560 inputs: []inputInfo{ 12561 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12562 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12563 }, 12564 }, 12565 }, 12566 { 12567 name: "ADDshiftLL", 12568 auxType: auxInt64, 12569 argLen: 2, 12570 asm: arm64.AADD, 12571 reg: regInfo{ 12572 inputs: []inputInfo{ 12573 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12574 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12575 }, 12576 outputs: []outputInfo{ 12577 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12578 }, 12579 }, 12580 }, 12581 { 12582 name: "ADDshiftRL", 12583 auxType: auxInt64, 12584 argLen: 2, 12585 asm: arm64.AADD, 12586 reg: regInfo{ 12587 inputs: []inputInfo{ 12588 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12589 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12590 }, 12591 outputs: []outputInfo{ 12592 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12593 }, 12594 }, 12595 }, 12596 { 12597 name: "ADDshiftRA", 12598 auxType: auxInt64, 12599 argLen: 2, 12600 asm: arm64.AADD, 12601 reg: regInfo{ 12602 inputs: []inputInfo{ 12603 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12604 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12605 }, 12606 outputs: []outputInfo{ 12607 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12608 }, 12609 }, 12610 }, 12611 { 12612 name: "SUBshiftLL", 12613 auxType: auxInt64, 12614 argLen: 2, 12615 asm: arm64.ASUB, 12616 reg: regInfo{ 12617 inputs: []inputInfo{ 12618 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12619 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12620 }, 12621 outputs: []outputInfo{ 12622 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12623 }, 12624 }, 12625 }, 12626 { 12627 name: "SUBshiftRL", 12628 auxType: auxInt64, 12629 argLen: 2, 12630 asm: arm64.ASUB, 12631 reg: regInfo{ 12632 inputs: []inputInfo{ 12633 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12634 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12635 }, 12636 outputs: []outputInfo{ 12637 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12638 }, 12639 }, 12640 }, 12641 { 12642 name: "SUBshiftRA", 12643 auxType: auxInt64, 12644 argLen: 2, 12645 asm: arm64.ASUB, 12646 reg: regInfo{ 12647 inputs: []inputInfo{ 12648 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12649 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12650 }, 12651 outputs: []outputInfo{ 12652 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12653 }, 12654 }, 12655 }, 12656 { 12657 name: "ANDshiftLL", 12658 auxType: auxInt64, 12659 argLen: 2, 12660 asm: arm64.AAND, 12661 reg: regInfo{ 12662 inputs: []inputInfo{ 12663 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12664 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12665 }, 12666 outputs: []outputInfo{ 12667 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12668 }, 12669 }, 12670 }, 12671 { 12672 name: "ANDshiftRL", 12673 auxType: auxInt64, 12674 argLen: 2, 12675 asm: arm64.AAND, 12676 reg: regInfo{ 12677 inputs: []inputInfo{ 12678 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12679 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12680 }, 12681 outputs: []outputInfo{ 12682 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12683 }, 12684 }, 12685 }, 12686 { 12687 name: "ANDshiftRA", 12688 auxType: auxInt64, 12689 argLen: 2, 12690 asm: arm64.AAND, 12691 reg: regInfo{ 12692 inputs: []inputInfo{ 12693 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12694 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12695 }, 12696 outputs: []outputInfo{ 12697 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12698 }, 12699 }, 12700 }, 12701 { 12702 name: "ORshiftLL", 12703 auxType: auxInt64, 12704 argLen: 2, 12705 asm: arm64.AORR, 12706 reg: regInfo{ 12707 inputs: []inputInfo{ 12708 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12709 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12710 }, 12711 outputs: []outputInfo{ 12712 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12713 }, 12714 }, 12715 }, 12716 { 12717 name: "ORshiftRL", 12718 auxType: auxInt64, 12719 argLen: 2, 12720 asm: arm64.AORR, 12721 reg: regInfo{ 12722 inputs: []inputInfo{ 12723 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12724 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12725 }, 12726 outputs: []outputInfo{ 12727 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12728 }, 12729 }, 12730 }, 12731 { 12732 name: "ORshiftRA", 12733 auxType: auxInt64, 12734 argLen: 2, 12735 asm: arm64.AORR, 12736 reg: regInfo{ 12737 inputs: []inputInfo{ 12738 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12739 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12740 }, 12741 outputs: []outputInfo{ 12742 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12743 }, 12744 }, 12745 }, 12746 { 12747 name: "XORshiftLL", 12748 auxType: auxInt64, 12749 argLen: 2, 12750 asm: arm64.AEOR, 12751 reg: regInfo{ 12752 inputs: []inputInfo{ 12753 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12754 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12755 }, 12756 outputs: []outputInfo{ 12757 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12758 }, 12759 }, 12760 }, 12761 { 12762 name: "XORshiftRL", 12763 auxType: auxInt64, 12764 argLen: 2, 12765 asm: arm64.AEOR, 12766 reg: regInfo{ 12767 inputs: []inputInfo{ 12768 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12769 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12770 }, 12771 outputs: []outputInfo{ 12772 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12773 }, 12774 }, 12775 }, 12776 { 12777 name: "XORshiftRA", 12778 auxType: auxInt64, 12779 argLen: 2, 12780 asm: arm64.AEOR, 12781 reg: regInfo{ 12782 inputs: []inputInfo{ 12783 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12784 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12785 }, 12786 outputs: []outputInfo{ 12787 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12788 }, 12789 }, 12790 }, 12791 { 12792 name: "BICshiftLL", 12793 auxType: auxInt64, 12794 argLen: 2, 12795 asm: arm64.ABIC, 12796 reg: regInfo{ 12797 inputs: []inputInfo{ 12798 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12799 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12800 }, 12801 outputs: []outputInfo{ 12802 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12803 }, 12804 }, 12805 }, 12806 { 12807 name: "BICshiftRL", 12808 auxType: auxInt64, 12809 argLen: 2, 12810 asm: arm64.ABIC, 12811 reg: regInfo{ 12812 inputs: []inputInfo{ 12813 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12814 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12815 }, 12816 outputs: []outputInfo{ 12817 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12818 }, 12819 }, 12820 }, 12821 { 12822 name: "BICshiftRA", 12823 auxType: auxInt64, 12824 argLen: 2, 12825 asm: arm64.ABIC, 12826 reg: regInfo{ 12827 inputs: []inputInfo{ 12828 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12829 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12830 }, 12831 outputs: []outputInfo{ 12832 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12833 }, 12834 }, 12835 }, 12836 { 12837 name: "CMPshiftLL", 12838 auxType: auxInt64, 12839 argLen: 2, 12840 asm: arm64.ACMP, 12841 reg: regInfo{ 12842 inputs: []inputInfo{ 12843 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12844 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12845 }, 12846 }, 12847 }, 12848 { 12849 name: "CMPshiftRL", 12850 auxType: auxInt64, 12851 argLen: 2, 12852 asm: arm64.ACMP, 12853 reg: regInfo{ 12854 inputs: []inputInfo{ 12855 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12856 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12857 }, 12858 }, 12859 }, 12860 { 12861 name: "CMPshiftRA", 12862 auxType: auxInt64, 12863 argLen: 2, 12864 asm: arm64.ACMP, 12865 reg: regInfo{ 12866 inputs: []inputInfo{ 12867 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12868 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12869 }, 12870 }, 12871 }, 12872 { 12873 name: "MOVDconst", 12874 auxType: auxInt64, 12875 argLen: 0, 12876 rematerializeable: true, 12877 asm: arm64.AMOVD, 12878 reg: regInfo{ 12879 outputs: []outputInfo{ 12880 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12881 }, 12882 }, 12883 }, 12884 { 12885 name: "FMOVSconst", 12886 auxType: auxFloat64, 12887 argLen: 0, 12888 rematerializeable: true, 12889 asm: arm64.AFMOVS, 12890 reg: regInfo{ 12891 outputs: []outputInfo{ 12892 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12893 }, 12894 }, 12895 }, 12896 { 12897 name: "FMOVDconst", 12898 auxType: auxFloat64, 12899 argLen: 0, 12900 rematerializeable: true, 12901 asm: arm64.AFMOVD, 12902 reg: regInfo{ 12903 outputs: []outputInfo{ 12904 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12905 }, 12906 }, 12907 }, 12908 { 12909 name: "MOVDaddr", 12910 auxType: auxSymOff, 12911 argLen: 1, 12912 rematerializeable: true, 12913 symEffect: SymAddr, 12914 asm: arm64.AMOVD, 12915 reg: regInfo{ 12916 inputs: []inputInfo{ 12917 {0, 9223372037928517632}, // SP SB 12918 }, 12919 outputs: []outputInfo{ 12920 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12921 }, 12922 }, 12923 }, 12924 { 12925 name: "MOVBload", 12926 auxType: auxSymOff, 12927 argLen: 2, 12928 faultOnNilArg0: true, 12929 symEffect: SymRead, 12930 asm: arm64.AMOVB, 12931 reg: regInfo{ 12932 inputs: []inputInfo{ 12933 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12934 }, 12935 outputs: []outputInfo{ 12936 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12937 }, 12938 }, 12939 }, 12940 { 12941 name: "MOVBUload", 12942 auxType: auxSymOff, 12943 argLen: 2, 12944 faultOnNilArg0: true, 12945 symEffect: SymRead, 12946 asm: arm64.AMOVBU, 12947 reg: regInfo{ 12948 inputs: []inputInfo{ 12949 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12950 }, 12951 outputs: []outputInfo{ 12952 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12953 }, 12954 }, 12955 }, 12956 { 12957 name: "MOVHload", 12958 auxType: auxSymOff, 12959 argLen: 2, 12960 faultOnNilArg0: true, 12961 symEffect: SymRead, 12962 asm: arm64.AMOVH, 12963 reg: regInfo{ 12964 inputs: []inputInfo{ 12965 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12966 }, 12967 outputs: []outputInfo{ 12968 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12969 }, 12970 }, 12971 }, 12972 { 12973 name: "MOVHUload", 12974 auxType: auxSymOff, 12975 argLen: 2, 12976 faultOnNilArg0: true, 12977 symEffect: SymRead, 12978 asm: arm64.AMOVHU, 12979 reg: regInfo{ 12980 inputs: []inputInfo{ 12981 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12982 }, 12983 outputs: []outputInfo{ 12984 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12985 }, 12986 }, 12987 }, 12988 { 12989 name: "MOVWload", 12990 auxType: auxSymOff, 12991 argLen: 2, 12992 faultOnNilArg0: true, 12993 symEffect: SymRead, 12994 asm: arm64.AMOVW, 12995 reg: regInfo{ 12996 inputs: []inputInfo{ 12997 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12998 }, 12999 outputs: []outputInfo{ 13000 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13001 }, 13002 }, 13003 }, 13004 { 13005 name: "MOVWUload", 13006 auxType: auxSymOff, 13007 argLen: 2, 13008 faultOnNilArg0: true, 13009 symEffect: SymRead, 13010 asm: arm64.AMOVWU, 13011 reg: regInfo{ 13012 inputs: []inputInfo{ 13013 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13014 }, 13015 outputs: []outputInfo{ 13016 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13017 }, 13018 }, 13019 }, 13020 { 13021 name: "MOVDload", 13022 auxType: auxSymOff, 13023 argLen: 2, 13024 faultOnNilArg0: true, 13025 symEffect: SymRead, 13026 asm: arm64.AMOVD, 13027 reg: regInfo{ 13028 inputs: []inputInfo{ 13029 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13030 }, 13031 outputs: []outputInfo{ 13032 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13033 }, 13034 }, 13035 }, 13036 { 13037 name: "FMOVSload", 13038 auxType: auxSymOff, 13039 argLen: 2, 13040 faultOnNilArg0: true, 13041 symEffect: SymRead, 13042 asm: arm64.AFMOVS, 13043 reg: regInfo{ 13044 inputs: []inputInfo{ 13045 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13046 }, 13047 outputs: []outputInfo{ 13048 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13049 }, 13050 }, 13051 }, 13052 { 13053 name: "FMOVDload", 13054 auxType: auxSymOff, 13055 argLen: 2, 13056 faultOnNilArg0: true, 13057 symEffect: SymRead, 13058 asm: arm64.AFMOVD, 13059 reg: regInfo{ 13060 inputs: []inputInfo{ 13061 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13062 }, 13063 outputs: []outputInfo{ 13064 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13065 }, 13066 }, 13067 }, 13068 { 13069 name: "MOVBstore", 13070 auxType: auxSymOff, 13071 argLen: 3, 13072 faultOnNilArg0: true, 13073 symEffect: SymWrite, 13074 asm: arm64.AMOVB, 13075 reg: regInfo{ 13076 inputs: []inputInfo{ 13077 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13078 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13079 }, 13080 }, 13081 }, 13082 { 13083 name: "MOVHstore", 13084 auxType: auxSymOff, 13085 argLen: 3, 13086 faultOnNilArg0: true, 13087 symEffect: SymWrite, 13088 asm: arm64.AMOVH, 13089 reg: regInfo{ 13090 inputs: []inputInfo{ 13091 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13092 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13093 }, 13094 }, 13095 }, 13096 { 13097 name: "MOVWstore", 13098 auxType: auxSymOff, 13099 argLen: 3, 13100 faultOnNilArg0: true, 13101 symEffect: SymWrite, 13102 asm: arm64.AMOVW, 13103 reg: regInfo{ 13104 inputs: []inputInfo{ 13105 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13106 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13107 }, 13108 }, 13109 }, 13110 { 13111 name: "MOVDstore", 13112 auxType: auxSymOff, 13113 argLen: 3, 13114 faultOnNilArg0: true, 13115 symEffect: SymWrite, 13116 asm: arm64.AMOVD, 13117 reg: regInfo{ 13118 inputs: []inputInfo{ 13119 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13120 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13121 }, 13122 }, 13123 }, 13124 { 13125 name: "STP", 13126 auxType: auxSymOff, 13127 argLen: 4, 13128 faultOnNilArg0: true, 13129 symEffect: SymWrite, 13130 asm: arm64.ASTP, 13131 reg: regInfo{ 13132 inputs: []inputInfo{ 13133 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13134 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13135 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13136 }, 13137 }, 13138 }, 13139 { 13140 name: "FMOVSstore", 13141 auxType: auxSymOff, 13142 argLen: 3, 13143 faultOnNilArg0: true, 13144 symEffect: SymWrite, 13145 asm: arm64.AFMOVS, 13146 reg: regInfo{ 13147 inputs: []inputInfo{ 13148 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13149 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13150 }, 13151 }, 13152 }, 13153 { 13154 name: "FMOVDstore", 13155 auxType: auxSymOff, 13156 argLen: 3, 13157 faultOnNilArg0: true, 13158 symEffect: SymWrite, 13159 asm: arm64.AFMOVD, 13160 reg: regInfo{ 13161 inputs: []inputInfo{ 13162 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13163 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13164 }, 13165 }, 13166 }, 13167 { 13168 name: "MOVBstorezero", 13169 auxType: auxSymOff, 13170 argLen: 2, 13171 faultOnNilArg0: true, 13172 symEffect: SymWrite, 13173 asm: arm64.AMOVB, 13174 reg: regInfo{ 13175 inputs: []inputInfo{ 13176 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13177 }, 13178 }, 13179 }, 13180 { 13181 name: "MOVHstorezero", 13182 auxType: auxSymOff, 13183 argLen: 2, 13184 faultOnNilArg0: true, 13185 symEffect: SymWrite, 13186 asm: arm64.AMOVH, 13187 reg: regInfo{ 13188 inputs: []inputInfo{ 13189 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13190 }, 13191 }, 13192 }, 13193 { 13194 name: "MOVWstorezero", 13195 auxType: auxSymOff, 13196 argLen: 2, 13197 faultOnNilArg0: true, 13198 symEffect: SymWrite, 13199 asm: arm64.AMOVW, 13200 reg: regInfo{ 13201 inputs: []inputInfo{ 13202 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13203 }, 13204 }, 13205 }, 13206 { 13207 name: "MOVDstorezero", 13208 auxType: auxSymOff, 13209 argLen: 2, 13210 faultOnNilArg0: true, 13211 symEffect: SymWrite, 13212 asm: arm64.AMOVD, 13213 reg: regInfo{ 13214 inputs: []inputInfo{ 13215 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13216 }, 13217 }, 13218 }, 13219 { 13220 name: "MOVQstorezero", 13221 auxType: auxSymOff, 13222 argLen: 2, 13223 faultOnNilArg0: true, 13224 symEffect: SymWrite, 13225 asm: arm64.ASTP, 13226 reg: regInfo{ 13227 inputs: []inputInfo{ 13228 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13229 }, 13230 }, 13231 }, 13232 { 13233 name: "MOVBreg", 13234 argLen: 1, 13235 asm: arm64.AMOVB, 13236 reg: regInfo{ 13237 inputs: []inputInfo{ 13238 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13239 }, 13240 outputs: []outputInfo{ 13241 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13242 }, 13243 }, 13244 }, 13245 { 13246 name: "MOVBUreg", 13247 argLen: 1, 13248 asm: arm64.AMOVBU, 13249 reg: regInfo{ 13250 inputs: []inputInfo{ 13251 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13252 }, 13253 outputs: []outputInfo{ 13254 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13255 }, 13256 }, 13257 }, 13258 { 13259 name: "MOVHreg", 13260 argLen: 1, 13261 asm: arm64.AMOVH, 13262 reg: regInfo{ 13263 inputs: []inputInfo{ 13264 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13265 }, 13266 outputs: []outputInfo{ 13267 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13268 }, 13269 }, 13270 }, 13271 { 13272 name: "MOVHUreg", 13273 argLen: 1, 13274 asm: arm64.AMOVHU, 13275 reg: regInfo{ 13276 inputs: []inputInfo{ 13277 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13278 }, 13279 outputs: []outputInfo{ 13280 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13281 }, 13282 }, 13283 }, 13284 { 13285 name: "MOVWreg", 13286 argLen: 1, 13287 asm: arm64.AMOVW, 13288 reg: regInfo{ 13289 inputs: []inputInfo{ 13290 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13291 }, 13292 outputs: []outputInfo{ 13293 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13294 }, 13295 }, 13296 }, 13297 { 13298 name: "MOVWUreg", 13299 argLen: 1, 13300 asm: arm64.AMOVWU, 13301 reg: regInfo{ 13302 inputs: []inputInfo{ 13303 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13304 }, 13305 outputs: []outputInfo{ 13306 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13307 }, 13308 }, 13309 }, 13310 { 13311 name: "MOVDreg", 13312 argLen: 1, 13313 asm: arm64.AMOVD, 13314 reg: regInfo{ 13315 inputs: []inputInfo{ 13316 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13317 }, 13318 outputs: []outputInfo{ 13319 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13320 }, 13321 }, 13322 }, 13323 { 13324 name: "MOVDnop", 13325 argLen: 1, 13326 resultInArg0: true, 13327 reg: regInfo{ 13328 inputs: []inputInfo{ 13329 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13330 }, 13331 outputs: []outputInfo{ 13332 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13333 }, 13334 }, 13335 }, 13336 { 13337 name: "SCVTFWS", 13338 argLen: 1, 13339 asm: arm64.ASCVTFWS, 13340 reg: regInfo{ 13341 inputs: []inputInfo{ 13342 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13343 }, 13344 outputs: []outputInfo{ 13345 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13346 }, 13347 }, 13348 }, 13349 { 13350 name: "SCVTFWD", 13351 argLen: 1, 13352 asm: arm64.ASCVTFWD, 13353 reg: regInfo{ 13354 inputs: []inputInfo{ 13355 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13356 }, 13357 outputs: []outputInfo{ 13358 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13359 }, 13360 }, 13361 }, 13362 { 13363 name: "UCVTFWS", 13364 argLen: 1, 13365 asm: arm64.AUCVTFWS, 13366 reg: regInfo{ 13367 inputs: []inputInfo{ 13368 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13369 }, 13370 outputs: []outputInfo{ 13371 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13372 }, 13373 }, 13374 }, 13375 { 13376 name: "UCVTFWD", 13377 argLen: 1, 13378 asm: arm64.AUCVTFWD, 13379 reg: regInfo{ 13380 inputs: []inputInfo{ 13381 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13382 }, 13383 outputs: []outputInfo{ 13384 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13385 }, 13386 }, 13387 }, 13388 { 13389 name: "SCVTFS", 13390 argLen: 1, 13391 asm: arm64.ASCVTFS, 13392 reg: regInfo{ 13393 inputs: []inputInfo{ 13394 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13395 }, 13396 outputs: []outputInfo{ 13397 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13398 }, 13399 }, 13400 }, 13401 { 13402 name: "SCVTFD", 13403 argLen: 1, 13404 asm: arm64.ASCVTFD, 13405 reg: regInfo{ 13406 inputs: []inputInfo{ 13407 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13408 }, 13409 outputs: []outputInfo{ 13410 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13411 }, 13412 }, 13413 }, 13414 { 13415 name: "UCVTFS", 13416 argLen: 1, 13417 asm: arm64.AUCVTFS, 13418 reg: regInfo{ 13419 inputs: []inputInfo{ 13420 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13421 }, 13422 outputs: []outputInfo{ 13423 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13424 }, 13425 }, 13426 }, 13427 { 13428 name: "UCVTFD", 13429 argLen: 1, 13430 asm: arm64.AUCVTFD, 13431 reg: regInfo{ 13432 inputs: []inputInfo{ 13433 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13434 }, 13435 outputs: []outputInfo{ 13436 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13437 }, 13438 }, 13439 }, 13440 { 13441 name: "FCVTZSSW", 13442 argLen: 1, 13443 asm: arm64.AFCVTZSSW, 13444 reg: regInfo{ 13445 inputs: []inputInfo{ 13446 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13447 }, 13448 outputs: []outputInfo{ 13449 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13450 }, 13451 }, 13452 }, 13453 { 13454 name: "FCVTZSDW", 13455 argLen: 1, 13456 asm: arm64.AFCVTZSDW, 13457 reg: regInfo{ 13458 inputs: []inputInfo{ 13459 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13460 }, 13461 outputs: []outputInfo{ 13462 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13463 }, 13464 }, 13465 }, 13466 { 13467 name: "FCVTZUSW", 13468 argLen: 1, 13469 asm: arm64.AFCVTZUSW, 13470 reg: regInfo{ 13471 inputs: []inputInfo{ 13472 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13473 }, 13474 outputs: []outputInfo{ 13475 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13476 }, 13477 }, 13478 }, 13479 { 13480 name: "FCVTZUDW", 13481 argLen: 1, 13482 asm: arm64.AFCVTZUDW, 13483 reg: regInfo{ 13484 inputs: []inputInfo{ 13485 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13486 }, 13487 outputs: []outputInfo{ 13488 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13489 }, 13490 }, 13491 }, 13492 { 13493 name: "FCVTZSS", 13494 argLen: 1, 13495 asm: arm64.AFCVTZSS, 13496 reg: regInfo{ 13497 inputs: []inputInfo{ 13498 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13499 }, 13500 outputs: []outputInfo{ 13501 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13502 }, 13503 }, 13504 }, 13505 { 13506 name: "FCVTZSD", 13507 argLen: 1, 13508 asm: arm64.AFCVTZSD, 13509 reg: regInfo{ 13510 inputs: []inputInfo{ 13511 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13512 }, 13513 outputs: []outputInfo{ 13514 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13515 }, 13516 }, 13517 }, 13518 { 13519 name: "FCVTZUS", 13520 argLen: 1, 13521 asm: arm64.AFCVTZUS, 13522 reg: regInfo{ 13523 inputs: []inputInfo{ 13524 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13525 }, 13526 outputs: []outputInfo{ 13527 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13528 }, 13529 }, 13530 }, 13531 { 13532 name: "FCVTZUD", 13533 argLen: 1, 13534 asm: arm64.AFCVTZUD, 13535 reg: regInfo{ 13536 inputs: []inputInfo{ 13537 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13538 }, 13539 outputs: []outputInfo{ 13540 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13541 }, 13542 }, 13543 }, 13544 { 13545 name: "FCVTSD", 13546 argLen: 1, 13547 asm: arm64.AFCVTSD, 13548 reg: regInfo{ 13549 inputs: []inputInfo{ 13550 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13551 }, 13552 outputs: []outputInfo{ 13553 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13554 }, 13555 }, 13556 }, 13557 { 13558 name: "FCVTDS", 13559 argLen: 1, 13560 asm: arm64.AFCVTDS, 13561 reg: regInfo{ 13562 inputs: []inputInfo{ 13563 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13564 }, 13565 outputs: []outputInfo{ 13566 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13567 }, 13568 }, 13569 }, 13570 { 13571 name: "CSELULT", 13572 argLen: 3, 13573 asm: arm64.ACSEL, 13574 reg: regInfo{ 13575 inputs: []inputInfo{ 13576 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13577 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13578 }, 13579 outputs: []outputInfo{ 13580 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13581 }, 13582 }, 13583 }, 13584 { 13585 name: "CSELULT0", 13586 argLen: 2, 13587 asm: arm64.ACSEL, 13588 reg: regInfo{ 13589 inputs: []inputInfo{ 13590 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13591 }, 13592 outputs: []outputInfo{ 13593 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13594 }, 13595 }, 13596 }, 13597 { 13598 name: "CALLstatic", 13599 auxType: auxSymOff, 13600 argLen: 1, 13601 clobberFlags: true, 13602 call: true, 13603 symEffect: SymNone, 13604 reg: regInfo{ 13605 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13606 }, 13607 }, 13608 { 13609 name: "CALLclosure", 13610 auxType: auxInt64, 13611 argLen: 3, 13612 clobberFlags: true, 13613 call: true, 13614 reg: regInfo{ 13615 inputs: []inputInfo{ 13616 {1, 67108864}, // R26 13617 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 13618 }, 13619 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13620 }, 13621 }, 13622 { 13623 name: "CALLinter", 13624 auxType: auxInt64, 13625 argLen: 2, 13626 clobberFlags: true, 13627 call: true, 13628 reg: regInfo{ 13629 inputs: []inputInfo{ 13630 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13631 }, 13632 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13633 }, 13634 }, 13635 { 13636 name: "LoweredNilCheck", 13637 argLen: 2, 13638 nilCheck: true, 13639 faultOnNilArg0: true, 13640 reg: regInfo{ 13641 inputs: []inputInfo{ 13642 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13643 }, 13644 }, 13645 }, 13646 { 13647 name: "Equal", 13648 argLen: 1, 13649 reg: regInfo{ 13650 outputs: []outputInfo{ 13651 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13652 }, 13653 }, 13654 }, 13655 { 13656 name: "NotEqual", 13657 argLen: 1, 13658 reg: regInfo{ 13659 outputs: []outputInfo{ 13660 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13661 }, 13662 }, 13663 }, 13664 { 13665 name: "LessThan", 13666 argLen: 1, 13667 reg: regInfo{ 13668 outputs: []outputInfo{ 13669 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13670 }, 13671 }, 13672 }, 13673 { 13674 name: "LessEqual", 13675 argLen: 1, 13676 reg: regInfo{ 13677 outputs: []outputInfo{ 13678 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13679 }, 13680 }, 13681 }, 13682 { 13683 name: "GreaterThan", 13684 argLen: 1, 13685 reg: regInfo{ 13686 outputs: []outputInfo{ 13687 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13688 }, 13689 }, 13690 }, 13691 { 13692 name: "GreaterEqual", 13693 argLen: 1, 13694 reg: regInfo{ 13695 outputs: []outputInfo{ 13696 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13697 }, 13698 }, 13699 }, 13700 { 13701 name: "LessThanU", 13702 argLen: 1, 13703 reg: regInfo{ 13704 outputs: []outputInfo{ 13705 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13706 }, 13707 }, 13708 }, 13709 { 13710 name: "LessEqualU", 13711 argLen: 1, 13712 reg: regInfo{ 13713 outputs: []outputInfo{ 13714 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13715 }, 13716 }, 13717 }, 13718 { 13719 name: "GreaterThanU", 13720 argLen: 1, 13721 reg: regInfo{ 13722 outputs: []outputInfo{ 13723 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13724 }, 13725 }, 13726 }, 13727 { 13728 name: "GreaterEqualU", 13729 argLen: 1, 13730 reg: regInfo{ 13731 outputs: []outputInfo{ 13732 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13733 }, 13734 }, 13735 }, 13736 { 13737 name: "DUFFZERO", 13738 auxType: auxInt64, 13739 argLen: 2, 13740 faultOnNilArg0: true, 13741 reg: regInfo{ 13742 inputs: []inputInfo{ 13743 {0, 65536}, // R16 13744 }, 13745 clobbers: 536936448, // R16 R30 13746 }, 13747 }, 13748 { 13749 name: "LoweredZero", 13750 argLen: 3, 13751 clobberFlags: true, 13752 faultOnNilArg0: true, 13753 reg: regInfo{ 13754 inputs: []inputInfo{ 13755 {0, 65536}, // R16 13756 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13757 }, 13758 clobbers: 65536, // R16 13759 }, 13760 }, 13761 { 13762 name: "DUFFCOPY", 13763 auxType: auxInt64, 13764 argLen: 3, 13765 faultOnNilArg0: true, 13766 faultOnNilArg1: true, 13767 reg: regInfo{ 13768 inputs: []inputInfo{ 13769 {0, 131072}, // R17 13770 {1, 65536}, // R16 13771 }, 13772 clobbers: 537067520, // R16 R17 R30 13773 }, 13774 }, 13775 { 13776 name: "LoweredMove", 13777 argLen: 4, 13778 clobberFlags: true, 13779 faultOnNilArg0: true, 13780 faultOnNilArg1: true, 13781 reg: regInfo{ 13782 inputs: []inputInfo{ 13783 {0, 131072}, // R17 13784 {1, 65536}, // R16 13785 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13786 }, 13787 clobbers: 196608, // R16 R17 13788 }, 13789 }, 13790 { 13791 name: "LoweredGetClosurePtr", 13792 argLen: 0, 13793 reg: regInfo{ 13794 outputs: []outputInfo{ 13795 {0, 67108864}, // R26 13796 }, 13797 }, 13798 }, 13799 { 13800 name: "LoweredGetCallerSP", 13801 argLen: 0, 13802 rematerializeable: true, 13803 reg: regInfo{ 13804 outputs: []outputInfo{ 13805 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13806 }, 13807 }, 13808 }, 13809 { 13810 name: "MOVDconvert", 13811 argLen: 2, 13812 asm: arm64.AMOVD, 13813 reg: regInfo{ 13814 inputs: []inputInfo{ 13815 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13816 }, 13817 outputs: []outputInfo{ 13818 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13819 }, 13820 }, 13821 }, 13822 { 13823 name: "FlagEQ", 13824 argLen: 0, 13825 reg: regInfo{}, 13826 }, 13827 { 13828 name: "FlagLT_ULT", 13829 argLen: 0, 13830 reg: regInfo{}, 13831 }, 13832 { 13833 name: "FlagLT_UGT", 13834 argLen: 0, 13835 reg: regInfo{}, 13836 }, 13837 { 13838 name: "FlagGT_UGT", 13839 argLen: 0, 13840 reg: regInfo{}, 13841 }, 13842 { 13843 name: "FlagGT_ULT", 13844 argLen: 0, 13845 reg: regInfo{}, 13846 }, 13847 { 13848 name: "InvertFlags", 13849 argLen: 1, 13850 reg: regInfo{}, 13851 }, 13852 { 13853 name: "LDAR", 13854 argLen: 2, 13855 faultOnNilArg0: true, 13856 asm: arm64.ALDAR, 13857 reg: regInfo{ 13858 inputs: []inputInfo{ 13859 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13860 }, 13861 outputs: []outputInfo{ 13862 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13863 }, 13864 }, 13865 }, 13866 { 13867 name: "LDARW", 13868 argLen: 2, 13869 faultOnNilArg0: true, 13870 asm: arm64.ALDARW, 13871 reg: regInfo{ 13872 inputs: []inputInfo{ 13873 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13874 }, 13875 outputs: []outputInfo{ 13876 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13877 }, 13878 }, 13879 }, 13880 { 13881 name: "STLR", 13882 argLen: 3, 13883 faultOnNilArg0: true, 13884 hasSideEffects: true, 13885 asm: arm64.ASTLR, 13886 reg: regInfo{ 13887 inputs: []inputInfo{ 13888 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13889 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13890 }, 13891 }, 13892 }, 13893 { 13894 name: "STLRW", 13895 argLen: 3, 13896 faultOnNilArg0: true, 13897 hasSideEffects: true, 13898 asm: arm64.ASTLRW, 13899 reg: regInfo{ 13900 inputs: []inputInfo{ 13901 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13902 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13903 }, 13904 }, 13905 }, 13906 { 13907 name: "LoweredAtomicExchange64", 13908 argLen: 3, 13909 resultNotInArgs: true, 13910 faultOnNilArg0: true, 13911 hasSideEffects: true, 13912 reg: regInfo{ 13913 inputs: []inputInfo{ 13914 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13915 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13916 }, 13917 outputs: []outputInfo{ 13918 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13919 }, 13920 }, 13921 }, 13922 { 13923 name: "LoweredAtomicExchange32", 13924 argLen: 3, 13925 resultNotInArgs: true, 13926 faultOnNilArg0: true, 13927 hasSideEffects: true, 13928 reg: regInfo{ 13929 inputs: []inputInfo{ 13930 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13931 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13932 }, 13933 outputs: []outputInfo{ 13934 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13935 }, 13936 }, 13937 }, 13938 { 13939 name: "LoweredAtomicAdd64", 13940 argLen: 3, 13941 resultNotInArgs: true, 13942 faultOnNilArg0: true, 13943 hasSideEffects: true, 13944 reg: regInfo{ 13945 inputs: []inputInfo{ 13946 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13947 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13948 }, 13949 outputs: []outputInfo{ 13950 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13951 }, 13952 }, 13953 }, 13954 { 13955 name: "LoweredAtomicAdd32", 13956 argLen: 3, 13957 resultNotInArgs: true, 13958 faultOnNilArg0: true, 13959 hasSideEffects: true, 13960 reg: regInfo{ 13961 inputs: []inputInfo{ 13962 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13963 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13964 }, 13965 outputs: []outputInfo{ 13966 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13967 }, 13968 }, 13969 }, 13970 { 13971 name: "LoweredAtomicCas64", 13972 argLen: 4, 13973 resultNotInArgs: true, 13974 clobberFlags: true, 13975 faultOnNilArg0: true, 13976 hasSideEffects: true, 13977 reg: regInfo{ 13978 inputs: []inputInfo{ 13979 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13980 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13981 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13982 }, 13983 outputs: []outputInfo{ 13984 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13985 }, 13986 }, 13987 }, 13988 { 13989 name: "LoweredAtomicCas32", 13990 argLen: 4, 13991 resultNotInArgs: true, 13992 clobberFlags: true, 13993 faultOnNilArg0: true, 13994 hasSideEffects: true, 13995 reg: regInfo{ 13996 inputs: []inputInfo{ 13997 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13998 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13999 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14000 }, 14001 outputs: []outputInfo{ 14002 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14003 }, 14004 }, 14005 }, 14006 { 14007 name: "LoweredAtomicAnd8", 14008 argLen: 3, 14009 faultOnNilArg0: true, 14010 hasSideEffects: true, 14011 asm: arm64.AAND, 14012 reg: regInfo{ 14013 inputs: []inputInfo{ 14014 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14015 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14016 }, 14017 }, 14018 }, 14019 { 14020 name: "LoweredAtomicOr8", 14021 argLen: 3, 14022 faultOnNilArg0: true, 14023 hasSideEffects: true, 14024 asm: arm64.AORR, 14025 reg: regInfo{ 14026 inputs: []inputInfo{ 14027 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14028 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14029 }, 14030 }, 14031 }, 14032 14033 { 14034 name: "ADD", 14035 argLen: 2, 14036 commutative: true, 14037 asm: mips.AADDU, 14038 reg: regInfo{ 14039 inputs: []inputInfo{ 14040 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14041 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14042 }, 14043 outputs: []outputInfo{ 14044 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14045 }, 14046 }, 14047 }, 14048 { 14049 name: "ADDconst", 14050 auxType: auxInt32, 14051 argLen: 1, 14052 asm: mips.AADDU, 14053 reg: regInfo{ 14054 inputs: []inputInfo{ 14055 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 14056 }, 14057 outputs: []outputInfo{ 14058 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14059 }, 14060 }, 14061 }, 14062 { 14063 name: "SUB", 14064 argLen: 2, 14065 asm: mips.ASUBU, 14066 reg: regInfo{ 14067 inputs: []inputInfo{ 14068 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14069 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14070 }, 14071 outputs: []outputInfo{ 14072 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14073 }, 14074 }, 14075 }, 14076 { 14077 name: "SUBconst", 14078 auxType: auxInt32, 14079 argLen: 1, 14080 asm: mips.ASUBU, 14081 reg: regInfo{ 14082 inputs: []inputInfo{ 14083 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14084 }, 14085 outputs: []outputInfo{ 14086 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14087 }, 14088 }, 14089 }, 14090 { 14091 name: "MUL", 14092 argLen: 2, 14093 commutative: true, 14094 asm: mips.AMUL, 14095 reg: regInfo{ 14096 inputs: []inputInfo{ 14097 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14098 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14099 }, 14100 clobbers: 105553116266496, // HI LO 14101 outputs: []outputInfo{ 14102 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14103 }, 14104 }, 14105 }, 14106 { 14107 name: "MULT", 14108 argLen: 2, 14109 commutative: true, 14110 asm: mips.AMUL, 14111 reg: regInfo{ 14112 inputs: []inputInfo{ 14113 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14114 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14115 }, 14116 outputs: []outputInfo{ 14117 {0, 35184372088832}, // HI 14118 {1, 70368744177664}, // LO 14119 }, 14120 }, 14121 }, 14122 { 14123 name: "MULTU", 14124 argLen: 2, 14125 commutative: true, 14126 asm: mips.AMULU, 14127 reg: regInfo{ 14128 inputs: []inputInfo{ 14129 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14130 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14131 }, 14132 outputs: []outputInfo{ 14133 {0, 35184372088832}, // HI 14134 {1, 70368744177664}, // LO 14135 }, 14136 }, 14137 }, 14138 { 14139 name: "DIV", 14140 argLen: 2, 14141 asm: mips.ADIV, 14142 reg: regInfo{ 14143 inputs: []inputInfo{ 14144 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14145 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14146 }, 14147 outputs: []outputInfo{ 14148 {0, 35184372088832}, // HI 14149 {1, 70368744177664}, // LO 14150 }, 14151 }, 14152 }, 14153 { 14154 name: "DIVU", 14155 argLen: 2, 14156 asm: mips.ADIVU, 14157 reg: regInfo{ 14158 inputs: []inputInfo{ 14159 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14160 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14161 }, 14162 outputs: []outputInfo{ 14163 {0, 35184372088832}, // HI 14164 {1, 70368744177664}, // LO 14165 }, 14166 }, 14167 }, 14168 { 14169 name: "ADDF", 14170 argLen: 2, 14171 commutative: true, 14172 asm: mips.AADDF, 14173 reg: regInfo{ 14174 inputs: []inputInfo{ 14175 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14176 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14177 }, 14178 outputs: []outputInfo{ 14179 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14180 }, 14181 }, 14182 }, 14183 { 14184 name: "ADDD", 14185 argLen: 2, 14186 commutative: true, 14187 asm: mips.AADDD, 14188 reg: regInfo{ 14189 inputs: []inputInfo{ 14190 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14191 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14192 }, 14193 outputs: []outputInfo{ 14194 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14195 }, 14196 }, 14197 }, 14198 { 14199 name: "SUBF", 14200 argLen: 2, 14201 asm: mips.ASUBF, 14202 reg: regInfo{ 14203 inputs: []inputInfo{ 14204 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14205 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14206 }, 14207 outputs: []outputInfo{ 14208 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14209 }, 14210 }, 14211 }, 14212 { 14213 name: "SUBD", 14214 argLen: 2, 14215 asm: mips.ASUBD, 14216 reg: regInfo{ 14217 inputs: []inputInfo{ 14218 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14219 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14220 }, 14221 outputs: []outputInfo{ 14222 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14223 }, 14224 }, 14225 }, 14226 { 14227 name: "MULF", 14228 argLen: 2, 14229 commutative: true, 14230 asm: mips.AMULF, 14231 reg: regInfo{ 14232 inputs: []inputInfo{ 14233 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14234 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14235 }, 14236 outputs: []outputInfo{ 14237 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14238 }, 14239 }, 14240 }, 14241 { 14242 name: "MULD", 14243 argLen: 2, 14244 commutative: true, 14245 asm: mips.AMULD, 14246 reg: regInfo{ 14247 inputs: []inputInfo{ 14248 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14249 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14250 }, 14251 outputs: []outputInfo{ 14252 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14253 }, 14254 }, 14255 }, 14256 { 14257 name: "DIVF", 14258 argLen: 2, 14259 asm: mips.ADIVF, 14260 reg: regInfo{ 14261 inputs: []inputInfo{ 14262 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14263 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14264 }, 14265 outputs: []outputInfo{ 14266 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14267 }, 14268 }, 14269 }, 14270 { 14271 name: "DIVD", 14272 argLen: 2, 14273 asm: mips.ADIVD, 14274 reg: regInfo{ 14275 inputs: []inputInfo{ 14276 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14277 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14278 }, 14279 outputs: []outputInfo{ 14280 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14281 }, 14282 }, 14283 }, 14284 { 14285 name: "AND", 14286 argLen: 2, 14287 commutative: true, 14288 asm: mips.AAND, 14289 reg: regInfo{ 14290 inputs: []inputInfo{ 14291 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14292 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14293 }, 14294 outputs: []outputInfo{ 14295 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14296 }, 14297 }, 14298 }, 14299 { 14300 name: "ANDconst", 14301 auxType: auxInt32, 14302 argLen: 1, 14303 asm: mips.AAND, 14304 reg: regInfo{ 14305 inputs: []inputInfo{ 14306 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14307 }, 14308 outputs: []outputInfo{ 14309 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14310 }, 14311 }, 14312 }, 14313 { 14314 name: "OR", 14315 argLen: 2, 14316 commutative: true, 14317 asm: mips.AOR, 14318 reg: regInfo{ 14319 inputs: []inputInfo{ 14320 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14321 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14322 }, 14323 outputs: []outputInfo{ 14324 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14325 }, 14326 }, 14327 }, 14328 { 14329 name: "ORconst", 14330 auxType: auxInt32, 14331 argLen: 1, 14332 asm: mips.AOR, 14333 reg: regInfo{ 14334 inputs: []inputInfo{ 14335 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14336 }, 14337 outputs: []outputInfo{ 14338 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14339 }, 14340 }, 14341 }, 14342 { 14343 name: "XOR", 14344 argLen: 2, 14345 commutative: true, 14346 asm: mips.AXOR, 14347 reg: regInfo{ 14348 inputs: []inputInfo{ 14349 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14350 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14351 }, 14352 outputs: []outputInfo{ 14353 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14354 }, 14355 }, 14356 }, 14357 { 14358 name: "XORconst", 14359 auxType: auxInt32, 14360 argLen: 1, 14361 asm: mips.AXOR, 14362 reg: regInfo{ 14363 inputs: []inputInfo{ 14364 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14365 }, 14366 outputs: []outputInfo{ 14367 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14368 }, 14369 }, 14370 }, 14371 { 14372 name: "NOR", 14373 argLen: 2, 14374 commutative: true, 14375 asm: mips.ANOR, 14376 reg: regInfo{ 14377 inputs: []inputInfo{ 14378 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14379 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14380 }, 14381 outputs: []outputInfo{ 14382 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14383 }, 14384 }, 14385 }, 14386 { 14387 name: "NORconst", 14388 auxType: auxInt32, 14389 argLen: 1, 14390 asm: mips.ANOR, 14391 reg: regInfo{ 14392 inputs: []inputInfo{ 14393 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14394 }, 14395 outputs: []outputInfo{ 14396 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14397 }, 14398 }, 14399 }, 14400 { 14401 name: "NEG", 14402 argLen: 1, 14403 reg: regInfo{ 14404 inputs: []inputInfo{ 14405 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14406 }, 14407 outputs: []outputInfo{ 14408 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14409 }, 14410 }, 14411 }, 14412 { 14413 name: "NEGF", 14414 argLen: 1, 14415 asm: mips.ANEGF, 14416 reg: regInfo{ 14417 inputs: []inputInfo{ 14418 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14419 }, 14420 outputs: []outputInfo{ 14421 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14422 }, 14423 }, 14424 }, 14425 { 14426 name: "NEGD", 14427 argLen: 1, 14428 asm: mips.ANEGD, 14429 reg: regInfo{ 14430 inputs: []inputInfo{ 14431 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14432 }, 14433 outputs: []outputInfo{ 14434 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14435 }, 14436 }, 14437 }, 14438 { 14439 name: "SQRTD", 14440 argLen: 1, 14441 asm: mips.ASQRTD, 14442 reg: regInfo{ 14443 inputs: []inputInfo{ 14444 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14445 }, 14446 outputs: []outputInfo{ 14447 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14448 }, 14449 }, 14450 }, 14451 { 14452 name: "SLL", 14453 argLen: 2, 14454 asm: mips.ASLL, 14455 reg: regInfo{ 14456 inputs: []inputInfo{ 14457 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14458 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14459 }, 14460 outputs: []outputInfo{ 14461 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14462 }, 14463 }, 14464 }, 14465 { 14466 name: "SLLconst", 14467 auxType: auxInt32, 14468 argLen: 1, 14469 asm: mips.ASLL, 14470 reg: regInfo{ 14471 inputs: []inputInfo{ 14472 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14473 }, 14474 outputs: []outputInfo{ 14475 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14476 }, 14477 }, 14478 }, 14479 { 14480 name: "SRL", 14481 argLen: 2, 14482 asm: mips.ASRL, 14483 reg: regInfo{ 14484 inputs: []inputInfo{ 14485 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14486 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14487 }, 14488 outputs: []outputInfo{ 14489 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14490 }, 14491 }, 14492 }, 14493 { 14494 name: "SRLconst", 14495 auxType: auxInt32, 14496 argLen: 1, 14497 asm: mips.ASRL, 14498 reg: regInfo{ 14499 inputs: []inputInfo{ 14500 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14501 }, 14502 outputs: []outputInfo{ 14503 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14504 }, 14505 }, 14506 }, 14507 { 14508 name: "SRA", 14509 argLen: 2, 14510 asm: mips.ASRA, 14511 reg: regInfo{ 14512 inputs: []inputInfo{ 14513 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14514 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14515 }, 14516 outputs: []outputInfo{ 14517 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14518 }, 14519 }, 14520 }, 14521 { 14522 name: "SRAconst", 14523 auxType: auxInt32, 14524 argLen: 1, 14525 asm: mips.ASRA, 14526 reg: regInfo{ 14527 inputs: []inputInfo{ 14528 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14529 }, 14530 outputs: []outputInfo{ 14531 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14532 }, 14533 }, 14534 }, 14535 { 14536 name: "CLZ", 14537 argLen: 1, 14538 asm: mips.ACLZ, 14539 reg: regInfo{ 14540 inputs: []inputInfo{ 14541 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14542 }, 14543 outputs: []outputInfo{ 14544 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14545 }, 14546 }, 14547 }, 14548 { 14549 name: "SGT", 14550 argLen: 2, 14551 asm: mips.ASGT, 14552 reg: regInfo{ 14553 inputs: []inputInfo{ 14554 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14555 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14556 }, 14557 outputs: []outputInfo{ 14558 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14559 }, 14560 }, 14561 }, 14562 { 14563 name: "SGTconst", 14564 auxType: auxInt32, 14565 argLen: 1, 14566 asm: mips.ASGT, 14567 reg: regInfo{ 14568 inputs: []inputInfo{ 14569 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14570 }, 14571 outputs: []outputInfo{ 14572 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14573 }, 14574 }, 14575 }, 14576 { 14577 name: "SGTzero", 14578 argLen: 1, 14579 asm: mips.ASGT, 14580 reg: regInfo{ 14581 inputs: []inputInfo{ 14582 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14583 }, 14584 outputs: []outputInfo{ 14585 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14586 }, 14587 }, 14588 }, 14589 { 14590 name: "SGTU", 14591 argLen: 2, 14592 asm: mips.ASGTU, 14593 reg: regInfo{ 14594 inputs: []inputInfo{ 14595 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14596 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14597 }, 14598 outputs: []outputInfo{ 14599 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14600 }, 14601 }, 14602 }, 14603 { 14604 name: "SGTUconst", 14605 auxType: auxInt32, 14606 argLen: 1, 14607 asm: mips.ASGTU, 14608 reg: regInfo{ 14609 inputs: []inputInfo{ 14610 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14611 }, 14612 outputs: []outputInfo{ 14613 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14614 }, 14615 }, 14616 }, 14617 { 14618 name: "SGTUzero", 14619 argLen: 1, 14620 asm: mips.ASGTU, 14621 reg: regInfo{ 14622 inputs: []inputInfo{ 14623 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14624 }, 14625 outputs: []outputInfo{ 14626 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14627 }, 14628 }, 14629 }, 14630 { 14631 name: "CMPEQF", 14632 argLen: 2, 14633 asm: mips.ACMPEQF, 14634 reg: regInfo{ 14635 inputs: []inputInfo{ 14636 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14637 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14638 }, 14639 }, 14640 }, 14641 { 14642 name: "CMPEQD", 14643 argLen: 2, 14644 asm: mips.ACMPEQD, 14645 reg: regInfo{ 14646 inputs: []inputInfo{ 14647 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14648 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14649 }, 14650 }, 14651 }, 14652 { 14653 name: "CMPGEF", 14654 argLen: 2, 14655 asm: mips.ACMPGEF, 14656 reg: regInfo{ 14657 inputs: []inputInfo{ 14658 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14659 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14660 }, 14661 }, 14662 }, 14663 { 14664 name: "CMPGED", 14665 argLen: 2, 14666 asm: mips.ACMPGED, 14667 reg: regInfo{ 14668 inputs: []inputInfo{ 14669 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14670 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14671 }, 14672 }, 14673 }, 14674 { 14675 name: "CMPGTF", 14676 argLen: 2, 14677 asm: mips.ACMPGTF, 14678 reg: regInfo{ 14679 inputs: []inputInfo{ 14680 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14681 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14682 }, 14683 }, 14684 }, 14685 { 14686 name: "CMPGTD", 14687 argLen: 2, 14688 asm: mips.ACMPGTD, 14689 reg: regInfo{ 14690 inputs: []inputInfo{ 14691 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14692 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14693 }, 14694 }, 14695 }, 14696 { 14697 name: "MOVWconst", 14698 auxType: auxInt32, 14699 argLen: 0, 14700 rematerializeable: true, 14701 asm: mips.AMOVW, 14702 reg: regInfo{ 14703 outputs: []outputInfo{ 14704 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14705 }, 14706 }, 14707 }, 14708 { 14709 name: "MOVFconst", 14710 auxType: auxFloat32, 14711 argLen: 0, 14712 rematerializeable: true, 14713 asm: mips.AMOVF, 14714 reg: regInfo{ 14715 outputs: []outputInfo{ 14716 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14717 }, 14718 }, 14719 }, 14720 { 14721 name: "MOVDconst", 14722 auxType: auxFloat64, 14723 argLen: 0, 14724 rematerializeable: true, 14725 asm: mips.AMOVD, 14726 reg: regInfo{ 14727 outputs: []outputInfo{ 14728 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14729 }, 14730 }, 14731 }, 14732 { 14733 name: "MOVWaddr", 14734 auxType: auxSymOff, 14735 argLen: 1, 14736 rematerializeable: true, 14737 symEffect: SymAddr, 14738 asm: mips.AMOVW, 14739 reg: regInfo{ 14740 inputs: []inputInfo{ 14741 {0, 140737555464192}, // SP SB 14742 }, 14743 outputs: []outputInfo{ 14744 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14745 }, 14746 }, 14747 }, 14748 { 14749 name: "MOVBload", 14750 auxType: auxSymOff, 14751 argLen: 2, 14752 faultOnNilArg0: true, 14753 symEffect: SymRead, 14754 asm: mips.AMOVB, 14755 reg: regInfo{ 14756 inputs: []inputInfo{ 14757 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14758 }, 14759 outputs: []outputInfo{ 14760 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14761 }, 14762 }, 14763 }, 14764 { 14765 name: "MOVBUload", 14766 auxType: auxSymOff, 14767 argLen: 2, 14768 faultOnNilArg0: true, 14769 symEffect: SymRead, 14770 asm: mips.AMOVBU, 14771 reg: regInfo{ 14772 inputs: []inputInfo{ 14773 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14774 }, 14775 outputs: []outputInfo{ 14776 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14777 }, 14778 }, 14779 }, 14780 { 14781 name: "MOVHload", 14782 auxType: auxSymOff, 14783 argLen: 2, 14784 faultOnNilArg0: true, 14785 symEffect: SymRead, 14786 asm: mips.AMOVH, 14787 reg: regInfo{ 14788 inputs: []inputInfo{ 14789 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14790 }, 14791 outputs: []outputInfo{ 14792 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14793 }, 14794 }, 14795 }, 14796 { 14797 name: "MOVHUload", 14798 auxType: auxSymOff, 14799 argLen: 2, 14800 faultOnNilArg0: true, 14801 symEffect: SymRead, 14802 asm: mips.AMOVHU, 14803 reg: regInfo{ 14804 inputs: []inputInfo{ 14805 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14806 }, 14807 outputs: []outputInfo{ 14808 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14809 }, 14810 }, 14811 }, 14812 { 14813 name: "MOVWload", 14814 auxType: auxSymOff, 14815 argLen: 2, 14816 faultOnNilArg0: true, 14817 symEffect: SymRead, 14818 asm: mips.AMOVW, 14819 reg: regInfo{ 14820 inputs: []inputInfo{ 14821 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14822 }, 14823 outputs: []outputInfo{ 14824 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14825 }, 14826 }, 14827 }, 14828 { 14829 name: "MOVFload", 14830 auxType: auxSymOff, 14831 argLen: 2, 14832 faultOnNilArg0: true, 14833 symEffect: SymRead, 14834 asm: mips.AMOVF, 14835 reg: regInfo{ 14836 inputs: []inputInfo{ 14837 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14838 }, 14839 outputs: []outputInfo{ 14840 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14841 }, 14842 }, 14843 }, 14844 { 14845 name: "MOVDload", 14846 auxType: auxSymOff, 14847 argLen: 2, 14848 faultOnNilArg0: true, 14849 symEffect: SymRead, 14850 asm: mips.AMOVD, 14851 reg: regInfo{ 14852 inputs: []inputInfo{ 14853 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14854 }, 14855 outputs: []outputInfo{ 14856 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14857 }, 14858 }, 14859 }, 14860 { 14861 name: "MOVBstore", 14862 auxType: auxSymOff, 14863 argLen: 3, 14864 faultOnNilArg0: true, 14865 symEffect: SymWrite, 14866 asm: mips.AMOVB, 14867 reg: regInfo{ 14868 inputs: []inputInfo{ 14869 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14870 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14871 }, 14872 }, 14873 }, 14874 { 14875 name: "MOVHstore", 14876 auxType: auxSymOff, 14877 argLen: 3, 14878 faultOnNilArg0: true, 14879 symEffect: SymWrite, 14880 asm: mips.AMOVH, 14881 reg: regInfo{ 14882 inputs: []inputInfo{ 14883 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14884 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14885 }, 14886 }, 14887 }, 14888 { 14889 name: "MOVWstore", 14890 auxType: auxSymOff, 14891 argLen: 3, 14892 faultOnNilArg0: true, 14893 symEffect: SymWrite, 14894 asm: mips.AMOVW, 14895 reg: regInfo{ 14896 inputs: []inputInfo{ 14897 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14898 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14899 }, 14900 }, 14901 }, 14902 { 14903 name: "MOVFstore", 14904 auxType: auxSymOff, 14905 argLen: 3, 14906 faultOnNilArg0: true, 14907 symEffect: SymWrite, 14908 asm: mips.AMOVF, 14909 reg: regInfo{ 14910 inputs: []inputInfo{ 14911 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14912 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14913 }, 14914 }, 14915 }, 14916 { 14917 name: "MOVDstore", 14918 auxType: auxSymOff, 14919 argLen: 3, 14920 faultOnNilArg0: true, 14921 symEffect: SymWrite, 14922 asm: mips.AMOVD, 14923 reg: regInfo{ 14924 inputs: []inputInfo{ 14925 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14926 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14927 }, 14928 }, 14929 }, 14930 { 14931 name: "MOVBstorezero", 14932 auxType: auxSymOff, 14933 argLen: 2, 14934 faultOnNilArg0: true, 14935 symEffect: SymWrite, 14936 asm: mips.AMOVB, 14937 reg: regInfo{ 14938 inputs: []inputInfo{ 14939 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14940 }, 14941 }, 14942 }, 14943 { 14944 name: "MOVHstorezero", 14945 auxType: auxSymOff, 14946 argLen: 2, 14947 faultOnNilArg0: true, 14948 symEffect: SymWrite, 14949 asm: mips.AMOVH, 14950 reg: regInfo{ 14951 inputs: []inputInfo{ 14952 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14953 }, 14954 }, 14955 }, 14956 { 14957 name: "MOVWstorezero", 14958 auxType: auxSymOff, 14959 argLen: 2, 14960 faultOnNilArg0: true, 14961 symEffect: SymWrite, 14962 asm: mips.AMOVW, 14963 reg: regInfo{ 14964 inputs: []inputInfo{ 14965 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14966 }, 14967 }, 14968 }, 14969 { 14970 name: "MOVBreg", 14971 argLen: 1, 14972 asm: mips.AMOVB, 14973 reg: regInfo{ 14974 inputs: []inputInfo{ 14975 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14976 }, 14977 outputs: []outputInfo{ 14978 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14979 }, 14980 }, 14981 }, 14982 { 14983 name: "MOVBUreg", 14984 argLen: 1, 14985 asm: mips.AMOVBU, 14986 reg: regInfo{ 14987 inputs: []inputInfo{ 14988 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14989 }, 14990 outputs: []outputInfo{ 14991 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14992 }, 14993 }, 14994 }, 14995 { 14996 name: "MOVHreg", 14997 argLen: 1, 14998 asm: mips.AMOVH, 14999 reg: regInfo{ 15000 inputs: []inputInfo{ 15001 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15002 }, 15003 outputs: []outputInfo{ 15004 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15005 }, 15006 }, 15007 }, 15008 { 15009 name: "MOVHUreg", 15010 argLen: 1, 15011 asm: mips.AMOVHU, 15012 reg: regInfo{ 15013 inputs: []inputInfo{ 15014 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15015 }, 15016 outputs: []outputInfo{ 15017 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15018 }, 15019 }, 15020 }, 15021 { 15022 name: "MOVWreg", 15023 argLen: 1, 15024 asm: mips.AMOVW, 15025 reg: regInfo{ 15026 inputs: []inputInfo{ 15027 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15028 }, 15029 outputs: []outputInfo{ 15030 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15031 }, 15032 }, 15033 }, 15034 { 15035 name: "MOVWnop", 15036 argLen: 1, 15037 resultInArg0: true, 15038 reg: regInfo{ 15039 inputs: []inputInfo{ 15040 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15041 }, 15042 outputs: []outputInfo{ 15043 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15044 }, 15045 }, 15046 }, 15047 { 15048 name: "CMOVZ", 15049 argLen: 3, 15050 resultInArg0: true, 15051 asm: mips.ACMOVZ, 15052 reg: regInfo{ 15053 inputs: []inputInfo{ 15054 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15055 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15056 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15057 }, 15058 outputs: []outputInfo{ 15059 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15060 }, 15061 }, 15062 }, 15063 { 15064 name: "CMOVZzero", 15065 argLen: 2, 15066 resultInArg0: true, 15067 asm: mips.ACMOVZ, 15068 reg: regInfo{ 15069 inputs: []inputInfo{ 15070 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15071 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15072 }, 15073 outputs: []outputInfo{ 15074 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15075 }, 15076 }, 15077 }, 15078 { 15079 name: "MOVWF", 15080 argLen: 1, 15081 asm: mips.AMOVWF, 15082 reg: regInfo{ 15083 inputs: []inputInfo{ 15084 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15085 }, 15086 outputs: []outputInfo{ 15087 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15088 }, 15089 }, 15090 }, 15091 { 15092 name: "MOVWD", 15093 argLen: 1, 15094 asm: mips.AMOVWD, 15095 reg: regInfo{ 15096 inputs: []inputInfo{ 15097 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15098 }, 15099 outputs: []outputInfo{ 15100 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15101 }, 15102 }, 15103 }, 15104 { 15105 name: "TRUNCFW", 15106 argLen: 1, 15107 asm: mips.ATRUNCFW, 15108 reg: regInfo{ 15109 inputs: []inputInfo{ 15110 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15111 }, 15112 outputs: []outputInfo{ 15113 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15114 }, 15115 }, 15116 }, 15117 { 15118 name: "TRUNCDW", 15119 argLen: 1, 15120 asm: mips.ATRUNCDW, 15121 reg: regInfo{ 15122 inputs: []inputInfo{ 15123 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15124 }, 15125 outputs: []outputInfo{ 15126 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15127 }, 15128 }, 15129 }, 15130 { 15131 name: "MOVFD", 15132 argLen: 1, 15133 asm: mips.AMOVFD, 15134 reg: regInfo{ 15135 inputs: []inputInfo{ 15136 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15137 }, 15138 outputs: []outputInfo{ 15139 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15140 }, 15141 }, 15142 }, 15143 { 15144 name: "MOVDF", 15145 argLen: 1, 15146 asm: mips.AMOVDF, 15147 reg: regInfo{ 15148 inputs: []inputInfo{ 15149 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15150 }, 15151 outputs: []outputInfo{ 15152 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15153 }, 15154 }, 15155 }, 15156 { 15157 name: "CALLstatic", 15158 auxType: auxSymOff, 15159 argLen: 1, 15160 clobberFlags: true, 15161 call: true, 15162 symEffect: SymNone, 15163 reg: regInfo{ 15164 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 15165 }, 15166 }, 15167 { 15168 name: "CALLclosure", 15169 auxType: auxInt64, 15170 argLen: 3, 15171 clobberFlags: true, 15172 call: true, 15173 reg: regInfo{ 15174 inputs: []inputInfo{ 15175 {1, 4194304}, // R22 15176 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 15177 }, 15178 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 15179 }, 15180 }, 15181 { 15182 name: "CALLinter", 15183 auxType: auxInt64, 15184 argLen: 2, 15185 clobberFlags: true, 15186 call: true, 15187 reg: regInfo{ 15188 inputs: []inputInfo{ 15189 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15190 }, 15191 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 15192 }, 15193 }, 15194 { 15195 name: "LoweredAtomicLoad", 15196 argLen: 2, 15197 faultOnNilArg0: true, 15198 reg: regInfo{ 15199 inputs: []inputInfo{ 15200 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15201 }, 15202 outputs: []outputInfo{ 15203 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15204 }, 15205 }, 15206 }, 15207 { 15208 name: "LoweredAtomicStore", 15209 argLen: 3, 15210 faultOnNilArg0: true, 15211 hasSideEffects: true, 15212 reg: regInfo{ 15213 inputs: []inputInfo{ 15214 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15215 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15216 }, 15217 }, 15218 }, 15219 { 15220 name: "LoweredAtomicStorezero", 15221 argLen: 2, 15222 faultOnNilArg0: true, 15223 hasSideEffects: true, 15224 reg: regInfo{ 15225 inputs: []inputInfo{ 15226 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15227 }, 15228 }, 15229 }, 15230 { 15231 name: "LoweredAtomicExchange", 15232 argLen: 3, 15233 resultNotInArgs: true, 15234 faultOnNilArg0: true, 15235 hasSideEffects: true, 15236 reg: regInfo{ 15237 inputs: []inputInfo{ 15238 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15239 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15240 }, 15241 outputs: []outputInfo{ 15242 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15243 }, 15244 }, 15245 }, 15246 { 15247 name: "LoweredAtomicAdd", 15248 argLen: 3, 15249 resultNotInArgs: true, 15250 faultOnNilArg0: true, 15251 hasSideEffects: true, 15252 reg: regInfo{ 15253 inputs: []inputInfo{ 15254 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15255 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15256 }, 15257 outputs: []outputInfo{ 15258 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15259 }, 15260 }, 15261 }, 15262 { 15263 name: "LoweredAtomicAddconst", 15264 auxType: auxInt32, 15265 argLen: 2, 15266 resultNotInArgs: true, 15267 faultOnNilArg0: true, 15268 hasSideEffects: true, 15269 reg: regInfo{ 15270 inputs: []inputInfo{ 15271 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15272 }, 15273 outputs: []outputInfo{ 15274 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15275 }, 15276 }, 15277 }, 15278 { 15279 name: "LoweredAtomicCas", 15280 argLen: 4, 15281 resultNotInArgs: true, 15282 faultOnNilArg0: true, 15283 hasSideEffects: true, 15284 reg: regInfo{ 15285 inputs: []inputInfo{ 15286 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15287 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15288 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15289 }, 15290 outputs: []outputInfo{ 15291 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15292 }, 15293 }, 15294 }, 15295 { 15296 name: "LoweredAtomicAnd", 15297 argLen: 3, 15298 faultOnNilArg0: true, 15299 hasSideEffects: true, 15300 asm: mips.AAND, 15301 reg: regInfo{ 15302 inputs: []inputInfo{ 15303 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15304 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15305 }, 15306 }, 15307 }, 15308 { 15309 name: "LoweredAtomicOr", 15310 argLen: 3, 15311 faultOnNilArg0: true, 15312 hasSideEffects: true, 15313 asm: mips.AOR, 15314 reg: regInfo{ 15315 inputs: []inputInfo{ 15316 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15317 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15318 }, 15319 }, 15320 }, 15321 { 15322 name: "LoweredZero", 15323 auxType: auxInt32, 15324 argLen: 3, 15325 faultOnNilArg0: true, 15326 reg: regInfo{ 15327 inputs: []inputInfo{ 15328 {0, 2}, // R1 15329 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15330 }, 15331 clobbers: 2, // R1 15332 }, 15333 }, 15334 { 15335 name: "LoweredMove", 15336 auxType: auxInt32, 15337 argLen: 4, 15338 faultOnNilArg0: true, 15339 faultOnNilArg1: true, 15340 reg: regInfo{ 15341 inputs: []inputInfo{ 15342 {0, 4}, // R2 15343 {1, 2}, // R1 15344 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15345 }, 15346 clobbers: 6, // R1 R2 15347 }, 15348 }, 15349 { 15350 name: "LoweredNilCheck", 15351 argLen: 2, 15352 nilCheck: true, 15353 faultOnNilArg0: true, 15354 reg: regInfo{ 15355 inputs: []inputInfo{ 15356 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15357 }, 15358 }, 15359 }, 15360 { 15361 name: "FPFlagTrue", 15362 argLen: 1, 15363 reg: regInfo{ 15364 outputs: []outputInfo{ 15365 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15366 }, 15367 }, 15368 }, 15369 { 15370 name: "FPFlagFalse", 15371 argLen: 1, 15372 reg: regInfo{ 15373 outputs: []outputInfo{ 15374 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15375 }, 15376 }, 15377 }, 15378 { 15379 name: "LoweredGetClosurePtr", 15380 argLen: 0, 15381 reg: regInfo{ 15382 outputs: []outputInfo{ 15383 {0, 4194304}, // R22 15384 }, 15385 }, 15386 }, 15387 { 15388 name: "LoweredGetCallerSP", 15389 argLen: 0, 15390 rematerializeable: true, 15391 reg: regInfo{ 15392 outputs: []outputInfo{ 15393 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15394 }, 15395 }, 15396 }, 15397 { 15398 name: "MOVWconvert", 15399 argLen: 2, 15400 asm: mips.AMOVW, 15401 reg: regInfo{ 15402 inputs: []inputInfo{ 15403 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15404 }, 15405 outputs: []outputInfo{ 15406 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15407 }, 15408 }, 15409 }, 15410 15411 { 15412 name: "ADDV", 15413 argLen: 2, 15414 commutative: true, 15415 asm: mips.AADDVU, 15416 reg: regInfo{ 15417 inputs: []inputInfo{ 15418 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15419 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15420 }, 15421 outputs: []outputInfo{ 15422 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15423 }, 15424 }, 15425 }, 15426 { 15427 name: "ADDVconst", 15428 auxType: auxInt64, 15429 argLen: 1, 15430 asm: mips.AADDVU, 15431 reg: regInfo{ 15432 inputs: []inputInfo{ 15433 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 15434 }, 15435 outputs: []outputInfo{ 15436 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15437 }, 15438 }, 15439 }, 15440 { 15441 name: "SUBV", 15442 argLen: 2, 15443 asm: mips.ASUBVU, 15444 reg: regInfo{ 15445 inputs: []inputInfo{ 15446 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15447 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15448 }, 15449 outputs: []outputInfo{ 15450 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15451 }, 15452 }, 15453 }, 15454 { 15455 name: "SUBVconst", 15456 auxType: auxInt64, 15457 argLen: 1, 15458 asm: mips.ASUBVU, 15459 reg: regInfo{ 15460 inputs: []inputInfo{ 15461 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15462 }, 15463 outputs: []outputInfo{ 15464 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15465 }, 15466 }, 15467 }, 15468 { 15469 name: "MULV", 15470 argLen: 2, 15471 commutative: true, 15472 asm: mips.AMULV, 15473 reg: regInfo{ 15474 inputs: []inputInfo{ 15475 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15476 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15477 }, 15478 outputs: []outputInfo{ 15479 {0, 1152921504606846976}, // HI 15480 {1, 2305843009213693952}, // LO 15481 }, 15482 }, 15483 }, 15484 { 15485 name: "MULVU", 15486 argLen: 2, 15487 commutative: true, 15488 asm: mips.AMULVU, 15489 reg: regInfo{ 15490 inputs: []inputInfo{ 15491 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15492 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15493 }, 15494 outputs: []outputInfo{ 15495 {0, 1152921504606846976}, // HI 15496 {1, 2305843009213693952}, // LO 15497 }, 15498 }, 15499 }, 15500 { 15501 name: "DIVV", 15502 argLen: 2, 15503 asm: mips.ADIVV, 15504 reg: regInfo{ 15505 inputs: []inputInfo{ 15506 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15507 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15508 }, 15509 outputs: []outputInfo{ 15510 {0, 1152921504606846976}, // HI 15511 {1, 2305843009213693952}, // LO 15512 }, 15513 }, 15514 }, 15515 { 15516 name: "DIVVU", 15517 argLen: 2, 15518 asm: mips.ADIVVU, 15519 reg: regInfo{ 15520 inputs: []inputInfo{ 15521 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15522 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15523 }, 15524 outputs: []outputInfo{ 15525 {0, 1152921504606846976}, // HI 15526 {1, 2305843009213693952}, // LO 15527 }, 15528 }, 15529 }, 15530 { 15531 name: "ADDF", 15532 argLen: 2, 15533 commutative: true, 15534 asm: mips.AADDF, 15535 reg: regInfo{ 15536 inputs: []inputInfo{ 15537 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15538 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15539 }, 15540 outputs: []outputInfo{ 15541 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15542 }, 15543 }, 15544 }, 15545 { 15546 name: "ADDD", 15547 argLen: 2, 15548 commutative: true, 15549 asm: mips.AADDD, 15550 reg: regInfo{ 15551 inputs: []inputInfo{ 15552 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15553 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15554 }, 15555 outputs: []outputInfo{ 15556 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15557 }, 15558 }, 15559 }, 15560 { 15561 name: "SUBF", 15562 argLen: 2, 15563 asm: mips.ASUBF, 15564 reg: regInfo{ 15565 inputs: []inputInfo{ 15566 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15567 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15568 }, 15569 outputs: []outputInfo{ 15570 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15571 }, 15572 }, 15573 }, 15574 { 15575 name: "SUBD", 15576 argLen: 2, 15577 asm: mips.ASUBD, 15578 reg: regInfo{ 15579 inputs: []inputInfo{ 15580 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15581 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15582 }, 15583 outputs: []outputInfo{ 15584 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15585 }, 15586 }, 15587 }, 15588 { 15589 name: "MULF", 15590 argLen: 2, 15591 commutative: true, 15592 asm: mips.AMULF, 15593 reg: regInfo{ 15594 inputs: []inputInfo{ 15595 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15596 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15597 }, 15598 outputs: []outputInfo{ 15599 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15600 }, 15601 }, 15602 }, 15603 { 15604 name: "MULD", 15605 argLen: 2, 15606 commutative: true, 15607 asm: mips.AMULD, 15608 reg: regInfo{ 15609 inputs: []inputInfo{ 15610 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15611 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15612 }, 15613 outputs: []outputInfo{ 15614 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15615 }, 15616 }, 15617 }, 15618 { 15619 name: "DIVF", 15620 argLen: 2, 15621 asm: mips.ADIVF, 15622 reg: regInfo{ 15623 inputs: []inputInfo{ 15624 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15625 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15626 }, 15627 outputs: []outputInfo{ 15628 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15629 }, 15630 }, 15631 }, 15632 { 15633 name: "DIVD", 15634 argLen: 2, 15635 asm: mips.ADIVD, 15636 reg: regInfo{ 15637 inputs: []inputInfo{ 15638 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15639 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15640 }, 15641 outputs: []outputInfo{ 15642 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15643 }, 15644 }, 15645 }, 15646 { 15647 name: "AND", 15648 argLen: 2, 15649 commutative: true, 15650 asm: mips.AAND, 15651 reg: regInfo{ 15652 inputs: []inputInfo{ 15653 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15654 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15655 }, 15656 outputs: []outputInfo{ 15657 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15658 }, 15659 }, 15660 }, 15661 { 15662 name: "ANDconst", 15663 auxType: auxInt64, 15664 argLen: 1, 15665 asm: mips.AAND, 15666 reg: regInfo{ 15667 inputs: []inputInfo{ 15668 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15669 }, 15670 outputs: []outputInfo{ 15671 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15672 }, 15673 }, 15674 }, 15675 { 15676 name: "OR", 15677 argLen: 2, 15678 commutative: true, 15679 asm: mips.AOR, 15680 reg: regInfo{ 15681 inputs: []inputInfo{ 15682 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15683 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15684 }, 15685 outputs: []outputInfo{ 15686 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15687 }, 15688 }, 15689 }, 15690 { 15691 name: "ORconst", 15692 auxType: auxInt64, 15693 argLen: 1, 15694 asm: mips.AOR, 15695 reg: regInfo{ 15696 inputs: []inputInfo{ 15697 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15698 }, 15699 outputs: []outputInfo{ 15700 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15701 }, 15702 }, 15703 }, 15704 { 15705 name: "XOR", 15706 argLen: 2, 15707 commutative: true, 15708 asm: mips.AXOR, 15709 reg: regInfo{ 15710 inputs: []inputInfo{ 15711 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15712 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15713 }, 15714 outputs: []outputInfo{ 15715 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15716 }, 15717 }, 15718 }, 15719 { 15720 name: "XORconst", 15721 auxType: auxInt64, 15722 argLen: 1, 15723 asm: mips.AXOR, 15724 reg: regInfo{ 15725 inputs: []inputInfo{ 15726 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15727 }, 15728 outputs: []outputInfo{ 15729 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15730 }, 15731 }, 15732 }, 15733 { 15734 name: "NOR", 15735 argLen: 2, 15736 commutative: true, 15737 asm: mips.ANOR, 15738 reg: regInfo{ 15739 inputs: []inputInfo{ 15740 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15741 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15742 }, 15743 outputs: []outputInfo{ 15744 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15745 }, 15746 }, 15747 }, 15748 { 15749 name: "NORconst", 15750 auxType: auxInt64, 15751 argLen: 1, 15752 asm: mips.ANOR, 15753 reg: regInfo{ 15754 inputs: []inputInfo{ 15755 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15756 }, 15757 outputs: []outputInfo{ 15758 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15759 }, 15760 }, 15761 }, 15762 { 15763 name: "NEGV", 15764 argLen: 1, 15765 reg: regInfo{ 15766 inputs: []inputInfo{ 15767 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15768 }, 15769 outputs: []outputInfo{ 15770 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15771 }, 15772 }, 15773 }, 15774 { 15775 name: "NEGF", 15776 argLen: 1, 15777 asm: mips.ANEGF, 15778 reg: regInfo{ 15779 inputs: []inputInfo{ 15780 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15781 }, 15782 outputs: []outputInfo{ 15783 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15784 }, 15785 }, 15786 }, 15787 { 15788 name: "NEGD", 15789 argLen: 1, 15790 asm: mips.ANEGD, 15791 reg: regInfo{ 15792 inputs: []inputInfo{ 15793 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15794 }, 15795 outputs: []outputInfo{ 15796 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15797 }, 15798 }, 15799 }, 15800 { 15801 name: "SLLV", 15802 argLen: 2, 15803 asm: mips.ASLLV, 15804 reg: regInfo{ 15805 inputs: []inputInfo{ 15806 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15807 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15808 }, 15809 outputs: []outputInfo{ 15810 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15811 }, 15812 }, 15813 }, 15814 { 15815 name: "SLLVconst", 15816 auxType: auxInt64, 15817 argLen: 1, 15818 asm: mips.ASLLV, 15819 reg: regInfo{ 15820 inputs: []inputInfo{ 15821 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15822 }, 15823 outputs: []outputInfo{ 15824 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15825 }, 15826 }, 15827 }, 15828 { 15829 name: "SRLV", 15830 argLen: 2, 15831 asm: mips.ASRLV, 15832 reg: regInfo{ 15833 inputs: []inputInfo{ 15834 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15835 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15836 }, 15837 outputs: []outputInfo{ 15838 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15839 }, 15840 }, 15841 }, 15842 { 15843 name: "SRLVconst", 15844 auxType: auxInt64, 15845 argLen: 1, 15846 asm: mips.ASRLV, 15847 reg: regInfo{ 15848 inputs: []inputInfo{ 15849 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15850 }, 15851 outputs: []outputInfo{ 15852 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15853 }, 15854 }, 15855 }, 15856 { 15857 name: "SRAV", 15858 argLen: 2, 15859 asm: mips.ASRAV, 15860 reg: regInfo{ 15861 inputs: []inputInfo{ 15862 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15863 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15864 }, 15865 outputs: []outputInfo{ 15866 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15867 }, 15868 }, 15869 }, 15870 { 15871 name: "SRAVconst", 15872 auxType: auxInt64, 15873 argLen: 1, 15874 asm: mips.ASRAV, 15875 reg: regInfo{ 15876 inputs: []inputInfo{ 15877 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15878 }, 15879 outputs: []outputInfo{ 15880 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15881 }, 15882 }, 15883 }, 15884 { 15885 name: "SGT", 15886 argLen: 2, 15887 asm: mips.ASGT, 15888 reg: regInfo{ 15889 inputs: []inputInfo{ 15890 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15891 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15892 }, 15893 outputs: []outputInfo{ 15894 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15895 }, 15896 }, 15897 }, 15898 { 15899 name: "SGTconst", 15900 auxType: auxInt64, 15901 argLen: 1, 15902 asm: mips.ASGT, 15903 reg: regInfo{ 15904 inputs: []inputInfo{ 15905 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15906 }, 15907 outputs: []outputInfo{ 15908 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15909 }, 15910 }, 15911 }, 15912 { 15913 name: "SGTU", 15914 argLen: 2, 15915 asm: mips.ASGTU, 15916 reg: regInfo{ 15917 inputs: []inputInfo{ 15918 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15919 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15920 }, 15921 outputs: []outputInfo{ 15922 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15923 }, 15924 }, 15925 }, 15926 { 15927 name: "SGTUconst", 15928 auxType: auxInt64, 15929 argLen: 1, 15930 asm: mips.ASGTU, 15931 reg: regInfo{ 15932 inputs: []inputInfo{ 15933 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15934 }, 15935 outputs: []outputInfo{ 15936 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15937 }, 15938 }, 15939 }, 15940 { 15941 name: "CMPEQF", 15942 argLen: 2, 15943 asm: mips.ACMPEQF, 15944 reg: regInfo{ 15945 inputs: []inputInfo{ 15946 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15947 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15948 }, 15949 }, 15950 }, 15951 { 15952 name: "CMPEQD", 15953 argLen: 2, 15954 asm: mips.ACMPEQD, 15955 reg: regInfo{ 15956 inputs: []inputInfo{ 15957 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15958 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15959 }, 15960 }, 15961 }, 15962 { 15963 name: "CMPGEF", 15964 argLen: 2, 15965 asm: mips.ACMPGEF, 15966 reg: regInfo{ 15967 inputs: []inputInfo{ 15968 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15969 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15970 }, 15971 }, 15972 }, 15973 { 15974 name: "CMPGED", 15975 argLen: 2, 15976 asm: mips.ACMPGED, 15977 reg: regInfo{ 15978 inputs: []inputInfo{ 15979 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15980 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15981 }, 15982 }, 15983 }, 15984 { 15985 name: "CMPGTF", 15986 argLen: 2, 15987 asm: mips.ACMPGTF, 15988 reg: regInfo{ 15989 inputs: []inputInfo{ 15990 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15991 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15992 }, 15993 }, 15994 }, 15995 { 15996 name: "CMPGTD", 15997 argLen: 2, 15998 asm: mips.ACMPGTD, 15999 reg: regInfo{ 16000 inputs: []inputInfo{ 16001 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16002 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16003 }, 16004 }, 16005 }, 16006 { 16007 name: "MOVVconst", 16008 auxType: auxInt64, 16009 argLen: 0, 16010 rematerializeable: true, 16011 asm: mips.AMOVV, 16012 reg: regInfo{ 16013 outputs: []outputInfo{ 16014 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16015 }, 16016 }, 16017 }, 16018 { 16019 name: "MOVFconst", 16020 auxType: auxFloat64, 16021 argLen: 0, 16022 rematerializeable: true, 16023 asm: mips.AMOVF, 16024 reg: regInfo{ 16025 outputs: []outputInfo{ 16026 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16027 }, 16028 }, 16029 }, 16030 { 16031 name: "MOVDconst", 16032 auxType: auxFloat64, 16033 argLen: 0, 16034 rematerializeable: true, 16035 asm: mips.AMOVD, 16036 reg: regInfo{ 16037 outputs: []outputInfo{ 16038 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16039 }, 16040 }, 16041 }, 16042 { 16043 name: "MOVVaddr", 16044 auxType: auxSymOff, 16045 argLen: 1, 16046 rematerializeable: true, 16047 symEffect: SymAddr, 16048 asm: mips.AMOVV, 16049 reg: regInfo{ 16050 inputs: []inputInfo{ 16051 {0, 4611686018460942336}, // SP SB 16052 }, 16053 outputs: []outputInfo{ 16054 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16055 }, 16056 }, 16057 }, 16058 { 16059 name: "MOVBload", 16060 auxType: auxSymOff, 16061 argLen: 2, 16062 faultOnNilArg0: true, 16063 symEffect: SymRead, 16064 asm: mips.AMOVB, 16065 reg: regInfo{ 16066 inputs: []inputInfo{ 16067 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16068 }, 16069 outputs: []outputInfo{ 16070 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16071 }, 16072 }, 16073 }, 16074 { 16075 name: "MOVBUload", 16076 auxType: auxSymOff, 16077 argLen: 2, 16078 faultOnNilArg0: true, 16079 symEffect: SymRead, 16080 asm: mips.AMOVBU, 16081 reg: regInfo{ 16082 inputs: []inputInfo{ 16083 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16084 }, 16085 outputs: []outputInfo{ 16086 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16087 }, 16088 }, 16089 }, 16090 { 16091 name: "MOVHload", 16092 auxType: auxSymOff, 16093 argLen: 2, 16094 faultOnNilArg0: true, 16095 symEffect: SymRead, 16096 asm: mips.AMOVH, 16097 reg: regInfo{ 16098 inputs: []inputInfo{ 16099 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16100 }, 16101 outputs: []outputInfo{ 16102 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16103 }, 16104 }, 16105 }, 16106 { 16107 name: "MOVHUload", 16108 auxType: auxSymOff, 16109 argLen: 2, 16110 faultOnNilArg0: true, 16111 symEffect: SymRead, 16112 asm: mips.AMOVHU, 16113 reg: regInfo{ 16114 inputs: []inputInfo{ 16115 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16116 }, 16117 outputs: []outputInfo{ 16118 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16119 }, 16120 }, 16121 }, 16122 { 16123 name: "MOVWload", 16124 auxType: auxSymOff, 16125 argLen: 2, 16126 faultOnNilArg0: true, 16127 symEffect: SymRead, 16128 asm: mips.AMOVW, 16129 reg: regInfo{ 16130 inputs: []inputInfo{ 16131 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16132 }, 16133 outputs: []outputInfo{ 16134 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16135 }, 16136 }, 16137 }, 16138 { 16139 name: "MOVWUload", 16140 auxType: auxSymOff, 16141 argLen: 2, 16142 faultOnNilArg0: true, 16143 symEffect: SymRead, 16144 asm: mips.AMOVWU, 16145 reg: regInfo{ 16146 inputs: []inputInfo{ 16147 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16148 }, 16149 outputs: []outputInfo{ 16150 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16151 }, 16152 }, 16153 }, 16154 { 16155 name: "MOVVload", 16156 auxType: auxSymOff, 16157 argLen: 2, 16158 faultOnNilArg0: true, 16159 symEffect: SymRead, 16160 asm: mips.AMOVV, 16161 reg: regInfo{ 16162 inputs: []inputInfo{ 16163 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16164 }, 16165 outputs: []outputInfo{ 16166 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16167 }, 16168 }, 16169 }, 16170 { 16171 name: "MOVFload", 16172 auxType: auxSymOff, 16173 argLen: 2, 16174 faultOnNilArg0: true, 16175 symEffect: SymRead, 16176 asm: mips.AMOVF, 16177 reg: regInfo{ 16178 inputs: []inputInfo{ 16179 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16180 }, 16181 outputs: []outputInfo{ 16182 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16183 }, 16184 }, 16185 }, 16186 { 16187 name: "MOVDload", 16188 auxType: auxSymOff, 16189 argLen: 2, 16190 faultOnNilArg0: true, 16191 symEffect: SymRead, 16192 asm: mips.AMOVD, 16193 reg: regInfo{ 16194 inputs: []inputInfo{ 16195 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16196 }, 16197 outputs: []outputInfo{ 16198 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16199 }, 16200 }, 16201 }, 16202 { 16203 name: "MOVBstore", 16204 auxType: auxSymOff, 16205 argLen: 3, 16206 faultOnNilArg0: true, 16207 symEffect: SymWrite, 16208 asm: mips.AMOVB, 16209 reg: regInfo{ 16210 inputs: []inputInfo{ 16211 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16212 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16213 }, 16214 }, 16215 }, 16216 { 16217 name: "MOVHstore", 16218 auxType: auxSymOff, 16219 argLen: 3, 16220 faultOnNilArg0: true, 16221 symEffect: SymWrite, 16222 asm: mips.AMOVH, 16223 reg: regInfo{ 16224 inputs: []inputInfo{ 16225 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16226 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16227 }, 16228 }, 16229 }, 16230 { 16231 name: "MOVWstore", 16232 auxType: auxSymOff, 16233 argLen: 3, 16234 faultOnNilArg0: true, 16235 symEffect: SymWrite, 16236 asm: mips.AMOVW, 16237 reg: regInfo{ 16238 inputs: []inputInfo{ 16239 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16240 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16241 }, 16242 }, 16243 }, 16244 { 16245 name: "MOVVstore", 16246 auxType: auxSymOff, 16247 argLen: 3, 16248 faultOnNilArg0: true, 16249 symEffect: SymWrite, 16250 asm: mips.AMOVV, 16251 reg: regInfo{ 16252 inputs: []inputInfo{ 16253 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16254 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16255 }, 16256 }, 16257 }, 16258 { 16259 name: "MOVFstore", 16260 auxType: auxSymOff, 16261 argLen: 3, 16262 faultOnNilArg0: true, 16263 symEffect: SymWrite, 16264 asm: mips.AMOVF, 16265 reg: regInfo{ 16266 inputs: []inputInfo{ 16267 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16268 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16269 }, 16270 }, 16271 }, 16272 { 16273 name: "MOVDstore", 16274 auxType: auxSymOff, 16275 argLen: 3, 16276 faultOnNilArg0: true, 16277 symEffect: SymWrite, 16278 asm: mips.AMOVD, 16279 reg: regInfo{ 16280 inputs: []inputInfo{ 16281 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16282 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16283 }, 16284 }, 16285 }, 16286 { 16287 name: "MOVBstorezero", 16288 auxType: auxSymOff, 16289 argLen: 2, 16290 faultOnNilArg0: true, 16291 symEffect: SymWrite, 16292 asm: mips.AMOVB, 16293 reg: regInfo{ 16294 inputs: []inputInfo{ 16295 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16296 }, 16297 }, 16298 }, 16299 { 16300 name: "MOVHstorezero", 16301 auxType: auxSymOff, 16302 argLen: 2, 16303 faultOnNilArg0: true, 16304 symEffect: SymWrite, 16305 asm: mips.AMOVH, 16306 reg: regInfo{ 16307 inputs: []inputInfo{ 16308 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16309 }, 16310 }, 16311 }, 16312 { 16313 name: "MOVWstorezero", 16314 auxType: auxSymOff, 16315 argLen: 2, 16316 faultOnNilArg0: true, 16317 symEffect: SymWrite, 16318 asm: mips.AMOVW, 16319 reg: regInfo{ 16320 inputs: []inputInfo{ 16321 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16322 }, 16323 }, 16324 }, 16325 { 16326 name: "MOVVstorezero", 16327 auxType: auxSymOff, 16328 argLen: 2, 16329 faultOnNilArg0: true, 16330 symEffect: SymWrite, 16331 asm: mips.AMOVV, 16332 reg: regInfo{ 16333 inputs: []inputInfo{ 16334 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16335 }, 16336 }, 16337 }, 16338 { 16339 name: "MOVBreg", 16340 argLen: 1, 16341 asm: mips.AMOVB, 16342 reg: regInfo{ 16343 inputs: []inputInfo{ 16344 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16345 }, 16346 outputs: []outputInfo{ 16347 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16348 }, 16349 }, 16350 }, 16351 { 16352 name: "MOVBUreg", 16353 argLen: 1, 16354 asm: mips.AMOVBU, 16355 reg: regInfo{ 16356 inputs: []inputInfo{ 16357 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16358 }, 16359 outputs: []outputInfo{ 16360 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16361 }, 16362 }, 16363 }, 16364 { 16365 name: "MOVHreg", 16366 argLen: 1, 16367 asm: mips.AMOVH, 16368 reg: regInfo{ 16369 inputs: []inputInfo{ 16370 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16371 }, 16372 outputs: []outputInfo{ 16373 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16374 }, 16375 }, 16376 }, 16377 { 16378 name: "MOVHUreg", 16379 argLen: 1, 16380 asm: mips.AMOVHU, 16381 reg: regInfo{ 16382 inputs: []inputInfo{ 16383 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16384 }, 16385 outputs: []outputInfo{ 16386 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16387 }, 16388 }, 16389 }, 16390 { 16391 name: "MOVWreg", 16392 argLen: 1, 16393 asm: mips.AMOVW, 16394 reg: regInfo{ 16395 inputs: []inputInfo{ 16396 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16397 }, 16398 outputs: []outputInfo{ 16399 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16400 }, 16401 }, 16402 }, 16403 { 16404 name: "MOVWUreg", 16405 argLen: 1, 16406 asm: mips.AMOVWU, 16407 reg: regInfo{ 16408 inputs: []inputInfo{ 16409 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16410 }, 16411 outputs: []outputInfo{ 16412 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16413 }, 16414 }, 16415 }, 16416 { 16417 name: "MOVVreg", 16418 argLen: 1, 16419 asm: mips.AMOVV, 16420 reg: regInfo{ 16421 inputs: []inputInfo{ 16422 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16423 }, 16424 outputs: []outputInfo{ 16425 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16426 }, 16427 }, 16428 }, 16429 { 16430 name: "MOVVnop", 16431 argLen: 1, 16432 resultInArg0: true, 16433 reg: regInfo{ 16434 inputs: []inputInfo{ 16435 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16436 }, 16437 outputs: []outputInfo{ 16438 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16439 }, 16440 }, 16441 }, 16442 { 16443 name: "MOVWF", 16444 argLen: 1, 16445 asm: mips.AMOVWF, 16446 reg: regInfo{ 16447 inputs: []inputInfo{ 16448 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16449 }, 16450 outputs: []outputInfo{ 16451 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16452 }, 16453 }, 16454 }, 16455 { 16456 name: "MOVWD", 16457 argLen: 1, 16458 asm: mips.AMOVWD, 16459 reg: regInfo{ 16460 inputs: []inputInfo{ 16461 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16462 }, 16463 outputs: []outputInfo{ 16464 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16465 }, 16466 }, 16467 }, 16468 { 16469 name: "MOVVF", 16470 argLen: 1, 16471 asm: mips.AMOVVF, 16472 reg: regInfo{ 16473 inputs: []inputInfo{ 16474 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16475 }, 16476 outputs: []outputInfo{ 16477 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16478 }, 16479 }, 16480 }, 16481 { 16482 name: "MOVVD", 16483 argLen: 1, 16484 asm: mips.AMOVVD, 16485 reg: regInfo{ 16486 inputs: []inputInfo{ 16487 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16488 }, 16489 outputs: []outputInfo{ 16490 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16491 }, 16492 }, 16493 }, 16494 { 16495 name: "TRUNCFW", 16496 argLen: 1, 16497 asm: mips.ATRUNCFW, 16498 reg: regInfo{ 16499 inputs: []inputInfo{ 16500 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16501 }, 16502 outputs: []outputInfo{ 16503 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16504 }, 16505 }, 16506 }, 16507 { 16508 name: "TRUNCDW", 16509 argLen: 1, 16510 asm: mips.ATRUNCDW, 16511 reg: regInfo{ 16512 inputs: []inputInfo{ 16513 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16514 }, 16515 outputs: []outputInfo{ 16516 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16517 }, 16518 }, 16519 }, 16520 { 16521 name: "TRUNCFV", 16522 argLen: 1, 16523 asm: mips.ATRUNCFV, 16524 reg: regInfo{ 16525 inputs: []inputInfo{ 16526 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16527 }, 16528 outputs: []outputInfo{ 16529 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16530 }, 16531 }, 16532 }, 16533 { 16534 name: "TRUNCDV", 16535 argLen: 1, 16536 asm: mips.ATRUNCDV, 16537 reg: regInfo{ 16538 inputs: []inputInfo{ 16539 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16540 }, 16541 outputs: []outputInfo{ 16542 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16543 }, 16544 }, 16545 }, 16546 { 16547 name: "MOVFD", 16548 argLen: 1, 16549 asm: mips.AMOVFD, 16550 reg: regInfo{ 16551 inputs: []inputInfo{ 16552 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16553 }, 16554 outputs: []outputInfo{ 16555 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16556 }, 16557 }, 16558 }, 16559 { 16560 name: "MOVDF", 16561 argLen: 1, 16562 asm: mips.AMOVDF, 16563 reg: regInfo{ 16564 inputs: []inputInfo{ 16565 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16566 }, 16567 outputs: []outputInfo{ 16568 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16569 }, 16570 }, 16571 }, 16572 { 16573 name: "CALLstatic", 16574 auxType: auxSymOff, 16575 argLen: 1, 16576 clobberFlags: true, 16577 call: true, 16578 symEffect: SymNone, 16579 reg: regInfo{ 16580 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 16581 }, 16582 }, 16583 { 16584 name: "CALLclosure", 16585 auxType: auxInt64, 16586 argLen: 3, 16587 clobberFlags: true, 16588 call: true, 16589 reg: regInfo{ 16590 inputs: []inputInfo{ 16591 {1, 4194304}, // R22 16592 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 16593 }, 16594 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 16595 }, 16596 }, 16597 { 16598 name: "CALLinter", 16599 auxType: auxInt64, 16600 argLen: 2, 16601 clobberFlags: true, 16602 call: true, 16603 reg: regInfo{ 16604 inputs: []inputInfo{ 16605 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16606 }, 16607 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 16608 }, 16609 }, 16610 { 16611 name: "DUFFZERO", 16612 auxType: auxInt64, 16613 argLen: 2, 16614 faultOnNilArg0: true, 16615 reg: regInfo{ 16616 inputs: []inputInfo{ 16617 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16618 }, 16619 clobbers: 134217730, // R1 R31 16620 }, 16621 }, 16622 { 16623 name: "LoweredZero", 16624 auxType: auxInt64, 16625 argLen: 3, 16626 clobberFlags: true, 16627 faultOnNilArg0: true, 16628 reg: regInfo{ 16629 inputs: []inputInfo{ 16630 {0, 2}, // R1 16631 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16632 }, 16633 clobbers: 2, // R1 16634 }, 16635 }, 16636 { 16637 name: "LoweredMove", 16638 auxType: auxInt64, 16639 argLen: 4, 16640 clobberFlags: true, 16641 faultOnNilArg0: true, 16642 faultOnNilArg1: true, 16643 reg: regInfo{ 16644 inputs: []inputInfo{ 16645 {0, 4}, // R2 16646 {1, 2}, // R1 16647 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16648 }, 16649 clobbers: 6, // R1 R2 16650 }, 16651 }, 16652 { 16653 name: "LoweredAtomicLoad32", 16654 argLen: 2, 16655 faultOnNilArg0: true, 16656 reg: regInfo{ 16657 inputs: []inputInfo{ 16658 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16659 }, 16660 outputs: []outputInfo{ 16661 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16662 }, 16663 }, 16664 }, 16665 { 16666 name: "LoweredAtomicLoad64", 16667 argLen: 2, 16668 faultOnNilArg0: true, 16669 reg: regInfo{ 16670 inputs: []inputInfo{ 16671 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16672 }, 16673 outputs: []outputInfo{ 16674 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16675 }, 16676 }, 16677 }, 16678 { 16679 name: "LoweredAtomicStore32", 16680 argLen: 3, 16681 faultOnNilArg0: true, 16682 hasSideEffects: true, 16683 reg: regInfo{ 16684 inputs: []inputInfo{ 16685 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16686 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16687 }, 16688 }, 16689 }, 16690 { 16691 name: "LoweredAtomicStore64", 16692 argLen: 3, 16693 faultOnNilArg0: true, 16694 hasSideEffects: true, 16695 reg: regInfo{ 16696 inputs: []inputInfo{ 16697 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16698 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16699 }, 16700 }, 16701 }, 16702 { 16703 name: "LoweredAtomicStorezero32", 16704 argLen: 2, 16705 faultOnNilArg0: true, 16706 hasSideEffects: true, 16707 reg: regInfo{ 16708 inputs: []inputInfo{ 16709 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16710 }, 16711 }, 16712 }, 16713 { 16714 name: "LoweredAtomicStorezero64", 16715 argLen: 2, 16716 faultOnNilArg0: true, 16717 hasSideEffects: true, 16718 reg: regInfo{ 16719 inputs: []inputInfo{ 16720 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16721 }, 16722 }, 16723 }, 16724 { 16725 name: "LoweredAtomicExchange32", 16726 argLen: 3, 16727 resultNotInArgs: true, 16728 faultOnNilArg0: true, 16729 hasSideEffects: true, 16730 reg: regInfo{ 16731 inputs: []inputInfo{ 16732 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16733 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16734 }, 16735 outputs: []outputInfo{ 16736 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16737 }, 16738 }, 16739 }, 16740 { 16741 name: "LoweredAtomicExchange64", 16742 argLen: 3, 16743 resultNotInArgs: true, 16744 faultOnNilArg0: true, 16745 hasSideEffects: true, 16746 reg: regInfo{ 16747 inputs: []inputInfo{ 16748 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16749 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16750 }, 16751 outputs: []outputInfo{ 16752 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16753 }, 16754 }, 16755 }, 16756 { 16757 name: "LoweredAtomicAdd32", 16758 argLen: 3, 16759 resultNotInArgs: true, 16760 faultOnNilArg0: true, 16761 hasSideEffects: true, 16762 reg: regInfo{ 16763 inputs: []inputInfo{ 16764 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16765 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16766 }, 16767 outputs: []outputInfo{ 16768 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16769 }, 16770 }, 16771 }, 16772 { 16773 name: "LoweredAtomicAdd64", 16774 argLen: 3, 16775 resultNotInArgs: true, 16776 faultOnNilArg0: true, 16777 hasSideEffects: true, 16778 reg: regInfo{ 16779 inputs: []inputInfo{ 16780 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16781 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16782 }, 16783 outputs: []outputInfo{ 16784 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16785 }, 16786 }, 16787 }, 16788 { 16789 name: "LoweredAtomicAddconst32", 16790 auxType: auxInt32, 16791 argLen: 2, 16792 resultNotInArgs: true, 16793 faultOnNilArg0: true, 16794 hasSideEffects: true, 16795 reg: regInfo{ 16796 inputs: []inputInfo{ 16797 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16798 }, 16799 outputs: []outputInfo{ 16800 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16801 }, 16802 }, 16803 }, 16804 { 16805 name: "LoweredAtomicAddconst64", 16806 auxType: auxInt64, 16807 argLen: 2, 16808 resultNotInArgs: true, 16809 faultOnNilArg0: true, 16810 hasSideEffects: true, 16811 reg: regInfo{ 16812 inputs: []inputInfo{ 16813 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16814 }, 16815 outputs: []outputInfo{ 16816 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16817 }, 16818 }, 16819 }, 16820 { 16821 name: "LoweredAtomicCas32", 16822 argLen: 4, 16823 resultNotInArgs: true, 16824 faultOnNilArg0: true, 16825 hasSideEffects: true, 16826 reg: regInfo{ 16827 inputs: []inputInfo{ 16828 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16829 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16830 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16831 }, 16832 outputs: []outputInfo{ 16833 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16834 }, 16835 }, 16836 }, 16837 { 16838 name: "LoweredAtomicCas64", 16839 argLen: 4, 16840 resultNotInArgs: true, 16841 faultOnNilArg0: true, 16842 hasSideEffects: true, 16843 reg: regInfo{ 16844 inputs: []inputInfo{ 16845 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16846 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16847 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16848 }, 16849 outputs: []outputInfo{ 16850 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16851 }, 16852 }, 16853 }, 16854 { 16855 name: "LoweredNilCheck", 16856 argLen: 2, 16857 nilCheck: true, 16858 faultOnNilArg0: true, 16859 reg: regInfo{ 16860 inputs: []inputInfo{ 16861 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16862 }, 16863 }, 16864 }, 16865 { 16866 name: "FPFlagTrue", 16867 argLen: 1, 16868 reg: regInfo{ 16869 outputs: []outputInfo{ 16870 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16871 }, 16872 }, 16873 }, 16874 { 16875 name: "FPFlagFalse", 16876 argLen: 1, 16877 reg: regInfo{ 16878 outputs: []outputInfo{ 16879 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16880 }, 16881 }, 16882 }, 16883 { 16884 name: "LoweredGetClosurePtr", 16885 argLen: 0, 16886 reg: regInfo{ 16887 outputs: []outputInfo{ 16888 {0, 4194304}, // R22 16889 }, 16890 }, 16891 }, 16892 { 16893 name: "LoweredGetCallerSP", 16894 argLen: 0, 16895 rematerializeable: true, 16896 reg: regInfo{ 16897 outputs: []outputInfo{ 16898 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16899 }, 16900 }, 16901 }, 16902 { 16903 name: "MOVVconvert", 16904 argLen: 2, 16905 asm: mips.AMOVV, 16906 reg: regInfo{ 16907 inputs: []inputInfo{ 16908 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16909 }, 16910 outputs: []outputInfo{ 16911 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16912 }, 16913 }, 16914 }, 16915 16916 { 16917 name: "ADD", 16918 argLen: 2, 16919 commutative: true, 16920 asm: ppc64.AADD, 16921 reg: regInfo{ 16922 inputs: []inputInfo{ 16923 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16924 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16925 }, 16926 outputs: []outputInfo{ 16927 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16928 }, 16929 }, 16930 }, 16931 { 16932 name: "ADDconst", 16933 auxType: auxInt64, 16934 argLen: 1, 16935 asm: ppc64.AADD, 16936 reg: regInfo{ 16937 inputs: []inputInfo{ 16938 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16939 }, 16940 outputs: []outputInfo{ 16941 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16942 }, 16943 }, 16944 }, 16945 { 16946 name: "FADD", 16947 argLen: 2, 16948 commutative: true, 16949 asm: ppc64.AFADD, 16950 reg: regInfo{ 16951 inputs: []inputInfo{ 16952 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16953 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16954 }, 16955 outputs: []outputInfo{ 16956 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16957 }, 16958 }, 16959 }, 16960 { 16961 name: "FADDS", 16962 argLen: 2, 16963 commutative: true, 16964 asm: ppc64.AFADDS, 16965 reg: regInfo{ 16966 inputs: []inputInfo{ 16967 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16968 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16969 }, 16970 outputs: []outputInfo{ 16971 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16972 }, 16973 }, 16974 }, 16975 { 16976 name: "SUB", 16977 argLen: 2, 16978 asm: ppc64.ASUB, 16979 reg: regInfo{ 16980 inputs: []inputInfo{ 16981 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16982 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16983 }, 16984 outputs: []outputInfo{ 16985 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16986 }, 16987 }, 16988 }, 16989 { 16990 name: "FSUB", 16991 argLen: 2, 16992 asm: ppc64.AFSUB, 16993 reg: regInfo{ 16994 inputs: []inputInfo{ 16995 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16996 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16997 }, 16998 outputs: []outputInfo{ 16999 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17000 }, 17001 }, 17002 }, 17003 { 17004 name: "FSUBS", 17005 argLen: 2, 17006 asm: ppc64.AFSUBS, 17007 reg: regInfo{ 17008 inputs: []inputInfo{ 17009 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17010 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17011 }, 17012 outputs: []outputInfo{ 17013 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17014 }, 17015 }, 17016 }, 17017 { 17018 name: "MULLD", 17019 argLen: 2, 17020 commutative: true, 17021 asm: ppc64.AMULLD, 17022 reg: regInfo{ 17023 inputs: []inputInfo{ 17024 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17025 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17026 }, 17027 outputs: []outputInfo{ 17028 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17029 }, 17030 }, 17031 }, 17032 { 17033 name: "MULLW", 17034 argLen: 2, 17035 commutative: true, 17036 asm: ppc64.AMULLW, 17037 reg: regInfo{ 17038 inputs: []inputInfo{ 17039 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17040 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17041 }, 17042 outputs: []outputInfo{ 17043 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17044 }, 17045 }, 17046 }, 17047 { 17048 name: "MULHD", 17049 argLen: 2, 17050 commutative: true, 17051 asm: ppc64.AMULHD, 17052 reg: regInfo{ 17053 inputs: []inputInfo{ 17054 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17055 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17056 }, 17057 outputs: []outputInfo{ 17058 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17059 }, 17060 }, 17061 }, 17062 { 17063 name: "MULHW", 17064 argLen: 2, 17065 commutative: true, 17066 asm: ppc64.AMULHW, 17067 reg: regInfo{ 17068 inputs: []inputInfo{ 17069 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17070 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17071 }, 17072 outputs: []outputInfo{ 17073 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17074 }, 17075 }, 17076 }, 17077 { 17078 name: "MULHDU", 17079 argLen: 2, 17080 commutative: true, 17081 asm: ppc64.AMULHDU, 17082 reg: regInfo{ 17083 inputs: []inputInfo{ 17084 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17085 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17086 }, 17087 outputs: []outputInfo{ 17088 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17089 }, 17090 }, 17091 }, 17092 { 17093 name: "MULHWU", 17094 argLen: 2, 17095 commutative: true, 17096 asm: ppc64.AMULHWU, 17097 reg: regInfo{ 17098 inputs: []inputInfo{ 17099 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17100 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17101 }, 17102 outputs: []outputInfo{ 17103 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17104 }, 17105 }, 17106 }, 17107 { 17108 name: "FMUL", 17109 argLen: 2, 17110 commutative: true, 17111 asm: ppc64.AFMUL, 17112 reg: regInfo{ 17113 inputs: []inputInfo{ 17114 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17115 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17116 }, 17117 outputs: []outputInfo{ 17118 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17119 }, 17120 }, 17121 }, 17122 { 17123 name: "FMULS", 17124 argLen: 2, 17125 commutative: true, 17126 asm: ppc64.AFMULS, 17127 reg: regInfo{ 17128 inputs: []inputInfo{ 17129 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17130 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17131 }, 17132 outputs: []outputInfo{ 17133 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17134 }, 17135 }, 17136 }, 17137 { 17138 name: "FMADD", 17139 argLen: 3, 17140 asm: ppc64.AFMADD, 17141 reg: regInfo{ 17142 inputs: []inputInfo{ 17143 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17144 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17145 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17146 }, 17147 outputs: []outputInfo{ 17148 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17149 }, 17150 }, 17151 }, 17152 { 17153 name: "FMADDS", 17154 argLen: 3, 17155 asm: ppc64.AFMADDS, 17156 reg: regInfo{ 17157 inputs: []inputInfo{ 17158 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17159 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17160 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17161 }, 17162 outputs: []outputInfo{ 17163 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17164 }, 17165 }, 17166 }, 17167 { 17168 name: "FMSUB", 17169 argLen: 3, 17170 asm: ppc64.AFMSUB, 17171 reg: regInfo{ 17172 inputs: []inputInfo{ 17173 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17174 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17175 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17176 }, 17177 outputs: []outputInfo{ 17178 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17179 }, 17180 }, 17181 }, 17182 { 17183 name: "FMSUBS", 17184 argLen: 3, 17185 asm: ppc64.AFMSUBS, 17186 reg: regInfo{ 17187 inputs: []inputInfo{ 17188 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17189 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17190 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17191 }, 17192 outputs: []outputInfo{ 17193 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17194 }, 17195 }, 17196 }, 17197 { 17198 name: "SRAD", 17199 argLen: 2, 17200 asm: ppc64.ASRAD, 17201 reg: regInfo{ 17202 inputs: []inputInfo{ 17203 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17204 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17205 }, 17206 outputs: []outputInfo{ 17207 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17208 }, 17209 }, 17210 }, 17211 { 17212 name: "SRAW", 17213 argLen: 2, 17214 asm: ppc64.ASRAW, 17215 reg: regInfo{ 17216 inputs: []inputInfo{ 17217 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17218 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17219 }, 17220 outputs: []outputInfo{ 17221 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17222 }, 17223 }, 17224 }, 17225 { 17226 name: "SRD", 17227 argLen: 2, 17228 asm: ppc64.ASRD, 17229 reg: regInfo{ 17230 inputs: []inputInfo{ 17231 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17232 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17233 }, 17234 outputs: []outputInfo{ 17235 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17236 }, 17237 }, 17238 }, 17239 { 17240 name: "SRW", 17241 argLen: 2, 17242 asm: ppc64.ASRW, 17243 reg: regInfo{ 17244 inputs: []inputInfo{ 17245 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17246 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17247 }, 17248 outputs: []outputInfo{ 17249 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17250 }, 17251 }, 17252 }, 17253 { 17254 name: "SLD", 17255 argLen: 2, 17256 asm: ppc64.ASLD, 17257 reg: regInfo{ 17258 inputs: []inputInfo{ 17259 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17260 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17261 }, 17262 outputs: []outputInfo{ 17263 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17264 }, 17265 }, 17266 }, 17267 { 17268 name: "SLW", 17269 argLen: 2, 17270 asm: ppc64.ASLW, 17271 reg: regInfo{ 17272 inputs: []inputInfo{ 17273 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17274 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17275 }, 17276 outputs: []outputInfo{ 17277 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17278 }, 17279 }, 17280 }, 17281 { 17282 name: "ROTL", 17283 argLen: 2, 17284 asm: ppc64.AROTL, 17285 reg: regInfo{ 17286 inputs: []inputInfo{ 17287 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17288 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17289 }, 17290 outputs: []outputInfo{ 17291 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17292 }, 17293 }, 17294 }, 17295 { 17296 name: "ROTLW", 17297 argLen: 2, 17298 asm: ppc64.AROTLW, 17299 reg: regInfo{ 17300 inputs: []inputInfo{ 17301 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17302 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17303 }, 17304 outputs: []outputInfo{ 17305 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17306 }, 17307 }, 17308 }, 17309 { 17310 name: "ADDconstForCarry", 17311 auxType: auxInt16, 17312 argLen: 1, 17313 asm: ppc64.AADDC, 17314 reg: regInfo{ 17315 inputs: []inputInfo{ 17316 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17317 }, 17318 clobbers: 2147483648, // R31 17319 }, 17320 }, 17321 { 17322 name: "MaskIfNotCarry", 17323 argLen: 1, 17324 asm: ppc64.AADDME, 17325 reg: regInfo{ 17326 outputs: []outputInfo{ 17327 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17328 }, 17329 }, 17330 }, 17331 { 17332 name: "SRADconst", 17333 auxType: auxInt64, 17334 argLen: 1, 17335 asm: ppc64.ASRAD, 17336 reg: regInfo{ 17337 inputs: []inputInfo{ 17338 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17339 }, 17340 outputs: []outputInfo{ 17341 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17342 }, 17343 }, 17344 }, 17345 { 17346 name: "SRAWconst", 17347 auxType: auxInt64, 17348 argLen: 1, 17349 asm: ppc64.ASRAW, 17350 reg: regInfo{ 17351 inputs: []inputInfo{ 17352 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17353 }, 17354 outputs: []outputInfo{ 17355 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17356 }, 17357 }, 17358 }, 17359 { 17360 name: "SRDconst", 17361 auxType: auxInt64, 17362 argLen: 1, 17363 asm: ppc64.ASRD, 17364 reg: regInfo{ 17365 inputs: []inputInfo{ 17366 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17367 }, 17368 outputs: []outputInfo{ 17369 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17370 }, 17371 }, 17372 }, 17373 { 17374 name: "SRWconst", 17375 auxType: auxInt64, 17376 argLen: 1, 17377 asm: ppc64.ASRW, 17378 reg: regInfo{ 17379 inputs: []inputInfo{ 17380 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17381 }, 17382 outputs: []outputInfo{ 17383 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17384 }, 17385 }, 17386 }, 17387 { 17388 name: "SLDconst", 17389 auxType: auxInt64, 17390 argLen: 1, 17391 asm: ppc64.ASLD, 17392 reg: regInfo{ 17393 inputs: []inputInfo{ 17394 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17395 }, 17396 outputs: []outputInfo{ 17397 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17398 }, 17399 }, 17400 }, 17401 { 17402 name: "SLWconst", 17403 auxType: auxInt64, 17404 argLen: 1, 17405 asm: ppc64.ASLW, 17406 reg: regInfo{ 17407 inputs: []inputInfo{ 17408 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17409 }, 17410 outputs: []outputInfo{ 17411 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17412 }, 17413 }, 17414 }, 17415 { 17416 name: "ROTLconst", 17417 auxType: auxInt64, 17418 argLen: 1, 17419 asm: ppc64.AROTL, 17420 reg: regInfo{ 17421 inputs: []inputInfo{ 17422 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17423 }, 17424 outputs: []outputInfo{ 17425 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17426 }, 17427 }, 17428 }, 17429 { 17430 name: "ROTLWconst", 17431 auxType: auxInt64, 17432 argLen: 1, 17433 asm: ppc64.AROTLW, 17434 reg: regInfo{ 17435 inputs: []inputInfo{ 17436 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17437 }, 17438 outputs: []outputInfo{ 17439 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17440 }, 17441 }, 17442 }, 17443 { 17444 name: "CNTLZD", 17445 argLen: 1, 17446 clobberFlags: true, 17447 asm: ppc64.ACNTLZD, 17448 reg: regInfo{ 17449 inputs: []inputInfo{ 17450 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17451 }, 17452 outputs: []outputInfo{ 17453 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17454 }, 17455 }, 17456 }, 17457 { 17458 name: "CNTLZW", 17459 argLen: 1, 17460 clobberFlags: true, 17461 asm: ppc64.ACNTLZW, 17462 reg: regInfo{ 17463 inputs: []inputInfo{ 17464 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17465 }, 17466 outputs: []outputInfo{ 17467 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17468 }, 17469 }, 17470 }, 17471 { 17472 name: "POPCNTD", 17473 argLen: 1, 17474 asm: ppc64.APOPCNTD, 17475 reg: regInfo{ 17476 inputs: []inputInfo{ 17477 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17478 }, 17479 outputs: []outputInfo{ 17480 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17481 }, 17482 }, 17483 }, 17484 { 17485 name: "POPCNTW", 17486 argLen: 1, 17487 asm: ppc64.APOPCNTW, 17488 reg: regInfo{ 17489 inputs: []inputInfo{ 17490 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17491 }, 17492 outputs: []outputInfo{ 17493 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17494 }, 17495 }, 17496 }, 17497 { 17498 name: "POPCNTB", 17499 argLen: 1, 17500 asm: ppc64.APOPCNTB, 17501 reg: regInfo{ 17502 inputs: []inputInfo{ 17503 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17504 }, 17505 outputs: []outputInfo{ 17506 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17507 }, 17508 }, 17509 }, 17510 { 17511 name: "FDIV", 17512 argLen: 2, 17513 asm: ppc64.AFDIV, 17514 reg: regInfo{ 17515 inputs: []inputInfo{ 17516 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17517 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17518 }, 17519 outputs: []outputInfo{ 17520 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17521 }, 17522 }, 17523 }, 17524 { 17525 name: "FDIVS", 17526 argLen: 2, 17527 asm: ppc64.AFDIVS, 17528 reg: regInfo{ 17529 inputs: []inputInfo{ 17530 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17531 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17532 }, 17533 outputs: []outputInfo{ 17534 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17535 }, 17536 }, 17537 }, 17538 { 17539 name: "DIVD", 17540 argLen: 2, 17541 asm: ppc64.ADIVD, 17542 reg: regInfo{ 17543 inputs: []inputInfo{ 17544 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17545 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17546 }, 17547 outputs: []outputInfo{ 17548 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17549 }, 17550 }, 17551 }, 17552 { 17553 name: "DIVW", 17554 argLen: 2, 17555 asm: ppc64.ADIVW, 17556 reg: regInfo{ 17557 inputs: []inputInfo{ 17558 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17559 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17560 }, 17561 outputs: []outputInfo{ 17562 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17563 }, 17564 }, 17565 }, 17566 { 17567 name: "DIVDU", 17568 argLen: 2, 17569 asm: ppc64.ADIVDU, 17570 reg: regInfo{ 17571 inputs: []inputInfo{ 17572 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17573 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17574 }, 17575 outputs: []outputInfo{ 17576 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17577 }, 17578 }, 17579 }, 17580 { 17581 name: "DIVWU", 17582 argLen: 2, 17583 asm: ppc64.ADIVWU, 17584 reg: regInfo{ 17585 inputs: []inputInfo{ 17586 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17587 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17588 }, 17589 outputs: []outputInfo{ 17590 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17591 }, 17592 }, 17593 }, 17594 { 17595 name: "FCTIDZ", 17596 argLen: 1, 17597 asm: ppc64.AFCTIDZ, 17598 reg: regInfo{ 17599 inputs: []inputInfo{ 17600 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17601 }, 17602 outputs: []outputInfo{ 17603 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17604 }, 17605 }, 17606 }, 17607 { 17608 name: "FCTIWZ", 17609 argLen: 1, 17610 asm: ppc64.AFCTIWZ, 17611 reg: regInfo{ 17612 inputs: []inputInfo{ 17613 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17614 }, 17615 outputs: []outputInfo{ 17616 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17617 }, 17618 }, 17619 }, 17620 { 17621 name: "FCFID", 17622 argLen: 1, 17623 asm: ppc64.AFCFID, 17624 reg: regInfo{ 17625 inputs: []inputInfo{ 17626 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17627 }, 17628 outputs: []outputInfo{ 17629 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17630 }, 17631 }, 17632 }, 17633 { 17634 name: "FCFIDS", 17635 argLen: 1, 17636 asm: ppc64.AFCFIDS, 17637 reg: regInfo{ 17638 inputs: []inputInfo{ 17639 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17640 }, 17641 outputs: []outputInfo{ 17642 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17643 }, 17644 }, 17645 }, 17646 { 17647 name: "FRSP", 17648 argLen: 1, 17649 asm: ppc64.AFRSP, 17650 reg: regInfo{ 17651 inputs: []inputInfo{ 17652 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17653 }, 17654 outputs: []outputInfo{ 17655 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17656 }, 17657 }, 17658 }, 17659 { 17660 name: "MFVSRD", 17661 argLen: 1, 17662 asm: ppc64.AMFVSRD, 17663 reg: regInfo{ 17664 inputs: []inputInfo{ 17665 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17666 }, 17667 outputs: []outputInfo{ 17668 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17669 }, 17670 }, 17671 }, 17672 { 17673 name: "MTVSRD", 17674 argLen: 1, 17675 asm: ppc64.AMTVSRD, 17676 reg: regInfo{ 17677 inputs: []inputInfo{ 17678 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17679 }, 17680 outputs: []outputInfo{ 17681 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17682 }, 17683 }, 17684 }, 17685 { 17686 name: "AND", 17687 argLen: 2, 17688 commutative: true, 17689 asm: ppc64.AAND, 17690 reg: regInfo{ 17691 inputs: []inputInfo{ 17692 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17693 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17694 }, 17695 outputs: []outputInfo{ 17696 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17697 }, 17698 }, 17699 }, 17700 { 17701 name: "ANDN", 17702 argLen: 2, 17703 asm: ppc64.AANDN, 17704 reg: regInfo{ 17705 inputs: []inputInfo{ 17706 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17707 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17708 }, 17709 outputs: []outputInfo{ 17710 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17711 }, 17712 }, 17713 }, 17714 { 17715 name: "OR", 17716 argLen: 2, 17717 commutative: true, 17718 asm: ppc64.AOR, 17719 reg: regInfo{ 17720 inputs: []inputInfo{ 17721 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17722 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17723 }, 17724 outputs: []outputInfo{ 17725 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17726 }, 17727 }, 17728 }, 17729 { 17730 name: "ORN", 17731 argLen: 2, 17732 asm: ppc64.AORN, 17733 reg: regInfo{ 17734 inputs: []inputInfo{ 17735 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17736 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17737 }, 17738 outputs: []outputInfo{ 17739 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17740 }, 17741 }, 17742 }, 17743 { 17744 name: "NOR", 17745 argLen: 2, 17746 commutative: true, 17747 asm: ppc64.ANOR, 17748 reg: regInfo{ 17749 inputs: []inputInfo{ 17750 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17751 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17752 }, 17753 outputs: []outputInfo{ 17754 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17755 }, 17756 }, 17757 }, 17758 { 17759 name: "XOR", 17760 argLen: 2, 17761 commutative: true, 17762 asm: ppc64.AXOR, 17763 reg: regInfo{ 17764 inputs: []inputInfo{ 17765 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17766 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17767 }, 17768 outputs: []outputInfo{ 17769 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17770 }, 17771 }, 17772 }, 17773 { 17774 name: "EQV", 17775 argLen: 2, 17776 commutative: true, 17777 asm: ppc64.AEQV, 17778 reg: regInfo{ 17779 inputs: []inputInfo{ 17780 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17781 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17782 }, 17783 outputs: []outputInfo{ 17784 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17785 }, 17786 }, 17787 }, 17788 { 17789 name: "NEG", 17790 argLen: 1, 17791 asm: ppc64.ANEG, 17792 reg: regInfo{ 17793 inputs: []inputInfo{ 17794 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17795 }, 17796 outputs: []outputInfo{ 17797 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17798 }, 17799 }, 17800 }, 17801 { 17802 name: "FNEG", 17803 argLen: 1, 17804 asm: ppc64.AFNEG, 17805 reg: regInfo{ 17806 inputs: []inputInfo{ 17807 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17808 }, 17809 outputs: []outputInfo{ 17810 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17811 }, 17812 }, 17813 }, 17814 { 17815 name: "FSQRT", 17816 argLen: 1, 17817 asm: ppc64.AFSQRT, 17818 reg: regInfo{ 17819 inputs: []inputInfo{ 17820 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17821 }, 17822 outputs: []outputInfo{ 17823 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17824 }, 17825 }, 17826 }, 17827 { 17828 name: "FSQRTS", 17829 argLen: 1, 17830 asm: ppc64.AFSQRTS, 17831 reg: regInfo{ 17832 inputs: []inputInfo{ 17833 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17834 }, 17835 outputs: []outputInfo{ 17836 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17837 }, 17838 }, 17839 }, 17840 { 17841 name: "FFLOOR", 17842 argLen: 1, 17843 asm: ppc64.AFRIM, 17844 reg: regInfo{ 17845 inputs: []inputInfo{ 17846 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17847 }, 17848 outputs: []outputInfo{ 17849 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17850 }, 17851 }, 17852 }, 17853 { 17854 name: "FCEIL", 17855 argLen: 1, 17856 asm: ppc64.AFRIP, 17857 reg: regInfo{ 17858 inputs: []inputInfo{ 17859 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17860 }, 17861 outputs: []outputInfo{ 17862 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17863 }, 17864 }, 17865 }, 17866 { 17867 name: "FTRUNC", 17868 argLen: 1, 17869 asm: ppc64.AFRIZ, 17870 reg: regInfo{ 17871 inputs: []inputInfo{ 17872 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17873 }, 17874 outputs: []outputInfo{ 17875 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17876 }, 17877 }, 17878 }, 17879 { 17880 name: "ORconst", 17881 auxType: auxInt64, 17882 argLen: 1, 17883 asm: ppc64.AOR, 17884 reg: regInfo{ 17885 inputs: []inputInfo{ 17886 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17887 }, 17888 outputs: []outputInfo{ 17889 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17890 }, 17891 }, 17892 }, 17893 { 17894 name: "XORconst", 17895 auxType: auxInt64, 17896 argLen: 1, 17897 asm: ppc64.AXOR, 17898 reg: regInfo{ 17899 inputs: []inputInfo{ 17900 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17901 }, 17902 outputs: []outputInfo{ 17903 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17904 }, 17905 }, 17906 }, 17907 { 17908 name: "ANDconst", 17909 auxType: auxInt64, 17910 argLen: 1, 17911 clobberFlags: true, 17912 asm: ppc64.AANDCC, 17913 reg: regInfo{ 17914 inputs: []inputInfo{ 17915 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17916 }, 17917 outputs: []outputInfo{ 17918 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17919 }, 17920 }, 17921 }, 17922 { 17923 name: "ANDCCconst", 17924 auxType: auxInt64, 17925 argLen: 1, 17926 asm: ppc64.AANDCC, 17927 reg: regInfo{ 17928 inputs: []inputInfo{ 17929 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17930 }, 17931 }, 17932 }, 17933 { 17934 name: "MOVBreg", 17935 argLen: 1, 17936 asm: ppc64.AMOVB, 17937 reg: regInfo{ 17938 inputs: []inputInfo{ 17939 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17940 }, 17941 outputs: []outputInfo{ 17942 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17943 }, 17944 }, 17945 }, 17946 { 17947 name: "MOVBZreg", 17948 argLen: 1, 17949 asm: ppc64.AMOVBZ, 17950 reg: regInfo{ 17951 inputs: []inputInfo{ 17952 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17953 }, 17954 outputs: []outputInfo{ 17955 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17956 }, 17957 }, 17958 }, 17959 { 17960 name: "MOVHreg", 17961 argLen: 1, 17962 asm: ppc64.AMOVH, 17963 reg: regInfo{ 17964 inputs: []inputInfo{ 17965 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17966 }, 17967 outputs: []outputInfo{ 17968 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17969 }, 17970 }, 17971 }, 17972 { 17973 name: "MOVHZreg", 17974 argLen: 1, 17975 asm: ppc64.AMOVHZ, 17976 reg: regInfo{ 17977 inputs: []inputInfo{ 17978 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17979 }, 17980 outputs: []outputInfo{ 17981 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17982 }, 17983 }, 17984 }, 17985 { 17986 name: "MOVWreg", 17987 argLen: 1, 17988 asm: ppc64.AMOVW, 17989 reg: regInfo{ 17990 inputs: []inputInfo{ 17991 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17992 }, 17993 outputs: []outputInfo{ 17994 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17995 }, 17996 }, 17997 }, 17998 { 17999 name: "MOVWZreg", 18000 argLen: 1, 18001 asm: ppc64.AMOVWZ, 18002 reg: regInfo{ 18003 inputs: []inputInfo{ 18004 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18005 }, 18006 outputs: []outputInfo{ 18007 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18008 }, 18009 }, 18010 }, 18011 { 18012 name: "MOVBZload", 18013 auxType: auxSymOff, 18014 argLen: 2, 18015 faultOnNilArg0: true, 18016 symEffect: SymRead, 18017 asm: ppc64.AMOVBZ, 18018 reg: regInfo{ 18019 inputs: []inputInfo{ 18020 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18021 }, 18022 outputs: []outputInfo{ 18023 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18024 }, 18025 }, 18026 }, 18027 { 18028 name: "MOVHload", 18029 auxType: auxSymOff, 18030 argLen: 2, 18031 faultOnNilArg0: true, 18032 symEffect: SymRead, 18033 asm: ppc64.AMOVH, 18034 reg: regInfo{ 18035 inputs: []inputInfo{ 18036 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18037 }, 18038 outputs: []outputInfo{ 18039 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18040 }, 18041 }, 18042 }, 18043 { 18044 name: "MOVHZload", 18045 auxType: auxSymOff, 18046 argLen: 2, 18047 faultOnNilArg0: true, 18048 symEffect: SymRead, 18049 asm: ppc64.AMOVHZ, 18050 reg: regInfo{ 18051 inputs: []inputInfo{ 18052 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18053 }, 18054 outputs: []outputInfo{ 18055 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18056 }, 18057 }, 18058 }, 18059 { 18060 name: "MOVWload", 18061 auxType: auxSymOff, 18062 argLen: 2, 18063 faultOnNilArg0: true, 18064 symEffect: SymRead, 18065 asm: ppc64.AMOVW, 18066 reg: regInfo{ 18067 inputs: []inputInfo{ 18068 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18069 }, 18070 outputs: []outputInfo{ 18071 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18072 }, 18073 }, 18074 }, 18075 { 18076 name: "MOVWZload", 18077 auxType: auxSymOff, 18078 argLen: 2, 18079 faultOnNilArg0: true, 18080 symEffect: SymRead, 18081 asm: ppc64.AMOVWZ, 18082 reg: regInfo{ 18083 inputs: []inputInfo{ 18084 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18085 }, 18086 outputs: []outputInfo{ 18087 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18088 }, 18089 }, 18090 }, 18091 { 18092 name: "MOVDload", 18093 auxType: auxSymOff, 18094 argLen: 2, 18095 faultOnNilArg0: true, 18096 symEffect: SymRead, 18097 asm: ppc64.AMOVD, 18098 reg: regInfo{ 18099 inputs: []inputInfo{ 18100 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18101 }, 18102 outputs: []outputInfo{ 18103 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18104 }, 18105 }, 18106 }, 18107 { 18108 name: "FMOVDload", 18109 auxType: auxSymOff, 18110 argLen: 2, 18111 faultOnNilArg0: true, 18112 symEffect: SymRead, 18113 asm: ppc64.AFMOVD, 18114 reg: regInfo{ 18115 inputs: []inputInfo{ 18116 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18117 }, 18118 outputs: []outputInfo{ 18119 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18120 }, 18121 }, 18122 }, 18123 { 18124 name: "FMOVSload", 18125 auxType: auxSymOff, 18126 argLen: 2, 18127 faultOnNilArg0: true, 18128 symEffect: SymRead, 18129 asm: ppc64.AFMOVS, 18130 reg: regInfo{ 18131 inputs: []inputInfo{ 18132 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18133 }, 18134 outputs: []outputInfo{ 18135 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18136 }, 18137 }, 18138 }, 18139 { 18140 name: "MOVBstore", 18141 auxType: auxSymOff, 18142 argLen: 3, 18143 faultOnNilArg0: true, 18144 symEffect: SymWrite, 18145 asm: ppc64.AMOVB, 18146 reg: regInfo{ 18147 inputs: []inputInfo{ 18148 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18149 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18150 }, 18151 }, 18152 }, 18153 { 18154 name: "MOVHstore", 18155 auxType: auxSymOff, 18156 argLen: 3, 18157 faultOnNilArg0: true, 18158 symEffect: SymWrite, 18159 asm: ppc64.AMOVH, 18160 reg: regInfo{ 18161 inputs: []inputInfo{ 18162 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18163 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18164 }, 18165 }, 18166 }, 18167 { 18168 name: "MOVWstore", 18169 auxType: auxSymOff, 18170 argLen: 3, 18171 faultOnNilArg0: true, 18172 symEffect: SymWrite, 18173 asm: ppc64.AMOVW, 18174 reg: regInfo{ 18175 inputs: []inputInfo{ 18176 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18177 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18178 }, 18179 }, 18180 }, 18181 { 18182 name: "MOVDstore", 18183 auxType: auxSymOff, 18184 argLen: 3, 18185 faultOnNilArg0: true, 18186 symEffect: SymWrite, 18187 asm: ppc64.AMOVD, 18188 reg: regInfo{ 18189 inputs: []inputInfo{ 18190 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18191 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18192 }, 18193 }, 18194 }, 18195 { 18196 name: "FMOVDstore", 18197 auxType: auxSymOff, 18198 argLen: 3, 18199 faultOnNilArg0: true, 18200 symEffect: SymWrite, 18201 asm: ppc64.AFMOVD, 18202 reg: regInfo{ 18203 inputs: []inputInfo{ 18204 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18205 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18206 }, 18207 }, 18208 }, 18209 { 18210 name: "FMOVSstore", 18211 auxType: auxSymOff, 18212 argLen: 3, 18213 faultOnNilArg0: true, 18214 symEffect: SymWrite, 18215 asm: ppc64.AFMOVS, 18216 reg: regInfo{ 18217 inputs: []inputInfo{ 18218 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18219 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18220 }, 18221 }, 18222 }, 18223 { 18224 name: "MOVBstorezero", 18225 auxType: auxSymOff, 18226 argLen: 2, 18227 faultOnNilArg0: true, 18228 symEffect: SymWrite, 18229 asm: ppc64.AMOVB, 18230 reg: regInfo{ 18231 inputs: []inputInfo{ 18232 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18233 }, 18234 }, 18235 }, 18236 { 18237 name: "MOVHstorezero", 18238 auxType: auxSymOff, 18239 argLen: 2, 18240 faultOnNilArg0: true, 18241 symEffect: SymWrite, 18242 asm: ppc64.AMOVH, 18243 reg: regInfo{ 18244 inputs: []inputInfo{ 18245 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18246 }, 18247 }, 18248 }, 18249 { 18250 name: "MOVWstorezero", 18251 auxType: auxSymOff, 18252 argLen: 2, 18253 faultOnNilArg0: true, 18254 symEffect: SymWrite, 18255 asm: ppc64.AMOVW, 18256 reg: regInfo{ 18257 inputs: []inputInfo{ 18258 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18259 }, 18260 }, 18261 }, 18262 { 18263 name: "MOVDstorezero", 18264 auxType: auxSymOff, 18265 argLen: 2, 18266 faultOnNilArg0: true, 18267 symEffect: SymWrite, 18268 asm: ppc64.AMOVD, 18269 reg: regInfo{ 18270 inputs: []inputInfo{ 18271 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18272 }, 18273 }, 18274 }, 18275 { 18276 name: "MOVDaddr", 18277 auxType: auxSymOff, 18278 argLen: 1, 18279 rematerializeable: true, 18280 symEffect: SymAddr, 18281 asm: ppc64.AMOVD, 18282 reg: regInfo{ 18283 inputs: []inputInfo{ 18284 {0, 6}, // SP SB 18285 }, 18286 outputs: []outputInfo{ 18287 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18288 }, 18289 }, 18290 }, 18291 { 18292 name: "MOVDconst", 18293 auxType: auxInt64, 18294 argLen: 0, 18295 rematerializeable: true, 18296 asm: ppc64.AMOVD, 18297 reg: regInfo{ 18298 outputs: []outputInfo{ 18299 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18300 }, 18301 }, 18302 }, 18303 { 18304 name: "FMOVDconst", 18305 auxType: auxFloat64, 18306 argLen: 0, 18307 rematerializeable: true, 18308 asm: ppc64.AFMOVD, 18309 reg: regInfo{ 18310 outputs: []outputInfo{ 18311 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18312 }, 18313 }, 18314 }, 18315 { 18316 name: "FMOVSconst", 18317 auxType: auxFloat32, 18318 argLen: 0, 18319 rematerializeable: true, 18320 asm: ppc64.AFMOVS, 18321 reg: regInfo{ 18322 outputs: []outputInfo{ 18323 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18324 }, 18325 }, 18326 }, 18327 { 18328 name: "FCMPU", 18329 argLen: 2, 18330 asm: ppc64.AFCMPU, 18331 reg: regInfo{ 18332 inputs: []inputInfo{ 18333 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18334 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18335 }, 18336 }, 18337 }, 18338 { 18339 name: "CMP", 18340 argLen: 2, 18341 asm: ppc64.ACMP, 18342 reg: regInfo{ 18343 inputs: []inputInfo{ 18344 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18345 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18346 }, 18347 }, 18348 }, 18349 { 18350 name: "CMPU", 18351 argLen: 2, 18352 asm: ppc64.ACMPU, 18353 reg: regInfo{ 18354 inputs: []inputInfo{ 18355 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18356 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18357 }, 18358 }, 18359 }, 18360 { 18361 name: "CMPW", 18362 argLen: 2, 18363 asm: ppc64.ACMPW, 18364 reg: regInfo{ 18365 inputs: []inputInfo{ 18366 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18367 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18368 }, 18369 }, 18370 }, 18371 { 18372 name: "CMPWU", 18373 argLen: 2, 18374 asm: ppc64.ACMPWU, 18375 reg: regInfo{ 18376 inputs: []inputInfo{ 18377 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18378 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18379 }, 18380 }, 18381 }, 18382 { 18383 name: "CMPconst", 18384 auxType: auxInt64, 18385 argLen: 1, 18386 asm: ppc64.ACMP, 18387 reg: regInfo{ 18388 inputs: []inputInfo{ 18389 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18390 }, 18391 }, 18392 }, 18393 { 18394 name: "CMPUconst", 18395 auxType: auxInt64, 18396 argLen: 1, 18397 asm: ppc64.ACMPU, 18398 reg: regInfo{ 18399 inputs: []inputInfo{ 18400 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18401 }, 18402 }, 18403 }, 18404 { 18405 name: "CMPWconst", 18406 auxType: auxInt32, 18407 argLen: 1, 18408 asm: ppc64.ACMPW, 18409 reg: regInfo{ 18410 inputs: []inputInfo{ 18411 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18412 }, 18413 }, 18414 }, 18415 { 18416 name: "CMPWUconst", 18417 auxType: auxInt32, 18418 argLen: 1, 18419 asm: ppc64.ACMPWU, 18420 reg: regInfo{ 18421 inputs: []inputInfo{ 18422 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18423 }, 18424 }, 18425 }, 18426 { 18427 name: "Equal", 18428 argLen: 1, 18429 reg: regInfo{ 18430 outputs: []outputInfo{ 18431 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18432 }, 18433 }, 18434 }, 18435 { 18436 name: "NotEqual", 18437 argLen: 1, 18438 reg: regInfo{ 18439 outputs: []outputInfo{ 18440 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18441 }, 18442 }, 18443 }, 18444 { 18445 name: "LessThan", 18446 argLen: 1, 18447 reg: regInfo{ 18448 outputs: []outputInfo{ 18449 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18450 }, 18451 }, 18452 }, 18453 { 18454 name: "FLessThan", 18455 argLen: 1, 18456 reg: regInfo{ 18457 outputs: []outputInfo{ 18458 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18459 }, 18460 }, 18461 }, 18462 { 18463 name: "LessEqual", 18464 argLen: 1, 18465 reg: regInfo{ 18466 outputs: []outputInfo{ 18467 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18468 }, 18469 }, 18470 }, 18471 { 18472 name: "FLessEqual", 18473 argLen: 1, 18474 reg: regInfo{ 18475 outputs: []outputInfo{ 18476 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18477 }, 18478 }, 18479 }, 18480 { 18481 name: "GreaterThan", 18482 argLen: 1, 18483 reg: regInfo{ 18484 outputs: []outputInfo{ 18485 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18486 }, 18487 }, 18488 }, 18489 { 18490 name: "FGreaterThan", 18491 argLen: 1, 18492 reg: regInfo{ 18493 outputs: []outputInfo{ 18494 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18495 }, 18496 }, 18497 }, 18498 { 18499 name: "GreaterEqual", 18500 argLen: 1, 18501 reg: regInfo{ 18502 outputs: []outputInfo{ 18503 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18504 }, 18505 }, 18506 }, 18507 { 18508 name: "FGreaterEqual", 18509 argLen: 1, 18510 reg: regInfo{ 18511 outputs: []outputInfo{ 18512 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18513 }, 18514 }, 18515 }, 18516 { 18517 name: "LoweredGetClosurePtr", 18518 argLen: 0, 18519 reg: regInfo{ 18520 outputs: []outputInfo{ 18521 {0, 2048}, // R11 18522 }, 18523 }, 18524 }, 18525 { 18526 name: "LoweredGetCallerSP", 18527 argLen: 0, 18528 rematerializeable: true, 18529 reg: regInfo{ 18530 outputs: []outputInfo{ 18531 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18532 }, 18533 }, 18534 }, 18535 { 18536 name: "LoweredNilCheck", 18537 argLen: 2, 18538 clobberFlags: true, 18539 nilCheck: true, 18540 faultOnNilArg0: true, 18541 reg: regInfo{ 18542 inputs: []inputInfo{ 18543 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18544 }, 18545 clobbers: 2147483648, // R31 18546 }, 18547 }, 18548 { 18549 name: "LoweredRound32F", 18550 argLen: 1, 18551 resultInArg0: true, 18552 reg: regInfo{ 18553 inputs: []inputInfo{ 18554 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18555 }, 18556 outputs: []outputInfo{ 18557 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18558 }, 18559 }, 18560 }, 18561 { 18562 name: "LoweredRound64F", 18563 argLen: 1, 18564 resultInArg0: true, 18565 reg: regInfo{ 18566 inputs: []inputInfo{ 18567 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18568 }, 18569 outputs: []outputInfo{ 18570 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18571 }, 18572 }, 18573 }, 18574 { 18575 name: "MOVDconvert", 18576 argLen: 2, 18577 asm: ppc64.AMOVD, 18578 reg: regInfo{ 18579 inputs: []inputInfo{ 18580 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18581 }, 18582 outputs: []outputInfo{ 18583 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18584 }, 18585 }, 18586 }, 18587 { 18588 name: "CALLstatic", 18589 auxType: auxSymOff, 18590 argLen: 1, 18591 clobberFlags: true, 18592 call: true, 18593 symEffect: SymNone, 18594 reg: regInfo{ 18595 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18596 }, 18597 }, 18598 { 18599 name: "CALLclosure", 18600 auxType: auxInt64, 18601 argLen: 3, 18602 clobberFlags: true, 18603 call: true, 18604 reg: regInfo{ 18605 inputs: []inputInfo{ 18606 {0, 4096}, // R12 18607 {1, 2048}, // R11 18608 }, 18609 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18610 }, 18611 }, 18612 { 18613 name: "CALLinter", 18614 auxType: auxInt64, 18615 argLen: 2, 18616 clobberFlags: true, 18617 call: true, 18618 reg: regInfo{ 18619 inputs: []inputInfo{ 18620 {0, 4096}, // R12 18621 }, 18622 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18623 }, 18624 }, 18625 { 18626 name: "LoweredZero", 18627 auxType: auxInt64, 18628 argLen: 2, 18629 clobberFlags: true, 18630 faultOnNilArg0: true, 18631 reg: regInfo{ 18632 inputs: []inputInfo{ 18633 {0, 8}, // R3 18634 }, 18635 clobbers: 8, // R3 18636 }, 18637 }, 18638 { 18639 name: "LoweredMove", 18640 auxType: auxInt64, 18641 argLen: 3, 18642 clobberFlags: true, 18643 faultOnNilArg0: true, 18644 faultOnNilArg1: true, 18645 reg: regInfo{ 18646 inputs: []inputInfo{ 18647 {0, 8}, // R3 18648 {1, 16}, // R4 18649 }, 18650 clobbers: 1944, // R3 R4 R7 R8 R9 R10 18651 }, 18652 }, 18653 { 18654 name: "LoweredAtomicStore32", 18655 argLen: 3, 18656 faultOnNilArg0: true, 18657 hasSideEffects: true, 18658 reg: regInfo{ 18659 inputs: []inputInfo{ 18660 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18661 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18662 }, 18663 }, 18664 }, 18665 { 18666 name: "LoweredAtomicStore64", 18667 argLen: 3, 18668 faultOnNilArg0: true, 18669 hasSideEffects: true, 18670 reg: regInfo{ 18671 inputs: []inputInfo{ 18672 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18673 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18674 }, 18675 }, 18676 }, 18677 { 18678 name: "LoweredAtomicLoad32", 18679 argLen: 2, 18680 clobberFlags: true, 18681 faultOnNilArg0: true, 18682 reg: regInfo{ 18683 inputs: []inputInfo{ 18684 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18685 }, 18686 outputs: []outputInfo{ 18687 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18688 }, 18689 }, 18690 }, 18691 { 18692 name: "LoweredAtomicLoad64", 18693 argLen: 2, 18694 clobberFlags: true, 18695 faultOnNilArg0: true, 18696 reg: regInfo{ 18697 inputs: []inputInfo{ 18698 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18699 }, 18700 outputs: []outputInfo{ 18701 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18702 }, 18703 }, 18704 }, 18705 { 18706 name: "LoweredAtomicLoadPtr", 18707 argLen: 2, 18708 clobberFlags: true, 18709 faultOnNilArg0: true, 18710 reg: regInfo{ 18711 inputs: []inputInfo{ 18712 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18713 }, 18714 outputs: []outputInfo{ 18715 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18716 }, 18717 }, 18718 }, 18719 { 18720 name: "LoweredAtomicAdd32", 18721 argLen: 3, 18722 resultNotInArgs: true, 18723 clobberFlags: true, 18724 faultOnNilArg0: true, 18725 hasSideEffects: true, 18726 reg: regInfo{ 18727 inputs: []inputInfo{ 18728 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18729 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18730 }, 18731 outputs: []outputInfo{ 18732 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18733 }, 18734 }, 18735 }, 18736 { 18737 name: "LoweredAtomicAdd64", 18738 argLen: 3, 18739 resultNotInArgs: true, 18740 clobberFlags: true, 18741 faultOnNilArg0: true, 18742 hasSideEffects: true, 18743 reg: regInfo{ 18744 inputs: []inputInfo{ 18745 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18746 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18747 }, 18748 outputs: []outputInfo{ 18749 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18750 }, 18751 }, 18752 }, 18753 { 18754 name: "LoweredAtomicExchange32", 18755 argLen: 3, 18756 resultNotInArgs: true, 18757 clobberFlags: true, 18758 faultOnNilArg0: true, 18759 hasSideEffects: true, 18760 reg: regInfo{ 18761 inputs: []inputInfo{ 18762 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18763 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18764 }, 18765 outputs: []outputInfo{ 18766 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18767 }, 18768 }, 18769 }, 18770 { 18771 name: "LoweredAtomicExchange64", 18772 argLen: 3, 18773 resultNotInArgs: true, 18774 clobberFlags: true, 18775 faultOnNilArg0: true, 18776 hasSideEffects: true, 18777 reg: regInfo{ 18778 inputs: []inputInfo{ 18779 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18780 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18781 }, 18782 outputs: []outputInfo{ 18783 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18784 }, 18785 }, 18786 }, 18787 { 18788 name: "LoweredAtomicCas64", 18789 argLen: 4, 18790 resultNotInArgs: true, 18791 clobberFlags: true, 18792 faultOnNilArg0: true, 18793 hasSideEffects: true, 18794 reg: regInfo{ 18795 inputs: []inputInfo{ 18796 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18797 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18798 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18799 }, 18800 outputs: []outputInfo{ 18801 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18802 }, 18803 }, 18804 }, 18805 { 18806 name: "LoweredAtomicCas32", 18807 argLen: 4, 18808 resultNotInArgs: true, 18809 clobberFlags: true, 18810 faultOnNilArg0: true, 18811 hasSideEffects: true, 18812 reg: regInfo{ 18813 inputs: []inputInfo{ 18814 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18815 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18816 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18817 }, 18818 outputs: []outputInfo{ 18819 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18820 }, 18821 }, 18822 }, 18823 { 18824 name: "LoweredAtomicAnd8", 18825 argLen: 3, 18826 faultOnNilArg0: true, 18827 hasSideEffects: true, 18828 asm: ppc64.AAND, 18829 reg: regInfo{ 18830 inputs: []inputInfo{ 18831 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18832 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18833 }, 18834 }, 18835 }, 18836 { 18837 name: "LoweredAtomicOr8", 18838 argLen: 3, 18839 faultOnNilArg0: true, 18840 hasSideEffects: true, 18841 asm: ppc64.AOR, 18842 reg: regInfo{ 18843 inputs: []inputInfo{ 18844 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18845 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18846 }, 18847 }, 18848 }, 18849 { 18850 name: "InvertFlags", 18851 argLen: 1, 18852 reg: regInfo{}, 18853 }, 18854 { 18855 name: "FlagEQ", 18856 argLen: 0, 18857 reg: regInfo{}, 18858 }, 18859 { 18860 name: "FlagLT", 18861 argLen: 0, 18862 reg: regInfo{}, 18863 }, 18864 { 18865 name: "FlagGT", 18866 argLen: 0, 18867 reg: regInfo{}, 18868 }, 18869 18870 { 18871 name: "FADDS", 18872 argLen: 2, 18873 commutative: true, 18874 resultInArg0: true, 18875 clobberFlags: true, 18876 asm: s390x.AFADDS, 18877 reg: regInfo{ 18878 inputs: []inputInfo{ 18879 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18880 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18881 }, 18882 outputs: []outputInfo{ 18883 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18884 }, 18885 }, 18886 }, 18887 { 18888 name: "FADD", 18889 argLen: 2, 18890 commutative: true, 18891 resultInArg0: true, 18892 clobberFlags: true, 18893 asm: s390x.AFADD, 18894 reg: regInfo{ 18895 inputs: []inputInfo{ 18896 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18897 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18898 }, 18899 outputs: []outputInfo{ 18900 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18901 }, 18902 }, 18903 }, 18904 { 18905 name: "FSUBS", 18906 argLen: 2, 18907 resultInArg0: true, 18908 clobberFlags: true, 18909 asm: s390x.AFSUBS, 18910 reg: regInfo{ 18911 inputs: []inputInfo{ 18912 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18913 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18914 }, 18915 outputs: []outputInfo{ 18916 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18917 }, 18918 }, 18919 }, 18920 { 18921 name: "FSUB", 18922 argLen: 2, 18923 resultInArg0: true, 18924 clobberFlags: true, 18925 asm: s390x.AFSUB, 18926 reg: regInfo{ 18927 inputs: []inputInfo{ 18928 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18929 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18930 }, 18931 outputs: []outputInfo{ 18932 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18933 }, 18934 }, 18935 }, 18936 { 18937 name: "FMULS", 18938 argLen: 2, 18939 commutative: true, 18940 resultInArg0: true, 18941 asm: s390x.AFMULS, 18942 reg: regInfo{ 18943 inputs: []inputInfo{ 18944 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18945 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18946 }, 18947 outputs: []outputInfo{ 18948 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18949 }, 18950 }, 18951 }, 18952 { 18953 name: "FMUL", 18954 argLen: 2, 18955 commutative: true, 18956 resultInArg0: true, 18957 asm: s390x.AFMUL, 18958 reg: regInfo{ 18959 inputs: []inputInfo{ 18960 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18961 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18962 }, 18963 outputs: []outputInfo{ 18964 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18965 }, 18966 }, 18967 }, 18968 { 18969 name: "FDIVS", 18970 argLen: 2, 18971 resultInArg0: true, 18972 asm: s390x.AFDIVS, 18973 reg: regInfo{ 18974 inputs: []inputInfo{ 18975 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18976 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18977 }, 18978 outputs: []outputInfo{ 18979 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18980 }, 18981 }, 18982 }, 18983 { 18984 name: "FDIV", 18985 argLen: 2, 18986 resultInArg0: true, 18987 asm: s390x.AFDIV, 18988 reg: regInfo{ 18989 inputs: []inputInfo{ 18990 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18991 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18992 }, 18993 outputs: []outputInfo{ 18994 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18995 }, 18996 }, 18997 }, 18998 { 18999 name: "FNEGS", 19000 argLen: 1, 19001 clobberFlags: true, 19002 asm: s390x.AFNEGS, 19003 reg: regInfo{ 19004 inputs: []inputInfo{ 19005 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19006 }, 19007 outputs: []outputInfo{ 19008 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19009 }, 19010 }, 19011 }, 19012 { 19013 name: "FNEG", 19014 argLen: 1, 19015 clobberFlags: true, 19016 asm: s390x.AFNEG, 19017 reg: regInfo{ 19018 inputs: []inputInfo{ 19019 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19020 }, 19021 outputs: []outputInfo{ 19022 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19023 }, 19024 }, 19025 }, 19026 { 19027 name: "FMADDS", 19028 argLen: 3, 19029 resultInArg0: true, 19030 asm: s390x.AFMADDS, 19031 reg: regInfo{ 19032 inputs: []inputInfo{ 19033 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19034 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19035 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19036 }, 19037 outputs: []outputInfo{ 19038 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19039 }, 19040 }, 19041 }, 19042 { 19043 name: "FMADD", 19044 argLen: 3, 19045 resultInArg0: true, 19046 asm: s390x.AFMADD, 19047 reg: regInfo{ 19048 inputs: []inputInfo{ 19049 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19050 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19051 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19052 }, 19053 outputs: []outputInfo{ 19054 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19055 }, 19056 }, 19057 }, 19058 { 19059 name: "FMSUBS", 19060 argLen: 3, 19061 resultInArg0: true, 19062 asm: s390x.AFMSUBS, 19063 reg: regInfo{ 19064 inputs: []inputInfo{ 19065 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19066 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19067 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19068 }, 19069 outputs: []outputInfo{ 19070 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19071 }, 19072 }, 19073 }, 19074 { 19075 name: "FMSUB", 19076 argLen: 3, 19077 resultInArg0: true, 19078 asm: s390x.AFMSUB, 19079 reg: regInfo{ 19080 inputs: []inputInfo{ 19081 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19082 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19083 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19084 }, 19085 outputs: []outputInfo{ 19086 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19087 }, 19088 }, 19089 }, 19090 { 19091 name: "FIDBR", 19092 auxType: auxInt8, 19093 argLen: 1, 19094 asm: s390x.AFIDBR, 19095 reg: regInfo{ 19096 inputs: []inputInfo{ 19097 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19098 }, 19099 outputs: []outputInfo{ 19100 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19101 }, 19102 }, 19103 }, 19104 { 19105 name: "FMOVSload", 19106 auxType: auxSymOff, 19107 argLen: 2, 19108 faultOnNilArg0: true, 19109 symEffect: SymRead, 19110 asm: s390x.AFMOVS, 19111 reg: regInfo{ 19112 inputs: []inputInfo{ 19113 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19114 }, 19115 outputs: []outputInfo{ 19116 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19117 }, 19118 }, 19119 }, 19120 { 19121 name: "FMOVDload", 19122 auxType: auxSymOff, 19123 argLen: 2, 19124 faultOnNilArg0: true, 19125 symEffect: SymRead, 19126 asm: s390x.AFMOVD, 19127 reg: regInfo{ 19128 inputs: []inputInfo{ 19129 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19130 }, 19131 outputs: []outputInfo{ 19132 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19133 }, 19134 }, 19135 }, 19136 { 19137 name: "FMOVSconst", 19138 auxType: auxFloat32, 19139 argLen: 0, 19140 rematerializeable: true, 19141 asm: s390x.AFMOVS, 19142 reg: regInfo{ 19143 outputs: []outputInfo{ 19144 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19145 }, 19146 }, 19147 }, 19148 { 19149 name: "FMOVDconst", 19150 auxType: auxFloat64, 19151 argLen: 0, 19152 rematerializeable: true, 19153 asm: s390x.AFMOVD, 19154 reg: regInfo{ 19155 outputs: []outputInfo{ 19156 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19157 }, 19158 }, 19159 }, 19160 { 19161 name: "FMOVSloadidx", 19162 auxType: auxSymOff, 19163 argLen: 3, 19164 symEffect: SymRead, 19165 asm: s390x.AFMOVS, 19166 reg: regInfo{ 19167 inputs: []inputInfo{ 19168 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19169 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19170 }, 19171 outputs: []outputInfo{ 19172 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19173 }, 19174 }, 19175 }, 19176 { 19177 name: "FMOVDloadidx", 19178 auxType: auxSymOff, 19179 argLen: 3, 19180 symEffect: SymRead, 19181 asm: s390x.AFMOVD, 19182 reg: regInfo{ 19183 inputs: []inputInfo{ 19184 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19185 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19186 }, 19187 outputs: []outputInfo{ 19188 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19189 }, 19190 }, 19191 }, 19192 { 19193 name: "FMOVSstore", 19194 auxType: auxSymOff, 19195 argLen: 3, 19196 faultOnNilArg0: true, 19197 symEffect: SymWrite, 19198 asm: s390x.AFMOVS, 19199 reg: regInfo{ 19200 inputs: []inputInfo{ 19201 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19202 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19203 }, 19204 }, 19205 }, 19206 { 19207 name: "FMOVDstore", 19208 auxType: auxSymOff, 19209 argLen: 3, 19210 faultOnNilArg0: true, 19211 symEffect: SymWrite, 19212 asm: s390x.AFMOVD, 19213 reg: regInfo{ 19214 inputs: []inputInfo{ 19215 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19216 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19217 }, 19218 }, 19219 }, 19220 { 19221 name: "FMOVSstoreidx", 19222 auxType: auxSymOff, 19223 argLen: 4, 19224 symEffect: SymWrite, 19225 asm: s390x.AFMOVS, 19226 reg: regInfo{ 19227 inputs: []inputInfo{ 19228 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19229 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19230 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19231 }, 19232 }, 19233 }, 19234 { 19235 name: "FMOVDstoreidx", 19236 auxType: auxSymOff, 19237 argLen: 4, 19238 symEffect: SymWrite, 19239 asm: s390x.AFMOVD, 19240 reg: regInfo{ 19241 inputs: []inputInfo{ 19242 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19243 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19244 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19245 }, 19246 }, 19247 }, 19248 { 19249 name: "ADD", 19250 argLen: 2, 19251 commutative: true, 19252 clobberFlags: true, 19253 asm: s390x.AADD, 19254 reg: regInfo{ 19255 inputs: []inputInfo{ 19256 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19257 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19258 }, 19259 outputs: []outputInfo{ 19260 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19261 }, 19262 }, 19263 }, 19264 { 19265 name: "ADDW", 19266 argLen: 2, 19267 commutative: true, 19268 clobberFlags: true, 19269 asm: s390x.AADDW, 19270 reg: regInfo{ 19271 inputs: []inputInfo{ 19272 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19273 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19274 }, 19275 outputs: []outputInfo{ 19276 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19277 }, 19278 }, 19279 }, 19280 { 19281 name: "ADDconst", 19282 auxType: auxInt64, 19283 argLen: 1, 19284 clobberFlags: true, 19285 asm: s390x.AADD, 19286 reg: regInfo{ 19287 inputs: []inputInfo{ 19288 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19289 }, 19290 outputs: []outputInfo{ 19291 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19292 }, 19293 }, 19294 }, 19295 { 19296 name: "ADDWconst", 19297 auxType: auxInt32, 19298 argLen: 1, 19299 clobberFlags: true, 19300 asm: s390x.AADDW, 19301 reg: regInfo{ 19302 inputs: []inputInfo{ 19303 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19304 }, 19305 outputs: []outputInfo{ 19306 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19307 }, 19308 }, 19309 }, 19310 { 19311 name: "ADDload", 19312 auxType: auxSymOff, 19313 argLen: 3, 19314 resultInArg0: true, 19315 clobberFlags: true, 19316 faultOnNilArg1: true, 19317 symEffect: SymRead, 19318 asm: s390x.AADD, 19319 reg: regInfo{ 19320 inputs: []inputInfo{ 19321 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19322 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19323 }, 19324 outputs: []outputInfo{ 19325 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19326 }, 19327 }, 19328 }, 19329 { 19330 name: "ADDWload", 19331 auxType: auxSymOff, 19332 argLen: 3, 19333 resultInArg0: true, 19334 clobberFlags: true, 19335 faultOnNilArg1: true, 19336 symEffect: SymRead, 19337 asm: s390x.AADDW, 19338 reg: regInfo{ 19339 inputs: []inputInfo{ 19340 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19341 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19342 }, 19343 outputs: []outputInfo{ 19344 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19345 }, 19346 }, 19347 }, 19348 { 19349 name: "SUB", 19350 argLen: 2, 19351 clobberFlags: true, 19352 asm: s390x.ASUB, 19353 reg: regInfo{ 19354 inputs: []inputInfo{ 19355 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19356 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19357 }, 19358 outputs: []outputInfo{ 19359 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19360 }, 19361 }, 19362 }, 19363 { 19364 name: "SUBW", 19365 argLen: 2, 19366 clobberFlags: true, 19367 asm: s390x.ASUBW, 19368 reg: regInfo{ 19369 inputs: []inputInfo{ 19370 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19371 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19372 }, 19373 outputs: []outputInfo{ 19374 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19375 }, 19376 }, 19377 }, 19378 { 19379 name: "SUBconst", 19380 auxType: auxInt64, 19381 argLen: 1, 19382 resultInArg0: true, 19383 clobberFlags: true, 19384 asm: s390x.ASUB, 19385 reg: regInfo{ 19386 inputs: []inputInfo{ 19387 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19388 }, 19389 outputs: []outputInfo{ 19390 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19391 }, 19392 }, 19393 }, 19394 { 19395 name: "SUBWconst", 19396 auxType: auxInt32, 19397 argLen: 1, 19398 resultInArg0: true, 19399 clobberFlags: true, 19400 asm: s390x.ASUBW, 19401 reg: regInfo{ 19402 inputs: []inputInfo{ 19403 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19404 }, 19405 outputs: []outputInfo{ 19406 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19407 }, 19408 }, 19409 }, 19410 { 19411 name: "SUBload", 19412 auxType: auxSymOff, 19413 argLen: 3, 19414 resultInArg0: true, 19415 clobberFlags: true, 19416 faultOnNilArg1: true, 19417 symEffect: SymRead, 19418 asm: s390x.ASUB, 19419 reg: regInfo{ 19420 inputs: []inputInfo{ 19421 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19422 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19423 }, 19424 outputs: []outputInfo{ 19425 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19426 }, 19427 }, 19428 }, 19429 { 19430 name: "SUBWload", 19431 auxType: auxSymOff, 19432 argLen: 3, 19433 resultInArg0: true, 19434 clobberFlags: true, 19435 faultOnNilArg1: true, 19436 symEffect: SymRead, 19437 asm: s390x.ASUBW, 19438 reg: regInfo{ 19439 inputs: []inputInfo{ 19440 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19441 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19442 }, 19443 outputs: []outputInfo{ 19444 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19445 }, 19446 }, 19447 }, 19448 { 19449 name: "MULLD", 19450 argLen: 2, 19451 commutative: true, 19452 resultInArg0: true, 19453 clobberFlags: true, 19454 asm: s390x.AMULLD, 19455 reg: regInfo{ 19456 inputs: []inputInfo{ 19457 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19458 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19459 }, 19460 outputs: []outputInfo{ 19461 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19462 }, 19463 }, 19464 }, 19465 { 19466 name: "MULLW", 19467 argLen: 2, 19468 commutative: true, 19469 resultInArg0: true, 19470 clobberFlags: true, 19471 asm: s390x.AMULLW, 19472 reg: regInfo{ 19473 inputs: []inputInfo{ 19474 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19475 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19476 }, 19477 outputs: []outputInfo{ 19478 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19479 }, 19480 }, 19481 }, 19482 { 19483 name: "MULLDconst", 19484 auxType: auxInt64, 19485 argLen: 1, 19486 resultInArg0: true, 19487 clobberFlags: true, 19488 asm: s390x.AMULLD, 19489 reg: regInfo{ 19490 inputs: []inputInfo{ 19491 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19492 }, 19493 outputs: []outputInfo{ 19494 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19495 }, 19496 }, 19497 }, 19498 { 19499 name: "MULLWconst", 19500 auxType: auxInt32, 19501 argLen: 1, 19502 resultInArg0: true, 19503 clobberFlags: true, 19504 asm: s390x.AMULLW, 19505 reg: regInfo{ 19506 inputs: []inputInfo{ 19507 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19508 }, 19509 outputs: []outputInfo{ 19510 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19511 }, 19512 }, 19513 }, 19514 { 19515 name: "MULLDload", 19516 auxType: auxSymOff, 19517 argLen: 3, 19518 resultInArg0: true, 19519 clobberFlags: true, 19520 faultOnNilArg1: true, 19521 symEffect: SymRead, 19522 asm: s390x.AMULLD, 19523 reg: regInfo{ 19524 inputs: []inputInfo{ 19525 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19526 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19527 }, 19528 outputs: []outputInfo{ 19529 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19530 }, 19531 }, 19532 }, 19533 { 19534 name: "MULLWload", 19535 auxType: auxSymOff, 19536 argLen: 3, 19537 resultInArg0: true, 19538 clobberFlags: true, 19539 faultOnNilArg1: true, 19540 symEffect: SymRead, 19541 asm: s390x.AMULLW, 19542 reg: regInfo{ 19543 inputs: []inputInfo{ 19544 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19545 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19546 }, 19547 outputs: []outputInfo{ 19548 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19549 }, 19550 }, 19551 }, 19552 { 19553 name: "MULHD", 19554 argLen: 2, 19555 commutative: true, 19556 resultInArg0: true, 19557 clobberFlags: true, 19558 asm: s390x.AMULHD, 19559 reg: regInfo{ 19560 inputs: []inputInfo{ 19561 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19562 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19563 }, 19564 outputs: []outputInfo{ 19565 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19566 }, 19567 }, 19568 }, 19569 { 19570 name: "MULHDU", 19571 argLen: 2, 19572 commutative: true, 19573 resultInArg0: true, 19574 clobberFlags: true, 19575 asm: s390x.AMULHDU, 19576 reg: regInfo{ 19577 inputs: []inputInfo{ 19578 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19579 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19580 }, 19581 outputs: []outputInfo{ 19582 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19583 }, 19584 }, 19585 }, 19586 { 19587 name: "DIVD", 19588 argLen: 2, 19589 resultInArg0: true, 19590 clobberFlags: true, 19591 asm: s390x.ADIVD, 19592 reg: regInfo{ 19593 inputs: []inputInfo{ 19594 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19595 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19596 }, 19597 outputs: []outputInfo{ 19598 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19599 }, 19600 }, 19601 }, 19602 { 19603 name: "DIVW", 19604 argLen: 2, 19605 resultInArg0: true, 19606 clobberFlags: true, 19607 asm: s390x.ADIVW, 19608 reg: regInfo{ 19609 inputs: []inputInfo{ 19610 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19611 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19612 }, 19613 outputs: []outputInfo{ 19614 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19615 }, 19616 }, 19617 }, 19618 { 19619 name: "DIVDU", 19620 argLen: 2, 19621 resultInArg0: true, 19622 clobberFlags: true, 19623 asm: s390x.ADIVDU, 19624 reg: regInfo{ 19625 inputs: []inputInfo{ 19626 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19627 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19628 }, 19629 outputs: []outputInfo{ 19630 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19631 }, 19632 }, 19633 }, 19634 { 19635 name: "DIVWU", 19636 argLen: 2, 19637 resultInArg0: true, 19638 clobberFlags: true, 19639 asm: s390x.ADIVWU, 19640 reg: regInfo{ 19641 inputs: []inputInfo{ 19642 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19643 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19644 }, 19645 outputs: []outputInfo{ 19646 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19647 }, 19648 }, 19649 }, 19650 { 19651 name: "MODD", 19652 argLen: 2, 19653 resultInArg0: true, 19654 clobberFlags: true, 19655 asm: s390x.AMODD, 19656 reg: regInfo{ 19657 inputs: []inputInfo{ 19658 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19659 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19660 }, 19661 outputs: []outputInfo{ 19662 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19663 }, 19664 }, 19665 }, 19666 { 19667 name: "MODW", 19668 argLen: 2, 19669 resultInArg0: true, 19670 clobberFlags: true, 19671 asm: s390x.AMODW, 19672 reg: regInfo{ 19673 inputs: []inputInfo{ 19674 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19675 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19676 }, 19677 outputs: []outputInfo{ 19678 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19679 }, 19680 }, 19681 }, 19682 { 19683 name: "MODDU", 19684 argLen: 2, 19685 resultInArg0: true, 19686 clobberFlags: true, 19687 asm: s390x.AMODDU, 19688 reg: regInfo{ 19689 inputs: []inputInfo{ 19690 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19691 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19692 }, 19693 outputs: []outputInfo{ 19694 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19695 }, 19696 }, 19697 }, 19698 { 19699 name: "MODWU", 19700 argLen: 2, 19701 resultInArg0: true, 19702 clobberFlags: true, 19703 asm: s390x.AMODWU, 19704 reg: regInfo{ 19705 inputs: []inputInfo{ 19706 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19707 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19708 }, 19709 outputs: []outputInfo{ 19710 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19711 }, 19712 }, 19713 }, 19714 { 19715 name: "AND", 19716 argLen: 2, 19717 commutative: true, 19718 clobberFlags: true, 19719 asm: s390x.AAND, 19720 reg: regInfo{ 19721 inputs: []inputInfo{ 19722 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19723 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19724 }, 19725 outputs: []outputInfo{ 19726 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19727 }, 19728 }, 19729 }, 19730 { 19731 name: "ANDW", 19732 argLen: 2, 19733 commutative: true, 19734 clobberFlags: true, 19735 asm: s390x.AANDW, 19736 reg: regInfo{ 19737 inputs: []inputInfo{ 19738 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19739 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19740 }, 19741 outputs: []outputInfo{ 19742 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19743 }, 19744 }, 19745 }, 19746 { 19747 name: "ANDconst", 19748 auxType: auxInt64, 19749 argLen: 1, 19750 resultInArg0: true, 19751 clobberFlags: true, 19752 asm: s390x.AAND, 19753 reg: regInfo{ 19754 inputs: []inputInfo{ 19755 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19756 }, 19757 outputs: []outputInfo{ 19758 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19759 }, 19760 }, 19761 }, 19762 { 19763 name: "ANDWconst", 19764 auxType: auxInt32, 19765 argLen: 1, 19766 resultInArg0: true, 19767 clobberFlags: true, 19768 asm: s390x.AANDW, 19769 reg: regInfo{ 19770 inputs: []inputInfo{ 19771 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19772 }, 19773 outputs: []outputInfo{ 19774 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19775 }, 19776 }, 19777 }, 19778 { 19779 name: "ANDload", 19780 auxType: auxSymOff, 19781 argLen: 3, 19782 resultInArg0: true, 19783 clobberFlags: true, 19784 faultOnNilArg1: true, 19785 symEffect: SymRead, 19786 asm: s390x.AAND, 19787 reg: regInfo{ 19788 inputs: []inputInfo{ 19789 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19790 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19791 }, 19792 outputs: []outputInfo{ 19793 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19794 }, 19795 }, 19796 }, 19797 { 19798 name: "ANDWload", 19799 auxType: auxSymOff, 19800 argLen: 3, 19801 resultInArg0: true, 19802 clobberFlags: true, 19803 faultOnNilArg1: true, 19804 symEffect: SymRead, 19805 asm: s390x.AANDW, 19806 reg: regInfo{ 19807 inputs: []inputInfo{ 19808 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19809 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19810 }, 19811 outputs: []outputInfo{ 19812 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19813 }, 19814 }, 19815 }, 19816 { 19817 name: "OR", 19818 argLen: 2, 19819 commutative: true, 19820 clobberFlags: true, 19821 asm: s390x.AOR, 19822 reg: regInfo{ 19823 inputs: []inputInfo{ 19824 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19825 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19826 }, 19827 outputs: []outputInfo{ 19828 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19829 }, 19830 }, 19831 }, 19832 { 19833 name: "ORW", 19834 argLen: 2, 19835 commutative: true, 19836 clobberFlags: true, 19837 asm: s390x.AORW, 19838 reg: regInfo{ 19839 inputs: []inputInfo{ 19840 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19841 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19842 }, 19843 outputs: []outputInfo{ 19844 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19845 }, 19846 }, 19847 }, 19848 { 19849 name: "ORconst", 19850 auxType: auxInt64, 19851 argLen: 1, 19852 resultInArg0: true, 19853 clobberFlags: true, 19854 asm: s390x.AOR, 19855 reg: regInfo{ 19856 inputs: []inputInfo{ 19857 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19858 }, 19859 outputs: []outputInfo{ 19860 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19861 }, 19862 }, 19863 }, 19864 { 19865 name: "ORWconst", 19866 auxType: auxInt32, 19867 argLen: 1, 19868 resultInArg0: true, 19869 clobberFlags: true, 19870 asm: s390x.AORW, 19871 reg: regInfo{ 19872 inputs: []inputInfo{ 19873 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19874 }, 19875 outputs: []outputInfo{ 19876 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19877 }, 19878 }, 19879 }, 19880 { 19881 name: "ORload", 19882 auxType: auxSymOff, 19883 argLen: 3, 19884 resultInArg0: true, 19885 clobberFlags: true, 19886 faultOnNilArg1: true, 19887 symEffect: SymRead, 19888 asm: s390x.AOR, 19889 reg: regInfo{ 19890 inputs: []inputInfo{ 19891 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19892 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19893 }, 19894 outputs: []outputInfo{ 19895 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19896 }, 19897 }, 19898 }, 19899 { 19900 name: "ORWload", 19901 auxType: auxSymOff, 19902 argLen: 3, 19903 resultInArg0: true, 19904 clobberFlags: true, 19905 faultOnNilArg1: true, 19906 symEffect: SymRead, 19907 asm: s390x.AORW, 19908 reg: regInfo{ 19909 inputs: []inputInfo{ 19910 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19911 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19912 }, 19913 outputs: []outputInfo{ 19914 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19915 }, 19916 }, 19917 }, 19918 { 19919 name: "XOR", 19920 argLen: 2, 19921 commutative: true, 19922 clobberFlags: true, 19923 asm: s390x.AXOR, 19924 reg: regInfo{ 19925 inputs: []inputInfo{ 19926 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19927 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19928 }, 19929 outputs: []outputInfo{ 19930 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19931 }, 19932 }, 19933 }, 19934 { 19935 name: "XORW", 19936 argLen: 2, 19937 commutative: true, 19938 clobberFlags: true, 19939 asm: s390x.AXORW, 19940 reg: regInfo{ 19941 inputs: []inputInfo{ 19942 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19943 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19944 }, 19945 outputs: []outputInfo{ 19946 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19947 }, 19948 }, 19949 }, 19950 { 19951 name: "XORconst", 19952 auxType: auxInt64, 19953 argLen: 1, 19954 resultInArg0: true, 19955 clobberFlags: true, 19956 asm: s390x.AXOR, 19957 reg: regInfo{ 19958 inputs: []inputInfo{ 19959 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19960 }, 19961 outputs: []outputInfo{ 19962 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19963 }, 19964 }, 19965 }, 19966 { 19967 name: "XORWconst", 19968 auxType: auxInt32, 19969 argLen: 1, 19970 resultInArg0: true, 19971 clobberFlags: true, 19972 asm: s390x.AXORW, 19973 reg: regInfo{ 19974 inputs: []inputInfo{ 19975 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19976 }, 19977 outputs: []outputInfo{ 19978 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19979 }, 19980 }, 19981 }, 19982 { 19983 name: "XORload", 19984 auxType: auxSymOff, 19985 argLen: 3, 19986 resultInArg0: true, 19987 clobberFlags: true, 19988 faultOnNilArg1: true, 19989 symEffect: SymRead, 19990 asm: s390x.AXOR, 19991 reg: regInfo{ 19992 inputs: []inputInfo{ 19993 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19994 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19995 }, 19996 outputs: []outputInfo{ 19997 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19998 }, 19999 }, 20000 }, 20001 { 20002 name: "XORWload", 20003 auxType: auxSymOff, 20004 argLen: 3, 20005 resultInArg0: true, 20006 clobberFlags: true, 20007 faultOnNilArg1: true, 20008 symEffect: SymRead, 20009 asm: s390x.AXORW, 20010 reg: regInfo{ 20011 inputs: []inputInfo{ 20012 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20013 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20014 }, 20015 outputs: []outputInfo{ 20016 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20017 }, 20018 }, 20019 }, 20020 { 20021 name: "CMP", 20022 argLen: 2, 20023 asm: s390x.ACMP, 20024 reg: regInfo{ 20025 inputs: []inputInfo{ 20026 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20027 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20028 }, 20029 }, 20030 }, 20031 { 20032 name: "CMPW", 20033 argLen: 2, 20034 asm: s390x.ACMPW, 20035 reg: regInfo{ 20036 inputs: []inputInfo{ 20037 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20038 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20039 }, 20040 }, 20041 }, 20042 { 20043 name: "CMPU", 20044 argLen: 2, 20045 asm: s390x.ACMPU, 20046 reg: regInfo{ 20047 inputs: []inputInfo{ 20048 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20049 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20050 }, 20051 }, 20052 }, 20053 { 20054 name: "CMPWU", 20055 argLen: 2, 20056 asm: s390x.ACMPWU, 20057 reg: regInfo{ 20058 inputs: []inputInfo{ 20059 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20060 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20061 }, 20062 }, 20063 }, 20064 { 20065 name: "CMPconst", 20066 auxType: auxInt64, 20067 argLen: 1, 20068 asm: s390x.ACMP, 20069 reg: regInfo{ 20070 inputs: []inputInfo{ 20071 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20072 }, 20073 }, 20074 }, 20075 { 20076 name: "CMPWconst", 20077 auxType: auxInt32, 20078 argLen: 1, 20079 asm: s390x.ACMPW, 20080 reg: regInfo{ 20081 inputs: []inputInfo{ 20082 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20083 }, 20084 }, 20085 }, 20086 { 20087 name: "CMPUconst", 20088 auxType: auxInt64, 20089 argLen: 1, 20090 asm: s390x.ACMPU, 20091 reg: regInfo{ 20092 inputs: []inputInfo{ 20093 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20094 }, 20095 }, 20096 }, 20097 { 20098 name: "CMPWUconst", 20099 auxType: auxInt32, 20100 argLen: 1, 20101 asm: s390x.ACMPWU, 20102 reg: regInfo{ 20103 inputs: []inputInfo{ 20104 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20105 }, 20106 }, 20107 }, 20108 { 20109 name: "FCMPS", 20110 argLen: 2, 20111 asm: s390x.ACEBR, 20112 reg: regInfo{ 20113 inputs: []inputInfo{ 20114 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20115 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20116 }, 20117 }, 20118 }, 20119 { 20120 name: "FCMP", 20121 argLen: 2, 20122 asm: s390x.AFCMPU, 20123 reg: regInfo{ 20124 inputs: []inputInfo{ 20125 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20126 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20127 }, 20128 }, 20129 }, 20130 { 20131 name: "SLD", 20132 argLen: 2, 20133 asm: s390x.ASLD, 20134 reg: regInfo{ 20135 inputs: []inputInfo{ 20136 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20137 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20138 }, 20139 outputs: []outputInfo{ 20140 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20141 }, 20142 }, 20143 }, 20144 { 20145 name: "SLW", 20146 argLen: 2, 20147 asm: s390x.ASLW, 20148 reg: regInfo{ 20149 inputs: []inputInfo{ 20150 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20151 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20152 }, 20153 outputs: []outputInfo{ 20154 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20155 }, 20156 }, 20157 }, 20158 { 20159 name: "SLDconst", 20160 auxType: auxInt8, 20161 argLen: 1, 20162 asm: s390x.ASLD, 20163 reg: regInfo{ 20164 inputs: []inputInfo{ 20165 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20166 }, 20167 outputs: []outputInfo{ 20168 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20169 }, 20170 }, 20171 }, 20172 { 20173 name: "SLWconst", 20174 auxType: auxInt8, 20175 argLen: 1, 20176 asm: s390x.ASLW, 20177 reg: regInfo{ 20178 inputs: []inputInfo{ 20179 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20180 }, 20181 outputs: []outputInfo{ 20182 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20183 }, 20184 }, 20185 }, 20186 { 20187 name: "SRD", 20188 argLen: 2, 20189 asm: s390x.ASRD, 20190 reg: regInfo{ 20191 inputs: []inputInfo{ 20192 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20193 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20194 }, 20195 outputs: []outputInfo{ 20196 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20197 }, 20198 }, 20199 }, 20200 { 20201 name: "SRW", 20202 argLen: 2, 20203 asm: s390x.ASRW, 20204 reg: regInfo{ 20205 inputs: []inputInfo{ 20206 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20207 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20208 }, 20209 outputs: []outputInfo{ 20210 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20211 }, 20212 }, 20213 }, 20214 { 20215 name: "SRDconst", 20216 auxType: auxInt8, 20217 argLen: 1, 20218 asm: s390x.ASRD, 20219 reg: regInfo{ 20220 inputs: []inputInfo{ 20221 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20222 }, 20223 outputs: []outputInfo{ 20224 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20225 }, 20226 }, 20227 }, 20228 { 20229 name: "SRWconst", 20230 auxType: auxInt8, 20231 argLen: 1, 20232 asm: s390x.ASRW, 20233 reg: regInfo{ 20234 inputs: []inputInfo{ 20235 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20236 }, 20237 outputs: []outputInfo{ 20238 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20239 }, 20240 }, 20241 }, 20242 { 20243 name: "SRAD", 20244 argLen: 2, 20245 clobberFlags: true, 20246 asm: s390x.ASRAD, 20247 reg: regInfo{ 20248 inputs: []inputInfo{ 20249 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20250 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20251 }, 20252 outputs: []outputInfo{ 20253 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20254 }, 20255 }, 20256 }, 20257 { 20258 name: "SRAW", 20259 argLen: 2, 20260 clobberFlags: true, 20261 asm: s390x.ASRAW, 20262 reg: regInfo{ 20263 inputs: []inputInfo{ 20264 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20265 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20266 }, 20267 outputs: []outputInfo{ 20268 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20269 }, 20270 }, 20271 }, 20272 { 20273 name: "SRADconst", 20274 auxType: auxInt8, 20275 argLen: 1, 20276 clobberFlags: true, 20277 asm: s390x.ASRAD, 20278 reg: regInfo{ 20279 inputs: []inputInfo{ 20280 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20281 }, 20282 outputs: []outputInfo{ 20283 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20284 }, 20285 }, 20286 }, 20287 { 20288 name: "SRAWconst", 20289 auxType: auxInt8, 20290 argLen: 1, 20291 clobberFlags: true, 20292 asm: s390x.ASRAW, 20293 reg: regInfo{ 20294 inputs: []inputInfo{ 20295 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20296 }, 20297 outputs: []outputInfo{ 20298 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20299 }, 20300 }, 20301 }, 20302 { 20303 name: "RLLGconst", 20304 auxType: auxInt8, 20305 argLen: 1, 20306 asm: s390x.ARLLG, 20307 reg: regInfo{ 20308 inputs: []inputInfo{ 20309 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20310 }, 20311 outputs: []outputInfo{ 20312 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20313 }, 20314 }, 20315 }, 20316 { 20317 name: "RLLconst", 20318 auxType: auxInt8, 20319 argLen: 1, 20320 asm: s390x.ARLL, 20321 reg: regInfo{ 20322 inputs: []inputInfo{ 20323 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20324 }, 20325 outputs: []outputInfo{ 20326 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20327 }, 20328 }, 20329 }, 20330 { 20331 name: "NEG", 20332 argLen: 1, 20333 clobberFlags: true, 20334 asm: s390x.ANEG, 20335 reg: regInfo{ 20336 inputs: []inputInfo{ 20337 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20338 }, 20339 outputs: []outputInfo{ 20340 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20341 }, 20342 }, 20343 }, 20344 { 20345 name: "NEGW", 20346 argLen: 1, 20347 clobberFlags: true, 20348 asm: s390x.ANEGW, 20349 reg: regInfo{ 20350 inputs: []inputInfo{ 20351 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20352 }, 20353 outputs: []outputInfo{ 20354 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20355 }, 20356 }, 20357 }, 20358 { 20359 name: "NOT", 20360 argLen: 1, 20361 resultInArg0: true, 20362 clobberFlags: true, 20363 reg: regInfo{ 20364 inputs: []inputInfo{ 20365 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20366 }, 20367 outputs: []outputInfo{ 20368 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20369 }, 20370 }, 20371 }, 20372 { 20373 name: "NOTW", 20374 argLen: 1, 20375 resultInArg0: true, 20376 clobberFlags: true, 20377 reg: regInfo{ 20378 inputs: []inputInfo{ 20379 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20380 }, 20381 outputs: []outputInfo{ 20382 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20383 }, 20384 }, 20385 }, 20386 { 20387 name: "FSQRT", 20388 argLen: 1, 20389 asm: s390x.AFSQRT, 20390 reg: regInfo{ 20391 inputs: []inputInfo{ 20392 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20393 }, 20394 outputs: []outputInfo{ 20395 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20396 }, 20397 }, 20398 }, 20399 { 20400 name: "SUBEcarrymask", 20401 argLen: 1, 20402 asm: s390x.ASUBE, 20403 reg: regInfo{ 20404 outputs: []outputInfo{ 20405 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20406 }, 20407 }, 20408 }, 20409 { 20410 name: "SUBEWcarrymask", 20411 argLen: 1, 20412 asm: s390x.ASUBE, 20413 reg: regInfo{ 20414 outputs: []outputInfo{ 20415 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20416 }, 20417 }, 20418 }, 20419 { 20420 name: "MOVDEQ", 20421 argLen: 3, 20422 resultInArg0: true, 20423 asm: s390x.AMOVDEQ, 20424 reg: regInfo{ 20425 inputs: []inputInfo{ 20426 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20427 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20428 }, 20429 outputs: []outputInfo{ 20430 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20431 }, 20432 }, 20433 }, 20434 { 20435 name: "MOVDNE", 20436 argLen: 3, 20437 resultInArg0: true, 20438 asm: s390x.AMOVDNE, 20439 reg: regInfo{ 20440 inputs: []inputInfo{ 20441 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20442 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20443 }, 20444 outputs: []outputInfo{ 20445 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20446 }, 20447 }, 20448 }, 20449 { 20450 name: "MOVDLT", 20451 argLen: 3, 20452 resultInArg0: true, 20453 asm: s390x.AMOVDLT, 20454 reg: regInfo{ 20455 inputs: []inputInfo{ 20456 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20457 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20458 }, 20459 outputs: []outputInfo{ 20460 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20461 }, 20462 }, 20463 }, 20464 { 20465 name: "MOVDLE", 20466 argLen: 3, 20467 resultInArg0: true, 20468 asm: s390x.AMOVDLE, 20469 reg: regInfo{ 20470 inputs: []inputInfo{ 20471 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20472 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20473 }, 20474 outputs: []outputInfo{ 20475 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20476 }, 20477 }, 20478 }, 20479 { 20480 name: "MOVDGT", 20481 argLen: 3, 20482 resultInArg0: true, 20483 asm: s390x.AMOVDGT, 20484 reg: regInfo{ 20485 inputs: []inputInfo{ 20486 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20487 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20488 }, 20489 outputs: []outputInfo{ 20490 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20491 }, 20492 }, 20493 }, 20494 { 20495 name: "MOVDGE", 20496 argLen: 3, 20497 resultInArg0: true, 20498 asm: s390x.AMOVDGE, 20499 reg: regInfo{ 20500 inputs: []inputInfo{ 20501 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20502 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20503 }, 20504 outputs: []outputInfo{ 20505 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20506 }, 20507 }, 20508 }, 20509 { 20510 name: "MOVDGTnoinv", 20511 argLen: 3, 20512 resultInArg0: true, 20513 asm: s390x.AMOVDGT, 20514 reg: regInfo{ 20515 inputs: []inputInfo{ 20516 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20517 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20518 }, 20519 outputs: []outputInfo{ 20520 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20521 }, 20522 }, 20523 }, 20524 { 20525 name: "MOVDGEnoinv", 20526 argLen: 3, 20527 resultInArg0: true, 20528 asm: s390x.AMOVDGE, 20529 reg: regInfo{ 20530 inputs: []inputInfo{ 20531 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20532 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20533 }, 20534 outputs: []outputInfo{ 20535 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20536 }, 20537 }, 20538 }, 20539 { 20540 name: "MOVBreg", 20541 argLen: 1, 20542 asm: s390x.AMOVB, 20543 reg: regInfo{ 20544 inputs: []inputInfo{ 20545 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20546 }, 20547 outputs: []outputInfo{ 20548 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20549 }, 20550 }, 20551 }, 20552 { 20553 name: "MOVBZreg", 20554 argLen: 1, 20555 asm: s390x.AMOVBZ, 20556 reg: regInfo{ 20557 inputs: []inputInfo{ 20558 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20559 }, 20560 outputs: []outputInfo{ 20561 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20562 }, 20563 }, 20564 }, 20565 { 20566 name: "MOVHreg", 20567 argLen: 1, 20568 asm: s390x.AMOVH, 20569 reg: regInfo{ 20570 inputs: []inputInfo{ 20571 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20572 }, 20573 outputs: []outputInfo{ 20574 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20575 }, 20576 }, 20577 }, 20578 { 20579 name: "MOVHZreg", 20580 argLen: 1, 20581 asm: s390x.AMOVHZ, 20582 reg: regInfo{ 20583 inputs: []inputInfo{ 20584 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20585 }, 20586 outputs: []outputInfo{ 20587 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20588 }, 20589 }, 20590 }, 20591 { 20592 name: "MOVWreg", 20593 argLen: 1, 20594 asm: s390x.AMOVW, 20595 reg: regInfo{ 20596 inputs: []inputInfo{ 20597 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20598 }, 20599 outputs: []outputInfo{ 20600 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20601 }, 20602 }, 20603 }, 20604 { 20605 name: "MOVWZreg", 20606 argLen: 1, 20607 asm: s390x.AMOVWZ, 20608 reg: regInfo{ 20609 inputs: []inputInfo{ 20610 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20611 }, 20612 outputs: []outputInfo{ 20613 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20614 }, 20615 }, 20616 }, 20617 { 20618 name: "MOVDreg", 20619 argLen: 1, 20620 asm: s390x.AMOVD, 20621 reg: regInfo{ 20622 inputs: []inputInfo{ 20623 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20624 }, 20625 outputs: []outputInfo{ 20626 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20627 }, 20628 }, 20629 }, 20630 { 20631 name: "MOVDnop", 20632 argLen: 1, 20633 resultInArg0: true, 20634 reg: regInfo{ 20635 inputs: []inputInfo{ 20636 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20637 }, 20638 outputs: []outputInfo{ 20639 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20640 }, 20641 }, 20642 }, 20643 { 20644 name: "MOVDconst", 20645 auxType: auxInt64, 20646 argLen: 0, 20647 rematerializeable: true, 20648 asm: s390x.AMOVD, 20649 reg: regInfo{ 20650 outputs: []outputInfo{ 20651 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20652 }, 20653 }, 20654 }, 20655 { 20656 name: "CFDBRA", 20657 argLen: 1, 20658 asm: s390x.ACFDBRA, 20659 reg: regInfo{ 20660 inputs: []inputInfo{ 20661 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20662 }, 20663 outputs: []outputInfo{ 20664 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20665 }, 20666 }, 20667 }, 20668 { 20669 name: "CGDBRA", 20670 argLen: 1, 20671 asm: s390x.ACGDBRA, 20672 reg: regInfo{ 20673 inputs: []inputInfo{ 20674 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20675 }, 20676 outputs: []outputInfo{ 20677 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20678 }, 20679 }, 20680 }, 20681 { 20682 name: "CFEBRA", 20683 argLen: 1, 20684 asm: s390x.ACFEBRA, 20685 reg: regInfo{ 20686 inputs: []inputInfo{ 20687 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20688 }, 20689 outputs: []outputInfo{ 20690 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20691 }, 20692 }, 20693 }, 20694 { 20695 name: "CGEBRA", 20696 argLen: 1, 20697 asm: s390x.ACGEBRA, 20698 reg: regInfo{ 20699 inputs: []inputInfo{ 20700 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20701 }, 20702 outputs: []outputInfo{ 20703 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20704 }, 20705 }, 20706 }, 20707 { 20708 name: "CEFBRA", 20709 argLen: 1, 20710 asm: s390x.ACEFBRA, 20711 reg: regInfo{ 20712 inputs: []inputInfo{ 20713 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20714 }, 20715 outputs: []outputInfo{ 20716 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20717 }, 20718 }, 20719 }, 20720 { 20721 name: "CDFBRA", 20722 argLen: 1, 20723 asm: s390x.ACDFBRA, 20724 reg: regInfo{ 20725 inputs: []inputInfo{ 20726 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20727 }, 20728 outputs: []outputInfo{ 20729 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20730 }, 20731 }, 20732 }, 20733 { 20734 name: "CEGBRA", 20735 argLen: 1, 20736 asm: s390x.ACEGBRA, 20737 reg: regInfo{ 20738 inputs: []inputInfo{ 20739 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20740 }, 20741 outputs: []outputInfo{ 20742 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20743 }, 20744 }, 20745 }, 20746 { 20747 name: "CDGBRA", 20748 argLen: 1, 20749 asm: s390x.ACDGBRA, 20750 reg: regInfo{ 20751 inputs: []inputInfo{ 20752 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20753 }, 20754 outputs: []outputInfo{ 20755 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20756 }, 20757 }, 20758 }, 20759 { 20760 name: "LEDBR", 20761 argLen: 1, 20762 asm: s390x.ALEDBR, 20763 reg: regInfo{ 20764 inputs: []inputInfo{ 20765 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20766 }, 20767 outputs: []outputInfo{ 20768 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20769 }, 20770 }, 20771 }, 20772 { 20773 name: "LDEBR", 20774 argLen: 1, 20775 asm: s390x.ALDEBR, 20776 reg: regInfo{ 20777 inputs: []inputInfo{ 20778 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20779 }, 20780 outputs: []outputInfo{ 20781 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20782 }, 20783 }, 20784 }, 20785 { 20786 name: "MOVDaddr", 20787 auxType: auxSymOff, 20788 argLen: 1, 20789 rematerializeable: true, 20790 symEffect: SymRead, 20791 reg: regInfo{ 20792 inputs: []inputInfo{ 20793 {0, 4295000064}, // SP SB 20794 }, 20795 outputs: []outputInfo{ 20796 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20797 }, 20798 }, 20799 }, 20800 { 20801 name: "MOVDaddridx", 20802 auxType: auxSymOff, 20803 argLen: 2, 20804 symEffect: SymRead, 20805 reg: regInfo{ 20806 inputs: []inputInfo{ 20807 {0, 4295000064}, // SP SB 20808 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20809 }, 20810 outputs: []outputInfo{ 20811 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20812 }, 20813 }, 20814 }, 20815 { 20816 name: "MOVBZload", 20817 auxType: auxSymOff, 20818 argLen: 2, 20819 clobberFlags: true, 20820 faultOnNilArg0: true, 20821 symEffect: SymRead, 20822 asm: s390x.AMOVBZ, 20823 reg: regInfo{ 20824 inputs: []inputInfo{ 20825 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20826 }, 20827 outputs: []outputInfo{ 20828 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20829 }, 20830 }, 20831 }, 20832 { 20833 name: "MOVBload", 20834 auxType: auxSymOff, 20835 argLen: 2, 20836 clobberFlags: true, 20837 faultOnNilArg0: true, 20838 symEffect: SymRead, 20839 asm: s390x.AMOVB, 20840 reg: regInfo{ 20841 inputs: []inputInfo{ 20842 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20843 }, 20844 outputs: []outputInfo{ 20845 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20846 }, 20847 }, 20848 }, 20849 { 20850 name: "MOVHZload", 20851 auxType: auxSymOff, 20852 argLen: 2, 20853 clobberFlags: true, 20854 faultOnNilArg0: true, 20855 symEffect: SymRead, 20856 asm: s390x.AMOVHZ, 20857 reg: regInfo{ 20858 inputs: []inputInfo{ 20859 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20860 }, 20861 outputs: []outputInfo{ 20862 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20863 }, 20864 }, 20865 }, 20866 { 20867 name: "MOVHload", 20868 auxType: auxSymOff, 20869 argLen: 2, 20870 clobberFlags: true, 20871 faultOnNilArg0: true, 20872 symEffect: SymRead, 20873 asm: s390x.AMOVH, 20874 reg: regInfo{ 20875 inputs: []inputInfo{ 20876 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20877 }, 20878 outputs: []outputInfo{ 20879 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20880 }, 20881 }, 20882 }, 20883 { 20884 name: "MOVWZload", 20885 auxType: auxSymOff, 20886 argLen: 2, 20887 clobberFlags: true, 20888 faultOnNilArg0: true, 20889 symEffect: SymRead, 20890 asm: s390x.AMOVWZ, 20891 reg: regInfo{ 20892 inputs: []inputInfo{ 20893 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20894 }, 20895 outputs: []outputInfo{ 20896 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20897 }, 20898 }, 20899 }, 20900 { 20901 name: "MOVWload", 20902 auxType: auxSymOff, 20903 argLen: 2, 20904 clobberFlags: true, 20905 faultOnNilArg0: true, 20906 symEffect: SymRead, 20907 asm: s390x.AMOVW, 20908 reg: regInfo{ 20909 inputs: []inputInfo{ 20910 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20911 }, 20912 outputs: []outputInfo{ 20913 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20914 }, 20915 }, 20916 }, 20917 { 20918 name: "MOVDload", 20919 auxType: auxSymOff, 20920 argLen: 2, 20921 clobberFlags: true, 20922 faultOnNilArg0: true, 20923 symEffect: SymRead, 20924 asm: s390x.AMOVD, 20925 reg: regInfo{ 20926 inputs: []inputInfo{ 20927 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20928 }, 20929 outputs: []outputInfo{ 20930 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20931 }, 20932 }, 20933 }, 20934 { 20935 name: "MOVWBR", 20936 argLen: 1, 20937 asm: s390x.AMOVWBR, 20938 reg: regInfo{ 20939 inputs: []inputInfo{ 20940 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20941 }, 20942 outputs: []outputInfo{ 20943 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20944 }, 20945 }, 20946 }, 20947 { 20948 name: "MOVDBR", 20949 argLen: 1, 20950 asm: s390x.AMOVDBR, 20951 reg: regInfo{ 20952 inputs: []inputInfo{ 20953 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20954 }, 20955 outputs: []outputInfo{ 20956 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20957 }, 20958 }, 20959 }, 20960 { 20961 name: "MOVHBRload", 20962 auxType: auxSymOff, 20963 argLen: 2, 20964 clobberFlags: true, 20965 faultOnNilArg0: true, 20966 symEffect: SymRead, 20967 asm: s390x.AMOVHBR, 20968 reg: regInfo{ 20969 inputs: []inputInfo{ 20970 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20971 }, 20972 outputs: []outputInfo{ 20973 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20974 }, 20975 }, 20976 }, 20977 { 20978 name: "MOVWBRload", 20979 auxType: auxSymOff, 20980 argLen: 2, 20981 clobberFlags: true, 20982 faultOnNilArg0: true, 20983 symEffect: SymRead, 20984 asm: s390x.AMOVWBR, 20985 reg: regInfo{ 20986 inputs: []inputInfo{ 20987 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20988 }, 20989 outputs: []outputInfo{ 20990 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20991 }, 20992 }, 20993 }, 20994 { 20995 name: "MOVDBRload", 20996 auxType: auxSymOff, 20997 argLen: 2, 20998 clobberFlags: true, 20999 faultOnNilArg0: true, 21000 symEffect: SymRead, 21001 asm: s390x.AMOVDBR, 21002 reg: regInfo{ 21003 inputs: []inputInfo{ 21004 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21005 }, 21006 outputs: []outputInfo{ 21007 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21008 }, 21009 }, 21010 }, 21011 { 21012 name: "MOVBstore", 21013 auxType: auxSymOff, 21014 argLen: 3, 21015 clobberFlags: true, 21016 faultOnNilArg0: true, 21017 symEffect: SymWrite, 21018 asm: s390x.AMOVB, 21019 reg: regInfo{ 21020 inputs: []inputInfo{ 21021 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21022 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21023 }, 21024 }, 21025 }, 21026 { 21027 name: "MOVHstore", 21028 auxType: auxSymOff, 21029 argLen: 3, 21030 clobberFlags: true, 21031 faultOnNilArg0: true, 21032 symEffect: SymWrite, 21033 asm: s390x.AMOVH, 21034 reg: regInfo{ 21035 inputs: []inputInfo{ 21036 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21037 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21038 }, 21039 }, 21040 }, 21041 { 21042 name: "MOVWstore", 21043 auxType: auxSymOff, 21044 argLen: 3, 21045 clobberFlags: true, 21046 faultOnNilArg0: true, 21047 symEffect: SymWrite, 21048 asm: s390x.AMOVW, 21049 reg: regInfo{ 21050 inputs: []inputInfo{ 21051 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21052 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21053 }, 21054 }, 21055 }, 21056 { 21057 name: "MOVDstore", 21058 auxType: auxSymOff, 21059 argLen: 3, 21060 clobberFlags: true, 21061 faultOnNilArg0: true, 21062 symEffect: SymWrite, 21063 asm: s390x.AMOVD, 21064 reg: regInfo{ 21065 inputs: []inputInfo{ 21066 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21067 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21068 }, 21069 }, 21070 }, 21071 { 21072 name: "MOVHBRstore", 21073 auxType: auxSymOff, 21074 argLen: 3, 21075 clobberFlags: true, 21076 faultOnNilArg0: true, 21077 symEffect: SymWrite, 21078 asm: s390x.AMOVHBR, 21079 reg: regInfo{ 21080 inputs: []inputInfo{ 21081 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21082 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21083 }, 21084 }, 21085 }, 21086 { 21087 name: "MOVWBRstore", 21088 auxType: auxSymOff, 21089 argLen: 3, 21090 clobberFlags: true, 21091 faultOnNilArg0: true, 21092 symEffect: SymWrite, 21093 asm: s390x.AMOVWBR, 21094 reg: regInfo{ 21095 inputs: []inputInfo{ 21096 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21097 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21098 }, 21099 }, 21100 }, 21101 { 21102 name: "MOVDBRstore", 21103 auxType: auxSymOff, 21104 argLen: 3, 21105 clobberFlags: true, 21106 faultOnNilArg0: true, 21107 symEffect: SymWrite, 21108 asm: s390x.AMOVDBR, 21109 reg: regInfo{ 21110 inputs: []inputInfo{ 21111 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21112 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21113 }, 21114 }, 21115 }, 21116 { 21117 name: "MVC", 21118 auxType: auxSymValAndOff, 21119 argLen: 3, 21120 clobberFlags: true, 21121 faultOnNilArg0: true, 21122 faultOnNilArg1: true, 21123 symEffect: SymNone, 21124 asm: s390x.AMVC, 21125 reg: regInfo{ 21126 inputs: []inputInfo{ 21127 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21128 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21129 }, 21130 }, 21131 }, 21132 { 21133 name: "MOVBZloadidx", 21134 auxType: auxSymOff, 21135 argLen: 3, 21136 commutative: true, 21137 clobberFlags: true, 21138 symEffect: SymRead, 21139 asm: s390x.AMOVBZ, 21140 reg: regInfo{ 21141 inputs: []inputInfo{ 21142 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21143 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21144 }, 21145 outputs: []outputInfo{ 21146 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21147 }, 21148 }, 21149 }, 21150 { 21151 name: "MOVHZloadidx", 21152 auxType: auxSymOff, 21153 argLen: 3, 21154 commutative: true, 21155 clobberFlags: true, 21156 symEffect: SymRead, 21157 asm: s390x.AMOVHZ, 21158 reg: regInfo{ 21159 inputs: []inputInfo{ 21160 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21161 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21162 }, 21163 outputs: []outputInfo{ 21164 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21165 }, 21166 }, 21167 }, 21168 { 21169 name: "MOVWZloadidx", 21170 auxType: auxSymOff, 21171 argLen: 3, 21172 commutative: true, 21173 clobberFlags: true, 21174 symEffect: SymRead, 21175 asm: s390x.AMOVWZ, 21176 reg: regInfo{ 21177 inputs: []inputInfo{ 21178 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21179 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21180 }, 21181 outputs: []outputInfo{ 21182 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21183 }, 21184 }, 21185 }, 21186 { 21187 name: "MOVDloadidx", 21188 auxType: auxSymOff, 21189 argLen: 3, 21190 commutative: true, 21191 clobberFlags: true, 21192 symEffect: SymRead, 21193 asm: s390x.AMOVD, 21194 reg: regInfo{ 21195 inputs: []inputInfo{ 21196 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21197 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21198 }, 21199 outputs: []outputInfo{ 21200 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21201 }, 21202 }, 21203 }, 21204 { 21205 name: "MOVHBRloadidx", 21206 auxType: auxSymOff, 21207 argLen: 3, 21208 commutative: true, 21209 clobberFlags: true, 21210 symEffect: SymRead, 21211 asm: s390x.AMOVHBR, 21212 reg: regInfo{ 21213 inputs: []inputInfo{ 21214 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21215 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21216 }, 21217 outputs: []outputInfo{ 21218 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21219 }, 21220 }, 21221 }, 21222 { 21223 name: "MOVWBRloadidx", 21224 auxType: auxSymOff, 21225 argLen: 3, 21226 commutative: true, 21227 clobberFlags: true, 21228 symEffect: SymRead, 21229 asm: s390x.AMOVWBR, 21230 reg: regInfo{ 21231 inputs: []inputInfo{ 21232 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21233 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21234 }, 21235 outputs: []outputInfo{ 21236 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21237 }, 21238 }, 21239 }, 21240 { 21241 name: "MOVDBRloadidx", 21242 auxType: auxSymOff, 21243 argLen: 3, 21244 commutative: true, 21245 clobberFlags: true, 21246 symEffect: SymRead, 21247 asm: s390x.AMOVDBR, 21248 reg: regInfo{ 21249 inputs: []inputInfo{ 21250 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21251 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21252 }, 21253 outputs: []outputInfo{ 21254 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21255 }, 21256 }, 21257 }, 21258 { 21259 name: "MOVBstoreidx", 21260 auxType: auxSymOff, 21261 argLen: 4, 21262 commutative: true, 21263 clobberFlags: true, 21264 symEffect: SymWrite, 21265 asm: s390x.AMOVB, 21266 reg: regInfo{ 21267 inputs: []inputInfo{ 21268 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21269 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21270 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21271 }, 21272 }, 21273 }, 21274 { 21275 name: "MOVHstoreidx", 21276 auxType: auxSymOff, 21277 argLen: 4, 21278 commutative: true, 21279 clobberFlags: true, 21280 symEffect: SymWrite, 21281 asm: s390x.AMOVH, 21282 reg: regInfo{ 21283 inputs: []inputInfo{ 21284 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21285 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21286 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21287 }, 21288 }, 21289 }, 21290 { 21291 name: "MOVWstoreidx", 21292 auxType: auxSymOff, 21293 argLen: 4, 21294 commutative: true, 21295 clobberFlags: true, 21296 symEffect: SymWrite, 21297 asm: s390x.AMOVW, 21298 reg: regInfo{ 21299 inputs: []inputInfo{ 21300 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21301 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21302 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21303 }, 21304 }, 21305 }, 21306 { 21307 name: "MOVDstoreidx", 21308 auxType: auxSymOff, 21309 argLen: 4, 21310 commutative: true, 21311 clobberFlags: true, 21312 symEffect: SymWrite, 21313 asm: s390x.AMOVD, 21314 reg: regInfo{ 21315 inputs: []inputInfo{ 21316 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21317 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21318 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21319 }, 21320 }, 21321 }, 21322 { 21323 name: "MOVHBRstoreidx", 21324 auxType: auxSymOff, 21325 argLen: 4, 21326 commutative: true, 21327 clobberFlags: true, 21328 symEffect: SymWrite, 21329 asm: s390x.AMOVHBR, 21330 reg: regInfo{ 21331 inputs: []inputInfo{ 21332 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21333 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21334 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21335 }, 21336 }, 21337 }, 21338 { 21339 name: "MOVWBRstoreidx", 21340 auxType: auxSymOff, 21341 argLen: 4, 21342 commutative: true, 21343 clobberFlags: true, 21344 symEffect: SymWrite, 21345 asm: s390x.AMOVWBR, 21346 reg: regInfo{ 21347 inputs: []inputInfo{ 21348 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21349 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21350 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21351 }, 21352 }, 21353 }, 21354 { 21355 name: "MOVDBRstoreidx", 21356 auxType: auxSymOff, 21357 argLen: 4, 21358 commutative: true, 21359 clobberFlags: true, 21360 symEffect: SymWrite, 21361 asm: s390x.AMOVDBR, 21362 reg: regInfo{ 21363 inputs: []inputInfo{ 21364 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21365 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21366 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21367 }, 21368 }, 21369 }, 21370 { 21371 name: "MOVBstoreconst", 21372 auxType: auxSymValAndOff, 21373 argLen: 2, 21374 faultOnNilArg0: true, 21375 symEffect: SymWrite, 21376 asm: s390x.AMOVB, 21377 reg: regInfo{ 21378 inputs: []inputInfo{ 21379 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21380 }, 21381 }, 21382 }, 21383 { 21384 name: "MOVHstoreconst", 21385 auxType: auxSymValAndOff, 21386 argLen: 2, 21387 faultOnNilArg0: true, 21388 symEffect: SymWrite, 21389 asm: s390x.AMOVH, 21390 reg: regInfo{ 21391 inputs: []inputInfo{ 21392 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21393 }, 21394 }, 21395 }, 21396 { 21397 name: "MOVWstoreconst", 21398 auxType: auxSymValAndOff, 21399 argLen: 2, 21400 faultOnNilArg0: true, 21401 symEffect: SymWrite, 21402 asm: s390x.AMOVW, 21403 reg: regInfo{ 21404 inputs: []inputInfo{ 21405 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21406 }, 21407 }, 21408 }, 21409 { 21410 name: "MOVDstoreconst", 21411 auxType: auxSymValAndOff, 21412 argLen: 2, 21413 faultOnNilArg0: true, 21414 symEffect: SymWrite, 21415 asm: s390x.AMOVD, 21416 reg: regInfo{ 21417 inputs: []inputInfo{ 21418 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21419 }, 21420 }, 21421 }, 21422 { 21423 name: "CLEAR", 21424 auxType: auxSymValAndOff, 21425 argLen: 2, 21426 clobberFlags: true, 21427 faultOnNilArg0: true, 21428 symEffect: SymWrite, 21429 asm: s390x.ACLEAR, 21430 reg: regInfo{ 21431 inputs: []inputInfo{ 21432 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21433 }, 21434 }, 21435 }, 21436 { 21437 name: "CALLstatic", 21438 auxType: auxSymOff, 21439 argLen: 1, 21440 clobberFlags: true, 21441 call: true, 21442 symEffect: SymNone, 21443 reg: regInfo{ 21444 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21445 }, 21446 }, 21447 { 21448 name: "CALLclosure", 21449 auxType: auxInt64, 21450 argLen: 3, 21451 clobberFlags: true, 21452 call: true, 21453 reg: regInfo{ 21454 inputs: []inputInfo{ 21455 {1, 4096}, // R12 21456 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21457 }, 21458 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21459 }, 21460 }, 21461 { 21462 name: "CALLinter", 21463 auxType: auxInt64, 21464 argLen: 2, 21465 clobberFlags: true, 21466 call: true, 21467 reg: regInfo{ 21468 inputs: []inputInfo{ 21469 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21470 }, 21471 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21472 }, 21473 }, 21474 { 21475 name: "InvertFlags", 21476 argLen: 1, 21477 reg: regInfo{}, 21478 }, 21479 { 21480 name: "LoweredGetG", 21481 argLen: 1, 21482 reg: regInfo{ 21483 outputs: []outputInfo{ 21484 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21485 }, 21486 }, 21487 }, 21488 { 21489 name: "LoweredGetClosurePtr", 21490 argLen: 0, 21491 reg: regInfo{ 21492 outputs: []outputInfo{ 21493 {0, 4096}, // R12 21494 }, 21495 }, 21496 }, 21497 { 21498 name: "LoweredGetCallerSP", 21499 argLen: 0, 21500 rematerializeable: true, 21501 reg: regInfo{ 21502 outputs: []outputInfo{ 21503 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21504 }, 21505 }, 21506 }, 21507 { 21508 name: "LoweredNilCheck", 21509 argLen: 2, 21510 clobberFlags: true, 21511 nilCheck: true, 21512 faultOnNilArg0: true, 21513 reg: regInfo{ 21514 inputs: []inputInfo{ 21515 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21516 }, 21517 }, 21518 }, 21519 { 21520 name: "LoweredRound32F", 21521 argLen: 1, 21522 resultInArg0: true, 21523 reg: regInfo{ 21524 inputs: []inputInfo{ 21525 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21526 }, 21527 outputs: []outputInfo{ 21528 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21529 }, 21530 }, 21531 }, 21532 { 21533 name: "LoweredRound64F", 21534 argLen: 1, 21535 resultInArg0: true, 21536 reg: regInfo{ 21537 inputs: []inputInfo{ 21538 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21539 }, 21540 outputs: []outputInfo{ 21541 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21542 }, 21543 }, 21544 }, 21545 { 21546 name: "MOVDconvert", 21547 argLen: 2, 21548 asm: s390x.AMOVD, 21549 reg: regInfo{ 21550 inputs: []inputInfo{ 21551 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21552 }, 21553 outputs: []outputInfo{ 21554 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21555 }, 21556 }, 21557 }, 21558 { 21559 name: "FlagEQ", 21560 argLen: 0, 21561 reg: regInfo{}, 21562 }, 21563 { 21564 name: "FlagLT", 21565 argLen: 0, 21566 reg: regInfo{}, 21567 }, 21568 { 21569 name: "FlagGT", 21570 argLen: 0, 21571 reg: regInfo{}, 21572 }, 21573 { 21574 name: "MOVWZatomicload", 21575 auxType: auxSymOff, 21576 argLen: 2, 21577 faultOnNilArg0: true, 21578 symEffect: SymRead, 21579 asm: s390x.AMOVWZ, 21580 reg: regInfo{ 21581 inputs: []inputInfo{ 21582 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21583 }, 21584 outputs: []outputInfo{ 21585 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21586 }, 21587 }, 21588 }, 21589 { 21590 name: "MOVDatomicload", 21591 auxType: auxSymOff, 21592 argLen: 2, 21593 faultOnNilArg0: true, 21594 symEffect: SymRead, 21595 asm: s390x.AMOVD, 21596 reg: regInfo{ 21597 inputs: []inputInfo{ 21598 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21599 }, 21600 outputs: []outputInfo{ 21601 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21602 }, 21603 }, 21604 }, 21605 { 21606 name: "MOVWatomicstore", 21607 auxType: auxSymOff, 21608 argLen: 3, 21609 clobberFlags: true, 21610 faultOnNilArg0: true, 21611 hasSideEffects: true, 21612 symEffect: SymWrite, 21613 asm: s390x.AMOVW, 21614 reg: regInfo{ 21615 inputs: []inputInfo{ 21616 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21617 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21618 }, 21619 }, 21620 }, 21621 { 21622 name: "MOVDatomicstore", 21623 auxType: auxSymOff, 21624 argLen: 3, 21625 clobberFlags: true, 21626 faultOnNilArg0: true, 21627 hasSideEffects: true, 21628 symEffect: SymWrite, 21629 asm: s390x.AMOVD, 21630 reg: regInfo{ 21631 inputs: []inputInfo{ 21632 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21633 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21634 }, 21635 }, 21636 }, 21637 { 21638 name: "LAA", 21639 auxType: auxSymOff, 21640 argLen: 3, 21641 faultOnNilArg0: true, 21642 hasSideEffects: true, 21643 symEffect: SymRdWr, 21644 asm: s390x.ALAA, 21645 reg: regInfo{ 21646 inputs: []inputInfo{ 21647 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21648 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21649 }, 21650 outputs: []outputInfo{ 21651 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21652 }, 21653 }, 21654 }, 21655 { 21656 name: "LAAG", 21657 auxType: auxSymOff, 21658 argLen: 3, 21659 faultOnNilArg0: true, 21660 hasSideEffects: true, 21661 symEffect: SymRdWr, 21662 asm: s390x.ALAAG, 21663 reg: regInfo{ 21664 inputs: []inputInfo{ 21665 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21666 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21667 }, 21668 outputs: []outputInfo{ 21669 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21670 }, 21671 }, 21672 }, 21673 { 21674 name: "AddTupleFirst32", 21675 argLen: 2, 21676 reg: regInfo{}, 21677 }, 21678 { 21679 name: "AddTupleFirst64", 21680 argLen: 2, 21681 reg: regInfo{}, 21682 }, 21683 { 21684 name: "LoweredAtomicCas32", 21685 auxType: auxSymOff, 21686 argLen: 4, 21687 clobberFlags: true, 21688 faultOnNilArg0: true, 21689 hasSideEffects: true, 21690 symEffect: SymRdWr, 21691 asm: s390x.ACS, 21692 reg: regInfo{ 21693 inputs: []inputInfo{ 21694 {1, 1}, // R0 21695 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21696 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21697 }, 21698 clobbers: 1, // R0 21699 outputs: []outputInfo{ 21700 {1, 0}, 21701 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21702 }, 21703 }, 21704 }, 21705 { 21706 name: "LoweredAtomicCas64", 21707 auxType: auxSymOff, 21708 argLen: 4, 21709 clobberFlags: true, 21710 faultOnNilArg0: true, 21711 hasSideEffects: true, 21712 symEffect: SymRdWr, 21713 asm: s390x.ACSG, 21714 reg: regInfo{ 21715 inputs: []inputInfo{ 21716 {1, 1}, // R0 21717 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21718 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21719 }, 21720 clobbers: 1, // R0 21721 outputs: []outputInfo{ 21722 {1, 0}, 21723 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21724 }, 21725 }, 21726 }, 21727 { 21728 name: "LoweredAtomicExchange32", 21729 auxType: auxSymOff, 21730 argLen: 3, 21731 clobberFlags: true, 21732 faultOnNilArg0: true, 21733 hasSideEffects: true, 21734 symEffect: SymRdWr, 21735 asm: s390x.ACS, 21736 reg: regInfo{ 21737 inputs: []inputInfo{ 21738 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21739 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21740 }, 21741 outputs: []outputInfo{ 21742 {1, 0}, 21743 {0, 1}, // R0 21744 }, 21745 }, 21746 }, 21747 { 21748 name: "LoweredAtomicExchange64", 21749 auxType: auxSymOff, 21750 argLen: 3, 21751 clobberFlags: true, 21752 faultOnNilArg0: true, 21753 hasSideEffects: true, 21754 symEffect: SymRdWr, 21755 asm: s390x.ACSG, 21756 reg: regInfo{ 21757 inputs: []inputInfo{ 21758 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21759 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21760 }, 21761 outputs: []outputInfo{ 21762 {1, 0}, 21763 {0, 1}, // R0 21764 }, 21765 }, 21766 }, 21767 { 21768 name: "FLOGR", 21769 argLen: 1, 21770 clobberFlags: true, 21771 asm: s390x.AFLOGR, 21772 reg: regInfo{ 21773 inputs: []inputInfo{ 21774 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21775 }, 21776 clobbers: 2, // R1 21777 outputs: []outputInfo{ 21778 {0, 1}, // R0 21779 }, 21780 }, 21781 }, 21782 { 21783 name: "STMG2", 21784 auxType: auxSymOff, 21785 argLen: 4, 21786 faultOnNilArg0: true, 21787 symEffect: SymWrite, 21788 asm: s390x.ASTMG, 21789 reg: regInfo{ 21790 inputs: []inputInfo{ 21791 {1, 2}, // R1 21792 {2, 4}, // R2 21793 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21794 }, 21795 }, 21796 }, 21797 { 21798 name: "STMG3", 21799 auxType: auxSymOff, 21800 argLen: 5, 21801 faultOnNilArg0: true, 21802 symEffect: SymWrite, 21803 asm: s390x.ASTMG, 21804 reg: regInfo{ 21805 inputs: []inputInfo{ 21806 {1, 2}, // R1 21807 {2, 4}, // R2 21808 {3, 8}, // R3 21809 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21810 }, 21811 }, 21812 }, 21813 { 21814 name: "STMG4", 21815 auxType: auxSymOff, 21816 argLen: 6, 21817 faultOnNilArg0: true, 21818 symEffect: SymWrite, 21819 asm: s390x.ASTMG, 21820 reg: regInfo{ 21821 inputs: []inputInfo{ 21822 {1, 2}, // R1 21823 {2, 4}, // R2 21824 {3, 8}, // R3 21825 {4, 16}, // R4 21826 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21827 }, 21828 }, 21829 }, 21830 { 21831 name: "STM2", 21832 auxType: auxSymOff, 21833 argLen: 4, 21834 faultOnNilArg0: true, 21835 symEffect: SymWrite, 21836 asm: s390x.ASTMY, 21837 reg: regInfo{ 21838 inputs: []inputInfo{ 21839 {1, 2}, // R1 21840 {2, 4}, // R2 21841 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21842 }, 21843 }, 21844 }, 21845 { 21846 name: "STM3", 21847 auxType: auxSymOff, 21848 argLen: 5, 21849 faultOnNilArg0: true, 21850 symEffect: SymWrite, 21851 asm: s390x.ASTMY, 21852 reg: regInfo{ 21853 inputs: []inputInfo{ 21854 {1, 2}, // R1 21855 {2, 4}, // R2 21856 {3, 8}, // R3 21857 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21858 }, 21859 }, 21860 }, 21861 { 21862 name: "STM4", 21863 auxType: auxSymOff, 21864 argLen: 6, 21865 faultOnNilArg0: true, 21866 symEffect: SymWrite, 21867 asm: s390x.ASTMY, 21868 reg: regInfo{ 21869 inputs: []inputInfo{ 21870 {1, 2}, // R1 21871 {2, 4}, // R2 21872 {3, 8}, // R3 21873 {4, 16}, // R4 21874 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21875 }, 21876 }, 21877 }, 21878 { 21879 name: "LoweredMove", 21880 auxType: auxInt64, 21881 argLen: 4, 21882 clobberFlags: true, 21883 faultOnNilArg0: true, 21884 faultOnNilArg1: true, 21885 reg: regInfo{ 21886 inputs: []inputInfo{ 21887 {0, 2}, // R1 21888 {1, 4}, // R2 21889 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21890 }, 21891 clobbers: 6, // R1 R2 21892 }, 21893 }, 21894 { 21895 name: "LoweredZero", 21896 auxType: auxInt64, 21897 argLen: 3, 21898 clobberFlags: true, 21899 faultOnNilArg0: true, 21900 reg: regInfo{ 21901 inputs: []inputInfo{ 21902 {0, 2}, // R1 21903 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21904 }, 21905 clobbers: 2, // R1 21906 }, 21907 }, 21908 21909 { 21910 name: "Add8", 21911 argLen: 2, 21912 commutative: true, 21913 generic: true, 21914 }, 21915 { 21916 name: "Add16", 21917 argLen: 2, 21918 commutative: true, 21919 generic: true, 21920 }, 21921 { 21922 name: "Add32", 21923 argLen: 2, 21924 commutative: true, 21925 generic: true, 21926 }, 21927 { 21928 name: "Add64", 21929 argLen: 2, 21930 commutative: true, 21931 generic: true, 21932 }, 21933 { 21934 name: "AddPtr", 21935 argLen: 2, 21936 generic: true, 21937 }, 21938 { 21939 name: "Add32F", 21940 argLen: 2, 21941 commutative: true, 21942 generic: true, 21943 }, 21944 { 21945 name: "Add64F", 21946 argLen: 2, 21947 commutative: true, 21948 generic: true, 21949 }, 21950 { 21951 name: "Sub8", 21952 argLen: 2, 21953 generic: true, 21954 }, 21955 { 21956 name: "Sub16", 21957 argLen: 2, 21958 generic: true, 21959 }, 21960 { 21961 name: "Sub32", 21962 argLen: 2, 21963 generic: true, 21964 }, 21965 { 21966 name: "Sub64", 21967 argLen: 2, 21968 generic: true, 21969 }, 21970 { 21971 name: "SubPtr", 21972 argLen: 2, 21973 generic: true, 21974 }, 21975 { 21976 name: "Sub32F", 21977 argLen: 2, 21978 generic: true, 21979 }, 21980 { 21981 name: "Sub64F", 21982 argLen: 2, 21983 generic: true, 21984 }, 21985 { 21986 name: "Mul8", 21987 argLen: 2, 21988 commutative: true, 21989 generic: true, 21990 }, 21991 { 21992 name: "Mul16", 21993 argLen: 2, 21994 commutative: true, 21995 generic: true, 21996 }, 21997 { 21998 name: "Mul32", 21999 argLen: 2, 22000 commutative: true, 22001 generic: true, 22002 }, 22003 { 22004 name: "Mul64", 22005 argLen: 2, 22006 commutative: true, 22007 generic: true, 22008 }, 22009 { 22010 name: "Mul32F", 22011 argLen: 2, 22012 commutative: true, 22013 generic: true, 22014 }, 22015 { 22016 name: "Mul64F", 22017 argLen: 2, 22018 commutative: true, 22019 generic: true, 22020 }, 22021 { 22022 name: "Div32F", 22023 argLen: 2, 22024 generic: true, 22025 }, 22026 { 22027 name: "Div64F", 22028 argLen: 2, 22029 generic: true, 22030 }, 22031 { 22032 name: "Hmul32", 22033 argLen: 2, 22034 commutative: true, 22035 generic: true, 22036 }, 22037 { 22038 name: "Hmul32u", 22039 argLen: 2, 22040 commutative: true, 22041 generic: true, 22042 }, 22043 { 22044 name: "Hmul64", 22045 argLen: 2, 22046 commutative: true, 22047 generic: true, 22048 }, 22049 { 22050 name: "Hmul64u", 22051 argLen: 2, 22052 commutative: true, 22053 generic: true, 22054 }, 22055 { 22056 name: "Mul32uhilo", 22057 argLen: 2, 22058 commutative: true, 22059 generic: true, 22060 }, 22061 { 22062 name: "Mul64uhilo", 22063 argLen: 2, 22064 commutative: true, 22065 generic: true, 22066 }, 22067 { 22068 name: "Avg32u", 22069 argLen: 2, 22070 generic: true, 22071 }, 22072 { 22073 name: "Avg64u", 22074 argLen: 2, 22075 generic: true, 22076 }, 22077 { 22078 name: "Div8", 22079 argLen: 2, 22080 generic: true, 22081 }, 22082 { 22083 name: "Div8u", 22084 argLen: 2, 22085 generic: true, 22086 }, 22087 { 22088 name: "Div16", 22089 argLen: 2, 22090 generic: true, 22091 }, 22092 { 22093 name: "Div16u", 22094 argLen: 2, 22095 generic: true, 22096 }, 22097 { 22098 name: "Div32", 22099 argLen: 2, 22100 generic: true, 22101 }, 22102 { 22103 name: "Div32u", 22104 argLen: 2, 22105 generic: true, 22106 }, 22107 { 22108 name: "Div64", 22109 argLen: 2, 22110 generic: true, 22111 }, 22112 { 22113 name: "Div64u", 22114 argLen: 2, 22115 generic: true, 22116 }, 22117 { 22118 name: "Div128u", 22119 argLen: 3, 22120 generic: true, 22121 }, 22122 { 22123 name: "Mod8", 22124 argLen: 2, 22125 generic: true, 22126 }, 22127 { 22128 name: "Mod8u", 22129 argLen: 2, 22130 generic: true, 22131 }, 22132 { 22133 name: "Mod16", 22134 argLen: 2, 22135 generic: true, 22136 }, 22137 { 22138 name: "Mod16u", 22139 argLen: 2, 22140 generic: true, 22141 }, 22142 { 22143 name: "Mod32", 22144 argLen: 2, 22145 generic: true, 22146 }, 22147 { 22148 name: "Mod32u", 22149 argLen: 2, 22150 generic: true, 22151 }, 22152 { 22153 name: "Mod64", 22154 argLen: 2, 22155 generic: true, 22156 }, 22157 { 22158 name: "Mod64u", 22159 argLen: 2, 22160 generic: true, 22161 }, 22162 { 22163 name: "And8", 22164 argLen: 2, 22165 commutative: true, 22166 generic: true, 22167 }, 22168 { 22169 name: "And16", 22170 argLen: 2, 22171 commutative: true, 22172 generic: true, 22173 }, 22174 { 22175 name: "And32", 22176 argLen: 2, 22177 commutative: true, 22178 generic: true, 22179 }, 22180 { 22181 name: "And64", 22182 argLen: 2, 22183 commutative: true, 22184 generic: true, 22185 }, 22186 { 22187 name: "Or8", 22188 argLen: 2, 22189 commutative: true, 22190 generic: true, 22191 }, 22192 { 22193 name: "Or16", 22194 argLen: 2, 22195 commutative: true, 22196 generic: true, 22197 }, 22198 { 22199 name: "Or32", 22200 argLen: 2, 22201 commutative: true, 22202 generic: true, 22203 }, 22204 { 22205 name: "Or64", 22206 argLen: 2, 22207 commutative: true, 22208 generic: true, 22209 }, 22210 { 22211 name: "Xor8", 22212 argLen: 2, 22213 commutative: true, 22214 generic: true, 22215 }, 22216 { 22217 name: "Xor16", 22218 argLen: 2, 22219 commutative: true, 22220 generic: true, 22221 }, 22222 { 22223 name: "Xor32", 22224 argLen: 2, 22225 commutative: true, 22226 generic: true, 22227 }, 22228 { 22229 name: "Xor64", 22230 argLen: 2, 22231 commutative: true, 22232 generic: true, 22233 }, 22234 { 22235 name: "Lsh8x8", 22236 argLen: 2, 22237 generic: true, 22238 }, 22239 { 22240 name: "Lsh8x16", 22241 argLen: 2, 22242 generic: true, 22243 }, 22244 { 22245 name: "Lsh8x32", 22246 argLen: 2, 22247 generic: true, 22248 }, 22249 { 22250 name: "Lsh8x64", 22251 argLen: 2, 22252 generic: true, 22253 }, 22254 { 22255 name: "Lsh16x8", 22256 argLen: 2, 22257 generic: true, 22258 }, 22259 { 22260 name: "Lsh16x16", 22261 argLen: 2, 22262 generic: true, 22263 }, 22264 { 22265 name: "Lsh16x32", 22266 argLen: 2, 22267 generic: true, 22268 }, 22269 { 22270 name: "Lsh16x64", 22271 argLen: 2, 22272 generic: true, 22273 }, 22274 { 22275 name: "Lsh32x8", 22276 argLen: 2, 22277 generic: true, 22278 }, 22279 { 22280 name: "Lsh32x16", 22281 argLen: 2, 22282 generic: true, 22283 }, 22284 { 22285 name: "Lsh32x32", 22286 argLen: 2, 22287 generic: true, 22288 }, 22289 { 22290 name: "Lsh32x64", 22291 argLen: 2, 22292 generic: true, 22293 }, 22294 { 22295 name: "Lsh64x8", 22296 argLen: 2, 22297 generic: true, 22298 }, 22299 { 22300 name: "Lsh64x16", 22301 argLen: 2, 22302 generic: true, 22303 }, 22304 { 22305 name: "Lsh64x32", 22306 argLen: 2, 22307 generic: true, 22308 }, 22309 { 22310 name: "Lsh64x64", 22311 argLen: 2, 22312 generic: true, 22313 }, 22314 { 22315 name: "Rsh8x8", 22316 argLen: 2, 22317 generic: true, 22318 }, 22319 { 22320 name: "Rsh8x16", 22321 argLen: 2, 22322 generic: true, 22323 }, 22324 { 22325 name: "Rsh8x32", 22326 argLen: 2, 22327 generic: true, 22328 }, 22329 { 22330 name: "Rsh8x64", 22331 argLen: 2, 22332 generic: true, 22333 }, 22334 { 22335 name: "Rsh16x8", 22336 argLen: 2, 22337 generic: true, 22338 }, 22339 { 22340 name: "Rsh16x16", 22341 argLen: 2, 22342 generic: true, 22343 }, 22344 { 22345 name: "Rsh16x32", 22346 argLen: 2, 22347 generic: true, 22348 }, 22349 { 22350 name: "Rsh16x64", 22351 argLen: 2, 22352 generic: true, 22353 }, 22354 { 22355 name: "Rsh32x8", 22356 argLen: 2, 22357 generic: true, 22358 }, 22359 { 22360 name: "Rsh32x16", 22361 argLen: 2, 22362 generic: true, 22363 }, 22364 { 22365 name: "Rsh32x32", 22366 argLen: 2, 22367 generic: true, 22368 }, 22369 { 22370 name: "Rsh32x64", 22371 argLen: 2, 22372 generic: true, 22373 }, 22374 { 22375 name: "Rsh64x8", 22376 argLen: 2, 22377 generic: true, 22378 }, 22379 { 22380 name: "Rsh64x16", 22381 argLen: 2, 22382 generic: true, 22383 }, 22384 { 22385 name: "Rsh64x32", 22386 argLen: 2, 22387 generic: true, 22388 }, 22389 { 22390 name: "Rsh64x64", 22391 argLen: 2, 22392 generic: true, 22393 }, 22394 { 22395 name: "Rsh8Ux8", 22396 argLen: 2, 22397 generic: true, 22398 }, 22399 { 22400 name: "Rsh8Ux16", 22401 argLen: 2, 22402 generic: true, 22403 }, 22404 { 22405 name: "Rsh8Ux32", 22406 argLen: 2, 22407 generic: true, 22408 }, 22409 { 22410 name: "Rsh8Ux64", 22411 argLen: 2, 22412 generic: true, 22413 }, 22414 { 22415 name: "Rsh16Ux8", 22416 argLen: 2, 22417 generic: true, 22418 }, 22419 { 22420 name: "Rsh16Ux16", 22421 argLen: 2, 22422 generic: true, 22423 }, 22424 { 22425 name: "Rsh16Ux32", 22426 argLen: 2, 22427 generic: true, 22428 }, 22429 { 22430 name: "Rsh16Ux64", 22431 argLen: 2, 22432 generic: true, 22433 }, 22434 { 22435 name: "Rsh32Ux8", 22436 argLen: 2, 22437 generic: true, 22438 }, 22439 { 22440 name: "Rsh32Ux16", 22441 argLen: 2, 22442 generic: true, 22443 }, 22444 { 22445 name: "Rsh32Ux32", 22446 argLen: 2, 22447 generic: true, 22448 }, 22449 { 22450 name: "Rsh32Ux64", 22451 argLen: 2, 22452 generic: true, 22453 }, 22454 { 22455 name: "Rsh64Ux8", 22456 argLen: 2, 22457 generic: true, 22458 }, 22459 { 22460 name: "Rsh64Ux16", 22461 argLen: 2, 22462 generic: true, 22463 }, 22464 { 22465 name: "Rsh64Ux32", 22466 argLen: 2, 22467 generic: true, 22468 }, 22469 { 22470 name: "Rsh64Ux64", 22471 argLen: 2, 22472 generic: true, 22473 }, 22474 { 22475 name: "Eq8", 22476 argLen: 2, 22477 commutative: true, 22478 generic: true, 22479 }, 22480 { 22481 name: "Eq16", 22482 argLen: 2, 22483 commutative: true, 22484 generic: true, 22485 }, 22486 { 22487 name: "Eq32", 22488 argLen: 2, 22489 commutative: true, 22490 generic: true, 22491 }, 22492 { 22493 name: "Eq64", 22494 argLen: 2, 22495 commutative: true, 22496 generic: true, 22497 }, 22498 { 22499 name: "EqPtr", 22500 argLen: 2, 22501 commutative: true, 22502 generic: true, 22503 }, 22504 { 22505 name: "EqInter", 22506 argLen: 2, 22507 generic: true, 22508 }, 22509 { 22510 name: "EqSlice", 22511 argLen: 2, 22512 generic: true, 22513 }, 22514 { 22515 name: "Eq32F", 22516 argLen: 2, 22517 commutative: true, 22518 generic: true, 22519 }, 22520 { 22521 name: "Eq64F", 22522 argLen: 2, 22523 commutative: true, 22524 generic: true, 22525 }, 22526 { 22527 name: "Neq8", 22528 argLen: 2, 22529 commutative: true, 22530 generic: true, 22531 }, 22532 { 22533 name: "Neq16", 22534 argLen: 2, 22535 commutative: true, 22536 generic: true, 22537 }, 22538 { 22539 name: "Neq32", 22540 argLen: 2, 22541 commutative: true, 22542 generic: true, 22543 }, 22544 { 22545 name: "Neq64", 22546 argLen: 2, 22547 commutative: true, 22548 generic: true, 22549 }, 22550 { 22551 name: "NeqPtr", 22552 argLen: 2, 22553 commutative: true, 22554 generic: true, 22555 }, 22556 { 22557 name: "NeqInter", 22558 argLen: 2, 22559 generic: true, 22560 }, 22561 { 22562 name: "NeqSlice", 22563 argLen: 2, 22564 generic: true, 22565 }, 22566 { 22567 name: "Neq32F", 22568 argLen: 2, 22569 commutative: true, 22570 generic: true, 22571 }, 22572 { 22573 name: "Neq64F", 22574 argLen: 2, 22575 commutative: true, 22576 generic: true, 22577 }, 22578 { 22579 name: "Less8", 22580 argLen: 2, 22581 generic: true, 22582 }, 22583 { 22584 name: "Less8U", 22585 argLen: 2, 22586 generic: true, 22587 }, 22588 { 22589 name: "Less16", 22590 argLen: 2, 22591 generic: true, 22592 }, 22593 { 22594 name: "Less16U", 22595 argLen: 2, 22596 generic: true, 22597 }, 22598 { 22599 name: "Less32", 22600 argLen: 2, 22601 generic: true, 22602 }, 22603 { 22604 name: "Less32U", 22605 argLen: 2, 22606 generic: true, 22607 }, 22608 { 22609 name: "Less64", 22610 argLen: 2, 22611 generic: true, 22612 }, 22613 { 22614 name: "Less64U", 22615 argLen: 2, 22616 generic: true, 22617 }, 22618 { 22619 name: "Less32F", 22620 argLen: 2, 22621 generic: true, 22622 }, 22623 { 22624 name: "Less64F", 22625 argLen: 2, 22626 generic: true, 22627 }, 22628 { 22629 name: "Leq8", 22630 argLen: 2, 22631 generic: true, 22632 }, 22633 { 22634 name: "Leq8U", 22635 argLen: 2, 22636 generic: true, 22637 }, 22638 { 22639 name: "Leq16", 22640 argLen: 2, 22641 generic: true, 22642 }, 22643 { 22644 name: "Leq16U", 22645 argLen: 2, 22646 generic: true, 22647 }, 22648 { 22649 name: "Leq32", 22650 argLen: 2, 22651 generic: true, 22652 }, 22653 { 22654 name: "Leq32U", 22655 argLen: 2, 22656 generic: true, 22657 }, 22658 { 22659 name: "Leq64", 22660 argLen: 2, 22661 generic: true, 22662 }, 22663 { 22664 name: "Leq64U", 22665 argLen: 2, 22666 generic: true, 22667 }, 22668 { 22669 name: "Leq32F", 22670 argLen: 2, 22671 generic: true, 22672 }, 22673 { 22674 name: "Leq64F", 22675 argLen: 2, 22676 generic: true, 22677 }, 22678 { 22679 name: "Greater8", 22680 argLen: 2, 22681 generic: true, 22682 }, 22683 { 22684 name: "Greater8U", 22685 argLen: 2, 22686 generic: true, 22687 }, 22688 { 22689 name: "Greater16", 22690 argLen: 2, 22691 generic: true, 22692 }, 22693 { 22694 name: "Greater16U", 22695 argLen: 2, 22696 generic: true, 22697 }, 22698 { 22699 name: "Greater32", 22700 argLen: 2, 22701 generic: true, 22702 }, 22703 { 22704 name: "Greater32U", 22705 argLen: 2, 22706 generic: true, 22707 }, 22708 { 22709 name: "Greater64", 22710 argLen: 2, 22711 generic: true, 22712 }, 22713 { 22714 name: "Greater64U", 22715 argLen: 2, 22716 generic: true, 22717 }, 22718 { 22719 name: "Greater32F", 22720 argLen: 2, 22721 generic: true, 22722 }, 22723 { 22724 name: "Greater64F", 22725 argLen: 2, 22726 generic: true, 22727 }, 22728 { 22729 name: "Geq8", 22730 argLen: 2, 22731 generic: true, 22732 }, 22733 { 22734 name: "Geq8U", 22735 argLen: 2, 22736 generic: true, 22737 }, 22738 { 22739 name: "Geq16", 22740 argLen: 2, 22741 generic: true, 22742 }, 22743 { 22744 name: "Geq16U", 22745 argLen: 2, 22746 generic: true, 22747 }, 22748 { 22749 name: "Geq32", 22750 argLen: 2, 22751 generic: true, 22752 }, 22753 { 22754 name: "Geq32U", 22755 argLen: 2, 22756 generic: true, 22757 }, 22758 { 22759 name: "Geq64", 22760 argLen: 2, 22761 generic: true, 22762 }, 22763 { 22764 name: "Geq64U", 22765 argLen: 2, 22766 generic: true, 22767 }, 22768 { 22769 name: "Geq32F", 22770 argLen: 2, 22771 generic: true, 22772 }, 22773 { 22774 name: "Geq64F", 22775 argLen: 2, 22776 generic: true, 22777 }, 22778 { 22779 name: "AndB", 22780 argLen: 2, 22781 commutative: true, 22782 generic: true, 22783 }, 22784 { 22785 name: "OrB", 22786 argLen: 2, 22787 commutative: true, 22788 generic: true, 22789 }, 22790 { 22791 name: "EqB", 22792 argLen: 2, 22793 commutative: true, 22794 generic: true, 22795 }, 22796 { 22797 name: "NeqB", 22798 argLen: 2, 22799 commutative: true, 22800 generic: true, 22801 }, 22802 { 22803 name: "Not", 22804 argLen: 1, 22805 generic: true, 22806 }, 22807 { 22808 name: "Neg8", 22809 argLen: 1, 22810 generic: true, 22811 }, 22812 { 22813 name: "Neg16", 22814 argLen: 1, 22815 generic: true, 22816 }, 22817 { 22818 name: "Neg32", 22819 argLen: 1, 22820 generic: true, 22821 }, 22822 { 22823 name: "Neg64", 22824 argLen: 1, 22825 generic: true, 22826 }, 22827 { 22828 name: "Neg32F", 22829 argLen: 1, 22830 generic: true, 22831 }, 22832 { 22833 name: "Neg64F", 22834 argLen: 1, 22835 generic: true, 22836 }, 22837 { 22838 name: "Com8", 22839 argLen: 1, 22840 generic: true, 22841 }, 22842 { 22843 name: "Com16", 22844 argLen: 1, 22845 generic: true, 22846 }, 22847 { 22848 name: "Com32", 22849 argLen: 1, 22850 generic: true, 22851 }, 22852 { 22853 name: "Com64", 22854 argLen: 1, 22855 generic: true, 22856 }, 22857 { 22858 name: "Ctz32", 22859 argLen: 1, 22860 generic: true, 22861 }, 22862 { 22863 name: "Ctz64", 22864 argLen: 1, 22865 generic: true, 22866 }, 22867 { 22868 name: "BitLen32", 22869 argLen: 1, 22870 generic: true, 22871 }, 22872 { 22873 name: "BitLen64", 22874 argLen: 1, 22875 generic: true, 22876 }, 22877 { 22878 name: "Bswap32", 22879 argLen: 1, 22880 generic: true, 22881 }, 22882 { 22883 name: "Bswap64", 22884 argLen: 1, 22885 generic: true, 22886 }, 22887 { 22888 name: "BitRev8", 22889 argLen: 1, 22890 generic: true, 22891 }, 22892 { 22893 name: "BitRev16", 22894 argLen: 1, 22895 generic: true, 22896 }, 22897 { 22898 name: "BitRev32", 22899 argLen: 1, 22900 generic: true, 22901 }, 22902 { 22903 name: "BitRev64", 22904 argLen: 1, 22905 generic: true, 22906 }, 22907 { 22908 name: "PopCount8", 22909 argLen: 1, 22910 generic: true, 22911 }, 22912 { 22913 name: "PopCount16", 22914 argLen: 1, 22915 generic: true, 22916 }, 22917 { 22918 name: "PopCount32", 22919 argLen: 1, 22920 generic: true, 22921 }, 22922 { 22923 name: "PopCount64", 22924 argLen: 1, 22925 generic: true, 22926 }, 22927 { 22928 name: "Sqrt", 22929 argLen: 1, 22930 generic: true, 22931 }, 22932 { 22933 name: "Floor", 22934 argLen: 1, 22935 generic: true, 22936 }, 22937 { 22938 name: "Ceil", 22939 argLen: 1, 22940 generic: true, 22941 }, 22942 { 22943 name: "Trunc", 22944 argLen: 1, 22945 generic: true, 22946 }, 22947 { 22948 name: "Round", 22949 argLen: 1, 22950 generic: true, 22951 }, 22952 { 22953 name: "Phi", 22954 argLen: -1, 22955 generic: true, 22956 }, 22957 { 22958 name: "Copy", 22959 argLen: 1, 22960 generic: true, 22961 }, 22962 { 22963 name: "Convert", 22964 argLen: 2, 22965 generic: true, 22966 }, 22967 { 22968 name: "ConstBool", 22969 auxType: auxBool, 22970 argLen: 0, 22971 generic: true, 22972 }, 22973 { 22974 name: "ConstString", 22975 auxType: auxString, 22976 argLen: 0, 22977 generic: true, 22978 }, 22979 { 22980 name: "ConstNil", 22981 argLen: 0, 22982 generic: true, 22983 }, 22984 { 22985 name: "Const8", 22986 auxType: auxInt8, 22987 argLen: 0, 22988 generic: true, 22989 }, 22990 { 22991 name: "Const16", 22992 auxType: auxInt16, 22993 argLen: 0, 22994 generic: true, 22995 }, 22996 { 22997 name: "Const32", 22998 auxType: auxInt32, 22999 argLen: 0, 23000 generic: true, 23001 }, 23002 { 23003 name: "Const64", 23004 auxType: auxInt64, 23005 argLen: 0, 23006 generic: true, 23007 }, 23008 { 23009 name: "Const32F", 23010 auxType: auxFloat32, 23011 argLen: 0, 23012 generic: true, 23013 }, 23014 { 23015 name: "Const64F", 23016 auxType: auxFloat64, 23017 argLen: 0, 23018 generic: true, 23019 }, 23020 { 23021 name: "ConstInterface", 23022 argLen: 0, 23023 generic: true, 23024 }, 23025 { 23026 name: "ConstSlice", 23027 argLen: 0, 23028 generic: true, 23029 }, 23030 { 23031 name: "InitMem", 23032 argLen: 0, 23033 generic: true, 23034 }, 23035 { 23036 name: "Arg", 23037 auxType: auxSymOff, 23038 argLen: 0, 23039 symEffect: SymRead, 23040 generic: true, 23041 }, 23042 { 23043 name: "Addr", 23044 auxType: auxSym, 23045 argLen: 1, 23046 symEffect: SymAddr, 23047 generic: true, 23048 }, 23049 { 23050 name: "SP", 23051 argLen: 0, 23052 generic: true, 23053 }, 23054 { 23055 name: "SB", 23056 argLen: 0, 23057 generic: true, 23058 }, 23059 { 23060 name: "Load", 23061 argLen: 2, 23062 generic: true, 23063 }, 23064 { 23065 name: "Store", 23066 auxType: auxTyp, 23067 argLen: 3, 23068 generic: true, 23069 }, 23070 { 23071 name: "Move", 23072 auxType: auxTypSize, 23073 argLen: 3, 23074 generic: true, 23075 }, 23076 { 23077 name: "Zero", 23078 auxType: auxTypSize, 23079 argLen: 2, 23080 generic: true, 23081 }, 23082 { 23083 name: "StoreWB", 23084 auxType: auxTyp, 23085 argLen: 3, 23086 generic: true, 23087 }, 23088 { 23089 name: "MoveWB", 23090 auxType: auxTypSize, 23091 argLen: 3, 23092 generic: true, 23093 }, 23094 { 23095 name: "ZeroWB", 23096 auxType: auxTypSize, 23097 argLen: 2, 23098 generic: true, 23099 }, 23100 { 23101 name: "ClosureCall", 23102 auxType: auxInt64, 23103 argLen: 3, 23104 call: true, 23105 generic: true, 23106 }, 23107 { 23108 name: "StaticCall", 23109 auxType: auxSymOff, 23110 argLen: 1, 23111 call: true, 23112 symEffect: SymNone, 23113 generic: true, 23114 }, 23115 { 23116 name: "InterCall", 23117 auxType: auxInt64, 23118 argLen: 2, 23119 call: true, 23120 generic: true, 23121 }, 23122 { 23123 name: "SignExt8to16", 23124 argLen: 1, 23125 generic: true, 23126 }, 23127 { 23128 name: "SignExt8to32", 23129 argLen: 1, 23130 generic: true, 23131 }, 23132 { 23133 name: "SignExt8to64", 23134 argLen: 1, 23135 generic: true, 23136 }, 23137 { 23138 name: "SignExt16to32", 23139 argLen: 1, 23140 generic: true, 23141 }, 23142 { 23143 name: "SignExt16to64", 23144 argLen: 1, 23145 generic: true, 23146 }, 23147 { 23148 name: "SignExt32to64", 23149 argLen: 1, 23150 generic: true, 23151 }, 23152 { 23153 name: "ZeroExt8to16", 23154 argLen: 1, 23155 generic: true, 23156 }, 23157 { 23158 name: "ZeroExt8to32", 23159 argLen: 1, 23160 generic: true, 23161 }, 23162 { 23163 name: "ZeroExt8to64", 23164 argLen: 1, 23165 generic: true, 23166 }, 23167 { 23168 name: "ZeroExt16to32", 23169 argLen: 1, 23170 generic: true, 23171 }, 23172 { 23173 name: "ZeroExt16to64", 23174 argLen: 1, 23175 generic: true, 23176 }, 23177 { 23178 name: "ZeroExt32to64", 23179 argLen: 1, 23180 generic: true, 23181 }, 23182 { 23183 name: "Trunc16to8", 23184 argLen: 1, 23185 generic: true, 23186 }, 23187 { 23188 name: "Trunc32to8", 23189 argLen: 1, 23190 generic: true, 23191 }, 23192 { 23193 name: "Trunc32to16", 23194 argLen: 1, 23195 generic: true, 23196 }, 23197 { 23198 name: "Trunc64to8", 23199 argLen: 1, 23200 generic: true, 23201 }, 23202 { 23203 name: "Trunc64to16", 23204 argLen: 1, 23205 generic: true, 23206 }, 23207 { 23208 name: "Trunc64to32", 23209 argLen: 1, 23210 generic: true, 23211 }, 23212 { 23213 name: "Cvt32to32F", 23214 argLen: 1, 23215 generic: true, 23216 }, 23217 { 23218 name: "Cvt32to64F", 23219 argLen: 1, 23220 generic: true, 23221 }, 23222 { 23223 name: "Cvt64to32F", 23224 argLen: 1, 23225 generic: true, 23226 }, 23227 { 23228 name: "Cvt64to64F", 23229 argLen: 1, 23230 generic: true, 23231 }, 23232 { 23233 name: "Cvt32Fto32", 23234 argLen: 1, 23235 generic: true, 23236 }, 23237 { 23238 name: "Cvt32Fto64", 23239 argLen: 1, 23240 generic: true, 23241 }, 23242 { 23243 name: "Cvt64Fto32", 23244 argLen: 1, 23245 generic: true, 23246 }, 23247 { 23248 name: "Cvt64Fto64", 23249 argLen: 1, 23250 generic: true, 23251 }, 23252 { 23253 name: "Cvt32Fto64F", 23254 argLen: 1, 23255 generic: true, 23256 }, 23257 { 23258 name: "Cvt64Fto32F", 23259 argLen: 1, 23260 generic: true, 23261 }, 23262 { 23263 name: "Round32F", 23264 argLen: 1, 23265 generic: true, 23266 }, 23267 { 23268 name: "Round64F", 23269 argLen: 1, 23270 generic: true, 23271 }, 23272 { 23273 name: "IsNonNil", 23274 argLen: 1, 23275 generic: true, 23276 }, 23277 { 23278 name: "IsInBounds", 23279 argLen: 2, 23280 generic: true, 23281 }, 23282 { 23283 name: "IsSliceInBounds", 23284 argLen: 2, 23285 generic: true, 23286 }, 23287 { 23288 name: "NilCheck", 23289 argLen: 2, 23290 generic: true, 23291 }, 23292 { 23293 name: "GetG", 23294 argLen: 1, 23295 generic: true, 23296 }, 23297 { 23298 name: "GetClosurePtr", 23299 argLen: 0, 23300 generic: true, 23301 }, 23302 { 23303 name: "GetCallerPC", 23304 argLen: 0, 23305 generic: true, 23306 }, 23307 { 23308 name: "GetCallerSP", 23309 argLen: 0, 23310 generic: true, 23311 }, 23312 { 23313 name: "PtrIndex", 23314 argLen: 2, 23315 generic: true, 23316 }, 23317 { 23318 name: "OffPtr", 23319 auxType: auxInt64, 23320 argLen: 1, 23321 generic: true, 23322 }, 23323 { 23324 name: "SliceMake", 23325 argLen: 3, 23326 generic: true, 23327 }, 23328 { 23329 name: "SlicePtr", 23330 argLen: 1, 23331 generic: true, 23332 }, 23333 { 23334 name: "SliceLen", 23335 argLen: 1, 23336 generic: true, 23337 }, 23338 { 23339 name: "SliceCap", 23340 argLen: 1, 23341 generic: true, 23342 }, 23343 { 23344 name: "ComplexMake", 23345 argLen: 2, 23346 generic: true, 23347 }, 23348 { 23349 name: "ComplexReal", 23350 argLen: 1, 23351 generic: true, 23352 }, 23353 { 23354 name: "ComplexImag", 23355 argLen: 1, 23356 generic: true, 23357 }, 23358 { 23359 name: "StringMake", 23360 argLen: 2, 23361 generic: true, 23362 }, 23363 { 23364 name: "StringPtr", 23365 argLen: 1, 23366 generic: true, 23367 }, 23368 { 23369 name: "StringLen", 23370 argLen: 1, 23371 generic: true, 23372 }, 23373 { 23374 name: "IMake", 23375 argLen: 2, 23376 generic: true, 23377 }, 23378 { 23379 name: "ITab", 23380 argLen: 1, 23381 generic: true, 23382 }, 23383 { 23384 name: "IData", 23385 argLen: 1, 23386 generic: true, 23387 }, 23388 { 23389 name: "StructMake0", 23390 argLen: 0, 23391 generic: true, 23392 }, 23393 { 23394 name: "StructMake1", 23395 argLen: 1, 23396 generic: true, 23397 }, 23398 { 23399 name: "StructMake2", 23400 argLen: 2, 23401 generic: true, 23402 }, 23403 { 23404 name: "StructMake3", 23405 argLen: 3, 23406 generic: true, 23407 }, 23408 { 23409 name: "StructMake4", 23410 argLen: 4, 23411 generic: true, 23412 }, 23413 { 23414 name: "StructSelect", 23415 auxType: auxInt64, 23416 argLen: 1, 23417 generic: true, 23418 }, 23419 { 23420 name: "ArrayMake0", 23421 argLen: 0, 23422 generic: true, 23423 }, 23424 { 23425 name: "ArrayMake1", 23426 argLen: 1, 23427 generic: true, 23428 }, 23429 { 23430 name: "ArraySelect", 23431 auxType: auxInt64, 23432 argLen: 1, 23433 generic: true, 23434 }, 23435 { 23436 name: "StoreReg", 23437 argLen: 1, 23438 generic: true, 23439 }, 23440 { 23441 name: "LoadReg", 23442 argLen: 1, 23443 generic: true, 23444 }, 23445 { 23446 name: "FwdRef", 23447 auxType: auxSym, 23448 argLen: 0, 23449 symEffect: SymNone, 23450 generic: true, 23451 }, 23452 { 23453 name: "Unknown", 23454 argLen: 0, 23455 generic: true, 23456 }, 23457 { 23458 name: "VarDef", 23459 auxType: auxSym, 23460 argLen: 1, 23461 symEffect: SymNone, 23462 generic: true, 23463 }, 23464 { 23465 name: "VarKill", 23466 auxType: auxSym, 23467 argLen: 1, 23468 symEffect: SymNone, 23469 generic: true, 23470 }, 23471 { 23472 name: "VarLive", 23473 auxType: auxSym, 23474 argLen: 1, 23475 symEffect: SymRead, 23476 generic: true, 23477 }, 23478 { 23479 name: "KeepAlive", 23480 argLen: 2, 23481 generic: true, 23482 }, 23483 { 23484 name: "RegKill", 23485 argLen: 0, 23486 generic: true, 23487 }, 23488 { 23489 name: "Int64Make", 23490 argLen: 2, 23491 generic: true, 23492 }, 23493 { 23494 name: "Int64Hi", 23495 argLen: 1, 23496 generic: true, 23497 }, 23498 { 23499 name: "Int64Lo", 23500 argLen: 1, 23501 generic: true, 23502 }, 23503 { 23504 name: "Add32carry", 23505 argLen: 2, 23506 commutative: true, 23507 generic: true, 23508 }, 23509 { 23510 name: "Add32withcarry", 23511 argLen: 3, 23512 commutative: true, 23513 generic: true, 23514 }, 23515 { 23516 name: "Sub32carry", 23517 argLen: 2, 23518 generic: true, 23519 }, 23520 { 23521 name: "Sub32withcarry", 23522 argLen: 3, 23523 generic: true, 23524 }, 23525 { 23526 name: "Signmask", 23527 argLen: 1, 23528 generic: true, 23529 }, 23530 { 23531 name: "Zeromask", 23532 argLen: 1, 23533 generic: true, 23534 }, 23535 { 23536 name: "Slicemask", 23537 argLen: 1, 23538 generic: true, 23539 }, 23540 { 23541 name: "Cvt32Uto32F", 23542 argLen: 1, 23543 generic: true, 23544 }, 23545 { 23546 name: "Cvt32Uto64F", 23547 argLen: 1, 23548 generic: true, 23549 }, 23550 { 23551 name: "Cvt32Fto32U", 23552 argLen: 1, 23553 generic: true, 23554 }, 23555 { 23556 name: "Cvt64Fto32U", 23557 argLen: 1, 23558 generic: true, 23559 }, 23560 { 23561 name: "Cvt64Uto32F", 23562 argLen: 1, 23563 generic: true, 23564 }, 23565 { 23566 name: "Cvt64Uto64F", 23567 argLen: 1, 23568 generic: true, 23569 }, 23570 { 23571 name: "Cvt32Fto64U", 23572 argLen: 1, 23573 generic: true, 23574 }, 23575 { 23576 name: "Cvt64Fto64U", 23577 argLen: 1, 23578 generic: true, 23579 }, 23580 { 23581 name: "Select0", 23582 argLen: 1, 23583 generic: true, 23584 }, 23585 { 23586 name: "Select1", 23587 argLen: 1, 23588 generic: true, 23589 }, 23590 { 23591 name: "AtomicLoad32", 23592 argLen: 2, 23593 generic: true, 23594 }, 23595 { 23596 name: "AtomicLoad64", 23597 argLen: 2, 23598 generic: true, 23599 }, 23600 { 23601 name: "AtomicLoadPtr", 23602 argLen: 2, 23603 generic: true, 23604 }, 23605 { 23606 name: "AtomicStore32", 23607 argLen: 3, 23608 hasSideEffects: true, 23609 generic: true, 23610 }, 23611 { 23612 name: "AtomicStore64", 23613 argLen: 3, 23614 hasSideEffects: true, 23615 generic: true, 23616 }, 23617 { 23618 name: "AtomicStorePtrNoWB", 23619 argLen: 3, 23620 hasSideEffects: true, 23621 generic: true, 23622 }, 23623 { 23624 name: "AtomicExchange32", 23625 argLen: 3, 23626 hasSideEffects: true, 23627 generic: true, 23628 }, 23629 { 23630 name: "AtomicExchange64", 23631 argLen: 3, 23632 hasSideEffects: true, 23633 generic: true, 23634 }, 23635 { 23636 name: "AtomicAdd32", 23637 argLen: 3, 23638 hasSideEffects: true, 23639 generic: true, 23640 }, 23641 { 23642 name: "AtomicAdd64", 23643 argLen: 3, 23644 hasSideEffects: true, 23645 generic: true, 23646 }, 23647 { 23648 name: "AtomicCompareAndSwap32", 23649 argLen: 4, 23650 hasSideEffects: true, 23651 generic: true, 23652 }, 23653 { 23654 name: "AtomicCompareAndSwap64", 23655 argLen: 4, 23656 hasSideEffects: true, 23657 generic: true, 23658 }, 23659 { 23660 name: "AtomicAnd8", 23661 argLen: 3, 23662 hasSideEffects: true, 23663 generic: true, 23664 }, 23665 { 23666 name: "AtomicOr8", 23667 argLen: 3, 23668 hasSideEffects: true, 23669 generic: true, 23670 }, 23671 { 23672 name: "Clobber", 23673 auxType: auxSymOff, 23674 argLen: 0, 23675 symEffect: SymNone, 23676 generic: true, 23677 }, 23678 } 23679 23680 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 23681 func (o Op) String() string { return opcodeTable[o].name } 23682 func (o Op) UsesScratch() bool { return opcodeTable[o].usesScratch } 23683 func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect } 23684 func (o Op) IsCall() bool { return opcodeTable[o].call } 23685 23686 var registers386 = [...]Register{ 23687 {0, x86.REG_AX, "AX"}, 23688 {1, x86.REG_CX, "CX"}, 23689 {2, x86.REG_DX, "DX"}, 23690 {3, x86.REG_BX, "BX"}, 23691 {4, x86.REGSP, "SP"}, 23692 {5, x86.REG_BP, "BP"}, 23693 {6, x86.REG_SI, "SI"}, 23694 {7, x86.REG_DI, "DI"}, 23695 {8, x86.REG_X0, "X0"}, 23696 {9, x86.REG_X1, "X1"}, 23697 {10, x86.REG_X2, "X2"}, 23698 {11, x86.REG_X3, "X3"}, 23699 {12, x86.REG_X4, "X4"}, 23700 {13, x86.REG_X5, "X5"}, 23701 {14, x86.REG_X6, "X6"}, 23702 {15, x86.REG_X7, "X7"}, 23703 {16, 0, "SB"}, 23704 } 23705 var gpRegMask386 = regMask(239) 23706 var fpRegMask386 = regMask(65280) 23707 var specialRegMask386 = regMask(0) 23708 var framepointerReg386 = int8(5) 23709 var linkReg386 = int8(-1) 23710 var registersAMD64 = [...]Register{ 23711 {0, x86.REG_AX, "AX"}, 23712 {1, x86.REG_CX, "CX"}, 23713 {2, x86.REG_DX, "DX"}, 23714 {3, x86.REG_BX, "BX"}, 23715 {4, x86.REGSP, "SP"}, 23716 {5, x86.REG_BP, "BP"}, 23717 {6, x86.REG_SI, "SI"}, 23718 {7, x86.REG_DI, "DI"}, 23719 {8, x86.REG_R8, "R8"}, 23720 {9, x86.REG_R9, "R9"}, 23721 {10, x86.REG_R10, "R10"}, 23722 {11, x86.REG_R11, "R11"}, 23723 {12, x86.REG_R12, "R12"}, 23724 {13, x86.REG_R13, "R13"}, 23725 {14, x86.REG_R14, "R14"}, 23726 {15, x86.REG_R15, "R15"}, 23727 {16, x86.REG_X0, "X0"}, 23728 {17, x86.REG_X1, "X1"}, 23729 {18, x86.REG_X2, "X2"}, 23730 {19, x86.REG_X3, "X3"}, 23731 {20, x86.REG_X4, "X4"}, 23732 {21, x86.REG_X5, "X5"}, 23733 {22, x86.REG_X6, "X6"}, 23734 {23, x86.REG_X7, "X7"}, 23735 {24, x86.REG_X8, "X8"}, 23736 {25, x86.REG_X9, "X9"}, 23737 {26, x86.REG_X10, "X10"}, 23738 {27, x86.REG_X11, "X11"}, 23739 {28, x86.REG_X12, "X12"}, 23740 {29, x86.REG_X13, "X13"}, 23741 {30, x86.REG_X14, "X14"}, 23742 {31, x86.REG_X15, "X15"}, 23743 {32, 0, "SB"}, 23744 } 23745 var gpRegMaskAMD64 = regMask(65519) 23746 var fpRegMaskAMD64 = regMask(4294901760) 23747 var specialRegMaskAMD64 = regMask(0) 23748 var framepointerRegAMD64 = int8(5) 23749 var linkRegAMD64 = int8(-1) 23750 var registersARM = [...]Register{ 23751 {0, arm.REG_R0, "R0"}, 23752 {1, arm.REG_R1, "R1"}, 23753 {2, arm.REG_R2, "R2"}, 23754 {3, arm.REG_R3, "R3"}, 23755 {4, arm.REG_R4, "R4"}, 23756 {5, arm.REG_R5, "R5"}, 23757 {6, arm.REG_R6, "R6"}, 23758 {7, arm.REG_R7, "R7"}, 23759 {8, arm.REG_R8, "R8"}, 23760 {9, arm.REG_R9, "R9"}, 23761 {10, arm.REGG, "g"}, 23762 {11, arm.REG_R11, "R11"}, 23763 {12, arm.REG_R12, "R12"}, 23764 {13, arm.REGSP, "SP"}, 23765 {14, arm.REG_R14, "R14"}, 23766 {15, arm.REG_R15, "R15"}, 23767 {16, arm.REG_F0, "F0"}, 23768 {17, arm.REG_F1, "F1"}, 23769 {18, arm.REG_F2, "F2"}, 23770 {19, arm.REG_F3, "F3"}, 23771 {20, arm.REG_F4, "F4"}, 23772 {21, arm.REG_F5, "F5"}, 23773 {22, arm.REG_F6, "F6"}, 23774 {23, arm.REG_F7, "F7"}, 23775 {24, arm.REG_F8, "F8"}, 23776 {25, arm.REG_F9, "F9"}, 23777 {26, arm.REG_F10, "F10"}, 23778 {27, arm.REG_F11, "F11"}, 23779 {28, arm.REG_F12, "F12"}, 23780 {29, arm.REG_F13, "F13"}, 23781 {30, arm.REG_F14, "F14"}, 23782 {31, arm.REG_F15, "F15"}, 23783 {32, 0, "SB"}, 23784 } 23785 var gpRegMaskARM = regMask(21503) 23786 var fpRegMaskARM = regMask(4294901760) 23787 var specialRegMaskARM = regMask(0) 23788 var framepointerRegARM = int8(-1) 23789 var linkRegARM = int8(14) 23790 var registersARM64 = [...]Register{ 23791 {0, arm64.REG_R0, "R0"}, 23792 {1, arm64.REG_R1, "R1"}, 23793 {2, arm64.REG_R2, "R2"}, 23794 {3, arm64.REG_R3, "R3"}, 23795 {4, arm64.REG_R4, "R4"}, 23796 {5, arm64.REG_R5, "R5"}, 23797 {6, arm64.REG_R6, "R6"}, 23798 {7, arm64.REG_R7, "R7"}, 23799 {8, arm64.REG_R8, "R8"}, 23800 {9, arm64.REG_R9, "R9"}, 23801 {10, arm64.REG_R10, "R10"}, 23802 {11, arm64.REG_R11, "R11"}, 23803 {12, arm64.REG_R12, "R12"}, 23804 {13, arm64.REG_R13, "R13"}, 23805 {14, arm64.REG_R14, "R14"}, 23806 {15, arm64.REG_R15, "R15"}, 23807 {16, arm64.REG_R16, "R16"}, 23808 {17, arm64.REG_R17, "R17"}, 23809 {18, arm64.REG_R18, "R18"}, 23810 {19, arm64.REG_R19, "R19"}, 23811 {20, arm64.REG_R20, "R20"}, 23812 {21, arm64.REG_R21, "R21"}, 23813 {22, arm64.REG_R22, "R22"}, 23814 {23, arm64.REG_R23, "R23"}, 23815 {24, arm64.REG_R24, "R24"}, 23816 {25, arm64.REG_R25, "R25"}, 23817 {26, arm64.REG_R26, "R26"}, 23818 {27, arm64.REGG, "g"}, 23819 {28, arm64.REG_R29, "R29"}, 23820 {29, arm64.REG_R30, "R30"}, 23821 {30, arm64.REGSP, "SP"}, 23822 {31, arm64.REG_F0, "F0"}, 23823 {32, arm64.REG_F1, "F1"}, 23824 {33, arm64.REG_F2, "F2"}, 23825 {34, arm64.REG_F3, "F3"}, 23826 {35, arm64.REG_F4, "F4"}, 23827 {36, arm64.REG_F5, "F5"}, 23828 {37, arm64.REG_F6, "F6"}, 23829 {38, arm64.REG_F7, "F7"}, 23830 {39, arm64.REG_F8, "F8"}, 23831 {40, arm64.REG_F9, "F9"}, 23832 {41, arm64.REG_F10, "F10"}, 23833 {42, arm64.REG_F11, "F11"}, 23834 {43, arm64.REG_F12, "F12"}, 23835 {44, arm64.REG_F13, "F13"}, 23836 {45, arm64.REG_F14, "F14"}, 23837 {46, arm64.REG_F15, "F15"}, 23838 {47, arm64.REG_F16, "F16"}, 23839 {48, arm64.REG_F17, "F17"}, 23840 {49, arm64.REG_F18, "F18"}, 23841 {50, arm64.REG_F19, "F19"}, 23842 {51, arm64.REG_F20, "F20"}, 23843 {52, arm64.REG_F21, "F21"}, 23844 {53, arm64.REG_F22, "F22"}, 23845 {54, arm64.REG_F23, "F23"}, 23846 {55, arm64.REG_F24, "F24"}, 23847 {56, arm64.REG_F25, "F25"}, 23848 {57, arm64.REG_F26, "F26"}, 23849 {58, arm64.REG_F27, "F27"}, 23850 {59, arm64.REG_F28, "F28"}, 23851 {60, arm64.REG_F29, "F29"}, 23852 {61, arm64.REG_F30, "F30"}, 23853 {62, arm64.REG_F31, "F31"}, 23854 {63, 0, "SB"}, 23855 } 23856 var gpRegMaskARM64 = regMask(670826495) 23857 var fpRegMaskARM64 = regMask(9223372034707292160) 23858 var specialRegMaskARM64 = regMask(0) 23859 var framepointerRegARM64 = int8(-1) 23860 var linkRegARM64 = int8(29) 23861 var registersMIPS = [...]Register{ 23862 {0, mips.REG_R0, "R0"}, 23863 {1, mips.REG_R1, "R1"}, 23864 {2, mips.REG_R2, "R2"}, 23865 {3, mips.REG_R3, "R3"}, 23866 {4, mips.REG_R4, "R4"}, 23867 {5, mips.REG_R5, "R5"}, 23868 {6, mips.REG_R6, "R6"}, 23869 {7, mips.REG_R7, "R7"}, 23870 {8, mips.REG_R8, "R8"}, 23871 {9, mips.REG_R9, "R9"}, 23872 {10, mips.REG_R10, "R10"}, 23873 {11, mips.REG_R11, "R11"}, 23874 {12, mips.REG_R12, "R12"}, 23875 {13, mips.REG_R13, "R13"}, 23876 {14, mips.REG_R14, "R14"}, 23877 {15, mips.REG_R15, "R15"}, 23878 {16, mips.REG_R16, "R16"}, 23879 {17, mips.REG_R17, "R17"}, 23880 {18, mips.REG_R18, "R18"}, 23881 {19, mips.REG_R19, "R19"}, 23882 {20, mips.REG_R20, "R20"}, 23883 {21, mips.REG_R21, "R21"}, 23884 {22, mips.REG_R22, "R22"}, 23885 {23, mips.REG_R24, "R24"}, 23886 {24, mips.REG_R25, "R25"}, 23887 {25, mips.REG_R28, "R28"}, 23888 {26, mips.REGSP, "SP"}, 23889 {27, mips.REGG, "g"}, 23890 {28, mips.REG_R31, "R31"}, 23891 {29, mips.REG_F0, "F0"}, 23892 {30, mips.REG_F2, "F2"}, 23893 {31, mips.REG_F4, "F4"}, 23894 {32, mips.REG_F6, "F6"}, 23895 {33, mips.REG_F8, "F8"}, 23896 {34, mips.REG_F10, "F10"}, 23897 {35, mips.REG_F12, "F12"}, 23898 {36, mips.REG_F14, "F14"}, 23899 {37, mips.REG_F16, "F16"}, 23900 {38, mips.REG_F18, "F18"}, 23901 {39, mips.REG_F20, "F20"}, 23902 {40, mips.REG_F22, "F22"}, 23903 {41, mips.REG_F24, "F24"}, 23904 {42, mips.REG_F26, "F26"}, 23905 {43, mips.REG_F28, "F28"}, 23906 {44, mips.REG_F30, "F30"}, 23907 {45, mips.REG_HI, "HI"}, 23908 {46, mips.REG_LO, "LO"}, 23909 {47, 0, "SB"}, 23910 } 23911 var gpRegMaskMIPS = regMask(335544318) 23912 var fpRegMaskMIPS = regMask(35183835217920) 23913 var specialRegMaskMIPS = regMask(105553116266496) 23914 var framepointerRegMIPS = int8(-1) 23915 var linkRegMIPS = int8(28) 23916 var registersMIPS64 = [...]Register{ 23917 {0, mips.REG_R0, "R0"}, 23918 {1, mips.REG_R1, "R1"}, 23919 {2, mips.REG_R2, "R2"}, 23920 {3, mips.REG_R3, "R3"}, 23921 {4, mips.REG_R4, "R4"}, 23922 {5, mips.REG_R5, "R5"}, 23923 {6, mips.REG_R6, "R6"}, 23924 {7, mips.REG_R7, "R7"}, 23925 {8, mips.REG_R8, "R8"}, 23926 {9, mips.REG_R9, "R9"}, 23927 {10, mips.REG_R10, "R10"}, 23928 {11, mips.REG_R11, "R11"}, 23929 {12, mips.REG_R12, "R12"}, 23930 {13, mips.REG_R13, "R13"}, 23931 {14, mips.REG_R14, "R14"}, 23932 {15, mips.REG_R15, "R15"}, 23933 {16, mips.REG_R16, "R16"}, 23934 {17, mips.REG_R17, "R17"}, 23935 {18, mips.REG_R18, "R18"}, 23936 {19, mips.REG_R19, "R19"}, 23937 {20, mips.REG_R20, "R20"}, 23938 {21, mips.REG_R21, "R21"}, 23939 {22, mips.REG_R22, "R22"}, 23940 {23, mips.REG_R24, "R24"}, 23941 {24, mips.REG_R25, "R25"}, 23942 {25, mips.REGSP, "SP"}, 23943 {26, mips.REGG, "g"}, 23944 {27, mips.REG_R31, "R31"}, 23945 {28, mips.REG_F0, "F0"}, 23946 {29, mips.REG_F1, "F1"}, 23947 {30, mips.REG_F2, "F2"}, 23948 {31, mips.REG_F3, "F3"}, 23949 {32, mips.REG_F4, "F4"}, 23950 {33, mips.REG_F5, "F5"}, 23951 {34, mips.REG_F6, "F6"}, 23952 {35, mips.REG_F7, "F7"}, 23953 {36, mips.REG_F8, "F8"}, 23954 {37, mips.REG_F9, "F9"}, 23955 {38, mips.REG_F10, "F10"}, 23956 {39, mips.REG_F11, "F11"}, 23957 {40, mips.REG_F12, "F12"}, 23958 {41, mips.REG_F13, "F13"}, 23959 {42, mips.REG_F14, "F14"}, 23960 {43, mips.REG_F15, "F15"}, 23961 {44, mips.REG_F16, "F16"}, 23962 {45, mips.REG_F17, "F17"}, 23963 {46, mips.REG_F18, "F18"}, 23964 {47, mips.REG_F19, "F19"}, 23965 {48, mips.REG_F20, "F20"}, 23966 {49, mips.REG_F21, "F21"}, 23967 {50, mips.REG_F22, "F22"}, 23968 {51, mips.REG_F23, "F23"}, 23969 {52, mips.REG_F24, "F24"}, 23970 {53, mips.REG_F25, "F25"}, 23971 {54, mips.REG_F26, "F26"}, 23972 {55, mips.REG_F27, "F27"}, 23973 {56, mips.REG_F28, "F28"}, 23974 {57, mips.REG_F29, "F29"}, 23975 {58, mips.REG_F30, "F30"}, 23976 {59, mips.REG_F31, "F31"}, 23977 {60, mips.REG_HI, "HI"}, 23978 {61, mips.REG_LO, "LO"}, 23979 {62, 0, "SB"}, 23980 } 23981 var gpRegMaskMIPS64 = regMask(167772158) 23982 var fpRegMaskMIPS64 = regMask(1152921504338411520) 23983 var specialRegMaskMIPS64 = regMask(3458764513820540928) 23984 var framepointerRegMIPS64 = int8(-1) 23985 var linkRegMIPS64 = int8(27) 23986 var registersPPC64 = [...]Register{ 23987 {0, ppc64.REG_R0, "R0"}, 23988 {1, ppc64.REGSP, "SP"}, 23989 {2, 0, "SB"}, 23990 {3, ppc64.REG_R3, "R3"}, 23991 {4, ppc64.REG_R4, "R4"}, 23992 {5, ppc64.REG_R5, "R5"}, 23993 {6, ppc64.REG_R6, "R6"}, 23994 {7, ppc64.REG_R7, "R7"}, 23995 {8, ppc64.REG_R8, "R8"}, 23996 {9, ppc64.REG_R9, "R9"}, 23997 {10, ppc64.REG_R10, "R10"}, 23998 {11, ppc64.REG_R11, "R11"}, 23999 {12, ppc64.REG_R12, "R12"}, 24000 {13, ppc64.REG_R13, "R13"}, 24001 {14, ppc64.REG_R14, "R14"}, 24002 {15, ppc64.REG_R15, "R15"}, 24003 {16, ppc64.REG_R16, "R16"}, 24004 {17, ppc64.REG_R17, "R17"}, 24005 {18, ppc64.REG_R18, "R18"}, 24006 {19, ppc64.REG_R19, "R19"}, 24007 {20, ppc64.REG_R20, "R20"}, 24008 {21, ppc64.REG_R21, "R21"}, 24009 {22, ppc64.REG_R22, "R22"}, 24010 {23, ppc64.REG_R23, "R23"}, 24011 {24, ppc64.REG_R24, "R24"}, 24012 {25, ppc64.REG_R25, "R25"}, 24013 {26, ppc64.REG_R26, "R26"}, 24014 {27, ppc64.REG_R27, "R27"}, 24015 {28, ppc64.REG_R28, "R28"}, 24016 {29, ppc64.REG_R29, "R29"}, 24017 {30, ppc64.REGG, "g"}, 24018 {31, ppc64.REG_R31, "R31"}, 24019 {32, ppc64.REG_F0, "F0"}, 24020 {33, ppc64.REG_F1, "F1"}, 24021 {34, ppc64.REG_F2, "F2"}, 24022 {35, ppc64.REG_F3, "F3"}, 24023 {36, ppc64.REG_F4, "F4"}, 24024 {37, ppc64.REG_F5, "F5"}, 24025 {38, ppc64.REG_F6, "F6"}, 24026 {39, ppc64.REG_F7, "F7"}, 24027 {40, ppc64.REG_F8, "F8"}, 24028 {41, ppc64.REG_F9, "F9"}, 24029 {42, ppc64.REG_F10, "F10"}, 24030 {43, ppc64.REG_F11, "F11"}, 24031 {44, ppc64.REG_F12, "F12"}, 24032 {45, ppc64.REG_F13, "F13"}, 24033 {46, ppc64.REG_F14, "F14"}, 24034 {47, ppc64.REG_F15, "F15"}, 24035 {48, ppc64.REG_F16, "F16"}, 24036 {49, ppc64.REG_F17, "F17"}, 24037 {50, ppc64.REG_F18, "F18"}, 24038 {51, ppc64.REG_F19, "F19"}, 24039 {52, ppc64.REG_F20, "F20"}, 24040 {53, ppc64.REG_F21, "F21"}, 24041 {54, ppc64.REG_F22, "F22"}, 24042 {55, ppc64.REG_F23, "F23"}, 24043 {56, ppc64.REG_F24, "F24"}, 24044 {57, ppc64.REG_F25, "F25"}, 24045 {58, ppc64.REG_F26, "F26"}, 24046 {59, ppc64.REG_F27, "F27"}, 24047 {60, ppc64.REG_F28, "F28"}, 24048 {61, ppc64.REG_F29, "F29"}, 24049 {62, ppc64.REG_F30, "F30"}, 24050 {63, ppc64.REG_F31, "F31"}, 24051 } 24052 var gpRegMaskPPC64 = regMask(1073733624) 24053 var fpRegMaskPPC64 = regMask(576460743713488896) 24054 var specialRegMaskPPC64 = regMask(0) 24055 var framepointerRegPPC64 = int8(1) 24056 var linkRegPPC64 = int8(-1) 24057 var registersS390X = [...]Register{ 24058 {0, s390x.REG_R0, "R0"}, 24059 {1, s390x.REG_R1, "R1"}, 24060 {2, s390x.REG_R2, "R2"}, 24061 {3, s390x.REG_R3, "R3"}, 24062 {4, s390x.REG_R4, "R4"}, 24063 {5, s390x.REG_R5, "R5"}, 24064 {6, s390x.REG_R6, "R6"}, 24065 {7, s390x.REG_R7, "R7"}, 24066 {8, s390x.REG_R8, "R8"}, 24067 {9, s390x.REG_R9, "R9"}, 24068 {10, s390x.REG_R10, "R10"}, 24069 {11, s390x.REG_R11, "R11"}, 24070 {12, s390x.REG_R12, "R12"}, 24071 {13, s390x.REGG, "g"}, 24072 {14, s390x.REG_R14, "R14"}, 24073 {15, s390x.REGSP, "SP"}, 24074 {16, s390x.REG_F0, "F0"}, 24075 {17, s390x.REG_F1, "F1"}, 24076 {18, s390x.REG_F2, "F2"}, 24077 {19, s390x.REG_F3, "F3"}, 24078 {20, s390x.REG_F4, "F4"}, 24079 {21, s390x.REG_F5, "F5"}, 24080 {22, s390x.REG_F6, "F6"}, 24081 {23, s390x.REG_F7, "F7"}, 24082 {24, s390x.REG_F8, "F8"}, 24083 {25, s390x.REG_F9, "F9"}, 24084 {26, s390x.REG_F10, "F10"}, 24085 {27, s390x.REG_F11, "F11"}, 24086 {28, s390x.REG_F12, "F12"}, 24087 {29, s390x.REG_F13, "F13"}, 24088 {30, s390x.REG_F14, "F14"}, 24089 {31, s390x.REG_F15, "F15"}, 24090 {32, 0, "SB"}, 24091 } 24092 var gpRegMaskS390X = regMask(21503) 24093 var fpRegMaskS390X = regMask(4294901760) 24094 var specialRegMaskS390X = regMask(0) 24095 var framepointerRegS390X = int8(-1) 24096 var linkRegS390X = int8(14)