github.com/mdaxf/iac@v0.0.0-20240519030858-58a061660378/vendor_skip/golang.org/x/sys/cpu/cpu.go (about) 1 // Copyright 2018 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 // Package cpu implements processor feature detection for 6 // various CPU architectures. 7 package cpu 8 9 import ( 10 "os" 11 "strings" 12 ) 13 14 // Initialized reports whether the CPU features were initialized. 15 // 16 // For some GOOS/GOARCH combinations initialization of the CPU features depends 17 // on reading an operating specific file, e.g. /proc/self/auxv on linux/arm 18 // Initialized will report false if reading the file fails. 19 var Initialized bool 20 21 // CacheLinePad is used to pad structs to avoid false sharing. 22 type CacheLinePad struct{ _ [cacheLineSize]byte } 23 24 // X86 contains the supported CPU features of the 25 // current X86/AMD64 platform. If the current platform 26 // is not X86/AMD64 then all feature flags are false. 27 // 28 // X86 is padded to avoid false sharing. Further the HasAVX 29 // and HasAVX2 are only set if the OS supports XMM and YMM 30 // registers in addition to the CPUID feature bit being set. 31 var X86 struct { 32 _ CacheLinePad 33 HasAES bool // AES hardware implementation (AES NI) 34 HasADX bool // Multi-precision add-carry instruction extensions 35 HasAVX bool // Advanced vector extension 36 HasAVX2 bool // Advanced vector extension 2 37 HasAVX512 bool // Advanced vector extension 512 38 HasAVX512F bool // Advanced vector extension 512 Foundation Instructions 39 HasAVX512CD bool // Advanced vector extension 512 Conflict Detection Instructions 40 HasAVX512ER bool // Advanced vector extension 512 Exponential and Reciprocal Instructions 41 HasAVX512PF bool // Advanced vector extension 512 Prefetch Instructions 42 HasAVX512VL bool // Advanced vector extension 512 Vector Length Extensions 43 HasAVX512BW bool // Advanced vector extension 512 Byte and Word Instructions 44 HasAVX512DQ bool // Advanced vector extension 512 Doubleword and Quadword Instructions 45 HasAVX512IFMA bool // Advanced vector extension 512 Integer Fused Multiply Add 46 HasAVX512VBMI bool // Advanced vector extension 512 Vector Byte Manipulation Instructions 47 HasAVX5124VNNIW bool // Advanced vector extension 512 Vector Neural Network Instructions Word variable precision 48 HasAVX5124FMAPS bool // Advanced vector extension 512 Fused Multiply Accumulation Packed Single precision 49 HasAVX512VPOPCNTDQ bool // Advanced vector extension 512 Double and quad word population count instructions 50 HasAVX512VPCLMULQDQ bool // Advanced vector extension 512 Vector carry-less multiply operations 51 HasAVX512VNNI bool // Advanced vector extension 512 Vector Neural Network Instructions 52 HasAVX512GFNI bool // Advanced vector extension 512 Galois field New Instructions 53 HasAVX512VAES bool // Advanced vector extension 512 Vector AES instructions 54 HasAVX512VBMI2 bool // Advanced vector extension 512 Vector Byte Manipulation Instructions 2 55 HasAVX512BITALG bool // Advanced vector extension 512 Bit Algorithms 56 HasAVX512BF16 bool // Advanced vector extension 512 BFloat16 Instructions 57 HasAMXTile bool // Advanced Matrix Extension Tile instructions 58 HasAMXInt8 bool // Advanced Matrix Extension Int8 instructions 59 HasAMXBF16 bool // Advanced Matrix Extension BFloat16 instructions 60 HasBMI1 bool // Bit manipulation instruction set 1 61 HasBMI2 bool // Bit manipulation instruction set 2 62 HasCX16 bool // Compare and exchange 16 Bytes 63 HasERMS bool // Enhanced REP for MOVSB and STOSB 64 HasFMA bool // Fused-multiply-add instructions 65 HasOSXSAVE bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers. 66 HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM 67 HasPOPCNT bool // Hamming weight instruction POPCNT. 68 HasRDRAND bool // RDRAND instruction (on-chip random number generator) 69 HasRDSEED bool // RDSEED instruction (on-chip random number generator) 70 HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64) 71 HasSSE3 bool // Streaming SIMD extension 3 72 HasSSSE3 bool // Supplemental streaming SIMD extension 3 73 HasSSE41 bool // Streaming SIMD extension 4 and 4.1 74 HasSSE42 bool // Streaming SIMD extension 4 and 4.2 75 _ CacheLinePad 76 } 77 78 // ARM64 contains the supported CPU features of the 79 // current ARMv8(aarch64) platform. If the current platform 80 // is not arm64 then all feature flags are false. 81 var ARM64 struct { 82 _ CacheLinePad 83 HasFP bool // Floating-point instruction set (always available) 84 HasASIMD bool // Advanced SIMD (always available) 85 HasEVTSTRM bool // Event stream support 86 HasAES bool // AES hardware implementation 87 HasPMULL bool // Polynomial multiplication instruction set 88 HasSHA1 bool // SHA1 hardware implementation 89 HasSHA2 bool // SHA2 hardware implementation 90 HasCRC32 bool // CRC32 hardware implementation 91 HasATOMICS bool // Atomic memory operation instruction set 92 HasFPHP bool // Half precision floating-point instruction set 93 HasASIMDHP bool // Advanced SIMD half precision instruction set 94 HasCPUID bool // CPUID identification scheme registers 95 HasASIMDRDM bool // Rounding double multiply add/subtract instruction set 96 HasJSCVT bool // Javascript conversion from floating-point to integer 97 HasFCMA bool // Floating-point multiplication and addition of complex numbers 98 HasLRCPC bool // Release Consistent processor consistent support 99 HasDCPOP bool // Persistent memory support 100 HasSHA3 bool // SHA3 hardware implementation 101 HasSM3 bool // SM3 hardware implementation 102 HasSM4 bool // SM4 hardware implementation 103 HasASIMDDP bool // Advanced SIMD double precision instruction set 104 HasSHA512 bool // SHA512 hardware implementation 105 HasSVE bool // Scalable Vector Extensions 106 HasASIMDFHM bool // Advanced SIMD multiplication FP16 to FP32 107 _ CacheLinePad 108 } 109 110 // ARM contains the supported CPU features of the current ARM (32-bit) platform. 111 // All feature flags are false if: 112 // 1. the current platform is not arm, or 113 // 2. the current operating system is not Linux. 114 var ARM struct { 115 _ CacheLinePad 116 HasSWP bool // SWP instruction support 117 HasHALF bool // Half-word load and store support 118 HasTHUMB bool // ARM Thumb instruction set 119 Has26BIT bool // Address space limited to 26-bits 120 HasFASTMUL bool // 32-bit operand, 64-bit result multiplication support 121 HasFPA bool // Floating point arithmetic support 122 HasVFP bool // Vector floating point support 123 HasEDSP bool // DSP Extensions support 124 HasJAVA bool // Java instruction set 125 HasIWMMXT bool // Intel Wireless MMX technology support 126 HasCRUNCH bool // MaverickCrunch context switching and handling 127 HasTHUMBEE bool // Thumb EE instruction set 128 HasNEON bool // NEON instruction set 129 HasVFPv3 bool // Vector floating point version 3 support 130 HasVFPv3D16 bool // Vector floating point version 3 D8-D15 131 HasTLS bool // Thread local storage support 132 HasVFPv4 bool // Vector floating point version 4 support 133 HasIDIVA bool // Integer divide instruction support in ARM mode 134 HasIDIVT bool // Integer divide instruction support in Thumb mode 135 HasVFPD32 bool // Vector floating point version 3 D15-D31 136 HasLPAE bool // Large Physical Address Extensions 137 HasEVTSTRM bool // Event stream support 138 HasAES bool // AES hardware implementation 139 HasPMULL bool // Polynomial multiplication instruction set 140 HasSHA1 bool // SHA1 hardware implementation 141 HasSHA2 bool // SHA2 hardware implementation 142 HasCRC32 bool // CRC32 hardware implementation 143 _ CacheLinePad 144 } 145 146 // MIPS64X contains the supported CPU features of the current mips64/mips64le 147 // platforms. If the current platform is not mips64/mips64le or the current 148 // operating system is not Linux then all feature flags are false. 149 var MIPS64X struct { 150 _ CacheLinePad 151 HasMSA bool // MIPS SIMD architecture 152 _ CacheLinePad 153 } 154 155 // PPC64 contains the supported CPU features of the current ppc64/ppc64le platforms. 156 // If the current platform is not ppc64/ppc64le then all feature flags are false. 157 // 158 // For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00, 159 // since there are no optional categories. There are some exceptions that also 160 // require kernel support to work (DARN, SCV), so there are feature bits for 161 // those as well. The struct is padded to avoid false sharing. 162 var PPC64 struct { 163 _ CacheLinePad 164 HasDARN bool // Hardware random number generator (requires kernel enablement) 165 HasSCV bool // Syscall vectored (requires kernel enablement) 166 IsPOWER8 bool // ISA v2.07 (POWER8) 167 IsPOWER9 bool // ISA v3.00 (POWER9), implies IsPOWER8 168 _ CacheLinePad 169 } 170 171 // S390X contains the supported CPU features of the current IBM Z 172 // (s390x) platform. If the current platform is not IBM Z then all 173 // feature flags are false. 174 // 175 // S390X is padded to avoid false sharing. Further HasVX is only set 176 // if the OS supports vector registers in addition to the STFLE 177 // feature bit being set. 178 var S390X struct { 179 _ CacheLinePad 180 HasZARCH bool // z/Architecture mode is active [mandatory] 181 HasSTFLE bool // store facility list extended 182 HasLDISP bool // long (20-bit) displacements 183 HasEIMM bool // 32-bit immediates 184 HasDFP bool // decimal floating point 185 HasETF3EH bool // ETF-3 enhanced 186 HasMSA bool // message security assist (CPACF) 187 HasAES bool // KM-AES{128,192,256} functions 188 HasAESCBC bool // KMC-AES{128,192,256} functions 189 HasAESCTR bool // KMCTR-AES{128,192,256} functions 190 HasAESGCM bool // KMA-GCM-AES{128,192,256} functions 191 HasGHASH bool // KIMD-GHASH function 192 HasSHA1 bool // K{I,L}MD-SHA-1 functions 193 HasSHA256 bool // K{I,L}MD-SHA-256 functions 194 HasSHA512 bool // K{I,L}MD-SHA-512 functions 195 HasSHA3 bool // K{I,L}MD-SHA3-{224,256,384,512} and K{I,L}MD-SHAKE-{128,256} functions 196 HasVX bool // vector facility 197 HasVXE bool // vector-enhancements facility 1 198 _ CacheLinePad 199 } 200 201 func init() { 202 archInit() 203 initOptions() 204 processOptions() 205 } 206 207 // options contains the cpu debug options that can be used in GODEBUG. 208 // Options are arch dependent and are added by the arch specific initOptions functions. 209 // Features that are mandatory for the specific GOARCH should have the Required field set 210 // (e.g. SSE2 on amd64). 211 var options []option 212 213 // Option names should be lower case. e.g. avx instead of AVX. 214 type option struct { 215 Name string 216 Feature *bool 217 Specified bool // whether feature value was specified in GODEBUG 218 Enable bool // whether feature should be enabled 219 Required bool // whether feature is mandatory and can not be disabled 220 } 221 222 func processOptions() { 223 env := os.Getenv("GODEBUG") 224 field: 225 for env != "" { 226 field := "" 227 i := strings.IndexByte(env, ',') 228 if i < 0 { 229 field, env = env, "" 230 } else { 231 field, env = env[:i], env[i+1:] 232 } 233 if len(field) < 4 || field[:4] != "cpu." { 234 continue 235 } 236 i = strings.IndexByte(field, '=') 237 if i < 0 { 238 print("GODEBUG sys/cpu: no value specified for \"", field, "\"\n") 239 continue 240 } 241 key, value := field[4:i], field[i+1:] // e.g. "SSE2", "on" 242 243 var enable bool 244 switch value { 245 case "on": 246 enable = true 247 case "off": 248 enable = false 249 default: 250 print("GODEBUG sys/cpu: value \"", value, "\" not supported for cpu option \"", key, "\"\n") 251 continue field 252 } 253 254 if key == "all" { 255 for i := range options { 256 options[i].Specified = true 257 options[i].Enable = enable || options[i].Required 258 } 259 continue field 260 } 261 262 for i := range options { 263 if options[i].Name == key { 264 options[i].Specified = true 265 options[i].Enable = enable 266 continue field 267 } 268 } 269 270 print("GODEBUG sys/cpu: unknown cpu feature \"", key, "\"\n") 271 } 272 273 for _, o := range options { 274 if !o.Specified { 275 continue 276 } 277 278 if o.Enable && !*o.Feature { 279 print("GODEBUG sys/cpu: can not enable \"", o.Name, "\", missing CPU support\n") 280 continue 281 } 282 283 if !o.Enable && o.Required { 284 print("GODEBUG sys/cpu: can not disable \"", o.Name, "\", required CPU feature\n") 285 continue 286 } 287 288 *o.Feature = o.Enable 289 } 290 }