github.com/megatontech/mynoteforgo@v0.0.0-20200507084910-5d0c6ea6e890/源码/cmd/compile/internal/ssa/opGen.go (about) 1 // Code generated from gen/*Ops.go; DO NOT EDIT. 2 3 package ssa 4 5 import ( 6 "cmd/internal/obj" 7 "cmd/internal/obj/arm" 8 "cmd/internal/obj/arm64" 9 "cmd/internal/obj/mips" 10 "cmd/internal/obj/ppc64" 11 "cmd/internal/obj/s390x" 12 "cmd/internal/obj/wasm" 13 "cmd/internal/obj/x86" 14 ) 15 16 const ( 17 BlockInvalid BlockKind = iota 18 19 Block386EQ 20 Block386NE 21 Block386LT 22 Block386LE 23 Block386GT 24 Block386GE 25 Block386OS 26 Block386OC 27 Block386ULT 28 Block386ULE 29 Block386UGT 30 Block386UGE 31 Block386EQF 32 Block386NEF 33 Block386ORD 34 Block386NAN 35 36 BlockAMD64EQ 37 BlockAMD64NE 38 BlockAMD64LT 39 BlockAMD64LE 40 BlockAMD64GT 41 BlockAMD64GE 42 BlockAMD64OS 43 BlockAMD64OC 44 BlockAMD64ULT 45 BlockAMD64ULE 46 BlockAMD64UGT 47 BlockAMD64UGE 48 BlockAMD64EQF 49 BlockAMD64NEF 50 BlockAMD64ORD 51 BlockAMD64NAN 52 53 BlockARMEQ 54 BlockARMNE 55 BlockARMLT 56 BlockARMLE 57 BlockARMGT 58 BlockARMGE 59 BlockARMULT 60 BlockARMULE 61 BlockARMUGT 62 BlockARMUGE 63 64 BlockARM64EQ 65 BlockARM64NE 66 BlockARM64LT 67 BlockARM64LE 68 BlockARM64GT 69 BlockARM64GE 70 BlockARM64ULT 71 BlockARM64ULE 72 BlockARM64UGT 73 BlockARM64UGE 74 BlockARM64Z 75 BlockARM64NZ 76 BlockARM64ZW 77 BlockARM64NZW 78 BlockARM64TBZ 79 BlockARM64TBNZ 80 81 BlockMIPSEQ 82 BlockMIPSNE 83 BlockMIPSLTZ 84 BlockMIPSLEZ 85 BlockMIPSGTZ 86 BlockMIPSGEZ 87 BlockMIPSFPT 88 BlockMIPSFPF 89 90 BlockMIPS64EQ 91 BlockMIPS64NE 92 BlockMIPS64LTZ 93 BlockMIPS64LEZ 94 BlockMIPS64GTZ 95 BlockMIPS64GEZ 96 BlockMIPS64FPT 97 BlockMIPS64FPF 98 99 BlockPPC64EQ 100 BlockPPC64NE 101 BlockPPC64LT 102 BlockPPC64LE 103 BlockPPC64GT 104 BlockPPC64GE 105 BlockPPC64FLT 106 BlockPPC64FLE 107 BlockPPC64FGT 108 BlockPPC64FGE 109 110 BlockS390XEQ 111 BlockS390XNE 112 BlockS390XLT 113 BlockS390XLE 114 BlockS390XGT 115 BlockS390XGE 116 BlockS390XGTF 117 BlockS390XGEF 118 119 BlockPlain 120 BlockIf 121 BlockDefer 122 BlockRet 123 BlockRetJmp 124 BlockExit 125 BlockFirst 126 ) 127 128 var blockString = [...]string{ 129 BlockInvalid: "BlockInvalid", 130 131 Block386EQ: "EQ", 132 Block386NE: "NE", 133 Block386LT: "LT", 134 Block386LE: "LE", 135 Block386GT: "GT", 136 Block386GE: "GE", 137 Block386OS: "OS", 138 Block386OC: "OC", 139 Block386ULT: "ULT", 140 Block386ULE: "ULE", 141 Block386UGT: "UGT", 142 Block386UGE: "UGE", 143 Block386EQF: "EQF", 144 Block386NEF: "NEF", 145 Block386ORD: "ORD", 146 Block386NAN: "NAN", 147 148 BlockAMD64EQ: "EQ", 149 BlockAMD64NE: "NE", 150 BlockAMD64LT: "LT", 151 BlockAMD64LE: "LE", 152 BlockAMD64GT: "GT", 153 BlockAMD64GE: "GE", 154 BlockAMD64OS: "OS", 155 BlockAMD64OC: "OC", 156 BlockAMD64ULT: "ULT", 157 BlockAMD64ULE: "ULE", 158 BlockAMD64UGT: "UGT", 159 BlockAMD64UGE: "UGE", 160 BlockAMD64EQF: "EQF", 161 BlockAMD64NEF: "NEF", 162 BlockAMD64ORD: "ORD", 163 BlockAMD64NAN: "NAN", 164 165 BlockARMEQ: "EQ", 166 BlockARMNE: "NE", 167 BlockARMLT: "LT", 168 BlockARMLE: "LE", 169 BlockARMGT: "GT", 170 BlockARMGE: "GE", 171 BlockARMULT: "ULT", 172 BlockARMULE: "ULE", 173 BlockARMUGT: "UGT", 174 BlockARMUGE: "UGE", 175 176 BlockARM64EQ: "EQ", 177 BlockARM64NE: "NE", 178 BlockARM64LT: "LT", 179 BlockARM64LE: "LE", 180 BlockARM64GT: "GT", 181 BlockARM64GE: "GE", 182 BlockARM64ULT: "ULT", 183 BlockARM64ULE: "ULE", 184 BlockARM64UGT: "UGT", 185 BlockARM64UGE: "UGE", 186 BlockARM64Z: "Z", 187 BlockARM64NZ: "NZ", 188 BlockARM64ZW: "ZW", 189 BlockARM64NZW: "NZW", 190 BlockARM64TBZ: "TBZ", 191 BlockARM64TBNZ: "TBNZ", 192 193 BlockMIPSEQ: "EQ", 194 BlockMIPSNE: "NE", 195 BlockMIPSLTZ: "LTZ", 196 BlockMIPSLEZ: "LEZ", 197 BlockMIPSGTZ: "GTZ", 198 BlockMIPSGEZ: "GEZ", 199 BlockMIPSFPT: "FPT", 200 BlockMIPSFPF: "FPF", 201 202 BlockMIPS64EQ: "EQ", 203 BlockMIPS64NE: "NE", 204 BlockMIPS64LTZ: "LTZ", 205 BlockMIPS64LEZ: "LEZ", 206 BlockMIPS64GTZ: "GTZ", 207 BlockMIPS64GEZ: "GEZ", 208 BlockMIPS64FPT: "FPT", 209 BlockMIPS64FPF: "FPF", 210 211 BlockPPC64EQ: "EQ", 212 BlockPPC64NE: "NE", 213 BlockPPC64LT: "LT", 214 BlockPPC64LE: "LE", 215 BlockPPC64GT: "GT", 216 BlockPPC64GE: "GE", 217 BlockPPC64FLT: "FLT", 218 BlockPPC64FLE: "FLE", 219 BlockPPC64FGT: "FGT", 220 BlockPPC64FGE: "FGE", 221 222 BlockS390XEQ: "EQ", 223 BlockS390XNE: "NE", 224 BlockS390XLT: "LT", 225 BlockS390XLE: "LE", 226 BlockS390XGT: "GT", 227 BlockS390XGE: "GE", 228 BlockS390XGTF: "GTF", 229 BlockS390XGEF: "GEF", 230 231 BlockPlain: "Plain", 232 BlockIf: "If", 233 BlockDefer: "Defer", 234 BlockRet: "Ret", 235 BlockRetJmp: "RetJmp", 236 BlockExit: "Exit", 237 BlockFirst: "First", 238 } 239 240 func (k BlockKind) String() string { return blockString[k] } 241 242 const ( 243 OpInvalid Op = iota 244 245 Op386ADDSS 246 Op386ADDSD 247 Op386SUBSS 248 Op386SUBSD 249 Op386MULSS 250 Op386MULSD 251 Op386DIVSS 252 Op386DIVSD 253 Op386MOVSSload 254 Op386MOVSDload 255 Op386MOVSSconst 256 Op386MOVSDconst 257 Op386MOVSSloadidx1 258 Op386MOVSSloadidx4 259 Op386MOVSDloadidx1 260 Op386MOVSDloadidx8 261 Op386MOVSSstore 262 Op386MOVSDstore 263 Op386MOVSSstoreidx1 264 Op386MOVSSstoreidx4 265 Op386MOVSDstoreidx1 266 Op386MOVSDstoreidx8 267 Op386ADDSSload 268 Op386ADDSDload 269 Op386SUBSSload 270 Op386SUBSDload 271 Op386MULSSload 272 Op386MULSDload 273 Op386DIVSSload 274 Op386DIVSDload 275 Op386ADDL 276 Op386ADDLconst 277 Op386ADDLcarry 278 Op386ADDLconstcarry 279 Op386ADCL 280 Op386ADCLconst 281 Op386SUBL 282 Op386SUBLconst 283 Op386SUBLcarry 284 Op386SUBLconstcarry 285 Op386SBBL 286 Op386SBBLconst 287 Op386MULL 288 Op386MULLconst 289 Op386MULLU 290 Op386HMULL 291 Op386HMULLU 292 Op386MULLQU 293 Op386AVGLU 294 Op386DIVL 295 Op386DIVW 296 Op386DIVLU 297 Op386DIVWU 298 Op386MODL 299 Op386MODW 300 Op386MODLU 301 Op386MODWU 302 Op386ANDL 303 Op386ANDLconst 304 Op386ORL 305 Op386ORLconst 306 Op386XORL 307 Op386XORLconst 308 Op386CMPL 309 Op386CMPW 310 Op386CMPB 311 Op386CMPLconst 312 Op386CMPWconst 313 Op386CMPBconst 314 Op386CMPLload 315 Op386CMPWload 316 Op386CMPBload 317 Op386CMPLconstload 318 Op386CMPWconstload 319 Op386CMPBconstload 320 Op386UCOMISS 321 Op386UCOMISD 322 Op386TESTL 323 Op386TESTW 324 Op386TESTB 325 Op386TESTLconst 326 Op386TESTWconst 327 Op386TESTBconst 328 Op386SHLL 329 Op386SHLLconst 330 Op386SHRL 331 Op386SHRW 332 Op386SHRB 333 Op386SHRLconst 334 Op386SHRWconst 335 Op386SHRBconst 336 Op386SARL 337 Op386SARW 338 Op386SARB 339 Op386SARLconst 340 Op386SARWconst 341 Op386SARBconst 342 Op386ROLLconst 343 Op386ROLWconst 344 Op386ROLBconst 345 Op386ADDLload 346 Op386SUBLload 347 Op386MULLload 348 Op386ANDLload 349 Op386ORLload 350 Op386XORLload 351 Op386ADDLloadidx4 352 Op386SUBLloadidx4 353 Op386MULLloadidx4 354 Op386ANDLloadidx4 355 Op386ORLloadidx4 356 Op386XORLloadidx4 357 Op386NEGL 358 Op386NOTL 359 Op386BSFL 360 Op386BSFW 361 Op386BSRL 362 Op386BSRW 363 Op386BSWAPL 364 Op386SQRTSD 365 Op386SBBLcarrymask 366 Op386SETEQ 367 Op386SETNE 368 Op386SETL 369 Op386SETLE 370 Op386SETG 371 Op386SETGE 372 Op386SETB 373 Op386SETBE 374 Op386SETA 375 Op386SETAE 376 Op386SETO 377 Op386SETEQF 378 Op386SETNEF 379 Op386SETORD 380 Op386SETNAN 381 Op386SETGF 382 Op386SETGEF 383 Op386MOVBLSX 384 Op386MOVBLZX 385 Op386MOVWLSX 386 Op386MOVWLZX 387 Op386MOVLconst 388 Op386CVTTSD2SL 389 Op386CVTTSS2SL 390 Op386CVTSL2SS 391 Op386CVTSL2SD 392 Op386CVTSD2SS 393 Op386CVTSS2SD 394 Op386PXOR 395 Op386LEAL 396 Op386LEAL1 397 Op386LEAL2 398 Op386LEAL4 399 Op386LEAL8 400 Op386MOVBload 401 Op386MOVBLSXload 402 Op386MOVWload 403 Op386MOVWLSXload 404 Op386MOVLload 405 Op386MOVBstore 406 Op386MOVWstore 407 Op386MOVLstore 408 Op386ADDLmodify 409 Op386SUBLmodify 410 Op386ANDLmodify 411 Op386ORLmodify 412 Op386XORLmodify 413 Op386ADDLmodifyidx4 414 Op386SUBLmodifyidx4 415 Op386ANDLmodifyidx4 416 Op386ORLmodifyidx4 417 Op386XORLmodifyidx4 418 Op386ADDLconstmodify 419 Op386ANDLconstmodify 420 Op386ORLconstmodify 421 Op386XORLconstmodify 422 Op386ADDLconstmodifyidx4 423 Op386ANDLconstmodifyidx4 424 Op386ORLconstmodifyidx4 425 Op386XORLconstmodifyidx4 426 Op386MOVBloadidx1 427 Op386MOVWloadidx1 428 Op386MOVWloadidx2 429 Op386MOVLloadidx1 430 Op386MOVLloadidx4 431 Op386MOVBstoreidx1 432 Op386MOVWstoreidx1 433 Op386MOVWstoreidx2 434 Op386MOVLstoreidx1 435 Op386MOVLstoreidx4 436 Op386MOVBstoreconst 437 Op386MOVWstoreconst 438 Op386MOVLstoreconst 439 Op386MOVBstoreconstidx1 440 Op386MOVWstoreconstidx1 441 Op386MOVWstoreconstidx2 442 Op386MOVLstoreconstidx1 443 Op386MOVLstoreconstidx4 444 Op386DUFFZERO 445 Op386REPSTOSL 446 Op386CALLstatic 447 Op386CALLclosure 448 Op386CALLinter 449 Op386DUFFCOPY 450 Op386REPMOVSL 451 Op386InvertFlags 452 Op386LoweredGetG 453 Op386LoweredGetClosurePtr 454 Op386LoweredGetCallerPC 455 Op386LoweredGetCallerSP 456 Op386LoweredNilCheck 457 Op386LoweredWB 458 Op386FlagEQ 459 Op386FlagLT_ULT 460 Op386FlagLT_UGT 461 Op386FlagGT_UGT 462 Op386FlagGT_ULT 463 Op386FCHS 464 Op386MOVSSconst1 465 Op386MOVSDconst1 466 Op386MOVSSconst2 467 Op386MOVSDconst2 468 469 OpAMD64ADDSS 470 OpAMD64ADDSD 471 OpAMD64SUBSS 472 OpAMD64SUBSD 473 OpAMD64MULSS 474 OpAMD64MULSD 475 OpAMD64DIVSS 476 OpAMD64DIVSD 477 OpAMD64MOVSSload 478 OpAMD64MOVSDload 479 OpAMD64MOVSSconst 480 OpAMD64MOVSDconst 481 OpAMD64MOVSSloadidx1 482 OpAMD64MOVSSloadidx4 483 OpAMD64MOVSDloadidx1 484 OpAMD64MOVSDloadidx8 485 OpAMD64MOVSSstore 486 OpAMD64MOVSDstore 487 OpAMD64MOVSSstoreidx1 488 OpAMD64MOVSSstoreidx4 489 OpAMD64MOVSDstoreidx1 490 OpAMD64MOVSDstoreidx8 491 OpAMD64ADDSSload 492 OpAMD64ADDSDload 493 OpAMD64SUBSSload 494 OpAMD64SUBSDload 495 OpAMD64MULSSload 496 OpAMD64MULSDload 497 OpAMD64DIVSSload 498 OpAMD64DIVSDload 499 OpAMD64ADDQ 500 OpAMD64ADDL 501 OpAMD64ADDQconst 502 OpAMD64ADDLconst 503 OpAMD64ADDQconstmodify 504 OpAMD64ADDLconstmodify 505 OpAMD64SUBQ 506 OpAMD64SUBL 507 OpAMD64SUBQconst 508 OpAMD64SUBLconst 509 OpAMD64MULQ 510 OpAMD64MULL 511 OpAMD64MULQconst 512 OpAMD64MULLconst 513 OpAMD64MULLU 514 OpAMD64MULQU 515 OpAMD64HMULQ 516 OpAMD64HMULL 517 OpAMD64HMULQU 518 OpAMD64HMULLU 519 OpAMD64AVGQU 520 OpAMD64DIVQ 521 OpAMD64DIVL 522 OpAMD64DIVW 523 OpAMD64DIVQU 524 OpAMD64DIVLU 525 OpAMD64DIVWU 526 OpAMD64NEGLflags 527 OpAMD64ADDQcarry 528 OpAMD64ADCQ 529 OpAMD64ADDQconstcarry 530 OpAMD64ADCQconst 531 OpAMD64SUBQborrow 532 OpAMD64SBBQ 533 OpAMD64SUBQconstborrow 534 OpAMD64SBBQconst 535 OpAMD64MULQU2 536 OpAMD64DIVQU2 537 OpAMD64ANDQ 538 OpAMD64ANDL 539 OpAMD64ANDQconst 540 OpAMD64ANDLconst 541 OpAMD64ANDQconstmodify 542 OpAMD64ANDLconstmodify 543 OpAMD64ORQ 544 OpAMD64ORL 545 OpAMD64ORQconst 546 OpAMD64ORLconst 547 OpAMD64ORQconstmodify 548 OpAMD64ORLconstmodify 549 OpAMD64XORQ 550 OpAMD64XORL 551 OpAMD64XORQconst 552 OpAMD64XORLconst 553 OpAMD64XORQconstmodify 554 OpAMD64XORLconstmodify 555 OpAMD64CMPQ 556 OpAMD64CMPL 557 OpAMD64CMPW 558 OpAMD64CMPB 559 OpAMD64CMPQconst 560 OpAMD64CMPLconst 561 OpAMD64CMPWconst 562 OpAMD64CMPBconst 563 OpAMD64CMPQload 564 OpAMD64CMPLload 565 OpAMD64CMPWload 566 OpAMD64CMPBload 567 OpAMD64CMPQconstload 568 OpAMD64CMPLconstload 569 OpAMD64CMPWconstload 570 OpAMD64CMPBconstload 571 OpAMD64UCOMISS 572 OpAMD64UCOMISD 573 OpAMD64BTL 574 OpAMD64BTQ 575 OpAMD64BTCL 576 OpAMD64BTCQ 577 OpAMD64BTRL 578 OpAMD64BTRQ 579 OpAMD64BTSL 580 OpAMD64BTSQ 581 OpAMD64BTLconst 582 OpAMD64BTQconst 583 OpAMD64BTCLconst 584 OpAMD64BTCQconst 585 OpAMD64BTRLconst 586 OpAMD64BTRQconst 587 OpAMD64BTSLconst 588 OpAMD64BTSQconst 589 OpAMD64BTCQmodify 590 OpAMD64BTCLmodify 591 OpAMD64BTSQmodify 592 OpAMD64BTSLmodify 593 OpAMD64BTRQmodify 594 OpAMD64BTRLmodify 595 OpAMD64BTCQconstmodify 596 OpAMD64BTCLconstmodify 597 OpAMD64BTSQconstmodify 598 OpAMD64BTSLconstmodify 599 OpAMD64BTRQconstmodify 600 OpAMD64BTRLconstmodify 601 OpAMD64TESTQ 602 OpAMD64TESTL 603 OpAMD64TESTW 604 OpAMD64TESTB 605 OpAMD64TESTQconst 606 OpAMD64TESTLconst 607 OpAMD64TESTWconst 608 OpAMD64TESTBconst 609 OpAMD64SHLQ 610 OpAMD64SHLL 611 OpAMD64SHLQconst 612 OpAMD64SHLLconst 613 OpAMD64SHRQ 614 OpAMD64SHRL 615 OpAMD64SHRW 616 OpAMD64SHRB 617 OpAMD64SHRQconst 618 OpAMD64SHRLconst 619 OpAMD64SHRWconst 620 OpAMD64SHRBconst 621 OpAMD64SARQ 622 OpAMD64SARL 623 OpAMD64SARW 624 OpAMD64SARB 625 OpAMD64SARQconst 626 OpAMD64SARLconst 627 OpAMD64SARWconst 628 OpAMD64SARBconst 629 OpAMD64ROLQ 630 OpAMD64ROLL 631 OpAMD64ROLW 632 OpAMD64ROLB 633 OpAMD64RORQ 634 OpAMD64RORL 635 OpAMD64RORW 636 OpAMD64RORB 637 OpAMD64ROLQconst 638 OpAMD64ROLLconst 639 OpAMD64ROLWconst 640 OpAMD64ROLBconst 641 OpAMD64ADDLload 642 OpAMD64ADDQload 643 OpAMD64SUBQload 644 OpAMD64SUBLload 645 OpAMD64ANDLload 646 OpAMD64ANDQload 647 OpAMD64ORQload 648 OpAMD64ORLload 649 OpAMD64XORQload 650 OpAMD64XORLload 651 OpAMD64ADDQmodify 652 OpAMD64SUBQmodify 653 OpAMD64ANDQmodify 654 OpAMD64ORQmodify 655 OpAMD64XORQmodify 656 OpAMD64ADDLmodify 657 OpAMD64SUBLmodify 658 OpAMD64ANDLmodify 659 OpAMD64ORLmodify 660 OpAMD64XORLmodify 661 OpAMD64NEGQ 662 OpAMD64NEGL 663 OpAMD64NOTQ 664 OpAMD64NOTL 665 OpAMD64BSFQ 666 OpAMD64BSFL 667 OpAMD64BSRQ 668 OpAMD64BSRL 669 OpAMD64CMOVQEQ 670 OpAMD64CMOVQNE 671 OpAMD64CMOVQLT 672 OpAMD64CMOVQGT 673 OpAMD64CMOVQLE 674 OpAMD64CMOVQGE 675 OpAMD64CMOVQLS 676 OpAMD64CMOVQHI 677 OpAMD64CMOVQCC 678 OpAMD64CMOVQCS 679 OpAMD64CMOVLEQ 680 OpAMD64CMOVLNE 681 OpAMD64CMOVLLT 682 OpAMD64CMOVLGT 683 OpAMD64CMOVLLE 684 OpAMD64CMOVLGE 685 OpAMD64CMOVLLS 686 OpAMD64CMOVLHI 687 OpAMD64CMOVLCC 688 OpAMD64CMOVLCS 689 OpAMD64CMOVWEQ 690 OpAMD64CMOVWNE 691 OpAMD64CMOVWLT 692 OpAMD64CMOVWGT 693 OpAMD64CMOVWLE 694 OpAMD64CMOVWGE 695 OpAMD64CMOVWLS 696 OpAMD64CMOVWHI 697 OpAMD64CMOVWCC 698 OpAMD64CMOVWCS 699 OpAMD64CMOVQEQF 700 OpAMD64CMOVQNEF 701 OpAMD64CMOVQGTF 702 OpAMD64CMOVQGEF 703 OpAMD64CMOVLEQF 704 OpAMD64CMOVLNEF 705 OpAMD64CMOVLGTF 706 OpAMD64CMOVLGEF 707 OpAMD64CMOVWEQF 708 OpAMD64CMOVWNEF 709 OpAMD64CMOVWGTF 710 OpAMD64CMOVWGEF 711 OpAMD64BSWAPQ 712 OpAMD64BSWAPL 713 OpAMD64POPCNTQ 714 OpAMD64POPCNTL 715 OpAMD64SQRTSD 716 OpAMD64ROUNDSD 717 OpAMD64SBBQcarrymask 718 OpAMD64SBBLcarrymask 719 OpAMD64SETEQ 720 OpAMD64SETNE 721 OpAMD64SETL 722 OpAMD64SETLE 723 OpAMD64SETG 724 OpAMD64SETGE 725 OpAMD64SETB 726 OpAMD64SETBE 727 OpAMD64SETA 728 OpAMD64SETAE 729 OpAMD64SETO 730 OpAMD64SETEQstore 731 OpAMD64SETNEstore 732 OpAMD64SETLstore 733 OpAMD64SETLEstore 734 OpAMD64SETGstore 735 OpAMD64SETGEstore 736 OpAMD64SETBstore 737 OpAMD64SETBEstore 738 OpAMD64SETAstore 739 OpAMD64SETAEstore 740 OpAMD64SETEQF 741 OpAMD64SETNEF 742 OpAMD64SETORD 743 OpAMD64SETNAN 744 OpAMD64SETGF 745 OpAMD64SETGEF 746 OpAMD64MOVBQSX 747 OpAMD64MOVBQZX 748 OpAMD64MOVWQSX 749 OpAMD64MOVWQZX 750 OpAMD64MOVLQSX 751 OpAMD64MOVLQZX 752 OpAMD64MOVLconst 753 OpAMD64MOVQconst 754 OpAMD64CVTTSD2SL 755 OpAMD64CVTTSD2SQ 756 OpAMD64CVTTSS2SL 757 OpAMD64CVTTSS2SQ 758 OpAMD64CVTSL2SS 759 OpAMD64CVTSL2SD 760 OpAMD64CVTSQ2SS 761 OpAMD64CVTSQ2SD 762 OpAMD64CVTSD2SS 763 OpAMD64CVTSS2SD 764 OpAMD64MOVQi2f 765 OpAMD64MOVQf2i 766 OpAMD64MOVLi2f 767 OpAMD64MOVLf2i 768 OpAMD64PXOR 769 OpAMD64LEAQ 770 OpAMD64LEAL 771 OpAMD64LEAW 772 OpAMD64LEAQ1 773 OpAMD64LEAL1 774 OpAMD64LEAW1 775 OpAMD64LEAQ2 776 OpAMD64LEAL2 777 OpAMD64LEAW2 778 OpAMD64LEAQ4 779 OpAMD64LEAL4 780 OpAMD64LEAW4 781 OpAMD64LEAQ8 782 OpAMD64LEAL8 783 OpAMD64LEAW8 784 OpAMD64MOVBload 785 OpAMD64MOVBQSXload 786 OpAMD64MOVWload 787 OpAMD64MOVWQSXload 788 OpAMD64MOVLload 789 OpAMD64MOVLQSXload 790 OpAMD64MOVQload 791 OpAMD64MOVBstore 792 OpAMD64MOVWstore 793 OpAMD64MOVLstore 794 OpAMD64MOVQstore 795 OpAMD64MOVOload 796 OpAMD64MOVOstore 797 OpAMD64MOVBloadidx1 798 OpAMD64MOVWloadidx1 799 OpAMD64MOVWloadidx2 800 OpAMD64MOVLloadidx1 801 OpAMD64MOVLloadidx4 802 OpAMD64MOVLloadidx8 803 OpAMD64MOVQloadidx1 804 OpAMD64MOVQloadidx8 805 OpAMD64MOVBstoreidx1 806 OpAMD64MOVWstoreidx1 807 OpAMD64MOVWstoreidx2 808 OpAMD64MOVLstoreidx1 809 OpAMD64MOVLstoreidx4 810 OpAMD64MOVLstoreidx8 811 OpAMD64MOVQstoreidx1 812 OpAMD64MOVQstoreidx8 813 OpAMD64MOVBstoreconst 814 OpAMD64MOVWstoreconst 815 OpAMD64MOVLstoreconst 816 OpAMD64MOVQstoreconst 817 OpAMD64MOVBstoreconstidx1 818 OpAMD64MOVWstoreconstidx1 819 OpAMD64MOVWstoreconstidx2 820 OpAMD64MOVLstoreconstidx1 821 OpAMD64MOVLstoreconstidx4 822 OpAMD64MOVQstoreconstidx1 823 OpAMD64MOVQstoreconstidx8 824 OpAMD64DUFFZERO 825 OpAMD64MOVOconst 826 OpAMD64REPSTOSQ 827 OpAMD64CALLstatic 828 OpAMD64CALLclosure 829 OpAMD64CALLinter 830 OpAMD64DUFFCOPY 831 OpAMD64REPMOVSQ 832 OpAMD64InvertFlags 833 OpAMD64LoweredGetG 834 OpAMD64LoweredGetClosurePtr 835 OpAMD64LoweredGetCallerPC 836 OpAMD64LoweredGetCallerSP 837 OpAMD64LoweredNilCheck 838 OpAMD64LoweredWB 839 OpAMD64FlagEQ 840 OpAMD64FlagLT_ULT 841 OpAMD64FlagLT_UGT 842 OpAMD64FlagGT_UGT 843 OpAMD64FlagGT_ULT 844 OpAMD64MOVLatomicload 845 OpAMD64MOVQatomicload 846 OpAMD64XCHGL 847 OpAMD64XCHGQ 848 OpAMD64XADDLlock 849 OpAMD64XADDQlock 850 OpAMD64AddTupleFirst32 851 OpAMD64AddTupleFirst64 852 OpAMD64CMPXCHGLlock 853 OpAMD64CMPXCHGQlock 854 OpAMD64ANDBlock 855 OpAMD64ORBlock 856 857 OpARMADD 858 OpARMADDconst 859 OpARMSUB 860 OpARMSUBconst 861 OpARMRSB 862 OpARMRSBconst 863 OpARMMUL 864 OpARMHMUL 865 OpARMHMULU 866 OpARMCALLudiv 867 OpARMADDS 868 OpARMADDSconst 869 OpARMADC 870 OpARMADCconst 871 OpARMSUBS 872 OpARMSUBSconst 873 OpARMRSBSconst 874 OpARMSBC 875 OpARMSBCconst 876 OpARMRSCconst 877 OpARMMULLU 878 OpARMMULA 879 OpARMMULS 880 OpARMADDF 881 OpARMADDD 882 OpARMSUBF 883 OpARMSUBD 884 OpARMMULF 885 OpARMMULD 886 OpARMNMULF 887 OpARMNMULD 888 OpARMDIVF 889 OpARMDIVD 890 OpARMMULAF 891 OpARMMULAD 892 OpARMMULSF 893 OpARMMULSD 894 OpARMAND 895 OpARMANDconst 896 OpARMOR 897 OpARMORconst 898 OpARMXOR 899 OpARMXORconst 900 OpARMBIC 901 OpARMBICconst 902 OpARMBFX 903 OpARMBFXU 904 OpARMMVN 905 OpARMNEGF 906 OpARMNEGD 907 OpARMSQRTD 908 OpARMCLZ 909 OpARMREV 910 OpARMRBIT 911 OpARMSLL 912 OpARMSLLconst 913 OpARMSRL 914 OpARMSRLconst 915 OpARMSRA 916 OpARMSRAconst 917 OpARMSRRconst 918 OpARMADDshiftLL 919 OpARMADDshiftRL 920 OpARMADDshiftRA 921 OpARMSUBshiftLL 922 OpARMSUBshiftRL 923 OpARMSUBshiftRA 924 OpARMRSBshiftLL 925 OpARMRSBshiftRL 926 OpARMRSBshiftRA 927 OpARMANDshiftLL 928 OpARMANDshiftRL 929 OpARMANDshiftRA 930 OpARMORshiftLL 931 OpARMORshiftRL 932 OpARMORshiftRA 933 OpARMXORshiftLL 934 OpARMXORshiftRL 935 OpARMXORshiftRA 936 OpARMXORshiftRR 937 OpARMBICshiftLL 938 OpARMBICshiftRL 939 OpARMBICshiftRA 940 OpARMMVNshiftLL 941 OpARMMVNshiftRL 942 OpARMMVNshiftRA 943 OpARMADCshiftLL 944 OpARMADCshiftRL 945 OpARMADCshiftRA 946 OpARMSBCshiftLL 947 OpARMSBCshiftRL 948 OpARMSBCshiftRA 949 OpARMRSCshiftLL 950 OpARMRSCshiftRL 951 OpARMRSCshiftRA 952 OpARMADDSshiftLL 953 OpARMADDSshiftRL 954 OpARMADDSshiftRA 955 OpARMSUBSshiftLL 956 OpARMSUBSshiftRL 957 OpARMSUBSshiftRA 958 OpARMRSBSshiftLL 959 OpARMRSBSshiftRL 960 OpARMRSBSshiftRA 961 OpARMADDshiftLLreg 962 OpARMADDshiftRLreg 963 OpARMADDshiftRAreg 964 OpARMSUBshiftLLreg 965 OpARMSUBshiftRLreg 966 OpARMSUBshiftRAreg 967 OpARMRSBshiftLLreg 968 OpARMRSBshiftRLreg 969 OpARMRSBshiftRAreg 970 OpARMANDshiftLLreg 971 OpARMANDshiftRLreg 972 OpARMANDshiftRAreg 973 OpARMORshiftLLreg 974 OpARMORshiftRLreg 975 OpARMORshiftRAreg 976 OpARMXORshiftLLreg 977 OpARMXORshiftRLreg 978 OpARMXORshiftRAreg 979 OpARMBICshiftLLreg 980 OpARMBICshiftRLreg 981 OpARMBICshiftRAreg 982 OpARMMVNshiftLLreg 983 OpARMMVNshiftRLreg 984 OpARMMVNshiftRAreg 985 OpARMADCshiftLLreg 986 OpARMADCshiftRLreg 987 OpARMADCshiftRAreg 988 OpARMSBCshiftLLreg 989 OpARMSBCshiftRLreg 990 OpARMSBCshiftRAreg 991 OpARMRSCshiftLLreg 992 OpARMRSCshiftRLreg 993 OpARMRSCshiftRAreg 994 OpARMADDSshiftLLreg 995 OpARMADDSshiftRLreg 996 OpARMADDSshiftRAreg 997 OpARMSUBSshiftLLreg 998 OpARMSUBSshiftRLreg 999 OpARMSUBSshiftRAreg 1000 OpARMRSBSshiftLLreg 1001 OpARMRSBSshiftRLreg 1002 OpARMRSBSshiftRAreg 1003 OpARMCMP 1004 OpARMCMPconst 1005 OpARMCMN 1006 OpARMCMNconst 1007 OpARMTST 1008 OpARMTSTconst 1009 OpARMTEQ 1010 OpARMTEQconst 1011 OpARMCMPF 1012 OpARMCMPD 1013 OpARMCMPshiftLL 1014 OpARMCMPshiftRL 1015 OpARMCMPshiftRA 1016 OpARMCMNshiftLL 1017 OpARMCMNshiftRL 1018 OpARMCMNshiftRA 1019 OpARMTSTshiftLL 1020 OpARMTSTshiftRL 1021 OpARMTSTshiftRA 1022 OpARMTEQshiftLL 1023 OpARMTEQshiftRL 1024 OpARMTEQshiftRA 1025 OpARMCMPshiftLLreg 1026 OpARMCMPshiftRLreg 1027 OpARMCMPshiftRAreg 1028 OpARMCMNshiftLLreg 1029 OpARMCMNshiftRLreg 1030 OpARMCMNshiftRAreg 1031 OpARMTSTshiftLLreg 1032 OpARMTSTshiftRLreg 1033 OpARMTSTshiftRAreg 1034 OpARMTEQshiftLLreg 1035 OpARMTEQshiftRLreg 1036 OpARMTEQshiftRAreg 1037 OpARMCMPF0 1038 OpARMCMPD0 1039 OpARMMOVWconst 1040 OpARMMOVFconst 1041 OpARMMOVDconst 1042 OpARMMOVWaddr 1043 OpARMMOVBload 1044 OpARMMOVBUload 1045 OpARMMOVHload 1046 OpARMMOVHUload 1047 OpARMMOVWload 1048 OpARMMOVFload 1049 OpARMMOVDload 1050 OpARMMOVBstore 1051 OpARMMOVHstore 1052 OpARMMOVWstore 1053 OpARMMOVFstore 1054 OpARMMOVDstore 1055 OpARMMOVWloadidx 1056 OpARMMOVWloadshiftLL 1057 OpARMMOVWloadshiftRL 1058 OpARMMOVWloadshiftRA 1059 OpARMMOVBUloadidx 1060 OpARMMOVBloadidx 1061 OpARMMOVHUloadidx 1062 OpARMMOVHloadidx 1063 OpARMMOVWstoreidx 1064 OpARMMOVWstoreshiftLL 1065 OpARMMOVWstoreshiftRL 1066 OpARMMOVWstoreshiftRA 1067 OpARMMOVBstoreidx 1068 OpARMMOVHstoreidx 1069 OpARMMOVBreg 1070 OpARMMOVBUreg 1071 OpARMMOVHreg 1072 OpARMMOVHUreg 1073 OpARMMOVWreg 1074 OpARMMOVWnop 1075 OpARMMOVWF 1076 OpARMMOVWD 1077 OpARMMOVWUF 1078 OpARMMOVWUD 1079 OpARMMOVFW 1080 OpARMMOVDW 1081 OpARMMOVFWU 1082 OpARMMOVDWU 1083 OpARMMOVFD 1084 OpARMMOVDF 1085 OpARMCMOVWHSconst 1086 OpARMCMOVWLSconst 1087 OpARMSRAcond 1088 OpARMCALLstatic 1089 OpARMCALLclosure 1090 OpARMCALLinter 1091 OpARMLoweredNilCheck 1092 OpARMEqual 1093 OpARMNotEqual 1094 OpARMLessThan 1095 OpARMLessEqual 1096 OpARMGreaterThan 1097 OpARMGreaterEqual 1098 OpARMLessThanU 1099 OpARMLessEqualU 1100 OpARMGreaterThanU 1101 OpARMGreaterEqualU 1102 OpARMDUFFZERO 1103 OpARMDUFFCOPY 1104 OpARMLoweredZero 1105 OpARMLoweredMove 1106 OpARMLoweredGetClosurePtr 1107 OpARMLoweredGetCallerSP 1108 OpARMLoweredGetCallerPC 1109 OpARMFlagEQ 1110 OpARMFlagLT_ULT 1111 OpARMFlagLT_UGT 1112 OpARMFlagGT_UGT 1113 OpARMFlagGT_ULT 1114 OpARMInvertFlags 1115 OpARMLoweredWB 1116 1117 OpARM64ADD 1118 OpARM64ADDconst 1119 OpARM64SUB 1120 OpARM64SUBconst 1121 OpARM64MUL 1122 OpARM64MULW 1123 OpARM64MNEG 1124 OpARM64MNEGW 1125 OpARM64MULH 1126 OpARM64UMULH 1127 OpARM64MULL 1128 OpARM64UMULL 1129 OpARM64DIV 1130 OpARM64UDIV 1131 OpARM64DIVW 1132 OpARM64UDIVW 1133 OpARM64MOD 1134 OpARM64UMOD 1135 OpARM64MODW 1136 OpARM64UMODW 1137 OpARM64FADDS 1138 OpARM64FADDD 1139 OpARM64FSUBS 1140 OpARM64FSUBD 1141 OpARM64FMULS 1142 OpARM64FMULD 1143 OpARM64FNMULS 1144 OpARM64FNMULD 1145 OpARM64FDIVS 1146 OpARM64FDIVD 1147 OpARM64AND 1148 OpARM64ANDconst 1149 OpARM64OR 1150 OpARM64ORconst 1151 OpARM64XOR 1152 OpARM64XORconst 1153 OpARM64BIC 1154 OpARM64EON 1155 OpARM64ORN 1156 OpARM64LoweredMuluhilo 1157 OpARM64MVN 1158 OpARM64NEG 1159 OpARM64FABSD 1160 OpARM64FNEGS 1161 OpARM64FNEGD 1162 OpARM64FSQRTD 1163 OpARM64REV 1164 OpARM64REVW 1165 OpARM64REV16W 1166 OpARM64RBIT 1167 OpARM64RBITW 1168 OpARM64CLZ 1169 OpARM64CLZW 1170 OpARM64VCNT 1171 OpARM64VUADDLV 1172 OpARM64LoweredRound32F 1173 OpARM64LoweredRound64F 1174 OpARM64FMADDS 1175 OpARM64FMADDD 1176 OpARM64FNMADDS 1177 OpARM64FNMADDD 1178 OpARM64FMSUBS 1179 OpARM64FMSUBD 1180 OpARM64FNMSUBS 1181 OpARM64FNMSUBD 1182 OpARM64MADD 1183 OpARM64MADDW 1184 OpARM64MSUB 1185 OpARM64MSUBW 1186 OpARM64SLL 1187 OpARM64SLLconst 1188 OpARM64SRL 1189 OpARM64SRLconst 1190 OpARM64SRA 1191 OpARM64SRAconst 1192 OpARM64ROR 1193 OpARM64RORW 1194 OpARM64RORconst 1195 OpARM64RORWconst 1196 OpARM64EXTRconst 1197 OpARM64EXTRWconst 1198 OpARM64CMP 1199 OpARM64CMPconst 1200 OpARM64CMPW 1201 OpARM64CMPWconst 1202 OpARM64CMN 1203 OpARM64CMNconst 1204 OpARM64CMNW 1205 OpARM64CMNWconst 1206 OpARM64TST 1207 OpARM64TSTconst 1208 OpARM64TSTW 1209 OpARM64TSTWconst 1210 OpARM64FCMPS 1211 OpARM64FCMPD 1212 OpARM64MVNshiftLL 1213 OpARM64MVNshiftRL 1214 OpARM64MVNshiftRA 1215 OpARM64NEGshiftLL 1216 OpARM64NEGshiftRL 1217 OpARM64NEGshiftRA 1218 OpARM64ADDshiftLL 1219 OpARM64ADDshiftRL 1220 OpARM64ADDshiftRA 1221 OpARM64SUBshiftLL 1222 OpARM64SUBshiftRL 1223 OpARM64SUBshiftRA 1224 OpARM64ANDshiftLL 1225 OpARM64ANDshiftRL 1226 OpARM64ANDshiftRA 1227 OpARM64ORshiftLL 1228 OpARM64ORshiftRL 1229 OpARM64ORshiftRA 1230 OpARM64XORshiftLL 1231 OpARM64XORshiftRL 1232 OpARM64XORshiftRA 1233 OpARM64BICshiftLL 1234 OpARM64BICshiftRL 1235 OpARM64BICshiftRA 1236 OpARM64EONshiftLL 1237 OpARM64EONshiftRL 1238 OpARM64EONshiftRA 1239 OpARM64ORNshiftLL 1240 OpARM64ORNshiftRL 1241 OpARM64ORNshiftRA 1242 OpARM64CMPshiftLL 1243 OpARM64CMPshiftRL 1244 OpARM64CMPshiftRA 1245 OpARM64CMNshiftLL 1246 OpARM64CMNshiftRL 1247 OpARM64CMNshiftRA 1248 OpARM64TSTshiftLL 1249 OpARM64TSTshiftRL 1250 OpARM64TSTshiftRA 1251 OpARM64BFI 1252 OpARM64BFXIL 1253 OpARM64SBFIZ 1254 OpARM64SBFX 1255 OpARM64UBFIZ 1256 OpARM64UBFX 1257 OpARM64MOVDconst 1258 OpARM64FMOVSconst 1259 OpARM64FMOVDconst 1260 OpARM64MOVDaddr 1261 OpARM64MOVBload 1262 OpARM64MOVBUload 1263 OpARM64MOVHload 1264 OpARM64MOVHUload 1265 OpARM64MOVWload 1266 OpARM64MOVWUload 1267 OpARM64MOVDload 1268 OpARM64FMOVSload 1269 OpARM64FMOVDload 1270 OpARM64MOVDloadidx 1271 OpARM64MOVWloadidx 1272 OpARM64MOVWUloadidx 1273 OpARM64MOVHloadidx 1274 OpARM64MOVHUloadidx 1275 OpARM64MOVBloadidx 1276 OpARM64MOVBUloadidx 1277 OpARM64FMOVSloadidx 1278 OpARM64FMOVDloadidx 1279 OpARM64MOVHloadidx2 1280 OpARM64MOVHUloadidx2 1281 OpARM64MOVWloadidx4 1282 OpARM64MOVWUloadidx4 1283 OpARM64MOVDloadidx8 1284 OpARM64MOVBstore 1285 OpARM64MOVHstore 1286 OpARM64MOVWstore 1287 OpARM64MOVDstore 1288 OpARM64STP 1289 OpARM64FMOVSstore 1290 OpARM64FMOVDstore 1291 OpARM64MOVBstoreidx 1292 OpARM64MOVHstoreidx 1293 OpARM64MOVWstoreidx 1294 OpARM64MOVDstoreidx 1295 OpARM64FMOVSstoreidx 1296 OpARM64FMOVDstoreidx 1297 OpARM64MOVHstoreidx2 1298 OpARM64MOVWstoreidx4 1299 OpARM64MOVDstoreidx8 1300 OpARM64MOVBstorezero 1301 OpARM64MOVHstorezero 1302 OpARM64MOVWstorezero 1303 OpARM64MOVDstorezero 1304 OpARM64MOVQstorezero 1305 OpARM64MOVBstorezeroidx 1306 OpARM64MOVHstorezeroidx 1307 OpARM64MOVWstorezeroidx 1308 OpARM64MOVDstorezeroidx 1309 OpARM64MOVHstorezeroidx2 1310 OpARM64MOVWstorezeroidx4 1311 OpARM64MOVDstorezeroidx8 1312 OpARM64FMOVDgpfp 1313 OpARM64FMOVDfpgp 1314 OpARM64FMOVSgpfp 1315 OpARM64FMOVSfpgp 1316 OpARM64MOVBreg 1317 OpARM64MOVBUreg 1318 OpARM64MOVHreg 1319 OpARM64MOVHUreg 1320 OpARM64MOVWreg 1321 OpARM64MOVWUreg 1322 OpARM64MOVDreg 1323 OpARM64MOVDnop 1324 OpARM64SCVTFWS 1325 OpARM64SCVTFWD 1326 OpARM64UCVTFWS 1327 OpARM64UCVTFWD 1328 OpARM64SCVTFS 1329 OpARM64SCVTFD 1330 OpARM64UCVTFS 1331 OpARM64UCVTFD 1332 OpARM64FCVTZSSW 1333 OpARM64FCVTZSDW 1334 OpARM64FCVTZUSW 1335 OpARM64FCVTZUDW 1336 OpARM64FCVTZSS 1337 OpARM64FCVTZSD 1338 OpARM64FCVTZUS 1339 OpARM64FCVTZUD 1340 OpARM64FCVTSD 1341 OpARM64FCVTDS 1342 OpARM64FRINTAD 1343 OpARM64FRINTMD 1344 OpARM64FRINTND 1345 OpARM64FRINTPD 1346 OpARM64FRINTZD 1347 OpARM64CSEL 1348 OpARM64CSEL0 1349 OpARM64CALLstatic 1350 OpARM64CALLclosure 1351 OpARM64CALLinter 1352 OpARM64LoweredNilCheck 1353 OpARM64Equal 1354 OpARM64NotEqual 1355 OpARM64LessThan 1356 OpARM64LessEqual 1357 OpARM64GreaterThan 1358 OpARM64GreaterEqual 1359 OpARM64LessThanU 1360 OpARM64LessEqualU 1361 OpARM64GreaterThanU 1362 OpARM64GreaterEqualU 1363 OpARM64DUFFZERO 1364 OpARM64LoweredZero 1365 OpARM64DUFFCOPY 1366 OpARM64LoweredMove 1367 OpARM64LoweredGetClosurePtr 1368 OpARM64LoweredGetCallerSP 1369 OpARM64LoweredGetCallerPC 1370 OpARM64FlagEQ 1371 OpARM64FlagLT_ULT 1372 OpARM64FlagLT_UGT 1373 OpARM64FlagGT_UGT 1374 OpARM64FlagGT_ULT 1375 OpARM64InvertFlags 1376 OpARM64LDAR 1377 OpARM64LDARW 1378 OpARM64STLR 1379 OpARM64STLRW 1380 OpARM64LoweredAtomicExchange64 1381 OpARM64LoweredAtomicExchange32 1382 OpARM64LoweredAtomicAdd64 1383 OpARM64LoweredAtomicAdd32 1384 OpARM64LoweredAtomicAdd64Variant 1385 OpARM64LoweredAtomicAdd32Variant 1386 OpARM64LoweredAtomicCas64 1387 OpARM64LoweredAtomicCas32 1388 OpARM64LoweredAtomicAnd8 1389 OpARM64LoweredAtomicOr8 1390 OpARM64LoweredWB 1391 1392 OpMIPSADD 1393 OpMIPSADDconst 1394 OpMIPSSUB 1395 OpMIPSSUBconst 1396 OpMIPSMUL 1397 OpMIPSMULT 1398 OpMIPSMULTU 1399 OpMIPSDIV 1400 OpMIPSDIVU 1401 OpMIPSADDF 1402 OpMIPSADDD 1403 OpMIPSSUBF 1404 OpMIPSSUBD 1405 OpMIPSMULF 1406 OpMIPSMULD 1407 OpMIPSDIVF 1408 OpMIPSDIVD 1409 OpMIPSAND 1410 OpMIPSANDconst 1411 OpMIPSOR 1412 OpMIPSORconst 1413 OpMIPSXOR 1414 OpMIPSXORconst 1415 OpMIPSNOR 1416 OpMIPSNORconst 1417 OpMIPSNEG 1418 OpMIPSNEGF 1419 OpMIPSNEGD 1420 OpMIPSSQRTD 1421 OpMIPSSLL 1422 OpMIPSSLLconst 1423 OpMIPSSRL 1424 OpMIPSSRLconst 1425 OpMIPSSRA 1426 OpMIPSSRAconst 1427 OpMIPSCLZ 1428 OpMIPSSGT 1429 OpMIPSSGTconst 1430 OpMIPSSGTzero 1431 OpMIPSSGTU 1432 OpMIPSSGTUconst 1433 OpMIPSSGTUzero 1434 OpMIPSCMPEQF 1435 OpMIPSCMPEQD 1436 OpMIPSCMPGEF 1437 OpMIPSCMPGED 1438 OpMIPSCMPGTF 1439 OpMIPSCMPGTD 1440 OpMIPSMOVWconst 1441 OpMIPSMOVFconst 1442 OpMIPSMOVDconst 1443 OpMIPSMOVWaddr 1444 OpMIPSMOVBload 1445 OpMIPSMOVBUload 1446 OpMIPSMOVHload 1447 OpMIPSMOVHUload 1448 OpMIPSMOVWload 1449 OpMIPSMOVFload 1450 OpMIPSMOVDload 1451 OpMIPSMOVBstore 1452 OpMIPSMOVHstore 1453 OpMIPSMOVWstore 1454 OpMIPSMOVFstore 1455 OpMIPSMOVDstore 1456 OpMIPSMOVBstorezero 1457 OpMIPSMOVHstorezero 1458 OpMIPSMOVWstorezero 1459 OpMIPSMOVBreg 1460 OpMIPSMOVBUreg 1461 OpMIPSMOVHreg 1462 OpMIPSMOVHUreg 1463 OpMIPSMOVWreg 1464 OpMIPSMOVWnop 1465 OpMIPSCMOVZ 1466 OpMIPSCMOVZzero 1467 OpMIPSMOVWF 1468 OpMIPSMOVWD 1469 OpMIPSTRUNCFW 1470 OpMIPSTRUNCDW 1471 OpMIPSMOVFD 1472 OpMIPSMOVDF 1473 OpMIPSCALLstatic 1474 OpMIPSCALLclosure 1475 OpMIPSCALLinter 1476 OpMIPSLoweredAtomicLoad 1477 OpMIPSLoweredAtomicStore 1478 OpMIPSLoweredAtomicStorezero 1479 OpMIPSLoweredAtomicExchange 1480 OpMIPSLoweredAtomicAdd 1481 OpMIPSLoweredAtomicAddconst 1482 OpMIPSLoweredAtomicCas 1483 OpMIPSLoweredAtomicAnd 1484 OpMIPSLoweredAtomicOr 1485 OpMIPSLoweredZero 1486 OpMIPSLoweredMove 1487 OpMIPSLoweredNilCheck 1488 OpMIPSFPFlagTrue 1489 OpMIPSFPFlagFalse 1490 OpMIPSLoweredGetClosurePtr 1491 OpMIPSLoweredGetCallerSP 1492 OpMIPSLoweredGetCallerPC 1493 OpMIPSLoweredWB 1494 1495 OpMIPS64ADDV 1496 OpMIPS64ADDVconst 1497 OpMIPS64SUBV 1498 OpMIPS64SUBVconst 1499 OpMIPS64MULV 1500 OpMIPS64MULVU 1501 OpMIPS64DIVV 1502 OpMIPS64DIVVU 1503 OpMIPS64ADDF 1504 OpMIPS64ADDD 1505 OpMIPS64SUBF 1506 OpMIPS64SUBD 1507 OpMIPS64MULF 1508 OpMIPS64MULD 1509 OpMIPS64DIVF 1510 OpMIPS64DIVD 1511 OpMIPS64AND 1512 OpMIPS64ANDconst 1513 OpMIPS64OR 1514 OpMIPS64ORconst 1515 OpMIPS64XOR 1516 OpMIPS64XORconst 1517 OpMIPS64NOR 1518 OpMIPS64NORconst 1519 OpMIPS64NEGV 1520 OpMIPS64NEGF 1521 OpMIPS64NEGD 1522 OpMIPS64SQRTD 1523 OpMIPS64SLLV 1524 OpMIPS64SLLVconst 1525 OpMIPS64SRLV 1526 OpMIPS64SRLVconst 1527 OpMIPS64SRAV 1528 OpMIPS64SRAVconst 1529 OpMIPS64SGT 1530 OpMIPS64SGTconst 1531 OpMIPS64SGTU 1532 OpMIPS64SGTUconst 1533 OpMIPS64CMPEQF 1534 OpMIPS64CMPEQD 1535 OpMIPS64CMPGEF 1536 OpMIPS64CMPGED 1537 OpMIPS64CMPGTF 1538 OpMIPS64CMPGTD 1539 OpMIPS64MOVVconst 1540 OpMIPS64MOVFconst 1541 OpMIPS64MOVDconst 1542 OpMIPS64MOVVaddr 1543 OpMIPS64MOVBload 1544 OpMIPS64MOVBUload 1545 OpMIPS64MOVHload 1546 OpMIPS64MOVHUload 1547 OpMIPS64MOVWload 1548 OpMIPS64MOVWUload 1549 OpMIPS64MOVVload 1550 OpMIPS64MOVFload 1551 OpMIPS64MOVDload 1552 OpMIPS64MOVBstore 1553 OpMIPS64MOVHstore 1554 OpMIPS64MOVWstore 1555 OpMIPS64MOVVstore 1556 OpMIPS64MOVFstore 1557 OpMIPS64MOVDstore 1558 OpMIPS64MOVBstorezero 1559 OpMIPS64MOVHstorezero 1560 OpMIPS64MOVWstorezero 1561 OpMIPS64MOVVstorezero 1562 OpMIPS64MOVBreg 1563 OpMIPS64MOVBUreg 1564 OpMIPS64MOVHreg 1565 OpMIPS64MOVHUreg 1566 OpMIPS64MOVWreg 1567 OpMIPS64MOVWUreg 1568 OpMIPS64MOVVreg 1569 OpMIPS64MOVVnop 1570 OpMIPS64MOVWF 1571 OpMIPS64MOVWD 1572 OpMIPS64MOVVF 1573 OpMIPS64MOVVD 1574 OpMIPS64TRUNCFW 1575 OpMIPS64TRUNCDW 1576 OpMIPS64TRUNCFV 1577 OpMIPS64TRUNCDV 1578 OpMIPS64MOVFD 1579 OpMIPS64MOVDF 1580 OpMIPS64CALLstatic 1581 OpMIPS64CALLclosure 1582 OpMIPS64CALLinter 1583 OpMIPS64DUFFZERO 1584 OpMIPS64LoweredZero 1585 OpMIPS64LoweredMove 1586 OpMIPS64LoweredAtomicLoad32 1587 OpMIPS64LoweredAtomicLoad64 1588 OpMIPS64LoweredAtomicStore32 1589 OpMIPS64LoweredAtomicStore64 1590 OpMIPS64LoweredAtomicStorezero32 1591 OpMIPS64LoweredAtomicStorezero64 1592 OpMIPS64LoweredAtomicExchange32 1593 OpMIPS64LoweredAtomicExchange64 1594 OpMIPS64LoweredAtomicAdd32 1595 OpMIPS64LoweredAtomicAdd64 1596 OpMIPS64LoweredAtomicAddconst32 1597 OpMIPS64LoweredAtomicAddconst64 1598 OpMIPS64LoweredAtomicCas32 1599 OpMIPS64LoweredAtomicCas64 1600 OpMIPS64LoweredNilCheck 1601 OpMIPS64FPFlagTrue 1602 OpMIPS64FPFlagFalse 1603 OpMIPS64LoweredGetClosurePtr 1604 OpMIPS64LoweredGetCallerSP 1605 OpMIPS64LoweredGetCallerPC 1606 OpMIPS64LoweredWB 1607 1608 OpPPC64ADD 1609 OpPPC64ADDconst 1610 OpPPC64FADD 1611 OpPPC64FADDS 1612 OpPPC64SUB 1613 OpPPC64FSUB 1614 OpPPC64FSUBS 1615 OpPPC64MULLD 1616 OpPPC64MULLW 1617 OpPPC64MULHD 1618 OpPPC64MULHW 1619 OpPPC64MULHDU 1620 OpPPC64MULHWU 1621 OpPPC64LoweredMuluhilo 1622 OpPPC64FMUL 1623 OpPPC64FMULS 1624 OpPPC64FMADD 1625 OpPPC64FMADDS 1626 OpPPC64FMSUB 1627 OpPPC64FMSUBS 1628 OpPPC64SRAD 1629 OpPPC64SRAW 1630 OpPPC64SRD 1631 OpPPC64SRW 1632 OpPPC64SLD 1633 OpPPC64SLW 1634 OpPPC64ROTL 1635 OpPPC64ROTLW 1636 OpPPC64ADDconstForCarry 1637 OpPPC64MaskIfNotCarry 1638 OpPPC64SRADconst 1639 OpPPC64SRAWconst 1640 OpPPC64SRDconst 1641 OpPPC64SRWconst 1642 OpPPC64SLDconst 1643 OpPPC64SLWconst 1644 OpPPC64ROTLconst 1645 OpPPC64ROTLWconst 1646 OpPPC64CNTLZD 1647 OpPPC64CNTLZW 1648 OpPPC64POPCNTD 1649 OpPPC64POPCNTW 1650 OpPPC64POPCNTB 1651 OpPPC64FDIV 1652 OpPPC64FDIVS 1653 OpPPC64DIVD 1654 OpPPC64DIVW 1655 OpPPC64DIVDU 1656 OpPPC64DIVWU 1657 OpPPC64FCTIDZ 1658 OpPPC64FCTIWZ 1659 OpPPC64FCFID 1660 OpPPC64FCFIDS 1661 OpPPC64FRSP 1662 OpPPC64MFVSRD 1663 OpPPC64MTVSRD 1664 OpPPC64AND 1665 OpPPC64ANDN 1666 OpPPC64ANDCC 1667 OpPPC64OR 1668 OpPPC64ORN 1669 OpPPC64ORCC 1670 OpPPC64NOR 1671 OpPPC64XOR 1672 OpPPC64XORCC 1673 OpPPC64EQV 1674 OpPPC64NEG 1675 OpPPC64FNEG 1676 OpPPC64FSQRT 1677 OpPPC64FSQRTS 1678 OpPPC64FFLOOR 1679 OpPPC64FCEIL 1680 OpPPC64FTRUNC 1681 OpPPC64FROUND 1682 OpPPC64FABS 1683 OpPPC64FNABS 1684 OpPPC64FCPSGN 1685 OpPPC64ORconst 1686 OpPPC64XORconst 1687 OpPPC64ANDconst 1688 OpPPC64ANDCCconst 1689 OpPPC64MOVBreg 1690 OpPPC64MOVBZreg 1691 OpPPC64MOVHreg 1692 OpPPC64MOVHZreg 1693 OpPPC64MOVWreg 1694 OpPPC64MOVWZreg 1695 OpPPC64MOVBZload 1696 OpPPC64MOVHload 1697 OpPPC64MOVHZload 1698 OpPPC64MOVWload 1699 OpPPC64MOVWZload 1700 OpPPC64MOVDload 1701 OpPPC64MOVDBRload 1702 OpPPC64MOVWBRload 1703 OpPPC64MOVHBRload 1704 OpPPC64MOVBZloadidx 1705 OpPPC64MOVHloadidx 1706 OpPPC64MOVHZloadidx 1707 OpPPC64MOVWloadidx 1708 OpPPC64MOVWZloadidx 1709 OpPPC64MOVDloadidx 1710 OpPPC64MOVHBRloadidx 1711 OpPPC64MOVWBRloadidx 1712 OpPPC64MOVDBRloadidx 1713 OpPPC64FMOVDloadidx 1714 OpPPC64FMOVSloadidx 1715 OpPPC64MOVDBRstore 1716 OpPPC64MOVWBRstore 1717 OpPPC64MOVHBRstore 1718 OpPPC64FMOVDload 1719 OpPPC64FMOVSload 1720 OpPPC64MOVBstore 1721 OpPPC64MOVHstore 1722 OpPPC64MOVWstore 1723 OpPPC64MOVDstore 1724 OpPPC64FMOVDstore 1725 OpPPC64FMOVSstore 1726 OpPPC64MOVBstoreidx 1727 OpPPC64MOVHstoreidx 1728 OpPPC64MOVWstoreidx 1729 OpPPC64MOVDstoreidx 1730 OpPPC64FMOVDstoreidx 1731 OpPPC64FMOVSstoreidx 1732 OpPPC64MOVHBRstoreidx 1733 OpPPC64MOVWBRstoreidx 1734 OpPPC64MOVDBRstoreidx 1735 OpPPC64MOVBstorezero 1736 OpPPC64MOVHstorezero 1737 OpPPC64MOVWstorezero 1738 OpPPC64MOVDstorezero 1739 OpPPC64MOVDaddr 1740 OpPPC64MOVDconst 1741 OpPPC64FMOVDconst 1742 OpPPC64FMOVSconst 1743 OpPPC64FCMPU 1744 OpPPC64CMP 1745 OpPPC64CMPU 1746 OpPPC64CMPW 1747 OpPPC64CMPWU 1748 OpPPC64CMPconst 1749 OpPPC64CMPUconst 1750 OpPPC64CMPWconst 1751 OpPPC64CMPWUconst 1752 OpPPC64Equal 1753 OpPPC64NotEqual 1754 OpPPC64LessThan 1755 OpPPC64FLessThan 1756 OpPPC64LessEqual 1757 OpPPC64FLessEqual 1758 OpPPC64GreaterThan 1759 OpPPC64FGreaterThan 1760 OpPPC64GreaterEqual 1761 OpPPC64FGreaterEqual 1762 OpPPC64LoweredGetClosurePtr 1763 OpPPC64LoweredGetCallerSP 1764 OpPPC64LoweredGetCallerPC 1765 OpPPC64LoweredNilCheck 1766 OpPPC64LoweredRound32F 1767 OpPPC64LoweredRound64F 1768 OpPPC64CALLstatic 1769 OpPPC64CALLclosure 1770 OpPPC64CALLinter 1771 OpPPC64LoweredZero 1772 OpPPC64LoweredMove 1773 OpPPC64LoweredAtomicStore32 1774 OpPPC64LoweredAtomicStore64 1775 OpPPC64LoweredAtomicLoad32 1776 OpPPC64LoweredAtomicLoad64 1777 OpPPC64LoweredAtomicLoadPtr 1778 OpPPC64LoweredAtomicAdd32 1779 OpPPC64LoweredAtomicAdd64 1780 OpPPC64LoweredAtomicExchange32 1781 OpPPC64LoweredAtomicExchange64 1782 OpPPC64LoweredAtomicCas64 1783 OpPPC64LoweredAtomicCas32 1784 OpPPC64LoweredAtomicAnd8 1785 OpPPC64LoweredAtomicOr8 1786 OpPPC64LoweredWB 1787 OpPPC64InvertFlags 1788 OpPPC64FlagEQ 1789 OpPPC64FlagLT 1790 OpPPC64FlagGT 1791 1792 OpS390XFADDS 1793 OpS390XFADD 1794 OpS390XFSUBS 1795 OpS390XFSUB 1796 OpS390XFMULS 1797 OpS390XFMUL 1798 OpS390XFDIVS 1799 OpS390XFDIV 1800 OpS390XFNEGS 1801 OpS390XFNEG 1802 OpS390XFMADDS 1803 OpS390XFMADD 1804 OpS390XFMSUBS 1805 OpS390XFMSUB 1806 OpS390XLPDFR 1807 OpS390XLNDFR 1808 OpS390XCPSDR 1809 OpS390XFIDBR 1810 OpS390XFMOVSload 1811 OpS390XFMOVDload 1812 OpS390XFMOVSconst 1813 OpS390XFMOVDconst 1814 OpS390XFMOVSloadidx 1815 OpS390XFMOVDloadidx 1816 OpS390XFMOVSstore 1817 OpS390XFMOVDstore 1818 OpS390XFMOVSstoreidx 1819 OpS390XFMOVDstoreidx 1820 OpS390XADD 1821 OpS390XADDW 1822 OpS390XADDconst 1823 OpS390XADDWconst 1824 OpS390XADDload 1825 OpS390XADDWload 1826 OpS390XSUB 1827 OpS390XSUBW 1828 OpS390XSUBconst 1829 OpS390XSUBWconst 1830 OpS390XSUBload 1831 OpS390XSUBWload 1832 OpS390XMULLD 1833 OpS390XMULLW 1834 OpS390XMULLDconst 1835 OpS390XMULLWconst 1836 OpS390XMULLDload 1837 OpS390XMULLWload 1838 OpS390XMULHD 1839 OpS390XMULHDU 1840 OpS390XDIVD 1841 OpS390XDIVW 1842 OpS390XDIVDU 1843 OpS390XDIVWU 1844 OpS390XMODD 1845 OpS390XMODW 1846 OpS390XMODDU 1847 OpS390XMODWU 1848 OpS390XAND 1849 OpS390XANDW 1850 OpS390XANDconst 1851 OpS390XANDWconst 1852 OpS390XANDload 1853 OpS390XANDWload 1854 OpS390XOR 1855 OpS390XORW 1856 OpS390XORconst 1857 OpS390XORWconst 1858 OpS390XORload 1859 OpS390XORWload 1860 OpS390XXOR 1861 OpS390XXORW 1862 OpS390XXORconst 1863 OpS390XXORWconst 1864 OpS390XXORload 1865 OpS390XXORWload 1866 OpS390XCMP 1867 OpS390XCMPW 1868 OpS390XCMPU 1869 OpS390XCMPWU 1870 OpS390XCMPconst 1871 OpS390XCMPWconst 1872 OpS390XCMPUconst 1873 OpS390XCMPWUconst 1874 OpS390XFCMPS 1875 OpS390XFCMP 1876 OpS390XSLD 1877 OpS390XSLW 1878 OpS390XSLDconst 1879 OpS390XSLWconst 1880 OpS390XSRD 1881 OpS390XSRW 1882 OpS390XSRDconst 1883 OpS390XSRWconst 1884 OpS390XSRAD 1885 OpS390XSRAW 1886 OpS390XSRADconst 1887 OpS390XSRAWconst 1888 OpS390XRLLG 1889 OpS390XRLL 1890 OpS390XRLLGconst 1891 OpS390XRLLconst 1892 OpS390XNEG 1893 OpS390XNEGW 1894 OpS390XNOT 1895 OpS390XNOTW 1896 OpS390XFSQRT 1897 OpS390XMOVDEQ 1898 OpS390XMOVDNE 1899 OpS390XMOVDLT 1900 OpS390XMOVDLE 1901 OpS390XMOVDGT 1902 OpS390XMOVDGE 1903 OpS390XMOVDGTnoinv 1904 OpS390XMOVDGEnoinv 1905 OpS390XMOVBreg 1906 OpS390XMOVBZreg 1907 OpS390XMOVHreg 1908 OpS390XMOVHZreg 1909 OpS390XMOVWreg 1910 OpS390XMOVWZreg 1911 OpS390XMOVDreg 1912 OpS390XMOVDnop 1913 OpS390XMOVDconst 1914 OpS390XLDGR 1915 OpS390XLGDR 1916 OpS390XCFDBRA 1917 OpS390XCGDBRA 1918 OpS390XCFEBRA 1919 OpS390XCGEBRA 1920 OpS390XCEFBRA 1921 OpS390XCDFBRA 1922 OpS390XCEGBRA 1923 OpS390XCDGBRA 1924 OpS390XLEDBR 1925 OpS390XLDEBR 1926 OpS390XMOVDaddr 1927 OpS390XMOVDaddridx 1928 OpS390XMOVBZload 1929 OpS390XMOVBload 1930 OpS390XMOVHZload 1931 OpS390XMOVHload 1932 OpS390XMOVWZload 1933 OpS390XMOVWload 1934 OpS390XMOVDload 1935 OpS390XMOVWBR 1936 OpS390XMOVDBR 1937 OpS390XMOVHBRload 1938 OpS390XMOVWBRload 1939 OpS390XMOVDBRload 1940 OpS390XMOVBstore 1941 OpS390XMOVHstore 1942 OpS390XMOVWstore 1943 OpS390XMOVDstore 1944 OpS390XMOVHBRstore 1945 OpS390XMOVWBRstore 1946 OpS390XMOVDBRstore 1947 OpS390XMVC 1948 OpS390XMOVBZloadidx 1949 OpS390XMOVBloadidx 1950 OpS390XMOVHZloadidx 1951 OpS390XMOVHloadidx 1952 OpS390XMOVWZloadidx 1953 OpS390XMOVWloadidx 1954 OpS390XMOVDloadidx 1955 OpS390XMOVHBRloadidx 1956 OpS390XMOVWBRloadidx 1957 OpS390XMOVDBRloadidx 1958 OpS390XMOVBstoreidx 1959 OpS390XMOVHstoreidx 1960 OpS390XMOVWstoreidx 1961 OpS390XMOVDstoreidx 1962 OpS390XMOVHBRstoreidx 1963 OpS390XMOVWBRstoreidx 1964 OpS390XMOVDBRstoreidx 1965 OpS390XMOVBstoreconst 1966 OpS390XMOVHstoreconst 1967 OpS390XMOVWstoreconst 1968 OpS390XMOVDstoreconst 1969 OpS390XCLEAR 1970 OpS390XCALLstatic 1971 OpS390XCALLclosure 1972 OpS390XCALLinter 1973 OpS390XInvertFlags 1974 OpS390XLoweredGetG 1975 OpS390XLoweredGetClosurePtr 1976 OpS390XLoweredGetCallerSP 1977 OpS390XLoweredGetCallerPC 1978 OpS390XLoweredNilCheck 1979 OpS390XLoweredRound32F 1980 OpS390XLoweredRound64F 1981 OpS390XLoweredWB 1982 OpS390XFlagEQ 1983 OpS390XFlagLT 1984 OpS390XFlagGT 1985 OpS390XMOVWZatomicload 1986 OpS390XMOVDatomicload 1987 OpS390XMOVWatomicstore 1988 OpS390XMOVDatomicstore 1989 OpS390XLAA 1990 OpS390XLAAG 1991 OpS390XAddTupleFirst32 1992 OpS390XAddTupleFirst64 1993 OpS390XLoweredAtomicCas32 1994 OpS390XLoweredAtomicCas64 1995 OpS390XLoweredAtomicExchange32 1996 OpS390XLoweredAtomicExchange64 1997 OpS390XFLOGR 1998 OpS390XPOPCNT 1999 OpS390XSumBytes2 2000 OpS390XSumBytes4 2001 OpS390XSumBytes8 2002 OpS390XSTMG2 2003 OpS390XSTMG3 2004 OpS390XSTMG4 2005 OpS390XSTM2 2006 OpS390XSTM3 2007 OpS390XSTM4 2008 OpS390XLoweredMove 2009 OpS390XLoweredZero 2010 2011 OpWasmLoweredStaticCall 2012 OpWasmLoweredClosureCall 2013 OpWasmLoweredInterCall 2014 OpWasmLoweredAddr 2015 OpWasmLoweredMove 2016 OpWasmLoweredZero 2017 OpWasmLoweredGetClosurePtr 2018 OpWasmLoweredGetCallerPC 2019 OpWasmLoweredGetCallerSP 2020 OpWasmLoweredNilCheck 2021 OpWasmLoweredWB 2022 OpWasmLoweredRound32F 2023 OpWasmLoweredConvert 2024 OpWasmSelect 2025 OpWasmI64Load8U 2026 OpWasmI64Load8S 2027 OpWasmI64Load16U 2028 OpWasmI64Load16S 2029 OpWasmI64Load32U 2030 OpWasmI64Load32S 2031 OpWasmI64Load 2032 OpWasmI64Store8 2033 OpWasmI64Store16 2034 OpWasmI64Store32 2035 OpWasmI64Store 2036 OpWasmF32Load 2037 OpWasmF64Load 2038 OpWasmF32Store 2039 OpWasmF64Store 2040 OpWasmI64Const 2041 OpWasmF64Const 2042 OpWasmI64Eqz 2043 OpWasmI64Eq 2044 OpWasmI64Ne 2045 OpWasmI64LtS 2046 OpWasmI64LtU 2047 OpWasmI64GtS 2048 OpWasmI64GtU 2049 OpWasmI64LeS 2050 OpWasmI64LeU 2051 OpWasmI64GeS 2052 OpWasmI64GeU 2053 OpWasmF64Eq 2054 OpWasmF64Ne 2055 OpWasmF64Lt 2056 OpWasmF64Gt 2057 OpWasmF64Le 2058 OpWasmF64Ge 2059 OpWasmI64Add 2060 OpWasmI64AddConst 2061 OpWasmI64Sub 2062 OpWasmI64Mul 2063 OpWasmI64DivS 2064 OpWasmI64DivU 2065 OpWasmI64RemS 2066 OpWasmI64RemU 2067 OpWasmI64And 2068 OpWasmI64Or 2069 OpWasmI64Xor 2070 OpWasmI64Shl 2071 OpWasmI64ShrS 2072 OpWasmI64ShrU 2073 OpWasmF64Neg 2074 OpWasmF64Add 2075 OpWasmF64Sub 2076 OpWasmF64Mul 2077 OpWasmF64Div 2078 OpWasmI64TruncSF64 2079 OpWasmI64TruncUF64 2080 OpWasmF64ConvertSI64 2081 OpWasmF64ConvertUI64 2082 2083 OpAdd8 2084 OpAdd16 2085 OpAdd32 2086 OpAdd64 2087 OpAddPtr 2088 OpAdd32F 2089 OpAdd64F 2090 OpSub8 2091 OpSub16 2092 OpSub32 2093 OpSub64 2094 OpSubPtr 2095 OpSub32F 2096 OpSub64F 2097 OpMul8 2098 OpMul16 2099 OpMul32 2100 OpMul64 2101 OpMul32F 2102 OpMul64F 2103 OpDiv32F 2104 OpDiv64F 2105 OpHmul32 2106 OpHmul32u 2107 OpHmul64 2108 OpHmul64u 2109 OpMul32uhilo 2110 OpMul64uhilo 2111 OpMul32uover 2112 OpMul64uover 2113 OpAvg32u 2114 OpAvg64u 2115 OpDiv8 2116 OpDiv8u 2117 OpDiv16 2118 OpDiv16u 2119 OpDiv32 2120 OpDiv32u 2121 OpDiv64 2122 OpDiv64u 2123 OpDiv128u 2124 OpMod8 2125 OpMod8u 2126 OpMod16 2127 OpMod16u 2128 OpMod32 2129 OpMod32u 2130 OpMod64 2131 OpMod64u 2132 OpAnd8 2133 OpAnd16 2134 OpAnd32 2135 OpAnd64 2136 OpOr8 2137 OpOr16 2138 OpOr32 2139 OpOr64 2140 OpXor8 2141 OpXor16 2142 OpXor32 2143 OpXor64 2144 OpLsh8x8 2145 OpLsh8x16 2146 OpLsh8x32 2147 OpLsh8x64 2148 OpLsh16x8 2149 OpLsh16x16 2150 OpLsh16x32 2151 OpLsh16x64 2152 OpLsh32x8 2153 OpLsh32x16 2154 OpLsh32x32 2155 OpLsh32x64 2156 OpLsh64x8 2157 OpLsh64x16 2158 OpLsh64x32 2159 OpLsh64x64 2160 OpRsh8x8 2161 OpRsh8x16 2162 OpRsh8x32 2163 OpRsh8x64 2164 OpRsh16x8 2165 OpRsh16x16 2166 OpRsh16x32 2167 OpRsh16x64 2168 OpRsh32x8 2169 OpRsh32x16 2170 OpRsh32x32 2171 OpRsh32x64 2172 OpRsh64x8 2173 OpRsh64x16 2174 OpRsh64x32 2175 OpRsh64x64 2176 OpRsh8Ux8 2177 OpRsh8Ux16 2178 OpRsh8Ux32 2179 OpRsh8Ux64 2180 OpRsh16Ux8 2181 OpRsh16Ux16 2182 OpRsh16Ux32 2183 OpRsh16Ux64 2184 OpRsh32Ux8 2185 OpRsh32Ux16 2186 OpRsh32Ux32 2187 OpRsh32Ux64 2188 OpRsh64Ux8 2189 OpRsh64Ux16 2190 OpRsh64Ux32 2191 OpRsh64Ux64 2192 OpEq8 2193 OpEq16 2194 OpEq32 2195 OpEq64 2196 OpEqPtr 2197 OpEqInter 2198 OpEqSlice 2199 OpEq32F 2200 OpEq64F 2201 OpNeq8 2202 OpNeq16 2203 OpNeq32 2204 OpNeq64 2205 OpNeqPtr 2206 OpNeqInter 2207 OpNeqSlice 2208 OpNeq32F 2209 OpNeq64F 2210 OpLess8 2211 OpLess8U 2212 OpLess16 2213 OpLess16U 2214 OpLess32 2215 OpLess32U 2216 OpLess64 2217 OpLess64U 2218 OpLess32F 2219 OpLess64F 2220 OpLeq8 2221 OpLeq8U 2222 OpLeq16 2223 OpLeq16U 2224 OpLeq32 2225 OpLeq32U 2226 OpLeq64 2227 OpLeq64U 2228 OpLeq32F 2229 OpLeq64F 2230 OpGreater8 2231 OpGreater8U 2232 OpGreater16 2233 OpGreater16U 2234 OpGreater32 2235 OpGreater32U 2236 OpGreater64 2237 OpGreater64U 2238 OpGreater32F 2239 OpGreater64F 2240 OpGeq8 2241 OpGeq8U 2242 OpGeq16 2243 OpGeq16U 2244 OpGeq32 2245 OpGeq32U 2246 OpGeq64 2247 OpGeq64U 2248 OpGeq32F 2249 OpGeq64F 2250 OpCondSelect 2251 OpAndB 2252 OpOrB 2253 OpEqB 2254 OpNeqB 2255 OpNot 2256 OpNeg8 2257 OpNeg16 2258 OpNeg32 2259 OpNeg64 2260 OpNeg32F 2261 OpNeg64F 2262 OpCom8 2263 OpCom16 2264 OpCom32 2265 OpCom64 2266 OpCtz8 2267 OpCtz16 2268 OpCtz32 2269 OpCtz64 2270 OpCtz8NonZero 2271 OpCtz16NonZero 2272 OpCtz32NonZero 2273 OpCtz64NonZero 2274 OpBitLen8 2275 OpBitLen16 2276 OpBitLen32 2277 OpBitLen64 2278 OpBswap32 2279 OpBswap64 2280 OpBitRev8 2281 OpBitRev16 2282 OpBitRev32 2283 OpBitRev64 2284 OpPopCount8 2285 OpPopCount16 2286 OpPopCount32 2287 OpPopCount64 2288 OpRotateLeft8 2289 OpRotateLeft16 2290 OpRotateLeft32 2291 OpRotateLeft64 2292 OpSqrt 2293 OpFloor 2294 OpCeil 2295 OpTrunc 2296 OpRound 2297 OpRoundToEven 2298 OpAbs 2299 OpCopysign 2300 OpPhi 2301 OpCopy 2302 OpConvert 2303 OpConstBool 2304 OpConstString 2305 OpConstNil 2306 OpConst8 2307 OpConst16 2308 OpConst32 2309 OpConst64 2310 OpConst32F 2311 OpConst64F 2312 OpConstInterface 2313 OpConstSlice 2314 OpInitMem 2315 OpArg 2316 OpAddr 2317 OpLocalAddr 2318 OpSP 2319 OpSB 2320 OpLoad 2321 OpStore 2322 OpMove 2323 OpZero 2324 OpStoreWB 2325 OpMoveWB 2326 OpZeroWB 2327 OpWB 2328 OpClosureCall 2329 OpStaticCall 2330 OpInterCall 2331 OpSignExt8to16 2332 OpSignExt8to32 2333 OpSignExt8to64 2334 OpSignExt16to32 2335 OpSignExt16to64 2336 OpSignExt32to64 2337 OpZeroExt8to16 2338 OpZeroExt8to32 2339 OpZeroExt8to64 2340 OpZeroExt16to32 2341 OpZeroExt16to64 2342 OpZeroExt32to64 2343 OpTrunc16to8 2344 OpTrunc32to8 2345 OpTrunc32to16 2346 OpTrunc64to8 2347 OpTrunc64to16 2348 OpTrunc64to32 2349 OpCvt32to32F 2350 OpCvt32to64F 2351 OpCvt64to32F 2352 OpCvt64to64F 2353 OpCvt32Fto32 2354 OpCvt32Fto64 2355 OpCvt64Fto32 2356 OpCvt64Fto64 2357 OpCvt32Fto64F 2358 OpCvt64Fto32F 2359 OpRound32F 2360 OpRound64F 2361 OpIsNonNil 2362 OpIsInBounds 2363 OpIsSliceInBounds 2364 OpNilCheck 2365 OpGetG 2366 OpGetClosurePtr 2367 OpGetCallerPC 2368 OpGetCallerSP 2369 OpPtrIndex 2370 OpOffPtr 2371 OpSliceMake 2372 OpSlicePtr 2373 OpSliceLen 2374 OpSliceCap 2375 OpComplexMake 2376 OpComplexReal 2377 OpComplexImag 2378 OpStringMake 2379 OpStringPtr 2380 OpStringLen 2381 OpIMake 2382 OpITab 2383 OpIData 2384 OpStructMake0 2385 OpStructMake1 2386 OpStructMake2 2387 OpStructMake3 2388 OpStructMake4 2389 OpStructSelect 2390 OpArrayMake0 2391 OpArrayMake1 2392 OpArraySelect 2393 OpStoreReg 2394 OpLoadReg 2395 OpFwdRef 2396 OpUnknown 2397 OpVarDef 2398 OpVarKill 2399 OpVarLive 2400 OpKeepAlive 2401 OpInlMark 2402 OpInt64Make 2403 OpInt64Hi 2404 OpInt64Lo 2405 OpAdd32carry 2406 OpAdd32withcarry 2407 OpSub32carry 2408 OpSub32withcarry 2409 OpAdd64carry 2410 OpSub64borrow 2411 OpSignmask 2412 OpZeromask 2413 OpSlicemask 2414 OpCvt32Uto32F 2415 OpCvt32Uto64F 2416 OpCvt32Fto32U 2417 OpCvt64Fto32U 2418 OpCvt64Uto32F 2419 OpCvt64Uto64F 2420 OpCvt32Fto64U 2421 OpCvt64Fto64U 2422 OpSelect0 2423 OpSelect1 2424 OpAtomicLoad32 2425 OpAtomicLoad64 2426 OpAtomicLoadPtr 2427 OpAtomicLoadAcq32 2428 OpAtomicStore32 2429 OpAtomicStore64 2430 OpAtomicStorePtrNoWB 2431 OpAtomicStoreRel32 2432 OpAtomicExchange32 2433 OpAtomicExchange64 2434 OpAtomicAdd32 2435 OpAtomicAdd64 2436 OpAtomicCompareAndSwap32 2437 OpAtomicCompareAndSwap64 2438 OpAtomicCompareAndSwapRel32 2439 OpAtomicAnd8 2440 OpAtomicOr8 2441 OpAtomicAdd32Variant 2442 OpAtomicAdd64Variant 2443 OpClobber 2444 ) 2445 2446 var opcodeTable = [...]opInfo{ 2447 {name: "OpInvalid"}, 2448 2449 { 2450 name: "ADDSS", 2451 argLen: 2, 2452 commutative: true, 2453 resultInArg0: true, 2454 usesScratch: true, 2455 asm: x86.AADDSS, 2456 reg: regInfo{ 2457 inputs: []inputInfo{ 2458 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2459 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2460 }, 2461 outputs: []outputInfo{ 2462 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2463 }, 2464 }, 2465 }, 2466 { 2467 name: "ADDSD", 2468 argLen: 2, 2469 commutative: true, 2470 resultInArg0: true, 2471 asm: x86.AADDSD, 2472 reg: regInfo{ 2473 inputs: []inputInfo{ 2474 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2475 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2476 }, 2477 outputs: []outputInfo{ 2478 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2479 }, 2480 }, 2481 }, 2482 { 2483 name: "SUBSS", 2484 argLen: 2, 2485 resultInArg0: true, 2486 usesScratch: true, 2487 asm: x86.ASUBSS, 2488 reg: regInfo{ 2489 inputs: []inputInfo{ 2490 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2491 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2492 }, 2493 outputs: []outputInfo{ 2494 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2495 }, 2496 }, 2497 }, 2498 { 2499 name: "SUBSD", 2500 argLen: 2, 2501 resultInArg0: true, 2502 asm: x86.ASUBSD, 2503 reg: regInfo{ 2504 inputs: []inputInfo{ 2505 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2506 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2507 }, 2508 outputs: []outputInfo{ 2509 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2510 }, 2511 }, 2512 }, 2513 { 2514 name: "MULSS", 2515 argLen: 2, 2516 commutative: true, 2517 resultInArg0: true, 2518 usesScratch: true, 2519 asm: x86.AMULSS, 2520 reg: regInfo{ 2521 inputs: []inputInfo{ 2522 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2523 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2524 }, 2525 outputs: []outputInfo{ 2526 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2527 }, 2528 }, 2529 }, 2530 { 2531 name: "MULSD", 2532 argLen: 2, 2533 commutative: true, 2534 resultInArg0: true, 2535 asm: x86.AMULSD, 2536 reg: regInfo{ 2537 inputs: []inputInfo{ 2538 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2539 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2540 }, 2541 outputs: []outputInfo{ 2542 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2543 }, 2544 }, 2545 }, 2546 { 2547 name: "DIVSS", 2548 argLen: 2, 2549 resultInArg0: true, 2550 usesScratch: true, 2551 asm: x86.ADIVSS, 2552 reg: regInfo{ 2553 inputs: []inputInfo{ 2554 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2555 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2556 }, 2557 outputs: []outputInfo{ 2558 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2559 }, 2560 }, 2561 }, 2562 { 2563 name: "DIVSD", 2564 argLen: 2, 2565 resultInArg0: true, 2566 asm: x86.ADIVSD, 2567 reg: regInfo{ 2568 inputs: []inputInfo{ 2569 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2570 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2571 }, 2572 outputs: []outputInfo{ 2573 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2574 }, 2575 }, 2576 }, 2577 { 2578 name: "MOVSSload", 2579 auxType: auxSymOff, 2580 argLen: 2, 2581 faultOnNilArg0: true, 2582 symEffect: SymRead, 2583 asm: x86.AMOVSS, 2584 reg: regInfo{ 2585 inputs: []inputInfo{ 2586 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2587 }, 2588 outputs: []outputInfo{ 2589 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2590 }, 2591 }, 2592 }, 2593 { 2594 name: "MOVSDload", 2595 auxType: auxSymOff, 2596 argLen: 2, 2597 faultOnNilArg0: true, 2598 symEffect: SymRead, 2599 asm: x86.AMOVSD, 2600 reg: regInfo{ 2601 inputs: []inputInfo{ 2602 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2603 }, 2604 outputs: []outputInfo{ 2605 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2606 }, 2607 }, 2608 }, 2609 { 2610 name: "MOVSSconst", 2611 auxType: auxFloat32, 2612 argLen: 0, 2613 rematerializeable: true, 2614 asm: x86.AMOVSS, 2615 reg: regInfo{ 2616 outputs: []outputInfo{ 2617 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2618 }, 2619 }, 2620 }, 2621 { 2622 name: "MOVSDconst", 2623 auxType: auxFloat64, 2624 argLen: 0, 2625 rematerializeable: true, 2626 asm: x86.AMOVSD, 2627 reg: regInfo{ 2628 outputs: []outputInfo{ 2629 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2630 }, 2631 }, 2632 }, 2633 { 2634 name: "MOVSSloadidx1", 2635 auxType: auxSymOff, 2636 argLen: 3, 2637 symEffect: SymRead, 2638 asm: x86.AMOVSS, 2639 reg: regInfo{ 2640 inputs: []inputInfo{ 2641 {1, 255}, // AX CX DX BX SP BP SI DI 2642 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2643 }, 2644 outputs: []outputInfo{ 2645 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2646 }, 2647 }, 2648 }, 2649 { 2650 name: "MOVSSloadidx4", 2651 auxType: auxSymOff, 2652 argLen: 3, 2653 symEffect: SymRead, 2654 asm: x86.AMOVSS, 2655 reg: regInfo{ 2656 inputs: []inputInfo{ 2657 {1, 255}, // AX CX DX BX SP BP SI DI 2658 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2659 }, 2660 outputs: []outputInfo{ 2661 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2662 }, 2663 }, 2664 }, 2665 { 2666 name: "MOVSDloadidx1", 2667 auxType: auxSymOff, 2668 argLen: 3, 2669 symEffect: SymRead, 2670 asm: x86.AMOVSD, 2671 reg: regInfo{ 2672 inputs: []inputInfo{ 2673 {1, 255}, // AX CX DX BX SP BP SI DI 2674 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2675 }, 2676 outputs: []outputInfo{ 2677 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2678 }, 2679 }, 2680 }, 2681 { 2682 name: "MOVSDloadidx8", 2683 auxType: auxSymOff, 2684 argLen: 3, 2685 symEffect: SymRead, 2686 asm: x86.AMOVSD, 2687 reg: regInfo{ 2688 inputs: []inputInfo{ 2689 {1, 255}, // AX CX DX BX SP BP SI DI 2690 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2691 }, 2692 outputs: []outputInfo{ 2693 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2694 }, 2695 }, 2696 }, 2697 { 2698 name: "MOVSSstore", 2699 auxType: auxSymOff, 2700 argLen: 3, 2701 faultOnNilArg0: true, 2702 symEffect: SymWrite, 2703 asm: x86.AMOVSS, 2704 reg: regInfo{ 2705 inputs: []inputInfo{ 2706 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2707 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2708 }, 2709 }, 2710 }, 2711 { 2712 name: "MOVSDstore", 2713 auxType: auxSymOff, 2714 argLen: 3, 2715 faultOnNilArg0: true, 2716 symEffect: SymWrite, 2717 asm: x86.AMOVSD, 2718 reg: regInfo{ 2719 inputs: []inputInfo{ 2720 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2721 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2722 }, 2723 }, 2724 }, 2725 { 2726 name: "MOVSSstoreidx1", 2727 auxType: auxSymOff, 2728 argLen: 4, 2729 symEffect: SymWrite, 2730 asm: x86.AMOVSS, 2731 reg: regInfo{ 2732 inputs: []inputInfo{ 2733 {1, 255}, // AX CX DX BX SP BP SI DI 2734 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2735 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2736 }, 2737 }, 2738 }, 2739 { 2740 name: "MOVSSstoreidx4", 2741 auxType: auxSymOff, 2742 argLen: 4, 2743 symEffect: SymWrite, 2744 asm: x86.AMOVSS, 2745 reg: regInfo{ 2746 inputs: []inputInfo{ 2747 {1, 255}, // AX CX DX BX SP BP SI DI 2748 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2749 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2750 }, 2751 }, 2752 }, 2753 { 2754 name: "MOVSDstoreidx1", 2755 auxType: auxSymOff, 2756 argLen: 4, 2757 symEffect: SymWrite, 2758 asm: x86.AMOVSD, 2759 reg: regInfo{ 2760 inputs: []inputInfo{ 2761 {1, 255}, // AX CX DX BX SP BP SI DI 2762 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2763 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2764 }, 2765 }, 2766 }, 2767 { 2768 name: "MOVSDstoreidx8", 2769 auxType: auxSymOff, 2770 argLen: 4, 2771 symEffect: SymWrite, 2772 asm: x86.AMOVSD, 2773 reg: regInfo{ 2774 inputs: []inputInfo{ 2775 {1, 255}, // AX CX DX BX SP BP SI DI 2776 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2777 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2778 }, 2779 }, 2780 }, 2781 { 2782 name: "ADDSSload", 2783 auxType: auxSymOff, 2784 argLen: 3, 2785 resultInArg0: true, 2786 faultOnNilArg1: true, 2787 symEffect: SymRead, 2788 asm: x86.AADDSS, 2789 reg: regInfo{ 2790 inputs: []inputInfo{ 2791 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2792 {1, 65791}, // AX CX DX BX SP BP SI DI SB 2793 }, 2794 outputs: []outputInfo{ 2795 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2796 }, 2797 }, 2798 }, 2799 { 2800 name: "ADDSDload", 2801 auxType: auxSymOff, 2802 argLen: 3, 2803 resultInArg0: true, 2804 faultOnNilArg1: true, 2805 symEffect: SymRead, 2806 asm: x86.AADDSD, 2807 reg: regInfo{ 2808 inputs: []inputInfo{ 2809 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2810 {1, 65791}, // AX CX DX BX SP BP SI DI SB 2811 }, 2812 outputs: []outputInfo{ 2813 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2814 }, 2815 }, 2816 }, 2817 { 2818 name: "SUBSSload", 2819 auxType: auxSymOff, 2820 argLen: 3, 2821 resultInArg0: true, 2822 faultOnNilArg1: true, 2823 symEffect: SymRead, 2824 asm: x86.ASUBSS, 2825 reg: regInfo{ 2826 inputs: []inputInfo{ 2827 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2828 {1, 65791}, // AX CX DX BX SP BP SI DI SB 2829 }, 2830 outputs: []outputInfo{ 2831 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2832 }, 2833 }, 2834 }, 2835 { 2836 name: "SUBSDload", 2837 auxType: auxSymOff, 2838 argLen: 3, 2839 resultInArg0: true, 2840 faultOnNilArg1: true, 2841 symEffect: SymRead, 2842 asm: x86.ASUBSD, 2843 reg: regInfo{ 2844 inputs: []inputInfo{ 2845 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2846 {1, 65791}, // AX CX DX BX SP BP SI DI SB 2847 }, 2848 outputs: []outputInfo{ 2849 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2850 }, 2851 }, 2852 }, 2853 { 2854 name: "MULSSload", 2855 auxType: auxSymOff, 2856 argLen: 3, 2857 resultInArg0: true, 2858 faultOnNilArg1: true, 2859 symEffect: SymRead, 2860 asm: x86.AMULSS, 2861 reg: regInfo{ 2862 inputs: []inputInfo{ 2863 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2864 {1, 65791}, // AX CX DX BX SP BP SI DI SB 2865 }, 2866 outputs: []outputInfo{ 2867 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2868 }, 2869 }, 2870 }, 2871 { 2872 name: "MULSDload", 2873 auxType: auxSymOff, 2874 argLen: 3, 2875 resultInArg0: true, 2876 faultOnNilArg1: true, 2877 symEffect: SymRead, 2878 asm: x86.AMULSD, 2879 reg: regInfo{ 2880 inputs: []inputInfo{ 2881 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2882 {1, 65791}, // AX CX DX BX SP BP SI DI SB 2883 }, 2884 outputs: []outputInfo{ 2885 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2886 }, 2887 }, 2888 }, 2889 { 2890 name: "DIVSSload", 2891 auxType: auxSymOff, 2892 argLen: 3, 2893 resultInArg0: true, 2894 faultOnNilArg1: true, 2895 symEffect: SymRead, 2896 asm: x86.ADIVSS, 2897 reg: regInfo{ 2898 inputs: []inputInfo{ 2899 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2900 {1, 65791}, // AX CX DX BX SP BP SI DI SB 2901 }, 2902 outputs: []outputInfo{ 2903 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2904 }, 2905 }, 2906 }, 2907 { 2908 name: "DIVSDload", 2909 auxType: auxSymOff, 2910 argLen: 3, 2911 resultInArg0: true, 2912 faultOnNilArg1: true, 2913 symEffect: SymRead, 2914 asm: x86.ADIVSD, 2915 reg: regInfo{ 2916 inputs: []inputInfo{ 2917 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2918 {1, 65791}, // AX CX DX BX SP BP SI DI SB 2919 }, 2920 outputs: []outputInfo{ 2921 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2922 }, 2923 }, 2924 }, 2925 { 2926 name: "ADDL", 2927 argLen: 2, 2928 commutative: true, 2929 clobberFlags: true, 2930 asm: x86.AADDL, 2931 reg: regInfo{ 2932 inputs: []inputInfo{ 2933 {1, 239}, // AX CX DX BX BP SI DI 2934 {0, 255}, // AX CX DX BX SP BP SI DI 2935 }, 2936 outputs: []outputInfo{ 2937 {0, 239}, // AX CX DX BX BP SI DI 2938 }, 2939 }, 2940 }, 2941 { 2942 name: "ADDLconst", 2943 auxType: auxInt32, 2944 argLen: 1, 2945 clobberFlags: true, 2946 asm: x86.AADDL, 2947 reg: regInfo{ 2948 inputs: []inputInfo{ 2949 {0, 255}, // AX CX DX BX SP BP SI DI 2950 }, 2951 outputs: []outputInfo{ 2952 {0, 239}, // AX CX DX BX BP SI DI 2953 }, 2954 }, 2955 }, 2956 { 2957 name: "ADDLcarry", 2958 argLen: 2, 2959 commutative: true, 2960 resultInArg0: true, 2961 asm: x86.AADDL, 2962 reg: regInfo{ 2963 inputs: []inputInfo{ 2964 {0, 239}, // AX CX DX BX BP SI DI 2965 {1, 239}, // AX CX DX BX BP SI DI 2966 }, 2967 outputs: []outputInfo{ 2968 {1, 0}, 2969 {0, 239}, // AX CX DX BX BP SI DI 2970 }, 2971 }, 2972 }, 2973 { 2974 name: "ADDLconstcarry", 2975 auxType: auxInt32, 2976 argLen: 1, 2977 resultInArg0: true, 2978 asm: x86.AADDL, 2979 reg: regInfo{ 2980 inputs: []inputInfo{ 2981 {0, 239}, // AX CX DX BX BP SI DI 2982 }, 2983 outputs: []outputInfo{ 2984 {1, 0}, 2985 {0, 239}, // AX CX DX BX BP SI DI 2986 }, 2987 }, 2988 }, 2989 { 2990 name: "ADCL", 2991 argLen: 3, 2992 commutative: true, 2993 resultInArg0: true, 2994 clobberFlags: true, 2995 asm: x86.AADCL, 2996 reg: regInfo{ 2997 inputs: []inputInfo{ 2998 {0, 239}, // AX CX DX BX BP SI DI 2999 {1, 239}, // AX CX DX BX BP SI DI 3000 }, 3001 outputs: []outputInfo{ 3002 {0, 239}, // AX CX DX BX BP SI DI 3003 }, 3004 }, 3005 }, 3006 { 3007 name: "ADCLconst", 3008 auxType: auxInt32, 3009 argLen: 2, 3010 resultInArg0: true, 3011 clobberFlags: true, 3012 asm: x86.AADCL, 3013 reg: regInfo{ 3014 inputs: []inputInfo{ 3015 {0, 239}, // AX CX DX BX BP SI DI 3016 }, 3017 outputs: []outputInfo{ 3018 {0, 239}, // AX CX DX BX BP SI DI 3019 }, 3020 }, 3021 }, 3022 { 3023 name: "SUBL", 3024 argLen: 2, 3025 resultInArg0: true, 3026 clobberFlags: true, 3027 asm: x86.ASUBL, 3028 reg: regInfo{ 3029 inputs: []inputInfo{ 3030 {0, 239}, // AX CX DX BX BP SI DI 3031 {1, 239}, // AX CX DX BX BP SI DI 3032 }, 3033 outputs: []outputInfo{ 3034 {0, 239}, // AX CX DX BX BP SI DI 3035 }, 3036 }, 3037 }, 3038 { 3039 name: "SUBLconst", 3040 auxType: auxInt32, 3041 argLen: 1, 3042 resultInArg0: true, 3043 clobberFlags: true, 3044 asm: x86.ASUBL, 3045 reg: regInfo{ 3046 inputs: []inputInfo{ 3047 {0, 239}, // AX CX DX BX BP SI DI 3048 }, 3049 outputs: []outputInfo{ 3050 {0, 239}, // AX CX DX BX BP SI DI 3051 }, 3052 }, 3053 }, 3054 { 3055 name: "SUBLcarry", 3056 argLen: 2, 3057 resultInArg0: true, 3058 asm: x86.ASUBL, 3059 reg: regInfo{ 3060 inputs: []inputInfo{ 3061 {0, 239}, // AX CX DX BX BP SI DI 3062 {1, 239}, // AX CX DX BX BP SI DI 3063 }, 3064 outputs: []outputInfo{ 3065 {1, 0}, 3066 {0, 239}, // AX CX DX BX BP SI DI 3067 }, 3068 }, 3069 }, 3070 { 3071 name: "SUBLconstcarry", 3072 auxType: auxInt32, 3073 argLen: 1, 3074 resultInArg0: true, 3075 asm: x86.ASUBL, 3076 reg: regInfo{ 3077 inputs: []inputInfo{ 3078 {0, 239}, // AX CX DX BX BP SI DI 3079 }, 3080 outputs: []outputInfo{ 3081 {1, 0}, 3082 {0, 239}, // AX CX DX BX BP SI DI 3083 }, 3084 }, 3085 }, 3086 { 3087 name: "SBBL", 3088 argLen: 3, 3089 resultInArg0: true, 3090 clobberFlags: true, 3091 asm: x86.ASBBL, 3092 reg: regInfo{ 3093 inputs: []inputInfo{ 3094 {0, 239}, // AX CX DX BX BP SI DI 3095 {1, 239}, // AX CX DX BX BP SI DI 3096 }, 3097 outputs: []outputInfo{ 3098 {0, 239}, // AX CX DX BX BP SI DI 3099 }, 3100 }, 3101 }, 3102 { 3103 name: "SBBLconst", 3104 auxType: auxInt32, 3105 argLen: 2, 3106 resultInArg0: true, 3107 clobberFlags: true, 3108 asm: x86.ASBBL, 3109 reg: regInfo{ 3110 inputs: []inputInfo{ 3111 {0, 239}, // AX CX DX BX BP SI DI 3112 }, 3113 outputs: []outputInfo{ 3114 {0, 239}, // AX CX DX BX BP SI DI 3115 }, 3116 }, 3117 }, 3118 { 3119 name: "MULL", 3120 argLen: 2, 3121 commutative: true, 3122 resultInArg0: true, 3123 clobberFlags: true, 3124 asm: x86.AIMULL, 3125 reg: regInfo{ 3126 inputs: []inputInfo{ 3127 {0, 239}, // AX CX DX BX BP SI DI 3128 {1, 239}, // AX CX DX BX BP SI DI 3129 }, 3130 outputs: []outputInfo{ 3131 {0, 239}, // AX CX DX BX BP SI DI 3132 }, 3133 }, 3134 }, 3135 { 3136 name: "MULLconst", 3137 auxType: auxInt32, 3138 argLen: 1, 3139 clobberFlags: true, 3140 asm: x86.AIMUL3L, 3141 reg: regInfo{ 3142 inputs: []inputInfo{ 3143 {0, 239}, // AX CX DX BX BP SI DI 3144 }, 3145 outputs: []outputInfo{ 3146 {0, 239}, // AX CX DX BX BP SI DI 3147 }, 3148 }, 3149 }, 3150 { 3151 name: "MULLU", 3152 argLen: 2, 3153 commutative: true, 3154 clobberFlags: true, 3155 asm: x86.AMULL, 3156 reg: regInfo{ 3157 inputs: []inputInfo{ 3158 {0, 1}, // AX 3159 {1, 255}, // AX CX DX BX SP BP SI DI 3160 }, 3161 clobbers: 4, // DX 3162 outputs: []outputInfo{ 3163 {1, 0}, 3164 {0, 1}, // AX 3165 }, 3166 }, 3167 }, 3168 { 3169 name: "HMULL", 3170 argLen: 2, 3171 commutative: true, 3172 clobberFlags: true, 3173 asm: x86.AIMULL, 3174 reg: regInfo{ 3175 inputs: []inputInfo{ 3176 {0, 1}, // AX 3177 {1, 255}, // AX CX DX BX SP BP SI DI 3178 }, 3179 clobbers: 1, // AX 3180 outputs: []outputInfo{ 3181 {0, 4}, // DX 3182 }, 3183 }, 3184 }, 3185 { 3186 name: "HMULLU", 3187 argLen: 2, 3188 commutative: true, 3189 clobberFlags: true, 3190 asm: x86.AMULL, 3191 reg: regInfo{ 3192 inputs: []inputInfo{ 3193 {0, 1}, // AX 3194 {1, 255}, // AX CX DX BX SP BP SI DI 3195 }, 3196 clobbers: 1, // AX 3197 outputs: []outputInfo{ 3198 {0, 4}, // DX 3199 }, 3200 }, 3201 }, 3202 { 3203 name: "MULLQU", 3204 argLen: 2, 3205 commutative: true, 3206 clobberFlags: true, 3207 asm: x86.AMULL, 3208 reg: regInfo{ 3209 inputs: []inputInfo{ 3210 {0, 1}, // AX 3211 {1, 255}, // AX CX DX BX SP BP SI DI 3212 }, 3213 outputs: []outputInfo{ 3214 {0, 4}, // DX 3215 {1, 1}, // AX 3216 }, 3217 }, 3218 }, 3219 { 3220 name: "AVGLU", 3221 argLen: 2, 3222 commutative: true, 3223 resultInArg0: true, 3224 clobberFlags: true, 3225 reg: regInfo{ 3226 inputs: []inputInfo{ 3227 {0, 239}, // AX CX DX BX BP SI DI 3228 {1, 239}, // AX CX DX BX BP SI DI 3229 }, 3230 outputs: []outputInfo{ 3231 {0, 239}, // AX CX DX BX BP SI DI 3232 }, 3233 }, 3234 }, 3235 { 3236 name: "DIVL", 3237 auxType: auxBool, 3238 argLen: 2, 3239 clobberFlags: true, 3240 asm: x86.AIDIVL, 3241 reg: regInfo{ 3242 inputs: []inputInfo{ 3243 {0, 1}, // AX 3244 {1, 251}, // AX CX BX SP BP SI DI 3245 }, 3246 clobbers: 4, // DX 3247 outputs: []outputInfo{ 3248 {0, 1}, // AX 3249 }, 3250 }, 3251 }, 3252 { 3253 name: "DIVW", 3254 auxType: auxBool, 3255 argLen: 2, 3256 clobberFlags: true, 3257 asm: x86.AIDIVW, 3258 reg: regInfo{ 3259 inputs: []inputInfo{ 3260 {0, 1}, // AX 3261 {1, 251}, // AX CX BX SP BP SI DI 3262 }, 3263 clobbers: 4, // DX 3264 outputs: []outputInfo{ 3265 {0, 1}, // AX 3266 }, 3267 }, 3268 }, 3269 { 3270 name: "DIVLU", 3271 argLen: 2, 3272 clobberFlags: true, 3273 asm: x86.ADIVL, 3274 reg: regInfo{ 3275 inputs: []inputInfo{ 3276 {0, 1}, // AX 3277 {1, 251}, // AX CX BX SP BP SI DI 3278 }, 3279 clobbers: 4, // DX 3280 outputs: []outputInfo{ 3281 {0, 1}, // AX 3282 }, 3283 }, 3284 }, 3285 { 3286 name: "DIVWU", 3287 argLen: 2, 3288 clobberFlags: true, 3289 asm: x86.ADIVW, 3290 reg: regInfo{ 3291 inputs: []inputInfo{ 3292 {0, 1}, // AX 3293 {1, 251}, // AX CX BX SP BP SI DI 3294 }, 3295 clobbers: 4, // DX 3296 outputs: []outputInfo{ 3297 {0, 1}, // AX 3298 }, 3299 }, 3300 }, 3301 { 3302 name: "MODL", 3303 auxType: auxBool, 3304 argLen: 2, 3305 clobberFlags: true, 3306 asm: x86.AIDIVL, 3307 reg: regInfo{ 3308 inputs: []inputInfo{ 3309 {0, 1}, // AX 3310 {1, 251}, // AX CX BX SP BP SI DI 3311 }, 3312 clobbers: 1, // AX 3313 outputs: []outputInfo{ 3314 {0, 4}, // DX 3315 }, 3316 }, 3317 }, 3318 { 3319 name: "MODW", 3320 auxType: auxBool, 3321 argLen: 2, 3322 clobberFlags: true, 3323 asm: x86.AIDIVW, 3324 reg: regInfo{ 3325 inputs: []inputInfo{ 3326 {0, 1}, // AX 3327 {1, 251}, // AX CX BX SP BP SI DI 3328 }, 3329 clobbers: 1, // AX 3330 outputs: []outputInfo{ 3331 {0, 4}, // DX 3332 }, 3333 }, 3334 }, 3335 { 3336 name: "MODLU", 3337 argLen: 2, 3338 clobberFlags: true, 3339 asm: x86.ADIVL, 3340 reg: regInfo{ 3341 inputs: []inputInfo{ 3342 {0, 1}, // AX 3343 {1, 251}, // AX CX BX SP BP SI DI 3344 }, 3345 clobbers: 1, // AX 3346 outputs: []outputInfo{ 3347 {0, 4}, // DX 3348 }, 3349 }, 3350 }, 3351 { 3352 name: "MODWU", 3353 argLen: 2, 3354 clobberFlags: true, 3355 asm: x86.ADIVW, 3356 reg: regInfo{ 3357 inputs: []inputInfo{ 3358 {0, 1}, // AX 3359 {1, 251}, // AX CX BX SP BP SI DI 3360 }, 3361 clobbers: 1, // AX 3362 outputs: []outputInfo{ 3363 {0, 4}, // DX 3364 }, 3365 }, 3366 }, 3367 { 3368 name: "ANDL", 3369 argLen: 2, 3370 commutative: true, 3371 resultInArg0: true, 3372 clobberFlags: true, 3373 asm: x86.AANDL, 3374 reg: regInfo{ 3375 inputs: []inputInfo{ 3376 {0, 239}, // AX CX DX BX BP SI DI 3377 {1, 239}, // AX CX DX BX BP SI DI 3378 }, 3379 outputs: []outputInfo{ 3380 {0, 239}, // AX CX DX BX BP SI DI 3381 }, 3382 }, 3383 }, 3384 { 3385 name: "ANDLconst", 3386 auxType: auxInt32, 3387 argLen: 1, 3388 resultInArg0: true, 3389 clobberFlags: true, 3390 asm: x86.AANDL, 3391 reg: regInfo{ 3392 inputs: []inputInfo{ 3393 {0, 239}, // AX CX DX BX BP SI DI 3394 }, 3395 outputs: []outputInfo{ 3396 {0, 239}, // AX CX DX BX BP SI DI 3397 }, 3398 }, 3399 }, 3400 { 3401 name: "ORL", 3402 argLen: 2, 3403 commutative: true, 3404 resultInArg0: true, 3405 clobberFlags: true, 3406 asm: x86.AORL, 3407 reg: regInfo{ 3408 inputs: []inputInfo{ 3409 {0, 239}, // AX CX DX BX BP SI DI 3410 {1, 239}, // AX CX DX BX BP SI DI 3411 }, 3412 outputs: []outputInfo{ 3413 {0, 239}, // AX CX DX BX BP SI DI 3414 }, 3415 }, 3416 }, 3417 { 3418 name: "ORLconst", 3419 auxType: auxInt32, 3420 argLen: 1, 3421 resultInArg0: true, 3422 clobberFlags: true, 3423 asm: x86.AORL, 3424 reg: regInfo{ 3425 inputs: []inputInfo{ 3426 {0, 239}, // AX CX DX BX BP SI DI 3427 }, 3428 outputs: []outputInfo{ 3429 {0, 239}, // AX CX DX BX BP SI DI 3430 }, 3431 }, 3432 }, 3433 { 3434 name: "XORL", 3435 argLen: 2, 3436 commutative: true, 3437 resultInArg0: true, 3438 clobberFlags: true, 3439 asm: x86.AXORL, 3440 reg: regInfo{ 3441 inputs: []inputInfo{ 3442 {0, 239}, // AX CX DX BX BP SI DI 3443 {1, 239}, // AX CX DX BX BP SI DI 3444 }, 3445 outputs: []outputInfo{ 3446 {0, 239}, // AX CX DX BX BP SI DI 3447 }, 3448 }, 3449 }, 3450 { 3451 name: "XORLconst", 3452 auxType: auxInt32, 3453 argLen: 1, 3454 resultInArg0: true, 3455 clobberFlags: true, 3456 asm: x86.AXORL, 3457 reg: regInfo{ 3458 inputs: []inputInfo{ 3459 {0, 239}, // AX CX DX BX BP SI DI 3460 }, 3461 outputs: []outputInfo{ 3462 {0, 239}, // AX CX DX BX BP SI DI 3463 }, 3464 }, 3465 }, 3466 { 3467 name: "CMPL", 3468 argLen: 2, 3469 asm: x86.ACMPL, 3470 reg: regInfo{ 3471 inputs: []inputInfo{ 3472 {0, 255}, // AX CX DX BX SP BP SI DI 3473 {1, 255}, // AX CX DX BX SP BP SI DI 3474 }, 3475 }, 3476 }, 3477 { 3478 name: "CMPW", 3479 argLen: 2, 3480 asm: x86.ACMPW, 3481 reg: regInfo{ 3482 inputs: []inputInfo{ 3483 {0, 255}, // AX CX DX BX SP BP SI DI 3484 {1, 255}, // AX CX DX BX SP BP SI DI 3485 }, 3486 }, 3487 }, 3488 { 3489 name: "CMPB", 3490 argLen: 2, 3491 asm: x86.ACMPB, 3492 reg: regInfo{ 3493 inputs: []inputInfo{ 3494 {0, 255}, // AX CX DX BX SP BP SI DI 3495 {1, 255}, // AX CX DX BX SP BP SI DI 3496 }, 3497 }, 3498 }, 3499 { 3500 name: "CMPLconst", 3501 auxType: auxInt32, 3502 argLen: 1, 3503 asm: x86.ACMPL, 3504 reg: regInfo{ 3505 inputs: []inputInfo{ 3506 {0, 255}, // AX CX DX BX SP BP SI DI 3507 }, 3508 }, 3509 }, 3510 { 3511 name: "CMPWconst", 3512 auxType: auxInt16, 3513 argLen: 1, 3514 asm: x86.ACMPW, 3515 reg: regInfo{ 3516 inputs: []inputInfo{ 3517 {0, 255}, // AX CX DX BX SP BP SI DI 3518 }, 3519 }, 3520 }, 3521 { 3522 name: "CMPBconst", 3523 auxType: auxInt8, 3524 argLen: 1, 3525 asm: x86.ACMPB, 3526 reg: regInfo{ 3527 inputs: []inputInfo{ 3528 {0, 255}, // AX CX DX BX SP BP SI DI 3529 }, 3530 }, 3531 }, 3532 { 3533 name: "CMPLload", 3534 auxType: auxSymOff, 3535 argLen: 3, 3536 faultOnNilArg0: true, 3537 symEffect: SymRead, 3538 asm: x86.ACMPL, 3539 reg: regInfo{ 3540 inputs: []inputInfo{ 3541 {1, 255}, // AX CX DX BX SP BP SI DI 3542 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3543 }, 3544 }, 3545 }, 3546 { 3547 name: "CMPWload", 3548 auxType: auxSymOff, 3549 argLen: 3, 3550 faultOnNilArg0: true, 3551 symEffect: SymRead, 3552 asm: x86.ACMPW, 3553 reg: regInfo{ 3554 inputs: []inputInfo{ 3555 {1, 255}, // AX CX DX BX SP BP SI DI 3556 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3557 }, 3558 }, 3559 }, 3560 { 3561 name: "CMPBload", 3562 auxType: auxSymOff, 3563 argLen: 3, 3564 faultOnNilArg0: true, 3565 symEffect: SymRead, 3566 asm: x86.ACMPB, 3567 reg: regInfo{ 3568 inputs: []inputInfo{ 3569 {1, 255}, // AX CX DX BX SP BP SI DI 3570 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3571 }, 3572 }, 3573 }, 3574 { 3575 name: "CMPLconstload", 3576 auxType: auxSymValAndOff, 3577 argLen: 2, 3578 faultOnNilArg0: true, 3579 symEffect: SymRead, 3580 asm: x86.ACMPL, 3581 reg: regInfo{ 3582 inputs: []inputInfo{ 3583 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3584 }, 3585 }, 3586 }, 3587 { 3588 name: "CMPWconstload", 3589 auxType: auxSymValAndOff, 3590 argLen: 2, 3591 faultOnNilArg0: true, 3592 symEffect: SymRead, 3593 asm: x86.ACMPW, 3594 reg: regInfo{ 3595 inputs: []inputInfo{ 3596 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3597 }, 3598 }, 3599 }, 3600 { 3601 name: "CMPBconstload", 3602 auxType: auxSymValAndOff, 3603 argLen: 2, 3604 faultOnNilArg0: true, 3605 symEffect: SymRead, 3606 asm: x86.ACMPB, 3607 reg: regInfo{ 3608 inputs: []inputInfo{ 3609 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3610 }, 3611 }, 3612 }, 3613 { 3614 name: "UCOMISS", 3615 argLen: 2, 3616 usesScratch: true, 3617 asm: x86.AUCOMISS, 3618 reg: regInfo{ 3619 inputs: []inputInfo{ 3620 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3621 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3622 }, 3623 }, 3624 }, 3625 { 3626 name: "UCOMISD", 3627 argLen: 2, 3628 usesScratch: true, 3629 asm: x86.AUCOMISD, 3630 reg: regInfo{ 3631 inputs: []inputInfo{ 3632 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3633 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3634 }, 3635 }, 3636 }, 3637 { 3638 name: "TESTL", 3639 argLen: 2, 3640 commutative: true, 3641 asm: x86.ATESTL, 3642 reg: regInfo{ 3643 inputs: []inputInfo{ 3644 {0, 255}, // AX CX DX BX SP BP SI DI 3645 {1, 255}, // AX CX DX BX SP BP SI DI 3646 }, 3647 }, 3648 }, 3649 { 3650 name: "TESTW", 3651 argLen: 2, 3652 commutative: true, 3653 asm: x86.ATESTW, 3654 reg: regInfo{ 3655 inputs: []inputInfo{ 3656 {0, 255}, // AX CX DX BX SP BP SI DI 3657 {1, 255}, // AX CX DX BX SP BP SI DI 3658 }, 3659 }, 3660 }, 3661 { 3662 name: "TESTB", 3663 argLen: 2, 3664 commutative: true, 3665 asm: x86.ATESTB, 3666 reg: regInfo{ 3667 inputs: []inputInfo{ 3668 {0, 255}, // AX CX DX BX SP BP SI DI 3669 {1, 255}, // AX CX DX BX SP BP SI DI 3670 }, 3671 }, 3672 }, 3673 { 3674 name: "TESTLconst", 3675 auxType: auxInt32, 3676 argLen: 1, 3677 asm: x86.ATESTL, 3678 reg: regInfo{ 3679 inputs: []inputInfo{ 3680 {0, 255}, // AX CX DX BX SP BP SI DI 3681 }, 3682 }, 3683 }, 3684 { 3685 name: "TESTWconst", 3686 auxType: auxInt16, 3687 argLen: 1, 3688 asm: x86.ATESTW, 3689 reg: regInfo{ 3690 inputs: []inputInfo{ 3691 {0, 255}, // AX CX DX BX SP BP SI DI 3692 }, 3693 }, 3694 }, 3695 { 3696 name: "TESTBconst", 3697 auxType: auxInt8, 3698 argLen: 1, 3699 asm: x86.ATESTB, 3700 reg: regInfo{ 3701 inputs: []inputInfo{ 3702 {0, 255}, // AX CX DX BX SP BP SI DI 3703 }, 3704 }, 3705 }, 3706 { 3707 name: "SHLL", 3708 argLen: 2, 3709 resultInArg0: true, 3710 clobberFlags: true, 3711 asm: x86.ASHLL, 3712 reg: regInfo{ 3713 inputs: []inputInfo{ 3714 {1, 2}, // CX 3715 {0, 239}, // AX CX DX BX BP SI DI 3716 }, 3717 outputs: []outputInfo{ 3718 {0, 239}, // AX CX DX BX BP SI DI 3719 }, 3720 }, 3721 }, 3722 { 3723 name: "SHLLconst", 3724 auxType: auxInt32, 3725 argLen: 1, 3726 resultInArg0: true, 3727 clobberFlags: true, 3728 asm: x86.ASHLL, 3729 reg: regInfo{ 3730 inputs: []inputInfo{ 3731 {0, 239}, // AX CX DX BX BP SI DI 3732 }, 3733 outputs: []outputInfo{ 3734 {0, 239}, // AX CX DX BX BP SI DI 3735 }, 3736 }, 3737 }, 3738 { 3739 name: "SHRL", 3740 argLen: 2, 3741 resultInArg0: true, 3742 clobberFlags: true, 3743 asm: x86.ASHRL, 3744 reg: regInfo{ 3745 inputs: []inputInfo{ 3746 {1, 2}, // CX 3747 {0, 239}, // AX CX DX BX BP SI DI 3748 }, 3749 outputs: []outputInfo{ 3750 {0, 239}, // AX CX DX BX BP SI DI 3751 }, 3752 }, 3753 }, 3754 { 3755 name: "SHRW", 3756 argLen: 2, 3757 resultInArg0: true, 3758 clobberFlags: true, 3759 asm: x86.ASHRW, 3760 reg: regInfo{ 3761 inputs: []inputInfo{ 3762 {1, 2}, // CX 3763 {0, 239}, // AX CX DX BX BP SI DI 3764 }, 3765 outputs: []outputInfo{ 3766 {0, 239}, // AX CX DX BX BP SI DI 3767 }, 3768 }, 3769 }, 3770 { 3771 name: "SHRB", 3772 argLen: 2, 3773 resultInArg0: true, 3774 clobberFlags: true, 3775 asm: x86.ASHRB, 3776 reg: regInfo{ 3777 inputs: []inputInfo{ 3778 {1, 2}, // CX 3779 {0, 239}, // AX CX DX BX BP SI DI 3780 }, 3781 outputs: []outputInfo{ 3782 {0, 239}, // AX CX DX BX BP SI DI 3783 }, 3784 }, 3785 }, 3786 { 3787 name: "SHRLconst", 3788 auxType: auxInt32, 3789 argLen: 1, 3790 resultInArg0: true, 3791 clobberFlags: true, 3792 asm: x86.ASHRL, 3793 reg: regInfo{ 3794 inputs: []inputInfo{ 3795 {0, 239}, // AX CX DX BX BP SI DI 3796 }, 3797 outputs: []outputInfo{ 3798 {0, 239}, // AX CX DX BX BP SI DI 3799 }, 3800 }, 3801 }, 3802 { 3803 name: "SHRWconst", 3804 auxType: auxInt16, 3805 argLen: 1, 3806 resultInArg0: true, 3807 clobberFlags: true, 3808 asm: x86.ASHRW, 3809 reg: regInfo{ 3810 inputs: []inputInfo{ 3811 {0, 239}, // AX CX DX BX BP SI DI 3812 }, 3813 outputs: []outputInfo{ 3814 {0, 239}, // AX CX DX BX BP SI DI 3815 }, 3816 }, 3817 }, 3818 { 3819 name: "SHRBconst", 3820 auxType: auxInt8, 3821 argLen: 1, 3822 resultInArg0: true, 3823 clobberFlags: true, 3824 asm: x86.ASHRB, 3825 reg: regInfo{ 3826 inputs: []inputInfo{ 3827 {0, 239}, // AX CX DX BX BP SI DI 3828 }, 3829 outputs: []outputInfo{ 3830 {0, 239}, // AX CX DX BX BP SI DI 3831 }, 3832 }, 3833 }, 3834 { 3835 name: "SARL", 3836 argLen: 2, 3837 resultInArg0: true, 3838 clobberFlags: true, 3839 asm: x86.ASARL, 3840 reg: regInfo{ 3841 inputs: []inputInfo{ 3842 {1, 2}, // CX 3843 {0, 239}, // AX CX DX BX BP SI DI 3844 }, 3845 outputs: []outputInfo{ 3846 {0, 239}, // AX CX DX BX BP SI DI 3847 }, 3848 }, 3849 }, 3850 { 3851 name: "SARW", 3852 argLen: 2, 3853 resultInArg0: true, 3854 clobberFlags: true, 3855 asm: x86.ASARW, 3856 reg: regInfo{ 3857 inputs: []inputInfo{ 3858 {1, 2}, // CX 3859 {0, 239}, // AX CX DX BX BP SI DI 3860 }, 3861 outputs: []outputInfo{ 3862 {0, 239}, // AX CX DX BX BP SI DI 3863 }, 3864 }, 3865 }, 3866 { 3867 name: "SARB", 3868 argLen: 2, 3869 resultInArg0: true, 3870 clobberFlags: true, 3871 asm: x86.ASARB, 3872 reg: regInfo{ 3873 inputs: []inputInfo{ 3874 {1, 2}, // CX 3875 {0, 239}, // AX CX DX BX BP SI DI 3876 }, 3877 outputs: []outputInfo{ 3878 {0, 239}, // AX CX DX BX BP SI DI 3879 }, 3880 }, 3881 }, 3882 { 3883 name: "SARLconst", 3884 auxType: auxInt32, 3885 argLen: 1, 3886 resultInArg0: true, 3887 clobberFlags: true, 3888 asm: x86.ASARL, 3889 reg: regInfo{ 3890 inputs: []inputInfo{ 3891 {0, 239}, // AX CX DX BX BP SI DI 3892 }, 3893 outputs: []outputInfo{ 3894 {0, 239}, // AX CX DX BX BP SI DI 3895 }, 3896 }, 3897 }, 3898 { 3899 name: "SARWconst", 3900 auxType: auxInt16, 3901 argLen: 1, 3902 resultInArg0: true, 3903 clobberFlags: true, 3904 asm: x86.ASARW, 3905 reg: regInfo{ 3906 inputs: []inputInfo{ 3907 {0, 239}, // AX CX DX BX BP SI DI 3908 }, 3909 outputs: []outputInfo{ 3910 {0, 239}, // AX CX DX BX BP SI DI 3911 }, 3912 }, 3913 }, 3914 { 3915 name: "SARBconst", 3916 auxType: auxInt8, 3917 argLen: 1, 3918 resultInArg0: true, 3919 clobberFlags: true, 3920 asm: x86.ASARB, 3921 reg: regInfo{ 3922 inputs: []inputInfo{ 3923 {0, 239}, // AX CX DX BX BP SI DI 3924 }, 3925 outputs: []outputInfo{ 3926 {0, 239}, // AX CX DX BX BP SI DI 3927 }, 3928 }, 3929 }, 3930 { 3931 name: "ROLLconst", 3932 auxType: auxInt32, 3933 argLen: 1, 3934 resultInArg0: true, 3935 clobberFlags: true, 3936 asm: x86.AROLL, 3937 reg: regInfo{ 3938 inputs: []inputInfo{ 3939 {0, 239}, // AX CX DX BX BP SI DI 3940 }, 3941 outputs: []outputInfo{ 3942 {0, 239}, // AX CX DX BX BP SI DI 3943 }, 3944 }, 3945 }, 3946 { 3947 name: "ROLWconst", 3948 auxType: auxInt16, 3949 argLen: 1, 3950 resultInArg0: true, 3951 clobberFlags: true, 3952 asm: x86.AROLW, 3953 reg: regInfo{ 3954 inputs: []inputInfo{ 3955 {0, 239}, // AX CX DX BX BP SI DI 3956 }, 3957 outputs: []outputInfo{ 3958 {0, 239}, // AX CX DX BX BP SI DI 3959 }, 3960 }, 3961 }, 3962 { 3963 name: "ROLBconst", 3964 auxType: auxInt8, 3965 argLen: 1, 3966 resultInArg0: true, 3967 clobberFlags: true, 3968 asm: x86.AROLB, 3969 reg: regInfo{ 3970 inputs: []inputInfo{ 3971 {0, 239}, // AX CX DX BX BP SI DI 3972 }, 3973 outputs: []outputInfo{ 3974 {0, 239}, // AX CX DX BX BP SI DI 3975 }, 3976 }, 3977 }, 3978 { 3979 name: "ADDLload", 3980 auxType: auxSymOff, 3981 argLen: 3, 3982 resultInArg0: true, 3983 clobberFlags: true, 3984 faultOnNilArg1: true, 3985 symEffect: SymRead, 3986 asm: x86.AADDL, 3987 reg: regInfo{ 3988 inputs: []inputInfo{ 3989 {0, 239}, // AX CX DX BX BP SI DI 3990 {1, 65791}, // AX CX DX BX SP BP SI DI SB 3991 }, 3992 outputs: []outputInfo{ 3993 {0, 239}, // AX CX DX BX BP SI DI 3994 }, 3995 }, 3996 }, 3997 { 3998 name: "SUBLload", 3999 auxType: auxSymOff, 4000 argLen: 3, 4001 resultInArg0: true, 4002 clobberFlags: true, 4003 faultOnNilArg1: true, 4004 symEffect: SymRead, 4005 asm: x86.ASUBL, 4006 reg: regInfo{ 4007 inputs: []inputInfo{ 4008 {0, 239}, // AX CX DX BX BP SI DI 4009 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4010 }, 4011 outputs: []outputInfo{ 4012 {0, 239}, // AX CX DX BX BP SI DI 4013 }, 4014 }, 4015 }, 4016 { 4017 name: "MULLload", 4018 auxType: auxSymOff, 4019 argLen: 3, 4020 resultInArg0: true, 4021 clobberFlags: true, 4022 faultOnNilArg1: true, 4023 symEffect: SymRead, 4024 asm: x86.AIMULL, 4025 reg: regInfo{ 4026 inputs: []inputInfo{ 4027 {0, 239}, // AX CX DX BX BP SI DI 4028 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4029 }, 4030 outputs: []outputInfo{ 4031 {0, 239}, // AX CX DX BX BP SI DI 4032 }, 4033 }, 4034 }, 4035 { 4036 name: "ANDLload", 4037 auxType: auxSymOff, 4038 argLen: 3, 4039 resultInArg0: true, 4040 clobberFlags: true, 4041 faultOnNilArg1: true, 4042 symEffect: SymRead, 4043 asm: x86.AANDL, 4044 reg: regInfo{ 4045 inputs: []inputInfo{ 4046 {0, 239}, // AX CX DX BX BP SI DI 4047 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4048 }, 4049 outputs: []outputInfo{ 4050 {0, 239}, // AX CX DX BX BP SI DI 4051 }, 4052 }, 4053 }, 4054 { 4055 name: "ORLload", 4056 auxType: auxSymOff, 4057 argLen: 3, 4058 resultInArg0: true, 4059 clobberFlags: true, 4060 faultOnNilArg1: true, 4061 symEffect: SymRead, 4062 asm: x86.AORL, 4063 reg: regInfo{ 4064 inputs: []inputInfo{ 4065 {0, 239}, // AX CX DX BX BP SI DI 4066 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4067 }, 4068 outputs: []outputInfo{ 4069 {0, 239}, // AX CX DX BX BP SI DI 4070 }, 4071 }, 4072 }, 4073 { 4074 name: "XORLload", 4075 auxType: auxSymOff, 4076 argLen: 3, 4077 resultInArg0: true, 4078 clobberFlags: true, 4079 faultOnNilArg1: true, 4080 symEffect: SymRead, 4081 asm: x86.AXORL, 4082 reg: regInfo{ 4083 inputs: []inputInfo{ 4084 {0, 239}, // AX CX DX BX BP SI DI 4085 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4086 }, 4087 outputs: []outputInfo{ 4088 {0, 239}, // AX CX DX BX BP SI DI 4089 }, 4090 }, 4091 }, 4092 { 4093 name: "ADDLloadidx4", 4094 auxType: auxSymOff, 4095 argLen: 4, 4096 resultInArg0: true, 4097 clobberFlags: true, 4098 faultOnNilArg1: true, 4099 symEffect: SymRead, 4100 asm: x86.AADDL, 4101 reg: regInfo{ 4102 inputs: []inputInfo{ 4103 {0, 239}, // AX CX DX BX BP SI DI 4104 {2, 255}, // AX CX DX BX SP BP SI DI 4105 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4106 }, 4107 outputs: []outputInfo{ 4108 {0, 239}, // AX CX DX BX BP SI DI 4109 }, 4110 }, 4111 }, 4112 { 4113 name: "SUBLloadidx4", 4114 auxType: auxSymOff, 4115 argLen: 4, 4116 resultInArg0: true, 4117 clobberFlags: true, 4118 faultOnNilArg1: true, 4119 symEffect: SymRead, 4120 asm: x86.ASUBL, 4121 reg: regInfo{ 4122 inputs: []inputInfo{ 4123 {0, 239}, // AX CX DX BX BP SI DI 4124 {2, 255}, // AX CX DX BX SP BP SI DI 4125 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4126 }, 4127 outputs: []outputInfo{ 4128 {0, 239}, // AX CX DX BX BP SI DI 4129 }, 4130 }, 4131 }, 4132 { 4133 name: "MULLloadidx4", 4134 auxType: auxSymOff, 4135 argLen: 4, 4136 resultInArg0: true, 4137 clobberFlags: true, 4138 faultOnNilArg1: true, 4139 symEffect: SymRead, 4140 asm: x86.AIMULL, 4141 reg: regInfo{ 4142 inputs: []inputInfo{ 4143 {0, 239}, // AX CX DX BX BP SI DI 4144 {2, 255}, // AX CX DX BX SP BP SI DI 4145 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4146 }, 4147 outputs: []outputInfo{ 4148 {0, 239}, // AX CX DX BX BP SI DI 4149 }, 4150 }, 4151 }, 4152 { 4153 name: "ANDLloadidx4", 4154 auxType: auxSymOff, 4155 argLen: 4, 4156 resultInArg0: true, 4157 clobberFlags: true, 4158 faultOnNilArg1: true, 4159 symEffect: SymRead, 4160 asm: x86.AANDL, 4161 reg: regInfo{ 4162 inputs: []inputInfo{ 4163 {0, 239}, // AX CX DX BX BP SI DI 4164 {2, 255}, // AX CX DX BX SP BP SI DI 4165 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4166 }, 4167 outputs: []outputInfo{ 4168 {0, 239}, // AX CX DX BX BP SI DI 4169 }, 4170 }, 4171 }, 4172 { 4173 name: "ORLloadidx4", 4174 auxType: auxSymOff, 4175 argLen: 4, 4176 resultInArg0: true, 4177 clobberFlags: true, 4178 faultOnNilArg1: true, 4179 symEffect: SymRead, 4180 asm: x86.AORL, 4181 reg: regInfo{ 4182 inputs: []inputInfo{ 4183 {0, 239}, // AX CX DX BX BP SI DI 4184 {2, 255}, // AX CX DX BX SP BP SI DI 4185 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4186 }, 4187 outputs: []outputInfo{ 4188 {0, 239}, // AX CX DX BX BP SI DI 4189 }, 4190 }, 4191 }, 4192 { 4193 name: "XORLloadidx4", 4194 auxType: auxSymOff, 4195 argLen: 4, 4196 resultInArg0: true, 4197 clobberFlags: true, 4198 faultOnNilArg1: true, 4199 symEffect: SymRead, 4200 asm: x86.AXORL, 4201 reg: regInfo{ 4202 inputs: []inputInfo{ 4203 {0, 239}, // AX CX DX BX BP SI DI 4204 {2, 255}, // AX CX DX BX SP BP SI DI 4205 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4206 }, 4207 outputs: []outputInfo{ 4208 {0, 239}, // AX CX DX BX BP SI DI 4209 }, 4210 }, 4211 }, 4212 { 4213 name: "NEGL", 4214 argLen: 1, 4215 resultInArg0: true, 4216 clobberFlags: true, 4217 asm: x86.ANEGL, 4218 reg: regInfo{ 4219 inputs: []inputInfo{ 4220 {0, 239}, // AX CX DX BX BP SI DI 4221 }, 4222 outputs: []outputInfo{ 4223 {0, 239}, // AX CX DX BX BP SI DI 4224 }, 4225 }, 4226 }, 4227 { 4228 name: "NOTL", 4229 argLen: 1, 4230 resultInArg0: true, 4231 clobberFlags: true, 4232 asm: x86.ANOTL, 4233 reg: regInfo{ 4234 inputs: []inputInfo{ 4235 {0, 239}, // AX CX DX BX BP SI DI 4236 }, 4237 outputs: []outputInfo{ 4238 {0, 239}, // AX CX DX BX BP SI DI 4239 }, 4240 }, 4241 }, 4242 { 4243 name: "BSFL", 4244 argLen: 1, 4245 clobberFlags: true, 4246 asm: x86.ABSFL, 4247 reg: regInfo{ 4248 inputs: []inputInfo{ 4249 {0, 239}, // AX CX DX BX BP SI DI 4250 }, 4251 outputs: []outputInfo{ 4252 {0, 239}, // AX CX DX BX BP SI DI 4253 }, 4254 }, 4255 }, 4256 { 4257 name: "BSFW", 4258 argLen: 1, 4259 clobberFlags: true, 4260 asm: x86.ABSFW, 4261 reg: regInfo{ 4262 inputs: []inputInfo{ 4263 {0, 239}, // AX CX DX BX BP SI DI 4264 }, 4265 outputs: []outputInfo{ 4266 {0, 239}, // AX CX DX BX BP SI DI 4267 }, 4268 }, 4269 }, 4270 { 4271 name: "BSRL", 4272 argLen: 1, 4273 clobberFlags: true, 4274 asm: x86.ABSRL, 4275 reg: regInfo{ 4276 inputs: []inputInfo{ 4277 {0, 239}, // AX CX DX BX BP SI DI 4278 }, 4279 outputs: []outputInfo{ 4280 {0, 239}, // AX CX DX BX BP SI DI 4281 }, 4282 }, 4283 }, 4284 { 4285 name: "BSRW", 4286 argLen: 1, 4287 clobberFlags: true, 4288 asm: x86.ABSRW, 4289 reg: regInfo{ 4290 inputs: []inputInfo{ 4291 {0, 239}, // AX CX DX BX BP SI DI 4292 }, 4293 outputs: []outputInfo{ 4294 {0, 239}, // AX CX DX BX BP SI DI 4295 }, 4296 }, 4297 }, 4298 { 4299 name: "BSWAPL", 4300 argLen: 1, 4301 resultInArg0: true, 4302 clobberFlags: true, 4303 asm: x86.ABSWAPL, 4304 reg: regInfo{ 4305 inputs: []inputInfo{ 4306 {0, 239}, // AX CX DX BX BP SI DI 4307 }, 4308 outputs: []outputInfo{ 4309 {0, 239}, // AX CX DX BX BP SI DI 4310 }, 4311 }, 4312 }, 4313 { 4314 name: "SQRTSD", 4315 argLen: 1, 4316 asm: x86.ASQRTSD, 4317 reg: regInfo{ 4318 inputs: []inputInfo{ 4319 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4320 }, 4321 outputs: []outputInfo{ 4322 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4323 }, 4324 }, 4325 }, 4326 { 4327 name: "SBBLcarrymask", 4328 argLen: 1, 4329 asm: x86.ASBBL, 4330 reg: regInfo{ 4331 outputs: []outputInfo{ 4332 {0, 239}, // AX CX DX BX BP SI DI 4333 }, 4334 }, 4335 }, 4336 { 4337 name: "SETEQ", 4338 argLen: 1, 4339 asm: x86.ASETEQ, 4340 reg: regInfo{ 4341 outputs: []outputInfo{ 4342 {0, 239}, // AX CX DX BX BP SI DI 4343 }, 4344 }, 4345 }, 4346 { 4347 name: "SETNE", 4348 argLen: 1, 4349 asm: x86.ASETNE, 4350 reg: regInfo{ 4351 outputs: []outputInfo{ 4352 {0, 239}, // AX CX DX BX BP SI DI 4353 }, 4354 }, 4355 }, 4356 { 4357 name: "SETL", 4358 argLen: 1, 4359 asm: x86.ASETLT, 4360 reg: regInfo{ 4361 outputs: []outputInfo{ 4362 {0, 239}, // AX CX DX BX BP SI DI 4363 }, 4364 }, 4365 }, 4366 { 4367 name: "SETLE", 4368 argLen: 1, 4369 asm: x86.ASETLE, 4370 reg: regInfo{ 4371 outputs: []outputInfo{ 4372 {0, 239}, // AX CX DX BX BP SI DI 4373 }, 4374 }, 4375 }, 4376 { 4377 name: "SETG", 4378 argLen: 1, 4379 asm: x86.ASETGT, 4380 reg: regInfo{ 4381 outputs: []outputInfo{ 4382 {0, 239}, // AX CX DX BX BP SI DI 4383 }, 4384 }, 4385 }, 4386 { 4387 name: "SETGE", 4388 argLen: 1, 4389 asm: x86.ASETGE, 4390 reg: regInfo{ 4391 outputs: []outputInfo{ 4392 {0, 239}, // AX CX DX BX BP SI DI 4393 }, 4394 }, 4395 }, 4396 { 4397 name: "SETB", 4398 argLen: 1, 4399 asm: x86.ASETCS, 4400 reg: regInfo{ 4401 outputs: []outputInfo{ 4402 {0, 239}, // AX CX DX BX BP SI DI 4403 }, 4404 }, 4405 }, 4406 { 4407 name: "SETBE", 4408 argLen: 1, 4409 asm: x86.ASETLS, 4410 reg: regInfo{ 4411 outputs: []outputInfo{ 4412 {0, 239}, // AX CX DX BX BP SI DI 4413 }, 4414 }, 4415 }, 4416 { 4417 name: "SETA", 4418 argLen: 1, 4419 asm: x86.ASETHI, 4420 reg: regInfo{ 4421 outputs: []outputInfo{ 4422 {0, 239}, // AX CX DX BX BP SI DI 4423 }, 4424 }, 4425 }, 4426 { 4427 name: "SETAE", 4428 argLen: 1, 4429 asm: x86.ASETCC, 4430 reg: regInfo{ 4431 outputs: []outputInfo{ 4432 {0, 239}, // AX CX DX BX BP SI DI 4433 }, 4434 }, 4435 }, 4436 { 4437 name: "SETO", 4438 argLen: 1, 4439 asm: x86.ASETOS, 4440 reg: regInfo{ 4441 outputs: []outputInfo{ 4442 {0, 239}, // AX CX DX BX BP SI DI 4443 }, 4444 }, 4445 }, 4446 { 4447 name: "SETEQF", 4448 argLen: 1, 4449 clobberFlags: true, 4450 asm: x86.ASETEQ, 4451 reg: regInfo{ 4452 clobbers: 1, // AX 4453 outputs: []outputInfo{ 4454 {0, 238}, // CX DX BX BP SI DI 4455 }, 4456 }, 4457 }, 4458 { 4459 name: "SETNEF", 4460 argLen: 1, 4461 clobberFlags: true, 4462 asm: x86.ASETNE, 4463 reg: regInfo{ 4464 clobbers: 1, // AX 4465 outputs: []outputInfo{ 4466 {0, 238}, // CX DX BX BP SI DI 4467 }, 4468 }, 4469 }, 4470 { 4471 name: "SETORD", 4472 argLen: 1, 4473 asm: x86.ASETPC, 4474 reg: regInfo{ 4475 outputs: []outputInfo{ 4476 {0, 239}, // AX CX DX BX BP SI DI 4477 }, 4478 }, 4479 }, 4480 { 4481 name: "SETNAN", 4482 argLen: 1, 4483 asm: x86.ASETPS, 4484 reg: regInfo{ 4485 outputs: []outputInfo{ 4486 {0, 239}, // AX CX DX BX BP SI DI 4487 }, 4488 }, 4489 }, 4490 { 4491 name: "SETGF", 4492 argLen: 1, 4493 asm: x86.ASETHI, 4494 reg: regInfo{ 4495 outputs: []outputInfo{ 4496 {0, 239}, // AX CX DX BX BP SI DI 4497 }, 4498 }, 4499 }, 4500 { 4501 name: "SETGEF", 4502 argLen: 1, 4503 asm: x86.ASETCC, 4504 reg: regInfo{ 4505 outputs: []outputInfo{ 4506 {0, 239}, // AX CX DX BX BP SI DI 4507 }, 4508 }, 4509 }, 4510 { 4511 name: "MOVBLSX", 4512 argLen: 1, 4513 asm: x86.AMOVBLSX, 4514 reg: regInfo{ 4515 inputs: []inputInfo{ 4516 {0, 239}, // AX CX DX BX BP SI DI 4517 }, 4518 outputs: []outputInfo{ 4519 {0, 239}, // AX CX DX BX BP SI DI 4520 }, 4521 }, 4522 }, 4523 { 4524 name: "MOVBLZX", 4525 argLen: 1, 4526 asm: x86.AMOVBLZX, 4527 reg: regInfo{ 4528 inputs: []inputInfo{ 4529 {0, 239}, // AX CX DX BX BP SI DI 4530 }, 4531 outputs: []outputInfo{ 4532 {0, 239}, // AX CX DX BX BP SI DI 4533 }, 4534 }, 4535 }, 4536 { 4537 name: "MOVWLSX", 4538 argLen: 1, 4539 asm: x86.AMOVWLSX, 4540 reg: regInfo{ 4541 inputs: []inputInfo{ 4542 {0, 239}, // AX CX DX BX BP SI DI 4543 }, 4544 outputs: []outputInfo{ 4545 {0, 239}, // AX CX DX BX BP SI DI 4546 }, 4547 }, 4548 }, 4549 { 4550 name: "MOVWLZX", 4551 argLen: 1, 4552 asm: x86.AMOVWLZX, 4553 reg: regInfo{ 4554 inputs: []inputInfo{ 4555 {0, 239}, // AX CX DX BX BP SI DI 4556 }, 4557 outputs: []outputInfo{ 4558 {0, 239}, // AX CX DX BX BP SI DI 4559 }, 4560 }, 4561 }, 4562 { 4563 name: "MOVLconst", 4564 auxType: auxInt32, 4565 argLen: 0, 4566 rematerializeable: true, 4567 asm: x86.AMOVL, 4568 reg: regInfo{ 4569 outputs: []outputInfo{ 4570 {0, 239}, // AX CX DX BX BP SI DI 4571 }, 4572 }, 4573 }, 4574 { 4575 name: "CVTTSD2SL", 4576 argLen: 1, 4577 usesScratch: true, 4578 asm: x86.ACVTTSD2SL, 4579 reg: regInfo{ 4580 inputs: []inputInfo{ 4581 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4582 }, 4583 outputs: []outputInfo{ 4584 {0, 239}, // AX CX DX BX BP SI DI 4585 }, 4586 }, 4587 }, 4588 { 4589 name: "CVTTSS2SL", 4590 argLen: 1, 4591 usesScratch: true, 4592 asm: x86.ACVTTSS2SL, 4593 reg: regInfo{ 4594 inputs: []inputInfo{ 4595 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4596 }, 4597 outputs: []outputInfo{ 4598 {0, 239}, // AX CX DX BX BP SI DI 4599 }, 4600 }, 4601 }, 4602 { 4603 name: "CVTSL2SS", 4604 argLen: 1, 4605 usesScratch: true, 4606 asm: x86.ACVTSL2SS, 4607 reg: regInfo{ 4608 inputs: []inputInfo{ 4609 {0, 239}, // AX CX DX BX BP SI DI 4610 }, 4611 outputs: []outputInfo{ 4612 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4613 }, 4614 }, 4615 }, 4616 { 4617 name: "CVTSL2SD", 4618 argLen: 1, 4619 usesScratch: true, 4620 asm: x86.ACVTSL2SD, 4621 reg: regInfo{ 4622 inputs: []inputInfo{ 4623 {0, 239}, // AX CX DX BX BP SI DI 4624 }, 4625 outputs: []outputInfo{ 4626 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4627 }, 4628 }, 4629 }, 4630 { 4631 name: "CVTSD2SS", 4632 argLen: 1, 4633 usesScratch: true, 4634 asm: x86.ACVTSD2SS, 4635 reg: regInfo{ 4636 inputs: []inputInfo{ 4637 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4638 }, 4639 outputs: []outputInfo{ 4640 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4641 }, 4642 }, 4643 }, 4644 { 4645 name: "CVTSS2SD", 4646 argLen: 1, 4647 asm: x86.ACVTSS2SD, 4648 reg: regInfo{ 4649 inputs: []inputInfo{ 4650 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4651 }, 4652 outputs: []outputInfo{ 4653 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4654 }, 4655 }, 4656 }, 4657 { 4658 name: "PXOR", 4659 argLen: 2, 4660 commutative: true, 4661 resultInArg0: true, 4662 asm: x86.APXOR, 4663 reg: regInfo{ 4664 inputs: []inputInfo{ 4665 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4666 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4667 }, 4668 outputs: []outputInfo{ 4669 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4670 }, 4671 }, 4672 }, 4673 { 4674 name: "LEAL", 4675 auxType: auxSymOff, 4676 argLen: 1, 4677 rematerializeable: true, 4678 symEffect: SymAddr, 4679 reg: regInfo{ 4680 inputs: []inputInfo{ 4681 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4682 }, 4683 outputs: []outputInfo{ 4684 {0, 239}, // AX CX DX BX BP SI DI 4685 }, 4686 }, 4687 }, 4688 { 4689 name: "LEAL1", 4690 auxType: auxSymOff, 4691 argLen: 2, 4692 commutative: true, 4693 symEffect: SymAddr, 4694 reg: regInfo{ 4695 inputs: []inputInfo{ 4696 {1, 255}, // AX CX DX BX SP BP SI DI 4697 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4698 }, 4699 outputs: []outputInfo{ 4700 {0, 239}, // AX CX DX BX BP SI DI 4701 }, 4702 }, 4703 }, 4704 { 4705 name: "LEAL2", 4706 auxType: auxSymOff, 4707 argLen: 2, 4708 symEffect: SymAddr, 4709 reg: regInfo{ 4710 inputs: []inputInfo{ 4711 {1, 255}, // AX CX DX BX SP BP SI DI 4712 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4713 }, 4714 outputs: []outputInfo{ 4715 {0, 239}, // AX CX DX BX BP SI DI 4716 }, 4717 }, 4718 }, 4719 { 4720 name: "LEAL4", 4721 auxType: auxSymOff, 4722 argLen: 2, 4723 symEffect: SymAddr, 4724 reg: regInfo{ 4725 inputs: []inputInfo{ 4726 {1, 255}, // AX CX DX BX SP BP SI DI 4727 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4728 }, 4729 outputs: []outputInfo{ 4730 {0, 239}, // AX CX DX BX BP SI DI 4731 }, 4732 }, 4733 }, 4734 { 4735 name: "LEAL8", 4736 auxType: auxSymOff, 4737 argLen: 2, 4738 symEffect: SymAddr, 4739 reg: regInfo{ 4740 inputs: []inputInfo{ 4741 {1, 255}, // AX CX DX BX SP BP SI DI 4742 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4743 }, 4744 outputs: []outputInfo{ 4745 {0, 239}, // AX CX DX BX BP SI DI 4746 }, 4747 }, 4748 }, 4749 { 4750 name: "MOVBload", 4751 auxType: auxSymOff, 4752 argLen: 2, 4753 faultOnNilArg0: true, 4754 symEffect: SymRead, 4755 asm: x86.AMOVBLZX, 4756 reg: regInfo{ 4757 inputs: []inputInfo{ 4758 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4759 }, 4760 outputs: []outputInfo{ 4761 {0, 239}, // AX CX DX BX BP SI DI 4762 }, 4763 }, 4764 }, 4765 { 4766 name: "MOVBLSXload", 4767 auxType: auxSymOff, 4768 argLen: 2, 4769 faultOnNilArg0: true, 4770 symEffect: SymRead, 4771 asm: x86.AMOVBLSX, 4772 reg: regInfo{ 4773 inputs: []inputInfo{ 4774 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4775 }, 4776 outputs: []outputInfo{ 4777 {0, 239}, // AX CX DX BX BP SI DI 4778 }, 4779 }, 4780 }, 4781 { 4782 name: "MOVWload", 4783 auxType: auxSymOff, 4784 argLen: 2, 4785 faultOnNilArg0: true, 4786 symEffect: SymRead, 4787 asm: x86.AMOVWLZX, 4788 reg: regInfo{ 4789 inputs: []inputInfo{ 4790 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4791 }, 4792 outputs: []outputInfo{ 4793 {0, 239}, // AX CX DX BX BP SI DI 4794 }, 4795 }, 4796 }, 4797 { 4798 name: "MOVWLSXload", 4799 auxType: auxSymOff, 4800 argLen: 2, 4801 faultOnNilArg0: true, 4802 symEffect: SymRead, 4803 asm: x86.AMOVWLSX, 4804 reg: regInfo{ 4805 inputs: []inputInfo{ 4806 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4807 }, 4808 outputs: []outputInfo{ 4809 {0, 239}, // AX CX DX BX BP SI DI 4810 }, 4811 }, 4812 }, 4813 { 4814 name: "MOVLload", 4815 auxType: auxSymOff, 4816 argLen: 2, 4817 faultOnNilArg0: true, 4818 symEffect: SymRead, 4819 asm: x86.AMOVL, 4820 reg: regInfo{ 4821 inputs: []inputInfo{ 4822 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4823 }, 4824 outputs: []outputInfo{ 4825 {0, 239}, // AX CX DX BX BP SI DI 4826 }, 4827 }, 4828 }, 4829 { 4830 name: "MOVBstore", 4831 auxType: auxSymOff, 4832 argLen: 3, 4833 faultOnNilArg0: true, 4834 symEffect: SymWrite, 4835 asm: x86.AMOVB, 4836 reg: regInfo{ 4837 inputs: []inputInfo{ 4838 {1, 255}, // AX CX DX BX SP BP SI DI 4839 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4840 }, 4841 }, 4842 }, 4843 { 4844 name: "MOVWstore", 4845 auxType: auxSymOff, 4846 argLen: 3, 4847 faultOnNilArg0: true, 4848 symEffect: SymWrite, 4849 asm: x86.AMOVW, 4850 reg: regInfo{ 4851 inputs: []inputInfo{ 4852 {1, 255}, // AX CX DX BX SP BP SI DI 4853 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4854 }, 4855 }, 4856 }, 4857 { 4858 name: "MOVLstore", 4859 auxType: auxSymOff, 4860 argLen: 3, 4861 faultOnNilArg0: true, 4862 symEffect: SymWrite, 4863 asm: x86.AMOVL, 4864 reg: regInfo{ 4865 inputs: []inputInfo{ 4866 {1, 255}, // AX CX DX BX SP BP SI DI 4867 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4868 }, 4869 }, 4870 }, 4871 { 4872 name: "ADDLmodify", 4873 auxType: auxSymOff, 4874 argLen: 3, 4875 clobberFlags: true, 4876 faultOnNilArg0: true, 4877 symEffect: SymRead | SymWrite, 4878 asm: x86.AADDL, 4879 reg: regInfo{ 4880 inputs: []inputInfo{ 4881 {1, 255}, // AX CX DX BX SP BP SI DI 4882 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4883 }, 4884 }, 4885 }, 4886 { 4887 name: "SUBLmodify", 4888 auxType: auxSymOff, 4889 argLen: 3, 4890 clobberFlags: true, 4891 faultOnNilArg0: true, 4892 symEffect: SymRead | SymWrite, 4893 asm: x86.ASUBL, 4894 reg: regInfo{ 4895 inputs: []inputInfo{ 4896 {1, 255}, // AX CX DX BX SP BP SI DI 4897 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4898 }, 4899 }, 4900 }, 4901 { 4902 name: "ANDLmodify", 4903 auxType: auxSymOff, 4904 argLen: 3, 4905 clobberFlags: true, 4906 faultOnNilArg0: true, 4907 symEffect: SymRead | SymWrite, 4908 asm: x86.AANDL, 4909 reg: regInfo{ 4910 inputs: []inputInfo{ 4911 {1, 255}, // AX CX DX BX SP BP SI DI 4912 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4913 }, 4914 }, 4915 }, 4916 { 4917 name: "ORLmodify", 4918 auxType: auxSymOff, 4919 argLen: 3, 4920 clobberFlags: true, 4921 faultOnNilArg0: true, 4922 symEffect: SymRead | SymWrite, 4923 asm: x86.AORL, 4924 reg: regInfo{ 4925 inputs: []inputInfo{ 4926 {1, 255}, // AX CX DX BX SP BP SI DI 4927 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4928 }, 4929 }, 4930 }, 4931 { 4932 name: "XORLmodify", 4933 auxType: auxSymOff, 4934 argLen: 3, 4935 clobberFlags: true, 4936 faultOnNilArg0: true, 4937 symEffect: SymRead | SymWrite, 4938 asm: x86.AXORL, 4939 reg: regInfo{ 4940 inputs: []inputInfo{ 4941 {1, 255}, // AX CX DX BX SP BP SI DI 4942 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4943 }, 4944 }, 4945 }, 4946 { 4947 name: "ADDLmodifyidx4", 4948 auxType: auxSymOff, 4949 argLen: 4, 4950 clobberFlags: true, 4951 faultOnNilArg0: true, 4952 symEffect: SymRead | SymWrite, 4953 asm: x86.AADDL, 4954 reg: regInfo{ 4955 inputs: []inputInfo{ 4956 {1, 255}, // AX CX DX BX SP BP SI DI 4957 {2, 255}, // AX CX DX BX SP BP SI DI 4958 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4959 }, 4960 }, 4961 }, 4962 { 4963 name: "SUBLmodifyidx4", 4964 auxType: auxSymOff, 4965 argLen: 4, 4966 clobberFlags: true, 4967 faultOnNilArg0: true, 4968 symEffect: SymRead | SymWrite, 4969 asm: x86.ASUBL, 4970 reg: regInfo{ 4971 inputs: []inputInfo{ 4972 {1, 255}, // AX CX DX BX SP BP SI DI 4973 {2, 255}, // AX CX DX BX SP BP SI DI 4974 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4975 }, 4976 }, 4977 }, 4978 { 4979 name: "ANDLmodifyidx4", 4980 auxType: auxSymOff, 4981 argLen: 4, 4982 clobberFlags: true, 4983 faultOnNilArg0: true, 4984 symEffect: SymRead | SymWrite, 4985 asm: x86.AANDL, 4986 reg: regInfo{ 4987 inputs: []inputInfo{ 4988 {1, 255}, // AX CX DX BX SP BP SI DI 4989 {2, 255}, // AX CX DX BX SP BP SI DI 4990 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4991 }, 4992 }, 4993 }, 4994 { 4995 name: "ORLmodifyidx4", 4996 auxType: auxSymOff, 4997 argLen: 4, 4998 clobberFlags: true, 4999 faultOnNilArg0: true, 5000 symEffect: SymRead | SymWrite, 5001 asm: x86.AORL, 5002 reg: regInfo{ 5003 inputs: []inputInfo{ 5004 {1, 255}, // AX CX DX BX SP BP SI DI 5005 {2, 255}, // AX CX DX BX SP BP SI DI 5006 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5007 }, 5008 }, 5009 }, 5010 { 5011 name: "XORLmodifyidx4", 5012 auxType: auxSymOff, 5013 argLen: 4, 5014 clobberFlags: true, 5015 faultOnNilArg0: true, 5016 symEffect: SymRead | SymWrite, 5017 asm: x86.AXORL, 5018 reg: regInfo{ 5019 inputs: []inputInfo{ 5020 {1, 255}, // AX CX DX BX SP BP SI DI 5021 {2, 255}, // AX CX DX BX SP BP SI DI 5022 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5023 }, 5024 }, 5025 }, 5026 { 5027 name: "ADDLconstmodify", 5028 auxType: auxSymValAndOff, 5029 argLen: 2, 5030 clobberFlags: true, 5031 faultOnNilArg0: true, 5032 symEffect: SymRead | SymWrite, 5033 asm: x86.AADDL, 5034 reg: regInfo{ 5035 inputs: []inputInfo{ 5036 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5037 }, 5038 }, 5039 }, 5040 { 5041 name: "ANDLconstmodify", 5042 auxType: auxSymValAndOff, 5043 argLen: 2, 5044 clobberFlags: true, 5045 faultOnNilArg0: true, 5046 symEffect: SymRead | SymWrite, 5047 asm: x86.AANDL, 5048 reg: regInfo{ 5049 inputs: []inputInfo{ 5050 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5051 }, 5052 }, 5053 }, 5054 { 5055 name: "ORLconstmodify", 5056 auxType: auxSymValAndOff, 5057 argLen: 2, 5058 clobberFlags: true, 5059 faultOnNilArg0: true, 5060 symEffect: SymRead | SymWrite, 5061 asm: x86.AORL, 5062 reg: regInfo{ 5063 inputs: []inputInfo{ 5064 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5065 }, 5066 }, 5067 }, 5068 { 5069 name: "XORLconstmodify", 5070 auxType: auxSymValAndOff, 5071 argLen: 2, 5072 clobberFlags: true, 5073 faultOnNilArg0: true, 5074 symEffect: SymRead | SymWrite, 5075 asm: x86.AXORL, 5076 reg: regInfo{ 5077 inputs: []inputInfo{ 5078 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5079 }, 5080 }, 5081 }, 5082 { 5083 name: "ADDLconstmodifyidx4", 5084 auxType: auxSymValAndOff, 5085 argLen: 3, 5086 clobberFlags: true, 5087 faultOnNilArg0: true, 5088 symEffect: SymRead | SymWrite, 5089 asm: x86.AADDL, 5090 reg: regInfo{ 5091 inputs: []inputInfo{ 5092 {1, 255}, // AX CX DX BX SP BP SI DI 5093 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5094 }, 5095 }, 5096 }, 5097 { 5098 name: "ANDLconstmodifyidx4", 5099 auxType: auxSymValAndOff, 5100 argLen: 3, 5101 clobberFlags: true, 5102 faultOnNilArg0: true, 5103 symEffect: SymRead | SymWrite, 5104 asm: x86.AANDL, 5105 reg: regInfo{ 5106 inputs: []inputInfo{ 5107 {1, 255}, // AX CX DX BX SP BP SI DI 5108 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5109 }, 5110 }, 5111 }, 5112 { 5113 name: "ORLconstmodifyidx4", 5114 auxType: auxSymValAndOff, 5115 argLen: 3, 5116 clobberFlags: true, 5117 faultOnNilArg0: true, 5118 symEffect: SymRead | SymWrite, 5119 asm: x86.AORL, 5120 reg: regInfo{ 5121 inputs: []inputInfo{ 5122 {1, 255}, // AX CX DX BX SP BP SI DI 5123 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5124 }, 5125 }, 5126 }, 5127 { 5128 name: "XORLconstmodifyidx4", 5129 auxType: auxSymValAndOff, 5130 argLen: 3, 5131 clobberFlags: true, 5132 faultOnNilArg0: true, 5133 symEffect: SymRead | SymWrite, 5134 asm: x86.AXORL, 5135 reg: regInfo{ 5136 inputs: []inputInfo{ 5137 {1, 255}, // AX CX DX BX SP BP SI DI 5138 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5139 }, 5140 }, 5141 }, 5142 { 5143 name: "MOVBloadidx1", 5144 auxType: auxSymOff, 5145 argLen: 3, 5146 commutative: true, 5147 symEffect: SymRead, 5148 asm: x86.AMOVBLZX, 5149 reg: regInfo{ 5150 inputs: []inputInfo{ 5151 {1, 255}, // AX CX DX BX SP BP SI DI 5152 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5153 }, 5154 outputs: []outputInfo{ 5155 {0, 239}, // AX CX DX BX BP SI DI 5156 }, 5157 }, 5158 }, 5159 { 5160 name: "MOVWloadidx1", 5161 auxType: auxSymOff, 5162 argLen: 3, 5163 commutative: true, 5164 symEffect: SymRead, 5165 asm: x86.AMOVWLZX, 5166 reg: regInfo{ 5167 inputs: []inputInfo{ 5168 {1, 255}, // AX CX DX BX SP BP SI DI 5169 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5170 }, 5171 outputs: []outputInfo{ 5172 {0, 239}, // AX CX DX BX BP SI DI 5173 }, 5174 }, 5175 }, 5176 { 5177 name: "MOVWloadidx2", 5178 auxType: auxSymOff, 5179 argLen: 3, 5180 symEffect: SymRead, 5181 asm: x86.AMOVWLZX, 5182 reg: regInfo{ 5183 inputs: []inputInfo{ 5184 {1, 255}, // AX CX DX BX SP BP SI DI 5185 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5186 }, 5187 outputs: []outputInfo{ 5188 {0, 239}, // AX CX DX BX BP SI DI 5189 }, 5190 }, 5191 }, 5192 { 5193 name: "MOVLloadidx1", 5194 auxType: auxSymOff, 5195 argLen: 3, 5196 commutative: true, 5197 symEffect: SymRead, 5198 asm: x86.AMOVL, 5199 reg: regInfo{ 5200 inputs: []inputInfo{ 5201 {1, 255}, // AX CX DX BX SP BP SI DI 5202 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5203 }, 5204 outputs: []outputInfo{ 5205 {0, 239}, // AX CX DX BX BP SI DI 5206 }, 5207 }, 5208 }, 5209 { 5210 name: "MOVLloadidx4", 5211 auxType: auxSymOff, 5212 argLen: 3, 5213 symEffect: SymRead, 5214 asm: x86.AMOVL, 5215 reg: regInfo{ 5216 inputs: []inputInfo{ 5217 {1, 255}, // AX CX DX BX SP BP SI DI 5218 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5219 }, 5220 outputs: []outputInfo{ 5221 {0, 239}, // AX CX DX BX BP SI DI 5222 }, 5223 }, 5224 }, 5225 { 5226 name: "MOVBstoreidx1", 5227 auxType: auxSymOff, 5228 argLen: 4, 5229 commutative: true, 5230 symEffect: SymWrite, 5231 asm: x86.AMOVB, 5232 reg: regInfo{ 5233 inputs: []inputInfo{ 5234 {1, 255}, // AX CX DX BX SP BP SI DI 5235 {2, 255}, // AX CX DX BX SP BP SI DI 5236 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5237 }, 5238 }, 5239 }, 5240 { 5241 name: "MOVWstoreidx1", 5242 auxType: auxSymOff, 5243 argLen: 4, 5244 commutative: true, 5245 symEffect: SymWrite, 5246 asm: x86.AMOVW, 5247 reg: regInfo{ 5248 inputs: []inputInfo{ 5249 {1, 255}, // AX CX DX BX SP BP SI DI 5250 {2, 255}, // AX CX DX BX SP BP SI DI 5251 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5252 }, 5253 }, 5254 }, 5255 { 5256 name: "MOVWstoreidx2", 5257 auxType: auxSymOff, 5258 argLen: 4, 5259 symEffect: SymWrite, 5260 asm: x86.AMOVW, 5261 reg: regInfo{ 5262 inputs: []inputInfo{ 5263 {1, 255}, // AX CX DX BX SP BP SI DI 5264 {2, 255}, // AX CX DX BX SP BP SI DI 5265 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5266 }, 5267 }, 5268 }, 5269 { 5270 name: "MOVLstoreidx1", 5271 auxType: auxSymOff, 5272 argLen: 4, 5273 commutative: true, 5274 symEffect: SymWrite, 5275 asm: x86.AMOVL, 5276 reg: regInfo{ 5277 inputs: []inputInfo{ 5278 {1, 255}, // AX CX DX BX SP BP SI DI 5279 {2, 255}, // AX CX DX BX SP BP SI DI 5280 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5281 }, 5282 }, 5283 }, 5284 { 5285 name: "MOVLstoreidx4", 5286 auxType: auxSymOff, 5287 argLen: 4, 5288 symEffect: SymWrite, 5289 asm: x86.AMOVL, 5290 reg: regInfo{ 5291 inputs: []inputInfo{ 5292 {1, 255}, // AX CX DX BX SP BP SI DI 5293 {2, 255}, // AX CX DX BX SP BP SI DI 5294 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5295 }, 5296 }, 5297 }, 5298 { 5299 name: "MOVBstoreconst", 5300 auxType: auxSymValAndOff, 5301 argLen: 2, 5302 faultOnNilArg0: true, 5303 symEffect: SymWrite, 5304 asm: x86.AMOVB, 5305 reg: regInfo{ 5306 inputs: []inputInfo{ 5307 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5308 }, 5309 }, 5310 }, 5311 { 5312 name: "MOVWstoreconst", 5313 auxType: auxSymValAndOff, 5314 argLen: 2, 5315 faultOnNilArg0: true, 5316 symEffect: SymWrite, 5317 asm: x86.AMOVW, 5318 reg: regInfo{ 5319 inputs: []inputInfo{ 5320 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5321 }, 5322 }, 5323 }, 5324 { 5325 name: "MOVLstoreconst", 5326 auxType: auxSymValAndOff, 5327 argLen: 2, 5328 faultOnNilArg0: true, 5329 symEffect: SymWrite, 5330 asm: x86.AMOVL, 5331 reg: regInfo{ 5332 inputs: []inputInfo{ 5333 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5334 }, 5335 }, 5336 }, 5337 { 5338 name: "MOVBstoreconstidx1", 5339 auxType: auxSymValAndOff, 5340 argLen: 3, 5341 symEffect: SymWrite, 5342 asm: x86.AMOVB, 5343 reg: regInfo{ 5344 inputs: []inputInfo{ 5345 {1, 255}, // AX CX DX BX SP BP SI DI 5346 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5347 }, 5348 }, 5349 }, 5350 { 5351 name: "MOVWstoreconstidx1", 5352 auxType: auxSymValAndOff, 5353 argLen: 3, 5354 symEffect: SymWrite, 5355 asm: x86.AMOVW, 5356 reg: regInfo{ 5357 inputs: []inputInfo{ 5358 {1, 255}, // AX CX DX BX SP BP SI DI 5359 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5360 }, 5361 }, 5362 }, 5363 { 5364 name: "MOVWstoreconstidx2", 5365 auxType: auxSymValAndOff, 5366 argLen: 3, 5367 symEffect: SymWrite, 5368 asm: x86.AMOVW, 5369 reg: regInfo{ 5370 inputs: []inputInfo{ 5371 {1, 255}, // AX CX DX BX SP BP SI DI 5372 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5373 }, 5374 }, 5375 }, 5376 { 5377 name: "MOVLstoreconstidx1", 5378 auxType: auxSymValAndOff, 5379 argLen: 3, 5380 symEffect: SymWrite, 5381 asm: x86.AMOVL, 5382 reg: regInfo{ 5383 inputs: []inputInfo{ 5384 {1, 255}, // AX CX DX BX SP BP SI DI 5385 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5386 }, 5387 }, 5388 }, 5389 { 5390 name: "MOVLstoreconstidx4", 5391 auxType: auxSymValAndOff, 5392 argLen: 3, 5393 symEffect: SymWrite, 5394 asm: x86.AMOVL, 5395 reg: regInfo{ 5396 inputs: []inputInfo{ 5397 {1, 255}, // AX CX DX BX SP BP SI DI 5398 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5399 }, 5400 }, 5401 }, 5402 { 5403 name: "DUFFZERO", 5404 auxType: auxInt64, 5405 argLen: 3, 5406 faultOnNilArg0: true, 5407 reg: regInfo{ 5408 inputs: []inputInfo{ 5409 {0, 128}, // DI 5410 {1, 1}, // AX 5411 }, 5412 clobbers: 130, // CX DI 5413 }, 5414 }, 5415 { 5416 name: "REPSTOSL", 5417 argLen: 4, 5418 faultOnNilArg0: true, 5419 reg: regInfo{ 5420 inputs: []inputInfo{ 5421 {0, 128}, // DI 5422 {1, 2}, // CX 5423 {2, 1}, // AX 5424 }, 5425 clobbers: 130, // CX DI 5426 }, 5427 }, 5428 { 5429 name: "CALLstatic", 5430 auxType: auxSymOff, 5431 argLen: 1, 5432 clobberFlags: true, 5433 call: true, 5434 symEffect: SymNone, 5435 reg: regInfo{ 5436 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 5437 }, 5438 }, 5439 { 5440 name: "CALLclosure", 5441 auxType: auxInt64, 5442 argLen: 3, 5443 clobberFlags: true, 5444 call: true, 5445 reg: regInfo{ 5446 inputs: []inputInfo{ 5447 {1, 4}, // DX 5448 {0, 255}, // AX CX DX BX SP BP SI DI 5449 }, 5450 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 5451 }, 5452 }, 5453 { 5454 name: "CALLinter", 5455 auxType: auxInt64, 5456 argLen: 2, 5457 clobberFlags: true, 5458 call: true, 5459 reg: regInfo{ 5460 inputs: []inputInfo{ 5461 {0, 239}, // AX CX DX BX BP SI DI 5462 }, 5463 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 5464 }, 5465 }, 5466 { 5467 name: "DUFFCOPY", 5468 auxType: auxInt64, 5469 argLen: 3, 5470 clobberFlags: true, 5471 faultOnNilArg0: true, 5472 faultOnNilArg1: true, 5473 reg: regInfo{ 5474 inputs: []inputInfo{ 5475 {0, 128}, // DI 5476 {1, 64}, // SI 5477 }, 5478 clobbers: 194, // CX SI DI 5479 }, 5480 }, 5481 { 5482 name: "REPMOVSL", 5483 argLen: 4, 5484 faultOnNilArg0: true, 5485 faultOnNilArg1: true, 5486 reg: regInfo{ 5487 inputs: []inputInfo{ 5488 {0, 128}, // DI 5489 {1, 64}, // SI 5490 {2, 2}, // CX 5491 }, 5492 clobbers: 194, // CX SI DI 5493 }, 5494 }, 5495 { 5496 name: "InvertFlags", 5497 argLen: 1, 5498 reg: regInfo{}, 5499 }, 5500 { 5501 name: "LoweredGetG", 5502 argLen: 1, 5503 reg: regInfo{ 5504 outputs: []outputInfo{ 5505 {0, 239}, // AX CX DX BX BP SI DI 5506 }, 5507 }, 5508 }, 5509 { 5510 name: "LoweredGetClosurePtr", 5511 argLen: 0, 5512 zeroWidth: true, 5513 reg: regInfo{ 5514 outputs: []outputInfo{ 5515 {0, 4}, // DX 5516 }, 5517 }, 5518 }, 5519 { 5520 name: "LoweredGetCallerPC", 5521 argLen: 0, 5522 rematerializeable: true, 5523 reg: regInfo{ 5524 outputs: []outputInfo{ 5525 {0, 239}, // AX CX DX BX BP SI DI 5526 }, 5527 }, 5528 }, 5529 { 5530 name: "LoweredGetCallerSP", 5531 argLen: 0, 5532 rematerializeable: true, 5533 reg: regInfo{ 5534 outputs: []outputInfo{ 5535 {0, 239}, // AX CX DX BX BP SI DI 5536 }, 5537 }, 5538 }, 5539 { 5540 name: "LoweredNilCheck", 5541 argLen: 2, 5542 clobberFlags: true, 5543 nilCheck: true, 5544 faultOnNilArg0: true, 5545 reg: regInfo{ 5546 inputs: []inputInfo{ 5547 {0, 255}, // AX CX DX BX SP BP SI DI 5548 }, 5549 }, 5550 }, 5551 { 5552 name: "LoweredWB", 5553 auxType: auxSym, 5554 argLen: 3, 5555 clobberFlags: true, 5556 symEffect: SymNone, 5557 reg: regInfo{ 5558 inputs: []inputInfo{ 5559 {0, 128}, // DI 5560 {1, 1}, // AX 5561 }, 5562 clobbers: 65280, // X0 X1 X2 X3 X4 X5 X6 X7 5563 }, 5564 }, 5565 { 5566 name: "FlagEQ", 5567 argLen: 0, 5568 reg: regInfo{}, 5569 }, 5570 { 5571 name: "FlagLT_ULT", 5572 argLen: 0, 5573 reg: regInfo{}, 5574 }, 5575 { 5576 name: "FlagLT_UGT", 5577 argLen: 0, 5578 reg: regInfo{}, 5579 }, 5580 { 5581 name: "FlagGT_UGT", 5582 argLen: 0, 5583 reg: regInfo{}, 5584 }, 5585 { 5586 name: "FlagGT_ULT", 5587 argLen: 0, 5588 reg: regInfo{}, 5589 }, 5590 { 5591 name: "FCHS", 5592 argLen: 1, 5593 reg: regInfo{ 5594 inputs: []inputInfo{ 5595 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5596 }, 5597 outputs: []outputInfo{ 5598 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5599 }, 5600 }, 5601 }, 5602 { 5603 name: "MOVSSconst1", 5604 auxType: auxFloat32, 5605 argLen: 0, 5606 reg: regInfo{ 5607 outputs: []outputInfo{ 5608 {0, 239}, // AX CX DX BX BP SI DI 5609 }, 5610 }, 5611 }, 5612 { 5613 name: "MOVSDconst1", 5614 auxType: auxFloat64, 5615 argLen: 0, 5616 reg: regInfo{ 5617 outputs: []outputInfo{ 5618 {0, 239}, // AX CX DX BX BP SI DI 5619 }, 5620 }, 5621 }, 5622 { 5623 name: "MOVSSconst2", 5624 argLen: 1, 5625 asm: x86.AMOVSS, 5626 reg: regInfo{ 5627 inputs: []inputInfo{ 5628 {0, 239}, // AX CX DX BX BP SI DI 5629 }, 5630 outputs: []outputInfo{ 5631 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5632 }, 5633 }, 5634 }, 5635 { 5636 name: "MOVSDconst2", 5637 argLen: 1, 5638 asm: x86.AMOVSD, 5639 reg: regInfo{ 5640 inputs: []inputInfo{ 5641 {0, 239}, // AX CX DX BX BP SI DI 5642 }, 5643 outputs: []outputInfo{ 5644 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5645 }, 5646 }, 5647 }, 5648 5649 { 5650 name: "ADDSS", 5651 argLen: 2, 5652 commutative: true, 5653 resultInArg0: true, 5654 asm: x86.AADDSS, 5655 reg: regInfo{ 5656 inputs: []inputInfo{ 5657 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5658 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5659 }, 5660 outputs: []outputInfo{ 5661 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5662 }, 5663 }, 5664 }, 5665 { 5666 name: "ADDSD", 5667 argLen: 2, 5668 commutative: true, 5669 resultInArg0: true, 5670 asm: x86.AADDSD, 5671 reg: regInfo{ 5672 inputs: []inputInfo{ 5673 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5674 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5675 }, 5676 outputs: []outputInfo{ 5677 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5678 }, 5679 }, 5680 }, 5681 { 5682 name: "SUBSS", 5683 argLen: 2, 5684 resultInArg0: true, 5685 asm: x86.ASUBSS, 5686 reg: regInfo{ 5687 inputs: []inputInfo{ 5688 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5689 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5690 }, 5691 outputs: []outputInfo{ 5692 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5693 }, 5694 }, 5695 }, 5696 { 5697 name: "SUBSD", 5698 argLen: 2, 5699 resultInArg0: true, 5700 asm: x86.ASUBSD, 5701 reg: regInfo{ 5702 inputs: []inputInfo{ 5703 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5704 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5705 }, 5706 outputs: []outputInfo{ 5707 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5708 }, 5709 }, 5710 }, 5711 { 5712 name: "MULSS", 5713 argLen: 2, 5714 commutative: true, 5715 resultInArg0: true, 5716 asm: x86.AMULSS, 5717 reg: regInfo{ 5718 inputs: []inputInfo{ 5719 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5720 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5721 }, 5722 outputs: []outputInfo{ 5723 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5724 }, 5725 }, 5726 }, 5727 { 5728 name: "MULSD", 5729 argLen: 2, 5730 commutative: true, 5731 resultInArg0: true, 5732 asm: x86.AMULSD, 5733 reg: regInfo{ 5734 inputs: []inputInfo{ 5735 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5736 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5737 }, 5738 outputs: []outputInfo{ 5739 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5740 }, 5741 }, 5742 }, 5743 { 5744 name: "DIVSS", 5745 argLen: 2, 5746 resultInArg0: true, 5747 asm: x86.ADIVSS, 5748 reg: regInfo{ 5749 inputs: []inputInfo{ 5750 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5751 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5752 }, 5753 outputs: []outputInfo{ 5754 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5755 }, 5756 }, 5757 }, 5758 { 5759 name: "DIVSD", 5760 argLen: 2, 5761 resultInArg0: true, 5762 asm: x86.ADIVSD, 5763 reg: regInfo{ 5764 inputs: []inputInfo{ 5765 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5766 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5767 }, 5768 outputs: []outputInfo{ 5769 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5770 }, 5771 }, 5772 }, 5773 { 5774 name: "MOVSSload", 5775 auxType: auxSymOff, 5776 argLen: 2, 5777 faultOnNilArg0: true, 5778 symEffect: SymRead, 5779 asm: x86.AMOVSS, 5780 reg: regInfo{ 5781 inputs: []inputInfo{ 5782 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5783 }, 5784 outputs: []outputInfo{ 5785 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5786 }, 5787 }, 5788 }, 5789 { 5790 name: "MOVSDload", 5791 auxType: auxSymOff, 5792 argLen: 2, 5793 faultOnNilArg0: true, 5794 symEffect: SymRead, 5795 asm: x86.AMOVSD, 5796 reg: regInfo{ 5797 inputs: []inputInfo{ 5798 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5799 }, 5800 outputs: []outputInfo{ 5801 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5802 }, 5803 }, 5804 }, 5805 { 5806 name: "MOVSSconst", 5807 auxType: auxFloat32, 5808 argLen: 0, 5809 rematerializeable: true, 5810 asm: x86.AMOVSS, 5811 reg: regInfo{ 5812 outputs: []outputInfo{ 5813 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5814 }, 5815 }, 5816 }, 5817 { 5818 name: "MOVSDconst", 5819 auxType: auxFloat64, 5820 argLen: 0, 5821 rematerializeable: true, 5822 asm: x86.AMOVSD, 5823 reg: regInfo{ 5824 outputs: []outputInfo{ 5825 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5826 }, 5827 }, 5828 }, 5829 { 5830 name: "MOVSSloadidx1", 5831 auxType: auxSymOff, 5832 argLen: 3, 5833 symEffect: SymRead, 5834 asm: x86.AMOVSS, 5835 reg: regInfo{ 5836 inputs: []inputInfo{ 5837 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5838 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5839 }, 5840 outputs: []outputInfo{ 5841 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5842 }, 5843 }, 5844 }, 5845 { 5846 name: "MOVSSloadidx4", 5847 auxType: auxSymOff, 5848 argLen: 3, 5849 symEffect: SymRead, 5850 asm: x86.AMOVSS, 5851 reg: regInfo{ 5852 inputs: []inputInfo{ 5853 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5854 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5855 }, 5856 outputs: []outputInfo{ 5857 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5858 }, 5859 }, 5860 }, 5861 { 5862 name: "MOVSDloadidx1", 5863 auxType: auxSymOff, 5864 argLen: 3, 5865 symEffect: SymRead, 5866 asm: x86.AMOVSD, 5867 reg: regInfo{ 5868 inputs: []inputInfo{ 5869 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5870 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5871 }, 5872 outputs: []outputInfo{ 5873 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5874 }, 5875 }, 5876 }, 5877 { 5878 name: "MOVSDloadidx8", 5879 auxType: auxSymOff, 5880 argLen: 3, 5881 symEffect: SymRead, 5882 asm: x86.AMOVSD, 5883 reg: regInfo{ 5884 inputs: []inputInfo{ 5885 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5886 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5887 }, 5888 outputs: []outputInfo{ 5889 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5890 }, 5891 }, 5892 }, 5893 { 5894 name: "MOVSSstore", 5895 auxType: auxSymOff, 5896 argLen: 3, 5897 faultOnNilArg0: true, 5898 symEffect: SymWrite, 5899 asm: x86.AMOVSS, 5900 reg: regInfo{ 5901 inputs: []inputInfo{ 5902 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5903 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5904 }, 5905 }, 5906 }, 5907 { 5908 name: "MOVSDstore", 5909 auxType: auxSymOff, 5910 argLen: 3, 5911 faultOnNilArg0: true, 5912 symEffect: SymWrite, 5913 asm: x86.AMOVSD, 5914 reg: regInfo{ 5915 inputs: []inputInfo{ 5916 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5917 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5918 }, 5919 }, 5920 }, 5921 { 5922 name: "MOVSSstoreidx1", 5923 auxType: auxSymOff, 5924 argLen: 4, 5925 symEffect: SymWrite, 5926 asm: x86.AMOVSS, 5927 reg: regInfo{ 5928 inputs: []inputInfo{ 5929 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5930 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5931 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5932 }, 5933 }, 5934 }, 5935 { 5936 name: "MOVSSstoreidx4", 5937 auxType: auxSymOff, 5938 argLen: 4, 5939 symEffect: SymWrite, 5940 asm: x86.AMOVSS, 5941 reg: regInfo{ 5942 inputs: []inputInfo{ 5943 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5944 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5945 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5946 }, 5947 }, 5948 }, 5949 { 5950 name: "MOVSDstoreidx1", 5951 auxType: auxSymOff, 5952 argLen: 4, 5953 symEffect: SymWrite, 5954 asm: x86.AMOVSD, 5955 reg: regInfo{ 5956 inputs: []inputInfo{ 5957 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5958 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5959 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5960 }, 5961 }, 5962 }, 5963 { 5964 name: "MOVSDstoreidx8", 5965 auxType: auxSymOff, 5966 argLen: 4, 5967 symEffect: SymWrite, 5968 asm: x86.AMOVSD, 5969 reg: regInfo{ 5970 inputs: []inputInfo{ 5971 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5972 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5973 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5974 }, 5975 }, 5976 }, 5977 { 5978 name: "ADDSSload", 5979 auxType: auxSymOff, 5980 argLen: 3, 5981 resultInArg0: true, 5982 faultOnNilArg1: true, 5983 symEffect: SymRead, 5984 asm: x86.AADDSS, 5985 reg: regInfo{ 5986 inputs: []inputInfo{ 5987 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5988 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5989 }, 5990 outputs: []outputInfo{ 5991 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5992 }, 5993 }, 5994 }, 5995 { 5996 name: "ADDSDload", 5997 auxType: auxSymOff, 5998 argLen: 3, 5999 resultInArg0: true, 6000 faultOnNilArg1: true, 6001 symEffect: SymRead, 6002 asm: x86.AADDSD, 6003 reg: regInfo{ 6004 inputs: []inputInfo{ 6005 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6006 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6007 }, 6008 outputs: []outputInfo{ 6009 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6010 }, 6011 }, 6012 }, 6013 { 6014 name: "SUBSSload", 6015 auxType: auxSymOff, 6016 argLen: 3, 6017 resultInArg0: true, 6018 faultOnNilArg1: true, 6019 symEffect: SymRead, 6020 asm: x86.ASUBSS, 6021 reg: regInfo{ 6022 inputs: []inputInfo{ 6023 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6024 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6025 }, 6026 outputs: []outputInfo{ 6027 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6028 }, 6029 }, 6030 }, 6031 { 6032 name: "SUBSDload", 6033 auxType: auxSymOff, 6034 argLen: 3, 6035 resultInArg0: true, 6036 faultOnNilArg1: true, 6037 symEffect: SymRead, 6038 asm: x86.ASUBSD, 6039 reg: regInfo{ 6040 inputs: []inputInfo{ 6041 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6042 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6043 }, 6044 outputs: []outputInfo{ 6045 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6046 }, 6047 }, 6048 }, 6049 { 6050 name: "MULSSload", 6051 auxType: auxSymOff, 6052 argLen: 3, 6053 resultInArg0: true, 6054 faultOnNilArg1: true, 6055 symEffect: SymRead, 6056 asm: x86.AMULSS, 6057 reg: regInfo{ 6058 inputs: []inputInfo{ 6059 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6060 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6061 }, 6062 outputs: []outputInfo{ 6063 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6064 }, 6065 }, 6066 }, 6067 { 6068 name: "MULSDload", 6069 auxType: auxSymOff, 6070 argLen: 3, 6071 resultInArg0: true, 6072 faultOnNilArg1: true, 6073 symEffect: SymRead, 6074 asm: x86.AMULSD, 6075 reg: regInfo{ 6076 inputs: []inputInfo{ 6077 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6078 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6079 }, 6080 outputs: []outputInfo{ 6081 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6082 }, 6083 }, 6084 }, 6085 { 6086 name: "DIVSSload", 6087 auxType: auxSymOff, 6088 argLen: 3, 6089 resultInArg0: true, 6090 faultOnNilArg1: true, 6091 symEffect: SymRead, 6092 asm: x86.ADIVSS, 6093 reg: regInfo{ 6094 inputs: []inputInfo{ 6095 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6096 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6097 }, 6098 outputs: []outputInfo{ 6099 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6100 }, 6101 }, 6102 }, 6103 { 6104 name: "DIVSDload", 6105 auxType: auxSymOff, 6106 argLen: 3, 6107 resultInArg0: true, 6108 faultOnNilArg1: true, 6109 symEffect: SymRead, 6110 asm: x86.ADIVSD, 6111 reg: regInfo{ 6112 inputs: []inputInfo{ 6113 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6114 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6115 }, 6116 outputs: []outputInfo{ 6117 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6118 }, 6119 }, 6120 }, 6121 { 6122 name: "ADDQ", 6123 argLen: 2, 6124 commutative: true, 6125 clobberFlags: true, 6126 asm: x86.AADDQ, 6127 reg: regInfo{ 6128 inputs: []inputInfo{ 6129 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6130 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6131 }, 6132 outputs: []outputInfo{ 6133 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6134 }, 6135 }, 6136 }, 6137 { 6138 name: "ADDL", 6139 argLen: 2, 6140 commutative: true, 6141 clobberFlags: true, 6142 asm: x86.AADDL, 6143 reg: regInfo{ 6144 inputs: []inputInfo{ 6145 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6146 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6147 }, 6148 outputs: []outputInfo{ 6149 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6150 }, 6151 }, 6152 }, 6153 { 6154 name: "ADDQconst", 6155 auxType: auxInt32, 6156 argLen: 1, 6157 clobberFlags: true, 6158 asm: x86.AADDQ, 6159 reg: regInfo{ 6160 inputs: []inputInfo{ 6161 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6162 }, 6163 outputs: []outputInfo{ 6164 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6165 }, 6166 }, 6167 }, 6168 { 6169 name: "ADDLconst", 6170 auxType: auxInt32, 6171 argLen: 1, 6172 clobberFlags: true, 6173 asm: x86.AADDL, 6174 reg: regInfo{ 6175 inputs: []inputInfo{ 6176 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6177 }, 6178 outputs: []outputInfo{ 6179 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6180 }, 6181 }, 6182 }, 6183 { 6184 name: "ADDQconstmodify", 6185 auxType: auxSymValAndOff, 6186 argLen: 2, 6187 clobberFlags: true, 6188 faultOnNilArg0: true, 6189 symEffect: SymRead | SymWrite, 6190 asm: x86.AADDQ, 6191 reg: regInfo{ 6192 inputs: []inputInfo{ 6193 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6194 }, 6195 }, 6196 }, 6197 { 6198 name: "ADDLconstmodify", 6199 auxType: auxSymValAndOff, 6200 argLen: 2, 6201 clobberFlags: true, 6202 faultOnNilArg0: true, 6203 symEffect: SymRead | SymWrite, 6204 asm: x86.AADDL, 6205 reg: regInfo{ 6206 inputs: []inputInfo{ 6207 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6208 }, 6209 }, 6210 }, 6211 { 6212 name: "SUBQ", 6213 argLen: 2, 6214 resultInArg0: true, 6215 clobberFlags: true, 6216 asm: x86.ASUBQ, 6217 reg: regInfo{ 6218 inputs: []inputInfo{ 6219 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6220 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6221 }, 6222 outputs: []outputInfo{ 6223 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6224 }, 6225 }, 6226 }, 6227 { 6228 name: "SUBL", 6229 argLen: 2, 6230 resultInArg0: true, 6231 clobberFlags: true, 6232 asm: x86.ASUBL, 6233 reg: regInfo{ 6234 inputs: []inputInfo{ 6235 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6236 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6237 }, 6238 outputs: []outputInfo{ 6239 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6240 }, 6241 }, 6242 }, 6243 { 6244 name: "SUBQconst", 6245 auxType: auxInt32, 6246 argLen: 1, 6247 resultInArg0: true, 6248 clobberFlags: true, 6249 asm: x86.ASUBQ, 6250 reg: regInfo{ 6251 inputs: []inputInfo{ 6252 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6253 }, 6254 outputs: []outputInfo{ 6255 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6256 }, 6257 }, 6258 }, 6259 { 6260 name: "SUBLconst", 6261 auxType: auxInt32, 6262 argLen: 1, 6263 resultInArg0: true, 6264 clobberFlags: true, 6265 asm: x86.ASUBL, 6266 reg: regInfo{ 6267 inputs: []inputInfo{ 6268 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6269 }, 6270 outputs: []outputInfo{ 6271 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6272 }, 6273 }, 6274 }, 6275 { 6276 name: "MULQ", 6277 argLen: 2, 6278 commutative: true, 6279 resultInArg0: true, 6280 clobberFlags: true, 6281 asm: x86.AIMULQ, 6282 reg: regInfo{ 6283 inputs: []inputInfo{ 6284 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6285 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6286 }, 6287 outputs: []outputInfo{ 6288 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6289 }, 6290 }, 6291 }, 6292 { 6293 name: "MULL", 6294 argLen: 2, 6295 commutative: true, 6296 resultInArg0: true, 6297 clobberFlags: true, 6298 asm: x86.AIMULL, 6299 reg: regInfo{ 6300 inputs: []inputInfo{ 6301 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6302 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6303 }, 6304 outputs: []outputInfo{ 6305 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6306 }, 6307 }, 6308 }, 6309 { 6310 name: "MULQconst", 6311 auxType: auxInt32, 6312 argLen: 1, 6313 clobberFlags: true, 6314 asm: x86.AIMUL3Q, 6315 reg: regInfo{ 6316 inputs: []inputInfo{ 6317 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6318 }, 6319 outputs: []outputInfo{ 6320 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6321 }, 6322 }, 6323 }, 6324 { 6325 name: "MULLconst", 6326 auxType: auxInt32, 6327 argLen: 1, 6328 clobberFlags: true, 6329 asm: x86.AIMUL3L, 6330 reg: regInfo{ 6331 inputs: []inputInfo{ 6332 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6333 }, 6334 outputs: []outputInfo{ 6335 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6336 }, 6337 }, 6338 }, 6339 { 6340 name: "MULLU", 6341 argLen: 2, 6342 commutative: true, 6343 clobberFlags: true, 6344 asm: x86.AMULL, 6345 reg: regInfo{ 6346 inputs: []inputInfo{ 6347 {0, 1}, // AX 6348 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6349 }, 6350 clobbers: 4, // DX 6351 outputs: []outputInfo{ 6352 {1, 0}, 6353 {0, 1}, // AX 6354 }, 6355 }, 6356 }, 6357 { 6358 name: "MULQU", 6359 argLen: 2, 6360 commutative: true, 6361 clobberFlags: true, 6362 asm: x86.AMULQ, 6363 reg: regInfo{ 6364 inputs: []inputInfo{ 6365 {0, 1}, // AX 6366 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6367 }, 6368 clobbers: 4, // DX 6369 outputs: []outputInfo{ 6370 {1, 0}, 6371 {0, 1}, // AX 6372 }, 6373 }, 6374 }, 6375 { 6376 name: "HMULQ", 6377 argLen: 2, 6378 commutative: true, 6379 clobberFlags: true, 6380 asm: x86.AIMULQ, 6381 reg: regInfo{ 6382 inputs: []inputInfo{ 6383 {0, 1}, // AX 6384 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6385 }, 6386 clobbers: 1, // AX 6387 outputs: []outputInfo{ 6388 {0, 4}, // DX 6389 }, 6390 }, 6391 }, 6392 { 6393 name: "HMULL", 6394 argLen: 2, 6395 commutative: true, 6396 clobberFlags: true, 6397 asm: x86.AIMULL, 6398 reg: regInfo{ 6399 inputs: []inputInfo{ 6400 {0, 1}, // AX 6401 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6402 }, 6403 clobbers: 1, // AX 6404 outputs: []outputInfo{ 6405 {0, 4}, // DX 6406 }, 6407 }, 6408 }, 6409 { 6410 name: "HMULQU", 6411 argLen: 2, 6412 commutative: true, 6413 clobberFlags: true, 6414 asm: x86.AMULQ, 6415 reg: regInfo{ 6416 inputs: []inputInfo{ 6417 {0, 1}, // AX 6418 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6419 }, 6420 clobbers: 1, // AX 6421 outputs: []outputInfo{ 6422 {0, 4}, // DX 6423 }, 6424 }, 6425 }, 6426 { 6427 name: "HMULLU", 6428 argLen: 2, 6429 commutative: true, 6430 clobberFlags: true, 6431 asm: x86.AMULL, 6432 reg: regInfo{ 6433 inputs: []inputInfo{ 6434 {0, 1}, // AX 6435 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6436 }, 6437 clobbers: 1, // AX 6438 outputs: []outputInfo{ 6439 {0, 4}, // DX 6440 }, 6441 }, 6442 }, 6443 { 6444 name: "AVGQU", 6445 argLen: 2, 6446 commutative: true, 6447 resultInArg0: true, 6448 clobberFlags: true, 6449 reg: regInfo{ 6450 inputs: []inputInfo{ 6451 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6452 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6453 }, 6454 outputs: []outputInfo{ 6455 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6456 }, 6457 }, 6458 }, 6459 { 6460 name: "DIVQ", 6461 auxType: auxBool, 6462 argLen: 2, 6463 clobberFlags: true, 6464 asm: x86.AIDIVQ, 6465 reg: regInfo{ 6466 inputs: []inputInfo{ 6467 {0, 1}, // AX 6468 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6469 }, 6470 outputs: []outputInfo{ 6471 {0, 1}, // AX 6472 {1, 4}, // DX 6473 }, 6474 }, 6475 }, 6476 { 6477 name: "DIVL", 6478 auxType: auxBool, 6479 argLen: 2, 6480 clobberFlags: true, 6481 asm: x86.AIDIVL, 6482 reg: regInfo{ 6483 inputs: []inputInfo{ 6484 {0, 1}, // AX 6485 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6486 }, 6487 outputs: []outputInfo{ 6488 {0, 1}, // AX 6489 {1, 4}, // DX 6490 }, 6491 }, 6492 }, 6493 { 6494 name: "DIVW", 6495 auxType: auxBool, 6496 argLen: 2, 6497 clobberFlags: true, 6498 asm: x86.AIDIVW, 6499 reg: regInfo{ 6500 inputs: []inputInfo{ 6501 {0, 1}, // AX 6502 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6503 }, 6504 outputs: []outputInfo{ 6505 {0, 1}, // AX 6506 {1, 4}, // DX 6507 }, 6508 }, 6509 }, 6510 { 6511 name: "DIVQU", 6512 argLen: 2, 6513 clobberFlags: true, 6514 asm: x86.ADIVQ, 6515 reg: regInfo{ 6516 inputs: []inputInfo{ 6517 {0, 1}, // AX 6518 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6519 }, 6520 outputs: []outputInfo{ 6521 {0, 1}, // AX 6522 {1, 4}, // DX 6523 }, 6524 }, 6525 }, 6526 { 6527 name: "DIVLU", 6528 argLen: 2, 6529 clobberFlags: true, 6530 asm: x86.ADIVL, 6531 reg: regInfo{ 6532 inputs: []inputInfo{ 6533 {0, 1}, // AX 6534 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6535 }, 6536 outputs: []outputInfo{ 6537 {0, 1}, // AX 6538 {1, 4}, // DX 6539 }, 6540 }, 6541 }, 6542 { 6543 name: "DIVWU", 6544 argLen: 2, 6545 clobberFlags: true, 6546 asm: x86.ADIVW, 6547 reg: regInfo{ 6548 inputs: []inputInfo{ 6549 {0, 1}, // AX 6550 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6551 }, 6552 outputs: []outputInfo{ 6553 {0, 1}, // AX 6554 {1, 4}, // DX 6555 }, 6556 }, 6557 }, 6558 { 6559 name: "NEGLflags", 6560 argLen: 1, 6561 resultInArg0: true, 6562 asm: x86.ANEGL, 6563 reg: regInfo{ 6564 inputs: []inputInfo{ 6565 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6566 }, 6567 outputs: []outputInfo{ 6568 {1, 0}, 6569 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6570 }, 6571 }, 6572 }, 6573 { 6574 name: "ADDQcarry", 6575 argLen: 2, 6576 commutative: true, 6577 resultInArg0: true, 6578 asm: x86.AADDQ, 6579 reg: regInfo{ 6580 inputs: []inputInfo{ 6581 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6582 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6583 }, 6584 outputs: []outputInfo{ 6585 {1, 0}, 6586 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6587 }, 6588 }, 6589 }, 6590 { 6591 name: "ADCQ", 6592 argLen: 3, 6593 commutative: true, 6594 resultInArg0: true, 6595 asm: x86.AADCQ, 6596 reg: regInfo{ 6597 inputs: []inputInfo{ 6598 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6599 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6600 }, 6601 outputs: []outputInfo{ 6602 {1, 0}, 6603 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6604 }, 6605 }, 6606 }, 6607 { 6608 name: "ADDQconstcarry", 6609 auxType: auxInt32, 6610 argLen: 1, 6611 resultInArg0: true, 6612 asm: x86.AADDQ, 6613 reg: regInfo{ 6614 inputs: []inputInfo{ 6615 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6616 }, 6617 outputs: []outputInfo{ 6618 {1, 0}, 6619 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6620 }, 6621 }, 6622 }, 6623 { 6624 name: "ADCQconst", 6625 auxType: auxInt32, 6626 argLen: 2, 6627 resultInArg0: true, 6628 asm: x86.AADCQ, 6629 reg: regInfo{ 6630 inputs: []inputInfo{ 6631 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6632 }, 6633 outputs: []outputInfo{ 6634 {1, 0}, 6635 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6636 }, 6637 }, 6638 }, 6639 { 6640 name: "SUBQborrow", 6641 argLen: 2, 6642 resultInArg0: true, 6643 asm: x86.ASUBQ, 6644 reg: regInfo{ 6645 inputs: []inputInfo{ 6646 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6647 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6648 }, 6649 outputs: []outputInfo{ 6650 {1, 0}, 6651 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6652 }, 6653 }, 6654 }, 6655 { 6656 name: "SBBQ", 6657 argLen: 3, 6658 resultInArg0: true, 6659 asm: x86.ASBBQ, 6660 reg: regInfo{ 6661 inputs: []inputInfo{ 6662 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6663 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6664 }, 6665 outputs: []outputInfo{ 6666 {1, 0}, 6667 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6668 }, 6669 }, 6670 }, 6671 { 6672 name: "SUBQconstborrow", 6673 auxType: auxInt32, 6674 argLen: 1, 6675 resultInArg0: true, 6676 asm: x86.ASUBQ, 6677 reg: regInfo{ 6678 inputs: []inputInfo{ 6679 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6680 }, 6681 outputs: []outputInfo{ 6682 {1, 0}, 6683 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6684 }, 6685 }, 6686 }, 6687 { 6688 name: "SBBQconst", 6689 auxType: auxInt32, 6690 argLen: 2, 6691 resultInArg0: true, 6692 asm: x86.ASBBQ, 6693 reg: regInfo{ 6694 inputs: []inputInfo{ 6695 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6696 }, 6697 outputs: []outputInfo{ 6698 {1, 0}, 6699 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6700 }, 6701 }, 6702 }, 6703 { 6704 name: "MULQU2", 6705 argLen: 2, 6706 commutative: true, 6707 clobberFlags: true, 6708 asm: x86.AMULQ, 6709 reg: regInfo{ 6710 inputs: []inputInfo{ 6711 {0, 1}, // AX 6712 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6713 }, 6714 outputs: []outputInfo{ 6715 {0, 4}, // DX 6716 {1, 1}, // AX 6717 }, 6718 }, 6719 }, 6720 { 6721 name: "DIVQU2", 6722 argLen: 3, 6723 clobberFlags: true, 6724 asm: x86.ADIVQ, 6725 reg: regInfo{ 6726 inputs: []inputInfo{ 6727 {0, 4}, // DX 6728 {1, 1}, // AX 6729 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6730 }, 6731 outputs: []outputInfo{ 6732 {0, 1}, // AX 6733 {1, 4}, // DX 6734 }, 6735 }, 6736 }, 6737 { 6738 name: "ANDQ", 6739 argLen: 2, 6740 commutative: true, 6741 resultInArg0: true, 6742 clobberFlags: true, 6743 asm: x86.AANDQ, 6744 reg: regInfo{ 6745 inputs: []inputInfo{ 6746 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6747 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6748 }, 6749 outputs: []outputInfo{ 6750 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6751 }, 6752 }, 6753 }, 6754 { 6755 name: "ANDL", 6756 argLen: 2, 6757 commutative: true, 6758 resultInArg0: true, 6759 clobberFlags: true, 6760 asm: x86.AANDL, 6761 reg: regInfo{ 6762 inputs: []inputInfo{ 6763 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6764 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6765 }, 6766 outputs: []outputInfo{ 6767 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6768 }, 6769 }, 6770 }, 6771 { 6772 name: "ANDQconst", 6773 auxType: auxInt32, 6774 argLen: 1, 6775 resultInArg0: true, 6776 clobberFlags: true, 6777 asm: x86.AANDQ, 6778 reg: regInfo{ 6779 inputs: []inputInfo{ 6780 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6781 }, 6782 outputs: []outputInfo{ 6783 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6784 }, 6785 }, 6786 }, 6787 { 6788 name: "ANDLconst", 6789 auxType: auxInt32, 6790 argLen: 1, 6791 resultInArg0: true, 6792 clobberFlags: true, 6793 asm: x86.AANDL, 6794 reg: regInfo{ 6795 inputs: []inputInfo{ 6796 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6797 }, 6798 outputs: []outputInfo{ 6799 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6800 }, 6801 }, 6802 }, 6803 { 6804 name: "ANDQconstmodify", 6805 auxType: auxSymValAndOff, 6806 argLen: 2, 6807 clobberFlags: true, 6808 faultOnNilArg0: true, 6809 symEffect: SymRead | SymWrite, 6810 asm: x86.AANDQ, 6811 reg: regInfo{ 6812 inputs: []inputInfo{ 6813 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6814 }, 6815 }, 6816 }, 6817 { 6818 name: "ANDLconstmodify", 6819 auxType: auxSymValAndOff, 6820 argLen: 2, 6821 clobberFlags: true, 6822 faultOnNilArg0: true, 6823 symEffect: SymRead | SymWrite, 6824 asm: x86.AANDL, 6825 reg: regInfo{ 6826 inputs: []inputInfo{ 6827 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6828 }, 6829 }, 6830 }, 6831 { 6832 name: "ORQ", 6833 argLen: 2, 6834 commutative: true, 6835 resultInArg0: true, 6836 clobberFlags: true, 6837 asm: x86.AORQ, 6838 reg: regInfo{ 6839 inputs: []inputInfo{ 6840 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6841 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6842 }, 6843 outputs: []outputInfo{ 6844 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6845 }, 6846 }, 6847 }, 6848 { 6849 name: "ORL", 6850 argLen: 2, 6851 commutative: true, 6852 resultInArg0: true, 6853 clobberFlags: true, 6854 asm: x86.AORL, 6855 reg: regInfo{ 6856 inputs: []inputInfo{ 6857 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6858 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6859 }, 6860 outputs: []outputInfo{ 6861 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6862 }, 6863 }, 6864 }, 6865 { 6866 name: "ORQconst", 6867 auxType: auxInt32, 6868 argLen: 1, 6869 resultInArg0: true, 6870 clobberFlags: true, 6871 asm: x86.AORQ, 6872 reg: regInfo{ 6873 inputs: []inputInfo{ 6874 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6875 }, 6876 outputs: []outputInfo{ 6877 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6878 }, 6879 }, 6880 }, 6881 { 6882 name: "ORLconst", 6883 auxType: auxInt32, 6884 argLen: 1, 6885 resultInArg0: true, 6886 clobberFlags: true, 6887 asm: x86.AORL, 6888 reg: regInfo{ 6889 inputs: []inputInfo{ 6890 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6891 }, 6892 outputs: []outputInfo{ 6893 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6894 }, 6895 }, 6896 }, 6897 { 6898 name: "ORQconstmodify", 6899 auxType: auxSymValAndOff, 6900 argLen: 2, 6901 clobberFlags: true, 6902 faultOnNilArg0: true, 6903 symEffect: SymRead | SymWrite, 6904 asm: x86.AORQ, 6905 reg: regInfo{ 6906 inputs: []inputInfo{ 6907 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6908 }, 6909 }, 6910 }, 6911 { 6912 name: "ORLconstmodify", 6913 auxType: auxSymValAndOff, 6914 argLen: 2, 6915 clobberFlags: true, 6916 faultOnNilArg0: true, 6917 symEffect: SymRead | SymWrite, 6918 asm: x86.AORL, 6919 reg: regInfo{ 6920 inputs: []inputInfo{ 6921 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6922 }, 6923 }, 6924 }, 6925 { 6926 name: "XORQ", 6927 argLen: 2, 6928 commutative: true, 6929 resultInArg0: true, 6930 clobberFlags: true, 6931 asm: x86.AXORQ, 6932 reg: regInfo{ 6933 inputs: []inputInfo{ 6934 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6935 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6936 }, 6937 outputs: []outputInfo{ 6938 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6939 }, 6940 }, 6941 }, 6942 { 6943 name: "XORL", 6944 argLen: 2, 6945 commutative: true, 6946 resultInArg0: true, 6947 clobberFlags: true, 6948 asm: x86.AXORL, 6949 reg: regInfo{ 6950 inputs: []inputInfo{ 6951 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6952 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6953 }, 6954 outputs: []outputInfo{ 6955 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6956 }, 6957 }, 6958 }, 6959 { 6960 name: "XORQconst", 6961 auxType: auxInt32, 6962 argLen: 1, 6963 resultInArg0: true, 6964 clobberFlags: true, 6965 asm: x86.AXORQ, 6966 reg: regInfo{ 6967 inputs: []inputInfo{ 6968 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6969 }, 6970 outputs: []outputInfo{ 6971 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6972 }, 6973 }, 6974 }, 6975 { 6976 name: "XORLconst", 6977 auxType: auxInt32, 6978 argLen: 1, 6979 resultInArg0: true, 6980 clobberFlags: true, 6981 asm: x86.AXORL, 6982 reg: regInfo{ 6983 inputs: []inputInfo{ 6984 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6985 }, 6986 outputs: []outputInfo{ 6987 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6988 }, 6989 }, 6990 }, 6991 { 6992 name: "XORQconstmodify", 6993 auxType: auxSymValAndOff, 6994 argLen: 2, 6995 clobberFlags: true, 6996 faultOnNilArg0: true, 6997 symEffect: SymRead | SymWrite, 6998 asm: x86.AXORQ, 6999 reg: regInfo{ 7000 inputs: []inputInfo{ 7001 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7002 }, 7003 }, 7004 }, 7005 { 7006 name: "XORLconstmodify", 7007 auxType: auxSymValAndOff, 7008 argLen: 2, 7009 clobberFlags: true, 7010 faultOnNilArg0: true, 7011 symEffect: SymRead | SymWrite, 7012 asm: x86.AXORL, 7013 reg: regInfo{ 7014 inputs: []inputInfo{ 7015 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7016 }, 7017 }, 7018 }, 7019 { 7020 name: "CMPQ", 7021 argLen: 2, 7022 asm: x86.ACMPQ, 7023 reg: regInfo{ 7024 inputs: []inputInfo{ 7025 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7026 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7027 }, 7028 }, 7029 }, 7030 { 7031 name: "CMPL", 7032 argLen: 2, 7033 asm: x86.ACMPL, 7034 reg: regInfo{ 7035 inputs: []inputInfo{ 7036 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7037 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7038 }, 7039 }, 7040 }, 7041 { 7042 name: "CMPW", 7043 argLen: 2, 7044 asm: x86.ACMPW, 7045 reg: regInfo{ 7046 inputs: []inputInfo{ 7047 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7048 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7049 }, 7050 }, 7051 }, 7052 { 7053 name: "CMPB", 7054 argLen: 2, 7055 asm: x86.ACMPB, 7056 reg: regInfo{ 7057 inputs: []inputInfo{ 7058 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7059 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7060 }, 7061 }, 7062 }, 7063 { 7064 name: "CMPQconst", 7065 auxType: auxInt32, 7066 argLen: 1, 7067 asm: x86.ACMPQ, 7068 reg: regInfo{ 7069 inputs: []inputInfo{ 7070 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7071 }, 7072 }, 7073 }, 7074 { 7075 name: "CMPLconst", 7076 auxType: auxInt32, 7077 argLen: 1, 7078 asm: x86.ACMPL, 7079 reg: regInfo{ 7080 inputs: []inputInfo{ 7081 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7082 }, 7083 }, 7084 }, 7085 { 7086 name: "CMPWconst", 7087 auxType: auxInt16, 7088 argLen: 1, 7089 asm: x86.ACMPW, 7090 reg: regInfo{ 7091 inputs: []inputInfo{ 7092 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7093 }, 7094 }, 7095 }, 7096 { 7097 name: "CMPBconst", 7098 auxType: auxInt8, 7099 argLen: 1, 7100 asm: x86.ACMPB, 7101 reg: regInfo{ 7102 inputs: []inputInfo{ 7103 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7104 }, 7105 }, 7106 }, 7107 { 7108 name: "CMPQload", 7109 auxType: auxSymOff, 7110 argLen: 3, 7111 faultOnNilArg0: true, 7112 symEffect: SymRead, 7113 asm: x86.ACMPQ, 7114 reg: regInfo{ 7115 inputs: []inputInfo{ 7116 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7117 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7118 }, 7119 }, 7120 }, 7121 { 7122 name: "CMPLload", 7123 auxType: auxSymOff, 7124 argLen: 3, 7125 faultOnNilArg0: true, 7126 symEffect: SymRead, 7127 asm: x86.ACMPL, 7128 reg: regInfo{ 7129 inputs: []inputInfo{ 7130 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7131 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7132 }, 7133 }, 7134 }, 7135 { 7136 name: "CMPWload", 7137 auxType: auxSymOff, 7138 argLen: 3, 7139 faultOnNilArg0: true, 7140 symEffect: SymRead, 7141 asm: x86.ACMPW, 7142 reg: regInfo{ 7143 inputs: []inputInfo{ 7144 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7145 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7146 }, 7147 }, 7148 }, 7149 { 7150 name: "CMPBload", 7151 auxType: auxSymOff, 7152 argLen: 3, 7153 faultOnNilArg0: true, 7154 symEffect: SymRead, 7155 asm: x86.ACMPB, 7156 reg: regInfo{ 7157 inputs: []inputInfo{ 7158 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7159 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7160 }, 7161 }, 7162 }, 7163 { 7164 name: "CMPQconstload", 7165 auxType: auxSymValAndOff, 7166 argLen: 2, 7167 faultOnNilArg0: true, 7168 symEffect: SymRead, 7169 asm: x86.ACMPQ, 7170 reg: regInfo{ 7171 inputs: []inputInfo{ 7172 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7173 }, 7174 }, 7175 }, 7176 { 7177 name: "CMPLconstload", 7178 auxType: auxSymValAndOff, 7179 argLen: 2, 7180 faultOnNilArg0: true, 7181 symEffect: SymRead, 7182 asm: x86.ACMPL, 7183 reg: regInfo{ 7184 inputs: []inputInfo{ 7185 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7186 }, 7187 }, 7188 }, 7189 { 7190 name: "CMPWconstload", 7191 auxType: auxSymValAndOff, 7192 argLen: 2, 7193 faultOnNilArg0: true, 7194 symEffect: SymRead, 7195 asm: x86.ACMPW, 7196 reg: regInfo{ 7197 inputs: []inputInfo{ 7198 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7199 }, 7200 }, 7201 }, 7202 { 7203 name: "CMPBconstload", 7204 auxType: auxSymValAndOff, 7205 argLen: 2, 7206 faultOnNilArg0: true, 7207 symEffect: SymRead, 7208 asm: x86.ACMPB, 7209 reg: regInfo{ 7210 inputs: []inputInfo{ 7211 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7212 }, 7213 }, 7214 }, 7215 { 7216 name: "UCOMISS", 7217 argLen: 2, 7218 asm: x86.AUCOMISS, 7219 reg: regInfo{ 7220 inputs: []inputInfo{ 7221 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7222 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7223 }, 7224 }, 7225 }, 7226 { 7227 name: "UCOMISD", 7228 argLen: 2, 7229 asm: x86.AUCOMISD, 7230 reg: regInfo{ 7231 inputs: []inputInfo{ 7232 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7233 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7234 }, 7235 }, 7236 }, 7237 { 7238 name: "BTL", 7239 argLen: 2, 7240 asm: x86.ABTL, 7241 reg: regInfo{ 7242 inputs: []inputInfo{ 7243 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7244 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7245 }, 7246 }, 7247 }, 7248 { 7249 name: "BTQ", 7250 argLen: 2, 7251 asm: x86.ABTQ, 7252 reg: regInfo{ 7253 inputs: []inputInfo{ 7254 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7255 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7256 }, 7257 }, 7258 }, 7259 { 7260 name: "BTCL", 7261 argLen: 2, 7262 resultInArg0: true, 7263 clobberFlags: true, 7264 asm: x86.ABTCL, 7265 reg: regInfo{ 7266 inputs: []inputInfo{ 7267 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7268 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7269 }, 7270 outputs: []outputInfo{ 7271 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7272 }, 7273 }, 7274 }, 7275 { 7276 name: "BTCQ", 7277 argLen: 2, 7278 resultInArg0: true, 7279 clobberFlags: true, 7280 asm: x86.ABTCQ, 7281 reg: regInfo{ 7282 inputs: []inputInfo{ 7283 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7284 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7285 }, 7286 outputs: []outputInfo{ 7287 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7288 }, 7289 }, 7290 }, 7291 { 7292 name: "BTRL", 7293 argLen: 2, 7294 resultInArg0: true, 7295 clobberFlags: true, 7296 asm: x86.ABTRL, 7297 reg: regInfo{ 7298 inputs: []inputInfo{ 7299 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7300 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7301 }, 7302 outputs: []outputInfo{ 7303 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7304 }, 7305 }, 7306 }, 7307 { 7308 name: "BTRQ", 7309 argLen: 2, 7310 resultInArg0: true, 7311 clobberFlags: true, 7312 asm: x86.ABTRQ, 7313 reg: regInfo{ 7314 inputs: []inputInfo{ 7315 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7316 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7317 }, 7318 outputs: []outputInfo{ 7319 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7320 }, 7321 }, 7322 }, 7323 { 7324 name: "BTSL", 7325 argLen: 2, 7326 resultInArg0: true, 7327 clobberFlags: true, 7328 asm: x86.ABTSL, 7329 reg: regInfo{ 7330 inputs: []inputInfo{ 7331 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7332 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7333 }, 7334 outputs: []outputInfo{ 7335 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7336 }, 7337 }, 7338 }, 7339 { 7340 name: "BTSQ", 7341 argLen: 2, 7342 resultInArg0: true, 7343 clobberFlags: true, 7344 asm: x86.ABTSQ, 7345 reg: regInfo{ 7346 inputs: []inputInfo{ 7347 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7348 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7349 }, 7350 outputs: []outputInfo{ 7351 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7352 }, 7353 }, 7354 }, 7355 { 7356 name: "BTLconst", 7357 auxType: auxInt8, 7358 argLen: 1, 7359 asm: x86.ABTL, 7360 reg: regInfo{ 7361 inputs: []inputInfo{ 7362 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7363 }, 7364 }, 7365 }, 7366 { 7367 name: "BTQconst", 7368 auxType: auxInt8, 7369 argLen: 1, 7370 asm: x86.ABTQ, 7371 reg: regInfo{ 7372 inputs: []inputInfo{ 7373 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7374 }, 7375 }, 7376 }, 7377 { 7378 name: "BTCLconst", 7379 auxType: auxInt8, 7380 argLen: 1, 7381 resultInArg0: true, 7382 clobberFlags: true, 7383 asm: x86.ABTCL, 7384 reg: regInfo{ 7385 inputs: []inputInfo{ 7386 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7387 }, 7388 outputs: []outputInfo{ 7389 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7390 }, 7391 }, 7392 }, 7393 { 7394 name: "BTCQconst", 7395 auxType: auxInt8, 7396 argLen: 1, 7397 resultInArg0: true, 7398 clobberFlags: true, 7399 asm: x86.ABTCQ, 7400 reg: regInfo{ 7401 inputs: []inputInfo{ 7402 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7403 }, 7404 outputs: []outputInfo{ 7405 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7406 }, 7407 }, 7408 }, 7409 { 7410 name: "BTRLconst", 7411 auxType: auxInt8, 7412 argLen: 1, 7413 resultInArg0: true, 7414 clobberFlags: true, 7415 asm: x86.ABTRL, 7416 reg: regInfo{ 7417 inputs: []inputInfo{ 7418 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7419 }, 7420 outputs: []outputInfo{ 7421 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7422 }, 7423 }, 7424 }, 7425 { 7426 name: "BTRQconst", 7427 auxType: auxInt8, 7428 argLen: 1, 7429 resultInArg0: true, 7430 clobberFlags: true, 7431 asm: x86.ABTRQ, 7432 reg: regInfo{ 7433 inputs: []inputInfo{ 7434 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7435 }, 7436 outputs: []outputInfo{ 7437 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7438 }, 7439 }, 7440 }, 7441 { 7442 name: "BTSLconst", 7443 auxType: auxInt8, 7444 argLen: 1, 7445 resultInArg0: true, 7446 clobberFlags: true, 7447 asm: x86.ABTSL, 7448 reg: regInfo{ 7449 inputs: []inputInfo{ 7450 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7451 }, 7452 outputs: []outputInfo{ 7453 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7454 }, 7455 }, 7456 }, 7457 { 7458 name: "BTSQconst", 7459 auxType: auxInt8, 7460 argLen: 1, 7461 resultInArg0: true, 7462 clobberFlags: true, 7463 asm: x86.ABTSQ, 7464 reg: regInfo{ 7465 inputs: []inputInfo{ 7466 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7467 }, 7468 outputs: []outputInfo{ 7469 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7470 }, 7471 }, 7472 }, 7473 { 7474 name: "BTCQmodify", 7475 auxType: auxSymOff, 7476 argLen: 3, 7477 clobberFlags: true, 7478 faultOnNilArg0: true, 7479 symEffect: SymRead | SymWrite, 7480 asm: x86.ABTCQ, 7481 reg: regInfo{ 7482 inputs: []inputInfo{ 7483 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7484 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7485 }, 7486 }, 7487 }, 7488 { 7489 name: "BTCLmodify", 7490 auxType: auxSymOff, 7491 argLen: 3, 7492 clobberFlags: true, 7493 faultOnNilArg0: true, 7494 symEffect: SymRead | SymWrite, 7495 asm: x86.ABTCL, 7496 reg: regInfo{ 7497 inputs: []inputInfo{ 7498 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7499 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7500 }, 7501 }, 7502 }, 7503 { 7504 name: "BTSQmodify", 7505 auxType: auxSymOff, 7506 argLen: 3, 7507 clobberFlags: true, 7508 faultOnNilArg0: true, 7509 symEffect: SymRead | SymWrite, 7510 asm: x86.ABTSQ, 7511 reg: regInfo{ 7512 inputs: []inputInfo{ 7513 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7514 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7515 }, 7516 }, 7517 }, 7518 { 7519 name: "BTSLmodify", 7520 auxType: auxSymOff, 7521 argLen: 3, 7522 clobberFlags: true, 7523 faultOnNilArg0: true, 7524 symEffect: SymRead | SymWrite, 7525 asm: x86.ABTSL, 7526 reg: regInfo{ 7527 inputs: []inputInfo{ 7528 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7529 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7530 }, 7531 }, 7532 }, 7533 { 7534 name: "BTRQmodify", 7535 auxType: auxSymOff, 7536 argLen: 3, 7537 clobberFlags: true, 7538 faultOnNilArg0: true, 7539 symEffect: SymRead | SymWrite, 7540 asm: x86.ABTRQ, 7541 reg: regInfo{ 7542 inputs: []inputInfo{ 7543 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7544 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7545 }, 7546 }, 7547 }, 7548 { 7549 name: "BTRLmodify", 7550 auxType: auxSymOff, 7551 argLen: 3, 7552 clobberFlags: true, 7553 faultOnNilArg0: true, 7554 symEffect: SymRead | SymWrite, 7555 asm: x86.ABTRL, 7556 reg: regInfo{ 7557 inputs: []inputInfo{ 7558 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7559 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7560 }, 7561 }, 7562 }, 7563 { 7564 name: "BTCQconstmodify", 7565 auxType: auxSymValAndOff, 7566 argLen: 2, 7567 clobberFlags: true, 7568 faultOnNilArg0: true, 7569 symEffect: SymRead | SymWrite, 7570 asm: x86.ABTCQ, 7571 reg: regInfo{ 7572 inputs: []inputInfo{ 7573 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7574 }, 7575 }, 7576 }, 7577 { 7578 name: "BTCLconstmodify", 7579 auxType: auxSymValAndOff, 7580 argLen: 2, 7581 clobberFlags: true, 7582 faultOnNilArg0: true, 7583 symEffect: SymRead | SymWrite, 7584 asm: x86.ABTCL, 7585 reg: regInfo{ 7586 inputs: []inputInfo{ 7587 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7588 }, 7589 }, 7590 }, 7591 { 7592 name: "BTSQconstmodify", 7593 auxType: auxSymValAndOff, 7594 argLen: 2, 7595 clobberFlags: true, 7596 faultOnNilArg0: true, 7597 symEffect: SymRead | SymWrite, 7598 asm: x86.ABTSQ, 7599 reg: regInfo{ 7600 inputs: []inputInfo{ 7601 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7602 }, 7603 }, 7604 }, 7605 { 7606 name: "BTSLconstmodify", 7607 auxType: auxSymValAndOff, 7608 argLen: 2, 7609 clobberFlags: true, 7610 faultOnNilArg0: true, 7611 symEffect: SymRead | SymWrite, 7612 asm: x86.ABTSL, 7613 reg: regInfo{ 7614 inputs: []inputInfo{ 7615 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7616 }, 7617 }, 7618 }, 7619 { 7620 name: "BTRQconstmodify", 7621 auxType: auxSymValAndOff, 7622 argLen: 2, 7623 clobberFlags: true, 7624 faultOnNilArg0: true, 7625 symEffect: SymRead | SymWrite, 7626 asm: x86.ABTRQ, 7627 reg: regInfo{ 7628 inputs: []inputInfo{ 7629 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7630 }, 7631 }, 7632 }, 7633 { 7634 name: "BTRLconstmodify", 7635 auxType: auxSymValAndOff, 7636 argLen: 2, 7637 clobberFlags: true, 7638 faultOnNilArg0: true, 7639 symEffect: SymRead | SymWrite, 7640 asm: x86.ABTRL, 7641 reg: regInfo{ 7642 inputs: []inputInfo{ 7643 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7644 }, 7645 }, 7646 }, 7647 { 7648 name: "TESTQ", 7649 argLen: 2, 7650 commutative: true, 7651 asm: x86.ATESTQ, 7652 reg: regInfo{ 7653 inputs: []inputInfo{ 7654 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7655 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7656 }, 7657 }, 7658 }, 7659 { 7660 name: "TESTL", 7661 argLen: 2, 7662 commutative: true, 7663 asm: x86.ATESTL, 7664 reg: regInfo{ 7665 inputs: []inputInfo{ 7666 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7667 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7668 }, 7669 }, 7670 }, 7671 { 7672 name: "TESTW", 7673 argLen: 2, 7674 commutative: true, 7675 asm: x86.ATESTW, 7676 reg: regInfo{ 7677 inputs: []inputInfo{ 7678 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7679 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7680 }, 7681 }, 7682 }, 7683 { 7684 name: "TESTB", 7685 argLen: 2, 7686 commutative: true, 7687 asm: x86.ATESTB, 7688 reg: regInfo{ 7689 inputs: []inputInfo{ 7690 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7691 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7692 }, 7693 }, 7694 }, 7695 { 7696 name: "TESTQconst", 7697 auxType: auxInt32, 7698 argLen: 1, 7699 asm: x86.ATESTQ, 7700 reg: regInfo{ 7701 inputs: []inputInfo{ 7702 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7703 }, 7704 }, 7705 }, 7706 { 7707 name: "TESTLconst", 7708 auxType: auxInt32, 7709 argLen: 1, 7710 asm: x86.ATESTL, 7711 reg: regInfo{ 7712 inputs: []inputInfo{ 7713 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7714 }, 7715 }, 7716 }, 7717 { 7718 name: "TESTWconst", 7719 auxType: auxInt16, 7720 argLen: 1, 7721 asm: x86.ATESTW, 7722 reg: regInfo{ 7723 inputs: []inputInfo{ 7724 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7725 }, 7726 }, 7727 }, 7728 { 7729 name: "TESTBconst", 7730 auxType: auxInt8, 7731 argLen: 1, 7732 asm: x86.ATESTB, 7733 reg: regInfo{ 7734 inputs: []inputInfo{ 7735 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7736 }, 7737 }, 7738 }, 7739 { 7740 name: "SHLQ", 7741 argLen: 2, 7742 resultInArg0: true, 7743 clobberFlags: true, 7744 asm: x86.ASHLQ, 7745 reg: regInfo{ 7746 inputs: []inputInfo{ 7747 {1, 2}, // CX 7748 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7749 }, 7750 outputs: []outputInfo{ 7751 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7752 }, 7753 }, 7754 }, 7755 { 7756 name: "SHLL", 7757 argLen: 2, 7758 resultInArg0: true, 7759 clobberFlags: true, 7760 asm: x86.ASHLL, 7761 reg: regInfo{ 7762 inputs: []inputInfo{ 7763 {1, 2}, // CX 7764 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7765 }, 7766 outputs: []outputInfo{ 7767 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7768 }, 7769 }, 7770 }, 7771 { 7772 name: "SHLQconst", 7773 auxType: auxInt8, 7774 argLen: 1, 7775 resultInArg0: true, 7776 clobberFlags: true, 7777 asm: x86.ASHLQ, 7778 reg: regInfo{ 7779 inputs: []inputInfo{ 7780 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7781 }, 7782 outputs: []outputInfo{ 7783 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7784 }, 7785 }, 7786 }, 7787 { 7788 name: "SHLLconst", 7789 auxType: auxInt8, 7790 argLen: 1, 7791 resultInArg0: true, 7792 clobberFlags: true, 7793 asm: x86.ASHLL, 7794 reg: regInfo{ 7795 inputs: []inputInfo{ 7796 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7797 }, 7798 outputs: []outputInfo{ 7799 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7800 }, 7801 }, 7802 }, 7803 { 7804 name: "SHRQ", 7805 argLen: 2, 7806 resultInArg0: true, 7807 clobberFlags: true, 7808 asm: x86.ASHRQ, 7809 reg: regInfo{ 7810 inputs: []inputInfo{ 7811 {1, 2}, // CX 7812 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7813 }, 7814 outputs: []outputInfo{ 7815 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7816 }, 7817 }, 7818 }, 7819 { 7820 name: "SHRL", 7821 argLen: 2, 7822 resultInArg0: true, 7823 clobberFlags: true, 7824 asm: x86.ASHRL, 7825 reg: regInfo{ 7826 inputs: []inputInfo{ 7827 {1, 2}, // CX 7828 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7829 }, 7830 outputs: []outputInfo{ 7831 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7832 }, 7833 }, 7834 }, 7835 { 7836 name: "SHRW", 7837 argLen: 2, 7838 resultInArg0: true, 7839 clobberFlags: true, 7840 asm: x86.ASHRW, 7841 reg: regInfo{ 7842 inputs: []inputInfo{ 7843 {1, 2}, // CX 7844 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7845 }, 7846 outputs: []outputInfo{ 7847 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7848 }, 7849 }, 7850 }, 7851 { 7852 name: "SHRB", 7853 argLen: 2, 7854 resultInArg0: true, 7855 clobberFlags: true, 7856 asm: x86.ASHRB, 7857 reg: regInfo{ 7858 inputs: []inputInfo{ 7859 {1, 2}, // CX 7860 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7861 }, 7862 outputs: []outputInfo{ 7863 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7864 }, 7865 }, 7866 }, 7867 { 7868 name: "SHRQconst", 7869 auxType: auxInt8, 7870 argLen: 1, 7871 resultInArg0: true, 7872 clobberFlags: true, 7873 asm: x86.ASHRQ, 7874 reg: regInfo{ 7875 inputs: []inputInfo{ 7876 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7877 }, 7878 outputs: []outputInfo{ 7879 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7880 }, 7881 }, 7882 }, 7883 { 7884 name: "SHRLconst", 7885 auxType: auxInt8, 7886 argLen: 1, 7887 resultInArg0: true, 7888 clobberFlags: true, 7889 asm: x86.ASHRL, 7890 reg: regInfo{ 7891 inputs: []inputInfo{ 7892 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7893 }, 7894 outputs: []outputInfo{ 7895 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7896 }, 7897 }, 7898 }, 7899 { 7900 name: "SHRWconst", 7901 auxType: auxInt8, 7902 argLen: 1, 7903 resultInArg0: true, 7904 clobberFlags: true, 7905 asm: x86.ASHRW, 7906 reg: regInfo{ 7907 inputs: []inputInfo{ 7908 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7909 }, 7910 outputs: []outputInfo{ 7911 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7912 }, 7913 }, 7914 }, 7915 { 7916 name: "SHRBconst", 7917 auxType: auxInt8, 7918 argLen: 1, 7919 resultInArg0: true, 7920 clobberFlags: true, 7921 asm: x86.ASHRB, 7922 reg: regInfo{ 7923 inputs: []inputInfo{ 7924 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7925 }, 7926 outputs: []outputInfo{ 7927 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7928 }, 7929 }, 7930 }, 7931 { 7932 name: "SARQ", 7933 argLen: 2, 7934 resultInArg0: true, 7935 clobberFlags: true, 7936 asm: x86.ASARQ, 7937 reg: regInfo{ 7938 inputs: []inputInfo{ 7939 {1, 2}, // CX 7940 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7941 }, 7942 outputs: []outputInfo{ 7943 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7944 }, 7945 }, 7946 }, 7947 { 7948 name: "SARL", 7949 argLen: 2, 7950 resultInArg0: true, 7951 clobberFlags: true, 7952 asm: x86.ASARL, 7953 reg: regInfo{ 7954 inputs: []inputInfo{ 7955 {1, 2}, // CX 7956 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7957 }, 7958 outputs: []outputInfo{ 7959 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7960 }, 7961 }, 7962 }, 7963 { 7964 name: "SARW", 7965 argLen: 2, 7966 resultInArg0: true, 7967 clobberFlags: true, 7968 asm: x86.ASARW, 7969 reg: regInfo{ 7970 inputs: []inputInfo{ 7971 {1, 2}, // CX 7972 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7973 }, 7974 outputs: []outputInfo{ 7975 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7976 }, 7977 }, 7978 }, 7979 { 7980 name: "SARB", 7981 argLen: 2, 7982 resultInArg0: true, 7983 clobberFlags: true, 7984 asm: x86.ASARB, 7985 reg: regInfo{ 7986 inputs: []inputInfo{ 7987 {1, 2}, // CX 7988 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7989 }, 7990 outputs: []outputInfo{ 7991 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7992 }, 7993 }, 7994 }, 7995 { 7996 name: "SARQconst", 7997 auxType: auxInt8, 7998 argLen: 1, 7999 resultInArg0: true, 8000 clobberFlags: true, 8001 asm: x86.ASARQ, 8002 reg: regInfo{ 8003 inputs: []inputInfo{ 8004 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8005 }, 8006 outputs: []outputInfo{ 8007 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8008 }, 8009 }, 8010 }, 8011 { 8012 name: "SARLconst", 8013 auxType: auxInt8, 8014 argLen: 1, 8015 resultInArg0: true, 8016 clobberFlags: true, 8017 asm: x86.ASARL, 8018 reg: regInfo{ 8019 inputs: []inputInfo{ 8020 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8021 }, 8022 outputs: []outputInfo{ 8023 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8024 }, 8025 }, 8026 }, 8027 { 8028 name: "SARWconst", 8029 auxType: auxInt8, 8030 argLen: 1, 8031 resultInArg0: true, 8032 clobberFlags: true, 8033 asm: x86.ASARW, 8034 reg: regInfo{ 8035 inputs: []inputInfo{ 8036 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8037 }, 8038 outputs: []outputInfo{ 8039 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8040 }, 8041 }, 8042 }, 8043 { 8044 name: "SARBconst", 8045 auxType: auxInt8, 8046 argLen: 1, 8047 resultInArg0: true, 8048 clobberFlags: true, 8049 asm: x86.ASARB, 8050 reg: regInfo{ 8051 inputs: []inputInfo{ 8052 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8053 }, 8054 outputs: []outputInfo{ 8055 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8056 }, 8057 }, 8058 }, 8059 { 8060 name: "ROLQ", 8061 argLen: 2, 8062 resultInArg0: true, 8063 clobberFlags: true, 8064 asm: x86.AROLQ, 8065 reg: regInfo{ 8066 inputs: []inputInfo{ 8067 {1, 2}, // CX 8068 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8069 }, 8070 outputs: []outputInfo{ 8071 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8072 }, 8073 }, 8074 }, 8075 { 8076 name: "ROLL", 8077 argLen: 2, 8078 resultInArg0: true, 8079 clobberFlags: true, 8080 asm: x86.AROLL, 8081 reg: regInfo{ 8082 inputs: []inputInfo{ 8083 {1, 2}, // CX 8084 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8085 }, 8086 outputs: []outputInfo{ 8087 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8088 }, 8089 }, 8090 }, 8091 { 8092 name: "ROLW", 8093 argLen: 2, 8094 resultInArg0: true, 8095 clobberFlags: true, 8096 asm: x86.AROLW, 8097 reg: regInfo{ 8098 inputs: []inputInfo{ 8099 {1, 2}, // CX 8100 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8101 }, 8102 outputs: []outputInfo{ 8103 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8104 }, 8105 }, 8106 }, 8107 { 8108 name: "ROLB", 8109 argLen: 2, 8110 resultInArg0: true, 8111 clobberFlags: true, 8112 asm: x86.AROLB, 8113 reg: regInfo{ 8114 inputs: []inputInfo{ 8115 {1, 2}, // CX 8116 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8117 }, 8118 outputs: []outputInfo{ 8119 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8120 }, 8121 }, 8122 }, 8123 { 8124 name: "RORQ", 8125 argLen: 2, 8126 resultInArg0: true, 8127 clobberFlags: true, 8128 asm: x86.ARORQ, 8129 reg: regInfo{ 8130 inputs: []inputInfo{ 8131 {1, 2}, // CX 8132 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8133 }, 8134 outputs: []outputInfo{ 8135 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8136 }, 8137 }, 8138 }, 8139 { 8140 name: "RORL", 8141 argLen: 2, 8142 resultInArg0: true, 8143 clobberFlags: true, 8144 asm: x86.ARORL, 8145 reg: regInfo{ 8146 inputs: []inputInfo{ 8147 {1, 2}, // CX 8148 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8149 }, 8150 outputs: []outputInfo{ 8151 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8152 }, 8153 }, 8154 }, 8155 { 8156 name: "RORW", 8157 argLen: 2, 8158 resultInArg0: true, 8159 clobberFlags: true, 8160 asm: x86.ARORW, 8161 reg: regInfo{ 8162 inputs: []inputInfo{ 8163 {1, 2}, // CX 8164 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8165 }, 8166 outputs: []outputInfo{ 8167 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8168 }, 8169 }, 8170 }, 8171 { 8172 name: "RORB", 8173 argLen: 2, 8174 resultInArg0: true, 8175 clobberFlags: true, 8176 asm: x86.ARORB, 8177 reg: regInfo{ 8178 inputs: []inputInfo{ 8179 {1, 2}, // CX 8180 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8181 }, 8182 outputs: []outputInfo{ 8183 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8184 }, 8185 }, 8186 }, 8187 { 8188 name: "ROLQconst", 8189 auxType: auxInt8, 8190 argLen: 1, 8191 resultInArg0: true, 8192 clobberFlags: true, 8193 asm: x86.AROLQ, 8194 reg: regInfo{ 8195 inputs: []inputInfo{ 8196 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8197 }, 8198 outputs: []outputInfo{ 8199 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8200 }, 8201 }, 8202 }, 8203 { 8204 name: "ROLLconst", 8205 auxType: auxInt8, 8206 argLen: 1, 8207 resultInArg0: true, 8208 clobberFlags: true, 8209 asm: x86.AROLL, 8210 reg: regInfo{ 8211 inputs: []inputInfo{ 8212 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8213 }, 8214 outputs: []outputInfo{ 8215 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8216 }, 8217 }, 8218 }, 8219 { 8220 name: "ROLWconst", 8221 auxType: auxInt8, 8222 argLen: 1, 8223 resultInArg0: true, 8224 clobberFlags: true, 8225 asm: x86.AROLW, 8226 reg: regInfo{ 8227 inputs: []inputInfo{ 8228 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8229 }, 8230 outputs: []outputInfo{ 8231 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8232 }, 8233 }, 8234 }, 8235 { 8236 name: "ROLBconst", 8237 auxType: auxInt8, 8238 argLen: 1, 8239 resultInArg0: true, 8240 clobberFlags: true, 8241 asm: x86.AROLB, 8242 reg: regInfo{ 8243 inputs: []inputInfo{ 8244 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8245 }, 8246 outputs: []outputInfo{ 8247 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8248 }, 8249 }, 8250 }, 8251 { 8252 name: "ADDLload", 8253 auxType: auxSymOff, 8254 argLen: 3, 8255 resultInArg0: true, 8256 clobberFlags: true, 8257 faultOnNilArg1: true, 8258 symEffect: SymRead, 8259 asm: x86.AADDL, 8260 reg: regInfo{ 8261 inputs: []inputInfo{ 8262 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8263 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8264 }, 8265 outputs: []outputInfo{ 8266 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8267 }, 8268 }, 8269 }, 8270 { 8271 name: "ADDQload", 8272 auxType: auxSymOff, 8273 argLen: 3, 8274 resultInArg0: true, 8275 clobberFlags: true, 8276 faultOnNilArg1: true, 8277 symEffect: SymRead, 8278 asm: x86.AADDQ, 8279 reg: regInfo{ 8280 inputs: []inputInfo{ 8281 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8282 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8283 }, 8284 outputs: []outputInfo{ 8285 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8286 }, 8287 }, 8288 }, 8289 { 8290 name: "SUBQload", 8291 auxType: auxSymOff, 8292 argLen: 3, 8293 resultInArg0: true, 8294 clobberFlags: true, 8295 faultOnNilArg1: true, 8296 symEffect: SymRead, 8297 asm: x86.ASUBQ, 8298 reg: regInfo{ 8299 inputs: []inputInfo{ 8300 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8301 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8302 }, 8303 outputs: []outputInfo{ 8304 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8305 }, 8306 }, 8307 }, 8308 { 8309 name: "SUBLload", 8310 auxType: auxSymOff, 8311 argLen: 3, 8312 resultInArg0: true, 8313 clobberFlags: true, 8314 faultOnNilArg1: true, 8315 symEffect: SymRead, 8316 asm: x86.ASUBL, 8317 reg: regInfo{ 8318 inputs: []inputInfo{ 8319 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8320 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8321 }, 8322 outputs: []outputInfo{ 8323 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8324 }, 8325 }, 8326 }, 8327 { 8328 name: "ANDLload", 8329 auxType: auxSymOff, 8330 argLen: 3, 8331 resultInArg0: true, 8332 clobberFlags: true, 8333 faultOnNilArg1: true, 8334 symEffect: SymRead, 8335 asm: x86.AANDL, 8336 reg: regInfo{ 8337 inputs: []inputInfo{ 8338 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8339 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8340 }, 8341 outputs: []outputInfo{ 8342 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8343 }, 8344 }, 8345 }, 8346 { 8347 name: "ANDQload", 8348 auxType: auxSymOff, 8349 argLen: 3, 8350 resultInArg0: true, 8351 clobberFlags: true, 8352 faultOnNilArg1: true, 8353 symEffect: SymRead, 8354 asm: x86.AANDQ, 8355 reg: regInfo{ 8356 inputs: []inputInfo{ 8357 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8358 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8359 }, 8360 outputs: []outputInfo{ 8361 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8362 }, 8363 }, 8364 }, 8365 { 8366 name: "ORQload", 8367 auxType: auxSymOff, 8368 argLen: 3, 8369 resultInArg0: true, 8370 clobberFlags: true, 8371 faultOnNilArg1: true, 8372 symEffect: SymRead, 8373 asm: x86.AORQ, 8374 reg: regInfo{ 8375 inputs: []inputInfo{ 8376 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8377 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8378 }, 8379 outputs: []outputInfo{ 8380 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8381 }, 8382 }, 8383 }, 8384 { 8385 name: "ORLload", 8386 auxType: auxSymOff, 8387 argLen: 3, 8388 resultInArg0: true, 8389 clobberFlags: true, 8390 faultOnNilArg1: true, 8391 symEffect: SymRead, 8392 asm: x86.AORL, 8393 reg: regInfo{ 8394 inputs: []inputInfo{ 8395 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8396 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8397 }, 8398 outputs: []outputInfo{ 8399 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8400 }, 8401 }, 8402 }, 8403 { 8404 name: "XORQload", 8405 auxType: auxSymOff, 8406 argLen: 3, 8407 resultInArg0: true, 8408 clobberFlags: true, 8409 faultOnNilArg1: true, 8410 symEffect: SymRead, 8411 asm: x86.AXORQ, 8412 reg: regInfo{ 8413 inputs: []inputInfo{ 8414 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8415 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8416 }, 8417 outputs: []outputInfo{ 8418 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8419 }, 8420 }, 8421 }, 8422 { 8423 name: "XORLload", 8424 auxType: auxSymOff, 8425 argLen: 3, 8426 resultInArg0: true, 8427 clobberFlags: true, 8428 faultOnNilArg1: true, 8429 symEffect: SymRead, 8430 asm: x86.AXORL, 8431 reg: regInfo{ 8432 inputs: []inputInfo{ 8433 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8434 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8435 }, 8436 outputs: []outputInfo{ 8437 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8438 }, 8439 }, 8440 }, 8441 { 8442 name: "ADDQmodify", 8443 auxType: auxSymOff, 8444 argLen: 3, 8445 clobberFlags: true, 8446 faultOnNilArg0: true, 8447 symEffect: SymRead | SymWrite, 8448 asm: x86.AADDQ, 8449 reg: regInfo{ 8450 inputs: []inputInfo{ 8451 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8452 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8453 }, 8454 }, 8455 }, 8456 { 8457 name: "SUBQmodify", 8458 auxType: auxSymOff, 8459 argLen: 3, 8460 clobberFlags: true, 8461 faultOnNilArg0: true, 8462 symEffect: SymRead | SymWrite, 8463 asm: x86.ASUBQ, 8464 reg: regInfo{ 8465 inputs: []inputInfo{ 8466 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8467 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8468 }, 8469 }, 8470 }, 8471 { 8472 name: "ANDQmodify", 8473 auxType: auxSymOff, 8474 argLen: 3, 8475 clobberFlags: true, 8476 faultOnNilArg0: true, 8477 symEffect: SymRead | SymWrite, 8478 asm: x86.AANDQ, 8479 reg: regInfo{ 8480 inputs: []inputInfo{ 8481 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8482 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8483 }, 8484 }, 8485 }, 8486 { 8487 name: "ORQmodify", 8488 auxType: auxSymOff, 8489 argLen: 3, 8490 clobberFlags: true, 8491 faultOnNilArg0: true, 8492 symEffect: SymRead | SymWrite, 8493 asm: x86.AORQ, 8494 reg: regInfo{ 8495 inputs: []inputInfo{ 8496 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8497 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8498 }, 8499 }, 8500 }, 8501 { 8502 name: "XORQmodify", 8503 auxType: auxSymOff, 8504 argLen: 3, 8505 clobberFlags: true, 8506 faultOnNilArg0: true, 8507 symEffect: SymRead | SymWrite, 8508 asm: x86.AXORQ, 8509 reg: regInfo{ 8510 inputs: []inputInfo{ 8511 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8512 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8513 }, 8514 }, 8515 }, 8516 { 8517 name: "ADDLmodify", 8518 auxType: auxSymOff, 8519 argLen: 3, 8520 clobberFlags: true, 8521 faultOnNilArg0: true, 8522 symEffect: SymRead | SymWrite, 8523 asm: x86.AADDL, 8524 reg: regInfo{ 8525 inputs: []inputInfo{ 8526 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8527 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8528 }, 8529 }, 8530 }, 8531 { 8532 name: "SUBLmodify", 8533 auxType: auxSymOff, 8534 argLen: 3, 8535 clobberFlags: true, 8536 faultOnNilArg0: true, 8537 symEffect: SymRead | SymWrite, 8538 asm: x86.ASUBL, 8539 reg: regInfo{ 8540 inputs: []inputInfo{ 8541 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8542 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8543 }, 8544 }, 8545 }, 8546 { 8547 name: "ANDLmodify", 8548 auxType: auxSymOff, 8549 argLen: 3, 8550 clobberFlags: true, 8551 faultOnNilArg0: true, 8552 symEffect: SymRead | SymWrite, 8553 asm: x86.AANDL, 8554 reg: regInfo{ 8555 inputs: []inputInfo{ 8556 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8557 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8558 }, 8559 }, 8560 }, 8561 { 8562 name: "ORLmodify", 8563 auxType: auxSymOff, 8564 argLen: 3, 8565 clobberFlags: true, 8566 faultOnNilArg0: true, 8567 symEffect: SymRead | SymWrite, 8568 asm: x86.AORL, 8569 reg: regInfo{ 8570 inputs: []inputInfo{ 8571 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8572 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8573 }, 8574 }, 8575 }, 8576 { 8577 name: "XORLmodify", 8578 auxType: auxSymOff, 8579 argLen: 3, 8580 clobberFlags: true, 8581 faultOnNilArg0: true, 8582 symEffect: SymRead | SymWrite, 8583 asm: x86.AXORL, 8584 reg: regInfo{ 8585 inputs: []inputInfo{ 8586 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8587 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8588 }, 8589 }, 8590 }, 8591 { 8592 name: "NEGQ", 8593 argLen: 1, 8594 resultInArg0: true, 8595 clobberFlags: true, 8596 asm: x86.ANEGQ, 8597 reg: regInfo{ 8598 inputs: []inputInfo{ 8599 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8600 }, 8601 outputs: []outputInfo{ 8602 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8603 }, 8604 }, 8605 }, 8606 { 8607 name: "NEGL", 8608 argLen: 1, 8609 resultInArg0: true, 8610 clobberFlags: true, 8611 asm: x86.ANEGL, 8612 reg: regInfo{ 8613 inputs: []inputInfo{ 8614 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8615 }, 8616 outputs: []outputInfo{ 8617 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8618 }, 8619 }, 8620 }, 8621 { 8622 name: "NOTQ", 8623 argLen: 1, 8624 resultInArg0: true, 8625 clobberFlags: true, 8626 asm: x86.ANOTQ, 8627 reg: regInfo{ 8628 inputs: []inputInfo{ 8629 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8630 }, 8631 outputs: []outputInfo{ 8632 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8633 }, 8634 }, 8635 }, 8636 { 8637 name: "NOTL", 8638 argLen: 1, 8639 resultInArg0: true, 8640 clobberFlags: true, 8641 asm: x86.ANOTL, 8642 reg: regInfo{ 8643 inputs: []inputInfo{ 8644 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8645 }, 8646 outputs: []outputInfo{ 8647 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8648 }, 8649 }, 8650 }, 8651 { 8652 name: "BSFQ", 8653 argLen: 1, 8654 asm: x86.ABSFQ, 8655 reg: regInfo{ 8656 inputs: []inputInfo{ 8657 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8658 }, 8659 outputs: []outputInfo{ 8660 {1, 0}, 8661 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8662 }, 8663 }, 8664 }, 8665 { 8666 name: "BSFL", 8667 argLen: 1, 8668 clobberFlags: true, 8669 asm: x86.ABSFL, 8670 reg: regInfo{ 8671 inputs: []inputInfo{ 8672 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8673 }, 8674 outputs: []outputInfo{ 8675 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8676 }, 8677 }, 8678 }, 8679 { 8680 name: "BSRQ", 8681 argLen: 1, 8682 asm: x86.ABSRQ, 8683 reg: regInfo{ 8684 inputs: []inputInfo{ 8685 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8686 }, 8687 outputs: []outputInfo{ 8688 {1, 0}, 8689 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8690 }, 8691 }, 8692 }, 8693 { 8694 name: "BSRL", 8695 argLen: 1, 8696 clobberFlags: true, 8697 asm: x86.ABSRL, 8698 reg: regInfo{ 8699 inputs: []inputInfo{ 8700 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8701 }, 8702 outputs: []outputInfo{ 8703 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8704 }, 8705 }, 8706 }, 8707 { 8708 name: "CMOVQEQ", 8709 argLen: 3, 8710 resultInArg0: true, 8711 asm: x86.ACMOVQEQ, 8712 reg: regInfo{ 8713 inputs: []inputInfo{ 8714 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8715 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8716 }, 8717 outputs: []outputInfo{ 8718 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8719 }, 8720 }, 8721 }, 8722 { 8723 name: "CMOVQNE", 8724 argLen: 3, 8725 resultInArg0: true, 8726 asm: x86.ACMOVQNE, 8727 reg: regInfo{ 8728 inputs: []inputInfo{ 8729 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8730 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8731 }, 8732 outputs: []outputInfo{ 8733 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8734 }, 8735 }, 8736 }, 8737 { 8738 name: "CMOVQLT", 8739 argLen: 3, 8740 resultInArg0: true, 8741 asm: x86.ACMOVQLT, 8742 reg: regInfo{ 8743 inputs: []inputInfo{ 8744 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8745 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8746 }, 8747 outputs: []outputInfo{ 8748 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8749 }, 8750 }, 8751 }, 8752 { 8753 name: "CMOVQGT", 8754 argLen: 3, 8755 resultInArg0: true, 8756 asm: x86.ACMOVQGT, 8757 reg: regInfo{ 8758 inputs: []inputInfo{ 8759 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8760 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8761 }, 8762 outputs: []outputInfo{ 8763 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8764 }, 8765 }, 8766 }, 8767 { 8768 name: "CMOVQLE", 8769 argLen: 3, 8770 resultInArg0: true, 8771 asm: x86.ACMOVQLE, 8772 reg: regInfo{ 8773 inputs: []inputInfo{ 8774 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8775 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8776 }, 8777 outputs: []outputInfo{ 8778 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8779 }, 8780 }, 8781 }, 8782 { 8783 name: "CMOVQGE", 8784 argLen: 3, 8785 resultInArg0: true, 8786 asm: x86.ACMOVQGE, 8787 reg: regInfo{ 8788 inputs: []inputInfo{ 8789 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8790 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8791 }, 8792 outputs: []outputInfo{ 8793 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8794 }, 8795 }, 8796 }, 8797 { 8798 name: "CMOVQLS", 8799 argLen: 3, 8800 resultInArg0: true, 8801 asm: x86.ACMOVQLS, 8802 reg: regInfo{ 8803 inputs: []inputInfo{ 8804 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8805 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8806 }, 8807 outputs: []outputInfo{ 8808 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8809 }, 8810 }, 8811 }, 8812 { 8813 name: "CMOVQHI", 8814 argLen: 3, 8815 resultInArg0: true, 8816 asm: x86.ACMOVQHI, 8817 reg: regInfo{ 8818 inputs: []inputInfo{ 8819 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8820 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8821 }, 8822 outputs: []outputInfo{ 8823 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8824 }, 8825 }, 8826 }, 8827 { 8828 name: "CMOVQCC", 8829 argLen: 3, 8830 resultInArg0: true, 8831 asm: x86.ACMOVQCC, 8832 reg: regInfo{ 8833 inputs: []inputInfo{ 8834 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8835 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8836 }, 8837 outputs: []outputInfo{ 8838 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8839 }, 8840 }, 8841 }, 8842 { 8843 name: "CMOVQCS", 8844 argLen: 3, 8845 resultInArg0: true, 8846 asm: x86.ACMOVQCS, 8847 reg: regInfo{ 8848 inputs: []inputInfo{ 8849 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8850 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8851 }, 8852 outputs: []outputInfo{ 8853 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8854 }, 8855 }, 8856 }, 8857 { 8858 name: "CMOVLEQ", 8859 argLen: 3, 8860 resultInArg0: true, 8861 asm: x86.ACMOVLEQ, 8862 reg: regInfo{ 8863 inputs: []inputInfo{ 8864 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8865 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8866 }, 8867 outputs: []outputInfo{ 8868 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8869 }, 8870 }, 8871 }, 8872 { 8873 name: "CMOVLNE", 8874 argLen: 3, 8875 resultInArg0: true, 8876 asm: x86.ACMOVLNE, 8877 reg: regInfo{ 8878 inputs: []inputInfo{ 8879 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8880 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8881 }, 8882 outputs: []outputInfo{ 8883 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8884 }, 8885 }, 8886 }, 8887 { 8888 name: "CMOVLLT", 8889 argLen: 3, 8890 resultInArg0: true, 8891 asm: x86.ACMOVLLT, 8892 reg: regInfo{ 8893 inputs: []inputInfo{ 8894 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8895 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8896 }, 8897 outputs: []outputInfo{ 8898 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8899 }, 8900 }, 8901 }, 8902 { 8903 name: "CMOVLGT", 8904 argLen: 3, 8905 resultInArg0: true, 8906 asm: x86.ACMOVLGT, 8907 reg: regInfo{ 8908 inputs: []inputInfo{ 8909 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8910 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8911 }, 8912 outputs: []outputInfo{ 8913 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8914 }, 8915 }, 8916 }, 8917 { 8918 name: "CMOVLLE", 8919 argLen: 3, 8920 resultInArg0: true, 8921 asm: x86.ACMOVLLE, 8922 reg: regInfo{ 8923 inputs: []inputInfo{ 8924 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8925 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8926 }, 8927 outputs: []outputInfo{ 8928 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8929 }, 8930 }, 8931 }, 8932 { 8933 name: "CMOVLGE", 8934 argLen: 3, 8935 resultInArg0: true, 8936 asm: x86.ACMOVLGE, 8937 reg: regInfo{ 8938 inputs: []inputInfo{ 8939 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8940 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8941 }, 8942 outputs: []outputInfo{ 8943 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8944 }, 8945 }, 8946 }, 8947 { 8948 name: "CMOVLLS", 8949 argLen: 3, 8950 resultInArg0: true, 8951 asm: x86.ACMOVLLS, 8952 reg: regInfo{ 8953 inputs: []inputInfo{ 8954 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8955 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8956 }, 8957 outputs: []outputInfo{ 8958 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8959 }, 8960 }, 8961 }, 8962 { 8963 name: "CMOVLHI", 8964 argLen: 3, 8965 resultInArg0: true, 8966 asm: x86.ACMOVLHI, 8967 reg: regInfo{ 8968 inputs: []inputInfo{ 8969 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8970 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8971 }, 8972 outputs: []outputInfo{ 8973 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8974 }, 8975 }, 8976 }, 8977 { 8978 name: "CMOVLCC", 8979 argLen: 3, 8980 resultInArg0: true, 8981 asm: x86.ACMOVLCC, 8982 reg: regInfo{ 8983 inputs: []inputInfo{ 8984 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8985 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8986 }, 8987 outputs: []outputInfo{ 8988 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8989 }, 8990 }, 8991 }, 8992 { 8993 name: "CMOVLCS", 8994 argLen: 3, 8995 resultInArg0: true, 8996 asm: x86.ACMOVLCS, 8997 reg: regInfo{ 8998 inputs: []inputInfo{ 8999 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9000 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9001 }, 9002 outputs: []outputInfo{ 9003 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9004 }, 9005 }, 9006 }, 9007 { 9008 name: "CMOVWEQ", 9009 argLen: 3, 9010 resultInArg0: true, 9011 asm: x86.ACMOVWEQ, 9012 reg: regInfo{ 9013 inputs: []inputInfo{ 9014 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9015 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9016 }, 9017 outputs: []outputInfo{ 9018 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9019 }, 9020 }, 9021 }, 9022 { 9023 name: "CMOVWNE", 9024 argLen: 3, 9025 resultInArg0: true, 9026 asm: x86.ACMOVWNE, 9027 reg: regInfo{ 9028 inputs: []inputInfo{ 9029 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9030 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9031 }, 9032 outputs: []outputInfo{ 9033 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9034 }, 9035 }, 9036 }, 9037 { 9038 name: "CMOVWLT", 9039 argLen: 3, 9040 resultInArg0: true, 9041 asm: x86.ACMOVWLT, 9042 reg: regInfo{ 9043 inputs: []inputInfo{ 9044 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9045 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9046 }, 9047 outputs: []outputInfo{ 9048 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9049 }, 9050 }, 9051 }, 9052 { 9053 name: "CMOVWGT", 9054 argLen: 3, 9055 resultInArg0: true, 9056 asm: x86.ACMOVWGT, 9057 reg: regInfo{ 9058 inputs: []inputInfo{ 9059 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9060 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9061 }, 9062 outputs: []outputInfo{ 9063 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9064 }, 9065 }, 9066 }, 9067 { 9068 name: "CMOVWLE", 9069 argLen: 3, 9070 resultInArg0: true, 9071 asm: x86.ACMOVWLE, 9072 reg: regInfo{ 9073 inputs: []inputInfo{ 9074 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9075 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9076 }, 9077 outputs: []outputInfo{ 9078 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9079 }, 9080 }, 9081 }, 9082 { 9083 name: "CMOVWGE", 9084 argLen: 3, 9085 resultInArg0: true, 9086 asm: x86.ACMOVWGE, 9087 reg: regInfo{ 9088 inputs: []inputInfo{ 9089 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9090 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9091 }, 9092 outputs: []outputInfo{ 9093 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9094 }, 9095 }, 9096 }, 9097 { 9098 name: "CMOVWLS", 9099 argLen: 3, 9100 resultInArg0: true, 9101 asm: x86.ACMOVWLS, 9102 reg: regInfo{ 9103 inputs: []inputInfo{ 9104 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9105 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9106 }, 9107 outputs: []outputInfo{ 9108 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9109 }, 9110 }, 9111 }, 9112 { 9113 name: "CMOVWHI", 9114 argLen: 3, 9115 resultInArg0: true, 9116 asm: x86.ACMOVWHI, 9117 reg: regInfo{ 9118 inputs: []inputInfo{ 9119 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9120 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9121 }, 9122 outputs: []outputInfo{ 9123 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9124 }, 9125 }, 9126 }, 9127 { 9128 name: "CMOVWCC", 9129 argLen: 3, 9130 resultInArg0: true, 9131 asm: x86.ACMOVWCC, 9132 reg: regInfo{ 9133 inputs: []inputInfo{ 9134 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9135 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9136 }, 9137 outputs: []outputInfo{ 9138 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9139 }, 9140 }, 9141 }, 9142 { 9143 name: "CMOVWCS", 9144 argLen: 3, 9145 resultInArg0: true, 9146 asm: x86.ACMOVWCS, 9147 reg: regInfo{ 9148 inputs: []inputInfo{ 9149 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9150 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9151 }, 9152 outputs: []outputInfo{ 9153 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9154 }, 9155 }, 9156 }, 9157 { 9158 name: "CMOVQEQF", 9159 argLen: 3, 9160 resultInArg0: true, 9161 asm: x86.ACMOVQNE, 9162 reg: regInfo{ 9163 inputs: []inputInfo{ 9164 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9165 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9166 }, 9167 clobbers: 1, // AX 9168 outputs: []outputInfo{ 9169 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9170 }, 9171 }, 9172 }, 9173 { 9174 name: "CMOVQNEF", 9175 argLen: 3, 9176 resultInArg0: true, 9177 asm: x86.ACMOVQNE, 9178 reg: regInfo{ 9179 inputs: []inputInfo{ 9180 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9181 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9182 }, 9183 outputs: []outputInfo{ 9184 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9185 }, 9186 }, 9187 }, 9188 { 9189 name: "CMOVQGTF", 9190 argLen: 3, 9191 resultInArg0: true, 9192 asm: x86.ACMOVQHI, 9193 reg: regInfo{ 9194 inputs: []inputInfo{ 9195 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9196 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9197 }, 9198 outputs: []outputInfo{ 9199 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9200 }, 9201 }, 9202 }, 9203 { 9204 name: "CMOVQGEF", 9205 argLen: 3, 9206 resultInArg0: true, 9207 asm: x86.ACMOVQCC, 9208 reg: regInfo{ 9209 inputs: []inputInfo{ 9210 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9211 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9212 }, 9213 outputs: []outputInfo{ 9214 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9215 }, 9216 }, 9217 }, 9218 { 9219 name: "CMOVLEQF", 9220 argLen: 3, 9221 resultInArg0: true, 9222 asm: x86.ACMOVLNE, 9223 reg: regInfo{ 9224 inputs: []inputInfo{ 9225 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9226 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9227 }, 9228 clobbers: 1, // AX 9229 outputs: []outputInfo{ 9230 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9231 }, 9232 }, 9233 }, 9234 { 9235 name: "CMOVLNEF", 9236 argLen: 3, 9237 resultInArg0: true, 9238 asm: x86.ACMOVLNE, 9239 reg: regInfo{ 9240 inputs: []inputInfo{ 9241 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9242 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9243 }, 9244 outputs: []outputInfo{ 9245 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9246 }, 9247 }, 9248 }, 9249 { 9250 name: "CMOVLGTF", 9251 argLen: 3, 9252 resultInArg0: true, 9253 asm: x86.ACMOVLHI, 9254 reg: regInfo{ 9255 inputs: []inputInfo{ 9256 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9257 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9258 }, 9259 outputs: []outputInfo{ 9260 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9261 }, 9262 }, 9263 }, 9264 { 9265 name: "CMOVLGEF", 9266 argLen: 3, 9267 resultInArg0: true, 9268 asm: x86.ACMOVLCC, 9269 reg: regInfo{ 9270 inputs: []inputInfo{ 9271 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9272 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9273 }, 9274 outputs: []outputInfo{ 9275 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9276 }, 9277 }, 9278 }, 9279 { 9280 name: "CMOVWEQF", 9281 argLen: 3, 9282 resultInArg0: true, 9283 asm: x86.ACMOVWNE, 9284 reg: regInfo{ 9285 inputs: []inputInfo{ 9286 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9287 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9288 }, 9289 clobbers: 1, // AX 9290 outputs: []outputInfo{ 9291 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9292 }, 9293 }, 9294 }, 9295 { 9296 name: "CMOVWNEF", 9297 argLen: 3, 9298 resultInArg0: true, 9299 asm: x86.ACMOVWNE, 9300 reg: regInfo{ 9301 inputs: []inputInfo{ 9302 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9303 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9304 }, 9305 outputs: []outputInfo{ 9306 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9307 }, 9308 }, 9309 }, 9310 { 9311 name: "CMOVWGTF", 9312 argLen: 3, 9313 resultInArg0: true, 9314 asm: x86.ACMOVWHI, 9315 reg: regInfo{ 9316 inputs: []inputInfo{ 9317 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9318 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9319 }, 9320 outputs: []outputInfo{ 9321 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9322 }, 9323 }, 9324 }, 9325 { 9326 name: "CMOVWGEF", 9327 argLen: 3, 9328 resultInArg0: true, 9329 asm: x86.ACMOVWCC, 9330 reg: regInfo{ 9331 inputs: []inputInfo{ 9332 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9333 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9334 }, 9335 outputs: []outputInfo{ 9336 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9337 }, 9338 }, 9339 }, 9340 { 9341 name: "BSWAPQ", 9342 argLen: 1, 9343 resultInArg0: true, 9344 clobberFlags: true, 9345 asm: x86.ABSWAPQ, 9346 reg: regInfo{ 9347 inputs: []inputInfo{ 9348 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9349 }, 9350 outputs: []outputInfo{ 9351 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9352 }, 9353 }, 9354 }, 9355 { 9356 name: "BSWAPL", 9357 argLen: 1, 9358 resultInArg0: true, 9359 clobberFlags: true, 9360 asm: x86.ABSWAPL, 9361 reg: regInfo{ 9362 inputs: []inputInfo{ 9363 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9364 }, 9365 outputs: []outputInfo{ 9366 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9367 }, 9368 }, 9369 }, 9370 { 9371 name: "POPCNTQ", 9372 argLen: 1, 9373 clobberFlags: true, 9374 asm: x86.APOPCNTQ, 9375 reg: regInfo{ 9376 inputs: []inputInfo{ 9377 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9378 }, 9379 outputs: []outputInfo{ 9380 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9381 }, 9382 }, 9383 }, 9384 { 9385 name: "POPCNTL", 9386 argLen: 1, 9387 clobberFlags: true, 9388 asm: x86.APOPCNTL, 9389 reg: regInfo{ 9390 inputs: []inputInfo{ 9391 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9392 }, 9393 outputs: []outputInfo{ 9394 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9395 }, 9396 }, 9397 }, 9398 { 9399 name: "SQRTSD", 9400 argLen: 1, 9401 asm: x86.ASQRTSD, 9402 reg: regInfo{ 9403 inputs: []inputInfo{ 9404 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9405 }, 9406 outputs: []outputInfo{ 9407 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9408 }, 9409 }, 9410 }, 9411 { 9412 name: "ROUNDSD", 9413 auxType: auxInt8, 9414 argLen: 1, 9415 asm: x86.AROUNDSD, 9416 reg: regInfo{ 9417 inputs: []inputInfo{ 9418 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9419 }, 9420 outputs: []outputInfo{ 9421 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9422 }, 9423 }, 9424 }, 9425 { 9426 name: "SBBQcarrymask", 9427 argLen: 1, 9428 asm: x86.ASBBQ, 9429 reg: regInfo{ 9430 outputs: []outputInfo{ 9431 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9432 }, 9433 }, 9434 }, 9435 { 9436 name: "SBBLcarrymask", 9437 argLen: 1, 9438 asm: x86.ASBBL, 9439 reg: regInfo{ 9440 outputs: []outputInfo{ 9441 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9442 }, 9443 }, 9444 }, 9445 { 9446 name: "SETEQ", 9447 argLen: 1, 9448 asm: x86.ASETEQ, 9449 reg: regInfo{ 9450 outputs: []outputInfo{ 9451 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9452 }, 9453 }, 9454 }, 9455 { 9456 name: "SETNE", 9457 argLen: 1, 9458 asm: x86.ASETNE, 9459 reg: regInfo{ 9460 outputs: []outputInfo{ 9461 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9462 }, 9463 }, 9464 }, 9465 { 9466 name: "SETL", 9467 argLen: 1, 9468 asm: x86.ASETLT, 9469 reg: regInfo{ 9470 outputs: []outputInfo{ 9471 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9472 }, 9473 }, 9474 }, 9475 { 9476 name: "SETLE", 9477 argLen: 1, 9478 asm: x86.ASETLE, 9479 reg: regInfo{ 9480 outputs: []outputInfo{ 9481 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9482 }, 9483 }, 9484 }, 9485 { 9486 name: "SETG", 9487 argLen: 1, 9488 asm: x86.ASETGT, 9489 reg: regInfo{ 9490 outputs: []outputInfo{ 9491 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9492 }, 9493 }, 9494 }, 9495 { 9496 name: "SETGE", 9497 argLen: 1, 9498 asm: x86.ASETGE, 9499 reg: regInfo{ 9500 outputs: []outputInfo{ 9501 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9502 }, 9503 }, 9504 }, 9505 { 9506 name: "SETB", 9507 argLen: 1, 9508 asm: x86.ASETCS, 9509 reg: regInfo{ 9510 outputs: []outputInfo{ 9511 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9512 }, 9513 }, 9514 }, 9515 { 9516 name: "SETBE", 9517 argLen: 1, 9518 asm: x86.ASETLS, 9519 reg: regInfo{ 9520 outputs: []outputInfo{ 9521 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9522 }, 9523 }, 9524 }, 9525 { 9526 name: "SETA", 9527 argLen: 1, 9528 asm: x86.ASETHI, 9529 reg: regInfo{ 9530 outputs: []outputInfo{ 9531 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9532 }, 9533 }, 9534 }, 9535 { 9536 name: "SETAE", 9537 argLen: 1, 9538 asm: x86.ASETCC, 9539 reg: regInfo{ 9540 outputs: []outputInfo{ 9541 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9542 }, 9543 }, 9544 }, 9545 { 9546 name: "SETO", 9547 argLen: 1, 9548 asm: x86.ASETOS, 9549 reg: regInfo{ 9550 outputs: []outputInfo{ 9551 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9552 }, 9553 }, 9554 }, 9555 { 9556 name: "SETEQstore", 9557 auxType: auxSymOff, 9558 argLen: 3, 9559 faultOnNilArg0: true, 9560 symEffect: SymWrite, 9561 asm: x86.ASETEQ, 9562 reg: regInfo{ 9563 inputs: []inputInfo{ 9564 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9565 }, 9566 }, 9567 }, 9568 { 9569 name: "SETNEstore", 9570 auxType: auxSymOff, 9571 argLen: 3, 9572 faultOnNilArg0: true, 9573 symEffect: SymWrite, 9574 asm: x86.ASETNE, 9575 reg: regInfo{ 9576 inputs: []inputInfo{ 9577 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9578 }, 9579 }, 9580 }, 9581 { 9582 name: "SETLstore", 9583 auxType: auxSymOff, 9584 argLen: 3, 9585 faultOnNilArg0: true, 9586 symEffect: SymWrite, 9587 asm: x86.ASETLT, 9588 reg: regInfo{ 9589 inputs: []inputInfo{ 9590 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9591 }, 9592 }, 9593 }, 9594 { 9595 name: "SETLEstore", 9596 auxType: auxSymOff, 9597 argLen: 3, 9598 faultOnNilArg0: true, 9599 symEffect: SymWrite, 9600 asm: x86.ASETLE, 9601 reg: regInfo{ 9602 inputs: []inputInfo{ 9603 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9604 }, 9605 }, 9606 }, 9607 { 9608 name: "SETGstore", 9609 auxType: auxSymOff, 9610 argLen: 3, 9611 faultOnNilArg0: true, 9612 symEffect: SymWrite, 9613 asm: x86.ASETGT, 9614 reg: regInfo{ 9615 inputs: []inputInfo{ 9616 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9617 }, 9618 }, 9619 }, 9620 { 9621 name: "SETGEstore", 9622 auxType: auxSymOff, 9623 argLen: 3, 9624 faultOnNilArg0: true, 9625 symEffect: SymWrite, 9626 asm: x86.ASETGE, 9627 reg: regInfo{ 9628 inputs: []inputInfo{ 9629 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9630 }, 9631 }, 9632 }, 9633 { 9634 name: "SETBstore", 9635 auxType: auxSymOff, 9636 argLen: 3, 9637 faultOnNilArg0: true, 9638 symEffect: SymWrite, 9639 asm: x86.ASETCS, 9640 reg: regInfo{ 9641 inputs: []inputInfo{ 9642 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9643 }, 9644 }, 9645 }, 9646 { 9647 name: "SETBEstore", 9648 auxType: auxSymOff, 9649 argLen: 3, 9650 faultOnNilArg0: true, 9651 symEffect: SymWrite, 9652 asm: x86.ASETLS, 9653 reg: regInfo{ 9654 inputs: []inputInfo{ 9655 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9656 }, 9657 }, 9658 }, 9659 { 9660 name: "SETAstore", 9661 auxType: auxSymOff, 9662 argLen: 3, 9663 faultOnNilArg0: true, 9664 symEffect: SymWrite, 9665 asm: x86.ASETHI, 9666 reg: regInfo{ 9667 inputs: []inputInfo{ 9668 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9669 }, 9670 }, 9671 }, 9672 { 9673 name: "SETAEstore", 9674 auxType: auxSymOff, 9675 argLen: 3, 9676 faultOnNilArg0: true, 9677 symEffect: SymWrite, 9678 asm: x86.ASETCC, 9679 reg: regInfo{ 9680 inputs: []inputInfo{ 9681 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 9682 }, 9683 }, 9684 }, 9685 { 9686 name: "SETEQF", 9687 argLen: 1, 9688 clobberFlags: true, 9689 asm: x86.ASETEQ, 9690 reg: regInfo{ 9691 clobbers: 1, // AX 9692 outputs: []outputInfo{ 9693 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9694 }, 9695 }, 9696 }, 9697 { 9698 name: "SETNEF", 9699 argLen: 1, 9700 clobberFlags: true, 9701 asm: x86.ASETNE, 9702 reg: regInfo{ 9703 clobbers: 1, // AX 9704 outputs: []outputInfo{ 9705 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9706 }, 9707 }, 9708 }, 9709 { 9710 name: "SETORD", 9711 argLen: 1, 9712 asm: x86.ASETPC, 9713 reg: regInfo{ 9714 outputs: []outputInfo{ 9715 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9716 }, 9717 }, 9718 }, 9719 { 9720 name: "SETNAN", 9721 argLen: 1, 9722 asm: x86.ASETPS, 9723 reg: regInfo{ 9724 outputs: []outputInfo{ 9725 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9726 }, 9727 }, 9728 }, 9729 { 9730 name: "SETGF", 9731 argLen: 1, 9732 asm: x86.ASETHI, 9733 reg: regInfo{ 9734 outputs: []outputInfo{ 9735 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9736 }, 9737 }, 9738 }, 9739 { 9740 name: "SETGEF", 9741 argLen: 1, 9742 asm: x86.ASETCC, 9743 reg: regInfo{ 9744 outputs: []outputInfo{ 9745 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9746 }, 9747 }, 9748 }, 9749 { 9750 name: "MOVBQSX", 9751 argLen: 1, 9752 asm: x86.AMOVBQSX, 9753 reg: regInfo{ 9754 inputs: []inputInfo{ 9755 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9756 }, 9757 outputs: []outputInfo{ 9758 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9759 }, 9760 }, 9761 }, 9762 { 9763 name: "MOVBQZX", 9764 argLen: 1, 9765 asm: x86.AMOVBLZX, 9766 reg: regInfo{ 9767 inputs: []inputInfo{ 9768 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9769 }, 9770 outputs: []outputInfo{ 9771 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9772 }, 9773 }, 9774 }, 9775 { 9776 name: "MOVWQSX", 9777 argLen: 1, 9778 asm: x86.AMOVWQSX, 9779 reg: regInfo{ 9780 inputs: []inputInfo{ 9781 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9782 }, 9783 outputs: []outputInfo{ 9784 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9785 }, 9786 }, 9787 }, 9788 { 9789 name: "MOVWQZX", 9790 argLen: 1, 9791 asm: x86.AMOVWLZX, 9792 reg: regInfo{ 9793 inputs: []inputInfo{ 9794 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9795 }, 9796 outputs: []outputInfo{ 9797 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9798 }, 9799 }, 9800 }, 9801 { 9802 name: "MOVLQSX", 9803 argLen: 1, 9804 asm: x86.AMOVLQSX, 9805 reg: regInfo{ 9806 inputs: []inputInfo{ 9807 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9808 }, 9809 outputs: []outputInfo{ 9810 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9811 }, 9812 }, 9813 }, 9814 { 9815 name: "MOVLQZX", 9816 argLen: 1, 9817 asm: x86.AMOVL, 9818 reg: regInfo{ 9819 inputs: []inputInfo{ 9820 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9821 }, 9822 outputs: []outputInfo{ 9823 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9824 }, 9825 }, 9826 }, 9827 { 9828 name: "MOVLconst", 9829 auxType: auxInt32, 9830 argLen: 0, 9831 rematerializeable: true, 9832 asm: x86.AMOVL, 9833 reg: regInfo{ 9834 outputs: []outputInfo{ 9835 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9836 }, 9837 }, 9838 }, 9839 { 9840 name: "MOVQconst", 9841 auxType: auxInt64, 9842 argLen: 0, 9843 rematerializeable: true, 9844 asm: x86.AMOVQ, 9845 reg: regInfo{ 9846 outputs: []outputInfo{ 9847 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9848 }, 9849 }, 9850 }, 9851 { 9852 name: "CVTTSD2SL", 9853 argLen: 1, 9854 asm: x86.ACVTTSD2SL, 9855 reg: regInfo{ 9856 inputs: []inputInfo{ 9857 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9858 }, 9859 outputs: []outputInfo{ 9860 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9861 }, 9862 }, 9863 }, 9864 { 9865 name: "CVTTSD2SQ", 9866 argLen: 1, 9867 asm: x86.ACVTTSD2SQ, 9868 reg: regInfo{ 9869 inputs: []inputInfo{ 9870 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9871 }, 9872 outputs: []outputInfo{ 9873 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9874 }, 9875 }, 9876 }, 9877 { 9878 name: "CVTTSS2SL", 9879 argLen: 1, 9880 asm: x86.ACVTTSS2SL, 9881 reg: regInfo{ 9882 inputs: []inputInfo{ 9883 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9884 }, 9885 outputs: []outputInfo{ 9886 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9887 }, 9888 }, 9889 }, 9890 { 9891 name: "CVTTSS2SQ", 9892 argLen: 1, 9893 asm: x86.ACVTTSS2SQ, 9894 reg: regInfo{ 9895 inputs: []inputInfo{ 9896 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9897 }, 9898 outputs: []outputInfo{ 9899 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9900 }, 9901 }, 9902 }, 9903 { 9904 name: "CVTSL2SS", 9905 argLen: 1, 9906 asm: x86.ACVTSL2SS, 9907 reg: regInfo{ 9908 inputs: []inputInfo{ 9909 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9910 }, 9911 outputs: []outputInfo{ 9912 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9913 }, 9914 }, 9915 }, 9916 { 9917 name: "CVTSL2SD", 9918 argLen: 1, 9919 asm: x86.ACVTSL2SD, 9920 reg: regInfo{ 9921 inputs: []inputInfo{ 9922 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9923 }, 9924 outputs: []outputInfo{ 9925 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9926 }, 9927 }, 9928 }, 9929 { 9930 name: "CVTSQ2SS", 9931 argLen: 1, 9932 asm: x86.ACVTSQ2SS, 9933 reg: regInfo{ 9934 inputs: []inputInfo{ 9935 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9936 }, 9937 outputs: []outputInfo{ 9938 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9939 }, 9940 }, 9941 }, 9942 { 9943 name: "CVTSQ2SD", 9944 argLen: 1, 9945 asm: x86.ACVTSQ2SD, 9946 reg: regInfo{ 9947 inputs: []inputInfo{ 9948 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9949 }, 9950 outputs: []outputInfo{ 9951 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9952 }, 9953 }, 9954 }, 9955 { 9956 name: "CVTSD2SS", 9957 argLen: 1, 9958 asm: x86.ACVTSD2SS, 9959 reg: regInfo{ 9960 inputs: []inputInfo{ 9961 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9962 }, 9963 outputs: []outputInfo{ 9964 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9965 }, 9966 }, 9967 }, 9968 { 9969 name: "CVTSS2SD", 9970 argLen: 1, 9971 asm: x86.ACVTSS2SD, 9972 reg: regInfo{ 9973 inputs: []inputInfo{ 9974 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9975 }, 9976 outputs: []outputInfo{ 9977 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9978 }, 9979 }, 9980 }, 9981 { 9982 name: "MOVQi2f", 9983 argLen: 1, 9984 reg: regInfo{ 9985 inputs: []inputInfo{ 9986 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 9987 }, 9988 outputs: []outputInfo{ 9989 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9990 }, 9991 }, 9992 }, 9993 { 9994 name: "MOVQf2i", 9995 argLen: 1, 9996 reg: regInfo{ 9997 inputs: []inputInfo{ 9998 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 9999 }, 10000 outputs: []outputInfo{ 10001 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10002 }, 10003 }, 10004 }, 10005 { 10006 name: "MOVLi2f", 10007 argLen: 1, 10008 reg: regInfo{ 10009 inputs: []inputInfo{ 10010 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10011 }, 10012 outputs: []outputInfo{ 10013 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10014 }, 10015 }, 10016 }, 10017 { 10018 name: "MOVLf2i", 10019 argLen: 1, 10020 reg: regInfo{ 10021 inputs: []inputInfo{ 10022 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10023 }, 10024 outputs: []outputInfo{ 10025 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10026 }, 10027 }, 10028 }, 10029 { 10030 name: "PXOR", 10031 argLen: 2, 10032 commutative: true, 10033 resultInArg0: true, 10034 asm: x86.APXOR, 10035 reg: regInfo{ 10036 inputs: []inputInfo{ 10037 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10038 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10039 }, 10040 outputs: []outputInfo{ 10041 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10042 }, 10043 }, 10044 }, 10045 { 10046 name: "LEAQ", 10047 auxType: auxSymOff, 10048 argLen: 1, 10049 rematerializeable: true, 10050 symEffect: SymAddr, 10051 asm: x86.ALEAQ, 10052 reg: regInfo{ 10053 inputs: []inputInfo{ 10054 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10055 }, 10056 outputs: []outputInfo{ 10057 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10058 }, 10059 }, 10060 }, 10061 { 10062 name: "LEAL", 10063 auxType: auxSymOff, 10064 argLen: 1, 10065 rematerializeable: true, 10066 symEffect: SymAddr, 10067 asm: x86.ALEAL, 10068 reg: regInfo{ 10069 inputs: []inputInfo{ 10070 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10071 }, 10072 outputs: []outputInfo{ 10073 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10074 }, 10075 }, 10076 }, 10077 { 10078 name: "LEAW", 10079 auxType: auxSymOff, 10080 argLen: 1, 10081 rematerializeable: true, 10082 symEffect: SymAddr, 10083 asm: x86.ALEAW, 10084 reg: regInfo{ 10085 inputs: []inputInfo{ 10086 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10087 }, 10088 outputs: []outputInfo{ 10089 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10090 }, 10091 }, 10092 }, 10093 { 10094 name: "LEAQ1", 10095 auxType: auxSymOff, 10096 argLen: 2, 10097 commutative: true, 10098 symEffect: SymAddr, 10099 asm: x86.ALEAQ, 10100 reg: regInfo{ 10101 inputs: []inputInfo{ 10102 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10103 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10104 }, 10105 outputs: []outputInfo{ 10106 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10107 }, 10108 }, 10109 }, 10110 { 10111 name: "LEAL1", 10112 auxType: auxSymOff, 10113 argLen: 2, 10114 commutative: true, 10115 symEffect: SymAddr, 10116 asm: x86.ALEAL, 10117 reg: regInfo{ 10118 inputs: []inputInfo{ 10119 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10120 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10121 }, 10122 outputs: []outputInfo{ 10123 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10124 }, 10125 }, 10126 }, 10127 { 10128 name: "LEAW1", 10129 auxType: auxSymOff, 10130 argLen: 2, 10131 commutative: true, 10132 symEffect: SymAddr, 10133 asm: x86.ALEAW, 10134 reg: regInfo{ 10135 inputs: []inputInfo{ 10136 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10137 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10138 }, 10139 outputs: []outputInfo{ 10140 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10141 }, 10142 }, 10143 }, 10144 { 10145 name: "LEAQ2", 10146 auxType: auxSymOff, 10147 argLen: 2, 10148 symEffect: SymAddr, 10149 asm: x86.ALEAQ, 10150 reg: regInfo{ 10151 inputs: []inputInfo{ 10152 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10153 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10154 }, 10155 outputs: []outputInfo{ 10156 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10157 }, 10158 }, 10159 }, 10160 { 10161 name: "LEAL2", 10162 auxType: auxSymOff, 10163 argLen: 2, 10164 symEffect: SymAddr, 10165 asm: x86.ALEAL, 10166 reg: regInfo{ 10167 inputs: []inputInfo{ 10168 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10169 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10170 }, 10171 outputs: []outputInfo{ 10172 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10173 }, 10174 }, 10175 }, 10176 { 10177 name: "LEAW2", 10178 auxType: auxSymOff, 10179 argLen: 2, 10180 symEffect: SymAddr, 10181 asm: x86.ALEAW, 10182 reg: regInfo{ 10183 inputs: []inputInfo{ 10184 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10185 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10186 }, 10187 outputs: []outputInfo{ 10188 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10189 }, 10190 }, 10191 }, 10192 { 10193 name: "LEAQ4", 10194 auxType: auxSymOff, 10195 argLen: 2, 10196 symEffect: SymAddr, 10197 asm: x86.ALEAQ, 10198 reg: regInfo{ 10199 inputs: []inputInfo{ 10200 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10201 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10202 }, 10203 outputs: []outputInfo{ 10204 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10205 }, 10206 }, 10207 }, 10208 { 10209 name: "LEAL4", 10210 auxType: auxSymOff, 10211 argLen: 2, 10212 symEffect: SymAddr, 10213 asm: x86.ALEAL, 10214 reg: regInfo{ 10215 inputs: []inputInfo{ 10216 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10217 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10218 }, 10219 outputs: []outputInfo{ 10220 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10221 }, 10222 }, 10223 }, 10224 { 10225 name: "LEAW4", 10226 auxType: auxSymOff, 10227 argLen: 2, 10228 symEffect: SymAddr, 10229 asm: x86.ALEAW, 10230 reg: regInfo{ 10231 inputs: []inputInfo{ 10232 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10233 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10234 }, 10235 outputs: []outputInfo{ 10236 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10237 }, 10238 }, 10239 }, 10240 { 10241 name: "LEAQ8", 10242 auxType: auxSymOff, 10243 argLen: 2, 10244 symEffect: SymAddr, 10245 asm: x86.ALEAQ, 10246 reg: regInfo{ 10247 inputs: []inputInfo{ 10248 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10249 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10250 }, 10251 outputs: []outputInfo{ 10252 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10253 }, 10254 }, 10255 }, 10256 { 10257 name: "LEAL8", 10258 auxType: auxSymOff, 10259 argLen: 2, 10260 symEffect: SymAddr, 10261 asm: x86.ALEAL, 10262 reg: regInfo{ 10263 inputs: []inputInfo{ 10264 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10265 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10266 }, 10267 outputs: []outputInfo{ 10268 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10269 }, 10270 }, 10271 }, 10272 { 10273 name: "LEAW8", 10274 auxType: auxSymOff, 10275 argLen: 2, 10276 symEffect: SymAddr, 10277 asm: x86.ALEAW, 10278 reg: regInfo{ 10279 inputs: []inputInfo{ 10280 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10281 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10282 }, 10283 outputs: []outputInfo{ 10284 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10285 }, 10286 }, 10287 }, 10288 { 10289 name: "MOVBload", 10290 auxType: auxSymOff, 10291 argLen: 2, 10292 faultOnNilArg0: true, 10293 symEffect: SymRead, 10294 asm: x86.AMOVBLZX, 10295 reg: regInfo{ 10296 inputs: []inputInfo{ 10297 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10298 }, 10299 outputs: []outputInfo{ 10300 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10301 }, 10302 }, 10303 }, 10304 { 10305 name: "MOVBQSXload", 10306 auxType: auxSymOff, 10307 argLen: 2, 10308 faultOnNilArg0: true, 10309 symEffect: SymRead, 10310 asm: x86.AMOVBQSX, 10311 reg: regInfo{ 10312 inputs: []inputInfo{ 10313 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10314 }, 10315 outputs: []outputInfo{ 10316 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10317 }, 10318 }, 10319 }, 10320 { 10321 name: "MOVWload", 10322 auxType: auxSymOff, 10323 argLen: 2, 10324 faultOnNilArg0: true, 10325 symEffect: SymRead, 10326 asm: x86.AMOVWLZX, 10327 reg: regInfo{ 10328 inputs: []inputInfo{ 10329 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10330 }, 10331 outputs: []outputInfo{ 10332 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10333 }, 10334 }, 10335 }, 10336 { 10337 name: "MOVWQSXload", 10338 auxType: auxSymOff, 10339 argLen: 2, 10340 faultOnNilArg0: true, 10341 symEffect: SymRead, 10342 asm: x86.AMOVWQSX, 10343 reg: regInfo{ 10344 inputs: []inputInfo{ 10345 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10346 }, 10347 outputs: []outputInfo{ 10348 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10349 }, 10350 }, 10351 }, 10352 { 10353 name: "MOVLload", 10354 auxType: auxSymOff, 10355 argLen: 2, 10356 faultOnNilArg0: true, 10357 symEffect: SymRead, 10358 asm: x86.AMOVL, 10359 reg: regInfo{ 10360 inputs: []inputInfo{ 10361 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10362 }, 10363 outputs: []outputInfo{ 10364 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10365 }, 10366 }, 10367 }, 10368 { 10369 name: "MOVLQSXload", 10370 auxType: auxSymOff, 10371 argLen: 2, 10372 faultOnNilArg0: true, 10373 symEffect: SymRead, 10374 asm: x86.AMOVLQSX, 10375 reg: regInfo{ 10376 inputs: []inputInfo{ 10377 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10378 }, 10379 outputs: []outputInfo{ 10380 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10381 }, 10382 }, 10383 }, 10384 { 10385 name: "MOVQload", 10386 auxType: auxSymOff, 10387 argLen: 2, 10388 faultOnNilArg0: true, 10389 symEffect: SymRead, 10390 asm: x86.AMOVQ, 10391 reg: regInfo{ 10392 inputs: []inputInfo{ 10393 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10394 }, 10395 outputs: []outputInfo{ 10396 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10397 }, 10398 }, 10399 }, 10400 { 10401 name: "MOVBstore", 10402 auxType: auxSymOff, 10403 argLen: 3, 10404 faultOnNilArg0: true, 10405 symEffect: SymWrite, 10406 asm: x86.AMOVB, 10407 reg: regInfo{ 10408 inputs: []inputInfo{ 10409 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10410 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10411 }, 10412 }, 10413 }, 10414 { 10415 name: "MOVWstore", 10416 auxType: auxSymOff, 10417 argLen: 3, 10418 faultOnNilArg0: true, 10419 symEffect: SymWrite, 10420 asm: x86.AMOVW, 10421 reg: regInfo{ 10422 inputs: []inputInfo{ 10423 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10424 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10425 }, 10426 }, 10427 }, 10428 { 10429 name: "MOVLstore", 10430 auxType: auxSymOff, 10431 argLen: 3, 10432 faultOnNilArg0: true, 10433 symEffect: SymWrite, 10434 asm: x86.AMOVL, 10435 reg: regInfo{ 10436 inputs: []inputInfo{ 10437 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10438 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10439 }, 10440 }, 10441 }, 10442 { 10443 name: "MOVQstore", 10444 auxType: auxSymOff, 10445 argLen: 3, 10446 faultOnNilArg0: true, 10447 symEffect: SymWrite, 10448 asm: x86.AMOVQ, 10449 reg: regInfo{ 10450 inputs: []inputInfo{ 10451 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10452 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10453 }, 10454 }, 10455 }, 10456 { 10457 name: "MOVOload", 10458 auxType: auxSymOff, 10459 argLen: 2, 10460 faultOnNilArg0: true, 10461 symEffect: SymRead, 10462 asm: x86.AMOVUPS, 10463 reg: regInfo{ 10464 inputs: []inputInfo{ 10465 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10466 }, 10467 outputs: []outputInfo{ 10468 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10469 }, 10470 }, 10471 }, 10472 { 10473 name: "MOVOstore", 10474 auxType: auxSymOff, 10475 argLen: 3, 10476 faultOnNilArg0: true, 10477 symEffect: SymWrite, 10478 asm: x86.AMOVUPS, 10479 reg: regInfo{ 10480 inputs: []inputInfo{ 10481 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10482 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10483 }, 10484 }, 10485 }, 10486 { 10487 name: "MOVBloadidx1", 10488 auxType: auxSymOff, 10489 argLen: 3, 10490 commutative: true, 10491 symEffect: SymRead, 10492 asm: x86.AMOVBLZX, 10493 reg: regInfo{ 10494 inputs: []inputInfo{ 10495 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10496 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10497 }, 10498 outputs: []outputInfo{ 10499 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10500 }, 10501 }, 10502 }, 10503 { 10504 name: "MOVWloadidx1", 10505 auxType: auxSymOff, 10506 argLen: 3, 10507 commutative: true, 10508 symEffect: SymRead, 10509 asm: x86.AMOVWLZX, 10510 reg: regInfo{ 10511 inputs: []inputInfo{ 10512 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10513 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10514 }, 10515 outputs: []outputInfo{ 10516 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10517 }, 10518 }, 10519 }, 10520 { 10521 name: "MOVWloadidx2", 10522 auxType: auxSymOff, 10523 argLen: 3, 10524 symEffect: SymRead, 10525 asm: x86.AMOVWLZX, 10526 reg: regInfo{ 10527 inputs: []inputInfo{ 10528 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10529 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10530 }, 10531 outputs: []outputInfo{ 10532 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10533 }, 10534 }, 10535 }, 10536 { 10537 name: "MOVLloadidx1", 10538 auxType: auxSymOff, 10539 argLen: 3, 10540 commutative: true, 10541 symEffect: SymRead, 10542 asm: x86.AMOVL, 10543 reg: regInfo{ 10544 inputs: []inputInfo{ 10545 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10546 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10547 }, 10548 outputs: []outputInfo{ 10549 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10550 }, 10551 }, 10552 }, 10553 { 10554 name: "MOVLloadidx4", 10555 auxType: auxSymOff, 10556 argLen: 3, 10557 symEffect: SymRead, 10558 asm: x86.AMOVL, 10559 reg: regInfo{ 10560 inputs: []inputInfo{ 10561 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10562 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10563 }, 10564 outputs: []outputInfo{ 10565 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10566 }, 10567 }, 10568 }, 10569 { 10570 name: "MOVLloadidx8", 10571 auxType: auxSymOff, 10572 argLen: 3, 10573 symEffect: SymRead, 10574 asm: x86.AMOVL, 10575 reg: regInfo{ 10576 inputs: []inputInfo{ 10577 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10578 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10579 }, 10580 outputs: []outputInfo{ 10581 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10582 }, 10583 }, 10584 }, 10585 { 10586 name: "MOVQloadidx1", 10587 auxType: auxSymOff, 10588 argLen: 3, 10589 commutative: true, 10590 symEffect: SymRead, 10591 asm: x86.AMOVQ, 10592 reg: regInfo{ 10593 inputs: []inputInfo{ 10594 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10595 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10596 }, 10597 outputs: []outputInfo{ 10598 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10599 }, 10600 }, 10601 }, 10602 { 10603 name: "MOVQloadidx8", 10604 auxType: auxSymOff, 10605 argLen: 3, 10606 symEffect: SymRead, 10607 asm: x86.AMOVQ, 10608 reg: regInfo{ 10609 inputs: []inputInfo{ 10610 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10611 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10612 }, 10613 outputs: []outputInfo{ 10614 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10615 }, 10616 }, 10617 }, 10618 { 10619 name: "MOVBstoreidx1", 10620 auxType: auxSymOff, 10621 argLen: 4, 10622 symEffect: SymWrite, 10623 asm: x86.AMOVB, 10624 reg: regInfo{ 10625 inputs: []inputInfo{ 10626 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10627 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10628 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10629 }, 10630 }, 10631 }, 10632 { 10633 name: "MOVWstoreidx1", 10634 auxType: auxSymOff, 10635 argLen: 4, 10636 symEffect: SymWrite, 10637 asm: x86.AMOVW, 10638 reg: regInfo{ 10639 inputs: []inputInfo{ 10640 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10641 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10642 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10643 }, 10644 }, 10645 }, 10646 { 10647 name: "MOVWstoreidx2", 10648 auxType: auxSymOff, 10649 argLen: 4, 10650 symEffect: SymWrite, 10651 asm: x86.AMOVW, 10652 reg: regInfo{ 10653 inputs: []inputInfo{ 10654 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10655 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10656 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10657 }, 10658 }, 10659 }, 10660 { 10661 name: "MOVLstoreidx1", 10662 auxType: auxSymOff, 10663 argLen: 4, 10664 symEffect: SymWrite, 10665 asm: x86.AMOVL, 10666 reg: regInfo{ 10667 inputs: []inputInfo{ 10668 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10669 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10670 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10671 }, 10672 }, 10673 }, 10674 { 10675 name: "MOVLstoreidx4", 10676 auxType: auxSymOff, 10677 argLen: 4, 10678 symEffect: SymWrite, 10679 asm: x86.AMOVL, 10680 reg: regInfo{ 10681 inputs: []inputInfo{ 10682 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10683 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10684 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10685 }, 10686 }, 10687 }, 10688 { 10689 name: "MOVLstoreidx8", 10690 auxType: auxSymOff, 10691 argLen: 4, 10692 symEffect: SymWrite, 10693 asm: x86.AMOVL, 10694 reg: regInfo{ 10695 inputs: []inputInfo{ 10696 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10697 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10698 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10699 }, 10700 }, 10701 }, 10702 { 10703 name: "MOVQstoreidx1", 10704 auxType: auxSymOff, 10705 argLen: 4, 10706 symEffect: SymWrite, 10707 asm: x86.AMOVQ, 10708 reg: regInfo{ 10709 inputs: []inputInfo{ 10710 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10711 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10712 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10713 }, 10714 }, 10715 }, 10716 { 10717 name: "MOVQstoreidx8", 10718 auxType: auxSymOff, 10719 argLen: 4, 10720 symEffect: SymWrite, 10721 asm: x86.AMOVQ, 10722 reg: regInfo{ 10723 inputs: []inputInfo{ 10724 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10725 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10726 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10727 }, 10728 }, 10729 }, 10730 { 10731 name: "MOVBstoreconst", 10732 auxType: auxSymValAndOff, 10733 argLen: 2, 10734 faultOnNilArg0: true, 10735 symEffect: SymWrite, 10736 asm: x86.AMOVB, 10737 reg: regInfo{ 10738 inputs: []inputInfo{ 10739 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10740 }, 10741 }, 10742 }, 10743 { 10744 name: "MOVWstoreconst", 10745 auxType: auxSymValAndOff, 10746 argLen: 2, 10747 faultOnNilArg0: true, 10748 symEffect: SymWrite, 10749 asm: x86.AMOVW, 10750 reg: regInfo{ 10751 inputs: []inputInfo{ 10752 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10753 }, 10754 }, 10755 }, 10756 { 10757 name: "MOVLstoreconst", 10758 auxType: auxSymValAndOff, 10759 argLen: 2, 10760 faultOnNilArg0: true, 10761 symEffect: SymWrite, 10762 asm: x86.AMOVL, 10763 reg: regInfo{ 10764 inputs: []inputInfo{ 10765 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10766 }, 10767 }, 10768 }, 10769 { 10770 name: "MOVQstoreconst", 10771 auxType: auxSymValAndOff, 10772 argLen: 2, 10773 faultOnNilArg0: true, 10774 symEffect: SymWrite, 10775 asm: x86.AMOVQ, 10776 reg: regInfo{ 10777 inputs: []inputInfo{ 10778 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10779 }, 10780 }, 10781 }, 10782 { 10783 name: "MOVBstoreconstidx1", 10784 auxType: auxSymValAndOff, 10785 argLen: 3, 10786 symEffect: SymWrite, 10787 asm: x86.AMOVB, 10788 reg: regInfo{ 10789 inputs: []inputInfo{ 10790 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10791 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10792 }, 10793 }, 10794 }, 10795 { 10796 name: "MOVWstoreconstidx1", 10797 auxType: auxSymValAndOff, 10798 argLen: 3, 10799 symEffect: SymWrite, 10800 asm: x86.AMOVW, 10801 reg: regInfo{ 10802 inputs: []inputInfo{ 10803 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10804 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10805 }, 10806 }, 10807 }, 10808 { 10809 name: "MOVWstoreconstidx2", 10810 auxType: auxSymValAndOff, 10811 argLen: 3, 10812 symEffect: SymWrite, 10813 asm: x86.AMOVW, 10814 reg: regInfo{ 10815 inputs: []inputInfo{ 10816 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10817 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10818 }, 10819 }, 10820 }, 10821 { 10822 name: "MOVLstoreconstidx1", 10823 auxType: auxSymValAndOff, 10824 argLen: 3, 10825 symEffect: SymWrite, 10826 asm: x86.AMOVL, 10827 reg: regInfo{ 10828 inputs: []inputInfo{ 10829 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10830 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10831 }, 10832 }, 10833 }, 10834 { 10835 name: "MOVLstoreconstidx4", 10836 auxType: auxSymValAndOff, 10837 argLen: 3, 10838 symEffect: SymWrite, 10839 asm: x86.AMOVL, 10840 reg: regInfo{ 10841 inputs: []inputInfo{ 10842 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10843 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10844 }, 10845 }, 10846 }, 10847 { 10848 name: "MOVQstoreconstidx1", 10849 auxType: auxSymValAndOff, 10850 argLen: 3, 10851 symEffect: SymWrite, 10852 asm: x86.AMOVQ, 10853 reg: regInfo{ 10854 inputs: []inputInfo{ 10855 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10856 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10857 }, 10858 }, 10859 }, 10860 { 10861 name: "MOVQstoreconstidx8", 10862 auxType: auxSymValAndOff, 10863 argLen: 3, 10864 symEffect: SymWrite, 10865 asm: x86.AMOVQ, 10866 reg: regInfo{ 10867 inputs: []inputInfo{ 10868 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10869 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 10870 }, 10871 }, 10872 }, 10873 { 10874 name: "DUFFZERO", 10875 auxType: auxInt64, 10876 argLen: 3, 10877 faultOnNilArg0: true, 10878 reg: regInfo{ 10879 inputs: []inputInfo{ 10880 {0, 128}, // DI 10881 {1, 65536}, // X0 10882 }, 10883 clobbers: 128, // DI 10884 }, 10885 }, 10886 { 10887 name: "MOVOconst", 10888 auxType: auxInt128, 10889 argLen: 0, 10890 rematerializeable: true, 10891 reg: regInfo{ 10892 outputs: []outputInfo{ 10893 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10894 }, 10895 }, 10896 }, 10897 { 10898 name: "REPSTOSQ", 10899 argLen: 4, 10900 faultOnNilArg0: true, 10901 reg: regInfo{ 10902 inputs: []inputInfo{ 10903 {0, 128}, // DI 10904 {1, 2}, // CX 10905 {2, 1}, // AX 10906 }, 10907 clobbers: 130, // CX DI 10908 }, 10909 }, 10910 { 10911 name: "CALLstatic", 10912 auxType: auxSymOff, 10913 argLen: 1, 10914 clobberFlags: true, 10915 call: true, 10916 symEffect: SymNone, 10917 reg: regInfo{ 10918 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10919 }, 10920 }, 10921 { 10922 name: "CALLclosure", 10923 auxType: auxInt64, 10924 argLen: 3, 10925 clobberFlags: true, 10926 call: true, 10927 reg: regInfo{ 10928 inputs: []inputInfo{ 10929 {1, 4}, // DX 10930 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10931 }, 10932 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10933 }, 10934 }, 10935 { 10936 name: "CALLinter", 10937 auxType: auxInt64, 10938 argLen: 2, 10939 clobberFlags: true, 10940 call: true, 10941 reg: regInfo{ 10942 inputs: []inputInfo{ 10943 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10944 }, 10945 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 10946 }, 10947 }, 10948 { 10949 name: "DUFFCOPY", 10950 auxType: auxInt64, 10951 argLen: 3, 10952 clobberFlags: true, 10953 faultOnNilArg0: true, 10954 faultOnNilArg1: true, 10955 reg: regInfo{ 10956 inputs: []inputInfo{ 10957 {0, 128}, // DI 10958 {1, 64}, // SI 10959 }, 10960 clobbers: 65728, // SI DI X0 10961 }, 10962 }, 10963 { 10964 name: "REPMOVSQ", 10965 argLen: 4, 10966 faultOnNilArg0: true, 10967 faultOnNilArg1: true, 10968 reg: regInfo{ 10969 inputs: []inputInfo{ 10970 {0, 128}, // DI 10971 {1, 64}, // SI 10972 {2, 2}, // CX 10973 }, 10974 clobbers: 194, // CX SI DI 10975 }, 10976 }, 10977 { 10978 name: "InvertFlags", 10979 argLen: 1, 10980 reg: regInfo{}, 10981 }, 10982 { 10983 name: "LoweredGetG", 10984 argLen: 1, 10985 reg: regInfo{ 10986 outputs: []outputInfo{ 10987 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 10988 }, 10989 }, 10990 }, 10991 { 10992 name: "LoweredGetClosurePtr", 10993 argLen: 0, 10994 zeroWidth: true, 10995 reg: regInfo{ 10996 outputs: []outputInfo{ 10997 {0, 4}, // DX 10998 }, 10999 }, 11000 }, 11001 { 11002 name: "LoweredGetCallerPC", 11003 argLen: 0, 11004 rematerializeable: true, 11005 reg: regInfo{ 11006 outputs: []outputInfo{ 11007 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11008 }, 11009 }, 11010 }, 11011 { 11012 name: "LoweredGetCallerSP", 11013 argLen: 0, 11014 rematerializeable: true, 11015 reg: regInfo{ 11016 outputs: []outputInfo{ 11017 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11018 }, 11019 }, 11020 }, 11021 { 11022 name: "LoweredNilCheck", 11023 argLen: 2, 11024 clobberFlags: true, 11025 nilCheck: true, 11026 faultOnNilArg0: true, 11027 reg: regInfo{ 11028 inputs: []inputInfo{ 11029 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11030 }, 11031 }, 11032 }, 11033 { 11034 name: "LoweredWB", 11035 auxType: auxSym, 11036 argLen: 3, 11037 clobberFlags: true, 11038 symEffect: SymNone, 11039 reg: regInfo{ 11040 inputs: []inputInfo{ 11041 {0, 128}, // DI 11042 {1, 1}, // AX 11043 }, 11044 clobbers: 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 11045 }, 11046 }, 11047 { 11048 name: "FlagEQ", 11049 argLen: 0, 11050 reg: regInfo{}, 11051 }, 11052 { 11053 name: "FlagLT_ULT", 11054 argLen: 0, 11055 reg: regInfo{}, 11056 }, 11057 { 11058 name: "FlagLT_UGT", 11059 argLen: 0, 11060 reg: regInfo{}, 11061 }, 11062 { 11063 name: "FlagGT_UGT", 11064 argLen: 0, 11065 reg: regInfo{}, 11066 }, 11067 { 11068 name: "FlagGT_ULT", 11069 argLen: 0, 11070 reg: regInfo{}, 11071 }, 11072 { 11073 name: "MOVLatomicload", 11074 auxType: auxSymOff, 11075 argLen: 2, 11076 faultOnNilArg0: true, 11077 symEffect: SymRead, 11078 asm: x86.AMOVL, 11079 reg: regInfo{ 11080 inputs: []inputInfo{ 11081 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 11082 }, 11083 outputs: []outputInfo{ 11084 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11085 }, 11086 }, 11087 }, 11088 { 11089 name: "MOVQatomicload", 11090 auxType: auxSymOff, 11091 argLen: 2, 11092 faultOnNilArg0: true, 11093 symEffect: SymRead, 11094 asm: x86.AMOVQ, 11095 reg: regInfo{ 11096 inputs: []inputInfo{ 11097 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 11098 }, 11099 outputs: []outputInfo{ 11100 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11101 }, 11102 }, 11103 }, 11104 { 11105 name: "XCHGL", 11106 auxType: auxSymOff, 11107 argLen: 3, 11108 resultInArg0: true, 11109 faultOnNilArg1: true, 11110 hasSideEffects: true, 11111 symEffect: SymRdWr, 11112 asm: x86.AXCHGL, 11113 reg: regInfo{ 11114 inputs: []inputInfo{ 11115 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11116 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 11117 }, 11118 outputs: []outputInfo{ 11119 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11120 }, 11121 }, 11122 }, 11123 { 11124 name: "XCHGQ", 11125 auxType: auxSymOff, 11126 argLen: 3, 11127 resultInArg0: true, 11128 faultOnNilArg1: true, 11129 hasSideEffects: true, 11130 symEffect: SymRdWr, 11131 asm: x86.AXCHGQ, 11132 reg: regInfo{ 11133 inputs: []inputInfo{ 11134 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11135 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 11136 }, 11137 outputs: []outputInfo{ 11138 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11139 }, 11140 }, 11141 }, 11142 { 11143 name: "XADDLlock", 11144 auxType: auxSymOff, 11145 argLen: 3, 11146 resultInArg0: true, 11147 clobberFlags: true, 11148 faultOnNilArg1: true, 11149 hasSideEffects: true, 11150 symEffect: SymRdWr, 11151 asm: x86.AXADDL, 11152 reg: regInfo{ 11153 inputs: []inputInfo{ 11154 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11155 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 11156 }, 11157 outputs: []outputInfo{ 11158 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11159 }, 11160 }, 11161 }, 11162 { 11163 name: "XADDQlock", 11164 auxType: auxSymOff, 11165 argLen: 3, 11166 resultInArg0: true, 11167 clobberFlags: true, 11168 faultOnNilArg1: true, 11169 hasSideEffects: true, 11170 symEffect: SymRdWr, 11171 asm: x86.AXADDQ, 11172 reg: regInfo{ 11173 inputs: []inputInfo{ 11174 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11175 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 11176 }, 11177 outputs: []outputInfo{ 11178 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11179 }, 11180 }, 11181 }, 11182 { 11183 name: "AddTupleFirst32", 11184 argLen: 2, 11185 reg: regInfo{}, 11186 }, 11187 { 11188 name: "AddTupleFirst64", 11189 argLen: 2, 11190 reg: regInfo{}, 11191 }, 11192 { 11193 name: "CMPXCHGLlock", 11194 auxType: auxSymOff, 11195 argLen: 4, 11196 clobberFlags: true, 11197 faultOnNilArg0: true, 11198 hasSideEffects: true, 11199 symEffect: SymRdWr, 11200 asm: x86.ACMPXCHGL, 11201 reg: regInfo{ 11202 inputs: []inputInfo{ 11203 {1, 1}, // AX 11204 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11205 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11206 }, 11207 clobbers: 1, // AX 11208 outputs: []outputInfo{ 11209 {1, 0}, 11210 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11211 }, 11212 }, 11213 }, 11214 { 11215 name: "CMPXCHGQlock", 11216 auxType: auxSymOff, 11217 argLen: 4, 11218 clobberFlags: true, 11219 faultOnNilArg0: true, 11220 hasSideEffects: true, 11221 symEffect: SymRdWr, 11222 asm: x86.ACMPXCHGQ, 11223 reg: regInfo{ 11224 inputs: []inputInfo{ 11225 {1, 1}, // AX 11226 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11227 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11228 }, 11229 clobbers: 1, // AX 11230 outputs: []outputInfo{ 11231 {1, 0}, 11232 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11233 }, 11234 }, 11235 }, 11236 { 11237 name: "ANDBlock", 11238 auxType: auxSymOff, 11239 argLen: 3, 11240 clobberFlags: true, 11241 faultOnNilArg0: true, 11242 hasSideEffects: true, 11243 symEffect: SymRdWr, 11244 asm: x86.AANDB, 11245 reg: regInfo{ 11246 inputs: []inputInfo{ 11247 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11248 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 11249 }, 11250 }, 11251 }, 11252 { 11253 name: "ORBlock", 11254 auxType: auxSymOff, 11255 argLen: 3, 11256 clobberFlags: true, 11257 faultOnNilArg0: true, 11258 hasSideEffects: true, 11259 symEffect: SymRdWr, 11260 asm: x86.AORB, 11261 reg: regInfo{ 11262 inputs: []inputInfo{ 11263 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 11264 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 11265 }, 11266 }, 11267 }, 11268 11269 { 11270 name: "ADD", 11271 argLen: 2, 11272 commutative: true, 11273 asm: arm.AADD, 11274 reg: regInfo{ 11275 inputs: []inputInfo{ 11276 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11277 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11278 }, 11279 outputs: []outputInfo{ 11280 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11281 }, 11282 }, 11283 }, 11284 { 11285 name: "ADDconst", 11286 auxType: auxInt32, 11287 argLen: 1, 11288 asm: arm.AADD, 11289 reg: regInfo{ 11290 inputs: []inputInfo{ 11291 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 11292 }, 11293 outputs: []outputInfo{ 11294 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11295 }, 11296 }, 11297 }, 11298 { 11299 name: "SUB", 11300 argLen: 2, 11301 asm: arm.ASUB, 11302 reg: regInfo{ 11303 inputs: []inputInfo{ 11304 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11305 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11306 }, 11307 outputs: []outputInfo{ 11308 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11309 }, 11310 }, 11311 }, 11312 { 11313 name: "SUBconst", 11314 auxType: auxInt32, 11315 argLen: 1, 11316 asm: arm.ASUB, 11317 reg: regInfo{ 11318 inputs: []inputInfo{ 11319 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11320 }, 11321 outputs: []outputInfo{ 11322 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11323 }, 11324 }, 11325 }, 11326 { 11327 name: "RSB", 11328 argLen: 2, 11329 asm: arm.ARSB, 11330 reg: regInfo{ 11331 inputs: []inputInfo{ 11332 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11333 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11334 }, 11335 outputs: []outputInfo{ 11336 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11337 }, 11338 }, 11339 }, 11340 { 11341 name: "RSBconst", 11342 auxType: auxInt32, 11343 argLen: 1, 11344 asm: arm.ARSB, 11345 reg: regInfo{ 11346 inputs: []inputInfo{ 11347 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11348 }, 11349 outputs: []outputInfo{ 11350 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11351 }, 11352 }, 11353 }, 11354 { 11355 name: "MUL", 11356 argLen: 2, 11357 commutative: true, 11358 asm: arm.AMUL, 11359 reg: regInfo{ 11360 inputs: []inputInfo{ 11361 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11362 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11363 }, 11364 outputs: []outputInfo{ 11365 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11366 }, 11367 }, 11368 }, 11369 { 11370 name: "HMUL", 11371 argLen: 2, 11372 commutative: true, 11373 asm: arm.AMULL, 11374 reg: regInfo{ 11375 inputs: []inputInfo{ 11376 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11377 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11378 }, 11379 outputs: []outputInfo{ 11380 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11381 }, 11382 }, 11383 }, 11384 { 11385 name: "HMULU", 11386 argLen: 2, 11387 commutative: true, 11388 asm: arm.AMULLU, 11389 reg: regInfo{ 11390 inputs: []inputInfo{ 11391 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11392 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11393 }, 11394 outputs: []outputInfo{ 11395 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11396 }, 11397 }, 11398 }, 11399 { 11400 name: "CALLudiv", 11401 argLen: 2, 11402 clobberFlags: true, 11403 reg: regInfo{ 11404 inputs: []inputInfo{ 11405 {0, 2}, // R1 11406 {1, 1}, // R0 11407 }, 11408 clobbers: 16396, // R2 R3 R14 11409 outputs: []outputInfo{ 11410 {0, 1}, // R0 11411 {1, 2}, // R1 11412 }, 11413 }, 11414 }, 11415 { 11416 name: "ADDS", 11417 argLen: 2, 11418 commutative: true, 11419 asm: arm.AADD, 11420 reg: regInfo{ 11421 inputs: []inputInfo{ 11422 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11423 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11424 }, 11425 outputs: []outputInfo{ 11426 {1, 0}, 11427 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11428 }, 11429 }, 11430 }, 11431 { 11432 name: "ADDSconst", 11433 auxType: auxInt32, 11434 argLen: 1, 11435 asm: arm.AADD, 11436 reg: regInfo{ 11437 inputs: []inputInfo{ 11438 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11439 }, 11440 outputs: []outputInfo{ 11441 {1, 0}, 11442 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11443 }, 11444 }, 11445 }, 11446 { 11447 name: "ADC", 11448 argLen: 3, 11449 commutative: true, 11450 asm: arm.AADC, 11451 reg: regInfo{ 11452 inputs: []inputInfo{ 11453 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11454 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11455 }, 11456 outputs: []outputInfo{ 11457 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11458 }, 11459 }, 11460 }, 11461 { 11462 name: "ADCconst", 11463 auxType: auxInt32, 11464 argLen: 2, 11465 asm: arm.AADC, 11466 reg: regInfo{ 11467 inputs: []inputInfo{ 11468 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11469 }, 11470 outputs: []outputInfo{ 11471 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11472 }, 11473 }, 11474 }, 11475 { 11476 name: "SUBS", 11477 argLen: 2, 11478 asm: arm.ASUB, 11479 reg: regInfo{ 11480 inputs: []inputInfo{ 11481 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11482 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11483 }, 11484 outputs: []outputInfo{ 11485 {1, 0}, 11486 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11487 }, 11488 }, 11489 }, 11490 { 11491 name: "SUBSconst", 11492 auxType: auxInt32, 11493 argLen: 1, 11494 asm: arm.ASUB, 11495 reg: regInfo{ 11496 inputs: []inputInfo{ 11497 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11498 }, 11499 outputs: []outputInfo{ 11500 {1, 0}, 11501 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11502 }, 11503 }, 11504 }, 11505 { 11506 name: "RSBSconst", 11507 auxType: auxInt32, 11508 argLen: 1, 11509 asm: arm.ARSB, 11510 reg: regInfo{ 11511 inputs: []inputInfo{ 11512 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11513 }, 11514 outputs: []outputInfo{ 11515 {1, 0}, 11516 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11517 }, 11518 }, 11519 }, 11520 { 11521 name: "SBC", 11522 argLen: 3, 11523 asm: arm.ASBC, 11524 reg: regInfo{ 11525 inputs: []inputInfo{ 11526 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11527 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11528 }, 11529 outputs: []outputInfo{ 11530 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11531 }, 11532 }, 11533 }, 11534 { 11535 name: "SBCconst", 11536 auxType: auxInt32, 11537 argLen: 2, 11538 asm: arm.ASBC, 11539 reg: regInfo{ 11540 inputs: []inputInfo{ 11541 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11542 }, 11543 outputs: []outputInfo{ 11544 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11545 }, 11546 }, 11547 }, 11548 { 11549 name: "RSCconst", 11550 auxType: auxInt32, 11551 argLen: 2, 11552 asm: arm.ARSC, 11553 reg: regInfo{ 11554 inputs: []inputInfo{ 11555 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11556 }, 11557 outputs: []outputInfo{ 11558 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11559 }, 11560 }, 11561 }, 11562 { 11563 name: "MULLU", 11564 argLen: 2, 11565 commutative: true, 11566 asm: arm.AMULLU, 11567 reg: regInfo{ 11568 inputs: []inputInfo{ 11569 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11570 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11571 }, 11572 outputs: []outputInfo{ 11573 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11574 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11575 }, 11576 }, 11577 }, 11578 { 11579 name: "MULA", 11580 argLen: 3, 11581 asm: arm.AMULA, 11582 reg: regInfo{ 11583 inputs: []inputInfo{ 11584 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11585 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11586 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11587 }, 11588 outputs: []outputInfo{ 11589 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11590 }, 11591 }, 11592 }, 11593 { 11594 name: "MULS", 11595 argLen: 3, 11596 asm: arm.AMULS, 11597 reg: regInfo{ 11598 inputs: []inputInfo{ 11599 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11600 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11601 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11602 }, 11603 outputs: []outputInfo{ 11604 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11605 }, 11606 }, 11607 }, 11608 { 11609 name: "ADDF", 11610 argLen: 2, 11611 commutative: true, 11612 asm: arm.AADDF, 11613 reg: regInfo{ 11614 inputs: []inputInfo{ 11615 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11616 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11617 }, 11618 outputs: []outputInfo{ 11619 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11620 }, 11621 }, 11622 }, 11623 { 11624 name: "ADDD", 11625 argLen: 2, 11626 commutative: true, 11627 asm: arm.AADDD, 11628 reg: regInfo{ 11629 inputs: []inputInfo{ 11630 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11631 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11632 }, 11633 outputs: []outputInfo{ 11634 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11635 }, 11636 }, 11637 }, 11638 { 11639 name: "SUBF", 11640 argLen: 2, 11641 asm: arm.ASUBF, 11642 reg: regInfo{ 11643 inputs: []inputInfo{ 11644 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11645 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11646 }, 11647 outputs: []outputInfo{ 11648 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11649 }, 11650 }, 11651 }, 11652 { 11653 name: "SUBD", 11654 argLen: 2, 11655 asm: arm.ASUBD, 11656 reg: regInfo{ 11657 inputs: []inputInfo{ 11658 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11659 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11660 }, 11661 outputs: []outputInfo{ 11662 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11663 }, 11664 }, 11665 }, 11666 { 11667 name: "MULF", 11668 argLen: 2, 11669 commutative: true, 11670 asm: arm.AMULF, 11671 reg: regInfo{ 11672 inputs: []inputInfo{ 11673 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11674 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11675 }, 11676 outputs: []outputInfo{ 11677 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11678 }, 11679 }, 11680 }, 11681 { 11682 name: "MULD", 11683 argLen: 2, 11684 commutative: true, 11685 asm: arm.AMULD, 11686 reg: regInfo{ 11687 inputs: []inputInfo{ 11688 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11689 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11690 }, 11691 outputs: []outputInfo{ 11692 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11693 }, 11694 }, 11695 }, 11696 { 11697 name: "NMULF", 11698 argLen: 2, 11699 commutative: true, 11700 asm: arm.ANMULF, 11701 reg: regInfo{ 11702 inputs: []inputInfo{ 11703 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11704 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11705 }, 11706 outputs: []outputInfo{ 11707 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11708 }, 11709 }, 11710 }, 11711 { 11712 name: "NMULD", 11713 argLen: 2, 11714 commutative: true, 11715 asm: arm.ANMULD, 11716 reg: regInfo{ 11717 inputs: []inputInfo{ 11718 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11719 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11720 }, 11721 outputs: []outputInfo{ 11722 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11723 }, 11724 }, 11725 }, 11726 { 11727 name: "DIVF", 11728 argLen: 2, 11729 asm: arm.ADIVF, 11730 reg: regInfo{ 11731 inputs: []inputInfo{ 11732 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11733 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11734 }, 11735 outputs: []outputInfo{ 11736 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11737 }, 11738 }, 11739 }, 11740 { 11741 name: "DIVD", 11742 argLen: 2, 11743 asm: arm.ADIVD, 11744 reg: regInfo{ 11745 inputs: []inputInfo{ 11746 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11747 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11748 }, 11749 outputs: []outputInfo{ 11750 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11751 }, 11752 }, 11753 }, 11754 { 11755 name: "MULAF", 11756 argLen: 3, 11757 resultInArg0: true, 11758 asm: arm.AMULAF, 11759 reg: regInfo{ 11760 inputs: []inputInfo{ 11761 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11762 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11763 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11764 }, 11765 outputs: []outputInfo{ 11766 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11767 }, 11768 }, 11769 }, 11770 { 11771 name: "MULAD", 11772 argLen: 3, 11773 resultInArg0: true, 11774 asm: arm.AMULAD, 11775 reg: regInfo{ 11776 inputs: []inputInfo{ 11777 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11778 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11779 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11780 }, 11781 outputs: []outputInfo{ 11782 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11783 }, 11784 }, 11785 }, 11786 { 11787 name: "MULSF", 11788 argLen: 3, 11789 resultInArg0: true, 11790 asm: arm.AMULSF, 11791 reg: regInfo{ 11792 inputs: []inputInfo{ 11793 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11794 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11795 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11796 }, 11797 outputs: []outputInfo{ 11798 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11799 }, 11800 }, 11801 }, 11802 { 11803 name: "MULSD", 11804 argLen: 3, 11805 resultInArg0: true, 11806 asm: arm.AMULSD, 11807 reg: regInfo{ 11808 inputs: []inputInfo{ 11809 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11810 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11811 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11812 }, 11813 outputs: []outputInfo{ 11814 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11815 }, 11816 }, 11817 }, 11818 { 11819 name: "AND", 11820 argLen: 2, 11821 commutative: true, 11822 asm: arm.AAND, 11823 reg: regInfo{ 11824 inputs: []inputInfo{ 11825 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11826 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11827 }, 11828 outputs: []outputInfo{ 11829 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11830 }, 11831 }, 11832 }, 11833 { 11834 name: "ANDconst", 11835 auxType: auxInt32, 11836 argLen: 1, 11837 asm: arm.AAND, 11838 reg: regInfo{ 11839 inputs: []inputInfo{ 11840 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11841 }, 11842 outputs: []outputInfo{ 11843 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11844 }, 11845 }, 11846 }, 11847 { 11848 name: "OR", 11849 argLen: 2, 11850 commutative: true, 11851 asm: arm.AORR, 11852 reg: regInfo{ 11853 inputs: []inputInfo{ 11854 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11855 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11856 }, 11857 outputs: []outputInfo{ 11858 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11859 }, 11860 }, 11861 }, 11862 { 11863 name: "ORconst", 11864 auxType: auxInt32, 11865 argLen: 1, 11866 asm: arm.AORR, 11867 reg: regInfo{ 11868 inputs: []inputInfo{ 11869 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11870 }, 11871 outputs: []outputInfo{ 11872 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11873 }, 11874 }, 11875 }, 11876 { 11877 name: "XOR", 11878 argLen: 2, 11879 commutative: true, 11880 asm: arm.AEOR, 11881 reg: regInfo{ 11882 inputs: []inputInfo{ 11883 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11884 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11885 }, 11886 outputs: []outputInfo{ 11887 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11888 }, 11889 }, 11890 }, 11891 { 11892 name: "XORconst", 11893 auxType: auxInt32, 11894 argLen: 1, 11895 asm: arm.AEOR, 11896 reg: regInfo{ 11897 inputs: []inputInfo{ 11898 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11899 }, 11900 outputs: []outputInfo{ 11901 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11902 }, 11903 }, 11904 }, 11905 { 11906 name: "BIC", 11907 argLen: 2, 11908 asm: arm.ABIC, 11909 reg: regInfo{ 11910 inputs: []inputInfo{ 11911 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11912 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11913 }, 11914 outputs: []outputInfo{ 11915 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11916 }, 11917 }, 11918 }, 11919 { 11920 name: "BICconst", 11921 auxType: auxInt32, 11922 argLen: 1, 11923 asm: arm.ABIC, 11924 reg: regInfo{ 11925 inputs: []inputInfo{ 11926 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11927 }, 11928 outputs: []outputInfo{ 11929 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11930 }, 11931 }, 11932 }, 11933 { 11934 name: "BFX", 11935 auxType: auxInt32, 11936 argLen: 1, 11937 asm: arm.ABFX, 11938 reg: regInfo{ 11939 inputs: []inputInfo{ 11940 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11941 }, 11942 outputs: []outputInfo{ 11943 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11944 }, 11945 }, 11946 }, 11947 { 11948 name: "BFXU", 11949 auxType: auxInt32, 11950 argLen: 1, 11951 asm: arm.ABFXU, 11952 reg: regInfo{ 11953 inputs: []inputInfo{ 11954 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11955 }, 11956 outputs: []outputInfo{ 11957 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11958 }, 11959 }, 11960 }, 11961 { 11962 name: "MVN", 11963 argLen: 1, 11964 asm: arm.AMVN, 11965 reg: regInfo{ 11966 inputs: []inputInfo{ 11967 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11968 }, 11969 outputs: []outputInfo{ 11970 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11971 }, 11972 }, 11973 }, 11974 { 11975 name: "NEGF", 11976 argLen: 1, 11977 asm: arm.ANEGF, 11978 reg: regInfo{ 11979 inputs: []inputInfo{ 11980 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11981 }, 11982 outputs: []outputInfo{ 11983 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11984 }, 11985 }, 11986 }, 11987 { 11988 name: "NEGD", 11989 argLen: 1, 11990 asm: arm.ANEGD, 11991 reg: regInfo{ 11992 inputs: []inputInfo{ 11993 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11994 }, 11995 outputs: []outputInfo{ 11996 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11997 }, 11998 }, 11999 }, 12000 { 12001 name: "SQRTD", 12002 argLen: 1, 12003 asm: arm.ASQRTD, 12004 reg: regInfo{ 12005 inputs: []inputInfo{ 12006 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 12007 }, 12008 outputs: []outputInfo{ 12009 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 12010 }, 12011 }, 12012 }, 12013 { 12014 name: "CLZ", 12015 argLen: 1, 12016 asm: arm.ACLZ, 12017 reg: regInfo{ 12018 inputs: []inputInfo{ 12019 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12020 }, 12021 outputs: []outputInfo{ 12022 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12023 }, 12024 }, 12025 }, 12026 { 12027 name: "REV", 12028 argLen: 1, 12029 asm: arm.AREV, 12030 reg: regInfo{ 12031 inputs: []inputInfo{ 12032 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12033 }, 12034 outputs: []outputInfo{ 12035 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12036 }, 12037 }, 12038 }, 12039 { 12040 name: "RBIT", 12041 argLen: 1, 12042 asm: arm.ARBIT, 12043 reg: regInfo{ 12044 inputs: []inputInfo{ 12045 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12046 }, 12047 outputs: []outputInfo{ 12048 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12049 }, 12050 }, 12051 }, 12052 { 12053 name: "SLL", 12054 argLen: 2, 12055 asm: arm.ASLL, 12056 reg: regInfo{ 12057 inputs: []inputInfo{ 12058 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12059 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12060 }, 12061 outputs: []outputInfo{ 12062 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12063 }, 12064 }, 12065 }, 12066 { 12067 name: "SLLconst", 12068 auxType: auxInt32, 12069 argLen: 1, 12070 asm: arm.ASLL, 12071 reg: regInfo{ 12072 inputs: []inputInfo{ 12073 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12074 }, 12075 outputs: []outputInfo{ 12076 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12077 }, 12078 }, 12079 }, 12080 { 12081 name: "SRL", 12082 argLen: 2, 12083 asm: arm.ASRL, 12084 reg: regInfo{ 12085 inputs: []inputInfo{ 12086 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12087 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12088 }, 12089 outputs: []outputInfo{ 12090 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12091 }, 12092 }, 12093 }, 12094 { 12095 name: "SRLconst", 12096 auxType: auxInt32, 12097 argLen: 1, 12098 asm: arm.ASRL, 12099 reg: regInfo{ 12100 inputs: []inputInfo{ 12101 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12102 }, 12103 outputs: []outputInfo{ 12104 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12105 }, 12106 }, 12107 }, 12108 { 12109 name: "SRA", 12110 argLen: 2, 12111 asm: arm.ASRA, 12112 reg: regInfo{ 12113 inputs: []inputInfo{ 12114 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12115 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12116 }, 12117 outputs: []outputInfo{ 12118 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12119 }, 12120 }, 12121 }, 12122 { 12123 name: "SRAconst", 12124 auxType: auxInt32, 12125 argLen: 1, 12126 asm: arm.ASRA, 12127 reg: regInfo{ 12128 inputs: []inputInfo{ 12129 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12130 }, 12131 outputs: []outputInfo{ 12132 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12133 }, 12134 }, 12135 }, 12136 { 12137 name: "SRRconst", 12138 auxType: auxInt32, 12139 argLen: 1, 12140 reg: regInfo{ 12141 inputs: []inputInfo{ 12142 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12143 }, 12144 outputs: []outputInfo{ 12145 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12146 }, 12147 }, 12148 }, 12149 { 12150 name: "ADDshiftLL", 12151 auxType: auxInt32, 12152 argLen: 2, 12153 asm: arm.AADD, 12154 reg: regInfo{ 12155 inputs: []inputInfo{ 12156 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12157 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12158 }, 12159 outputs: []outputInfo{ 12160 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12161 }, 12162 }, 12163 }, 12164 { 12165 name: "ADDshiftRL", 12166 auxType: auxInt32, 12167 argLen: 2, 12168 asm: arm.AADD, 12169 reg: regInfo{ 12170 inputs: []inputInfo{ 12171 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12172 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12173 }, 12174 outputs: []outputInfo{ 12175 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12176 }, 12177 }, 12178 }, 12179 { 12180 name: "ADDshiftRA", 12181 auxType: auxInt32, 12182 argLen: 2, 12183 asm: arm.AADD, 12184 reg: regInfo{ 12185 inputs: []inputInfo{ 12186 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12187 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12188 }, 12189 outputs: []outputInfo{ 12190 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12191 }, 12192 }, 12193 }, 12194 { 12195 name: "SUBshiftLL", 12196 auxType: auxInt32, 12197 argLen: 2, 12198 asm: arm.ASUB, 12199 reg: regInfo{ 12200 inputs: []inputInfo{ 12201 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12202 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12203 }, 12204 outputs: []outputInfo{ 12205 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12206 }, 12207 }, 12208 }, 12209 { 12210 name: "SUBshiftRL", 12211 auxType: auxInt32, 12212 argLen: 2, 12213 asm: arm.ASUB, 12214 reg: regInfo{ 12215 inputs: []inputInfo{ 12216 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12217 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12218 }, 12219 outputs: []outputInfo{ 12220 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12221 }, 12222 }, 12223 }, 12224 { 12225 name: "SUBshiftRA", 12226 auxType: auxInt32, 12227 argLen: 2, 12228 asm: arm.ASUB, 12229 reg: regInfo{ 12230 inputs: []inputInfo{ 12231 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12232 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12233 }, 12234 outputs: []outputInfo{ 12235 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12236 }, 12237 }, 12238 }, 12239 { 12240 name: "RSBshiftLL", 12241 auxType: auxInt32, 12242 argLen: 2, 12243 asm: arm.ARSB, 12244 reg: regInfo{ 12245 inputs: []inputInfo{ 12246 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12247 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12248 }, 12249 outputs: []outputInfo{ 12250 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12251 }, 12252 }, 12253 }, 12254 { 12255 name: "RSBshiftRL", 12256 auxType: auxInt32, 12257 argLen: 2, 12258 asm: arm.ARSB, 12259 reg: regInfo{ 12260 inputs: []inputInfo{ 12261 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12262 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12263 }, 12264 outputs: []outputInfo{ 12265 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12266 }, 12267 }, 12268 }, 12269 { 12270 name: "RSBshiftRA", 12271 auxType: auxInt32, 12272 argLen: 2, 12273 asm: arm.ARSB, 12274 reg: regInfo{ 12275 inputs: []inputInfo{ 12276 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12277 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12278 }, 12279 outputs: []outputInfo{ 12280 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12281 }, 12282 }, 12283 }, 12284 { 12285 name: "ANDshiftLL", 12286 auxType: auxInt32, 12287 argLen: 2, 12288 asm: arm.AAND, 12289 reg: regInfo{ 12290 inputs: []inputInfo{ 12291 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12292 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12293 }, 12294 outputs: []outputInfo{ 12295 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12296 }, 12297 }, 12298 }, 12299 { 12300 name: "ANDshiftRL", 12301 auxType: auxInt32, 12302 argLen: 2, 12303 asm: arm.AAND, 12304 reg: regInfo{ 12305 inputs: []inputInfo{ 12306 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12307 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12308 }, 12309 outputs: []outputInfo{ 12310 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12311 }, 12312 }, 12313 }, 12314 { 12315 name: "ANDshiftRA", 12316 auxType: auxInt32, 12317 argLen: 2, 12318 asm: arm.AAND, 12319 reg: regInfo{ 12320 inputs: []inputInfo{ 12321 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12322 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12323 }, 12324 outputs: []outputInfo{ 12325 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12326 }, 12327 }, 12328 }, 12329 { 12330 name: "ORshiftLL", 12331 auxType: auxInt32, 12332 argLen: 2, 12333 asm: arm.AORR, 12334 reg: regInfo{ 12335 inputs: []inputInfo{ 12336 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12337 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12338 }, 12339 outputs: []outputInfo{ 12340 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12341 }, 12342 }, 12343 }, 12344 { 12345 name: "ORshiftRL", 12346 auxType: auxInt32, 12347 argLen: 2, 12348 asm: arm.AORR, 12349 reg: regInfo{ 12350 inputs: []inputInfo{ 12351 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12352 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12353 }, 12354 outputs: []outputInfo{ 12355 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12356 }, 12357 }, 12358 }, 12359 { 12360 name: "ORshiftRA", 12361 auxType: auxInt32, 12362 argLen: 2, 12363 asm: arm.AORR, 12364 reg: regInfo{ 12365 inputs: []inputInfo{ 12366 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12367 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12368 }, 12369 outputs: []outputInfo{ 12370 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12371 }, 12372 }, 12373 }, 12374 { 12375 name: "XORshiftLL", 12376 auxType: auxInt32, 12377 argLen: 2, 12378 asm: arm.AEOR, 12379 reg: regInfo{ 12380 inputs: []inputInfo{ 12381 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12382 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12383 }, 12384 outputs: []outputInfo{ 12385 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12386 }, 12387 }, 12388 }, 12389 { 12390 name: "XORshiftRL", 12391 auxType: auxInt32, 12392 argLen: 2, 12393 asm: arm.AEOR, 12394 reg: regInfo{ 12395 inputs: []inputInfo{ 12396 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12397 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12398 }, 12399 outputs: []outputInfo{ 12400 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12401 }, 12402 }, 12403 }, 12404 { 12405 name: "XORshiftRA", 12406 auxType: auxInt32, 12407 argLen: 2, 12408 asm: arm.AEOR, 12409 reg: regInfo{ 12410 inputs: []inputInfo{ 12411 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12412 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12413 }, 12414 outputs: []outputInfo{ 12415 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12416 }, 12417 }, 12418 }, 12419 { 12420 name: "XORshiftRR", 12421 auxType: auxInt32, 12422 argLen: 2, 12423 asm: arm.AEOR, 12424 reg: regInfo{ 12425 inputs: []inputInfo{ 12426 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12427 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12428 }, 12429 outputs: []outputInfo{ 12430 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12431 }, 12432 }, 12433 }, 12434 { 12435 name: "BICshiftLL", 12436 auxType: auxInt32, 12437 argLen: 2, 12438 asm: arm.ABIC, 12439 reg: regInfo{ 12440 inputs: []inputInfo{ 12441 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12442 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12443 }, 12444 outputs: []outputInfo{ 12445 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12446 }, 12447 }, 12448 }, 12449 { 12450 name: "BICshiftRL", 12451 auxType: auxInt32, 12452 argLen: 2, 12453 asm: arm.ABIC, 12454 reg: regInfo{ 12455 inputs: []inputInfo{ 12456 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12457 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12458 }, 12459 outputs: []outputInfo{ 12460 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12461 }, 12462 }, 12463 }, 12464 { 12465 name: "BICshiftRA", 12466 auxType: auxInt32, 12467 argLen: 2, 12468 asm: arm.ABIC, 12469 reg: regInfo{ 12470 inputs: []inputInfo{ 12471 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12472 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12473 }, 12474 outputs: []outputInfo{ 12475 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12476 }, 12477 }, 12478 }, 12479 { 12480 name: "MVNshiftLL", 12481 auxType: auxInt32, 12482 argLen: 1, 12483 asm: arm.AMVN, 12484 reg: regInfo{ 12485 inputs: []inputInfo{ 12486 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12487 }, 12488 outputs: []outputInfo{ 12489 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12490 }, 12491 }, 12492 }, 12493 { 12494 name: "MVNshiftRL", 12495 auxType: auxInt32, 12496 argLen: 1, 12497 asm: arm.AMVN, 12498 reg: regInfo{ 12499 inputs: []inputInfo{ 12500 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12501 }, 12502 outputs: []outputInfo{ 12503 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12504 }, 12505 }, 12506 }, 12507 { 12508 name: "MVNshiftRA", 12509 auxType: auxInt32, 12510 argLen: 1, 12511 asm: arm.AMVN, 12512 reg: regInfo{ 12513 inputs: []inputInfo{ 12514 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12515 }, 12516 outputs: []outputInfo{ 12517 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12518 }, 12519 }, 12520 }, 12521 { 12522 name: "ADCshiftLL", 12523 auxType: auxInt32, 12524 argLen: 3, 12525 asm: arm.AADC, 12526 reg: regInfo{ 12527 inputs: []inputInfo{ 12528 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12529 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12530 }, 12531 outputs: []outputInfo{ 12532 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12533 }, 12534 }, 12535 }, 12536 { 12537 name: "ADCshiftRL", 12538 auxType: auxInt32, 12539 argLen: 3, 12540 asm: arm.AADC, 12541 reg: regInfo{ 12542 inputs: []inputInfo{ 12543 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12544 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12545 }, 12546 outputs: []outputInfo{ 12547 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12548 }, 12549 }, 12550 }, 12551 { 12552 name: "ADCshiftRA", 12553 auxType: auxInt32, 12554 argLen: 3, 12555 asm: arm.AADC, 12556 reg: regInfo{ 12557 inputs: []inputInfo{ 12558 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12559 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12560 }, 12561 outputs: []outputInfo{ 12562 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12563 }, 12564 }, 12565 }, 12566 { 12567 name: "SBCshiftLL", 12568 auxType: auxInt32, 12569 argLen: 3, 12570 asm: arm.ASBC, 12571 reg: regInfo{ 12572 inputs: []inputInfo{ 12573 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12574 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12575 }, 12576 outputs: []outputInfo{ 12577 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12578 }, 12579 }, 12580 }, 12581 { 12582 name: "SBCshiftRL", 12583 auxType: auxInt32, 12584 argLen: 3, 12585 asm: arm.ASBC, 12586 reg: regInfo{ 12587 inputs: []inputInfo{ 12588 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12589 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12590 }, 12591 outputs: []outputInfo{ 12592 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12593 }, 12594 }, 12595 }, 12596 { 12597 name: "SBCshiftRA", 12598 auxType: auxInt32, 12599 argLen: 3, 12600 asm: arm.ASBC, 12601 reg: regInfo{ 12602 inputs: []inputInfo{ 12603 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12604 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12605 }, 12606 outputs: []outputInfo{ 12607 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12608 }, 12609 }, 12610 }, 12611 { 12612 name: "RSCshiftLL", 12613 auxType: auxInt32, 12614 argLen: 3, 12615 asm: arm.ARSC, 12616 reg: regInfo{ 12617 inputs: []inputInfo{ 12618 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12619 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12620 }, 12621 outputs: []outputInfo{ 12622 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12623 }, 12624 }, 12625 }, 12626 { 12627 name: "RSCshiftRL", 12628 auxType: auxInt32, 12629 argLen: 3, 12630 asm: arm.ARSC, 12631 reg: regInfo{ 12632 inputs: []inputInfo{ 12633 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12634 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12635 }, 12636 outputs: []outputInfo{ 12637 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12638 }, 12639 }, 12640 }, 12641 { 12642 name: "RSCshiftRA", 12643 auxType: auxInt32, 12644 argLen: 3, 12645 asm: arm.ARSC, 12646 reg: regInfo{ 12647 inputs: []inputInfo{ 12648 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12649 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12650 }, 12651 outputs: []outputInfo{ 12652 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12653 }, 12654 }, 12655 }, 12656 { 12657 name: "ADDSshiftLL", 12658 auxType: auxInt32, 12659 argLen: 2, 12660 asm: arm.AADD, 12661 reg: regInfo{ 12662 inputs: []inputInfo{ 12663 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12664 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12665 }, 12666 outputs: []outputInfo{ 12667 {1, 0}, 12668 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12669 }, 12670 }, 12671 }, 12672 { 12673 name: "ADDSshiftRL", 12674 auxType: auxInt32, 12675 argLen: 2, 12676 asm: arm.AADD, 12677 reg: regInfo{ 12678 inputs: []inputInfo{ 12679 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12680 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12681 }, 12682 outputs: []outputInfo{ 12683 {1, 0}, 12684 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12685 }, 12686 }, 12687 }, 12688 { 12689 name: "ADDSshiftRA", 12690 auxType: auxInt32, 12691 argLen: 2, 12692 asm: arm.AADD, 12693 reg: regInfo{ 12694 inputs: []inputInfo{ 12695 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12696 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12697 }, 12698 outputs: []outputInfo{ 12699 {1, 0}, 12700 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12701 }, 12702 }, 12703 }, 12704 { 12705 name: "SUBSshiftLL", 12706 auxType: auxInt32, 12707 argLen: 2, 12708 asm: arm.ASUB, 12709 reg: regInfo{ 12710 inputs: []inputInfo{ 12711 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12712 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12713 }, 12714 outputs: []outputInfo{ 12715 {1, 0}, 12716 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12717 }, 12718 }, 12719 }, 12720 { 12721 name: "SUBSshiftRL", 12722 auxType: auxInt32, 12723 argLen: 2, 12724 asm: arm.ASUB, 12725 reg: regInfo{ 12726 inputs: []inputInfo{ 12727 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12728 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12729 }, 12730 outputs: []outputInfo{ 12731 {1, 0}, 12732 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12733 }, 12734 }, 12735 }, 12736 { 12737 name: "SUBSshiftRA", 12738 auxType: auxInt32, 12739 argLen: 2, 12740 asm: arm.ASUB, 12741 reg: regInfo{ 12742 inputs: []inputInfo{ 12743 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12744 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12745 }, 12746 outputs: []outputInfo{ 12747 {1, 0}, 12748 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12749 }, 12750 }, 12751 }, 12752 { 12753 name: "RSBSshiftLL", 12754 auxType: auxInt32, 12755 argLen: 2, 12756 asm: arm.ARSB, 12757 reg: regInfo{ 12758 inputs: []inputInfo{ 12759 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12760 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12761 }, 12762 outputs: []outputInfo{ 12763 {1, 0}, 12764 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12765 }, 12766 }, 12767 }, 12768 { 12769 name: "RSBSshiftRL", 12770 auxType: auxInt32, 12771 argLen: 2, 12772 asm: arm.ARSB, 12773 reg: regInfo{ 12774 inputs: []inputInfo{ 12775 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12776 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12777 }, 12778 outputs: []outputInfo{ 12779 {1, 0}, 12780 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12781 }, 12782 }, 12783 }, 12784 { 12785 name: "RSBSshiftRA", 12786 auxType: auxInt32, 12787 argLen: 2, 12788 asm: arm.ARSB, 12789 reg: regInfo{ 12790 inputs: []inputInfo{ 12791 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12792 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 12793 }, 12794 outputs: []outputInfo{ 12795 {1, 0}, 12796 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12797 }, 12798 }, 12799 }, 12800 { 12801 name: "ADDshiftLLreg", 12802 argLen: 3, 12803 asm: arm.AADD, 12804 reg: regInfo{ 12805 inputs: []inputInfo{ 12806 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12807 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12808 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12809 }, 12810 outputs: []outputInfo{ 12811 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12812 }, 12813 }, 12814 }, 12815 { 12816 name: "ADDshiftRLreg", 12817 argLen: 3, 12818 asm: arm.AADD, 12819 reg: regInfo{ 12820 inputs: []inputInfo{ 12821 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12822 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12823 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12824 }, 12825 outputs: []outputInfo{ 12826 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12827 }, 12828 }, 12829 }, 12830 { 12831 name: "ADDshiftRAreg", 12832 argLen: 3, 12833 asm: arm.AADD, 12834 reg: regInfo{ 12835 inputs: []inputInfo{ 12836 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12837 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12838 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12839 }, 12840 outputs: []outputInfo{ 12841 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12842 }, 12843 }, 12844 }, 12845 { 12846 name: "SUBshiftLLreg", 12847 argLen: 3, 12848 asm: arm.ASUB, 12849 reg: regInfo{ 12850 inputs: []inputInfo{ 12851 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12852 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12853 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12854 }, 12855 outputs: []outputInfo{ 12856 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12857 }, 12858 }, 12859 }, 12860 { 12861 name: "SUBshiftRLreg", 12862 argLen: 3, 12863 asm: arm.ASUB, 12864 reg: regInfo{ 12865 inputs: []inputInfo{ 12866 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12867 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12868 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12869 }, 12870 outputs: []outputInfo{ 12871 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12872 }, 12873 }, 12874 }, 12875 { 12876 name: "SUBshiftRAreg", 12877 argLen: 3, 12878 asm: arm.ASUB, 12879 reg: regInfo{ 12880 inputs: []inputInfo{ 12881 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12882 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12883 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12884 }, 12885 outputs: []outputInfo{ 12886 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12887 }, 12888 }, 12889 }, 12890 { 12891 name: "RSBshiftLLreg", 12892 argLen: 3, 12893 asm: arm.ARSB, 12894 reg: regInfo{ 12895 inputs: []inputInfo{ 12896 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12897 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12898 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12899 }, 12900 outputs: []outputInfo{ 12901 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12902 }, 12903 }, 12904 }, 12905 { 12906 name: "RSBshiftRLreg", 12907 argLen: 3, 12908 asm: arm.ARSB, 12909 reg: regInfo{ 12910 inputs: []inputInfo{ 12911 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12912 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12913 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12914 }, 12915 outputs: []outputInfo{ 12916 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12917 }, 12918 }, 12919 }, 12920 { 12921 name: "RSBshiftRAreg", 12922 argLen: 3, 12923 asm: arm.ARSB, 12924 reg: regInfo{ 12925 inputs: []inputInfo{ 12926 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12927 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12928 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12929 }, 12930 outputs: []outputInfo{ 12931 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12932 }, 12933 }, 12934 }, 12935 { 12936 name: "ANDshiftLLreg", 12937 argLen: 3, 12938 asm: arm.AAND, 12939 reg: regInfo{ 12940 inputs: []inputInfo{ 12941 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12942 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12943 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12944 }, 12945 outputs: []outputInfo{ 12946 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12947 }, 12948 }, 12949 }, 12950 { 12951 name: "ANDshiftRLreg", 12952 argLen: 3, 12953 asm: arm.AAND, 12954 reg: regInfo{ 12955 inputs: []inputInfo{ 12956 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12957 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12958 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12959 }, 12960 outputs: []outputInfo{ 12961 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12962 }, 12963 }, 12964 }, 12965 { 12966 name: "ANDshiftRAreg", 12967 argLen: 3, 12968 asm: arm.AAND, 12969 reg: regInfo{ 12970 inputs: []inputInfo{ 12971 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12972 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12973 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12974 }, 12975 outputs: []outputInfo{ 12976 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12977 }, 12978 }, 12979 }, 12980 { 12981 name: "ORshiftLLreg", 12982 argLen: 3, 12983 asm: arm.AORR, 12984 reg: regInfo{ 12985 inputs: []inputInfo{ 12986 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12987 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12988 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12989 }, 12990 outputs: []outputInfo{ 12991 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 12992 }, 12993 }, 12994 }, 12995 { 12996 name: "ORshiftRLreg", 12997 argLen: 3, 12998 asm: arm.AORR, 12999 reg: regInfo{ 13000 inputs: []inputInfo{ 13001 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13002 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13003 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13004 }, 13005 outputs: []outputInfo{ 13006 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13007 }, 13008 }, 13009 }, 13010 { 13011 name: "ORshiftRAreg", 13012 argLen: 3, 13013 asm: arm.AORR, 13014 reg: regInfo{ 13015 inputs: []inputInfo{ 13016 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13017 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13018 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13019 }, 13020 outputs: []outputInfo{ 13021 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13022 }, 13023 }, 13024 }, 13025 { 13026 name: "XORshiftLLreg", 13027 argLen: 3, 13028 asm: arm.AEOR, 13029 reg: regInfo{ 13030 inputs: []inputInfo{ 13031 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13032 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13033 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13034 }, 13035 outputs: []outputInfo{ 13036 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13037 }, 13038 }, 13039 }, 13040 { 13041 name: "XORshiftRLreg", 13042 argLen: 3, 13043 asm: arm.AEOR, 13044 reg: regInfo{ 13045 inputs: []inputInfo{ 13046 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13047 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13048 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13049 }, 13050 outputs: []outputInfo{ 13051 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13052 }, 13053 }, 13054 }, 13055 { 13056 name: "XORshiftRAreg", 13057 argLen: 3, 13058 asm: arm.AEOR, 13059 reg: regInfo{ 13060 inputs: []inputInfo{ 13061 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13062 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13063 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13064 }, 13065 outputs: []outputInfo{ 13066 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13067 }, 13068 }, 13069 }, 13070 { 13071 name: "BICshiftLLreg", 13072 argLen: 3, 13073 asm: arm.ABIC, 13074 reg: regInfo{ 13075 inputs: []inputInfo{ 13076 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13077 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13078 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13079 }, 13080 outputs: []outputInfo{ 13081 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13082 }, 13083 }, 13084 }, 13085 { 13086 name: "BICshiftRLreg", 13087 argLen: 3, 13088 asm: arm.ABIC, 13089 reg: regInfo{ 13090 inputs: []inputInfo{ 13091 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13092 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13093 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13094 }, 13095 outputs: []outputInfo{ 13096 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13097 }, 13098 }, 13099 }, 13100 { 13101 name: "BICshiftRAreg", 13102 argLen: 3, 13103 asm: arm.ABIC, 13104 reg: regInfo{ 13105 inputs: []inputInfo{ 13106 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13107 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13108 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13109 }, 13110 outputs: []outputInfo{ 13111 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13112 }, 13113 }, 13114 }, 13115 { 13116 name: "MVNshiftLLreg", 13117 argLen: 2, 13118 asm: arm.AMVN, 13119 reg: regInfo{ 13120 inputs: []inputInfo{ 13121 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13122 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13123 }, 13124 outputs: []outputInfo{ 13125 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13126 }, 13127 }, 13128 }, 13129 { 13130 name: "MVNshiftRLreg", 13131 argLen: 2, 13132 asm: arm.AMVN, 13133 reg: regInfo{ 13134 inputs: []inputInfo{ 13135 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13136 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13137 }, 13138 outputs: []outputInfo{ 13139 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13140 }, 13141 }, 13142 }, 13143 { 13144 name: "MVNshiftRAreg", 13145 argLen: 2, 13146 asm: arm.AMVN, 13147 reg: regInfo{ 13148 inputs: []inputInfo{ 13149 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13150 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13151 }, 13152 outputs: []outputInfo{ 13153 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13154 }, 13155 }, 13156 }, 13157 { 13158 name: "ADCshiftLLreg", 13159 argLen: 4, 13160 asm: arm.AADC, 13161 reg: regInfo{ 13162 inputs: []inputInfo{ 13163 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13164 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13165 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13166 }, 13167 outputs: []outputInfo{ 13168 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13169 }, 13170 }, 13171 }, 13172 { 13173 name: "ADCshiftRLreg", 13174 argLen: 4, 13175 asm: arm.AADC, 13176 reg: regInfo{ 13177 inputs: []inputInfo{ 13178 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13179 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13180 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13181 }, 13182 outputs: []outputInfo{ 13183 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13184 }, 13185 }, 13186 }, 13187 { 13188 name: "ADCshiftRAreg", 13189 argLen: 4, 13190 asm: arm.AADC, 13191 reg: regInfo{ 13192 inputs: []inputInfo{ 13193 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13194 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13195 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13196 }, 13197 outputs: []outputInfo{ 13198 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13199 }, 13200 }, 13201 }, 13202 { 13203 name: "SBCshiftLLreg", 13204 argLen: 4, 13205 asm: arm.ASBC, 13206 reg: regInfo{ 13207 inputs: []inputInfo{ 13208 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13209 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13210 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13211 }, 13212 outputs: []outputInfo{ 13213 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13214 }, 13215 }, 13216 }, 13217 { 13218 name: "SBCshiftRLreg", 13219 argLen: 4, 13220 asm: arm.ASBC, 13221 reg: regInfo{ 13222 inputs: []inputInfo{ 13223 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13224 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13225 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13226 }, 13227 outputs: []outputInfo{ 13228 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13229 }, 13230 }, 13231 }, 13232 { 13233 name: "SBCshiftRAreg", 13234 argLen: 4, 13235 asm: arm.ASBC, 13236 reg: regInfo{ 13237 inputs: []inputInfo{ 13238 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13239 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13240 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13241 }, 13242 outputs: []outputInfo{ 13243 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13244 }, 13245 }, 13246 }, 13247 { 13248 name: "RSCshiftLLreg", 13249 argLen: 4, 13250 asm: arm.ARSC, 13251 reg: regInfo{ 13252 inputs: []inputInfo{ 13253 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13254 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13255 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13256 }, 13257 outputs: []outputInfo{ 13258 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13259 }, 13260 }, 13261 }, 13262 { 13263 name: "RSCshiftRLreg", 13264 argLen: 4, 13265 asm: arm.ARSC, 13266 reg: regInfo{ 13267 inputs: []inputInfo{ 13268 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13269 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13270 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13271 }, 13272 outputs: []outputInfo{ 13273 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13274 }, 13275 }, 13276 }, 13277 { 13278 name: "RSCshiftRAreg", 13279 argLen: 4, 13280 asm: arm.ARSC, 13281 reg: regInfo{ 13282 inputs: []inputInfo{ 13283 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13284 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13285 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13286 }, 13287 outputs: []outputInfo{ 13288 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13289 }, 13290 }, 13291 }, 13292 { 13293 name: "ADDSshiftLLreg", 13294 argLen: 3, 13295 asm: arm.AADD, 13296 reg: regInfo{ 13297 inputs: []inputInfo{ 13298 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13299 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13300 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13301 }, 13302 outputs: []outputInfo{ 13303 {1, 0}, 13304 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13305 }, 13306 }, 13307 }, 13308 { 13309 name: "ADDSshiftRLreg", 13310 argLen: 3, 13311 asm: arm.AADD, 13312 reg: regInfo{ 13313 inputs: []inputInfo{ 13314 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13315 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13316 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13317 }, 13318 outputs: []outputInfo{ 13319 {1, 0}, 13320 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13321 }, 13322 }, 13323 }, 13324 { 13325 name: "ADDSshiftRAreg", 13326 argLen: 3, 13327 asm: arm.AADD, 13328 reg: regInfo{ 13329 inputs: []inputInfo{ 13330 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13331 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13332 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13333 }, 13334 outputs: []outputInfo{ 13335 {1, 0}, 13336 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13337 }, 13338 }, 13339 }, 13340 { 13341 name: "SUBSshiftLLreg", 13342 argLen: 3, 13343 asm: arm.ASUB, 13344 reg: regInfo{ 13345 inputs: []inputInfo{ 13346 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13347 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13348 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13349 }, 13350 outputs: []outputInfo{ 13351 {1, 0}, 13352 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13353 }, 13354 }, 13355 }, 13356 { 13357 name: "SUBSshiftRLreg", 13358 argLen: 3, 13359 asm: arm.ASUB, 13360 reg: regInfo{ 13361 inputs: []inputInfo{ 13362 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13363 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13364 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13365 }, 13366 outputs: []outputInfo{ 13367 {1, 0}, 13368 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13369 }, 13370 }, 13371 }, 13372 { 13373 name: "SUBSshiftRAreg", 13374 argLen: 3, 13375 asm: arm.ASUB, 13376 reg: regInfo{ 13377 inputs: []inputInfo{ 13378 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13379 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13380 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13381 }, 13382 outputs: []outputInfo{ 13383 {1, 0}, 13384 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13385 }, 13386 }, 13387 }, 13388 { 13389 name: "RSBSshiftLLreg", 13390 argLen: 3, 13391 asm: arm.ARSB, 13392 reg: regInfo{ 13393 inputs: []inputInfo{ 13394 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13395 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13396 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13397 }, 13398 outputs: []outputInfo{ 13399 {1, 0}, 13400 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13401 }, 13402 }, 13403 }, 13404 { 13405 name: "RSBSshiftRLreg", 13406 argLen: 3, 13407 asm: arm.ARSB, 13408 reg: regInfo{ 13409 inputs: []inputInfo{ 13410 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13411 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13412 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13413 }, 13414 outputs: []outputInfo{ 13415 {1, 0}, 13416 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13417 }, 13418 }, 13419 }, 13420 { 13421 name: "RSBSshiftRAreg", 13422 argLen: 3, 13423 asm: arm.ARSB, 13424 reg: regInfo{ 13425 inputs: []inputInfo{ 13426 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13427 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13428 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13429 }, 13430 outputs: []outputInfo{ 13431 {1, 0}, 13432 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13433 }, 13434 }, 13435 }, 13436 { 13437 name: "CMP", 13438 argLen: 2, 13439 asm: arm.ACMP, 13440 reg: regInfo{ 13441 inputs: []inputInfo{ 13442 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13443 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13444 }, 13445 }, 13446 }, 13447 { 13448 name: "CMPconst", 13449 auxType: auxInt32, 13450 argLen: 1, 13451 asm: arm.ACMP, 13452 reg: regInfo{ 13453 inputs: []inputInfo{ 13454 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13455 }, 13456 }, 13457 }, 13458 { 13459 name: "CMN", 13460 argLen: 2, 13461 commutative: true, 13462 asm: arm.ACMN, 13463 reg: regInfo{ 13464 inputs: []inputInfo{ 13465 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13466 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13467 }, 13468 }, 13469 }, 13470 { 13471 name: "CMNconst", 13472 auxType: auxInt32, 13473 argLen: 1, 13474 asm: arm.ACMN, 13475 reg: regInfo{ 13476 inputs: []inputInfo{ 13477 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13478 }, 13479 }, 13480 }, 13481 { 13482 name: "TST", 13483 argLen: 2, 13484 commutative: true, 13485 asm: arm.ATST, 13486 reg: regInfo{ 13487 inputs: []inputInfo{ 13488 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13489 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13490 }, 13491 }, 13492 }, 13493 { 13494 name: "TSTconst", 13495 auxType: auxInt32, 13496 argLen: 1, 13497 asm: arm.ATST, 13498 reg: regInfo{ 13499 inputs: []inputInfo{ 13500 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13501 }, 13502 }, 13503 }, 13504 { 13505 name: "TEQ", 13506 argLen: 2, 13507 commutative: true, 13508 asm: arm.ATEQ, 13509 reg: regInfo{ 13510 inputs: []inputInfo{ 13511 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13512 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13513 }, 13514 }, 13515 }, 13516 { 13517 name: "TEQconst", 13518 auxType: auxInt32, 13519 argLen: 1, 13520 asm: arm.ATEQ, 13521 reg: regInfo{ 13522 inputs: []inputInfo{ 13523 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13524 }, 13525 }, 13526 }, 13527 { 13528 name: "CMPF", 13529 argLen: 2, 13530 asm: arm.ACMPF, 13531 reg: regInfo{ 13532 inputs: []inputInfo{ 13533 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13534 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13535 }, 13536 }, 13537 }, 13538 { 13539 name: "CMPD", 13540 argLen: 2, 13541 asm: arm.ACMPD, 13542 reg: regInfo{ 13543 inputs: []inputInfo{ 13544 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13545 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13546 }, 13547 }, 13548 }, 13549 { 13550 name: "CMPshiftLL", 13551 auxType: auxInt32, 13552 argLen: 2, 13553 asm: arm.ACMP, 13554 reg: regInfo{ 13555 inputs: []inputInfo{ 13556 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13557 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13558 }, 13559 }, 13560 }, 13561 { 13562 name: "CMPshiftRL", 13563 auxType: auxInt32, 13564 argLen: 2, 13565 asm: arm.ACMP, 13566 reg: regInfo{ 13567 inputs: []inputInfo{ 13568 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13569 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13570 }, 13571 }, 13572 }, 13573 { 13574 name: "CMPshiftRA", 13575 auxType: auxInt32, 13576 argLen: 2, 13577 asm: arm.ACMP, 13578 reg: regInfo{ 13579 inputs: []inputInfo{ 13580 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13581 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13582 }, 13583 }, 13584 }, 13585 { 13586 name: "CMNshiftLL", 13587 auxType: auxInt32, 13588 argLen: 2, 13589 asm: arm.ACMN, 13590 reg: regInfo{ 13591 inputs: []inputInfo{ 13592 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13593 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13594 }, 13595 }, 13596 }, 13597 { 13598 name: "CMNshiftRL", 13599 auxType: auxInt32, 13600 argLen: 2, 13601 asm: arm.ACMN, 13602 reg: regInfo{ 13603 inputs: []inputInfo{ 13604 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13605 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13606 }, 13607 }, 13608 }, 13609 { 13610 name: "CMNshiftRA", 13611 auxType: auxInt32, 13612 argLen: 2, 13613 asm: arm.ACMN, 13614 reg: regInfo{ 13615 inputs: []inputInfo{ 13616 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13617 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13618 }, 13619 }, 13620 }, 13621 { 13622 name: "TSTshiftLL", 13623 auxType: auxInt32, 13624 argLen: 2, 13625 asm: arm.ATST, 13626 reg: regInfo{ 13627 inputs: []inputInfo{ 13628 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13629 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13630 }, 13631 }, 13632 }, 13633 { 13634 name: "TSTshiftRL", 13635 auxType: auxInt32, 13636 argLen: 2, 13637 asm: arm.ATST, 13638 reg: regInfo{ 13639 inputs: []inputInfo{ 13640 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13641 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13642 }, 13643 }, 13644 }, 13645 { 13646 name: "TSTshiftRA", 13647 auxType: auxInt32, 13648 argLen: 2, 13649 asm: arm.ATST, 13650 reg: regInfo{ 13651 inputs: []inputInfo{ 13652 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13653 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13654 }, 13655 }, 13656 }, 13657 { 13658 name: "TEQshiftLL", 13659 auxType: auxInt32, 13660 argLen: 2, 13661 asm: arm.ATEQ, 13662 reg: regInfo{ 13663 inputs: []inputInfo{ 13664 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13665 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13666 }, 13667 }, 13668 }, 13669 { 13670 name: "TEQshiftRL", 13671 auxType: auxInt32, 13672 argLen: 2, 13673 asm: arm.ATEQ, 13674 reg: regInfo{ 13675 inputs: []inputInfo{ 13676 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13677 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13678 }, 13679 }, 13680 }, 13681 { 13682 name: "TEQshiftRA", 13683 auxType: auxInt32, 13684 argLen: 2, 13685 asm: arm.ATEQ, 13686 reg: regInfo{ 13687 inputs: []inputInfo{ 13688 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13689 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 13690 }, 13691 }, 13692 }, 13693 { 13694 name: "CMPshiftLLreg", 13695 argLen: 3, 13696 asm: arm.ACMP, 13697 reg: regInfo{ 13698 inputs: []inputInfo{ 13699 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13700 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13701 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13702 }, 13703 }, 13704 }, 13705 { 13706 name: "CMPshiftRLreg", 13707 argLen: 3, 13708 asm: arm.ACMP, 13709 reg: regInfo{ 13710 inputs: []inputInfo{ 13711 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13712 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13713 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13714 }, 13715 }, 13716 }, 13717 { 13718 name: "CMPshiftRAreg", 13719 argLen: 3, 13720 asm: arm.ACMP, 13721 reg: regInfo{ 13722 inputs: []inputInfo{ 13723 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13724 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13725 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13726 }, 13727 }, 13728 }, 13729 { 13730 name: "CMNshiftLLreg", 13731 argLen: 3, 13732 asm: arm.ACMN, 13733 reg: regInfo{ 13734 inputs: []inputInfo{ 13735 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13736 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13737 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13738 }, 13739 }, 13740 }, 13741 { 13742 name: "CMNshiftRLreg", 13743 argLen: 3, 13744 asm: arm.ACMN, 13745 reg: regInfo{ 13746 inputs: []inputInfo{ 13747 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13748 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13749 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13750 }, 13751 }, 13752 }, 13753 { 13754 name: "CMNshiftRAreg", 13755 argLen: 3, 13756 asm: arm.ACMN, 13757 reg: regInfo{ 13758 inputs: []inputInfo{ 13759 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13760 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13761 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13762 }, 13763 }, 13764 }, 13765 { 13766 name: "TSTshiftLLreg", 13767 argLen: 3, 13768 asm: arm.ATST, 13769 reg: regInfo{ 13770 inputs: []inputInfo{ 13771 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13772 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13773 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13774 }, 13775 }, 13776 }, 13777 { 13778 name: "TSTshiftRLreg", 13779 argLen: 3, 13780 asm: arm.ATST, 13781 reg: regInfo{ 13782 inputs: []inputInfo{ 13783 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13784 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13785 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13786 }, 13787 }, 13788 }, 13789 { 13790 name: "TSTshiftRAreg", 13791 argLen: 3, 13792 asm: arm.ATST, 13793 reg: regInfo{ 13794 inputs: []inputInfo{ 13795 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13796 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13797 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13798 }, 13799 }, 13800 }, 13801 { 13802 name: "TEQshiftLLreg", 13803 argLen: 3, 13804 asm: arm.ATEQ, 13805 reg: regInfo{ 13806 inputs: []inputInfo{ 13807 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13808 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13809 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13810 }, 13811 }, 13812 }, 13813 { 13814 name: "TEQshiftRLreg", 13815 argLen: 3, 13816 asm: arm.ATEQ, 13817 reg: regInfo{ 13818 inputs: []inputInfo{ 13819 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13820 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13821 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13822 }, 13823 }, 13824 }, 13825 { 13826 name: "TEQshiftRAreg", 13827 argLen: 3, 13828 asm: arm.ATEQ, 13829 reg: regInfo{ 13830 inputs: []inputInfo{ 13831 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13832 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13833 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13834 }, 13835 }, 13836 }, 13837 { 13838 name: "CMPF0", 13839 argLen: 1, 13840 asm: arm.ACMPF, 13841 reg: regInfo{ 13842 inputs: []inputInfo{ 13843 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13844 }, 13845 }, 13846 }, 13847 { 13848 name: "CMPD0", 13849 argLen: 1, 13850 asm: arm.ACMPD, 13851 reg: regInfo{ 13852 inputs: []inputInfo{ 13853 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13854 }, 13855 }, 13856 }, 13857 { 13858 name: "MOVWconst", 13859 auxType: auxInt32, 13860 argLen: 0, 13861 rematerializeable: true, 13862 asm: arm.AMOVW, 13863 reg: regInfo{ 13864 outputs: []outputInfo{ 13865 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13866 }, 13867 }, 13868 }, 13869 { 13870 name: "MOVFconst", 13871 auxType: auxFloat64, 13872 argLen: 0, 13873 rematerializeable: true, 13874 asm: arm.AMOVF, 13875 reg: regInfo{ 13876 outputs: []outputInfo{ 13877 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13878 }, 13879 }, 13880 }, 13881 { 13882 name: "MOVDconst", 13883 auxType: auxFloat64, 13884 argLen: 0, 13885 rematerializeable: true, 13886 asm: arm.AMOVD, 13887 reg: regInfo{ 13888 outputs: []outputInfo{ 13889 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 13890 }, 13891 }, 13892 }, 13893 { 13894 name: "MOVWaddr", 13895 auxType: auxSymOff, 13896 argLen: 1, 13897 rematerializeable: true, 13898 symEffect: SymAddr, 13899 asm: arm.AMOVW, 13900 reg: regInfo{ 13901 inputs: []inputInfo{ 13902 {0, 4294975488}, // SP SB 13903 }, 13904 outputs: []outputInfo{ 13905 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13906 }, 13907 }, 13908 }, 13909 { 13910 name: "MOVBload", 13911 auxType: auxSymOff, 13912 argLen: 2, 13913 faultOnNilArg0: true, 13914 symEffect: SymRead, 13915 asm: arm.AMOVB, 13916 reg: regInfo{ 13917 inputs: []inputInfo{ 13918 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13919 }, 13920 outputs: []outputInfo{ 13921 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13922 }, 13923 }, 13924 }, 13925 { 13926 name: "MOVBUload", 13927 auxType: auxSymOff, 13928 argLen: 2, 13929 faultOnNilArg0: true, 13930 symEffect: SymRead, 13931 asm: arm.AMOVBU, 13932 reg: regInfo{ 13933 inputs: []inputInfo{ 13934 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13935 }, 13936 outputs: []outputInfo{ 13937 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13938 }, 13939 }, 13940 }, 13941 { 13942 name: "MOVHload", 13943 auxType: auxSymOff, 13944 argLen: 2, 13945 faultOnNilArg0: true, 13946 symEffect: SymRead, 13947 asm: arm.AMOVH, 13948 reg: regInfo{ 13949 inputs: []inputInfo{ 13950 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13951 }, 13952 outputs: []outputInfo{ 13953 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13954 }, 13955 }, 13956 }, 13957 { 13958 name: "MOVHUload", 13959 auxType: auxSymOff, 13960 argLen: 2, 13961 faultOnNilArg0: true, 13962 symEffect: SymRead, 13963 asm: arm.AMOVHU, 13964 reg: regInfo{ 13965 inputs: []inputInfo{ 13966 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13967 }, 13968 outputs: []outputInfo{ 13969 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13970 }, 13971 }, 13972 }, 13973 { 13974 name: "MOVWload", 13975 auxType: auxSymOff, 13976 argLen: 2, 13977 faultOnNilArg0: true, 13978 symEffect: SymRead, 13979 asm: arm.AMOVW, 13980 reg: regInfo{ 13981 inputs: []inputInfo{ 13982 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13983 }, 13984 outputs: []outputInfo{ 13985 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 13986 }, 13987 }, 13988 }, 13989 { 13990 name: "MOVFload", 13991 auxType: auxSymOff, 13992 argLen: 2, 13993 faultOnNilArg0: true, 13994 symEffect: SymRead, 13995 asm: arm.AMOVF, 13996 reg: regInfo{ 13997 inputs: []inputInfo{ 13998 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 13999 }, 14000 outputs: []outputInfo{ 14001 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14002 }, 14003 }, 14004 }, 14005 { 14006 name: "MOVDload", 14007 auxType: auxSymOff, 14008 argLen: 2, 14009 faultOnNilArg0: true, 14010 symEffect: SymRead, 14011 asm: arm.AMOVD, 14012 reg: regInfo{ 14013 inputs: []inputInfo{ 14014 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14015 }, 14016 outputs: []outputInfo{ 14017 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14018 }, 14019 }, 14020 }, 14021 { 14022 name: "MOVBstore", 14023 auxType: auxSymOff, 14024 argLen: 3, 14025 faultOnNilArg0: true, 14026 symEffect: SymWrite, 14027 asm: arm.AMOVB, 14028 reg: regInfo{ 14029 inputs: []inputInfo{ 14030 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14031 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14032 }, 14033 }, 14034 }, 14035 { 14036 name: "MOVHstore", 14037 auxType: auxSymOff, 14038 argLen: 3, 14039 faultOnNilArg0: true, 14040 symEffect: SymWrite, 14041 asm: arm.AMOVH, 14042 reg: regInfo{ 14043 inputs: []inputInfo{ 14044 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14045 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14046 }, 14047 }, 14048 }, 14049 { 14050 name: "MOVWstore", 14051 auxType: auxSymOff, 14052 argLen: 3, 14053 faultOnNilArg0: true, 14054 symEffect: SymWrite, 14055 asm: arm.AMOVW, 14056 reg: regInfo{ 14057 inputs: []inputInfo{ 14058 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14059 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14060 }, 14061 }, 14062 }, 14063 { 14064 name: "MOVFstore", 14065 auxType: auxSymOff, 14066 argLen: 3, 14067 faultOnNilArg0: true, 14068 symEffect: SymWrite, 14069 asm: arm.AMOVF, 14070 reg: regInfo{ 14071 inputs: []inputInfo{ 14072 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14073 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14074 }, 14075 }, 14076 }, 14077 { 14078 name: "MOVDstore", 14079 auxType: auxSymOff, 14080 argLen: 3, 14081 faultOnNilArg0: true, 14082 symEffect: SymWrite, 14083 asm: arm.AMOVD, 14084 reg: regInfo{ 14085 inputs: []inputInfo{ 14086 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14087 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14088 }, 14089 }, 14090 }, 14091 { 14092 name: "MOVWloadidx", 14093 argLen: 3, 14094 asm: arm.AMOVW, 14095 reg: regInfo{ 14096 inputs: []inputInfo{ 14097 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14098 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14099 }, 14100 outputs: []outputInfo{ 14101 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14102 }, 14103 }, 14104 }, 14105 { 14106 name: "MOVWloadshiftLL", 14107 auxType: auxInt32, 14108 argLen: 3, 14109 asm: arm.AMOVW, 14110 reg: regInfo{ 14111 inputs: []inputInfo{ 14112 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14113 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14114 }, 14115 outputs: []outputInfo{ 14116 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14117 }, 14118 }, 14119 }, 14120 { 14121 name: "MOVWloadshiftRL", 14122 auxType: auxInt32, 14123 argLen: 3, 14124 asm: arm.AMOVW, 14125 reg: regInfo{ 14126 inputs: []inputInfo{ 14127 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14128 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14129 }, 14130 outputs: []outputInfo{ 14131 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14132 }, 14133 }, 14134 }, 14135 { 14136 name: "MOVWloadshiftRA", 14137 auxType: auxInt32, 14138 argLen: 3, 14139 asm: arm.AMOVW, 14140 reg: regInfo{ 14141 inputs: []inputInfo{ 14142 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14143 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14144 }, 14145 outputs: []outputInfo{ 14146 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14147 }, 14148 }, 14149 }, 14150 { 14151 name: "MOVBUloadidx", 14152 argLen: 3, 14153 asm: arm.AMOVBU, 14154 reg: regInfo{ 14155 inputs: []inputInfo{ 14156 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14157 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14158 }, 14159 outputs: []outputInfo{ 14160 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14161 }, 14162 }, 14163 }, 14164 { 14165 name: "MOVBloadidx", 14166 argLen: 3, 14167 asm: arm.AMOVB, 14168 reg: regInfo{ 14169 inputs: []inputInfo{ 14170 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14171 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14172 }, 14173 outputs: []outputInfo{ 14174 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14175 }, 14176 }, 14177 }, 14178 { 14179 name: "MOVHUloadidx", 14180 argLen: 3, 14181 asm: arm.AMOVHU, 14182 reg: regInfo{ 14183 inputs: []inputInfo{ 14184 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14185 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14186 }, 14187 outputs: []outputInfo{ 14188 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14189 }, 14190 }, 14191 }, 14192 { 14193 name: "MOVHloadidx", 14194 argLen: 3, 14195 asm: arm.AMOVH, 14196 reg: regInfo{ 14197 inputs: []inputInfo{ 14198 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14199 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14200 }, 14201 outputs: []outputInfo{ 14202 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14203 }, 14204 }, 14205 }, 14206 { 14207 name: "MOVWstoreidx", 14208 argLen: 4, 14209 asm: arm.AMOVW, 14210 reg: regInfo{ 14211 inputs: []inputInfo{ 14212 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14213 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14214 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14215 }, 14216 }, 14217 }, 14218 { 14219 name: "MOVWstoreshiftLL", 14220 auxType: auxInt32, 14221 argLen: 4, 14222 asm: arm.AMOVW, 14223 reg: regInfo{ 14224 inputs: []inputInfo{ 14225 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14226 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14227 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14228 }, 14229 }, 14230 }, 14231 { 14232 name: "MOVWstoreshiftRL", 14233 auxType: auxInt32, 14234 argLen: 4, 14235 asm: arm.AMOVW, 14236 reg: regInfo{ 14237 inputs: []inputInfo{ 14238 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14239 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14240 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14241 }, 14242 }, 14243 }, 14244 { 14245 name: "MOVWstoreshiftRA", 14246 auxType: auxInt32, 14247 argLen: 4, 14248 asm: arm.AMOVW, 14249 reg: regInfo{ 14250 inputs: []inputInfo{ 14251 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14252 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14253 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14254 }, 14255 }, 14256 }, 14257 { 14258 name: "MOVBstoreidx", 14259 argLen: 4, 14260 asm: arm.AMOVB, 14261 reg: regInfo{ 14262 inputs: []inputInfo{ 14263 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14264 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14265 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14266 }, 14267 }, 14268 }, 14269 { 14270 name: "MOVHstoreidx", 14271 argLen: 4, 14272 asm: arm.AMOVH, 14273 reg: regInfo{ 14274 inputs: []inputInfo{ 14275 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14276 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14277 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 14278 }, 14279 }, 14280 }, 14281 { 14282 name: "MOVBreg", 14283 argLen: 1, 14284 asm: arm.AMOVBS, 14285 reg: regInfo{ 14286 inputs: []inputInfo{ 14287 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14288 }, 14289 outputs: []outputInfo{ 14290 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14291 }, 14292 }, 14293 }, 14294 { 14295 name: "MOVBUreg", 14296 argLen: 1, 14297 asm: arm.AMOVBU, 14298 reg: regInfo{ 14299 inputs: []inputInfo{ 14300 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14301 }, 14302 outputs: []outputInfo{ 14303 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14304 }, 14305 }, 14306 }, 14307 { 14308 name: "MOVHreg", 14309 argLen: 1, 14310 asm: arm.AMOVHS, 14311 reg: regInfo{ 14312 inputs: []inputInfo{ 14313 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14314 }, 14315 outputs: []outputInfo{ 14316 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14317 }, 14318 }, 14319 }, 14320 { 14321 name: "MOVHUreg", 14322 argLen: 1, 14323 asm: arm.AMOVHU, 14324 reg: regInfo{ 14325 inputs: []inputInfo{ 14326 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14327 }, 14328 outputs: []outputInfo{ 14329 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14330 }, 14331 }, 14332 }, 14333 { 14334 name: "MOVWreg", 14335 argLen: 1, 14336 asm: arm.AMOVW, 14337 reg: regInfo{ 14338 inputs: []inputInfo{ 14339 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14340 }, 14341 outputs: []outputInfo{ 14342 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14343 }, 14344 }, 14345 }, 14346 { 14347 name: "MOVWnop", 14348 argLen: 1, 14349 resultInArg0: true, 14350 reg: regInfo{ 14351 inputs: []inputInfo{ 14352 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14353 }, 14354 outputs: []outputInfo{ 14355 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14356 }, 14357 }, 14358 }, 14359 { 14360 name: "MOVWF", 14361 argLen: 1, 14362 asm: arm.AMOVWF, 14363 reg: regInfo{ 14364 inputs: []inputInfo{ 14365 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14366 }, 14367 clobbers: 2147483648, // F15 14368 outputs: []outputInfo{ 14369 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14370 }, 14371 }, 14372 }, 14373 { 14374 name: "MOVWD", 14375 argLen: 1, 14376 asm: arm.AMOVWD, 14377 reg: regInfo{ 14378 inputs: []inputInfo{ 14379 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14380 }, 14381 clobbers: 2147483648, // F15 14382 outputs: []outputInfo{ 14383 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14384 }, 14385 }, 14386 }, 14387 { 14388 name: "MOVWUF", 14389 argLen: 1, 14390 asm: arm.AMOVWF, 14391 reg: regInfo{ 14392 inputs: []inputInfo{ 14393 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14394 }, 14395 clobbers: 2147483648, // F15 14396 outputs: []outputInfo{ 14397 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14398 }, 14399 }, 14400 }, 14401 { 14402 name: "MOVWUD", 14403 argLen: 1, 14404 asm: arm.AMOVWD, 14405 reg: regInfo{ 14406 inputs: []inputInfo{ 14407 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14408 }, 14409 clobbers: 2147483648, // F15 14410 outputs: []outputInfo{ 14411 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14412 }, 14413 }, 14414 }, 14415 { 14416 name: "MOVFW", 14417 argLen: 1, 14418 asm: arm.AMOVFW, 14419 reg: regInfo{ 14420 inputs: []inputInfo{ 14421 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14422 }, 14423 clobbers: 2147483648, // F15 14424 outputs: []outputInfo{ 14425 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14426 }, 14427 }, 14428 }, 14429 { 14430 name: "MOVDW", 14431 argLen: 1, 14432 asm: arm.AMOVDW, 14433 reg: regInfo{ 14434 inputs: []inputInfo{ 14435 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14436 }, 14437 clobbers: 2147483648, // F15 14438 outputs: []outputInfo{ 14439 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14440 }, 14441 }, 14442 }, 14443 { 14444 name: "MOVFWU", 14445 argLen: 1, 14446 asm: arm.AMOVFW, 14447 reg: regInfo{ 14448 inputs: []inputInfo{ 14449 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14450 }, 14451 clobbers: 2147483648, // F15 14452 outputs: []outputInfo{ 14453 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14454 }, 14455 }, 14456 }, 14457 { 14458 name: "MOVDWU", 14459 argLen: 1, 14460 asm: arm.AMOVDW, 14461 reg: regInfo{ 14462 inputs: []inputInfo{ 14463 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14464 }, 14465 clobbers: 2147483648, // F15 14466 outputs: []outputInfo{ 14467 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14468 }, 14469 }, 14470 }, 14471 { 14472 name: "MOVFD", 14473 argLen: 1, 14474 asm: arm.AMOVFD, 14475 reg: regInfo{ 14476 inputs: []inputInfo{ 14477 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14478 }, 14479 outputs: []outputInfo{ 14480 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14481 }, 14482 }, 14483 }, 14484 { 14485 name: "MOVDF", 14486 argLen: 1, 14487 asm: arm.AMOVDF, 14488 reg: regInfo{ 14489 inputs: []inputInfo{ 14490 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14491 }, 14492 outputs: []outputInfo{ 14493 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14494 }, 14495 }, 14496 }, 14497 { 14498 name: "CMOVWHSconst", 14499 auxType: auxInt32, 14500 argLen: 2, 14501 resultInArg0: true, 14502 asm: arm.AMOVW, 14503 reg: regInfo{ 14504 inputs: []inputInfo{ 14505 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14506 }, 14507 outputs: []outputInfo{ 14508 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14509 }, 14510 }, 14511 }, 14512 { 14513 name: "CMOVWLSconst", 14514 auxType: auxInt32, 14515 argLen: 2, 14516 resultInArg0: true, 14517 asm: arm.AMOVW, 14518 reg: regInfo{ 14519 inputs: []inputInfo{ 14520 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14521 }, 14522 outputs: []outputInfo{ 14523 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14524 }, 14525 }, 14526 }, 14527 { 14528 name: "SRAcond", 14529 argLen: 3, 14530 asm: arm.ASRA, 14531 reg: regInfo{ 14532 inputs: []inputInfo{ 14533 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14534 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14535 }, 14536 outputs: []outputInfo{ 14537 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14538 }, 14539 }, 14540 }, 14541 { 14542 name: "CALLstatic", 14543 auxType: auxSymOff, 14544 argLen: 1, 14545 clobberFlags: true, 14546 call: true, 14547 symEffect: SymNone, 14548 reg: regInfo{ 14549 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14550 }, 14551 }, 14552 { 14553 name: "CALLclosure", 14554 auxType: auxInt64, 14555 argLen: 3, 14556 clobberFlags: true, 14557 call: true, 14558 reg: regInfo{ 14559 inputs: []inputInfo{ 14560 {1, 128}, // R7 14561 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 14562 }, 14563 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14564 }, 14565 }, 14566 { 14567 name: "CALLinter", 14568 auxType: auxInt64, 14569 argLen: 2, 14570 clobberFlags: true, 14571 call: true, 14572 reg: regInfo{ 14573 inputs: []inputInfo{ 14574 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14575 }, 14576 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14577 }, 14578 }, 14579 { 14580 name: "LoweredNilCheck", 14581 argLen: 2, 14582 nilCheck: true, 14583 faultOnNilArg0: true, 14584 reg: regInfo{ 14585 inputs: []inputInfo{ 14586 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14587 }, 14588 }, 14589 }, 14590 { 14591 name: "Equal", 14592 argLen: 1, 14593 reg: regInfo{ 14594 outputs: []outputInfo{ 14595 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14596 }, 14597 }, 14598 }, 14599 { 14600 name: "NotEqual", 14601 argLen: 1, 14602 reg: regInfo{ 14603 outputs: []outputInfo{ 14604 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14605 }, 14606 }, 14607 }, 14608 { 14609 name: "LessThan", 14610 argLen: 1, 14611 reg: regInfo{ 14612 outputs: []outputInfo{ 14613 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14614 }, 14615 }, 14616 }, 14617 { 14618 name: "LessEqual", 14619 argLen: 1, 14620 reg: regInfo{ 14621 outputs: []outputInfo{ 14622 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14623 }, 14624 }, 14625 }, 14626 { 14627 name: "GreaterThan", 14628 argLen: 1, 14629 reg: regInfo{ 14630 outputs: []outputInfo{ 14631 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14632 }, 14633 }, 14634 }, 14635 { 14636 name: "GreaterEqual", 14637 argLen: 1, 14638 reg: regInfo{ 14639 outputs: []outputInfo{ 14640 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14641 }, 14642 }, 14643 }, 14644 { 14645 name: "LessThanU", 14646 argLen: 1, 14647 reg: regInfo{ 14648 outputs: []outputInfo{ 14649 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14650 }, 14651 }, 14652 }, 14653 { 14654 name: "LessEqualU", 14655 argLen: 1, 14656 reg: regInfo{ 14657 outputs: []outputInfo{ 14658 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14659 }, 14660 }, 14661 }, 14662 { 14663 name: "GreaterThanU", 14664 argLen: 1, 14665 reg: regInfo{ 14666 outputs: []outputInfo{ 14667 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14668 }, 14669 }, 14670 }, 14671 { 14672 name: "GreaterEqualU", 14673 argLen: 1, 14674 reg: regInfo{ 14675 outputs: []outputInfo{ 14676 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14677 }, 14678 }, 14679 }, 14680 { 14681 name: "DUFFZERO", 14682 auxType: auxInt64, 14683 argLen: 3, 14684 faultOnNilArg0: true, 14685 reg: regInfo{ 14686 inputs: []inputInfo{ 14687 {0, 2}, // R1 14688 {1, 1}, // R0 14689 }, 14690 clobbers: 16386, // R1 R14 14691 }, 14692 }, 14693 { 14694 name: "DUFFCOPY", 14695 auxType: auxInt64, 14696 argLen: 3, 14697 faultOnNilArg0: true, 14698 faultOnNilArg1: true, 14699 reg: regInfo{ 14700 inputs: []inputInfo{ 14701 {0, 4}, // R2 14702 {1, 2}, // R1 14703 }, 14704 clobbers: 16391, // R0 R1 R2 R14 14705 }, 14706 }, 14707 { 14708 name: "LoweredZero", 14709 auxType: auxInt64, 14710 argLen: 4, 14711 clobberFlags: true, 14712 faultOnNilArg0: true, 14713 reg: regInfo{ 14714 inputs: []inputInfo{ 14715 {0, 2}, // R1 14716 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14717 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14718 }, 14719 clobbers: 2, // R1 14720 }, 14721 }, 14722 { 14723 name: "LoweredMove", 14724 auxType: auxInt64, 14725 argLen: 4, 14726 clobberFlags: true, 14727 faultOnNilArg0: true, 14728 faultOnNilArg1: true, 14729 reg: regInfo{ 14730 inputs: []inputInfo{ 14731 {0, 4}, // R2 14732 {1, 2}, // R1 14733 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14734 }, 14735 clobbers: 6, // R1 R2 14736 }, 14737 }, 14738 { 14739 name: "LoweredGetClosurePtr", 14740 argLen: 0, 14741 zeroWidth: true, 14742 reg: regInfo{ 14743 outputs: []outputInfo{ 14744 {0, 128}, // R7 14745 }, 14746 }, 14747 }, 14748 { 14749 name: "LoweredGetCallerSP", 14750 argLen: 0, 14751 rematerializeable: true, 14752 reg: regInfo{ 14753 outputs: []outputInfo{ 14754 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14755 }, 14756 }, 14757 }, 14758 { 14759 name: "LoweredGetCallerPC", 14760 argLen: 0, 14761 rematerializeable: true, 14762 reg: regInfo{ 14763 outputs: []outputInfo{ 14764 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14765 }, 14766 }, 14767 }, 14768 { 14769 name: "FlagEQ", 14770 argLen: 0, 14771 reg: regInfo{}, 14772 }, 14773 { 14774 name: "FlagLT_ULT", 14775 argLen: 0, 14776 reg: regInfo{}, 14777 }, 14778 { 14779 name: "FlagLT_UGT", 14780 argLen: 0, 14781 reg: regInfo{}, 14782 }, 14783 { 14784 name: "FlagGT_UGT", 14785 argLen: 0, 14786 reg: regInfo{}, 14787 }, 14788 { 14789 name: "FlagGT_ULT", 14790 argLen: 0, 14791 reg: regInfo{}, 14792 }, 14793 { 14794 name: "InvertFlags", 14795 argLen: 1, 14796 reg: regInfo{}, 14797 }, 14798 { 14799 name: "LoweredWB", 14800 auxType: auxSym, 14801 argLen: 3, 14802 clobberFlags: true, 14803 symEffect: SymNone, 14804 reg: regInfo{ 14805 inputs: []inputInfo{ 14806 {0, 4}, // R2 14807 {1, 8}, // R3 14808 }, 14809 clobbers: 4294918144, // R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 14810 }, 14811 }, 14812 14813 { 14814 name: "ADD", 14815 argLen: 2, 14816 commutative: true, 14817 asm: arm64.AADD, 14818 reg: regInfo{ 14819 inputs: []inputInfo{ 14820 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14821 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14822 }, 14823 outputs: []outputInfo{ 14824 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14825 }, 14826 }, 14827 }, 14828 { 14829 name: "ADDconst", 14830 auxType: auxInt64, 14831 argLen: 1, 14832 asm: arm64.AADD, 14833 reg: regInfo{ 14834 inputs: []inputInfo{ 14835 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 14836 }, 14837 outputs: []outputInfo{ 14838 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14839 }, 14840 }, 14841 }, 14842 { 14843 name: "SUB", 14844 argLen: 2, 14845 asm: arm64.ASUB, 14846 reg: regInfo{ 14847 inputs: []inputInfo{ 14848 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14849 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14850 }, 14851 outputs: []outputInfo{ 14852 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14853 }, 14854 }, 14855 }, 14856 { 14857 name: "SUBconst", 14858 auxType: auxInt64, 14859 argLen: 1, 14860 asm: arm64.ASUB, 14861 reg: regInfo{ 14862 inputs: []inputInfo{ 14863 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14864 }, 14865 outputs: []outputInfo{ 14866 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14867 }, 14868 }, 14869 }, 14870 { 14871 name: "MUL", 14872 argLen: 2, 14873 commutative: true, 14874 asm: arm64.AMUL, 14875 reg: regInfo{ 14876 inputs: []inputInfo{ 14877 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14878 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14879 }, 14880 outputs: []outputInfo{ 14881 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14882 }, 14883 }, 14884 }, 14885 { 14886 name: "MULW", 14887 argLen: 2, 14888 commutative: true, 14889 asm: arm64.AMULW, 14890 reg: regInfo{ 14891 inputs: []inputInfo{ 14892 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14893 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14894 }, 14895 outputs: []outputInfo{ 14896 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14897 }, 14898 }, 14899 }, 14900 { 14901 name: "MNEG", 14902 argLen: 2, 14903 commutative: true, 14904 asm: arm64.AMNEG, 14905 reg: regInfo{ 14906 inputs: []inputInfo{ 14907 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14908 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14909 }, 14910 outputs: []outputInfo{ 14911 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14912 }, 14913 }, 14914 }, 14915 { 14916 name: "MNEGW", 14917 argLen: 2, 14918 commutative: true, 14919 asm: arm64.AMNEGW, 14920 reg: regInfo{ 14921 inputs: []inputInfo{ 14922 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14923 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14924 }, 14925 outputs: []outputInfo{ 14926 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14927 }, 14928 }, 14929 }, 14930 { 14931 name: "MULH", 14932 argLen: 2, 14933 commutative: true, 14934 asm: arm64.ASMULH, 14935 reg: regInfo{ 14936 inputs: []inputInfo{ 14937 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14938 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14939 }, 14940 outputs: []outputInfo{ 14941 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14942 }, 14943 }, 14944 }, 14945 { 14946 name: "UMULH", 14947 argLen: 2, 14948 commutative: true, 14949 asm: arm64.AUMULH, 14950 reg: regInfo{ 14951 inputs: []inputInfo{ 14952 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14953 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14954 }, 14955 outputs: []outputInfo{ 14956 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14957 }, 14958 }, 14959 }, 14960 { 14961 name: "MULL", 14962 argLen: 2, 14963 commutative: true, 14964 asm: arm64.ASMULL, 14965 reg: regInfo{ 14966 inputs: []inputInfo{ 14967 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14968 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14969 }, 14970 outputs: []outputInfo{ 14971 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14972 }, 14973 }, 14974 }, 14975 { 14976 name: "UMULL", 14977 argLen: 2, 14978 commutative: true, 14979 asm: arm64.AUMULL, 14980 reg: regInfo{ 14981 inputs: []inputInfo{ 14982 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14983 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14984 }, 14985 outputs: []outputInfo{ 14986 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14987 }, 14988 }, 14989 }, 14990 { 14991 name: "DIV", 14992 argLen: 2, 14993 asm: arm64.ASDIV, 14994 reg: regInfo{ 14995 inputs: []inputInfo{ 14996 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14997 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14998 }, 14999 outputs: []outputInfo{ 15000 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15001 }, 15002 }, 15003 }, 15004 { 15005 name: "UDIV", 15006 argLen: 2, 15007 asm: arm64.AUDIV, 15008 reg: regInfo{ 15009 inputs: []inputInfo{ 15010 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15011 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15012 }, 15013 outputs: []outputInfo{ 15014 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15015 }, 15016 }, 15017 }, 15018 { 15019 name: "DIVW", 15020 argLen: 2, 15021 asm: arm64.ASDIVW, 15022 reg: regInfo{ 15023 inputs: []inputInfo{ 15024 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15025 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15026 }, 15027 outputs: []outputInfo{ 15028 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15029 }, 15030 }, 15031 }, 15032 { 15033 name: "UDIVW", 15034 argLen: 2, 15035 asm: arm64.AUDIVW, 15036 reg: regInfo{ 15037 inputs: []inputInfo{ 15038 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15039 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15040 }, 15041 outputs: []outputInfo{ 15042 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15043 }, 15044 }, 15045 }, 15046 { 15047 name: "MOD", 15048 argLen: 2, 15049 asm: arm64.AREM, 15050 reg: regInfo{ 15051 inputs: []inputInfo{ 15052 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15053 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15054 }, 15055 outputs: []outputInfo{ 15056 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15057 }, 15058 }, 15059 }, 15060 { 15061 name: "UMOD", 15062 argLen: 2, 15063 asm: arm64.AUREM, 15064 reg: regInfo{ 15065 inputs: []inputInfo{ 15066 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15067 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15068 }, 15069 outputs: []outputInfo{ 15070 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15071 }, 15072 }, 15073 }, 15074 { 15075 name: "MODW", 15076 argLen: 2, 15077 asm: arm64.AREMW, 15078 reg: regInfo{ 15079 inputs: []inputInfo{ 15080 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15081 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15082 }, 15083 outputs: []outputInfo{ 15084 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15085 }, 15086 }, 15087 }, 15088 { 15089 name: "UMODW", 15090 argLen: 2, 15091 asm: arm64.AUREMW, 15092 reg: regInfo{ 15093 inputs: []inputInfo{ 15094 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15095 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15096 }, 15097 outputs: []outputInfo{ 15098 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15099 }, 15100 }, 15101 }, 15102 { 15103 name: "FADDS", 15104 argLen: 2, 15105 commutative: true, 15106 asm: arm64.AFADDS, 15107 reg: regInfo{ 15108 inputs: []inputInfo{ 15109 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15110 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15111 }, 15112 outputs: []outputInfo{ 15113 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15114 }, 15115 }, 15116 }, 15117 { 15118 name: "FADDD", 15119 argLen: 2, 15120 commutative: true, 15121 asm: arm64.AFADDD, 15122 reg: regInfo{ 15123 inputs: []inputInfo{ 15124 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15125 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15126 }, 15127 outputs: []outputInfo{ 15128 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15129 }, 15130 }, 15131 }, 15132 { 15133 name: "FSUBS", 15134 argLen: 2, 15135 asm: arm64.AFSUBS, 15136 reg: regInfo{ 15137 inputs: []inputInfo{ 15138 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15139 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15140 }, 15141 outputs: []outputInfo{ 15142 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15143 }, 15144 }, 15145 }, 15146 { 15147 name: "FSUBD", 15148 argLen: 2, 15149 asm: arm64.AFSUBD, 15150 reg: regInfo{ 15151 inputs: []inputInfo{ 15152 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15153 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15154 }, 15155 outputs: []outputInfo{ 15156 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15157 }, 15158 }, 15159 }, 15160 { 15161 name: "FMULS", 15162 argLen: 2, 15163 commutative: true, 15164 asm: arm64.AFMULS, 15165 reg: regInfo{ 15166 inputs: []inputInfo{ 15167 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15168 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15169 }, 15170 outputs: []outputInfo{ 15171 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15172 }, 15173 }, 15174 }, 15175 { 15176 name: "FMULD", 15177 argLen: 2, 15178 commutative: true, 15179 asm: arm64.AFMULD, 15180 reg: regInfo{ 15181 inputs: []inputInfo{ 15182 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15183 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15184 }, 15185 outputs: []outputInfo{ 15186 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15187 }, 15188 }, 15189 }, 15190 { 15191 name: "FNMULS", 15192 argLen: 2, 15193 commutative: true, 15194 asm: arm64.AFNMULS, 15195 reg: regInfo{ 15196 inputs: []inputInfo{ 15197 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15198 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15199 }, 15200 outputs: []outputInfo{ 15201 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15202 }, 15203 }, 15204 }, 15205 { 15206 name: "FNMULD", 15207 argLen: 2, 15208 commutative: true, 15209 asm: arm64.AFNMULD, 15210 reg: regInfo{ 15211 inputs: []inputInfo{ 15212 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15213 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15214 }, 15215 outputs: []outputInfo{ 15216 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15217 }, 15218 }, 15219 }, 15220 { 15221 name: "FDIVS", 15222 argLen: 2, 15223 asm: arm64.AFDIVS, 15224 reg: regInfo{ 15225 inputs: []inputInfo{ 15226 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15227 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15228 }, 15229 outputs: []outputInfo{ 15230 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15231 }, 15232 }, 15233 }, 15234 { 15235 name: "FDIVD", 15236 argLen: 2, 15237 asm: arm64.AFDIVD, 15238 reg: regInfo{ 15239 inputs: []inputInfo{ 15240 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15241 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15242 }, 15243 outputs: []outputInfo{ 15244 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15245 }, 15246 }, 15247 }, 15248 { 15249 name: "AND", 15250 argLen: 2, 15251 commutative: true, 15252 asm: arm64.AAND, 15253 reg: regInfo{ 15254 inputs: []inputInfo{ 15255 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15256 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15257 }, 15258 outputs: []outputInfo{ 15259 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15260 }, 15261 }, 15262 }, 15263 { 15264 name: "ANDconst", 15265 auxType: auxInt64, 15266 argLen: 1, 15267 asm: arm64.AAND, 15268 reg: regInfo{ 15269 inputs: []inputInfo{ 15270 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15271 }, 15272 outputs: []outputInfo{ 15273 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15274 }, 15275 }, 15276 }, 15277 { 15278 name: "OR", 15279 argLen: 2, 15280 commutative: true, 15281 asm: arm64.AORR, 15282 reg: regInfo{ 15283 inputs: []inputInfo{ 15284 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15285 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15286 }, 15287 outputs: []outputInfo{ 15288 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15289 }, 15290 }, 15291 }, 15292 { 15293 name: "ORconst", 15294 auxType: auxInt64, 15295 argLen: 1, 15296 asm: arm64.AORR, 15297 reg: regInfo{ 15298 inputs: []inputInfo{ 15299 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15300 }, 15301 outputs: []outputInfo{ 15302 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15303 }, 15304 }, 15305 }, 15306 { 15307 name: "XOR", 15308 argLen: 2, 15309 commutative: true, 15310 asm: arm64.AEOR, 15311 reg: regInfo{ 15312 inputs: []inputInfo{ 15313 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15314 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15315 }, 15316 outputs: []outputInfo{ 15317 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15318 }, 15319 }, 15320 }, 15321 { 15322 name: "XORconst", 15323 auxType: auxInt64, 15324 argLen: 1, 15325 asm: arm64.AEOR, 15326 reg: regInfo{ 15327 inputs: []inputInfo{ 15328 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15329 }, 15330 outputs: []outputInfo{ 15331 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15332 }, 15333 }, 15334 }, 15335 { 15336 name: "BIC", 15337 argLen: 2, 15338 asm: arm64.ABIC, 15339 reg: regInfo{ 15340 inputs: []inputInfo{ 15341 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15342 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15343 }, 15344 outputs: []outputInfo{ 15345 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15346 }, 15347 }, 15348 }, 15349 { 15350 name: "EON", 15351 argLen: 2, 15352 asm: arm64.AEON, 15353 reg: regInfo{ 15354 inputs: []inputInfo{ 15355 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15356 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15357 }, 15358 outputs: []outputInfo{ 15359 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15360 }, 15361 }, 15362 }, 15363 { 15364 name: "ORN", 15365 argLen: 2, 15366 asm: arm64.AORN, 15367 reg: regInfo{ 15368 inputs: []inputInfo{ 15369 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15370 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15371 }, 15372 outputs: []outputInfo{ 15373 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15374 }, 15375 }, 15376 }, 15377 { 15378 name: "LoweredMuluhilo", 15379 argLen: 2, 15380 resultNotInArgs: true, 15381 reg: regInfo{ 15382 inputs: []inputInfo{ 15383 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15384 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15385 }, 15386 outputs: []outputInfo{ 15387 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15388 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15389 }, 15390 }, 15391 }, 15392 { 15393 name: "MVN", 15394 argLen: 1, 15395 asm: arm64.AMVN, 15396 reg: regInfo{ 15397 inputs: []inputInfo{ 15398 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15399 }, 15400 outputs: []outputInfo{ 15401 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15402 }, 15403 }, 15404 }, 15405 { 15406 name: "NEG", 15407 argLen: 1, 15408 asm: arm64.ANEG, 15409 reg: regInfo{ 15410 inputs: []inputInfo{ 15411 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15412 }, 15413 outputs: []outputInfo{ 15414 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15415 }, 15416 }, 15417 }, 15418 { 15419 name: "FABSD", 15420 argLen: 1, 15421 asm: arm64.AFABSD, 15422 reg: regInfo{ 15423 inputs: []inputInfo{ 15424 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15425 }, 15426 outputs: []outputInfo{ 15427 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15428 }, 15429 }, 15430 }, 15431 { 15432 name: "FNEGS", 15433 argLen: 1, 15434 asm: arm64.AFNEGS, 15435 reg: regInfo{ 15436 inputs: []inputInfo{ 15437 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15438 }, 15439 outputs: []outputInfo{ 15440 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15441 }, 15442 }, 15443 }, 15444 { 15445 name: "FNEGD", 15446 argLen: 1, 15447 asm: arm64.AFNEGD, 15448 reg: regInfo{ 15449 inputs: []inputInfo{ 15450 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15451 }, 15452 outputs: []outputInfo{ 15453 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15454 }, 15455 }, 15456 }, 15457 { 15458 name: "FSQRTD", 15459 argLen: 1, 15460 asm: arm64.AFSQRTD, 15461 reg: regInfo{ 15462 inputs: []inputInfo{ 15463 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15464 }, 15465 outputs: []outputInfo{ 15466 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15467 }, 15468 }, 15469 }, 15470 { 15471 name: "REV", 15472 argLen: 1, 15473 asm: arm64.AREV, 15474 reg: regInfo{ 15475 inputs: []inputInfo{ 15476 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15477 }, 15478 outputs: []outputInfo{ 15479 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15480 }, 15481 }, 15482 }, 15483 { 15484 name: "REVW", 15485 argLen: 1, 15486 asm: arm64.AREVW, 15487 reg: regInfo{ 15488 inputs: []inputInfo{ 15489 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15490 }, 15491 outputs: []outputInfo{ 15492 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15493 }, 15494 }, 15495 }, 15496 { 15497 name: "REV16W", 15498 argLen: 1, 15499 asm: arm64.AREV16W, 15500 reg: regInfo{ 15501 inputs: []inputInfo{ 15502 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15503 }, 15504 outputs: []outputInfo{ 15505 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15506 }, 15507 }, 15508 }, 15509 { 15510 name: "RBIT", 15511 argLen: 1, 15512 asm: arm64.ARBIT, 15513 reg: regInfo{ 15514 inputs: []inputInfo{ 15515 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15516 }, 15517 outputs: []outputInfo{ 15518 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15519 }, 15520 }, 15521 }, 15522 { 15523 name: "RBITW", 15524 argLen: 1, 15525 asm: arm64.ARBITW, 15526 reg: regInfo{ 15527 inputs: []inputInfo{ 15528 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15529 }, 15530 outputs: []outputInfo{ 15531 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15532 }, 15533 }, 15534 }, 15535 { 15536 name: "CLZ", 15537 argLen: 1, 15538 asm: arm64.ACLZ, 15539 reg: regInfo{ 15540 inputs: []inputInfo{ 15541 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15542 }, 15543 outputs: []outputInfo{ 15544 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15545 }, 15546 }, 15547 }, 15548 { 15549 name: "CLZW", 15550 argLen: 1, 15551 asm: arm64.ACLZW, 15552 reg: regInfo{ 15553 inputs: []inputInfo{ 15554 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15555 }, 15556 outputs: []outputInfo{ 15557 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15558 }, 15559 }, 15560 }, 15561 { 15562 name: "VCNT", 15563 argLen: 1, 15564 asm: arm64.AVCNT, 15565 reg: regInfo{ 15566 inputs: []inputInfo{ 15567 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15568 }, 15569 outputs: []outputInfo{ 15570 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15571 }, 15572 }, 15573 }, 15574 { 15575 name: "VUADDLV", 15576 argLen: 1, 15577 asm: arm64.AVUADDLV, 15578 reg: regInfo{ 15579 inputs: []inputInfo{ 15580 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15581 }, 15582 outputs: []outputInfo{ 15583 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15584 }, 15585 }, 15586 }, 15587 { 15588 name: "LoweredRound32F", 15589 argLen: 1, 15590 resultInArg0: true, 15591 zeroWidth: true, 15592 reg: regInfo{ 15593 inputs: []inputInfo{ 15594 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15595 }, 15596 outputs: []outputInfo{ 15597 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15598 }, 15599 }, 15600 }, 15601 { 15602 name: "LoweredRound64F", 15603 argLen: 1, 15604 resultInArg0: true, 15605 zeroWidth: true, 15606 reg: regInfo{ 15607 inputs: []inputInfo{ 15608 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15609 }, 15610 outputs: []outputInfo{ 15611 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15612 }, 15613 }, 15614 }, 15615 { 15616 name: "FMADDS", 15617 argLen: 3, 15618 asm: arm64.AFMADDS, 15619 reg: regInfo{ 15620 inputs: []inputInfo{ 15621 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15622 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15623 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15624 }, 15625 outputs: []outputInfo{ 15626 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15627 }, 15628 }, 15629 }, 15630 { 15631 name: "FMADDD", 15632 argLen: 3, 15633 asm: arm64.AFMADDD, 15634 reg: regInfo{ 15635 inputs: []inputInfo{ 15636 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15637 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15638 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15639 }, 15640 outputs: []outputInfo{ 15641 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15642 }, 15643 }, 15644 }, 15645 { 15646 name: "FNMADDS", 15647 argLen: 3, 15648 asm: arm64.AFNMADDS, 15649 reg: regInfo{ 15650 inputs: []inputInfo{ 15651 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15652 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15653 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15654 }, 15655 outputs: []outputInfo{ 15656 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15657 }, 15658 }, 15659 }, 15660 { 15661 name: "FNMADDD", 15662 argLen: 3, 15663 asm: arm64.AFNMADDD, 15664 reg: regInfo{ 15665 inputs: []inputInfo{ 15666 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15667 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15668 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15669 }, 15670 outputs: []outputInfo{ 15671 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15672 }, 15673 }, 15674 }, 15675 { 15676 name: "FMSUBS", 15677 argLen: 3, 15678 asm: arm64.AFMSUBS, 15679 reg: regInfo{ 15680 inputs: []inputInfo{ 15681 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15682 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15683 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15684 }, 15685 outputs: []outputInfo{ 15686 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15687 }, 15688 }, 15689 }, 15690 { 15691 name: "FMSUBD", 15692 argLen: 3, 15693 asm: arm64.AFMSUBD, 15694 reg: regInfo{ 15695 inputs: []inputInfo{ 15696 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15697 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15698 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15699 }, 15700 outputs: []outputInfo{ 15701 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15702 }, 15703 }, 15704 }, 15705 { 15706 name: "FNMSUBS", 15707 argLen: 3, 15708 asm: arm64.AFNMSUBS, 15709 reg: regInfo{ 15710 inputs: []inputInfo{ 15711 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15712 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15713 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15714 }, 15715 outputs: []outputInfo{ 15716 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15717 }, 15718 }, 15719 }, 15720 { 15721 name: "FNMSUBD", 15722 argLen: 3, 15723 asm: arm64.AFNMSUBD, 15724 reg: regInfo{ 15725 inputs: []inputInfo{ 15726 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15727 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15728 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15729 }, 15730 outputs: []outputInfo{ 15731 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15732 }, 15733 }, 15734 }, 15735 { 15736 name: "MADD", 15737 argLen: 3, 15738 asm: arm64.AMADD, 15739 reg: regInfo{ 15740 inputs: []inputInfo{ 15741 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15742 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15743 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15744 }, 15745 outputs: []outputInfo{ 15746 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15747 }, 15748 }, 15749 }, 15750 { 15751 name: "MADDW", 15752 argLen: 3, 15753 asm: arm64.AMADDW, 15754 reg: regInfo{ 15755 inputs: []inputInfo{ 15756 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15757 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15758 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15759 }, 15760 outputs: []outputInfo{ 15761 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15762 }, 15763 }, 15764 }, 15765 { 15766 name: "MSUB", 15767 argLen: 3, 15768 asm: arm64.AMSUB, 15769 reg: regInfo{ 15770 inputs: []inputInfo{ 15771 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15772 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15773 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15774 }, 15775 outputs: []outputInfo{ 15776 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15777 }, 15778 }, 15779 }, 15780 { 15781 name: "MSUBW", 15782 argLen: 3, 15783 asm: arm64.AMSUBW, 15784 reg: regInfo{ 15785 inputs: []inputInfo{ 15786 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15787 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15788 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15789 }, 15790 outputs: []outputInfo{ 15791 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15792 }, 15793 }, 15794 }, 15795 { 15796 name: "SLL", 15797 argLen: 2, 15798 asm: arm64.ALSL, 15799 reg: regInfo{ 15800 inputs: []inputInfo{ 15801 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15802 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15803 }, 15804 outputs: []outputInfo{ 15805 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15806 }, 15807 }, 15808 }, 15809 { 15810 name: "SLLconst", 15811 auxType: auxInt64, 15812 argLen: 1, 15813 asm: arm64.ALSL, 15814 reg: regInfo{ 15815 inputs: []inputInfo{ 15816 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15817 }, 15818 outputs: []outputInfo{ 15819 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15820 }, 15821 }, 15822 }, 15823 { 15824 name: "SRL", 15825 argLen: 2, 15826 asm: arm64.ALSR, 15827 reg: regInfo{ 15828 inputs: []inputInfo{ 15829 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15830 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15831 }, 15832 outputs: []outputInfo{ 15833 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15834 }, 15835 }, 15836 }, 15837 { 15838 name: "SRLconst", 15839 auxType: auxInt64, 15840 argLen: 1, 15841 asm: arm64.ALSR, 15842 reg: regInfo{ 15843 inputs: []inputInfo{ 15844 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15845 }, 15846 outputs: []outputInfo{ 15847 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15848 }, 15849 }, 15850 }, 15851 { 15852 name: "SRA", 15853 argLen: 2, 15854 asm: arm64.AASR, 15855 reg: regInfo{ 15856 inputs: []inputInfo{ 15857 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15858 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15859 }, 15860 outputs: []outputInfo{ 15861 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15862 }, 15863 }, 15864 }, 15865 { 15866 name: "SRAconst", 15867 auxType: auxInt64, 15868 argLen: 1, 15869 asm: arm64.AASR, 15870 reg: regInfo{ 15871 inputs: []inputInfo{ 15872 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15873 }, 15874 outputs: []outputInfo{ 15875 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15876 }, 15877 }, 15878 }, 15879 { 15880 name: "ROR", 15881 argLen: 2, 15882 asm: arm64.AROR, 15883 reg: regInfo{ 15884 inputs: []inputInfo{ 15885 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15886 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15887 }, 15888 outputs: []outputInfo{ 15889 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15890 }, 15891 }, 15892 }, 15893 { 15894 name: "RORW", 15895 argLen: 2, 15896 asm: arm64.ARORW, 15897 reg: regInfo{ 15898 inputs: []inputInfo{ 15899 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15900 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15901 }, 15902 outputs: []outputInfo{ 15903 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15904 }, 15905 }, 15906 }, 15907 { 15908 name: "RORconst", 15909 auxType: auxInt64, 15910 argLen: 1, 15911 asm: arm64.AROR, 15912 reg: regInfo{ 15913 inputs: []inputInfo{ 15914 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15915 }, 15916 outputs: []outputInfo{ 15917 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15918 }, 15919 }, 15920 }, 15921 { 15922 name: "RORWconst", 15923 auxType: auxInt64, 15924 argLen: 1, 15925 asm: arm64.ARORW, 15926 reg: regInfo{ 15927 inputs: []inputInfo{ 15928 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15929 }, 15930 outputs: []outputInfo{ 15931 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15932 }, 15933 }, 15934 }, 15935 { 15936 name: "EXTRconst", 15937 auxType: auxInt64, 15938 argLen: 2, 15939 asm: arm64.AEXTR, 15940 reg: regInfo{ 15941 inputs: []inputInfo{ 15942 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15943 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15944 }, 15945 outputs: []outputInfo{ 15946 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15947 }, 15948 }, 15949 }, 15950 { 15951 name: "EXTRWconst", 15952 auxType: auxInt64, 15953 argLen: 2, 15954 asm: arm64.AEXTRW, 15955 reg: regInfo{ 15956 inputs: []inputInfo{ 15957 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15958 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15959 }, 15960 outputs: []outputInfo{ 15961 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 15962 }, 15963 }, 15964 }, 15965 { 15966 name: "CMP", 15967 argLen: 2, 15968 asm: arm64.ACMP, 15969 reg: regInfo{ 15970 inputs: []inputInfo{ 15971 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15972 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15973 }, 15974 }, 15975 }, 15976 { 15977 name: "CMPconst", 15978 auxType: auxInt64, 15979 argLen: 1, 15980 asm: arm64.ACMP, 15981 reg: regInfo{ 15982 inputs: []inputInfo{ 15983 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15984 }, 15985 }, 15986 }, 15987 { 15988 name: "CMPW", 15989 argLen: 2, 15990 asm: arm64.ACMPW, 15991 reg: regInfo{ 15992 inputs: []inputInfo{ 15993 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15994 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 15995 }, 15996 }, 15997 }, 15998 { 15999 name: "CMPWconst", 16000 auxType: auxInt32, 16001 argLen: 1, 16002 asm: arm64.ACMPW, 16003 reg: regInfo{ 16004 inputs: []inputInfo{ 16005 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16006 }, 16007 }, 16008 }, 16009 { 16010 name: "CMN", 16011 argLen: 2, 16012 commutative: true, 16013 asm: arm64.ACMN, 16014 reg: regInfo{ 16015 inputs: []inputInfo{ 16016 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16017 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16018 }, 16019 }, 16020 }, 16021 { 16022 name: "CMNconst", 16023 auxType: auxInt64, 16024 argLen: 1, 16025 asm: arm64.ACMN, 16026 reg: regInfo{ 16027 inputs: []inputInfo{ 16028 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16029 }, 16030 }, 16031 }, 16032 { 16033 name: "CMNW", 16034 argLen: 2, 16035 commutative: true, 16036 asm: arm64.ACMNW, 16037 reg: regInfo{ 16038 inputs: []inputInfo{ 16039 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16040 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16041 }, 16042 }, 16043 }, 16044 { 16045 name: "CMNWconst", 16046 auxType: auxInt32, 16047 argLen: 1, 16048 asm: arm64.ACMNW, 16049 reg: regInfo{ 16050 inputs: []inputInfo{ 16051 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16052 }, 16053 }, 16054 }, 16055 { 16056 name: "TST", 16057 argLen: 2, 16058 commutative: true, 16059 asm: arm64.ATST, 16060 reg: regInfo{ 16061 inputs: []inputInfo{ 16062 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16063 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16064 }, 16065 }, 16066 }, 16067 { 16068 name: "TSTconst", 16069 auxType: auxInt64, 16070 argLen: 1, 16071 asm: arm64.ATST, 16072 reg: regInfo{ 16073 inputs: []inputInfo{ 16074 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16075 }, 16076 }, 16077 }, 16078 { 16079 name: "TSTW", 16080 argLen: 2, 16081 commutative: true, 16082 asm: arm64.ATSTW, 16083 reg: regInfo{ 16084 inputs: []inputInfo{ 16085 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16086 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16087 }, 16088 }, 16089 }, 16090 { 16091 name: "TSTWconst", 16092 auxType: auxInt32, 16093 argLen: 1, 16094 asm: arm64.ATSTW, 16095 reg: regInfo{ 16096 inputs: []inputInfo{ 16097 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16098 }, 16099 }, 16100 }, 16101 { 16102 name: "FCMPS", 16103 argLen: 2, 16104 asm: arm64.AFCMPS, 16105 reg: regInfo{ 16106 inputs: []inputInfo{ 16107 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16108 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16109 }, 16110 }, 16111 }, 16112 { 16113 name: "FCMPD", 16114 argLen: 2, 16115 asm: arm64.AFCMPD, 16116 reg: regInfo{ 16117 inputs: []inputInfo{ 16118 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16119 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16120 }, 16121 }, 16122 }, 16123 { 16124 name: "MVNshiftLL", 16125 auxType: auxInt64, 16126 argLen: 1, 16127 asm: arm64.AMVN, 16128 reg: regInfo{ 16129 inputs: []inputInfo{ 16130 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16131 }, 16132 outputs: []outputInfo{ 16133 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16134 }, 16135 }, 16136 }, 16137 { 16138 name: "MVNshiftRL", 16139 auxType: auxInt64, 16140 argLen: 1, 16141 asm: arm64.AMVN, 16142 reg: regInfo{ 16143 inputs: []inputInfo{ 16144 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16145 }, 16146 outputs: []outputInfo{ 16147 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16148 }, 16149 }, 16150 }, 16151 { 16152 name: "MVNshiftRA", 16153 auxType: auxInt64, 16154 argLen: 1, 16155 asm: arm64.AMVN, 16156 reg: regInfo{ 16157 inputs: []inputInfo{ 16158 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16159 }, 16160 outputs: []outputInfo{ 16161 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16162 }, 16163 }, 16164 }, 16165 { 16166 name: "NEGshiftLL", 16167 auxType: auxInt64, 16168 argLen: 1, 16169 asm: arm64.ANEG, 16170 reg: regInfo{ 16171 inputs: []inputInfo{ 16172 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16173 }, 16174 outputs: []outputInfo{ 16175 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16176 }, 16177 }, 16178 }, 16179 { 16180 name: "NEGshiftRL", 16181 auxType: auxInt64, 16182 argLen: 1, 16183 asm: arm64.ANEG, 16184 reg: regInfo{ 16185 inputs: []inputInfo{ 16186 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16187 }, 16188 outputs: []outputInfo{ 16189 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16190 }, 16191 }, 16192 }, 16193 { 16194 name: "NEGshiftRA", 16195 auxType: auxInt64, 16196 argLen: 1, 16197 asm: arm64.ANEG, 16198 reg: regInfo{ 16199 inputs: []inputInfo{ 16200 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16201 }, 16202 outputs: []outputInfo{ 16203 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16204 }, 16205 }, 16206 }, 16207 { 16208 name: "ADDshiftLL", 16209 auxType: auxInt64, 16210 argLen: 2, 16211 asm: arm64.AADD, 16212 reg: regInfo{ 16213 inputs: []inputInfo{ 16214 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16215 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16216 }, 16217 outputs: []outputInfo{ 16218 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16219 }, 16220 }, 16221 }, 16222 { 16223 name: "ADDshiftRL", 16224 auxType: auxInt64, 16225 argLen: 2, 16226 asm: arm64.AADD, 16227 reg: regInfo{ 16228 inputs: []inputInfo{ 16229 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16230 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16231 }, 16232 outputs: []outputInfo{ 16233 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16234 }, 16235 }, 16236 }, 16237 { 16238 name: "ADDshiftRA", 16239 auxType: auxInt64, 16240 argLen: 2, 16241 asm: arm64.AADD, 16242 reg: regInfo{ 16243 inputs: []inputInfo{ 16244 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16245 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16246 }, 16247 outputs: []outputInfo{ 16248 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16249 }, 16250 }, 16251 }, 16252 { 16253 name: "SUBshiftLL", 16254 auxType: auxInt64, 16255 argLen: 2, 16256 asm: arm64.ASUB, 16257 reg: regInfo{ 16258 inputs: []inputInfo{ 16259 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16260 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16261 }, 16262 outputs: []outputInfo{ 16263 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16264 }, 16265 }, 16266 }, 16267 { 16268 name: "SUBshiftRL", 16269 auxType: auxInt64, 16270 argLen: 2, 16271 asm: arm64.ASUB, 16272 reg: regInfo{ 16273 inputs: []inputInfo{ 16274 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16275 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16276 }, 16277 outputs: []outputInfo{ 16278 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16279 }, 16280 }, 16281 }, 16282 { 16283 name: "SUBshiftRA", 16284 auxType: auxInt64, 16285 argLen: 2, 16286 asm: arm64.ASUB, 16287 reg: regInfo{ 16288 inputs: []inputInfo{ 16289 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16290 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16291 }, 16292 outputs: []outputInfo{ 16293 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16294 }, 16295 }, 16296 }, 16297 { 16298 name: "ANDshiftLL", 16299 auxType: auxInt64, 16300 argLen: 2, 16301 asm: arm64.AAND, 16302 reg: regInfo{ 16303 inputs: []inputInfo{ 16304 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16305 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16306 }, 16307 outputs: []outputInfo{ 16308 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16309 }, 16310 }, 16311 }, 16312 { 16313 name: "ANDshiftRL", 16314 auxType: auxInt64, 16315 argLen: 2, 16316 asm: arm64.AAND, 16317 reg: regInfo{ 16318 inputs: []inputInfo{ 16319 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16320 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16321 }, 16322 outputs: []outputInfo{ 16323 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16324 }, 16325 }, 16326 }, 16327 { 16328 name: "ANDshiftRA", 16329 auxType: auxInt64, 16330 argLen: 2, 16331 asm: arm64.AAND, 16332 reg: regInfo{ 16333 inputs: []inputInfo{ 16334 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16335 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16336 }, 16337 outputs: []outputInfo{ 16338 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16339 }, 16340 }, 16341 }, 16342 { 16343 name: "ORshiftLL", 16344 auxType: auxInt64, 16345 argLen: 2, 16346 asm: arm64.AORR, 16347 reg: regInfo{ 16348 inputs: []inputInfo{ 16349 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16350 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16351 }, 16352 outputs: []outputInfo{ 16353 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16354 }, 16355 }, 16356 }, 16357 { 16358 name: "ORshiftRL", 16359 auxType: auxInt64, 16360 argLen: 2, 16361 asm: arm64.AORR, 16362 reg: regInfo{ 16363 inputs: []inputInfo{ 16364 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16365 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16366 }, 16367 outputs: []outputInfo{ 16368 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16369 }, 16370 }, 16371 }, 16372 { 16373 name: "ORshiftRA", 16374 auxType: auxInt64, 16375 argLen: 2, 16376 asm: arm64.AORR, 16377 reg: regInfo{ 16378 inputs: []inputInfo{ 16379 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16380 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16381 }, 16382 outputs: []outputInfo{ 16383 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16384 }, 16385 }, 16386 }, 16387 { 16388 name: "XORshiftLL", 16389 auxType: auxInt64, 16390 argLen: 2, 16391 asm: arm64.AEOR, 16392 reg: regInfo{ 16393 inputs: []inputInfo{ 16394 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16395 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16396 }, 16397 outputs: []outputInfo{ 16398 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16399 }, 16400 }, 16401 }, 16402 { 16403 name: "XORshiftRL", 16404 auxType: auxInt64, 16405 argLen: 2, 16406 asm: arm64.AEOR, 16407 reg: regInfo{ 16408 inputs: []inputInfo{ 16409 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16410 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16411 }, 16412 outputs: []outputInfo{ 16413 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16414 }, 16415 }, 16416 }, 16417 { 16418 name: "XORshiftRA", 16419 auxType: auxInt64, 16420 argLen: 2, 16421 asm: arm64.AEOR, 16422 reg: regInfo{ 16423 inputs: []inputInfo{ 16424 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16425 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16426 }, 16427 outputs: []outputInfo{ 16428 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16429 }, 16430 }, 16431 }, 16432 { 16433 name: "BICshiftLL", 16434 auxType: auxInt64, 16435 argLen: 2, 16436 asm: arm64.ABIC, 16437 reg: regInfo{ 16438 inputs: []inputInfo{ 16439 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16440 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16441 }, 16442 outputs: []outputInfo{ 16443 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16444 }, 16445 }, 16446 }, 16447 { 16448 name: "BICshiftRL", 16449 auxType: auxInt64, 16450 argLen: 2, 16451 asm: arm64.ABIC, 16452 reg: regInfo{ 16453 inputs: []inputInfo{ 16454 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16455 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16456 }, 16457 outputs: []outputInfo{ 16458 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16459 }, 16460 }, 16461 }, 16462 { 16463 name: "BICshiftRA", 16464 auxType: auxInt64, 16465 argLen: 2, 16466 asm: arm64.ABIC, 16467 reg: regInfo{ 16468 inputs: []inputInfo{ 16469 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16470 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16471 }, 16472 outputs: []outputInfo{ 16473 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16474 }, 16475 }, 16476 }, 16477 { 16478 name: "EONshiftLL", 16479 auxType: auxInt64, 16480 argLen: 2, 16481 asm: arm64.AEON, 16482 reg: regInfo{ 16483 inputs: []inputInfo{ 16484 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16485 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16486 }, 16487 outputs: []outputInfo{ 16488 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16489 }, 16490 }, 16491 }, 16492 { 16493 name: "EONshiftRL", 16494 auxType: auxInt64, 16495 argLen: 2, 16496 asm: arm64.AEON, 16497 reg: regInfo{ 16498 inputs: []inputInfo{ 16499 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16500 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16501 }, 16502 outputs: []outputInfo{ 16503 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16504 }, 16505 }, 16506 }, 16507 { 16508 name: "EONshiftRA", 16509 auxType: auxInt64, 16510 argLen: 2, 16511 asm: arm64.AEON, 16512 reg: regInfo{ 16513 inputs: []inputInfo{ 16514 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16515 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16516 }, 16517 outputs: []outputInfo{ 16518 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16519 }, 16520 }, 16521 }, 16522 { 16523 name: "ORNshiftLL", 16524 auxType: auxInt64, 16525 argLen: 2, 16526 asm: arm64.AORN, 16527 reg: regInfo{ 16528 inputs: []inputInfo{ 16529 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16530 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16531 }, 16532 outputs: []outputInfo{ 16533 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16534 }, 16535 }, 16536 }, 16537 { 16538 name: "ORNshiftRL", 16539 auxType: auxInt64, 16540 argLen: 2, 16541 asm: arm64.AORN, 16542 reg: regInfo{ 16543 inputs: []inputInfo{ 16544 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16545 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16546 }, 16547 outputs: []outputInfo{ 16548 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16549 }, 16550 }, 16551 }, 16552 { 16553 name: "ORNshiftRA", 16554 auxType: auxInt64, 16555 argLen: 2, 16556 asm: arm64.AORN, 16557 reg: regInfo{ 16558 inputs: []inputInfo{ 16559 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16560 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16561 }, 16562 outputs: []outputInfo{ 16563 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16564 }, 16565 }, 16566 }, 16567 { 16568 name: "CMPshiftLL", 16569 auxType: auxInt64, 16570 argLen: 2, 16571 asm: arm64.ACMP, 16572 reg: regInfo{ 16573 inputs: []inputInfo{ 16574 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16575 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16576 }, 16577 }, 16578 }, 16579 { 16580 name: "CMPshiftRL", 16581 auxType: auxInt64, 16582 argLen: 2, 16583 asm: arm64.ACMP, 16584 reg: regInfo{ 16585 inputs: []inputInfo{ 16586 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16587 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16588 }, 16589 }, 16590 }, 16591 { 16592 name: "CMPshiftRA", 16593 auxType: auxInt64, 16594 argLen: 2, 16595 asm: arm64.ACMP, 16596 reg: regInfo{ 16597 inputs: []inputInfo{ 16598 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16599 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16600 }, 16601 }, 16602 }, 16603 { 16604 name: "CMNshiftLL", 16605 auxType: auxInt64, 16606 argLen: 2, 16607 asm: arm64.ACMN, 16608 reg: regInfo{ 16609 inputs: []inputInfo{ 16610 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16611 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16612 }, 16613 }, 16614 }, 16615 { 16616 name: "CMNshiftRL", 16617 auxType: auxInt64, 16618 argLen: 2, 16619 asm: arm64.ACMN, 16620 reg: regInfo{ 16621 inputs: []inputInfo{ 16622 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16623 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16624 }, 16625 }, 16626 }, 16627 { 16628 name: "CMNshiftRA", 16629 auxType: auxInt64, 16630 argLen: 2, 16631 asm: arm64.ACMN, 16632 reg: regInfo{ 16633 inputs: []inputInfo{ 16634 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16635 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16636 }, 16637 }, 16638 }, 16639 { 16640 name: "TSTshiftLL", 16641 auxType: auxInt64, 16642 argLen: 2, 16643 asm: arm64.ATST, 16644 reg: regInfo{ 16645 inputs: []inputInfo{ 16646 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16647 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16648 }, 16649 }, 16650 }, 16651 { 16652 name: "TSTshiftRL", 16653 auxType: auxInt64, 16654 argLen: 2, 16655 asm: arm64.ATST, 16656 reg: regInfo{ 16657 inputs: []inputInfo{ 16658 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16659 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16660 }, 16661 }, 16662 }, 16663 { 16664 name: "TSTshiftRA", 16665 auxType: auxInt64, 16666 argLen: 2, 16667 asm: arm64.ATST, 16668 reg: regInfo{ 16669 inputs: []inputInfo{ 16670 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16671 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16672 }, 16673 }, 16674 }, 16675 { 16676 name: "BFI", 16677 auxType: auxInt64, 16678 argLen: 2, 16679 resultInArg0: true, 16680 asm: arm64.ABFI, 16681 reg: regInfo{ 16682 inputs: []inputInfo{ 16683 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16684 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16685 }, 16686 outputs: []outputInfo{ 16687 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16688 }, 16689 }, 16690 }, 16691 { 16692 name: "BFXIL", 16693 auxType: auxInt64, 16694 argLen: 2, 16695 resultInArg0: true, 16696 asm: arm64.ABFXIL, 16697 reg: regInfo{ 16698 inputs: []inputInfo{ 16699 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16700 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16701 }, 16702 outputs: []outputInfo{ 16703 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16704 }, 16705 }, 16706 }, 16707 { 16708 name: "SBFIZ", 16709 auxType: auxInt64, 16710 argLen: 1, 16711 asm: arm64.ASBFIZ, 16712 reg: regInfo{ 16713 inputs: []inputInfo{ 16714 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16715 }, 16716 outputs: []outputInfo{ 16717 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16718 }, 16719 }, 16720 }, 16721 { 16722 name: "SBFX", 16723 auxType: auxInt64, 16724 argLen: 1, 16725 asm: arm64.ASBFX, 16726 reg: regInfo{ 16727 inputs: []inputInfo{ 16728 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16729 }, 16730 outputs: []outputInfo{ 16731 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16732 }, 16733 }, 16734 }, 16735 { 16736 name: "UBFIZ", 16737 auxType: auxInt64, 16738 argLen: 1, 16739 asm: arm64.AUBFIZ, 16740 reg: regInfo{ 16741 inputs: []inputInfo{ 16742 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16743 }, 16744 outputs: []outputInfo{ 16745 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16746 }, 16747 }, 16748 }, 16749 { 16750 name: "UBFX", 16751 auxType: auxInt64, 16752 argLen: 1, 16753 asm: arm64.AUBFX, 16754 reg: regInfo{ 16755 inputs: []inputInfo{ 16756 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16757 }, 16758 outputs: []outputInfo{ 16759 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16760 }, 16761 }, 16762 }, 16763 { 16764 name: "MOVDconst", 16765 auxType: auxInt64, 16766 argLen: 0, 16767 rematerializeable: true, 16768 asm: arm64.AMOVD, 16769 reg: regInfo{ 16770 outputs: []outputInfo{ 16771 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16772 }, 16773 }, 16774 }, 16775 { 16776 name: "FMOVSconst", 16777 auxType: auxFloat64, 16778 argLen: 0, 16779 rematerializeable: true, 16780 asm: arm64.AFMOVS, 16781 reg: regInfo{ 16782 outputs: []outputInfo{ 16783 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16784 }, 16785 }, 16786 }, 16787 { 16788 name: "FMOVDconst", 16789 auxType: auxFloat64, 16790 argLen: 0, 16791 rematerializeable: true, 16792 asm: arm64.AFMOVD, 16793 reg: regInfo{ 16794 outputs: []outputInfo{ 16795 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16796 }, 16797 }, 16798 }, 16799 { 16800 name: "MOVDaddr", 16801 auxType: auxSymOff, 16802 argLen: 1, 16803 rematerializeable: true, 16804 symEffect: SymAddr, 16805 asm: arm64.AMOVD, 16806 reg: regInfo{ 16807 inputs: []inputInfo{ 16808 {0, 9223372037928517632}, // SP SB 16809 }, 16810 outputs: []outputInfo{ 16811 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16812 }, 16813 }, 16814 }, 16815 { 16816 name: "MOVBload", 16817 auxType: auxSymOff, 16818 argLen: 2, 16819 faultOnNilArg0: true, 16820 symEffect: SymRead, 16821 asm: arm64.AMOVB, 16822 reg: regInfo{ 16823 inputs: []inputInfo{ 16824 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16825 }, 16826 outputs: []outputInfo{ 16827 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16828 }, 16829 }, 16830 }, 16831 { 16832 name: "MOVBUload", 16833 auxType: auxSymOff, 16834 argLen: 2, 16835 faultOnNilArg0: true, 16836 symEffect: SymRead, 16837 asm: arm64.AMOVBU, 16838 reg: regInfo{ 16839 inputs: []inputInfo{ 16840 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16841 }, 16842 outputs: []outputInfo{ 16843 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16844 }, 16845 }, 16846 }, 16847 { 16848 name: "MOVHload", 16849 auxType: auxSymOff, 16850 argLen: 2, 16851 faultOnNilArg0: true, 16852 symEffect: SymRead, 16853 asm: arm64.AMOVH, 16854 reg: regInfo{ 16855 inputs: []inputInfo{ 16856 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16857 }, 16858 outputs: []outputInfo{ 16859 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16860 }, 16861 }, 16862 }, 16863 { 16864 name: "MOVHUload", 16865 auxType: auxSymOff, 16866 argLen: 2, 16867 faultOnNilArg0: true, 16868 symEffect: SymRead, 16869 asm: arm64.AMOVHU, 16870 reg: regInfo{ 16871 inputs: []inputInfo{ 16872 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16873 }, 16874 outputs: []outputInfo{ 16875 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16876 }, 16877 }, 16878 }, 16879 { 16880 name: "MOVWload", 16881 auxType: auxSymOff, 16882 argLen: 2, 16883 faultOnNilArg0: true, 16884 symEffect: SymRead, 16885 asm: arm64.AMOVW, 16886 reg: regInfo{ 16887 inputs: []inputInfo{ 16888 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16889 }, 16890 outputs: []outputInfo{ 16891 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16892 }, 16893 }, 16894 }, 16895 { 16896 name: "MOVWUload", 16897 auxType: auxSymOff, 16898 argLen: 2, 16899 faultOnNilArg0: true, 16900 symEffect: SymRead, 16901 asm: arm64.AMOVWU, 16902 reg: regInfo{ 16903 inputs: []inputInfo{ 16904 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16905 }, 16906 outputs: []outputInfo{ 16907 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16908 }, 16909 }, 16910 }, 16911 { 16912 name: "MOVDload", 16913 auxType: auxSymOff, 16914 argLen: 2, 16915 faultOnNilArg0: true, 16916 symEffect: SymRead, 16917 asm: arm64.AMOVD, 16918 reg: regInfo{ 16919 inputs: []inputInfo{ 16920 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16921 }, 16922 outputs: []outputInfo{ 16923 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16924 }, 16925 }, 16926 }, 16927 { 16928 name: "FMOVSload", 16929 auxType: auxSymOff, 16930 argLen: 2, 16931 faultOnNilArg0: true, 16932 symEffect: SymRead, 16933 asm: arm64.AFMOVS, 16934 reg: regInfo{ 16935 inputs: []inputInfo{ 16936 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16937 }, 16938 outputs: []outputInfo{ 16939 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16940 }, 16941 }, 16942 }, 16943 { 16944 name: "FMOVDload", 16945 auxType: auxSymOff, 16946 argLen: 2, 16947 faultOnNilArg0: true, 16948 symEffect: SymRead, 16949 asm: arm64.AFMOVD, 16950 reg: regInfo{ 16951 inputs: []inputInfo{ 16952 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16953 }, 16954 outputs: []outputInfo{ 16955 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16956 }, 16957 }, 16958 }, 16959 { 16960 name: "MOVDloadidx", 16961 argLen: 3, 16962 asm: arm64.AMOVD, 16963 reg: regInfo{ 16964 inputs: []inputInfo{ 16965 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16966 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16967 }, 16968 outputs: []outputInfo{ 16969 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16970 }, 16971 }, 16972 }, 16973 { 16974 name: "MOVWloadidx", 16975 argLen: 3, 16976 asm: arm64.AMOVW, 16977 reg: regInfo{ 16978 inputs: []inputInfo{ 16979 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16980 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16981 }, 16982 outputs: []outputInfo{ 16983 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16984 }, 16985 }, 16986 }, 16987 { 16988 name: "MOVWUloadidx", 16989 argLen: 3, 16990 asm: arm64.AMOVWU, 16991 reg: regInfo{ 16992 inputs: []inputInfo{ 16993 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 16994 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 16995 }, 16996 outputs: []outputInfo{ 16997 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 16998 }, 16999 }, 17000 }, 17001 { 17002 name: "MOVHloadidx", 17003 argLen: 3, 17004 asm: arm64.AMOVH, 17005 reg: regInfo{ 17006 inputs: []inputInfo{ 17007 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17008 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17009 }, 17010 outputs: []outputInfo{ 17011 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17012 }, 17013 }, 17014 }, 17015 { 17016 name: "MOVHUloadidx", 17017 argLen: 3, 17018 asm: arm64.AMOVHU, 17019 reg: regInfo{ 17020 inputs: []inputInfo{ 17021 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17022 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17023 }, 17024 outputs: []outputInfo{ 17025 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17026 }, 17027 }, 17028 }, 17029 { 17030 name: "MOVBloadidx", 17031 argLen: 3, 17032 asm: arm64.AMOVB, 17033 reg: regInfo{ 17034 inputs: []inputInfo{ 17035 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17036 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17037 }, 17038 outputs: []outputInfo{ 17039 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17040 }, 17041 }, 17042 }, 17043 { 17044 name: "MOVBUloadidx", 17045 argLen: 3, 17046 asm: arm64.AMOVBU, 17047 reg: regInfo{ 17048 inputs: []inputInfo{ 17049 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17050 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17051 }, 17052 outputs: []outputInfo{ 17053 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17054 }, 17055 }, 17056 }, 17057 { 17058 name: "FMOVSloadidx", 17059 argLen: 3, 17060 asm: arm64.AFMOVS, 17061 reg: regInfo{ 17062 inputs: []inputInfo{ 17063 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17064 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17065 }, 17066 outputs: []outputInfo{ 17067 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17068 }, 17069 }, 17070 }, 17071 { 17072 name: "FMOVDloadidx", 17073 argLen: 3, 17074 asm: arm64.AFMOVD, 17075 reg: regInfo{ 17076 inputs: []inputInfo{ 17077 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17078 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17079 }, 17080 outputs: []outputInfo{ 17081 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17082 }, 17083 }, 17084 }, 17085 { 17086 name: "MOVHloadidx2", 17087 argLen: 3, 17088 asm: arm64.AMOVH, 17089 reg: regInfo{ 17090 inputs: []inputInfo{ 17091 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17092 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17093 }, 17094 outputs: []outputInfo{ 17095 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17096 }, 17097 }, 17098 }, 17099 { 17100 name: "MOVHUloadidx2", 17101 argLen: 3, 17102 asm: arm64.AMOVHU, 17103 reg: regInfo{ 17104 inputs: []inputInfo{ 17105 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17106 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17107 }, 17108 outputs: []outputInfo{ 17109 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17110 }, 17111 }, 17112 }, 17113 { 17114 name: "MOVWloadidx4", 17115 argLen: 3, 17116 asm: arm64.AMOVW, 17117 reg: regInfo{ 17118 inputs: []inputInfo{ 17119 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17120 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17121 }, 17122 outputs: []outputInfo{ 17123 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17124 }, 17125 }, 17126 }, 17127 { 17128 name: "MOVWUloadidx4", 17129 argLen: 3, 17130 asm: arm64.AMOVWU, 17131 reg: regInfo{ 17132 inputs: []inputInfo{ 17133 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17134 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17135 }, 17136 outputs: []outputInfo{ 17137 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17138 }, 17139 }, 17140 }, 17141 { 17142 name: "MOVDloadidx8", 17143 argLen: 3, 17144 asm: arm64.AMOVD, 17145 reg: regInfo{ 17146 inputs: []inputInfo{ 17147 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17148 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17149 }, 17150 outputs: []outputInfo{ 17151 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17152 }, 17153 }, 17154 }, 17155 { 17156 name: "MOVBstore", 17157 auxType: auxSymOff, 17158 argLen: 3, 17159 faultOnNilArg0: true, 17160 symEffect: SymWrite, 17161 asm: arm64.AMOVB, 17162 reg: regInfo{ 17163 inputs: []inputInfo{ 17164 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17165 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17166 }, 17167 }, 17168 }, 17169 { 17170 name: "MOVHstore", 17171 auxType: auxSymOff, 17172 argLen: 3, 17173 faultOnNilArg0: true, 17174 symEffect: SymWrite, 17175 asm: arm64.AMOVH, 17176 reg: regInfo{ 17177 inputs: []inputInfo{ 17178 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17179 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17180 }, 17181 }, 17182 }, 17183 { 17184 name: "MOVWstore", 17185 auxType: auxSymOff, 17186 argLen: 3, 17187 faultOnNilArg0: true, 17188 symEffect: SymWrite, 17189 asm: arm64.AMOVW, 17190 reg: regInfo{ 17191 inputs: []inputInfo{ 17192 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17193 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17194 }, 17195 }, 17196 }, 17197 { 17198 name: "MOVDstore", 17199 auxType: auxSymOff, 17200 argLen: 3, 17201 faultOnNilArg0: true, 17202 symEffect: SymWrite, 17203 asm: arm64.AMOVD, 17204 reg: regInfo{ 17205 inputs: []inputInfo{ 17206 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17207 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17208 }, 17209 }, 17210 }, 17211 { 17212 name: "STP", 17213 auxType: auxSymOff, 17214 argLen: 4, 17215 faultOnNilArg0: true, 17216 symEffect: SymWrite, 17217 asm: arm64.ASTP, 17218 reg: regInfo{ 17219 inputs: []inputInfo{ 17220 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17221 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17222 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17223 }, 17224 }, 17225 }, 17226 { 17227 name: "FMOVSstore", 17228 auxType: auxSymOff, 17229 argLen: 3, 17230 faultOnNilArg0: true, 17231 symEffect: SymWrite, 17232 asm: arm64.AFMOVS, 17233 reg: regInfo{ 17234 inputs: []inputInfo{ 17235 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17236 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17237 }, 17238 }, 17239 }, 17240 { 17241 name: "FMOVDstore", 17242 auxType: auxSymOff, 17243 argLen: 3, 17244 faultOnNilArg0: true, 17245 symEffect: SymWrite, 17246 asm: arm64.AFMOVD, 17247 reg: regInfo{ 17248 inputs: []inputInfo{ 17249 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17250 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17251 }, 17252 }, 17253 }, 17254 { 17255 name: "MOVBstoreidx", 17256 argLen: 4, 17257 asm: arm64.AMOVB, 17258 reg: regInfo{ 17259 inputs: []inputInfo{ 17260 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17261 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17262 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17263 }, 17264 }, 17265 }, 17266 { 17267 name: "MOVHstoreidx", 17268 argLen: 4, 17269 asm: arm64.AMOVH, 17270 reg: regInfo{ 17271 inputs: []inputInfo{ 17272 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17273 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17274 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17275 }, 17276 }, 17277 }, 17278 { 17279 name: "MOVWstoreidx", 17280 argLen: 4, 17281 asm: arm64.AMOVW, 17282 reg: regInfo{ 17283 inputs: []inputInfo{ 17284 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17285 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17286 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17287 }, 17288 }, 17289 }, 17290 { 17291 name: "MOVDstoreidx", 17292 argLen: 4, 17293 asm: arm64.AMOVD, 17294 reg: regInfo{ 17295 inputs: []inputInfo{ 17296 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17297 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17298 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17299 }, 17300 }, 17301 }, 17302 { 17303 name: "FMOVSstoreidx", 17304 argLen: 4, 17305 asm: arm64.AFMOVS, 17306 reg: regInfo{ 17307 inputs: []inputInfo{ 17308 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17309 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17310 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17311 }, 17312 }, 17313 }, 17314 { 17315 name: "FMOVDstoreidx", 17316 argLen: 4, 17317 asm: arm64.AFMOVD, 17318 reg: regInfo{ 17319 inputs: []inputInfo{ 17320 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17321 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17322 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17323 }, 17324 }, 17325 }, 17326 { 17327 name: "MOVHstoreidx2", 17328 argLen: 4, 17329 asm: arm64.AMOVH, 17330 reg: regInfo{ 17331 inputs: []inputInfo{ 17332 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17333 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17334 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17335 }, 17336 }, 17337 }, 17338 { 17339 name: "MOVWstoreidx4", 17340 argLen: 4, 17341 asm: arm64.AMOVW, 17342 reg: regInfo{ 17343 inputs: []inputInfo{ 17344 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17345 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17346 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17347 }, 17348 }, 17349 }, 17350 { 17351 name: "MOVDstoreidx8", 17352 argLen: 4, 17353 asm: arm64.AMOVD, 17354 reg: regInfo{ 17355 inputs: []inputInfo{ 17356 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17357 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17358 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17359 }, 17360 }, 17361 }, 17362 { 17363 name: "MOVBstorezero", 17364 auxType: auxSymOff, 17365 argLen: 2, 17366 faultOnNilArg0: true, 17367 symEffect: SymWrite, 17368 asm: arm64.AMOVB, 17369 reg: regInfo{ 17370 inputs: []inputInfo{ 17371 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17372 }, 17373 }, 17374 }, 17375 { 17376 name: "MOVHstorezero", 17377 auxType: auxSymOff, 17378 argLen: 2, 17379 faultOnNilArg0: true, 17380 symEffect: SymWrite, 17381 asm: arm64.AMOVH, 17382 reg: regInfo{ 17383 inputs: []inputInfo{ 17384 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17385 }, 17386 }, 17387 }, 17388 { 17389 name: "MOVWstorezero", 17390 auxType: auxSymOff, 17391 argLen: 2, 17392 faultOnNilArg0: true, 17393 symEffect: SymWrite, 17394 asm: arm64.AMOVW, 17395 reg: regInfo{ 17396 inputs: []inputInfo{ 17397 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17398 }, 17399 }, 17400 }, 17401 { 17402 name: "MOVDstorezero", 17403 auxType: auxSymOff, 17404 argLen: 2, 17405 faultOnNilArg0: true, 17406 symEffect: SymWrite, 17407 asm: arm64.AMOVD, 17408 reg: regInfo{ 17409 inputs: []inputInfo{ 17410 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17411 }, 17412 }, 17413 }, 17414 { 17415 name: "MOVQstorezero", 17416 auxType: auxSymOff, 17417 argLen: 2, 17418 faultOnNilArg0: true, 17419 symEffect: SymWrite, 17420 asm: arm64.ASTP, 17421 reg: regInfo{ 17422 inputs: []inputInfo{ 17423 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17424 }, 17425 }, 17426 }, 17427 { 17428 name: "MOVBstorezeroidx", 17429 argLen: 3, 17430 asm: arm64.AMOVB, 17431 reg: regInfo{ 17432 inputs: []inputInfo{ 17433 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17434 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17435 }, 17436 }, 17437 }, 17438 { 17439 name: "MOVHstorezeroidx", 17440 argLen: 3, 17441 asm: arm64.AMOVH, 17442 reg: regInfo{ 17443 inputs: []inputInfo{ 17444 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17445 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17446 }, 17447 }, 17448 }, 17449 { 17450 name: "MOVWstorezeroidx", 17451 argLen: 3, 17452 asm: arm64.AMOVW, 17453 reg: regInfo{ 17454 inputs: []inputInfo{ 17455 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17456 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17457 }, 17458 }, 17459 }, 17460 { 17461 name: "MOVDstorezeroidx", 17462 argLen: 3, 17463 asm: arm64.AMOVD, 17464 reg: regInfo{ 17465 inputs: []inputInfo{ 17466 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17467 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17468 }, 17469 }, 17470 }, 17471 { 17472 name: "MOVHstorezeroidx2", 17473 argLen: 3, 17474 asm: arm64.AMOVH, 17475 reg: regInfo{ 17476 inputs: []inputInfo{ 17477 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17478 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17479 }, 17480 }, 17481 }, 17482 { 17483 name: "MOVWstorezeroidx4", 17484 argLen: 3, 17485 asm: arm64.AMOVW, 17486 reg: regInfo{ 17487 inputs: []inputInfo{ 17488 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17489 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17490 }, 17491 }, 17492 }, 17493 { 17494 name: "MOVDstorezeroidx8", 17495 argLen: 3, 17496 asm: arm64.AMOVD, 17497 reg: regInfo{ 17498 inputs: []inputInfo{ 17499 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17500 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 17501 }, 17502 }, 17503 }, 17504 { 17505 name: "FMOVDgpfp", 17506 argLen: 1, 17507 asm: arm64.AFMOVD, 17508 reg: regInfo{ 17509 inputs: []inputInfo{ 17510 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17511 }, 17512 outputs: []outputInfo{ 17513 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17514 }, 17515 }, 17516 }, 17517 { 17518 name: "FMOVDfpgp", 17519 argLen: 1, 17520 asm: arm64.AFMOVD, 17521 reg: regInfo{ 17522 inputs: []inputInfo{ 17523 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17524 }, 17525 outputs: []outputInfo{ 17526 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17527 }, 17528 }, 17529 }, 17530 { 17531 name: "FMOVSgpfp", 17532 argLen: 1, 17533 asm: arm64.AFMOVS, 17534 reg: regInfo{ 17535 inputs: []inputInfo{ 17536 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17537 }, 17538 outputs: []outputInfo{ 17539 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17540 }, 17541 }, 17542 }, 17543 { 17544 name: "FMOVSfpgp", 17545 argLen: 1, 17546 asm: arm64.AFMOVS, 17547 reg: regInfo{ 17548 inputs: []inputInfo{ 17549 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17550 }, 17551 outputs: []outputInfo{ 17552 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17553 }, 17554 }, 17555 }, 17556 { 17557 name: "MOVBreg", 17558 argLen: 1, 17559 asm: arm64.AMOVB, 17560 reg: regInfo{ 17561 inputs: []inputInfo{ 17562 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17563 }, 17564 outputs: []outputInfo{ 17565 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17566 }, 17567 }, 17568 }, 17569 { 17570 name: "MOVBUreg", 17571 argLen: 1, 17572 asm: arm64.AMOVBU, 17573 reg: regInfo{ 17574 inputs: []inputInfo{ 17575 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17576 }, 17577 outputs: []outputInfo{ 17578 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17579 }, 17580 }, 17581 }, 17582 { 17583 name: "MOVHreg", 17584 argLen: 1, 17585 asm: arm64.AMOVH, 17586 reg: regInfo{ 17587 inputs: []inputInfo{ 17588 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17589 }, 17590 outputs: []outputInfo{ 17591 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17592 }, 17593 }, 17594 }, 17595 { 17596 name: "MOVHUreg", 17597 argLen: 1, 17598 asm: arm64.AMOVHU, 17599 reg: regInfo{ 17600 inputs: []inputInfo{ 17601 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17602 }, 17603 outputs: []outputInfo{ 17604 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17605 }, 17606 }, 17607 }, 17608 { 17609 name: "MOVWreg", 17610 argLen: 1, 17611 asm: arm64.AMOVW, 17612 reg: regInfo{ 17613 inputs: []inputInfo{ 17614 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17615 }, 17616 outputs: []outputInfo{ 17617 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17618 }, 17619 }, 17620 }, 17621 { 17622 name: "MOVWUreg", 17623 argLen: 1, 17624 asm: arm64.AMOVWU, 17625 reg: regInfo{ 17626 inputs: []inputInfo{ 17627 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17628 }, 17629 outputs: []outputInfo{ 17630 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17631 }, 17632 }, 17633 }, 17634 { 17635 name: "MOVDreg", 17636 argLen: 1, 17637 asm: arm64.AMOVD, 17638 reg: regInfo{ 17639 inputs: []inputInfo{ 17640 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17641 }, 17642 outputs: []outputInfo{ 17643 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17644 }, 17645 }, 17646 }, 17647 { 17648 name: "MOVDnop", 17649 argLen: 1, 17650 resultInArg0: true, 17651 reg: regInfo{ 17652 inputs: []inputInfo{ 17653 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17654 }, 17655 outputs: []outputInfo{ 17656 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17657 }, 17658 }, 17659 }, 17660 { 17661 name: "SCVTFWS", 17662 argLen: 1, 17663 asm: arm64.ASCVTFWS, 17664 reg: regInfo{ 17665 inputs: []inputInfo{ 17666 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17667 }, 17668 outputs: []outputInfo{ 17669 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17670 }, 17671 }, 17672 }, 17673 { 17674 name: "SCVTFWD", 17675 argLen: 1, 17676 asm: arm64.ASCVTFWD, 17677 reg: regInfo{ 17678 inputs: []inputInfo{ 17679 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17680 }, 17681 outputs: []outputInfo{ 17682 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17683 }, 17684 }, 17685 }, 17686 { 17687 name: "UCVTFWS", 17688 argLen: 1, 17689 asm: arm64.AUCVTFWS, 17690 reg: regInfo{ 17691 inputs: []inputInfo{ 17692 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17693 }, 17694 outputs: []outputInfo{ 17695 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17696 }, 17697 }, 17698 }, 17699 { 17700 name: "UCVTFWD", 17701 argLen: 1, 17702 asm: arm64.AUCVTFWD, 17703 reg: regInfo{ 17704 inputs: []inputInfo{ 17705 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17706 }, 17707 outputs: []outputInfo{ 17708 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17709 }, 17710 }, 17711 }, 17712 { 17713 name: "SCVTFS", 17714 argLen: 1, 17715 asm: arm64.ASCVTFS, 17716 reg: regInfo{ 17717 inputs: []inputInfo{ 17718 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17719 }, 17720 outputs: []outputInfo{ 17721 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17722 }, 17723 }, 17724 }, 17725 { 17726 name: "SCVTFD", 17727 argLen: 1, 17728 asm: arm64.ASCVTFD, 17729 reg: regInfo{ 17730 inputs: []inputInfo{ 17731 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17732 }, 17733 outputs: []outputInfo{ 17734 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17735 }, 17736 }, 17737 }, 17738 { 17739 name: "UCVTFS", 17740 argLen: 1, 17741 asm: arm64.AUCVTFS, 17742 reg: regInfo{ 17743 inputs: []inputInfo{ 17744 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17745 }, 17746 outputs: []outputInfo{ 17747 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17748 }, 17749 }, 17750 }, 17751 { 17752 name: "UCVTFD", 17753 argLen: 1, 17754 asm: arm64.AUCVTFD, 17755 reg: regInfo{ 17756 inputs: []inputInfo{ 17757 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17758 }, 17759 outputs: []outputInfo{ 17760 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17761 }, 17762 }, 17763 }, 17764 { 17765 name: "FCVTZSSW", 17766 argLen: 1, 17767 asm: arm64.AFCVTZSSW, 17768 reg: regInfo{ 17769 inputs: []inputInfo{ 17770 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17771 }, 17772 outputs: []outputInfo{ 17773 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17774 }, 17775 }, 17776 }, 17777 { 17778 name: "FCVTZSDW", 17779 argLen: 1, 17780 asm: arm64.AFCVTZSDW, 17781 reg: regInfo{ 17782 inputs: []inputInfo{ 17783 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17784 }, 17785 outputs: []outputInfo{ 17786 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17787 }, 17788 }, 17789 }, 17790 { 17791 name: "FCVTZUSW", 17792 argLen: 1, 17793 asm: arm64.AFCVTZUSW, 17794 reg: regInfo{ 17795 inputs: []inputInfo{ 17796 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17797 }, 17798 outputs: []outputInfo{ 17799 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17800 }, 17801 }, 17802 }, 17803 { 17804 name: "FCVTZUDW", 17805 argLen: 1, 17806 asm: arm64.AFCVTZUDW, 17807 reg: regInfo{ 17808 inputs: []inputInfo{ 17809 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17810 }, 17811 outputs: []outputInfo{ 17812 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17813 }, 17814 }, 17815 }, 17816 { 17817 name: "FCVTZSS", 17818 argLen: 1, 17819 asm: arm64.AFCVTZSS, 17820 reg: regInfo{ 17821 inputs: []inputInfo{ 17822 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17823 }, 17824 outputs: []outputInfo{ 17825 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17826 }, 17827 }, 17828 }, 17829 { 17830 name: "FCVTZSD", 17831 argLen: 1, 17832 asm: arm64.AFCVTZSD, 17833 reg: regInfo{ 17834 inputs: []inputInfo{ 17835 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17836 }, 17837 outputs: []outputInfo{ 17838 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17839 }, 17840 }, 17841 }, 17842 { 17843 name: "FCVTZUS", 17844 argLen: 1, 17845 asm: arm64.AFCVTZUS, 17846 reg: regInfo{ 17847 inputs: []inputInfo{ 17848 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17849 }, 17850 outputs: []outputInfo{ 17851 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17852 }, 17853 }, 17854 }, 17855 { 17856 name: "FCVTZUD", 17857 argLen: 1, 17858 asm: arm64.AFCVTZUD, 17859 reg: regInfo{ 17860 inputs: []inputInfo{ 17861 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17862 }, 17863 outputs: []outputInfo{ 17864 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17865 }, 17866 }, 17867 }, 17868 { 17869 name: "FCVTSD", 17870 argLen: 1, 17871 asm: arm64.AFCVTSD, 17872 reg: regInfo{ 17873 inputs: []inputInfo{ 17874 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17875 }, 17876 outputs: []outputInfo{ 17877 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17878 }, 17879 }, 17880 }, 17881 { 17882 name: "FCVTDS", 17883 argLen: 1, 17884 asm: arm64.AFCVTDS, 17885 reg: regInfo{ 17886 inputs: []inputInfo{ 17887 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17888 }, 17889 outputs: []outputInfo{ 17890 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17891 }, 17892 }, 17893 }, 17894 { 17895 name: "FRINTAD", 17896 argLen: 1, 17897 asm: arm64.AFRINTAD, 17898 reg: regInfo{ 17899 inputs: []inputInfo{ 17900 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17901 }, 17902 outputs: []outputInfo{ 17903 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17904 }, 17905 }, 17906 }, 17907 { 17908 name: "FRINTMD", 17909 argLen: 1, 17910 asm: arm64.AFRINTMD, 17911 reg: regInfo{ 17912 inputs: []inputInfo{ 17913 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17914 }, 17915 outputs: []outputInfo{ 17916 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17917 }, 17918 }, 17919 }, 17920 { 17921 name: "FRINTND", 17922 argLen: 1, 17923 asm: arm64.AFRINTND, 17924 reg: regInfo{ 17925 inputs: []inputInfo{ 17926 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17927 }, 17928 outputs: []outputInfo{ 17929 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17930 }, 17931 }, 17932 }, 17933 { 17934 name: "FRINTPD", 17935 argLen: 1, 17936 asm: arm64.AFRINTPD, 17937 reg: regInfo{ 17938 inputs: []inputInfo{ 17939 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17940 }, 17941 outputs: []outputInfo{ 17942 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17943 }, 17944 }, 17945 }, 17946 { 17947 name: "FRINTZD", 17948 argLen: 1, 17949 asm: arm64.AFRINTZD, 17950 reg: regInfo{ 17951 inputs: []inputInfo{ 17952 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17953 }, 17954 outputs: []outputInfo{ 17955 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17956 }, 17957 }, 17958 }, 17959 { 17960 name: "CSEL", 17961 auxType: auxCCop, 17962 argLen: 3, 17963 asm: arm64.ACSEL, 17964 reg: regInfo{ 17965 inputs: []inputInfo{ 17966 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17967 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17968 }, 17969 outputs: []outputInfo{ 17970 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17971 }, 17972 }, 17973 }, 17974 { 17975 name: "CSEL0", 17976 auxType: auxCCop, 17977 argLen: 2, 17978 asm: arm64.ACSEL, 17979 reg: regInfo{ 17980 inputs: []inputInfo{ 17981 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 17982 }, 17983 outputs: []outputInfo{ 17984 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 17985 }, 17986 }, 17987 }, 17988 { 17989 name: "CALLstatic", 17990 auxType: auxSymOff, 17991 argLen: 1, 17992 clobberFlags: true, 17993 call: true, 17994 symEffect: SymNone, 17995 reg: regInfo{ 17996 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17997 }, 17998 }, 17999 { 18000 name: "CALLclosure", 18001 auxType: auxInt64, 18002 argLen: 3, 18003 clobberFlags: true, 18004 call: true, 18005 reg: regInfo{ 18006 inputs: []inputInfo{ 18007 {1, 67108864}, // R26 18008 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 18009 }, 18010 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18011 }, 18012 }, 18013 { 18014 name: "CALLinter", 18015 auxType: auxInt64, 18016 argLen: 2, 18017 clobberFlags: true, 18018 call: true, 18019 reg: regInfo{ 18020 inputs: []inputInfo{ 18021 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18022 }, 18023 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18024 }, 18025 }, 18026 { 18027 name: "LoweredNilCheck", 18028 argLen: 2, 18029 nilCheck: true, 18030 faultOnNilArg0: true, 18031 reg: regInfo{ 18032 inputs: []inputInfo{ 18033 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18034 }, 18035 }, 18036 }, 18037 { 18038 name: "Equal", 18039 argLen: 1, 18040 reg: regInfo{ 18041 outputs: []outputInfo{ 18042 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18043 }, 18044 }, 18045 }, 18046 { 18047 name: "NotEqual", 18048 argLen: 1, 18049 reg: regInfo{ 18050 outputs: []outputInfo{ 18051 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18052 }, 18053 }, 18054 }, 18055 { 18056 name: "LessThan", 18057 argLen: 1, 18058 reg: regInfo{ 18059 outputs: []outputInfo{ 18060 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18061 }, 18062 }, 18063 }, 18064 { 18065 name: "LessEqual", 18066 argLen: 1, 18067 reg: regInfo{ 18068 outputs: []outputInfo{ 18069 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18070 }, 18071 }, 18072 }, 18073 { 18074 name: "GreaterThan", 18075 argLen: 1, 18076 reg: regInfo{ 18077 outputs: []outputInfo{ 18078 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18079 }, 18080 }, 18081 }, 18082 { 18083 name: "GreaterEqual", 18084 argLen: 1, 18085 reg: regInfo{ 18086 outputs: []outputInfo{ 18087 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18088 }, 18089 }, 18090 }, 18091 { 18092 name: "LessThanU", 18093 argLen: 1, 18094 reg: regInfo{ 18095 outputs: []outputInfo{ 18096 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18097 }, 18098 }, 18099 }, 18100 { 18101 name: "LessEqualU", 18102 argLen: 1, 18103 reg: regInfo{ 18104 outputs: []outputInfo{ 18105 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18106 }, 18107 }, 18108 }, 18109 { 18110 name: "GreaterThanU", 18111 argLen: 1, 18112 reg: regInfo{ 18113 outputs: []outputInfo{ 18114 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18115 }, 18116 }, 18117 }, 18118 { 18119 name: "GreaterEqualU", 18120 argLen: 1, 18121 reg: regInfo{ 18122 outputs: []outputInfo{ 18123 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18124 }, 18125 }, 18126 }, 18127 { 18128 name: "DUFFZERO", 18129 auxType: auxInt64, 18130 argLen: 2, 18131 faultOnNilArg0: true, 18132 reg: regInfo{ 18133 inputs: []inputInfo{ 18134 {0, 65536}, // R16 18135 }, 18136 clobbers: 536936448, // R16 R30 18137 }, 18138 }, 18139 { 18140 name: "LoweredZero", 18141 argLen: 3, 18142 clobberFlags: true, 18143 faultOnNilArg0: true, 18144 reg: regInfo{ 18145 inputs: []inputInfo{ 18146 {0, 65536}, // R16 18147 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18148 }, 18149 clobbers: 65536, // R16 18150 }, 18151 }, 18152 { 18153 name: "DUFFCOPY", 18154 auxType: auxInt64, 18155 argLen: 3, 18156 faultOnNilArg0: true, 18157 faultOnNilArg1: true, 18158 reg: regInfo{ 18159 inputs: []inputInfo{ 18160 {0, 131072}, // R17 18161 {1, 65536}, // R16 18162 }, 18163 clobbers: 604176384, // R16 R17 R26 R30 18164 }, 18165 }, 18166 { 18167 name: "LoweredMove", 18168 argLen: 4, 18169 clobberFlags: true, 18170 faultOnNilArg0: true, 18171 faultOnNilArg1: true, 18172 reg: regInfo{ 18173 inputs: []inputInfo{ 18174 {0, 131072}, // R17 18175 {1, 65536}, // R16 18176 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18177 }, 18178 clobbers: 196608, // R16 R17 18179 }, 18180 }, 18181 { 18182 name: "LoweredGetClosurePtr", 18183 argLen: 0, 18184 zeroWidth: true, 18185 reg: regInfo{ 18186 outputs: []outputInfo{ 18187 {0, 67108864}, // R26 18188 }, 18189 }, 18190 }, 18191 { 18192 name: "LoweredGetCallerSP", 18193 argLen: 0, 18194 rematerializeable: true, 18195 reg: regInfo{ 18196 outputs: []outputInfo{ 18197 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18198 }, 18199 }, 18200 }, 18201 { 18202 name: "LoweredGetCallerPC", 18203 argLen: 0, 18204 rematerializeable: true, 18205 reg: regInfo{ 18206 outputs: []outputInfo{ 18207 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18208 }, 18209 }, 18210 }, 18211 { 18212 name: "FlagEQ", 18213 argLen: 0, 18214 reg: regInfo{}, 18215 }, 18216 { 18217 name: "FlagLT_ULT", 18218 argLen: 0, 18219 reg: regInfo{}, 18220 }, 18221 { 18222 name: "FlagLT_UGT", 18223 argLen: 0, 18224 reg: regInfo{}, 18225 }, 18226 { 18227 name: "FlagGT_UGT", 18228 argLen: 0, 18229 reg: regInfo{}, 18230 }, 18231 { 18232 name: "FlagGT_ULT", 18233 argLen: 0, 18234 reg: regInfo{}, 18235 }, 18236 { 18237 name: "InvertFlags", 18238 argLen: 1, 18239 reg: regInfo{}, 18240 }, 18241 { 18242 name: "LDAR", 18243 argLen: 2, 18244 faultOnNilArg0: true, 18245 asm: arm64.ALDAR, 18246 reg: regInfo{ 18247 inputs: []inputInfo{ 18248 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18249 }, 18250 outputs: []outputInfo{ 18251 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18252 }, 18253 }, 18254 }, 18255 { 18256 name: "LDARW", 18257 argLen: 2, 18258 faultOnNilArg0: true, 18259 asm: arm64.ALDARW, 18260 reg: regInfo{ 18261 inputs: []inputInfo{ 18262 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18263 }, 18264 outputs: []outputInfo{ 18265 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18266 }, 18267 }, 18268 }, 18269 { 18270 name: "STLR", 18271 argLen: 3, 18272 faultOnNilArg0: true, 18273 hasSideEffects: true, 18274 asm: arm64.ASTLR, 18275 reg: regInfo{ 18276 inputs: []inputInfo{ 18277 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18278 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18279 }, 18280 }, 18281 }, 18282 { 18283 name: "STLRW", 18284 argLen: 3, 18285 faultOnNilArg0: true, 18286 hasSideEffects: true, 18287 asm: arm64.ASTLRW, 18288 reg: regInfo{ 18289 inputs: []inputInfo{ 18290 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18291 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18292 }, 18293 }, 18294 }, 18295 { 18296 name: "LoweredAtomicExchange64", 18297 argLen: 3, 18298 resultNotInArgs: true, 18299 faultOnNilArg0: true, 18300 hasSideEffects: true, 18301 reg: regInfo{ 18302 inputs: []inputInfo{ 18303 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18304 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18305 }, 18306 outputs: []outputInfo{ 18307 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18308 }, 18309 }, 18310 }, 18311 { 18312 name: "LoweredAtomicExchange32", 18313 argLen: 3, 18314 resultNotInArgs: true, 18315 faultOnNilArg0: true, 18316 hasSideEffects: true, 18317 reg: regInfo{ 18318 inputs: []inputInfo{ 18319 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18320 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18321 }, 18322 outputs: []outputInfo{ 18323 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18324 }, 18325 }, 18326 }, 18327 { 18328 name: "LoweredAtomicAdd64", 18329 argLen: 3, 18330 resultNotInArgs: true, 18331 faultOnNilArg0: true, 18332 hasSideEffects: true, 18333 reg: regInfo{ 18334 inputs: []inputInfo{ 18335 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18336 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18337 }, 18338 outputs: []outputInfo{ 18339 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18340 }, 18341 }, 18342 }, 18343 { 18344 name: "LoweredAtomicAdd32", 18345 argLen: 3, 18346 resultNotInArgs: true, 18347 faultOnNilArg0: true, 18348 hasSideEffects: true, 18349 reg: regInfo{ 18350 inputs: []inputInfo{ 18351 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18352 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18353 }, 18354 outputs: []outputInfo{ 18355 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18356 }, 18357 }, 18358 }, 18359 { 18360 name: "LoweredAtomicAdd64Variant", 18361 argLen: 3, 18362 resultNotInArgs: true, 18363 faultOnNilArg0: true, 18364 hasSideEffects: true, 18365 reg: regInfo{ 18366 inputs: []inputInfo{ 18367 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18368 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18369 }, 18370 outputs: []outputInfo{ 18371 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18372 }, 18373 }, 18374 }, 18375 { 18376 name: "LoweredAtomicAdd32Variant", 18377 argLen: 3, 18378 resultNotInArgs: true, 18379 faultOnNilArg0: true, 18380 hasSideEffects: true, 18381 reg: regInfo{ 18382 inputs: []inputInfo{ 18383 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18384 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18385 }, 18386 outputs: []outputInfo{ 18387 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18388 }, 18389 }, 18390 }, 18391 { 18392 name: "LoweredAtomicCas64", 18393 argLen: 4, 18394 resultNotInArgs: true, 18395 clobberFlags: true, 18396 faultOnNilArg0: true, 18397 hasSideEffects: true, 18398 reg: regInfo{ 18399 inputs: []inputInfo{ 18400 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18401 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18402 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18403 }, 18404 outputs: []outputInfo{ 18405 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18406 }, 18407 }, 18408 }, 18409 { 18410 name: "LoweredAtomicCas32", 18411 argLen: 4, 18412 resultNotInArgs: true, 18413 clobberFlags: true, 18414 faultOnNilArg0: true, 18415 hasSideEffects: true, 18416 reg: regInfo{ 18417 inputs: []inputInfo{ 18418 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18419 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18420 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18421 }, 18422 outputs: []outputInfo{ 18423 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18424 }, 18425 }, 18426 }, 18427 { 18428 name: "LoweredAtomicAnd8", 18429 argLen: 3, 18430 resultNotInArgs: true, 18431 faultOnNilArg0: true, 18432 hasSideEffects: true, 18433 asm: arm64.AAND, 18434 reg: regInfo{ 18435 inputs: []inputInfo{ 18436 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18437 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18438 }, 18439 outputs: []outputInfo{ 18440 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18441 }, 18442 }, 18443 }, 18444 { 18445 name: "LoweredAtomicOr8", 18446 argLen: 3, 18447 resultNotInArgs: true, 18448 faultOnNilArg0: true, 18449 hasSideEffects: true, 18450 asm: arm64.AORR, 18451 reg: regInfo{ 18452 inputs: []inputInfo{ 18453 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18454 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 18455 }, 18456 outputs: []outputInfo{ 18457 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18458 }, 18459 }, 18460 }, 18461 { 18462 name: "LoweredWB", 18463 auxType: auxSym, 18464 argLen: 3, 18465 clobberFlags: true, 18466 symEffect: SymNone, 18467 reg: regInfo{ 18468 inputs: []inputInfo{ 18469 {0, 4}, // R2 18470 {1, 8}, // R3 18471 }, 18472 clobbers: 9223372035244163072, // R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18473 }, 18474 }, 18475 18476 { 18477 name: "ADD", 18478 argLen: 2, 18479 commutative: true, 18480 asm: mips.AADDU, 18481 reg: regInfo{ 18482 inputs: []inputInfo{ 18483 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18484 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18485 }, 18486 outputs: []outputInfo{ 18487 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18488 }, 18489 }, 18490 }, 18491 { 18492 name: "ADDconst", 18493 auxType: auxInt32, 18494 argLen: 1, 18495 asm: mips.AADDU, 18496 reg: regInfo{ 18497 inputs: []inputInfo{ 18498 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 18499 }, 18500 outputs: []outputInfo{ 18501 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18502 }, 18503 }, 18504 }, 18505 { 18506 name: "SUB", 18507 argLen: 2, 18508 asm: mips.ASUBU, 18509 reg: regInfo{ 18510 inputs: []inputInfo{ 18511 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18512 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18513 }, 18514 outputs: []outputInfo{ 18515 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18516 }, 18517 }, 18518 }, 18519 { 18520 name: "SUBconst", 18521 auxType: auxInt32, 18522 argLen: 1, 18523 asm: mips.ASUBU, 18524 reg: regInfo{ 18525 inputs: []inputInfo{ 18526 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18527 }, 18528 outputs: []outputInfo{ 18529 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18530 }, 18531 }, 18532 }, 18533 { 18534 name: "MUL", 18535 argLen: 2, 18536 commutative: true, 18537 asm: mips.AMUL, 18538 reg: regInfo{ 18539 inputs: []inputInfo{ 18540 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18541 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18542 }, 18543 clobbers: 105553116266496, // HI LO 18544 outputs: []outputInfo{ 18545 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18546 }, 18547 }, 18548 }, 18549 { 18550 name: "MULT", 18551 argLen: 2, 18552 commutative: true, 18553 asm: mips.AMUL, 18554 reg: regInfo{ 18555 inputs: []inputInfo{ 18556 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18557 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18558 }, 18559 outputs: []outputInfo{ 18560 {0, 35184372088832}, // HI 18561 {1, 70368744177664}, // LO 18562 }, 18563 }, 18564 }, 18565 { 18566 name: "MULTU", 18567 argLen: 2, 18568 commutative: true, 18569 asm: mips.AMULU, 18570 reg: regInfo{ 18571 inputs: []inputInfo{ 18572 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18573 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18574 }, 18575 outputs: []outputInfo{ 18576 {0, 35184372088832}, // HI 18577 {1, 70368744177664}, // LO 18578 }, 18579 }, 18580 }, 18581 { 18582 name: "DIV", 18583 argLen: 2, 18584 asm: mips.ADIV, 18585 reg: regInfo{ 18586 inputs: []inputInfo{ 18587 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18588 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18589 }, 18590 outputs: []outputInfo{ 18591 {0, 35184372088832}, // HI 18592 {1, 70368744177664}, // LO 18593 }, 18594 }, 18595 }, 18596 { 18597 name: "DIVU", 18598 argLen: 2, 18599 asm: mips.ADIVU, 18600 reg: regInfo{ 18601 inputs: []inputInfo{ 18602 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18603 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18604 }, 18605 outputs: []outputInfo{ 18606 {0, 35184372088832}, // HI 18607 {1, 70368744177664}, // LO 18608 }, 18609 }, 18610 }, 18611 { 18612 name: "ADDF", 18613 argLen: 2, 18614 commutative: true, 18615 asm: mips.AADDF, 18616 reg: regInfo{ 18617 inputs: []inputInfo{ 18618 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18619 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18620 }, 18621 outputs: []outputInfo{ 18622 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18623 }, 18624 }, 18625 }, 18626 { 18627 name: "ADDD", 18628 argLen: 2, 18629 commutative: true, 18630 asm: mips.AADDD, 18631 reg: regInfo{ 18632 inputs: []inputInfo{ 18633 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18634 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18635 }, 18636 outputs: []outputInfo{ 18637 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18638 }, 18639 }, 18640 }, 18641 { 18642 name: "SUBF", 18643 argLen: 2, 18644 asm: mips.ASUBF, 18645 reg: regInfo{ 18646 inputs: []inputInfo{ 18647 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18648 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18649 }, 18650 outputs: []outputInfo{ 18651 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18652 }, 18653 }, 18654 }, 18655 { 18656 name: "SUBD", 18657 argLen: 2, 18658 asm: mips.ASUBD, 18659 reg: regInfo{ 18660 inputs: []inputInfo{ 18661 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18662 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18663 }, 18664 outputs: []outputInfo{ 18665 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18666 }, 18667 }, 18668 }, 18669 { 18670 name: "MULF", 18671 argLen: 2, 18672 commutative: true, 18673 asm: mips.AMULF, 18674 reg: regInfo{ 18675 inputs: []inputInfo{ 18676 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18677 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18678 }, 18679 outputs: []outputInfo{ 18680 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18681 }, 18682 }, 18683 }, 18684 { 18685 name: "MULD", 18686 argLen: 2, 18687 commutative: true, 18688 asm: mips.AMULD, 18689 reg: regInfo{ 18690 inputs: []inputInfo{ 18691 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18692 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18693 }, 18694 outputs: []outputInfo{ 18695 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18696 }, 18697 }, 18698 }, 18699 { 18700 name: "DIVF", 18701 argLen: 2, 18702 asm: mips.ADIVF, 18703 reg: regInfo{ 18704 inputs: []inputInfo{ 18705 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18706 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18707 }, 18708 outputs: []outputInfo{ 18709 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18710 }, 18711 }, 18712 }, 18713 { 18714 name: "DIVD", 18715 argLen: 2, 18716 asm: mips.ADIVD, 18717 reg: regInfo{ 18718 inputs: []inputInfo{ 18719 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18720 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18721 }, 18722 outputs: []outputInfo{ 18723 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18724 }, 18725 }, 18726 }, 18727 { 18728 name: "AND", 18729 argLen: 2, 18730 commutative: true, 18731 asm: mips.AAND, 18732 reg: regInfo{ 18733 inputs: []inputInfo{ 18734 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18735 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18736 }, 18737 outputs: []outputInfo{ 18738 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18739 }, 18740 }, 18741 }, 18742 { 18743 name: "ANDconst", 18744 auxType: auxInt32, 18745 argLen: 1, 18746 asm: mips.AAND, 18747 reg: regInfo{ 18748 inputs: []inputInfo{ 18749 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18750 }, 18751 outputs: []outputInfo{ 18752 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18753 }, 18754 }, 18755 }, 18756 { 18757 name: "OR", 18758 argLen: 2, 18759 commutative: true, 18760 asm: mips.AOR, 18761 reg: regInfo{ 18762 inputs: []inputInfo{ 18763 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18764 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18765 }, 18766 outputs: []outputInfo{ 18767 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18768 }, 18769 }, 18770 }, 18771 { 18772 name: "ORconst", 18773 auxType: auxInt32, 18774 argLen: 1, 18775 asm: mips.AOR, 18776 reg: regInfo{ 18777 inputs: []inputInfo{ 18778 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18779 }, 18780 outputs: []outputInfo{ 18781 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18782 }, 18783 }, 18784 }, 18785 { 18786 name: "XOR", 18787 argLen: 2, 18788 commutative: true, 18789 asm: mips.AXOR, 18790 reg: regInfo{ 18791 inputs: []inputInfo{ 18792 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18793 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18794 }, 18795 outputs: []outputInfo{ 18796 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18797 }, 18798 }, 18799 }, 18800 { 18801 name: "XORconst", 18802 auxType: auxInt32, 18803 argLen: 1, 18804 asm: mips.AXOR, 18805 reg: regInfo{ 18806 inputs: []inputInfo{ 18807 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18808 }, 18809 outputs: []outputInfo{ 18810 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18811 }, 18812 }, 18813 }, 18814 { 18815 name: "NOR", 18816 argLen: 2, 18817 commutative: true, 18818 asm: mips.ANOR, 18819 reg: regInfo{ 18820 inputs: []inputInfo{ 18821 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18822 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18823 }, 18824 outputs: []outputInfo{ 18825 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18826 }, 18827 }, 18828 }, 18829 { 18830 name: "NORconst", 18831 auxType: auxInt32, 18832 argLen: 1, 18833 asm: mips.ANOR, 18834 reg: regInfo{ 18835 inputs: []inputInfo{ 18836 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18837 }, 18838 outputs: []outputInfo{ 18839 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18840 }, 18841 }, 18842 }, 18843 { 18844 name: "NEG", 18845 argLen: 1, 18846 reg: regInfo{ 18847 inputs: []inputInfo{ 18848 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18849 }, 18850 outputs: []outputInfo{ 18851 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18852 }, 18853 }, 18854 }, 18855 { 18856 name: "NEGF", 18857 argLen: 1, 18858 asm: mips.ANEGF, 18859 reg: regInfo{ 18860 inputs: []inputInfo{ 18861 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18862 }, 18863 outputs: []outputInfo{ 18864 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18865 }, 18866 }, 18867 }, 18868 { 18869 name: "NEGD", 18870 argLen: 1, 18871 asm: mips.ANEGD, 18872 reg: regInfo{ 18873 inputs: []inputInfo{ 18874 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18875 }, 18876 outputs: []outputInfo{ 18877 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18878 }, 18879 }, 18880 }, 18881 { 18882 name: "SQRTD", 18883 argLen: 1, 18884 asm: mips.ASQRTD, 18885 reg: regInfo{ 18886 inputs: []inputInfo{ 18887 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18888 }, 18889 outputs: []outputInfo{ 18890 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 18891 }, 18892 }, 18893 }, 18894 { 18895 name: "SLL", 18896 argLen: 2, 18897 asm: mips.ASLL, 18898 reg: regInfo{ 18899 inputs: []inputInfo{ 18900 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18901 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18902 }, 18903 outputs: []outputInfo{ 18904 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18905 }, 18906 }, 18907 }, 18908 { 18909 name: "SLLconst", 18910 auxType: auxInt32, 18911 argLen: 1, 18912 asm: mips.ASLL, 18913 reg: regInfo{ 18914 inputs: []inputInfo{ 18915 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18916 }, 18917 outputs: []outputInfo{ 18918 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18919 }, 18920 }, 18921 }, 18922 { 18923 name: "SRL", 18924 argLen: 2, 18925 asm: mips.ASRL, 18926 reg: regInfo{ 18927 inputs: []inputInfo{ 18928 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18929 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18930 }, 18931 outputs: []outputInfo{ 18932 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18933 }, 18934 }, 18935 }, 18936 { 18937 name: "SRLconst", 18938 auxType: auxInt32, 18939 argLen: 1, 18940 asm: mips.ASRL, 18941 reg: regInfo{ 18942 inputs: []inputInfo{ 18943 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18944 }, 18945 outputs: []outputInfo{ 18946 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18947 }, 18948 }, 18949 }, 18950 { 18951 name: "SRA", 18952 argLen: 2, 18953 asm: mips.ASRA, 18954 reg: regInfo{ 18955 inputs: []inputInfo{ 18956 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18957 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18958 }, 18959 outputs: []outputInfo{ 18960 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18961 }, 18962 }, 18963 }, 18964 { 18965 name: "SRAconst", 18966 auxType: auxInt32, 18967 argLen: 1, 18968 asm: mips.ASRA, 18969 reg: regInfo{ 18970 inputs: []inputInfo{ 18971 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18972 }, 18973 outputs: []outputInfo{ 18974 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18975 }, 18976 }, 18977 }, 18978 { 18979 name: "CLZ", 18980 argLen: 1, 18981 asm: mips.ACLZ, 18982 reg: regInfo{ 18983 inputs: []inputInfo{ 18984 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18985 }, 18986 outputs: []outputInfo{ 18987 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 18988 }, 18989 }, 18990 }, 18991 { 18992 name: "SGT", 18993 argLen: 2, 18994 asm: mips.ASGT, 18995 reg: regInfo{ 18996 inputs: []inputInfo{ 18997 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18998 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 18999 }, 19000 outputs: []outputInfo{ 19001 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19002 }, 19003 }, 19004 }, 19005 { 19006 name: "SGTconst", 19007 auxType: auxInt32, 19008 argLen: 1, 19009 asm: mips.ASGT, 19010 reg: regInfo{ 19011 inputs: []inputInfo{ 19012 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19013 }, 19014 outputs: []outputInfo{ 19015 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19016 }, 19017 }, 19018 }, 19019 { 19020 name: "SGTzero", 19021 argLen: 1, 19022 asm: mips.ASGT, 19023 reg: regInfo{ 19024 inputs: []inputInfo{ 19025 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19026 }, 19027 outputs: []outputInfo{ 19028 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19029 }, 19030 }, 19031 }, 19032 { 19033 name: "SGTU", 19034 argLen: 2, 19035 asm: mips.ASGTU, 19036 reg: regInfo{ 19037 inputs: []inputInfo{ 19038 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19039 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19040 }, 19041 outputs: []outputInfo{ 19042 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19043 }, 19044 }, 19045 }, 19046 { 19047 name: "SGTUconst", 19048 auxType: auxInt32, 19049 argLen: 1, 19050 asm: mips.ASGTU, 19051 reg: regInfo{ 19052 inputs: []inputInfo{ 19053 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19054 }, 19055 outputs: []outputInfo{ 19056 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19057 }, 19058 }, 19059 }, 19060 { 19061 name: "SGTUzero", 19062 argLen: 1, 19063 asm: mips.ASGTU, 19064 reg: regInfo{ 19065 inputs: []inputInfo{ 19066 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19067 }, 19068 outputs: []outputInfo{ 19069 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19070 }, 19071 }, 19072 }, 19073 { 19074 name: "CMPEQF", 19075 argLen: 2, 19076 asm: mips.ACMPEQF, 19077 reg: regInfo{ 19078 inputs: []inputInfo{ 19079 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19080 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19081 }, 19082 }, 19083 }, 19084 { 19085 name: "CMPEQD", 19086 argLen: 2, 19087 asm: mips.ACMPEQD, 19088 reg: regInfo{ 19089 inputs: []inputInfo{ 19090 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19091 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19092 }, 19093 }, 19094 }, 19095 { 19096 name: "CMPGEF", 19097 argLen: 2, 19098 asm: mips.ACMPGEF, 19099 reg: regInfo{ 19100 inputs: []inputInfo{ 19101 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19102 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19103 }, 19104 }, 19105 }, 19106 { 19107 name: "CMPGED", 19108 argLen: 2, 19109 asm: mips.ACMPGED, 19110 reg: regInfo{ 19111 inputs: []inputInfo{ 19112 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19113 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19114 }, 19115 }, 19116 }, 19117 { 19118 name: "CMPGTF", 19119 argLen: 2, 19120 asm: mips.ACMPGTF, 19121 reg: regInfo{ 19122 inputs: []inputInfo{ 19123 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19124 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19125 }, 19126 }, 19127 }, 19128 { 19129 name: "CMPGTD", 19130 argLen: 2, 19131 asm: mips.ACMPGTD, 19132 reg: regInfo{ 19133 inputs: []inputInfo{ 19134 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19135 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19136 }, 19137 }, 19138 }, 19139 { 19140 name: "MOVWconst", 19141 auxType: auxInt32, 19142 argLen: 0, 19143 rematerializeable: true, 19144 asm: mips.AMOVW, 19145 reg: regInfo{ 19146 outputs: []outputInfo{ 19147 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19148 }, 19149 }, 19150 }, 19151 { 19152 name: "MOVFconst", 19153 auxType: auxFloat32, 19154 argLen: 0, 19155 rematerializeable: true, 19156 asm: mips.AMOVF, 19157 reg: regInfo{ 19158 outputs: []outputInfo{ 19159 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19160 }, 19161 }, 19162 }, 19163 { 19164 name: "MOVDconst", 19165 auxType: auxFloat64, 19166 argLen: 0, 19167 rematerializeable: true, 19168 asm: mips.AMOVD, 19169 reg: regInfo{ 19170 outputs: []outputInfo{ 19171 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19172 }, 19173 }, 19174 }, 19175 { 19176 name: "MOVWaddr", 19177 auxType: auxSymOff, 19178 argLen: 1, 19179 rematerializeable: true, 19180 symEffect: SymAddr, 19181 asm: mips.AMOVW, 19182 reg: regInfo{ 19183 inputs: []inputInfo{ 19184 {0, 140737555464192}, // SP SB 19185 }, 19186 outputs: []outputInfo{ 19187 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19188 }, 19189 }, 19190 }, 19191 { 19192 name: "MOVBload", 19193 auxType: auxSymOff, 19194 argLen: 2, 19195 faultOnNilArg0: true, 19196 symEffect: SymRead, 19197 asm: mips.AMOVB, 19198 reg: regInfo{ 19199 inputs: []inputInfo{ 19200 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19201 }, 19202 outputs: []outputInfo{ 19203 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19204 }, 19205 }, 19206 }, 19207 { 19208 name: "MOVBUload", 19209 auxType: auxSymOff, 19210 argLen: 2, 19211 faultOnNilArg0: true, 19212 symEffect: SymRead, 19213 asm: mips.AMOVBU, 19214 reg: regInfo{ 19215 inputs: []inputInfo{ 19216 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19217 }, 19218 outputs: []outputInfo{ 19219 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19220 }, 19221 }, 19222 }, 19223 { 19224 name: "MOVHload", 19225 auxType: auxSymOff, 19226 argLen: 2, 19227 faultOnNilArg0: true, 19228 symEffect: SymRead, 19229 asm: mips.AMOVH, 19230 reg: regInfo{ 19231 inputs: []inputInfo{ 19232 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19233 }, 19234 outputs: []outputInfo{ 19235 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19236 }, 19237 }, 19238 }, 19239 { 19240 name: "MOVHUload", 19241 auxType: auxSymOff, 19242 argLen: 2, 19243 faultOnNilArg0: true, 19244 symEffect: SymRead, 19245 asm: mips.AMOVHU, 19246 reg: regInfo{ 19247 inputs: []inputInfo{ 19248 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19249 }, 19250 outputs: []outputInfo{ 19251 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19252 }, 19253 }, 19254 }, 19255 { 19256 name: "MOVWload", 19257 auxType: auxSymOff, 19258 argLen: 2, 19259 faultOnNilArg0: true, 19260 symEffect: SymRead, 19261 asm: mips.AMOVW, 19262 reg: regInfo{ 19263 inputs: []inputInfo{ 19264 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19265 }, 19266 outputs: []outputInfo{ 19267 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19268 }, 19269 }, 19270 }, 19271 { 19272 name: "MOVFload", 19273 auxType: auxSymOff, 19274 argLen: 2, 19275 faultOnNilArg0: true, 19276 symEffect: SymRead, 19277 asm: mips.AMOVF, 19278 reg: regInfo{ 19279 inputs: []inputInfo{ 19280 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19281 }, 19282 outputs: []outputInfo{ 19283 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19284 }, 19285 }, 19286 }, 19287 { 19288 name: "MOVDload", 19289 auxType: auxSymOff, 19290 argLen: 2, 19291 faultOnNilArg0: true, 19292 symEffect: SymRead, 19293 asm: mips.AMOVD, 19294 reg: regInfo{ 19295 inputs: []inputInfo{ 19296 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19297 }, 19298 outputs: []outputInfo{ 19299 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19300 }, 19301 }, 19302 }, 19303 { 19304 name: "MOVBstore", 19305 auxType: auxSymOff, 19306 argLen: 3, 19307 faultOnNilArg0: true, 19308 symEffect: SymWrite, 19309 asm: mips.AMOVB, 19310 reg: regInfo{ 19311 inputs: []inputInfo{ 19312 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19313 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19314 }, 19315 }, 19316 }, 19317 { 19318 name: "MOVHstore", 19319 auxType: auxSymOff, 19320 argLen: 3, 19321 faultOnNilArg0: true, 19322 symEffect: SymWrite, 19323 asm: mips.AMOVH, 19324 reg: regInfo{ 19325 inputs: []inputInfo{ 19326 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19327 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19328 }, 19329 }, 19330 }, 19331 { 19332 name: "MOVWstore", 19333 auxType: auxSymOff, 19334 argLen: 3, 19335 faultOnNilArg0: true, 19336 symEffect: SymWrite, 19337 asm: mips.AMOVW, 19338 reg: regInfo{ 19339 inputs: []inputInfo{ 19340 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19341 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19342 }, 19343 }, 19344 }, 19345 { 19346 name: "MOVFstore", 19347 auxType: auxSymOff, 19348 argLen: 3, 19349 faultOnNilArg0: true, 19350 symEffect: SymWrite, 19351 asm: mips.AMOVF, 19352 reg: regInfo{ 19353 inputs: []inputInfo{ 19354 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19355 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19356 }, 19357 }, 19358 }, 19359 { 19360 name: "MOVDstore", 19361 auxType: auxSymOff, 19362 argLen: 3, 19363 faultOnNilArg0: true, 19364 symEffect: SymWrite, 19365 asm: mips.AMOVD, 19366 reg: regInfo{ 19367 inputs: []inputInfo{ 19368 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19369 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19370 }, 19371 }, 19372 }, 19373 { 19374 name: "MOVBstorezero", 19375 auxType: auxSymOff, 19376 argLen: 2, 19377 faultOnNilArg0: true, 19378 symEffect: SymWrite, 19379 asm: mips.AMOVB, 19380 reg: regInfo{ 19381 inputs: []inputInfo{ 19382 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19383 }, 19384 }, 19385 }, 19386 { 19387 name: "MOVHstorezero", 19388 auxType: auxSymOff, 19389 argLen: 2, 19390 faultOnNilArg0: true, 19391 symEffect: SymWrite, 19392 asm: mips.AMOVH, 19393 reg: regInfo{ 19394 inputs: []inputInfo{ 19395 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19396 }, 19397 }, 19398 }, 19399 { 19400 name: "MOVWstorezero", 19401 auxType: auxSymOff, 19402 argLen: 2, 19403 faultOnNilArg0: true, 19404 symEffect: SymWrite, 19405 asm: mips.AMOVW, 19406 reg: regInfo{ 19407 inputs: []inputInfo{ 19408 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19409 }, 19410 }, 19411 }, 19412 { 19413 name: "MOVBreg", 19414 argLen: 1, 19415 asm: mips.AMOVB, 19416 reg: regInfo{ 19417 inputs: []inputInfo{ 19418 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19419 }, 19420 outputs: []outputInfo{ 19421 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19422 }, 19423 }, 19424 }, 19425 { 19426 name: "MOVBUreg", 19427 argLen: 1, 19428 asm: mips.AMOVBU, 19429 reg: regInfo{ 19430 inputs: []inputInfo{ 19431 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19432 }, 19433 outputs: []outputInfo{ 19434 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19435 }, 19436 }, 19437 }, 19438 { 19439 name: "MOVHreg", 19440 argLen: 1, 19441 asm: mips.AMOVH, 19442 reg: regInfo{ 19443 inputs: []inputInfo{ 19444 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19445 }, 19446 outputs: []outputInfo{ 19447 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19448 }, 19449 }, 19450 }, 19451 { 19452 name: "MOVHUreg", 19453 argLen: 1, 19454 asm: mips.AMOVHU, 19455 reg: regInfo{ 19456 inputs: []inputInfo{ 19457 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19458 }, 19459 outputs: []outputInfo{ 19460 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19461 }, 19462 }, 19463 }, 19464 { 19465 name: "MOVWreg", 19466 argLen: 1, 19467 asm: mips.AMOVW, 19468 reg: regInfo{ 19469 inputs: []inputInfo{ 19470 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19471 }, 19472 outputs: []outputInfo{ 19473 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19474 }, 19475 }, 19476 }, 19477 { 19478 name: "MOVWnop", 19479 argLen: 1, 19480 resultInArg0: true, 19481 reg: regInfo{ 19482 inputs: []inputInfo{ 19483 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19484 }, 19485 outputs: []outputInfo{ 19486 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19487 }, 19488 }, 19489 }, 19490 { 19491 name: "CMOVZ", 19492 argLen: 3, 19493 resultInArg0: true, 19494 asm: mips.ACMOVZ, 19495 reg: regInfo{ 19496 inputs: []inputInfo{ 19497 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19498 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19499 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19500 }, 19501 outputs: []outputInfo{ 19502 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19503 }, 19504 }, 19505 }, 19506 { 19507 name: "CMOVZzero", 19508 argLen: 2, 19509 resultInArg0: true, 19510 asm: mips.ACMOVZ, 19511 reg: regInfo{ 19512 inputs: []inputInfo{ 19513 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19514 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19515 }, 19516 outputs: []outputInfo{ 19517 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19518 }, 19519 }, 19520 }, 19521 { 19522 name: "MOVWF", 19523 argLen: 1, 19524 asm: mips.AMOVWF, 19525 reg: regInfo{ 19526 inputs: []inputInfo{ 19527 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19528 }, 19529 outputs: []outputInfo{ 19530 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19531 }, 19532 }, 19533 }, 19534 { 19535 name: "MOVWD", 19536 argLen: 1, 19537 asm: mips.AMOVWD, 19538 reg: regInfo{ 19539 inputs: []inputInfo{ 19540 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19541 }, 19542 outputs: []outputInfo{ 19543 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19544 }, 19545 }, 19546 }, 19547 { 19548 name: "TRUNCFW", 19549 argLen: 1, 19550 asm: mips.ATRUNCFW, 19551 reg: regInfo{ 19552 inputs: []inputInfo{ 19553 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19554 }, 19555 outputs: []outputInfo{ 19556 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19557 }, 19558 }, 19559 }, 19560 { 19561 name: "TRUNCDW", 19562 argLen: 1, 19563 asm: mips.ATRUNCDW, 19564 reg: regInfo{ 19565 inputs: []inputInfo{ 19566 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19567 }, 19568 outputs: []outputInfo{ 19569 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19570 }, 19571 }, 19572 }, 19573 { 19574 name: "MOVFD", 19575 argLen: 1, 19576 asm: mips.AMOVFD, 19577 reg: regInfo{ 19578 inputs: []inputInfo{ 19579 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19580 }, 19581 outputs: []outputInfo{ 19582 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19583 }, 19584 }, 19585 }, 19586 { 19587 name: "MOVDF", 19588 argLen: 1, 19589 asm: mips.AMOVDF, 19590 reg: regInfo{ 19591 inputs: []inputInfo{ 19592 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19593 }, 19594 outputs: []outputInfo{ 19595 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 19596 }, 19597 }, 19598 }, 19599 { 19600 name: "CALLstatic", 19601 auxType: auxSymOff, 19602 argLen: 1, 19603 clobberFlags: true, 19604 call: true, 19605 symEffect: SymNone, 19606 reg: regInfo{ 19607 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 19608 }, 19609 }, 19610 { 19611 name: "CALLclosure", 19612 auxType: auxInt64, 19613 argLen: 3, 19614 clobberFlags: true, 19615 call: true, 19616 reg: regInfo{ 19617 inputs: []inputInfo{ 19618 {1, 4194304}, // R22 19619 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 19620 }, 19621 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 19622 }, 19623 }, 19624 { 19625 name: "CALLinter", 19626 auxType: auxInt64, 19627 argLen: 2, 19628 clobberFlags: true, 19629 call: true, 19630 reg: regInfo{ 19631 inputs: []inputInfo{ 19632 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19633 }, 19634 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 19635 }, 19636 }, 19637 { 19638 name: "LoweredAtomicLoad", 19639 argLen: 2, 19640 faultOnNilArg0: true, 19641 reg: regInfo{ 19642 inputs: []inputInfo{ 19643 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19644 }, 19645 outputs: []outputInfo{ 19646 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19647 }, 19648 }, 19649 }, 19650 { 19651 name: "LoweredAtomicStore", 19652 argLen: 3, 19653 faultOnNilArg0: true, 19654 hasSideEffects: true, 19655 reg: regInfo{ 19656 inputs: []inputInfo{ 19657 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19658 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19659 }, 19660 }, 19661 }, 19662 { 19663 name: "LoweredAtomicStorezero", 19664 argLen: 2, 19665 faultOnNilArg0: true, 19666 hasSideEffects: true, 19667 reg: regInfo{ 19668 inputs: []inputInfo{ 19669 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19670 }, 19671 }, 19672 }, 19673 { 19674 name: "LoweredAtomicExchange", 19675 argLen: 3, 19676 resultNotInArgs: true, 19677 faultOnNilArg0: true, 19678 hasSideEffects: true, 19679 reg: regInfo{ 19680 inputs: []inputInfo{ 19681 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19682 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19683 }, 19684 outputs: []outputInfo{ 19685 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19686 }, 19687 }, 19688 }, 19689 { 19690 name: "LoweredAtomicAdd", 19691 argLen: 3, 19692 resultNotInArgs: true, 19693 faultOnNilArg0: true, 19694 hasSideEffects: true, 19695 reg: regInfo{ 19696 inputs: []inputInfo{ 19697 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19698 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19699 }, 19700 outputs: []outputInfo{ 19701 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19702 }, 19703 }, 19704 }, 19705 { 19706 name: "LoweredAtomicAddconst", 19707 auxType: auxInt32, 19708 argLen: 2, 19709 resultNotInArgs: true, 19710 faultOnNilArg0: true, 19711 hasSideEffects: true, 19712 reg: regInfo{ 19713 inputs: []inputInfo{ 19714 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19715 }, 19716 outputs: []outputInfo{ 19717 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19718 }, 19719 }, 19720 }, 19721 { 19722 name: "LoweredAtomicCas", 19723 argLen: 4, 19724 resultNotInArgs: true, 19725 faultOnNilArg0: true, 19726 hasSideEffects: true, 19727 reg: regInfo{ 19728 inputs: []inputInfo{ 19729 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19730 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19731 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19732 }, 19733 outputs: []outputInfo{ 19734 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19735 }, 19736 }, 19737 }, 19738 { 19739 name: "LoweredAtomicAnd", 19740 argLen: 3, 19741 faultOnNilArg0: true, 19742 hasSideEffects: true, 19743 asm: mips.AAND, 19744 reg: regInfo{ 19745 inputs: []inputInfo{ 19746 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19747 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19748 }, 19749 }, 19750 }, 19751 { 19752 name: "LoweredAtomicOr", 19753 argLen: 3, 19754 faultOnNilArg0: true, 19755 hasSideEffects: true, 19756 asm: mips.AOR, 19757 reg: regInfo{ 19758 inputs: []inputInfo{ 19759 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19760 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 19761 }, 19762 }, 19763 }, 19764 { 19765 name: "LoweredZero", 19766 auxType: auxInt32, 19767 argLen: 3, 19768 faultOnNilArg0: true, 19769 reg: regInfo{ 19770 inputs: []inputInfo{ 19771 {0, 2}, // R1 19772 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19773 }, 19774 clobbers: 2, // R1 19775 }, 19776 }, 19777 { 19778 name: "LoweredMove", 19779 auxType: auxInt32, 19780 argLen: 4, 19781 faultOnNilArg0: true, 19782 faultOnNilArg1: true, 19783 reg: regInfo{ 19784 inputs: []inputInfo{ 19785 {0, 4}, // R2 19786 {1, 2}, // R1 19787 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19788 }, 19789 clobbers: 6, // R1 R2 19790 }, 19791 }, 19792 { 19793 name: "LoweredNilCheck", 19794 argLen: 2, 19795 nilCheck: true, 19796 faultOnNilArg0: true, 19797 reg: regInfo{ 19798 inputs: []inputInfo{ 19799 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 19800 }, 19801 }, 19802 }, 19803 { 19804 name: "FPFlagTrue", 19805 argLen: 1, 19806 reg: regInfo{ 19807 outputs: []outputInfo{ 19808 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19809 }, 19810 }, 19811 }, 19812 { 19813 name: "FPFlagFalse", 19814 argLen: 1, 19815 reg: regInfo{ 19816 outputs: []outputInfo{ 19817 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19818 }, 19819 }, 19820 }, 19821 { 19822 name: "LoweredGetClosurePtr", 19823 argLen: 0, 19824 zeroWidth: true, 19825 reg: regInfo{ 19826 outputs: []outputInfo{ 19827 {0, 4194304}, // R22 19828 }, 19829 }, 19830 }, 19831 { 19832 name: "LoweredGetCallerSP", 19833 argLen: 0, 19834 rematerializeable: true, 19835 reg: regInfo{ 19836 outputs: []outputInfo{ 19837 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19838 }, 19839 }, 19840 }, 19841 { 19842 name: "LoweredGetCallerPC", 19843 argLen: 0, 19844 rematerializeable: true, 19845 reg: regInfo{ 19846 outputs: []outputInfo{ 19847 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 19848 }, 19849 }, 19850 }, 19851 { 19852 name: "LoweredWB", 19853 auxType: auxSym, 19854 argLen: 3, 19855 clobberFlags: true, 19856 symEffect: SymNone, 19857 reg: regInfo{ 19858 inputs: []inputInfo{ 19859 {0, 1048576}, // R20 19860 {1, 2097152}, // R21 19861 }, 19862 clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 19863 }, 19864 }, 19865 19866 { 19867 name: "ADDV", 19868 argLen: 2, 19869 commutative: true, 19870 asm: mips.AADDVU, 19871 reg: regInfo{ 19872 inputs: []inputInfo{ 19873 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19874 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19875 }, 19876 outputs: []outputInfo{ 19877 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 19878 }, 19879 }, 19880 }, 19881 { 19882 name: "ADDVconst", 19883 auxType: auxInt64, 19884 argLen: 1, 19885 asm: mips.AADDVU, 19886 reg: regInfo{ 19887 inputs: []inputInfo{ 19888 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 19889 }, 19890 outputs: []outputInfo{ 19891 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 19892 }, 19893 }, 19894 }, 19895 { 19896 name: "SUBV", 19897 argLen: 2, 19898 asm: mips.ASUBVU, 19899 reg: regInfo{ 19900 inputs: []inputInfo{ 19901 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19902 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19903 }, 19904 outputs: []outputInfo{ 19905 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 19906 }, 19907 }, 19908 }, 19909 { 19910 name: "SUBVconst", 19911 auxType: auxInt64, 19912 argLen: 1, 19913 asm: mips.ASUBVU, 19914 reg: regInfo{ 19915 inputs: []inputInfo{ 19916 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19917 }, 19918 outputs: []outputInfo{ 19919 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 19920 }, 19921 }, 19922 }, 19923 { 19924 name: "MULV", 19925 argLen: 2, 19926 commutative: true, 19927 asm: mips.AMULV, 19928 reg: regInfo{ 19929 inputs: []inputInfo{ 19930 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19931 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19932 }, 19933 outputs: []outputInfo{ 19934 {0, 1152921504606846976}, // HI 19935 {1, 2305843009213693952}, // LO 19936 }, 19937 }, 19938 }, 19939 { 19940 name: "MULVU", 19941 argLen: 2, 19942 commutative: true, 19943 asm: mips.AMULVU, 19944 reg: regInfo{ 19945 inputs: []inputInfo{ 19946 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19947 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19948 }, 19949 outputs: []outputInfo{ 19950 {0, 1152921504606846976}, // HI 19951 {1, 2305843009213693952}, // LO 19952 }, 19953 }, 19954 }, 19955 { 19956 name: "DIVV", 19957 argLen: 2, 19958 asm: mips.ADIVV, 19959 reg: regInfo{ 19960 inputs: []inputInfo{ 19961 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19962 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19963 }, 19964 outputs: []outputInfo{ 19965 {0, 1152921504606846976}, // HI 19966 {1, 2305843009213693952}, // LO 19967 }, 19968 }, 19969 }, 19970 { 19971 name: "DIVVU", 19972 argLen: 2, 19973 asm: mips.ADIVVU, 19974 reg: regInfo{ 19975 inputs: []inputInfo{ 19976 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19977 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 19978 }, 19979 outputs: []outputInfo{ 19980 {0, 1152921504606846976}, // HI 19981 {1, 2305843009213693952}, // LO 19982 }, 19983 }, 19984 }, 19985 { 19986 name: "ADDF", 19987 argLen: 2, 19988 commutative: true, 19989 asm: mips.AADDF, 19990 reg: regInfo{ 19991 inputs: []inputInfo{ 19992 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19993 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19994 }, 19995 outputs: []outputInfo{ 19996 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19997 }, 19998 }, 19999 }, 20000 { 20001 name: "ADDD", 20002 argLen: 2, 20003 commutative: true, 20004 asm: mips.AADDD, 20005 reg: regInfo{ 20006 inputs: []inputInfo{ 20007 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20008 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20009 }, 20010 outputs: []outputInfo{ 20011 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20012 }, 20013 }, 20014 }, 20015 { 20016 name: "SUBF", 20017 argLen: 2, 20018 asm: mips.ASUBF, 20019 reg: regInfo{ 20020 inputs: []inputInfo{ 20021 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20022 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20023 }, 20024 outputs: []outputInfo{ 20025 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20026 }, 20027 }, 20028 }, 20029 { 20030 name: "SUBD", 20031 argLen: 2, 20032 asm: mips.ASUBD, 20033 reg: regInfo{ 20034 inputs: []inputInfo{ 20035 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20036 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20037 }, 20038 outputs: []outputInfo{ 20039 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20040 }, 20041 }, 20042 }, 20043 { 20044 name: "MULF", 20045 argLen: 2, 20046 commutative: true, 20047 asm: mips.AMULF, 20048 reg: regInfo{ 20049 inputs: []inputInfo{ 20050 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20051 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20052 }, 20053 outputs: []outputInfo{ 20054 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20055 }, 20056 }, 20057 }, 20058 { 20059 name: "MULD", 20060 argLen: 2, 20061 commutative: true, 20062 asm: mips.AMULD, 20063 reg: regInfo{ 20064 inputs: []inputInfo{ 20065 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20066 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20067 }, 20068 outputs: []outputInfo{ 20069 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20070 }, 20071 }, 20072 }, 20073 { 20074 name: "DIVF", 20075 argLen: 2, 20076 asm: mips.ADIVF, 20077 reg: regInfo{ 20078 inputs: []inputInfo{ 20079 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20080 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20081 }, 20082 outputs: []outputInfo{ 20083 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20084 }, 20085 }, 20086 }, 20087 { 20088 name: "DIVD", 20089 argLen: 2, 20090 asm: mips.ADIVD, 20091 reg: regInfo{ 20092 inputs: []inputInfo{ 20093 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20094 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20095 }, 20096 outputs: []outputInfo{ 20097 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20098 }, 20099 }, 20100 }, 20101 { 20102 name: "AND", 20103 argLen: 2, 20104 commutative: true, 20105 asm: mips.AAND, 20106 reg: regInfo{ 20107 inputs: []inputInfo{ 20108 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20109 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20110 }, 20111 outputs: []outputInfo{ 20112 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20113 }, 20114 }, 20115 }, 20116 { 20117 name: "ANDconst", 20118 auxType: auxInt64, 20119 argLen: 1, 20120 asm: mips.AAND, 20121 reg: regInfo{ 20122 inputs: []inputInfo{ 20123 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20124 }, 20125 outputs: []outputInfo{ 20126 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20127 }, 20128 }, 20129 }, 20130 { 20131 name: "OR", 20132 argLen: 2, 20133 commutative: true, 20134 asm: mips.AOR, 20135 reg: regInfo{ 20136 inputs: []inputInfo{ 20137 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20138 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20139 }, 20140 outputs: []outputInfo{ 20141 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20142 }, 20143 }, 20144 }, 20145 { 20146 name: "ORconst", 20147 auxType: auxInt64, 20148 argLen: 1, 20149 asm: mips.AOR, 20150 reg: regInfo{ 20151 inputs: []inputInfo{ 20152 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20153 }, 20154 outputs: []outputInfo{ 20155 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20156 }, 20157 }, 20158 }, 20159 { 20160 name: "XOR", 20161 argLen: 2, 20162 commutative: true, 20163 asm: mips.AXOR, 20164 reg: regInfo{ 20165 inputs: []inputInfo{ 20166 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20167 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20168 }, 20169 outputs: []outputInfo{ 20170 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20171 }, 20172 }, 20173 }, 20174 { 20175 name: "XORconst", 20176 auxType: auxInt64, 20177 argLen: 1, 20178 asm: mips.AXOR, 20179 reg: regInfo{ 20180 inputs: []inputInfo{ 20181 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20182 }, 20183 outputs: []outputInfo{ 20184 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20185 }, 20186 }, 20187 }, 20188 { 20189 name: "NOR", 20190 argLen: 2, 20191 commutative: true, 20192 asm: mips.ANOR, 20193 reg: regInfo{ 20194 inputs: []inputInfo{ 20195 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20196 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20197 }, 20198 outputs: []outputInfo{ 20199 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20200 }, 20201 }, 20202 }, 20203 { 20204 name: "NORconst", 20205 auxType: auxInt64, 20206 argLen: 1, 20207 asm: mips.ANOR, 20208 reg: regInfo{ 20209 inputs: []inputInfo{ 20210 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20211 }, 20212 outputs: []outputInfo{ 20213 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20214 }, 20215 }, 20216 }, 20217 { 20218 name: "NEGV", 20219 argLen: 1, 20220 reg: regInfo{ 20221 inputs: []inputInfo{ 20222 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20223 }, 20224 outputs: []outputInfo{ 20225 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20226 }, 20227 }, 20228 }, 20229 { 20230 name: "NEGF", 20231 argLen: 1, 20232 asm: mips.ANEGF, 20233 reg: regInfo{ 20234 inputs: []inputInfo{ 20235 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20236 }, 20237 outputs: []outputInfo{ 20238 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20239 }, 20240 }, 20241 }, 20242 { 20243 name: "NEGD", 20244 argLen: 1, 20245 asm: mips.ANEGD, 20246 reg: regInfo{ 20247 inputs: []inputInfo{ 20248 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20249 }, 20250 outputs: []outputInfo{ 20251 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20252 }, 20253 }, 20254 }, 20255 { 20256 name: "SQRTD", 20257 argLen: 1, 20258 asm: mips.ASQRTD, 20259 reg: regInfo{ 20260 inputs: []inputInfo{ 20261 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20262 }, 20263 outputs: []outputInfo{ 20264 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20265 }, 20266 }, 20267 }, 20268 { 20269 name: "SLLV", 20270 argLen: 2, 20271 asm: mips.ASLLV, 20272 reg: regInfo{ 20273 inputs: []inputInfo{ 20274 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20275 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20276 }, 20277 outputs: []outputInfo{ 20278 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20279 }, 20280 }, 20281 }, 20282 { 20283 name: "SLLVconst", 20284 auxType: auxInt64, 20285 argLen: 1, 20286 asm: mips.ASLLV, 20287 reg: regInfo{ 20288 inputs: []inputInfo{ 20289 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20290 }, 20291 outputs: []outputInfo{ 20292 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20293 }, 20294 }, 20295 }, 20296 { 20297 name: "SRLV", 20298 argLen: 2, 20299 asm: mips.ASRLV, 20300 reg: regInfo{ 20301 inputs: []inputInfo{ 20302 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20303 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20304 }, 20305 outputs: []outputInfo{ 20306 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20307 }, 20308 }, 20309 }, 20310 { 20311 name: "SRLVconst", 20312 auxType: auxInt64, 20313 argLen: 1, 20314 asm: mips.ASRLV, 20315 reg: regInfo{ 20316 inputs: []inputInfo{ 20317 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20318 }, 20319 outputs: []outputInfo{ 20320 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20321 }, 20322 }, 20323 }, 20324 { 20325 name: "SRAV", 20326 argLen: 2, 20327 asm: mips.ASRAV, 20328 reg: regInfo{ 20329 inputs: []inputInfo{ 20330 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20331 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20332 }, 20333 outputs: []outputInfo{ 20334 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20335 }, 20336 }, 20337 }, 20338 { 20339 name: "SRAVconst", 20340 auxType: auxInt64, 20341 argLen: 1, 20342 asm: mips.ASRAV, 20343 reg: regInfo{ 20344 inputs: []inputInfo{ 20345 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20346 }, 20347 outputs: []outputInfo{ 20348 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20349 }, 20350 }, 20351 }, 20352 { 20353 name: "SGT", 20354 argLen: 2, 20355 asm: mips.ASGT, 20356 reg: regInfo{ 20357 inputs: []inputInfo{ 20358 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20359 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20360 }, 20361 outputs: []outputInfo{ 20362 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20363 }, 20364 }, 20365 }, 20366 { 20367 name: "SGTconst", 20368 auxType: auxInt64, 20369 argLen: 1, 20370 asm: mips.ASGT, 20371 reg: regInfo{ 20372 inputs: []inputInfo{ 20373 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20374 }, 20375 outputs: []outputInfo{ 20376 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20377 }, 20378 }, 20379 }, 20380 { 20381 name: "SGTU", 20382 argLen: 2, 20383 asm: mips.ASGTU, 20384 reg: regInfo{ 20385 inputs: []inputInfo{ 20386 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20387 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20388 }, 20389 outputs: []outputInfo{ 20390 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20391 }, 20392 }, 20393 }, 20394 { 20395 name: "SGTUconst", 20396 auxType: auxInt64, 20397 argLen: 1, 20398 asm: mips.ASGTU, 20399 reg: regInfo{ 20400 inputs: []inputInfo{ 20401 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20402 }, 20403 outputs: []outputInfo{ 20404 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20405 }, 20406 }, 20407 }, 20408 { 20409 name: "CMPEQF", 20410 argLen: 2, 20411 asm: mips.ACMPEQF, 20412 reg: regInfo{ 20413 inputs: []inputInfo{ 20414 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20415 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20416 }, 20417 }, 20418 }, 20419 { 20420 name: "CMPEQD", 20421 argLen: 2, 20422 asm: mips.ACMPEQD, 20423 reg: regInfo{ 20424 inputs: []inputInfo{ 20425 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20426 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20427 }, 20428 }, 20429 }, 20430 { 20431 name: "CMPGEF", 20432 argLen: 2, 20433 asm: mips.ACMPGEF, 20434 reg: regInfo{ 20435 inputs: []inputInfo{ 20436 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20437 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20438 }, 20439 }, 20440 }, 20441 { 20442 name: "CMPGED", 20443 argLen: 2, 20444 asm: mips.ACMPGED, 20445 reg: regInfo{ 20446 inputs: []inputInfo{ 20447 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20448 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20449 }, 20450 }, 20451 }, 20452 { 20453 name: "CMPGTF", 20454 argLen: 2, 20455 asm: mips.ACMPGTF, 20456 reg: regInfo{ 20457 inputs: []inputInfo{ 20458 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20459 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20460 }, 20461 }, 20462 }, 20463 { 20464 name: "CMPGTD", 20465 argLen: 2, 20466 asm: mips.ACMPGTD, 20467 reg: regInfo{ 20468 inputs: []inputInfo{ 20469 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20470 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20471 }, 20472 }, 20473 }, 20474 { 20475 name: "MOVVconst", 20476 auxType: auxInt64, 20477 argLen: 0, 20478 rematerializeable: true, 20479 asm: mips.AMOVV, 20480 reg: regInfo{ 20481 outputs: []outputInfo{ 20482 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20483 }, 20484 }, 20485 }, 20486 { 20487 name: "MOVFconst", 20488 auxType: auxFloat64, 20489 argLen: 0, 20490 rematerializeable: true, 20491 asm: mips.AMOVF, 20492 reg: regInfo{ 20493 outputs: []outputInfo{ 20494 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20495 }, 20496 }, 20497 }, 20498 { 20499 name: "MOVDconst", 20500 auxType: auxFloat64, 20501 argLen: 0, 20502 rematerializeable: true, 20503 asm: mips.AMOVD, 20504 reg: regInfo{ 20505 outputs: []outputInfo{ 20506 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20507 }, 20508 }, 20509 }, 20510 { 20511 name: "MOVVaddr", 20512 auxType: auxSymOff, 20513 argLen: 1, 20514 rematerializeable: true, 20515 symEffect: SymAddr, 20516 asm: mips.AMOVV, 20517 reg: regInfo{ 20518 inputs: []inputInfo{ 20519 {0, 4611686018460942336}, // SP SB 20520 }, 20521 outputs: []outputInfo{ 20522 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20523 }, 20524 }, 20525 }, 20526 { 20527 name: "MOVBload", 20528 auxType: auxSymOff, 20529 argLen: 2, 20530 faultOnNilArg0: true, 20531 symEffect: SymRead, 20532 asm: mips.AMOVB, 20533 reg: regInfo{ 20534 inputs: []inputInfo{ 20535 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20536 }, 20537 outputs: []outputInfo{ 20538 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20539 }, 20540 }, 20541 }, 20542 { 20543 name: "MOVBUload", 20544 auxType: auxSymOff, 20545 argLen: 2, 20546 faultOnNilArg0: true, 20547 symEffect: SymRead, 20548 asm: mips.AMOVBU, 20549 reg: regInfo{ 20550 inputs: []inputInfo{ 20551 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20552 }, 20553 outputs: []outputInfo{ 20554 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20555 }, 20556 }, 20557 }, 20558 { 20559 name: "MOVHload", 20560 auxType: auxSymOff, 20561 argLen: 2, 20562 faultOnNilArg0: true, 20563 symEffect: SymRead, 20564 asm: mips.AMOVH, 20565 reg: regInfo{ 20566 inputs: []inputInfo{ 20567 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20568 }, 20569 outputs: []outputInfo{ 20570 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20571 }, 20572 }, 20573 }, 20574 { 20575 name: "MOVHUload", 20576 auxType: auxSymOff, 20577 argLen: 2, 20578 faultOnNilArg0: true, 20579 symEffect: SymRead, 20580 asm: mips.AMOVHU, 20581 reg: regInfo{ 20582 inputs: []inputInfo{ 20583 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20584 }, 20585 outputs: []outputInfo{ 20586 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20587 }, 20588 }, 20589 }, 20590 { 20591 name: "MOVWload", 20592 auxType: auxSymOff, 20593 argLen: 2, 20594 faultOnNilArg0: true, 20595 symEffect: SymRead, 20596 asm: mips.AMOVW, 20597 reg: regInfo{ 20598 inputs: []inputInfo{ 20599 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20600 }, 20601 outputs: []outputInfo{ 20602 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20603 }, 20604 }, 20605 }, 20606 { 20607 name: "MOVWUload", 20608 auxType: auxSymOff, 20609 argLen: 2, 20610 faultOnNilArg0: true, 20611 symEffect: SymRead, 20612 asm: mips.AMOVWU, 20613 reg: regInfo{ 20614 inputs: []inputInfo{ 20615 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20616 }, 20617 outputs: []outputInfo{ 20618 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20619 }, 20620 }, 20621 }, 20622 { 20623 name: "MOVVload", 20624 auxType: auxSymOff, 20625 argLen: 2, 20626 faultOnNilArg0: true, 20627 symEffect: SymRead, 20628 asm: mips.AMOVV, 20629 reg: regInfo{ 20630 inputs: []inputInfo{ 20631 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20632 }, 20633 outputs: []outputInfo{ 20634 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20635 }, 20636 }, 20637 }, 20638 { 20639 name: "MOVFload", 20640 auxType: auxSymOff, 20641 argLen: 2, 20642 faultOnNilArg0: true, 20643 symEffect: SymRead, 20644 asm: mips.AMOVF, 20645 reg: regInfo{ 20646 inputs: []inputInfo{ 20647 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20648 }, 20649 outputs: []outputInfo{ 20650 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20651 }, 20652 }, 20653 }, 20654 { 20655 name: "MOVDload", 20656 auxType: auxSymOff, 20657 argLen: 2, 20658 faultOnNilArg0: true, 20659 symEffect: SymRead, 20660 asm: mips.AMOVD, 20661 reg: regInfo{ 20662 inputs: []inputInfo{ 20663 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20664 }, 20665 outputs: []outputInfo{ 20666 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20667 }, 20668 }, 20669 }, 20670 { 20671 name: "MOVBstore", 20672 auxType: auxSymOff, 20673 argLen: 3, 20674 faultOnNilArg0: true, 20675 symEffect: SymWrite, 20676 asm: mips.AMOVB, 20677 reg: regInfo{ 20678 inputs: []inputInfo{ 20679 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20680 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20681 }, 20682 }, 20683 }, 20684 { 20685 name: "MOVHstore", 20686 auxType: auxSymOff, 20687 argLen: 3, 20688 faultOnNilArg0: true, 20689 symEffect: SymWrite, 20690 asm: mips.AMOVH, 20691 reg: regInfo{ 20692 inputs: []inputInfo{ 20693 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20694 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20695 }, 20696 }, 20697 }, 20698 { 20699 name: "MOVWstore", 20700 auxType: auxSymOff, 20701 argLen: 3, 20702 faultOnNilArg0: true, 20703 symEffect: SymWrite, 20704 asm: mips.AMOVW, 20705 reg: regInfo{ 20706 inputs: []inputInfo{ 20707 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20708 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20709 }, 20710 }, 20711 }, 20712 { 20713 name: "MOVVstore", 20714 auxType: auxSymOff, 20715 argLen: 3, 20716 faultOnNilArg0: true, 20717 symEffect: SymWrite, 20718 asm: mips.AMOVV, 20719 reg: regInfo{ 20720 inputs: []inputInfo{ 20721 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20722 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20723 }, 20724 }, 20725 }, 20726 { 20727 name: "MOVFstore", 20728 auxType: auxSymOff, 20729 argLen: 3, 20730 faultOnNilArg0: true, 20731 symEffect: SymWrite, 20732 asm: mips.AMOVF, 20733 reg: regInfo{ 20734 inputs: []inputInfo{ 20735 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20736 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20737 }, 20738 }, 20739 }, 20740 { 20741 name: "MOVDstore", 20742 auxType: auxSymOff, 20743 argLen: 3, 20744 faultOnNilArg0: true, 20745 symEffect: SymWrite, 20746 asm: mips.AMOVD, 20747 reg: regInfo{ 20748 inputs: []inputInfo{ 20749 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20750 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20751 }, 20752 }, 20753 }, 20754 { 20755 name: "MOVBstorezero", 20756 auxType: auxSymOff, 20757 argLen: 2, 20758 faultOnNilArg0: true, 20759 symEffect: SymWrite, 20760 asm: mips.AMOVB, 20761 reg: regInfo{ 20762 inputs: []inputInfo{ 20763 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20764 }, 20765 }, 20766 }, 20767 { 20768 name: "MOVHstorezero", 20769 auxType: auxSymOff, 20770 argLen: 2, 20771 faultOnNilArg0: true, 20772 symEffect: SymWrite, 20773 asm: mips.AMOVH, 20774 reg: regInfo{ 20775 inputs: []inputInfo{ 20776 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20777 }, 20778 }, 20779 }, 20780 { 20781 name: "MOVWstorezero", 20782 auxType: auxSymOff, 20783 argLen: 2, 20784 faultOnNilArg0: true, 20785 symEffect: SymWrite, 20786 asm: mips.AMOVW, 20787 reg: regInfo{ 20788 inputs: []inputInfo{ 20789 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20790 }, 20791 }, 20792 }, 20793 { 20794 name: "MOVVstorezero", 20795 auxType: auxSymOff, 20796 argLen: 2, 20797 faultOnNilArg0: true, 20798 symEffect: SymWrite, 20799 asm: mips.AMOVV, 20800 reg: regInfo{ 20801 inputs: []inputInfo{ 20802 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 20803 }, 20804 }, 20805 }, 20806 { 20807 name: "MOVBreg", 20808 argLen: 1, 20809 asm: mips.AMOVB, 20810 reg: regInfo{ 20811 inputs: []inputInfo{ 20812 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20813 }, 20814 outputs: []outputInfo{ 20815 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20816 }, 20817 }, 20818 }, 20819 { 20820 name: "MOVBUreg", 20821 argLen: 1, 20822 asm: mips.AMOVBU, 20823 reg: regInfo{ 20824 inputs: []inputInfo{ 20825 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20826 }, 20827 outputs: []outputInfo{ 20828 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20829 }, 20830 }, 20831 }, 20832 { 20833 name: "MOVHreg", 20834 argLen: 1, 20835 asm: mips.AMOVH, 20836 reg: regInfo{ 20837 inputs: []inputInfo{ 20838 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20839 }, 20840 outputs: []outputInfo{ 20841 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20842 }, 20843 }, 20844 }, 20845 { 20846 name: "MOVHUreg", 20847 argLen: 1, 20848 asm: mips.AMOVHU, 20849 reg: regInfo{ 20850 inputs: []inputInfo{ 20851 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20852 }, 20853 outputs: []outputInfo{ 20854 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20855 }, 20856 }, 20857 }, 20858 { 20859 name: "MOVWreg", 20860 argLen: 1, 20861 asm: mips.AMOVW, 20862 reg: regInfo{ 20863 inputs: []inputInfo{ 20864 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20865 }, 20866 outputs: []outputInfo{ 20867 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20868 }, 20869 }, 20870 }, 20871 { 20872 name: "MOVWUreg", 20873 argLen: 1, 20874 asm: mips.AMOVWU, 20875 reg: regInfo{ 20876 inputs: []inputInfo{ 20877 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20878 }, 20879 outputs: []outputInfo{ 20880 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20881 }, 20882 }, 20883 }, 20884 { 20885 name: "MOVVreg", 20886 argLen: 1, 20887 asm: mips.AMOVV, 20888 reg: regInfo{ 20889 inputs: []inputInfo{ 20890 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 20891 }, 20892 outputs: []outputInfo{ 20893 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20894 }, 20895 }, 20896 }, 20897 { 20898 name: "MOVVnop", 20899 argLen: 1, 20900 resultInArg0: true, 20901 reg: regInfo{ 20902 inputs: []inputInfo{ 20903 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20904 }, 20905 outputs: []outputInfo{ 20906 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 20907 }, 20908 }, 20909 }, 20910 { 20911 name: "MOVWF", 20912 argLen: 1, 20913 asm: mips.AMOVWF, 20914 reg: regInfo{ 20915 inputs: []inputInfo{ 20916 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20917 }, 20918 outputs: []outputInfo{ 20919 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20920 }, 20921 }, 20922 }, 20923 { 20924 name: "MOVWD", 20925 argLen: 1, 20926 asm: mips.AMOVWD, 20927 reg: regInfo{ 20928 inputs: []inputInfo{ 20929 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20930 }, 20931 outputs: []outputInfo{ 20932 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20933 }, 20934 }, 20935 }, 20936 { 20937 name: "MOVVF", 20938 argLen: 1, 20939 asm: mips.AMOVVF, 20940 reg: regInfo{ 20941 inputs: []inputInfo{ 20942 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20943 }, 20944 outputs: []outputInfo{ 20945 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20946 }, 20947 }, 20948 }, 20949 { 20950 name: "MOVVD", 20951 argLen: 1, 20952 asm: mips.AMOVVD, 20953 reg: regInfo{ 20954 inputs: []inputInfo{ 20955 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20956 }, 20957 outputs: []outputInfo{ 20958 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20959 }, 20960 }, 20961 }, 20962 { 20963 name: "TRUNCFW", 20964 argLen: 1, 20965 asm: mips.ATRUNCFW, 20966 reg: regInfo{ 20967 inputs: []inputInfo{ 20968 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20969 }, 20970 outputs: []outputInfo{ 20971 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20972 }, 20973 }, 20974 }, 20975 { 20976 name: "TRUNCDW", 20977 argLen: 1, 20978 asm: mips.ATRUNCDW, 20979 reg: regInfo{ 20980 inputs: []inputInfo{ 20981 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20982 }, 20983 outputs: []outputInfo{ 20984 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20985 }, 20986 }, 20987 }, 20988 { 20989 name: "TRUNCFV", 20990 argLen: 1, 20991 asm: mips.ATRUNCFV, 20992 reg: regInfo{ 20993 inputs: []inputInfo{ 20994 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20995 }, 20996 outputs: []outputInfo{ 20997 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20998 }, 20999 }, 21000 }, 21001 { 21002 name: "TRUNCDV", 21003 argLen: 1, 21004 asm: mips.ATRUNCDV, 21005 reg: regInfo{ 21006 inputs: []inputInfo{ 21007 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21008 }, 21009 outputs: []outputInfo{ 21010 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21011 }, 21012 }, 21013 }, 21014 { 21015 name: "MOVFD", 21016 argLen: 1, 21017 asm: mips.AMOVFD, 21018 reg: regInfo{ 21019 inputs: []inputInfo{ 21020 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21021 }, 21022 outputs: []outputInfo{ 21023 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21024 }, 21025 }, 21026 }, 21027 { 21028 name: "MOVDF", 21029 argLen: 1, 21030 asm: mips.AMOVDF, 21031 reg: regInfo{ 21032 inputs: []inputInfo{ 21033 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21034 }, 21035 outputs: []outputInfo{ 21036 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21037 }, 21038 }, 21039 }, 21040 { 21041 name: "CALLstatic", 21042 auxType: auxSymOff, 21043 argLen: 1, 21044 clobberFlags: true, 21045 call: true, 21046 symEffect: SymNone, 21047 reg: regInfo{ 21048 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 21049 }, 21050 }, 21051 { 21052 name: "CALLclosure", 21053 auxType: auxInt64, 21054 argLen: 3, 21055 clobberFlags: true, 21056 call: true, 21057 reg: regInfo{ 21058 inputs: []inputInfo{ 21059 {1, 4194304}, // R22 21060 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 21061 }, 21062 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 21063 }, 21064 }, 21065 { 21066 name: "CALLinter", 21067 auxType: auxInt64, 21068 argLen: 2, 21069 clobberFlags: true, 21070 call: true, 21071 reg: regInfo{ 21072 inputs: []inputInfo{ 21073 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21074 }, 21075 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 21076 }, 21077 }, 21078 { 21079 name: "DUFFZERO", 21080 auxType: auxInt64, 21081 argLen: 2, 21082 faultOnNilArg0: true, 21083 reg: regInfo{ 21084 inputs: []inputInfo{ 21085 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21086 }, 21087 clobbers: 134217730, // R1 R31 21088 }, 21089 }, 21090 { 21091 name: "LoweredZero", 21092 auxType: auxInt64, 21093 argLen: 3, 21094 clobberFlags: true, 21095 faultOnNilArg0: true, 21096 reg: regInfo{ 21097 inputs: []inputInfo{ 21098 {0, 2}, // R1 21099 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21100 }, 21101 clobbers: 2, // R1 21102 }, 21103 }, 21104 { 21105 name: "LoweredMove", 21106 auxType: auxInt64, 21107 argLen: 4, 21108 clobberFlags: true, 21109 faultOnNilArg0: true, 21110 faultOnNilArg1: true, 21111 reg: regInfo{ 21112 inputs: []inputInfo{ 21113 {0, 4}, // R2 21114 {1, 2}, // R1 21115 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21116 }, 21117 clobbers: 6, // R1 R2 21118 }, 21119 }, 21120 { 21121 name: "LoweredAtomicLoad32", 21122 argLen: 2, 21123 faultOnNilArg0: true, 21124 reg: regInfo{ 21125 inputs: []inputInfo{ 21126 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21127 }, 21128 outputs: []outputInfo{ 21129 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21130 }, 21131 }, 21132 }, 21133 { 21134 name: "LoweredAtomicLoad64", 21135 argLen: 2, 21136 faultOnNilArg0: true, 21137 reg: regInfo{ 21138 inputs: []inputInfo{ 21139 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21140 }, 21141 outputs: []outputInfo{ 21142 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21143 }, 21144 }, 21145 }, 21146 { 21147 name: "LoweredAtomicStore32", 21148 argLen: 3, 21149 faultOnNilArg0: true, 21150 hasSideEffects: true, 21151 reg: regInfo{ 21152 inputs: []inputInfo{ 21153 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21154 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21155 }, 21156 }, 21157 }, 21158 { 21159 name: "LoweredAtomicStore64", 21160 argLen: 3, 21161 faultOnNilArg0: true, 21162 hasSideEffects: true, 21163 reg: regInfo{ 21164 inputs: []inputInfo{ 21165 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21166 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21167 }, 21168 }, 21169 }, 21170 { 21171 name: "LoweredAtomicStorezero32", 21172 argLen: 2, 21173 faultOnNilArg0: true, 21174 hasSideEffects: true, 21175 reg: regInfo{ 21176 inputs: []inputInfo{ 21177 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21178 }, 21179 }, 21180 }, 21181 { 21182 name: "LoweredAtomicStorezero64", 21183 argLen: 2, 21184 faultOnNilArg0: true, 21185 hasSideEffects: true, 21186 reg: regInfo{ 21187 inputs: []inputInfo{ 21188 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21189 }, 21190 }, 21191 }, 21192 { 21193 name: "LoweredAtomicExchange32", 21194 argLen: 3, 21195 resultNotInArgs: true, 21196 faultOnNilArg0: true, 21197 hasSideEffects: true, 21198 reg: regInfo{ 21199 inputs: []inputInfo{ 21200 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21201 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21202 }, 21203 outputs: []outputInfo{ 21204 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21205 }, 21206 }, 21207 }, 21208 { 21209 name: "LoweredAtomicExchange64", 21210 argLen: 3, 21211 resultNotInArgs: true, 21212 faultOnNilArg0: true, 21213 hasSideEffects: true, 21214 reg: regInfo{ 21215 inputs: []inputInfo{ 21216 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21217 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21218 }, 21219 outputs: []outputInfo{ 21220 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21221 }, 21222 }, 21223 }, 21224 { 21225 name: "LoweredAtomicAdd32", 21226 argLen: 3, 21227 resultNotInArgs: true, 21228 faultOnNilArg0: true, 21229 hasSideEffects: true, 21230 reg: regInfo{ 21231 inputs: []inputInfo{ 21232 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21233 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21234 }, 21235 outputs: []outputInfo{ 21236 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21237 }, 21238 }, 21239 }, 21240 { 21241 name: "LoweredAtomicAdd64", 21242 argLen: 3, 21243 resultNotInArgs: true, 21244 faultOnNilArg0: true, 21245 hasSideEffects: true, 21246 reg: regInfo{ 21247 inputs: []inputInfo{ 21248 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21249 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21250 }, 21251 outputs: []outputInfo{ 21252 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21253 }, 21254 }, 21255 }, 21256 { 21257 name: "LoweredAtomicAddconst32", 21258 auxType: auxInt32, 21259 argLen: 2, 21260 resultNotInArgs: true, 21261 faultOnNilArg0: true, 21262 hasSideEffects: true, 21263 reg: regInfo{ 21264 inputs: []inputInfo{ 21265 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21266 }, 21267 outputs: []outputInfo{ 21268 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21269 }, 21270 }, 21271 }, 21272 { 21273 name: "LoweredAtomicAddconst64", 21274 auxType: auxInt64, 21275 argLen: 2, 21276 resultNotInArgs: true, 21277 faultOnNilArg0: true, 21278 hasSideEffects: true, 21279 reg: regInfo{ 21280 inputs: []inputInfo{ 21281 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21282 }, 21283 outputs: []outputInfo{ 21284 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21285 }, 21286 }, 21287 }, 21288 { 21289 name: "LoweredAtomicCas32", 21290 argLen: 4, 21291 resultNotInArgs: true, 21292 faultOnNilArg0: true, 21293 hasSideEffects: true, 21294 reg: regInfo{ 21295 inputs: []inputInfo{ 21296 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21297 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21298 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21299 }, 21300 outputs: []outputInfo{ 21301 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21302 }, 21303 }, 21304 }, 21305 { 21306 name: "LoweredAtomicCas64", 21307 argLen: 4, 21308 resultNotInArgs: true, 21309 faultOnNilArg0: true, 21310 hasSideEffects: true, 21311 reg: regInfo{ 21312 inputs: []inputInfo{ 21313 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21314 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21315 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 21316 }, 21317 outputs: []outputInfo{ 21318 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21319 }, 21320 }, 21321 }, 21322 { 21323 name: "LoweredNilCheck", 21324 argLen: 2, 21325 nilCheck: true, 21326 faultOnNilArg0: true, 21327 reg: regInfo{ 21328 inputs: []inputInfo{ 21329 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 21330 }, 21331 }, 21332 }, 21333 { 21334 name: "FPFlagTrue", 21335 argLen: 1, 21336 reg: regInfo{ 21337 outputs: []outputInfo{ 21338 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21339 }, 21340 }, 21341 }, 21342 { 21343 name: "FPFlagFalse", 21344 argLen: 1, 21345 reg: regInfo{ 21346 outputs: []outputInfo{ 21347 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21348 }, 21349 }, 21350 }, 21351 { 21352 name: "LoweredGetClosurePtr", 21353 argLen: 0, 21354 zeroWidth: true, 21355 reg: regInfo{ 21356 outputs: []outputInfo{ 21357 {0, 4194304}, // R22 21358 }, 21359 }, 21360 }, 21361 { 21362 name: "LoweredGetCallerSP", 21363 argLen: 0, 21364 rematerializeable: true, 21365 reg: regInfo{ 21366 outputs: []outputInfo{ 21367 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21368 }, 21369 }, 21370 }, 21371 { 21372 name: "LoweredGetCallerPC", 21373 argLen: 0, 21374 rematerializeable: true, 21375 reg: regInfo{ 21376 outputs: []outputInfo{ 21377 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 21378 }, 21379 }, 21380 }, 21381 { 21382 name: "LoweredWB", 21383 auxType: auxSym, 21384 argLen: 3, 21385 clobberFlags: true, 21386 symEffect: SymNone, 21387 reg: regInfo{ 21388 inputs: []inputInfo{ 21389 {0, 1048576}, // R20 21390 {1, 2097152}, // R21 21391 }, 21392 clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 21393 }, 21394 }, 21395 21396 { 21397 name: "ADD", 21398 argLen: 2, 21399 commutative: true, 21400 asm: ppc64.AADD, 21401 reg: regInfo{ 21402 inputs: []inputInfo{ 21403 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21404 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21405 }, 21406 outputs: []outputInfo{ 21407 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21408 }, 21409 }, 21410 }, 21411 { 21412 name: "ADDconst", 21413 auxType: auxInt64, 21414 argLen: 1, 21415 asm: ppc64.AADD, 21416 reg: regInfo{ 21417 inputs: []inputInfo{ 21418 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21419 }, 21420 outputs: []outputInfo{ 21421 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21422 }, 21423 }, 21424 }, 21425 { 21426 name: "FADD", 21427 argLen: 2, 21428 commutative: true, 21429 asm: ppc64.AFADD, 21430 reg: regInfo{ 21431 inputs: []inputInfo{ 21432 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21433 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21434 }, 21435 outputs: []outputInfo{ 21436 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21437 }, 21438 }, 21439 }, 21440 { 21441 name: "FADDS", 21442 argLen: 2, 21443 commutative: true, 21444 asm: ppc64.AFADDS, 21445 reg: regInfo{ 21446 inputs: []inputInfo{ 21447 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21448 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21449 }, 21450 outputs: []outputInfo{ 21451 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21452 }, 21453 }, 21454 }, 21455 { 21456 name: "SUB", 21457 argLen: 2, 21458 asm: ppc64.ASUB, 21459 reg: regInfo{ 21460 inputs: []inputInfo{ 21461 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21462 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21463 }, 21464 outputs: []outputInfo{ 21465 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21466 }, 21467 }, 21468 }, 21469 { 21470 name: "FSUB", 21471 argLen: 2, 21472 asm: ppc64.AFSUB, 21473 reg: regInfo{ 21474 inputs: []inputInfo{ 21475 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21476 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21477 }, 21478 outputs: []outputInfo{ 21479 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21480 }, 21481 }, 21482 }, 21483 { 21484 name: "FSUBS", 21485 argLen: 2, 21486 asm: ppc64.AFSUBS, 21487 reg: regInfo{ 21488 inputs: []inputInfo{ 21489 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21490 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21491 }, 21492 outputs: []outputInfo{ 21493 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21494 }, 21495 }, 21496 }, 21497 { 21498 name: "MULLD", 21499 argLen: 2, 21500 commutative: true, 21501 asm: ppc64.AMULLD, 21502 reg: regInfo{ 21503 inputs: []inputInfo{ 21504 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21505 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21506 }, 21507 outputs: []outputInfo{ 21508 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21509 }, 21510 }, 21511 }, 21512 { 21513 name: "MULLW", 21514 argLen: 2, 21515 commutative: true, 21516 asm: ppc64.AMULLW, 21517 reg: regInfo{ 21518 inputs: []inputInfo{ 21519 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21520 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21521 }, 21522 outputs: []outputInfo{ 21523 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21524 }, 21525 }, 21526 }, 21527 { 21528 name: "MULHD", 21529 argLen: 2, 21530 commutative: true, 21531 asm: ppc64.AMULHD, 21532 reg: regInfo{ 21533 inputs: []inputInfo{ 21534 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21535 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21536 }, 21537 outputs: []outputInfo{ 21538 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21539 }, 21540 }, 21541 }, 21542 { 21543 name: "MULHW", 21544 argLen: 2, 21545 commutative: true, 21546 asm: ppc64.AMULHW, 21547 reg: regInfo{ 21548 inputs: []inputInfo{ 21549 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21550 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21551 }, 21552 outputs: []outputInfo{ 21553 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21554 }, 21555 }, 21556 }, 21557 { 21558 name: "MULHDU", 21559 argLen: 2, 21560 commutative: true, 21561 asm: ppc64.AMULHDU, 21562 reg: regInfo{ 21563 inputs: []inputInfo{ 21564 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21565 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21566 }, 21567 outputs: []outputInfo{ 21568 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21569 }, 21570 }, 21571 }, 21572 { 21573 name: "MULHWU", 21574 argLen: 2, 21575 commutative: true, 21576 asm: ppc64.AMULHWU, 21577 reg: regInfo{ 21578 inputs: []inputInfo{ 21579 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21580 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21581 }, 21582 outputs: []outputInfo{ 21583 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21584 }, 21585 }, 21586 }, 21587 { 21588 name: "LoweredMuluhilo", 21589 argLen: 2, 21590 resultNotInArgs: true, 21591 reg: regInfo{ 21592 inputs: []inputInfo{ 21593 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21594 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21595 }, 21596 outputs: []outputInfo{ 21597 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21598 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21599 }, 21600 }, 21601 }, 21602 { 21603 name: "FMUL", 21604 argLen: 2, 21605 commutative: true, 21606 asm: ppc64.AFMUL, 21607 reg: regInfo{ 21608 inputs: []inputInfo{ 21609 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21610 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21611 }, 21612 outputs: []outputInfo{ 21613 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21614 }, 21615 }, 21616 }, 21617 { 21618 name: "FMULS", 21619 argLen: 2, 21620 commutative: true, 21621 asm: ppc64.AFMULS, 21622 reg: regInfo{ 21623 inputs: []inputInfo{ 21624 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21625 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21626 }, 21627 outputs: []outputInfo{ 21628 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21629 }, 21630 }, 21631 }, 21632 { 21633 name: "FMADD", 21634 argLen: 3, 21635 asm: ppc64.AFMADD, 21636 reg: regInfo{ 21637 inputs: []inputInfo{ 21638 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21639 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21640 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21641 }, 21642 outputs: []outputInfo{ 21643 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21644 }, 21645 }, 21646 }, 21647 { 21648 name: "FMADDS", 21649 argLen: 3, 21650 asm: ppc64.AFMADDS, 21651 reg: regInfo{ 21652 inputs: []inputInfo{ 21653 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21654 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21655 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21656 }, 21657 outputs: []outputInfo{ 21658 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21659 }, 21660 }, 21661 }, 21662 { 21663 name: "FMSUB", 21664 argLen: 3, 21665 asm: ppc64.AFMSUB, 21666 reg: regInfo{ 21667 inputs: []inputInfo{ 21668 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21669 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21670 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21671 }, 21672 outputs: []outputInfo{ 21673 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21674 }, 21675 }, 21676 }, 21677 { 21678 name: "FMSUBS", 21679 argLen: 3, 21680 asm: ppc64.AFMSUBS, 21681 reg: regInfo{ 21682 inputs: []inputInfo{ 21683 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21684 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21685 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21686 }, 21687 outputs: []outputInfo{ 21688 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 21689 }, 21690 }, 21691 }, 21692 { 21693 name: "SRAD", 21694 argLen: 2, 21695 asm: ppc64.ASRAD, 21696 reg: regInfo{ 21697 inputs: []inputInfo{ 21698 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21699 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21700 }, 21701 outputs: []outputInfo{ 21702 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21703 }, 21704 }, 21705 }, 21706 { 21707 name: "SRAW", 21708 argLen: 2, 21709 asm: ppc64.ASRAW, 21710 reg: regInfo{ 21711 inputs: []inputInfo{ 21712 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21713 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21714 }, 21715 outputs: []outputInfo{ 21716 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21717 }, 21718 }, 21719 }, 21720 { 21721 name: "SRD", 21722 argLen: 2, 21723 asm: ppc64.ASRD, 21724 reg: regInfo{ 21725 inputs: []inputInfo{ 21726 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21727 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21728 }, 21729 outputs: []outputInfo{ 21730 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21731 }, 21732 }, 21733 }, 21734 { 21735 name: "SRW", 21736 argLen: 2, 21737 asm: ppc64.ASRW, 21738 reg: regInfo{ 21739 inputs: []inputInfo{ 21740 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21741 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21742 }, 21743 outputs: []outputInfo{ 21744 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21745 }, 21746 }, 21747 }, 21748 { 21749 name: "SLD", 21750 argLen: 2, 21751 asm: ppc64.ASLD, 21752 reg: regInfo{ 21753 inputs: []inputInfo{ 21754 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21755 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21756 }, 21757 outputs: []outputInfo{ 21758 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21759 }, 21760 }, 21761 }, 21762 { 21763 name: "SLW", 21764 argLen: 2, 21765 asm: ppc64.ASLW, 21766 reg: regInfo{ 21767 inputs: []inputInfo{ 21768 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21769 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21770 }, 21771 outputs: []outputInfo{ 21772 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21773 }, 21774 }, 21775 }, 21776 { 21777 name: "ROTL", 21778 argLen: 2, 21779 asm: ppc64.AROTL, 21780 reg: regInfo{ 21781 inputs: []inputInfo{ 21782 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21783 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21784 }, 21785 outputs: []outputInfo{ 21786 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21787 }, 21788 }, 21789 }, 21790 { 21791 name: "ROTLW", 21792 argLen: 2, 21793 asm: ppc64.AROTLW, 21794 reg: regInfo{ 21795 inputs: []inputInfo{ 21796 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21797 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21798 }, 21799 outputs: []outputInfo{ 21800 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21801 }, 21802 }, 21803 }, 21804 { 21805 name: "ADDconstForCarry", 21806 auxType: auxInt16, 21807 argLen: 1, 21808 asm: ppc64.AADDC, 21809 reg: regInfo{ 21810 inputs: []inputInfo{ 21811 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21812 }, 21813 clobbers: 2147483648, // R31 21814 }, 21815 }, 21816 { 21817 name: "MaskIfNotCarry", 21818 argLen: 1, 21819 asm: ppc64.AADDME, 21820 reg: regInfo{ 21821 outputs: []outputInfo{ 21822 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21823 }, 21824 }, 21825 }, 21826 { 21827 name: "SRADconst", 21828 auxType: auxInt64, 21829 argLen: 1, 21830 asm: ppc64.ASRAD, 21831 reg: regInfo{ 21832 inputs: []inputInfo{ 21833 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21834 }, 21835 outputs: []outputInfo{ 21836 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21837 }, 21838 }, 21839 }, 21840 { 21841 name: "SRAWconst", 21842 auxType: auxInt64, 21843 argLen: 1, 21844 asm: ppc64.ASRAW, 21845 reg: regInfo{ 21846 inputs: []inputInfo{ 21847 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21848 }, 21849 outputs: []outputInfo{ 21850 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21851 }, 21852 }, 21853 }, 21854 { 21855 name: "SRDconst", 21856 auxType: auxInt64, 21857 argLen: 1, 21858 asm: ppc64.ASRD, 21859 reg: regInfo{ 21860 inputs: []inputInfo{ 21861 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21862 }, 21863 outputs: []outputInfo{ 21864 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21865 }, 21866 }, 21867 }, 21868 { 21869 name: "SRWconst", 21870 auxType: auxInt64, 21871 argLen: 1, 21872 asm: ppc64.ASRW, 21873 reg: regInfo{ 21874 inputs: []inputInfo{ 21875 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21876 }, 21877 outputs: []outputInfo{ 21878 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21879 }, 21880 }, 21881 }, 21882 { 21883 name: "SLDconst", 21884 auxType: auxInt64, 21885 argLen: 1, 21886 asm: ppc64.ASLD, 21887 reg: regInfo{ 21888 inputs: []inputInfo{ 21889 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21890 }, 21891 outputs: []outputInfo{ 21892 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21893 }, 21894 }, 21895 }, 21896 { 21897 name: "SLWconst", 21898 auxType: auxInt64, 21899 argLen: 1, 21900 asm: ppc64.ASLW, 21901 reg: regInfo{ 21902 inputs: []inputInfo{ 21903 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21904 }, 21905 outputs: []outputInfo{ 21906 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21907 }, 21908 }, 21909 }, 21910 { 21911 name: "ROTLconst", 21912 auxType: auxInt64, 21913 argLen: 1, 21914 asm: ppc64.AROTL, 21915 reg: regInfo{ 21916 inputs: []inputInfo{ 21917 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21918 }, 21919 outputs: []outputInfo{ 21920 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21921 }, 21922 }, 21923 }, 21924 { 21925 name: "ROTLWconst", 21926 auxType: auxInt64, 21927 argLen: 1, 21928 asm: ppc64.AROTLW, 21929 reg: regInfo{ 21930 inputs: []inputInfo{ 21931 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21932 }, 21933 outputs: []outputInfo{ 21934 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21935 }, 21936 }, 21937 }, 21938 { 21939 name: "CNTLZD", 21940 argLen: 1, 21941 clobberFlags: true, 21942 asm: ppc64.ACNTLZD, 21943 reg: regInfo{ 21944 inputs: []inputInfo{ 21945 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21946 }, 21947 outputs: []outputInfo{ 21948 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21949 }, 21950 }, 21951 }, 21952 { 21953 name: "CNTLZW", 21954 argLen: 1, 21955 clobberFlags: true, 21956 asm: ppc64.ACNTLZW, 21957 reg: regInfo{ 21958 inputs: []inputInfo{ 21959 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21960 }, 21961 outputs: []outputInfo{ 21962 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21963 }, 21964 }, 21965 }, 21966 { 21967 name: "POPCNTD", 21968 argLen: 1, 21969 asm: ppc64.APOPCNTD, 21970 reg: regInfo{ 21971 inputs: []inputInfo{ 21972 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21973 }, 21974 outputs: []outputInfo{ 21975 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21976 }, 21977 }, 21978 }, 21979 { 21980 name: "POPCNTW", 21981 argLen: 1, 21982 asm: ppc64.APOPCNTW, 21983 reg: regInfo{ 21984 inputs: []inputInfo{ 21985 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21986 }, 21987 outputs: []outputInfo{ 21988 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21989 }, 21990 }, 21991 }, 21992 { 21993 name: "POPCNTB", 21994 argLen: 1, 21995 asm: ppc64.APOPCNTB, 21996 reg: regInfo{ 21997 inputs: []inputInfo{ 21998 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 21999 }, 22000 outputs: []outputInfo{ 22001 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22002 }, 22003 }, 22004 }, 22005 { 22006 name: "FDIV", 22007 argLen: 2, 22008 asm: ppc64.AFDIV, 22009 reg: regInfo{ 22010 inputs: []inputInfo{ 22011 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22012 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22013 }, 22014 outputs: []outputInfo{ 22015 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22016 }, 22017 }, 22018 }, 22019 { 22020 name: "FDIVS", 22021 argLen: 2, 22022 asm: ppc64.AFDIVS, 22023 reg: regInfo{ 22024 inputs: []inputInfo{ 22025 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22026 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22027 }, 22028 outputs: []outputInfo{ 22029 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22030 }, 22031 }, 22032 }, 22033 { 22034 name: "DIVD", 22035 argLen: 2, 22036 asm: ppc64.ADIVD, 22037 reg: regInfo{ 22038 inputs: []inputInfo{ 22039 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22040 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22041 }, 22042 outputs: []outputInfo{ 22043 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22044 }, 22045 }, 22046 }, 22047 { 22048 name: "DIVW", 22049 argLen: 2, 22050 asm: ppc64.ADIVW, 22051 reg: regInfo{ 22052 inputs: []inputInfo{ 22053 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22054 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22055 }, 22056 outputs: []outputInfo{ 22057 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22058 }, 22059 }, 22060 }, 22061 { 22062 name: "DIVDU", 22063 argLen: 2, 22064 asm: ppc64.ADIVDU, 22065 reg: regInfo{ 22066 inputs: []inputInfo{ 22067 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22068 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22069 }, 22070 outputs: []outputInfo{ 22071 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22072 }, 22073 }, 22074 }, 22075 { 22076 name: "DIVWU", 22077 argLen: 2, 22078 asm: ppc64.ADIVWU, 22079 reg: regInfo{ 22080 inputs: []inputInfo{ 22081 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22082 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22083 }, 22084 outputs: []outputInfo{ 22085 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22086 }, 22087 }, 22088 }, 22089 { 22090 name: "FCTIDZ", 22091 argLen: 1, 22092 asm: ppc64.AFCTIDZ, 22093 reg: regInfo{ 22094 inputs: []inputInfo{ 22095 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22096 }, 22097 outputs: []outputInfo{ 22098 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22099 }, 22100 }, 22101 }, 22102 { 22103 name: "FCTIWZ", 22104 argLen: 1, 22105 asm: ppc64.AFCTIWZ, 22106 reg: regInfo{ 22107 inputs: []inputInfo{ 22108 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22109 }, 22110 outputs: []outputInfo{ 22111 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22112 }, 22113 }, 22114 }, 22115 { 22116 name: "FCFID", 22117 argLen: 1, 22118 asm: ppc64.AFCFID, 22119 reg: regInfo{ 22120 inputs: []inputInfo{ 22121 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22122 }, 22123 outputs: []outputInfo{ 22124 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22125 }, 22126 }, 22127 }, 22128 { 22129 name: "FCFIDS", 22130 argLen: 1, 22131 asm: ppc64.AFCFIDS, 22132 reg: regInfo{ 22133 inputs: []inputInfo{ 22134 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22135 }, 22136 outputs: []outputInfo{ 22137 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22138 }, 22139 }, 22140 }, 22141 { 22142 name: "FRSP", 22143 argLen: 1, 22144 asm: ppc64.AFRSP, 22145 reg: regInfo{ 22146 inputs: []inputInfo{ 22147 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22148 }, 22149 outputs: []outputInfo{ 22150 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22151 }, 22152 }, 22153 }, 22154 { 22155 name: "MFVSRD", 22156 argLen: 1, 22157 asm: ppc64.AMFVSRD, 22158 reg: regInfo{ 22159 inputs: []inputInfo{ 22160 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22161 }, 22162 outputs: []outputInfo{ 22163 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22164 }, 22165 }, 22166 }, 22167 { 22168 name: "MTVSRD", 22169 argLen: 1, 22170 asm: ppc64.AMTVSRD, 22171 reg: regInfo{ 22172 inputs: []inputInfo{ 22173 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22174 }, 22175 outputs: []outputInfo{ 22176 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22177 }, 22178 }, 22179 }, 22180 { 22181 name: "AND", 22182 argLen: 2, 22183 commutative: true, 22184 asm: ppc64.AAND, 22185 reg: regInfo{ 22186 inputs: []inputInfo{ 22187 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22188 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22189 }, 22190 outputs: []outputInfo{ 22191 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22192 }, 22193 }, 22194 }, 22195 { 22196 name: "ANDN", 22197 argLen: 2, 22198 asm: ppc64.AANDN, 22199 reg: regInfo{ 22200 inputs: []inputInfo{ 22201 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22202 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22203 }, 22204 outputs: []outputInfo{ 22205 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22206 }, 22207 }, 22208 }, 22209 { 22210 name: "ANDCC", 22211 argLen: 2, 22212 commutative: true, 22213 asm: ppc64.AANDCC, 22214 reg: regInfo{ 22215 inputs: []inputInfo{ 22216 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22217 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22218 }, 22219 outputs: []outputInfo{ 22220 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22221 }, 22222 }, 22223 }, 22224 { 22225 name: "OR", 22226 argLen: 2, 22227 commutative: true, 22228 asm: ppc64.AOR, 22229 reg: regInfo{ 22230 inputs: []inputInfo{ 22231 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22232 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22233 }, 22234 outputs: []outputInfo{ 22235 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22236 }, 22237 }, 22238 }, 22239 { 22240 name: "ORN", 22241 argLen: 2, 22242 asm: ppc64.AORN, 22243 reg: regInfo{ 22244 inputs: []inputInfo{ 22245 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22246 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22247 }, 22248 outputs: []outputInfo{ 22249 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22250 }, 22251 }, 22252 }, 22253 { 22254 name: "ORCC", 22255 argLen: 2, 22256 commutative: true, 22257 asm: ppc64.AORCC, 22258 reg: regInfo{ 22259 inputs: []inputInfo{ 22260 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22261 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22262 }, 22263 outputs: []outputInfo{ 22264 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22265 }, 22266 }, 22267 }, 22268 { 22269 name: "NOR", 22270 argLen: 2, 22271 commutative: true, 22272 asm: ppc64.ANOR, 22273 reg: regInfo{ 22274 inputs: []inputInfo{ 22275 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22276 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22277 }, 22278 outputs: []outputInfo{ 22279 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22280 }, 22281 }, 22282 }, 22283 { 22284 name: "XOR", 22285 argLen: 2, 22286 commutative: true, 22287 asm: ppc64.AXOR, 22288 reg: regInfo{ 22289 inputs: []inputInfo{ 22290 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22291 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22292 }, 22293 outputs: []outputInfo{ 22294 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22295 }, 22296 }, 22297 }, 22298 { 22299 name: "XORCC", 22300 argLen: 2, 22301 commutative: true, 22302 asm: ppc64.AXORCC, 22303 reg: regInfo{ 22304 inputs: []inputInfo{ 22305 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22306 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22307 }, 22308 outputs: []outputInfo{ 22309 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22310 }, 22311 }, 22312 }, 22313 { 22314 name: "EQV", 22315 argLen: 2, 22316 commutative: true, 22317 asm: ppc64.AEQV, 22318 reg: regInfo{ 22319 inputs: []inputInfo{ 22320 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22321 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22322 }, 22323 outputs: []outputInfo{ 22324 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22325 }, 22326 }, 22327 }, 22328 { 22329 name: "NEG", 22330 argLen: 1, 22331 asm: ppc64.ANEG, 22332 reg: regInfo{ 22333 inputs: []inputInfo{ 22334 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22335 }, 22336 outputs: []outputInfo{ 22337 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22338 }, 22339 }, 22340 }, 22341 { 22342 name: "FNEG", 22343 argLen: 1, 22344 asm: ppc64.AFNEG, 22345 reg: regInfo{ 22346 inputs: []inputInfo{ 22347 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22348 }, 22349 outputs: []outputInfo{ 22350 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22351 }, 22352 }, 22353 }, 22354 { 22355 name: "FSQRT", 22356 argLen: 1, 22357 asm: ppc64.AFSQRT, 22358 reg: regInfo{ 22359 inputs: []inputInfo{ 22360 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22361 }, 22362 outputs: []outputInfo{ 22363 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22364 }, 22365 }, 22366 }, 22367 { 22368 name: "FSQRTS", 22369 argLen: 1, 22370 asm: ppc64.AFSQRTS, 22371 reg: regInfo{ 22372 inputs: []inputInfo{ 22373 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22374 }, 22375 outputs: []outputInfo{ 22376 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22377 }, 22378 }, 22379 }, 22380 { 22381 name: "FFLOOR", 22382 argLen: 1, 22383 asm: ppc64.AFRIM, 22384 reg: regInfo{ 22385 inputs: []inputInfo{ 22386 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22387 }, 22388 outputs: []outputInfo{ 22389 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22390 }, 22391 }, 22392 }, 22393 { 22394 name: "FCEIL", 22395 argLen: 1, 22396 asm: ppc64.AFRIP, 22397 reg: regInfo{ 22398 inputs: []inputInfo{ 22399 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22400 }, 22401 outputs: []outputInfo{ 22402 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22403 }, 22404 }, 22405 }, 22406 { 22407 name: "FTRUNC", 22408 argLen: 1, 22409 asm: ppc64.AFRIZ, 22410 reg: regInfo{ 22411 inputs: []inputInfo{ 22412 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22413 }, 22414 outputs: []outputInfo{ 22415 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22416 }, 22417 }, 22418 }, 22419 { 22420 name: "FROUND", 22421 argLen: 1, 22422 asm: ppc64.AFRIN, 22423 reg: regInfo{ 22424 inputs: []inputInfo{ 22425 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22426 }, 22427 outputs: []outputInfo{ 22428 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22429 }, 22430 }, 22431 }, 22432 { 22433 name: "FABS", 22434 argLen: 1, 22435 asm: ppc64.AFABS, 22436 reg: regInfo{ 22437 inputs: []inputInfo{ 22438 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22439 }, 22440 outputs: []outputInfo{ 22441 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22442 }, 22443 }, 22444 }, 22445 { 22446 name: "FNABS", 22447 argLen: 1, 22448 asm: ppc64.AFNABS, 22449 reg: regInfo{ 22450 inputs: []inputInfo{ 22451 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22452 }, 22453 outputs: []outputInfo{ 22454 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22455 }, 22456 }, 22457 }, 22458 { 22459 name: "FCPSGN", 22460 argLen: 2, 22461 asm: ppc64.AFCPSGN, 22462 reg: regInfo{ 22463 inputs: []inputInfo{ 22464 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22465 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22466 }, 22467 outputs: []outputInfo{ 22468 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22469 }, 22470 }, 22471 }, 22472 { 22473 name: "ORconst", 22474 auxType: auxInt64, 22475 argLen: 1, 22476 asm: ppc64.AOR, 22477 reg: regInfo{ 22478 inputs: []inputInfo{ 22479 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22480 }, 22481 outputs: []outputInfo{ 22482 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22483 }, 22484 }, 22485 }, 22486 { 22487 name: "XORconst", 22488 auxType: auxInt64, 22489 argLen: 1, 22490 asm: ppc64.AXOR, 22491 reg: regInfo{ 22492 inputs: []inputInfo{ 22493 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22494 }, 22495 outputs: []outputInfo{ 22496 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22497 }, 22498 }, 22499 }, 22500 { 22501 name: "ANDconst", 22502 auxType: auxInt64, 22503 argLen: 1, 22504 clobberFlags: true, 22505 asm: ppc64.AANDCC, 22506 reg: regInfo{ 22507 inputs: []inputInfo{ 22508 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22509 }, 22510 outputs: []outputInfo{ 22511 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22512 }, 22513 }, 22514 }, 22515 { 22516 name: "ANDCCconst", 22517 auxType: auxInt64, 22518 argLen: 1, 22519 asm: ppc64.AANDCC, 22520 reg: regInfo{ 22521 inputs: []inputInfo{ 22522 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22523 }, 22524 }, 22525 }, 22526 { 22527 name: "MOVBreg", 22528 argLen: 1, 22529 asm: ppc64.AMOVB, 22530 reg: regInfo{ 22531 inputs: []inputInfo{ 22532 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22533 }, 22534 outputs: []outputInfo{ 22535 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22536 }, 22537 }, 22538 }, 22539 { 22540 name: "MOVBZreg", 22541 argLen: 1, 22542 asm: ppc64.AMOVBZ, 22543 reg: regInfo{ 22544 inputs: []inputInfo{ 22545 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22546 }, 22547 outputs: []outputInfo{ 22548 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22549 }, 22550 }, 22551 }, 22552 { 22553 name: "MOVHreg", 22554 argLen: 1, 22555 asm: ppc64.AMOVH, 22556 reg: regInfo{ 22557 inputs: []inputInfo{ 22558 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22559 }, 22560 outputs: []outputInfo{ 22561 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22562 }, 22563 }, 22564 }, 22565 { 22566 name: "MOVHZreg", 22567 argLen: 1, 22568 asm: ppc64.AMOVHZ, 22569 reg: regInfo{ 22570 inputs: []inputInfo{ 22571 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22572 }, 22573 outputs: []outputInfo{ 22574 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22575 }, 22576 }, 22577 }, 22578 { 22579 name: "MOVWreg", 22580 argLen: 1, 22581 asm: ppc64.AMOVW, 22582 reg: regInfo{ 22583 inputs: []inputInfo{ 22584 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22585 }, 22586 outputs: []outputInfo{ 22587 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22588 }, 22589 }, 22590 }, 22591 { 22592 name: "MOVWZreg", 22593 argLen: 1, 22594 asm: ppc64.AMOVWZ, 22595 reg: regInfo{ 22596 inputs: []inputInfo{ 22597 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22598 }, 22599 outputs: []outputInfo{ 22600 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22601 }, 22602 }, 22603 }, 22604 { 22605 name: "MOVBZload", 22606 auxType: auxSymOff, 22607 argLen: 2, 22608 faultOnNilArg0: true, 22609 symEffect: SymRead, 22610 asm: ppc64.AMOVBZ, 22611 reg: regInfo{ 22612 inputs: []inputInfo{ 22613 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22614 }, 22615 outputs: []outputInfo{ 22616 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22617 }, 22618 }, 22619 }, 22620 { 22621 name: "MOVHload", 22622 auxType: auxSymOff, 22623 argLen: 2, 22624 faultOnNilArg0: true, 22625 symEffect: SymRead, 22626 asm: ppc64.AMOVH, 22627 reg: regInfo{ 22628 inputs: []inputInfo{ 22629 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22630 }, 22631 outputs: []outputInfo{ 22632 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22633 }, 22634 }, 22635 }, 22636 { 22637 name: "MOVHZload", 22638 auxType: auxSymOff, 22639 argLen: 2, 22640 faultOnNilArg0: true, 22641 symEffect: SymRead, 22642 asm: ppc64.AMOVHZ, 22643 reg: regInfo{ 22644 inputs: []inputInfo{ 22645 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22646 }, 22647 outputs: []outputInfo{ 22648 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22649 }, 22650 }, 22651 }, 22652 { 22653 name: "MOVWload", 22654 auxType: auxSymOff, 22655 argLen: 2, 22656 faultOnNilArg0: true, 22657 symEffect: SymRead, 22658 asm: ppc64.AMOVW, 22659 reg: regInfo{ 22660 inputs: []inputInfo{ 22661 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22662 }, 22663 outputs: []outputInfo{ 22664 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22665 }, 22666 }, 22667 }, 22668 { 22669 name: "MOVWZload", 22670 auxType: auxSymOff, 22671 argLen: 2, 22672 faultOnNilArg0: true, 22673 symEffect: SymRead, 22674 asm: ppc64.AMOVWZ, 22675 reg: regInfo{ 22676 inputs: []inputInfo{ 22677 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22678 }, 22679 outputs: []outputInfo{ 22680 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22681 }, 22682 }, 22683 }, 22684 { 22685 name: "MOVDload", 22686 auxType: auxSymOff, 22687 argLen: 2, 22688 faultOnNilArg0: true, 22689 symEffect: SymRead, 22690 asm: ppc64.AMOVD, 22691 reg: regInfo{ 22692 inputs: []inputInfo{ 22693 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22694 }, 22695 outputs: []outputInfo{ 22696 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22697 }, 22698 }, 22699 }, 22700 { 22701 name: "MOVDBRload", 22702 auxType: auxSymOff, 22703 argLen: 2, 22704 faultOnNilArg0: true, 22705 symEffect: SymRead, 22706 asm: ppc64.AMOVDBR, 22707 reg: regInfo{ 22708 inputs: []inputInfo{ 22709 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22710 }, 22711 outputs: []outputInfo{ 22712 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22713 }, 22714 }, 22715 }, 22716 { 22717 name: "MOVWBRload", 22718 auxType: auxSymOff, 22719 argLen: 2, 22720 faultOnNilArg0: true, 22721 symEffect: SymRead, 22722 asm: ppc64.AMOVWBR, 22723 reg: regInfo{ 22724 inputs: []inputInfo{ 22725 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22726 }, 22727 outputs: []outputInfo{ 22728 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22729 }, 22730 }, 22731 }, 22732 { 22733 name: "MOVHBRload", 22734 auxType: auxSymOff, 22735 argLen: 2, 22736 faultOnNilArg0: true, 22737 symEffect: SymRead, 22738 asm: ppc64.AMOVHBR, 22739 reg: regInfo{ 22740 inputs: []inputInfo{ 22741 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22742 }, 22743 outputs: []outputInfo{ 22744 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22745 }, 22746 }, 22747 }, 22748 { 22749 name: "MOVBZloadidx", 22750 auxType: auxSymOff, 22751 argLen: 3, 22752 faultOnNilArg0: true, 22753 symEffect: SymRead, 22754 asm: ppc64.AMOVBZ, 22755 reg: regInfo{ 22756 inputs: []inputInfo{ 22757 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22758 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22759 }, 22760 outputs: []outputInfo{ 22761 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22762 }, 22763 }, 22764 }, 22765 { 22766 name: "MOVHloadidx", 22767 auxType: auxSymOff, 22768 argLen: 3, 22769 faultOnNilArg0: true, 22770 symEffect: SymRead, 22771 asm: ppc64.AMOVH, 22772 reg: regInfo{ 22773 inputs: []inputInfo{ 22774 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22775 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22776 }, 22777 outputs: []outputInfo{ 22778 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22779 }, 22780 }, 22781 }, 22782 { 22783 name: "MOVHZloadidx", 22784 auxType: auxSymOff, 22785 argLen: 3, 22786 faultOnNilArg0: true, 22787 symEffect: SymRead, 22788 asm: ppc64.AMOVHZ, 22789 reg: regInfo{ 22790 inputs: []inputInfo{ 22791 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22792 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22793 }, 22794 outputs: []outputInfo{ 22795 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22796 }, 22797 }, 22798 }, 22799 { 22800 name: "MOVWloadidx", 22801 auxType: auxSymOff, 22802 argLen: 3, 22803 faultOnNilArg0: true, 22804 symEffect: SymRead, 22805 asm: ppc64.AMOVW, 22806 reg: regInfo{ 22807 inputs: []inputInfo{ 22808 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22809 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22810 }, 22811 outputs: []outputInfo{ 22812 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22813 }, 22814 }, 22815 }, 22816 { 22817 name: "MOVWZloadidx", 22818 auxType: auxSymOff, 22819 argLen: 3, 22820 faultOnNilArg0: true, 22821 symEffect: SymRead, 22822 asm: ppc64.AMOVWZ, 22823 reg: regInfo{ 22824 inputs: []inputInfo{ 22825 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22826 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22827 }, 22828 outputs: []outputInfo{ 22829 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22830 }, 22831 }, 22832 }, 22833 { 22834 name: "MOVDloadidx", 22835 auxType: auxSymOff, 22836 argLen: 3, 22837 faultOnNilArg0: true, 22838 symEffect: SymRead, 22839 asm: ppc64.AMOVD, 22840 reg: regInfo{ 22841 inputs: []inputInfo{ 22842 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22843 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22844 }, 22845 outputs: []outputInfo{ 22846 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22847 }, 22848 }, 22849 }, 22850 { 22851 name: "MOVHBRloadidx", 22852 auxType: auxSymOff, 22853 argLen: 3, 22854 faultOnNilArg0: true, 22855 symEffect: SymRead, 22856 asm: ppc64.AMOVHBR, 22857 reg: regInfo{ 22858 inputs: []inputInfo{ 22859 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22860 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22861 }, 22862 outputs: []outputInfo{ 22863 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22864 }, 22865 }, 22866 }, 22867 { 22868 name: "MOVWBRloadidx", 22869 auxType: auxSymOff, 22870 argLen: 3, 22871 faultOnNilArg0: true, 22872 symEffect: SymRead, 22873 asm: ppc64.AMOVWBR, 22874 reg: regInfo{ 22875 inputs: []inputInfo{ 22876 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22877 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22878 }, 22879 outputs: []outputInfo{ 22880 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22881 }, 22882 }, 22883 }, 22884 { 22885 name: "MOVDBRloadidx", 22886 auxType: auxSymOff, 22887 argLen: 3, 22888 faultOnNilArg0: true, 22889 symEffect: SymRead, 22890 asm: ppc64.AMOVDBR, 22891 reg: regInfo{ 22892 inputs: []inputInfo{ 22893 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22894 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22895 }, 22896 outputs: []outputInfo{ 22897 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22898 }, 22899 }, 22900 }, 22901 { 22902 name: "FMOVDloadidx", 22903 auxType: auxSymOff, 22904 argLen: 3, 22905 faultOnNilArg0: true, 22906 symEffect: SymRead, 22907 asm: ppc64.AFMOVD, 22908 reg: regInfo{ 22909 inputs: []inputInfo{ 22910 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22911 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22912 }, 22913 outputs: []outputInfo{ 22914 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22915 }, 22916 }, 22917 }, 22918 { 22919 name: "FMOVSloadidx", 22920 auxType: auxSymOff, 22921 argLen: 3, 22922 faultOnNilArg0: true, 22923 symEffect: SymRead, 22924 asm: ppc64.AFMOVS, 22925 reg: regInfo{ 22926 inputs: []inputInfo{ 22927 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22928 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22929 }, 22930 outputs: []outputInfo{ 22931 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22932 }, 22933 }, 22934 }, 22935 { 22936 name: "MOVDBRstore", 22937 auxType: auxSymOff, 22938 argLen: 3, 22939 faultOnNilArg0: true, 22940 symEffect: SymWrite, 22941 asm: ppc64.AMOVDBR, 22942 reg: regInfo{ 22943 inputs: []inputInfo{ 22944 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22945 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22946 }, 22947 }, 22948 }, 22949 { 22950 name: "MOVWBRstore", 22951 auxType: auxSymOff, 22952 argLen: 3, 22953 faultOnNilArg0: true, 22954 symEffect: SymWrite, 22955 asm: ppc64.AMOVWBR, 22956 reg: regInfo{ 22957 inputs: []inputInfo{ 22958 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22959 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22960 }, 22961 }, 22962 }, 22963 { 22964 name: "MOVHBRstore", 22965 auxType: auxSymOff, 22966 argLen: 3, 22967 faultOnNilArg0: true, 22968 symEffect: SymWrite, 22969 asm: ppc64.AMOVHBR, 22970 reg: regInfo{ 22971 inputs: []inputInfo{ 22972 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22973 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22974 }, 22975 }, 22976 }, 22977 { 22978 name: "FMOVDload", 22979 auxType: auxSymOff, 22980 argLen: 2, 22981 faultOnNilArg0: true, 22982 symEffect: SymRead, 22983 asm: ppc64.AFMOVD, 22984 reg: regInfo{ 22985 inputs: []inputInfo{ 22986 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 22987 }, 22988 outputs: []outputInfo{ 22989 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 22990 }, 22991 }, 22992 }, 22993 { 22994 name: "FMOVSload", 22995 auxType: auxSymOff, 22996 argLen: 2, 22997 faultOnNilArg0: true, 22998 symEffect: SymRead, 22999 asm: ppc64.AFMOVS, 23000 reg: regInfo{ 23001 inputs: []inputInfo{ 23002 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23003 }, 23004 outputs: []outputInfo{ 23005 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23006 }, 23007 }, 23008 }, 23009 { 23010 name: "MOVBstore", 23011 auxType: auxSymOff, 23012 argLen: 3, 23013 faultOnNilArg0: true, 23014 symEffect: SymWrite, 23015 asm: ppc64.AMOVB, 23016 reg: regInfo{ 23017 inputs: []inputInfo{ 23018 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23019 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23020 }, 23021 }, 23022 }, 23023 { 23024 name: "MOVHstore", 23025 auxType: auxSymOff, 23026 argLen: 3, 23027 faultOnNilArg0: true, 23028 symEffect: SymWrite, 23029 asm: ppc64.AMOVH, 23030 reg: regInfo{ 23031 inputs: []inputInfo{ 23032 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23033 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23034 }, 23035 }, 23036 }, 23037 { 23038 name: "MOVWstore", 23039 auxType: auxSymOff, 23040 argLen: 3, 23041 faultOnNilArg0: true, 23042 symEffect: SymWrite, 23043 asm: ppc64.AMOVW, 23044 reg: regInfo{ 23045 inputs: []inputInfo{ 23046 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23047 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23048 }, 23049 }, 23050 }, 23051 { 23052 name: "MOVDstore", 23053 auxType: auxSymOff, 23054 argLen: 3, 23055 faultOnNilArg0: true, 23056 symEffect: SymWrite, 23057 asm: ppc64.AMOVD, 23058 reg: regInfo{ 23059 inputs: []inputInfo{ 23060 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23061 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23062 }, 23063 }, 23064 }, 23065 { 23066 name: "FMOVDstore", 23067 auxType: auxSymOff, 23068 argLen: 3, 23069 faultOnNilArg0: true, 23070 symEffect: SymWrite, 23071 asm: ppc64.AFMOVD, 23072 reg: regInfo{ 23073 inputs: []inputInfo{ 23074 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23075 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23076 }, 23077 }, 23078 }, 23079 { 23080 name: "FMOVSstore", 23081 auxType: auxSymOff, 23082 argLen: 3, 23083 faultOnNilArg0: true, 23084 symEffect: SymWrite, 23085 asm: ppc64.AFMOVS, 23086 reg: regInfo{ 23087 inputs: []inputInfo{ 23088 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23089 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23090 }, 23091 }, 23092 }, 23093 { 23094 name: "MOVBstoreidx", 23095 auxType: auxSymOff, 23096 argLen: 4, 23097 faultOnNilArg0: true, 23098 symEffect: SymWrite, 23099 asm: ppc64.AMOVB, 23100 reg: regInfo{ 23101 inputs: []inputInfo{ 23102 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23103 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23104 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23105 }, 23106 }, 23107 }, 23108 { 23109 name: "MOVHstoreidx", 23110 auxType: auxSymOff, 23111 argLen: 4, 23112 faultOnNilArg0: true, 23113 symEffect: SymWrite, 23114 asm: ppc64.AMOVH, 23115 reg: regInfo{ 23116 inputs: []inputInfo{ 23117 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23118 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23119 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23120 }, 23121 }, 23122 }, 23123 { 23124 name: "MOVWstoreidx", 23125 auxType: auxSymOff, 23126 argLen: 4, 23127 faultOnNilArg0: true, 23128 symEffect: SymWrite, 23129 asm: ppc64.AMOVW, 23130 reg: regInfo{ 23131 inputs: []inputInfo{ 23132 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23133 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23134 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23135 }, 23136 }, 23137 }, 23138 { 23139 name: "MOVDstoreidx", 23140 auxType: auxSymOff, 23141 argLen: 4, 23142 faultOnNilArg0: true, 23143 symEffect: SymWrite, 23144 asm: ppc64.AMOVD, 23145 reg: regInfo{ 23146 inputs: []inputInfo{ 23147 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23148 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23149 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23150 }, 23151 }, 23152 }, 23153 { 23154 name: "FMOVDstoreidx", 23155 auxType: auxSymOff, 23156 argLen: 4, 23157 faultOnNilArg0: true, 23158 symEffect: SymWrite, 23159 asm: ppc64.AFMOVD, 23160 reg: regInfo{ 23161 inputs: []inputInfo{ 23162 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23163 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23164 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23165 }, 23166 }, 23167 }, 23168 { 23169 name: "FMOVSstoreidx", 23170 auxType: auxSymOff, 23171 argLen: 4, 23172 faultOnNilArg0: true, 23173 symEffect: SymWrite, 23174 asm: ppc64.AFMOVS, 23175 reg: regInfo{ 23176 inputs: []inputInfo{ 23177 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23178 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23179 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23180 }, 23181 }, 23182 }, 23183 { 23184 name: "MOVHBRstoreidx", 23185 auxType: auxSymOff, 23186 argLen: 4, 23187 faultOnNilArg0: true, 23188 symEffect: SymWrite, 23189 asm: ppc64.AMOVHBR, 23190 reg: regInfo{ 23191 inputs: []inputInfo{ 23192 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23193 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23194 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23195 }, 23196 }, 23197 }, 23198 { 23199 name: "MOVWBRstoreidx", 23200 auxType: auxSymOff, 23201 argLen: 4, 23202 faultOnNilArg0: true, 23203 symEffect: SymWrite, 23204 asm: ppc64.AMOVWBR, 23205 reg: regInfo{ 23206 inputs: []inputInfo{ 23207 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23208 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23209 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23210 }, 23211 }, 23212 }, 23213 { 23214 name: "MOVDBRstoreidx", 23215 auxType: auxSymOff, 23216 argLen: 4, 23217 faultOnNilArg0: true, 23218 symEffect: SymWrite, 23219 asm: ppc64.AMOVDBR, 23220 reg: regInfo{ 23221 inputs: []inputInfo{ 23222 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23223 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23224 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23225 }, 23226 }, 23227 }, 23228 { 23229 name: "MOVBstorezero", 23230 auxType: auxSymOff, 23231 argLen: 2, 23232 faultOnNilArg0: true, 23233 symEffect: SymWrite, 23234 asm: ppc64.AMOVB, 23235 reg: regInfo{ 23236 inputs: []inputInfo{ 23237 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23238 }, 23239 }, 23240 }, 23241 { 23242 name: "MOVHstorezero", 23243 auxType: auxSymOff, 23244 argLen: 2, 23245 faultOnNilArg0: true, 23246 symEffect: SymWrite, 23247 asm: ppc64.AMOVH, 23248 reg: regInfo{ 23249 inputs: []inputInfo{ 23250 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23251 }, 23252 }, 23253 }, 23254 { 23255 name: "MOVWstorezero", 23256 auxType: auxSymOff, 23257 argLen: 2, 23258 faultOnNilArg0: true, 23259 symEffect: SymWrite, 23260 asm: ppc64.AMOVW, 23261 reg: regInfo{ 23262 inputs: []inputInfo{ 23263 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23264 }, 23265 }, 23266 }, 23267 { 23268 name: "MOVDstorezero", 23269 auxType: auxSymOff, 23270 argLen: 2, 23271 faultOnNilArg0: true, 23272 symEffect: SymWrite, 23273 asm: ppc64.AMOVD, 23274 reg: regInfo{ 23275 inputs: []inputInfo{ 23276 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23277 }, 23278 }, 23279 }, 23280 { 23281 name: "MOVDaddr", 23282 auxType: auxSymOff, 23283 argLen: 1, 23284 rematerializeable: true, 23285 symEffect: SymAddr, 23286 asm: ppc64.AMOVD, 23287 reg: regInfo{ 23288 inputs: []inputInfo{ 23289 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23290 }, 23291 outputs: []outputInfo{ 23292 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23293 }, 23294 }, 23295 }, 23296 { 23297 name: "MOVDconst", 23298 auxType: auxInt64, 23299 argLen: 0, 23300 rematerializeable: true, 23301 asm: ppc64.AMOVD, 23302 reg: regInfo{ 23303 outputs: []outputInfo{ 23304 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23305 }, 23306 }, 23307 }, 23308 { 23309 name: "FMOVDconst", 23310 auxType: auxFloat64, 23311 argLen: 0, 23312 rematerializeable: true, 23313 asm: ppc64.AFMOVD, 23314 reg: regInfo{ 23315 outputs: []outputInfo{ 23316 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23317 }, 23318 }, 23319 }, 23320 { 23321 name: "FMOVSconst", 23322 auxType: auxFloat32, 23323 argLen: 0, 23324 rematerializeable: true, 23325 asm: ppc64.AFMOVS, 23326 reg: regInfo{ 23327 outputs: []outputInfo{ 23328 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23329 }, 23330 }, 23331 }, 23332 { 23333 name: "FCMPU", 23334 argLen: 2, 23335 asm: ppc64.AFCMPU, 23336 reg: regInfo{ 23337 inputs: []inputInfo{ 23338 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23339 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23340 }, 23341 }, 23342 }, 23343 { 23344 name: "CMP", 23345 argLen: 2, 23346 asm: ppc64.ACMP, 23347 reg: regInfo{ 23348 inputs: []inputInfo{ 23349 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23350 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23351 }, 23352 }, 23353 }, 23354 { 23355 name: "CMPU", 23356 argLen: 2, 23357 asm: ppc64.ACMPU, 23358 reg: regInfo{ 23359 inputs: []inputInfo{ 23360 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23361 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23362 }, 23363 }, 23364 }, 23365 { 23366 name: "CMPW", 23367 argLen: 2, 23368 asm: ppc64.ACMPW, 23369 reg: regInfo{ 23370 inputs: []inputInfo{ 23371 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23372 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23373 }, 23374 }, 23375 }, 23376 { 23377 name: "CMPWU", 23378 argLen: 2, 23379 asm: ppc64.ACMPWU, 23380 reg: regInfo{ 23381 inputs: []inputInfo{ 23382 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23383 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23384 }, 23385 }, 23386 }, 23387 { 23388 name: "CMPconst", 23389 auxType: auxInt64, 23390 argLen: 1, 23391 asm: ppc64.ACMP, 23392 reg: regInfo{ 23393 inputs: []inputInfo{ 23394 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23395 }, 23396 }, 23397 }, 23398 { 23399 name: "CMPUconst", 23400 auxType: auxInt64, 23401 argLen: 1, 23402 asm: ppc64.ACMPU, 23403 reg: regInfo{ 23404 inputs: []inputInfo{ 23405 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23406 }, 23407 }, 23408 }, 23409 { 23410 name: "CMPWconst", 23411 auxType: auxInt32, 23412 argLen: 1, 23413 asm: ppc64.ACMPW, 23414 reg: regInfo{ 23415 inputs: []inputInfo{ 23416 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23417 }, 23418 }, 23419 }, 23420 { 23421 name: "CMPWUconst", 23422 auxType: auxInt32, 23423 argLen: 1, 23424 asm: ppc64.ACMPWU, 23425 reg: regInfo{ 23426 inputs: []inputInfo{ 23427 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23428 }, 23429 }, 23430 }, 23431 { 23432 name: "Equal", 23433 argLen: 1, 23434 reg: regInfo{ 23435 outputs: []outputInfo{ 23436 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23437 }, 23438 }, 23439 }, 23440 { 23441 name: "NotEqual", 23442 argLen: 1, 23443 reg: regInfo{ 23444 outputs: []outputInfo{ 23445 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23446 }, 23447 }, 23448 }, 23449 { 23450 name: "LessThan", 23451 argLen: 1, 23452 reg: regInfo{ 23453 outputs: []outputInfo{ 23454 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23455 }, 23456 }, 23457 }, 23458 { 23459 name: "FLessThan", 23460 argLen: 1, 23461 reg: regInfo{ 23462 outputs: []outputInfo{ 23463 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23464 }, 23465 }, 23466 }, 23467 { 23468 name: "LessEqual", 23469 argLen: 1, 23470 reg: regInfo{ 23471 outputs: []outputInfo{ 23472 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23473 }, 23474 }, 23475 }, 23476 { 23477 name: "FLessEqual", 23478 argLen: 1, 23479 reg: regInfo{ 23480 outputs: []outputInfo{ 23481 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23482 }, 23483 }, 23484 }, 23485 { 23486 name: "GreaterThan", 23487 argLen: 1, 23488 reg: regInfo{ 23489 outputs: []outputInfo{ 23490 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23491 }, 23492 }, 23493 }, 23494 { 23495 name: "FGreaterThan", 23496 argLen: 1, 23497 reg: regInfo{ 23498 outputs: []outputInfo{ 23499 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23500 }, 23501 }, 23502 }, 23503 { 23504 name: "GreaterEqual", 23505 argLen: 1, 23506 reg: regInfo{ 23507 outputs: []outputInfo{ 23508 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23509 }, 23510 }, 23511 }, 23512 { 23513 name: "FGreaterEqual", 23514 argLen: 1, 23515 reg: regInfo{ 23516 outputs: []outputInfo{ 23517 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23518 }, 23519 }, 23520 }, 23521 { 23522 name: "LoweredGetClosurePtr", 23523 argLen: 0, 23524 zeroWidth: true, 23525 reg: regInfo{ 23526 outputs: []outputInfo{ 23527 {0, 2048}, // R11 23528 }, 23529 }, 23530 }, 23531 { 23532 name: "LoweredGetCallerSP", 23533 argLen: 0, 23534 rematerializeable: true, 23535 reg: regInfo{ 23536 outputs: []outputInfo{ 23537 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23538 }, 23539 }, 23540 }, 23541 { 23542 name: "LoweredGetCallerPC", 23543 argLen: 0, 23544 rematerializeable: true, 23545 reg: regInfo{ 23546 outputs: []outputInfo{ 23547 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23548 }, 23549 }, 23550 }, 23551 { 23552 name: "LoweredNilCheck", 23553 argLen: 2, 23554 clobberFlags: true, 23555 nilCheck: true, 23556 faultOnNilArg0: true, 23557 reg: regInfo{ 23558 inputs: []inputInfo{ 23559 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23560 }, 23561 clobbers: 2147483648, // R31 23562 }, 23563 }, 23564 { 23565 name: "LoweredRound32F", 23566 argLen: 1, 23567 resultInArg0: true, 23568 zeroWidth: true, 23569 reg: regInfo{ 23570 inputs: []inputInfo{ 23571 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23572 }, 23573 outputs: []outputInfo{ 23574 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23575 }, 23576 }, 23577 }, 23578 { 23579 name: "LoweredRound64F", 23580 argLen: 1, 23581 resultInArg0: true, 23582 zeroWidth: true, 23583 reg: regInfo{ 23584 inputs: []inputInfo{ 23585 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23586 }, 23587 outputs: []outputInfo{ 23588 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23589 }, 23590 }, 23591 }, 23592 { 23593 name: "CALLstatic", 23594 auxType: auxSymOff, 23595 argLen: 1, 23596 clobberFlags: true, 23597 call: true, 23598 symEffect: SymNone, 23599 reg: regInfo{ 23600 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23601 }, 23602 }, 23603 { 23604 name: "CALLclosure", 23605 auxType: auxInt64, 23606 argLen: 3, 23607 clobberFlags: true, 23608 call: true, 23609 reg: regInfo{ 23610 inputs: []inputInfo{ 23611 {0, 4096}, // R12 23612 {1, 2048}, // R11 23613 }, 23614 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23615 }, 23616 }, 23617 { 23618 name: "CALLinter", 23619 auxType: auxInt64, 23620 argLen: 2, 23621 clobberFlags: true, 23622 call: true, 23623 reg: regInfo{ 23624 inputs: []inputInfo{ 23625 {0, 4096}, // R12 23626 }, 23627 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23628 }, 23629 }, 23630 { 23631 name: "LoweredZero", 23632 auxType: auxInt64, 23633 argLen: 2, 23634 clobberFlags: true, 23635 faultOnNilArg0: true, 23636 reg: regInfo{ 23637 inputs: []inputInfo{ 23638 {0, 8}, // R3 23639 }, 23640 clobbers: 8, // R3 23641 }, 23642 }, 23643 { 23644 name: "LoweredMove", 23645 auxType: auxInt64, 23646 argLen: 3, 23647 clobberFlags: true, 23648 faultOnNilArg0: true, 23649 faultOnNilArg1: true, 23650 reg: regInfo{ 23651 inputs: []inputInfo{ 23652 {0, 8}, // R3 23653 {1, 16}, // R4 23654 }, 23655 clobbers: 1944, // R3 R4 R7 R8 R9 R10 23656 }, 23657 }, 23658 { 23659 name: "LoweredAtomicStore32", 23660 auxType: auxInt64, 23661 argLen: 3, 23662 faultOnNilArg0: true, 23663 hasSideEffects: true, 23664 reg: regInfo{ 23665 inputs: []inputInfo{ 23666 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23667 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23668 }, 23669 }, 23670 }, 23671 { 23672 name: "LoweredAtomicStore64", 23673 auxType: auxInt64, 23674 argLen: 3, 23675 faultOnNilArg0: true, 23676 hasSideEffects: true, 23677 reg: regInfo{ 23678 inputs: []inputInfo{ 23679 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23680 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23681 }, 23682 }, 23683 }, 23684 { 23685 name: "LoweredAtomicLoad32", 23686 auxType: auxInt64, 23687 argLen: 2, 23688 clobberFlags: true, 23689 faultOnNilArg0: true, 23690 reg: regInfo{ 23691 inputs: []inputInfo{ 23692 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23693 }, 23694 outputs: []outputInfo{ 23695 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23696 }, 23697 }, 23698 }, 23699 { 23700 name: "LoweredAtomicLoad64", 23701 auxType: auxInt64, 23702 argLen: 2, 23703 clobberFlags: true, 23704 faultOnNilArg0: true, 23705 reg: regInfo{ 23706 inputs: []inputInfo{ 23707 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23708 }, 23709 outputs: []outputInfo{ 23710 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23711 }, 23712 }, 23713 }, 23714 { 23715 name: "LoweredAtomicLoadPtr", 23716 auxType: auxInt64, 23717 argLen: 2, 23718 clobberFlags: true, 23719 faultOnNilArg0: true, 23720 reg: regInfo{ 23721 inputs: []inputInfo{ 23722 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23723 }, 23724 outputs: []outputInfo{ 23725 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23726 }, 23727 }, 23728 }, 23729 { 23730 name: "LoweredAtomicAdd32", 23731 argLen: 3, 23732 resultNotInArgs: true, 23733 clobberFlags: true, 23734 faultOnNilArg0: true, 23735 hasSideEffects: true, 23736 reg: regInfo{ 23737 inputs: []inputInfo{ 23738 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23739 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23740 }, 23741 outputs: []outputInfo{ 23742 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23743 }, 23744 }, 23745 }, 23746 { 23747 name: "LoweredAtomicAdd64", 23748 argLen: 3, 23749 resultNotInArgs: true, 23750 clobberFlags: true, 23751 faultOnNilArg0: true, 23752 hasSideEffects: true, 23753 reg: regInfo{ 23754 inputs: []inputInfo{ 23755 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23756 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23757 }, 23758 outputs: []outputInfo{ 23759 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23760 }, 23761 }, 23762 }, 23763 { 23764 name: "LoweredAtomicExchange32", 23765 argLen: 3, 23766 resultNotInArgs: true, 23767 clobberFlags: true, 23768 faultOnNilArg0: true, 23769 hasSideEffects: true, 23770 reg: regInfo{ 23771 inputs: []inputInfo{ 23772 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23773 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23774 }, 23775 outputs: []outputInfo{ 23776 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23777 }, 23778 }, 23779 }, 23780 { 23781 name: "LoweredAtomicExchange64", 23782 argLen: 3, 23783 resultNotInArgs: true, 23784 clobberFlags: true, 23785 faultOnNilArg0: true, 23786 hasSideEffects: true, 23787 reg: regInfo{ 23788 inputs: []inputInfo{ 23789 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23790 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23791 }, 23792 outputs: []outputInfo{ 23793 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23794 }, 23795 }, 23796 }, 23797 { 23798 name: "LoweredAtomicCas64", 23799 auxType: auxInt64, 23800 argLen: 4, 23801 resultNotInArgs: true, 23802 clobberFlags: true, 23803 faultOnNilArg0: true, 23804 hasSideEffects: true, 23805 reg: regInfo{ 23806 inputs: []inputInfo{ 23807 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23808 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23809 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23810 }, 23811 outputs: []outputInfo{ 23812 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23813 }, 23814 }, 23815 }, 23816 { 23817 name: "LoweredAtomicCas32", 23818 auxType: auxInt64, 23819 argLen: 4, 23820 resultNotInArgs: true, 23821 clobberFlags: true, 23822 faultOnNilArg0: true, 23823 hasSideEffects: true, 23824 reg: regInfo{ 23825 inputs: []inputInfo{ 23826 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23827 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23828 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23829 }, 23830 outputs: []outputInfo{ 23831 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23832 }, 23833 }, 23834 }, 23835 { 23836 name: "LoweredAtomicAnd8", 23837 argLen: 3, 23838 faultOnNilArg0: true, 23839 hasSideEffects: true, 23840 asm: ppc64.AAND, 23841 reg: regInfo{ 23842 inputs: []inputInfo{ 23843 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23844 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23845 }, 23846 }, 23847 }, 23848 { 23849 name: "LoweredAtomicOr8", 23850 argLen: 3, 23851 faultOnNilArg0: true, 23852 hasSideEffects: true, 23853 asm: ppc64.AOR, 23854 reg: regInfo{ 23855 inputs: []inputInfo{ 23856 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23857 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 23858 }, 23859 }, 23860 }, 23861 { 23862 name: "LoweredWB", 23863 auxType: auxSym, 23864 argLen: 3, 23865 clobberFlags: true, 23866 symEffect: SymNone, 23867 reg: regInfo{ 23868 inputs: []inputInfo{ 23869 {0, 1048576}, // R20 23870 {1, 2097152}, // R21 23871 }, 23872 clobbers: 576460746931503104, // R16 R17 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 23873 }, 23874 }, 23875 { 23876 name: "InvertFlags", 23877 argLen: 1, 23878 reg: regInfo{}, 23879 }, 23880 { 23881 name: "FlagEQ", 23882 argLen: 0, 23883 reg: regInfo{}, 23884 }, 23885 { 23886 name: "FlagLT", 23887 argLen: 0, 23888 reg: regInfo{}, 23889 }, 23890 { 23891 name: "FlagGT", 23892 argLen: 0, 23893 reg: regInfo{}, 23894 }, 23895 23896 { 23897 name: "FADDS", 23898 argLen: 2, 23899 commutative: true, 23900 resultInArg0: true, 23901 clobberFlags: true, 23902 asm: s390x.AFADDS, 23903 reg: regInfo{ 23904 inputs: []inputInfo{ 23905 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23906 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23907 }, 23908 outputs: []outputInfo{ 23909 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23910 }, 23911 }, 23912 }, 23913 { 23914 name: "FADD", 23915 argLen: 2, 23916 commutative: true, 23917 resultInArg0: true, 23918 clobberFlags: true, 23919 asm: s390x.AFADD, 23920 reg: regInfo{ 23921 inputs: []inputInfo{ 23922 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23923 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23924 }, 23925 outputs: []outputInfo{ 23926 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23927 }, 23928 }, 23929 }, 23930 { 23931 name: "FSUBS", 23932 argLen: 2, 23933 resultInArg0: true, 23934 clobberFlags: true, 23935 asm: s390x.AFSUBS, 23936 reg: regInfo{ 23937 inputs: []inputInfo{ 23938 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23939 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23940 }, 23941 outputs: []outputInfo{ 23942 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23943 }, 23944 }, 23945 }, 23946 { 23947 name: "FSUB", 23948 argLen: 2, 23949 resultInArg0: true, 23950 clobberFlags: true, 23951 asm: s390x.AFSUB, 23952 reg: regInfo{ 23953 inputs: []inputInfo{ 23954 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23955 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23956 }, 23957 outputs: []outputInfo{ 23958 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23959 }, 23960 }, 23961 }, 23962 { 23963 name: "FMULS", 23964 argLen: 2, 23965 commutative: true, 23966 resultInArg0: true, 23967 asm: s390x.AFMULS, 23968 reg: regInfo{ 23969 inputs: []inputInfo{ 23970 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23971 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23972 }, 23973 outputs: []outputInfo{ 23974 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23975 }, 23976 }, 23977 }, 23978 { 23979 name: "FMUL", 23980 argLen: 2, 23981 commutative: true, 23982 resultInArg0: true, 23983 asm: s390x.AFMUL, 23984 reg: regInfo{ 23985 inputs: []inputInfo{ 23986 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23987 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23988 }, 23989 outputs: []outputInfo{ 23990 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 23991 }, 23992 }, 23993 }, 23994 { 23995 name: "FDIVS", 23996 argLen: 2, 23997 resultInArg0: true, 23998 asm: s390x.AFDIVS, 23999 reg: regInfo{ 24000 inputs: []inputInfo{ 24001 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24002 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24003 }, 24004 outputs: []outputInfo{ 24005 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24006 }, 24007 }, 24008 }, 24009 { 24010 name: "FDIV", 24011 argLen: 2, 24012 resultInArg0: true, 24013 asm: s390x.AFDIV, 24014 reg: regInfo{ 24015 inputs: []inputInfo{ 24016 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24017 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24018 }, 24019 outputs: []outputInfo{ 24020 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24021 }, 24022 }, 24023 }, 24024 { 24025 name: "FNEGS", 24026 argLen: 1, 24027 clobberFlags: true, 24028 asm: s390x.AFNEGS, 24029 reg: regInfo{ 24030 inputs: []inputInfo{ 24031 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24032 }, 24033 outputs: []outputInfo{ 24034 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24035 }, 24036 }, 24037 }, 24038 { 24039 name: "FNEG", 24040 argLen: 1, 24041 clobberFlags: true, 24042 asm: s390x.AFNEG, 24043 reg: regInfo{ 24044 inputs: []inputInfo{ 24045 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24046 }, 24047 outputs: []outputInfo{ 24048 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24049 }, 24050 }, 24051 }, 24052 { 24053 name: "FMADDS", 24054 argLen: 3, 24055 resultInArg0: true, 24056 asm: s390x.AFMADDS, 24057 reg: regInfo{ 24058 inputs: []inputInfo{ 24059 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24060 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24061 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24062 }, 24063 outputs: []outputInfo{ 24064 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24065 }, 24066 }, 24067 }, 24068 { 24069 name: "FMADD", 24070 argLen: 3, 24071 resultInArg0: true, 24072 asm: s390x.AFMADD, 24073 reg: regInfo{ 24074 inputs: []inputInfo{ 24075 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24076 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24077 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24078 }, 24079 outputs: []outputInfo{ 24080 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24081 }, 24082 }, 24083 }, 24084 { 24085 name: "FMSUBS", 24086 argLen: 3, 24087 resultInArg0: true, 24088 asm: s390x.AFMSUBS, 24089 reg: regInfo{ 24090 inputs: []inputInfo{ 24091 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24092 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24093 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24094 }, 24095 outputs: []outputInfo{ 24096 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24097 }, 24098 }, 24099 }, 24100 { 24101 name: "FMSUB", 24102 argLen: 3, 24103 resultInArg0: true, 24104 asm: s390x.AFMSUB, 24105 reg: regInfo{ 24106 inputs: []inputInfo{ 24107 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24108 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24109 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24110 }, 24111 outputs: []outputInfo{ 24112 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24113 }, 24114 }, 24115 }, 24116 { 24117 name: "LPDFR", 24118 argLen: 1, 24119 asm: s390x.ALPDFR, 24120 reg: regInfo{ 24121 inputs: []inputInfo{ 24122 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24123 }, 24124 outputs: []outputInfo{ 24125 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24126 }, 24127 }, 24128 }, 24129 { 24130 name: "LNDFR", 24131 argLen: 1, 24132 asm: s390x.ALNDFR, 24133 reg: regInfo{ 24134 inputs: []inputInfo{ 24135 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24136 }, 24137 outputs: []outputInfo{ 24138 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24139 }, 24140 }, 24141 }, 24142 { 24143 name: "CPSDR", 24144 argLen: 2, 24145 asm: s390x.ACPSDR, 24146 reg: regInfo{ 24147 inputs: []inputInfo{ 24148 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24149 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24150 }, 24151 outputs: []outputInfo{ 24152 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24153 }, 24154 }, 24155 }, 24156 { 24157 name: "FIDBR", 24158 auxType: auxInt8, 24159 argLen: 1, 24160 asm: s390x.AFIDBR, 24161 reg: regInfo{ 24162 inputs: []inputInfo{ 24163 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24164 }, 24165 outputs: []outputInfo{ 24166 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24167 }, 24168 }, 24169 }, 24170 { 24171 name: "FMOVSload", 24172 auxType: auxSymOff, 24173 argLen: 2, 24174 faultOnNilArg0: true, 24175 symEffect: SymRead, 24176 asm: s390x.AFMOVS, 24177 reg: regInfo{ 24178 inputs: []inputInfo{ 24179 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 24180 }, 24181 outputs: []outputInfo{ 24182 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24183 }, 24184 }, 24185 }, 24186 { 24187 name: "FMOVDload", 24188 auxType: auxSymOff, 24189 argLen: 2, 24190 faultOnNilArg0: true, 24191 symEffect: SymRead, 24192 asm: s390x.AFMOVD, 24193 reg: regInfo{ 24194 inputs: []inputInfo{ 24195 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 24196 }, 24197 outputs: []outputInfo{ 24198 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24199 }, 24200 }, 24201 }, 24202 { 24203 name: "FMOVSconst", 24204 auxType: auxFloat32, 24205 argLen: 0, 24206 rematerializeable: true, 24207 asm: s390x.AFMOVS, 24208 reg: regInfo{ 24209 outputs: []outputInfo{ 24210 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24211 }, 24212 }, 24213 }, 24214 { 24215 name: "FMOVDconst", 24216 auxType: auxFloat64, 24217 argLen: 0, 24218 rematerializeable: true, 24219 asm: s390x.AFMOVD, 24220 reg: regInfo{ 24221 outputs: []outputInfo{ 24222 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24223 }, 24224 }, 24225 }, 24226 { 24227 name: "FMOVSloadidx", 24228 auxType: auxSymOff, 24229 argLen: 3, 24230 symEffect: SymRead, 24231 asm: s390x.AFMOVS, 24232 reg: regInfo{ 24233 inputs: []inputInfo{ 24234 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24235 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24236 }, 24237 outputs: []outputInfo{ 24238 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24239 }, 24240 }, 24241 }, 24242 { 24243 name: "FMOVDloadidx", 24244 auxType: auxSymOff, 24245 argLen: 3, 24246 symEffect: SymRead, 24247 asm: s390x.AFMOVD, 24248 reg: regInfo{ 24249 inputs: []inputInfo{ 24250 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24251 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24252 }, 24253 outputs: []outputInfo{ 24254 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24255 }, 24256 }, 24257 }, 24258 { 24259 name: "FMOVSstore", 24260 auxType: auxSymOff, 24261 argLen: 3, 24262 faultOnNilArg0: true, 24263 symEffect: SymWrite, 24264 asm: s390x.AFMOVS, 24265 reg: regInfo{ 24266 inputs: []inputInfo{ 24267 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 24268 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24269 }, 24270 }, 24271 }, 24272 { 24273 name: "FMOVDstore", 24274 auxType: auxSymOff, 24275 argLen: 3, 24276 faultOnNilArg0: true, 24277 symEffect: SymWrite, 24278 asm: s390x.AFMOVD, 24279 reg: regInfo{ 24280 inputs: []inputInfo{ 24281 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 24282 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24283 }, 24284 }, 24285 }, 24286 { 24287 name: "FMOVSstoreidx", 24288 auxType: auxSymOff, 24289 argLen: 4, 24290 symEffect: SymWrite, 24291 asm: s390x.AFMOVS, 24292 reg: regInfo{ 24293 inputs: []inputInfo{ 24294 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24295 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24296 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24297 }, 24298 }, 24299 }, 24300 { 24301 name: "FMOVDstoreidx", 24302 auxType: auxSymOff, 24303 argLen: 4, 24304 symEffect: SymWrite, 24305 asm: s390x.AFMOVD, 24306 reg: regInfo{ 24307 inputs: []inputInfo{ 24308 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24309 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24310 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 24311 }, 24312 }, 24313 }, 24314 { 24315 name: "ADD", 24316 argLen: 2, 24317 commutative: true, 24318 clobberFlags: true, 24319 asm: s390x.AADD, 24320 reg: regInfo{ 24321 inputs: []inputInfo{ 24322 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24323 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24324 }, 24325 outputs: []outputInfo{ 24326 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24327 }, 24328 }, 24329 }, 24330 { 24331 name: "ADDW", 24332 argLen: 2, 24333 commutative: true, 24334 clobberFlags: true, 24335 asm: s390x.AADDW, 24336 reg: regInfo{ 24337 inputs: []inputInfo{ 24338 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24339 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24340 }, 24341 outputs: []outputInfo{ 24342 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24343 }, 24344 }, 24345 }, 24346 { 24347 name: "ADDconst", 24348 auxType: auxInt32, 24349 argLen: 1, 24350 clobberFlags: true, 24351 asm: s390x.AADD, 24352 reg: regInfo{ 24353 inputs: []inputInfo{ 24354 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24355 }, 24356 outputs: []outputInfo{ 24357 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24358 }, 24359 }, 24360 }, 24361 { 24362 name: "ADDWconst", 24363 auxType: auxInt32, 24364 argLen: 1, 24365 clobberFlags: true, 24366 asm: s390x.AADDW, 24367 reg: regInfo{ 24368 inputs: []inputInfo{ 24369 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24370 }, 24371 outputs: []outputInfo{ 24372 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24373 }, 24374 }, 24375 }, 24376 { 24377 name: "ADDload", 24378 auxType: auxSymOff, 24379 argLen: 3, 24380 resultInArg0: true, 24381 clobberFlags: true, 24382 faultOnNilArg1: true, 24383 symEffect: SymRead, 24384 asm: s390x.AADD, 24385 reg: regInfo{ 24386 inputs: []inputInfo{ 24387 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24388 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24389 }, 24390 outputs: []outputInfo{ 24391 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24392 }, 24393 }, 24394 }, 24395 { 24396 name: "ADDWload", 24397 auxType: auxSymOff, 24398 argLen: 3, 24399 resultInArg0: true, 24400 clobberFlags: true, 24401 faultOnNilArg1: true, 24402 symEffect: SymRead, 24403 asm: s390x.AADDW, 24404 reg: regInfo{ 24405 inputs: []inputInfo{ 24406 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24407 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24408 }, 24409 outputs: []outputInfo{ 24410 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24411 }, 24412 }, 24413 }, 24414 { 24415 name: "SUB", 24416 argLen: 2, 24417 clobberFlags: true, 24418 asm: s390x.ASUB, 24419 reg: regInfo{ 24420 inputs: []inputInfo{ 24421 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24422 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24423 }, 24424 outputs: []outputInfo{ 24425 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24426 }, 24427 }, 24428 }, 24429 { 24430 name: "SUBW", 24431 argLen: 2, 24432 clobberFlags: true, 24433 asm: s390x.ASUBW, 24434 reg: regInfo{ 24435 inputs: []inputInfo{ 24436 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24437 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24438 }, 24439 outputs: []outputInfo{ 24440 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24441 }, 24442 }, 24443 }, 24444 { 24445 name: "SUBconst", 24446 auxType: auxInt32, 24447 argLen: 1, 24448 resultInArg0: true, 24449 clobberFlags: true, 24450 asm: s390x.ASUB, 24451 reg: regInfo{ 24452 inputs: []inputInfo{ 24453 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24454 }, 24455 outputs: []outputInfo{ 24456 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24457 }, 24458 }, 24459 }, 24460 { 24461 name: "SUBWconst", 24462 auxType: auxInt32, 24463 argLen: 1, 24464 resultInArg0: true, 24465 clobberFlags: true, 24466 asm: s390x.ASUBW, 24467 reg: regInfo{ 24468 inputs: []inputInfo{ 24469 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24470 }, 24471 outputs: []outputInfo{ 24472 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24473 }, 24474 }, 24475 }, 24476 { 24477 name: "SUBload", 24478 auxType: auxSymOff, 24479 argLen: 3, 24480 resultInArg0: true, 24481 clobberFlags: true, 24482 faultOnNilArg1: true, 24483 symEffect: SymRead, 24484 asm: s390x.ASUB, 24485 reg: regInfo{ 24486 inputs: []inputInfo{ 24487 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24488 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24489 }, 24490 outputs: []outputInfo{ 24491 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24492 }, 24493 }, 24494 }, 24495 { 24496 name: "SUBWload", 24497 auxType: auxSymOff, 24498 argLen: 3, 24499 resultInArg0: true, 24500 clobberFlags: true, 24501 faultOnNilArg1: true, 24502 symEffect: SymRead, 24503 asm: s390x.ASUBW, 24504 reg: regInfo{ 24505 inputs: []inputInfo{ 24506 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24507 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24508 }, 24509 outputs: []outputInfo{ 24510 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24511 }, 24512 }, 24513 }, 24514 { 24515 name: "MULLD", 24516 argLen: 2, 24517 commutative: true, 24518 resultInArg0: true, 24519 clobberFlags: true, 24520 asm: s390x.AMULLD, 24521 reg: regInfo{ 24522 inputs: []inputInfo{ 24523 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24524 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24525 }, 24526 outputs: []outputInfo{ 24527 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24528 }, 24529 }, 24530 }, 24531 { 24532 name: "MULLW", 24533 argLen: 2, 24534 commutative: true, 24535 resultInArg0: true, 24536 clobberFlags: true, 24537 asm: s390x.AMULLW, 24538 reg: regInfo{ 24539 inputs: []inputInfo{ 24540 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24541 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24542 }, 24543 outputs: []outputInfo{ 24544 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24545 }, 24546 }, 24547 }, 24548 { 24549 name: "MULLDconst", 24550 auxType: auxInt32, 24551 argLen: 1, 24552 resultInArg0: true, 24553 clobberFlags: true, 24554 asm: s390x.AMULLD, 24555 reg: regInfo{ 24556 inputs: []inputInfo{ 24557 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24558 }, 24559 outputs: []outputInfo{ 24560 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24561 }, 24562 }, 24563 }, 24564 { 24565 name: "MULLWconst", 24566 auxType: auxInt32, 24567 argLen: 1, 24568 resultInArg0: true, 24569 clobberFlags: true, 24570 asm: s390x.AMULLW, 24571 reg: regInfo{ 24572 inputs: []inputInfo{ 24573 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24574 }, 24575 outputs: []outputInfo{ 24576 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24577 }, 24578 }, 24579 }, 24580 { 24581 name: "MULLDload", 24582 auxType: auxSymOff, 24583 argLen: 3, 24584 resultInArg0: true, 24585 clobberFlags: true, 24586 faultOnNilArg1: true, 24587 symEffect: SymRead, 24588 asm: s390x.AMULLD, 24589 reg: regInfo{ 24590 inputs: []inputInfo{ 24591 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24592 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24593 }, 24594 outputs: []outputInfo{ 24595 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24596 }, 24597 }, 24598 }, 24599 { 24600 name: "MULLWload", 24601 auxType: auxSymOff, 24602 argLen: 3, 24603 resultInArg0: true, 24604 clobberFlags: true, 24605 faultOnNilArg1: true, 24606 symEffect: SymRead, 24607 asm: s390x.AMULLW, 24608 reg: regInfo{ 24609 inputs: []inputInfo{ 24610 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24611 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24612 }, 24613 outputs: []outputInfo{ 24614 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24615 }, 24616 }, 24617 }, 24618 { 24619 name: "MULHD", 24620 argLen: 2, 24621 commutative: true, 24622 resultInArg0: true, 24623 clobberFlags: true, 24624 asm: s390x.AMULHD, 24625 reg: regInfo{ 24626 inputs: []inputInfo{ 24627 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24628 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24629 }, 24630 clobbers: 2048, // R11 24631 outputs: []outputInfo{ 24632 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24633 }, 24634 }, 24635 }, 24636 { 24637 name: "MULHDU", 24638 argLen: 2, 24639 commutative: true, 24640 resultInArg0: true, 24641 clobberFlags: true, 24642 asm: s390x.AMULHDU, 24643 reg: regInfo{ 24644 inputs: []inputInfo{ 24645 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24646 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24647 }, 24648 clobbers: 2048, // R11 24649 outputs: []outputInfo{ 24650 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24651 }, 24652 }, 24653 }, 24654 { 24655 name: "DIVD", 24656 argLen: 2, 24657 resultInArg0: true, 24658 clobberFlags: true, 24659 asm: s390x.ADIVD, 24660 reg: regInfo{ 24661 inputs: []inputInfo{ 24662 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24663 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24664 }, 24665 clobbers: 2048, // R11 24666 outputs: []outputInfo{ 24667 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24668 }, 24669 }, 24670 }, 24671 { 24672 name: "DIVW", 24673 argLen: 2, 24674 resultInArg0: true, 24675 clobberFlags: true, 24676 asm: s390x.ADIVW, 24677 reg: regInfo{ 24678 inputs: []inputInfo{ 24679 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24680 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24681 }, 24682 clobbers: 2048, // R11 24683 outputs: []outputInfo{ 24684 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24685 }, 24686 }, 24687 }, 24688 { 24689 name: "DIVDU", 24690 argLen: 2, 24691 resultInArg0: true, 24692 clobberFlags: true, 24693 asm: s390x.ADIVDU, 24694 reg: regInfo{ 24695 inputs: []inputInfo{ 24696 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24697 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24698 }, 24699 clobbers: 2048, // R11 24700 outputs: []outputInfo{ 24701 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24702 }, 24703 }, 24704 }, 24705 { 24706 name: "DIVWU", 24707 argLen: 2, 24708 resultInArg0: true, 24709 clobberFlags: true, 24710 asm: s390x.ADIVWU, 24711 reg: regInfo{ 24712 inputs: []inputInfo{ 24713 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24714 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24715 }, 24716 clobbers: 2048, // R11 24717 outputs: []outputInfo{ 24718 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24719 }, 24720 }, 24721 }, 24722 { 24723 name: "MODD", 24724 argLen: 2, 24725 resultInArg0: true, 24726 clobberFlags: true, 24727 asm: s390x.AMODD, 24728 reg: regInfo{ 24729 inputs: []inputInfo{ 24730 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24731 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24732 }, 24733 clobbers: 2048, // R11 24734 outputs: []outputInfo{ 24735 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24736 }, 24737 }, 24738 }, 24739 { 24740 name: "MODW", 24741 argLen: 2, 24742 resultInArg0: true, 24743 clobberFlags: true, 24744 asm: s390x.AMODW, 24745 reg: regInfo{ 24746 inputs: []inputInfo{ 24747 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24748 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24749 }, 24750 clobbers: 2048, // R11 24751 outputs: []outputInfo{ 24752 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24753 }, 24754 }, 24755 }, 24756 { 24757 name: "MODDU", 24758 argLen: 2, 24759 resultInArg0: true, 24760 clobberFlags: true, 24761 asm: s390x.AMODDU, 24762 reg: regInfo{ 24763 inputs: []inputInfo{ 24764 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24765 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24766 }, 24767 clobbers: 2048, // R11 24768 outputs: []outputInfo{ 24769 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24770 }, 24771 }, 24772 }, 24773 { 24774 name: "MODWU", 24775 argLen: 2, 24776 resultInArg0: true, 24777 clobberFlags: true, 24778 asm: s390x.AMODWU, 24779 reg: regInfo{ 24780 inputs: []inputInfo{ 24781 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24782 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24783 }, 24784 clobbers: 2048, // R11 24785 outputs: []outputInfo{ 24786 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 24787 }, 24788 }, 24789 }, 24790 { 24791 name: "AND", 24792 argLen: 2, 24793 commutative: true, 24794 clobberFlags: true, 24795 asm: s390x.AAND, 24796 reg: regInfo{ 24797 inputs: []inputInfo{ 24798 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24799 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24800 }, 24801 outputs: []outputInfo{ 24802 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24803 }, 24804 }, 24805 }, 24806 { 24807 name: "ANDW", 24808 argLen: 2, 24809 commutative: true, 24810 clobberFlags: true, 24811 asm: s390x.AANDW, 24812 reg: regInfo{ 24813 inputs: []inputInfo{ 24814 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24815 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24816 }, 24817 outputs: []outputInfo{ 24818 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24819 }, 24820 }, 24821 }, 24822 { 24823 name: "ANDconst", 24824 auxType: auxInt64, 24825 argLen: 1, 24826 resultInArg0: true, 24827 clobberFlags: true, 24828 asm: s390x.AAND, 24829 reg: regInfo{ 24830 inputs: []inputInfo{ 24831 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24832 }, 24833 outputs: []outputInfo{ 24834 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24835 }, 24836 }, 24837 }, 24838 { 24839 name: "ANDWconst", 24840 auxType: auxInt32, 24841 argLen: 1, 24842 resultInArg0: true, 24843 clobberFlags: true, 24844 asm: s390x.AANDW, 24845 reg: regInfo{ 24846 inputs: []inputInfo{ 24847 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24848 }, 24849 outputs: []outputInfo{ 24850 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24851 }, 24852 }, 24853 }, 24854 { 24855 name: "ANDload", 24856 auxType: auxSymOff, 24857 argLen: 3, 24858 resultInArg0: true, 24859 clobberFlags: true, 24860 faultOnNilArg1: true, 24861 symEffect: SymRead, 24862 asm: s390x.AAND, 24863 reg: regInfo{ 24864 inputs: []inputInfo{ 24865 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24866 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24867 }, 24868 outputs: []outputInfo{ 24869 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24870 }, 24871 }, 24872 }, 24873 { 24874 name: "ANDWload", 24875 auxType: auxSymOff, 24876 argLen: 3, 24877 resultInArg0: true, 24878 clobberFlags: true, 24879 faultOnNilArg1: true, 24880 symEffect: SymRead, 24881 asm: s390x.AANDW, 24882 reg: regInfo{ 24883 inputs: []inputInfo{ 24884 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24885 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24886 }, 24887 outputs: []outputInfo{ 24888 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24889 }, 24890 }, 24891 }, 24892 { 24893 name: "OR", 24894 argLen: 2, 24895 commutative: true, 24896 clobberFlags: true, 24897 asm: s390x.AOR, 24898 reg: regInfo{ 24899 inputs: []inputInfo{ 24900 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24901 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24902 }, 24903 outputs: []outputInfo{ 24904 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24905 }, 24906 }, 24907 }, 24908 { 24909 name: "ORW", 24910 argLen: 2, 24911 commutative: true, 24912 clobberFlags: true, 24913 asm: s390x.AORW, 24914 reg: regInfo{ 24915 inputs: []inputInfo{ 24916 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24917 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24918 }, 24919 outputs: []outputInfo{ 24920 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24921 }, 24922 }, 24923 }, 24924 { 24925 name: "ORconst", 24926 auxType: auxInt64, 24927 argLen: 1, 24928 resultInArg0: true, 24929 clobberFlags: true, 24930 asm: s390x.AOR, 24931 reg: regInfo{ 24932 inputs: []inputInfo{ 24933 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24934 }, 24935 outputs: []outputInfo{ 24936 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24937 }, 24938 }, 24939 }, 24940 { 24941 name: "ORWconst", 24942 auxType: auxInt32, 24943 argLen: 1, 24944 resultInArg0: true, 24945 clobberFlags: true, 24946 asm: s390x.AORW, 24947 reg: regInfo{ 24948 inputs: []inputInfo{ 24949 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24950 }, 24951 outputs: []outputInfo{ 24952 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24953 }, 24954 }, 24955 }, 24956 { 24957 name: "ORload", 24958 auxType: auxSymOff, 24959 argLen: 3, 24960 resultInArg0: true, 24961 clobberFlags: true, 24962 faultOnNilArg1: true, 24963 symEffect: SymRead, 24964 asm: s390x.AOR, 24965 reg: regInfo{ 24966 inputs: []inputInfo{ 24967 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24968 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24969 }, 24970 outputs: []outputInfo{ 24971 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24972 }, 24973 }, 24974 }, 24975 { 24976 name: "ORWload", 24977 auxType: auxSymOff, 24978 argLen: 3, 24979 resultInArg0: true, 24980 clobberFlags: true, 24981 faultOnNilArg1: true, 24982 symEffect: SymRead, 24983 asm: s390x.AORW, 24984 reg: regInfo{ 24985 inputs: []inputInfo{ 24986 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24987 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 24988 }, 24989 outputs: []outputInfo{ 24990 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 24991 }, 24992 }, 24993 }, 24994 { 24995 name: "XOR", 24996 argLen: 2, 24997 commutative: true, 24998 clobberFlags: true, 24999 asm: s390x.AXOR, 25000 reg: regInfo{ 25001 inputs: []inputInfo{ 25002 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25003 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25004 }, 25005 outputs: []outputInfo{ 25006 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25007 }, 25008 }, 25009 }, 25010 { 25011 name: "XORW", 25012 argLen: 2, 25013 commutative: true, 25014 clobberFlags: true, 25015 asm: s390x.AXORW, 25016 reg: regInfo{ 25017 inputs: []inputInfo{ 25018 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25019 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25020 }, 25021 outputs: []outputInfo{ 25022 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25023 }, 25024 }, 25025 }, 25026 { 25027 name: "XORconst", 25028 auxType: auxInt64, 25029 argLen: 1, 25030 resultInArg0: true, 25031 clobberFlags: true, 25032 asm: s390x.AXOR, 25033 reg: regInfo{ 25034 inputs: []inputInfo{ 25035 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25036 }, 25037 outputs: []outputInfo{ 25038 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25039 }, 25040 }, 25041 }, 25042 { 25043 name: "XORWconst", 25044 auxType: auxInt32, 25045 argLen: 1, 25046 resultInArg0: true, 25047 clobberFlags: true, 25048 asm: s390x.AXORW, 25049 reg: regInfo{ 25050 inputs: []inputInfo{ 25051 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25052 }, 25053 outputs: []outputInfo{ 25054 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25055 }, 25056 }, 25057 }, 25058 { 25059 name: "XORload", 25060 auxType: auxSymOff, 25061 argLen: 3, 25062 resultInArg0: true, 25063 clobberFlags: true, 25064 faultOnNilArg1: true, 25065 symEffect: SymRead, 25066 asm: s390x.AXOR, 25067 reg: regInfo{ 25068 inputs: []inputInfo{ 25069 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25070 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25071 }, 25072 outputs: []outputInfo{ 25073 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25074 }, 25075 }, 25076 }, 25077 { 25078 name: "XORWload", 25079 auxType: auxSymOff, 25080 argLen: 3, 25081 resultInArg0: true, 25082 clobberFlags: true, 25083 faultOnNilArg1: true, 25084 symEffect: SymRead, 25085 asm: s390x.AXORW, 25086 reg: regInfo{ 25087 inputs: []inputInfo{ 25088 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25089 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25090 }, 25091 outputs: []outputInfo{ 25092 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25093 }, 25094 }, 25095 }, 25096 { 25097 name: "CMP", 25098 argLen: 2, 25099 asm: s390x.ACMP, 25100 reg: regInfo{ 25101 inputs: []inputInfo{ 25102 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25103 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25104 }, 25105 }, 25106 }, 25107 { 25108 name: "CMPW", 25109 argLen: 2, 25110 asm: s390x.ACMPW, 25111 reg: regInfo{ 25112 inputs: []inputInfo{ 25113 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25114 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25115 }, 25116 }, 25117 }, 25118 { 25119 name: "CMPU", 25120 argLen: 2, 25121 asm: s390x.ACMPU, 25122 reg: regInfo{ 25123 inputs: []inputInfo{ 25124 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25125 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25126 }, 25127 }, 25128 }, 25129 { 25130 name: "CMPWU", 25131 argLen: 2, 25132 asm: s390x.ACMPWU, 25133 reg: regInfo{ 25134 inputs: []inputInfo{ 25135 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25136 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25137 }, 25138 }, 25139 }, 25140 { 25141 name: "CMPconst", 25142 auxType: auxInt32, 25143 argLen: 1, 25144 asm: s390x.ACMP, 25145 reg: regInfo{ 25146 inputs: []inputInfo{ 25147 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25148 }, 25149 }, 25150 }, 25151 { 25152 name: "CMPWconst", 25153 auxType: auxInt32, 25154 argLen: 1, 25155 asm: s390x.ACMPW, 25156 reg: regInfo{ 25157 inputs: []inputInfo{ 25158 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25159 }, 25160 }, 25161 }, 25162 { 25163 name: "CMPUconst", 25164 auxType: auxInt32, 25165 argLen: 1, 25166 asm: s390x.ACMPU, 25167 reg: regInfo{ 25168 inputs: []inputInfo{ 25169 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25170 }, 25171 }, 25172 }, 25173 { 25174 name: "CMPWUconst", 25175 auxType: auxInt32, 25176 argLen: 1, 25177 asm: s390x.ACMPWU, 25178 reg: regInfo{ 25179 inputs: []inputInfo{ 25180 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25181 }, 25182 }, 25183 }, 25184 { 25185 name: "FCMPS", 25186 argLen: 2, 25187 asm: s390x.ACEBR, 25188 reg: regInfo{ 25189 inputs: []inputInfo{ 25190 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25191 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25192 }, 25193 }, 25194 }, 25195 { 25196 name: "FCMP", 25197 argLen: 2, 25198 asm: s390x.AFCMPU, 25199 reg: regInfo{ 25200 inputs: []inputInfo{ 25201 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25202 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25203 }, 25204 }, 25205 }, 25206 { 25207 name: "SLD", 25208 argLen: 2, 25209 asm: s390x.ASLD, 25210 reg: regInfo{ 25211 inputs: []inputInfo{ 25212 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25213 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25214 }, 25215 outputs: []outputInfo{ 25216 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25217 }, 25218 }, 25219 }, 25220 { 25221 name: "SLW", 25222 argLen: 2, 25223 asm: s390x.ASLW, 25224 reg: regInfo{ 25225 inputs: []inputInfo{ 25226 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25227 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25228 }, 25229 outputs: []outputInfo{ 25230 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25231 }, 25232 }, 25233 }, 25234 { 25235 name: "SLDconst", 25236 auxType: auxInt8, 25237 argLen: 1, 25238 asm: s390x.ASLD, 25239 reg: regInfo{ 25240 inputs: []inputInfo{ 25241 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25242 }, 25243 outputs: []outputInfo{ 25244 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25245 }, 25246 }, 25247 }, 25248 { 25249 name: "SLWconst", 25250 auxType: auxInt8, 25251 argLen: 1, 25252 asm: s390x.ASLW, 25253 reg: regInfo{ 25254 inputs: []inputInfo{ 25255 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25256 }, 25257 outputs: []outputInfo{ 25258 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25259 }, 25260 }, 25261 }, 25262 { 25263 name: "SRD", 25264 argLen: 2, 25265 asm: s390x.ASRD, 25266 reg: regInfo{ 25267 inputs: []inputInfo{ 25268 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25269 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25270 }, 25271 outputs: []outputInfo{ 25272 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25273 }, 25274 }, 25275 }, 25276 { 25277 name: "SRW", 25278 argLen: 2, 25279 asm: s390x.ASRW, 25280 reg: regInfo{ 25281 inputs: []inputInfo{ 25282 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25283 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25284 }, 25285 outputs: []outputInfo{ 25286 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25287 }, 25288 }, 25289 }, 25290 { 25291 name: "SRDconst", 25292 auxType: auxInt8, 25293 argLen: 1, 25294 asm: s390x.ASRD, 25295 reg: regInfo{ 25296 inputs: []inputInfo{ 25297 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25298 }, 25299 outputs: []outputInfo{ 25300 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25301 }, 25302 }, 25303 }, 25304 { 25305 name: "SRWconst", 25306 auxType: auxInt8, 25307 argLen: 1, 25308 asm: s390x.ASRW, 25309 reg: regInfo{ 25310 inputs: []inputInfo{ 25311 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25312 }, 25313 outputs: []outputInfo{ 25314 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25315 }, 25316 }, 25317 }, 25318 { 25319 name: "SRAD", 25320 argLen: 2, 25321 clobberFlags: true, 25322 asm: s390x.ASRAD, 25323 reg: regInfo{ 25324 inputs: []inputInfo{ 25325 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25326 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25327 }, 25328 outputs: []outputInfo{ 25329 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25330 }, 25331 }, 25332 }, 25333 { 25334 name: "SRAW", 25335 argLen: 2, 25336 clobberFlags: true, 25337 asm: s390x.ASRAW, 25338 reg: regInfo{ 25339 inputs: []inputInfo{ 25340 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25341 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25342 }, 25343 outputs: []outputInfo{ 25344 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25345 }, 25346 }, 25347 }, 25348 { 25349 name: "SRADconst", 25350 auxType: auxInt8, 25351 argLen: 1, 25352 clobberFlags: true, 25353 asm: s390x.ASRAD, 25354 reg: regInfo{ 25355 inputs: []inputInfo{ 25356 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25357 }, 25358 outputs: []outputInfo{ 25359 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25360 }, 25361 }, 25362 }, 25363 { 25364 name: "SRAWconst", 25365 auxType: auxInt8, 25366 argLen: 1, 25367 clobberFlags: true, 25368 asm: s390x.ASRAW, 25369 reg: regInfo{ 25370 inputs: []inputInfo{ 25371 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25372 }, 25373 outputs: []outputInfo{ 25374 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25375 }, 25376 }, 25377 }, 25378 { 25379 name: "RLLG", 25380 argLen: 2, 25381 asm: s390x.ARLLG, 25382 reg: regInfo{ 25383 inputs: []inputInfo{ 25384 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25385 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25386 }, 25387 outputs: []outputInfo{ 25388 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25389 }, 25390 }, 25391 }, 25392 { 25393 name: "RLL", 25394 argLen: 2, 25395 asm: s390x.ARLL, 25396 reg: regInfo{ 25397 inputs: []inputInfo{ 25398 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25399 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25400 }, 25401 outputs: []outputInfo{ 25402 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25403 }, 25404 }, 25405 }, 25406 { 25407 name: "RLLGconst", 25408 auxType: auxInt8, 25409 argLen: 1, 25410 asm: s390x.ARLLG, 25411 reg: regInfo{ 25412 inputs: []inputInfo{ 25413 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25414 }, 25415 outputs: []outputInfo{ 25416 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25417 }, 25418 }, 25419 }, 25420 { 25421 name: "RLLconst", 25422 auxType: auxInt8, 25423 argLen: 1, 25424 asm: s390x.ARLL, 25425 reg: regInfo{ 25426 inputs: []inputInfo{ 25427 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25428 }, 25429 outputs: []outputInfo{ 25430 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25431 }, 25432 }, 25433 }, 25434 { 25435 name: "NEG", 25436 argLen: 1, 25437 clobberFlags: true, 25438 asm: s390x.ANEG, 25439 reg: regInfo{ 25440 inputs: []inputInfo{ 25441 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25442 }, 25443 outputs: []outputInfo{ 25444 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25445 }, 25446 }, 25447 }, 25448 { 25449 name: "NEGW", 25450 argLen: 1, 25451 clobberFlags: true, 25452 asm: s390x.ANEGW, 25453 reg: regInfo{ 25454 inputs: []inputInfo{ 25455 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25456 }, 25457 outputs: []outputInfo{ 25458 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25459 }, 25460 }, 25461 }, 25462 { 25463 name: "NOT", 25464 argLen: 1, 25465 resultInArg0: true, 25466 clobberFlags: true, 25467 reg: regInfo{ 25468 inputs: []inputInfo{ 25469 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25470 }, 25471 outputs: []outputInfo{ 25472 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25473 }, 25474 }, 25475 }, 25476 { 25477 name: "NOTW", 25478 argLen: 1, 25479 resultInArg0: true, 25480 clobberFlags: true, 25481 reg: regInfo{ 25482 inputs: []inputInfo{ 25483 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25484 }, 25485 outputs: []outputInfo{ 25486 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25487 }, 25488 }, 25489 }, 25490 { 25491 name: "FSQRT", 25492 argLen: 1, 25493 asm: s390x.AFSQRT, 25494 reg: regInfo{ 25495 inputs: []inputInfo{ 25496 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25497 }, 25498 outputs: []outputInfo{ 25499 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25500 }, 25501 }, 25502 }, 25503 { 25504 name: "MOVDEQ", 25505 argLen: 3, 25506 resultInArg0: true, 25507 asm: s390x.AMOVDEQ, 25508 reg: regInfo{ 25509 inputs: []inputInfo{ 25510 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25511 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25512 }, 25513 outputs: []outputInfo{ 25514 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25515 }, 25516 }, 25517 }, 25518 { 25519 name: "MOVDNE", 25520 argLen: 3, 25521 resultInArg0: true, 25522 asm: s390x.AMOVDNE, 25523 reg: regInfo{ 25524 inputs: []inputInfo{ 25525 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25526 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25527 }, 25528 outputs: []outputInfo{ 25529 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25530 }, 25531 }, 25532 }, 25533 { 25534 name: "MOVDLT", 25535 argLen: 3, 25536 resultInArg0: true, 25537 asm: s390x.AMOVDLT, 25538 reg: regInfo{ 25539 inputs: []inputInfo{ 25540 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25541 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25542 }, 25543 outputs: []outputInfo{ 25544 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25545 }, 25546 }, 25547 }, 25548 { 25549 name: "MOVDLE", 25550 argLen: 3, 25551 resultInArg0: true, 25552 asm: s390x.AMOVDLE, 25553 reg: regInfo{ 25554 inputs: []inputInfo{ 25555 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25556 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25557 }, 25558 outputs: []outputInfo{ 25559 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25560 }, 25561 }, 25562 }, 25563 { 25564 name: "MOVDGT", 25565 argLen: 3, 25566 resultInArg0: true, 25567 asm: s390x.AMOVDGT, 25568 reg: regInfo{ 25569 inputs: []inputInfo{ 25570 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25571 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25572 }, 25573 outputs: []outputInfo{ 25574 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25575 }, 25576 }, 25577 }, 25578 { 25579 name: "MOVDGE", 25580 argLen: 3, 25581 resultInArg0: true, 25582 asm: s390x.AMOVDGE, 25583 reg: regInfo{ 25584 inputs: []inputInfo{ 25585 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25586 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25587 }, 25588 outputs: []outputInfo{ 25589 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25590 }, 25591 }, 25592 }, 25593 { 25594 name: "MOVDGTnoinv", 25595 argLen: 3, 25596 resultInArg0: true, 25597 asm: s390x.AMOVDGT, 25598 reg: regInfo{ 25599 inputs: []inputInfo{ 25600 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25601 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25602 }, 25603 outputs: []outputInfo{ 25604 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25605 }, 25606 }, 25607 }, 25608 { 25609 name: "MOVDGEnoinv", 25610 argLen: 3, 25611 resultInArg0: true, 25612 asm: s390x.AMOVDGE, 25613 reg: regInfo{ 25614 inputs: []inputInfo{ 25615 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25616 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25617 }, 25618 outputs: []outputInfo{ 25619 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25620 }, 25621 }, 25622 }, 25623 { 25624 name: "MOVBreg", 25625 argLen: 1, 25626 asm: s390x.AMOVB, 25627 reg: regInfo{ 25628 inputs: []inputInfo{ 25629 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25630 }, 25631 outputs: []outputInfo{ 25632 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25633 }, 25634 }, 25635 }, 25636 { 25637 name: "MOVBZreg", 25638 argLen: 1, 25639 asm: s390x.AMOVBZ, 25640 reg: regInfo{ 25641 inputs: []inputInfo{ 25642 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25643 }, 25644 outputs: []outputInfo{ 25645 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25646 }, 25647 }, 25648 }, 25649 { 25650 name: "MOVHreg", 25651 argLen: 1, 25652 asm: s390x.AMOVH, 25653 reg: regInfo{ 25654 inputs: []inputInfo{ 25655 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25656 }, 25657 outputs: []outputInfo{ 25658 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25659 }, 25660 }, 25661 }, 25662 { 25663 name: "MOVHZreg", 25664 argLen: 1, 25665 asm: s390x.AMOVHZ, 25666 reg: regInfo{ 25667 inputs: []inputInfo{ 25668 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25669 }, 25670 outputs: []outputInfo{ 25671 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25672 }, 25673 }, 25674 }, 25675 { 25676 name: "MOVWreg", 25677 argLen: 1, 25678 asm: s390x.AMOVW, 25679 reg: regInfo{ 25680 inputs: []inputInfo{ 25681 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25682 }, 25683 outputs: []outputInfo{ 25684 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25685 }, 25686 }, 25687 }, 25688 { 25689 name: "MOVWZreg", 25690 argLen: 1, 25691 asm: s390x.AMOVWZ, 25692 reg: regInfo{ 25693 inputs: []inputInfo{ 25694 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25695 }, 25696 outputs: []outputInfo{ 25697 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25698 }, 25699 }, 25700 }, 25701 { 25702 name: "MOVDreg", 25703 argLen: 1, 25704 asm: s390x.AMOVD, 25705 reg: regInfo{ 25706 inputs: []inputInfo{ 25707 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25708 }, 25709 outputs: []outputInfo{ 25710 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25711 }, 25712 }, 25713 }, 25714 { 25715 name: "MOVDnop", 25716 argLen: 1, 25717 resultInArg0: true, 25718 reg: regInfo{ 25719 inputs: []inputInfo{ 25720 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25721 }, 25722 outputs: []outputInfo{ 25723 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25724 }, 25725 }, 25726 }, 25727 { 25728 name: "MOVDconst", 25729 auxType: auxInt64, 25730 argLen: 0, 25731 rematerializeable: true, 25732 asm: s390x.AMOVD, 25733 reg: regInfo{ 25734 outputs: []outputInfo{ 25735 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25736 }, 25737 }, 25738 }, 25739 { 25740 name: "LDGR", 25741 argLen: 1, 25742 asm: s390x.ALDGR, 25743 reg: regInfo{ 25744 inputs: []inputInfo{ 25745 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25746 }, 25747 outputs: []outputInfo{ 25748 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25749 }, 25750 }, 25751 }, 25752 { 25753 name: "LGDR", 25754 argLen: 1, 25755 asm: s390x.ALGDR, 25756 reg: regInfo{ 25757 inputs: []inputInfo{ 25758 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25759 }, 25760 outputs: []outputInfo{ 25761 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25762 }, 25763 }, 25764 }, 25765 { 25766 name: "CFDBRA", 25767 argLen: 1, 25768 asm: s390x.ACFDBRA, 25769 reg: regInfo{ 25770 inputs: []inputInfo{ 25771 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25772 }, 25773 outputs: []outputInfo{ 25774 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25775 }, 25776 }, 25777 }, 25778 { 25779 name: "CGDBRA", 25780 argLen: 1, 25781 asm: s390x.ACGDBRA, 25782 reg: regInfo{ 25783 inputs: []inputInfo{ 25784 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25785 }, 25786 outputs: []outputInfo{ 25787 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25788 }, 25789 }, 25790 }, 25791 { 25792 name: "CFEBRA", 25793 argLen: 1, 25794 asm: s390x.ACFEBRA, 25795 reg: regInfo{ 25796 inputs: []inputInfo{ 25797 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25798 }, 25799 outputs: []outputInfo{ 25800 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25801 }, 25802 }, 25803 }, 25804 { 25805 name: "CGEBRA", 25806 argLen: 1, 25807 asm: s390x.ACGEBRA, 25808 reg: regInfo{ 25809 inputs: []inputInfo{ 25810 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25811 }, 25812 outputs: []outputInfo{ 25813 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25814 }, 25815 }, 25816 }, 25817 { 25818 name: "CEFBRA", 25819 argLen: 1, 25820 asm: s390x.ACEFBRA, 25821 reg: regInfo{ 25822 inputs: []inputInfo{ 25823 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25824 }, 25825 outputs: []outputInfo{ 25826 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25827 }, 25828 }, 25829 }, 25830 { 25831 name: "CDFBRA", 25832 argLen: 1, 25833 asm: s390x.ACDFBRA, 25834 reg: regInfo{ 25835 inputs: []inputInfo{ 25836 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25837 }, 25838 outputs: []outputInfo{ 25839 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25840 }, 25841 }, 25842 }, 25843 { 25844 name: "CEGBRA", 25845 argLen: 1, 25846 asm: s390x.ACEGBRA, 25847 reg: regInfo{ 25848 inputs: []inputInfo{ 25849 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25850 }, 25851 outputs: []outputInfo{ 25852 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25853 }, 25854 }, 25855 }, 25856 { 25857 name: "CDGBRA", 25858 argLen: 1, 25859 asm: s390x.ACDGBRA, 25860 reg: regInfo{ 25861 inputs: []inputInfo{ 25862 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25863 }, 25864 outputs: []outputInfo{ 25865 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25866 }, 25867 }, 25868 }, 25869 { 25870 name: "LEDBR", 25871 argLen: 1, 25872 asm: s390x.ALEDBR, 25873 reg: regInfo{ 25874 inputs: []inputInfo{ 25875 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25876 }, 25877 outputs: []outputInfo{ 25878 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25879 }, 25880 }, 25881 }, 25882 { 25883 name: "LDEBR", 25884 argLen: 1, 25885 asm: s390x.ALDEBR, 25886 reg: regInfo{ 25887 inputs: []inputInfo{ 25888 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25889 }, 25890 outputs: []outputInfo{ 25891 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 25892 }, 25893 }, 25894 }, 25895 { 25896 name: "MOVDaddr", 25897 auxType: auxSymOff, 25898 argLen: 1, 25899 rematerializeable: true, 25900 symEffect: SymRead, 25901 reg: regInfo{ 25902 inputs: []inputInfo{ 25903 {0, 4295000064}, // SP SB 25904 }, 25905 outputs: []outputInfo{ 25906 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25907 }, 25908 }, 25909 }, 25910 { 25911 name: "MOVDaddridx", 25912 auxType: auxSymOff, 25913 argLen: 2, 25914 symEffect: SymRead, 25915 reg: regInfo{ 25916 inputs: []inputInfo{ 25917 {0, 4295000064}, // SP SB 25918 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 25919 }, 25920 outputs: []outputInfo{ 25921 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25922 }, 25923 }, 25924 }, 25925 { 25926 name: "MOVBZload", 25927 auxType: auxSymOff, 25928 argLen: 2, 25929 clobberFlags: true, 25930 faultOnNilArg0: true, 25931 symEffect: SymRead, 25932 asm: s390x.AMOVBZ, 25933 reg: regInfo{ 25934 inputs: []inputInfo{ 25935 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25936 }, 25937 outputs: []outputInfo{ 25938 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25939 }, 25940 }, 25941 }, 25942 { 25943 name: "MOVBload", 25944 auxType: auxSymOff, 25945 argLen: 2, 25946 clobberFlags: true, 25947 faultOnNilArg0: true, 25948 symEffect: SymRead, 25949 asm: s390x.AMOVB, 25950 reg: regInfo{ 25951 inputs: []inputInfo{ 25952 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25953 }, 25954 outputs: []outputInfo{ 25955 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25956 }, 25957 }, 25958 }, 25959 { 25960 name: "MOVHZload", 25961 auxType: auxSymOff, 25962 argLen: 2, 25963 clobberFlags: true, 25964 faultOnNilArg0: true, 25965 symEffect: SymRead, 25966 asm: s390x.AMOVHZ, 25967 reg: regInfo{ 25968 inputs: []inputInfo{ 25969 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25970 }, 25971 outputs: []outputInfo{ 25972 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25973 }, 25974 }, 25975 }, 25976 { 25977 name: "MOVHload", 25978 auxType: auxSymOff, 25979 argLen: 2, 25980 clobberFlags: true, 25981 faultOnNilArg0: true, 25982 symEffect: SymRead, 25983 asm: s390x.AMOVH, 25984 reg: regInfo{ 25985 inputs: []inputInfo{ 25986 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 25987 }, 25988 outputs: []outputInfo{ 25989 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 25990 }, 25991 }, 25992 }, 25993 { 25994 name: "MOVWZload", 25995 auxType: auxSymOff, 25996 argLen: 2, 25997 clobberFlags: true, 25998 faultOnNilArg0: true, 25999 symEffect: SymRead, 26000 asm: s390x.AMOVWZ, 26001 reg: regInfo{ 26002 inputs: []inputInfo{ 26003 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26004 }, 26005 outputs: []outputInfo{ 26006 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26007 }, 26008 }, 26009 }, 26010 { 26011 name: "MOVWload", 26012 auxType: auxSymOff, 26013 argLen: 2, 26014 clobberFlags: true, 26015 faultOnNilArg0: true, 26016 symEffect: SymRead, 26017 asm: s390x.AMOVW, 26018 reg: regInfo{ 26019 inputs: []inputInfo{ 26020 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26021 }, 26022 outputs: []outputInfo{ 26023 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26024 }, 26025 }, 26026 }, 26027 { 26028 name: "MOVDload", 26029 auxType: auxSymOff, 26030 argLen: 2, 26031 clobberFlags: true, 26032 faultOnNilArg0: true, 26033 symEffect: SymRead, 26034 asm: s390x.AMOVD, 26035 reg: regInfo{ 26036 inputs: []inputInfo{ 26037 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26038 }, 26039 outputs: []outputInfo{ 26040 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26041 }, 26042 }, 26043 }, 26044 { 26045 name: "MOVWBR", 26046 argLen: 1, 26047 asm: s390x.AMOVWBR, 26048 reg: regInfo{ 26049 inputs: []inputInfo{ 26050 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26051 }, 26052 outputs: []outputInfo{ 26053 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26054 }, 26055 }, 26056 }, 26057 { 26058 name: "MOVDBR", 26059 argLen: 1, 26060 asm: s390x.AMOVDBR, 26061 reg: regInfo{ 26062 inputs: []inputInfo{ 26063 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26064 }, 26065 outputs: []outputInfo{ 26066 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26067 }, 26068 }, 26069 }, 26070 { 26071 name: "MOVHBRload", 26072 auxType: auxSymOff, 26073 argLen: 2, 26074 clobberFlags: true, 26075 faultOnNilArg0: true, 26076 symEffect: SymRead, 26077 asm: s390x.AMOVHBR, 26078 reg: regInfo{ 26079 inputs: []inputInfo{ 26080 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26081 }, 26082 outputs: []outputInfo{ 26083 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26084 }, 26085 }, 26086 }, 26087 { 26088 name: "MOVWBRload", 26089 auxType: auxSymOff, 26090 argLen: 2, 26091 clobberFlags: true, 26092 faultOnNilArg0: true, 26093 symEffect: SymRead, 26094 asm: s390x.AMOVWBR, 26095 reg: regInfo{ 26096 inputs: []inputInfo{ 26097 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26098 }, 26099 outputs: []outputInfo{ 26100 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26101 }, 26102 }, 26103 }, 26104 { 26105 name: "MOVDBRload", 26106 auxType: auxSymOff, 26107 argLen: 2, 26108 clobberFlags: true, 26109 faultOnNilArg0: true, 26110 symEffect: SymRead, 26111 asm: s390x.AMOVDBR, 26112 reg: regInfo{ 26113 inputs: []inputInfo{ 26114 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26115 }, 26116 outputs: []outputInfo{ 26117 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26118 }, 26119 }, 26120 }, 26121 { 26122 name: "MOVBstore", 26123 auxType: auxSymOff, 26124 argLen: 3, 26125 clobberFlags: true, 26126 faultOnNilArg0: true, 26127 symEffect: SymWrite, 26128 asm: s390x.AMOVB, 26129 reg: regInfo{ 26130 inputs: []inputInfo{ 26131 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26132 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26133 }, 26134 }, 26135 }, 26136 { 26137 name: "MOVHstore", 26138 auxType: auxSymOff, 26139 argLen: 3, 26140 clobberFlags: true, 26141 faultOnNilArg0: true, 26142 symEffect: SymWrite, 26143 asm: s390x.AMOVH, 26144 reg: regInfo{ 26145 inputs: []inputInfo{ 26146 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26147 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26148 }, 26149 }, 26150 }, 26151 { 26152 name: "MOVWstore", 26153 auxType: auxSymOff, 26154 argLen: 3, 26155 clobberFlags: true, 26156 faultOnNilArg0: true, 26157 symEffect: SymWrite, 26158 asm: s390x.AMOVW, 26159 reg: regInfo{ 26160 inputs: []inputInfo{ 26161 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26162 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26163 }, 26164 }, 26165 }, 26166 { 26167 name: "MOVDstore", 26168 auxType: auxSymOff, 26169 argLen: 3, 26170 clobberFlags: true, 26171 faultOnNilArg0: true, 26172 symEffect: SymWrite, 26173 asm: s390x.AMOVD, 26174 reg: regInfo{ 26175 inputs: []inputInfo{ 26176 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26177 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26178 }, 26179 }, 26180 }, 26181 { 26182 name: "MOVHBRstore", 26183 auxType: auxSymOff, 26184 argLen: 3, 26185 clobberFlags: true, 26186 faultOnNilArg0: true, 26187 symEffect: SymWrite, 26188 asm: s390x.AMOVHBR, 26189 reg: regInfo{ 26190 inputs: []inputInfo{ 26191 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26192 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26193 }, 26194 }, 26195 }, 26196 { 26197 name: "MOVWBRstore", 26198 auxType: auxSymOff, 26199 argLen: 3, 26200 clobberFlags: true, 26201 faultOnNilArg0: true, 26202 symEffect: SymWrite, 26203 asm: s390x.AMOVWBR, 26204 reg: regInfo{ 26205 inputs: []inputInfo{ 26206 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26207 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26208 }, 26209 }, 26210 }, 26211 { 26212 name: "MOVDBRstore", 26213 auxType: auxSymOff, 26214 argLen: 3, 26215 clobberFlags: true, 26216 faultOnNilArg0: true, 26217 symEffect: SymWrite, 26218 asm: s390x.AMOVDBR, 26219 reg: regInfo{ 26220 inputs: []inputInfo{ 26221 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26222 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26223 }, 26224 }, 26225 }, 26226 { 26227 name: "MVC", 26228 auxType: auxSymValAndOff, 26229 argLen: 3, 26230 clobberFlags: true, 26231 faultOnNilArg0: true, 26232 faultOnNilArg1: true, 26233 symEffect: SymNone, 26234 asm: s390x.AMVC, 26235 reg: regInfo{ 26236 inputs: []inputInfo{ 26237 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26238 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26239 }, 26240 }, 26241 }, 26242 { 26243 name: "MOVBZloadidx", 26244 auxType: auxSymOff, 26245 argLen: 3, 26246 commutative: true, 26247 clobberFlags: true, 26248 symEffect: SymRead, 26249 asm: s390x.AMOVBZ, 26250 reg: regInfo{ 26251 inputs: []inputInfo{ 26252 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26253 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26254 }, 26255 outputs: []outputInfo{ 26256 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26257 }, 26258 }, 26259 }, 26260 { 26261 name: "MOVBloadidx", 26262 auxType: auxSymOff, 26263 argLen: 3, 26264 commutative: true, 26265 clobberFlags: true, 26266 symEffect: SymRead, 26267 asm: s390x.AMOVB, 26268 reg: regInfo{ 26269 inputs: []inputInfo{ 26270 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26271 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26272 }, 26273 outputs: []outputInfo{ 26274 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26275 }, 26276 }, 26277 }, 26278 { 26279 name: "MOVHZloadidx", 26280 auxType: auxSymOff, 26281 argLen: 3, 26282 commutative: true, 26283 clobberFlags: true, 26284 symEffect: SymRead, 26285 asm: s390x.AMOVHZ, 26286 reg: regInfo{ 26287 inputs: []inputInfo{ 26288 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26289 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26290 }, 26291 outputs: []outputInfo{ 26292 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26293 }, 26294 }, 26295 }, 26296 { 26297 name: "MOVHloadidx", 26298 auxType: auxSymOff, 26299 argLen: 3, 26300 commutative: true, 26301 clobberFlags: true, 26302 symEffect: SymRead, 26303 asm: s390x.AMOVH, 26304 reg: regInfo{ 26305 inputs: []inputInfo{ 26306 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26307 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26308 }, 26309 outputs: []outputInfo{ 26310 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26311 }, 26312 }, 26313 }, 26314 { 26315 name: "MOVWZloadidx", 26316 auxType: auxSymOff, 26317 argLen: 3, 26318 commutative: true, 26319 clobberFlags: true, 26320 symEffect: SymRead, 26321 asm: s390x.AMOVWZ, 26322 reg: regInfo{ 26323 inputs: []inputInfo{ 26324 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26325 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26326 }, 26327 outputs: []outputInfo{ 26328 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26329 }, 26330 }, 26331 }, 26332 { 26333 name: "MOVWloadidx", 26334 auxType: auxSymOff, 26335 argLen: 3, 26336 commutative: true, 26337 clobberFlags: true, 26338 symEffect: SymRead, 26339 asm: s390x.AMOVW, 26340 reg: regInfo{ 26341 inputs: []inputInfo{ 26342 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26343 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26344 }, 26345 outputs: []outputInfo{ 26346 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26347 }, 26348 }, 26349 }, 26350 { 26351 name: "MOVDloadidx", 26352 auxType: auxSymOff, 26353 argLen: 3, 26354 commutative: true, 26355 clobberFlags: true, 26356 symEffect: SymRead, 26357 asm: s390x.AMOVD, 26358 reg: regInfo{ 26359 inputs: []inputInfo{ 26360 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26361 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26362 }, 26363 outputs: []outputInfo{ 26364 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26365 }, 26366 }, 26367 }, 26368 { 26369 name: "MOVHBRloadidx", 26370 auxType: auxSymOff, 26371 argLen: 3, 26372 commutative: true, 26373 clobberFlags: true, 26374 symEffect: SymRead, 26375 asm: s390x.AMOVHBR, 26376 reg: regInfo{ 26377 inputs: []inputInfo{ 26378 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26379 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26380 }, 26381 outputs: []outputInfo{ 26382 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26383 }, 26384 }, 26385 }, 26386 { 26387 name: "MOVWBRloadidx", 26388 auxType: auxSymOff, 26389 argLen: 3, 26390 commutative: true, 26391 clobberFlags: true, 26392 symEffect: SymRead, 26393 asm: s390x.AMOVWBR, 26394 reg: regInfo{ 26395 inputs: []inputInfo{ 26396 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26397 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26398 }, 26399 outputs: []outputInfo{ 26400 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26401 }, 26402 }, 26403 }, 26404 { 26405 name: "MOVDBRloadidx", 26406 auxType: auxSymOff, 26407 argLen: 3, 26408 commutative: true, 26409 clobberFlags: true, 26410 symEffect: SymRead, 26411 asm: s390x.AMOVDBR, 26412 reg: regInfo{ 26413 inputs: []inputInfo{ 26414 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26415 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26416 }, 26417 outputs: []outputInfo{ 26418 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26419 }, 26420 }, 26421 }, 26422 { 26423 name: "MOVBstoreidx", 26424 auxType: auxSymOff, 26425 argLen: 4, 26426 commutative: true, 26427 clobberFlags: true, 26428 symEffect: SymWrite, 26429 asm: s390x.AMOVB, 26430 reg: regInfo{ 26431 inputs: []inputInfo{ 26432 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26433 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26434 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26435 }, 26436 }, 26437 }, 26438 { 26439 name: "MOVHstoreidx", 26440 auxType: auxSymOff, 26441 argLen: 4, 26442 commutative: true, 26443 clobberFlags: true, 26444 symEffect: SymWrite, 26445 asm: s390x.AMOVH, 26446 reg: regInfo{ 26447 inputs: []inputInfo{ 26448 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26449 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26450 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26451 }, 26452 }, 26453 }, 26454 { 26455 name: "MOVWstoreidx", 26456 auxType: auxSymOff, 26457 argLen: 4, 26458 commutative: true, 26459 clobberFlags: true, 26460 symEffect: SymWrite, 26461 asm: s390x.AMOVW, 26462 reg: regInfo{ 26463 inputs: []inputInfo{ 26464 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26465 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26466 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26467 }, 26468 }, 26469 }, 26470 { 26471 name: "MOVDstoreidx", 26472 auxType: auxSymOff, 26473 argLen: 4, 26474 commutative: true, 26475 clobberFlags: true, 26476 symEffect: SymWrite, 26477 asm: s390x.AMOVD, 26478 reg: regInfo{ 26479 inputs: []inputInfo{ 26480 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26481 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26482 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26483 }, 26484 }, 26485 }, 26486 { 26487 name: "MOVHBRstoreidx", 26488 auxType: auxSymOff, 26489 argLen: 4, 26490 commutative: true, 26491 clobberFlags: true, 26492 symEffect: SymWrite, 26493 asm: s390x.AMOVHBR, 26494 reg: regInfo{ 26495 inputs: []inputInfo{ 26496 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26497 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26498 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26499 }, 26500 }, 26501 }, 26502 { 26503 name: "MOVWBRstoreidx", 26504 auxType: auxSymOff, 26505 argLen: 4, 26506 commutative: true, 26507 clobberFlags: true, 26508 symEffect: SymWrite, 26509 asm: s390x.AMOVWBR, 26510 reg: regInfo{ 26511 inputs: []inputInfo{ 26512 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26513 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26514 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26515 }, 26516 }, 26517 }, 26518 { 26519 name: "MOVDBRstoreidx", 26520 auxType: auxSymOff, 26521 argLen: 4, 26522 commutative: true, 26523 clobberFlags: true, 26524 symEffect: SymWrite, 26525 asm: s390x.AMOVDBR, 26526 reg: regInfo{ 26527 inputs: []inputInfo{ 26528 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26529 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26530 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26531 }, 26532 }, 26533 }, 26534 { 26535 name: "MOVBstoreconst", 26536 auxType: auxSymValAndOff, 26537 argLen: 2, 26538 faultOnNilArg0: true, 26539 symEffect: SymWrite, 26540 asm: s390x.AMOVB, 26541 reg: regInfo{ 26542 inputs: []inputInfo{ 26543 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26544 }, 26545 }, 26546 }, 26547 { 26548 name: "MOVHstoreconst", 26549 auxType: auxSymValAndOff, 26550 argLen: 2, 26551 faultOnNilArg0: true, 26552 symEffect: SymWrite, 26553 asm: s390x.AMOVH, 26554 reg: regInfo{ 26555 inputs: []inputInfo{ 26556 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26557 }, 26558 }, 26559 }, 26560 { 26561 name: "MOVWstoreconst", 26562 auxType: auxSymValAndOff, 26563 argLen: 2, 26564 faultOnNilArg0: true, 26565 symEffect: SymWrite, 26566 asm: s390x.AMOVW, 26567 reg: regInfo{ 26568 inputs: []inputInfo{ 26569 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26570 }, 26571 }, 26572 }, 26573 { 26574 name: "MOVDstoreconst", 26575 auxType: auxSymValAndOff, 26576 argLen: 2, 26577 faultOnNilArg0: true, 26578 symEffect: SymWrite, 26579 asm: s390x.AMOVD, 26580 reg: regInfo{ 26581 inputs: []inputInfo{ 26582 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26583 }, 26584 }, 26585 }, 26586 { 26587 name: "CLEAR", 26588 auxType: auxSymValAndOff, 26589 argLen: 2, 26590 clobberFlags: true, 26591 faultOnNilArg0: true, 26592 symEffect: SymWrite, 26593 asm: s390x.ACLEAR, 26594 reg: regInfo{ 26595 inputs: []inputInfo{ 26596 {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26597 }, 26598 }, 26599 }, 26600 { 26601 name: "CALLstatic", 26602 auxType: auxSymOff, 26603 argLen: 1, 26604 clobberFlags: true, 26605 call: true, 26606 symEffect: SymNone, 26607 reg: regInfo{ 26608 clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 26609 }, 26610 }, 26611 { 26612 name: "CALLclosure", 26613 auxType: auxInt64, 26614 argLen: 3, 26615 clobberFlags: true, 26616 call: true, 26617 reg: regInfo{ 26618 inputs: []inputInfo{ 26619 {1, 4096}, // R12 26620 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26621 }, 26622 clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 26623 }, 26624 }, 26625 { 26626 name: "CALLinter", 26627 auxType: auxInt64, 26628 argLen: 2, 26629 clobberFlags: true, 26630 call: true, 26631 reg: regInfo{ 26632 inputs: []inputInfo{ 26633 {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26634 }, 26635 clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 26636 }, 26637 }, 26638 { 26639 name: "InvertFlags", 26640 argLen: 1, 26641 reg: regInfo{}, 26642 }, 26643 { 26644 name: "LoweredGetG", 26645 argLen: 1, 26646 reg: regInfo{ 26647 outputs: []outputInfo{ 26648 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26649 }, 26650 }, 26651 }, 26652 { 26653 name: "LoweredGetClosurePtr", 26654 argLen: 0, 26655 zeroWidth: true, 26656 reg: regInfo{ 26657 outputs: []outputInfo{ 26658 {0, 4096}, // R12 26659 }, 26660 }, 26661 }, 26662 { 26663 name: "LoweredGetCallerSP", 26664 argLen: 0, 26665 rematerializeable: true, 26666 reg: regInfo{ 26667 outputs: []outputInfo{ 26668 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26669 }, 26670 }, 26671 }, 26672 { 26673 name: "LoweredGetCallerPC", 26674 argLen: 0, 26675 rematerializeable: true, 26676 reg: regInfo{ 26677 outputs: []outputInfo{ 26678 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26679 }, 26680 }, 26681 }, 26682 { 26683 name: "LoweredNilCheck", 26684 argLen: 2, 26685 clobberFlags: true, 26686 nilCheck: true, 26687 faultOnNilArg0: true, 26688 reg: regInfo{ 26689 inputs: []inputInfo{ 26690 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26691 }, 26692 }, 26693 }, 26694 { 26695 name: "LoweredRound32F", 26696 argLen: 1, 26697 resultInArg0: true, 26698 zeroWidth: true, 26699 reg: regInfo{ 26700 inputs: []inputInfo{ 26701 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 26702 }, 26703 outputs: []outputInfo{ 26704 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 26705 }, 26706 }, 26707 }, 26708 { 26709 name: "LoweredRound64F", 26710 argLen: 1, 26711 resultInArg0: true, 26712 zeroWidth: true, 26713 reg: regInfo{ 26714 inputs: []inputInfo{ 26715 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 26716 }, 26717 outputs: []outputInfo{ 26718 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 26719 }, 26720 }, 26721 }, 26722 { 26723 name: "LoweredWB", 26724 auxType: auxSym, 26725 argLen: 3, 26726 clobberFlags: true, 26727 symEffect: SymNone, 26728 reg: regInfo{ 26729 inputs: []inputInfo{ 26730 {0, 4}, // R2 26731 {1, 8}, // R3 26732 }, 26733 clobbers: 4294918144, // R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 26734 }, 26735 }, 26736 { 26737 name: "FlagEQ", 26738 argLen: 0, 26739 reg: regInfo{}, 26740 }, 26741 { 26742 name: "FlagLT", 26743 argLen: 0, 26744 reg: regInfo{}, 26745 }, 26746 { 26747 name: "FlagGT", 26748 argLen: 0, 26749 reg: regInfo{}, 26750 }, 26751 { 26752 name: "MOVWZatomicload", 26753 auxType: auxSymOff, 26754 argLen: 2, 26755 faultOnNilArg0: true, 26756 symEffect: SymRead, 26757 asm: s390x.AMOVWZ, 26758 reg: regInfo{ 26759 inputs: []inputInfo{ 26760 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26761 }, 26762 outputs: []outputInfo{ 26763 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26764 }, 26765 }, 26766 }, 26767 { 26768 name: "MOVDatomicload", 26769 auxType: auxSymOff, 26770 argLen: 2, 26771 faultOnNilArg0: true, 26772 symEffect: SymRead, 26773 asm: s390x.AMOVD, 26774 reg: regInfo{ 26775 inputs: []inputInfo{ 26776 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26777 }, 26778 outputs: []outputInfo{ 26779 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26780 }, 26781 }, 26782 }, 26783 { 26784 name: "MOVWatomicstore", 26785 auxType: auxSymOff, 26786 argLen: 3, 26787 clobberFlags: true, 26788 faultOnNilArg0: true, 26789 hasSideEffects: true, 26790 symEffect: SymWrite, 26791 asm: s390x.AMOVW, 26792 reg: regInfo{ 26793 inputs: []inputInfo{ 26794 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26795 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26796 }, 26797 }, 26798 }, 26799 { 26800 name: "MOVDatomicstore", 26801 auxType: auxSymOff, 26802 argLen: 3, 26803 clobberFlags: true, 26804 faultOnNilArg0: true, 26805 hasSideEffects: true, 26806 symEffect: SymWrite, 26807 asm: s390x.AMOVD, 26808 reg: regInfo{ 26809 inputs: []inputInfo{ 26810 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26811 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26812 }, 26813 }, 26814 }, 26815 { 26816 name: "LAA", 26817 auxType: auxSymOff, 26818 argLen: 3, 26819 clobberFlags: true, 26820 faultOnNilArg0: true, 26821 hasSideEffects: true, 26822 symEffect: SymRdWr, 26823 asm: s390x.ALAA, 26824 reg: regInfo{ 26825 inputs: []inputInfo{ 26826 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26827 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26828 }, 26829 outputs: []outputInfo{ 26830 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26831 }, 26832 }, 26833 }, 26834 { 26835 name: "LAAG", 26836 auxType: auxSymOff, 26837 argLen: 3, 26838 clobberFlags: true, 26839 faultOnNilArg0: true, 26840 hasSideEffects: true, 26841 symEffect: SymRdWr, 26842 asm: s390x.ALAAG, 26843 reg: regInfo{ 26844 inputs: []inputInfo{ 26845 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 26846 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26847 }, 26848 outputs: []outputInfo{ 26849 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26850 }, 26851 }, 26852 }, 26853 { 26854 name: "AddTupleFirst32", 26855 argLen: 2, 26856 reg: regInfo{}, 26857 }, 26858 { 26859 name: "AddTupleFirst64", 26860 argLen: 2, 26861 reg: regInfo{}, 26862 }, 26863 { 26864 name: "LoweredAtomicCas32", 26865 auxType: auxSymOff, 26866 argLen: 4, 26867 clobberFlags: true, 26868 faultOnNilArg0: true, 26869 hasSideEffects: true, 26870 symEffect: SymRdWr, 26871 asm: s390x.ACS, 26872 reg: regInfo{ 26873 inputs: []inputInfo{ 26874 {1, 1}, // R0 26875 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26876 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26877 }, 26878 clobbers: 1, // R0 26879 outputs: []outputInfo{ 26880 {1, 0}, 26881 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26882 }, 26883 }, 26884 }, 26885 { 26886 name: "LoweredAtomicCas64", 26887 auxType: auxSymOff, 26888 argLen: 4, 26889 clobberFlags: true, 26890 faultOnNilArg0: true, 26891 hasSideEffects: true, 26892 symEffect: SymRdWr, 26893 asm: s390x.ACSG, 26894 reg: regInfo{ 26895 inputs: []inputInfo{ 26896 {1, 1}, // R0 26897 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26898 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26899 }, 26900 clobbers: 1, // R0 26901 outputs: []outputInfo{ 26902 {1, 0}, 26903 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26904 }, 26905 }, 26906 }, 26907 { 26908 name: "LoweredAtomicExchange32", 26909 auxType: auxSymOff, 26910 argLen: 3, 26911 clobberFlags: true, 26912 faultOnNilArg0: true, 26913 hasSideEffects: true, 26914 symEffect: SymRdWr, 26915 asm: s390x.ACS, 26916 reg: regInfo{ 26917 inputs: []inputInfo{ 26918 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26919 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26920 }, 26921 outputs: []outputInfo{ 26922 {1, 0}, 26923 {0, 1}, // R0 26924 }, 26925 }, 26926 }, 26927 { 26928 name: "LoweredAtomicExchange64", 26929 auxType: auxSymOff, 26930 argLen: 3, 26931 clobberFlags: true, 26932 faultOnNilArg0: true, 26933 hasSideEffects: true, 26934 symEffect: SymRdWr, 26935 asm: s390x.ACSG, 26936 reg: regInfo{ 26937 inputs: []inputInfo{ 26938 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26939 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 26940 }, 26941 outputs: []outputInfo{ 26942 {1, 0}, 26943 {0, 1}, // R0 26944 }, 26945 }, 26946 }, 26947 { 26948 name: "FLOGR", 26949 argLen: 1, 26950 clobberFlags: true, 26951 asm: s390x.AFLOGR, 26952 reg: regInfo{ 26953 inputs: []inputInfo{ 26954 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26955 }, 26956 clobbers: 2, // R1 26957 outputs: []outputInfo{ 26958 {0, 1}, // R0 26959 }, 26960 }, 26961 }, 26962 { 26963 name: "POPCNT", 26964 argLen: 1, 26965 clobberFlags: true, 26966 asm: s390x.APOPCNT, 26967 reg: regInfo{ 26968 inputs: []inputInfo{ 26969 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26970 }, 26971 outputs: []outputInfo{ 26972 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 26973 }, 26974 }, 26975 }, 26976 { 26977 name: "SumBytes2", 26978 argLen: 1, 26979 reg: regInfo{}, 26980 }, 26981 { 26982 name: "SumBytes4", 26983 argLen: 1, 26984 reg: regInfo{}, 26985 }, 26986 { 26987 name: "SumBytes8", 26988 argLen: 1, 26989 reg: regInfo{}, 26990 }, 26991 { 26992 name: "STMG2", 26993 auxType: auxSymOff, 26994 argLen: 4, 26995 faultOnNilArg0: true, 26996 symEffect: SymWrite, 26997 asm: s390x.ASTMG, 26998 reg: regInfo{ 26999 inputs: []inputInfo{ 27000 {1, 2}, // R1 27001 {2, 4}, // R2 27002 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 27003 }, 27004 }, 27005 }, 27006 { 27007 name: "STMG3", 27008 auxType: auxSymOff, 27009 argLen: 5, 27010 faultOnNilArg0: true, 27011 symEffect: SymWrite, 27012 asm: s390x.ASTMG, 27013 reg: regInfo{ 27014 inputs: []inputInfo{ 27015 {1, 2}, // R1 27016 {2, 4}, // R2 27017 {3, 8}, // R3 27018 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 27019 }, 27020 }, 27021 }, 27022 { 27023 name: "STMG4", 27024 auxType: auxSymOff, 27025 argLen: 6, 27026 faultOnNilArg0: true, 27027 symEffect: SymWrite, 27028 asm: s390x.ASTMG, 27029 reg: regInfo{ 27030 inputs: []inputInfo{ 27031 {1, 2}, // R1 27032 {2, 4}, // R2 27033 {3, 8}, // R3 27034 {4, 16}, // R4 27035 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 27036 }, 27037 }, 27038 }, 27039 { 27040 name: "STM2", 27041 auxType: auxSymOff, 27042 argLen: 4, 27043 faultOnNilArg0: true, 27044 symEffect: SymWrite, 27045 asm: s390x.ASTMY, 27046 reg: regInfo{ 27047 inputs: []inputInfo{ 27048 {1, 2}, // R1 27049 {2, 4}, // R2 27050 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 27051 }, 27052 }, 27053 }, 27054 { 27055 name: "STM3", 27056 auxType: auxSymOff, 27057 argLen: 5, 27058 faultOnNilArg0: true, 27059 symEffect: SymWrite, 27060 asm: s390x.ASTMY, 27061 reg: regInfo{ 27062 inputs: []inputInfo{ 27063 {1, 2}, // R1 27064 {2, 4}, // R2 27065 {3, 8}, // R3 27066 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 27067 }, 27068 }, 27069 }, 27070 { 27071 name: "STM4", 27072 auxType: auxSymOff, 27073 argLen: 6, 27074 faultOnNilArg0: true, 27075 symEffect: SymWrite, 27076 asm: s390x.ASTMY, 27077 reg: regInfo{ 27078 inputs: []inputInfo{ 27079 {1, 2}, // R1 27080 {2, 4}, // R2 27081 {3, 8}, // R3 27082 {4, 16}, // R4 27083 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 27084 }, 27085 }, 27086 }, 27087 { 27088 name: "LoweredMove", 27089 auxType: auxInt64, 27090 argLen: 4, 27091 clobberFlags: true, 27092 faultOnNilArg0: true, 27093 faultOnNilArg1: true, 27094 reg: regInfo{ 27095 inputs: []inputInfo{ 27096 {0, 2}, // R1 27097 {1, 4}, // R2 27098 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 27099 }, 27100 clobbers: 6, // R1 R2 27101 }, 27102 }, 27103 { 27104 name: "LoweredZero", 27105 auxType: auxInt64, 27106 argLen: 3, 27107 clobberFlags: true, 27108 faultOnNilArg0: true, 27109 reg: regInfo{ 27110 inputs: []inputInfo{ 27111 {0, 2}, // R1 27112 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 27113 }, 27114 clobbers: 2, // R1 27115 }, 27116 }, 27117 27118 { 27119 name: "LoweredStaticCall", 27120 auxType: auxSymOff, 27121 argLen: 1, 27122 call: true, 27123 symEffect: SymNone, 27124 reg: regInfo{ 27125 clobbers: 12884901887, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 g 27126 }, 27127 }, 27128 { 27129 name: "LoweredClosureCall", 27130 auxType: auxInt64, 27131 argLen: 3, 27132 call: true, 27133 reg: regInfo{ 27134 inputs: []inputInfo{ 27135 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27136 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27137 }, 27138 clobbers: 12884901887, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 g 27139 }, 27140 }, 27141 { 27142 name: "LoweredInterCall", 27143 auxType: auxInt64, 27144 argLen: 2, 27145 call: true, 27146 reg: regInfo{ 27147 inputs: []inputInfo{ 27148 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27149 }, 27150 clobbers: 12884901887, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 g 27151 }, 27152 }, 27153 { 27154 name: "LoweredAddr", 27155 auxType: auxSymOff, 27156 argLen: 1, 27157 rematerializeable: true, 27158 symEffect: SymAddr, 27159 reg: regInfo{ 27160 inputs: []inputInfo{ 27161 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27162 }, 27163 outputs: []outputInfo{ 27164 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27165 }, 27166 }, 27167 }, 27168 { 27169 name: "LoweredMove", 27170 auxType: auxInt64, 27171 argLen: 3, 27172 reg: regInfo{ 27173 inputs: []inputInfo{ 27174 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27175 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27176 }, 27177 }, 27178 }, 27179 { 27180 name: "LoweredZero", 27181 auxType: auxInt64, 27182 argLen: 2, 27183 reg: regInfo{ 27184 inputs: []inputInfo{ 27185 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27186 }, 27187 }, 27188 }, 27189 { 27190 name: "LoweredGetClosurePtr", 27191 argLen: 0, 27192 reg: regInfo{ 27193 outputs: []outputInfo{ 27194 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27195 }, 27196 }, 27197 }, 27198 { 27199 name: "LoweredGetCallerPC", 27200 argLen: 0, 27201 rematerializeable: true, 27202 reg: regInfo{ 27203 outputs: []outputInfo{ 27204 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27205 }, 27206 }, 27207 }, 27208 { 27209 name: "LoweredGetCallerSP", 27210 argLen: 0, 27211 rematerializeable: true, 27212 reg: regInfo{ 27213 outputs: []outputInfo{ 27214 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27215 }, 27216 }, 27217 }, 27218 { 27219 name: "LoweredNilCheck", 27220 argLen: 2, 27221 nilCheck: true, 27222 faultOnNilArg0: true, 27223 reg: regInfo{ 27224 inputs: []inputInfo{ 27225 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27226 }, 27227 }, 27228 }, 27229 { 27230 name: "LoweredWB", 27231 auxType: auxSym, 27232 argLen: 3, 27233 symEffect: SymNone, 27234 reg: regInfo{ 27235 inputs: []inputInfo{ 27236 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27237 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27238 }, 27239 }, 27240 }, 27241 { 27242 name: "LoweredRound32F", 27243 argLen: 1, 27244 reg: regInfo{ 27245 inputs: []inputInfo{ 27246 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27247 }, 27248 outputs: []outputInfo{ 27249 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27250 }, 27251 }, 27252 }, 27253 { 27254 name: "LoweredConvert", 27255 argLen: 2, 27256 reg: regInfo{ 27257 inputs: []inputInfo{ 27258 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27259 }, 27260 outputs: []outputInfo{ 27261 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27262 }, 27263 }, 27264 }, 27265 { 27266 name: "Select", 27267 argLen: 3, 27268 asm: wasm.ASelect, 27269 reg: regInfo{ 27270 inputs: []inputInfo{ 27271 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27272 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27273 {2, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27274 }, 27275 outputs: []outputInfo{ 27276 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27277 }, 27278 }, 27279 }, 27280 { 27281 name: "I64Load8U", 27282 auxType: auxInt64, 27283 argLen: 2, 27284 asm: wasm.AI64Load8U, 27285 reg: regInfo{ 27286 inputs: []inputInfo{ 27287 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27288 }, 27289 outputs: []outputInfo{ 27290 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27291 }, 27292 }, 27293 }, 27294 { 27295 name: "I64Load8S", 27296 auxType: auxInt64, 27297 argLen: 2, 27298 asm: wasm.AI64Load8S, 27299 reg: regInfo{ 27300 inputs: []inputInfo{ 27301 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27302 }, 27303 outputs: []outputInfo{ 27304 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27305 }, 27306 }, 27307 }, 27308 { 27309 name: "I64Load16U", 27310 auxType: auxInt64, 27311 argLen: 2, 27312 asm: wasm.AI64Load16U, 27313 reg: regInfo{ 27314 inputs: []inputInfo{ 27315 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27316 }, 27317 outputs: []outputInfo{ 27318 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27319 }, 27320 }, 27321 }, 27322 { 27323 name: "I64Load16S", 27324 auxType: auxInt64, 27325 argLen: 2, 27326 asm: wasm.AI64Load16S, 27327 reg: regInfo{ 27328 inputs: []inputInfo{ 27329 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27330 }, 27331 outputs: []outputInfo{ 27332 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27333 }, 27334 }, 27335 }, 27336 { 27337 name: "I64Load32U", 27338 auxType: auxInt64, 27339 argLen: 2, 27340 asm: wasm.AI64Load32U, 27341 reg: regInfo{ 27342 inputs: []inputInfo{ 27343 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27344 }, 27345 outputs: []outputInfo{ 27346 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27347 }, 27348 }, 27349 }, 27350 { 27351 name: "I64Load32S", 27352 auxType: auxInt64, 27353 argLen: 2, 27354 asm: wasm.AI64Load32S, 27355 reg: regInfo{ 27356 inputs: []inputInfo{ 27357 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27358 }, 27359 outputs: []outputInfo{ 27360 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27361 }, 27362 }, 27363 }, 27364 { 27365 name: "I64Load", 27366 auxType: auxInt64, 27367 argLen: 2, 27368 asm: wasm.AI64Load, 27369 reg: regInfo{ 27370 inputs: []inputInfo{ 27371 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27372 }, 27373 outputs: []outputInfo{ 27374 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27375 }, 27376 }, 27377 }, 27378 { 27379 name: "I64Store8", 27380 auxType: auxInt64, 27381 argLen: 3, 27382 asm: wasm.AI64Store8, 27383 reg: regInfo{ 27384 inputs: []inputInfo{ 27385 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27386 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27387 }, 27388 }, 27389 }, 27390 { 27391 name: "I64Store16", 27392 auxType: auxInt64, 27393 argLen: 3, 27394 asm: wasm.AI64Store16, 27395 reg: regInfo{ 27396 inputs: []inputInfo{ 27397 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27398 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27399 }, 27400 }, 27401 }, 27402 { 27403 name: "I64Store32", 27404 auxType: auxInt64, 27405 argLen: 3, 27406 asm: wasm.AI64Store32, 27407 reg: regInfo{ 27408 inputs: []inputInfo{ 27409 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27410 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27411 }, 27412 }, 27413 }, 27414 { 27415 name: "I64Store", 27416 auxType: auxInt64, 27417 argLen: 3, 27418 asm: wasm.AI64Store, 27419 reg: regInfo{ 27420 inputs: []inputInfo{ 27421 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27422 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27423 }, 27424 }, 27425 }, 27426 { 27427 name: "F32Load", 27428 auxType: auxInt64, 27429 argLen: 2, 27430 asm: wasm.AF32Load, 27431 reg: regInfo{ 27432 inputs: []inputInfo{ 27433 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27434 }, 27435 outputs: []outputInfo{ 27436 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27437 }, 27438 }, 27439 }, 27440 { 27441 name: "F64Load", 27442 auxType: auxInt64, 27443 argLen: 2, 27444 asm: wasm.AF64Load, 27445 reg: regInfo{ 27446 inputs: []inputInfo{ 27447 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27448 }, 27449 outputs: []outputInfo{ 27450 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27451 }, 27452 }, 27453 }, 27454 { 27455 name: "F32Store", 27456 auxType: auxInt64, 27457 argLen: 3, 27458 asm: wasm.AF32Store, 27459 reg: regInfo{ 27460 inputs: []inputInfo{ 27461 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27462 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27463 }, 27464 }, 27465 }, 27466 { 27467 name: "F64Store", 27468 auxType: auxInt64, 27469 argLen: 3, 27470 asm: wasm.AF64Store, 27471 reg: regInfo{ 27472 inputs: []inputInfo{ 27473 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27474 {0, 21474902015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 27475 }, 27476 }, 27477 }, 27478 { 27479 name: "I64Const", 27480 auxType: auxInt64, 27481 argLen: 0, 27482 rematerializeable: true, 27483 reg: regInfo{ 27484 outputs: []outputInfo{ 27485 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27486 }, 27487 }, 27488 }, 27489 { 27490 name: "F64Const", 27491 auxType: auxFloat64, 27492 argLen: 0, 27493 rematerializeable: true, 27494 reg: regInfo{ 27495 outputs: []outputInfo{ 27496 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27497 }, 27498 }, 27499 }, 27500 { 27501 name: "I64Eqz", 27502 argLen: 1, 27503 asm: wasm.AI64Eqz, 27504 reg: regInfo{ 27505 inputs: []inputInfo{ 27506 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27507 }, 27508 outputs: []outputInfo{ 27509 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27510 }, 27511 }, 27512 }, 27513 { 27514 name: "I64Eq", 27515 argLen: 2, 27516 asm: wasm.AI64Eq, 27517 reg: regInfo{ 27518 inputs: []inputInfo{ 27519 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27520 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27521 }, 27522 outputs: []outputInfo{ 27523 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27524 }, 27525 }, 27526 }, 27527 { 27528 name: "I64Ne", 27529 argLen: 2, 27530 asm: wasm.AI64Ne, 27531 reg: regInfo{ 27532 inputs: []inputInfo{ 27533 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27534 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27535 }, 27536 outputs: []outputInfo{ 27537 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27538 }, 27539 }, 27540 }, 27541 { 27542 name: "I64LtS", 27543 argLen: 2, 27544 asm: wasm.AI64LtS, 27545 reg: regInfo{ 27546 inputs: []inputInfo{ 27547 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27548 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27549 }, 27550 outputs: []outputInfo{ 27551 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27552 }, 27553 }, 27554 }, 27555 { 27556 name: "I64LtU", 27557 argLen: 2, 27558 asm: wasm.AI64LtU, 27559 reg: regInfo{ 27560 inputs: []inputInfo{ 27561 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27562 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27563 }, 27564 outputs: []outputInfo{ 27565 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27566 }, 27567 }, 27568 }, 27569 { 27570 name: "I64GtS", 27571 argLen: 2, 27572 asm: wasm.AI64GtS, 27573 reg: regInfo{ 27574 inputs: []inputInfo{ 27575 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27576 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27577 }, 27578 outputs: []outputInfo{ 27579 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27580 }, 27581 }, 27582 }, 27583 { 27584 name: "I64GtU", 27585 argLen: 2, 27586 asm: wasm.AI64GtU, 27587 reg: regInfo{ 27588 inputs: []inputInfo{ 27589 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27590 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27591 }, 27592 outputs: []outputInfo{ 27593 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27594 }, 27595 }, 27596 }, 27597 { 27598 name: "I64LeS", 27599 argLen: 2, 27600 asm: wasm.AI64LeS, 27601 reg: regInfo{ 27602 inputs: []inputInfo{ 27603 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27604 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27605 }, 27606 outputs: []outputInfo{ 27607 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27608 }, 27609 }, 27610 }, 27611 { 27612 name: "I64LeU", 27613 argLen: 2, 27614 asm: wasm.AI64LeU, 27615 reg: regInfo{ 27616 inputs: []inputInfo{ 27617 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27618 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27619 }, 27620 outputs: []outputInfo{ 27621 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27622 }, 27623 }, 27624 }, 27625 { 27626 name: "I64GeS", 27627 argLen: 2, 27628 asm: wasm.AI64GeS, 27629 reg: regInfo{ 27630 inputs: []inputInfo{ 27631 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27632 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27633 }, 27634 outputs: []outputInfo{ 27635 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27636 }, 27637 }, 27638 }, 27639 { 27640 name: "I64GeU", 27641 argLen: 2, 27642 asm: wasm.AI64GeU, 27643 reg: regInfo{ 27644 inputs: []inputInfo{ 27645 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27646 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27647 }, 27648 outputs: []outputInfo{ 27649 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27650 }, 27651 }, 27652 }, 27653 { 27654 name: "F64Eq", 27655 argLen: 2, 27656 asm: wasm.AF64Eq, 27657 reg: regInfo{ 27658 inputs: []inputInfo{ 27659 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27660 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27661 }, 27662 outputs: []outputInfo{ 27663 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27664 }, 27665 }, 27666 }, 27667 { 27668 name: "F64Ne", 27669 argLen: 2, 27670 asm: wasm.AF64Ne, 27671 reg: regInfo{ 27672 inputs: []inputInfo{ 27673 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27674 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27675 }, 27676 outputs: []outputInfo{ 27677 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27678 }, 27679 }, 27680 }, 27681 { 27682 name: "F64Lt", 27683 argLen: 2, 27684 asm: wasm.AF64Lt, 27685 reg: regInfo{ 27686 inputs: []inputInfo{ 27687 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27688 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27689 }, 27690 outputs: []outputInfo{ 27691 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27692 }, 27693 }, 27694 }, 27695 { 27696 name: "F64Gt", 27697 argLen: 2, 27698 asm: wasm.AF64Gt, 27699 reg: regInfo{ 27700 inputs: []inputInfo{ 27701 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27702 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27703 }, 27704 outputs: []outputInfo{ 27705 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27706 }, 27707 }, 27708 }, 27709 { 27710 name: "F64Le", 27711 argLen: 2, 27712 asm: wasm.AF64Le, 27713 reg: regInfo{ 27714 inputs: []inputInfo{ 27715 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27716 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27717 }, 27718 outputs: []outputInfo{ 27719 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27720 }, 27721 }, 27722 }, 27723 { 27724 name: "F64Ge", 27725 argLen: 2, 27726 asm: wasm.AF64Ge, 27727 reg: regInfo{ 27728 inputs: []inputInfo{ 27729 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27730 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27731 }, 27732 outputs: []outputInfo{ 27733 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27734 }, 27735 }, 27736 }, 27737 { 27738 name: "I64Add", 27739 argLen: 2, 27740 asm: wasm.AI64Add, 27741 reg: regInfo{ 27742 inputs: []inputInfo{ 27743 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27744 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27745 }, 27746 outputs: []outputInfo{ 27747 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27748 }, 27749 }, 27750 }, 27751 { 27752 name: "I64AddConst", 27753 auxType: auxInt64, 27754 argLen: 1, 27755 asm: wasm.AI64Add, 27756 reg: regInfo{ 27757 inputs: []inputInfo{ 27758 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27759 }, 27760 outputs: []outputInfo{ 27761 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27762 }, 27763 }, 27764 }, 27765 { 27766 name: "I64Sub", 27767 argLen: 2, 27768 asm: wasm.AI64Sub, 27769 reg: regInfo{ 27770 inputs: []inputInfo{ 27771 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27772 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27773 }, 27774 outputs: []outputInfo{ 27775 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27776 }, 27777 }, 27778 }, 27779 { 27780 name: "I64Mul", 27781 argLen: 2, 27782 asm: wasm.AI64Mul, 27783 reg: regInfo{ 27784 inputs: []inputInfo{ 27785 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27786 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27787 }, 27788 outputs: []outputInfo{ 27789 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27790 }, 27791 }, 27792 }, 27793 { 27794 name: "I64DivS", 27795 argLen: 2, 27796 asm: wasm.AI64DivS, 27797 reg: regInfo{ 27798 inputs: []inputInfo{ 27799 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27800 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27801 }, 27802 outputs: []outputInfo{ 27803 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27804 }, 27805 }, 27806 }, 27807 { 27808 name: "I64DivU", 27809 argLen: 2, 27810 asm: wasm.AI64DivU, 27811 reg: regInfo{ 27812 inputs: []inputInfo{ 27813 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27814 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27815 }, 27816 outputs: []outputInfo{ 27817 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27818 }, 27819 }, 27820 }, 27821 { 27822 name: "I64RemS", 27823 argLen: 2, 27824 asm: wasm.AI64RemS, 27825 reg: regInfo{ 27826 inputs: []inputInfo{ 27827 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27828 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27829 }, 27830 outputs: []outputInfo{ 27831 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27832 }, 27833 }, 27834 }, 27835 { 27836 name: "I64RemU", 27837 argLen: 2, 27838 asm: wasm.AI64RemU, 27839 reg: regInfo{ 27840 inputs: []inputInfo{ 27841 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27842 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27843 }, 27844 outputs: []outputInfo{ 27845 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27846 }, 27847 }, 27848 }, 27849 { 27850 name: "I64And", 27851 argLen: 2, 27852 asm: wasm.AI64And, 27853 reg: regInfo{ 27854 inputs: []inputInfo{ 27855 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27856 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27857 }, 27858 outputs: []outputInfo{ 27859 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27860 }, 27861 }, 27862 }, 27863 { 27864 name: "I64Or", 27865 argLen: 2, 27866 asm: wasm.AI64Or, 27867 reg: regInfo{ 27868 inputs: []inputInfo{ 27869 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27870 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27871 }, 27872 outputs: []outputInfo{ 27873 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27874 }, 27875 }, 27876 }, 27877 { 27878 name: "I64Xor", 27879 argLen: 2, 27880 asm: wasm.AI64Xor, 27881 reg: regInfo{ 27882 inputs: []inputInfo{ 27883 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27884 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27885 }, 27886 outputs: []outputInfo{ 27887 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27888 }, 27889 }, 27890 }, 27891 { 27892 name: "I64Shl", 27893 argLen: 2, 27894 asm: wasm.AI64Shl, 27895 reg: regInfo{ 27896 inputs: []inputInfo{ 27897 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27898 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27899 }, 27900 outputs: []outputInfo{ 27901 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27902 }, 27903 }, 27904 }, 27905 { 27906 name: "I64ShrS", 27907 argLen: 2, 27908 asm: wasm.AI64ShrS, 27909 reg: regInfo{ 27910 inputs: []inputInfo{ 27911 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27912 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27913 }, 27914 outputs: []outputInfo{ 27915 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27916 }, 27917 }, 27918 }, 27919 { 27920 name: "I64ShrU", 27921 argLen: 2, 27922 asm: wasm.AI64ShrU, 27923 reg: regInfo{ 27924 inputs: []inputInfo{ 27925 {0, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27926 {1, 4295032831}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 27927 }, 27928 outputs: []outputInfo{ 27929 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 27930 }, 27931 }, 27932 }, 27933 { 27934 name: "F64Neg", 27935 argLen: 1, 27936 asm: wasm.AF64Neg, 27937 reg: regInfo{ 27938 inputs: []inputInfo{ 27939 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27940 }, 27941 outputs: []outputInfo{ 27942 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27943 }, 27944 }, 27945 }, 27946 { 27947 name: "F64Add", 27948 argLen: 2, 27949 asm: wasm.AF64Add, 27950 reg: regInfo{ 27951 inputs: []inputInfo{ 27952 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27953 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27954 }, 27955 outputs: []outputInfo{ 27956 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27957 }, 27958 }, 27959 }, 27960 { 27961 name: "F64Sub", 27962 argLen: 2, 27963 asm: wasm.AF64Sub, 27964 reg: regInfo{ 27965 inputs: []inputInfo{ 27966 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27967 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27968 }, 27969 outputs: []outputInfo{ 27970 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27971 }, 27972 }, 27973 }, 27974 { 27975 name: "F64Mul", 27976 argLen: 2, 27977 asm: wasm.AF64Mul, 27978 reg: regInfo{ 27979 inputs: []inputInfo{ 27980 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27981 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27982 }, 27983 outputs: []outputInfo{ 27984 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27985 }, 27986 }, 27987 }, 27988 { 27989 name: "F64Div", 27990 argLen: 2, 27991 asm: wasm.AF64Div, 27992 reg: regInfo{ 27993 inputs: []inputInfo{ 27994 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27995 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27996 }, 27997 outputs: []outputInfo{ 27998 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 27999 }, 28000 }, 28001 }, 28002 { 28003 name: "I64TruncSF64", 28004 argLen: 1, 28005 asm: wasm.AI64TruncSF64, 28006 reg: regInfo{ 28007 inputs: []inputInfo{ 28008 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 28009 }, 28010 outputs: []outputInfo{ 28011 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 28012 }, 28013 }, 28014 }, 28015 { 28016 name: "I64TruncUF64", 28017 argLen: 1, 28018 asm: wasm.AI64TruncUF64, 28019 reg: regInfo{ 28020 inputs: []inputInfo{ 28021 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 28022 }, 28023 outputs: []outputInfo{ 28024 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 28025 }, 28026 }, 28027 }, 28028 { 28029 name: "F64ConvertSI64", 28030 argLen: 1, 28031 asm: wasm.AF64ConvertSI64, 28032 reg: regInfo{ 28033 inputs: []inputInfo{ 28034 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 28035 }, 28036 outputs: []outputInfo{ 28037 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 28038 }, 28039 }, 28040 }, 28041 { 28042 name: "F64ConvertUI64", 28043 argLen: 1, 28044 asm: wasm.AF64ConvertUI64, 28045 reg: regInfo{ 28046 inputs: []inputInfo{ 28047 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 28048 }, 28049 outputs: []outputInfo{ 28050 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 28051 }, 28052 }, 28053 }, 28054 28055 { 28056 name: "Add8", 28057 argLen: 2, 28058 commutative: true, 28059 generic: true, 28060 }, 28061 { 28062 name: "Add16", 28063 argLen: 2, 28064 commutative: true, 28065 generic: true, 28066 }, 28067 { 28068 name: "Add32", 28069 argLen: 2, 28070 commutative: true, 28071 generic: true, 28072 }, 28073 { 28074 name: "Add64", 28075 argLen: 2, 28076 commutative: true, 28077 generic: true, 28078 }, 28079 { 28080 name: "AddPtr", 28081 argLen: 2, 28082 generic: true, 28083 }, 28084 { 28085 name: "Add32F", 28086 argLen: 2, 28087 commutative: true, 28088 generic: true, 28089 }, 28090 { 28091 name: "Add64F", 28092 argLen: 2, 28093 commutative: true, 28094 generic: true, 28095 }, 28096 { 28097 name: "Sub8", 28098 argLen: 2, 28099 generic: true, 28100 }, 28101 { 28102 name: "Sub16", 28103 argLen: 2, 28104 generic: true, 28105 }, 28106 { 28107 name: "Sub32", 28108 argLen: 2, 28109 generic: true, 28110 }, 28111 { 28112 name: "Sub64", 28113 argLen: 2, 28114 generic: true, 28115 }, 28116 { 28117 name: "SubPtr", 28118 argLen: 2, 28119 generic: true, 28120 }, 28121 { 28122 name: "Sub32F", 28123 argLen: 2, 28124 generic: true, 28125 }, 28126 { 28127 name: "Sub64F", 28128 argLen: 2, 28129 generic: true, 28130 }, 28131 { 28132 name: "Mul8", 28133 argLen: 2, 28134 commutative: true, 28135 generic: true, 28136 }, 28137 { 28138 name: "Mul16", 28139 argLen: 2, 28140 commutative: true, 28141 generic: true, 28142 }, 28143 { 28144 name: "Mul32", 28145 argLen: 2, 28146 commutative: true, 28147 generic: true, 28148 }, 28149 { 28150 name: "Mul64", 28151 argLen: 2, 28152 commutative: true, 28153 generic: true, 28154 }, 28155 { 28156 name: "Mul32F", 28157 argLen: 2, 28158 commutative: true, 28159 generic: true, 28160 }, 28161 { 28162 name: "Mul64F", 28163 argLen: 2, 28164 commutative: true, 28165 generic: true, 28166 }, 28167 { 28168 name: "Div32F", 28169 argLen: 2, 28170 generic: true, 28171 }, 28172 { 28173 name: "Div64F", 28174 argLen: 2, 28175 generic: true, 28176 }, 28177 { 28178 name: "Hmul32", 28179 argLen: 2, 28180 commutative: true, 28181 generic: true, 28182 }, 28183 { 28184 name: "Hmul32u", 28185 argLen: 2, 28186 commutative: true, 28187 generic: true, 28188 }, 28189 { 28190 name: "Hmul64", 28191 argLen: 2, 28192 commutative: true, 28193 generic: true, 28194 }, 28195 { 28196 name: "Hmul64u", 28197 argLen: 2, 28198 commutative: true, 28199 generic: true, 28200 }, 28201 { 28202 name: "Mul32uhilo", 28203 argLen: 2, 28204 commutative: true, 28205 generic: true, 28206 }, 28207 { 28208 name: "Mul64uhilo", 28209 argLen: 2, 28210 commutative: true, 28211 generic: true, 28212 }, 28213 { 28214 name: "Mul32uover", 28215 argLen: 2, 28216 commutative: true, 28217 generic: true, 28218 }, 28219 { 28220 name: "Mul64uover", 28221 argLen: 2, 28222 commutative: true, 28223 generic: true, 28224 }, 28225 { 28226 name: "Avg32u", 28227 argLen: 2, 28228 generic: true, 28229 }, 28230 { 28231 name: "Avg64u", 28232 argLen: 2, 28233 generic: true, 28234 }, 28235 { 28236 name: "Div8", 28237 argLen: 2, 28238 generic: true, 28239 }, 28240 { 28241 name: "Div8u", 28242 argLen: 2, 28243 generic: true, 28244 }, 28245 { 28246 name: "Div16", 28247 auxType: auxBool, 28248 argLen: 2, 28249 generic: true, 28250 }, 28251 { 28252 name: "Div16u", 28253 argLen: 2, 28254 generic: true, 28255 }, 28256 { 28257 name: "Div32", 28258 auxType: auxBool, 28259 argLen: 2, 28260 generic: true, 28261 }, 28262 { 28263 name: "Div32u", 28264 argLen: 2, 28265 generic: true, 28266 }, 28267 { 28268 name: "Div64", 28269 auxType: auxBool, 28270 argLen: 2, 28271 generic: true, 28272 }, 28273 { 28274 name: "Div64u", 28275 argLen: 2, 28276 generic: true, 28277 }, 28278 { 28279 name: "Div128u", 28280 argLen: 3, 28281 generic: true, 28282 }, 28283 { 28284 name: "Mod8", 28285 argLen: 2, 28286 generic: true, 28287 }, 28288 { 28289 name: "Mod8u", 28290 argLen: 2, 28291 generic: true, 28292 }, 28293 { 28294 name: "Mod16", 28295 auxType: auxBool, 28296 argLen: 2, 28297 generic: true, 28298 }, 28299 { 28300 name: "Mod16u", 28301 argLen: 2, 28302 generic: true, 28303 }, 28304 { 28305 name: "Mod32", 28306 auxType: auxBool, 28307 argLen: 2, 28308 generic: true, 28309 }, 28310 { 28311 name: "Mod32u", 28312 argLen: 2, 28313 generic: true, 28314 }, 28315 { 28316 name: "Mod64", 28317 auxType: auxBool, 28318 argLen: 2, 28319 generic: true, 28320 }, 28321 { 28322 name: "Mod64u", 28323 argLen: 2, 28324 generic: true, 28325 }, 28326 { 28327 name: "And8", 28328 argLen: 2, 28329 commutative: true, 28330 generic: true, 28331 }, 28332 { 28333 name: "And16", 28334 argLen: 2, 28335 commutative: true, 28336 generic: true, 28337 }, 28338 { 28339 name: "And32", 28340 argLen: 2, 28341 commutative: true, 28342 generic: true, 28343 }, 28344 { 28345 name: "And64", 28346 argLen: 2, 28347 commutative: true, 28348 generic: true, 28349 }, 28350 { 28351 name: "Or8", 28352 argLen: 2, 28353 commutative: true, 28354 generic: true, 28355 }, 28356 { 28357 name: "Or16", 28358 argLen: 2, 28359 commutative: true, 28360 generic: true, 28361 }, 28362 { 28363 name: "Or32", 28364 argLen: 2, 28365 commutative: true, 28366 generic: true, 28367 }, 28368 { 28369 name: "Or64", 28370 argLen: 2, 28371 commutative: true, 28372 generic: true, 28373 }, 28374 { 28375 name: "Xor8", 28376 argLen: 2, 28377 commutative: true, 28378 generic: true, 28379 }, 28380 { 28381 name: "Xor16", 28382 argLen: 2, 28383 commutative: true, 28384 generic: true, 28385 }, 28386 { 28387 name: "Xor32", 28388 argLen: 2, 28389 commutative: true, 28390 generic: true, 28391 }, 28392 { 28393 name: "Xor64", 28394 argLen: 2, 28395 commutative: true, 28396 generic: true, 28397 }, 28398 { 28399 name: "Lsh8x8", 28400 auxType: auxBool, 28401 argLen: 2, 28402 generic: true, 28403 }, 28404 { 28405 name: "Lsh8x16", 28406 auxType: auxBool, 28407 argLen: 2, 28408 generic: true, 28409 }, 28410 { 28411 name: "Lsh8x32", 28412 auxType: auxBool, 28413 argLen: 2, 28414 generic: true, 28415 }, 28416 { 28417 name: "Lsh8x64", 28418 auxType: auxBool, 28419 argLen: 2, 28420 generic: true, 28421 }, 28422 { 28423 name: "Lsh16x8", 28424 auxType: auxBool, 28425 argLen: 2, 28426 generic: true, 28427 }, 28428 { 28429 name: "Lsh16x16", 28430 auxType: auxBool, 28431 argLen: 2, 28432 generic: true, 28433 }, 28434 { 28435 name: "Lsh16x32", 28436 auxType: auxBool, 28437 argLen: 2, 28438 generic: true, 28439 }, 28440 { 28441 name: "Lsh16x64", 28442 auxType: auxBool, 28443 argLen: 2, 28444 generic: true, 28445 }, 28446 { 28447 name: "Lsh32x8", 28448 auxType: auxBool, 28449 argLen: 2, 28450 generic: true, 28451 }, 28452 { 28453 name: "Lsh32x16", 28454 auxType: auxBool, 28455 argLen: 2, 28456 generic: true, 28457 }, 28458 { 28459 name: "Lsh32x32", 28460 auxType: auxBool, 28461 argLen: 2, 28462 generic: true, 28463 }, 28464 { 28465 name: "Lsh32x64", 28466 auxType: auxBool, 28467 argLen: 2, 28468 generic: true, 28469 }, 28470 { 28471 name: "Lsh64x8", 28472 auxType: auxBool, 28473 argLen: 2, 28474 generic: true, 28475 }, 28476 { 28477 name: "Lsh64x16", 28478 auxType: auxBool, 28479 argLen: 2, 28480 generic: true, 28481 }, 28482 { 28483 name: "Lsh64x32", 28484 auxType: auxBool, 28485 argLen: 2, 28486 generic: true, 28487 }, 28488 { 28489 name: "Lsh64x64", 28490 auxType: auxBool, 28491 argLen: 2, 28492 generic: true, 28493 }, 28494 { 28495 name: "Rsh8x8", 28496 auxType: auxBool, 28497 argLen: 2, 28498 generic: true, 28499 }, 28500 { 28501 name: "Rsh8x16", 28502 auxType: auxBool, 28503 argLen: 2, 28504 generic: true, 28505 }, 28506 { 28507 name: "Rsh8x32", 28508 auxType: auxBool, 28509 argLen: 2, 28510 generic: true, 28511 }, 28512 { 28513 name: "Rsh8x64", 28514 auxType: auxBool, 28515 argLen: 2, 28516 generic: true, 28517 }, 28518 { 28519 name: "Rsh16x8", 28520 auxType: auxBool, 28521 argLen: 2, 28522 generic: true, 28523 }, 28524 { 28525 name: "Rsh16x16", 28526 auxType: auxBool, 28527 argLen: 2, 28528 generic: true, 28529 }, 28530 { 28531 name: "Rsh16x32", 28532 auxType: auxBool, 28533 argLen: 2, 28534 generic: true, 28535 }, 28536 { 28537 name: "Rsh16x64", 28538 auxType: auxBool, 28539 argLen: 2, 28540 generic: true, 28541 }, 28542 { 28543 name: "Rsh32x8", 28544 auxType: auxBool, 28545 argLen: 2, 28546 generic: true, 28547 }, 28548 { 28549 name: "Rsh32x16", 28550 auxType: auxBool, 28551 argLen: 2, 28552 generic: true, 28553 }, 28554 { 28555 name: "Rsh32x32", 28556 auxType: auxBool, 28557 argLen: 2, 28558 generic: true, 28559 }, 28560 { 28561 name: "Rsh32x64", 28562 auxType: auxBool, 28563 argLen: 2, 28564 generic: true, 28565 }, 28566 { 28567 name: "Rsh64x8", 28568 auxType: auxBool, 28569 argLen: 2, 28570 generic: true, 28571 }, 28572 { 28573 name: "Rsh64x16", 28574 auxType: auxBool, 28575 argLen: 2, 28576 generic: true, 28577 }, 28578 { 28579 name: "Rsh64x32", 28580 auxType: auxBool, 28581 argLen: 2, 28582 generic: true, 28583 }, 28584 { 28585 name: "Rsh64x64", 28586 auxType: auxBool, 28587 argLen: 2, 28588 generic: true, 28589 }, 28590 { 28591 name: "Rsh8Ux8", 28592 auxType: auxBool, 28593 argLen: 2, 28594 generic: true, 28595 }, 28596 { 28597 name: "Rsh8Ux16", 28598 auxType: auxBool, 28599 argLen: 2, 28600 generic: true, 28601 }, 28602 { 28603 name: "Rsh8Ux32", 28604 auxType: auxBool, 28605 argLen: 2, 28606 generic: true, 28607 }, 28608 { 28609 name: "Rsh8Ux64", 28610 auxType: auxBool, 28611 argLen: 2, 28612 generic: true, 28613 }, 28614 { 28615 name: "Rsh16Ux8", 28616 auxType: auxBool, 28617 argLen: 2, 28618 generic: true, 28619 }, 28620 { 28621 name: "Rsh16Ux16", 28622 auxType: auxBool, 28623 argLen: 2, 28624 generic: true, 28625 }, 28626 { 28627 name: "Rsh16Ux32", 28628 auxType: auxBool, 28629 argLen: 2, 28630 generic: true, 28631 }, 28632 { 28633 name: "Rsh16Ux64", 28634 auxType: auxBool, 28635 argLen: 2, 28636 generic: true, 28637 }, 28638 { 28639 name: "Rsh32Ux8", 28640 auxType: auxBool, 28641 argLen: 2, 28642 generic: true, 28643 }, 28644 { 28645 name: "Rsh32Ux16", 28646 auxType: auxBool, 28647 argLen: 2, 28648 generic: true, 28649 }, 28650 { 28651 name: "Rsh32Ux32", 28652 auxType: auxBool, 28653 argLen: 2, 28654 generic: true, 28655 }, 28656 { 28657 name: "Rsh32Ux64", 28658 auxType: auxBool, 28659 argLen: 2, 28660 generic: true, 28661 }, 28662 { 28663 name: "Rsh64Ux8", 28664 auxType: auxBool, 28665 argLen: 2, 28666 generic: true, 28667 }, 28668 { 28669 name: "Rsh64Ux16", 28670 auxType: auxBool, 28671 argLen: 2, 28672 generic: true, 28673 }, 28674 { 28675 name: "Rsh64Ux32", 28676 auxType: auxBool, 28677 argLen: 2, 28678 generic: true, 28679 }, 28680 { 28681 name: "Rsh64Ux64", 28682 auxType: auxBool, 28683 argLen: 2, 28684 generic: true, 28685 }, 28686 { 28687 name: "Eq8", 28688 argLen: 2, 28689 commutative: true, 28690 generic: true, 28691 }, 28692 { 28693 name: "Eq16", 28694 argLen: 2, 28695 commutative: true, 28696 generic: true, 28697 }, 28698 { 28699 name: "Eq32", 28700 argLen: 2, 28701 commutative: true, 28702 generic: true, 28703 }, 28704 { 28705 name: "Eq64", 28706 argLen: 2, 28707 commutative: true, 28708 generic: true, 28709 }, 28710 { 28711 name: "EqPtr", 28712 argLen: 2, 28713 commutative: true, 28714 generic: true, 28715 }, 28716 { 28717 name: "EqInter", 28718 argLen: 2, 28719 generic: true, 28720 }, 28721 { 28722 name: "EqSlice", 28723 argLen: 2, 28724 generic: true, 28725 }, 28726 { 28727 name: "Eq32F", 28728 argLen: 2, 28729 commutative: true, 28730 generic: true, 28731 }, 28732 { 28733 name: "Eq64F", 28734 argLen: 2, 28735 commutative: true, 28736 generic: true, 28737 }, 28738 { 28739 name: "Neq8", 28740 argLen: 2, 28741 commutative: true, 28742 generic: true, 28743 }, 28744 { 28745 name: "Neq16", 28746 argLen: 2, 28747 commutative: true, 28748 generic: true, 28749 }, 28750 { 28751 name: "Neq32", 28752 argLen: 2, 28753 commutative: true, 28754 generic: true, 28755 }, 28756 { 28757 name: "Neq64", 28758 argLen: 2, 28759 commutative: true, 28760 generic: true, 28761 }, 28762 { 28763 name: "NeqPtr", 28764 argLen: 2, 28765 commutative: true, 28766 generic: true, 28767 }, 28768 { 28769 name: "NeqInter", 28770 argLen: 2, 28771 generic: true, 28772 }, 28773 { 28774 name: "NeqSlice", 28775 argLen: 2, 28776 generic: true, 28777 }, 28778 { 28779 name: "Neq32F", 28780 argLen: 2, 28781 commutative: true, 28782 generic: true, 28783 }, 28784 { 28785 name: "Neq64F", 28786 argLen: 2, 28787 commutative: true, 28788 generic: true, 28789 }, 28790 { 28791 name: "Less8", 28792 argLen: 2, 28793 generic: true, 28794 }, 28795 { 28796 name: "Less8U", 28797 argLen: 2, 28798 generic: true, 28799 }, 28800 { 28801 name: "Less16", 28802 argLen: 2, 28803 generic: true, 28804 }, 28805 { 28806 name: "Less16U", 28807 argLen: 2, 28808 generic: true, 28809 }, 28810 { 28811 name: "Less32", 28812 argLen: 2, 28813 generic: true, 28814 }, 28815 { 28816 name: "Less32U", 28817 argLen: 2, 28818 generic: true, 28819 }, 28820 { 28821 name: "Less64", 28822 argLen: 2, 28823 generic: true, 28824 }, 28825 { 28826 name: "Less64U", 28827 argLen: 2, 28828 generic: true, 28829 }, 28830 { 28831 name: "Less32F", 28832 argLen: 2, 28833 generic: true, 28834 }, 28835 { 28836 name: "Less64F", 28837 argLen: 2, 28838 generic: true, 28839 }, 28840 { 28841 name: "Leq8", 28842 argLen: 2, 28843 generic: true, 28844 }, 28845 { 28846 name: "Leq8U", 28847 argLen: 2, 28848 generic: true, 28849 }, 28850 { 28851 name: "Leq16", 28852 argLen: 2, 28853 generic: true, 28854 }, 28855 { 28856 name: "Leq16U", 28857 argLen: 2, 28858 generic: true, 28859 }, 28860 { 28861 name: "Leq32", 28862 argLen: 2, 28863 generic: true, 28864 }, 28865 { 28866 name: "Leq32U", 28867 argLen: 2, 28868 generic: true, 28869 }, 28870 { 28871 name: "Leq64", 28872 argLen: 2, 28873 generic: true, 28874 }, 28875 { 28876 name: "Leq64U", 28877 argLen: 2, 28878 generic: true, 28879 }, 28880 { 28881 name: "Leq32F", 28882 argLen: 2, 28883 generic: true, 28884 }, 28885 { 28886 name: "Leq64F", 28887 argLen: 2, 28888 generic: true, 28889 }, 28890 { 28891 name: "Greater8", 28892 argLen: 2, 28893 generic: true, 28894 }, 28895 { 28896 name: "Greater8U", 28897 argLen: 2, 28898 generic: true, 28899 }, 28900 { 28901 name: "Greater16", 28902 argLen: 2, 28903 generic: true, 28904 }, 28905 { 28906 name: "Greater16U", 28907 argLen: 2, 28908 generic: true, 28909 }, 28910 { 28911 name: "Greater32", 28912 argLen: 2, 28913 generic: true, 28914 }, 28915 { 28916 name: "Greater32U", 28917 argLen: 2, 28918 generic: true, 28919 }, 28920 { 28921 name: "Greater64", 28922 argLen: 2, 28923 generic: true, 28924 }, 28925 { 28926 name: "Greater64U", 28927 argLen: 2, 28928 generic: true, 28929 }, 28930 { 28931 name: "Greater32F", 28932 argLen: 2, 28933 generic: true, 28934 }, 28935 { 28936 name: "Greater64F", 28937 argLen: 2, 28938 generic: true, 28939 }, 28940 { 28941 name: "Geq8", 28942 argLen: 2, 28943 generic: true, 28944 }, 28945 { 28946 name: "Geq8U", 28947 argLen: 2, 28948 generic: true, 28949 }, 28950 { 28951 name: "Geq16", 28952 argLen: 2, 28953 generic: true, 28954 }, 28955 { 28956 name: "Geq16U", 28957 argLen: 2, 28958 generic: true, 28959 }, 28960 { 28961 name: "Geq32", 28962 argLen: 2, 28963 generic: true, 28964 }, 28965 { 28966 name: "Geq32U", 28967 argLen: 2, 28968 generic: true, 28969 }, 28970 { 28971 name: "Geq64", 28972 argLen: 2, 28973 generic: true, 28974 }, 28975 { 28976 name: "Geq64U", 28977 argLen: 2, 28978 generic: true, 28979 }, 28980 { 28981 name: "Geq32F", 28982 argLen: 2, 28983 generic: true, 28984 }, 28985 { 28986 name: "Geq64F", 28987 argLen: 2, 28988 generic: true, 28989 }, 28990 { 28991 name: "CondSelect", 28992 argLen: 3, 28993 generic: true, 28994 }, 28995 { 28996 name: "AndB", 28997 argLen: 2, 28998 commutative: true, 28999 generic: true, 29000 }, 29001 { 29002 name: "OrB", 29003 argLen: 2, 29004 commutative: true, 29005 generic: true, 29006 }, 29007 { 29008 name: "EqB", 29009 argLen: 2, 29010 commutative: true, 29011 generic: true, 29012 }, 29013 { 29014 name: "NeqB", 29015 argLen: 2, 29016 commutative: true, 29017 generic: true, 29018 }, 29019 { 29020 name: "Not", 29021 argLen: 1, 29022 generic: true, 29023 }, 29024 { 29025 name: "Neg8", 29026 argLen: 1, 29027 generic: true, 29028 }, 29029 { 29030 name: "Neg16", 29031 argLen: 1, 29032 generic: true, 29033 }, 29034 { 29035 name: "Neg32", 29036 argLen: 1, 29037 generic: true, 29038 }, 29039 { 29040 name: "Neg64", 29041 argLen: 1, 29042 generic: true, 29043 }, 29044 { 29045 name: "Neg32F", 29046 argLen: 1, 29047 generic: true, 29048 }, 29049 { 29050 name: "Neg64F", 29051 argLen: 1, 29052 generic: true, 29053 }, 29054 { 29055 name: "Com8", 29056 argLen: 1, 29057 generic: true, 29058 }, 29059 { 29060 name: "Com16", 29061 argLen: 1, 29062 generic: true, 29063 }, 29064 { 29065 name: "Com32", 29066 argLen: 1, 29067 generic: true, 29068 }, 29069 { 29070 name: "Com64", 29071 argLen: 1, 29072 generic: true, 29073 }, 29074 { 29075 name: "Ctz8", 29076 argLen: 1, 29077 generic: true, 29078 }, 29079 { 29080 name: "Ctz16", 29081 argLen: 1, 29082 generic: true, 29083 }, 29084 { 29085 name: "Ctz32", 29086 argLen: 1, 29087 generic: true, 29088 }, 29089 { 29090 name: "Ctz64", 29091 argLen: 1, 29092 generic: true, 29093 }, 29094 { 29095 name: "Ctz8NonZero", 29096 argLen: 1, 29097 generic: true, 29098 }, 29099 { 29100 name: "Ctz16NonZero", 29101 argLen: 1, 29102 generic: true, 29103 }, 29104 { 29105 name: "Ctz32NonZero", 29106 argLen: 1, 29107 generic: true, 29108 }, 29109 { 29110 name: "Ctz64NonZero", 29111 argLen: 1, 29112 generic: true, 29113 }, 29114 { 29115 name: "BitLen8", 29116 argLen: 1, 29117 generic: true, 29118 }, 29119 { 29120 name: "BitLen16", 29121 argLen: 1, 29122 generic: true, 29123 }, 29124 { 29125 name: "BitLen32", 29126 argLen: 1, 29127 generic: true, 29128 }, 29129 { 29130 name: "BitLen64", 29131 argLen: 1, 29132 generic: true, 29133 }, 29134 { 29135 name: "Bswap32", 29136 argLen: 1, 29137 generic: true, 29138 }, 29139 { 29140 name: "Bswap64", 29141 argLen: 1, 29142 generic: true, 29143 }, 29144 { 29145 name: "BitRev8", 29146 argLen: 1, 29147 generic: true, 29148 }, 29149 { 29150 name: "BitRev16", 29151 argLen: 1, 29152 generic: true, 29153 }, 29154 { 29155 name: "BitRev32", 29156 argLen: 1, 29157 generic: true, 29158 }, 29159 { 29160 name: "BitRev64", 29161 argLen: 1, 29162 generic: true, 29163 }, 29164 { 29165 name: "PopCount8", 29166 argLen: 1, 29167 generic: true, 29168 }, 29169 { 29170 name: "PopCount16", 29171 argLen: 1, 29172 generic: true, 29173 }, 29174 { 29175 name: "PopCount32", 29176 argLen: 1, 29177 generic: true, 29178 }, 29179 { 29180 name: "PopCount64", 29181 argLen: 1, 29182 generic: true, 29183 }, 29184 { 29185 name: "RotateLeft8", 29186 argLen: 2, 29187 generic: true, 29188 }, 29189 { 29190 name: "RotateLeft16", 29191 argLen: 2, 29192 generic: true, 29193 }, 29194 { 29195 name: "RotateLeft32", 29196 argLen: 2, 29197 generic: true, 29198 }, 29199 { 29200 name: "RotateLeft64", 29201 argLen: 2, 29202 generic: true, 29203 }, 29204 { 29205 name: "Sqrt", 29206 argLen: 1, 29207 generic: true, 29208 }, 29209 { 29210 name: "Floor", 29211 argLen: 1, 29212 generic: true, 29213 }, 29214 { 29215 name: "Ceil", 29216 argLen: 1, 29217 generic: true, 29218 }, 29219 { 29220 name: "Trunc", 29221 argLen: 1, 29222 generic: true, 29223 }, 29224 { 29225 name: "Round", 29226 argLen: 1, 29227 generic: true, 29228 }, 29229 { 29230 name: "RoundToEven", 29231 argLen: 1, 29232 generic: true, 29233 }, 29234 { 29235 name: "Abs", 29236 argLen: 1, 29237 generic: true, 29238 }, 29239 { 29240 name: "Copysign", 29241 argLen: 2, 29242 generic: true, 29243 }, 29244 { 29245 name: "Phi", 29246 argLen: -1, 29247 zeroWidth: true, 29248 generic: true, 29249 }, 29250 { 29251 name: "Copy", 29252 argLen: 1, 29253 generic: true, 29254 }, 29255 { 29256 name: "Convert", 29257 argLen: 2, 29258 resultInArg0: true, 29259 zeroWidth: true, 29260 generic: true, 29261 }, 29262 { 29263 name: "ConstBool", 29264 auxType: auxBool, 29265 argLen: 0, 29266 generic: true, 29267 }, 29268 { 29269 name: "ConstString", 29270 auxType: auxString, 29271 argLen: 0, 29272 generic: true, 29273 }, 29274 { 29275 name: "ConstNil", 29276 argLen: 0, 29277 generic: true, 29278 }, 29279 { 29280 name: "Const8", 29281 auxType: auxInt8, 29282 argLen: 0, 29283 generic: true, 29284 }, 29285 { 29286 name: "Const16", 29287 auxType: auxInt16, 29288 argLen: 0, 29289 generic: true, 29290 }, 29291 { 29292 name: "Const32", 29293 auxType: auxInt32, 29294 argLen: 0, 29295 generic: true, 29296 }, 29297 { 29298 name: "Const64", 29299 auxType: auxInt64, 29300 argLen: 0, 29301 generic: true, 29302 }, 29303 { 29304 name: "Const32F", 29305 auxType: auxFloat32, 29306 argLen: 0, 29307 generic: true, 29308 }, 29309 { 29310 name: "Const64F", 29311 auxType: auxFloat64, 29312 argLen: 0, 29313 generic: true, 29314 }, 29315 { 29316 name: "ConstInterface", 29317 argLen: 0, 29318 generic: true, 29319 }, 29320 { 29321 name: "ConstSlice", 29322 argLen: 0, 29323 generic: true, 29324 }, 29325 { 29326 name: "InitMem", 29327 argLen: 0, 29328 zeroWidth: true, 29329 generic: true, 29330 }, 29331 { 29332 name: "Arg", 29333 auxType: auxSymOff, 29334 argLen: 0, 29335 zeroWidth: true, 29336 symEffect: SymRead, 29337 generic: true, 29338 }, 29339 { 29340 name: "Addr", 29341 auxType: auxSym, 29342 argLen: 1, 29343 symEffect: SymAddr, 29344 generic: true, 29345 }, 29346 { 29347 name: "LocalAddr", 29348 auxType: auxSym, 29349 argLen: 2, 29350 symEffect: SymAddr, 29351 generic: true, 29352 }, 29353 { 29354 name: "SP", 29355 argLen: 0, 29356 zeroWidth: true, 29357 generic: true, 29358 }, 29359 { 29360 name: "SB", 29361 argLen: 0, 29362 zeroWidth: true, 29363 generic: true, 29364 }, 29365 { 29366 name: "Load", 29367 argLen: 2, 29368 generic: true, 29369 }, 29370 { 29371 name: "Store", 29372 auxType: auxTyp, 29373 argLen: 3, 29374 generic: true, 29375 }, 29376 { 29377 name: "Move", 29378 auxType: auxTypSize, 29379 argLen: 3, 29380 generic: true, 29381 }, 29382 { 29383 name: "Zero", 29384 auxType: auxTypSize, 29385 argLen: 2, 29386 generic: true, 29387 }, 29388 { 29389 name: "StoreWB", 29390 auxType: auxTyp, 29391 argLen: 3, 29392 generic: true, 29393 }, 29394 { 29395 name: "MoveWB", 29396 auxType: auxTypSize, 29397 argLen: 3, 29398 generic: true, 29399 }, 29400 { 29401 name: "ZeroWB", 29402 auxType: auxTypSize, 29403 argLen: 2, 29404 generic: true, 29405 }, 29406 { 29407 name: "WB", 29408 auxType: auxSym, 29409 argLen: 3, 29410 symEffect: SymNone, 29411 generic: true, 29412 }, 29413 { 29414 name: "ClosureCall", 29415 auxType: auxInt64, 29416 argLen: 3, 29417 call: true, 29418 generic: true, 29419 }, 29420 { 29421 name: "StaticCall", 29422 auxType: auxSymOff, 29423 argLen: 1, 29424 call: true, 29425 symEffect: SymNone, 29426 generic: true, 29427 }, 29428 { 29429 name: "InterCall", 29430 auxType: auxInt64, 29431 argLen: 2, 29432 call: true, 29433 generic: true, 29434 }, 29435 { 29436 name: "SignExt8to16", 29437 argLen: 1, 29438 generic: true, 29439 }, 29440 { 29441 name: "SignExt8to32", 29442 argLen: 1, 29443 generic: true, 29444 }, 29445 { 29446 name: "SignExt8to64", 29447 argLen: 1, 29448 generic: true, 29449 }, 29450 { 29451 name: "SignExt16to32", 29452 argLen: 1, 29453 generic: true, 29454 }, 29455 { 29456 name: "SignExt16to64", 29457 argLen: 1, 29458 generic: true, 29459 }, 29460 { 29461 name: "SignExt32to64", 29462 argLen: 1, 29463 generic: true, 29464 }, 29465 { 29466 name: "ZeroExt8to16", 29467 argLen: 1, 29468 generic: true, 29469 }, 29470 { 29471 name: "ZeroExt8to32", 29472 argLen: 1, 29473 generic: true, 29474 }, 29475 { 29476 name: "ZeroExt8to64", 29477 argLen: 1, 29478 generic: true, 29479 }, 29480 { 29481 name: "ZeroExt16to32", 29482 argLen: 1, 29483 generic: true, 29484 }, 29485 { 29486 name: "ZeroExt16to64", 29487 argLen: 1, 29488 generic: true, 29489 }, 29490 { 29491 name: "ZeroExt32to64", 29492 argLen: 1, 29493 generic: true, 29494 }, 29495 { 29496 name: "Trunc16to8", 29497 argLen: 1, 29498 generic: true, 29499 }, 29500 { 29501 name: "Trunc32to8", 29502 argLen: 1, 29503 generic: true, 29504 }, 29505 { 29506 name: "Trunc32to16", 29507 argLen: 1, 29508 generic: true, 29509 }, 29510 { 29511 name: "Trunc64to8", 29512 argLen: 1, 29513 generic: true, 29514 }, 29515 { 29516 name: "Trunc64to16", 29517 argLen: 1, 29518 generic: true, 29519 }, 29520 { 29521 name: "Trunc64to32", 29522 argLen: 1, 29523 generic: true, 29524 }, 29525 { 29526 name: "Cvt32to32F", 29527 argLen: 1, 29528 generic: true, 29529 }, 29530 { 29531 name: "Cvt32to64F", 29532 argLen: 1, 29533 generic: true, 29534 }, 29535 { 29536 name: "Cvt64to32F", 29537 argLen: 1, 29538 generic: true, 29539 }, 29540 { 29541 name: "Cvt64to64F", 29542 argLen: 1, 29543 generic: true, 29544 }, 29545 { 29546 name: "Cvt32Fto32", 29547 argLen: 1, 29548 generic: true, 29549 }, 29550 { 29551 name: "Cvt32Fto64", 29552 argLen: 1, 29553 generic: true, 29554 }, 29555 { 29556 name: "Cvt64Fto32", 29557 argLen: 1, 29558 generic: true, 29559 }, 29560 { 29561 name: "Cvt64Fto64", 29562 argLen: 1, 29563 generic: true, 29564 }, 29565 { 29566 name: "Cvt32Fto64F", 29567 argLen: 1, 29568 generic: true, 29569 }, 29570 { 29571 name: "Cvt64Fto32F", 29572 argLen: 1, 29573 generic: true, 29574 }, 29575 { 29576 name: "Round32F", 29577 argLen: 1, 29578 generic: true, 29579 }, 29580 { 29581 name: "Round64F", 29582 argLen: 1, 29583 generic: true, 29584 }, 29585 { 29586 name: "IsNonNil", 29587 argLen: 1, 29588 generic: true, 29589 }, 29590 { 29591 name: "IsInBounds", 29592 argLen: 2, 29593 generic: true, 29594 }, 29595 { 29596 name: "IsSliceInBounds", 29597 argLen: 2, 29598 generic: true, 29599 }, 29600 { 29601 name: "NilCheck", 29602 argLen: 2, 29603 generic: true, 29604 }, 29605 { 29606 name: "GetG", 29607 argLen: 1, 29608 zeroWidth: true, 29609 generic: true, 29610 }, 29611 { 29612 name: "GetClosurePtr", 29613 argLen: 0, 29614 generic: true, 29615 }, 29616 { 29617 name: "GetCallerPC", 29618 argLen: 0, 29619 generic: true, 29620 }, 29621 { 29622 name: "GetCallerSP", 29623 argLen: 0, 29624 generic: true, 29625 }, 29626 { 29627 name: "PtrIndex", 29628 argLen: 2, 29629 generic: true, 29630 }, 29631 { 29632 name: "OffPtr", 29633 auxType: auxInt64, 29634 argLen: 1, 29635 generic: true, 29636 }, 29637 { 29638 name: "SliceMake", 29639 argLen: 3, 29640 generic: true, 29641 }, 29642 { 29643 name: "SlicePtr", 29644 argLen: 1, 29645 generic: true, 29646 }, 29647 { 29648 name: "SliceLen", 29649 argLen: 1, 29650 generic: true, 29651 }, 29652 { 29653 name: "SliceCap", 29654 argLen: 1, 29655 generic: true, 29656 }, 29657 { 29658 name: "ComplexMake", 29659 argLen: 2, 29660 generic: true, 29661 }, 29662 { 29663 name: "ComplexReal", 29664 argLen: 1, 29665 generic: true, 29666 }, 29667 { 29668 name: "ComplexImag", 29669 argLen: 1, 29670 generic: true, 29671 }, 29672 { 29673 name: "StringMake", 29674 argLen: 2, 29675 generic: true, 29676 }, 29677 { 29678 name: "StringPtr", 29679 argLen: 1, 29680 generic: true, 29681 }, 29682 { 29683 name: "StringLen", 29684 argLen: 1, 29685 generic: true, 29686 }, 29687 { 29688 name: "IMake", 29689 argLen: 2, 29690 generic: true, 29691 }, 29692 { 29693 name: "ITab", 29694 argLen: 1, 29695 generic: true, 29696 }, 29697 { 29698 name: "IData", 29699 argLen: 1, 29700 generic: true, 29701 }, 29702 { 29703 name: "StructMake0", 29704 argLen: 0, 29705 generic: true, 29706 }, 29707 { 29708 name: "StructMake1", 29709 argLen: 1, 29710 generic: true, 29711 }, 29712 { 29713 name: "StructMake2", 29714 argLen: 2, 29715 generic: true, 29716 }, 29717 { 29718 name: "StructMake3", 29719 argLen: 3, 29720 generic: true, 29721 }, 29722 { 29723 name: "StructMake4", 29724 argLen: 4, 29725 generic: true, 29726 }, 29727 { 29728 name: "StructSelect", 29729 auxType: auxInt64, 29730 argLen: 1, 29731 generic: true, 29732 }, 29733 { 29734 name: "ArrayMake0", 29735 argLen: 0, 29736 generic: true, 29737 }, 29738 { 29739 name: "ArrayMake1", 29740 argLen: 1, 29741 generic: true, 29742 }, 29743 { 29744 name: "ArraySelect", 29745 auxType: auxInt64, 29746 argLen: 1, 29747 generic: true, 29748 }, 29749 { 29750 name: "StoreReg", 29751 argLen: 1, 29752 generic: true, 29753 }, 29754 { 29755 name: "LoadReg", 29756 argLen: 1, 29757 generic: true, 29758 }, 29759 { 29760 name: "FwdRef", 29761 auxType: auxSym, 29762 argLen: 0, 29763 symEffect: SymNone, 29764 generic: true, 29765 }, 29766 { 29767 name: "Unknown", 29768 argLen: 0, 29769 generic: true, 29770 }, 29771 { 29772 name: "VarDef", 29773 auxType: auxSym, 29774 argLen: 1, 29775 zeroWidth: true, 29776 symEffect: SymNone, 29777 generic: true, 29778 }, 29779 { 29780 name: "VarKill", 29781 auxType: auxSym, 29782 argLen: 1, 29783 symEffect: SymNone, 29784 generic: true, 29785 }, 29786 { 29787 name: "VarLive", 29788 auxType: auxSym, 29789 argLen: 1, 29790 zeroWidth: true, 29791 symEffect: SymRead, 29792 generic: true, 29793 }, 29794 { 29795 name: "KeepAlive", 29796 argLen: 2, 29797 zeroWidth: true, 29798 generic: true, 29799 }, 29800 { 29801 name: "InlMark", 29802 auxType: auxInt32, 29803 argLen: 1, 29804 generic: true, 29805 }, 29806 { 29807 name: "Int64Make", 29808 argLen: 2, 29809 generic: true, 29810 }, 29811 { 29812 name: "Int64Hi", 29813 argLen: 1, 29814 generic: true, 29815 }, 29816 { 29817 name: "Int64Lo", 29818 argLen: 1, 29819 generic: true, 29820 }, 29821 { 29822 name: "Add32carry", 29823 argLen: 2, 29824 commutative: true, 29825 generic: true, 29826 }, 29827 { 29828 name: "Add32withcarry", 29829 argLen: 3, 29830 commutative: true, 29831 generic: true, 29832 }, 29833 { 29834 name: "Sub32carry", 29835 argLen: 2, 29836 generic: true, 29837 }, 29838 { 29839 name: "Sub32withcarry", 29840 argLen: 3, 29841 generic: true, 29842 }, 29843 { 29844 name: "Add64carry", 29845 argLen: 3, 29846 commutative: true, 29847 generic: true, 29848 }, 29849 { 29850 name: "Sub64borrow", 29851 argLen: 3, 29852 generic: true, 29853 }, 29854 { 29855 name: "Signmask", 29856 argLen: 1, 29857 generic: true, 29858 }, 29859 { 29860 name: "Zeromask", 29861 argLen: 1, 29862 generic: true, 29863 }, 29864 { 29865 name: "Slicemask", 29866 argLen: 1, 29867 generic: true, 29868 }, 29869 { 29870 name: "Cvt32Uto32F", 29871 argLen: 1, 29872 generic: true, 29873 }, 29874 { 29875 name: "Cvt32Uto64F", 29876 argLen: 1, 29877 generic: true, 29878 }, 29879 { 29880 name: "Cvt32Fto32U", 29881 argLen: 1, 29882 generic: true, 29883 }, 29884 { 29885 name: "Cvt64Fto32U", 29886 argLen: 1, 29887 generic: true, 29888 }, 29889 { 29890 name: "Cvt64Uto32F", 29891 argLen: 1, 29892 generic: true, 29893 }, 29894 { 29895 name: "Cvt64Uto64F", 29896 argLen: 1, 29897 generic: true, 29898 }, 29899 { 29900 name: "Cvt32Fto64U", 29901 argLen: 1, 29902 generic: true, 29903 }, 29904 { 29905 name: "Cvt64Fto64U", 29906 argLen: 1, 29907 generic: true, 29908 }, 29909 { 29910 name: "Select0", 29911 argLen: 1, 29912 zeroWidth: true, 29913 generic: true, 29914 }, 29915 { 29916 name: "Select1", 29917 argLen: 1, 29918 zeroWidth: true, 29919 generic: true, 29920 }, 29921 { 29922 name: "AtomicLoad32", 29923 argLen: 2, 29924 generic: true, 29925 }, 29926 { 29927 name: "AtomicLoad64", 29928 argLen: 2, 29929 generic: true, 29930 }, 29931 { 29932 name: "AtomicLoadPtr", 29933 argLen: 2, 29934 generic: true, 29935 }, 29936 { 29937 name: "AtomicLoadAcq32", 29938 argLen: 2, 29939 generic: true, 29940 }, 29941 { 29942 name: "AtomicStore32", 29943 argLen: 3, 29944 hasSideEffects: true, 29945 generic: true, 29946 }, 29947 { 29948 name: "AtomicStore64", 29949 argLen: 3, 29950 hasSideEffects: true, 29951 generic: true, 29952 }, 29953 { 29954 name: "AtomicStorePtrNoWB", 29955 argLen: 3, 29956 hasSideEffects: true, 29957 generic: true, 29958 }, 29959 { 29960 name: "AtomicStoreRel32", 29961 argLen: 3, 29962 hasSideEffects: true, 29963 generic: true, 29964 }, 29965 { 29966 name: "AtomicExchange32", 29967 argLen: 3, 29968 hasSideEffects: true, 29969 generic: true, 29970 }, 29971 { 29972 name: "AtomicExchange64", 29973 argLen: 3, 29974 hasSideEffects: true, 29975 generic: true, 29976 }, 29977 { 29978 name: "AtomicAdd32", 29979 argLen: 3, 29980 hasSideEffects: true, 29981 generic: true, 29982 }, 29983 { 29984 name: "AtomicAdd64", 29985 argLen: 3, 29986 hasSideEffects: true, 29987 generic: true, 29988 }, 29989 { 29990 name: "AtomicCompareAndSwap32", 29991 argLen: 4, 29992 hasSideEffects: true, 29993 generic: true, 29994 }, 29995 { 29996 name: "AtomicCompareAndSwap64", 29997 argLen: 4, 29998 hasSideEffects: true, 29999 generic: true, 30000 }, 30001 { 30002 name: "AtomicCompareAndSwapRel32", 30003 argLen: 4, 30004 hasSideEffects: true, 30005 generic: true, 30006 }, 30007 { 30008 name: "AtomicAnd8", 30009 argLen: 3, 30010 hasSideEffects: true, 30011 generic: true, 30012 }, 30013 { 30014 name: "AtomicOr8", 30015 argLen: 3, 30016 hasSideEffects: true, 30017 generic: true, 30018 }, 30019 { 30020 name: "AtomicAdd32Variant", 30021 argLen: 3, 30022 hasSideEffects: true, 30023 generic: true, 30024 }, 30025 { 30026 name: "AtomicAdd64Variant", 30027 argLen: 3, 30028 hasSideEffects: true, 30029 generic: true, 30030 }, 30031 { 30032 name: "Clobber", 30033 auxType: auxSymOff, 30034 argLen: 0, 30035 symEffect: SymNone, 30036 generic: true, 30037 }, 30038 } 30039 30040 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 30041 func (o Op) String() string { return opcodeTable[o].name } 30042 func (o Op) UsesScratch() bool { return opcodeTable[o].usesScratch } 30043 func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect } 30044 func (o Op) IsCall() bool { return opcodeTable[o].call } 30045 30046 var registers386 = [...]Register{ 30047 {0, x86.REG_AX, 0, "AX"}, 30048 {1, x86.REG_CX, 1, "CX"}, 30049 {2, x86.REG_DX, 2, "DX"}, 30050 {3, x86.REG_BX, 3, "BX"}, 30051 {4, x86.REGSP, -1, "SP"}, 30052 {5, x86.REG_BP, 4, "BP"}, 30053 {6, x86.REG_SI, 5, "SI"}, 30054 {7, x86.REG_DI, 6, "DI"}, 30055 {8, x86.REG_X0, -1, "X0"}, 30056 {9, x86.REG_X1, -1, "X1"}, 30057 {10, x86.REG_X2, -1, "X2"}, 30058 {11, x86.REG_X3, -1, "X3"}, 30059 {12, x86.REG_X4, -1, "X4"}, 30060 {13, x86.REG_X5, -1, "X5"}, 30061 {14, x86.REG_X6, -1, "X6"}, 30062 {15, x86.REG_X7, -1, "X7"}, 30063 {16, 0, -1, "SB"}, 30064 } 30065 var gpRegMask386 = regMask(239) 30066 var fpRegMask386 = regMask(65280) 30067 var specialRegMask386 = regMask(0) 30068 var framepointerReg386 = int8(5) 30069 var linkReg386 = int8(-1) 30070 var registersAMD64 = [...]Register{ 30071 {0, x86.REG_AX, 0, "AX"}, 30072 {1, x86.REG_CX, 1, "CX"}, 30073 {2, x86.REG_DX, 2, "DX"}, 30074 {3, x86.REG_BX, 3, "BX"}, 30075 {4, x86.REGSP, -1, "SP"}, 30076 {5, x86.REG_BP, 4, "BP"}, 30077 {6, x86.REG_SI, 5, "SI"}, 30078 {7, x86.REG_DI, 6, "DI"}, 30079 {8, x86.REG_R8, 7, "R8"}, 30080 {9, x86.REG_R9, 8, "R9"}, 30081 {10, x86.REG_R10, 9, "R10"}, 30082 {11, x86.REG_R11, 10, "R11"}, 30083 {12, x86.REG_R12, 11, "R12"}, 30084 {13, x86.REG_R13, 12, "R13"}, 30085 {14, x86.REG_R14, 13, "R14"}, 30086 {15, x86.REG_R15, 14, "R15"}, 30087 {16, x86.REG_X0, -1, "X0"}, 30088 {17, x86.REG_X1, -1, "X1"}, 30089 {18, x86.REG_X2, -1, "X2"}, 30090 {19, x86.REG_X3, -1, "X3"}, 30091 {20, x86.REG_X4, -1, "X4"}, 30092 {21, x86.REG_X5, -1, "X5"}, 30093 {22, x86.REG_X6, -1, "X6"}, 30094 {23, x86.REG_X7, -1, "X7"}, 30095 {24, x86.REG_X8, -1, "X8"}, 30096 {25, x86.REG_X9, -1, "X9"}, 30097 {26, x86.REG_X10, -1, "X10"}, 30098 {27, x86.REG_X11, -1, "X11"}, 30099 {28, x86.REG_X12, -1, "X12"}, 30100 {29, x86.REG_X13, -1, "X13"}, 30101 {30, x86.REG_X14, -1, "X14"}, 30102 {31, x86.REG_X15, -1, "X15"}, 30103 {32, 0, -1, "SB"}, 30104 } 30105 var gpRegMaskAMD64 = regMask(65519) 30106 var fpRegMaskAMD64 = regMask(4294901760) 30107 var specialRegMaskAMD64 = regMask(0) 30108 var framepointerRegAMD64 = int8(5) 30109 var linkRegAMD64 = int8(-1) 30110 var registersARM = [...]Register{ 30111 {0, arm.REG_R0, 0, "R0"}, 30112 {1, arm.REG_R1, 1, "R1"}, 30113 {2, arm.REG_R2, 2, "R2"}, 30114 {3, arm.REG_R3, 3, "R3"}, 30115 {4, arm.REG_R4, 4, "R4"}, 30116 {5, arm.REG_R5, 5, "R5"}, 30117 {6, arm.REG_R6, 6, "R6"}, 30118 {7, arm.REG_R7, 7, "R7"}, 30119 {8, arm.REG_R8, 8, "R8"}, 30120 {9, arm.REG_R9, 9, "R9"}, 30121 {10, arm.REGG, -1, "g"}, 30122 {11, arm.REG_R11, -1, "R11"}, 30123 {12, arm.REG_R12, 10, "R12"}, 30124 {13, arm.REGSP, -1, "SP"}, 30125 {14, arm.REG_R14, 11, "R14"}, 30126 {15, arm.REG_R15, -1, "R15"}, 30127 {16, arm.REG_F0, -1, "F0"}, 30128 {17, arm.REG_F1, -1, "F1"}, 30129 {18, arm.REG_F2, -1, "F2"}, 30130 {19, arm.REG_F3, -1, "F3"}, 30131 {20, arm.REG_F4, -1, "F4"}, 30132 {21, arm.REG_F5, -1, "F5"}, 30133 {22, arm.REG_F6, -1, "F6"}, 30134 {23, arm.REG_F7, -1, "F7"}, 30135 {24, arm.REG_F8, -1, "F8"}, 30136 {25, arm.REG_F9, -1, "F9"}, 30137 {26, arm.REG_F10, -1, "F10"}, 30138 {27, arm.REG_F11, -1, "F11"}, 30139 {28, arm.REG_F12, -1, "F12"}, 30140 {29, arm.REG_F13, -1, "F13"}, 30141 {30, arm.REG_F14, -1, "F14"}, 30142 {31, arm.REG_F15, -1, "F15"}, 30143 {32, 0, -1, "SB"}, 30144 } 30145 var gpRegMaskARM = regMask(21503) 30146 var fpRegMaskARM = regMask(4294901760) 30147 var specialRegMaskARM = regMask(0) 30148 var framepointerRegARM = int8(-1) 30149 var linkRegARM = int8(14) 30150 var registersARM64 = [...]Register{ 30151 {0, arm64.REG_R0, 0, "R0"}, 30152 {1, arm64.REG_R1, 1, "R1"}, 30153 {2, arm64.REG_R2, 2, "R2"}, 30154 {3, arm64.REG_R3, 3, "R3"}, 30155 {4, arm64.REG_R4, 4, "R4"}, 30156 {5, arm64.REG_R5, 5, "R5"}, 30157 {6, arm64.REG_R6, 6, "R6"}, 30158 {7, arm64.REG_R7, 7, "R7"}, 30159 {8, arm64.REG_R8, 8, "R8"}, 30160 {9, arm64.REG_R9, 9, "R9"}, 30161 {10, arm64.REG_R10, 10, "R10"}, 30162 {11, arm64.REG_R11, 11, "R11"}, 30163 {12, arm64.REG_R12, 12, "R12"}, 30164 {13, arm64.REG_R13, 13, "R13"}, 30165 {14, arm64.REG_R14, 14, "R14"}, 30166 {15, arm64.REG_R15, 15, "R15"}, 30167 {16, arm64.REG_R16, 16, "R16"}, 30168 {17, arm64.REG_R17, 17, "R17"}, 30169 {18, arm64.REG_R18, -1, "R18"}, 30170 {19, arm64.REG_R19, 18, "R19"}, 30171 {20, arm64.REG_R20, 19, "R20"}, 30172 {21, arm64.REG_R21, 20, "R21"}, 30173 {22, arm64.REG_R22, 21, "R22"}, 30174 {23, arm64.REG_R23, 22, "R23"}, 30175 {24, arm64.REG_R24, 23, "R24"}, 30176 {25, arm64.REG_R25, 24, "R25"}, 30177 {26, arm64.REG_R26, 25, "R26"}, 30178 {27, arm64.REGG, -1, "g"}, 30179 {28, arm64.REG_R29, -1, "R29"}, 30180 {29, arm64.REG_R30, 26, "R30"}, 30181 {30, arm64.REGSP, -1, "SP"}, 30182 {31, arm64.REG_F0, -1, "F0"}, 30183 {32, arm64.REG_F1, -1, "F1"}, 30184 {33, arm64.REG_F2, -1, "F2"}, 30185 {34, arm64.REG_F3, -1, "F3"}, 30186 {35, arm64.REG_F4, -1, "F4"}, 30187 {36, arm64.REG_F5, -1, "F5"}, 30188 {37, arm64.REG_F6, -1, "F6"}, 30189 {38, arm64.REG_F7, -1, "F7"}, 30190 {39, arm64.REG_F8, -1, "F8"}, 30191 {40, arm64.REG_F9, -1, "F9"}, 30192 {41, arm64.REG_F10, -1, "F10"}, 30193 {42, arm64.REG_F11, -1, "F11"}, 30194 {43, arm64.REG_F12, -1, "F12"}, 30195 {44, arm64.REG_F13, -1, "F13"}, 30196 {45, arm64.REG_F14, -1, "F14"}, 30197 {46, arm64.REG_F15, -1, "F15"}, 30198 {47, arm64.REG_F16, -1, "F16"}, 30199 {48, arm64.REG_F17, -1, "F17"}, 30200 {49, arm64.REG_F18, -1, "F18"}, 30201 {50, arm64.REG_F19, -1, "F19"}, 30202 {51, arm64.REG_F20, -1, "F20"}, 30203 {52, arm64.REG_F21, -1, "F21"}, 30204 {53, arm64.REG_F22, -1, "F22"}, 30205 {54, arm64.REG_F23, -1, "F23"}, 30206 {55, arm64.REG_F24, -1, "F24"}, 30207 {56, arm64.REG_F25, -1, "F25"}, 30208 {57, arm64.REG_F26, -1, "F26"}, 30209 {58, arm64.REG_F27, -1, "F27"}, 30210 {59, arm64.REG_F28, -1, "F28"}, 30211 {60, arm64.REG_F29, -1, "F29"}, 30212 {61, arm64.REG_F30, -1, "F30"}, 30213 {62, arm64.REG_F31, -1, "F31"}, 30214 {63, 0, -1, "SB"}, 30215 } 30216 var gpRegMaskARM64 = regMask(670826495) 30217 var fpRegMaskARM64 = regMask(9223372034707292160) 30218 var specialRegMaskARM64 = regMask(0) 30219 var framepointerRegARM64 = int8(-1) 30220 var linkRegARM64 = int8(29) 30221 var registersMIPS = [...]Register{ 30222 {0, mips.REG_R0, -1, "R0"}, 30223 {1, mips.REG_R1, 0, "R1"}, 30224 {2, mips.REG_R2, 1, "R2"}, 30225 {3, mips.REG_R3, 2, "R3"}, 30226 {4, mips.REG_R4, 3, "R4"}, 30227 {5, mips.REG_R5, 4, "R5"}, 30228 {6, mips.REG_R6, 5, "R6"}, 30229 {7, mips.REG_R7, 6, "R7"}, 30230 {8, mips.REG_R8, 7, "R8"}, 30231 {9, mips.REG_R9, 8, "R9"}, 30232 {10, mips.REG_R10, 9, "R10"}, 30233 {11, mips.REG_R11, 10, "R11"}, 30234 {12, mips.REG_R12, 11, "R12"}, 30235 {13, mips.REG_R13, 12, "R13"}, 30236 {14, mips.REG_R14, 13, "R14"}, 30237 {15, mips.REG_R15, 14, "R15"}, 30238 {16, mips.REG_R16, 15, "R16"}, 30239 {17, mips.REG_R17, 16, "R17"}, 30240 {18, mips.REG_R18, 17, "R18"}, 30241 {19, mips.REG_R19, 18, "R19"}, 30242 {20, mips.REG_R20, 19, "R20"}, 30243 {21, mips.REG_R21, 20, "R21"}, 30244 {22, mips.REG_R22, 21, "R22"}, 30245 {23, mips.REG_R24, 22, "R24"}, 30246 {24, mips.REG_R25, 23, "R25"}, 30247 {25, mips.REG_R28, 24, "R28"}, 30248 {26, mips.REGSP, -1, "SP"}, 30249 {27, mips.REGG, -1, "g"}, 30250 {28, mips.REG_R31, 25, "R31"}, 30251 {29, mips.REG_F0, -1, "F0"}, 30252 {30, mips.REG_F2, -1, "F2"}, 30253 {31, mips.REG_F4, -1, "F4"}, 30254 {32, mips.REG_F6, -1, "F6"}, 30255 {33, mips.REG_F8, -1, "F8"}, 30256 {34, mips.REG_F10, -1, "F10"}, 30257 {35, mips.REG_F12, -1, "F12"}, 30258 {36, mips.REG_F14, -1, "F14"}, 30259 {37, mips.REG_F16, -1, "F16"}, 30260 {38, mips.REG_F18, -1, "F18"}, 30261 {39, mips.REG_F20, -1, "F20"}, 30262 {40, mips.REG_F22, -1, "F22"}, 30263 {41, mips.REG_F24, -1, "F24"}, 30264 {42, mips.REG_F26, -1, "F26"}, 30265 {43, mips.REG_F28, -1, "F28"}, 30266 {44, mips.REG_F30, -1, "F30"}, 30267 {45, mips.REG_HI, -1, "HI"}, 30268 {46, mips.REG_LO, -1, "LO"}, 30269 {47, 0, -1, "SB"}, 30270 } 30271 var gpRegMaskMIPS = regMask(335544318) 30272 var fpRegMaskMIPS = regMask(35183835217920) 30273 var specialRegMaskMIPS = regMask(105553116266496) 30274 var framepointerRegMIPS = int8(-1) 30275 var linkRegMIPS = int8(28) 30276 var registersMIPS64 = [...]Register{ 30277 {0, mips.REG_R0, -1, "R0"}, 30278 {1, mips.REG_R1, 0, "R1"}, 30279 {2, mips.REG_R2, 1, "R2"}, 30280 {3, mips.REG_R3, 2, "R3"}, 30281 {4, mips.REG_R4, 3, "R4"}, 30282 {5, mips.REG_R5, 4, "R5"}, 30283 {6, mips.REG_R6, 5, "R6"}, 30284 {7, mips.REG_R7, 6, "R7"}, 30285 {8, mips.REG_R8, 7, "R8"}, 30286 {9, mips.REG_R9, 8, "R9"}, 30287 {10, mips.REG_R10, 9, "R10"}, 30288 {11, mips.REG_R11, 10, "R11"}, 30289 {12, mips.REG_R12, 11, "R12"}, 30290 {13, mips.REG_R13, 12, "R13"}, 30291 {14, mips.REG_R14, 13, "R14"}, 30292 {15, mips.REG_R15, 14, "R15"}, 30293 {16, mips.REG_R16, 15, "R16"}, 30294 {17, mips.REG_R17, 16, "R17"}, 30295 {18, mips.REG_R18, 17, "R18"}, 30296 {19, mips.REG_R19, 18, "R19"}, 30297 {20, mips.REG_R20, 19, "R20"}, 30298 {21, mips.REG_R21, 20, "R21"}, 30299 {22, mips.REG_R22, 21, "R22"}, 30300 {23, mips.REG_R24, 22, "R24"}, 30301 {24, mips.REG_R25, 23, "R25"}, 30302 {25, mips.REGSP, -1, "SP"}, 30303 {26, mips.REGG, -1, "g"}, 30304 {27, mips.REG_R31, 24, "R31"}, 30305 {28, mips.REG_F0, -1, "F0"}, 30306 {29, mips.REG_F1, -1, "F1"}, 30307 {30, mips.REG_F2, -1, "F2"}, 30308 {31, mips.REG_F3, -1, "F3"}, 30309 {32, mips.REG_F4, -1, "F4"}, 30310 {33, mips.REG_F5, -1, "F5"}, 30311 {34, mips.REG_F6, -1, "F6"}, 30312 {35, mips.REG_F7, -1, "F7"}, 30313 {36, mips.REG_F8, -1, "F8"}, 30314 {37, mips.REG_F9, -1, "F9"}, 30315 {38, mips.REG_F10, -1, "F10"}, 30316 {39, mips.REG_F11, -1, "F11"}, 30317 {40, mips.REG_F12, -1, "F12"}, 30318 {41, mips.REG_F13, -1, "F13"}, 30319 {42, mips.REG_F14, -1, "F14"}, 30320 {43, mips.REG_F15, -1, "F15"}, 30321 {44, mips.REG_F16, -1, "F16"}, 30322 {45, mips.REG_F17, -1, "F17"}, 30323 {46, mips.REG_F18, -1, "F18"}, 30324 {47, mips.REG_F19, -1, "F19"}, 30325 {48, mips.REG_F20, -1, "F20"}, 30326 {49, mips.REG_F21, -1, "F21"}, 30327 {50, mips.REG_F22, -1, "F22"}, 30328 {51, mips.REG_F23, -1, "F23"}, 30329 {52, mips.REG_F24, -1, "F24"}, 30330 {53, mips.REG_F25, -1, "F25"}, 30331 {54, mips.REG_F26, -1, "F26"}, 30332 {55, mips.REG_F27, -1, "F27"}, 30333 {56, mips.REG_F28, -1, "F28"}, 30334 {57, mips.REG_F29, -1, "F29"}, 30335 {58, mips.REG_F30, -1, "F30"}, 30336 {59, mips.REG_F31, -1, "F31"}, 30337 {60, mips.REG_HI, -1, "HI"}, 30338 {61, mips.REG_LO, -1, "LO"}, 30339 {62, 0, -1, "SB"}, 30340 } 30341 var gpRegMaskMIPS64 = regMask(167772158) 30342 var fpRegMaskMIPS64 = regMask(1152921504338411520) 30343 var specialRegMaskMIPS64 = regMask(3458764513820540928) 30344 var framepointerRegMIPS64 = int8(-1) 30345 var linkRegMIPS64 = int8(27) 30346 var registersPPC64 = [...]Register{ 30347 {0, ppc64.REG_R0, -1, "R0"}, 30348 {1, ppc64.REGSP, -1, "SP"}, 30349 {2, 0, -1, "SB"}, 30350 {3, ppc64.REG_R3, 0, "R3"}, 30351 {4, ppc64.REG_R4, 1, "R4"}, 30352 {5, ppc64.REG_R5, 2, "R5"}, 30353 {6, ppc64.REG_R6, 3, "R6"}, 30354 {7, ppc64.REG_R7, 4, "R7"}, 30355 {8, ppc64.REG_R8, 5, "R8"}, 30356 {9, ppc64.REG_R9, 6, "R9"}, 30357 {10, ppc64.REG_R10, 7, "R10"}, 30358 {11, ppc64.REG_R11, 8, "R11"}, 30359 {12, ppc64.REG_R12, 9, "R12"}, 30360 {13, ppc64.REG_R13, -1, "R13"}, 30361 {14, ppc64.REG_R14, 10, "R14"}, 30362 {15, ppc64.REG_R15, 11, "R15"}, 30363 {16, ppc64.REG_R16, 12, "R16"}, 30364 {17, ppc64.REG_R17, 13, "R17"}, 30365 {18, ppc64.REG_R18, 14, "R18"}, 30366 {19, ppc64.REG_R19, 15, "R19"}, 30367 {20, ppc64.REG_R20, 16, "R20"}, 30368 {21, ppc64.REG_R21, 17, "R21"}, 30369 {22, ppc64.REG_R22, 18, "R22"}, 30370 {23, ppc64.REG_R23, 19, "R23"}, 30371 {24, ppc64.REG_R24, 20, "R24"}, 30372 {25, ppc64.REG_R25, 21, "R25"}, 30373 {26, ppc64.REG_R26, 22, "R26"}, 30374 {27, ppc64.REG_R27, 23, "R27"}, 30375 {28, ppc64.REG_R28, 24, "R28"}, 30376 {29, ppc64.REG_R29, 25, "R29"}, 30377 {30, ppc64.REGG, -1, "g"}, 30378 {31, ppc64.REG_R31, -1, "R31"}, 30379 {32, ppc64.REG_F0, -1, "F0"}, 30380 {33, ppc64.REG_F1, -1, "F1"}, 30381 {34, ppc64.REG_F2, -1, "F2"}, 30382 {35, ppc64.REG_F3, -1, "F3"}, 30383 {36, ppc64.REG_F4, -1, "F4"}, 30384 {37, ppc64.REG_F5, -1, "F5"}, 30385 {38, ppc64.REG_F6, -1, "F6"}, 30386 {39, ppc64.REG_F7, -1, "F7"}, 30387 {40, ppc64.REG_F8, -1, "F8"}, 30388 {41, ppc64.REG_F9, -1, "F9"}, 30389 {42, ppc64.REG_F10, -1, "F10"}, 30390 {43, ppc64.REG_F11, -1, "F11"}, 30391 {44, ppc64.REG_F12, -1, "F12"}, 30392 {45, ppc64.REG_F13, -1, "F13"}, 30393 {46, ppc64.REG_F14, -1, "F14"}, 30394 {47, ppc64.REG_F15, -1, "F15"}, 30395 {48, ppc64.REG_F16, -1, "F16"}, 30396 {49, ppc64.REG_F17, -1, "F17"}, 30397 {50, ppc64.REG_F18, -1, "F18"}, 30398 {51, ppc64.REG_F19, -1, "F19"}, 30399 {52, ppc64.REG_F20, -1, "F20"}, 30400 {53, ppc64.REG_F21, -1, "F21"}, 30401 {54, ppc64.REG_F22, -1, "F22"}, 30402 {55, ppc64.REG_F23, -1, "F23"}, 30403 {56, ppc64.REG_F24, -1, "F24"}, 30404 {57, ppc64.REG_F25, -1, "F25"}, 30405 {58, ppc64.REG_F26, -1, "F26"}, 30406 {59, ppc64.REG_F27, -1, "F27"}, 30407 {60, ppc64.REG_F28, -1, "F28"}, 30408 {61, ppc64.REG_F29, -1, "F29"}, 30409 {62, ppc64.REG_F30, -1, "F30"}, 30410 {63, ppc64.REG_F31, -1, "F31"}, 30411 } 30412 var gpRegMaskPPC64 = regMask(1073733624) 30413 var fpRegMaskPPC64 = regMask(576460743713488896) 30414 var specialRegMaskPPC64 = regMask(0) 30415 var framepointerRegPPC64 = int8(1) 30416 var linkRegPPC64 = int8(-1) 30417 var registersS390X = [...]Register{ 30418 {0, s390x.REG_R0, 0, "R0"}, 30419 {1, s390x.REG_R1, 1, "R1"}, 30420 {2, s390x.REG_R2, 2, "R2"}, 30421 {3, s390x.REG_R3, 3, "R3"}, 30422 {4, s390x.REG_R4, 4, "R4"}, 30423 {5, s390x.REG_R5, 5, "R5"}, 30424 {6, s390x.REG_R6, 6, "R6"}, 30425 {7, s390x.REG_R7, 7, "R7"}, 30426 {8, s390x.REG_R8, 8, "R8"}, 30427 {9, s390x.REG_R9, 9, "R9"}, 30428 {10, s390x.REG_R10, -1, "R10"}, 30429 {11, s390x.REG_R11, 10, "R11"}, 30430 {12, s390x.REG_R12, 11, "R12"}, 30431 {13, s390x.REGG, -1, "g"}, 30432 {14, s390x.REG_R14, 12, "R14"}, 30433 {15, s390x.REGSP, -1, "SP"}, 30434 {16, s390x.REG_F0, -1, "F0"}, 30435 {17, s390x.REG_F1, -1, "F1"}, 30436 {18, s390x.REG_F2, -1, "F2"}, 30437 {19, s390x.REG_F3, -1, "F3"}, 30438 {20, s390x.REG_F4, -1, "F4"}, 30439 {21, s390x.REG_F5, -1, "F5"}, 30440 {22, s390x.REG_F6, -1, "F6"}, 30441 {23, s390x.REG_F7, -1, "F7"}, 30442 {24, s390x.REG_F8, -1, "F8"}, 30443 {25, s390x.REG_F9, -1, "F9"}, 30444 {26, s390x.REG_F10, -1, "F10"}, 30445 {27, s390x.REG_F11, -1, "F11"}, 30446 {28, s390x.REG_F12, -1, "F12"}, 30447 {29, s390x.REG_F13, -1, "F13"}, 30448 {30, s390x.REG_F14, -1, "F14"}, 30449 {31, s390x.REG_F15, -1, "F15"}, 30450 {32, 0, -1, "SB"}, 30451 } 30452 var gpRegMaskS390X = regMask(23551) 30453 var fpRegMaskS390X = regMask(4294901760) 30454 var specialRegMaskS390X = regMask(0) 30455 var framepointerRegS390X = int8(-1) 30456 var linkRegS390X = int8(14) 30457 var registersWasm = [...]Register{ 30458 {0, wasm.REG_R0, 0, "R0"}, 30459 {1, wasm.REG_R1, 1, "R1"}, 30460 {2, wasm.REG_R2, 2, "R2"}, 30461 {3, wasm.REG_R3, 3, "R3"}, 30462 {4, wasm.REG_R4, 4, "R4"}, 30463 {5, wasm.REG_R5, 5, "R5"}, 30464 {6, wasm.REG_R6, 6, "R6"}, 30465 {7, wasm.REG_R7, 7, "R7"}, 30466 {8, wasm.REG_R8, 8, "R8"}, 30467 {9, wasm.REG_R9, 9, "R9"}, 30468 {10, wasm.REG_R10, 10, "R10"}, 30469 {11, wasm.REG_R11, 11, "R11"}, 30470 {12, wasm.REG_R12, 12, "R12"}, 30471 {13, wasm.REG_R13, 13, "R13"}, 30472 {14, wasm.REG_R14, 14, "R14"}, 30473 {15, wasm.REG_R15, 15, "R15"}, 30474 {16, wasm.REG_F0, -1, "F0"}, 30475 {17, wasm.REG_F1, -1, "F1"}, 30476 {18, wasm.REG_F2, -1, "F2"}, 30477 {19, wasm.REG_F3, -1, "F3"}, 30478 {20, wasm.REG_F4, -1, "F4"}, 30479 {21, wasm.REG_F5, -1, "F5"}, 30480 {22, wasm.REG_F6, -1, "F6"}, 30481 {23, wasm.REG_F7, -1, "F7"}, 30482 {24, wasm.REG_F8, -1, "F8"}, 30483 {25, wasm.REG_F9, -1, "F9"}, 30484 {26, wasm.REG_F10, -1, "F10"}, 30485 {27, wasm.REG_F11, -1, "F11"}, 30486 {28, wasm.REG_F12, -1, "F12"}, 30487 {29, wasm.REG_F13, -1, "F13"}, 30488 {30, wasm.REG_F14, -1, "F14"}, 30489 {31, wasm.REG_F15, -1, "F15"}, 30490 {32, wasm.REGSP, -1, "SP"}, 30491 {33, wasm.REGG, -1, "g"}, 30492 {34, 0, -1, "SB"}, 30493 } 30494 var gpRegMaskWasm = regMask(65535) 30495 var fpRegMaskWasm = regMask(4294901760) 30496 var specialRegMaskWasm = regMask(0) 30497 var framepointerRegWasm = int8(-1) 30498 var linkRegWasm = int8(-1)