github.com/metacubex/gvisor@v0.0.0-20240320004321-933faba989ec/pkg/abi/nvgpu/ctrl.go (about) 1 // Copyright 2023 The gVisor Authors. 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 package nvgpu 16 17 // From src/nvidia/interface/deprecated/rmapi_deprecated.h: 18 const ( 19 RM_GSS_LEGACY_MASK = 0x00008000 20 ) 21 22 // From src/nvidia/inc/kernel/rmapi/param_copy.h: 23 const ( 24 // RMAPI_PARAM_COPY_MAX_PARAMS_SIZE is the size limit imposed while copying 25 // "embedded pointers" in rmapi parameter structs. 26 // See src/nvidia/src/kernel/rmapi/param_copy.c:rmapiParamsAcquire(). 27 RMAPI_PARAM_COPY_MAX_PARAMS_SIZE = 1 * 1024 * 1024 28 ) 29 30 // From src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h: 31 32 // +marshal 33 type NVXXXX_CTRL_XXX_INFO struct { 34 Index uint32 35 Data uint32 36 } 37 38 // From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h: 39 const ( 40 NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE = 0xd01 41 NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY = 0xd04 42 ) 43 44 // From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h: 45 const ( 46 NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS = 0x201 47 NV0000_CTRL_CMD_GPU_GET_ID_INFO = 0x202 48 NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 = 0x205 49 NV0000_CTRL_CMD_GPU_GET_PROBED_IDS = 0x214 50 NV0000_CTRL_CMD_GPU_ATTACH_IDS = 0x215 51 NV0000_CTRL_CMD_GPU_DETACH_IDS = 0x216 52 NV0000_CTRL_CMD_GPU_GET_PCI_INFO = 0x21b 53 NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE = 0x279 54 NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE = 0x27b 55 ) 56 57 // From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h: 58 const ( 59 NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO = 0xa04 60 ) 61 62 // From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h: 63 const ( 64 NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION = 0x101 65 NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS = 0x127 66 NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS = 0x136 67 NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX = 0x13a 68 ) 69 70 // +marshal 71 type NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS struct { 72 SizeOfStrings uint32 73 Pad [4]byte 74 PDriverVersionBuffer P64 75 PVersionBuffer P64 76 PTitleBuffer P64 77 ChangelistNumber uint32 78 OfficialChangelistNumber uint32 79 } 80 81 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h: 82 const ( 83 NV0080_CTRL_CMD_FB_GET_CAPS_V2 = 0x801307 84 ) 85 86 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h: 87 const ( 88 NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST = 0x80170d 89 ) 90 91 // +marshal 92 type NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS struct { 93 NumChannels uint32 94 Pad [4]byte 95 PChannelHandleList P64 96 PChannelList P64 97 } 98 99 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h: 100 const ( 101 NV0080_CTRL_CMD_GPU_GET_CLASSLIST = 0x800201 102 NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES = 0x800280 103 NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE = 0x800288 104 NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE = 0x800289 105 NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 = 0x800292 106 ) 107 108 // +marshal 109 type NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS struct { 110 NumClasses uint32 111 Pad [4]byte 112 ClassList P64 113 } 114 115 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h: 116 117 // +marshal 118 type NV0080_CTRL_GR_ROUTE_INFO struct { 119 Flags uint32 120 Pad [4]byte 121 Route uint64 122 } 123 124 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h: 125 const ( 126 NV0080_CTRL_CMD_HOST_GET_CAPS_V2 = 0x801402 127 ) 128 129 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h: 130 const ( 131 NV2080_CTRL_CMD_BUS_GET_PCI_INFO = 0x20801801 132 NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO = 0x20801803 133 NV2080_CTRL_CMD_BUS_GET_INFO_V2 = 0x20801823 134 NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS = 0x2080182a 135 NV2080_CTRL_CMD_BUS_GET_C2C_INFO = 0x2080182b 136 ) 137 138 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h: 139 const ( 140 NV2080_CTRL_CMD_CE_GET_ALL_CAPS = 0x20802a0a 141 ) 142 143 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h: 144 const ( 145 NV2080_CTRL_CMD_FB_GET_INFO_V2 = 0x20801303 146 ) 147 148 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h: 149 const ( 150 NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS = 0x2080110b 151 152 NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES = 64 153 ) 154 155 // +marshal 156 type NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS struct { 157 BDisable uint8 158 Pad1 [3]byte 159 NumChannels uint32 160 BOnlyDisableScheduling uint8 161 BRewindGpPut uint8 162 Pad2 [6]byte 163 PRunlistPreemptEvent P64 164 HClientList [NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]Handle 165 HChannelList [NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]Handle 166 } 167 168 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h: 169 const ( 170 NV2080_CTRL_CMD_GPU_GET_INFO_V2 = 0x20800102 171 NV2080_CTRL_CMD_GPU_GET_NAME_STRING = 0x20800110 172 NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING = 0x20800111 173 NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO = 0x20800119 174 NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS = 0x2080012f 175 NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES = 0x20800131 176 NV2080_CTRL_CMD_GPU_ACQUIRE_COMPUTE_MODE_RESERVATION = 0x20800145 // undocumented; paramSize == 0 177 NV2080_CTRL_CMD_GPU_RELEASE_COMPUTE_MODE_RESERVATION = 0x20800146 // undocumented; paramSize == 0 178 NV2080_CTRL_CMD_GPU_GET_GID_INFO = 0x2080014a 179 NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 = 0x20800170 180 NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS = 0x2080018b 181 NV2080_CTRL_CMD_GPU_GET_PIDS = 0x2080018d 182 NV2080_CTRL_CMD_GPU_GET_PID_INFO = 0x2080018e 183 NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG = 0x20800195 184 NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO = 0x208001a3 185 ) 186 187 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h: 188 const ( 189 NV2080_CTRL_CMD_GR_GET_INFO = 0x20801201 190 NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE = 0x20801210 191 NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE = 0x20801218 192 NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER = 0x2080121b 193 NV2080_CTRL_CMD_GR_GET_CAPS_V2 = 0x20801227 194 NV2080_CTRL_CMD_GR_GET_GPC_MASK = 0x2080122a 195 NV2080_CTRL_CMD_GR_GET_TPC_MASK = 0x2080122b 196 NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER = 0x20801230 197 ) 198 199 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h: 200 const ( 201 NV2080_CTRL_CMD_GSP_GET_FEATURES = 0x20803601 202 ) 203 204 // +marshal 205 type NV2080_CTRL_GR_GET_INFO_PARAMS struct { 206 GRInfoListSize uint32 // in elements 207 Pad [4]byte 208 GRInfoList P64 209 GRRouteInfo NV0080_CTRL_GR_ROUTE_INFO 210 } 211 212 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h: 213 const ( 214 NV2080_CTRL_CMD_MC_GET_ARCH_INFO = 0x20801701 215 NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS = 0x20801702 216 ) 217 218 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h: 219 const ( 220 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS = 0x20803001 221 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS = 0x20803002 222 ) 223 224 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h: 225 const ( 226 NV2080_CTRL_CMD_PERF_BOOST = 0x2080200a 227 ) 228 229 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h: 230 const ( 231 NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO = 0x20802209 232 NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS = 0x2080220c 233 NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG = 0x20802210 234 ) 235 236 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h: 237 const ( 238 NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO = 0x20800406 239 ) 240 241 // From src/common/sdk/nvidia/inc/ctrl/ctrl503c.h: 242 const ( 243 NV503C_CTRL_CMD_REGISTER_VA_SPACE = 0x503c0102 244 NV503C_CTRL_CMD_REGISTER_VIDMEM = 0x503c0104 245 NV503C_CTRL_CMD_UNREGISTER_VIDMEM = 0x503c0105 246 ) 247 248 // From src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h: 249 const ( 250 NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK = 0x83de0309 251 NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES = 0x83de030c 252 NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES = 0x83de0310 253 ) 254 255 // From src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h: 256 const ( 257 NVC36F_CTRL_GET_CLASS_ENGINEID = 0xc36f0101 258 NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN = 0xc36f0108 259 ) 260 261 // From src/common/sdk/nvidia/inc/ctrl/ctrl906f.h: 262 const ( 263 NV906F_CTRL_CMD_RESET_CHANNEL = 0x906f0102 264 ) 265 266 // From src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h: 267 const ( 268 NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK = 0x90e60102 269 ) 270 271 // From src/common/sdk/nvidia/inc/ctrl/ctrla06c.h: 272 const ( 273 NVA06C_CTRL_CMD_GPFIFO_SCHEDULE = 0xa06c0101 274 NVA06C_CTRL_CMD_SET_TIMESLICE = 0xa06c0103 275 NVA06C_CTRL_CMD_PREEMPT = 0xa06c0105 276 ) 277 278 // From src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h: 279 const ( 280 NVA06F_CTRL_CMD_GPFIFO_SCHEDULE = 0xa06f0103 281 ) 282 283 // From src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h: 284 const ( 285 NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES = 0xcb330101 286 )