github.com/metacubex/gvisor@v0.0.0-20240320004321-933faba989ec/pkg/abi/nvgpu/uvm.go (about)

     1  // Copyright 2023 The gVisor Authors.
     2  //
     3  // Licensed under the Apache License, Version 2.0 (the "License");
     4  // you may not use this file except in compliance with the License.
     5  // You may obtain a copy of the License at
     6  //
     7  //     http://www.apache.org/licenses/LICENSE-2.0
     8  //
     9  // Unless required by applicable law or agreed to in writing, software
    10  // distributed under the License is distributed on an "AS IS" BASIS,
    11  // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    12  // See the License for the specific language governing permissions and
    13  // limitations under the License.
    14  
    15  package nvgpu
    16  
    17  // HasRMCtrlFD is a type constraint for UVM parameter structs containing a
    18  // RMCtrlFD field. This is necessary because, as of this writing (Go 1.20),
    19  // there is no way to enable field access using a Go type constraint.
    20  type HasRMCtrlFD interface {
    21  	GetRMCtrlFD() int32
    22  	SetRMCtrlFD(int32)
    23  }
    24  
    25  // UVM ioctl commands.
    26  const (
    27  	// From kernel-open/nvidia-uvm/uvm_linux_ioctl.h:
    28  	UVM_INITIALIZE   = 0x30000001
    29  	UVM_DEINITIALIZE = 0x30000002
    30  
    31  	// From kernel-open/nvidia-uvm/uvm_ioctl.h:
    32  	UVM_CREATE_RANGE_GROUP             = 23
    33  	UVM_DESTROY_RANGE_GROUP            = 24
    34  	UVM_REGISTER_GPU_VASPACE           = 25
    35  	UVM_UNREGISTER_GPU_VASPACE         = 26
    36  	UVM_REGISTER_CHANNEL               = 27
    37  	UVM_UNREGISTER_CHANNEL             = 28
    38  	UVM_MAP_EXTERNAL_ALLOCATION        = 33
    39  	UVM_FREE                           = 34
    40  	UVM_REGISTER_GPU                   = 37
    41  	UVM_UNREGISTER_GPU                 = 38
    42  	UVM_PAGEABLE_MEM_ACCESS            = 39
    43  	UVM_DISABLE_READ_DUPLICATION       = 45
    44  	UVM_MAP_DYNAMIC_PARALLELISM_REGION = 65
    45  	UVM_ALLOC_SEMAPHORE_POOL           = 68
    46  	UVM_VALIDATE_VA_RANGE              = 72
    47  	UVM_CREATE_EXTERNAL_RANGE          = 73
    48  	UVM_MM_INITIALIZE                  = 75
    49  )
    50  
    51  // +marshal
    52  type UVM_INITIALIZE_PARAMS struct {
    53  	Flags    uint64
    54  	RMStatus uint32
    55  	Pad0     [4]byte
    56  }
    57  
    58  // UVM_INITIALIZE_PARAMS flags, from kernel-open/nvidia-uvm/uvm_types.h.
    59  const (
    60  	UVM_INIT_FLAGS_MULTI_PROCESS_SHARING_MODE = 0x2
    61  )
    62  
    63  // +marshal
    64  type UVM_CREATE_RANGE_GROUP_PARAMS struct {
    65  	RangeGroupID uint64
    66  	RMStatus     uint32
    67  	Pad0         [4]byte
    68  }
    69  
    70  // +marshal
    71  type UVM_DESTROY_RANGE_GROUP_PARAMS struct {
    72  	RangeGroupID uint64
    73  	RMStatus     uint32
    74  	Pad0         [4]byte
    75  }
    76  
    77  // +marshal
    78  type UVM_REGISTER_GPU_VASPACE_PARAMS struct {
    79  	GPUUUID  [16]uint8
    80  	RMCtrlFD int32
    81  	HClient  Handle
    82  	HVASpace Handle
    83  	RMStatus uint32
    84  }
    85  
    86  func (p *UVM_REGISTER_GPU_VASPACE_PARAMS) GetRMCtrlFD() int32 {
    87  	return p.RMCtrlFD
    88  }
    89  
    90  func (p *UVM_REGISTER_GPU_VASPACE_PARAMS) SetRMCtrlFD(fd int32) {
    91  	p.RMCtrlFD = fd
    92  }
    93  
    94  // +marshal
    95  type UVM_UNREGISTER_GPU_VASPACE_PARAMS struct {
    96  	GPUUUID  [16]uint8
    97  	RMStatus uint32
    98  }
    99  
   100  // +marshal
   101  type UVM_REGISTER_CHANNEL_PARAMS struct {
   102  	GPUUUID  [16]uint8
   103  	RMCtrlFD int32
   104  	HClient  Handle
   105  	HChannel Handle
   106  	Pad      [4]byte
   107  	Base     uint64
   108  	Length   uint64
   109  	RMStatus uint32
   110  	Pad0     [4]byte
   111  }
   112  
   113  func (p *UVM_REGISTER_CHANNEL_PARAMS) GetRMCtrlFD() int32 {
   114  	return p.RMCtrlFD
   115  }
   116  
   117  func (p *UVM_REGISTER_CHANNEL_PARAMS) SetRMCtrlFD(fd int32) {
   118  	p.RMCtrlFD = fd
   119  }
   120  
   121  // +marshal
   122  type UVM_UNREGISTER_CHANNEL_PARAMS struct {
   123  	GPUUUID  [16]uint8
   124  	HClient  Handle
   125  	HChannel Handle
   126  	RMStatus uint32
   127  }
   128  
   129  // +marshal
   130  type UVM_MAP_EXTERNAL_ALLOCATION_PARAMS struct {
   131  	Base               uint64
   132  	Length             uint64
   133  	Offset             uint64
   134  	PerGPUAttributes   [UVM_MAX_GPUS]UvmGpuMappingAttributes
   135  	GPUAttributesCount uint64
   136  	RMCtrlFD           int32
   137  	HClient            Handle
   138  	HMemory            Handle
   139  	RMStatus           uint32
   140  }
   141  
   142  func (p *UVM_MAP_EXTERNAL_ALLOCATION_PARAMS) GetRMCtrlFD() int32 {
   143  	return p.RMCtrlFD
   144  }
   145  
   146  func (p *UVM_MAP_EXTERNAL_ALLOCATION_PARAMS) SetRMCtrlFD(fd int32) {
   147  	p.RMCtrlFD = fd
   148  }
   149  
   150  // +marshal
   151  type UVM_FREE_PARAMS struct {
   152  	Base     uint64
   153  	Length   uint64
   154  	RMStatus uint32
   155  	Pad0     [4]byte
   156  }
   157  
   158  // +marshal
   159  type UVM_REGISTER_GPU_PARAMS struct {
   160  	GPUUUID     [16]uint8
   161  	NumaEnabled uint8
   162  	Pad         [3]byte
   163  	NumaNodeID  int32
   164  	RMCtrlFD    int32
   165  	HClient     Handle
   166  	HSMCPartRef Handle
   167  	RMStatus    uint32
   168  }
   169  
   170  func (p *UVM_REGISTER_GPU_PARAMS) GetRMCtrlFD() int32 {
   171  	return p.RMCtrlFD
   172  }
   173  
   174  func (p *UVM_REGISTER_GPU_PARAMS) SetRMCtrlFD(fd int32) {
   175  	p.RMCtrlFD = fd
   176  }
   177  
   178  // +marshal
   179  type UVM_UNREGISTER_GPU_PARAMS struct {
   180  	GPUUUID  [16]uint8
   181  	RMStatus uint32
   182  }
   183  
   184  // +marshal
   185  type UVM_PAGEABLE_MEM_ACCESS_PARAMS struct {
   186  	PageableMemAccess uint8
   187  	Pad               [3]byte
   188  	RMStatus          uint32
   189  }
   190  
   191  // +marshal
   192  type UVM_DISABLE_READ_DUPLICATION_PARAMS struct {
   193  	RequestedBase uint64
   194  	Length        uint64
   195  	RMStatus      uint32
   196  	Pad0          [4]byte
   197  }
   198  
   199  // +marshal
   200  type UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS struct {
   201  	Base     uint64
   202  	Length   uint64
   203  	GPUUUID  [16]uint8
   204  	RMStatus uint32
   205  	Pad0     [4]byte
   206  }
   207  
   208  // +marshal
   209  type UVM_ALLOC_SEMAPHORE_POOL_PARAMS struct {
   210  	Base               uint64
   211  	Length             uint64
   212  	PerGPUAttributes   [UVM_MAX_GPUS]UvmGpuMappingAttributes
   213  	GPUAttributesCount uint64
   214  	RMStatus           uint32
   215  	Pad0               [4]byte
   216  }
   217  
   218  // +marshal
   219  type UVM_VALIDATE_VA_RANGE_PARAMS struct {
   220  	Base     uint64
   221  	Length   uint64
   222  	RMStatus uint32
   223  	Pad0     [4]byte
   224  }
   225  
   226  // +marshal
   227  type UVM_CREATE_EXTERNAL_RANGE_PARAMS struct {
   228  	Base     uint64
   229  	Length   uint64
   230  	RMStatus uint32
   231  	Pad0     [4]byte
   232  }
   233  
   234  // +marshal
   235  type UVM_MM_INITIALIZE_PARAMS struct {
   236  	UvmFD  int32
   237  	Status uint32
   238  }
   239  
   240  // From kernel-open/nvidia-uvm/uvm_types.h:
   241  
   242  const UVM_MAX_GPUS = NV_MAX_DEVICES
   243  
   244  // +marshal
   245  type UvmGpuMappingAttributes struct {
   246  	GPUUUID            [16]byte
   247  	GPUMappingType     uint32
   248  	GPUCachingType     uint32
   249  	GPUFormatType      uint32
   250  	GPUElementBits     uint32
   251  	GPUCompressionType uint32
   252  }