github.com/metacubex/gvisor@v0.0.0-20240320004321-933faba989ec/pkg/ring0/lib_amd64.s (about) 1 // Copyright 2018 The gVisor Authors. 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #include "funcdata.h" 16 #include "textflag.h" 17 18 // fxrstor loads floating point state. 19 // 20 // The code corresponds to: 21 // 22 // fxrstor64 (%rbx) 23 // 24 TEXT ·fxrstor(SB),NOSPLIT|NOFRAME,$0-8 25 MOVQ addr+0(FP), BX 26 MOVL $0xffffffff, AX 27 MOVL $0xffffffff, DX 28 BYTE $0x48; BYTE $0x0f; BYTE $0xae; BYTE $0x0b; 29 RET 30 31 // xrstor loads floating point state. 32 // 33 // The code corresponds to: 34 // 35 // xrstor (%rdi) 36 // 37 TEXT ·xrstor(SB),NOSPLIT|NOFRAME,$0-8 38 MOVQ addr+0(FP), DI 39 MOVL $0xffffffff, AX 40 MOVL $0xffffffff, DX 41 BYTE $0x48; BYTE $0x0f; BYTE $0xae; BYTE $0x2f; 42 RET 43 44 // fxsave saves floating point state. 45 // 46 // The code corresponds to: 47 // 48 // fxsave64 (%rbx) 49 // 50 TEXT ·fxsave(SB),NOSPLIT|NOFRAME,$0-8 51 MOVQ addr+0(FP), BX 52 MOVL $0xffffffff, AX 53 MOVL $0xffffffff, DX 54 BYTE $0x48; BYTE $0x0f; BYTE $0xae; BYTE $0x03; 55 RET 56 57 // xsave saves floating point state. 58 // 59 // The code corresponds to: 60 // 61 // xsave (%rdi) 62 // 63 TEXT ·xsave(SB),NOSPLIT|NOFRAME,$0-8 64 MOVQ addr+0(FP), DI 65 MOVL $0xffffffff, AX 66 MOVL $0xffffffff, DX 67 BYTE $0x48; BYTE $0x0f; BYTE $0xae; BYTE $0x27; 68 RET 69 70 // xsaveopt saves floating point state. 71 // 72 // The code corresponds to: 73 // 74 // xsaveopt (%rdi) 75 // 76 TEXT ·xsaveopt(SB),NOSPLIT|NOFRAME,$0-8 77 MOVQ addr+0(FP), DI 78 MOVL $0xffffffff, AX 79 MOVL $0xffffffff, DX 80 BYTE $0x48; BYTE $0x0f; BYTE $0xae; BYTE $0x37; 81 RET 82 83 // writeFS writes to the FS base. 84 // 85 // This is written in assembly because it must be safe to call before the Go 86 // environment is set up. See comment on start(). 87 // 88 // Preconditions: must be running in the lower address space, as it accesses 89 // global data. 90 TEXT ·writeFS(SB),NOSPLIT,$8-8 91 MOVQ addr+0(FP), AX 92 93 CMPB ·hasFSGSBASE(SB), $1 94 JNE msr 95 96 PUSHQ AX 97 CALL ·wrfsbase(SB) 98 POPQ AX 99 RET 100 msr: 101 PUSHQ AX 102 CALL ·wrfsmsr(SB) 103 POPQ AX 104 RET 105 106 // wrfsbase writes to the FS base. 107 // 108 // The code corresponds to: 109 // 110 // wrfsbase %rax 111 // 112 TEXT ·wrfsbase(SB),NOSPLIT|NOFRAME,$0-8 113 MOVQ addr+0(FP), AX 114 BYTE $0xf3; BYTE $0x48; BYTE $0x0f; BYTE $0xae; BYTE $0xd0; 115 RET 116 117 // wrfsmsr writes to the FSBASE MSR. 118 // 119 // The code corresponds to: 120 // 121 // wrmsr (writes EDX:EAX to the MSR in ECX) 122 // 123 TEXT ·wrfsmsr(SB),NOSPLIT|NOFRAME,$0-8 124 MOVQ addr+0(FP), AX 125 MOVQ AX, DX 126 SHRQ $32, DX 127 MOVQ $0xc0000100, CX // MSR_FS_BASE 128 BYTE $0x0f; BYTE $0x30; 129 RET 130 131 // writeGS writes to the GS base. 132 // 133 // This is written in assembly because it must be callable from assembly (ABI0) 134 // without an intermediate transition to ABIInternal. 135 // 136 // Preconditions: must be running in the lower address space, as it accesses 137 // global data. 138 TEXT ·writeGS(SB),NOSPLIT,$8-8 139 MOVQ addr+0(FP), AX 140 141 CMPB ·hasFSGSBASE(SB), $1 142 JNE msr 143 144 PUSHQ AX 145 CALL ·wrgsbase(SB) 146 POPQ AX 147 RET 148 msr: 149 PUSHQ AX 150 CALL ·wrgsmsr(SB) 151 POPQ AX 152 RET 153 154 // wrgsbase writes to the GS base. 155 // 156 // The code corresponds to: 157 // 158 // wrgsbase %rax 159 // 160 TEXT ·wrgsbase(SB),NOSPLIT|NOFRAME,$0-8 161 MOVQ addr+0(FP), AX 162 BYTE $0xf3; BYTE $0x48; BYTE $0x0f; BYTE $0xae; BYTE $0xd8; 163 RET 164 165 // wrgsmsr writes to the GSBASE MSR. 166 // 167 // See wrfsmsr. 168 TEXT ·wrgsmsr(SB),NOSPLIT|NOFRAME,$0-8 169 MOVQ addr+0(FP), AX 170 MOVQ AX, DX 171 SHRQ $32, DX 172 MOVQ $0xc0000101, CX // MSR_GS_BASE 173 BYTE $0x0f; BYTE $0x30; // WRMSR 174 RET 175 176 // readCR2 reads the current CR2 value. 177 // 178 // The code corresponds to: 179 // 180 // mov %cr2, %rax 181 // 182 TEXT ·readCR2(SB),NOSPLIT|NOFRAME,$0-8 183 BYTE $0x0f; BYTE $0x20; BYTE $0xd0; 184 MOVQ AX, ret+0(FP) 185 RET 186 187 // fninit initializes the floating point unit. 188 // 189 // The code corresponds to: 190 // 191 // fninit 192 TEXT ·fninit(SB),NOSPLIT|NOFRAME,$0 193 BYTE $0xdb; BYTE $0xe3; 194 RET 195 196 // xsetbv writes to an extended control register. 197 // 198 // The code corresponds to: 199 // 200 // xsetbv 201 // 202 TEXT ·xsetbv(SB),NOSPLIT|NOFRAME,$0-16 203 MOVQ reg+0(FP), CX 204 MOVL value+8(FP), AX 205 MOVL value+12(FP), DX 206 BYTE $0x0f; BYTE $0x01; BYTE $0xd1; 207 RET 208 209 // xgetbv reads an extended control register. 210 // 211 // The code corresponds to: 212 // 213 // xgetbv 214 // 215 TEXT ·xgetbv(SB),NOSPLIT|NOFRAME,$0-16 216 MOVQ reg+0(FP), CX 217 BYTE $0x0f; BYTE $0x01; BYTE $0xd0; 218 MOVL AX, ret+8(FP) 219 MOVL DX, ret+12(FP) 220 RET 221 222 // wrmsr writes to a control register. 223 // 224 // The code corresponds to: 225 // 226 // wrmsr 227 // 228 TEXT ·wrmsr(SB),NOSPLIT|NOFRAME,$0-16 229 MOVQ reg+0(FP), CX 230 MOVL value+8(FP), AX 231 MOVL value+12(FP), DX 232 BYTE $0x0f; BYTE $0x30; 233 RET 234 235 // rdmsr reads a control register. 236 // 237 // The code corresponds to: 238 // 239 // rdmsr 240 // 241 TEXT ·rdmsr(SB),NOSPLIT|NOFRAME,$0-16 242 MOVQ reg+0(FP), CX 243 BYTE $0x0f; BYTE $0x32; 244 MOVL AX, ret+8(FP) 245 MOVL DX, ret+12(FP) 246 RET 247 248 // stmxcsr reads the MXCSR control and status register. 249 TEXT ·stmxcsr(SB),NOSPLIT|NOFRAME,$0-8 250 MOVQ addr+0(FP), SI 251 STMXCSR (SI) 252 RET 253 254 // ldmxcsr writes to the MXCSR control and status register. 255 TEXT ·ldmxcsr(SB),NOSPLIT|NOFRAME,$0-8 256 MOVQ addr+0(FP), SI 257 LDMXCSR (SI) 258 RET