github.com/mh-cbon/go@v0.0.0-20160603070303-9e112a3fe4c0/src/cmd/compile/internal/ssa/opGen.go (about) 1 // autogenerated: do not edit! 2 // generated from gen/*Ops.go 3 4 package ssa 5 6 import ( 7 "cmd/internal/obj" 8 "cmd/internal/obj/arm" 9 "cmd/internal/obj/x86" 10 ) 11 12 const ( 13 BlockInvalid BlockKind = iota 14 15 BlockAMD64EQ 16 BlockAMD64NE 17 BlockAMD64LT 18 BlockAMD64LE 19 BlockAMD64GT 20 BlockAMD64GE 21 BlockAMD64ULT 22 BlockAMD64ULE 23 BlockAMD64UGT 24 BlockAMD64UGE 25 BlockAMD64EQF 26 BlockAMD64NEF 27 BlockAMD64ORD 28 BlockAMD64NAN 29 30 BlockARMEQ 31 BlockARMNE 32 BlockARMLT 33 BlockARMLE 34 BlockARMGT 35 BlockARMGE 36 BlockARMULT 37 BlockARMULE 38 BlockARMUGT 39 BlockARMUGE 40 41 BlockPlain 42 BlockIf 43 BlockCall 44 BlockDefer 45 BlockCheck 46 BlockRet 47 BlockRetJmp 48 BlockExit 49 BlockFirst 50 ) 51 52 var blockString = [...]string{ 53 BlockInvalid: "BlockInvalid", 54 55 BlockAMD64EQ: "EQ", 56 BlockAMD64NE: "NE", 57 BlockAMD64LT: "LT", 58 BlockAMD64LE: "LE", 59 BlockAMD64GT: "GT", 60 BlockAMD64GE: "GE", 61 BlockAMD64ULT: "ULT", 62 BlockAMD64ULE: "ULE", 63 BlockAMD64UGT: "UGT", 64 BlockAMD64UGE: "UGE", 65 BlockAMD64EQF: "EQF", 66 BlockAMD64NEF: "NEF", 67 BlockAMD64ORD: "ORD", 68 BlockAMD64NAN: "NAN", 69 70 BlockARMEQ: "EQ", 71 BlockARMNE: "NE", 72 BlockARMLT: "LT", 73 BlockARMLE: "LE", 74 BlockARMGT: "GT", 75 BlockARMGE: "GE", 76 BlockARMULT: "ULT", 77 BlockARMULE: "ULE", 78 BlockARMUGT: "UGT", 79 BlockARMUGE: "UGE", 80 81 BlockPlain: "Plain", 82 BlockIf: "If", 83 BlockCall: "Call", 84 BlockDefer: "Defer", 85 BlockCheck: "Check", 86 BlockRet: "Ret", 87 BlockRetJmp: "RetJmp", 88 BlockExit: "Exit", 89 BlockFirst: "First", 90 } 91 92 func (k BlockKind) String() string { return blockString[k] } 93 94 const ( 95 OpInvalid Op = iota 96 97 OpAMD64ADDSS 98 OpAMD64ADDSD 99 OpAMD64SUBSS 100 OpAMD64SUBSD 101 OpAMD64MULSS 102 OpAMD64MULSD 103 OpAMD64DIVSS 104 OpAMD64DIVSD 105 OpAMD64MOVSSload 106 OpAMD64MOVSDload 107 OpAMD64MOVSSconst 108 OpAMD64MOVSDconst 109 OpAMD64MOVSSloadidx1 110 OpAMD64MOVSSloadidx4 111 OpAMD64MOVSDloadidx1 112 OpAMD64MOVSDloadidx8 113 OpAMD64MOVSSstore 114 OpAMD64MOVSDstore 115 OpAMD64MOVSSstoreidx1 116 OpAMD64MOVSSstoreidx4 117 OpAMD64MOVSDstoreidx1 118 OpAMD64MOVSDstoreidx8 119 OpAMD64ADDQ 120 OpAMD64ADDL 121 OpAMD64ADDQconst 122 OpAMD64ADDLconst 123 OpAMD64SUBQ 124 OpAMD64SUBL 125 OpAMD64SUBQconst 126 OpAMD64SUBLconst 127 OpAMD64MULQ 128 OpAMD64MULL 129 OpAMD64MULQconst 130 OpAMD64MULLconst 131 OpAMD64HMULQ 132 OpAMD64HMULL 133 OpAMD64HMULW 134 OpAMD64HMULB 135 OpAMD64HMULQU 136 OpAMD64HMULLU 137 OpAMD64HMULWU 138 OpAMD64HMULBU 139 OpAMD64AVGQU 140 OpAMD64DIVQ 141 OpAMD64DIVL 142 OpAMD64DIVW 143 OpAMD64DIVQU 144 OpAMD64DIVLU 145 OpAMD64DIVWU 146 OpAMD64MODQ 147 OpAMD64MODL 148 OpAMD64MODW 149 OpAMD64MODQU 150 OpAMD64MODLU 151 OpAMD64MODWU 152 OpAMD64ANDQ 153 OpAMD64ANDL 154 OpAMD64ANDQconst 155 OpAMD64ANDLconst 156 OpAMD64ORQ 157 OpAMD64ORL 158 OpAMD64ORQconst 159 OpAMD64ORLconst 160 OpAMD64XORQ 161 OpAMD64XORL 162 OpAMD64XORQconst 163 OpAMD64XORLconst 164 OpAMD64CMPQ 165 OpAMD64CMPL 166 OpAMD64CMPW 167 OpAMD64CMPB 168 OpAMD64CMPQconst 169 OpAMD64CMPLconst 170 OpAMD64CMPWconst 171 OpAMD64CMPBconst 172 OpAMD64UCOMISS 173 OpAMD64UCOMISD 174 OpAMD64TESTQ 175 OpAMD64TESTL 176 OpAMD64TESTW 177 OpAMD64TESTB 178 OpAMD64TESTQconst 179 OpAMD64TESTLconst 180 OpAMD64TESTWconst 181 OpAMD64TESTBconst 182 OpAMD64SHLQ 183 OpAMD64SHLL 184 OpAMD64SHLQconst 185 OpAMD64SHLLconst 186 OpAMD64SHRQ 187 OpAMD64SHRL 188 OpAMD64SHRW 189 OpAMD64SHRB 190 OpAMD64SHRQconst 191 OpAMD64SHRLconst 192 OpAMD64SHRWconst 193 OpAMD64SHRBconst 194 OpAMD64SARQ 195 OpAMD64SARL 196 OpAMD64SARW 197 OpAMD64SARB 198 OpAMD64SARQconst 199 OpAMD64SARLconst 200 OpAMD64SARWconst 201 OpAMD64SARBconst 202 OpAMD64ROLQconst 203 OpAMD64ROLLconst 204 OpAMD64ROLWconst 205 OpAMD64ROLBconst 206 OpAMD64NEGQ 207 OpAMD64NEGL 208 OpAMD64NOTQ 209 OpAMD64NOTL 210 OpAMD64BSFQ 211 OpAMD64BSFL 212 OpAMD64BSFW 213 OpAMD64BSRQ 214 OpAMD64BSRL 215 OpAMD64BSRW 216 OpAMD64CMOVQEQconst 217 OpAMD64CMOVLEQconst 218 OpAMD64CMOVWEQconst 219 OpAMD64CMOVQNEconst 220 OpAMD64CMOVLNEconst 221 OpAMD64CMOVWNEconst 222 OpAMD64BSWAPQ 223 OpAMD64BSWAPL 224 OpAMD64SQRTSD 225 OpAMD64SBBQcarrymask 226 OpAMD64SBBLcarrymask 227 OpAMD64SETEQ 228 OpAMD64SETNE 229 OpAMD64SETL 230 OpAMD64SETLE 231 OpAMD64SETG 232 OpAMD64SETGE 233 OpAMD64SETB 234 OpAMD64SETBE 235 OpAMD64SETA 236 OpAMD64SETAE 237 OpAMD64SETEQF 238 OpAMD64SETNEF 239 OpAMD64SETORD 240 OpAMD64SETNAN 241 OpAMD64SETGF 242 OpAMD64SETGEF 243 OpAMD64MOVBQSX 244 OpAMD64MOVBQZX 245 OpAMD64MOVWQSX 246 OpAMD64MOVWQZX 247 OpAMD64MOVLQSX 248 OpAMD64MOVLQZX 249 OpAMD64MOVLconst 250 OpAMD64MOVQconst 251 OpAMD64CVTTSD2SL 252 OpAMD64CVTTSD2SQ 253 OpAMD64CVTTSS2SL 254 OpAMD64CVTTSS2SQ 255 OpAMD64CVTSL2SS 256 OpAMD64CVTSL2SD 257 OpAMD64CVTSQ2SS 258 OpAMD64CVTSQ2SD 259 OpAMD64CVTSD2SS 260 OpAMD64CVTSS2SD 261 OpAMD64PXOR 262 OpAMD64LEAQ 263 OpAMD64LEAQ1 264 OpAMD64LEAQ2 265 OpAMD64LEAQ4 266 OpAMD64LEAQ8 267 OpAMD64MOVBload 268 OpAMD64MOVBQSXload 269 OpAMD64MOVWload 270 OpAMD64MOVWQSXload 271 OpAMD64MOVLload 272 OpAMD64MOVLQSXload 273 OpAMD64MOVQload 274 OpAMD64MOVBstore 275 OpAMD64MOVWstore 276 OpAMD64MOVLstore 277 OpAMD64MOVQstore 278 OpAMD64MOVOload 279 OpAMD64MOVOstore 280 OpAMD64MOVBloadidx1 281 OpAMD64MOVWloadidx1 282 OpAMD64MOVWloadidx2 283 OpAMD64MOVLloadidx1 284 OpAMD64MOVLloadidx4 285 OpAMD64MOVQloadidx1 286 OpAMD64MOVQloadidx8 287 OpAMD64MOVBstoreidx1 288 OpAMD64MOVWstoreidx1 289 OpAMD64MOVWstoreidx2 290 OpAMD64MOVLstoreidx1 291 OpAMD64MOVLstoreidx4 292 OpAMD64MOVQstoreidx1 293 OpAMD64MOVQstoreidx8 294 OpAMD64MOVBstoreconst 295 OpAMD64MOVWstoreconst 296 OpAMD64MOVLstoreconst 297 OpAMD64MOVQstoreconst 298 OpAMD64MOVBstoreconstidx1 299 OpAMD64MOVWstoreconstidx1 300 OpAMD64MOVWstoreconstidx2 301 OpAMD64MOVLstoreconstidx1 302 OpAMD64MOVLstoreconstidx4 303 OpAMD64MOVQstoreconstidx1 304 OpAMD64MOVQstoreconstidx8 305 OpAMD64DUFFZERO 306 OpAMD64MOVOconst 307 OpAMD64REPSTOSQ 308 OpAMD64CALLstatic 309 OpAMD64CALLclosure 310 OpAMD64CALLdefer 311 OpAMD64CALLgo 312 OpAMD64CALLinter 313 OpAMD64DUFFCOPY 314 OpAMD64REPMOVSQ 315 OpAMD64InvertFlags 316 OpAMD64LoweredGetG 317 OpAMD64LoweredGetClosurePtr 318 OpAMD64LoweredNilCheck 319 OpAMD64MOVQconvert 320 OpAMD64FlagEQ 321 OpAMD64FlagLT_ULT 322 OpAMD64FlagLT_UGT 323 OpAMD64FlagGT_UGT 324 OpAMD64FlagGT_ULT 325 326 OpARMADD 327 OpARMADDconst 328 OpARMMOVWconst 329 OpARMCMP 330 OpARMMOVWload 331 OpARMMOVWstore 332 OpARMCALLstatic 333 OpARMLessThan 334 335 OpAdd8 336 OpAdd16 337 OpAdd32 338 OpAdd64 339 OpAddPtr 340 OpAdd32F 341 OpAdd64F 342 OpSub8 343 OpSub16 344 OpSub32 345 OpSub64 346 OpSubPtr 347 OpSub32F 348 OpSub64F 349 OpMul8 350 OpMul16 351 OpMul32 352 OpMul64 353 OpMul32F 354 OpMul64F 355 OpDiv32F 356 OpDiv64F 357 OpHmul8 358 OpHmul8u 359 OpHmul16 360 OpHmul16u 361 OpHmul32 362 OpHmul32u 363 OpHmul64 364 OpHmul64u 365 OpAvg64u 366 OpDiv8 367 OpDiv8u 368 OpDiv16 369 OpDiv16u 370 OpDiv32 371 OpDiv32u 372 OpDiv64 373 OpDiv64u 374 OpMod8 375 OpMod8u 376 OpMod16 377 OpMod16u 378 OpMod32 379 OpMod32u 380 OpMod64 381 OpMod64u 382 OpAnd8 383 OpAnd16 384 OpAnd32 385 OpAnd64 386 OpOr8 387 OpOr16 388 OpOr32 389 OpOr64 390 OpXor8 391 OpXor16 392 OpXor32 393 OpXor64 394 OpLsh8x8 395 OpLsh8x16 396 OpLsh8x32 397 OpLsh8x64 398 OpLsh16x8 399 OpLsh16x16 400 OpLsh16x32 401 OpLsh16x64 402 OpLsh32x8 403 OpLsh32x16 404 OpLsh32x32 405 OpLsh32x64 406 OpLsh64x8 407 OpLsh64x16 408 OpLsh64x32 409 OpLsh64x64 410 OpRsh8x8 411 OpRsh8x16 412 OpRsh8x32 413 OpRsh8x64 414 OpRsh16x8 415 OpRsh16x16 416 OpRsh16x32 417 OpRsh16x64 418 OpRsh32x8 419 OpRsh32x16 420 OpRsh32x32 421 OpRsh32x64 422 OpRsh64x8 423 OpRsh64x16 424 OpRsh64x32 425 OpRsh64x64 426 OpRsh8Ux8 427 OpRsh8Ux16 428 OpRsh8Ux32 429 OpRsh8Ux64 430 OpRsh16Ux8 431 OpRsh16Ux16 432 OpRsh16Ux32 433 OpRsh16Ux64 434 OpRsh32Ux8 435 OpRsh32Ux16 436 OpRsh32Ux32 437 OpRsh32Ux64 438 OpRsh64Ux8 439 OpRsh64Ux16 440 OpRsh64Ux32 441 OpRsh64Ux64 442 OpLrot8 443 OpLrot16 444 OpLrot32 445 OpLrot64 446 OpEq8 447 OpEq16 448 OpEq32 449 OpEq64 450 OpEqPtr 451 OpEqInter 452 OpEqSlice 453 OpEq32F 454 OpEq64F 455 OpNeq8 456 OpNeq16 457 OpNeq32 458 OpNeq64 459 OpNeqPtr 460 OpNeqInter 461 OpNeqSlice 462 OpNeq32F 463 OpNeq64F 464 OpLess8 465 OpLess8U 466 OpLess16 467 OpLess16U 468 OpLess32 469 OpLess32U 470 OpLess64 471 OpLess64U 472 OpLess32F 473 OpLess64F 474 OpLeq8 475 OpLeq8U 476 OpLeq16 477 OpLeq16U 478 OpLeq32 479 OpLeq32U 480 OpLeq64 481 OpLeq64U 482 OpLeq32F 483 OpLeq64F 484 OpGreater8 485 OpGreater8U 486 OpGreater16 487 OpGreater16U 488 OpGreater32 489 OpGreater32U 490 OpGreater64 491 OpGreater64U 492 OpGreater32F 493 OpGreater64F 494 OpGeq8 495 OpGeq8U 496 OpGeq16 497 OpGeq16U 498 OpGeq32 499 OpGeq32U 500 OpGeq64 501 OpGeq64U 502 OpGeq32F 503 OpGeq64F 504 OpAndB 505 OpOrB 506 OpEqB 507 OpNeqB 508 OpNot 509 OpNeg8 510 OpNeg16 511 OpNeg32 512 OpNeg64 513 OpNeg32F 514 OpNeg64F 515 OpCom8 516 OpCom16 517 OpCom32 518 OpCom64 519 OpCtz16 520 OpCtz32 521 OpCtz64 522 OpClz16 523 OpClz32 524 OpClz64 525 OpBswap32 526 OpBswap64 527 OpSqrt 528 OpPhi 529 OpCopy 530 OpConvert 531 OpConstBool 532 OpConstString 533 OpConstNil 534 OpConst8 535 OpConst16 536 OpConst32 537 OpConst64 538 OpConst32F 539 OpConst64F 540 OpConstInterface 541 OpConstSlice 542 OpInitMem 543 OpArg 544 OpAddr 545 OpSP 546 OpSB 547 OpFunc 548 OpLoad 549 OpStore 550 OpMove 551 OpZero 552 OpClosureCall 553 OpStaticCall 554 OpDeferCall 555 OpGoCall 556 OpInterCall 557 OpSignExt8to16 558 OpSignExt8to32 559 OpSignExt8to64 560 OpSignExt16to32 561 OpSignExt16to64 562 OpSignExt32to64 563 OpZeroExt8to16 564 OpZeroExt8to32 565 OpZeroExt8to64 566 OpZeroExt16to32 567 OpZeroExt16to64 568 OpZeroExt32to64 569 OpTrunc16to8 570 OpTrunc32to8 571 OpTrunc32to16 572 OpTrunc64to8 573 OpTrunc64to16 574 OpTrunc64to32 575 OpCvt32to32F 576 OpCvt32to64F 577 OpCvt64to32F 578 OpCvt64to64F 579 OpCvt32Fto32 580 OpCvt32Fto64 581 OpCvt64Fto32 582 OpCvt64Fto64 583 OpCvt32Fto64F 584 OpCvt64Fto32F 585 OpIsNonNil 586 OpIsInBounds 587 OpIsSliceInBounds 588 OpNilCheck 589 OpGetG 590 OpGetClosurePtr 591 OpArrayIndex 592 OpPtrIndex 593 OpOffPtr 594 OpSliceMake 595 OpSlicePtr 596 OpSliceLen 597 OpSliceCap 598 OpComplexMake 599 OpComplexReal 600 OpComplexImag 601 OpStringMake 602 OpStringPtr 603 OpStringLen 604 OpIMake 605 OpITab 606 OpIData 607 OpStructMake0 608 OpStructMake1 609 OpStructMake2 610 OpStructMake3 611 OpStructMake4 612 OpStructSelect 613 OpStoreReg 614 OpLoadReg 615 OpFwdRef 616 OpUnknown 617 OpVarDef 618 OpVarKill 619 OpVarLive 620 OpKeepAlive 621 ) 622 623 var opcodeTable = [...]opInfo{ 624 {name: "OpInvalid"}, 625 626 { 627 name: "ADDSS", 628 argLen: 2, 629 commutative: true, 630 resultInArg0: true, 631 asm: x86.AADDSS, 632 reg: regInfo{ 633 inputs: []inputInfo{ 634 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 635 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 636 }, 637 outputs: []regMask{ 638 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 639 }, 640 }, 641 }, 642 { 643 name: "ADDSD", 644 argLen: 2, 645 commutative: true, 646 resultInArg0: true, 647 asm: x86.AADDSD, 648 reg: regInfo{ 649 inputs: []inputInfo{ 650 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 651 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 652 }, 653 outputs: []regMask{ 654 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 655 }, 656 }, 657 }, 658 { 659 name: "SUBSS", 660 argLen: 2, 661 resultInArg0: true, 662 asm: x86.ASUBSS, 663 reg: regInfo{ 664 inputs: []inputInfo{ 665 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 666 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 667 }, 668 clobbers: 2147483648, // X15 669 outputs: []regMask{ 670 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 671 }, 672 }, 673 }, 674 { 675 name: "SUBSD", 676 argLen: 2, 677 resultInArg0: true, 678 asm: x86.ASUBSD, 679 reg: regInfo{ 680 inputs: []inputInfo{ 681 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 682 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 683 }, 684 clobbers: 2147483648, // X15 685 outputs: []regMask{ 686 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 687 }, 688 }, 689 }, 690 { 691 name: "MULSS", 692 argLen: 2, 693 commutative: true, 694 resultInArg0: true, 695 asm: x86.AMULSS, 696 reg: regInfo{ 697 inputs: []inputInfo{ 698 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 699 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 700 }, 701 outputs: []regMask{ 702 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 703 }, 704 }, 705 }, 706 { 707 name: "MULSD", 708 argLen: 2, 709 commutative: true, 710 resultInArg0: true, 711 asm: x86.AMULSD, 712 reg: regInfo{ 713 inputs: []inputInfo{ 714 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 715 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 716 }, 717 outputs: []regMask{ 718 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 719 }, 720 }, 721 }, 722 { 723 name: "DIVSS", 724 argLen: 2, 725 resultInArg0: true, 726 asm: x86.ADIVSS, 727 reg: regInfo{ 728 inputs: []inputInfo{ 729 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 730 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 731 }, 732 clobbers: 2147483648, // X15 733 outputs: []regMask{ 734 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 735 }, 736 }, 737 }, 738 { 739 name: "DIVSD", 740 argLen: 2, 741 resultInArg0: true, 742 asm: x86.ADIVSD, 743 reg: regInfo{ 744 inputs: []inputInfo{ 745 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 746 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 747 }, 748 clobbers: 2147483648, // X15 749 outputs: []regMask{ 750 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 751 }, 752 }, 753 }, 754 { 755 name: "MOVSSload", 756 auxType: auxSymOff, 757 argLen: 2, 758 asm: x86.AMOVSS, 759 reg: regInfo{ 760 inputs: []inputInfo{ 761 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 762 }, 763 outputs: []regMask{ 764 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 765 }, 766 }, 767 }, 768 { 769 name: "MOVSDload", 770 auxType: auxSymOff, 771 argLen: 2, 772 asm: x86.AMOVSD, 773 reg: regInfo{ 774 inputs: []inputInfo{ 775 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 776 }, 777 outputs: []regMask{ 778 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 779 }, 780 }, 781 }, 782 { 783 name: "MOVSSconst", 784 auxType: auxFloat32, 785 argLen: 0, 786 rematerializeable: true, 787 asm: x86.AMOVSS, 788 reg: regInfo{ 789 outputs: []regMask{ 790 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 791 }, 792 }, 793 }, 794 { 795 name: "MOVSDconst", 796 auxType: auxFloat64, 797 argLen: 0, 798 rematerializeable: true, 799 asm: x86.AMOVSD, 800 reg: regInfo{ 801 outputs: []regMask{ 802 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 803 }, 804 }, 805 }, 806 { 807 name: "MOVSSloadidx1", 808 auxType: auxSymOff, 809 argLen: 3, 810 asm: x86.AMOVSS, 811 reg: regInfo{ 812 inputs: []inputInfo{ 813 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 814 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 815 }, 816 outputs: []regMask{ 817 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 818 }, 819 }, 820 }, 821 { 822 name: "MOVSSloadidx4", 823 auxType: auxSymOff, 824 argLen: 3, 825 asm: x86.AMOVSS, 826 reg: regInfo{ 827 inputs: []inputInfo{ 828 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 829 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 830 }, 831 outputs: []regMask{ 832 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 833 }, 834 }, 835 }, 836 { 837 name: "MOVSDloadidx1", 838 auxType: auxSymOff, 839 argLen: 3, 840 asm: x86.AMOVSD, 841 reg: regInfo{ 842 inputs: []inputInfo{ 843 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 844 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 845 }, 846 outputs: []regMask{ 847 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 848 }, 849 }, 850 }, 851 { 852 name: "MOVSDloadidx8", 853 auxType: auxSymOff, 854 argLen: 3, 855 asm: x86.AMOVSD, 856 reg: regInfo{ 857 inputs: []inputInfo{ 858 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 859 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 860 }, 861 outputs: []regMask{ 862 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 863 }, 864 }, 865 }, 866 { 867 name: "MOVSSstore", 868 auxType: auxSymOff, 869 argLen: 3, 870 asm: x86.AMOVSS, 871 reg: regInfo{ 872 inputs: []inputInfo{ 873 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 874 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 875 }, 876 }, 877 }, 878 { 879 name: "MOVSDstore", 880 auxType: auxSymOff, 881 argLen: 3, 882 asm: x86.AMOVSD, 883 reg: regInfo{ 884 inputs: []inputInfo{ 885 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 886 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 887 }, 888 }, 889 }, 890 { 891 name: "MOVSSstoreidx1", 892 auxType: auxSymOff, 893 argLen: 4, 894 asm: x86.AMOVSS, 895 reg: regInfo{ 896 inputs: []inputInfo{ 897 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 898 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 899 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 900 }, 901 }, 902 }, 903 { 904 name: "MOVSSstoreidx4", 905 auxType: auxSymOff, 906 argLen: 4, 907 asm: x86.AMOVSS, 908 reg: regInfo{ 909 inputs: []inputInfo{ 910 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 911 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 912 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 913 }, 914 }, 915 }, 916 { 917 name: "MOVSDstoreidx1", 918 auxType: auxSymOff, 919 argLen: 4, 920 asm: x86.AMOVSD, 921 reg: regInfo{ 922 inputs: []inputInfo{ 923 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 924 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 925 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 926 }, 927 }, 928 }, 929 { 930 name: "MOVSDstoreidx8", 931 auxType: auxSymOff, 932 argLen: 4, 933 asm: x86.AMOVSD, 934 reg: regInfo{ 935 inputs: []inputInfo{ 936 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 937 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 938 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 939 }, 940 }, 941 }, 942 { 943 name: "ADDQ", 944 argLen: 2, 945 commutative: true, 946 asm: x86.AADDQ, 947 reg: regInfo{ 948 inputs: []inputInfo{ 949 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 950 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 951 }, 952 clobbers: 8589934592, // FLAGS 953 outputs: []regMask{ 954 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 955 }, 956 }, 957 }, 958 { 959 name: "ADDL", 960 argLen: 2, 961 commutative: true, 962 asm: x86.AADDL, 963 reg: regInfo{ 964 inputs: []inputInfo{ 965 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 966 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 967 }, 968 clobbers: 8589934592, // FLAGS 969 outputs: []regMask{ 970 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 971 }, 972 }, 973 }, 974 { 975 name: "ADDQconst", 976 auxType: auxInt64, 977 argLen: 1, 978 asm: x86.AADDQ, 979 reg: regInfo{ 980 inputs: []inputInfo{ 981 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 982 }, 983 clobbers: 8589934592, // FLAGS 984 outputs: []regMask{ 985 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 986 }, 987 }, 988 }, 989 { 990 name: "ADDLconst", 991 auxType: auxInt32, 992 argLen: 1, 993 asm: x86.AADDL, 994 reg: regInfo{ 995 inputs: []inputInfo{ 996 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 997 }, 998 clobbers: 8589934592, // FLAGS 999 outputs: []regMask{ 1000 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1001 }, 1002 }, 1003 }, 1004 { 1005 name: "SUBQ", 1006 argLen: 2, 1007 resultInArg0: true, 1008 asm: x86.ASUBQ, 1009 reg: regInfo{ 1010 inputs: []inputInfo{ 1011 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1012 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1013 }, 1014 clobbers: 8589934592, // FLAGS 1015 outputs: []regMask{ 1016 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1017 }, 1018 }, 1019 }, 1020 { 1021 name: "SUBL", 1022 argLen: 2, 1023 resultInArg0: true, 1024 asm: x86.ASUBL, 1025 reg: regInfo{ 1026 inputs: []inputInfo{ 1027 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1028 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1029 }, 1030 clobbers: 8589934592, // FLAGS 1031 outputs: []regMask{ 1032 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1033 }, 1034 }, 1035 }, 1036 { 1037 name: "SUBQconst", 1038 auxType: auxInt64, 1039 argLen: 1, 1040 resultInArg0: true, 1041 asm: x86.ASUBQ, 1042 reg: regInfo{ 1043 inputs: []inputInfo{ 1044 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1045 }, 1046 clobbers: 8589934592, // FLAGS 1047 outputs: []regMask{ 1048 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1049 }, 1050 }, 1051 }, 1052 { 1053 name: "SUBLconst", 1054 auxType: auxInt32, 1055 argLen: 1, 1056 resultInArg0: true, 1057 asm: x86.ASUBL, 1058 reg: regInfo{ 1059 inputs: []inputInfo{ 1060 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1061 }, 1062 clobbers: 8589934592, // FLAGS 1063 outputs: []regMask{ 1064 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1065 }, 1066 }, 1067 }, 1068 { 1069 name: "MULQ", 1070 argLen: 2, 1071 commutative: true, 1072 resultInArg0: true, 1073 asm: x86.AIMULQ, 1074 reg: regInfo{ 1075 inputs: []inputInfo{ 1076 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1077 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1078 }, 1079 clobbers: 8589934592, // FLAGS 1080 outputs: []regMask{ 1081 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1082 }, 1083 }, 1084 }, 1085 { 1086 name: "MULL", 1087 argLen: 2, 1088 commutative: true, 1089 resultInArg0: true, 1090 asm: x86.AIMULL, 1091 reg: regInfo{ 1092 inputs: []inputInfo{ 1093 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1094 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1095 }, 1096 clobbers: 8589934592, // FLAGS 1097 outputs: []regMask{ 1098 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1099 }, 1100 }, 1101 }, 1102 { 1103 name: "MULQconst", 1104 auxType: auxInt64, 1105 argLen: 1, 1106 resultInArg0: true, 1107 asm: x86.AIMULQ, 1108 reg: regInfo{ 1109 inputs: []inputInfo{ 1110 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1111 }, 1112 clobbers: 8589934592, // FLAGS 1113 outputs: []regMask{ 1114 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1115 }, 1116 }, 1117 }, 1118 { 1119 name: "MULLconst", 1120 auxType: auxInt32, 1121 argLen: 1, 1122 resultInArg0: true, 1123 asm: x86.AIMULL, 1124 reg: regInfo{ 1125 inputs: []inputInfo{ 1126 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1127 }, 1128 clobbers: 8589934592, // FLAGS 1129 outputs: []regMask{ 1130 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1131 }, 1132 }, 1133 }, 1134 { 1135 name: "HMULQ", 1136 argLen: 2, 1137 asm: x86.AIMULQ, 1138 reg: regInfo{ 1139 inputs: []inputInfo{ 1140 {0, 1}, // AX 1141 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1142 }, 1143 clobbers: 8589934593, // AX FLAGS 1144 outputs: []regMask{ 1145 4, // DX 1146 }, 1147 }, 1148 }, 1149 { 1150 name: "HMULL", 1151 argLen: 2, 1152 asm: x86.AIMULL, 1153 reg: regInfo{ 1154 inputs: []inputInfo{ 1155 {0, 1}, // AX 1156 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1157 }, 1158 clobbers: 8589934593, // AX FLAGS 1159 outputs: []regMask{ 1160 4, // DX 1161 }, 1162 }, 1163 }, 1164 { 1165 name: "HMULW", 1166 argLen: 2, 1167 asm: x86.AIMULW, 1168 reg: regInfo{ 1169 inputs: []inputInfo{ 1170 {0, 1}, // AX 1171 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1172 }, 1173 clobbers: 8589934593, // AX FLAGS 1174 outputs: []regMask{ 1175 4, // DX 1176 }, 1177 }, 1178 }, 1179 { 1180 name: "HMULB", 1181 argLen: 2, 1182 asm: x86.AIMULB, 1183 reg: regInfo{ 1184 inputs: []inputInfo{ 1185 {0, 1}, // AX 1186 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1187 }, 1188 clobbers: 8589934593, // AX FLAGS 1189 outputs: []regMask{ 1190 4, // DX 1191 }, 1192 }, 1193 }, 1194 { 1195 name: "HMULQU", 1196 argLen: 2, 1197 asm: x86.AMULQ, 1198 reg: regInfo{ 1199 inputs: []inputInfo{ 1200 {0, 1}, // AX 1201 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1202 }, 1203 clobbers: 8589934593, // AX FLAGS 1204 outputs: []regMask{ 1205 4, // DX 1206 }, 1207 }, 1208 }, 1209 { 1210 name: "HMULLU", 1211 argLen: 2, 1212 asm: x86.AMULL, 1213 reg: regInfo{ 1214 inputs: []inputInfo{ 1215 {0, 1}, // AX 1216 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1217 }, 1218 clobbers: 8589934593, // AX FLAGS 1219 outputs: []regMask{ 1220 4, // DX 1221 }, 1222 }, 1223 }, 1224 { 1225 name: "HMULWU", 1226 argLen: 2, 1227 asm: x86.AMULW, 1228 reg: regInfo{ 1229 inputs: []inputInfo{ 1230 {0, 1}, // AX 1231 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1232 }, 1233 clobbers: 8589934593, // AX FLAGS 1234 outputs: []regMask{ 1235 4, // DX 1236 }, 1237 }, 1238 }, 1239 { 1240 name: "HMULBU", 1241 argLen: 2, 1242 asm: x86.AMULB, 1243 reg: regInfo{ 1244 inputs: []inputInfo{ 1245 {0, 1}, // AX 1246 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1247 }, 1248 clobbers: 8589934593, // AX FLAGS 1249 outputs: []regMask{ 1250 4, // DX 1251 }, 1252 }, 1253 }, 1254 { 1255 name: "AVGQU", 1256 argLen: 2, 1257 commutative: true, 1258 resultInArg0: true, 1259 reg: regInfo{ 1260 inputs: []inputInfo{ 1261 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1262 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1263 }, 1264 clobbers: 8589934592, // FLAGS 1265 outputs: []regMask{ 1266 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1267 }, 1268 }, 1269 }, 1270 { 1271 name: "DIVQ", 1272 argLen: 2, 1273 asm: x86.AIDIVQ, 1274 reg: regInfo{ 1275 inputs: []inputInfo{ 1276 {0, 1}, // AX 1277 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1278 }, 1279 clobbers: 8589934596, // DX FLAGS 1280 outputs: []regMask{ 1281 1, // AX 1282 }, 1283 }, 1284 }, 1285 { 1286 name: "DIVL", 1287 argLen: 2, 1288 asm: x86.AIDIVL, 1289 reg: regInfo{ 1290 inputs: []inputInfo{ 1291 {0, 1}, // AX 1292 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1293 }, 1294 clobbers: 8589934596, // DX FLAGS 1295 outputs: []regMask{ 1296 1, // AX 1297 }, 1298 }, 1299 }, 1300 { 1301 name: "DIVW", 1302 argLen: 2, 1303 asm: x86.AIDIVW, 1304 reg: regInfo{ 1305 inputs: []inputInfo{ 1306 {0, 1}, // AX 1307 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1308 }, 1309 clobbers: 8589934596, // DX FLAGS 1310 outputs: []regMask{ 1311 1, // AX 1312 }, 1313 }, 1314 }, 1315 { 1316 name: "DIVQU", 1317 argLen: 2, 1318 asm: x86.ADIVQ, 1319 reg: regInfo{ 1320 inputs: []inputInfo{ 1321 {0, 1}, // AX 1322 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1323 }, 1324 clobbers: 8589934596, // DX FLAGS 1325 outputs: []regMask{ 1326 1, // AX 1327 }, 1328 }, 1329 }, 1330 { 1331 name: "DIVLU", 1332 argLen: 2, 1333 asm: x86.ADIVL, 1334 reg: regInfo{ 1335 inputs: []inputInfo{ 1336 {0, 1}, // AX 1337 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1338 }, 1339 clobbers: 8589934596, // DX FLAGS 1340 outputs: []regMask{ 1341 1, // AX 1342 }, 1343 }, 1344 }, 1345 { 1346 name: "DIVWU", 1347 argLen: 2, 1348 asm: x86.ADIVW, 1349 reg: regInfo{ 1350 inputs: []inputInfo{ 1351 {0, 1}, // AX 1352 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1353 }, 1354 clobbers: 8589934596, // DX FLAGS 1355 outputs: []regMask{ 1356 1, // AX 1357 }, 1358 }, 1359 }, 1360 { 1361 name: "MODQ", 1362 argLen: 2, 1363 asm: x86.AIDIVQ, 1364 reg: regInfo{ 1365 inputs: []inputInfo{ 1366 {0, 1}, // AX 1367 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1368 }, 1369 clobbers: 8589934593, // AX FLAGS 1370 outputs: []regMask{ 1371 4, // DX 1372 }, 1373 }, 1374 }, 1375 { 1376 name: "MODL", 1377 argLen: 2, 1378 asm: x86.AIDIVL, 1379 reg: regInfo{ 1380 inputs: []inputInfo{ 1381 {0, 1}, // AX 1382 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1383 }, 1384 clobbers: 8589934593, // AX FLAGS 1385 outputs: []regMask{ 1386 4, // DX 1387 }, 1388 }, 1389 }, 1390 { 1391 name: "MODW", 1392 argLen: 2, 1393 asm: x86.AIDIVW, 1394 reg: regInfo{ 1395 inputs: []inputInfo{ 1396 {0, 1}, // AX 1397 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1398 }, 1399 clobbers: 8589934593, // AX FLAGS 1400 outputs: []regMask{ 1401 4, // DX 1402 }, 1403 }, 1404 }, 1405 { 1406 name: "MODQU", 1407 argLen: 2, 1408 asm: x86.ADIVQ, 1409 reg: regInfo{ 1410 inputs: []inputInfo{ 1411 {0, 1}, // AX 1412 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1413 }, 1414 clobbers: 8589934593, // AX FLAGS 1415 outputs: []regMask{ 1416 4, // DX 1417 }, 1418 }, 1419 }, 1420 { 1421 name: "MODLU", 1422 argLen: 2, 1423 asm: x86.ADIVL, 1424 reg: regInfo{ 1425 inputs: []inputInfo{ 1426 {0, 1}, // AX 1427 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1428 }, 1429 clobbers: 8589934593, // AX FLAGS 1430 outputs: []regMask{ 1431 4, // DX 1432 }, 1433 }, 1434 }, 1435 { 1436 name: "MODWU", 1437 argLen: 2, 1438 asm: x86.ADIVW, 1439 reg: regInfo{ 1440 inputs: []inputInfo{ 1441 {0, 1}, // AX 1442 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1443 }, 1444 clobbers: 8589934593, // AX FLAGS 1445 outputs: []regMask{ 1446 4, // DX 1447 }, 1448 }, 1449 }, 1450 { 1451 name: "ANDQ", 1452 argLen: 2, 1453 commutative: true, 1454 resultInArg0: true, 1455 asm: x86.AANDQ, 1456 reg: regInfo{ 1457 inputs: []inputInfo{ 1458 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1459 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1460 }, 1461 clobbers: 8589934592, // FLAGS 1462 outputs: []regMask{ 1463 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1464 }, 1465 }, 1466 }, 1467 { 1468 name: "ANDL", 1469 argLen: 2, 1470 commutative: true, 1471 resultInArg0: true, 1472 asm: x86.AANDL, 1473 reg: regInfo{ 1474 inputs: []inputInfo{ 1475 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1476 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1477 }, 1478 clobbers: 8589934592, // FLAGS 1479 outputs: []regMask{ 1480 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1481 }, 1482 }, 1483 }, 1484 { 1485 name: "ANDQconst", 1486 auxType: auxInt64, 1487 argLen: 1, 1488 resultInArg0: true, 1489 asm: x86.AANDQ, 1490 reg: regInfo{ 1491 inputs: []inputInfo{ 1492 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1493 }, 1494 clobbers: 8589934592, // FLAGS 1495 outputs: []regMask{ 1496 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1497 }, 1498 }, 1499 }, 1500 { 1501 name: "ANDLconst", 1502 auxType: auxInt32, 1503 argLen: 1, 1504 resultInArg0: true, 1505 asm: x86.AANDL, 1506 reg: regInfo{ 1507 inputs: []inputInfo{ 1508 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1509 }, 1510 clobbers: 8589934592, // FLAGS 1511 outputs: []regMask{ 1512 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1513 }, 1514 }, 1515 }, 1516 { 1517 name: "ORQ", 1518 argLen: 2, 1519 commutative: true, 1520 resultInArg0: true, 1521 asm: x86.AORQ, 1522 reg: regInfo{ 1523 inputs: []inputInfo{ 1524 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1525 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1526 }, 1527 clobbers: 8589934592, // FLAGS 1528 outputs: []regMask{ 1529 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1530 }, 1531 }, 1532 }, 1533 { 1534 name: "ORL", 1535 argLen: 2, 1536 commutative: true, 1537 resultInArg0: true, 1538 asm: x86.AORL, 1539 reg: regInfo{ 1540 inputs: []inputInfo{ 1541 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1542 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1543 }, 1544 clobbers: 8589934592, // FLAGS 1545 outputs: []regMask{ 1546 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1547 }, 1548 }, 1549 }, 1550 { 1551 name: "ORQconst", 1552 auxType: auxInt64, 1553 argLen: 1, 1554 resultInArg0: true, 1555 asm: x86.AORQ, 1556 reg: regInfo{ 1557 inputs: []inputInfo{ 1558 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1559 }, 1560 clobbers: 8589934592, // FLAGS 1561 outputs: []regMask{ 1562 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1563 }, 1564 }, 1565 }, 1566 { 1567 name: "ORLconst", 1568 auxType: auxInt32, 1569 argLen: 1, 1570 resultInArg0: true, 1571 asm: x86.AORL, 1572 reg: regInfo{ 1573 inputs: []inputInfo{ 1574 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1575 }, 1576 clobbers: 8589934592, // FLAGS 1577 outputs: []regMask{ 1578 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1579 }, 1580 }, 1581 }, 1582 { 1583 name: "XORQ", 1584 argLen: 2, 1585 commutative: true, 1586 resultInArg0: true, 1587 asm: x86.AXORQ, 1588 reg: regInfo{ 1589 inputs: []inputInfo{ 1590 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1591 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1592 }, 1593 clobbers: 8589934592, // FLAGS 1594 outputs: []regMask{ 1595 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1596 }, 1597 }, 1598 }, 1599 { 1600 name: "XORL", 1601 argLen: 2, 1602 commutative: true, 1603 resultInArg0: true, 1604 asm: x86.AXORL, 1605 reg: regInfo{ 1606 inputs: []inputInfo{ 1607 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1608 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1609 }, 1610 clobbers: 8589934592, // FLAGS 1611 outputs: []regMask{ 1612 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1613 }, 1614 }, 1615 }, 1616 { 1617 name: "XORQconst", 1618 auxType: auxInt64, 1619 argLen: 1, 1620 resultInArg0: true, 1621 asm: x86.AXORQ, 1622 reg: regInfo{ 1623 inputs: []inputInfo{ 1624 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1625 }, 1626 clobbers: 8589934592, // FLAGS 1627 outputs: []regMask{ 1628 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1629 }, 1630 }, 1631 }, 1632 { 1633 name: "XORLconst", 1634 auxType: auxInt32, 1635 argLen: 1, 1636 resultInArg0: true, 1637 asm: x86.AXORL, 1638 reg: regInfo{ 1639 inputs: []inputInfo{ 1640 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1641 }, 1642 clobbers: 8589934592, // FLAGS 1643 outputs: []regMask{ 1644 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1645 }, 1646 }, 1647 }, 1648 { 1649 name: "CMPQ", 1650 argLen: 2, 1651 asm: x86.ACMPQ, 1652 reg: regInfo{ 1653 inputs: []inputInfo{ 1654 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1655 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1656 }, 1657 outputs: []regMask{ 1658 8589934592, // FLAGS 1659 }, 1660 }, 1661 }, 1662 { 1663 name: "CMPL", 1664 argLen: 2, 1665 asm: x86.ACMPL, 1666 reg: regInfo{ 1667 inputs: []inputInfo{ 1668 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1669 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1670 }, 1671 outputs: []regMask{ 1672 8589934592, // FLAGS 1673 }, 1674 }, 1675 }, 1676 { 1677 name: "CMPW", 1678 argLen: 2, 1679 asm: x86.ACMPW, 1680 reg: regInfo{ 1681 inputs: []inputInfo{ 1682 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1683 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1684 }, 1685 outputs: []regMask{ 1686 8589934592, // FLAGS 1687 }, 1688 }, 1689 }, 1690 { 1691 name: "CMPB", 1692 argLen: 2, 1693 asm: x86.ACMPB, 1694 reg: regInfo{ 1695 inputs: []inputInfo{ 1696 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1697 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1698 }, 1699 outputs: []regMask{ 1700 8589934592, // FLAGS 1701 }, 1702 }, 1703 }, 1704 { 1705 name: "CMPQconst", 1706 auxType: auxInt64, 1707 argLen: 1, 1708 asm: x86.ACMPQ, 1709 reg: regInfo{ 1710 inputs: []inputInfo{ 1711 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1712 }, 1713 outputs: []regMask{ 1714 8589934592, // FLAGS 1715 }, 1716 }, 1717 }, 1718 { 1719 name: "CMPLconst", 1720 auxType: auxInt32, 1721 argLen: 1, 1722 asm: x86.ACMPL, 1723 reg: regInfo{ 1724 inputs: []inputInfo{ 1725 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1726 }, 1727 outputs: []regMask{ 1728 8589934592, // FLAGS 1729 }, 1730 }, 1731 }, 1732 { 1733 name: "CMPWconst", 1734 auxType: auxInt16, 1735 argLen: 1, 1736 asm: x86.ACMPW, 1737 reg: regInfo{ 1738 inputs: []inputInfo{ 1739 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1740 }, 1741 outputs: []regMask{ 1742 8589934592, // FLAGS 1743 }, 1744 }, 1745 }, 1746 { 1747 name: "CMPBconst", 1748 auxType: auxInt8, 1749 argLen: 1, 1750 asm: x86.ACMPB, 1751 reg: regInfo{ 1752 inputs: []inputInfo{ 1753 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1754 }, 1755 outputs: []regMask{ 1756 8589934592, // FLAGS 1757 }, 1758 }, 1759 }, 1760 { 1761 name: "UCOMISS", 1762 argLen: 2, 1763 asm: x86.AUCOMISS, 1764 reg: regInfo{ 1765 inputs: []inputInfo{ 1766 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 1767 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 1768 }, 1769 outputs: []regMask{ 1770 8589934592, // FLAGS 1771 }, 1772 }, 1773 }, 1774 { 1775 name: "UCOMISD", 1776 argLen: 2, 1777 asm: x86.AUCOMISD, 1778 reg: regInfo{ 1779 inputs: []inputInfo{ 1780 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 1781 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 1782 }, 1783 outputs: []regMask{ 1784 8589934592, // FLAGS 1785 }, 1786 }, 1787 }, 1788 { 1789 name: "TESTQ", 1790 argLen: 2, 1791 asm: x86.ATESTQ, 1792 reg: regInfo{ 1793 inputs: []inputInfo{ 1794 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1795 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1796 }, 1797 outputs: []regMask{ 1798 8589934592, // FLAGS 1799 }, 1800 }, 1801 }, 1802 { 1803 name: "TESTL", 1804 argLen: 2, 1805 asm: x86.ATESTL, 1806 reg: regInfo{ 1807 inputs: []inputInfo{ 1808 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1809 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1810 }, 1811 outputs: []regMask{ 1812 8589934592, // FLAGS 1813 }, 1814 }, 1815 }, 1816 { 1817 name: "TESTW", 1818 argLen: 2, 1819 asm: x86.ATESTW, 1820 reg: regInfo{ 1821 inputs: []inputInfo{ 1822 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1823 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1824 }, 1825 outputs: []regMask{ 1826 8589934592, // FLAGS 1827 }, 1828 }, 1829 }, 1830 { 1831 name: "TESTB", 1832 argLen: 2, 1833 asm: x86.ATESTB, 1834 reg: regInfo{ 1835 inputs: []inputInfo{ 1836 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1837 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1838 }, 1839 outputs: []regMask{ 1840 8589934592, // FLAGS 1841 }, 1842 }, 1843 }, 1844 { 1845 name: "TESTQconst", 1846 auxType: auxInt64, 1847 argLen: 1, 1848 asm: x86.ATESTQ, 1849 reg: regInfo{ 1850 inputs: []inputInfo{ 1851 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1852 }, 1853 outputs: []regMask{ 1854 8589934592, // FLAGS 1855 }, 1856 }, 1857 }, 1858 { 1859 name: "TESTLconst", 1860 auxType: auxInt32, 1861 argLen: 1, 1862 asm: x86.ATESTL, 1863 reg: regInfo{ 1864 inputs: []inputInfo{ 1865 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1866 }, 1867 outputs: []regMask{ 1868 8589934592, // FLAGS 1869 }, 1870 }, 1871 }, 1872 { 1873 name: "TESTWconst", 1874 auxType: auxInt16, 1875 argLen: 1, 1876 asm: x86.ATESTW, 1877 reg: regInfo{ 1878 inputs: []inputInfo{ 1879 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1880 }, 1881 outputs: []regMask{ 1882 8589934592, // FLAGS 1883 }, 1884 }, 1885 }, 1886 { 1887 name: "TESTBconst", 1888 auxType: auxInt8, 1889 argLen: 1, 1890 asm: x86.ATESTB, 1891 reg: regInfo{ 1892 inputs: []inputInfo{ 1893 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1894 }, 1895 outputs: []regMask{ 1896 8589934592, // FLAGS 1897 }, 1898 }, 1899 }, 1900 { 1901 name: "SHLQ", 1902 argLen: 2, 1903 resultInArg0: true, 1904 asm: x86.ASHLQ, 1905 reg: regInfo{ 1906 inputs: []inputInfo{ 1907 {1, 2}, // CX 1908 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1909 }, 1910 clobbers: 8589934592, // FLAGS 1911 outputs: []regMask{ 1912 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1913 }, 1914 }, 1915 }, 1916 { 1917 name: "SHLL", 1918 argLen: 2, 1919 resultInArg0: true, 1920 asm: x86.ASHLL, 1921 reg: regInfo{ 1922 inputs: []inputInfo{ 1923 {1, 2}, // CX 1924 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1925 }, 1926 clobbers: 8589934592, // FLAGS 1927 outputs: []regMask{ 1928 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1929 }, 1930 }, 1931 }, 1932 { 1933 name: "SHLQconst", 1934 auxType: auxInt64, 1935 argLen: 1, 1936 resultInArg0: true, 1937 asm: x86.ASHLQ, 1938 reg: regInfo{ 1939 inputs: []inputInfo{ 1940 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1941 }, 1942 clobbers: 8589934592, // FLAGS 1943 outputs: []regMask{ 1944 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1945 }, 1946 }, 1947 }, 1948 { 1949 name: "SHLLconst", 1950 auxType: auxInt32, 1951 argLen: 1, 1952 resultInArg0: true, 1953 asm: x86.ASHLL, 1954 reg: regInfo{ 1955 inputs: []inputInfo{ 1956 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1957 }, 1958 clobbers: 8589934592, // FLAGS 1959 outputs: []regMask{ 1960 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1961 }, 1962 }, 1963 }, 1964 { 1965 name: "SHRQ", 1966 argLen: 2, 1967 resultInArg0: true, 1968 asm: x86.ASHRQ, 1969 reg: regInfo{ 1970 inputs: []inputInfo{ 1971 {1, 2}, // CX 1972 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1973 }, 1974 clobbers: 8589934592, // FLAGS 1975 outputs: []regMask{ 1976 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1977 }, 1978 }, 1979 }, 1980 { 1981 name: "SHRL", 1982 argLen: 2, 1983 resultInArg0: true, 1984 asm: x86.ASHRL, 1985 reg: regInfo{ 1986 inputs: []inputInfo{ 1987 {1, 2}, // CX 1988 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1989 }, 1990 clobbers: 8589934592, // FLAGS 1991 outputs: []regMask{ 1992 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1993 }, 1994 }, 1995 }, 1996 { 1997 name: "SHRW", 1998 argLen: 2, 1999 resultInArg0: true, 2000 asm: x86.ASHRW, 2001 reg: regInfo{ 2002 inputs: []inputInfo{ 2003 {1, 2}, // CX 2004 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2005 }, 2006 clobbers: 8589934592, // FLAGS 2007 outputs: []regMask{ 2008 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2009 }, 2010 }, 2011 }, 2012 { 2013 name: "SHRB", 2014 argLen: 2, 2015 resultInArg0: true, 2016 asm: x86.ASHRB, 2017 reg: regInfo{ 2018 inputs: []inputInfo{ 2019 {1, 2}, // CX 2020 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2021 }, 2022 clobbers: 8589934592, // FLAGS 2023 outputs: []regMask{ 2024 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2025 }, 2026 }, 2027 }, 2028 { 2029 name: "SHRQconst", 2030 auxType: auxInt64, 2031 argLen: 1, 2032 resultInArg0: true, 2033 asm: x86.ASHRQ, 2034 reg: regInfo{ 2035 inputs: []inputInfo{ 2036 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2037 }, 2038 clobbers: 8589934592, // FLAGS 2039 outputs: []regMask{ 2040 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2041 }, 2042 }, 2043 }, 2044 { 2045 name: "SHRLconst", 2046 auxType: auxInt32, 2047 argLen: 1, 2048 resultInArg0: true, 2049 asm: x86.ASHRL, 2050 reg: regInfo{ 2051 inputs: []inputInfo{ 2052 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2053 }, 2054 clobbers: 8589934592, // FLAGS 2055 outputs: []regMask{ 2056 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2057 }, 2058 }, 2059 }, 2060 { 2061 name: "SHRWconst", 2062 auxType: auxInt16, 2063 argLen: 1, 2064 resultInArg0: true, 2065 asm: x86.ASHRW, 2066 reg: regInfo{ 2067 inputs: []inputInfo{ 2068 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2069 }, 2070 clobbers: 8589934592, // FLAGS 2071 outputs: []regMask{ 2072 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2073 }, 2074 }, 2075 }, 2076 { 2077 name: "SHRBconst", 2078 auxType: auxInt8, 2079 argLen: 1, 2080 resultInArg0: true, 2081 asm: x86.ASHRB, 2082 reg: regInfo{ 2083 inputs: []inputInfo{ 2084 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2085 }, 2086 clobbers: 8589934592, // FLAGS 2087 outputs: []regMask{ 2088 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2089 }, 2090 }, 2091 }, 2092 { 2093 name: "SARQ", 2094 argLen: 2, 2095 resultInArg0: true, 2096 asm: x86.ASARQ, 2097 reg: regInfo{ 2098 inputs: []inputInfo{ 2099 {1, 2}, // CX 2100 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2101 }, 2102 clobbers: 8589934592, // FLAGS 2103 outputs: []regMask{ 2104 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2105 }, 2106 }, 2107 }, 2108 { 2109 name: "SARL", 2110 argLen: 2, 2111 resultInArg0: true, 2112 asm: x86.ASARL, 2113 reg: regInfo{ 2114 inputs: []inputInfo{ 2115 {1, 2}, // CX 2116 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2117 }, 2118 clobbers: 8589934592, // FLAGS 2119 outputs: []regMask{ 2120 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2121 }, 2122 }, 2123 }, 2124 { 2125 name: "SARW", 2126 argLen: 2, 2127 resultInArg0: true, 2128 asm: x86.ASARW, 2129 reg: regInfo{ 2130 inputs: []inputInfo{ 2131 {1, 2}, // CX 2132 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2133 }, 2134 clobbers: 8589934592, // FLAGS 2135 outputs: []regMask{ 2136 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2137 }, 2138 }, 2139 }, 2140 { 2141 name: "SARB", 2142 argLen: 2, 2143 resultInArg0: true, 2144 asm: x86.ASARB, 2145 reg: regInfo{ 2146 inputs: []inputInfo{ 2147 {1, 2}, // CX 2148 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2149 }, 2150 clobbers: 8589934592, // FLAGS 2151 outputs: []regMask{ 2152 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2153 }, 2154 }, 2155 }, 2156 { 2157 name: "SARQconst", 2158 auxType: auxInt64, 2159 argLen: 1, 2160 resultInArg0: true, 2161 asm: x86.ASARQ, 2162 reg: regInfo{ 2163 inputs: []inputInfo{ 2164 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2165 }, 2166 clobbers: 8589934592, // FLAGS 2167 outputs: []regMask{ 2168 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2169 }, 2170 }, 2171 }, 2172 { 2173 name: "SARLconst", 2174 auxType: auxInt32, 2175 argLen: 1, 2176 resultInArg0: true, 2177 asm: x86.ASARL, 2178 reg: regInfo{ 2179 inputs: []inputInfo{ 2180 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2181 }, 2182 clobbers: 8589934592, // FLAGS 2183 outputs: []regMask{ 2184 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2185 }, 2186 }, 2187 }, 2188 { 2189 name: "SARWconst", 2190 auxType: auxInt16, 2191 argLen: 1, 2192 resultInArg0: true, 2193 asm: x86.ASARW, 2194 reg: regInfo{ 2195 inputs: []inputInfo{ 2196 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2197 }, 2198 clobbers: 8589934592, // FLAGS 2199 outputs: []regMask{ 2200 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2201 }, 2202 }, 2203 }, 2204 { 2205 name: "SARBconst", 2206 auxType: auxInt8, 2207 argLen: 1, 2208 resultInArg0: true, 2209 asm: x86.ASARB, 2210 reg: regInfo{ 2211 inputs: []inputInfo{ 2212 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2213 }, 2214 clobbers: 8589934592, // FLAGS 2215 outputs: []regMask{ 2216 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2217 }, 2218 }, 2219 }, 2220 { 2221 name: "ROLQconst", 2222 auxType: auxInt64, 2223 argLen: 1, 2224 resultInArg0: true, 2225 asm: x86.AROLQ, 2226 reg: regInfo{ 2227 inputs: []inputInfo{ 2228 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2229 }, 2230 clobbers: 8589934592, // FLAGS 2231 outputs: []regMask{ 2232 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2233 }, 2234 }, 2235 }, 2236 { 2237 name: "ROLLconst", 2238 auxType: auxInt32, 2239 argLen: 1, 2240 resultInArg0: true, 2241 asm: x86.AROLL, 2242 reg: regInfo{ 2243 inputs: []inputInfo{ 2244 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2245 }, 2246 clobbers: 8589934592, // FLAGS 2247 outputs: []regMask{ 2248 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2249 }, 2250 }, 2251 }, 2252 { 2253 name: "ROLWconst", 2254 auxType: auxInt16, 2255 argLen: 1, 2256 resultInArg0: true, 2257 asm: x86.AROLW, 2258 reg: regInfo{ 2259 inputs: []inputInfo{ 2260 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2261 }, 2262 clobbers: 8589934592, // FLAGS 2263 outputs: []regMask{ 2264 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2265 }, 2266 }, 2267 }, 2268 { 2269 name: "ROLBconst", 2270 auxType: auxInt8, 2271 argLen: 1, 2272 resultInArg0: true, 2273 asm: x86.AROLB, 2274 reg: regInfo{ 2275 inputs: []inputInfo{ 2276 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2277 }, 2278 clobbers: 8589934592, // FLAGS 2279 outputs: []regMask{ 2280 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2281 }, 2282 }, 2283 }, 2284 { 2285 name: "NEGQ", 2286 argLen: 1, 2287 resultInArg0: true, 2288 asm: x86.ANEGQ, 2289 reg: regInfo{ 2290 inputs: []inputInfo{ 2291 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2292 }, 2293 clobbers: 8589934592, // FLAGS 2294 outputs: []regMask{ 2295 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2296 }, 2297 }, 2298 }, 2299 { 2300 name: "NEGL", 2301 argLen: 1, 2302 resultInArg0: true, 2303 asm: x86.ANEGL, 2304 reg: regInfo{ 2305 inputs: []inputInfo{ 2306 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2307 }, 2308 clobbers: 8589934592, // FLAGS 2309 outputs: []regMask{ 2310 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2311 }, 2312 }, 2313 }, 2314 { 2315 name: "NOTQ", 2316 argLen: 1, 2317 resultInArg0: true, 2318 asm: x86.ANOTQ, 2319 reg: regInfo{ 2320 inputs: []inputInfo{ 2321 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2322 }, 2323 clobbers: 8589934592, // FLAGS 2324 outputs: []regMask{ 2325 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2326 }, 2327 }, 2328 }, 2329 { 2330 name: "NOTL", 2331 argLen: 1, 2332 resultInArg0: true, 2333 asm: x86.ANOTL, 2334 reg: regInfo{ 2335 inputs: []inputInfo{ 2336 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2337 }, 2338 clobbers: 8589934592, // FLAGS 2339 outputs: []regMask{ 2340 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2341 }, 2342 }, 2343 }, 2344 { 2345 name: "BSFQ", 2346 argLen: 1, 2347 asm: x86.ABSFQ, 2348 reg: regInfo{ 2349 inputs: []inputInfo{ 2350 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2351 }, 2352 clobbers: 8589934592, // FLAGS 2353 outputs: []regMask{ 2354 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2355 }, 2356 }, 2357 }, 2358 { 2359 name: "BSFL", 2360 argLen: 1, 2361 asm: x86.ABSFL, 2362 reg: regInfo{ 2363 inputs: []inputInfo{ 2364 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2365 }, 2366 clobbers: 8589934592, // FLAGS 2367 outputs: []regMask{ 2368 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2369 }, 2370 }, 2371 }, 2372 { 2373 name: "BSFW", 2374 argLen: 1, 2375 asm: x86.ABSFW, 2376 reg: regInfo{ 2377 inputs: []inputInfo{ 2378 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2379 }, 2380 clobbers: 8589934592, // FLAGS 2381 outputs: []regMask{ 2382 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2383 }, 2384 }, 2385 }, 2386 { 2387 name: "BSRQ", 2388 argLen: 1, 2389 asm: x86.ABSRQ, 2390 reg: regInfo{ 2391 inputs: []inputInfo{ 2392 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2393 }, 2394 clobbers: 8589934592, // FLAGS 2395 outputs: []regMask{ 2396 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2397 }, 2398 }, 2399 }, 2400 { 2401 name: "BSRL", 2402 argLen: 1, 2403 asm: x86.ABSRL, 2404 reg: regInfo{ 2405 inputs: []inputInfo{ 2406 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2407 }, 2408 clobbers: 8589934592, // FLAGS 2409 outputs: []regMask{ 2410 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2411 }, 2412 }, 2413 }, 2414 { 2415 name: "BSRW", 2416 argLen: 1, 2417 asm: x86.ABSRW, 2418 reg: regInfo{ 2419 inputs: []inputInfo{ 2420 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2421 }, 2422 clobbers: 8589934592, // FLAGS 2423 outputs: []regMask{ 2424 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2425 }, 2426 }, 2427 }, 2428 { 2429 name: "CMOVQEQconst", 2430 auxType: auxInt64, 2431 argLen: 2, 2432 resultInArg0: true, 2433 asm: x86.ACMOVQEQ, 2434 reg: regInfo{ 2435 inputs: []inputInfo{ 2436 {1, 8589934592}, // FLAGS 2437 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2438 }, 2439 clobbers: 8589934593, // AX FLAGS 2440 outputs: []regMask{ 2441 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2442 }, 2443 }, 2444 }, 2445 { 2446 name: "CMOVLEQconst", 2447 auxType: auxInt32, 2448 argLen: 2, 2449 resultInArg0: true, 2450 asm: x86.ACMOVLEQ, 2451 reg: regInfo{ 2452 inputs: []inputInfo{ 2453 {1, 8589934592}, // FLAGS 2454 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2455 }, 2456 clobbers: 8589934593, // AX FLAGS 2457 outputs: []regMask{ 2458 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2459 }, 2460 }, 2461 }, 2462 { 2463 name: "CMOVWEQconst", 2464 auxType: auxInt16, 2465 argLen: 2, 2466 resultInArg0: true, 2467 asm: x86.ACMOVLEQ, 2468 reg: regInfo{ 2469 inputs: []inputInfo{ 2470 {1, 8589934592}, // FLAGS 2471 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2472 }, 2473 clobbers: 8589934593, // AX FLAGS 2474 outputs: []regMask{ 2475 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2476 }, 2477 }, 2478 }, 2479 { 2480 name: "CMOVQNEconst", 2481 auxType: auxInt64, 2482 argLen: 2, 2483 resultInArg0: true, 2484 asm: x86.ACMOVQNE, 2485 reg: regInfo{ 2486 inputs: []inputInfo{ 2487 {1, 8589934592}, // FLAGS 2488 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2489 }, 2490 clobbers: 8589934593, // AX FLAGS 2491 outputs: []regMask{ 2492 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2493 }, 2494 }, 2495 }, 2496 { 2497 name: "CMOVLNEconst", 2498 auxType: auxInt32, 2499 argLen: 2, 2500 resultInArg0: true, 2501 asm: x86.ACMOVLNE, 2502 reg: regInfo{ 2503 inputs: []inputInfo{ 2504 {1, 8589934592}, // FLAGS 2505 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2506 }, 2507 clobbers: 8589934593, // AX FLAGS 2508 outputs: []regMask{ 2509 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2510 }, 2511 }, 2512 }, 2513 { 2514 name: "CMOVWNEconst", 2515 auxType: auxInt16, 2516 argLen: 2, 2517 resultInArg0: true, 2518 asm: x86.ACMOVLNE, 2519 reg: regInfo{ 2520 inputs: []inputInfo{ 2521 {1, 8589934592}, // FLAGS 2522 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2523 }, 2524 clobbers: 8589934593, // AX FLAGS 2525 outputs: []regMask{ 2526 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2527 }, 2528 }, 2529 }, 2530 { 2531 name: "BSWAPQ", 2532 argLen: 1, 2533 resultInArg0: true, 2534 asm: x86.ABSWAPQ, 2535 reg: regInfo{ 2536 inputs: []inputInfo{ 2537 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2538 }, 2539 clobbers: 8589934592, // FLAGS 2540 outputs: []regMask{ 2541 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2542 }, 2543 }, 2544 }, 2545 { 2546 name: "BSWAPL", 2547 argLen: 1, 2548 resultInArg0: true, 2549 asm: x86.ABSWAPL, 2550 reg: regInfo{ 2551 inputs: []inputInfo{ 2552 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2553 }, 2554 clobbers: 8589934592, // FLAGS 2555 outputs: []regMask{ 2556 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2557 }, 2558 }, 2559 }, 2560 { 2561 name: "SQRTSD", 2562 argLen: 1, 2563 asm: x86.ASQRTSD, 2564 reg: regInfo{ 2565 inputs: []inputInfo{ 2566 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 2567 }, 2568 outputs: []regMask{ 2569 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 2570 }, 2571 }, 2572 }, 2573 { 2574 name: "SBBQcarrymask", 2575 argLen: 1, 2576 asm: x86.ASBBQ, 2577 reg: regInfo{ 2578 inputs: []inputInfo{ 2579 {0, 8589934592}, // FLAGS 2580 }, 2581 outputs: []regMask{ 2582 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2583 }, 2584 }, 2585 }, 2586 { 2587 name: "SBBLcarrymask", 2588 argLen: 1, 2589 asm: x86.ASBBL, 2590 reg: regInfo{ 2591 inputs: []inputInfo{ 2592 {0, 8589934592}, // FLAGS 2593 }, 2594 outputs: []regMask{ 2595 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2596 }, 2597 }, 2598 }, 2599 { 2600 name: "SETEQ", 2601 argLen: 1, 2602 asm: x86.ASETEQ, 2603 reg: regInfo{ 2604 inputs: []inputInfo{ 2605 {0, 8589934592}, // FLAGS 2606 }, 2607 outputs: []regMask{ 2608 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2609 }, 2610 }, 2611 }, 2612 { 2613 name: "SETNE", 2614 argLen: 1, 2615 asm: x86.ASETNE, 2616 reg: regInfo{ 2617 inputs: []inputInfo{ 2618 {0, 8589934592}, // FLAGS 2619 }, 2620 outputs: []regMask{ 2621 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2622 }, 2623 }, 2624 }, 2625 { 2626 name: "SETL", 2627 argLen: 1, 2628 asm: x86.ASETLT, 2629 reg: regInfo{ 2630 inputs: []inputInfo{ 2631 {0, 8589934592}, // FLAGS 2632 }, 2633 outputs: []regMask{ 2634 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2635 }, 2636 }, 2637 }, 2638 { 2639 name: "SETLE", 2640 argLen: 1, 2641 asm: x86.ASETLE, 2642 reg: regInfo{ 2643 inputs: []inputInfo{ 2644 {0, 8589934592}, // FLAGS 2645 }, 2646 outputs: []regMask{ 2647 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2648 }, 2649 }, 2650 }, 2651 { 2652 name: "SETG", 2653 argLen: 1, 2654 asm: x86.ASETGT, 2655 reg: regInfo{ 2656 inputs: []inputInfo{ 2657 {0, 8589934592}, // FLAGS 2658 }, 2659 outputs: []regMask{ 2660 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2661 }, 2662 }, 2663 }, 2664 { 2665 name: "SETGE", 2666 argLen: 1, 2667 asm: x86.ASETGE, 2668 reg: regInfo{ 2669 inputs: []inputInfo{ 2670 {0, 8589934592}, // FLAGS 2671 }, 2672 outputs: []regMask{ 2673 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2674 }, 2675 }, 2676 }, 2677 { 2678 name: "SETB", 2679 argLen: 1, 2680 asm: x86.ASETCS, 2681 reg: regInfo{ 2682 inputs: []inputInfo{ 2683 {0, 8589934592}, // FLAGS 2684 }, 2685 outputs: []regMask{ 2686 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2687 }, 2688 }, 2689 }, 2690 { 2691 name: "SETBE", 2692 argLen: 1, 2693 asm: x86.ASETLS, 2694 reg: regInfo{ 2695 inputs: []inputInfo{ 2696 {0, 8589934592}, // FLAGS 2697 }, 2698 outputs: []regMask{ 2699 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2700 }, 2701 }, 2702 }, 2703 { 2704 name: "SETA", 2705 argLen: 1, 2706 asm: x86.ASETHI, 2707 reg: regInfo{ 2708 inputs: []inputInfo{ 2709 {0, 8589934592}, // FLAGS 2710 }, 2711 outputs: []regMask{ 2712 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2713 }, 2714 }, 2715 }, 2716 { 2717 name: "SETAE", 2718 argLen: 1, 2719 asm: x86.ASETCC, 2720 reg: regInfo{ 2721 inputs: []inputInfo{ 2722 {0, 8589934592}, // FLAGS 2723 }, 2724 outputs: []regMask{ 2725 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2726 }, 2727 }, 2728 }, 2729 { 2730 name: "SETEQF", 2731 argLen: 1, 2732 asm: x86.ASETEQ, 2733 reg: regInfo{ 2734 inputs: []inputInfo{ 2735 {0, 8589934592}, // FLAGS 2736 }, 2737 clobbers: 8589934593, // AX FLAGS 2738 outputs: []regMask{ 2739 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2740 }, 2741 }, 2742 }, 2743 { 2744 name: "SETNEF", 2745 argLen: 1, 2746 asm: x86.ASETNE, 2747 reg: regInfo{ 2748 inputs: []inputInfo{ 2749 {0, 8589934592}, // FLAGS 2750 }, 2751 clobbers: 8589934593, // AX FLAGS 2752 outputs: []regMask{ 2753 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2754 }, 2755 }, 2756 }, 2757 { 2758 name: "SETORD", 2759 argLen: 1, 2760 asm: x86.ASETPC, 2761 reg: regInfo{ 2762 inputs: []inputInfo{ 2763 {0, 8589934592}, // FLAGS 2764 }, 2765 outputs: []regMask{ 2766 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2767 }, 2768 }, 2769 }, 2770 { 2771 name: "SETNAN", 2772 argLen: 1, 2773 asm: x86.ASETPS, 2774 reg: regInfo{ 2775 inputs: []inputInfo{ 2776 {0, 8589934592}, // FLAGS 2777 }, 2778 outputs: []regMask{ 2779 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2780 }, 2781 }, 2782 }, 2783 { 2784 name: "SETGF", 2785 argLen: 1, 2786 asm: x86.ASETHI, 2787 reg: regInfo{ 2788 inputs: []inputInfo{ 2789 {0, 8589934592}, // FLAGS 2790 }, 2791 outputs: []regMask{ 2792 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2793 }, 2794 }, 2795 }, 2796 { 2797 name: "SETGEF", 2798 argLen: 1, 2799 asm: x86.ASETCC, 2800 reg: regInfo{ 2801 inputs: []inputInfo{ 2802 {0, 8589934592}, // FLAGS 2803 }, 2804 outputs: []regMask{ 2805 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2806 }, 2807 }, 2808 }, 2809 { 2810 name: "MOVBQSX", 2811 argLen: 1, 2812 asm: x86.AMOVBQSX, 2813 reg: regInfo{ 2814 inputs: []inputInfo{ 2815 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2816 }, 2817 outputs: []regMask{ 2818 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2819 }, 2820 }, 2821 }, 2822 { 2823 name: "MOVBQZX", 2824 argLen: 1, 2825 asm: x86.AMOVBQZX, 2826 reg: regInfo{ 2827 inputs: []inputInfo{ 2828 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2829 }, 2830 outputs: []regMask{ 2831 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2832 }, 2833 }, 2834 }, 2835 { 2836 name: "MOVWQSX", 2837 argLen: 1, 2838 asm: x86.AMOVWQSX, 2839 reg: regInfo{ 2840 inputs: []inputInfo{ 2841 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2842 }, 2843 outputs: []regMask{ 2844 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2845 }, 2846 }, 2847 }, 2848 { 2849 name: "MOVWQZX", 2850 argLen: 1, 2851 asm: x86.AMOVWQZX, 2852 reg: regInfo{ 2853 inputs: []inputInfo{ 2854 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2855 }, 2856 outputs: []regMask{ 2857 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2858 }, 2859 }, 2860 }, 2861 { 2862 name: "MOVLQSX", 2863 argLen: 1, 2864 asm: x86.AMOVLQSX, 2865 reg: regInfo{ 2866 inputs: []inputInfo{ 2867 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2868 }, 2869 outputs: []regMask{ 2870 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2871 }, 2872 }, 2873 }, 2874 { 2875 name: "MOVLQZX", 2876 argLen: 1, 2877 asm: x86.AMOVLQZX, 2878 reg: regInfo{ 2879 inputs: []inputInfo{ 2880 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2881 }, 2882 outputs: []regMask{ 2883 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2884 }, 2885 }, 2886 }, 2887 { 2888 name: "MOVLconst", 2889 auxType: auxInt32, 2890 argLen: 0, 2891 rematerializeable: true, 2892 asm: x86.AMOVL, 2893 reg: regInfo{ 2894 outputs: []regMask{ 2895 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2896 }, 2897 }, 2898 }, 2899 { 2900 name: "MOVQconst", 2901 auxType: auxInt64, 2902 argLen: 0, 2903 rematerializeable: true, 2904 asm: x86.AMOVQ, 2905 reg: regInfo{ 2906 outputs: []regMask{ 2907 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2908 }, 2909 }, 2910 }, 2911 { 2912 name: "CVTTSD2SL", 2913 argLen: 1, 2914 asm: x86.ACVTTSD2SL, 2915 reg: regInfo{ 2916 inputs: []inputInfo{ 2917 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 2918 }, 2919 outputs: []regMask{ 2920 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2921 }, 2922 }, 2923 }, 2924 { 2925 name: "CVTTSD2SQ", 2926 argLen: 1, 2927 asm: x86.ACVTTSD2SQ, 2928 reg: regInfo{ 2929 inputs: []inputInfo{ 2930 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 2931 }, 2932 outputs: []regMask{ 2933 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2934 }, 2935 }, 2936 }, 2937 { 2938 name: "CVTTSS2SL", 2939 argLen: 1, 2940 asm: x86.ACVTTSS2SL, 2941 reg: regInfo{ 2942 inputs: []inputInfo{ 2943 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 2944 }, 2945 outputs: []regMask{ 2946 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2947 }, 2948 }, 2949 }, 2950 { 2951 name: "CVTTSS2SQ", 2952 argLen: 1, 2953 asm: x86.ACVTTSS2SQ, 2954 reg: regInfo{ 2955 inputs: []inputInfo{ 2956 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 2957 }, 2958 outputs: []regMask{ 2959 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2960 }, 2961 }, 2962 }, 2963 { 2964 name: "CVTSL2SS", 2965 argLen: 1, 2966 asm: x86.ACVTSL2SS, 2967 reg: regInfo{ 2968 inputs: []inputInfo{ 2969 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2970 }, 2971 outputs: []regMask{ 2972 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 2973 }, 2974 }, 2975 }, 2976 { 2977 name: "CVTSL2SD", 2978 argLen: 1, 2979 asm: x86.ACVTSL2SD, 2980 reg: regInfo{ 2981 inputs: []inputInfo{ 2982 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2983 }, 2984 outputs: []regMask{ 2985 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 2986 }, 2987 }, 2988 }, 2989 { 2990 name: "CVTSQ2SS", 2991 argLen: 1, 2992 asm: x86.ACVTSQ2SS, 2993 reg: regInfo{ 2994 inputs: []inputInfo{ 2995 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2996 }, 2997 outputs: []regMask{ 2998 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 2999 }, 3000 }, 3001 }, 3002 { 3003 name: "CVTSQ2SD", 3004 argLen: 1, 3005 asm: x86.ACVTSQ2SD, 3006 reg: regInfo{ 3007 inputs: []inputInfo{ 3008 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3009 }, 3010 outputs: []regMask{ 3011 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3012 }, 3013 }, 3014 }, 3015 { 3016 name: "CVTSD2SS", 3017 argLen: 1, 3018 asm: x86.ACVTSD2SS, 3019 reg: regInfo{ 3020 inputs: []inputInfo{ 3021 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3022 }, 3023 outputs: []regMask{ 3024 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3025 }, 3026 }, 3027 }, 3028 { 3029 name: "CVTSS2SD", 3030 argLen: 1, 3031 asm: x86.ACVTSS2SD, 3032 reg: regInfo{ 3033 inputs: []inputInfo{ 3034 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3035 }, 3036 outputs: []regMask{ 3037 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3038 }, 3039 }, 3040 }, 3041 { 3042 name: "PXOR", 3043 argLen: 2, 3044 commutative: true, 3045 resultInArg0: true, 3046 asm: x86.APXOR, 3047 reg: regInfo{ 3048 inputs: []inputInfo{ 3049 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3050 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3051 }, 3052 outputs: []regMask{ 3053 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3054 }, 3055 }, 3056 }, 3057 { 3058 name: "LEAQ", 3059 auxType: auxSymOff, 3060 argLen: 1, 3061 rematerializeable: true, 3062 reg: regInfo{ 3063 inputs: []inputInfo{ 3064 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3065 }, 3066 outputs: []regMask{ 3067 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3068 }, 3069 }, 3070 }, 3071 { 3072 name: "LEAQ1", 3073 auxType: auxSymOff, 3074 argLen: 2, 3075 reg: regInfo{ 3076 inputs: []inputInfo{ 3077 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3078 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3079 }, 3080 outputs: []regMask{ 3081 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3082 }, 3083 }, 3084 }, 3085 { 3086 name: "LEAQ2", 3087 auxType: auxSymOff, 3088 argLen: 2, 3089 reg: regInfo{ 3090 inputs: []inputInfo{ 3091 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3092 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3093 }, 3094 outputs: []regMask{ 3095 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3096 }, 3097 }, 3098 }, 3099 { 3100 name: "LEAQ4", 3101 auxType: auxSymOff, 3102 argLen: 2, 3103 reg: regInfo{ 3104 inputs: []inputInfo{ 3105 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3106 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3107 }, 3108 outputs: []regMask{ 3109 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3110 }, 3111 }, 3112 }, 3113 { 3114 name: "LEAQ8", 3115 auxType: auxSymOff, 3116 argLen: 2, 3117 reg: regInfo{ 3118 inputs: []inputInfo{ 3119 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3120 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3121 }, 3122 outputs: []regMask{ 3123 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3124 }, 3125 }, 3126 }, 3127 { 3128 name: "MOVBload", 3129 auxType: auxSymOff, 3130 argLen: 2, 3131 asm: x86.AMOVBLZX, 3132 reg: regInfo{ 3133 inputs: []inputInfo{ 3134 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3135 }, 3136 outputs: []regMask{ 3137 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3138 }, 3139 }, 3140 }, 3141 { 3142 name: "MOVBQSXload", 3143 auxType: auxSymOff, 3144 argLen: 2, 3145 asm: x86.AMOVBQSX, 3146 reg: regInfo{ 3147 inputs: []inputInfo{ 3148 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3149 }, 3150 outputs: []regMask{ 3151 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3152 }, 3153 }, 3154 }, 3155 { 3156 name: "MOVWload", 3157 auxType: auxSymOff, 3158 argLen: 2, 3159 asm: x86.AMOVWLZX, 3160 reg: regInfo{ 3161 inputs: []inputInfo{ 3162 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3163 }, 3164 outputs: []regMask{ 3165 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3166 }, 3167 }, 3168 }, 3169 { 3170 name: "MOVWQSXload", 3171 auxType: auxSymOff, 3172 argLen: 2, 3173 asm: x86.AMOVWQSX, 3174 reg: regInfo{ 3175 inputs: []inputInfo{ 3176 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3177 }, 3178 outputs: []regMask{ 3179 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3180 }, 3181 }, 3182 }, 3183 { 3184 name: "MOVLload", 3185 auxType: auxSymOff, 3186 argLen: 2, 3187 asm: x86.AMOVL, 3188 reg: regInfo{ 3189 inputs: []inputInfo{ 3190 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3191 }, 3192 outputs: []regMask{ 3193 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3194 }, 3195 }, 3196 }, 3197 { 3198 name: "MOVLQSXload", 3199 auxType: auxSymOff, 3200 argLen: 2, 3201 asm: x86.AMOVLQSX, 3202 reg: regInfo{ 3203 inputs: []inputInfo{ 3204 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3205 }, 3206 outputs: []regMask{ 3207 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3208 }, 3209 }, 3210 }, 3211 { 3212 name: "MOVQload", 3213 auxType: auxSymOff, 3214 argLen: 2, 3215 asm: x86.AMOVQ, 3216 reg: regInfo{ 3217 inputs: []inputInfo{ 3218 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3219 }, 3220 outputs: []regMask{ 3221 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3222 }, 3223 }, 3224 }, 3225 { 3226 name: "MOVBstore", 3227 auxType: auxSymOff, 3228 argLen: 3, 3229 asm: x86.AMOVB, 3230 reg: regInfo{ 3231 inputs: []inputInfo{ 3232 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3233 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3234 }, 3235 }, 3236 }, 3237 { 3238 name: "MOVWstore", 3239 auxType: auxSymOff, 3240 argLen: 3, 3241 asm: x86.AMOVW, 3242 reg: regInfo{ 3243 inputs: []inputInfo{ 3244 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3245 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3246 }, 3247 }, 3248 }, 3249 { 3250 name: "MOVLstore", 3251 auxType: auxSymOff, 3252 argLen: 3, 3253 asm: x86.AMOVL, 3254 reg: regInfo{ 3255 inputs: []inputInfo{ 3256 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3257 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3258 }, 3259 }, 3260 }, 3261 { 3262 name: "MOVQstore", 3263 auxType: auxSymOff, 3264 argLen: 3, 3265 asm: x86.AMOVQ, 3266 reg: regInfo{ 3267 inputs: []inputInfo{ 3268 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3269 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3270 }, 3271 }, 3272 }, 3273 { 3274 name: "MOVOload", 3275 auxType: auxSymOff, 3276 argLen: 2, 3277 asm: x86.AMOVUPS, 3278 reg: regInfo{ 3279 inputs: []inputInfo{ 3280 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3281 }, 3282 outputs: []regMask{ 3283 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3284 }, 3285 }, 3286 }, 3287 { 3288 name: "MOVOstore", 3289 auxType: auxSymOff, 3290 argLen: 3, 3291 asm: x86.AMOVUPS, 3292 reg: regInfo{ 3293 inputs: []inputInfo{ 3294 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3295 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3296 }, 3297 }, 3298 }, 3299 { 3300 name: "MOVBloadidx1", 3301 auxType: auxSymOff, 3302 argLen: 3, 3303 asm: x86.AMOVBLZX, 3304 reg: regInfo{ 3305 inputs: []inputInfo{ 3306 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3307 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3308 }, 3309 outputs: []regMask{ 3310 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3311 }, 3312 }, 3313 }, 3314 { 3315 name: "MOVWloadidx1", 3316 auxType: auxSymOff, 3317 argLen: 3, 3318 asm: x86.AMOVWLZX, 3319 reg: regInfo{ 3320 inputs: []inputInfo{ 3321 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3322 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3323 }, 3324 outputs: []regMask{ 3325 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3326 }, 3327 }, 3328 }, 3329 { 3330 name: "MOVWloadidx2", 3331 auxType: auxSymOff, 3332 argLen: 3, 3333 asm: x86.AMOVWLZX, 3334 reg: regInfo{ 3335 inputs: []inputInfo{ 3336 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3337 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3338 }, 3339 outputs: []regMask{ 3340 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3341 }, 3342 }, 3343 }, 3344 { 3345 name: "MOVLloadidx1", 3346 auxType: auxSymOff, 3347 argLen: 3, 3348 asm: x86.AMOVL, 3349 reg: regInfo{ 3350 inputs: []inputInfo{ 3351 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3352 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3353 }, 3354 outputs: []regMask{ 3355 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3356 }, 3357 }, 3358 }, 3359 { 3360 name: "MOVLloadidx4", 3361 auxType: auxSymOff, 3362 argLen: 3, 3363 asm: x86.AMOVL, 3364 reg: regInfo{ 3365 inputs: []inputInfo{ 3366 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3367 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3368 }, 3369 outputs: []regMask{ 3370 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3371 }, 3372 }, 3373 }, 3374 { 3375 name: "MOVQloadidx1", 3376 auxType: auxSymOff, 3377 argLen: 3, 3378 asm: x86.AMOVQ, 3379 reg: regInfo{ 3380 inputs: []inputInfo{ 3381 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3382 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3383 }, 3384 outputs: []regMask{ 3385 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3386 }, 3387 }, 3388 }, 3389 { 3390 name: "MOVQloadidx8", 3391 auxType: auxSymOff, 3392 argLen: 3, 3393 asm: x86.AMOVQ, 3394 reg: regInfo{ 3395 inputs: []inputInfo{ 3396 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3397 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3398 }, 3399 outputs: []regMask{ 3400 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3401 }, 3402 }, 3403 }, 3404 { 3405 name: "MOVBstoreidx1", 3406 auxType: auxSymOff, 3407 argLen: 4, 3408 asm: x86.AMOVB, 3409 reg: regInfo{ 3410 inputs: []inputInfo{ 3411 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3412 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3413 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3414 }, 3415 }, 3416 }, 3417 { 3418 name: "MOVWstoreidx1", 3419 auxType: auxSymOff, 3420 argLen: 4, 3421 asm: x86.AMOVW, 3422 reg: regInfo{ 3423 inputs: []inputInfo{ 3424 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3425 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3426 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3427 }, 3428 }, 3429 }, 3430 { 3431 name: "MOVWstoreidx2", 3432 auxType: auxSymOff, 3433 argLen: 4, 3434 asm: x86.AMOVW, 3435 reg: regInfo{ 3436 inputs: []inputInfo{ 3437 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3438 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3439 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3440 }, 3441 }, 3442 }, 3443 { 3444 name: "MOVLstoreidx1", 3445 auxType: auxSymOff, 3446 argLen: 4, 3447 asm: x86.AMOVL, 3448 reg: regInfo{ 3449 inputs: []inputInfo{ 3450 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3451 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3452 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3453 }, 3454 }, 3455 }, 3456 { 3457 name: "MOVLstoreidx4", 3458 auxType: auxSymOff, 3459 argLen: 4, 3460 asm: x86.AMOVL, 3461 reg: regInfo{ 3462 inputs: []inputInfo{ 3463 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3464 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3465 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3466 }, 3467 }, 3468 }, 3469 { 3470 name: "MOVQstoreidx1", 3471 auxType: auxSymOff, 3472 argLen: 4, 3473 asm: x86.AMOVQ, 3474 reg: regInfo{ 3475 inputs: []inputInfo{ 3476 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3477 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3478 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3479 }, 3480 }, 3481 }, 3482 { 3483 name: "MOVQstoreidx8", 3484 auxType: auxSymOff, 3485 argLen: 4, 3486 asm: x86.AMOVQ, 3487 reg: regInfo{ 3488 inputs: []inputInfo{ 3489 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3490 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3491 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3492 }, 3493 }, 3494 }, 3495 { 3496 name: "MOVBstoreconst", 3497 auxType: auxSymValAndOff, 3498 argLen: 2, 3499 asm: x86.AMOVB, 3500 reg: regInfo{ 3501 inputs: []inputInfo{ 3502 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3503 }, 3504 }, 3505 }, 3506 { 3507 name: "MOVWstoreconst", 3508 auxType: auxSymValAndOff, 3509 argLen: 2, 3510 asm: x86.AMOVW, 3511 reg: regInfo{ 3512 inputs: []inputInfo{ 3513 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3514 }, 3515 }, 3516 }, 3517 { 3518 name: "MOVLstoreconst", 3519 auxType: auxSymValAndOff, 3520 argLen: 2, 3521 asm: x86.AMOVL, 3522 reg: regInfo{ 3523 inputs: []inputInfo{ 3524 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3525 }, 3526 }, 3527 }, 3528 { 3529 name: "MOVQstoreconst", 3530 auxType: auxSymValAndOff, 3531 argLen: 2, 3532 asm: x86.AMOVQ, 3533 reg: regInfo{ 3534 inputs: []inputInfo{ 3535 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3536 }, 3537 }, 3538 }, 3539 { 3540 name: "MOVBstoreconstidx1", 3541 auxType: auxSymValAndOff, 3542 argLen: 3, 3543 asm: x86.AMOVB, 3544 reg: regInfo{ 3545 inputs: []inputInfo{ 3546 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3547 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3548 }, 3549 }, 3550 }, 3551 { 3552 name: "MOVWstoreconstidx1", 3553 auxType: auxSymValAndOff, 3554 argLen: 3, 3555 asm: x86.AMOVW, 3556 reg: regInfo{ 3557 inputs: []inputInfo{ 3558 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3559 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3560 }, 3561 }, 3562 }, 3563 { 3564 name: "MOVWstoreconstidx2", 3565 auxType: auxSymValAndOff, 3566 argLen: 3, 3567 asm: x86.AMOVW, 3568 reg: regInfo{ 3569 inputs: []inputInfo{ 3570 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3571 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3572 }, 3573 }, 3574 }, 3575 { 3576 name: "MOVLstoreconstidx1", 3577 auxType: auxSymValAndOff, 3578 argLen: 3, 3579 asm: x86.AMOVL, 3580 reg: regInfo{ 3581 inputs: []inputInfo{ 3582 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3583 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3584 }, 3585 }, 3586 }, 3587 { 3588 name: "MOVLstoreconstidx4", 3589 auxType: auxSymValAndOff, 3590 argLen: 3, 3591 asm: x86.AMOVL, 3592 reg: regInfo{ 3593 inputs: []inputInfo{ 3594 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3595 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3596 }, 3597 }, 3598 }, 3599 { 3600 name: "MOVQstoreconstidx1", 3601 auxType: auxSymValAndOff, 3602 argLen: 3, 3603 asm: x86.AMOVQ, 3604 reg: regInfo{ 3605 inputs: []inputInfo{ 3606 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3607 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3608 }, 3609 }, 3610 }, 3611 { 3612 name: "MOVQstoreconstidx8", 3613 auxType: auxSymValAndOff, 3614 argLen: 3, 3615 asm: x86.AMOVQ, 3616 reg: regInfo{ 3617 inputs: []inputInfo{ 3618 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3619 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3620 }, 3621 }, 3622 }, 3623 { 3624 name: "DUFFZERO", 3625 auxType: auxInt64, 3626 argLen: 3, 3627 reg: regInfo{ 3628 inputs: []inputInfo{ 3629 {0, 128}, // DI 3630 {1, 65536}, // X0 3631 }, 3632 clobbers: 8589934720, // DI FLAGS 3633 }, 3634 }, 3635 { 3636 name: "MOVOconst", 3637 auxType: auxInt128, 3638 argLen: 0, 3639 rematerializeable: true, 3640 reg: regInfo{ 3641 outputs: []regMask{ 3642 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3643 }, 3644 }, 3645 }, 3646 { 3647 name: "REPSTOSQ", 3648 argLen: 4, 3649 reg: regInfo{ 3650 inputs: []inputInfo{ 3651 {0, 128}, // DI 3652 {1, 2}, // CX 3653 {2, 1}, // AX 3654 }, 3655 clobbers: 130, // CX DI 3656 }, 3657 }, 3658 { 3659 name: "CALLstatic", 3660 auxType: auxSymOff, 3661 argLen: 1, 3662 reg: regInfo{ 3663 clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS 3664 }, 3665 }, 3666 { 3667 name: "CALLclosure", 3668 auxType: auxInt64, 3669 argLen: 3, 3670 reg: regInfo{ 3671 inputs: []inputInfo{ 3672 {1, 4}, // DX 3673 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3674 }, 3675 clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS 3676 }, 3677 }, 3678 { 3679 name: "CALLdefer", 3680 auxType: auxInt64, 3681 argLen: 1, 3682 reg: regInfo{ 3683 clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS 3684 }, 3685 }, 3686 { 3687 name: "CALLgo", 3688 auxType: auxInt64, 3689 argLen: 1, 3690 reg: regInfo{ 3691 clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS 3692 }, 3693 }, 3694 { 3695 name: "CALLinter", 3696 auxType: auxInt64, 3697 argLen: 2, 3698 reg: regInfo{ 3699 inputs: []inputInfo{ 3700 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3701 }, 3702 clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS 3703 }, 3704 }, 3705 { 3706 name: "DUFFCOPY", 3707 auxType: auxInt64, 3708 argLen: 3, 3709 reg: regInfo{ 3710 inputs: []inputInfo{ 3711 {0, 128}, // DI 3712 {1, 64}, // SI 3713 }, 3714 clobbers: 8590000320, // SI DI X0 FLAGS 3715 }, 3716 }, 3717 { 3718 name: "REPMOVSQ", 3719 argLen: 4, 3720 reg: regInfo{ 3721 inputs: []inputInfo{ 3722 {0, 128}, // DI 3723 {1, 64}, // SI 3724 {2, 2}, // CX 3725 }, 3726 clobbers: 194, // CX SI DI 3727 }, 3728 }, 3729 { 3730 name: "InvertFlags", 3731 argLen: 1, 3732 reg: regInfo{}, 3733 }, 3734 { 3735 name: "LoweredGetG", 3736 argLen: 1, 3737 reg: regInfo{ 3738 outputs: []regMask{ 3739 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3740 }, 3741 }, 3742 }, 3743 { 3744 name: "LoweredGetClosurePtr", 3745 argLen: 0, 3746 reg: regInfo{ 3747 outputs: []regMask{ 3748 4, // DX 3749 }, 3750 }, 3751 }, 3752 { 3753 name: "LoweredNilCheck", 3754 argLen: 2, 3755 reg: regInfo{ 3756 inputs: []inputInfo{ 3757 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3758 }, 3759 clobbers: 8589934592, // FLAGS 3760 }, 3761 }, 3762 { 3763 name: "MOVQconvert", 3764 argLen: 2, 3765 asm: x86.AMOVQ, 3766 reg: regInfo{ 3767 inputs: []inputInfo{ 3768 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3769 }, 3770 outputs: []regMask{ 3771 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3772 }, 3773 }, 3774 }, 3775 { 3776 name: "FlagEQ", 3777 argLen: 0, 3778 reg: regInfo{}, 3779 }, 3780 { 3781 name: "FlagLT_ULT", 3782 argLen: 0, 3783 reg: regInfo{}, 3784 }, 3785 { 3786 name: "FlagLT_UGT", 3787 argLen: 0, 3788 reg: regInfo{}, 3789 }, 3790 { 3791 name: "FlagGT_UGT", 3792 argLen: 0, 3793 reg: regInfo{}, 3794 }, 3795 { 3796 name: "FlagGT_ULT", 3797 argLen: 0, 3798 reg: regInfo{}, 3799 }, 3800 3801 { 3802 name: "ADD", 3803 argLen: 2, 3804 commutative: true, 3805 asm: arm.AADD, 3806 reg: regInfo{ 3807 inputs: []inputInfo{ 3808 {0, 31}, // R0 R1 R2 R3 SP 3809 {1, 31}, // R0 R1 R2 R3 SP 3810 }, 3811 outputs: []regMask{ 3812 31, // R0 R1 R2 R3 SP 3813 }, 3814 }, 3815 }, 3816 { 3817 name: "ADDconst", 3818 auxType: auxSymOff, 3819 argLen: 1, 3820 asm: arm.AADD, 3821 reg: regInfo{ 3822 inputs: []inputInfo{ 3823 {0, 31}, // R0 R1 R2 R3 SP 3824 }, 3825 outputs: []regMask{ 3826 31, // R0 R1 R2 R3 SP 3827 }, 3828 }, 3829 }, 3830 { 3831 name: "MOVWconst", 3832 auxType: auxInt32, 3833 argLen: 0, 3834 rematerializeable: true, 3835 asm: arm.AMOVW, 3836 reg: regInfo{ 3837 outputs: []regMask{ 3838 31, // R0 R1 R2 R3 SP 3839 }, 3840 }, 3841 }, 3842 { 3843 name: "CMP", 3844 argLen: 2, 3845 asm: arm.ACMP, 3846 reg: regInfo{ 3847 inputs: []inputInfo{ 3848 {0, 31}, // R0 R1 R2 R3 SP 3849 {1, 31}, // R0 R1 R2 R3 SP 3850 }, 3851 outputs: []regMask{ 3852 32, // FLAGS 3853 }, 3854 }, 3855 }, 3856 { 3857 name: "MOVWload", 3858 auxType: auxSymOff, 3859 argLen: 2, 3860 asm: arm.AMOVW, 3861 reg: regInfo{ 3862 inputs: []inputInfo{ 3863 {0, 31}, // R0 R1 R2 R3 SP 3864 }, 3865 outputs: []regMask{ 3866 31, // R0 R1 R2 R3 SP 3867 }, 3868 }, 3869 }, 3870 { 3871 name: "MOVWstore", 3872 auxType: auxSymOff, 3873 argLen: 3, 3874 asm: arm.AMOVW, 3875 reg: regInfo{ 3876 inputs: []inputInfo{ 3877 {0, 31}, // R0 R1 R2 R3 SP 3878 {1, 31}, // R0 R1 R2 R3 SP 3879 }, 3880 }, 3881 }, 3882 { 3883 name: "CALLstatic", 3884 auxType: auxSymOff, 3885 argLen: 1, 3886 reg: regInfo{ 3887 clobbers: 15, // R0 R1 R2 R3 3888 }, 3889 }, 3890 { 3891 name: "LessThan", 3892 argLen: 1, 3893 reg: regInfo{ 3894 inputs: []inputInfo{ 3895 {0, 32}, // FLAGS 3896 }, 3897 outputs: []regMask{ 3898 31, // R0 R1 R2 R3 SP 3899 }, 3900 }, 3901 }, 3902 3903 { 3904 name: "Add8", 3905 argLen: 2, 3906 commutative: true, 3907 generic: true, 3908 }, 3909 { 3910 name: "Add16", 3911 argLen: 2, 3912 commutative: true, 3913 generic: true, 3914 }, 3915 { 3916 name: "Add32", 3917 argLen: 2, 3918 commutative: true, 3919 generic: true, 3920 }, 3921 { 3922 name: "Add64", 3923 argLen: 2, 3924 commutative: true, 3925 generic: true, 3926 }, 3927 { 3928 name: "AddPtr", 3929 argLen: 2, 3930 generic: true, 3931 }, 3932 { 3933 name: "Add32F", 3934 argLen: 2, 3935 generic: true, 3936 }, 3937 { 3938 name: "Add64F", 3939 argLen: 2, 3940 generic: true, 3941 }, 3942 { 3943 name: "Sub8", 3944 argLen: 2, 3945 generic: true, 3946 }, 3947 { 3948 name: "Sub16", 3949 argLen: 2, 3950 generic: true, 3951 }, 3952 { 3953 name: "Sub32", 3954 argLen: 2, 3955 generic: true, 3956 }, 3957 { 3958 name: "Sub64", 3959 argLen: 2, 3960 generic: true, 3961 }, 3962 { 3963 name: "SubPtr", 3964 argLen: 2, 3965 generic: true, 3966 }, 3967 { 3968 name: "Sub32F", 3969 argLen: 2, 3970 generic: true, 3971 }, 3972 { 3973 name: "Sub64F", 3974 argLen: 2, 3975 generic: true, 3976 }, 3977 { 3978 name: "Mul8", 3979 argLen: 2, 3980 commutative: true, 3981 generic: true, 3982 }, 3983 { 3984 name: "Mul16", 3985 argLen: 2, 3986 commutative: true, 3987 generic: true, 3988 }, 3989 { 3990 name: "Mul32", 3991 argLen: 2, 3992 commutative: true, 3993 generic: true, 3994 }, 3995 { 3996 name: "Mul64", 3997 argLen: 2, 3998 commutative: true, 3999 generic: true, 4000 }, 4001 { 4002 name: "Mul32F", 4003 argLen: 2, 4004 generic: true, 4005 }, 4006 { 4007 name: "Mul64F", 4008 argLen: 2, 4009 generic: true, 4010 }, 4011 { 4012 name: "Div32F", 4013 argLen: 2, 4014 generic: true, 4015 }, 4016 { 4017 name: "Div64F", 4018 argLen: 2, 4019 generic: true, 4020 }, 4021 { 4022 name: "Hmul8", 4023 argLen: 2, 4024 generic: true, 4025 }, 4026 { 4027 name: "Hmul8u", 4028 argLen: 2, 4029 generic: true, 4030 }, 4031 { 4032 name: "Hmul16", 4033 argLen: 2, 4034 generic: true, 4035 }, 4036 { 4037 name: "Hmul16u", 4038 argLen: 2, 4039 generic: true, 4040 }, 4041 { 4042 name: "Hmul32", 4043 argLen: 2, 4044 generic: true, 4045 }, 4046 { 4047 name: "Hmul32u", 4048 argLen: 2, 4049 generic: true, 4050 }, 4051 { 4052 name: "Hmul64", 4053 argLen: 2, 4054 generic: true, 4055 }, 4056 { 4057 name: "Hmul64u", 4058 argLen: 2, 4059 generic: true, 4060 }, 4061 { 4062 name: "Avg64u", 4063 argLen: 2, 4064 generic: true, 4065 }, 4066 { 4067 name: "Div8", 4068 argLen: 2, 4069 generic: true, 4070 }, 4071 { 4072 name: "Div8u", 4073 argLen: 2, 4074 generic: true, 4075 }, 4076 { 4077 name: "Div16", 4078 argLen: 2, 4079 generic: true, 4080 }, 4081 { 4082 name: "Div16u", 4083 argLen: 2, 4084 generic: true, 4085 }, 4086 { 4087 name: "Div32", 4088 argLen: 2, 4089 generic: true, 4090 }, 4091 { 4092 name: "Div32u", 4093 argLen: 2, 4094 generic: true, 4095 }, 4096 { 4097 name: "Div64", 4098 argLen: 2, 4099 generic: true, 4100 }, 4101 { 4102 name: "Div64u", 4103 argLen: 2, 4104 generic: true, 4105 }, 4106 { 4107 name: "Mod8", 4108 argLen: 2, 4109 generic: true, 4110 }, 4111 { 4112 name: "Mod8u", 4113 argLen: 2, 4114 generic: true, 4115 }, 4116 { 4117 name: "Mod16", 4118 argLen: 2, 4119 generic: true, 4120 }, 4121 { 4122 name: "Mod16u", 4123 argLen: 2, 4124 generic: true, 4125 }, 4126 { 4127 name: "Mod32", 4128 argLen: 2, 4129 generic: true, 4130 }, 4131 { 4132 name: "Mod32u", 4133 argLen: 2, 4134 generic: true, 4135 }, 4136 { 4137 name: "Mod64", 4138 argLen: 2, 4139 generic: true, 4140 }, 4141 { 4142 name: "Mod64u", 4143 argLen: 2, 4144 generic: true, 4145 }, 4146 { 4147 name: "And8", 4148 argLen: 2, 4149 commutative: true, 4150 generic: true, 4151 }, 4152 { 4153 name: "And16", 4154 argLen: 2, 4155 commutative: true, 4156 generic: true, 4157 }, 4158 { 4159 name: "And32", 4160 argLen: 2, 4161 commutative: true, 4162 generic: true, 4163 }, 4164 { 4165 name: "And64", 4166 argLen: 2, 4167 commutative: true, 4168 generic: true, 4169 }, 4170 { 4171 name: "Or8", 4172 argLen: 2, 4173 commutative: true, 4174 generic: true, 4175 }, 4176 { 4177 name: "Or16", 4178 argLen: 2, 4179 commutative: true, 4180 generic: true, 4181 }, 4182 { 4183 name: "Or32", 4184 argLen: 2, 4185 commutative: true, 4186 generic: true, 4187 }, 4188 { 4189 name: "Or64", 4190 argLen: 2, 4191 commutative: true, 4192 generic: true, 4193 }, 4194 { 4195 name: "Xor8", 4196 argLen: 2, 4197 commutative: true, 4198 generic: true, 4199 }, 4200 { 4201 name: "Xor16", 4202 argLen: 2, 4203 commutative: true, 4204 generic: true, 4205 }, 4206 { 4207 name: "Xor32", 4208 argLen: 2, 4209 commutative: true, 4210 generic: true, 4211 }, 4212 { 4213 name: "Xor64", 4214 argLen: 2, 4215 commutative: true, 4216 generic: true, 4217 }, 4218 { 4219 name: "Lsh8x8", 4220 argLen: 2, 4221 generic: true, 4222 }, 4223 { 4224 name: "Lsh8x16", 4225 argLen: 2, 4226 generic: true, 4227 }, 4228 { 4229 name: "Lsh8x32", 4230 argLen: 2, 4231 generic: true, 4232 }, 4233 { 4234 name: "Lsh8x64", 4235 argLen: 2, 4236 generic: true, 4237 }, 4238 { 4239 name: "Lsh16x8", 4240 argLen: 2, 4241 generic: true, 4242 }, 4243 { 4244 name: "Lsh16x16", 4245 argLen: 2, 4246 generic: true, 4247 }, 4248 { 4249 name: "Lsh16x32", 4250 argLen: 2, 4251 generic: true, 4252 }, 4253 { 4254 name: "Lsh16x64", 4255 argLen: 2, 4256 generic: true, 4257 }, 4258 { 4259 name: "Lsh32x8", 4260 argLen: 2, 4261 generic: true, 4262 }, 4263 { 4264 name: "Lsh32x16", 4265 argLen: 2, 4266 generic: true, 4267 }, 4268 { 4269 name: "Lsh32x32", 4270 argLen: 2, 4271 generic: true, 4272 }, 4273 { 4274 name: "Lsh32x64", 4275 argLen: 2, 4276 generic: true, 4277 }, 4278 { 4279 name: "Lsh64x8", 4280 argLen: 2, 4281 generic: true, 4282 }, 4283 { 4284 name: "Lsh64x16", 4285 argLen: 2, 4286 generic: true, 4287 }, 4288 { 4289 name: "Lsh64x32", 4290 argLen: 2, 4291 generic: true, 4292 }, 4293 { 4294 name: "Lsh64x64", 4295 argLen: 2, 4296 generic: true, 4297 }, 4298 { 4299 name: "Rsh8x8", 4300 argLen: 2, 4301 generic: true, 4302 }, 4303 { 4304 name: "Rsh8x16", 4305 argLen: 2, 4306 generic: true, 4307 }, 4308 { 4309 name: "Rsh8x32", 4310 argLen: 2, 4311 generic: true, 4312 }, 4313 { 4314 name: "Rsh8x64", 4315 argLen: 2, 4316 generic: true, 4317 }, 4318 { 4319 name: "Rsh16x8", 4320 argLen: 2, 4321 generic: true, 4322 }, 4323 { 4324 name: "Rsh16x16", 4325 argLen: 2, 4326 generic: true, 4327 }, 4328 { 4329 name: "Rsh16x32", 4330 argLen: 2, 4331 generic: true, 4332 }, 4333 { 4334 name: "Rsh16x64", 4335 argLen: 2, 4336 generic: true, 4337 }, 4338 { 4339 name: "Rsh32x8", 4340 argLen: 2, 4341 generic: true, 4342 }, 4343 { 4344 name: "Rsh32x16", 4345 argLen: 2, 4346 generic: true, 4347 }, 4348 { 4349 name: "Rsh32x32", 4350 argLen: 2, 4351 generic: true, 4352 }, 4353 { 4354 name: "Rsh32x64", 4355 argLen: 2, 4356 generic: true, 4357 }, 4358 { 4359 name: "Rsh64x8", 4360 argLen: 2, 4361 generic: true, 4362 }, 4363 { 4364 name: "Rsh64x16", 4365 argLen: 2, 4366 generic: true, 4367 }, 4368 { 4369 name: "Rsh64x32", 4370 argLen: 2, 4371 generic: true, 4372 }, 4373 { 4374 name: "Rsh64x64", 4375 argLen: 2, 4376 generic: true, 4377 }, 4378 { 4379 name: "Rsh8Ux8", 4380 argLen: 2, 4381 generic: true, 4382 }, 4383 { 4384 name: "Rsh8Ux16", 4385 argLen: 2, 4386 generic: true, 4387 }, 4388 { 4389 name: "Rsh8Ux32", 4390 argLen: 2, 4391 generic: true, 4392 }, 4393 { 4394 name: "Rsh8Ux64", 4395 argLen: 2, 4396 generic: true, 4397 }, 4398 { 4399 name: "Rsh16Ux8", 4400 argLen: 2, 4401 generic: true, 4402 }, 4403 { 4404 name: "Rsh16Ux16", 4405 argLen: 2, 4406 generic: true, 4407 }, 4408 { 4409 name: "Rsh16Ux32", 4410 argLen: 2, 4411 generic: true, 4412 }, 4413 { 4414 name: "Rsh16Ux64", 4415 argLen: 2, 4416 generic: true, 4417 }, 4418 { 4419 name: "Rsh32Ux8", 4420 argLen: 2, 4421 generic: true, 4422 }, 4423 { 4424 name: "Rsh32Ux16", 4425 argLen: 2, 4426 generic: true, 4427 }, 4428 { 4429 name: "Rsh32Ux32", 4430 argLen: 2, 4431 generic: true, 4432 }, 4433 { 4434 name: "Rsh32Ux64", 4435 argLen: 2, 4436 generic: true, 4437 }, 4438 { 4439 name: "Rsh64Ux8", 4440 argLen: 2, 4441 generic: true, 4442 }, 4443 { 4444 name: "Rsh64Ux16", 4445 argLen: 2, 4446 generic: true, 4447 }, 4448 { 4449 name: "Rsh64Ux32", 4450 argLen: 2, 4451 generic: true, 4452 }, 4453 { 4454 name: "Rsh64Ux64", 4455 argLen: 2, 4456 generic: true, 4457 }, 4458 { 4459 name: "Lrot8", 4460 auxType: auxInt64, 4461 argLen: 1, 4462 generic: true, 4463 }, 4464 { 4465 name: "Lrot16", 4466 auxType: auxInt64, 4467 argLen: 1, 4468 generic: true, 4469 }, 4470 { 4471 name: "Lrot32", 4472 auxType: auxInt64, 4473 argLen: 1, 4474 generic: true, 4475 }, 4476 { 4477 name: "Lrot64", 4478 auxType: auxInt64, 4479 argLen: 1, 4480 generic: true, 4481 }, 4482 { 4483 name: "Eq8", 4484 argLen: 2, 4485 commutative: true, 4486 generic: true, 4487 }, 4488 { 4489 name: "Eq16", 4490 argLen: 2, 4491 commutative: true, 4492 generic: true, 4493 }, 4494 { 4495 name: "Eq32", 4496 argLen: 2, 4497 commutative: true, 4498 generic: true, 4499 }, 4500 { 4501 name: "Eq64", 4502 argLen: 2, 4503 commutative: true, 4504 generic: true, 4505 }, 4506 { 4507 name: "EqPtr", 4508 argLen: 2, 4509 commutative: true, 4510 generic: true, 4511 }, 4512 { 4513 name: "EqInter", 4514 argLen: 2, 4515 generic: true, 4516 }, 4517 { 4518 name: "EqSlice", 4519 argLen: 2, 4520 generic: true, 4521 }, 4522 { 4523 name: "Eq32F", 4524 argLen: 2, 4525 generic: true, 4526 }, 4527 { 4528 name: "Eq64F", 4529 argLen: 2, 4530 generic: true, 4531 }, 4532 { 4533 name: "Neq8", 4534 argLen: 2, 4535 commutative: true, 4536 generic: true, 4537 }, 4538 { 4539 name: "Neq16", 4540 argLen: 2, 4541 commutative: true, 4542 generic: true, 4543 }, 4544 { 4545 name: "Neq32", 4546 argLen: 2, 4547 commutative: true, 4548 generic: true, 4549 }, 4550 { 4551 name: "Neq64", 4552 argLen: 2, 4553 commutative: true, 4554 generic: true, 4555 }, 4556 { 4557 name: "NeqPtr", 4558 argLen: 2, 4559 commutative: true, 4560 generic: true, 4561 }, 4562 { 4563 name: "NeqInter", 4564 argLen: 2, 4565 generic: true, 4566 }, 4567 { 4568 name: "NeqSlice", 4569 argLen: 2, 4570 generic: true, 4571 }, 4572 { 4573 name: "Neq32F", 4574 argLen: 2, 4575 generic: true, 4576 }, 4577 { 4578 name: "Neq64F", 4579 argLen: 2, 4580 generic: true, 4581 }, 4582 { 4583 name: "Less8", 4584 argLen: 2, 4585 generic: true, 4586 }, 4587 { 4588 name: "Less8U", 4589 argLen: 2, 4590 generic: true, 4591 }, 4592 { 4593 name: "Less16", 4594 argLen: 2, 4595 generic: true, 4596 }, 4597 { 4598 name: "Less16U", 4599 argLen: 2, 4600 generic: true, 4601 }, 4602 { 4603 name: "Less32", 4604 argLen: 2, 4605 generic: true, 4606 }, 4607 { 4608 name: "Less32U", 4609 argLen: 2, 4610 generic: true, 4611 }, 4612 { 4613 name: "Less64", 4614 argLen: 2, 4615 generic: true, 4616 }, 4617 { 4618 name: "Less64U", 4619 argLen: 2, 4620 generic: true, 4621 }, 4622 { 4623 name: "Less32F", 4624 argLen: 2, 4625 generic: true, 4626 }, 4627 { 4628 name: "Less64F", 4629 argLen: 2, 4630 generic: true, 4631 }, 4632 { 4633 name: "Leq8", 4634 argLen: 2, 4635 generic: true, 4636 }, 4637 { 4638 name: "Leq8U", 4639 argLen: 2, 4640 generic: true, 4641 }, 4642 { 4643 name: "Leq16", 4644 argLen: 2, 4645 generic: true, 4646 }, 4647 { 4648 name: "Leq16U", 4649 argLen: 2, 4650 generic: true, 4651 }, 4652 { 4653 name: "Leq32", 4654 argLen: 2, 4655 generic: true, 4656 }, 4657 { 4658 name: "Leq32U", 4659 argLen: 2, 4660 generic: true, 4661 }, 4662 { 4663 name: "Leq64", 4664 argLen: 2, 4665 generic: true, 4666 }, 4667 { 4668 name: "Leq64U", 4669 argLen: 2, 4670 generic: true, 4671 }, 4672 { 4673 name: "Leq32F", 4674 argLen: 2, 4675 generic: true, 4676 }, 4677 { 4678 name: "Leq64F", 4679 argLen: 2, 4680 generic: true, 4681 }, 4682 { 4683 name: "Greater8", 4684 argLen: 2, 4685 generic: true, 4686 }, 4687 { 4688 name: "Greater8U", 4689 argLen: 2, 4690 generic: true, 4691 }, 4692 { 4693 name: "Greater16", 4694 argLen: 2, 4695 generic: true, 4696 }, 4697 { 4698 name: "Greater16U", 4699 argLen: 2, 4700 generic: true, 4701 }, 4702 { 4703 name: "Greater32", 4704 argLen: 2, 4705 generic: true, 4706 }, 4707 { 4708 name: "Greater32U", 4709 argLen: 2, 4710 generic: true, 4711 }, 4712 { 4713 name: "Greater64", 4714 argLen: 2, 4715 generic: true, 4716 }, 4717 { 4718 name: "Greater64U", 4719 argLen: 2, 4720 generic: true, 4721 }, 4722 { 4723 name: "Greater32F", 4724 argLen: 2, 4725 generic: true, 4726 }, 4727 { 4728 name: "Greater64F", 4729 argLen: 2, 4730 generic: true, 4731 }, 4732 { 4733 name: "Geq8", 4734 argLen: 2, 4735 generic: true, 4736 }, 4737 { 4738 name: "Geq8U", 4739 argLen: 2, 4740 generic: true, 4741 }, 4742 { 4743 name: "Geq16", 4744 argLen: 2, 4745 generic: true, 4746 }, 4747 { 4748 name: "Geq16U", 4749 argLen: 2, 4750 generic: true, 4751 }, 4752 { 4753 name: "Geq32", 4754 argLen: 2, 4755 generic: true, 4756 }, 4757 { 4758 name: "Geq32U", 4759 argLen: 2, 4760 generic: true, 4761 }, 4762 { 4763 name: "Geq64", 4764 argLen: 2, 4765 generic: true, 4766 }, 4767 { 4768 name: "Geq64U", 4769 argLen: 2, 4770 generic: true, 4771 }, 4772 { 4773 name: "Geq32F", 4774 argLen: 2, 4775 generic: true, 4776 }, 4777 { 4778 name: "Geq64F", 4779 argLen: 2, 4780 generic: true, 4781 }, 4782 { 4783 name: "AndB", 4784 argLen: 2, 4785 generic: true, 4786 }, 4787 { 4788 name: "OrB", 4789 argLen: 2, 4790 generic: true, 4791 }, 4792 { 4793 name: "EqB", 4794 argLen: 2, 4795 generic: true, 4796 }, 4797 { 4798 name: "NeqB", 4799 argLen: 2, 4800 generic: true, 4801 }, 4802 { 4803 name: "Not", 4804 argLen: 1, 4805 generic: true, 4806 }, 4807 { 4808 name: "Neg8", 4809 argLen: 1, 4810 generic: true, 4811 }, 4812 { 4813 name: "Neg16", 4814 argLen: 1, 4815 generic: true, 4816 }, 4817 { 4818 name: "Neg32", 4819 argLen: 1, 4820 generic: true, 4821 }, 4822 { 4823 name: "Neg64", 4824 argLen: 1, 4825 generic: true, 4826 }, 4827 { 4828 name: "Neg32F", 4829 argLen: 1, 4830 generic: true, 4831 }, 4832 { 4833 name: "Neg64F", 4834 argLen: 1, 4835 generic: true, 4836 }, 4837 { 4838 name: "Com8", 4839 argLen: 1, 4840 generic: true, 4841 }, 4842 { 4843 name: "Com16", 4844 argLen: 1, 4845 generic: true, 4846 }, 4847 { 4848 name: "Com32", 4849 argLen: 1, 4850 generic: true, 4851 }, 4852 { 4853 name: "Com64", 4854 argLen: 1, 4855 generic: true, 4856 }, 4857 { 4858 name: "Ctz16", 4859 argLen: 1, 4860 generic: true, 4861 }, 4862 { 4863 name: "Ctz32", 4864 argLen: 1, 4865 generic: true, 4866 }, 4867 { 4868 name: "Ctz64", 4869 argLen: 1, 4870 generic: true, 4871 }, 4872 { 4873 name: "Clz16", 4874 argLen: 1, 4875 generic: true, 4876 }, 4877 { 4878 name: "Clz32", 4879 argLen: 1, 4880 generic: true, 4881 }, 4882 { 4883 name: "Clz64", 4884 argLen: 1, 4885 generic: true, 4886 }, 4887 { 4888 name: "Bswap32", 4889 argLen: 1, 4890 generic: true, 4891 }, 4892 { 4893 name: "Bswap64", 4894 argLen: 1, 4895 generic: true, 4896 }, 4897 { 4898 name: "Sqrt", 4899 argLen: 1, 4900 generic: true, 4901 }, 4902 { 4903 name: "Phi", 4904 argLen: -1, 4905 generic: true, 4906 }, 4907 { 4908 name: "Copy", 4909 argLen: 1, 4910 generic: true, 4911 }, 4912 { 4913 name: "Convert", 4914 argLen: 2, 4915 generic: true, 4916 }, 4917 { 4918 name: "ConstBool", 4919 auxType: auxBool, 4920 argLen: 0, 4921 generic: true, 4922 }, 4923 { 4924 name: "ConstString", 4925 auxType: auxString, 4926 argLen: 0, 4927 generic: true, 4928 }, 4929 { 4930 name: "ConstNil", 4931 argLen: 0, 4932 generic: true, 4933 }, 4934 { 4935 name: "Const8", 4936 auxType: auxInt8, 4937 argLen: 0, 4938 generic: true, 4939 }, 4940 { 4941 name: "Const16", 4942 auxType: auxInt16, 4943 argLen: 0, 4944 generic: true, 4945 }, 4946 { 4947 name: "Const32", 4948 auxType: auxInt32, 4949 argLen: 0, 4950 generic: true, 4951 }, 4952 { 4953 name: "Const64", 4954 auxType: auxInt64, 4955 argLen: 0, 4956 generic: true, 4957 }, 4958 { 4959 name: "Const32F", 4960 auxType: auxFloat32, 4961 argLen: 0, 4962 generic: true, 4963 }, 4964 { 4965 name: "Const64F", 4966 auxType: auxFloat64, 4967 argLen: 0, 4968 generic: true, 4969 }, 4970 { 4971 name: "ConstInterface", 4972 argLen: 0, 4973 generic: true, 4974 }, 4975 { 4976 name: "ConstSlice", 4977 argLen: 0, 4978 generic: true, 4979 }, 4980 { 4981 name: "InitMem", 4982 argLen: 0, 4983 generic: true, 4984 }, 4985 { 4986 name: "Arg", 4987 auxType: auxSymOff, 4988 argLen: 0, 4989 generic: true, 4990 }, 4991 { 4992 name: "Addr", 4993 auxType: auxSym, 4994 argLen: 1, 4995 generic: true, 4996 }, 4997 { 4998 name: "SP", 4999 argLen: 0, 5000 generic: true, 5001 }, 5002 { 5003 name: "SB", 5004 argLen: 0, 5005 generic: true, 5006 }, 5007 { 5008 name: "Func", 5009 auxType: auxSym, 5010 argLen: 0, 5011 generic: true, 5012 }, 5013 { 5014 name: "Load", 5015 argLen: 2, 5016 generic: true, 5017 }, 5018 { 5019 name: "Store", 5020 auxType: auxInt64, 5021 argLen: 3, 5022 generic: true, 5023 }, 5024 { 5025 name: "Move", 5026 auxType: auxInt64, 5027 argLen: 3, 5028 generic: true, 5029 }, 5030 { 5031 name: "Zero", 5032 auxType: auxInt64, 5033 argLen: 2, 5034 generic: true, 5035 }, 5036 { 5037 name: "ClosureCall", 5038 auxType: auxInt64, 5039 argLen: 3, 5040 generic: true, 5041 }, 5042 { 5043 name: "StaticCall", 5044 auxType: auxSymOff, 5045 argLen: 1, 5046 generic: true, 5047 }, 5048 { 5049 name: "DeferCall", 5050 auxType: auxInt64, 5051 argLen: 1, 5052 generic: true, 5053 }, 5054 { 5055 name: "GoCall", 5056 auxType: auxInt64, 5057 argLen: 1, 5058 generic: true, 5059 }, 5060 { 5061 name: "InterCall", 5062 auxType: auxInt64, 5063 argLen: 2, 5064 generic: true, 5065 }, 5066 { 5067 name: "SignExt8to16", 5068 argLen: 1, 5069 generic: true, 5070 }, 5071 { 5072 name: "SignExt8to32", 5073 argLen: 1, 5074 generic: true, 5075 }, 5076 { 5077 name: "SignExt8to64", 5078 argLen: 1, 5079 generic: true, 5080 }, 5081 { 5082 name: "SignExt16to32", 5083 argLen: 1, 5084 generic: true, 5085 }, 5086 { 5087 name: "SignExt16to64", 5088 argLen: 1, 5089 generic: true, 5090 }, 5091 { 5092 name: "SignExt32to64", 5093 argLen: 1, 5094 generic: true, 5095 }, 5096 { 5097 name: "ZeroExt8to16", 5098 argLen: 1, 5099 generic: true, 5100 }, 5101 { 5102 name: "ZeroExt8to32", 5103 argLen: 1, 5104 generic: true, 5105 }, 5106 { 5107 name: "ZeroExt8to64", 5108 argLen: 1, 5109 generic: true, 5110 }, 5111 { 5112 name: "ZeroExt16to32", 5113 argLen: 1, 5114 generic: true, 5115 }, 5116 { 5117 name: "ZeroExt16to64", 5118 argLen: 1, 5119 generic: true, 5120 }, 5121 { 5122 name: "ZeroExt32to64", 5123 argLen: 1, 5124 generic: true, 5125 }, 5126 { 5127 name: "Trunc16to8", 5128 argLen: 1, 5129 generic: true, 5130 }, 5131 { 5132 name: "Trunc32to8", 5133 argLen: 1, 5134 generic: true, 5135 }, 5136 { 5137 name: "Trunc32to16", 5138 argLen: 1, 5139 generic: true, 5140 }, 5141 { 5142 name: "Trunc64to8", 5143 argLen: 1, 5144 generic: true, 5145 }, 5146 { 5147 name: "Trunc64to16", 5148 argLen: 1, 5149 generic: true, 5150 }, 5151 { 5152 name: "Trunc64to32", 5153 argLen: 1, 5154 generic: true, 5155 }, 5156 { 5157 name: "Cvt32to32F", 5158 argLen: 1, 5159 generic: true, 5160 }, 5161 { 5162 name: "Cvt32to64F", 5163 argLen: 1, 5164 generic: true, 5165 }, 5166 { 5167 name: "Cvt64to32F", 5168 argLen: 1, 5169 generic: true, 5170 }, 5171 { 5172 name: "Cvt64to64F", 5173 argLen: 1, 5174 generic: true, 5175 }, 5176 { 5177 name: "Cvt32Fto32", 5178 argLen: 1, 5179 generic: true, 5180 }, 5181 { 5182 name: "Cvt32Fto64", 5183 argLen: 1, 5184 generic: true, 5185 }, 5186 { 5187 name: "Cvt64Fto32", 5188 argLen: 1, 5189 generic: true, 5190 }, 5191 { 5192 name: "Cvt64Fto64", 5193 argLen: 1, 5194 generic: true, 5195 }, 5196 { 5197 name: "Cvt32Fto64F", 5198 argLen: 1, 5199 generic: true, 5200 }, 5201 { 5202 name: "Cvt64Fto32F", 5203 argLen: 1, 5204 generic: true, 5205 }, 5206 { 5207 name: "IsNonNil", 5208 argLen: 1, 5209 generic: true, 5210 }, 5211 { 5212 name: "IsInBounds", 5213 argLen: 2, 5214 generic: true, 5215 }, 5216 { 5217 name: "IsSliceInBounds", 5218 argLen: 2, 5219 generic: true, 5220 }, 5221 { 5222 name: "NilCheck", 5223 argLen: 2, 5224 generic: true, 5225 }, 5226 { 5227 name: "GetG", 5228 argLen: 1, 5229 generic: true, 5230 }, 5231 { 5232 name: "GetClosurePtr", 5233 argLen: 0, 5234 generic: true, 5235 }, 5236 { 5237 name: "ArrayIndex", 5238 auxType: auxInt64, 5239 argLen: 1, 5240 generic: true, 5241 }, 5242 { 5243 name: "PtrIndex", 5244 argLen: 2, 5245 generic: true, 5246 }, 5247 { 5248 name: "OffPtr", 5249 auxType: auxInt64, 5250 argLen: 1, 5251 generic: true, 5252 }, 5253 { 5254 name: "SliceMake", 5255 argLen: 3, 5256 generic: true, 5257 }, 5258 { 5259 name: "SlicePtr", 5260 argLen: 1, 5261 generic: true, 5262 }, 5263 { 5264 name: "SliceLen", 5265 argLen: 1, 5266 generic: true, 5267 }, 5268 { 5269 name: "SliceCap", 5270 argLen: 1, 5271 generic: true, 5272 }, 5273 { 5274 name: "ComplexMake", 5275 argLen: 2, 5276 generic: true, 5277 }, 5278 { 5279 name: "ComplexReal", 5280 argLen: 1, 5281 generic: true, 5282 }, 5283 { 5284 name: "ComplexImag", 5285 argLen: 1, 5286 generic: true, 5287 }, 5288 { 5289 name: "StringMake", 5290 argLen: 2, 5291 generic: true, 5292 }, 5293 { 5294 name: "StringPtr", 5295 argLen: 1, 5296 generic: true, 5297 }, 5298 { 5299 name: "StringLen", 5300 argLen: 1, 5301 generic: true, 5302 }, 5303 { 5304 name: "IMake", 5305 argLen: 2, 5306 generic: true, 5307 }, 5308 { 5309 name: "ITab", 5310 argLen: 1, 5311 generic: true, 5312 }, 5313 { 5314 name: "IData", 5315 argLen: 1, 5316 generic: true, 5317 }, 5318 { 5319 name: "StructMake0", 5320 argLen: 0, 5321 generic: true, 5322 }, 5323 { 5324 name: "StructMake1", 5325 argLen: 1, 5326 generic: true, 5327 }, 5328 { 5329 name: "StructMake2", 5330 argLen: 2, 5331 generic: true, 5332 }, 5333 { 5334 name: "StructMake3", 5335 argLen: 3, 5336 generic: true, 5337 }, 5338 { 5339 name: "StructMake4", 5340 argLen: 4, 5341 generic: true, 5342 }, 5343 { 5344 name: "StructSelect", 5345 auxType: auxInt64, 5346 argLen: 1, 5347 generic: true, 5348 }, 5349 { 5350 name: "StoreReg", 5351 argLen: 1, 5352 generic: true, 5353 }, 5354 { 5355 name: "LoadReg", 5356 argLen: 1, 5357 generic: true, 5358 }, 5359 { 5360 name: "FwdRef", 5361 auxType: auxSym, 5362 argLen: 0, 5363 generic: true, 5364 }, 5365 { 5366 name: "Unknown", 5367 argLen: 0, 5368 generic: true, 5369 }, 5370 { 5371 name: "VarDef", 5372 auxType: auxSym, 5373 argLen: 1, 5374 generic: true, 5375 }, 5376 { 5377 name: "VarKill", 5378 auxType: auxSym, 5379 argLen: 1, 5380 generic: true, 5381 }, 5382 { 5383 name: "VarLive", 5384 auxType: auxSym, 5385 argLen: 1, 5386 generic: true, 5387 }, 5388 { 5389 name: "KeepAlive", 5390 argLen: 2, 5391 generic: true, 5392 }, 5393 } 5394 5395 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 5396 func (o Op) String() string { return opcodeTable[o].name } 5397 5398 var registersAMD64 = [...]Register{ 5399 {0, "AX"}, 5400 {1, "CX"}, 5401 {2, "DX"}, 5402 {3, "BX"}, 5403 {4, "SP"}, 5404 {5, "BP"}, 5405 {6, "SI"}, 5406 {7, "DI"}, 5407 {8, "R8"}, 5408 {9, "R9"}, 5409 {10, "R10"}, 5410 {11, "R11"}, 5411 {12, "R12"}, 5412 {13, "R13"}, 5413 {14, "R14"}, 5414 {15, "R15"}, 5415 {16, "X0"}, 5416 {17, "X1"}, 5417 {18, "X2"}, 5418 {19, "X3"}, 5419 {20, "X4"}, 5420 {21, "X5"}, 5421 {22, "X6"}, 5422 {23, "X7"}, 5423 {24, "X8"}, 5424 {25, "X9"}, 5425 {26, "X10"}, 5426 {27, "X11"}, 5427 {28, "X12"}, 5428 {29, "X13"}, 5429 {30, "X14"}, 5430 {31, "X15"}, 5431 {32, "SB"}, 5432 {33, "FLAGS"}, 5433 } 5434 var registersARM = [...]Register{ 5435 {0, "R0"}, 5436 {1, "R1"}, 5437 {2, "R2"}, 5438 {3, "R3"}, 5439 {4, "SP"}, 5440 {5, "FLAGS"}, 5441 {6, "SB"}, 5442 }