github.com/miolini/go@v0.0.0-20160405192216-fca68c8cb408/src/cmd/compile/internal/ssa/opGen.go (about) 1 // autogenerated: do not edit! 2 // generated from gen/*Ops.go 3 4 package ssa 5 6 import ( 7 "cmd/internal/obj" 8 "cmd/internal/obj/arm" 9 "cmd/internal/obj/x86" 10 ) 11 12 const ( 13 BlockInvalid BlockKind = iota 14 15 BlockAMD64EQ 16 BlockAMD64NE 17 BlockAMD64LT 18 BlockAMD64LE 19 BlockAMD64GT 20 BlockAMD64GE 21 BlockAMD64ULT 22 BlockAMD64ULE 23 BlockAMD64UGT 24 BlockAMD64UGE 25 BlockAMD64EQF 26 BlockAMD64NEF 27 BlockAMD64ORD 28 BlockAMD64NAN 29 30 BlockARMEQ 31 BlockARMNE 32 BlockARMLT 33 BlockARMLE 34 BlockARMGT 35 BlockARMGE 36 BlockARMULT 37 BlockARMULE 38 BlockARMUGT 39 BlockARMUGE 40 41 BlockPlain 42 BlockIf 43 BlockCall 44 BlockDefer 45 BlockCheck 46 BlockRet 47 BlockRetJmp 48 BlockExit 49 BlockFirst 50 BlockDead 51 ) 52 53 var blockString = [...]string{ 54 BlockInvalid: "BlockInvalid", 55 56 BlockAMD64EQ: "EQ", 57 BlockAMD64NE: "NE", 58 BlockAMD64LT: "LT", 59 BlockAMD64LE: "LE", 60 BlockAMD64GT: "GT", 61 BlockAMD64GE: "GE", 62 BlockAMD64ULT: "ULT", 63 BlockAMD64ULE: "ULE", 64 BlockAMD64UGT: "UGT", 65 BlockAMD64UGE: "UGE", 66 BlockAMD64EQF: "EQF", 67 BlockAMD64NEF: "NEF", 68 BlockAMD64ORD: "ORD", 69 BlockAMD64NAN: "NAN", 70 71 BlockARMEQ: "EQ", 72 BlockARMNE: "NE", 73 BlockARMLT: "LT", 74 BlockARMLE: "LE", 75 BlockARMGT: "GT", 76 BlockARMGE: "GE", 77 BlockARMULT: "ULT", 78 BlockARMULE: "ULE", 79 BlockARMUGT: "UGT", 80 BlockARMUGE: "UGE", 81 82 BlockPlain: "Plain", 83 BlockIf: "If", 84 BlockCall: "Call", 85 BlockDefer: "Defer", 86 BlockCheck: "Check", 87 BlockRet: "Ret", 88 BlockRetJmp: "RetJmp", 89 BlockExit: "Exit", 90 BlockFirst: "First", 91 BlockDead: "Dead", 92 } 93 94 func (k BlockKind) String() string { return blockString[k] } 95 96 const ( 97 OpInvalid Op = iota 98 99 OpAMD64ADDSS 100 OpAMD64ADDSD 101 OpAMD64SUBSS 102 OpAMD64SUBSD 103 OpAMD64MULSS 104 OpAMD64MULSD 105 OpAMD64DIVSS 106 OpAMD64DIVSD 107 OpAMD64MOVSSload 108 OpAMD64MOVSDload 109 OpAMD64MOVSSconst 110 OpAMD64MOVSDconst 111 OpAMD64MOVSSloadidx1 112 OpAMD64MOVSSloadidx4 113 OpAMD64MOVSDloadidx1 114 OpAMD64MOVSDloadidx8 115 OpAMD64MOVSSstore 116 OpAMD64MOVSDstore 117 OpAMD64MOVSSstoreidx1 118 OpAMD64MOVSSstoreidx4 119 OpAMD64MOVSDstoreidx1 120 OpAMD64MOVSDstoreidx8 121 OpAMD64ADDQ 122 OpAMD64ADDL 123 OpAMD64ADDW 124 OpAMD64ADDB 125 OpAMD64ADDQconst 126 OpAMD64ADDLconst 127 OpAMD64ADDWconst 128 OpAMD64ADDBconst 129 OpAMD64SUBQ 130 OpAMD64SUBL 131 OpAMD64SUBW 132 OpAMD64SUBB 133 OpAMD64SUBQconst 134 OpAMD64SUBLconst 135 OpAMD64SUBWconst 136 OpAMD64SUBBconst 137 OpAMD64MULQ 138 OpAMD64MULL 139 OpAMD64MULW 140 OpAMD64MULB 141 OpAMD64MULQconst 142 OpAMD64MULLconst 143 OpAMD64MULWconst 144 OpAMD64MULBconst 145 OpAMD64HMULQ 146 OpAMD64HMULL 147 OpAMD64HMULW 148 OpAMD64HMULB 149 OpAMD64HMULQU 150 OpAMD64HMULLU 151 OpAMD64HMULWU 152 OpAMD64HMULBU 153 OpAMD64AVGQU 154 OpAMD64DIVQ 155 OpAMD64DIVL 156 OpAMD64DIVW 157 OpAMD64DIVQU 158 OpAMD64DIVLU 159 OpAMD64DIVWU 160 OpAMD64MODQ 161 OpAMD64MODL 162 OpAMD64MODW 163 OpAMD64MODQU 164 OpAMD64MODLU 165 OpAMD64MODWU 166 OpAMD64ANDQ 167 OpAMD64ANDL 168 OpAMD64ANDW 169 OpAMD64ANDB 170 OpAMD64ANDQconst 171 OpAMD64ANDLconst 172 OpAMD64ANDWconst 173 OpAMD64ANDBconst 174 OpAMD64ORQ 175 OpAMD64ORL 176 OpAMD64ORW 177 OpAMD64ORB 178 OpAMD64ORQconst 179 OpAMD64ORLconst 180 OpAMD64ORWconst 181 OpAMD64ORBconst 182 OpAMD64XORQ 183 OpAMD64XORL 184 OpAMD64XORW 185 OpAMD64XORB 186 OpAMD64XORQconst 187 OpAMD64XORLconst 188 OpAMD64XORWconst 189 OpAMD64XORBconst 190 OpAMD64CMPQ 191 OpAMD64CMPL 192 OpAMD64CMPW 193 OpAMD64CMPB 194 OpAMD64CMPQconst 195 OpAMD64CMPLconst 196 OpAMD64CMPWconst 197 OpAMD64CMPBconst 198 OpAMD64UCOMISS 199 OpAMD64UCOMISD 200 OpAMD64TESTQ 201 OpAMD64TESTL 202 OpAMD64TESTW 203 OpAMD64TESTB 204 OpAMD64TESTQconst 205 OpAMD64TESTLconst 206 OpAMD64TESTWconst 207 OpAMD64TESTBconst 208 OpAMD64SHLQ 209 OpAMD64SHLL 210 OpAMD64SHLW 211 OpAMD64SHLB 212 OpAMD64SHLQconst 213 OpAMD64SHLLconst 214 OpAMD64SHLWconst 215 OpAMD64SHLBconst 216 OpAMD64SHRQ 217 OpAMD64SHRL 218 OpAMD64SHRW 219 OpAMD64SHRB 220 OpAMD64SHRQconst 221 OpAMD64SHRLconst 222 OpAMD64SHRWconst 223 OpAMD64SHRBconst 224 OpAMD64SARQ 225 OpAMD64SARL 226 OpAMD64SARW 227 OpAMD64SARB 228 OpAMD64SARQconst 229 OpAMD64SARLconst 230 OpAMD64SARWconst 231 OpAMD64SARBconst 232 OpAMD64ROLQconst 233 OpAMD64ROLLconst 234 OpAMD64ROLWconst 235 OpAMD64ROLBconst 236 OpAMD64NEGQ 237 OpAMD64NEGL 238 OpAMD64NEGW 239 OpAMD64NEGB 240 OpAMD64NOTQ 241 OpAMD64NOTL 242 OpAMD64NOTW 243 OpAMD64NOTB 244 OpAMD64BSFQ 245 OpAMD64BSFL 246 OpAMD64BSFW 247 OpAMD64BSRQ 248 OpAMD64BSRL 249 OpAMD64BSRW 250 OpAMD64CMOVQEQconst 251 OpAMD64CMOVLEQconst 252 OpAMD64CMOVWEQconst 253 OpAMD64CMOVQNEconst 254 OpAMD64CMOVLNEconst 255 OpAMD64CMOVWNEconst 256 OpAMD64BSWAPQ 257 OpAMD64BSWAPL 258 OpAMD64SQRTSD 259 OpAMD64SBBQcarrymask 260 OpAMD64SBBLcarrymask 261 OpAMD64SETEQ 262 OpAMD64SETNE 263 OpAMD64SETL 264 OpAMD64SETLE 265 OpAMD64SETG 266 OpAMD64SETGE 267 OpAMD64SETB 268 OpAMD64SETBE 269 OpAMD64SETA 270 OpAMD64SETAE 271 OpAMD64SETEQF 272 OpAMD64SETNEF 273 OpAMD64SETORD 274 OpAMD64SETNAN 275 OpAMD64SETGF 276 OpAMD64SETGEF 277 OpAMD64MOVBQSX 278 OpAMD64MOVBQZX 279 OpAMD64MOVWQSX 280 OpAMD64MOVWQZX 281 OpAMD64MOVLQSX 282 OpAMD64MOVLQZX 283 OpAMD64MOVBconst 284 OpAMD64MOVWconst 285 OpAMD64MOVLconst 286 OpAMD64MOVQconst 287 OpAMD64CVTTSD2SL 288 OpAMD64CVTTSD2SQ 289 OpAMD64CVTTSS2SL 290 OpAMD64CVTTSS2SQ 291 OpAMD64CVTSL2SS 292 OpAMD64CVTSL2SD 293 OpAMD64CVTSQ2SS 294 OpAMD64CVTSQ2SD 295 OpAMD64CVTSD2SS 296 OpAMD64CVTSS2SD 297 OpAMD64PXOR 298 OpAMD64LEAQ 299 OpAMD64LEAQ1 300 OpAMD64LEAQ2 301 OpAMD64LEAQ4 302 OpAMD64LEAQ8 303 OpAMD64MOVBload 304 OpAMD64MOVBQSXload 305 OpAMD64MOVWload 306 OpAMD64MOVWQSXload 307 OpAMD64MOVLload 308 OpAMD64MOVLQSXload 309 OpAMD64MOVQload 310 OpAMD64MOVBstore 311 OpAMD64MOVWstore 312 OpAMD64MOVLstore 313 OpAMD64MOVQstore 314 OpAMD64MOVOload 315 OpAMD64MOVOstore 316 OpAMD64MOVBloadidx1 317 OpAMD64MOVWloadidx1 318 OpAMD64MOVWloadidx2 319 OpAMD64MOVLloadidx1 320 OpAMD64MOVLloadidx4 321 OpAMD64MOVQloadidx1 322 OpAMD64MOVQloadidx8 323 OpAMD64MOVBstoreidx1 324 OpAMD64MOVWstoreidx1 325 OpAMD64MOVWstoreidx2 326 OpAMD64MOVLstoreidx1 327 OpAMD64MOVLstoreidx4 328 OpAMD64MOVQstoreidx1 329 OpAMD64MOVQstoreidx8 330 OpAMD64MOVBstoreconst 331 OpAMD64MOVWstoreconst 332 OpAMD64MOVLstoreconst 333 OpAMD64MOVQstoreconst 334 OpAMD64MOVBstoreconstidx1 335 OpAMD64MOVWstoreconstidx1 336 OpAMD64MOVWstoreconstidx2 337 OpAMD64MOVLstoreconstidx1 338 OpAMD64MOVLstoreconstidx4 339 OpAMD64MOVQstoreconstidx1 340 OpAMD64MOVQstoreconstidx8 341 OpAMD64DUFFZERO 342 OpAMD64MOVOconst 343 OpAMD64REPSTOSQ 344 OpAMD64CALLstatic 345 OpAMD64CALLclosure 346 OpAMD64CALLdefer 347 OpAMD64CALLgo 348 OpAMD64CALLinter 349 OpAMD64DUFFCOPY 350 OpAMD64REPMOVSQ 351 OpAMD64InvertFlags 352 OpAMD64LoweredGetG 353 OpAMD64LoweredGetClosurePtr 354 OpAMD64LoweredNilCheck 355 OpAMD64MOVQconvert 356 OpAMD64FlagEQ 357 OpAMD64FlagLT_ULT 358 OpAMD64FlagLT_UGT 359 OpAMD64FlagGT_UGT 360 OpAMD64FlagGT_ULT 361 362 OpARMADD 363 OpARMADDconst 364 OpARMMOVWconst 365 OpARMCMP 366 OpARMMOVWload 367 OpARMMOVWstore 368 OpARMCALLstatic 369 OpARMLessThan 370 371 OpAdd8 372 OpAdd16 373 OpAdd32 374 OpAdd64 375 OpAddPtr 376 OpAdd32F 377 OpAdd64F 378 OpSub8 379 OpSub16 380 OpSub32 381 OpSub64 382 OpSubPtr 383 OpSub32F 384 OpSub64F 385 OpMul8 386 OpMul16 387 OpMul32 388 OpMul64 389 OpMul32F 390 OpMul64F 391 OpDiv32F 392 OpDiv64F 393 OpHmul8 394 OpHmul8u 395 OpHmul16 396 OpHmul16u 397 OpHmul32 398 OpHmul32u 399 OpHmul64 400 OpHmul64u 401 OpAvg64u 402 OpDiv8 403 OpDiv8u 404 OpDiv16 405 OpDiv16u 406 OpDiv32 407 OpDiv32u 408 OpDiv64 409 OpDiv64u 410 OpMod8 411 OpMod8u 412 OpMod16 413 OpMod16u 414 OpMod32 415 OpMod32u 416 OpMod64 417 OpMod64u 418 OpAnd8 419 OpAnd16 420 OpAnd32 421 OpAnd64 422 OpOr8 423 OpOr16 424 OpOr32 425 OpOr64 426 OpXor8 427 OpXor16 428 OpXor32 429 OpXor64 430 OpLsh8x8 431 OpLsh8x16 432 OpLsh8x32 433 OpLsh8x64 434 OpLsh16x8 435 OpLsh16x16 436 OpLsh16x32 437 OpLsh16x64 438 OpLsh32x8 439 OpLsh32x16 440 OpLsh32x32 441 OpLsh32x64 442 OpLsh64x8 443 OpLsh64x16 444 OpLsh64x32 445 OpLsh64x64 446 OpRsh8x8 447 OpRsh8x16 448 OpRsh8x32 449 OpRsh8x64 450 OpRsh16x8 451 OpRsh16x16 452 OpRsh16x32 453 OpRsh16x64 454 OpRsh32x8 455 OpRsh32x16 456 OpRsh32x32 457 OpRsh32x64 458 OpRsh64x8 459 OpRsh64x16 460 OpRsh64x32 461 OpRsh64x64 462 OpRsh8Ux8 463 OpRsh8Ux16 464 OpRsh8Ux32 465 OpRsh8Ux64 466 OpRsh16Ux8 467 OpRsh16Ux16 468 OpRsh16Ux32 469 OpRsh16Ux64 470 OpRsh32Ux8 471 OpRsh32Ux16 472 OpRsh32Ux32 473 OpRsh32Ux64 474 OpRsh64Ux8 475 OpRsh64Ux16 476 OpRsh64Ux32 477 OpRsh64Ux64 478 OpLrot8 479 OpLrot16 480 OpLrot32 481 OpLrot64 482 OpEq8 483 OpEq16 484 OpEq32 485 OpEq64 486 OpEqPtr 487 OpEqInter 488 OpEqSlice 489 OpEq32F 490 OpEq64F 491 OpNeq8 492 OpNeq16 493 OpNeq32 494 OpNeq64 495 OpNeqPtr 496 OpNeqInter 497 OpNeqSlice 498 OpNeq32F 499 OpNeq64F 500 OpLess8 501 OpLess8U 502 OpLess16 503 OpLess16U 504 OpLess32 505 OpLess32U 506 OpLess64 507 OpLess64U 508 OpLess32F 509 OpLess64F 510 OpLeq8 511 OpLeq8U 512 OpLeq16 513 OpLeq16U 514 OpLeq32 515 OpLeq32U 516 OpLeq64 517 OpLeq64U 518 OpLeq32F 519 OpLeq64F 520 OpGreater8 521 OpGreater8U 522 OpGreater16 523 OpGreater16U 524 OpGreater32 525 OpGreater32U 526 OpGreater64 527 OpGreater64U 528 OpGreater32F 529 OpGreater64F 530 OpGeq8 531 OpGeq8U 532 OpGeq16 533 OpGeq16U 534 OpGeq32 535 OpGeq32U 536 OpGeq64 537 OpGeq64U 538 OpGeq32F 539 OpGeq64F 540 OpNot 541 OpNeg8 542 OpNeg16 543 OpNeg32 544 OpNeg64 545 OpNeg32F 546 OpNeg64F 547 OpCom8 548 OpCom16 549 OpCom32 550 OpCom64 551 OpCtz16 552 OpCtz32 553 OpCtz64 554 OpClz16 555 OpClz32 556 OpClz64 557 OpBswap32 558 OpBswap64 559 OpSqrt 560 OpPhi 561 OpCopy 562 OpConvert 563 OpConstBool 564 OpConstString 565 OpConstNil 566 OpConst8 567 OpConst16 568 OpConst32 569 OpConst64 570 OpConst32F 571 OpConst64F 572 OpConstInterface 573 OpConstSlice 574 OpInitMem 575 OpArg 576 OpAddr 577 OpSP 578 OpSB 579 OpFunc 580 OpLoad 581 OpStore 582 OpMove 583 OpZero 584 OpClosureCall 585 OpStaticCall 586 OpDeferCall 587 OpGoCall 588 OpInterCall 589 OpSignExt8to16 590 OpSignExt8to32 591 OpSignExt8to64 592 OpSignExt16to32 593 OpSignExt16to64 594 OpSignExt32to64 595 OpZeroExt8to16 596 OpZeroExt8to32 597 OpZeroExt8to64 598 OpZeroExt16to32 599 OpZeroExt16to64 600 OpZeroExt32to64 601 OpTrunc16to8 602 OpTrunc32to8 603 OpTrunc32to16 604 OpTrunc64to8 605 OpTrunc64to16 606 OpTrunc64to32 607 OpCvt32to32F 608 OpCvt32to64F 609 OpCvt64to32F 610 OpCvt64to64F 611 OpCvt32Fto32 612 OpCvt32Fto64 613 OpCvt64Fto32 614 OpCvt64Fto64 615 OpCvt32Fto64F 616 OpCvt64Fto32F 617 OpIsNonNil 618 OpIsInBounds 619 OpIsSliceInBounds 620 OpNilCheck 621 OpGetG 622 OpGetClosurePtr 623 OpArrayIndex 624 OpPtrIndex 625 OpOffPtr 626 OpSliceMake 627 OpSlicePtr 628 OpSliceLen 629 OpSliceCap 630 OpComplexMake 631 OpComplexReal 632 OpComplexImag 633 OpStringMake 634 OpStringPtr 635 OpStringLen 636 OpIMake 637 OpITab 638 OpIData 639 OpStructMake0 640 OpStructMake1 641 OpStructMake2 642 OpStructMake3 643 OpStructMake4 644 OpStructSelect 645 OpStoreReg 646 OpLoadReg 647 OpFwdRef 648 OpUnknown 649 OpVarDef 650 OpVarKill 651 OpVarLive 652 ) 653 654 var opcodeTable = [...]opInfo{ 655 {name: "OpInvalid"}, 656 657 { 658 name: "ADDSS", 659 argLen: 2, 660 commutative: true, 661 resultInArg0: true, 662 asm: x86.AADDSS, 663 reg: regInfo{ 664 inputs: []inputInfo{ 665 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 666 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 667 }, 668 outputs: []regMask{ 669 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 670 }, 671 }, 672 }, 673 { 674 name: "ADDSD", 675 argLen: 2, 676 commutative: true, 677 resultInArg0: true, 678 asm: x86.AADDSD, 679 reg: regInfo{ 680 inputs: []inputInfo{ 681 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 682 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 683 }, 684 outputs: []regMask{ 685 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 686 }, 687 }, 688 }, 689 { 690 name: "SUBSS", 691 argLen: 2, 692 resultInArg0: true, 693 asm: x86.ASUBSS, 694 reg: regInfo{ 695 inputs: []inputInfo{ 696 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 697 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 698 }, 699 clobbers: 2147483648, // X15 700 outputs: []regMask{ 701 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 702 }, 703 }, 704 }, 705 { 706 name: "SUBSD", 707 argLen: 2, 708 resultInArg0: true, 709 asm: x86.ASUBSD, 710 reg: regInfo{ 711 inputs: []inputInfo{ 712 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 713 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 714 }, 715 clobbers: 2147483648, // X15 716 outputs: []regMask{ 717 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 718 }, 719 }, 720 }, 721 { 722 name: "MULSS", 723 argLen: 2, 724 commutative: true, 725 resultInArg0: true, 726 asm: x86.AMULSS, 727 reg: regInfo{ 728 inputs: []inputInfo{ 729 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 730 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 731 }, 732 outputs: []regMask{ 733 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 734 }, 735 }, 736 }, 737 { 738 name: "MULSD", 739 argLen: 2, 740 commutative: true, 741 resultInArg0: true, 742 asm: x86.AMULSD, 743 reg: regInfo{ 744 inputs: []inputInfo{ 745 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 746 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 747 }, 748 outputs: []regMask{ 749 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 750 }, 751 }, 752 }, 753 { 754 name: "DIVSS", 755 argLen: 2, 756 resultInArg0: true, 757 asm: x86.ADIVSS, 758 reg: regInfo{ 759 inputs: []inputInfo{ 760 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 761 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 762 }, 763 clobbers: 2147483648, // X15 764 outputs: []regMask{ 765 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 766 }, 767 }, 768 }, 769 { 770 name: "DIVSD", 771 argLen: 2, 772 resultInArg0: true, 773 asm: x86.ADIVSD, 774 reg: regInfo{ 775 inputs: []inputInfo{ 776 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 777 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 778 }, 779 clobbers: 2147483648, // X15 780 outputs: []regMask{ 781 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 782 }, 783 }, 784 }, 785 { 786 name: "MOVSSload", 787 auxType: auxSymOff, 788 argLen: 2, 789 asm: x86.AMOVSS, 790 reg: regInfo{ 791 inputs: []inputInfo{ 792 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 793 }, 794 outputs: []regMask{ 795 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 796 }, 797 }, 798 }, 799 { 800 name: "MOVSDload", 801 auxType: auxSymOff, 802 argLen: 2, 803 asm: x86.AMOVSD, 804 reg: regInfo{ 805 inputs: []inputInfo{ 806 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 807 }, 808 outputs: []regMask{ 809 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 810 }, 811 }, 812 }, 813 { 814 name: "MOVSSconst", 815 auxType: auxFloat32, 816 argLen: 0, 817 rematerializeable: true, 818 asm: x86.AMOVSS, 819 reg: regInfo{ 820 outputs: []regMask{ 821 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 822 }, 823 }, 824 }, 825 { 826 name: "MOVSDconst", 827 auxType: auxFloat64, 828 argLen: 0, 829 rematerializeable: true, 830 asm: x86.AMOVSD, 831 reg: regInfo{ 832 outputs: []regMask{ 833 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 834 }, 835 }, 836 }, 837 { 838 name: "MOVSSloadidx1", 839 auxType: auxSymOff, 840 argLen: 3, 841 asm: x86.AMOVSS, 842 reg: regInfo{ 843 inputs: []inputInfo{ 844 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 845 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 846 }, 847 outputs: []regMask{ 848 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 849 }, 850 }, 851 }, 852 { 853 name: "MOVSSloadidx4", 854 auxType: auxSymOff, 855 argLen: 3, 856 asm: x86.AMOVSS, 857 reg: regInfo{ 858 inputs: []inputInfo{ 859 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 860 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 861 }, 862 outputs: []regMask{ 863 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 864 }, 865 }, 866 }, 867 { 868 name: "MOVSDloadidx1", 869 auxType: auxSymOff, 870 argLen: 3, 871 asm: x86.AMOVSD, 872 reg: regInfo{ 873 inputs: []inputInfo{ 874 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 875 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 876 }, 877 outputs: []regMask{ 878 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 879 }, 880 }, 881 }, 882 { 883 name: "MOVSDloadidx8", 884 auxType: auxSymOff, 885 argLen: 3, 886 asm: x86.AMOVSD, 887 reg: regInfo{ 888 inputs: []inputInfo{ 889 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 890 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 891 }, 892 outputs: []regMask{ 893 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 894 }, 895 }, 896 }, 897 { 898 name: "MOVSSstore", 899 auxType: auxSymOff, 900 argLen: 3, 901 asm: x86.AMOVSS, 902 reg: regInfo{ 903 inputs: []inputInfo{ 904 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 905 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 906 }, 907 }, 908 }, 909 { 910 name: "MOVSDstore", 911 auxType: auxSymOff, 912 argLen: 3, 913 asm: x86.AMOVSD, 914 reg: regInfo{ 915 inputs: []inputInfo{ 916 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 917 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 918 }, 919 }, 920 }, 921 { 922 name: "MOVSSstoreidx1", 923 auxType: auxSymOff, 924 argLen: 4, 925 asm: x86.AMOVSS, 926 reg: regInfo{ 927 inputs: []inputInfo{ 928 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 929 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 930 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 931 }, 932 }, 933 }, 934 { 935 name: "MOVSSstoreidx4", 936 auxType: auxSymOff, 937 argLen: 4, 938 asm: x86.AMOVSS, 939 reg: regInfo{ 940 inputs: []inputInfo{ 941 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 942 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 943 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 944 }, 945 }, 946 }, 947 { 948 name: "MOVSDstoreidx1", 949 auxType: auxSymOff, 950 argLen: 4, 951 asm: x86.AMOVSD, 952 reg: regInfo{ 953 inputs: []inputInfo{ 954 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 955 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 956 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 957 }, 958 }, 959 }, 960 { 961 name: "MOVSDstoreidx8", 962 auxType: auxSymOff, 963 argLen: 4, 964 asm: x86.AMOVSD, 965 reg: regInfo{ 966 inputs: []inputInfo{ 967 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 968 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 969 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 970 }, 971 }, 972 }, 973 { 974 name: "ADDQ", 975 argLen: 2, 976 commutative: true, 977 resultInArg0: true, 978 asm: x86.AADDQ, 979 reg: regInfo{ 980 inputs: []inputInfo{ 981 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 982 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 983 }, 984 clobbers: 8589934592, // FLAGS 985 outputs: []regMask{ 986 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 987 }, 988 }, 989 }, 990 { 991 name: "ADDL", 992 argLen: 2, 993 commutative: true, 994 resultInArg0: true, 995 asm: x86.AADDL, 996 reg: regInfo{ 997 inputs: []inputInfo{ 998 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 999 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1000 }, 1001 clobbers: 8589934592, // FLAGS 1002 outputs: []regMask{ 1003 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1004 }, 1005 }, 1006 }, 1007 { 1008 name: "ADDW", 1009 argLen: 2, 1010 commutative: true, 1011 resultInArg0: true, 1012 asm: x86.AADDL, 1013 reg: regInfo{ 1014 inputs: []inputInfo{ 1015 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1016 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1017 }, 1018 clobbers: 8589934592, // FLAGS 1019 outputs: []regMask{ 1020 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1021 }, 1022 }, 1023 }, 1024 { 1025 name: "ADDB", 1026 argLen: 2, 1027 commutative: true, 1028 resultInArg0: true, 1029 asm: x86.AADDL, 1030 reg: regInfo{ 1031 inputs: []inputInfo{ 1032 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1033 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1034 }, 1035 clobbers: 8589934592, // FLAGS 1036 outputs: []regMask{ 1037 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1038 }, 1039 }, 1040 }, 1041 { 1042 name: "ADDQconst", 1043 auxType: auxInt64, 1044 argLen: 1, 1045 resultInArg0: true, 1046 asm: x86.AADDQ, 1047 reg: regInfo{ 1048 inputs: []inputInfo{ 1049 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1050 }, 1051 clobbers: 8589934592, // FLAGS 1052 outputs: []regMask{ 1053 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1054 }, 1055 }, 1056 }, 1057 { 1058 name: "ADDLconst", 1059 auxType: auxInt32, 1060 argLen: 1, 1061 resultInArg0: true, 1062 asm: x86.AADDL, 1063 reg: regInfo{ 1064 inputs: []inputInfo{ 1065 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1066 }, 1067 clobbers: 8589934592, // FLAGS 1068 outputs: []regMask{ 1069 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1070 }, 1071 }, 1072 }, 1073 { 1074 name: "ADDWconst", 1075 auxType: auxInt16, 1076 argLen: 1, 1077 resultInArg0: true, 1078 asm: x86.AADDL, 1079 reg: regInfo{ 1080 inputs: []inputInfo{ 1081 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1082 }, 1083 clobbers: 8589934592, // FLAGS 1084 outputs: []regMask{ 1085 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1086 }, 1087 }, 1088 }, 1089 { 1090 name: "ADDBconst", 1091 auxType: auxInt8, 1092 argLen: 1, 1093 resultInArg0: true, 1094 asm: x86.AADDL, 1095 reg: regInfo{ 1096 inputs: []inputInfo{ 1097 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1098 }, 1099 clobbers: 8589934592, // FLAGS 1100 outputs: []regMask{ 1101 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1102 }, 1103 }, 1104 }, 1105 { 1106 name: "SUBQ", 1107 argLen: 2, 1108 resultInArg0: true, 1109 asm: x86.ASUBQ, 1110 reg: regInfo{ 1111 inputs: []inputInfo{ 1112 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1113 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1114 }, 1115 clobbers: 8589934592, // FLAGS 1116 outputs: []regMask{ 1117 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1118 }, 1119 }, 1120 }, 1121 { 1122 name: "SUBL", 1123 argLen: 2, 1124 resultInArg0: true, 1125 asm: x86.ASUBL, 1126 reg: regInfo{ 1127 inputs: []inputInfo{ 1128 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1129 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1130 }, 1131 clobbers: 8589934592, // FLAGS 1132 outputs: []regMask{ 1133 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1134 }, 1135 }, 1136 }, 1137 { 1138 name: "SUBW", 1139 argLen: 2, 1140 resultInArg0: true, 1141 asm: x86.ASUBL, 1142 reg: regInfo{ 1143 inputs: []inputInfo{ 1144 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1145 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1146 }, 1147 clobbers: 8589934592, // FLAGS 1148 outputs: []regMask{ 1149 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1150 }, 1151 }, 1152 }, 1153 { 1154 name: "SUBB", 1155 argLen: 2, 1156 resultInArg0: true, 1157 asm: x86.ASUBL, 1158 reg: regInfo{ 1159 inputs: []inputInfo{ 1160 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1161 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1162 }, 1163 clobbers: 8589934592, // FLAGS 1164 outputs: []regMask{ 1165 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1166 }, 1167 }, 1168 }, 1169 { 1170 name: "SUBQconst", 1171 auxType: auxInt64, 1172 argLen: 1, 1173 resultInArg0: true, 1174 asm: x86.ASUBQ, 1175 reg: regInfo{ 1176 inputs: []inputInfo{ 1177 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1178 }, 1179 clobbers: 8589934592, // FLAGS 1180 outputs: []regMask{ 1181 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1182 }, 1183 }, 1184 }, 1185 { 1186 name: "SUBLconst", 1187 auxType: auxInt32, 1188 argLen: 1, 1189 resultInArg0: true, 1190 asm: x86.ASUBL, 1191 reg: regInfo{ 1192 inputs: []inputInfo{ 1193 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1194 }, 1195 clobbers: 8589934592, // FLAGS 1196 outputs: []regMask{ 1197 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1198 }, 1199 }, 1200 }, 1201 { 1202 name: "SUBWconst", 1203 auxType: auxInt16, 1204 argLen: 1, 1205 resultInArg0: true, 1206 asm: x86.ASUBL, 1207 reg: regInfo{ 1208 inputs: []inputInfo{ 1209 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1210 }, 1211 clobbers: 8589934592, // FLAGS 1212 outputs: []regMask{ 1213 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1214 }, 1215 }, 1216 }, 1217 { 1218 name: "SUBBconst", 1219 auxType: auxInt8, 1220 argLen: 1, 1221 resultInArg0: true, 1222 asm: x86.ASUBL, 1223 reg: regInfo{ 1224 inputs: []inputInfo{ 1225 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1226 }, 1227 clobbers: 8589934592, // FLAGS 1228 outputs: []regMask{ 1229 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1230 }, 1231 }, 1232 }, 1233 { 1234 name: "MULQ", 1235 argLen: 2, 1236 commutative: true, 1237 resultInArg0: true, 1238 asm: x86.AIMULQ, 1239 reg: regInfo{ 1240 inputs: []inputInfo{ 1241 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1242 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1243 }, 1244 clobbers: 8589934592, // FLAGS 1245 outputs: []regMask{ 1246 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1247 }, 1248 }, 1249 }, 1250 { 1251 name: "MULL", 1252 argLen: 2, 1253 commutative: true, 1254 resultInArg0: true, 1255 asm: x86.AIMULL, 1256 reg: regInfo{ 1257 inputs: []inputInfo{ 1258 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1259 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1260 }, 1261 clobbers: 8589934592, // FLAGS 1262 outputs: []regMask{ 1263 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1264 }, 1265 }, 1266 }, 1267 { 1268 name: "MULW", 1269 argLen: 2, 1270 commutative: true, 1271 resultInArg0: true, 1272 asm: x86.AIMULW, 1273 reg: regInfo{ 1274 inputs: []inputInfo{ 1275 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1276 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1277 }, 1278 clobbers: 8589934592, // FLAGS 1279 outputs: []regMask{ 1280 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1281 }, 1282 }, 1283 }, 1284 { 1285 name: "MULB", 1286 argLen: 2, 1287 commutative: true, 1288 resultInArg0: true, 1289 asm: x86.AIMULW, 1290 reg: regInfo{ 1291 inputs: []inputInfo{ 1292 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1293 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1294 }, 1295 clobbers: 8589934592, // FLAGS 1296 outputs: []regMask{ 1297 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1298 }, 1299 }, 1300 }, 1301 { 1302 name: "MULQconst", 1303 auxType: auxInt64, 1304 argLen: 1, 1305 resultInArg0: true, 1306 asm: x86.AIMULQ, 1307 reg: regInfo{ 1308 inputs: []inputInfo{ 1309 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1310 }, 1311 clobbers: 8589934592, // FLAGS 1312 outputs: []regMask{ 1313 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1314 }, 1315 }, 1316 }, 1317 { 1318 name: "MULLconst", 1319 auxType: auxInt32, 1320 argLen: 1, 1321 resultInArg0: true, 1322 asm: x86.AIMULL, 1323 reg: regInfo{ 1324 inputs: []inputInfo{ 1325 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1326 }, 1327 clobbers: 8589934592, // FLAGS 1328 outputs: []regMask{ 1329 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1330 }, 1331 }, 1332 }, 1333 { 1334 name: "MULWconst", 1335 auxType: auxInt16, 1336 argLen: 1, 1337 resultInArg0: true, 1338 asm: x86.AIMULW, 1339 reg: regInfo{ 1340 inputs: []inputInfo{ 1341 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1342 }, 1343 clobbers: 8589934592, // FLAGS 1344 outputs: []regMask{ 1345 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1346 }, 1347 }, 1348 }, 1349 { 1350 name: "MULBconst", 1351 auxType: auxInt8, 1352 argLen: 1, 1353 resultInArg0: true, 1354 asm: x86.AIMULW, 1355 reg: regInfo{ 1356 inputs: []inputInfo{ 1357 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1358 }, 1359 clobbers: 8589934592, // FLAGS 1360 outputs: []regMask{ 1361 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1362 }, 1363 }, 1364 }, 1365 { 1366 name: "HMULQ", 1367 argLen: 2, 1368 asm: x86.AIMULQ, 1369 reg: regInfo{ 1370 inputs: []inputInfo{ 1371 {0, 1}, // AX 1372 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1373 }, 1374 clobbers: 8589934593, // AX FLAGS 1375 outputs: []regMask{ 1376 4, // DX 1377 }, 1378 }, 1379 }, 1380 { 1381 name: "HMULL", 1382 argLen: 2, 1383 asm: x86.AIMULL, 1384 reg: regInfo{ 1385 inputs: []inputInfo{ 1386 {0, 1}, // AX 1387 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1388 }, 1389 clobbers: 8589934593, // AX FLAGS 1390 outputs: []regMask{ 1391 4, // DX 1392 }, 1393 }, 1394 }, 1395 { 1396 name: "HMULW", 1397 argLen: 2, 1398 asm: x86.AIMULW, 1399 reg: regInfo{ 1400 inputs: []inputInfo{ 1401 {0, 1}, // AX 1402 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1403 }, 1404 clobbers: 8589934593, // AX FLAGS 1405 outputs: []regMask{ 1406 4, // DX 1407 }, 1408 }, 1409 }, 1410 { 1411 name: "HMULB", 1412 argLen: 2, 1413 asm: x86.AIMULB, 1414 reg: regInfo{ 1415 inputs: []inputInfo{ 1416 {0, 1}, // AX 1417 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1418 }, 1419 clobbers: 8589934593, // AX FLAGS 1420 outputs: []regMask{ 1421 4, // DX 1422 }, 1423 }, 1424 }, 1425 { 1426 name: "HMULQU", 1427 argLen: 2, 1428 asm: x86.AMULQ, 1429 reg: regInfo{ 1430 inputs: []inputInfo{ 1431 {0, 1}, // AX 1432 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1433 }, 1434 clobbers: 8589934593, // AX FLAGS 1435 outputs: []regMask{ 1436 4, // DX 1437 }, 1438 }, 1439 }, 1440 { 1441 name: "HMULLU", 1442 argLen: 2, 1443 asm: x86.AMULL, 1444 reg: regInfo{ 1445 inputs: []inputInfo{ 1446 {0, 1}, // AX 1447 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1448 }, 1449 clobbers: 8589934593, // AX FLAGS 1450 outputs: []regMask{ 1451 4, // DX 1452 }, 1453 }, 1454 }, 1455 { 1456 name: "HMULWU", 1457 argLen: 2, 1458 asm: x86.AMULW, 1459 reg: regInfo{ 1460 inputs: []inputInfo{ 1461 {0, 1}, // AX 1462 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1463 }, 1464 clobbers: 8589934593, // AX FLAGS 1465 outputs: []regMask{ 1466 4, // DX 1467 }, 1468 }, 1469 }, 1470 { 1471 name: "HMULBU", 1472 argLen: 2, 1473 asm: x86.AMULB, 1474 reg: regInfo{ 1475 inputs: []inputInfo{ 1476 {0, 1}, // AX 1477 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1478 }, 1479 clobbers: 8589934593, // AX FLAGS 1480 outputs: []regMask{ 1481 4, // DX 1482 }, 1483 }, 1484 }, 1485 { 1486 name: "AVGQU", 1487 argLen: 2, 1488 commutative: true, 1489 resultInArg0: true, 1490 reg: regInfo{ 1491 inputs: []inputInfo{ 1492 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1493 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1494 }, 1495 clobbers: 8589934592, // FLAGS 1496 outputs: []regMask{ 1497 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1498 }, 1499 }, 1500 }, 1501 { 1502 name: "DIVQ", 1503 argLen: 2, 1504 asm: x86.AIDIVQ, 1505 reg: regInfo{ 1506 inputs: []inputInfo{ 1507 {0, 1}, // AX 1508 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1509 }, 1510 clobbers: 8589934596, // DX FLAGS 1511 outputs: []regMask{ 1512 1, // AX 1513 }, 1514 }, 1515 }, 1516 { 1517 name: "DIVL", 1518 argLen: 2, 1519 asm: x86.AIDIVL, 1520 reg: regInfo{ 1521 inputs: []inputInfo{ 1522 {0, 1}, // AX 1523 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1524 }, 1525 clobbers: 8589934596, // DX FLAGS 1526 outputs: []regMask{ 1527 1, // AX 1528 }, 1529 }, 1530 }, 1531 { 1532 name: "DIVW", 1533 argLen: 2, 1534 asm: x86.AIDIVW, 1535 reg: regInfo{ 1536 inputs: []inputInfo{ 1537 {0, 1}, // AX 1538 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1539 }, 1540 clobbers: 8589934596, // DX FLAGS 1541 outputs: []regMask{ 1542 1, // AX 1543 }, 1544 }, 1545 }, 1546 { 1547 name: "DIVQU", 1548 argLen: 2, 1549 asm: x86.ADIVQ, 1550 reg: regInfo{ 1551 inputs: []inputInfo{ 1552 {0, 1}, // AX 1553 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1554 }, 1555 clobbers: 8589934596, // DX FLAGS 1556 outputs: []regMask{ 1557 1, // AX 1558 }, 1559 }, 1560 }, 1561 { 1562 name: "DIVLU", 1563 argLen: 2, 1564 asm: x86.ADIVL, 1565 reg: regInfo{ 1566 inputs: []inputInfo{ 1567 {0, 1}, // AX 1568 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1569 }, 1570 clobbers: 8589934596, // DX FLAGS 1571 outputs: []regMask{ 1572 1, // AX 1573 }, 1574 }, 1575 }, 1576 { 1577 name: "DIVWU", 1578 argLen: 2, 1579 asm: x86.ADIVW, 1580 reg: regInfo{ 1581 inputs: []inputInfo{ 1582 {0, 1}, // AX 1583 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1584 }, 1585 clobbers: 8589934596, // DX FLAGS 1586 outputs: []regMask{ 1587 1, // AX 1588 }, 1589 }, 1590 }, 1591 { 1592 name: "MODQ", 1593 argLen: 2, 1594 asm: x86.AIDIVQ, 1595 reg: regInfo{ 1596 inputs: []inputInfo{ 1597 {0, 1}, // AX 1598 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1599 }, 1600 clobbers: 8589934593, // AX FLAGS 1601 outputs: []regMask{ 1602 4, // DX 1603 }, 1604 }, 1605 }, 1606 { 1607 name: "MODL", 1608 argLen: 2, 1609 asm: x86.AIDIVL, 1610 reg: regInfo{ 1611 inputs: []inputInfo{ 1612 {0, 1}, // AX 1613 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1614 }, 1615 clobbers: 8589934593, // AX FLAGS 1616 outputs: []regMask{ 1617 4, // DX 1618 }, 1619 }, 1620 }, 1621 { 1622 name: "MODW", 1623 argLen: 2, 1624 asm: x86.AIDIVW, 1625 reg: regInfo{ 1626 inputs: []inputInfo{ 1627 {0, 1}, // AX 1628 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1629 }, 1630 clobbers: 8589934593, // AX FLAGS 1631 outputs: []regMask{ 1632 4, // DX 1633 }, 1634 }, 1635 }, 1636 { 1637 name: "MODQU", 1638 argLen: 2, 1639 asm: x86.ADIVQ, 1640 reg: regInfo{ 1641 inputs: []inputInfo{ 1642 {0, 1}, // AX 1643 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1644 }, 1645 clobbers: 8589934593, // AX FLAGS 1646 outputs: []regMask{ 1647 4, // DX 1648 }, 1649 }, 1650 }, 1651 { 1652 name: "MODLU", 1653 argLen: 2, 1654 asm: x86.ADIVL, 1655 reg: regInfo{ 1656 inputs: []inputInfo{ 1657 {0, 1}, // AX 1658 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1659 }, 1660 clobbers: 8589934593, // AX FLAGS 1661 outputs: []regMask{ 1662 4, // DX 1663 }, 1664 }, 1665 }, 1666 { 1667 name: "MODWU", 1668 argLen: 2, 1669 asm: x86.ADIVW, 1670 reg: regInfo{ 1671 inputs: []inputInfo{ 1672 {0, 1}, // AX 1673 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1674 }, 1675 clobbers: 8589934593, // AX FLAGS 1676 outputs: []regMask{ 1677 4, // DX 1678 }, 1679 }, 1680 }, 1681 { 1682 name: "ANDQ", 1683 argLen: 2, 1684 commutative: true, 1685 resultInArg0: true, 1686 asm: x86.AANDQ, 1687 reg: regInfo{ 1688 inputs: []inputInfo{ 1689 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1690 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1691 }, 1692 clobbers: 8589934592, // FLAGS 1693 outputs: []regMask{ 1694 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1695 }, 1696 }, 1697 }, 1698 { 1699 name: "ANDL", 1700 argLen: 2, 1701 commutative: true, 1702 resultInArg0: true, 1703 asm: x86.AANDL, 1704 reg: regInfo{ 1705 inputs: []inputInfo{ 1706 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1707 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1708 }, 1709 clobbers: 8589934592, // FLAGS 1710 outputs: []regMask{ 1711 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1712 }, 1713 }, 1714 }, 1715 { 1716 name: "ANDW", 1717 argLen: 2, 1718 commutative: true, 1719 resultInArg0: true, 1720 asm: x86.AANDL, 1721 reg: regInfo{ 1722 inputs: []inputInfo{ 1723 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1724 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1725 }, 1726 clobbers: 8589934592, // FLAGS 1727 outputs: []regMask{ 1728 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1729 }, 1730 }, 1731 }, 1732 { 1733 name: "ANDB", 1734 argLen: 2, 1735 commutative: true, 1736 resultInArg0: true, 1737 asm: x86.AANDL, 1738 reg: regInfo{ 1739 inputs: []inputInfo{ 1740 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1741 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1742 }, 1743 clobbers: 8589934592, // FLAGS 1744 outputs: []regMask{ 1745 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1746 }, 1747 }, 1748 }, 1749 { 1750 name: "ANDQconst", 1751 auxType: auxInt64, 1752 argLen: 1, 1753 resultInArg0: true, 1754 asm: x86.AANDQ, 1755 reg: regInfo{ 1756 inputs: []inputInfo{ 1757 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1758 }, 1759 clobbers: 8589934592, // FLAGS 1760 outputs: []regMask{ 1761 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1762 }, 1763 }, 1764 }, 1765 { 1766 name: "ANDLconst", 1767 auxType: auxInt32, 1768 argLen: 1, 1769 resultInArg0: true, 1770 asm: x86.AANDL, 1771 reg: regInfo{ 1772 inputs: []inputInfo{ 1773 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1774 }, 1775 clobbers: 8589934592, // FLAGS 1776 outputs: []regMask{ 1777 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1778 }, 1779 }, 1780 }, 1781 { 1782 name: "ANDWconst", 1783 auxType: auxInt16, 1784 argLen: 1, 1785 resultInArg0: true, 1786 asm: x86.AANDL, 1787 reg: regInfo{ 1788 inputs: []inputInfo{ 1789 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1790 }, 1791 clobbers: 8589934592, // FLAGS 1792 outputs: []regMask{ 1793 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1794 }, 1795 }, 1796 }, 1797 { 1798 name: "ANDBconst", 1799 auxType: auxInt8, 1800 argLen: 1, 1801 resultInArg0: true, 1802 asm: x86.AANDL, 1803 reg: regInfo{ 1804 inputs: []inputInfo{ 1805 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1806 }, 1807 clobbers: 8589934592, // FLAGS 1808 outputs: []regMask{ 1809 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1810 }, 1811 }, 1812 }, 1813 { 1814 name: "ORQ", 1815 argLen: 2, 1816 commutative: true, 1817 resultInArg0: true, 1818 asm: x86.AORQ, 1819 reg: regInfo{ 1820 inputs: []inputInfo{ 1821 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1822 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1823 }, 1824 clobbers: 8589934592, // FLAGS 1825 outputs: []regMask{ 1826 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1827 }, 1828 }, 1829 }, 1830 { 1831 name: "ORL", 1832 argLen: 2, 1833 commutative: true, 1834 resultInArg0: true, 1835 asm: x86.AORL, 1836 reg: regInfo{ 1837 inputs: []inputInfo{ 1838 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1839 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1840 }, 1841 clobbers: 8589934592, // FLAGS 1842 outputs: []regMask{ 1843 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1844 }, 1845 }, 1846 }, 1847 { 1848 name: "ORW", 1849 argLen: 2, 1850 commutative: true, 1851 resultInArg0: true, 1852 asm: x86.AORL, 1853 reg: regInfo{ 1854 inputs: []inputInfo{ 1855 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1856 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1857 }, 1858 clobbers: 8589934592, // FLAGS 1859 outputs: []regMask{ 1860 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1861 }, 1862 }, 1863 }, 1864 { 1865 name: "ORB", 1866 argLen: 2, 1867 commutative: true, 1868 resultInArg0: true, 1869 asm: x86.AORL, 1870 reg: regInfo{ 1871 inputs: []inputInfo{ 1872 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1873 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1874 }, 1875 clobbers: 8589934592, // FLAGS 1876 outputs: []regMask{ 1877 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1878 }, 1879 }, 1880 }, 1881 { 1882 name: "ORQconst", 1883 auxType: auxInt64, 1884 argLen: 1, 1885 resultInArg0: true, 1886 asm: x86.AORQ, 1887 reg: regInfo{ 1888 inputs: []inputInfo{ 1889 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1890 }, 1891 clobbers: 8589934592, // FLAGS 1892 outputs: []regMask{ 1893 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1894 }, 1895 }, 1896 }, 1897 { 1898 name: "ORLconst", 1899 auxType: auxInt32, 1900 argLen: 1, 1901 resultInArg0: true, 1902 asm: x86.AORL, 1903 reg: regInfo{ 1904 inputs: []inputInfo{ 1905 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1906 }, 1907 clobbers: 8589934592, // FLAGS 1908 outputs: []regMask{ 1909 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1910 }, 1911 }, 1912 }, 1913 { 1914 name: "ORWconst", 1915 auxType: auxInt16, 1916 argLen: 1, 1917 resultInArg0: true, 1918 asm: x86.AORL, 1919 reg: regInfo{ 1920 inputs: []inputInfo{ 1921 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1922 }, 1923 clobbers: 8589934592, // FLAGS 1924 outputs: []regMask{ 1925 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1926 }, 1927 }, 1928 }, 1929 { 1930 name: "ORBconst", 1931 auxType: auxInt8, 1932 argLen: 1, 1933 resultInArg0: true, 1934 asm: x86.AORL, 1935 reg: regInfo{ 1936 inputs: []inputInfo{ 1937 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1938 }, 1939 clobbers: 8589934592, // FLAGS 1940 outputs: []regMask{ 1941 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1942 }, 1943 }, 1944 }, 1945 { 1946 name: "XORQ", 1947 argLen: 2, 1948 commutative: true, 1949 resultInArg0: true, 1950 asm: x86.AXORQ, 1951 reg: regInfo{ 1952 inputs: []inputInfo{ 1953 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1954 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1955 }, 1956 clobbers: 8589934592, // FLAGS 1957 outputs: []regMask{ 1958 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1959 }, 1960 }, 1961 }, 1962 { 1963 name: "XORL", 1964 argLen: 2, 1965 commutative: true, 1966 resultInArg0: true, 1967 asm: x86.AXORL, 1968 reg: regInfo{ 1969 inputs: []inputInfo{ 1970 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1971 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1972 }, 1973 clobbers: 8589934592, // FLAGS 1974 outputs: []regMask{ 1975 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1976 }, 1977 }, 1978 }, 1979 { 1980 name: "XORW", 1981 argLen: 2, 1982 commutative: true, 1983 resultInArg0: true, 1984 asm: x86.AXORL, 1985 reg: regInfo{ 1986 inputs: []inputInfo{ 1987 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1988 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1989 }, 1990 clobbers: 8589934592, // FLAGS 1991 outputs: []regMask{ 1992 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 1993 }, 1994 }, 1995 }, 1996 { 1997 name: "XORB", 1998 argLen: 2, 1999 commutative: true, 2000 resultInArg0: true, 2001 asm: x86.AXORL, 2002 reg: regInfo{ 2003 inputs: []inputInfo{ 2004 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2005 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2006 }, 2007 clobbers: 8589934592, // FLAGS 2008 outputs: []regMask{ 2009 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2010 }, 2011 }, 2012 }, 2013 { 2014 name: "XORQconst", 2015 auxType: auxInt64, 2016 argLen: 1, 2017 resultInArg0: true, 2018 asm: x86.AXORQ, 2019 reg: regInfo{ 2020 inputs: []inputInfo{ 2021 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2022 }, 2023 clobbers: 8589934592, // FLAGS 2024 outputs: []regMask{ 2025 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2026 }, 2027 }, 2028 }, 2029 { 2030 name: "XORLconst", 2031 auxType: auxInt32, 2032 argLen: 1, 2033 resultInArg0: true, 2034 asm: x86.AXORL, 2035 reg: regInfo{ 2036 inputs: []inputInfo{ 2037 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2038 }, 2039 clobbers: 8589934592, // FLAGS 2040 outputs: []regMask{ 2041 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2042 }, 2043 }, 2044 }, 2045 { 2046 name: "XORWconst", 2047 auxType: auxInt16, 2048 argLen: 1, 2049 resultInArg0: true, 2050 asm: x86.AXORL, 2051 reg: regInfo{ 2052 inputs: []inputInfo{ 2053 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2054 }, 2055 clobbers: 8589934592, // FLAGS 2056 outputs: []regMask{ 2057 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2058 }, 2059 }, 2060 }, 2061 { 2062 name: "XORBconst", 2063 auxType: auxInt8, 2064 argLen: 1, 2065 resultInArg0: true, 2066 asm: x86.AXORL, 2067 reg: regInfo{ 2068 inputs: []inputInfo{ 2069 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2070 }, 2071 clobbers: 8589934592, // FLAGS 2072 outputs: []regMask{ 2073 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2074 }, 2075 }, 2076 }, 2077 { 2078 name: "CMPQ", 2079 argLen: 2, 2080 asm: x86.ACMPQ, 2081 reg: regInfo{ 2082 inputs: []inputInfo{ 2083 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2084 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2085 }, 2086 outputs: []regMask{ 2087 8589934592, // FLAGS 2088 }, 2089 }, 2090 }, 2091 { 2092 name: "CMPL", 2093 argLen: 2, 2094 asm: x86.ACMPL, 2095 reg: regInfo{ 2096 inputs: []inputInfo{ 2097 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2098 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2099 }, 2100 outputs: []regMask{ 2101 8589934592, // FLAGS 2102 }, 2103 }, 2104 }, 2105 { 2106 name: "CMPW", 2107 argLen: 2, 2108 asm: x86.ACMPW, 2109 reg: regInfo{ 2110 inputs: []inputInfo{ 2111 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2112 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2113 }, 2114 outputs: []regMask{ 2115 8589934592, // FLAGS 2116 }, 2117 }, 2118 }, 2119 { 2120 name: "CMPB", 2121 argLen: 2, 2122 asm: x86.ACMPB, 2123 reg: regInfo{ 2124 inputs: []inputInfo{ 2125 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2126 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2127 }, 2128 outputs: []regMask{ 2129 8589934592, // FLAGS 2130 }, 2131 }, 2132 }, 2133 { 2134 name: "CMPQconst", 2135 auxType: auxInt64, 2136 argLen: 1, 2137 asm: x86.ACMPQ, 2138 reg: regInfo{ 2139 inputs: []inputInfo{ 2140 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2141 }, 2142 outputs: []regMask{ 2143 8589934592, // FLAGS 2144 }, 2145 }, 2146 }, 2147 { 2148 name: "CMPLconst", 2149 auxType: auxInt32, 2150 argLen: 1, 2151 asm: x86.ACMPL, 2152 reg: regInfo{ 2153 inputs: []inputInfo{ 2154 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2155 }, 2156 outputs: []regMask{ 2157 8589934592, // FLAGS 2158 }, 2159 }, 2160 }, 2161 { 2162 name: "CMPWconst", 2163 auxType: auxInt16, 2164 argLen: 1, 2165 asm: x86.ACMPW, 2166 reg: regInfo{ 2167 inputs: []inputInfo{ 2168 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2169 }, 2170 outputs: []regMask{ 2171 8589934592, // FLAGS 2172 }, 2173 }, 2174 }, 2175 { 2176 name: "CMPBconst", 2177 auxType: auxInt8, 2178 argLen: 1, 2179 asm: x86.ACMPB, 2180 reg: regInfo{ 2181 inputs: []inputInfo{ 2182 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2183 }, 2184 outputs: []regMask{ 2185 8589934592, // FLAGS 2186 }, 2187 }, 2188 }, 2189 { 2190 name: "UCOMISS", 2191 argLen: 2, 2192 asm: x86.AUCOMISS, 2193 reg: regInfo{ 2194 inputs: []inputInfo{ 2195 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 2196 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 2197 }, 2198 outputs: []regMask{ 2199 8589934592, // FLAGS 2200 }, 2201 }, 2202 }, 2203 { 2204 name: "UCOMISD", 2205 argLen: 2, 2206 asm: x86.AUCOMISD, 2207 reg: regInfo{ 2208 inputs: []inputInfo{ 2209 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 2210 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 2211 }, 2212 outputs: []regMask{ 2213 8589934592, // FLAGS 2214 }, 2215 }, 2216 }, 2217 { 2218 name: "TESTQ", 2219 argLen: 2, 2220 asm: x86.ATESTQ, 2221 reg: regInfo{ 2222 inputs: []inputInfo{ 2223 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2224 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2225 }, 2226 outputs: []regMask{ 2227 8589934592, // FLAGS 2228 }, 2229 }, 2230 }, 2231 { 2232 name: "TESTL", 2233 argLen: 2, 2234 asm: x86.ATESTL, 2235 reg: regInfo{ 2236 inputs: []inputInfo{ 2237 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2238 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2239 }, 2240 outputs: []regMask{ 2241 8589934592, // FLAGS 2242 }, 2243 }, 2244 }, 2245 { 2246 name: "TESTW", 2247 argLen: 2, 2248 asm: x86.ATESTW, 2249 reg: regInfo{ 2250 inputs: []inputInfo{ 2251 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2252 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2253 }, 2254 outputs: []regMask{ 2255 8589934592, // FLAGS 2256 }, 2257 }, 2258 }, 2259 { 2260 name: "TESTB", 2261 argLen: 2, 2262 asm: x86.ATESTB, 2263 reg: regInfo{ 2264 inputs: []inputInfo{ 2265 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2266 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2267 }, 2268 outputs: []regMask{ 2269 8589934592, // FLAGS 2270 }, 2271 }, 2272 }, 2273 { 2274 name: "TESTQconst", 2275 auxType: auxInt64, 2276 argLen: 1, 2277 asm: x86.ATESTQ, 2278 reg: regInfo{ 2279 inputs: []inputInfo{ 2280 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2281 }, 2282 outputs: []regMask{ 2283 8589934592, // FLAGS 2284 }, 2285 }, 2286 }, 2287 { 2288 name: "TESTLconst", 2289 auxType: auxInt32, 2290 argLen: 1, 2291 asm: x86.ATESTL, 2292 reg: regInfo{ 2293 inputs: []inputInfo{ 2294 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2295 }, 2296 outputs: []regMask{ 2297 8589934592, // FLAGS 2298 }, 2299 }, 2300 }, 2301 { 2302 name: "TESTWconst", 2303 auxType: auxInt16, 2304 argLen: 1, 2305 asm: x86.ATESTW, 2306 reg: regInfo{ 2307 inputs: []inputInfo{ 2308 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2309 }, 2310 outputs: []regMask{ 2311 8589934592, // FLAGS 2312 }, 2313 }, 2314 }, 2315 { 2316 name: "TESTBconst", 2317 auxType: auxInt8, 2318 argLen: 1, 2319 asm: x86.ATESTB, 2320 reg: regInfo{ 2321 inputs: []inputInfo{ 2322 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2323 }, 2324 outputs: []regMask{ 2325 8589934592, // FLAGS 2326 }, 2327 }, 2328 }, 2329 { 2330 name: "SHLQ", 2331 argLen: 2, 2332 resultInArg0: true, 2333 asm: x86.ASHLQ, 2334 reg: regInfo{ 2335 inputs: []inputInfo{ 2336 {1, 2}, // CX 2337 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2338 }, 2339 clobbers: 8589934592, // FLAGS 2340 outputs: []regMask{ 2341 65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2342 }, 2343 }, 2344 }, 2345 { 2346 name: "SHLL", 2347 argLen: 2, 2348 resultInArg0: true, 2349 asm: x86.ASHLL, 2350 reg: regInfo{ 2351 inputs: []inputInfo{ 2352 {1, 2}, // CX 2353 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2354 }, 2355 clobbers: 8589934592, // FLAGS 2356 outputs: []regMask{ 2357 65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2358 }, 2359 }, 2360 }, 2361 { 2362 name: "SHLW", 2363 argLen: 2, 2364 resultInArg0: true, 2365 asm: x86.ASHLL, 2366 reg: regInfo{ 2367 inputs: []inputInfo{ 2368 {1, 2}, // CX 2369 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2370 }, 2371 clobbers: 8589934592, // FLAGS 2372 outputs: []regMask{ 2373 65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2374 }, 2375 }, 2376 }, 2377 { 2378 name: "SHLB", 2379 argLen: 2, 2380 resultInArg0: true, 2381 asm: x86.ASHLL, 2382 reg: regInfo{ 2383 inputs: []inputInfo{ 2384 {1, 2}, // CX 2385 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2386 }, 2387 clobbers: 8589934592, // FLAGS 2388 outputs: []regMask{ 2389 65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2390 }, 2391 }, 2392 }, 2393 { 2394 name: "SHLQconst", 2395 auxType: auxInt64, 2396 argLen: 1, 2397 resultInArg0: true, 2398 asm: x86.ASHLQ, 2399 reg: regInfo{ 2400 inputs: []inputInfo{ 2401 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2402 }, 2403 clobbers: 8589934592, // FLAGS 2404 outputs: []regMask{ 2405 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2406 }, 2407 }, 2408 }, 2409 { 2410 name: "SHLLconst", 2411 auxType: auxInt32, 2412 argLen: 1, 2413 resultInArg0: true, 2414 asm: x86.ASHLL, 2415 reg: regInfo{ 2416 inputs: []inputInfo{ 2417 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2418 }, 2419 clobbers: 8589934592, // FLAGS 2420 outputs: []regMask{ 2421 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2422 }, 2423 }, 2424 }, 2425 { 2426 name: "SHLWconst", 2427 auxType: auxInt16, 2428 argLen: 1, 2429 resultInArg0: true, 2430 asm: x86.ASHLL, 2431 reg: regInfo{ 2432 inputs: []inputInfo{ 2433 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2434 }, 2435 clobbers: 8589934592, // FLAGS 2436 outputs: []regMask{ 2437 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2438 }, 2439 }, 2440 }, 2441 { 2442 name: "SHLBconst", 2443 auxType: auxInt8, 2444 argLen: 1, 2445 resultInArg0: true, 2446 asm: x86.ASHLL, 2447 reg: regInfo{ 2448 inputs: []inputInfo{ 2449 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2450 }, 2451 clobbers: 8589934592, // FLAGS 2452 outputs: []regMask{ 2453 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2454 }, 2455 }, 2456 }, 2457 { 2458 name: "SHRQ", 2459 argLen: 2, 2460 resultInArg0: true, 2461 asm: x86.ASHRQ, 2462 reg: regInfo{ 2463 inputs: []inputInfo{ 2464 {1, 2}, // CX 2465 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2466 }, 2467 clobbers: 8589934592, // FLAGS 2468 outputs: []regMask{ 2469 65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2470 }, 2471 }, 2472 }, 2473 { 2474 name: "SHRL", 2475 argLen: 2, 2476 resultInArg0: true, 2477 asm: x86.ASHRL, 2478 reg: regInfo{ 2479 inputs: []inputInfo{ 2480 {1, 2}, // CX 2481 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2482 }, 2483 clobbers: 8589934592, // FLAGS 2484 outputs: []regMask{ 2485 65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2486 }, 2487 }, 2488 }, 2489 { 2490 name: "SHRW", 2491 argLen: 2, 2492 resultInArg0: true, 2493 asm: x86.ASHRW, 2494 reg: regInfo{ 2495 inputs: []inputInfo{ 2496 {1, 2}, // CX 2497 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2498 }, 2499 clobbers: 8589934592, // FLAGS 2500 outputs: []regMask{ 2501 65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2502 }, 2503 }, 2504 }, 2505 { 2506 name: "SHRB", 2507 argLen: 2, 2508 resultInArg0: true, 2509 asm: x86.ASHRB, 2510 reg: regInfo{ 2511 inputs: []inputInfo{ 2512 {1, 2}, // CX 2513 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2514 }, 2515 clobbers: 8589934592, // FLAGS 2516 outputs: []regMask{ 2517 65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2518 }, 2519 }, 2520 }, 2521 { 2522 name: "SHRQconst", 2523 auxType: auxInt64, 2524 argLen: 1, 2525 resultInArg0: true, 2526 asm: x86.ASHRQ, 2527 reg: regInfo{ 2528 inputs: []inputInfo{ 2529 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2530 }, 2531 clobbers: 8589934592, // FLAGS 2532 outputs: []regMask{ 2533 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2534 }, 2535 }, 2536 }, 2537 { 2538 name: "SHRLconst", 2539 auxType: auxInt32, 2540 argLen: 1, 2541 resultInArg0: true, 2542 asm: x86.ASHRL, 2543 reg: regInfo{ 2544 inputs: []inputInfo{ 2545 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2546 }, 2547 clobbers: 8589934592, // FLAGS 2548 outputs: []regMask{ 2549 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2550 }, 2551 }, 2552 }, 2553 { 2554 name: "SHRWconst", 2555 auxType: auxInt16, 2556 argLen: 1, 2557 resultInArg0: true, 2558 asm: x86.ASHRW, 2559 reg: regInfo{ 2560 inputs: []inputInfo{ 2561 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2562 }, 2563 clobbers: 8589934592, // FLAGS 2564 outputs: []regMask{ 2565 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2566 }, 2567 }, 2568 }, 2569 { 2570 name: "SHRBconst", 2571 auxType: auxInt8, 2572 argLen: 1, 2573 resultInArg0: true, 2574 asm: x86.ASHRB, 2575 reg: regInfo{ 2576 inputs: []inputInfo{ 2577 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2578 }, 2579 clobbers: 8589934592, // FLAGS 2580 outputs: []regMask{ 2581 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2582 }, 2583 }, 2584 }, 2585 { 2586 name: "SARQ", 2587 argLen: 2, 2588 resultInArg0: true, 2589 asm: x86.ASARQ, 2590 reg: regInfo{ 2591 inputs: []inputInfo{ 2592 {1, 2}, // CX 2593 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2594 }, 2595 clobbers: 8589934592, // FLAGS 2596 outputs: []regMask{ 2597 65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2598 }, 2599 }, 2600 }, 2601 { 2602 name: "SARL", 2603 argLen: 2, 2604 resultInArg0: true, 2605 asm: x86.ASARL, 2606 reg: regInfo{ 2607 inputs: []inputInfo{ 2608 {1, 2}, // CX 2609 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2610 }, 2611 clobbers: 8589934592, // FLAGS 2612 outputs: []regMask{ 2613 65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2614 }, 2615 }, 2616 }, 2617 { 2618 name: "SARW", 2619 argLen: 2, 2620 resultInArg0: true, 2621 asm: x86.ASARW, 2622 reg: regInfo{ 2623 inputs: []inputInfo{ 2624 {1, 2}, // CX 2625 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2626 }, 2627 clobbers: 8589934592, // FLAGS 2628 outputs: []regMask{ 2629 65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2630 }, 2631 }, 2632 }, 2633 { 2634 name: "SARB", 2635 argLen: 2, 2636 resultInArg0: true, 2637 asm: x86.ASARB, 2638 reg: regInfo{ 2639 inputs: []inputInfo{ 2640 {1, 2}, // CX 2641 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2642 }, 2643 clobbers: 8589934592, // FLAGS 2644 outputs: []regMask{ 2645 65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2646 }, 2647 }, 2648 }, 2649 { 2650 name: "SARQconst", 2651 auxType: auxInt64, 2652 argLen: 1, 2653 resultInArg0: true, 2654 asm: x86.ASARQ, 2655 reg: regInfo{ 2656 inputs: []inputInfo{ 2657 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2658 }, 2659 clobbers: 8589934592, // FLAGS 2660 outputs: []regMask{ 2661 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2662 }, 2663 }, 2664 }, 2665 { 2666 name: "SARLconst", 2667 auxType: auxInt32, 2668 argLen: 1, 2669 resultInArg0: true, 2670 asm: x86.ASARL, 2671 reg: regInfo{ 2672 inputs: []inputInfo{ 2673 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2674 }, 2675 clobbers: 8589934592, // FLAGS 2676 outputs: []regMask{ 2677 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2678 }, 2679 }, 2680 }, 2681 { 2682 name: "SARWconst", 2683 auxType: auxInt16, 2684 argLen: 1, 2685 resultInArg0: true, 2686 asm: x86.ASARW, 2687 reg: regInfo{ 2688 inputs: []inputInfo{ 2689 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2690 }, 2691 clobbers: 8589934592, // FLAGS 2692 outputs: []regMask{ 2693 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2694 }, 2695 }, 2696 }, 2697 { 2698 name: "SARBconst", 2699 auxType: auxInt8, 2700 argLen: 1, 2701 resultInArg0: true, 2702 asm: x86.ASARB, 2703 reg: regInfo{ 2704 inputs: []inputInfo{ 2705 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2706 }, 2707 clobbers: 8589934592, // FLAGS 2708 outputs: []regMask{ 2709 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2710 }, 2711 }, 2712 }, 2713 { 2714 name: "ROLQconst", 2715 auxType: auxInt64, 2716 argLen: 1, 2717 resultInArg0: true, 2718 asm: x86.AROLQ, 2719 reg: regInfo{ 2720 inputs: []inputInfo{ 2721 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2722 }, 2723 clobbers: 8589934592, // FLAGS 2724 outputs: []regMask{ 2725 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2726 }, 2727 }, 2728 }, 2729 { 2730 name: "ROLLconst", 2731 auxType: auxInt32, 2732 argLen: 1, 2733 resultInArg0: true, 2734 asm: x86.AROLL, 2735 reg: regInfo{ 2736 inputs: []inputInfo{ 2737 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2738 }, 2739 clobbers: 8589934592, // FLAGS 2740 outputs: []regMask{ 2741 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2742 }, 2743 }, 2744 }, 2745 { 2746 name: "ROLWconst", 2747 auxType: auxInt16, 2748 argLen: 1, 2749 resultInArg0: true, 2750 asm: x86.AROLW, 2751 reg: regInfo{ 2752 inputs: []inputInfo{ 2753 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2754 }, 2755 clobbers: 8589934592, // FLAGS 2756 outputs: []regMask{ 2757 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2758 }, 2759 }, 2760 }, 2761 { 2762 name: "ROLBconst", 2763 auxType: auxInt8, 2764 argLen: 1, 2765 resultInArg0: true, 2766 asm: x86.AROLB, 2767 reg: regInfo{ 2768 inputs: []inputInfo{ 2769 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2770 }, 2771 clobbers: 8589934592, // FLAGS 2772 outputs: []regMask{ 2773 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2774 }, 2775 }, 2776 }, 2777 { 2778 name: "NEGQ", 2779 argLen: 1, 2780 resultInArg0: true, 2781 asm: x86.ANEGQ, 2782 reg: regInfo{ 2783 inputs: []inputInfo{ 2784 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2785 }, 2786 clobbers: 8589934592, // FLAGS 2787 outputs: []regMask{ 2788 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2789 }, 2790 }, 2791 }, 2792 { 2793 name: "NEGL", 2794 argLen: 1, 2795 resultInArg0: true, 2796 asm: x86.ANEGL, 2797 reg: regInfo{ 2798 inputs: []inputInfo{ 2799 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2800 }, 2801 clobbers: 8589934592, // FLAGS 2802 outputs: []regMask{ 2803 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2804 }, 2805 }, 2806 }, 2807 { 2808 name: "NEGW", 2809 argLen: 1, 2810 resultInArg0: true, 2811 asm: x86.ANEGL, 2812 reg: regInfo{ 2813 inputs: []inputInfo{ 2814 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2815 }, 2816 clobbers: 8589934592, // FLAGS 2817 outputs: []regMask{ 2818 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2819 }, 2820 }, 2821 }, 2822 { 2823 name: "NEGB", 2824 argLen: 1, 2825 resultInArg0: true, 2826 asm: x86.ANEGL, 2827 reg: regInfo{ 2828 inputs: []inputInfo{ 2829 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2830 }, 2831 clobbers: 8589934592, // FLAGS 2832 outputs: []regMask{ 2833 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2834 }, 2835 }, 2836 }, 2837 { 2838 name: "NOTQ", 2839 argLen: 1, 2840 resultInArg0: true, 2841 asm: x86.ANOTQ, 2842 reg: regInfo{ 2843 inputs: []inputInfo{ 2844 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2845 }, 2846 clobbers: 8589934592, // FLAGS 2847 outputs: []regMask{ 2848 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2849 }, 2850 }, 2851 }, 2852 { 2853 name: "NOTL", 2854 argLen: 1, 2855 resultInArg0: true, 2856 asm: x86.ANOTL, 2857 reg: regInfo{ 2858 inputs: []inputInfo{ 2859 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2860 }, 2861 clobbers: 8589934592, // FLAGS 2862 outputs: []regMask{ 2863 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2864 }, 2865 }, 2866 }, 2867 { 2868 name: "NOTW", 2869 argLen: 1, 2870 resultInArg0: true, 2871 asm: x86.ANOTL, 2872 reg: regInfo{ 2873 inputs: []inputInfo{ 2874 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2875 }, 2876 clobbers: 8589934592, // FLAGS 2877 outputs: []regMask{ 2878 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2879 }, 2880 }, 2881 }, 2882 { 2883 name: "NOTB", 2884 argLen: 1, 2885 resultInArg0: true, 2886 asm: x86.ANOTL, 2887 reg: regInfo{ 2888 inputs: []inputInfo{ 2889 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2890 }, 2891 clobbers: 8589934592, // FLAGS 2892 outputs: []regMask{ 2893 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2894 }, 2895 }, 2896 }, 2897 { 2898 name: "BSFQ", 2899 argLen: 1, 2900 asm: x86.ABSFQ, 2901 reg: regInfo{ 2902 inputs: []inputInfo{ 2903 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2904 }, 2905 clobbers: 8589934592, // FLAGS 2906 outputs: []regMask{ 2907 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2908 }, 2909 }, 2910 }, 2911 { 2912 name: "BSFL", 2913 argLen: 1, 2914 asm: x86.ABSFL, 2915 reg: regInfo{ 2916 inputs: []inputInfo{ 2917 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2918 }, 2919 clobbers: 8589934592, // FLAGS 2920 outputs: []regMask{ 2921 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2922 }, 2923 }, 2924 }, 2925 { 2926 name: "BSFW", 2927 argLen: 1, 2928 asm: x86.ABSFW, 2929 reg: regInfo{ 2930 inputs: []inputInfo{ 2931 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2932 }, 2933 clobbers: 8589934592, // FLAGS 2934 outputs: []regMask{ 2935 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2936 }, 2937 }, 2938 }, 2939 { 2940 name: "BSRQ", 2941 argLen: 1, 2942 asm: x86.ABSRQ, 2943 reg: regInfo{ 2944 inputs: []inputInfo{ 2945 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2946 }, 2947 clobbers: 8589934592, // FLAGS 2948 outputs: []regMask{ 2949 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2950 }, 2951 }, 2952 }, 2953 { 2954 name: "BSRL", 2955 argLen: 1, 2956 asm: x86.ABSRL, 2957 reg: regInfo{ 2958 inputs: []inputInfo{ 2959 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2960 }, 2961 clobbers: 8589934592, // FLAGS 2962 outputs: []regMask{ 2963 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2964 }, 2965 }, 2966 }, 2967 { 2968 name: "BSRW", 2969 argLen: 1, 2970 asm: x86.ABSRW, 2971 reg: regInfo{ 2972 inputs: []inputInfo{ 2973 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2974 }, 2975 clobbers: 8589934592, // FLAGS 2976 outputs: []regMask{ 2977 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2978 }, 2979 }, 2980 }, 2981 { 2982 name: "CMOVQEQconst", 2983 auxType: auxInt64, 2984 argLen: 2, 2985 resultInArg0: true, 2986 asm: x86.ACMOVQEQ, 2987 reg: regInfo{ 2988 inputs: []inputInfo{ 2989 {1, 8589934592}, // FLAGS 2990 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2991 }, 2992 clobbers: 8589934593, // AX FLAGS 2993 outputs: []regMask{ 2994 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 2995 }, 2996 }, 2997 }, 2998 { 2999 name: "CMOVLEQconst", 3000 auxType: auxInt32, 3001 argLen: 2, 3002 resultInArg0: true, 3003 asm: x86.ACMOVLEQ, 3004 reg: regInfo{ 3005 inputs: []inputInfo{ 3006 {1, 8589934592}, // FLAGS 3007 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3008 }, 3009 clobbers: 8589934593, // AX FLAGS 3010 outputs: []regMask{ 3011 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3012 }, 3013 }, 3014 }, 3015 { 3016 name: "CMOVWEQconst", 3017 auxType: auxInt16, 3018 argLen: 2, 3019 resultInArg0: true, 3020 asm: x86.ACMOVLEQ, 3021 reg: regInfo{ 3022 inputs: []inputInfo{ 3023 {1, 8589934592}, // FLAGS 3024 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3025 }, 3026 clobbers: 8589934593, // AX FLAGS 3027 outputs: []regMask{ 3028 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3029 }, 3030 }, 3031 }, 3032 { 3033 name: "CMOVQNEconst", 3034 auxType: auxInt64, 3035 argLen: 2, 3036 resultInArg0: true, 3037 asm: x86.ACMOVQNE, 3038 reg: regInfo{ 3039 inputs: []inputInfo{ 3040 {1, 8589934592}, // FLAGS 3041 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3042 }, 3043 clobbers: 8589934593, // AX FLAGS 3044 outputs: []regMask{ 3045 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3046 }, 3047 }, 3048 }, 3049 { 3050 name: "CMOVLNEconst", 3051 auxType: auxInt32, 3052 argLen: 2, 3053 resultInArg0: true, 3054 asm: x86.ACMOVLNE, 3055 reg: regInfo{ 3056 inputs: []inputInfo{ 3057 {1, 8589934592}, // FLAGS 3058 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3059 }, 3060 clobbers: 8589934593, // AX FLAGS 3061 outputs: []regMask{ 3062 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3063 }, 3064 }, 3065 }, 3066 { 3067 name: "CMOVWNEconst", 3068 auxType: auxInt16, 3069 argLen: 2, 3070 resultInArg0: true, 3071 asm: x86.ACMOVLNE, 3072 reg: regInfo{ 3073 inputs: []inputInfo{ 3074 {1, 8589934592}, // FLAGS 3075 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3076 }, 3077 clobbers: 8589934593, // AX FLAGS 3078 outputs: []regMask{ 3079 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3080 }, 3081 }, 3082 }, 3083 { 3084 name: "BSWAPQ", 3085 argLen: 1, 3086 resultInArg0: true, 3087 asm: x86.ABSWAPQ, 3088 reg: regInfo{ 3089 inputs: []inputInfo{ 3090 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3091 }, 3092 clobbers: 8589934592, // FLAGS 3093 outputs: []regMask{ 3094 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3095 }, 3096 }, 3097 }, 3098 { 3099 name: "BSWAPL", 3100 argLen: 1, 3101 resultInArg0: true, 3102 asm: x86.ABSWAPL, 3103 reg: regInfo{ 3104 inputs: []inputInfo{ 3105 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3106 }, 3107 clobbers: 8589934592, // FLAGS 3108 outputs: []regMask{ 3109 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3110 }, 3111 }, 3112 }, 3113 { 3114 name: "SQRTSD", 3115 argLen: 1, 3116 asm: x86.ASQRTSD, 3117 reg: regInfo{ 3118 inputs: []inputInfo{ 3119 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3120 }, 3121 outputs: []regMask{ 3122 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3123 }, 3124 }, 3125 }, 3126 { 3127 name: "SBBQcarrymask", 3128 argLen: 1, 3129 asm: x86.ASBBQ, 3130 reg: regInfo{ 3131 inputs: []inputInfo{ 3132 {0, 8589934592}, // FLAGS 3133 }, 3134 outputs: []regMask{ 3135 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3136 }, 3137 }, 3138 }, 3139 { 3140 name: "SBBLcarrymask", 3141 argLen: 1, 3142 asm: x86.ASBBL, 3143 reg: regInfo{ 3144 inputs: []inputInfo{ 3145 {0, 8589934592}, // FLAGS 3146 }, 3147 outputs: []regMask{ 3148 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3149 }, 3150 }, 3151 }, 3152 { 3153 name: "SETEQ", 3154 argLen: 1, 3155 asm: x86.ASETEQ, 3156 reg: regInfo{ 3157 inputs: []inputInfo{ 3158 {0, 8589934592}, // FLAGS 3159 }, 3160 outputs: []regMask{ 3161 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3162 }, 3163 }, 3164 }, 3165 { 3166 name: "SETNE", 3167 argLen: 1, 3168 asm: x86.ASETNE, 3169 reg: regInfo{ 3170 inputs: []inputInfo{ 3171 {0, 8589934592}, // FLAGS 3172 }, 3173 outputs: []regMask{ 3174 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3175 }, 3176 }, 3177 }, 3178 { 3179 name: "SETL", 3180 argLen: 1, 3181 asm: x86.ASETLT, 3182 reg: regInfo{ 3183 inputs: []inputInfo{ 3184 {0, 8589934592}, // FLAGS 3185 }, 3186 outputs: []regMask{ 3187 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3188 }, 3189 }, 3190 }, 3191 { 3192 name: "SETLE", 3193 argLen: 1, 3194 asm: x86.ASETLE, 3195 reg: regInfo{ 3196 inputs: []inputInfo{ 3197 {0, 8589934592}, // FLAGS 3198 }, 3199 outputs: []regMask{ 3200 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3201 }, 3202 }, 3203 }, 3204 { 3205 name: "SETG", 3206 argLen: 1, 3207 asm: x86.ASETGT, 3208 reg: regInfo{ 3209 inputs: []inputInfo{ 3210 {0, 8589934592}, // FLAGS 3211 }, 3212 outputs: []regMask{ 3213 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3214 }, 3215 }, 3216 }, 3217 { 3218 name: "SETGE", 3219 argLen: 1, 3220 asm: x86.ASETGE, 3221 reg: regInfo{ 3222 inputs: []inputInfo{ 3223 {0, 8589934592}, // FLAGS 3224 }, 3225 outputs: []regMask{ 3226 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3227 }, 3228 }, 3229 }, 3230 { 3231 name: "SETB", 3232 argLen: 1, 3233 asm: x86.ASETCS, 3234 reg: regInfo{ 3235 inputs: []inputInfo{ 3236 {0, 8589934592}, // FLAGS 3237 }, 3238 outputs: []regMask{ 3239 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3240 }, 3241 }, 3242 }, 3243 { 3244 name: "SETBE", 3245 argLen: 1, 3246 asm: x86.ASETLS, 3247 reg: regInfo{ 3248 inputs: []inputInfo{ 3249 {0, 8589934592}, // FLAGS 3250 }, 3251 outputs: []regMask{ 3252 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3253 }, 3254 }, 3255 }, 3256 { 3257 name: "SETA", 3258 argLen: 1, 3259 asm: x86.ASETHI, 3260 reg: regInfo{ 3261 inputs: []inputInfo{ 3262 {0, 8589934592}, // FLAGS 3263 }, 3264 outputs: []regMask{ 3265 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3266 }, 3267 }, 3268 }, 3269 { 3270 name: "SETAE", 3271 argLen: 1, 3272 asm: x86.ASETCC, 3273 reg: regInfo{ 3274 inputs: []inputInfo{ 3275 {0, 8589934592}, // FLAGS 3276 }, 3277 outputs: []regMask{ 3278 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3279 }, 3280 }, 3281 }, 3282 { 3283 name: "SETEQF", 3284 argLen: 1, 3285 asm: x86.ASETEQ, 3286 reg: regInfo{ 3287 inputs: []inputInfo{ 3288 {0, 8589934592}, // FLAGS 3289 }, 3290 clobbers: 8589934593, // AX FLAGS 3291 outputs: []regMask{ 3292 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3293 }, 3294 }, 3295 }, 3296 { 3297 name: "SETNEF", 3298 argLen: 1, 3299 asm: x86.ASETNE, 3300 reg: regInfo{ 3301 inputs: []inputInfo{ 3302 {0, 8589934592}, // FLAGS 3303 }, 3304 clobbers: 8589934593, // AX FLAGS 3305 outputs: []regMask{ 3306 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3307 }, 3308 }, 3309 }, 3310 { 3311 name: "SETORD", 3312 argLen: 1, 3313 asm: x86.ASETPC, 3314 reg: regInfo{ 3315 inputs: []inputInfo{ 3316 {0, 8589934592}, // FLAGS 3317 }, 3318 outputs: []regMask{ 3319 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3320 }, 3321 }, 3322 }, 3323 { 3324 name: "SETNAN", 3325 argLen: 1, 3326 asm: x86.ASETPS, 3327 reg: regInfo{ 3328 inputs: []inputInfo{ 3329 {0, 8589934592}, // FLAGS 3330 }, 3331 outputs: []regMask{ 3332 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3333 }, 3334 }, 3335 }, 3336 { 3337 name: "SETGF", 3338 argLen: 1, 3339 asm: x86.ASETHI, 3340 reg: regInfo{ 3341 inputs: []inputInfo{ 3342 {0, 8589934592}, // FLAGS 3343 }, 3344 outputs: []regMask{ 3345 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3346 }, 3347 }, 3348 }, 3349 { 3350 name: "SETGEF", 3351 argLen: 1, 3352 asm: x86.ASETCC, 3353 reg: regInfo{ 3354 inputs: []inputInfo{ 3355 {0, 8589934592}, // FLAGS 3356 }, 3357 outputs: []regMask{ 3358 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3359 }, 3360 }, 3361 }, 3362 { 3363 name: "MOVBQSX", 3364 argLen: 1, 3365 asm: x86.AMOVBQSX, 3366 reg: regInfo{ 3367 inputs: []inputInfo{ 3368 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3369 }, 3370 outputs: []regMask{ 3371 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3372 }, 3373 }, 3374 }, 3375 { 3376 name: "MOVBQZX", 3377 argLen: 1, 3378 asm: x86.AMOVBQZX, 3379 reg: regInfo{ 3380 inputs: []inputInfo{ 3381 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3382 }, 3383 outputs: []regMask{ 3384 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3385 }, 3386 }, 3387 }, 3388 { 3389 name: "MOVWQSX", 3390 argLen: 1, 3391 asm: x86.AMOVWQSX, 3392 reg: regInfo{ 3393 inputs: []inputInfo{ 3394 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3395 }, 3396 outputs: []regMask{ 3397 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3398 }, 3399 }, 3400 }, 3401 { 3402 name: "MOVWQZX", 3403 argLen: 1, 3404 asm: x86.AMOVWQZX, 3405 reg: regInfo{ 3406 inputs: []inputInfo{ 3407 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3408 }, 3409 outputs: []regMask{ 3410 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3411 }, 3412 }, 3413 }, 3414 { 3415 name: "MOVLQSX", 3416 argLen: 1, 3417 asm: x86.AMOVLQSX, 3418 reg: regInfo{ 3419 inputs: []inputInfo{ 3420 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3421 }, 3422 outputs: []regMask{ 3423 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3424 }, 3425 }, 3426 }, 3427 { 3428 name: "MOVLQZX", 3429 argLen: 1, 3430 asm: x86.AMOVLQZX, 3431 reg: regInfo{ 3432 inputs: []inputInfo{ 3433 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3434 }, 3435 outputs: []regMask{ 3436 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3437 }, 3438 }, 3439 }, 3440 { 3441 name: "MOVBconst", 3442 auxType: auxInt8, 3443 argLen: 0, 3444 rematerializeable: true, 3445 asm: x86.AMOVB, 3446 reg: regInfo{ 3447 outputs: []regMask{ 3448 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3449 }, 3450 }, 3451 }, 3452 { 3453 name: "MOVWconst", 3454 auxType: auxInt16, 3455 argLen: 0, 3456 rematerializeable: true, 3457 asm: x86.AMOVW, 3458 reg: regInfo{ 3459 outputs: []regMask{ 3460 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3461 }, 3462 }, 3463 }, 3464 { 3465 name: "MOVLconst", 3466 auxType: auxInt32, 3467 argLen: 0, 3468 rematerializeable: true, 3469 asm: x86.AMOVL, 3470 reg: regInfo{ 3471 outputs: []regMask{ 3472 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3473 }, 3474 }, 3475 }, 3476 { 3477 name: "MOVQconst", 3478 auxType: auxInt64, 3479 argLen: 0, 3480 rematerializeable: true, 3481 asm: x86.AMOVQ, 3482 reg: regInfo{ 3483 outputs: []regMask{ 3484 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3485 }, 3486 }, 3487 }, 3488 { 3489 name: "CVTTSD2SL", 3490 argLen: 1, 3491 asm: x86.ACVTTSD2SL, 3492 reg: regInfo{ 3493 inputs: []inputInfo{ 3494 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3495 }, 3496 outputs: []regMask{ 3497 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3498 }, 3499 }, 3500 }, 3501 { 3502 name: "CVTTSD2SQ", 3503 argLen: 1, 3504 asm: x86.ACVTTSD2SQ, 3505 reg: regInfo{ 3506 inputs: []inputInfo{ 3507 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3508 }, 3509 outputs: []regMask{ 3510 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3511 }, 3512 }, 3513 }, 3514 { 3515 name: "CVTTSS2SL", 3516 argLen: 1, 3517 asm: x86.ACVTTSS2SL, 3518 reg: regInfo{ 3519 inputs: []inputInfo{ 3520 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3521 }, 3522 outputs: []regMask{ 3523 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3524 }, 3525 }, 3526 }, 3527 { 3528 name: "CVTTSS2SQ", 3529 argLen: 1, 3530 asm: x86.ACVTTSS2SQ, 3531 reg: regInfo{ 3532 inputs: []inputInfo{ 3533 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3534 }, 3535 outputs: []regMask{ 3536 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3537 }, 3538 }, 3539 }, 3540 { 3541 name: "CVTSL2SS", 3542 argLen: 1, 3543 asm: x86.ACVTSL2SS, 3544 reg: regInfo{ 3545 inputs: []inputInfo{ 3546 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3547 }, 3548 outputs: []regMask{ 3549 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3550 }, 3551 }, 3552 }, 3553 { 3554 name: "CVTSL2SD", 3555 argLen: 1, 3556 asm: x86.ACVTSL2SD, 3557 reg: regInfo{ 3558 inputs: []inputInfo{ 3559 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3560 }, 3561 outputs: []regMask{ 3562 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3563 }, 3564 }, 3565 }, 3566 { 3567 name: "CVTSQ2SS", 3568 argLen: 1, 3569 asm: x86.ACVTSQ2SS, 3570 reg: regInfo{ 3571 inputs: []inputInfo{ 3572 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3573 }, 3574 outputs: []regMask{ 3575 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3576 }, 3577 }, 3578 }, 3579 { 3580 name: "CVTSQ2SD", 3581 argLen: 1, 3582 asm: x86.ACVTSQ2SD, 3583 reg: regInfo{ 3584 inputs: []inputInfo{ 3585 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3586 }, 3587 outputs: []regMask{ 3588 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3589 }, 3590 }, 3591 }, 3592 { 3593 name: "CVTSD2SS", 3594 argLen: 1, 3595 asm: x86.ACVTSD2SS, 3596 reg: regInfo{ 3597 inputs: []inputInfo{ 3598 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3599 }, 3600 outputs: []regMask{ 3601 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3602 }, 3603 }, 3604 }, 3605 { 3606 name: "CVTSS2SD", 3607 argLen: 1, 3608 asm: x86.ACVTSS2SD, 3609 reg: regInfo{ 3610 inputs: []inputInfo{ 3611 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3612 }, 3613 outputs: []regMask{ 3614 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3615 }, 3616 }, 3617 }, 3618 { 3619 name: "PXOR", 3620 argLen: 2, 3621 commutative: true, 3622 resultInArg0: true, 3623 asm: x86.APXOR, 3624 reg: regInfo{ 3625 inputs: []inputInfo{ 3626 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3627 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3628 }, 3629 outputs: []regMask{ 3630 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3631 }, 3632 }, 3633 }, 3634 { 3635 name: "LEAQ", 3636 auxType: auxSymOff, 3637 argLen: 1, 3638 rematerializeable: true, 3639 reg: regInfo{ 3640 inputs: []inputInfo{ 3641 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3642 }, 3643 outputs: []regMask{ 3644 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3645 }, 3646 }, 3647 }, 3648 { 3649 name: "LEAQ1", 3650 auxType: auxSymOff, 3651 argLen: 2, 3652 reg: regInfo{ 3653 inputs: []inputInfo{ 3654 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3655 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3656 }, 3657 outputs: []regMask{ 3658 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3659 }, 3660 }, 3661 }, 3662 { 3663 name: "LEAQ2", 3664 auxType: auxSymOff, 3665 argLen: 2, 3666 reg: regInfo{ 3667 inputs: []inputInfo{ 3668 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3669 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3670 }, 3671 outputs: []regMask{ 3672 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3673 }, 3674 }, 3675 }, 3676 { 3677 name: "LEAQ4", 3678 auxType: auxSymOff, 3679 argLen: 2, 3680 reg: regInfo{ 3681 inputs: []inputInfo{ 3682 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3683 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3684 }, 3685 outputs: []regMask{ 3686 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3687 }, 3688 }, 3689 }, 3690 { 3691 name: "LEAQ8", 3692 auxType: auxSymOff, 3693 argLen: 2, 3694 reg: regInfo{ 3695 inputs: []inputInfo{ 3696 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3697 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3698 }, 3699 outputs: []regMask{ 3700 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3701 }, 3702 }, 3703 }, 3704 { 3705 name: "MOVBload", 3706 auxType: auxSymOff, 3707 argLen: 2, 3708 asm: x86.AMOVBLZX, 3709 reg: regInfo{ 3710 inputs: []inputInfo{ 3711 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3712 }, 3713 outputs: []regMask{ 3714 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3715 }, 3716 }, 3717 }, 3718 { 3719 name: "MOVBQSXload", 3720 auxType: auxSymOff, 3721 argLen: 2, 3722 asm: x86.AMOVBQSX, 3723 reg: regInfo{ 3724 inputs: []inputInfo{ 3725 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3726 }, 3727 outputs: []regMask{ 3728 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3729 }, 3730 }, 3731 }, 3732 { 3733 name: "MOVWload", 3734 auxType: auxSymOff, 3735 argLen: 2, 3736 asm: x86.AMOVWLZX, 3737 reg: regInfo{ 3738 inputs: []inputInfo{ 3739 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3740 }, 3741 outputs: []regMask{ 3742 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3743 }, 3744 }, 3745 }, 3746 { 3747 name: "MOVWQSXload", 3748 auxType: auxSymOff, 3749 argLen: 2, 3750 asm: x86.AMOVWQSX, 3751 reg: regInfo{ 3752 inputs: []inputInfo{ 3753 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3754 }, 3755 outputs: []regMask{ 3756 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3757 }, 3758 }, 3759 }, 3760 { 3761 name: "MOVLload", 3762 auxType: auxSymOff, 3763 argLen: 2, 3764 asm: x86.AMOVL, 3765 reg: regInfo{ 3766 inputs: []inputInfo{ 3767 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3768 }, 3769 outputs: []regMask{ 3770 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3771 }, 3772 }, 3773 }, 3774 { 3775 name: "MOVLQSXload", 3776 auxType: auxSymOff, 3777 argLen: 2, 3778 asm: x86.AMOVLQSX, 3779 reg: regInfo{ 3780 inputs: []inputInfo{ 3781 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3782 }, 3783 outputs: []regMask{ 3784 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3785 }, 3786 }, 3787 }, 3788 { 3789 name: "MOVQload", 3790 auxType: auxSymOff, 3791 argLen: 2, 3792 asm: x86.AMOVQ, 3793 reg: regInfo{ 3794 inputs: []inputInfo{ 3795 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3796 }, 3797 outputs: []regMask{ 3798 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3799 }, 3800 }, 3801 }, 3802 { 3803 name: "MOVBstore", 3804 auxType: auxSymOff, 3805 argLen: 3, 3806 asm: x86.AMOVB, 3807 reg: regInfo{ 3808 inputs: []inputInfo{ 3809 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3810 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3811 }, 3812 }, 3813 }, 3814 { 3815 name: "MOVWstore", 3816 auxType: auxSymOff, 3817 argLen: 3, 3818 asm: x86.AMOVW, 3819 reg: regInfo{ 3820 inputs: []inputInfo{ 3821 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3822 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3823 }, 3824 }, 3825 }, 3826 { 3827 name: "MOVLstore", 3828 auxType: auxSymOff, 3829 argLen: 3, 3830 asm: x86.AMOVL, 3831 reg: regInfo{ 3832 inputs: []inputInfo{ 3833 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3834 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3835 }, 3836 }, 3837 }, 3838 { 3839 name: "MOVQstore", 3840 auxType: auxSymOff, 3841 argLen: 3, 3842 asm: x86.AMOVQ, 3843 reg: regInfo{ 3844 inputs: []inputInfo{ 3845 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3846 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3847 }, 3848 }, 3849 }, 3850 { 3851 name: "MOVOload", 3852 auxType: auxSymOff, 3853 argLen: 2, 3854 asm: x86.AMOVUPS, 3855 reg: regInfo{ 3856 inputs: []inputInfo{ 3857 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3858 }, 3859 outputs: []regMask{ 3860 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3861 }, 3862 }, 3863 }, 3864 { 3865 name: "MOVOstore", 3866 auxType: auxSymOff, 3867 argLen: 3, 3868 asm: x86.AMOVUPS, 3869 reg: regInfo{ 3870 inputs: []inputInfo{ 3871 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3872 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3873 }, 3874 }, 3875 }, 3876 { 3877 name: "MOVBloadidx1", 3878 auxType: auxSymOff, 3879 argLen: 3, 3880 asm: x86.AMOVBLZX, 3881 reg: regInfo{ 3882 inputs: []inputInfo{ 3883 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3884 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3885 }, 3886 outputs: []regMask{ 3887 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3888 }, 3889 }, 3890 }, 3891 { 3892 name: "MOVWloadidx1", 3893 auxType: auxSymOff, 3894 argLen: 3, 3895 asm: x86.AMOVWLZX, 3896 reg: regInfo{ 3897 inputs: []inputInfo{ 3898 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3899 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3900 }, 3901 outputs: []regMask{ 3902 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3903 }, 3904 }, 3905 }, 3906 { 3907 name: "MOVWloadidx2", 3908 auxType: auxSymOff, 3909 argLen: 3, 3910 asm: x86.AMOVWLZX, 3911 reg: regInfo{ 3912 inputs: []inputInfo{ 3913 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3914 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3915 }, 3916 outputs: []regMask{ 3917 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3918 }, 3919 }, 3920 }, 3921 { 3922 name: "MOVLloadidx1", 3923 auxType: auxSymOff, 3924 argLen: 3, 3925 asm: x86.AMOVL, 3926 reg: regInfo{ 3927 inputs: []inputInfo{ 3928 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3929 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3930 }, 3931 outputs: []regMask{ 3932 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3933 }, 3934 }, 3935 }, 3936 { 3937 name: "MOVLloadidx4", 3938 auxType: auxSymOff, 3939 argLen: 3, 3940 asm: x86.AMOVL, 3941 reg: regInfo{ 3942 inputs: []inputInfo{ 3943 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3944 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3945 }, 3946 outputs: []regMask{ 3947 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3948 }, 3949 }, 3950 }, 3951 { 3952 name: "MOVQloadidx1", 3953 auxType: auxSymOff, 3954 argLen: 3, 3955 asm: x86.AMOVQ, 3956 reg: regInfo{ 3957 inputs: []inputInfo{ 3958 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3959 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3960 }, 3961 outputs: []regMask{ 3962 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3963 }, 3964 }, 3965 }, 3966 { 3967 name: "MOVQloadidx8", 3968 auxType: auxSymOff, 3969 argLen: 3, 3970 asm: x86.AMOVQ, 3971 reg: regInfo{ 3972 inputs: []inputInfo{ 3973 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3974 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3975 }, 3976 outputs: []regMask{ 3977 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3978 }, 3979 }, 3980 }, 3981 { 3982 name: "MOVBstoreidx1", 3983 auxType: auxSymOff, 3984 argLen: 4, 3985 asm: x86.AMOVB, 3986 reg: regInfo{ 3987 inputs: []inputInfo{ 3988 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3989 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 3990 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 3991 }, 3992 }, 3993 }, 3994 { 3995 name: "MOVWstoreidx1", 3996 auxType: auxSymOff, 3997 argLen: 4, 3998 asm: x86.AMOVW, 3999 reg: regInfo{ 4000 inputs: []inputInfo{ 4001 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4002 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4003 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4004 }, 4005 }, 4006 }, 4007 { 4008 name: "MOVWstoreidx2", 4009 auxType: auxSymOff, 4010 argLen: 4, 4011 asm: x86.AMOVW, 4012 reg: regInfo{ 4013 inputs: []inputInfo{ 4014 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4015 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4016 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4017 }, 4018 }, 4019 }, 4020 { 4021 name: "MOVLstoreidx1", 4022 auxType: auxSymOff, 4023 argLen: 4, 4024 asm: x86.AMOVL, 4025 reg: regInfo{ 4026 inputs: []inputInfo{ 4027 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4028 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4029 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4030 }, 4031 }, 4032 }, 4033 { 4034 name: "MOVLstoreidx4", 4035 auxType: auxSymOff, 4036 argLen: 4, 4037 asm: x86.AMOVL, 4038 reg: regInfo{ 4039 inputs: []inputInfo{ 4040 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4041 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4042 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4043 }, 4044 }, 4045 }, 4046 { 4047 name: "MOVQstoreidx1", 4048 auxType: auxSymOff, 4049 argLen: 4, 4050 asm: x86.AMOVQ, 4051 reg: regInfo{ 4052 inputs: []inputInfo{ 4053 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4054 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4055 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4056 }, 4057 }, 4058 }, 4059 { 4060 name: "MOVQstoreidx8", 4061 auxType: auxSymOff, 4062 argLen: 4, 4063 asm: x86.AMOVQ, 4064 reg: regInfo{ 4065 inputs: []inputInfo{ 4066 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4067 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4068 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4069 }, 4070 }, 4071 }, 4072 { 4073 name: "MOVBstoreconst", 4074 auxType: auxSymValAndOff, 4075 argLen: 2, 4076 asm: x86.AMOVB, 4077 reg: regInfo{ 4078 inputs: []inputInfo{ 4079 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4080 }, 4081 }, 4082 }, 4083 { 4084 name: "MOVWstoreconst", 4085 auxType: auxSymValAndOff, 4086 argLen: 2, 4087 asm: x86.AMOVW, 4088 reg: regInfo{ 4089 inputs: []inputInfo{ 4090 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4091 }, 4092 }, 4093 }, 4094 { 4095 name: "MOVLstoreconst", 4096 auxType: auxSymValAndOff, 4097 argLen: 2, 4098 asm: x86.AMOVL, 4099 reg: regInfo{ 4100 inputs: []inputInfo{ 4101 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4102 }, 4103 }, 4104 }, 4105 { 4106 name: "MOVQstoreconst", 4107 auxType: auxSymValAndOff, 4108 argLen: 2, 4109 asm: x86.AMOVQ, 4110 reg: regInfo{ 4111 inputs: []inputInfo{ 4112 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4113 }, 4114 }, 4115 }, 4116 { 4117 name: "MOVBstoreconstidx1", 4118 auxType: auxSymValAndOff, 4119 argLen: 3, 4120 asm: x86.AMOVB, 4121 reg: regInfo{ 4122 inputs: []inputInfo{ 4123 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4124 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4125 }, 4126 }, 4127 }, 4128 { 4129 name: "MOVWstoreconstidx1", 4130 auxType: auxSymValAndOff, 4131 argLen: 3, 4132 asm: x86.AMOVW, 4133 reg: regInfo{ 4134 inputs: []inputInfo{ 4135 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4136 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4137 }, 4138 }, 4139 }, 4140 { 4141 name: "MOVWstoreconstidx2", 4142 auxType: auxSymValAndOff, 4143 argLen: 3, 4144 asm: x86.AMOVW, 4145 reg: regInfo{ 4146 inputs: []inputInfo{ 4147 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4148 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4149 }, 4150 }, 4151 }, 4152 { 4153 name: "MOVLstoreconstidx1", 4154 auxType: auxSymValAndOff, 4155 argLen: 3, 4156 asm: x86.AMOVL, 4157 reg: regInfo{ 4158 inputs: []inputInfo{ 4159 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4160 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4161 }, 4162 }, 4163 }, 4164 { 4165 name: "MOVLstoreconstidx4", 4166 auxType: auxSymValAndOff, 4167 argLen: 3, 4168 asm: x86.AMOVL, 4169 reg: regInfo{ 4170 inputs: []inputInfo{ 4171 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4172 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4173 }, 4174 }, 4175 }, 4176 { 4177 name: "MOVQstoreconstidx1", 4178 auxType: auxSymValAndOff, 4179 argLen: 3, 4180 asm: x86.AMOVQ, 4181 reg: regInfo{ 4182 inputs: []inputInfo{ 4183 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4184 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4185 }, 4186 }, 4187 }, 4188 { 4189 name: "MOVQstoreconstidx8", 4190 auxType: auxSymValAndOff, 4191 argLen: 3, 4192 asm: x86.AMOVQ, 4193 reg: regInfo{ 4194 inputs: []inputInfo{ 4195 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4196 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4197 }, 4198 }, 4199 }, 4200 { 4201 name: "DUFFZERO", 4202 auxType: auxInt64, 4203 argLen: 3, 4204 reg: regInfo{ 4205 inputs: []inputInfo{ 4206 {0, 128}, // DI 4207 {1, 65536}, // X0 4208 }, 4209 clobbers: 8589934720, // DI FLAGS 4210 }, 4211 }, 4212 { 4213 name: "MOVOconst", 4214 argLen: 0, 4215 rematerializeable: true, 4216 reg: regInfo{ 4217 outputs: []regMask{ 4218 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4219 }, 4220 }, 4221 }, 4222 { 4223 name: "REPSTOSQ", 4224 argLen: 4, 4225 reg: regInfo{ 4226 inputs: []inputInfo{ 4227 {0, 128}, // DI 4228 {1, 2}, // CX 4229 {2, 1}, // AX 4230 }, 4231 clobbers: 130, // CX DI 4232 }, 4233 }, 4234 { 4235 name: "CALLstatic", 4236 auxType: auxSymOff, 4237 argLen: 1, 4238 reg: regInfo{ 4239 clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS 4240 }, 4241 }, 4242 { 4243 name: "CALLclosure", 4244 auxType: auxInt64, 4245 argLen: 3, 4246 reg: regInfo{ 4247 inputs: []inputInfo{ 4248 {1, 4}, // DX 4249 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4250 }, 4251 clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS 4252 }, 4253 }, 4254 { 4255 name: "CALLdefer", 4256 auxType: auxInt64, 4257 argLen: 1, 4258 reg: regInfo{ 4259 clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS 4260 }, 4261 }, 4262 { 4263 name: "CALLgo", 4264 auxType: auxInt64, 4265 argLen: 1, 4266 reg: regInfo{ 4267 clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS 4268 }, 4269 }, 4270 { 4271 name: "CALLinter", 4272 auxType: auxInt64, 4273 argLen: 2, 4274 reg: regInfo{ 4275 inputs: []inputInfo{ 4276 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4277 }, 4278 clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS 4279 }, 4280 }, 4281 { 4282 name: "DUFFCOPY", 4283 auxType: auxInt64, 4284 argLen: 3, 4285 reg: regInfo{ 4286 inputs: []inputInfo{ 4287 {0, 128}, // DI 4288 {1, 64}, // SI 4289 }, 4290 clobbers: 8590000320, // SI DI X0 FLAGS 4291 }, 4292 }, 4293 { 4294 name: "REPMOVSQ", 4295 argLen: 4, 4296 reg: regInfo{ 4297 inputs: []inputInfo{ 4298 {0, 128}, // DI 4299 {1, 64}, // SI 4300 {2, 2}, // CX 4301 }, 4302 clobbers: 194, // CX SI DI 4303 }, 4304 }, 4305 { 4306 name: "InvertFlags", 4307 argLen: 1, 4308 reg: regInfo{}, 4309 }, 4310 { 4311 name: "LoweredGetG", 4312 argLen: 1, 4313 reg: regInfo{ 4314 outputs: []regMask{ 4315 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4316 }, 4317 }, 4318 }, 4319 { 4320 name: "LoweredGetClosurePtr", 4321 argLen: 0, 4322 reg: regInfo{ 4323 outputs: []regMask{ 4324 4, // DX 4325 }, 4326 }, 4327 }, 4328 { 4329 name: "LoweredNilCheck", 4330 argLen: 2, 4331 reg: regInfo{ 4332 inputs: []inputInfo{ 4333 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4334 }, 4335 clobbers: 8589934592, // FLAGS 4336 }, 4337 }, 4338 { 4339 name: "MOVQconvert", 4340 argLen: 2, 4341 asm: x86.AMOVQ, 4342 reg: regInfo{ 4343 inputs: []inputInfo{ 4344 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4345 }, 4346 outputs: []regMask{ 4347 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4348 }, 4349 }, 4350 }, 4351 { 4352 name: "FlagEQ", 4353 argLen: 0, 4354 reg: regInfo{}, 4355 }, 4356 { 4357 name: "FlagLT_ULT", 4358 argLen: 0, 4359 reg: regInfo{}, 4360 }, 4361 { 4362 name: "FlagLT_UGT", 4363 argLen: 0, 4364 reg: regInfo{}, 4365 }, 4366 { 4367 name: "FlagGT_UGT", 4368 argLen: 0, 4369 reg: regInfo{}, 4370 }, 4371 { 4372 name: "FlagGT_ULT", 4373 argLen: 0, 4374 reg: regInfo{}, 4375 }, 4376 4377 { 4378 name: "ADD", 4379 argLen: 2, 4380 commutative: true, 4381 asm: arm.AADD, 4382 reg: regInfo{ 4383 inputs: []inputInfo{ 4384 {0, 31}, // R0 R1 R2 R3 SP 4385 {1, 31}, // R0 R1 R2 R3 SP 4386 }, 4387 outputs: []regMask{ 4388 31, // R0 R1 R2 R3 SP 4389 }, 4390 }, 4391 }, 4392 { 4393 name: "ADDconst", 4394 auxType: auxSymOff, 4395 argLen: 1, 4396 asm: arm.AADD, 4397 reg: regInfo{ 4398 inputs: []inputInfo{ 4399 {0, 31}, // R0 R1 R2 R3 SP 4400 }, 4401 outputs: []regMask{ 4402 31, // R0 R1 R2 R3 SP 4403 }, 4404 }, 4405 }, 4406 { 4407 name: "MOVWconst", 4408 auxType: auxInt32, 4409 argLen: 0, 4410 rematerializeable: true, 4411 asm: arm.AMOVW, 4412 reg: regInfo{ 4413 outputs: []regMask{ 4414 31, // R0 R1 R2 R3 SP 4415 }, 4416 }, 4417 }, 4418 { 4419 name: "CMP", 4420 argLen: 2, 4421 asm: arm.ACMP, 4422 reg: regInfo{ 4423 inputs: []inputInfo{ 4424 {0, 31}, // R0 R1 R2 R3 SP 4425 {1, 31}, // R0 R1 R2 R3 SP 4426 }, 4427 outputs: []regMask{ 4428 32, // FLAGS 4429 }, 4430 }, 4431 }, 4432 { 4433 name: "MOVWload", 4434 argLen: 2, 4435 asm: arm.AMOVW, 4436 reg: regInfo{ 4437 inputs: []inputInfo{ 4438 {0, 31}, // R0 R1 R2 R3 SP 4439 }, 4440 outputs: []regMask{ 4441 31, // R0 R1 R2 R3 SP 4442 }, 4443 }, 4444 }, 4445 { 4446 name: "MOVWstore", 4447 argLen: 3, 4448 asm: arm.AMOVW, 4449 reg: regInfo{ 4450 inputs: []inputInfo{ 4451 {0, 31}, // R0 R1 R2 R3 SP 4452 {1, 31}, // R0 R1 R2 R3 SP 4453 }, 4454 }, 4455 }, 4456 { 4457 name: "CALLstatic", 4458 auxType: auxSymOff, 4459 argLen: 1, 4460 reg: regInfo{ 4461 clobbers: 15, // R0 R1 R2 R3 4462 }, 4463 }, 4464 { 4465 name: "LessThan", 4466 argLen: 2, 4467 reg: regInfo{ 4468 inputs: []inputInfo{ 4469 {0, 32}, // FLAGS 4470 }, 4471 outputs: []regMask{ 4472 31, // R0 R1 R2 R3 SP 4473 }, 4474 }, 4475 }, 4476 4477 { 4478 name: "Add8", 4479 argLen: 2, 4480 commutative: true, 4481 generic: true, 4482 }, 4483 { 4484 name: "Add16", 4485 argLen: 2, 4486 commutative: true, 4487 generic: true, 4488 }, 4489 { 4490 name: "Add32", 4491 argLen: 2, 4492 commutative: true, 4493 generic: true, 4494 }, 4495 { 4496 name: "Add64", 4497 argLen: 2, 4498 commutative: true, 4499 generic: true, 4500 }, 4501 { 4502 name: "AddPtr", 4503 argLen: 2, 4504 generic: true, 4505 }, 4506 { 4507 name: "Add32F", 4508 argLen: 2, 4509 generic: true, 4510 }, 4511 { 4512 name: "Add64F", 4513 argLen: 2, 4514 generic: true, 4515 }, 4516 { 4517 name: "Sub8", 4518 argLen: 2, 4519 generic: true, 4520 }, 4521 { 4522 name: "Sub16", 4523 argLen: 2, 4524 generic: true, 4525 }, 4526 { 4527 name: "Sub32", 4528 argLen: 2, 4529 generic: true, 4530 }, 4531 { 4532 name: "Sub64", 4533 argLen: 2, 4534 generic: true, 4535 }, 4536 { 4537 name: "SubPtr", 4538 argLen: 2, 4539 generic: true, 4540 }, 4541 { 4542 name: "Sub32F", 4543 argLen: 2, 4544 generic: true, 4545 }, 4546 { 4547 name: "Sub64F", 4548 argLen: 2, 4549 generic: true, 4550 }, 4551 { 4552 name: "Mul8", 4553 argLen: 2, 4554 commutative: true, 4555 generic: true, 4556 }, 4557 { 4558 name: "Mul16", 4559 argLen: 2, 4560 commutative: true, 4561 generic: true, 4562 }, 4563 { 4564 name: "Mul32", 4565 argLen: 2, 4566 commutative: true, 4567 generic: true, 4568 }, 4569 { 4570 name: "Mul64", 4571 argLen: 2, 4572 commutative: true, 4573 generic: true, 4574 }, 4575 { 4576 name: "Mul32F", 4577 argLen: 2, 4578 generic: true, 4579 }, 4580 { 4581 name: "Mul64F", 4582 argLen: 2, 4583 generic: true, 4584 }, 4585 { 4586 name: "Div32F", 4587 argLen: 2, 4588 generic: true, 4589 }, 4590 { 4591 name: "Div64F", 4592 argLen: 2, 4593 generic: true, 4594 }, 4595 { 4596 name: "Hmul8", 4597 argLen: 2, 4598 generic: true, 4599 }, 4600 { 4601 name: "Hmul8u", 4602 argLen: 2, 4603 generic: true, 4604 }, 4605 { 4606 name: "Hmul16", 4607 argLen: 2, 4608 generic: true, 4609 }, 4610 { 4611 name: "Hmul16u", 4612 argLen: 2, 4613 generic: true, 4614 }, 4615 { 4616 name: "Hmul32", 4617 argLen: 2, 4618 generic: true, 4619 }, 4620 { 4621 name: "Hmul32u", 4622 argLen: 2, 4623 generic: true, 4624 }, 4625 { 4626 name: "Hmul64", 4627 argLen: 2, 4628 generic: true, 4629 }, 4630 { 4631 name: "Hmul64u", 4632 argLen: 2, 4633 generic: true, 4634 }, 4635 { 4636 name: "Avg64u", 4637 argLen: 2, 4638 generic: true, 4639 }, 4640 { 4641 name: "Div8", 4642 argLen: 2, 4643 generic: true, 4644 }, 4645 { 4646 name: "Div8u", 4647 argLen: 2, 4648 generic: true, 4649 }, 4650 { 4651 name: "Div16", 4652 argLen: 2, 4653 generic: true, 4654 }, 4655 { 4656 name: "Div16u", 4657 argLen: 2, 4658 generic: true, 4659 }, 4660 { 4661 name: "Div32", 4662 argLen: 2, 4663 generic: true, 4664 }, 4665 { 4666 name: "Div32u", 4667 argLen: 2, 4668 generic: true, 4669 }, 4670 { 4671 name: "Div64", 4672 argLen: 2, 4673 generic: true, 4674 }, 4675 { 4676 name: "Div64u", 4677 argLen: 2, 4678 generic: true, 4679 }, 4680 { 4681 name: "Mod8", 4682 argLen: 2, 4683 generic: true, 4684 }, 4685 { 4686 name: "Mod8u", 4687 argLen: 2, 4688 generic: true, 4689 }, 4690 { 4691 name: "Mod16", 4692 argLen: 2, 4693 generic: true, 4694 }, 4695 { 4696 name: "Mod16u", 4697 argLen: 2, 4698 generic: true, 4699 }, 4700 { 4701 name: "Mod32", 4702 argLen: 2, 4703 generic: true, 4704 }, 4705 { 4706 name: "Mod32u", 4707 argLen: 2, 4708 generic: true, 4709 }, 4710 { 4711 name: "Mod64", 4712 argLen: 2, 4713 generic: true, 4714 }, 4715 { 4716 name: "Mod64u", 4717 argLen: 2, 4718 generic: true, 4719 }, 4720 { 4721 name: "And8", 4722 argLen: 2, 4723 commutative: true, 4724 generic: true, 4725 }, 4726 { 4727 name: "And16", 4728 argLen: 2, 4729 commutative: true, 4730 generic: true, 4731 }, 4732 { 4733 name: "And32", 4734 argLen: 2, 4735 commutative: true, 4736 generic: true, 4737 }, 4738 { 4739 name: "And64", 4740 argLen: 2, 4741 commutative: true, 4742 generic: true, 4743 }, 4744 { 4745 name: "Or8", 4746 argLen: 2, 4747 commutative: true, 4748 generic: true, 4749 }, 4750 { 4751 name: "Or16", 4752 argLen: 2, 4753 commutative: true, 4754 generic: true, 4755 }, 4756 { 4757 name: "Or32", 4758 argLen: 2, 4759 commutative: true, 4760 generic: true, 4761 }, 4762 { 4763 name: "Or64", 4764 argLen: 2, 4765 commutative: true, 4766 generic: true, 4767 }, 4768 { 4769 name: "Xor8", 4770 argLen: 2, 4771 commutative: true, 4772 generic: true, 4773 }, 4774 { 4775 name: "Xor16", 4776 argLen: 2, 4777 commutative: true, 4778 generic: true, 4779 }, 4780 { 4781 name: "Xor32", 4782 argLen: 2, 4783 commutative: true, 4784 generic: true, 4785 }, 4786 { 4787 name: "Xor64", 4788 argLen: 2, 4789 commutative: true, 4790 generic: true, 4791 }, 4792 { 4793 name: "Lsh8x8", 4794 argLen: 2, 4795 generic: true, 4796 }, 4797 { 4798 name: "Lsh8x16", 4799 argLen: 2, 4800 generic: true, 4801 }, 4802 { 4803 name: "Lsh8x32", 4804 argLen: 2, 4805 generic: true, 4806 }, 4807 { 4808 name: "Lsh8x64", 4809 argLen: 2, 4810 generic: true, 4811 }, 4812 { 4813 name: "Lsh16x8", 4814 argLen: 2, 4815 generic: true, 4816 }, 4817 { 4818 name: "Lsh16x16", 4819 argLen: 2, 4820 generic: true, 4821 }, 4822 { 4823 name: "Lsh16x32", 4824 argLen: 2, 4825 generic: true, 4826 }, 4827 { 4828 name: "Lsh16x64", 4829 argLen: 2, 4830 generic: true, 4831 }, 4832 { 4833 name: "Lsh32x8", 4834 argLen: 2, 4835 generic: true, 4836 }, 4837 { 4838 name: "Lsh32x16", 4839 argLen: 2, 4840 generic: true, 4841 }, 4842 { 4843 name: "Lsh32x32", 4844 argLen: 2, 4845 generic: true, 4846 }, 4847 { 4848 name: "Lsh32x64", 4849 argLen: 2, 4850 generic: true, 4851 }, 4852 { 4853 name: "Lsh64x8", 4854 argLen: 2, 4855 generic: true, 4856 }, 4857 { 4858 name: "Lsh64x16", 4859 argLen: 2, 4860 generic: true, 4861 }, 4862 { 4863 name: "Lsh64x32", 4864 argLen: 2, 4865 generic: true, 4866 }, 4867 { 4868 name: "Lsh64x64", 4869 argLen: 2, 4870 generic: true, 4871 }, 4872 { 4873 name: "Rsh8x8", 4874 argLen: 2, 4875 generic: true, 4876 }, 4877 { 4878 name: "Rsh8x16", 4879 argLen: 2, 4880 generic: true, 4881 }, 4882 { 4883 name: "Rsh8x32", 4884 argLen: 2, 4885 generic: true, 4886 }, 4887 { 4888 name: "Rsh8x64", 4889 argLen: 2, 4890 generic: true, 4891 }, 4892 { 4893 name: "Rsh16x8", 4894 argLen: 2, 4895 generic: true, 4896 }, 4897 { 4898 name: "Rsh16x16", 4899 argLen: 2, 4900 generic: true, 4901 }, 4902 { 4903 name: "Rsh16x32", 4904 argLen: 2, 4905 generic: true, 4906 }, 4907 { 4908 name: "Rsh16x64", 4909 argLen: 2, 4910 generic: true, 4911 }, 4912 { 4913 name: "Rsh32x8", 4914 argLen: 2, 4915 generic: true, 4916 }, 4917 { 4918 name: "Rsh32x16", 4919 argLen: 2, 4920 generic: true, 4921 }, 4922 { 4923 name: "Rsh32x32", 4924 argLen: 2, 4925 generic: true, 4926 }, 4927 { 4928 name: "Rsh32x64", 4929 argLen: 2, 4930 generic: true, 4931 }, 4932 { 4933 name: "Rsh64x8", 4934 argLen: 2, 4935 generic: true, 4936 }, 4937 { 4938 name: "Rsh64x16", 4939 argLen: 2, 4940 generic: true, 4941 }, 4942 { 4943 name: "Rsh64x32", 4944 argLen: 2, 4945 generic: true, 4946 }, 4947 { 4948 name: "Rsh64x64", 4949 argLen: 2, 4950 generic: true, 4951 }, 4952 { 4953 name: "Rsh8Ux8", 4954 argLen: 2, 4955 generic: true, 4956 }, 4957 { 4958 name: "Rsh8Ux16", 4959 argLen: 2, 4960 generic: true, 4961 }, 4962 { 4963 name: "Rsh8Ux32", 4964 argLen: 2, 4965 generic: true, 4966 }, 4967 { 4968 name: "Rsh8Ux64", 4969 argLen: 2, 4970 generic: true, 4971 }, 4972 { 4973 name: "Rsh16Ux8", 4974 argLen: 2, 4975 generic: true, 4976 }, 4977 { 4978 name: "Rsh16Ux16", 4979 argLen: 2, 4980 generic: true, 4981 }, 4982 { 4983 name: "Rsh16Ux32", 4984 argLen: 2, 4985 generic: true, 4986 }, 4987 { 4988 name: "Rsh16Ux64", 4989 argLen: 2, 4990 generic: true, 4991 }, 4992 { 4993 name: "Rsh32Ux8", 4994 argLen: 2, 4995 generic: true, 4996 }, 4997 { 4998 name: "Rsh32Ux16", 4999 argLen: 2, 5000 generic: true, 5001 }, 5002 { 5003 name: "Rsh32Ux32", 5004 argLen: 2, 5005 generic: true, 5006 }, 5007 { 5008 name: "Rsh32Ux64", 5009 argLen: 2, 5010 generic: true, 5011 }, 5012 { 5013 name: "Rsh64Ux8", 5014 argLen: 2, 5015 generic: true, 5016 }, 5017 { 5018 name: "Rsh64Ux16", 5019 argLen: 2, 5020 generic: true, 5021 }, 5022 { 5023 name: "Rsh64Ux32", 5024 argLen: 2, 5025 generic: true, 5026 }, 5027 { 5028 name: "Rsh64Ux64", 5029 argLen: 2, 5030 generic: true, 5031 }, 5032 { 5033 name: "Lrot8", 5034 auxType: auxInt64, 5035 argLen: 1, 5036 generic: true, 5037 }, 5038 { 5039 name: "Lrot16", 5040 auxType: auxInt64, 5041 argLen: 1, 5042 generic: true, 5043 }, 5044 { 5045 name: "Lrot32", 5046 auxType: auxInt64, 5047 argLen: 1, 5048 generic: true, 5049 }, 5050 { 5051 name: "Lrot64", 5052 auxType: auxInt64, 5053 argLen: 1, 5054 generic: true, 5055 }, 5056 { 5057 name: "Eq8", 5058 argLen: 2, 5059 commutative: true, 5060 generic: true, 5061 }, 5062 { 5063 name: "Eq16", 5064 argLen: 2, 5065 commutative: true, 5066 generic: true, 5067 }, 5068 { 5069 name: "Eq32", 5070 argLen: 2, 5071 commutative: true, 5072 generic: true, 5073 }, 5074 { 5075 name: "Eq64", 5076 argLen: 2, 5077 commutative: true, 5078 generic: true, 5079 }, 5080 { 5081 name: "EqPtr", 5082 argLen: 2, 5083 commutative: true, 5084 generic: true, 5085 }, 5086 { 5087 name: "EqInter", 5088 argLen: 2, 5089 generic: true, 5090 }, 5091 { 5092 name: "EqSlice", 5093 argLen: 2, 5094 generic: true, 5095 }, 5096 { 5097 name: "Eq32F", 5098 argLen: 2, 5099 generic: true, 5100 }, 5101 { 5102 name: "Eq64F", 5103 argLen: 2, 5104 generic: true, 5105 }, 5106 { 5107 name: "Neq8", 5108 argLen: 2, 5109 commutative: true, 5110 generic: true, 5111 }, 5112 { 5113 name: "Neq16", 5114 argLen: 2, 5115 commutative: true, 5116 generic: true, 5117 }, 5118 { 5119 name: "Neq32", 5120 argLen: 2, 5121 commutative: true, 5122 generic: true, 5123 }, 5124 { 5125 name: "Neq64", 5126 argLen: 2, 5127 commutative: true, 5128 generic: true, 5129 }, 5130 { 5131 name: "NeqPtr", 5132 argLen: 2, 5133 commutative: true, 5134 generic: true, 5135 }, 5136 { 5137 name: "NeqInter", 5138 argLen: 2, 5139 generic: true, 5140 }, 5141 { 5142 name: "NeqSlice", 5143 argLen: 2, 5144 generic: true, 5145 }, 5146 { 5147 name: "Neq32F", 5148 argLen: 2, 5149 generic: true, 5150 }, 5151 { 5152 name: "Neq64F", 5153 argLen: 2, 5154 generic: true, 5155 }, 5156 { 5157 name: "Less8", 5158 argLen: 2, 5159 generic: true, 5160 }, 5161 { 5162 name: "Less8U", 5163 argLen: 2, 5164 generic: true, 5165 }, 5166 { 5167 name: "Less16", 5168 argLen: 2, 5169 generic: true, 5170 }, 5171 { 5172 name: "Less16U", 5173 argLen: 2, 5174 generic: true, 5175 }, 5176 { 5177 name: "Less32", 5178 argLen: 2, 5179 generic: true, 5180 }, 5181 { 5182 name: "Less32U", 5183 argLen: 2, 5184 generic: true, 5185 }, 5186 { 5187 name: "Less64", 5188 argLen: 2, 5189 generic: true, 5190 }, 5191 { 5192 name: "Less64U", 5193 argLen: 2, 5194 generic: true, 5195 }, 5196 { 5197 name: "Less32F", 5198 argLen: 2, 5199 generic: true, 5200 }, 5201 { 5202 name: "Less64F", 5203 argLen: 2, 5204 generic: true, 5205 }, 5206 { 5207 name: "Leq8", 5208 argLen: 2, 5209 generic: true, 5210 }, 5211 { 5212 name: "Leq8U", 5213 argLen: 2, 5214 generic: true, 5215 }, 5216 { 5217 name: "Leq16", 5218 argLen: 2, 5219 generic: true, 5220 }, 5221 { 5222 name: "Leq16U", 5223 argLen: 2, 5224 generic: true, 5225 }, 5226 { 5227 name: "Leq32", 5228 argLen: 2, 5229 generic: true, 5230 }, 5231 { 5232 name: "Leq32U", 5233 argLen: 2, 5234 generic: true, 5235 }, 5236 { 5237 name: "Leq64", 5238 argLen: 2, 5239 generic: true, 5240 }, 5241 { 5242 name: "Leq64U", 5243 argLen: 2, 5244 generic: true, 5245 }, 5246 { 5247 name: "Leq32F", 5248 argLen: 2, 5249 generic: true, 5250 }, 5251 { 5252 name: "Leq64F", 5253 argLen: 2, 5254 generic: true, 5255 }, 5256 { 5257 name: "Greater8", 5258 argLen: 2, 5259 generic: true, 5260 }, 5261 { 5262 name: "Greater8U", 5263 argLen: 2, 5264 generic: true, 5265 }, 5266 { 5267 name: "Greater16", 5268 argLen: 2, 5269 generic: true, 5270 }, 5271 { 5272 name: "Greater16U", 5273 argLen: 2, 5274 generic: true, 5275 }, 5276 { 5277 name: "Greater32", 5278 argLen: 2, 5279 generic: true, 5280 }, 5281 { 5282 name: "Greater32U", 5283 argLen: 2, 5284 generic: true, 5285 }, 5286 { 5287 name: "Greater64", 5288 argLen: 2, 5289 generic: true, 5290 }, 5291 { 5292 name: "Greater64U", 5293 argLen: 2, 5294 generic: true, 5295 }, 5296 { 5297 name: "Greater32F", 5298 argLen: 2, 5299 generic: true, 5300 }, 5301 { 5302 name: "Greater64F", 5303 argLen: 2, 5304 generic: true, 5305 }, 5306 { 5307 name: "Geq8", 5308 argLen: 2, 5309 generic: true, 5310 }, 5311 { 5312 name: "Geq8U", 5313 argLen: 2, 5314 generic: true, 5315 }, 5316 { 5317 name: "Geq16", 5318 argLen: 2, 5319 generic: true, 5320 }, 5321 { 5322 name: "Geq16U", 5323 argLen: 2, 5324 generic: true, 5325 }, 5326 { 5327 name: "Geq32", 5328 argLen: 2, 5329 generic: true, 5330 }, 5331 { 5332 name: "Geq32U", 5333 argLen: 2, 5334 generic: true, 5335 }, 5336 { 5337 name: "Geq64", 5338 argLen: 2, 5339 generic: true, 5340 }, 5341 { 5342 name: "Geq64U", 5343 argLen: 2, 5344 generic: true, 5345 }, 5346 { 5347 name: "Geq32F", 5348 argLen: 2, 5349 generic: true, 5350 }, 5351 { 5352 name: "Geq64F", 5353 argLen: 2, 5354 generic: true, 5355 }, 5356 { 5357 name: "Not", 5358 argLen: 1, 5359 generic: true, 5360 }, 5361 { 5362 name: "Neg8", 5363 argLen: 1, 5364 generic: true, 5365 }, 5366 { 5367 name: "Neg16", 5368 argLen: 1, 5369 generic: true, 5370 }, 5371 { 5372 name: "Neg32", 5373 argLen: 1, 5374 generic: true, 5375 }, 5376 { 5377 name: "Neg64", 5378 argLen: 1, 5379 generic: true, 5380 }, 5381 { 5382 name: "Neg32F", 5383 argLen: 1, 5384 generic: true, 5385 }, 5386 { 5387 name: "Neg64F", 5388 argLen: 1, 5389 generic: true, 5390 }, 5391 { 5392 name: "Com8", 5393 argLen: 1, 5394 generic: true, 5395 }, 5396 { 5397 name: "Com16", 5398 argLen: 1, 5399 generic: true, 5400 }, 5401 { 5402 name: "Com32", 5403 argLen: 1, 5404 generic: true, 5405 }, 5406 { 5407 name: "Com64", 5408 argLen: 1, 5409 generic: true, 5410 }, 5411 { 5412 name: "Ctz16", 5413 argLen: 1, 5414 generic: true, 5415 }, 5416 { 5417 name: "Ctz32", 5418 argLen: 1, 5419 generic: true, 5420 }, 5421 { 5422 name: "Ctz64", 5423 argLen: 1, 5424 generic: true, 5425 }, 5426 { 5427 name: "Clz16", 5428 argLen: 1, 5429 generic: true, 5430 }, 5431 { 5432 name: "Clz32", 5433 argLen: 1, 5434 generic: true, 5435 }, 5436 { 5437 name: "Clz64", 5438 argLen: 1, 5439 generic: true, 5440 }, 5441 { 5442 name: "Bswap32", 5443 argLen: 1, 5444 generic: true, 5445 }, 5446 { 5447 name: "Bswap64", 5448 argLen: 1, 5449 generic: true, 5450 }, 5451 { 5452 name: "Sqrt", 5453 argLen: 1, 5454 generic: true, 5455 }, 5456 { 5457 name: "Phi", 5458 argLen: -1, 5459 generic: true, 5460 }, 5461 { 5462 name: "Copy", 5463 argLen: 1, 5464 generic: true, 5465 }, 5466 { 5467 name: "Convert", 5468 argLen: 2, 5469 generic: true, 5470 }, 5471 { 5472 name: "ConstBool", 5473 auxType: auxBool, 5474 argLen: 0, 5475 generic: true, 5476 }, 5477 { 5478 name: "ConstString", 5479 auxType: auxString, 5480 argLen: 0, 5481 generic: true, 5482 }, 5483 { 5484 name: "ConstNil", 5485 argLen: 0, 5486 generic: true, 5487 }, 5488 { 5489 name: "Const8", 5490 auxType: auxInt8, 5491 argLen: 0, 5492 generic: true, 5493 }, 5494 { 5495 name: "Const16", 5496 auxType: auxInt16, 5497 argLen: 0, 5498 generic: true, 5499 }, 5500 { 5501 name: "Const32", 5502 auxType: auxInt32, 5503 argLen: 0, 5504 generic: true, 5505 }, 5506 { 5507 name: "Const64", 5508 auxType: auxInt64, 5509 argLen: 0, 5510 generic: true, 5511 }, 5512 { 5513 name: "Const32F", 5514 auxType: auxFloat32, 5515 argLen: 0, 5516 generic: true, 5517 }, 5518 { 5519 name: "Const64F", 5520 auxType: auxFloat64, 5521 argLen: 0, 5522 generic: true, 5523 }, 5524 { 5525 name: "ConstInterface", 5526 argLen: 0, 5527 generic: true, 5528 }, 5529 { 5530 name: "ConstSlice", 5531 argLen: 0, 5532 generic: true, 5533 }, 5534 { 5535 name: "InitMem", 5536 argLen: 0, 5537 generic: true, 5538 }, 5539 { 5540 name: "Arg", 5541 auxType: auxSymOff, 5542 argLen: 0, 5543 generic: true, 5544 }, 5545 { 5546 name: "Addr", 5547 auxType: auxSym, 5548 argLen: 1, 5549 generic: true, 5550 }, 5551 { 5552 name: "SP", 5553 argLen: 0, 5554 generic: true, 5555 }, 5556 { 5557 name: "SB", 5558 argLen: 0, 5559 generic: true, 5560 }, 5561 { 5562 name: "Func", 5563 auxType: auxSym, 5564 argLen: 0, 5565 generic: true, 5566 }, 5567 { 5568 name: "Load", 5569 argLen: 2, 5570 generic: true, 5571 }, 5572 { 5573 name: "Store", 5574 auxType: auxInt64, 5575 argLen: 3, 5576 generic: true, 5577 }, 5578 { 5579 name: "Move", 5580 auxType: auxInt64, 5581 argLen: 3, 5582 generic: true, 5583 }, 5584 { 5585 name: "Zero", 5586 auxType: auxInt64, 5587 argLen: 2, 5588 generic: true, 5589 }, 5590 { 5591 name: "ClosureCall", 5592 auxType: auxInt64, 5593 argLen: 3, 5594 generic: true, 5595 }, 5596 { 5597 name: "StaticCall", 5598 auxType: auxSymOff, 5599 argLen: 1, 5600 generic: true, 5601 }, 5602 { 5603 name: "DeferCall", 5604 auxType: auxInt64, 5605 argLen: 1, 5606 generic: true, 5607 }, 5608 { 5609 name: "GoCall", 5610 auxType: auxInt64, 5611 argLen: 1, 5612 generic: true, 5613 }, 5614 { 5615 name: "InterCall", 5616 auxType: auxInt64, 5617 argLen: 2, 5618 generic: true, 5619 }, 5620 { 5621 name: "SignExt8to16", 5622 argLen: 1, 5623 generic: true, 5624 }, 5625 { 5626 name: "SignExt8to32", 5627 argLen: 1, 5628 generic: true, 5629 }, 5630 { 5631 name: "SignExt8to64", 5632 argLen: 1, 5633 generic: true, 5634 }, 5635 { 5636 name: "SignExt16to32", 5637 argLen: 1, 5638 generic: true, 5639 }, 5640 { 5641 name: "SignExt16to64", 5642 argLen: 1, 5643 generic: true, 5644 }, 5645 { 5646 name: "SignExt32to64", 5647 argLen: 1, 5648 generic: true, 5649 }, 5650 { 5651 name: "ZeroExt8to16", 5652 argLen: 1, 5653 generic: true, 5654 }, 5655 { 5656 name: "ZeroExt8to32", 5657 argLen: 1, 5658 generic: true, 5659 }, 5660 { 5661 name: "ZeroExt8to64", 5662 argLen: 1, 5663 generic: true, 5664 }, 5665 { 5666 name: "ZeroExt16to32", 5667 argLen: 1, 5668 generic: true, 5669 }, 5670 { 5671 name: "ZeroExt16to64", 5672 argLen: 1, 5673 generic: true, 5674 }, 5675 { 5676 name: "ZeroExt32to64", 5677 argLen: 1, 5678 generic: true, 5679 }, 5680 { 5681 name: "Trunc16to8", 5682 argLen: 1, 5683 generic: true, 5684 }, 5685 { 5686 name: "Trunc32to8", 5687 argLen: 1, 5688 generic: true, 5689 }, 5690 { 5691 name: "Trunc32to16", 5692 argLen: 1, 5693 generic: true, 5694 }, 5695 { 5696 name: "Trunc64to8", 5697 argLen: 1, 5698 generic: true, 5699 }, 5700 { 5701 name: "Trunc64to16", 5702 argLen: 1, 5703 generic: true, 5704 }, 5705 { 5706 name: "Trunc64to32", 5707 argLen: 1, 5708 generic: true, 5709 }, 5710 { 5711 name: "Cvt32to32F", 5712 argLen: 1, 5713 generic: true, 5714 }, 5715 { 5716 name: "Cvt32to64F", 5717 argLen: 1, 5718 generic: true, 5719 }, 5720 { 5721 name: "Cvt64to32F", 5722 argLen: 1, 5723 generic: true, 5724 }, 5725 { 5726 name: "Cvt64to64F", 5727 argLen: 1, 5728 generic: true, 5729 }, 5730 { 5731 name: "Cvt32Fto32", 5732 argLen: 1, 5733 generic: true, 5734 }, 5735 { 5736 name: "Cvt32Fto64", 5737 argLen: 1, 5738 generic: true, 5739 }, 5740 { 5741 name: "Cvt64Fto32", 5742 argLen: 1, 5743 generic: true, 5744 }, 5745 { 5746 name: "Cvt64Fto64", 5747 argLen: 1, 5748 generic: true, 5749 }, 5750 { 5751 name: "Cvt32Fto64F", 5752 argLen: 1, 5753 generic: true, 5754 }, 5755 { 5756 name: "Cvt64Fto32F", 5757 argLen: 1, 5758 generic: true, 5759 }, 5760 { 5761 name: "IsNonNil", 5762 argLen: 1, 5763 generic: true, 5764 }, 5765 { 5766 name: "IsInBounds", 5767 argLen: 2, 5768 generic: true, 5769 }, 5770 { 5771 name: "IsSliceInBounds", 5772 argLen: 2, 5773 generic: true, 5774 }, 5775 { 5776 name: "NilCheck", 5777 argLen: 2, 5778 generic: true, 5779 }, 5780 { 5781 name: "GetG", 5782 argLen: 1, 5783 generic: true, 5784 }, 5785 { 5786 name: "GetClosurePtr", 5787 argLen: 0, 5788 generic: true, 5789 }, 5790 { 5791 name: "ArrayIndex", 5792 auxType: auxInt64, 5793 argLen: 1, 5794 generic: true, 5795 }, 5796 { 5797 name: "PtrIndex", 5798 argLen: 2, 5799 generic: true, 5800 }, 5801 { 5802 name: "OffPtr", 5803 auxType: auxInt64, 5804 argLen: 1, 5805 generic: true, 5806 }, 5807 { 5808 name: "SliceMake", 5809 argLen: 3, 5810 generic: true, 5811 }, 5812 { 5813 name: "SlicePtr", 5814 argLen: 1, 5815 generic: true, 5816 }, 5817 { 5818 name: "SliceLen", 5819 argLen: 1, 5820 generic: true, 5821 }, 5822 { 5823 name: "SliceCap", 5824 argLen: 1, 5825 generic: true, 5826 }, 5827 { 5828 name: "ComplexMake", 5829 argLen: 2, 5830 generic: true, 5831 }, 5832 { 5833 name: "ComplexReal", 5834 argLen: 1, 5835 generic: true, 5836 }, 5837 { 5838 name: "ComplexImag", 5839 argLen: 1, 5840 generic: true, 5841 }, 5842 { 5843 name: "StringMake", 5844 argLen: 2, 5845 generic: true, 5846 }, 5847 { 5848 name: "StringPtr", 5849 argLen: 1, 5850 generic: true, 5851 }, 5852 { 5853 name: "StringLen", 5854 argLen: 1, 5855 generic: true, 5856 }, 5857 { 5858 name: "IMake", 5859 argLen: 2, 5860 generic: true, 5861 }, 5862 { 5863 name: "ITab", 5864 argLen: 1, 5865 generic: true, 5866 }, 5867 { 5868 name: "IData", 5869 argLen: 1, 5870 generic: true, 5871 }, 5872 { 5873 name: "StructMake0", 5874 argLen: 0, 5875 generic: true, 5876 }, 5877 { 5878 name: "StructMake1", 5879 argLen: 1, 5880 generic: true, 5881 }, 5882 { 5883 name: "StructMake2", 5884 argLen: 2, 5885 generic: true, 5886 }, 5887 { 5888 name: "StructMake3", 5889 argLen: 3, 5890 generic: true, 5891 }, 5892 { 5893 name: "StructMake4", 5894 argLen: 4, 5895 generic: true, 5896 }, 5897 { 5898 name: "StructSelect", 5899 auxType: auxInt64, 5900 argLen: 1, 5901 generic: true, 5902 }, 5903 { 5904 name: "StoreReg", 5905 argLen: 1, 5906 generic: true, 5907 }, 5908 { 5909 name: "LoadReg", 5910 argLen: 1, 5911 generic: true, 5912 }, 5913 { 5914 name: "FwdRef", 5915 argLen: 0, 5916 generic: true, 5917 }, 5918 { 5919 name: "Unknown", 5920 argLen: 0, 5921 generic: true, 5922 }, 5923 { 5924 name: "VarDef", 5925 auxType: auxSym, 5926 argLen: 1, 5927 generic: true, 5928 }, 5929 { 5930 name: "VarKill", 5931 auxType: auxSym, 5932 argLen: 1, 5933 generic: true, 5934 }, 5935 { 5936 name: "VarLive", 5937 auxType: auxSym, 5938 argLen: 1, 5939 generic: true, 5940 }, 5941 } 5942 5943 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 5944 func (o Op) String() string { return opcodeTable[o].name } 5945 5946 var registersAMD64 = [...]Register{ 5947 {0, "AX"}, 5948 {1, "CX"}, 5949 {2, "DX"}, 5950 {3, "BX"}, 5951 {4, "SP"}, 5952 {5, "BP"}, 5953 {6, "SI"}, 5954 {7, "DI"}, 5955 {8, "R8"}, 5956 {9, "R9"}, 5957 {10, "R10"}, 5958 {11, "R11"}, 5959 {12, "R12"}, 5960 {13, "R13"}, 5961 {14, "R14"}, 5962 {15, "R15"}, 5963 {16, "X0"}, 5964 {17, "X1"}, 5965 {18, "X2"}, 5966 {19, "X3"}, 5967 {20, "X4"}, 5968 {21, "X5"}, 5969 {22, "X6"}, 5970 {23, "X7"}, 5971 {24, "X8"}, 5972 {25, "X9"}, 5973 {26, "X10"}, 5974 {27, "X11"}, 5975 {28, "X12"}, 5976 {29, "X13"}, 5977 {30, "X14"}, 5978 {31, "X15"}, 5979 {32, "SB"}, 5980 {33, "FLAGS"}, 5981 } 5982 var registersARM = [...]Register{ 5983 {0, "R0"}, 5984 {1, "R1"}, 5985 {2, "R2"}, 5986 {3, "R3"}, 5987 {4, "SP"}, 5988 {5, "FLAGS"}, 5989 {6, "SB"}, 5990 }