github.com/miolini/go@v0.0.0-20160405192216-fca68c8cb408/src/cmd/internal/obj/s390x/asmz.go (about) 1 // Based on cmd/internal/obj/ppc64/asm9.go. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package s390x 31 32 import ( 33 "cmd/internal/obj" 34 "log" 35 "math" 36 "sort" 37 ) 38 39 // instruction layout. 40 const ( 41 FuncAlign = 16 42 ) 43 44 type Optab struct { 45 as obj.As // opcode 46 a1 uint8 // From 47 a2 uint8 // Reg 48 a3 uint8 // From3 49 a4 uint8 // To 50 type_ int8 51 param int16 // REGSP for auto variables 52 } 53 54 var optab = []Optab{ 55 // instruction, From, Reg, From3, To, type, param 56 Optab{obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0}, 57 Optab{obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0}, 58 59 // move register 60 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 61 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 62 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 63 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 64 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 65 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 1, 0}, 66 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 67 68 // load constant 69 Optab{AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 70 Optab{AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 71 Optab{AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 72 Optab{AMOVD, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 73 Optab{AMOVW, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 74 Optab{AMOVWZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 75 Optab{AMOVB, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 76 Optab{AMOVBZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 77 78 // store constant 79 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_ADDR, 73, 0}, 80 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 81 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 82 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 83 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 84 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 85 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 86 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 87 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 88 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 89 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 90 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 91 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_LOREG, 72, 0}, 92 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 93 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 94 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 95 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 96 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 97 98 // store 99 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 100 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 101 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 102 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 103 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 104 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 105 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 106 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 107 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 108 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 109 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 110 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 111 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 112 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 113 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 114 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 115 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 116 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 117 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 118 119 // load 120 Optab{AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 121 Optab{AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 122 Optab{AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 123 Optab{AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 124 Optab{AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 125 Optab{AMOVDBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 126 Optab{AMOVHBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 127 Optab{AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 128 Optab{AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 129 Optab{AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 130 Optab{AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 131 Optab{AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 132 Optab{AMOVDBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 133 Optab{AMOVHBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 134 Optab{AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 135 Optab{AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 136 Optab{AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 137 Optab{AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 138 Optab{AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 139 140 // integer arithmetic 141 Optab{AADD, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 142 Optab{AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 143 Optab{AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 0}, 144 Optab{AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 0}, 145 Optab{AADDC, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 146 Optab{AADDC, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 147 Optab{AADDC, C_LCON, C_REG, C_NONE, C_REG, 22, 0}, 148 Optab{AADDC, C_LCON, C_NONE, C_NONE, C_REG, 22, 0}, 149 Optab{AMULLW, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 150 Optab{AMULLW, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 151 Optab{AMULLW, C_LCON, C_REG, C_NONE, C_REG, 22, 0}, 152 Optab{AMULLW, C_LCON, C_NONE, C_NONE, C_REG, 22, 0}, 153 Optab{ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 0}, 154 Optab{ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 0}, 155 Optab{ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 156 Optab{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 157 Optab{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 0}, 158 Optab{ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 0}, 159 Optab{AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 0}, 160 Optab{ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 0}, 161 Optab{ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 0}, 162 163 // integer logical 164 Optab{AAND, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 165 Optab{AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 166 Optab{AAND, C_LCON, C_NONE, C_NONE, C_REG, 23, 0}, 167 Optab{AAND, C_LCON, C_REG, C_NONE, C_REG, 23, 0}, 168 Optab{AOR, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 169 Optab{AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 170 Optab{AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 0}, 171 Optab{AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 0}, 172 Optab{ASLD, C_REG, C_NONE, C_NONE, C_REG, 7, 0}, 173 Optab{ASLD, C_REG, C_REG, C_NONE, C_REG, 7, 0}, 174 Optab{ASLD, C_SCON, C_REG, C_NONE, C_REG, 7, 0}, 175 Optab{ASLD, C_SCON, C_NONE, C_NONE, C_REG, 7, 0}, 176 177 // compare and swap 178 Optab{ACSG, C_REG, C_REG, C_NONE, C_SOREG, 79, 0}, 179 180 // floating point 181 Optab{AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 0}, 182 Optab{AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 0}, 183 Optab{AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 0}, 184 Optab{AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 0}, 185 Optab{AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 0}, 186 Optab{AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 187 Optab{AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 0}, 188 Optab{AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, REGSP}, 189 Optab{AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 0}, 190 Optab{AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 0}, 191 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 192 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 0}, 193 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 0}, 194 Optab{AFMOVD, C_ZCON, C_NONE, C_NONE, C_FREG, 67, 0}, 195 Optab{ACEFBRA, C_REG, C_NONE, C_NONE, C_FREG, 82, 0}, 196 Optab{ACFEBRA, C_FREG, C_NONE, C_NONE, C_REG, 83, 0}, 197 198 // load symbol address (plus offset) 199 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_REG, 19, 0}, 200 Optab{AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 93, 0}, 201 Optab{AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 94, 0}, 202 Optab{AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 95, 0}, 203 204 // system call 205 Optab{ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 0}, 206 Optab{ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 0}, 207 208 // branch 209 Optab{ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 0}, 210 Optab{ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 0}, 211 Optab{ABC, C_SCON, C_REG, C_NONE, C_LBRA, 16, 0}, 212 Optab{ABR, C_NONE, C_NONE, C_NONE, C_REG, 18, 0}, 213 Optab{ABR, C_REG, C_NONE, C_NONE, C_REG, 18, 0}, 214 Optab{ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 215 Optab{ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 216 Optab{ACMPBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 217 Optab{ACMPBEQ, C_REG, C_NONE, C_ADDCON, C_SBRA, 90, 0}, 218 Optab{ACMPBEQ, C_REG, C_NONE, C_SCON, C_SBRA, 90, 0}, 219 Optab{ACMPUBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 220 Optab{ACMPUBEQ, C_REG, C_NONE, C_ANDCON, C_SBRA, 90, 0}, 221 222 // compare 223 Optab{ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 224 Optab{ACMP, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 225 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 226 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 227 Optab{AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 0}, 228 Optab{AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 0}, 229 230 // 32-bit access registers 231 Optab{AMOVW, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 232 Optab{AMOVWZ, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 233 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 234 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 235 236 // macros 237 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LOREG, 96, 0}, 238 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LAUTO, 96, REGSP}, 239 240 // load/store multiple 241 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LOREG, 97, 0}, 242 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LAUTO, 97, REGSP}, 243 Optab{ALMG, C_LOREG, C_REG, C_NONE, C_REG, 98, 0}, 244 Optab{ALMG, C_LAUTO, C_REG, C_NONE, C_REG, 98, REGSP}, 245 246 // bytes 247 Optab{ABYTE, C_SCON, C_NONE, C_NONE, C_NONE, 40, 0}, 248 Optab{AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 0}, 249 Optab{ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 0}, 250 Optab{ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 0}, 251 252 // fast synchronization 253 Optab{ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 81, 0}, 254 255 // store clock 256 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SAUTO, 88, REGSP}, 257 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SOREG, 88, 0}, 258 259 // storage and storage 260 Optab{AMVC, C_LOREG, C_NONE, C_SCON, C_LOREG, 84, 0}, 261 Optab{AMVC, C_LOREG, C_NONE, C_SCON, C_LAUTO, 84, REGSP}, 262 Optab{AMVC, C_LAUTO, C_NONE, C_SCON, C_LAUTO, 84, REGSP}, 263 264 // address 265 Optab{ALARL, C_LCON, C_NONE, C_NONE, C_REG, 85, 0}, 266 Optab{ALARL, C_SYMADDR, C_NONE, C_NONE, C_REG, 85, 0}, 267 Optab{ALA, C_SOREG, C_NONE, C_NONE, C_REG, 86, 0}, 268 Optab{ALA, C_SAUTO, C_NONE, C_NONE, C_REG, 86, REGSP}, 269 Optab{AEXRL, C_SYMADDR, C_NONE, C_NONE, C_REG, 87, 0}, 270 271 // misc 272 Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 0}, 273 Optab{obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0}, 274 Optab{obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0}, 275 Optab{obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0}, 276 Optab{obj.ANOP, C_SAUTO, C_NONE, C_NONE, C_NONE, 0, 0}, 277 278 // vector instructions 279 280 // VRX store 281 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SOREG, 100, 0}, 282 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SAUTO, 100, REGSP}, 283 Optab{AVSTEG, C_VREG, C_NONE, C_SCON, C_SOREG, 100, 0}, 284 Optab{AVSTEG, C_VREG, C_NONE, C_SCON, C_SAUTO, 100, REGSP}, 285 286 // VRX load 287 Optab{AVL, C_SOREG, C_NONE, C_NONE, C_VREG, 101, 0}, 288 Optab{AVL, C_SAUTO, C_NONE, C_NONE, C_VREG, 101, REGSP}, 289 Optab{AVLEG, C_SOREG, C_NONE, C_SCON, C_VREG, 101, 0}, 290 Optab{AVLEG, C_SAUTO, C_NONE, C_SCON, C_VREG, 101, REGSP}, 291 292 // VRV scatter 293 Optab{AVSCEG, C_VREG, C_NONE, C_SCON, C_SOREG, 102, 0}, 294 Optab{AVSCEG, C_VREG, C_NONE, C_SCON, C_SAUTO, 102, REGSP}, 295 296 // VRV gather 297 Optab{AVGEG, C_SOREG, C_NONE, C_SCON, C_VREG, 103, 0}, 298 Optab{AVGEG, C_SAUTO, C_NONE, C_SCON, C_VREG, 103, REGSP}, 299 300 // VRS element shift/rotate and load gr to/from vr element 301 Optab{AVESLG, C_SCON, C_VREG, C_NONE, C_VREG, 104, 0}, 302 Optab{AVESLG, C_REG, C_VREG, C_NONE, C_VREG, 104, 0}, 303 Optab{AVESLG, C_SCON, C_NONE, C_NONE, C_VREG, 104, 0}, 304 Optab{AVESLG, C_REG, C_NONE, C_NONE, C_VREG, 104, 0}, 305 Optab{AVLGVG, C_SCON, C_VREG, C_NONE, C_REG, 104, 0}, 306 Optab{AVLGVG, C_REG, C_VREG, C_NONE, C_REG, 104, 0}, 307 Optab{AVLVGG, C_SCON, C_REG, C_NONE, C_VREG, 104, 0}, 308 Optab{AVLVGG, C_REG, C_REG, C_NONE, C_VREG, 104, 0}, 309 310 // VRS store multiple 311 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SOREG, 105, 0}, 312 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SAUTO, 105, REGSP}, 313 314 // VRS load multiple 315 Optab{AVLM, C_SOREG, C_VREG, C_NONE, C_VREG, 106, 0}, 316 Optab{AVLM, C_SAUTO, C_VREG, C_NONE, C_VREG, 106, REGSP}, 317 318 // VRS store with length 319 Optab{AVSTL, C_VREG, C_NONE, C_REG, C_SOREG, 107, 0}, 320 Optab{AVSTL, C_VREG, C_NONE, C_REG, C_SAUTO, 107, REGSP}, 321 322 // VRS load with length 323 Optab{AVLL, C_SOREG, C_NONE, C_REG, C_VREG, 108, 0}, 324 Optab{AVLL, C_SAUTO, C_NONE, C_REG, C_VREG, 108, REGSP}, 325 326 // VRI-a 327 Optab{AVGBM, C_ANDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 328 Optab{AVZERO, C_NONE, C_NONE, C_NONE, C_VREG, 109, 0}, 329 Optab{AVREPIG, C_ADDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 330 Optab{AVREPIG, C_SCON, C_NONE, C_NONE, C_VREG, 109, 0}, 331 Optab{AVLEIG, C_ADDCON, C_NONE, C_SCON, C_VREG, 109, 0}, 332 Optab{AVLEIG, C_SCON, C_NONE, C_SCON, C_VREG, 109, 0}, 333 334 // VRI-b generate mask 335 Optab{AVGMG, C_SCON, C_NONE, C_SCON, C_VREG, 110, 0}, 336 337 // VRI-c replicate 338 Optab{AVREPG, C_UCON, C_VREG, C_NONE, C_VREG, 111, 0}, 339 340 // VRI-d element rotate and insert under mask and 341 // shift left double by byte 342 Optab{AVERIMG, C_VREG, C_VREG, C_SCON, C_VREG, 112, 0}, 343 Optab{AVSLDB, C_VREG, C_VREG, C_SCON, C_VREG, 112, 0}, 344 345 // VRI-d fp test data class immediate 346 Optab{AVFTCIDB, C_SCON, C_VREG, C_NONE, C_VREG, 113, 0}, 347 348 // VRR-a load reg 349 Optab{AVLR, C_VREG, C_NONE, C_NONE, C_VREG, 114, 0}, 350 351 // VRR-a compare 352 Optab{AVECG, C_VREG, C_NONE, C_NONE, C_VREG, 115, 0}, 353 354 // VRR-b 355 Optab{AVCEQG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 356 Optab{AVFAEF, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 357 Optab{AVPKSG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 358 359 // VRR-c 360 Optab{AVAQ, C_VREG, C_VREG, C_NONE, C_VREG, 118, 0}, 361 Optab{AVAQ, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 362 Optab{AVNOT, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 363 Optab{AVPDI, C_VREG, C_VREG, C_SCON, C_VREG, 123, 0}, 364 365 // VRR-c shifts 366 Optab{AVERLLVG, C_VREG, C_VREG, C_NONE, C_VREG, 119, 0}, 367 Optab{AVERLLVG, C_VREG, C_NONE, C_NONE, C_VREG, 119, 0}, 368 369 // VRR-d 370 // 2 3 1 4 371 Optab{AVACQ, C_VREG, C_VREG, C_VREG, C_VREG, 120, 0}, 372 373 // VRR-e 374 Optab{AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 121, 0}, 375 376 // VRR-f 377 Optab{AVLVGP, C_REG, C_REG, C_NONE, C_VREG, 122, 0}, 378 } 379 380 var oprange [ALAST & obj.AMask][]Optab 381 382 var xcmp [C_NCLASS][C_NCLASS]bool 383 384 func spanz(ctxt *obj.Link, cursym *obj.LSym) { 385 p := cursym.Text 386 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 387 return 388 } 389 ctxt.Cursym = cursym 390 ctxt.Autosize = int32(p.To.Offset) 391 392 if oprange[AANDN&obj.AMask] == nil { 393 buildop(ctxt) 394 } 395 396 buffer := make([]byte, 0) 397 changed := true 398 loop := 0 399 for changed { 400 if loop > 10 { 401 ctxt.Diag("stuck in spanz loop") 402 break 403 } 404 changed = false 405 buffer = buffer[:0] 406 ctxt.Cursym.R = make([]obj.Reloc, 0) 407 for p := cursym.Text; p != nil; p = p.Link { 408 pc := int64(len(buffer)) 409 if pc != p.Pc { 410 changed = true 411 } 412 p.Pc = pc 413 ctxt.Pc = p.Pc 414 ctxt.Curp = p 415 asmout(ctxt, &buffer) 416 if pc == int64(len(buffer)) { 417 switch p.As { 418 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT: 419 // ok 420 default: 421 ctxt.Diag("zero-width instruction\n%v", p) 422 } 423 } 424 } 425 loop++ 426 } 427 428 cursym.Size = int64(len(buffer)) 429 if cursym.Size%FuncAlign != 0 { 430 cursym.Size += FuncAlign - (cursym.Size % FuncAlign) 431 } 432 cursym.Grow(cursym.Size) 433 copy(cursym.P, buffer) 434 } 435 436 func isint32(v int64) bool { 437 return int64(int32(v)) == v 438 } 439 440 func isuint32(v uint64) bool { 441 return uint64(uint32(v)) == v 442 } 443 444 func aclass(ctxt *obj.Link, a *obj.Addr) int { 445 switch a.Type { 446 case obj.TYPE_NONE: 447 return C_NONE 448 449 case obj.TYPE_REG: 450 if REG_R0 <= a.Reg && a.Reg <= REG_R15 { 451 return C_REG 452 } 453 if REG_F0 <= a.Reg && a.Reg <= REG_F15 { 454 return C_FREG 455 } 456 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 { 457 return C_AREG 458 } 459 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 460 return C_VREG 461 } 462 return C_GOK 463 464 case obj.TYPE_MEM: 465 switch a.Name { 466 case obj.NAME_EXTERN, 467 obj.NAME_STATIC: 468 if a.Sym == nil { 469 // must have a symbol 470 break 471 } 472 ctxt.Instoffset = a.Offset 473 if a.Sym.Type == obj.STLSBSS { 474 if ctxt.Flag_shared != 0 { 475 return C_TLS_IE // initial exec model 476 } 477 return C_TLS_LE // local exec model 478 } 479 return C_ADDR 480 481 case obj.NAME_GOTREF: 482 return C_GOTADDR 483 484 case obj.NAME_AUTO: 485 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset 486 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 487 return C_SAUTO 488 } 489 return C_LAUTO 490 491 case obj.NAME_PARAM: 492 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + ctxt.FixedFrameSize() 493 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 494 return C_SAUTO 495 } 496 return C_LAUTO 497 498 case obj.NAME_NONE: 499 ctxt.Instoffset = a.Offset 500 if ctxt.Instoffset == 0 { 501 return C_ZOREG 502 } 503 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 504 return C_SOREG 505 } 506 return C_LOREG 507 } 508 509 return C_GOK 510 511 case obj.TYPE_TEXTSIZE: 512 return C_TEXTSIZE 513 514 case obj.TYPE_FCONST: 515 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 { 516 return C_ZCON 517 } 518 ctxt.Diag("cannot handle the floating point constant %v", a.Val) 519 520 case obj.TYPE_CONST, 521 obj.TYPE_ADDR: 522 switch a.Name { 523 case obj.NAME_NONE: 524 ctxt.Instoffset = a.Offset 525 if a.Reg != 0 { 526 if -BIG <= ctxt.Instoffset && ctxt.Instoffset <= BIG { 527 return C_SACON 528 } 529 if isint32(ctxt.Instoffset) { 530 return C_LACON 531 } 532 return C_DACON 533 } 534 goto consize 535 536 case obj.NAME_EXTERN, 537 obj.NAME_STATIC: 538 s := a.Sym 539 if s == nil { 540 break 541 } 542 ctxt.Instoffset = a.Offset 543 if s.Type == obj.SCONST { 544 goto consize 545 } 546 547 return C_SYMADDR 548 549 case obj.NAME_AUTO: 550 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset 551 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 552 return C_SACON 553 } 554 return C_LACON 555 556 case obj.NAME_PARAM: 557 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + ctxt.FixedFrameSize() 558 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 559 return C_SACON 560 } 561 return C_LACON 562 } 563 564 return C_GOK 565 566 consize: 567 if ctxt.Instoffset == 0 { 568 return C_ZCON 569 } 570 if ctxt.Instoffset >= 0 { 571 if ctxt.Instoffset <= 0x7fff { 572 return C_SCON 573 } 574 if ctxt.Instoffset <= 0xffff { 575 return C_ANDCON 576 } 577 if ctxt.Instoffset&0xffff == 0 && isuint32(uint64(ctxt.Instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 578 return C_UCON 579 } 580 if isint32(ctxt.Instoffset) || isuint32(uint64(ctxt.Instoffset)) { 581 return C_LCON 582 } 583 return C_DCON 584 } 585 586 if ctxt.Instoffset >= -0x8000 { 587 return C_ADDCON 588 } 589 if ctxt.Instoffset&0xffff == 0 && isint32(ctxt.Instoffset) { 590 return C_UCON 591 } 592 if isint32(ctxt.Instoffset) { 593 return C_LCON 594 } 595 return C_DCON 596 597 case obj.TYPE_BRANCH: 598 return C_SBRA 599 } 600 601 return C_GOK 602 } 603 604 func oplook(ctxt *obj.Link, p *obj.Prog) *Optab { 605 a1 := int(p.Optab) 606 if a1 != 0 { 607 return &optab[a1-1:][0] 608 } 609 a1 = int(p.From.Class) 610 if a1 == 0 { 611 a1 = aclass(ctxt, &p.From) + 1 612 p.From.Class = int8(a1) 613 } 614 615 a1-- 616 a3 := C_NONE + 1 617 if p.From3 != nil { 618 a3 = int(p.From3.Class) 619 if a3 == 0 { 620 a3 = aclass(ctxt, p.From3) + 1 621 p.From3.Class = int8(a3) 622 } 623 } 624 625 a3-- 626 a4 := int(p.To.Class) 627 if a4 == 0 { 628 a4 = aclass(ctxt, &p.To) + 1 629 p.To.Class = int8(a4) 630 } 631 632 a4-- 633 a2 := C_NONE 634 if p.Reg != 0 { 635 if REG_R0 <= p.Reg && p.Reg <= REG_R15 { 636 a2 = C_REG 637 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 638 a2 = C_VREG 639 } else if REG_F0 <= p.Reg && p.Reg <= REG_F15 { 640 a2 = C_FREG 641 } else if REG_AR0 <= p.Reg && p.Reg <= REG_AR15 { 642 a2 = C_AREG 643 } 644 } 645 646 ops := oprange[p.As&obj.AMask] 647 c1 := &xcmp[a1] 648 c2 := &xcmp[a2] 649 c3 := &xcmp[a3] 650 c4 := &xcmp[a4] 651 for i := range ops { 652 op := &ops[i] 653 if (int(op.a2) == a2 || c2[op.a2]) && c4[op.a4] && c1[op.a1] && c3[op.a3] { 654 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 655 return op 656 } 657 } 658 659 // cannot find a case; abort 660 ctxt.Diag("illegal combination %v %v %v %v %v\n", obj.Aconv(p.As), DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 661 ctxt.Diag("prog: %v\n", p) 662 return nil 663 } 664 665 func cmp(a int, b int) bool { 666 if a == b { 667 return true 668 } 669 switch a { 670 case C_DCON: 671 if b == C_LCON { 672 return true 673 } 674 fallthrough 675 case C_LCON: 676 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 677 return true 678 } 679 680 case C_ADDCON: 681 if b == C_ZCON || b == C_SCON { 682 return true 683 } 684 685 case C_ANDCON: 686 if b == C_ZCON || b == C_SCON { 687 return true 688 } 689 690 case C_UCON: 691 if b == C_ZCON || b == C_SCON { 692 return true 693 } 694 695 case C_SCON: 696 if b == C_ZCON { 697 return true 698 } 699 700 case C_LACON: 701 if b == C_SACON { 702 return true 703 } 704 705 case C_LBRA: 706 if b == C_SBRA { 707 return true 708 } 709 710 case C_LAUTO: 711 if b == C_SAUTO { 712 return true 713 } 714 715 case C_LOREG: 716 if b == C_ZOREG || b == C_SOREG { 717 return true 718 } 719 720 case C_SOREG: 721 if b == C_ZOREG { 722 return true 723 } 724 725 case C_ANY: 726 return true 727 } 728 729 return false 730 } 731 732 type ocmp []Optab 733 734 func (x ocmp) Len() int { 735 return len(x) 736 } 737 738 func (x ocmp) Swap(i, j int) { 739 x[i], x[j] = x[j], x[i] 740 } 741 742 func (x ocmp) Less(i, j int) bool { 743 p1 := &x[i] 744 p2 := &x[j] 745 n := int(p1.as) - int(p2.as) 746 if n != 0 { 747 return n < 0 748 } 749 n = int(p1.a1) - int(p2.a1) 750 if n != 0 { 751 return n < 0 752 } 753 n = int(p1.a2) - int(p2.a2) 754 if n != 0 { 755 return n < 0 756 } 757 n = int(p1.a3) - int(p2.a3) 758 if n != 0 { 759 return n < 0 760 } 761 n = int(p1.a4) - int(p2.a4) 762 if n != 0 { 763 return n < 0 764 } 765 return false 766 } 767 func opset(a, b obj.As) { 768 oprange[a&obj.AMask] = oprange[b&obj.AMask] 769 } 770 771 func buildop(ctxt *obj.Link) { 772 for i := 0; i < C_NCLASS; i++ { 773 for n := 0; n < C_NCLASS; n++ { 774 if cmp(n, i) { 775 xcmp[i][n] = true 776 } 777 } 778 } 779 sort.Sort(ocmp(optab)) 780 for i := 0; i < len(optab); i++ { 781 r := optab[i].as 782 start := i 783 for ; i+1 < len(optab); i++ { 784 if optab[i+1].as != r { 785 break 786 } 787 } 788 oprange[r&obj.AMask] = optab[start : i+1] 789 790 // opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array. 791 // oprange[] is used by oplook() to find the Optab entry that applies to a given Prog. 792 switch r { 793 case ADIVW: 794 opset(AADDE, r) 795 opset(AMULLD, r) 796 opset(AMULHDU, r) 797 opset(ADIVD, r) 798 opset(ADIVDU, r) 799 opset(ADIVWU, r) 800 case AMOVBZ: 801 opset(AMOVH, r) 802 opset(AMOVHZ, r) 803 case ALA: 804 opset(ALAY, r) 805 case AMVC: 806 opset(ACLC, r) 807 opset(AXC, r) 808 opset(AOC, r) 809 opset(ANC, r) 810 case ASTCK: 811 opset(ASTCKC, r) 812 opset(ASTCKE, r) 813 opset(ASTCKF, r) 814 case ASTMG: 815 opset(ASTMY, r) 816 case ALMG: 817 opset(ALMY, r) 818 case AAND: 819 opset(AANDN, r) 820 opset(ANAND, r) 821 opset(ANOR, r) 822 opset(AORN, r) 823 case AADDME: 824 opset(AADDZE, r) 825 opset(ASUBME, r) 826 opset(ASUBZE, r) 827 case ABEQ: 828 opset(ABGE, r) 829 opset(ABGT, r) 830 opset(ABLE, r) 831 opset(ABLT, r) 832 opset(ABNE, r) 833 opset(ABVC, r) 834 opset(ABVS, r) 835 case ABR: 836 opset(ABL, r) 837 case ABC: 838 opset(ABCL, r) 839 case AFABS: 840 opset(AFNABS, r) 841 opset(AFNEG, r) 842 opset(ALEDBR, r) 843 opset(ALDEBR, r) 844 opset(AFSQRT, r) 845 opset(AFSQRTS, r) 846 case AFADD: 847 opset(AFADDS, r) 848 opset(AFDIV, r) 849 opset(AFDIVS, r) 850 opset(AFSUB, r) 851 opset(AFSUBS, r) 852 case AFMADD: 853 opset(AFMADDS, r) 854 opset(AFMSUB, r) 855 opset(AFMSUBS, r) 856 opset(AFNMADD, r) 857 opset(AFNMADDS, r) 858 opset(AFNMSUB, r) 859 opset(AFNMSUBS, r) 860 case AFMUL: 861 opset(AFMULS, r) 862 case AFCMPO: 863 opset(AFCMPU, r) 864 opset(ACEBR, r) 865 case AOR: 866 opset(AXOR, r) 867 case ASLD: 868 opset(ASRD, r) 869 opset(ASLW, r) 870 opset(ASRW, r) 871 opset(ASRAD, r) 872 opset(ASRAW, r) 873 opset(ARLL, r) 874 opset(ARLLG, r) 875 case ACSG: 876 opset(ACS, r) 877 case ASUB: 878 opset(ASUBC, r) 879 opset(ASUBE, r) 880 case AFMOVD: 881 opset(AFMOVS, r) 882 case AMOVDBR: 883 opset(AMOVWBR, r) 884 case ACMP: 885 opset(ACMPW, r) 886 case ACMPU: 887 opset(ACMPWU, r) 888 case ACEFBRA: 889 opset(ACDFBRA, r) 890 opset(ACEGBRA, r) 891 opset(ACDGBRA, r) 892 opset(ACELFBR, r) 893 opset(ACDLFBR, r) 894 opset(ACELGBR, r) 895 opset(ACDLGBR, r) 896 case ACFEBRA: 897 opset(ACFDBRA, r) 898 opset(ACGEBRA, r) 899 opset(ACGDBRA, r) 900 opset(ACLFEBR, r) 901 opset(ACLFDBR, r) 902 opset(ACLGEBR, r) 903 opset(ACLGDBR, r) 904 case ACMPBEQ: 905 opset(ACMPBGE, r) 906 opset(ACMPBGT, r) 907 opset(ACMPBLE, r) 908 opset(ACMPBLT, r) 909 opset(ACMPBNE, r) 910 case ACMPUBEQ: 911 opset(ACMPUBGE, r) 912 opset(ACMPUBGT, r) 913 opset(ACMPUBLE, r) 914 opset(ACMPUBLT, r) 915 opset(ACMPUBNE, r) 916 case AVL: 917 opset(AVLLEZB, r) 918 opset(AVLLEZH, r) 919 opset(AVLLEZF, r) 920 opset(AVLLEZG, r) 921 opset(AVLREPB, r) 922 opset(AVLREPH, r) 923 opset(AVLREPF, r) 924 opset(AVLREPG, r) 925 case AVLEG: 926 opset(AVLBB, r) 927 opset(AVLEB, r) 928 opset(AVLEH, r) 929 opset(AVLEF, r) 930 opset(AVLEG, r) 931 opset(AVLREP, r) 932 case AVSTEG: 933 opset(AVSTEB, r) 934 opset(AVSTEH, r) 935 opset(AVSTEF, r) 936 case AVSCEG: 937 opset(AVSCEF, r) 938 case AVGEG: 939 opset(AVGEF, r) 940 case AVESLG: 941 opset(AVESLB, r) 942 opset(AVESLH, r) 943 opset(AVESLF, r) 944 opset(AVERLLB, r) 945 opset(AVERLLH, r) 946 opset(AVERLLF, r) 947 opset(AVERLLG, r) 948 opset(AVESRAB, r) 949 opset(AVESRAH, r) 950 opset(AVESRAF, r) 951 opset(AVESRAG, r) 952 opset(AVESRLB, r) 953 opset(AVESRLH, r) 954 opset(AVESRLF, r) 955 opset(AVESRLG, r) 956 case AVLGVG: 957 opset(AVLGVB, r) 958 opset(AVLGVH, r) 959 opset(AVLGVF, r) 960 case AVLVGG: 961 opset(AVLVGB, r) 962 opset(AVLVGH, r) 963 opset(AVLVGF, r) 964 case AVZERO: 965 opset(AVONE, r) 966 case AVREPIG: 967 opset(AVREPIB, r) 968 opset(AVREPIH, r) 969 opset(AVREPIF, r) 970 case AVLEIG: 971 opset(AVLEIB, r) 972 opset(AVLEIH, r) 973 opset(AVLEIF, r) 974 case AVGMG: 975 opset(AVGMB, r) 976 opset(AVGMH, r) 977 opset(AVGMF, r) 978 case AVREPG: 979 opset(AVREPB, r) 980 opset(AVREPH, r) 981 opset(AVREPF, r) 982 case AVERIMG: 983 opset(AVERIMB, r) 984 opset(AVERIMH, r) 985 opset(AVERIMF, r) 986 case AVFTCIDB: 987 opset(AWFTCIDB, r) 988 case AVLR: 989 opset(AVUPHB, r) 990 opset(AVUPHH, r) 991 opset(AVUPHF, r) 992 opset(AVUPLHB, r) 993 opset(AVUPLHH, r) 994 opset(AVUPLHF, r) 995 opset(AVUPLB, r) 996 opset(AVUPLHW, r) 997 opset(AVUPLF, r) 998 opset(AVUPLLB, r) 999 opset(AVUPLLH, r) 1000 opset(AVUPLLF, r) 1001 opset(AVCLZB, r) 1002 opset(AVCLZH, r) 1003 opset(AVCLZF, r) 1004 opset(AVCLZG, r) 1005 opset(AVCTZB, r) 1006 opset(AVCTZH, r) 1007 opset(AVCTZF, r) 1008 opset(AVCTZG, r) 1009 opset(AVLDEB, r) 1010 opset(AWLDEB, r) 1011 opset(AVFLCDB, r) 1012 opset(AWFLCDB, r) 1013 opset(AVFLNDB, r) 1014 opset(AWFLNDB, r) 1015 opset(AVFLPDB, r) 1016 opset(AWFLPDB, r) 1017 opset(AVFSQDB, r) 1018 opset(AWFSQDB, r) 1019 opset(AVISTRB, r) 1020 opset(AVISTRH, r) 1021 opset(AVISTRF, r) 1022 opset(AVISTRBS, r) 1023 opset(AVISTRHS, r) 1024 opset(AVISTRFS, r) 1025 opset(AVLCB, r) 1026 opset(AVLCH, r) 1027 opset(AVLCF, r) 1028 opset(AVLCG, r) 1029 opset(AVLPB, r) 1030 opset(AVLPH, r) 1031 opset(AVLPF, r) 1032 opset(AVLPG, r) 1033 opset(AVPOPCT, r) 1034 opset(AVSEGB, r) 1035 opset(AVSEGH, r) 1036 opset(AVSEGF, r) 1037 case AVECG: 1038 opset(AVECB, r) 1039 opset(AVECH, r) 1040 opset(AVECF, r) 1041 opset(AVECLB, r) 1042 opset(AVECLH, r) 1043 opset(AVECLF, r) 1044 opset(AVECLG, r) 1045 opset(AWFCDB, r) 1046 opset(AWFKDB, r) 1047 case AVCEQG: 1048 opset(AVCEQB, r) 1049 opset(AVCEQH, r) 1050 opset(AVCEQF, r) 1051 opset(AVCEQBS, r) 1052 opset(AVCEQHS, r) 1053 opset(AVCEQFS, r) 1054 opset(AVCEQGS, r) 1055 opset(AVCHB, r) 1056 opset(AVCHH, r) 1057 opset(AVCHF, r) 1058 opset(AVCHG, r) 1059 opset(AVCHBS, r) 1060 opset(AVCHHS, r) 1061 opset(AVCHFS, r) 1062 opset(AVCHGS, r) 1063 opset(AVCHLB, r) 1064 opset(AVCHLH, r) 1065 opset(AVCHLF, r) 1066 opset(AVCHLG, r) 1067 opset(AVCHLBS, r) 1068 opset(AVCHLHS, r) 1069 opset(AVCHLFS, r) 1070 opset(AVCHLGS, r) 1071 case AVFAEF: 1072 opset(AVFAEB, r) 1073 opset(AVFAEH, r) 1074 opset(AVFAEBS, r) 1075 opset(AVFAEHS, r) 1076 opset(AVFAEFS, r) 1077 opset(AVFAEZB, r) 1078 opset(AVFAEZH, r) 1079 opset(AVFAEZF, r) 1080 opset(AVFAEZBS, r) 1081 opset(AVFAEZHS, r) 1082 opset(AVFAEZFS, r) 1083 opset(AVFEEB, r) 1084 opset(AVFEEH, r) 1085 opset(AVFEEF, r) 1086 opset(AVFEEBS, r) 1087 opset(AVFEEHS, r) 1088 opset(AVFEEFS, r) 1089 opset(AVFEEZB, r) 1090 opset(AVFEEZH, r) 1091 opset(AVFEEZF, r) 1092 opset(AVFEEZBS, r) 1093 opset(AVFEEZHS, r) 1094 opset(AVFEEZFS, r) 1095 opset(AVFENEB, r) 1096 opset(AVFENEH, r) 1097 opset(AVFENEF, r) 1098 opset(AVFENEBS, r) 1099 opset(AVFENEHS, r) 1100 opset(AVFENEFS, r) 1101 opset(AVFENEZB, r) 1102 opset(AVFENEZH, r) 1103 opset(AVFENEZF, r) 1104 opset(AVFENEZBS, r) 1105 opset(AVFENEZHS, r) 1106 opset(AVFENEZFS, r) 1107 case AVPKSG: 1108 opset(AVPKSH, r) 1109 opset(AVPKSF, r) 1110 opset(AVPKSHS, r) 1111 opset(AVPKSFS, r) 1112 opset(AVPKSGS, r) 1113 opset(AVPKLSH, r) 1114 opset(AVPKLSF, r) 1115 opset(AVPKLSG, r) 1116 opset(AVPKLSHS, r) 1117 opset(AVPKLSFS, r) 1118 opset(AVPKLSGS, r) 1119 case AVAQ: 1120 opset(AVAB, r) 1121 opset(AVAH, r) 1122 opset(AVAF, r) 1123 opset(AVAG, r) 1124 opset(AVACCB, r) 1125 opset(AVACCH, r) 1126 opset(AVACCF, r) 1127 opset(AVACCG, r) 1128 opset(AVACCQ, r) 1129 opset(AVN, r) 1130 opset(AVNC, r) 1131 opset(AVAVGB, r) 1132 opset(AVAVGH, r) 1133 opset(AVAVGF, r) 1134 opset(AVAVGG, r) 1135 opset(AVAVGLB, r) 1136 opset(AVAVGLH, r) 1137 opset(AVAVGLF, r) 1138 opset(AVAVGLG, r) 1139 opset(AVCKSM, r) 1140 opset(AVX, r) 1141 opset(AVFADB, r) 1142 opset(AWFADB, r) 1143 opset(AVFCEDB, r) 1144 opset(AVFCEDBS, r) 1145 opset(AWFCEDB, r) 1146 opset(AWFCEDBS, r) 1147 opset(AVFCHDB, r) 1148 opset(AVFCHDBS, r) 1149 opset(AWFCHDB, r) 1150 opset(AWFCHDBS, r) 1151 opset(AVFCHEDB, r) 1152 opset(AVFCHEDBS, r) 1153 opset(AWFCHEDB, r) 1154 opset(AWFCHEDBS, r) 1155 opset(AVFMDB, r) 1156 opset(AWFMDB, r) 1157 opset(AVGFMB, r) 1158 opset(AVGFMH, r) 1159 opset(AVGFMF, r) 1160 opset(AVGFMG, r) 1161 opset(AVMXB, r) 1162 opset(AVMXH, r) 1163 opset(AVMXF, r) 1164 opset(AVMXG, r) 1165 opset(AVMXLB, r) 1166 opset(AVMXLH, r) 1167 opset(AVMXLF, r) 1168 opset(AVMXLG, r) 1169 opset(AVMNB, r) 1170 opset(AVMNH, r) 1171 opset(AVMNF, r) 1172 opset(AVMNG, r) 1173 opset(AVMNLB, r) 1174 opset(AVMNLH, r) 1175 opset(AVMNLF, r) 1176 opset(AVMNLG, r) 1177 opset(AVMRHB, r) 1178 opset(AVMRHH, r) 1179 opset(AVMRHF, r) 1180 opset(AVMRHG, r) 1181 opset(AVMRLB, r) 1182 opset(AVMRLH, r) 1183 opset(AVMRLF, r) 1184 opset(AVMRLG, r) 1185 opset(AVMEB, r) 1186 opset(AVMEH, r) 1187 opset(AVMEF, r) 1188 opset(AVMLEB, r) 1189 opset(AVMLEH, r) 1190 opset(AVMLEF, r) 1191 opset(AVMOB, r) 1192 opset(AVMOH, r) 1193 opset(AVMOF, r) 1194 opset(AVMLOB, r) 1195 opset(AVMLOH, r) 1196 opset(AVMLOF, r) 1197 opset(AVMHB, r) 1198 opset(AVMHH, r) 1199 opset(AVMHF, r) 1200 opset(AVMLHB, r) 1201 opset(AVMLHH, r) 1202 opset(AVMLHF, r) 1203 opset(AVMLH, r) 1204 opset(AVMLHW, r) 1205 opset(AVMLF, r) 1206 opset(AVNO, r) 1207 opset(AVO, r) 1208 opset(AVPKH, r) 1209 opset(AVPKF, r) 1210 opset(AVPKG, r) 1211 opset(AVSUMGH, r) 1212 opset(AVSUMGF, r) 1213 opset(AVSUMQF, r) 1214 opset(AVSUMQG, r) 1215 opset(AVSUMB, r) 1216 opset(AVSUMH, r) 1217 case AVERLLVG: 1218 opset(AVERLLVB, r) 1219 opset(AVERLLVH, r) 1220 opset(AVERLLVF, r) 1221 opset(AVESLVB, r) 1222 opset(AVESLVH, r) 1223 opset(AVESLVF, r) 1224 opset(AVESLVG, r) 1225 opset(AVESRAVB, r) 1226 opset(AVESRAVH, r) 1227 opset(AVESRAVF, r) 1228 opset(AVESRAVG, r) 1229 opset(AVESRLVB, r) 1230 opset(AVESRLVH, r) 1231 opset(AVESRLVF, r) 1232 opset(AVESRLVG, r) 1233 opset(AVFDDB, r) 1234 opset(AWFDDB, r) 1235 opset(AVFSDB, r) 1236 opset(AWFSDB, r) 1237 opset(AVSL, r) 1238 opset(AVSLB, r) 1239 opset(AVSRA, r) 1240 opset(AVSRAB, r) 1241 opset(AVSRL, r) 1242 opset(AVSRLB, r) 1243 opset(AVSF, r) 1244 opset(AVSG, r) 1245 opset(AVSQ, r) 1246 opset(AVSCBIB, r) 1247 opset(AVSCBIH, r) 1248 opset(AVSCBIF, r) 1249 opset(AVSCBIG, r) 1250 opset(AVSCBIQ, r) 1251 case AVACQ: 1252 opset(AVACCCQ, r) 1253 opset(AVGFMAB, r) 1254 opset(AVGFMAH, r) 1255 opset(AVGFMAF, r) 1256 opset(AVGFMAG, r) 1257 opset(AVMALB, r) 1258 opset(AVMALHW, r) 1259 opset(AVMALF, r) 1260 opset(AVMAHB, r) 1261 opset(AVMAHH, r) 1262 opset(AVMAHF, r) 1263 opset(AVMALHB, r) 1264 opset(AVMALHH, r) 1265 opset(AVMALHF, r) 1266 opset(AVMAEB, r) 1267 opset(AVMAEH, r) 1268 opset(AVMAEF, r) 1269 opset(AVMALEB, r) 1270 opset(AVMALEH, r) 1271 opset(AVMALEF, r) 1272 opset(AVMAOB, r) 1273 opset(AVMAOH, r) 1274 opset(AVMAOF, r) 1275 opset(AVMALOB, r) 1276 opset(AVMALOH, r) 1277 opset(AVMALOF, r) 1278 opset(AVSTRCB, r) 1279 opset(AVSTRCH, r) 1280 opset(AVSTRCF, r) 1281 opset(AVSTRCBS, r) 1282 opset(AVSTRCHS, r) 1283 opset(AVSTRCFS, r) 1284 opset(AVSTRCZB, r) 1285 opset(AVSTRCZH, r) 1286 opset(AVSTRCZF, r) 1287 opset(AVSTRCZBS, r) 1288 opset(AVSTRCZHS, r) 1289 opset(AVSTRCZFS, r) 1290 opset(AVSBCBIQ, r) 1291 opset(AVSBIQ, r) 1292 case AVSEL: 1293 opset(AVFMADB, r) 1294 opset(AWFMADB, r) 1295 opset(AVFMSDB, r) 1296 opset(AWFMSDB, r) 1297 opset(AVPERM, r) 1298 } 1299 } 1300 } 1301 1302 const ( 1303 op_A uint32 = 0x5A00 // FORMAT_RX1 ADD (32) 1304 op_AD uint32 = 0x6A00 // FORMAT_RX1 ADD NORMALIZED (long HFP) 1305 op_ADB uint32 = 0xED1A // FORMAT_RXE ADD (long BFP) 1306 op_ADBR uint32 = 0xB31A // FORMAT_RRE ADD (long BFP) 1307 op_ADR uint32 = 0x2A00 // FORMAT_RR ADD NORMALIZED (long HFP) 1308 op_ADTR uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1309 op_ADTRA uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1310 op_AE uint32 = 0x7A00 // FORMAT_RX1 ADD NORMALIZED (short HFP) 1311 op_AEB uint32 = 0xED0A // FORMAT_RXE ADD (short BFP) 1312 op_AEBR uint32 = 0xB30A // FORMAT_RRE ADD (short BFP) 1313 op_AER uint32 = 0x3A00 // FORMAT_RR ADD NORMALIZED (short HFP) 1314 op_AFI uint32 = 0xC209 // FORMAT_RIL1 ADD IMMEDIATE (32) 1315 op_AG uint32 = 0xE308 // FORMAT_RXY1 ADD (64) 1316 op_AGF uint32 = 0xE318 // FORMAT_RXY1 ADD (64<-32) 1317 op_AGFI uint32 = 0xC208 // FORMAT_RIL1 ADD IMMEDIATE (64<-32) 1318 op_AGFR uint32 = 0xB918 // FORMAT_RRE ADD (64<-32) 1319 op_AGHI uint32 = 0xA70B // FORMAT_RI1 ADD HALFWORD IMMEDIATE (64) 1320 op_AGHIK uint32 = 0xECD9 // FORMAT_RIE4 ADD IMMEDIATE (64<-16) 1321 op_AGR uint32 = 0xB908 // FORMAT_RRE ADD (64) 1322 op_AGRK uint32 = 0xB9E8 // FORMAT_RRF1 ADD (64) 1323 op_AGSI uint32 = 0xEB7A // FORMAT_SIY ADD IMMEDIATE (64<-8) 1324 op_AH uint32 = 0x4A00 // FORMAT_RX1 ADD HALFWORD 1325 op_AHHHR uint32 = 0xB9C8 // FORMAT_RRF1 ADD HIGH (32) 1326 op_AHHLR uint32 = 0xB9D8 // FORMAT_RRF1 ADD HIGH (32) 1327 op_AHI uint32 = 0xA70A // FORMAT_RI1 ADD HALFWORD IMMEDIATE (32) 1328 op_AHIK uint32 = 0xECD8 // FORMAT_RIE4 ADD IMMEDIATE (32<-16) 1329 op_AHY uint32 = 0xE37A // FORMAT_RXY1 ADD HALFWORD 1330 op_AIH uint32 = 0xCC08 // FORMAT_RIL1 ADD IMMEDIATE HIGH (32) 1331 op_AL uint32 = 0x5E00 // FORMAT_RX1 ADD LOGICAL (32) 1332 op_ALC uint32 = 0xE398 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (32) 1333 op_ALCG uint32 = 0xE388 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (64) 1334 op_ALCGR uint32 = 0xB988 // FORMAT_RRE ADD LOGICAL WITH CARRY (64) 1335 op_ALCR uint32 = 0xB998 // FORMAT_RRE ADD LOGICAL WITH CARRY (32) 1336 op_ALFI uint32 = 0xC20B // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (32) 1337 op_ALG uint32 = 0xE30A // FORMAT_RXY1 ADD LOGICAL (64) 1338 op_ALGF uint32 = 0xE31A // FORMAT_RXY1 ADD LOGICAL (64<-32) 1339 op_ALGFI uint32 = 0xC20A // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (64<-32) 1340 op_ALGFR uint32 = 0xB91A // FORMAT_RRE ADD LOGICAL (64<-32) 1341 op_ALGHSIK uint32 = 0xECDB // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16) 1342 op_ALGR uint32 = 0xB90A // FORMAT_RRE ADD LOGICAL (64) 1343 op_ALGRK uint32 = 0xB9EA // FORMAT_RRF1 ADD LOGICAL (64) 1344 op_ALGSI uint32 = 0xEB7E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8) 1345 op_ALHHHR uint32 = 0xB9CA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1346 op_ALHHLR uint32 = 0xB9DA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1347 op_ALHSIK uint32 = 0xECDA // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16) 1348 op_ALR uint32 = 0x1E00 // FORMAT_RR ADD LOGICAL (32) 1349 op_ALRK uint32 = 0xB9FA // FORMAT_RRF1 ADD LOGICAL (32) 1350 op_ALSI uint32 = 0xEB6E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8) 1351 op_ALSIH uint32 = 0xCC0A // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1352 op_ALSIHN uint32 = 0xCC0B // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1353 op_ALY uint32 = 0xE35E // FORMAT_RXY1 ADD LOGICAL (32) 1354 op_AP uint32 = 0xFA00 // FORMAT_SS2 ADD DECIMAL 1355 op_AR uint32 = 0x1A00 // FORMAT_RR ADD (32) 1356 op_ARK uint32 = 0xB9F8 // FORMAT_RRF1 ADD (32) 1357 op_ASI uint32 = 0xEB6A // FORMAT_SIY ADD IMMEDIATE (32<-8) 1358 op_AU uint32 = 0x7E00 // FORMAT_RX1 ADD UNNORMALIZED (short HFP) 1359 op_AUR uint32 = 0x3E00 // FORMAT_RR ADD UNNORMALIZED (short HFP) 1360 op_AW uint32 = 0x6E00 // FORMAT_RX1 ADD UNNORMALIZED (long HFP) 1361 op_AWR uint32 = 0x2E00 // FORMAT_RR ADD UNNORMALIZED (long HFP) 1362 op_AXBR uint32 = 0xB34A // FORMAT_RRE ADD (extended BFP) 1363 op_AXR uint32 = 0x3600 // FORMAT_RR ADD NORMALIZED (extended HFP) 1364 op_AXTR uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1365 op_AXTRA uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1366 op_AY uint32 = 0xE35A // FORMAT_RXY1 ADD (32) 1367 op_BAKR uint32 = 0xB240 // FORMAT_RRE BRANCH AND STACK 1368 op_BAL uint32 = 0x4500 // FORMAT_RX1 BRANCH AND LINK 1369 op_BALR uint32 = 0x0500 // FORMAT_RR BRANCH AND LINK 1370 op_BAS uint32 = 0x4D00 // FORMAT_RX1 BRANCH AND SAVE 1371 op_BASR uint32 = 0x0D00 // FORMAT_RR BRANCH AND SAVE 1372 op_BASSM uint32 = 0x0C00 // FORMAT_RR BRANCH AND SAVE AND SET MODE 1373 op_BC uint32 = 0x4700 // FORMAT_RX2 BRANCH ON CONDITION 1374 op_BCR uint32 = 0x0700 // FORMAT_RR BRANCH ON CONDITION 1375 op_BCT uint32 = 0x4600 // FORMAT_RX1 BRANCH ON COUNT (32) 1376 op_BCTG uint32 = 0xE346 // FORMAT_RXY1 BRANCH ON COUNT (64) 1377 op_BCTGR uint32 = 0xB946 // FORMAT_RRE BRANCH ON COUNT (64) 1378 op_BCTR uint32 = 0x0600 // FORMAT_RR BRANCH ON COUNT (32) 1379 op_BPP uint32 = 0xC700 // FORMAT_SMI BRANCH PREDICTION PRELOAD 1380 op_BPRP uint32 = 0xC500 // FORMAT_MII BRANCH PREDICTION RELATIVE PRELOAD 1381 op_BRAS uint32 = 0xA705 // FORMAT_RI2 BRANCH RELATIVE AND SAVE 1382 op_BRASL uint32 = 0xC005 // FORMAT_RIL2 BRANCH RELATIVE AND SAVE LONG 1383 op_BRC uint32 = 0xA704 // FORMAT_RI3 BRANCH RELATIVE ON CONDITION 1384 op_BRCL uint32 = 0xC004 // FORMAT_RIL3 BRANCH RELATIVE ON CONDITION LONG 1385 op_BRCT uint32 = 0xA706 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (32) 1386 op_BRCTG uint32 = 0xA707 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (64) 1387 op_BRCTH uint32 = 0xCC06 // FORMAT_RIL2 BRANCH RELATIVE ON COUNT HIGH (32) 1388 op_BRXH uint32 = 0x8400 // FORMAT_RSI BRANCH RELATIVE ON INDEX HIGH (32) 1389 op_BRXHG uint32 = 0xEC44 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX HIGH (64) 1390 op_BRXLE uint32 = 0x8500 // FORMAT_RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32) 1391 op_BRXLG uint32 = 0xEC45 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX LOW OR EQ. (64) 1392 op_BSA uint32 = 0xB25A // FORMAT_RRE BRANCH AND SET AUTHORITY 1393 op_BSG uint32 = 0xB258 // FORMAT_RRE BRANCH IN SUBSPACE GROUP 1394 op_BSM uint32 = 0x0B00 // FORMAT_RR BRANCH AND SET MODE 1395 op_BXH uint32 = 0x8600 // FORMAT_RS1 BRANCH ON INDEX HIGH (32) 1396 op_BXHG uint32 = 0xEB44 // FORMAT_RSY1 BRANCH ON INDEX HIGH (64) 1397 op_BXLE uint32 = 0x8700 // FORMAT_RS1 BRANCH ON INDEX LOW OR EQUAL (32) 1398 op_BXLEG uint32 = 0xEB45 // FORMAT_RSY1 BRANCH ON INDEX LOW OR EQUAL (64) 1399 op_C uint32 = 0x5900 // FORMAT_RX1 COMPARE (32) 1400 op_CD uint32 = 0x6900 // FORMAT_RX1 COMPARE (long HFP) 1401 op_CDB uint32 = 0xED19 // FORMAT_RXE COMPARE (long BFP) 1402 op_CDBR uint32 = 0xB319 // FORMAT_RRE COMPARE (long BFP) 1403 op_CDFBR uint32 = 0xB395 // FORMAT_RRE CONVERT FROM FIXED (32 to long BFP) 1404 op_CDFBRA uint32 = 0xB395 // FORMAT_RRF5 CONVERT FROM FIXED (32 to long BFP) 1405 op_CDFR uint32 = 0xB3B5 // FORMAT_RRE CONVERT FROM FIXED (32 to long HFP) 1406 op_CDFTR uint32 = 0xB951 // FORMAT_RRE CONVERT FROM FIXED (32 to long DFP) 1407 op_CDGBR uint32 = 0xB3A5 // FORMAT_RRE CONVERT FROM FIXED (64 to long BFP) 1408 op_CDGBRA uint32 = 0xB3A5 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long BFP) 1409 op_CDGR uint32 = 0xB3C5 // FORMAT_RRE CONVERT FROM FIXED (64 to long HFP) 1410 op_CDGTR uint32 = 0xB3F1 // FORMAT_RRE CONVERT FROM FIXED (64 to long DFP) 1411 op_CDGTRA uint32 = 0xB3F1 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long DFP) 1412 op_CDLFBR uint32 = 0xB391 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long BFP) 1413 op_CDLFTR uint32 = 0xB953 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long DFP) 1414 op_CDLGBR uint32 = 0xB3A1 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long BFP) 1415 op_CDLGTR uint32 = 0xB952 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long DFP) 1416 op_CDR uint32 = 0x2900 // FORMAT_RR COMPARE (long HFP) 1417 op_CDS uint32 = 0xBB00 // FORMAT_RS1 COMPARE DOUBLE AND SWAP (32) 1418 op_CDSG uint32 = 0xEB3E // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (64) 1419 op_CDSTR uint32 = 0xB3F3 // FORMAT_RRE CONVERT FROM SIGNED PACKED (64 to long DFP) 1420 op_CDSY uint32 = 0xEB31 // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (32) 1421 op_CDTR uint32 = 0xB3E4 // FORMAT_RRE COMPARE (long DFP) 1422 op_CDUTR uint32 = 0xB3F2 // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP) 1423 op_CDZT uint32 = 0xEDAA // FORMAT_RSL CONVERT FROM ZONED (to long DFP) 1424 op_CE uint32 = 0x7900 // FORMAT_RX1 COMPARE (short HFP) 1425 op_CEB uint32 = 0xED09 // FORMAT_RXE COMPARE (short BFP) 1426 op_CEBR uint32 = 0xB309 // FORMAT_RRE COMPARE (short BFP) 1427 op_CEDTR uint32 = 0xB3F4 // FORMAT_RRE COMPARE BIASED EXPONENT (long DFP) 1428 op_CEFBR uint32 = 0xB394 // FORMAT_RRE CONVERT FROM FIXED (32 to short BFP) 1429 op_CEFBRA uint32 = 0xB394 // FORMAT_RRF5 CONVERT FROM FIXED (32 to short BFP) 1430 op_CEFR uint32 = 0xB3B4 // FORMAT_RRE CONVERT FROM FIXED (32 to short HFP) 1431 op_CEGBR uint32 = 0xB3A4 // FORMAT_RRE CONVERT FROM FIXED (64 to short BFP) 1432 op_CEGBRA uint32 = 0xB3A4 // FORMAT_RRF5 CONVERT FROM FIXED (64 to short BFP) 1433 op_CEGR uint32 = 0xB3C4 // FORMAT_RRE CONVERT FROM FIXED (64 to short HFP) 1434 op_CELFBR uint32 = 0xB390 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to short BFP) 1435 op_CELGBR uint32 = 0xB3A0 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to short BFP) 1436 op_CER uint32 = 0x3900 // FORMAT_RR COMPARE (short HFP) 1437 op_CEXTR uint32 = 0xB3FC // FORMAT_RRE COMPARE BIASED EXPONENT (extended DFP) 1438 op_CFC uint32 = 0xB21A // FORMAT_S COMPARE AND FORM CODEWORD 1439 op_CFDBR uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1440 op_CFDBRA uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1441 op_CFDR uint32 = 0xB3B9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 32) 1442 op_CFDTR uint32 = 0xB941 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 32) 1443 op_CFEBR uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1444 op_CFEBRA uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1445 op_CFER uint32 = 0xB3B8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 32) 1446 op_CFI uint32 = 0xC20D // FORMAT_RIL1 COMPARE IMMEDIATE (32) 1447 op_CFXBR uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1448 op_CFXBRA uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1449 op_CFXR uint32 = 0xB3BA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 32) 1450 op_CFXTR uint32 = 0xB949 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 32) 1451 op_CG uint32 = 0xE320 // FORMAT_RXY1 COMPARE (64) 1452 op_CGDBR uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1453 op_CGDBRA uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1454 op_CGDR uint32 = 0xB3C9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 64) 1455 op_CGDTR uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1456 op_CGDTRA uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1457 op_CGEBR uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1458 op_CGEBRA uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1459 op_CGER uint32 = 0xB3C8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 64) 1460 op_CGF uint32 = 0xE330 // FORMAT_RXY1 COMPARE (64<-32) 1461 op_CGFI uint32 = 0xC20C // FORMAT_RIL1 COMPARE IMMEDIATE (64<-32) 1462 op_CGFR uint32 = 0xB930 // FORMAT_RRE COMPARE (64<-32) 1463 op_CGFRL uint32 = 0xC60C // FORMAT_RIL2 COMPARE RELATIVE LONG (64<-32) 1464 op_CGH uint32 = 0xE334 // FORMAT_RXY1 COMPARE HALFWORD (64<-16) 1465 op_CGHI uint32 = 0xA70F // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (64<-16) 1466 op_CGHRL uint32 = 0xC604 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (64<-16) 1467 op_CGHSI uint32 = 0xE558 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (64<-16) 1468 op_CGIB uint32 = 0xECFC // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (64<-8) 1469 op_CGIJ uint32 = 0xEC7C // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8) 1470 op_CGIT uint32 = 0xEC70 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (64<-16) 1471 op_CGR uint32 = 0xB920 // FORMAT_RRE COMPARE (64) 1472 op_CGRB uint32 = 0xECE4 // FORMAT_RRS COMPARE AND BRANCH (64) 1473 op_CGRJ uint32 = 0xEC64 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (64) 1474 op_CGRL uint32 = 0xC608 // FORMAT_RIL2 COMPARE RELATIVE LONG (64) 1475 op_CGRT uint32 = 0xB960 // FORMAT_RRF3 COMPARE AND TRAP (64) 1476 op_CGXBR uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1477 op_CGXBRA uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1478 op_CGXR uint32 = 0xB3CA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 64) 1479 op_CGXTR uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1480 op_CGXTRA uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1481 op_CH uint32 = 0x4900 // FORMAT_RX1 COMPARE HALFWORD (32<-16) 1482 op_CHF uint32 = 0xE3CD // FORMAT_RXY1 COMPARE HIGH (32) 1483 op_CHHR uint32 = 0xB9CD // FORMAT_RRE COMPARE HIGH (32) 1484 op_CHHSI uint32 = 0xE554 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (16) 1485 op_CHI uint32 = 0xA70E // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (32<-16) 1486 op_CHLR uint32 = 0xB9DD // FORMAT_RRE COMPARE HIGH (32) 1487 op_CHRL uint32 = 0xC605 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (32<-16) 1488 op_CHSI uint32 = 0xE55C // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (32<-16) 1489 op_CHY uint32 = 0xE379 // FORMAT_RXY1 COMPARE HALFWORD (32<-16) 1490 op_CIB uint32 = 0xECFE // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (32<-8) 1491 op_CIH uint32 = 0xCC0D // FORMAT_RIL1 COMPARE IMMEDIATE HIGH (32) 1492 op_CIJ uint32 = 0xEC7E // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8) 1493 op_CIT uint32 = 0xEC72 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (32<-16) 1494 op_CKSM uint32 = 0xB241 // FORMAT_RRE CHECKSUM 1495 op_CL uint32 = 0x5500 // FORMAT_RX1 COMPARE LOGICAL (32) 1496 op_CLC uint32 = 0xD500 // FORMAT_SS1 COMPARE LOGICAL (character) 1497 op_CLCL uint32 = 0x0F00 // FORMAT_RR COMPARE LOGICAL LONG 1498 op_CLCLE uint32 = 0xA900 // FORMAT_RS1 COMPARE LOGICAL LONG EXTENDED 1499 op_CLCLU uint32 = 0xEB8F // FORMAT_RSY1 COMPARE LOGICAL LONG UNICODE 1500 op_CLFDBR uint32 = 0xB39D // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 32) 1501 op_CLFDTR uint32 = 0xB943 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 32) 1502 op_CLFEBR uint32 = 0xB39C // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 32) 1503 op_CLFHSI uint32 = 0xE55D // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (32<-16) 1504 op_CLFI uint32 = 0xC20F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (32) 1505 op_CLFIT uint32 = 0xEC73 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16) 1506 op_CLFXBR uint32 = 0xB39E // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 32) 1507 op_CLFXTR uint32 = 0xB94B // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 32) 1508 op_CLG uint32 = 0xE321 // FORMAT_RXY1 COMPARE LOGICAL (64) 1509 op_CLGDBR uint32 = 0xB3AD // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 64) 1510 op_CLGDTR uint32 = 0xB942 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 64) 1511 op_CLGEBR uint32 = 0xB3AC // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 64) 1512 op_CLGF uint32 = 0xE331 // FORMAT_RXY1 COMPARE LOGICAL (64<-32) 1513 op_CLGFI uint32 = 0xC20E // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (64<-32) 1514 op_CLGFR uint32 = 0xB931 // FORMAT_RRE COMPARE LOGICAL (64<-32) 1515 op_CLGFRL uint32 = 0xC60E // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-32) 1516 op_CLGHRL uint32 = 0xC606 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-16) 1517 op_CLGHSI uint32 = 0xE559 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (64<-16) 1518 op_CLGIB uint32 = 0xECFD // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8) 1519 op_CLGIJ uint32 = 0xEC7D // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (64<-8) 1520 op_CLGIT uint32 = 0xEC71 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16) 1521 op_CLGR uint32 = 0xB921 // FORMAT_RRE COMPARE LOGICAL (64) 1522 op_CLGRB uint32 = 0xECE5 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (64) 1523 op_CLGRJ uint32 = 0xEC65 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (64) 1524 op_CLGRL uint32 = 0xC60A // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64) 1525 op_CLGRT uint32 = 0xB961 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (64) 1526 op_CLGT uint32 = 0xEB2B // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (64) 1527 op_CLGXBR uint32 = 0xB3AE // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 64) 1528 op_CLGXTR uint32 = 0xB94A // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 64) 1529 op_CLHF uint32 = 0xE3CF // FORMAT_RXY1 COMPARE LOGICAL HIGH (32) 1530 op_CLHHR uint32 = 0xB9CF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1531 op_CLHHSI uint32 = 0xE555 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (16) 1532 op_CLHLR uint32 = 0xB9DF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1533 op_CLHRL uint32 = 0xC607 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32<-16) 1534 op_CLI uint32 = 0x9500 // FORMAT_SI COMPARE LOGICAL (immediate) 1535 op_CLIB uint32 = 0xECFF // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8) 1536 op_CLIH uint32 = 0xCC0F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE HIGH (32) 1537 op_CLIJ uint32 = 0xEC7F // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (32<-8) 1538 op_CLIY uint32 = 0xEB55 // FORMAT_SIY COMPARE LOGICAL (immediate) 1539 op_CLM uint32 = 0xBD00 // FORMAT_RS2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1540 op_CLMH uint32 = 0xEB20 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (high) 1541 op_CLMY uint32 = 0xEB21 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1542 op_CLR uint32 = 0x1500 // FORMAT_RR COMPARE LOGICAL (32) 1543 op_CLRB uint32 = 0xECF7 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (32) 1544 op_CLRJ uint32 = 0xEC77 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (32) 1545 op_CLRL uint32 = 0xC60F // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32) 1546 op_CLRT uint32 = 0xB973 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (32) 1547 op_CLST uint32 = 0xB25D // FORMAT_RRE COMPARE LOGICAL STRING 1548 op_CLT uint32 = 0xEB23 // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (32) 1549 op_CLY uint32 = 0xE355 // FORMAT_RXY1 COMPARE LOGICAL (32) 1550 op_CMPSC uint32 = 0xB263 // FORMAT_RRE COMPRESSION CALL 1551 op_CP uint32 = 0xF900 // FORMAT_SS2 COMPARE DECIMAL 1552 op_CPSDR uint32 = 0xB372 // FORMAT_RRF2 COPY SIGN (long) 1553 op_CPYA uint32 = 0xB24D // FORMAT_RRE COPY ACCESS 1554 op_CR uint32 = 0x1900 // FORMAT_RR COMPARE (32) 1555 op_CRB uint32 = 0xECF6 // FORMAT_RRS COMPARE AND BRANCH (32) 1556 op_CRDTE uint32 = 0xB98F // FORMAT_RRF2 COMPARE AND REPLACE DAT TABLE ENTRY 1557 op_CRJ uint32 = 0xEC76 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (32) 1558 op_CRL uint32 = 0xC60D // FORMAT_RIL2 COMPARE RELATIVE LONG (32) 1559 op_CRT uint32 = 0xB972 // FORMAT_RRF3 COMPARE AND TRAP (32) 1560 op_CS uint32 = 0xBA00 // FORMAT_RS1 COMPARE AND SWAP (32) 1561 op_CSCH uint32 = 0xB230 // FORMAT_S CLEAR SUBCHANNEL 1562 op_CSDTR uint32 = 0xB3E3 // FORMAT_RRF4 CONVERT TO SIGNED PACKED (long DFP to 64) 1563 op_CSG uint32 = 0xEB30 // FORMAT_RSY1 COMPARE AND SWAP (64) 1564 op_CSP uint32 = 0xB250 // FORMAT_RRE COMPARE AND SWAP AND PURGE 1565 op_CSPG uint32 = 0xB98A // FORMAT_RRE COMPARE AND SWAP AND PURGE 1566 op_CSST uint32 = 0xC802 // FORMAT_SSF COMPARE AND SWAP AND STORE 1567 op_CSXTR uint32 = 0xB3EB // FORMAT_RRF4 CONVERT TO SIGNED PACKED (extended DFP to 128) 1568 op_CSY uint32 = 0xEB14 // FORMAT_RSY1 COMPARE AND SWAP (32) 1569 op_CU12 uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-16 1570 op_CU14 uint32 = 0xB9B0 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-32 1571 op_CU21 uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-8 1572 op_CU24 uint32 = 0xB9B1 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-32 1573 op_CU41 uint32 = 0xB9B2 // FORMAT_RRE CONVERT UTF-32 TO UTF-8 1574 op_CU42 uint32 = 0xB9B3 // FORMAT_RRE CONVERT UTF-32 TO UTF-16 1575 op_CUDTR uint32 = 0xB3E2 // FORMAT_RRE CONVERT TO UNSIGNED PACKED (long DFP to 64) 1576 op_CUSE uint32 = 0xB257 // FORMAT_RRE COMPARE UNTIL SUBSTRING EQUAL 1577 op_CUTFU uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UNICODE 1578 op_CUUTF uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UNICODE TO UTF-8 1579 op_CUXTR uint32 = 0xB3EA // FORMAT_RRE CONVERT TO UNSIGNED PACKED (extended DFP to 128) 1580 op_CVB uint32 = 0x4F00 // FORMAT_RX1 CONVERT TO BINARY (32) 1581 op_CVBG uint32 = 0xE30E // FORMAT_RXY1 CONVERT TO BINARY (64) 1582 op_CVBY uint32 = 0xE306 // FORMAT_RXY1 CONVERT TO BINARY (32) 1583 op_CVD uint32 = 0x4E00 // FORMAT_RX1 CONVERT TO DECIMAL (32) 1584 op_CVDG uint32 = 0xE32E // FORMAT_RXY1 CONVERT TO DECIMAL (64) 1585 op_CVDY uint32 = 0xE326 // FORMAT_RXY1 CONVERT TO DECIMAL (32) 1586 op_CXBR uint32 = 0xB349 // FORMAT_RRE COMPARE (extended BFP) 1587 op_CXFBR uint32 = 0xB396 // FORMAT_RRE CONVERT FROM FIXED (32 to extended BFP) 1588 op_CXFBRA uint32 = 0xB396 // FORMAT_RRF5 CONVERT FROM FIXED (32 to extended BFP) 1589 op_CXFR uint32 = 0xB3B6 // FORMAT_RRE CONVERT FROM FIXED (32 to extended HFP) 1590 op_CXFTR uint32 = 0xB959 // FORMAT_RRE CONVERT FROM FIXED (32 to extended DFP) 1591 op_CXGBR uint32 = 0xB3A6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended BFP) 1592 op_CXGBRA uint32 = 0xB3A6 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended BFP) 1593 op_CXGR uint32 = 0xB3C6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended HFP) 1594 op_CXGTR uint32 = 0xB3F9 // FORMAT_RRE CONVERT FROM FIXED (64 to extended DFP) 1595 op_CXGTRA uint32 = 0xB3F9 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended DFP) 1596 op_CXLFBR uint32 = 0xB392 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended BFP) 1597 op_CXLFTR uint32 = 0xB95B // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended DFP) 1598 op_CXLGBR uint32 = 0xB3A2 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended BFP) 1599 op_CXLGTR uint32 = 0xB95A // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended DFP) 1600 op_CXR uint32 = 0xB369 // FORMAT_RRE COMPARE (extended HFP) 1601 op_CXSTR uint32 = 0xB3FB // FORMAT_RRE CONVERT FROM SIGNED PACKED (128 to extended DFP) 1602 op_CXTR uint32 = 0xB3EC // FORMAT_RRE COMPARE (extended DFP) 1603 op_CXUTR uint32 = 0xB3FA // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) 1604 op_CXZT uint32 = 0xEDAB // FORMAT_RSL CONVERT FROM ZONED (to extended DFP) 1605 op_CY uint32 = 0xE359 // FORMAT_RXY1 COMPARE (32) 1606 op_CZDT uint32 = 0xEDA8 // FORMAT_RSL CONVERT TO ZONED (from long DFP) 1607 op_CZXT uint32 = 0xEDA9 // FORMAT_RSL CONVERT TO ZONED (from extended DFP) 1608 op_D uint32 = 0x5D00 // FORMAT_RX1 DIVIDE (32<-64) 1609 op_DD uint32 = 0x6D00 // FORMAT_RX1 DIVIDE (long HFP) 1610 op_DDB uint32 = 0xED1D // FORMAT_RXE DIVIDE (long BFP) 1611 op_DDBR uint32 = 0xB31D // FORMAT_RRE DIVIDE (long BFP) 1612 op_DDR uint32 = 0x2D00 // FORMAT_RR DIVIDE (long HFP) 1613 op_DDTR uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1614 op_DDTRA uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1615 op_DE uint32 = 0x7D00 // FORMAT_RX1 DIVIDE (short HFP) 1616 op_DEB uint32 = 0xED0D // FORMAT_RXE DIVIDE (short BFP) 1617 op_DEBR uint32 = 0xB30D // FORMAT_RRE DIVIDE (short BFP) 1618 op_DER uint32 = 0x3D00 // FORMAT_RR DIVIDE (short HFP) 1619 op_DIDBR uint32 = 0xB35B // FORMAT_RRF2 DIVIDE TO INTEGER (long BFP) 1620 op_DIEBR uint32 = 0xB353 // FORMAT_RRF2 DIVIDE TO INTEGER (short BFP) 1621 op_DL uint32 = 0xE397 // FORMAT_RXY1 DIVIDE LOGICAL (32<-64) 1622 op_DLG uint32 = 0xE387 // FORMAT_RXY1 DIVIDE LOGICAL (64<-128) 1623 op_DLGR uint32 = 0xB987 // FORMAT_RRE DIVIDE LOGICAL (64<-128) 1624 op_DLR uint32 = 0xB997 // FORMAT_RRE DIVIDE LOGICAL (32<-64) 1625 op_DP uint32 = 0xFD00 // FORMAT_SS2 DIVIDE DECIMAL 1626 op_DR uint32 = 0x1D00 // FORMAT_RR DIVIDE (32<-64) 1627 op_DSG uint32 = 0xE30D // FORMAT_RXY1 DIVIDE SINGLE (64) 1628 op_DSGF uint32 = 0xE31D // FORMAT_RXY1 DIVIDE SINGLE (64<-32) 1629 op_DSGFR uint32 = 0xB91D // FORMAT_RRE DIVIDE SINGLE (64<-32) 1630 op_DSGR uint32 = 0xB90D // FORMAT_RRE DIVIDE SINGLE (64) 1631 op_DXBR uint32 = 0xB34D // FORMAT_RRE DIVIDE (extended BFP) 1632 op_DXR uint32 = 0xB22D // FORMAT_RRE DIVIDE (extended HFP) 1633 op_DXTR uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1634 op_DXTRA uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1635 op_EAR uint32 = 0xB24F // FORMAT_RRE EXTRACT ACCESS 1636 op_ECAG uint32 = 0xEB4C // FORMAT_RSY1 EXTRACT CACHE ATTRIBUTE 1637 op_ECTG uint32 = 0xC801 // FORMAT_SSF EXTRACT CPU TIME 1638 op_ED uint32 = 0xDE00 // FORMAT_SS1 EDIT 1639 op_EDMK uint32 = 0xDF00 // FORMAT_SS1 EDIT AND MARK 1640 op_EEDTR uint32 = 0xB3E5 // FORMAT_RRE EXTRACT BIASED EXPONENT (long DFP to 64) 1641 op_EEXTR uint32 = 0xB3ED // FORMAT_RRE EXTRACT BIASED EXPONENT (extended DFP to 64) 1642 op_EFPC uint32 = 0xB38C // FORMAT_RRE EXTRACT FPC 1643 op_EPAIR uint32 = 0xB99A // FORMAT_RRE EXTRACT PRIMARY ASN AND INSTANCE 1644 op_EPAR uint32 = 0xB226 // FORMAT_RRE EXTRACT PRIMARY ASN 1645 op_EPSW uint32 = 0xB98D // FORMAT_RRE EXTRACT PSW 1646 op_EREG uint32 = 0xB249 // FORMAT_RRE EXTRACT STACKED REGISTERS (32) 1647 op_EREGG uint32 = 0xB90E // FORMAT_RRE EXTRACT STACKED REGISTERS (64) 1648 op_ESAIR uint32 = 0xB99B // FORMAT_RRE EXTRACT SECONDARY ASN AND INSTANCE 1649 op_ESAR uint32 = 0xB227 // FORMAT_RRE EXTRACT SECONDARY ASN 1650 op_ESDTR uint32 = 0xB3E7 // FORMAT_RRE EXTRACT SIGNIFICANCE (long DFP) 1651 op_ESEA uint32 = 0xB99D // FORMAT_RRE EXTRACT AND SET EXTENDED AUTHORITY 1652 op_ESTA uint32 = 0xB24A // FORMAT_RRE EXTRACT STACKED STATE 1653 op_ESXTR uint32 = 0xB3EF // FORMAT_RRE EXTRACT SIGNIFICANCE (extended DFP) 1654 op_ETND uint32 = 0xB2EC // FORMAT_RRE EXTRACT TRANSACTION NESTING DEPTH 1655 op_EX uint32 = 0x4400 // FORMAT_RX1 EXECUTE 1656 op_EXRL uint32 = 0xC600 // FORMAT_RIL2 EXECUTE RELATIVE LONG 1657 op_FIDBR uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1658 op_FIDBRA uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1659 op_FIDR uint32 = 0xB37F // FORMAT_RRE LOAD FP INTEGER (long HFP) 1660 op_FIDTR uint32 = 0xB3D7 // FORMAT_RRF5 LOAD FP INTEGER (long DFP) 1661 op_FIEBR uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1662 op_FIEBRA uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1663 op_FIER uint32 = 0xB377 // FORMAT_RRE LOAD FP INTEGER (short HFP) 1664 op_FIXBR uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1665 op_FIXBRA uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1666 op_FIXR uint32 = 0xB367 // FORMAT_RRE LOAD FP INTEGER (extended HFP) 1667 op_FIXTR uint32 = 0xB3DF // FORMAT_RRF5 LOAD FP INTEGER (extended DFP) 1668 op_FLOGR uint32 = 0xB983 // FORMAT_RRE FIND LEFTMOST ONE 1669 op_HDR uint32 = 0x2400 // FORMAT_RR HALVE (long HFP) 1670 op_HER uint32 = 0x3400 // FORMAT_RR HALVE (short HFP) 1671 op_HSCH uint32 = 0xB231 // FORMAT_S HALT SUBCHANNEL 1672 op_IAC uint32 = 0xB224 // FORMAT_RRE INSERT ADDRESS SPACE CONTROL 1673 op_IC uint32 = 0x4300 // FORMAT_RX1 INSERT CHARACTER 1674 op_ICM uint32 = 0xBF00 // FORMAT_RS2 INSERT CHARACTERS UNDER MASK (low) 1675 op_ICMH uint32 = 0xEB80 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (high) 1676 op_ICMY uint32 = 0xEB81 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (low) 1677 op_ICY uint32 = 0xE373 // FORMAT_RXY1 INSERT CHARACTER 1678 op_IDTE uint32 = 0xB98E // FORMAT_RRF2 INVALIDATE DAT TABLE ENTRY 1679 op_IEDTR uint32 = 0xB3F6 // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to long DFP) 1680 op_IEXTR uint32 = 0xB3FE // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to extended DFP) 1681 op_IIHF uint32 = 0xC008 // FORMAT_RIL1 INSERT IMMEDIATE (high) 1682 op_IIHH uint32 = 0xA500 // FORMAT_RI1 INSERT IMMEDIATE (high high) 1683 op_IIHL uint32 = 0xA501 // FORMAT_RI1 INSERT IMMEDIATE (high low) 1684 op_IILF uint32 = 0xC009 // FORMAT_RIL1 INSERT IMMEDIATE (low) 1685 op_IILH uint32 = 0xA502 // FORMAT_RI1 INSERT IMMEDIATE (low high) 1686 op_IILL uint32 = 0xA503 // FORMAT_RI1 INSERT IMMEDIATE (low low) 1687 op_IPK uint32 = 0xB20B // FORMAT_S INSERT PSW KEY 1688 op_IPM uint32 = 0xB222 // FORMAT_RRE INSERT PROGRAM MASK 1689 op_IPTE uint32 = 0xB221 // FORMAT_RRF1 INVALIDATE PAGE TABLE ENTRY 1690 op_ISKE uint32 = 0xB229 // FORMAT_RRE INSERT STORAGE KEY EXTENDED 1691 op_IVSK uint32 = 0xB223 // FORMAT_RRE INSERT VIRTUAL STORAGE KEY 1692 op_KDB uint32 = 0xED18 // FORMAT_RXE COMPARE AND SIGNAL (long BFP) 1693 op_KDBR uint32 = 0xB318 // FORMAT_RRE COMPARE AND SIGNAL (long BFP) 1694 op_KDTR uint32 = 0xB3E0 // FORMAT_RRE COMPARE AND SIGNAL (long DFP) 1695 op_KEB uint32 = 0xED08 // FORMAT_RXE COMPARE AND SIGNAL (short BFP) 1696 op_KEBR uint32 = 0xB308 // FORMAT_RRE COMPARE AND SIGNAL (short BFP) 1697 op_KIMD uint32 = 0xB93E // FORMAT_RRE COMPUTE INTERMEDIATE MESSAGE DIGEST 1698 op_KLMD uint32 = 0xB93F // FORMAT_RRE COMPUTE LAST MESSAGE DIGEST 1699 op_KM uint32 = 0xB92E // FORMAT_RRE CIPHER MESSAGE 1700 op_KMAC uint32 = 0xB91E // FORMAT_RRE COMPUTE MESSAGE AUTHENTICATION CODE 1701 op_KMC uint32 = 0xB92F // FORMAT_RRE CIPHER MESSAGE WITH CHAINING 1702 op_KMCTR uint32 = 0xB92D // FORMAT_RRF2 CIPHER MESSAGE WITH COUNTER 1703 op_KMF uint32 = 0xB92A // FORMAT_RRE CIPHER MESSAGE WITH CFB 1704 op_KMO uint32 = 0xB92B // FORMAT_RRE CIPHER MESSAGE WITH OFB 1705 op_KXBR uint32 = 0xB348 // FORMAT_RRE COMPARE AND SIGNAL (extended BFP) 1706 op_KXTR uint32 = 0xB3E8 // FORMAT_RRE COMPARE AND SIGNAL (extended DFP) 1707 op_L uint32 = 0x5800 // FORMAT_RX1 LOAD (32) 1708 op_LA uint32 = 0x4100 // FORMAT_RX1 LOAD ADDRESS 1709 op_LAA uint32 = 0xEBF8 // FORMAT_RSY1 LOAD AND ADD (32) 1710 op_LAAG uint32 = 0xEBE8 // FORMAT_RSY1 LOAD AND ADD (64) 1711 op_LAAL uint32 = 0xEBFA // FORMAT_RSY1 LOAD AND ADD LOGICAL (32) 1712 op_LAALG uint32 = 0xEBEA // FORMAT_RSY1 LOAD AND ADD LOGICAL (64) 1713 op_LAE uint32 = 0x5100 // FORMAT_RX1 LOAD ADDRESS EXTENDED 1714 op_LAEY uint32 = 0xE375 // FORMAT_RXY1 LOAD ADDRESS EXTENDED 1715 op_LAM uint32 = 0x9A00 // FORMAT_RS1 LOAD ACCESS MULTIPLE 1716 op_LAMY uint32 = 0xEB9A // FORMAT_RSY1 LOAD ACCESS MULTIPLE 1717 op_LAN uint32 = 0xEBF4 // FORMAT_RSY1 LOAD AND AND (32) 1718 op_LANG uint32 = 0xEBE4 // FORMAT_RSY1 LOAD AND AND (64) 1719 op_LAO uint32 = 0xEBF6 // FORMAT_RSY1 LOAD AND OR (32) 1720 op_LAOG uint32 = 0xEBE6 // FORMAT_RSY1 LOAD AND OR (64) 1721 op_LARL uint32 = 0xC000 // FORMAT_RIL2 LOAD ADDRESS RELATIVE LONG 1722 op_LASP uint32 = 0xE500 // FORMAT_SSE LOAD ADDRESS SPACE PARAMETERS 1723 op_LAT uint32 = 0xE39F // FORMAT_RXY1 LOAD AND TRAP (32L<-32) 1724 op_LAX uint32 = 0xEBF7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (32) 1725 op_LAXG uint32 = 0xEBE7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (64) 1726 op_LAY uint32 = 0xE371 // FORMAT_RXY1 LOAD ADDRESS 1727 op_LB uint32 = 0xE376 // FORMAT_RXY1 LOAD BYTE (32) 1728 op_LBH uint32 = 0xE3C0 // FORMAT_RXY1 LOAD BYTE HIGH (32<-8) 1729 op_LBR uint32 = 0xB926 // FORMAT_RRE LOAD BYTE (32) 1730 op_LCDBR uint32 = 0xB313 // FORMAT_RRE LOAD COMPLEMENT (long BFP) 1731 op_LCDFR uint32 = 0xB373 // FORMAT_RRE LOAD COMPLEMENT (long) 1732 op_LCDR uint32 = 0x2300 // FORMAT_RR LOAD COMPLEMENT (long HFP) 1733 op_LCEBR uint32 = 0xB303 // FORMAT_RRE LOAD COMPLEMENT (short BFP) 1734 op_LCER uint32 = 0x3300 // FORMAT_RR LOAD COMPLEMENT (short HFP) 1735 op_LCGFR uint32 = 0xB913 // FORMAT_RRE LOAD COMPLEMENT (64<-32) 1736 op_LCGR uint32 = 0xB903 // FORMAT_RRE LOAD COMPLEMENT (64) 1737 op_LCR uint32 = 0x1300 // FORMAT_RR LOAD COMPLEMENT (32) 1738 op_LCTL uint32 = 0xB700 // FORMAT_RS1 LOAD CONTROL (32) 1739 op_LCTLG uint32 = 0xEB2F // FORMAT_RSY1 LOAD CONTROL (64) 1740 op_LCXBR uint32 = 0xB343 // FORMAT_RRE LOAD COMPLEMENT (extended BFP) 1741 op_LCXR uint32 = 0xB363 // FORMAT_RRE LOAD COMPLEMENT (extended HFP) 1742 op_LD uint32 = 0x6800 // FORMAT_RX1 LOAD (long) 1743 op_LDE uint32 = 0xED24 // FORMAT_RXE LOAD LENGTHENED (short to long HFP) 1744 op_LDEB uint32 = 0xED04 // FORMAT_RXE LOAD LENGTHENED (short to long BFP) 1745 op_LDEBR uint32 = 0xB304 // FORMAT_RRE LOAD LENGTHENED (short to long BFP) 1746 op_LDER uint32 = 0xB324 // FORMAT_RRE LOAD LENGTHENED (short to long HFP) 1747 op_LDETR uint32 = 0xB3D4 // FORMAT_RRF4 LOAD LENGTHENED (short to long DFP) 1748 op_LDGR uint32 = 0xB3C1 // FORMAT_RRE LOAD FPR FROM GR (64 to long) 1749 op_LDR uint32 = 0x2800 // FORMAT_RR LOAD (long) 1750 op_LDXBR uint32 = 0xB345 // FORMAT_RRE LOAD ROUNDED (extended to long BFP) 1751 op_LDXBRA uint32 = 0xB345 // FORMAT_RRF5 LOAD ROUNDED (extended to long BFP) 1752 op_LDXR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1753 op_LDXTR uint32 = 0xB3DD // FORMAT_RRF5 LOAD ROUNDED (extended to long DFP) 1754 op_LDY uint32 = 0xED65 // FORMAT_RXY1 LOAD (long) 1755 op_LE uint32 = 0x7800 // FORMAT_RX1 LOAD (short) 1756 op_LEDBR uint32 = 0xB344 // FORMAT_RRE LOAD ROUNDED (long to short BFP) 1757 op_LEDBRA uint32 = 0xB344 // FORMAT_RRF5 LOAD ROUNDED (long to short BFP) 1758 op_LEDR uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1759 op_LEDTR uint32 = 0xB3D5 // FORMAT_RRF5 LOAD ROUNDED (long to short DFP) 1760 op_LER uint32 = 0x3800 // FORMAT_RR LOAD (short) 1761 op_LEXBR uint32 = 0xB346 // FORMAT_RRE LOAD ROUNDED (extended to short BFP) 1762 op_LEXBRA uint32 = 0xB346 // FORMAT_RRF5 LOAD ROUNDED (extended to short BFP) 1763 op_LEXR uint32 = 0xB366 // FORMAT_RRE LOAD ROUNDED (extended to short HFP) 1764 op_LEY uint32 = 0xED64 // FORMAT_RXY1 LOAD (short) 1765 op_LFAS uint32 = 0xB2BD // FORMAT_S LOAD FPC AND SIGNAL 1766 op_LFH uint32 = 0xE3CA // FORMAT_RXY1 LOAD HIGH (32) 1767 op_LFHAT uint32 = 0xE3C8 // FORMAT_RXY1 LOAD HIGH AND TRAP (32H<-32) 1768 op_LFPC uint32 = 0xB29D // FORMAT_S LOAD FPC 1769 op_LG uint32 = 0xE304 // FORMAT_RXY1 LOAD (64) 1770 op_LGAT uint32 = 0xE385 // FORMAT_RXY1 LOAD AND TRAP (64) 1771 op_LGB uint32 = 0xE377 // FORMAT_RXY1 LOAD BYTE (64) 1772 op_LGBR uint32 = 0xB906 // FORMAT_RRE LOAD BYTE (64) 1773 op_LGDR uint32 = 0xB3CD // FORMAT_RRE LOAD GR FROM FPR (long to 64) 1774 op_LGF uint32 = 0xE314 // FORMAT_RXY1 LOAD (64<-32) 1775 op_LGFI uint32 = 0xC001 // FORMAT_RIL1 LOAD IMMEDIATE (64<-32) 1776 op_LGFR uint32 = 0xB914 // FORMAT_RRE LOAD (64<-32) 1777 op_LGFRL uint32 = 0xC40C // FORMAT_RIL2 LOAD RELATIVE LONG (64<-32) 1778 op_LGH uint32 = 0xE315 // FORMAT_RXY1 LOAD HALFWORD (64) 1779 op_LGHI uint32 = 0xA709 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (64) 1780 op_LGHR uint32 = 0xB907 // FORMAT_RRE LOAD HALFWORD (64) 1781 op_LGHRL uint32 = 0xC404 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (64<-16) 1782 op_LGR uint32 = 0xB904 // FORMAT_RRE LOAD (64) 1783 op_LGRL uint32 = 0xC408 // FORMAT_RIL2 LOAD RELATIVE LONG (64) 1784 op_LH uint32 = 0x4800 // FORMAT_RX1 LOAD HALFWORD (32) 1785 op_LHH uint32 = 0xE3C4 // FORMAT_RXY1 LOAD HALFWORD HIGH (32<-16) 1786 op_LHI uint32 = 0xA708 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (32) 1787 op_LHR uint32 = 0xB927 // FORMAT_RRE LOAD HALFWORD (32) 1788 op_LHRL uint32 = 0xC405 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (32<-16) 1789 op_LHY uint32 = 0xE378 // FORMAT_RXY1 LOAD HALFWORD (32) 1790 op_LLC uint32 = 0xE394 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (32) 1791 op_LLCH uint32 = 0xE3C2 // FORMAT_RXY1 LOAD LOGICAL CHARACTER HIGH (32<-8) 1792 op_LLCR uint32 = 0xB994 // FORMAT_RRE LOAD LOGICAL CHARACTER (32) 1793 op_LLGC uint32 = 0xE390 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (64) 1794 op_LLGCR uint32 = 0xB984 // FORMAT_RRE LOAD LOGICAL CHARACTER (64) 1795 op_LLGF uint32 = 0xE316 // FORMAT_RXY1 LOAD LOGICAL (64<-32) 1796 op_LLGFAT uint32 = 0xE39D // FORMAT_RXY1 LOAD LOGICAL AND TRAP (64<-32) 1797 op_LLGFR uint32 = 0xB916 // FORMAT_RRE LOAD LOGICAL (64<-32) 1798 op_LLGFRL uint32 = 0xC40E // FORMAT_RIL2 LOAD LOGICAL RELATIVE LONG (64<-32) 1799 op_LLGH uint32 = 0xE391 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (64) 1800 op_LLGHR uint32 = 0xB985 // FORMAT_RRE LOAD LOGICAL HALFWORD (64) 1801 op_LLGHRL uint32 = 0xC406 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16) 1802 op_LLGT uint32 = 0xE317 // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS 1803 op_LLGTAT uint32 = 0xE39C // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31) 1804 op_LLGTR uint32 = 0xB917 // FORMAT_RRE LOAD LOGICAL THIRTY ONE BITS 1805 op_LLH uint32 = 0xE395 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (32) 1806 op_LLHH uint32 = 0xE3C6 // FORMAT_RXY1 LOAD LOGICAL HALFWORD HIGH (32<-16) 1807 op_LLHR uint32 = 0xB995 // FORMAT_RRE LOAD LOGICAL HALFWORD (32) 1808 op_LLHRL uint32 = 0xC402 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16) 1809 op_LLIHF uint32 = 0xC00E // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (high) 1810 op_LLIHH uint32 = 0xA50C // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high high) 1811 op_LLIHL uint32 = 0xA50D // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high low) 1812 op_LLILF uint32 = 0xC00F // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (low) 1813 op_LLILH uint32 = 0xA50E // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low high) 1814 op_LLILL uint32 = 0xA50F // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low low) 1815 op_LM uint32 = 0x9800 // FORMAT_RS1 LOAD MULTIPLE (32) 1816 op_LMD uint32 = 0xEF00 // FORMAT_SS5 LOAD MULTIPLE DISJOINT 1817 op_LMG uint32 = 0xEB04 // FORMAT_RSY1 LOAD MULTIPLE (64) 1818 op_LMH uint32 = 0xEB96 // FORMAT_RSY1 LOAD MULTIPLE HIGH 1819 op_LMY uint32 = 0xEB98 // FORMAT_RSY1 LOAD MULTIPLE (32) 1820 op_LNDBR uint32 = 0xB311 // FORMAT_RRE LOAD NEGATIVE (long BFP) 1821 op_LNDFR uint32 = 0xB371 // FORMAT_RRE LOAD NEGATIVE (long) 1822 op_LNDR uint32 = 0x2100 // FORMAT_RR LOAD NEGATIVE (long HFP) 1823 op_LNEBR uint32 = 0xB301 // FORMAT_RRE LOAD NEGATIVE (short BFP) 1824 op_LNER uint32 = 0x3100 // FORMAT_RR LOAD NEGATIVE (short HFP) 1825 op_LNGFR uint32 = 0xB911 // FORMAT_RRE LOAD NEGATIVE (64<-32) 1826 op_LNGR uint32 = 0xB901 // FORMAT_RRE LOAD NEGATIVE (64) 1827 op_LNR uint32 = 0x1100 // FORMAT_RR LOAD NEGATIVE (32) 1828 op_LNXBR uint32 = 0xB341 // FORMAT_RRE LOAD NEGATIVE (extended BFP) 1829 op_LNXR uint32 = 0xB361 // FORMAT_RRE LOAD NEGATIVE (extended HFP) 1830 op_LOC uint32 = 0xEBF2 // FORMAT_RSY2 LOAD ON CONDITION (32) 1831 op_LOCG uint32 = 0xEBE2 // FORMAT_RSY2 LOAD ON CONDITION (64) 1832 op_LOCGR uint32 = 0xB9E2 // FORMAT_RRF3 LOAD ON CONDITION (64) 1833 op_LOCR uint32 = 0xB9F2 // FORMAT_RRF3 LOAD ON CONDITION (32) 1834 op_LPD uint32 = 0xC804 // FORMAT_SSF LOAD PAIR DISJOINT (32) 1835 op_LPDBR uint32 = 0xB310 // FORMAT_RRE LOAD POSITIVE (long BFP) 1836 op_LPDFR uint32 = 0xB370 // FORMAT_RRE LOAD POSITIVE (long) 1837 op_LPDG uint32 = 0xC805 // FORMAT_SSF LOAD PAIR DISJOINT (64) 1838 op_LPDR uint32 = 0x2000 // FORMAT_RR LOAD POSITIVE (long HFP) 1839 op_LPEBR uint32 = 0xB300 // FORMAT_RRE LOAD POSITIVE (short BFP) 1840 op_LPER uint32 = 0x3000 // FORMAT_RR LOAD POSITIVE (short HFP) 1841 op_LPGFR uint32 = 0xB910 // FORMAT_RRE LOAD POSITIVE (64<-32) 1842 op_LPGR uint32 = 0xB900 // FORMAT_RRE LOAD POSITIVE (64) 1843 op_LPQ uint32 = 0xE38F // FORMAT_RXY1 LOAD PAIR FROM QUADWORD 1844 op_LPR uint32 = 0x1000 // FORMAT_RR LOAD POSITIVE (32) 1845 op_LPSW uint32 = 0x8200 // FORMAT_S LOAD PSW 1846 op_LPSWE uint32 = 0xB2B2 // FORMAT_S LOAD PSW EXTENDED 1847 op_LPTEA uint32 = 0xB9AA // FORMAT_RRF2 LOAD PAGE TABLE ENTRY ADDRESS 1848 op_LPXBR uint32 = 0xB340 // FORMAT_RRE LOAD POSITIVE (extended BFP) 1849 op_LPXR uint32 = 0xB360 // FORMAT_RRE LOAD POSITIVE (extended HFP) 1850 op_LR uint32 = 0x1800 // FORMAT_RR LOAD (32) 1851 op_LRA uint32 = 0xB100 // FORMAT_RX1 LOAD REAL ADDRESS (32) 1852 op_LRAG uint32 = 0xE303 // FORMAT_RXY1 LOAD REAL ADDRESS (64) 1853 op_LRAY uint32 = 0xE313 // FORMAT_RXY1 LOAD REAL ADDRESS (32) 1854 op_LRDR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1855 op_LRER uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1856 op_LRL uint32 = 0xC40D // FORMAT_RIL2 LOAD RELATIVE LONG (32) 1857 op_LRV uint32 = 0xE31E // FORMAT_RXY1 LOAD REVERSED (32) 1858 op_LRVG uint32 = 0xE30F // FORMAT_RXY1 LOAD REVERSED (64) 1859 op_LRVGR uint32 = 0xB90F // FORMAT_RRE LOAD REVERSED (64) 1860 op_LRVH uint32 = 0xE31F // FORMAT_RXY1 LOAD REVERSED (16) 1861 op_LRVR uint32 = 0xB91F // FORMAT_RRE LOAD REVERSED (32) 1862 op_LT uint32 = 0xE312 // FORMAT_RXY1 LOAD AND TEST (32) 1863 op_LTDBR uint32 = 0xB312 // FORMAT_RRE LOAD AND TEST (long BFP) 1864 op_LTDR uint32 = 0x2200 // FORMAT_RR LOAD AND TEST (long HFP) 1865 op_LTDTR uint32 = 0xB3D6 // FORMAT_RRE LOAD AND TEST (long DFP) 1866 op_LTEBR uint32 = 0xB302 // FORMAT_RRE LOAD AND TEST (short BFP) 1867 op_LTER uint32 = 0x3200 // FORMAT_RR LOAD AND TEST (short HFP) 1868 op_LTG uint32 = 0xE302 // FORMAT_RXY1 LOAD AND TEST (64) 1869 op_LTGF uint32 = 0xE332 // FORMAT_RXY1 LOAD AND TEST (64<-32) 1870 op_LTGFR uint32 = 0xB912 // FORMAT_RRE LOAD AND TEST (64<-32) 1871 op_LTGR uint32 = 0xB902 // FORMAT_RRE LOAD AND TEST (64) 1872 op_LTR uint32 = 0x1200 // FORMAT_RR LOAD AND TEST (32) 1873 op_LTXBR uint32 = 0xB342 // FORMAT_RRE LOAD AND TEST (extended BFP) 1874 op_LTXR uint32 = 0xB362 // FORMAT_RRE LOAD AND TEST (extended HFP) 1875 op_LTXTR uint32 = 0xB3DE // FORMAT_RRE LOAD AND TEST (extended DFP) 1876 op_LURA uint32 = 0xB24B // FORMAT_RRE LOAD USING REAL ADDRESS (32) 1877 op_LURAG uint32 = 0xB905 // FORMAT_RRE LOAD USING REAL ADDRESS (64) 1878 op_LXD uint32 = 0xED25 // FORMAT_RXE LOAD LENGTHENED (long to extended HFP) 1879 op_LXDB uint32 = 0xED05 // FORMAT_RXE LOAD LENGTHENED (long to extended BFP) 1880 op_LXDBR uint32 = 0xB305 // FORMAT_RRE LOAD LENGTHENED (long to extended BFP) 1881 op_LXDR uint32 = 0xB325 // FORMAT_RRE LOAD LENGTHENED (long to extended HFP) 1882 op_LXDTR uint32 = 0xB3DC // FORMAT_RRF4 LOAD LENGTHENED (long to extended DFP) 1883 op_LXE uint32 = 0xED26 // FORMAT_RXE LOAD LENGTHENED (short to extended HFP) 1884 op_LXEB uint32 = 0xED06 // FORMAT_RXE LOAD LENGTHENED (short to extended BFP) 1885 op_LXEBR uint32 = 0xB306 // FORMAT_RRE LOAD LENGTHENED (short to extended BFP) 1886 op_LXER uint32 = 0xB326 // FORMAT_RRE LOAD LENGTHENED (short to extended HFP) 1887 op_LXR uint32 = 0xB365 // FORMAT_RRE LOAD (extended) 1888 op_LY uint32 = 0xE358 // FORMAT_RXY1 LOAD (32) 1889 op_LZDR uint32 = 0xB375 // FORMAT_RRE LOAD ZERO (long) 1890 op_LZER uint32 = 0xB374 // FORMAT_RRE LOAD ZERO (short) 1891 op_LZXR uint32 = 0xB376 // FORMAT_RRE LOAD ZERO (extended) 1892 op_M uint32 = 0x5C00 // FORMAT_RX1 MULTIPLY (64<-32) 1893 op_MAD uint32 = 0xED3E // FORMAT_RXF MULTIPLY AND ADD (long HFP) 1894 op_MADB uint32 = 0xED1E // FORMAT_RXF MULTIPLY AND ADD (long BFP) 1895 op_MADBR uint32 = 0xB31E // FORMAT_RRD MULTIPLY AND ADD (long BFP) 1896 op_MADR uint32 = 0xB33E // FORMAT_RRD MULTIPLY AND ADD (long HFP) 1897 op_MAE uint32 = 0xED2E // FORMAT_RXF MULTIPLY AND ADD (short HFP) 1898 op_MAEB uint32 = 0xED0E // FORMAT_RXF MULTIPLY AND ADD (short BFP) 1899 op_MAEBR uint32 = 0xB30E // FORMAT_RRD MULTIPLY AND ADD (short BFP) 1900 op_MAER uint32 = 0xB32E // FORMAT_RRD MULTIPLY AND ADD (short HFP) 1901 op_MAY uint32 = 0xED3A // FORMAT_RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1902 op_MAYH uint32 = 0xED3C // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1903 op_MAYHR uint32 = 0xB33C // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1904 op_MAYL uint32 = 0xED38 // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1905 op_MAYLR uint32 = 0xB338 // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1906 op_MAYR uint32 = 0xB33A // FORMAT_RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1907 op_MC uint32 = 0xAF00 // FORMAT_SI MONITOR CALL 1908 op_MD uint32 = 0x6C00 // FORMAT_RX1 MULTIPLY (long HFP) 1909 op_MDB uint32 = 0xED1C // FORMAT_RXE MULTIPLY (long BFP) 1910 op_MDBR uint32 = 0xB31C // FORMAT_RRE MULTIPLY (long BFP) 1911 op_MDE uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1912 op_MDEB uint32 = 0xED0C // FORMAT_RXE MULTIPLY (short to long BFP) 1913 op_MDEBR uint32 = 0xB30C // FORMAT_RRE MULTIPLY (short to long BFP) 1914 op_MDER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1915 op_MDR uint32 = 0x2C00 // FORMAT_RR MULTIPLY (long HFP) 1916 op_MDTR uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1917 op_MDTRA uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1918 op_ME uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1919 op_MEE uint32 = 0xED37 // FORMAT_RXE MULTIPLY (short HFP) 1920 op_MEEB uint32 = 0xED17 // FORMAT_RXE MULTIPLY (short BFP) 1921 op_MEEBR uint32 = 0xB317 // FORMAT_RRE MULTIPLY (short BFP) 1922 op_MEER uint32 = 0xB337 // FORMAT_RRE MULTIPLY (short HFP) 1923 op_MER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1924 op_MFY uint32 = 0xE35C // FORMAT_RXY1 MULTIPLY (64<-32) 1925 op_MGHI uint32 = 0xA70D // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (64) 1926 op_MH uint32 = 0x4C00 // FORMAT_RX1 MULTIPLY HALFWORD (32) 1927 op_MHI uint32 = 0xA70C // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (32) 1928 op_MHY uint32 = 0xE37C // FORMAT_RXY1 MULTIPLY HALFWORD (32) 1929 op_ML uint32 = 0xE396 // FORMAT_RXY1 MULTIPLY LOGICAL (64<-32) 1930 op_MLG uint32 = 0xE386 // FORMAT_RXY1 MULTIPLY LOGICAL (128<-64) 1931 op_MLGR uint32 = 0xB986 // FORMAT_RRE MULTIPLY LOGICAL (128<-64) 1932 op_MLR uint32 = 0xB996 // FORMAT_RRE MULTIPLY LOGICAL (64<-32) 1933 op_MP uint32 = 0xFC00 // FORMAT_SS2 MULTIPLY DECIMAL 1934 op_MR uint32 = 0x1C00 // FORMAT_RR MULTIPLY (64<-32) 1935 op_MS uint32 = 0x7100 // FORMAT_RX1 MULTIPLY SINGLE (32) 1936 op_MSCH uint32 = 0xB232 // FORMAT_S MODIFY SUBCHANNEL 1937 op_MSD uint32 = 0xED3F // FORMAT_RXF MULTIPLY AND SUBTRACT (long HFP) 1938 op_MSDB uint32 = 0xED1F // FORMAT_RXF MULTIPLY AND SUBTRACT (long BFP) 1939 op_MSDBR uint32 = 0xB31F // FORMAT_RRD MULTIPLY AND SUBTRACT (long BFP) 1940 op_MSDR uint32 = 0xB33F // FORMAT_RRD MULTIPLY AND SUBTRACT (long HFP) 1941 op_MSE uint32 = 0xED2F // FORMAT_RXF MULTIPLY AND SUBTRACT (short HFP) 1942 op_MSEB uint32 = 0xED0F // FORMAT_RXF MULTIPLY AND SUBTRACT (short BFP) 1943 op_MSEBR uint32 = 0xB30F // FORMAT_RRD MULTIPLY AND SUBTRACT (short BFP) 1944 op_MSER uint32 = 0xB32F // FORMAT_RRD MULTIPLY AND SUBTRACT (short HFP) 1945 op_MSFI uint32 = 0xC201 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (32) 1946 op_MSG uint32 = 0xE30C // FORMAT_RXY1 MULTIPLY SINGLE (64) 1947 op_MSGF uint32 = 0xE31C // FORMAT_RXY1 MULTIPLY SINGLE (64<-32) 1948 op_MSGFI uint32 = 0xC200 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (64<-32) 1949 op_MSGFR uint32 = 0xB91C // FORMAT_RRE MULTIPLY SINGLE (64<-32) 1950 op_MSGR uint32 = 0xB90C // FORMAT_RRE MULTIPLY SINGLE (64) 1951 op_MSR uint32 = 0xB252 // FORMAT_RRE MULTIPLY SINGLE (32) 1952 op_MSTA uint32 = 0xB247 // FORMAT_RRE MODIFY STACKED STATE 1953 op_MSY uint32 = 0xE351 // FORMAT_RXY1 MULTIPLY SINGLE (32) 1954 op_MVC uint32 = 0xD200 // FORMAT_SS1 MOVE (character) 1955 op_MVCDK uint32 = 0xE50F // FORMAT_SSE MOVE WITH DESTINATION KEY 1956 op_MVCIN uint32 = 0xE800 // FORMAT_SS1 MOVE INVERSE 1957 op_MVCK uint32 = 0xD900 // FORMAT_SS4 MOVE WITH KEY 1958 op_MVCL uint32 = 0x0E00 // FORMAT_RR MOVE LONG 1959 op_MVCLE uint32 = 0xA800 // FORMAT_RS1 MOVE LONG EXTENDED 1960 op_MVCLU uint32 = 0xEB8E // FORMAT_RSY1 MOVE LONG UNICODE 1961 op_MVCOS uint32 = 0xC800 // FORMAT_SSF MOVE WITH OPTIONAL SPECIFICATIONS 1962 op_MVCP uint32 = 0xDA00 // FORMAT_SS4 MOVE TO PRIMARY 1963 op_MVCS uint32 = 0xDB00 // FORMAT_SS4 MOVE TO SECONDARY 1964 op_MVCSK uint32 = 0xE50E // FORMAT_SSE MOVE WITH SOURCE KEY 1965 op_MVGHI uint32 = 0xE548 // FORMAT_SIL MOVE (64<-16) 1966 op_MVHHI uint32 = 0xE544 // FORMAT_SIL MOVE (16<-16) 1967 op_MVHI uint32 = 0xE54C // FORMAT_SIL MOVE (32<-16) 1968 op_MVI uint32 = 0x9200 // FORMAT_SI MOVE (immediate) 1969 op_MVIY uint32 = 0xEB52 // FORMAT_SIY MOVE (immediate) 1970 op_MVN uint32 = 0xD100 // FORMAT_SS1 MOVE NUMERICS 1971 op_MVO uint32 = 0xF100 // FORMAT_SS2 MOVE WITH OFFSET 1972 op_MVPG uint32 = 0xB254 // FORMAT_RRE MOVE PAGE 1973 op_MVST uint32 = 0xB255 // FORMAT_RRE MOVE STRING 1974 op_MVZ uint32 = 0xD300 // FORMAT_SS1 MOVE ZONES 1975 op_MXBR uint32 = 0xB34C // FORMAT_RRE MULTIPLY (extended BFP) 1976 op_MXD uint32 = 0x6700 // FORMAT_RX1 MULTIPLY (long to extended HFP) 1977 op_MXDB uint32 = 0xED07 // FORMAT_RXE MULTIPLY (long to extended BFP) 1978 op_MXDBR uint32 = 0xB307 // FORMAT_RRE MULTIPLY (long to extended BFP) 1979 op_MXDR uint32 = 0x2700 // FORMAT_RR MULTIPLY (long to extended HFP) 1980 op_MXR uint32 = 0x2600 // FORMAT_RR MULTIPLY (extended HFP) 1981 op_MXTR uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 1982 op_MXTRA uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 1983 op_MY uint32 = 0xED3B // FORMAT_RXF MULTIPLY UNNORMALIZED (long to ext. HFP) 1984 op_MYH uint32 = 0xED3D // FORMAT_RXF MULTIPLY UNNORM. (long to ext. high HFP) 1985 op_MYHR uint32 = 0xB33D // FORMAT_RRD MULTIPLY UNNORM. (long to ext. high HFP) 1986 op_MYL uint32 = 0xED39 // FORMAT_RXF MULTIPLY UNNORM. (long to ext. low HFP) 1987 op_MYLR uint32 = 0xB339 // FORMAT_RRD MULTIPLY UNNORM. (long to ext. low HFP) 1988 op_MYR uint32 = 0xB33B // FORMAT_RRD MULTIPLY UNNORMALIZED (long to ext. HFP) 1989 op_N uint32 = 0x5400 // FORMAT_RX1 AND (32) 1990 op_NC uint32 = 0xD400 // FORMAT_SS1 AND (character) 1991 op_NG uint32 = 0xE380 // FORMAT_RXY1 AND (64) 1992 op_NGR uint32 = 0xB980 // FORMAT_RRE AND (64) 1993 op_NGRK uint32 = 0xB9E4 // FORMAT_RRF1 AND (64) 1994 op_NI uint32 = 0x9400 // FORMAT_SI AND (immediate) 1995 op_NIAI uint32 = 0xB2FA // FORMAT_IE NEXT INSTRUCTION ACCESS INTENT 1996 op_NIHF uint32 = 0xC00A // FORMAT_RIL1 AND IMMEDIATE (high) 1997 op_NIHH uint32 = 0xA504 // FORMAT_RI1 AND IMMEDIATE (high high) 1998 op_NIHL uint32 = 0xA505 // FORMAT_RI1 AND IMMEDIATE (high low) 1999 op_NILF uint32 = 0xC00B // FORMAT_RIL1 AND IMMEDIATE (low) 2000 op_NILH uint32 = 0xA506 // FORMAT_RI1 AND IMMEDIATE (low high) 2001 op_NILL uint32 = 0xA507 // FORMAT_RI1 AND IMMEDIATE (low low) 2002 op_NIY uint32 = 0xEB54 // FORMAT_SIY AND (immediate) 2003 op_NR uint32 = 0x1400 // FORMAT_RR AND (32) 2004 op_NRK uint32 = 0xB9F4 // FORMAT_RRF1 AND (32) 2005 op_NTSTG uint32 = 0xE325 // FORMAT_RXY1 NONTRANSACTIONAL STORE 2006 op_NY uint32 = 0xE354 // FORMAT_RXY1 AND (32) 2007 op_O uint32 = 0x5600 // FORMAT_RX1 OR (32) 2008 op_OC uint32 = 0xD600 // FORMAT_SS1 OR (character) 2009 op_OG uint32 = 0xE381 // FORMAT_RXY1 OR (64) 2010 op_OGR uint32 = 0xB981 // FORMAT_RRE OR (64) 2011 op_OGRK uint32 = 0xB9E6 // FORMAT_RRF1 OR (64) 2012 op_OI uint32 = 0x9600 // FORMAT_SI OR (immediate) 2013 op_OIHF uint32 = 0xC00C // FORMAT_RIL1 OR IMMEDIATE (high) 2014 op_OIHH uint32 = 0xA508 // FORMAT_RI1 OR IMMEDIATE (high high) 2015 op_OIHL uint32 = 0xA509 // FORMAT_RI1 OR IMMEDIATE (high low) 2016 op_OILF uint32 = 0xC00D // FORMAT_RIL1 OR IMMEDIATE (low) 2017 op_OILH uint32 = 0xA50A // FORMAT_RI1 OR IMMEDIATE (low high) 2018 op_OILL uint32 = 0xA50B // FORMAT_RI1 OR IMMEDIATE (low low) 2019 op_OIY uint32 = 0xEB56 // FORMAT_SIY OR (immediate) 2020 op_OR uint32 = 0x1600 // FORMAT_RR OR (32) 2021 op_ORK uint32 = 0xB9F6 // FORMAT_RRF1 OR (32) 2022 op_OY uint32 = 0xE356 // FORMAT_RXY1 OR (32) 2023 op_PACK uint32 = 0xF200 // FORMAT_SS2 PACK 2024 op_PALB uint32 = 0xB248 // FORMAT_RRE PURGE ALB 2025 op_PC uint32 = 0xB218 // FORMAT_S PROGRAM CALL 2026 op_PCC uint32 = 0xB92C // FORMAT_RRE PERFORM CRYPTOGRAPHIC COMPUTATION 2027 op_PCKMO uint32 = 0xB928 // FORMAT_RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS 2028 op_PFD uint32 = 0xE336 // FORMAT_RXY2 PREFETCH DATA 2029 op_PFDRL uint32 = 0xC602 // FORMAT_RIL3 PREFETCH DATA RELATIVE LONG 2030 op_PFMF uint32 = 0xB9AF // FORMAT_RRE PERFORM FRAME MANAGEMENT FUNCTION 2031 op_PFPO uint32 = 0x010A // FORMAT_E PERFORM FLOATING-POINT OPERATION 2032 op_PGIN uint32 = 0xB22E // FORMAT_RRE PAGE IN 2033 op_PGOUT uint32 = 0xB22F // FORMAT_RRE PAGE OUT 2034 op_PKA uint32 = 0xE900 // FORMAT_SS6 PACK ASCII 2035 op_PKU uint32 = 0xE100 // FORMAT_SS6 PACK UNICODE 2036 op_PLO uint32 = 0xEE00 // FORMAT_SS5 PERFORM LOCKED OPERATION 2037 op_POPCNT uint32 = 0xB9E1 // FORMAT_RRE POPULATION COUNT 2038 op_PPA uint32 = 0xB2E8 // FORMAT_RRF3 PERFORM PROCESSOR ASSIST 2039 op_PR uint32 = 0x0101 // FORMAT_E PROGRAM RETURN 2040 op_PT uint32 = 0xB228 // FORMAT_RRE PROGRAM TRANSFER 2041 op_PTF uint32 = 0xB9A2 // FORMAT_RRE PERFORM TOPOLOGY FUNCTION 2042 op_PTFF uint32 = 0x0104 // FORMAT_E PERFORM TIMING FACILITY FUNCTION 2043 op_PTI uint32 = 0xB99E // FORMAT_RRE PROGRAM TRANSFER WITH INSTANCE 2044 op_PTLB uint32 = 0xB20D // FORMAT_S PURGE TLB 2045 op_QADTR uint32 = 0xB3F5 // FORMAT_RRF2 QUANTIZE (long DFP) 2046 op_QAXTR uint32 = 0xB3FD // FORMAT_RRF2 QUANTIZE (extended DFP) 2047 op_RCHP uint32 = 0xB23B // FORMAT_S RESET CHANNEL PATH 2048 op_RISBG uint32 = 0xEC55 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2049 op_RISBGN uint32 = 0xEC59 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2050 op_RISBHG uint32 = 0xEC5D // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS HIGH 2051 op_RISBLG uint32 = 0xEC51 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS LOW 2052 op_RLL uint32 = 0xEB1D // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (32) 2053 op_RLLG uint32 = 0xEB1C // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (64) 2054 op_RNSBG uint32 = 0xEC54 // FORMAT_RIE6 ROTATE THEN AND SELECTED BITS 2055 op_ROSBG uint32 = 0xEC56 // FORMAT_RIE6 ROTATE THEN OR SELECTED BITS 2056 op_RP uint32 = 0xB277 // FORMAT_S RESUME PROGRAM 2057 op_RRBE uint32 = 0xB22A // FORMAT_RRE RESET REFERENCE BIT EXTENDED 2058 op_RRBM uint32 = 0xB9AE // FORMAT_RRE RESET REFERENCE BITS MULTIPLE 2059 op_RRDTR uint32 = 0xB3F7 // FORMAT_RRF2 REROUND (long DFP) 2060 op_RRXTR uint32 = 0xB3FF // FORMAT_RRF2 REROUND (extended DFP) 2061 op_RSCH uint32 = 0xB238 // FORMAT_S RESUME SUBCHANNEL 2062 op_RXSBG uint32 = 0xEC57 // FORMAT_RIE6 ROTATE THEN EXCLUSIVE OR SELECTED BITS 2063 op_S uint32 = 0x5B00 // FORMAT_RX1 SUBTRACT (32) 2064 op_SAC uint32 = 0xB219 // FORMAT_S SET ADDRESS SPACE CONTROL 2065 op_SACF uint32 = 0xB279 // FORMAT_S SET ADDRESS SPACE CONTROL FAST 2066 op_SAL uint32 = 0xB237 // FORMAT_S SET ADDRESS LIMIT 2067 op_SAM24 uint32 = 0x010C // FORMAT_E SET ADDRESSING MODE (24) 2068 op_SAM31 uint32 = 0x010D // FORMAT_E SET ADDRESSING MODE (31) 2069 op_SAM64 uint32 = 0x010E // FORMAT_E SET ADDRESSING MODE (64) 2070 op_SAR uint32 = 0xB24E // FORMAT_RRE SET ACCESS 2071 op_SCHM uint32 = 0xB23C // FORMAT_S SET CHANNEL MONITOR 2072 op_SCK uint32 = 0xB204 // FORMAT_S SET CLOCK 2073 op_SCKC uint32 = 0xB206 // FORMAT_S SET CLOCK COMPARATOR 2074 op_SCKPF uint32 = 0x0107 // FORMAT_E SET CLOCK PROGRAMMABLE FIELD 2075 op_SD uint32 = 0x6B00 // FORMAT_RX1 SUBTRACT NORMALIZED (long HFP) 2076 op_SDB uint32 = 0xED1B // FORMAT_RXE SUBTRACT (long BFP) 2077 op_SDBR uint32 = 0xB31B // FORMAT_RRE SUBTRACT (long BFP) 2078 op_SDR uint32 = 0x2B00 // FORMAT_RR SUBTRACT NORMALIZED (long HFP) 2079 op_SDTR uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2080 op_SDTRA uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2081 op_SE uint32 = 0x7B00 // FORMAT_RX1 SUBTRACT NORMALIZED (short HFP) 2082 op_SEB uint32 = 0xED0B // FORMAT_RXE SUBTRACT (short BFP) 2083 op_SEBR uint32 = 0xB30B // FORMAT_RRE SUBTRACT (short BFP) 2084 op_SER uint32 = 0x3B00 // FORMAT_RR SUBTRACT NORMALIZED (short HFP) 2085 op_SFASR uint32 = 0xB385 // FORMAT_RRE SET FPC AND SIGNAL 2086 op_SFPC uint32 = 0xB384 // FORMAT_RRE SET FPC 2087 op_SG uint32 = 0xE309 // FORMAT_RXY1 SUBTRACT (64) 2088 op_SGF uint32 = 0xE319 // FORMAT_RXY1 SUBTRACT (64<-32) 2089 op_SGFR uint32 = 0xB919 // FORMAT_RRE SUBTRACT (64<-32) 2090 op_SGR uint32 = 0xB909 // FORMAT_RRE SUBTRACT (64) 2091 op_SGRK uint32 = 0xB9E9 // FORMAT_RRF1 SUBTRACT (64) 2092 op_SH uint32 = 0x4B00 // FORMAT_RX1 SUBTRACT HALFWORD 2093 op_SHHHR uint32 = 0xB9C9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2094 op_SHHLR uint32 = 0xB9D9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2095 op_SHY uint32 = 0xE37B // FORMAT_RXY1 SUBTRACT HALFWORD 2096 op_SIGP uint32 = 0xAE00 // FORMAT_RS1 SIGNAL PROCESSOR 2097 op_SL uint32 = 0x5F00 // FORMAT_RX1 SUBTRACT LOGICAL (32) 2098 op_SLA uint32 = 0x8B00 // FORMAT_RS1 SHIFT LEFT SINGLE (32) 2099 op_SLAG uint32 = 0xEB0B // FORMAT_RSY1 SHIFT LEFT SINGLE (64) 2100 op_SLAK uint32 = 0xEBDD // FORMAT_RSY1 SHIFT LEFT SINGLE (32) 2101 op_SLB uint32 = 0xE399 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (32) 2102 op_SLBG uint32 = 0xE389 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (64) 2103 op_SLBGR uint32 = 0xB989 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (64) 2104 op_SLBR uint32 = 0xB999 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (32) 2105 op_SLDA uint32 = 0x8F00 // FORMAT_RS1 SHIFT LEFT DOUBLE 2106 op_SLDL uint32 = 0x8D00 // FORMAT_RS1 SHIFT LEFT DOUBLE LOGICAL 2107 op_SLDT uint32 = 0xED40 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (long DFP) 2108 op_SLFI uint32 = 0xC205 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (32) 2109 op_SLG uint32 = 0xE30B // FORMAT_RXY1 SUBTRACT LOGICAL (64) 2110 op_SLGF uint32 = 0xE31B // FORMAT_RXY1 SUBTRACT LOGICAL (64<-32) 2111 op_SLGFI uint32 = 0xC204 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (64<-32) 2112 op_SLGFR uint32 = 0xB91B // FORMAT_RRE SUBTRACT LOGICAL (64<-32) 2113 op_SLGR uint32 = 0xB90B // FORMAT_RRE SUBTRACT LOGICAL (64) 2114 op_SLGRK uint32 = 0xB9EB // FORMAT_RRF1 SUBTRACT LOGICAL (64) 2115 op_SLHHHR uint32 = 0xB9CB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2116 op_SLHHLR uint32 = 0xB9DB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2117 op_SLL uint32 = 0x8900 // FORMAT_RS1 SHIFT LEFT SINGLE LOGICAL (32) 2118 op_SLLG uint32 = 0xEB0D // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (64) 2119 op_SLLK uint32 = 0xEBDF // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (32) 2120 op_SLR uint32 = 0x1F00 // FORMAT_RR SUBTRACT LOGICAL (32) 2121 op_SLRK uint32 = 0xB9FB // FORMAT_RRF1 SUBTRACT LOGICAL (32) 2122 op_SLXT uint32 = 0xED48 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (extended DFP) 2123 op_SLY uint32 = 0xE35F // FORMAT_RXY1 SUBTRACT LOGICAL (32) 2124 op_SP uint32 = 0xFB00 // FORMAT_SS2 SUBTRACT DECIMAL 2125 op_SPKA uint32 = 0xB20A // FORMAT_S SET PSW KEY FROM ADDRESS 2126 op_SPM uint32 = 0x0400 // FORMAT_RR SET PROGRAM MASK 2127 op_SPT uint32 = 0xB208 // FORMAT_S SET CPU TIMER 2128 op_SPX uint32 = 0xB210 // FORMAT_S SET PREFIX 2129 op_SQD uint32 = 0xED35 // FORMAT_RXE SQUARE ROOT (long HFP) 2130 op_SQDB uint32 = 0xED15 // FORMAT_RXE SQUARE ROOT (long BFP) 2131 op_SQDBR uint32 = 0xB315 // FORMAT_RRE SQUARE ROOT (long BFP) 2132 op_SQDR uint32 = 0xB244 // FORMAT_RRE SQUARE ROOT (long HFP) 2133 op_SQE uint32 = 0xED34 // FORMAT_RXE SQUARE ROOT (short HFP) 2134 op_SQEB uint32 = 0xED14 // FORMAT_RXE SQUARE ROOT (short BFP) 2135 op_SQEBR uint32 = 0xB314 // FORMAT_RRE SQUARE ROOT (short BFP) 2136 op_SQER uint32 = 0xB245 // FORMAT_RRE SQUARE ROOT (short HFP) 2137 op_SQXBR uint32 = 0xB316 // FORMAT_RRE SQUARE ROOT (extended BFP) 2138 op_SQXR uint32 = 0xB336 // FORMAT_RRE SQUARE ROOT (extended HFP) 2139 op_SR uint32 = 0x1B00 // FORMAT_RR SUBTRACT (32) 2140 op_SRA uint32 = 0x8A00 // FORMAT_RS1 SHIFT RIGHT SINGLE (32) 2141 op_SRAG uint32 = 0xEB0A // FORMAT_RSY1 SHIFT RIGHT SINGLE (64) 2142 op_SRAK uint32 = 0xEBDC // FORMAT_RSY1 SHIFT RIGHT SINGLE (32) 2143 op_SRDA uint32 = 0x8E00 // FORMAT_RS1 SHIFT RIGHT DOUBLE 2144 op_SRDL uint32 = 0x8C00 // FORMAT_RS1 SHIFT RIGHT DOUBLE LOGICAL 2145 op_SRDT uint32 = 0xED41 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (long DFP) 2146 op_SRK uint32 = 0xB9F9 // FORMAT_RRF1 SUBTRACT (32) 2147 op_SRL uint32 = 0x8800 // FORMAT_RS1 SHIFT RIGHT SINGLE LOGICAL (32) 2148 op_SRLG uint32 = 0xEB0C // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (64) 2149 op_SRLK uint32 = 0xEBDE // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (32) 2150 op_SRNM uint32 = 0xB299 // FORMAT_S SET BFP ROUNDING MODE (2 bit) 2151 op_SRNMB uint32 = 0xB2B8 // FORMAT_S SET BFP ROUNDING MODE (3 bit) 2152 op_SRNMT uint32 = 0xB2B9 // FORMAT_S SET DFP ROUNDING MODE 2153 op_SRP uint32 = 0xF000 // FORMAT_SS3 SHIFT AND ROUND DECIMAL 2154 op_SRST uint32 = 0xB25E // FORMAT_RRE SEARCH STRING 2155 op_SRSTU uint32 = 0xB9BE // FORMAT_RRE SEARCH STRING UNICODE 2156 op_SRXT uint32 = 0xED49 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (extended DFP) 2157 op_SSAIR uint32 = 0xB99F // FORMAT_RRE SET SECONDARY ASN WITH INSTANCE 2158 op_SSAR uint32 = 0xB225 // FORMAT_RRE SET SECONDARY ASN 2159 op_SSCH uint32 = 0xB233 // FORMAT_S START SUBCHANNEL 2160 op_SSKE uint32 = 0xB22B // FORMAT_RRF3 SET STORAGE KEY EXTENDED 2161 op_SSM uint32 = 0x8000 // FORMAT_S SET SYSTEM MASK 2162 op_ST uint32 = 0x5000 // FORMAT_RX1 STORE (32) 2163 op_STAM uint32 = 0x9B00 // FORMAT_RS1 STORE ACCESS MULTIPLE 2164 op_STAMY uint32 = 0xEB9B // FORMAT_RSY1 STORE ACCESS MULTIPLE 2165 op_STAP uint32 = 0xB212 // FORMAT_S STORE CPU ADDRESS 2166 op_STC uint32 = 0x4200 // FORMAT_RX1 STORE CHARACTER 2167 op_STCH uint32 = 0xE3C3 // FORMAT_RXY1 STORE CHARACTER HIGH (8) 2168 op_STCK uint32 = 0xB205 // FORMAT_S STORE CLOCK 2169 op_STCKC uint32 = 0xB207 // FORMAT_S STORE CLOCK COMPARATOR 2170 op_STCKE uint32 = 0xB278 // FORMAT_S STORE CLOCK EXTENDED 2171 op_STCKF uint32 = 0xB27C // FORMAT_S STORE CLOCK FAST 2172 op_STCM uint32 = 0xBE00 // FORMAT_RS2 STORE CHARACTERS UNDER MASK (low) 2173 op_STCMH uint32 = 0xEB2C // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (high) 2174 op_STCMY uint32 = 0xEB2D // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (low) 2175 op_STCPS uint32 = 0xB23A // FORMAT_S STORE CHANNEL PATH STATUS 2176 op_STCRW uint32 = 0xB239 // FORMAT_S STORE CHANNEL REPORT WORD 2177 op_STCTG uint32 = 0xEB25 // FORMAT_RSY1 STORE CONTROL (64) 2178 op_STCTL uint32 = 0xB600 // FORMAT_RS1 STORE CONTROL (32) 2179 op_STCY uint32 = 0xE372 // FORMAT_RXY1 STORE CHARACTER 2180 op_STD uint32 = 0x6000 // FORMAT_RX1 STORE (long) 2181 op_STDY uint32 = 0xED67 // FORMAT_RXY1 STORE (long) 2182 op_STE uint32 = 0x7000 // FORMAT_RX1 STORE (short) 2183 op_STEY uint32 = 0xED66 // FORMAT_RXY1 STORE (short) 2184 op_STFH uint32 = 0xE3CB // FORMAT_RXY1 STORE HIGH (32) 2185 op_STFL uint32 = 0xB2B1 // FORMAT_S STORE FACILITY LIST 2186 op_STFLE uint32 = 0xB2B0 // FORMAT_S STORE FACILITY LIST EXTENDED 2187 op_STFPC uint32 = 0xB29C // FORMAT_S STORE FPC 2188 op_STG uint32 = 0xE324 // FORMAT_RXY1 STORE (64) 2189 op_STGRL uint32 = 0xC40B // FORMAT_RIL2 STORE RELATIVE LONG (64) 2190 op_STH uint32 = 0x4000 // FORMAT_RX1 STORE HALFWORD 2191 op_STHH uint32 = 0xE3C7 // FORMAT_RXY1 STORE HALFWORD HIGH (16) 2192 op_STHRL uint32 = 0xC407 // FORMAT_RIL2 STORE HALFWORD RELATIVE LONG 2193 op_STHY uint32 = 0xE370 // FORMAT_RXY1 STORE HALFWORD 2194 op_STIDP uint32 = 0xB202 // FORMAT_S STORE CPU ID 2195 op_STM uint32 = 0x9000 // FORMAT_RS1 STORE MULTIPLE (32) 2196 op_STMG uint32 = 0xEB24 // FORMAT_RSY1 STORE MULTIPLE (64) 2197 op_STMH uint32 = 0xEB26 // FORMAT_RSY1 STORE MULTIPLE HIGH 2198 op_STMY uint32 = 0xEB90 // FORMAT_RSY1 STORE MULTIPLE (32) 2199 op_STNSM uint32 = 0xAC00 // FORMAT_SI STORE THEN AND SYSTEM MASK 2200 op_STOC uint32 = 0xEBF3 // FORMAT_RSY2 STORE ON CONDITION (32) 2201 op_STOCG uint32 = 0xEBE3 // FORMAT_RSY2 STORE ON CONDITION (64) 2202 op_STOSM uint32 = 0xAD00 // FORMAT_SI STORE THEN OR SYSTEM MASK 2203 op_STPQ uint32 = 0xE38E // FORMAT_RXY1 STORE PAIR TO QUADWORD 2204 op_STPT uint32 = 0xB209 // FORMAT_S STORE CPU TIMER 2205 op_STPX uint32 = 0xB211 // FORMAT_S STORE PREFIX 2206 op_STRAG uint32 = 0xE502 // FORMAT_SSE STORE REAL ADDRESS 2207 op_STRL uint32 = 0xC40F // FORMAT_RIL2 STORE RELATIVE LONG (32) 2208 op_STRV uint32 = 0xE33E // FORMAT_RXY1 STORE REVERSED (32) 2209 op_STRVG uint32 = 0xE32F // FORMAT_RXY1 STORE REVERSED (64) 2210 op_STRVH uint32 = 0xE33F // FORMAT_RXY1 STORE REVERSED (16) 2211 op_STSCH uint32 = 0xB234 // FORMAT_S STORE SUBCHANNEL 2212 op_STSI uint32 = 0xB27D // FORMAT_S STORE SYSTEM INFORMATION 2213 op_STURA uint32 = 0xB246 // FORMAT_RRE STORE USING REAL ADDRESS (32) 2214 op_STURG uint32 = 0xB925 // FORMAT_RRE STORE USING REAL ADDRESS (64) 2215 op_STY uint32 = 0xE350 // FORMAT_RXY1 STORE (32) 2216 op_SU uint32 = 0x7F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (short HFP) 2217 op_SUR uint32 = 0x3F00 // FORMAT_RR SUBTRACT UNNORMALIZED (short HFP) 2218 op_SVC uint32 = 0x0A00 // FORMAT_I SUPERVISOR CALL 2219 op_SW uint32 = 0x6F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (long HFP) 2220 op_SWR uint32 = 0x2F00 // FORMAT_RR SUBTRACT UNNORMALIZED (long HFP) 2221 op_SXBR uint32 = 0xB34B // FORMAT_RRE SUBTRACT (extended BFP) 2222 op_SXR uint32 = 0x3700 // FORMAT_RR SUBTRACT NORMALIZED (extended HFP) 2223 op_SXTR uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2224 op_SXTRA uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2225 op_SY uint32 = 0xE35B // FORMAT_RXY1 SUBTRACT (32) 2226 op_TABORT uint32 = 0xB2FC // FORMAT_S TRANSACTION ABORT 2227 op_TAM uint32 = 0x010B // FORMAT_E TEST ADDRESSING MODE 2228 op_TAR uint32 = 0xB24C // FORMAT_RRE TEST ACCESS 2229 op_TB uint32 = 0xB22C // FORMAT_RRE TEST BLOCK 2230 op_TBDR uint32 = 0xB351 // FORMAT_RRF5 CONVERT HFP TO BFP (long) 2231 op_TBEDR uint32 = 0xB350 // FORMAT_RRF5 CONVERT HFP TO BFP (long to short) 2232 op_TBEGIN uint32 = 0xE560 // FORMAT_SIL TRANSACTION BEGIN 2233 op_TBEGINC uint32 = 0xE561 // FORMAT_SIL TRANSACTION BEGIN 2234 op_TCDB uint32 = 0xED11 // FORMAT_RXE TEST DATA CLASS (long BFP) 2235 op_TCEB uint32 = 0xED10 // FORMAT_RXE TEST DATA CLASS (short BFP) 2236 op_TCXB uint32 = 0xED12 // FORMAT_RXE TEST DATA CLASS (extended BFP) 2237 op_TDCDT uint32 = 0xED54 // FORMAT_RXE TEST DATA CLASS (long DFP) 2238 op_TDCET uint32 = 0xED50 // FORMAT_RXE TEST DATA CLASS (short DFP) 2239 op_TDCXT uint32 = 0xED58 // FORMAT_RXE TEST DATA CLASS (extended DFP) 2240 op_TDGDT uint32 = 0xED55 // FORMAT_RXE TEST DATA GROUP (long DFP) 2241 op_TDGET uint32 = 0xED51 // FORMAT_RXE TEST DATA GROUP (short DFP) 2242 op_TDGXT uint32 = 0xED59 // FORMAT_RXE TEST DATA GROUP (extended DFP) 2243 op_TEND uint32 = 0xB2F8 // FORMAT_S TRANSACTION END 2244 op_THDER uint32 = 0xB358 // FORMAT_RRE CONVERT BFP TO HFP (short to long) 2245 op_THDR uint32 = 0xB359 // FORMAT_RRE CONVERT BFP TO HFP (long) 2246 op_TM uint32 = 0x9100 // FORMAT_SI TEST UNDER MASK 2247 op_TMH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK HIGH 2248 op_TMHH uint32 = 0xA702 // FORMAT_RI1 TEST UNDER MASK (high high) 2249 op_TMHL uint32 = 0xA703 // FORMAT_RI1 TEST UNDER MASK (high low) 2250 op_TML uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK LOW 2251 op_TMLH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK (low high) 2252 op_TMLL uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK (low low) 2253 op_TMY uint32 = 0xEB51 // FORMAT_SIY TEST UNDER MASK 2254 op_TP uint32 = 0xEBC0 // FORMAT_RSL TEST DECIMAL 2255 op_TPI uint32 = 0xB236 // FORMAT_S TEST PENDING INTERRUPTION 2256 op_TPROT uint32 = 0xE501 // FORMAT_SSE TEST PROTECTION 2257 op_TR uint32 = 0xDC00 // FORMAT_SS1 TRANSLATE 2258 op_TRACE uint32 = 0x9900 // FORMAT_RS1 TRACE (32) 2259 op_TRACG uint32 = 0xEB0F // FORMAT_RSY1 TRACE (64) 2260 op_TRAP2 uint32 = 0x01FF // FORMAT_E TRAP 2261 op_TRAP4 uint32 = 0xB2FF // FORMAT_S TRAP 2262 op_TRE uint32 = 0xB2A5 // FORMAT_RRE TRANSLATE EXTENDED 2263 op_TROO uint32 = 0xB993 // FORMAT_RRF3 TRANSLATE ONE TO ONE 2264 op_TROT uint32 = 0xB992 // FORMAT_RRF3 TRANSLATE ONE TO TWO 2265 op_TRT uint32 = 0xDD00 // FORMAT_SS1 TRANSLATE AND TEST 2266 op_TRTE uint32 = 0xB9BF // FORMAT_RRF3 TRANSLATE AND TEST EXTENDED 2267 op_TRTO uint32 = 0xB991 // FORMAT_RRF3 TRANSLATE TWO TO ONE 2268 op_TRTR uint32 = 0xD000 // FORMAT_SS1 TRANSLATE AND TEST REVERSE 2269 op_TRTRE uint32 = 0xB9BD // FORMAT_RRF3 TRANSLATE AND TEST REVERSE EXTENDED 2270 op_TRTT uint32 = 0xB990 // FORMAT_RRF3 TRANSLATE TWO TO TWO 2271 op_TS uint32 = 0x9300 // FORMAT_S TEST AND SET 2272 op_TSCH uint32 = 0xB235 // FORMAT_S TEST SUBCHANNEL 2273 op_UNPK uint32 = 0xF300 // FORMAT_SS2 UNPACK 2274 op_UNPKA uint32 = 0xEA00 // FORMAT_SS1 UNPACK ASCII 2275 op_UNPKU uint32 = 0xE200 // FORMAT_SS1 UNPACK UNICODE 2276 op_UPT uint32 = 0x0102 // FORMAT_E UPDATE TREE 2277 op_X uint32 = 0x5700 // FORMAT_RX1 EXCLUSIVE OR (32) 2278 op_XC uint32 = 0xD700 // FORMAT_SS1 EXCLUSIVE OR (character) 2279 op_XG uint32 = 0xE382 // FORMAT_RXY1 EXCLUSIVE OR (64) 2280 op_XGR uint32 = 0xB982 // FORMAT_RRE EXCLUSIVE OR (64) 2281 op_XGRK uint32 = 0xB9E7 // FORMAT_RRF1 EXCLUSIVE OR (64) 2282 op_XI uint32 = 0x9700 // FORMAT_SI EXCLUSIVE OR (immediate) 2283 op_XIHF uint32 = 0xC006 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (high) 2284 op_XILF uint32 = 0xC007 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (low) 2285 op_XIY uint32 = 0xEB57 // FORMAT_SIY EXCLUSIVE OR (immediate) 2286 op_XR uint32 = 0x1700 // FORMAT_RR EXCLUSIVE OR (32) 2287 op_XRK uint32 = 0xB9F7 // FORMAT_RRF1 EXCLUSIVE OR (32) 2288 op_XSCH uint32 = 0xB276 // FORMAT_S CANCEL SUBCHANNEL 2289 op_XY uint32 = 0xE357 // FORMAT_RXY1 EXCLUSIVE OR (32) 2290 op_ZAP uint32 = 0xF800 // FORMAT_SS2 ZERO AND ADD 2291 2292 // added in z13 2293 op_CXPT uint32 = 0xEDAF // RSL-b CONVERT FROM PACKED (to extended DFP) 2294 op_CDPT uint32 = 0xEDAE // RSL-b CONVERT FROM PACKED (to long DFP) 2295 op_CPXT uint32 = 0xEDAD // RSL-b CONVERT TO PACKED (from extended DFP) 2296 op_CPDT uint32 = 0xEDAC // RSL-b CONVERT TO PACKED (from long DFP) 2297 op_LZRF uint32 = 0xE33B // RXY-a LOAD AND ZERO RIGHTMOST BYTE (32) 2298 op_LZRG uint32 = 0xE32A // RXY-a LOAD AND ZERO RIGHTMOST BYTE (64) 2299 op_LCCB uint32 = 0xE727 // RXE LOAD COUNT TO BLOCK BOUNDARY 2300 op_LOCHHI uint32 = 0xEC4E // RIE-g LOAD HALFWORD HIGH IMMEDIATE ON CONDITION (32←16) 2301 op_LOCHI uint32 = 0xEC42 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (32←16) 2302 op_LOCGHI uint32 = 0xEC46 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (64←16) 2303 op_LOCFH uint32 = 0xEBE0 // RSY-b LOAD HIGH ON CONDITION (32) 2304 op_LOCFHR uint32 = 0xB9E0 // RRF-c LOAD HIGH ON CONDITION (32) 2305 op_LLZRGF uint32 = 0xE33A // RXY-a LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64←32) 2306 op_STOCFH uint32 = 0xEBE1 // RSY-b STORE HIGH ON CONDITION 2307 op_VA uint32 = 0xE7F3 // VRR-c VECTOR ADD 2308 op_VACC uint32 = 0xE7F1 // VRR-c VECTOR ADD COMPUTE CARRY 2309 op_VAC uint32 = 0xE7BB // VRR-d VECTOR ADD WITH CARRY 2310 op_VACCC uint32 = 0xE7B9 // VRR-d VECTOR ADD WITH CARRY COMPUTE CARRY 2311 op_VN uint32 = 0xE768 // VRR-c VECTOR AND 2312 op_VNC uint32 = 0xE769 // VRR-c VECTOR AND WITH COMPLEMENT 2313 op_VAVG uint32 = 0xE7F2 // VRR-c VECTOR AVERAGE 2314 op_VAVGL uint32 = 0xE7F0 // VRR-c VECTOR AVERAGE LOGICAL 2315 op_VCKSM uint32 = 0xE766 // VRR-c VECTOR CHECKSUM 2316 op_VCEQ uint32 = 0xE7F8 // VRR-b VECTOR COMPARE EQUAL 2317 op_VCH uint32 = 0xE7FB // VRR-b VECTOR COMPARE HIGH 2318 op_VCHL uint32 = 0xE7F9 // VRR-b VECTOR COMPARE HIGH LOGICAL 2319 op_VCLZ uint32 = 0xE753 // VRR-a VECTOR COUNT LEADING ZEROS 2320 op_VCTZ uint32 = 0xE752 // VRR-a VECTOR COUNT TRAILING ZEROS 2321 op_VEC uint32 = 0xE7DB // VRR-a VECTOR ELEMENT COMPARE 2322 op_VECL uint32 = 0xE7D9 // VRR-a VECTOR ELEMENT COMPARE LOGICAL 2323 op_VERIM uint32 = 0xE772 // VRI-d VECTOR ELEMENT ROTATE AND INSERT UNDER MASK 2324 op_VERLL uint32 = 0xE733 // VRS-a VECTOR ELEMENT ROTATE LEFT LOGICAL 2325 op_VERLLV uint32 = 0xE773 // VRR-c VECTOR ELEMENT ROTATE LEFT LOGICAL 2326 op_VESLV uint32 = 0xE770 // VRR-c VECTOR ELEMENT SHIFT LEFT 2327 op_VESL uint32 = 0xE730 // VRS-a VECTOR ELEMENT SHIFT LEFT 2328 op_VESRA uint32 = 0xE73A // VRS-a VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2329 op_VESRAV uint32 = 0xE77A // VRR-c VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2330 op_VESRL uint32 = 0xE738 // VRS-a VECTOR ELEMENT SHIFT RIGHT LOGICAL 2331 op_VESRLV uint32 = 0xE778 // VRR-c VECTOR ELEMENT SHIFT RIGHT LOGICAL 2332 op_VX uint32 = 0xE76D // VRR-c VECTOR EXCLUSIVE OR 2333 op_VFAE uint32 = 0xE782 // VRR-b VECTOR FIND ANY ELEMENT EQUAL 2334 op_VFEE uint32 = 0xE780 // VRR-b VECTOR FIND ELEMENT EQUAL 2335 op_VFENE uint32 = 0xE781 // VRR-b VECTOR FIND ELEMENT NOT EQUAL 2336 op_VFA uint32 = 0xE7E3 // VRR-c VECTOR FP ADD 2337 op_WFK uint32 = 0xE7CA // VRR-a VECTOR FP COMPARE AND SIGNAL SCALAR 2338 op_VFCE uint32 = 0xE7E8 // VRR-c VECTOR FP COMPARE EQUAL 2339 op_VFCH uint32 = 0xE7EB // VRR-c VECTOR FP COMPARE HIGH 2340 op_VFCHE uint32 = 0xE7EA // VRR-c VECTOR FP COMPARE HIGH OR EQUAL 2341 op_WFC uint32 = 0xE7CB // VRR-a VECTOR FP COMPARE SCALAR 2342 op_VCDG uint32 = 0xE7C3 // VRR-a VECTOR FP CONVERT FROM FIXED 64-BIT 2343 op_VCDLG uint32 = 0xE7C1 // VRR-a VECTOR FP CONVERT FROM LOGICAL 64-BIT 2344 op_VCGD uint32 = 0xE7C2 // VRR-a VECTOR FP CONVERT TO FIXED 64-BIT 2345 op_VCLGD uint32 = 0xE7C0 // VRR-a VECTOR FP CONVERT TO LOGICAL 64-BIT 2346 op_VFD uint32 = 0xE7E5 // VRR-c VECTOR FP DIVIDE 2347 op_VLDE uint32 = 0xE7C4 // VRR-a VECTOR FP LOAD LENGTHENED 2348 op_VLED uint32 = 0xE7C5 // VRR-a VECTOR FP LOAD ROUNDED 2349 op_VFM uint32 = 0xE7E7 // VRR-c VECTOR FP MULTIPLY 2350 op_VFMA uint32 = 0xE78F // VRR-e VECTOR FP MULTIPLY AND ADD 2351 op_VFMS uint32 = 0xE78E // VRR-e VECTOR FP MULTIPLY AND SUBTRACT 2352 op_VFPSO uint32 = 0xE7CC // VRR-a VECTOR FP PERFORM SIGN OPERATION 2353 op_VFSQ uint32 = 0xE7CE // VRR-a VECTOR FP SQUARE ROOT 2354 op_VFS uint32 = 0xE7E2 // VRR-c VECTOR FP SUBTRACT 2355 op_VFTCI uint32 = 0xE74A // VRI-e VECTOR FP TEST DATA CLASS IMMEDIATE 2356 op_VGFM uint32 = 0xE7B4 // VRR-c VECTOR GALOIS FIELD MULTIPLY SUM 2357 op_VGFMA uint32 = 0xE7BC // VRR-d VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE 2358 op_VGEF uint32 = 0xE713 // VRV VECTOR GATHER ELEMENT (32) 2359 op_VGEG uint32 = 0xE712 // VRV VECTOR GATHER ELEMENT (64) 2360 op_VGBM uint32 = 0xE744 // VRI-a VECTOR GENERATE BYTE MASK 2361 op_VGM uint32 = 0xE746 // VRI-b VECTOR GENERATE MASK 2362 op_VISTR uint32 = 0xE75C // VRR-a VECTOR ISOLATE STRING 2363 op_VL uint32 = 0xE706 // VRX VECTOR LOAD 2364 op_VLR uint32 = 0xE756 // VRR-a VECTOR LOAD 2365 op_VLREP uint32 = 0xE705 // VRX VECTOR LOAD AND REPLICATE 2366 op_VLC uint32 = 0xE7DE // VRR-a VECTOR LOAD COMPLEMENT 2367 op_VLEH uint32 = 0xE701 // VRX VECTOR LOAD ELEMENT (16) 2368 op_VLEF uint32 = 0xE703 // VRX VECTOR LOAD ELEMENT (32) 2369 op_VLEG uint32 = 0xE702 // VRX VECTOR LOAD ELEMENT (64) 2370 op_VLEB uint32 = 0xE700 // VRX VECTOR LOAD ELEMENT (8) 2371 op_VLEIH uint32 = 0xE741 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (16) 2372 op_VLEIF uint32 = 0xE743 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (32) 2373 op_VLEIG uint32 = 0xE742 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (64) 2374 op_VLEIB uint32 = 0xE740 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (8) 2375 op_VFI uint32 = 0xE7C7 // VRR-a VECTOR LOAD FP INTEGER 2376 op_VLGV uint32 = 0xE721 // VRS-c VECTOR LOAD GR FROM VR ELEMENT 2377 op_VLLEZ uint32 = 0xE704 // VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO 2378 op_VLM uint32 = 0xE736 // VRS-a VECTOR LOAD MULTIPLE 2379 op_VLP uint32 = 0xE7DF // VRR-a VECTOR LOAD POSITIVE 2380 op_VLBB uint32 = 0xE707 // VRX VECTOR LOAD TO BLOCK BOUNDARY 2381 op_VLVG uint32 = 0xE722 // VRS-b VECTOR LOAD VR ELEMENT FROM GR 2382 op_VLVGP uint32 = 0xE762 // VRR-f VECTOR LOAD VR FROM GRS DISJOINT 2383 op_VLL uint32 = 0xE737 // VRS-b VECTOR LOAD WITH LENGTH 2384 op_VMX uint32 = 0xE7FF // VRR-c VECTOR MAXIMUM 2385 op_VMXL uint32 = 0xE7FD // VRR-c VECTOR MAXIMUM LOGICAL 2386 op_VMRH uint32 = 0xE761 // VRR-c VECTOR MERGE HIGH 2387 op_VMRL uint32 = 0xE760 // VRR-c VECTOR MERGE LOW 2388 op_VMN uint32 = 0xE7FE // VRR-c VECTOR MINIMUM 2389 op_VMNL uint32 = 0xE7FC // VRR-c VECTOR MINIMUM LOGICAL 2390 op_VMAE uint32 = 0xE7AE // VRR-d VECTOR MULTIPLY AND ADD EVEN 2391 op_VMAH uint32 = 0xE7AB // VRR-d VECTOR MULTIPLY AND ADD HIGH 2392 op_VMALE uint32 = 0xE7AC // VRR-d VECTOR MULTIPLY AND ADD LOGICAL EVEN 2393 op_VMALH uint32 = 0xE7A9 // VRR-d VECTOR MULTIPLY AND ADD LOGICAL HIGH 2394 op_VMALO uint32 = 0xE7AD // VRR-d VECTOR MULTIPLY AND ADD LOGICAL ODD 2395 op_VMAL uint32 = 0xE7AA // VRR-d VECTOR MULTIPLY AND ADD LOW 2396 op_VMAO uint32 = 0xE7AF // VRR-d VECTOR MULTIPLY AND ADD ODD 2397 op_VME uint32 = 0xE7A6 // VRR-c VECTOR MULTIPLY EVEN 2398 op_VMH uint32 = 0xE7A3 // VRR-c VECTOR MULTIPLY HIGH 2399 op_VMLE uint32 = 0xE7A4 // VRR-c VECTOR MULTIPLY EVEN LOGICAL 2400 op_VMLH uint32 = 0xE7A1 // VRR-c VECTOR MULTIPLY HIGH LOGICAL 2401 op_VMLO uint32 = 0xE7A5 // VRR-c VECTOR MULTIPLY ODD LOGICAL 2402 op_VML uint32 = 0xE7A2 // VRR-c VECTOR MULTIPLY LOW 2403 op_VMO uint32 = 0xE7A7 // VRR-c VECTOR MULTIPLY ODD 2404 op_VNO uint32 = 0xE76B // VRR-c VECTOR NOR 2405 op_VO uint32 = 0xE76A // VRR-c VECTOR OR 2406 op_VPK uint32 = 0xE794 // VRR-c VECTOR PACK 2407 op_VPKLS uint32 = 0xE795 // VRR-b VECTOR PACK LOGICAL SATURATE 2408 op_VPKS uint32 = 0xE797 // VRR-b VECTOR PACK SATURATE 2409 op_VPERM uint32 = 0xE78C // VRR-e VECTOR PERMUTE 2410 op_VPDI uint32 = 0xE784 // VRR-c VECTOR PERMUTE DOUBLEWORD IMMEDIATE 2411 op_VPOPCT uint32 = 0xE750 // VRR-a VECTOR POPULATION COUNT 2412 op_VREP uint32 = 0xE74D // VRI-c VECTOR REPLICATE 2413 op_VREPI uint32 = 0xE745 // VRI-a VECTOR REPLICATE IMMEDIATE 2414 op_VSCEF uint32 = 0xE71B // VRV VECTOR SCATTER ELEMENT (32) 2415 op_VSCEG uint32 = 0xE71A // VRV VECTOR SCATTER ELEMENT (64) 2416 op_VSEL uint32 = 0xE78D // VRR-e VECTOR SELECT 2417 op_VSL uint32 = 0xE774 // VRR-c VECTOR SHIFT LEFT 2418 op_VSLB uint32 = 0xE775 // VRR-c VECTOR SHIFT LEFT BY BYTE 2419 op_VSLDB uint32 = 0xE777 // VRI-d VECTOR SHIFT LEFT DOUBLE BY BYTE 2420 op_VSRA uint32 = 0xE77E // VRR-c VECTOR SHIFT RIGHT ARITHMETIC 2421 op_VSRAB uint32 = 0xE77F // VRR-c VECTOR SHIFT RIGHT ARITHMETIC BY BYTE 2422 op_VSRL uint32 = 0xE77C // VRR-c VECTOR SHIFT RIGHT LOGICAL 2423 op_VSRLB uint32 = 0xE77D // VRR-c VECTOR SHIFT RIGHT LOGICAL BY BYTE 2424 op_VSEG uint32 = 0xE75F // VRR-a VECTOR SIGN EXTEND TO DOUBLEWORD 2425 op_VST uint32 = 0xE70E // VRX VECTOR STORE 2426 op_VSTEH uint32 = 0xE709 // VRX VECTOR STORE ELEMENT (16) 2427 op_VSTEF uint32 = 0xE70B // VRX VECTOR STORE ELEMENT (32) 2428 op_VSTEG uint32 = 0xE70A // VRX VECTOR STORE ELEMENT (64) 2429 op_VSTEB uint32 = 0xE708 // VRX VECTOR STORE ELEMENT (8) 2430 op_VSTM uint32 = 0xE73E // VRS-a VECTOR STORE MULTIPLE 2431 op_VSTL uint32 = 0xE73F // VRS-b VECTOR STORE WITH LENGTH 2432 op_VSTRC uint32 = 0xE78A // VRR-d VECTOR STRING RANGE COMPARE 2433 op_VS uint32 = 0xE7F7 // VRR-c VECTOR SUBTRACT 2434 op_VSCBI uint32 = 0xE7F5 // VRR-c VECTOR SUBTRACT COMPUTE BORROW INDICATION 2435 op_VSBCBI uint32 = 0xE7BD // VRR-d VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION 2436 op_VSBI uint32 = 0xE7BF // VRR-d VECTOR SUBTRACT WITH BORROW INDICATION 2437 op_VSUMG uint32 = 0xE765 // VRR-c VECTOR SUM ACROSS DOUBLEWORD 2438 op_VSUMQ uint32 = 0xE767 // VRR-c VECTOR SUM ACROSS QUADWORD 2439 op_VSUM uint32 = 0xE764 // VRR-c VECTOR SUM ACROSS WORD 2440 op_VTM uint32 = 0xE7D8 // VRR-a VECTOR TEST UNDER MASK 2441 op_VUPH uint32 = 0xE7D7 // VRR-a VECTOR UNPACK HIGH 2442 op_VUPLH uint32 = 0xE7D5 // VRR-a VECTOR UNPACK LOGICAL HIGH 2443 op_VUPLL uint32 = 0xE7D4 // VRR-a VECTOR UNPACK LOGICAL LOW 2444 op_VUPL uint32 = 0xE7D6 // VRR-a VECTOR UNPACK LOW 2445 ) 2446 2447 func oclass(a *obj.Addr) int { 2448 return int(a.Class) - 1 2449 } 2450 2451 // Add a relocation for the immediate in a RIL style instruction. 2452 // The addend will be adjusted as required. 2453 func addrilreloc(ctxt *obj.Link, sym *obj.LSym, add int64) *obj.Reloc { 2454 if sym == nil { 2455 ctxt.Diag("require symbol to apply relocation") 2456 } 2457 offset := int64(2) // relocation offset from start of instruction 2458 rel := obj.Addrel(ctxt.Cursym) 2459 rel.Off = int32(ctxt.Pc + offset) 2460 rel.Siz = 4 2461 rel.Sym = sym 2462 rel.Add = add + offset + int64(rel.Siz) 2463 rel.Type = obj.R_PCRELDBL 2464 return rel 2465 } 2466 2467 func addrilrelocoffset(ctxt *obj.Link, sym *obj.LSym, add, offset int64) *obj.Reloc { 2468 if sym == nil { 2469 ctxt.Diag("require symbol to apply relocation") 2470 } 2471 offset += int64(2) // relocation offset from start of instruction 2472 rel := obj.Addrel(ctxt.Cursym) 2473 rel.Off = int32(ctxt.Pc + offset) 2474 rel.Siz = 4 2475 rel.Sym = sym 2476 rel.Add = add + offset + int64(rel.Siz) 2477 rel.Type = obj.R_PCRELDBL 2478 return rel 2479 } 2480 2481 // Add a CALL relocation for the immediate in a RIL style instruction. 2482 // The addend will be adjusted as required. 2483 func addcallreloc(ctxt *obj.Link, sym *obj.LSym, add int64) *obj.Reloc { 2484 if sym == nil { 2485 ctxt.Diag("require symbol to apply relocation") 2486 } 2487 offset := int64(2) // relocation offset from start of instruction 2488 rel := obj.Addrel(ctxt.Cursym) 2489 rel.Off = int32(ctxt.Pc + offset) 2490 rel.Siz = 4 2491 rel.Sym = sym 2492 rel.Add = add + offset + int64(rel.Siz) 2493 rel.Type = obj.R_CALL 2494 return rel 2495 } 2496 2497 func branchMask(ctxt *obj.Link, p *obj.Prog) uint32 { 2498 switch p.As { 2499 case ABEQ, ACMPBEQ, ACMPUBEQ: 2500 return 0x8 2501 case ABGE, ACMPBGE, ACMPUBGE: 2502 return 0xA 2503 case ABGT, ACMPBGT, ACMPUBGT: 2504 return 0x2 2505 case ABLE, ACMPBLE, ACMPUBLE: 2506 return 0xC 2507 case ABLT, ACMPBLT, ACMPUBLT: 2508 return 0x4 2509 case ABNE, ACMPBNE, ACMPUBNE: 2510 return 0x7 2511 case ABVC: 2512 return 0x0 //needs extra instruction 2513 case ABVS: 2514 return 0x1 2515 } 2516 ctxt.Diag("unknown conditional branch %v", p.As) 2517 return 0xF 2518 } 2519 2520 func asmout(ctxt *obj.Link, asm *[]byte) { 2521 p := ctxt.Curp 2522 o := oplook(ctxt, p) 2523 ctxt.Printp = p 2524 2525 switch o.type_ { 2526 default: 2527 ctxt.Diag("unknown type %d", o.type_) 2528 2529 case 0: // PSEUDO OPS 2530 break 2531 2532 case 1: // mov reg reg 2533 switch p.As { 2534 default: 2535 ctxt.Diag("unhandled operation: %v", p.As) 2536 case AMOVD: 2537 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2538 // sign extend 2539 case AMOVW: 2540 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2541 case AMOVH: 2542 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2543 case AMOVB: 2544 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2545 // zero extend 2546 case AMOVWZ: 2547 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2548 case AMOVHZ: 2549 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2550 case AMOVBZ: 2551 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2552 // reverse bytes 2553 case AMOVDBR: 2554 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2555 case AMOVWBR: 2556 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2557 // floating point 2558 case AFMOVD, AFMOVS: 2559 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2560 } 2561 2562 case 2: // arithmetic op reg [reg] reg 2563 r := int(p.Reg) 2564 if r == 0 { 2565 r = int(p.To.Reg) 2566 } 2567 2568 var opcode uint32 2569 2570 switch p.As { 2571 default: 2572 ctxt.Diag("invalid opcode") 2573 case AADD: 2574 opcode = op_AGRK 2575 case AADDC: 2576 opcode = op_ALGRK 2577 case AADDE: 2578 opcode = op_ALCGR 2579 case AMULLW: 2580 opcode = op_MSGFR 2581 case AMULLD: 2582 opcode = op_MSGR 2583 case AMULHDU: 2584 opcode = op_MLGR 2585 case ADIVW: 2586 opcode = op_DSGFR 2587 case ADIVWU: 2588 opcode = op_DLR 2589 case ADIVD: 2590 opcode = op_DSGR 2591 case ADIVDU: 2592 opcode = op_DLGR 2593 case AFADD: 2594 opcode = op_ADBR 2595 case AFADDS: 2596 opcode = op_AEBR 2597 case AFSUB: 2598 opcode = op_SDBR 2599 case AFSUBS: 2600 opcode = op_SEBR 2601 case AFDIV: 2602 opcode = op_DDBR 2603 case AFDIVS: 2604 opcode = op_DEBR 2605 } 2606 2607 switch p.As { 2608 default: 2609 2610 case AADD, AADDC: 2611 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2612 2613 case AADDE, AMULLW, AMULLD: 2614 if r == int(p.To.Reg) { 2615 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2616 } else if p.From.Reg == p.To.Reg { 2617 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2618 } else { 2619 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2620 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2621 } 2622 2623 case ADIVW, ADIVWU, ADIVD, ADIVDU: 2624 if p.As == ADIVWU || p.As == ADIVDU { 2625 zRRE(op_LGR, REGTMP, REGZERO, asm) 2626 } 2627 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2628 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2629 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm) 2630 2631 case AMULHDU: 2632 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2633 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2634 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2635 2636 case AFADD, AFADDS: 2637 if r == int(p.To.Reg) { 2638 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2639 } else if p.From.Reg == p.To.Reg { 2640 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2641 } else { 2642 zRR(op_LDR, uint32(p.To.Reg), uint32(r), asm) 2643 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2644 } 2645 2646 case AFSUB, AFSUBS, AFDIV, AFDIVS: 2647 if r == int(p.To.Reg) { 2648 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2649 } else if p.From.Reg == p.To.Reg { 2650 zRRE(op_LGDR, REGTMP, uint32(r), asm) 2651 zRRE(opcode, uint32(r), uint32(p.From.Reg), asm) 2652 zRR(op_LDR, uint32(p.To.Reg), uint32(r), asm) 2653 zRRE(op_LDGR, uint32(r), REGTMP, asm) 2654 } else { 2655 zRR(op_LDR, uint32(p.To.Reg), uint32(r), asm) 2656 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2657 } 2658 2659 } 2660 2661 case 3: // mov $constant reg 2662 v := vregoff(ctxt, &p.From) 2663 switch p.As { 2664 case AMOVBZ: 2665 v = int64(uint8(v)) 2666 case AMOVHZ: 2667 v = int64(uint16(v)) 2668 case AMOVWZ: 2669 v = int64(uint32(v)) 2670 case AMOVB: 2671 v = int64(int8(v)) 2672 case AMOVH: 2673 v = int64(int16(v)) 2674 case AMOVW: 2675 v = int64(int32(v)) 2676 } 2677 if v&0xffff == v { 2678 zRI(op_LLILL, uint32(p.To.Reg), uint32(v), asm) 2679 } else if v&0xffff0000 == v { 2680 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm) 2681 } else if v&0xffff00000000 == v { 2682 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm) 2683 } else if uint64(v)&0xffff000000000000 == uint64(v) { 2684 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm) 2685 } else if int64(int16(v)) == v { 2686 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm) 2687 } else if int64(int32(v)) == v { 2688 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm) 2689 } else if int64(uint32(v)) == v { 2690 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2691 } else if uint64(v)&0xffffffff00000000 == uint64(v) { 2692 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2693 } else { 2694 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2695 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2696 } 2697 2698 case 5: // syscall 2699 zI(op_SVC, 0, asm) 2700 2701 case 6: // logical op reg [reg] reg 2702 if p.To.Reg == 0 { 2703 ctxt.Diag("literal operation on R0\n%v", p) 2704 } 2705 2706 switch p.As { 2707 case AAND, AOR, AXOR: 2708 var opcode1, opcode2 uint32 2709 switch p.As { 2710 default: 2711 case AAND: 2712 opcode1 = op_NGR 2713 opcode2 = op_NGRK 2714 case AOR: 2715 opcode1 = op_OGR 2716 opcode2 = op_OGRK 2717 case AXOR: 2718 opcode1 = op_XGR 2719 opcode2 = op_XGRK 2720 } 2721 2722 r := int(p.Reg) 2723 if r == 0 { 2724 zRRE(opcode1, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2725 } else { 2726 zRRF(opcode2, uint32(r), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2727 } 2728 2729 case AANDN, AORN: 2730 var opcode1, opcode2 uint32 2731 switch p.As { 2732 default: 2733 case AANDN: 2734 opcode1 = op_NGR 2735 opcode2 = op_NGRK 2736 case AORN: 2737 opcode1 = op_OGR 2738 opcode2 = op_OGRK 2739 } 2740 2741 r := int(p.Reg) 2742 if r == 0 { 2743 zRRE(op_LCGR, uint32(p.To.Reg), uint32(p.To.Reg), asm) 2744 zRRE(opcode1, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2745 } else { 2746 zRRE(op_LCGR, REGTMP, uint32(r), asm) 2747 zRRF(opcode2, REGTMP, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2748 } 2749 2750 case ANAND, ANOR: 2751 var opcode1, opcode2 uint32 2752 switch p.As { 2753 default: 2754 case ANAND: 2755 opcode1 = op_NGR 2756 opcode2 = op_NGRK 2757 case ANOR: 2758 opcode1 = op_OGR 2759 opcode2 = op_OGRK 2760 } 2761 2762 r := int(p.Reg) 2763 if r == 0 { 2764 zRRE(opcode1, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2765 } else { 2766 zRRF(opcode2, uint32(r), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2767 } 2768 2769 zRRE(op_LCGR, uint32(p.To.Reg), uint32(p.To.Reg), asm) 2770 } 2771 2772 case 7: // shift/rotate reg [reg] reg 2773 d2 := vregoff(ctxt, &p.From) 2774 b2 := p.From.Reg 2775 r3 := p.Reg 2776 if r3 == 0 { 2777 r3 = p.To.Reg 2778 } 2779 r1 := p.To.Reg 2780 var opcode uint32 2781 switch p.As { 2782 default: 2783 case ASLD: 2784 opcode = op_SLLG 2785 case ASRD: 2786 opcode = op_SRLG 2787 case ASLW: 2788 opcode = op_SLLK 2789 case ASRW: 2790 opcode = op_SRLK 2791 case ARLL: 2792 opcode = op_RLL 2793 case ARLLG: 2794 opcode = op_RLLG 2795 case ASRAW: 2796 opcode = op_SRAK 2797 case ASRAD: 2798 opcode = op_SRAG 2799 } 2800 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm) 2801 2802 case 10: // subtract reg [reg] reg 2803 r := int(p.Reg) 2804 2805 switch p.As { 2806 default: 2807 case ASUB: 2808 if r == 0 { 2809 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2810 } else { 2811 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2812 } 2813 case ASUBC: 2814 if r == 0 { 2815 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2816 } else { 2817 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2818 } 2819 2820 case ASUBE: 2821 if r == 0 { 2822 r = int(p.To.Reg) 2823 } 2824 if r == int(p.To.Reg) { 2825 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2826 } else if p.From.Reg == p.To.Reg { 2827 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 2828 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2829 zRRE(op_SLBGR, uint32(p.To.Reg), REGTMP, asm) 2830 } else { 2831 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2832 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2833 } 2834 } 2835 2836 case 11: // br/bl 2837 v := int32(0) 2838 2839 if p.Pcond != nil { 2840 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2841 } 2842 2843 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v { 2844 zRI(op_BRC, 0xF, uint32(v), asm) 2845 } else { 2846 if p.As == ABL { 2847 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm) 2848 } else { 2849 zRIL(_c, op_BRCL, 0xF, uint32(v), asm) 2850 } 2851 if p.To.Sym != nil { 2852 addcallreloc(ctxt, p.To.Sym, p.To.Offset) 2853 } 2854 } 2855 2856 case 15: // br/bl (reg) 2857 r := p.To.Reg 2858 if p.As == ABCL || p.As == ABL { 2859 zRR(op_BASR, uint32(REG_LR), uint32(r), asm) 2860 } else { 2861 zRR(op_BCR, 0xF, uint32(r), asm) 2862 } 2863 2864 case 16: // conditional branch 2865 v := int32(0) 2866 if p.Pcond != nil { 2867 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2868 } 2869 mask := branchMask(ctxt, p) 2870 if p.To.Sym == nil && int32(int16(v)) == v { 2871 zRI(op_BRC, mask, uint32(v), asm) 2872 } else { 2873 zRIL(_c, op_BRCL, mask, uint32(v), asm) 2874 } 2875 if p.To.Sym != nil { 2876 addrilreloc(ctxt, p.To.Sym, p.To.Offset) 2877 } 2878 2879 case 18: // br/bl reg 2880 if p.As == ABL { 2881 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm) 2882 } else { 2883 zRR(op_BCR, 0xF, uint32(p.To.Reg), asm) 2884 } 2885 2886 case 19: // mov $sym+n(SB) reg 2887 d := vregoff(ctxt, &p.From) 2888 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm) 2889 if d&1 != 0 { 2890 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm) 2891 d -= 1 2892 } 2893 addrilreloc(ctxt, p.From.Sym, d) 2894 2895 case 22: // arithmetic op $constant [reg] reg 2896 if p.From.Sym != nil { 2897 ctxt.Diag("%v is not supported", p) 2898 } 2899 v := vregoff(ctxt, &p.From) 2900 r := p.Reg 2901 if r == 0 { 2902 r = p.To.Reg 2903 } 2904 switch p.As { 2905 default: 2906 case AADD: 2907 if r == p.To.Reg { 2908 zRIL(_a, op_AGFI, uint32(p.To.Reg), uint32(v), asm) 2909 } else if int64(int16(v)) == v { 2910 zRIE(_d, op_AGHIK, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm) 2911 } else { 2912 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2913 zRIL(_a, op_AGFI, uint32(p.To.Reg), uint32(v), asm) 2914 } 2915 case AADDC: 2916 if r != p.To.Reg { 2917 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2918 } 2919 zRIL(_a, op_ALGFI, uint32(p.To.Reg), uint32(v), asm) 2920 case AMULLW: 2921 if r != p.To.Reg { 2922 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2923 } 2924 zRIL(_a, op_MSGFI, uint32(p.To.Reg), uint32(v), asm) 2925 } 2926 2927 case 23: // logical op $constant [reg] reg 2928 v := vregoff(ctxt, &p.From) 2929 var opcode uint32 2930 r := p.Reg 2931 if r == 0 { 2932 r = p.To.Reg 2933 } 2934 if r == p.To.Reg { 2935 switch p.As { 2936 default: 2937 ctxt.Diag("%v is not supported", p) 2938 case AAND: 2939 if v >= 0 { // needs zero extend 2940 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 2941 zRRE(op_NGR, uint32(p.To.Reg), REGTMP, asm) 2942 } else if int64(int16(v)) == v { 2943 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 2944 } else { // r.To.Reg & 0xffffffff00000000 & uint32(v) 2945 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 2946 } 2947 case AOR: 2948 if int64(uint32(v)) != v { // needs sign extend 2949 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 2950 zRRE(op_OGR, uint32(p.To.Reg), REGTMP, asm) 2951 } else if int64(uint16(v)) == v { 2952 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 2953 } else { 2954 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 2955 } 2956 case AXOR: 2957 if int64(uint32(v)) != v { // needs sign extend 2958 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 2959 zRRE(op_XGR, uint32(p.To.Reg), REGTMP, asm) 2960 } else { 2961 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 2962 } 2963 } 2964 } else { 2965 switch p.As { 2966 default: 2967 ctxt.Diag("%v is not supported", p) 2968 case AAND: 2969 opcode = op_NGRK 2970 case AOR: 2971 opcode = op_OGRK 2972 case AXOR: 2973 opcode = op_XGRK 2974 } 2975 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 2976 zRRF(opcode, uint32(r), 0, uint32(p.To.Reg), REGTMP, asm) 2977 } 2978 2979 case 26: // mov $addr/sym reg 2980 v := regoff(ctxt, &p.From) 2981 r := p.From.Reg 2982 if r == 0 { 2983 r = o.param 2984 } 2985 if v >= 0 && v < DISP12 { 2986 zRX(op_LA, uint32(p.To.Reg), uint32(r), 0, uint32(v), asm) 2987 } else if v >= -DISP20/2 && v < DISP20/2 { 2988 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), 0, uint32(v), asm) 2989 } else { 2990 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 2991 zRX(op_LA, uint32(p.To.Reg), uint32(r), REGTMP, 0, asm) 2992 } 2993 2994 case 31: // dword 2995 wd := uint64(vregoff(ctxt, &p.From)) 2996 *asm = append(*asm, 2997 uint8(wd>>56), 2998 uint8(wd>>48), 2999 uint8(wd>>40), 3000 uint8(wd>>32), 3001 uint8(wd>>24), 3002 uint8(wd>>16), 3003 uint8(wd>>8), 3004 uint8(wd)) 3005 3006 case 32: // fmul freg [freg] freg 3007 r := int(p.Reg) 3008 if r == 0 { 3009 r = int(p.To.Reg) 3010 } 3011 3012 var opcode uint32 3013 3014 switch p.As { 3015 default: 3016 ctxt.Diag("invalid opcode") 3017 case AFMUL: 3018 opcode = op_MDBR 3019 case AFMULS: 3020 opcode = op_MEEBR 3021 } 3022 3023 if r == int(p.To.Reg) { 3024 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3025 } else if p.From.Reg == p.To.Reg { 3026 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3027 } else { 3028 zRR(op_LDR, uint32(p.To.Reg), uint32(r), asm) 3029 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3030 } 3031 3032 case 33: // float op [freg] freg 3033 r := p.From.Reg 3034 if oclass(&p.From) == C_NONE { 3035 r = p.To.Reg 3036 } 3037 var opcode uint32 3038 switch p.As { 3039 default: 3040 case AFABS: 3041 opcode = op_LPDBR 3042 case AFNABS: 3043 opcode = op_LNDBR 3044 case AFNEG: 3045 opcode = op_LCDFR 3046 case ALEDBR: 3047 opcode = op_LEDBR 3048 case ALDEBR: 3049 opcode = op_LDEBR 3050 case AFSQRT: 3051 opcode = op_SQDBR 3052 case AFSQRTS: 3053 opcode = op_SQEBR 3054 } 3055 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3056 3057 case 34: // float multiply-add freg freg freg freg 3058 var opcode uint32 3059 3060 switch p.As { 3061 default: 3062 ctxt.Diag("invalid opcode") 3063 case AFMADD: 3064 opcode = op_MADBR 3065 case AFMADDS: 3066 opcode = op_MAEBR 3067 case AFMSUB: 3068 opcode = op_MSDBR 3069 case AFMSUBS: 3070 opcode = op_MSEBR 3071 case AFNMADD: 3072 opcode = op_MADBR 3073 case AFNMADDS: 3074 opcode = op_MAEBR 3075 case AFNMSUB: 3076 opcode = op_MSDBR 3077 case AFNMSUBS: 3078 opcode = op_MSEBR 3079 } 3080 3081 zRR(op_LDR, uint32(p.To.Reg), uint32(p.Reg), asm) 3082 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From3.Reg), asm) 3083 3084 if p.As == AFNMADD || p.As == AFNMADDS || p.As == AFNMSUB || p.As == AFNMSUBS { 3085 zRRE(op_LCDFR, uint32(p.To.Reg), uint32(p.To.Reg), asm) 3086 } 3087 3088 case 35: // mov reg mem (no relocation) 3089 d2 := regoff(ctxt, &p.To) 3090 b2 := p.To.Reg 3091 if b2 == 0 { 3092 b2 = o.param 3093 } 3094 x2 := p.To.Index 3095 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3096 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3097 if x2 != 0 { 3098 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3099 } 3100 x2 = REGTMP 3101 d2 = 0 3102 } 3103 zRXY(zopstore(ctxt, p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3104 3105 case 36: // mov mem reg (no relocation) 3106 d2 := regoff(ctxt, &p.From) 3107 b2 := p.From.Reg 3108 if b2 == 0 { 3109 b2 = o.param 3110 } 3111 x2 := p.From.Index 3112 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3113 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3114 if x2 != 0 { 3115 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3116 } 3117 x2 = REGTMP 3118 d2 = 0 3119 } 3120 zRXY(zopload(ctxt, p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3121 3122 case 40: // word/byte 3123 wd := uint32(regoff(ctxt, &p.From)) 3124 if p.As == AWORD { //WORD 3125 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd)) 3126 } else { //BYTE 3127 *asm = append(*asm, uint8(wd)) 3128 } 3129 3130 case 47: // arithmetic op (carry) reg [reg] reg 3131 switch p.As { 3132 default: 3133 3134 case AADDME: 3135 r := int(p.From.Reg) 3136 if p.To.Reg == p.From.Reg { 3137 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 3138 r = REGTMP 3139 } 3140 zRIL(_a, op_LGFI, uint32(p.To.Reg), 0xffffffff, asm) // p.To.Reg <- -1 3141 zRRE(op_ALCGR, uint32(p.To.Reg), uint32(r), asm) 3142 3143 case AADDZE: 3144 r := int(p.From.Reg) 3145 if p.To.Reg == p.From.Reg { 3146 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 3147 r = REGTMP 3148 } 3149 zRRE(op_LGR, uint32(p.To.Reg), REGZERO, asm) // p.To.Reg <- 0 3150 zRRE(op_ALCGR, uint32(p.To.Reg), uint32(r), asm) 3151 3152 case ASUBME: 3153 r := int(p.From.Reg) 3154 if p.To.Reg == p.From.Reg { 3155 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 3156 r = REGTMP 3157 } 3158 zRIL(_a, op_LGFI, uint32(p.To.Reg), 0xffffffff, asm) // p.To.Reg <- -1 3159 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(r), asm) 3160 3161 case ASUBZE: 3162 r := int(p.From.Reg) 3163 if p.To.Reg == p.From.Reg { 3164 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 3165 r = REGTMP 3166 } 3167 zRRE(op_LGR, uint32(p.To.Reg), REGZERO, asm) // p.To.Reg <- 0 3168 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(r), asm) 3169 3170 case ANEG: 3171 r := int(p.From.Reg) 3172 if r == 0 { 3173 r = int(p.To.Reg) 3174 } 3175 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm) 3176 } 3177 3178 case 67: // fmov $0 freg 3179 var opcode uint32 3180 switch p.As { 3181 case AFMOVS: 3182 opcode = op_LZER 3183 case AFMOVD: 3184 opcode = op_LZDR 3185 } 3186 zRRE(opcode, uint32(p.To.Reg), 0, asm) 3187 3188 case 68: // movw areg reg 3189 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm) 3190 3191 case 69: // movw reg areg 3192 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm) 3193 3194 case 70: // cmp reg reg 3195 if p.As == ACMPW || p.As == ACMPWU { 3196 zRR(zoprr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3197 } else { 3198 zRRE(zoprre(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3199 } 3200 3201 case 71: // cmp reg $constant 3202 v := vregoff(ctxt, &p.To) 3203 switch p.As { 3204 case ACMP, ACMPW: 3205 if int64(int32(v)) != v { 3206 ctxt.Diag("%v overflows an int32", v) 3207 } 3208 case ACMPU, ACMPWU: 3209 if int64(uint32(v)) != v { 3210 ctxt.Diag("%v overflows a uint32", v) 3211 } 3212 } 3213 zRIL(_a, zopril(ctxt, p.As), uint32(p.From.Reg), uint32(regoff(ctxt, &p.To)), asm) 3214 3215 case 72: // mov $constant/$addr mem 3216 v := regoff(ctxt, &p.From) 3217 d := regoff(ctxt, &p.To) 3218 r := p.To.Reg 3219 x := p.To.Index 3220 if r == 0 { 3221 r = o.param 3222 } 3223 if p.From.Sym != nil { 3224 zRIL(_b, op_LARL, REGTMP, 0, asm) 3225 if v&0x1 != 0 { 3226 v -= 1 3227 zRX(op_LA, REGTMP, REGTMP, 0, 1, asm) 3228 } 3229 addrilreloc(ctxt, p.From.Sym, int64(v)) 3230 if d < -DISP20/2 || d >= DISP20/2 { 3231 zRIL(_a, op_LGFI, REGTMP2, uint32(d), asm) 3232 if x != 0 { 3233 zRRE(op_AGR, REGTMP2, uint32(x), asm) 3234 } 3235 d = 0 3236 x = REGTMP2 3237 } 3238 zRXY(zopstore(ctxt, p.As), REGTMP, uint32(x), uint32(r), uint32(d), asm) 3239 } else if int32(int16(v)) == v && x == 0 { 3240 if d < 0 || d >= DISP12 { 3241 if r == REGTMP || r == REGTMP2 { 3242 zRIL(_a, op_AGFI, uint32(r), uint32(d), asm) 3243 } else { 3244 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm) 3245 zRRE(op_AGR, REGTMP, uint32(r), asm) 3246 r = REGTMP 3247 } 3248 d = 0 3249 } 3250 var opcode uint32 3251 switch p.As { 3252 case AMOVD: 3253 opcode = op_MVGHI 3254 case AMOVW, AMOVWZ: 3255 opcode = op_MVHI 3256 case AMOVH, AMOVHZ: 3257 opcode = op_MVHHI 3258 case AMOVB, AMOVBZ: 3259 opcode = op_MVI 3260 } 3261 if opcode == op_MVI { 3262 zSI(opcode, uint32(v), uint32(r), uint32(d), asm) 3263 } else { 3264 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm) 3265 } 3266 } else { 3267 zRIL(_a, op_LGFI, REGTMP2, uint32(v), asm) 3268 if d < -DISP20/2 || d >= DISP20/2 { 3269 if r == REGTMP { 3270 zRIL(_a, op_AGFI, REGTMP, uint32(d), asm) 3271 } else { 3272 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm) 3273 if x != 0 { 3274 zRRE(op_AGR, REGTMP, uint32(x), asm) 3275 } 3276 x = REGTMP 3277 } 3278 d = 0 3279 } 3280 zRXY(zopstore(ctxt, p.As), REGTMP2, uint32(x), uint32(r), uint32(d), asm) 3281 } 3282 3283 case 73: // mov $constant addr (including relocation) 3284 v := regoff(ctxt, &p.From) 3285 d := regoff(ctxt, &p.To) 3286 a := uint32(0) 3287 if d&1 != 0 { 3288 d -= 1 3289 a = 1 3290 } 3291 zRIL(_b, op_LARL, REGTMP, uint32(d), asm) 3292 addrilreloc(ctxt, p.To.Sym, int64(d)) 3293 if p.From.Sym != nil { 3294 zRIL(_b, op_LARL, REGTMP2, 0, asm) 3295 a := uint32(0) 3296 if v&0x1 != 0 { 3297 v -= 1 3298 zRX(op_LA, REGTMP2, REGTMP2, 0, 1, asm) 3299 } 3300 addrilrelocoffset(ctxt, p.From.Sym, int64(v), sizeRIL) 3301 zRXY(zopstore(ctxt, p.As), REGTMP2, 0, REGTMP, a, asm) 3302 } else if int32(int16(v)) == v { 3303 var opcode uint32 3304 switch p.As { 3305 case AMOVD: 3306 opcode = op_MVGHI 3307 case AMOVW, AMOVWZ: 3308 opcode = op_MVHI 3309 case AMOVH, AMOVHZ: 3310 opcode = op_MVHHI 3311 case AMOVB, AMOVBZ: 3312 opcode = op_MVI 3313 } 3314 if opcode == op_MVI { 3315 zSI(opcode, uint32(v), REGTMP, a, asm) 3316 } else { 3317 zSIL(opcode, REGTMP, a, uint32(v), asm) 3318 } 3319 } else { 3320 zRIL(_a, op_LGFI, REGTMP2, uint32(v), asm) 3321 zRXY(zopstore(ctxt, p.As), REGTMP2, 0, REGTMP, a, asm) 3322 } 3323 3324 case 74: // mov reg addr (including relocation) 3325 i2 := regoff(ctxt, &p.To) 3326 switch p.As { 3327 case AMOVD: 3328 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm) 3329 case AMOVW, AMOVWZ: // The zero extension doesn't affect store instructions 3330 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm) 3331 case AMOVH, AMOVHZ: // The zero extension doesn't affect store instructions 3332 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm) 3333 case AMOVB, AMOVBZ: // The zero extension doesn't affect store instructions 3334 zRIL(_b, op_LARL, REGTMP, 0, asm) 3335 adj := uint32(0) // adjustment needed for odd addresses 3336 if i2&1 != 0 { 3337 i2 -= 1 3338 adj = 1 3339 } 3340 zRX(op_STC, uint32(p.From.Reg), 0, REGTMP, adj, asm) 3341 case AFMOVD: 3342 zRIL(_b, op_LARL, REGTMP, 0, asm) 3343 zRX(op_STD, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3344 case AFMOVS: 3345 zRIL(_b, op_LARL, REGTMP, 0, asm) 3346 zRX(op_STE, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3347 } 3348 addrilreloc(ctxt, p.To.Sym, int64(i2)) 3349 3350 case 75: // mov addr reg (including relocation) 3351 i2 := regoff(ctxt, &p.From) 3352 switch p.As { 3353 case AMOVD: 3354 if i2&1 != 0 { 3355 zRIL(_b, op_LARL, REGTMP, 0, asm) 3356 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 1, asm) 3357 i2 -= 1 3358 } else { 3359 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3360 } 3361 case AMOVW: 3362 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm) 3363 case AMOVWZ: 3364 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm) 3365 case AMOVH: 3366 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm) 3367 case AMOVHZ: 3368 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm) 3369 case AMOVB, AMOVBZ: 3370 zRIL(_b, op_LARL, REGTMP, 0, asm) 3371 adj := uint32(0) // adjustment needed for odd addresses 3372 if i2&1 != 0 { 3373 i2 -= 1 3374 adj = 1 3375 } 3376 switch p.As { 3377 case AMOVB: 3378 zRXY(op_LGB, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3379 case AMOVBZ: 3380 zRXY(op_LLGC, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3381 } 3382 case AFMOVD: 3383 zRIL(_a, op_LARL, REGTMP, 0, asm) 3384 zRX(op_LD, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3385 case AFMOVS: 3386 zRIL(_a, op_LARL, REGTMP, 0, asm) 3387 zRX(op_LE, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3388 } 3389 addrilreloc(ctxt, p.From.Sym, int64(i2)) 3390 3391 case 77: // syscall $constant 3392 if p.From.Offset > 255 || p.From.Offset < 1 { 3393 ctxt.Diag("illegal system call; system call number out of range: %v", p) 3394 zE(op_TRAP2, asm) // trap always 3395 } else { 3396 zI(op_SVC, uint32(p.From.Offset), asm) 3397 } 3398 3399 case 78: // undef 3400 // "An instruction consisting entirely of binary 0s is guaranteed 3401 // always to be an illegal instruction." 3402 *asm = append(*asm, 0, 0, 0, 0) 3403 3404 case 79: // compare and swap reg reg reg 3405 v := regoff(ctxt, &p.To) 3406 if v < 0 { 3407 v = 0 3408 } 3409 if p.As == ACS { 3410 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3411 } else if p.As == ACSG { 3412 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3413 } 3414 3415 case 81: // sync 3416 zRR(op_BCR, 0xE, 0, asm) 3417 3418 case 82: // fixed to float conversion 3419 var opcode uint32 3420 switch p.As { 3421 default: 3422 log.Fatalf("unexpected opcode %v", p.As) 3423 case ACEFBRA: 3424 opcode = op_CEFBRA 3425 case ACDFBRA: 3426 opcode = op_CDFBRA 3427 case ACEGBRA: 3428 opcode = op_CEGBRA 3429 case ACDGBRA: 3430 opcode = op_CDGBRA 3431 case ACELFBR: 3432 opcode = op_CELFBR 3433 case ACDLFBR: 3434 opcode = op_CDLFBR 3435 case ACELGBR: 3436 opcode = op_CELGBR 3437 case ACDLGBR: 3438 opcode = op_CDLGBR 3439 } 3440 // set immediate operand M3 to 0 to use the default BFP rounding mode 3441 // (usually round to nearest, ties to even) 3442 // TODO(mundaym): should this be fixed at round to nearest, ties to even? 3443 // M4 is reserved and must be 0 3444 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3445 3446 case 83: // float to fixed conversion 3447 var opcode uint32 3448 switch p.As { 3449 default: 3450 log.Fatalf("unexpected opcode %v", p.As) 3451 case ACFEBRA: 3452 opcode = op_CFEBRA 3453 case ACFDBRA: 3454 opcode = op_CFDBRA 3455 case ACGEBRA: 3456 opcode = op_CGEBRA 3457 case ACGDBRA: 3458 opcode = op_CGDBRA 3459 case ACLFEBR: 3460 opcode = op_CLFEBR 3461 case ACLFDBR: 3462 opcode = op_CLFDBR 3463 case ACLGEBR: 3464 opcode = op_CLGEBR 3465 case ACLGDBR: 3466 opcode = op_CLGDBR 3467 } 3468 // set immediate operand M3 to 5 for rounding toward zero (required by Go spec) 3469 // M4 is reserved and must be 0 3470 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3471 3472 case 84: // storage-and-storage operations $length mem mem (length in From3) 3473 l := regoff(ctxt, p.From3) 3474 if l < 1 || l > 256 { 3475 ctxt.Diag("number of bytes (%v) not in range [1,256]", l) 3476 } 3477 if p.From.Index != 0 || p.To.Index != 0 { 3478 ctxt.Diag("cannot use index reg") 3479 } 3480 b1 := p.To.Reg 3481 b2 := p.From.Reg 3482 if b1 == 0 { 3483 b1 = o.param 3484 } 3485 if b2 == 0 { 3486 b2 = o.param 3487 } 3488 d1 := regoff(ctxt, &p.To) 3489 d2 := regoff(ctxt, &p.From) 3490 if d1 < 0 || d1 >= DISP12 { 3491 if b2 == REGTMP { 3492 ctxt.Diag("REGTMP conflict") 3493 } 3494 if b1 != REGTMP { 3495 zRRE(op_LGR, REGTMP, uint32(b1), asm) 3496 } 3497 zRIL(_a, op_AGFI, REGTMP, uint32(d1), asm) 3498 if d1 == d2 && b1 == b2 { 3499 d2 = 0 3500 b2 = REGTMP 3501 } 3502 d1 = 0 3503 b1 = REGTMP 3504 } 3505 if d2 < 0 || d2 >= DISP12 { 3506 if b1 == REGTMP2 { 3507 ctxt.Diag("REGTMP2 conflict") 3508 } 3509 if b2 != REGTMP2 { 3510 zRRE(op_LGR, REGTMP2, uint32(b2), asm) 3511 } 3512 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm) 3513 d2 = 0 3514 b2 = REGTMP2 3515 } 3516 var opcode uint32 3517 switch p.As { 3518 default: 3519 ctxt.Diag("unexpected opcode %v", p.As) 3520 case AMVC: 3521 opcode = op_MVC 3522 case ACLC: 3523 opcode = op_CLC 3524 // swap operand order for CLC so that it matches CMP 3525 b1, b2 = b2, b1 3526 d1, d2 = d2, d1 3527 case AXC: 3528 opcode = op_XC 3529 case AOC: 3530 opcode = op_OC 3531 case ANC: 3532 opcode = op_NC 3533 } 3534 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm) 3535 3536 case 85: // load address relative long 3537 v := regoff(ctxt, &p.From) 3538 if p.From.Sym == nil { 3539 if (v & 1) != 0 { 3540 ctxt.Diag("cannot use LARL with odd offset: %v", v) 3541 } 3542 } else { 3543 addrilreloc(ctxt, p.From.Sym, int64(v)) 3544 v = 0 3545 } 3546 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm) 3547 3548 case 86: // load address 3549 d := vregoff(ctxt, &p.From) 3550 x := p.From.Index 3551 b := p.From.Reg 3552 if b == 0 { 3553 b = o.param 3554 } 3555 switch p.As { 3556 case ALA: 3557 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3558 case ALAY: 3559 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3560 } 3561 3562 case 87: // execute relative long 3563 v := vregoff(ctxt, &p.From) 3564 if p.From.Sym == nil { 3565 if v&1 != 0 { 3566 ctxt.Diag("cannot use EXRL with odd offset: %v", v) 3567 } 3568 } else { 3569 addrilreloc(ctxt, p.From.Sym, v) 3570 v = 0 3571 } 3572 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm) 3573 3574 case 88: // store clock 3575 var opcode uint32 3576 switch p.As { 3577 case ASTCK: 3578 opcode = op_STCK 3579 case ASTCKC: 3580 opcode = op_STCKC 3581 case ASTCKE: 3582 opcode = op_STCKE 3583 case ASTCKF: 3584 opcode = op_STCKF 3585 } 3586 v := vregoff(ctxt, &p.To) 3587 r := int(p.To.Reg) 3588 if r == 0 { 3589 r = int(o.param) 3590 } 3591 zS(opcode, uint32(r), uint32(v), asm) 3592 3593 case 89: // compare and branch reg reg 3594 var v int32 3595 if p.Pcond != nil { 3596 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3597 } 3598 var opcode, opcode2 uint32 3599 switch p.As { 3600 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3601 opcode = op_CGRJ 3602 opcode2 = op_CGR 3603 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3604 opcode = op_CLGRJ 3605 opcode2 = op_CLGR 3606 } 3607 mask := branchMask(ctxt, p) 3608 if int32(int16(v)) != v { 3609 zRRE(opcode2, uint32(p.From.Reg), uint32(p.Reg), asm) 3610 zRIL(_c, op_BRCL, mask, uint32(v-sizeRRE/2), asm) 3611 } else { 3612 zRIE(_b, opcode, uint32(p.From.Reg), uint32(p.Reg), uint32(v), 0, 0, mask, 0, asm) 3613 } 3614 3615 case 90: // compare and branch reg $constant 3616 var v int32 3617 if p.Pcond != nil { 3618 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3619 } 3620 var opcode, opcode2 uint32 3621 switch p.As { 3622 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3623 opcode = op_CGIJ 3624 opcode2 = op_CGFI 3625 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3626 opcode = op_CLGIJ 3627 opcode2 = op_CLGFI 3628 } 3629 mask := branchMask(ctxt, p) 3630 if int32(int16(v)) != v { 3631 zRIL(_a, opcode2, uint32(p.From.Reg), uint32(regoff(ctxt, p.From3)), asm) 3632 zRIL(_c, op_BRCL, mask, uint32(v-sizeRIL/2), asm) 3633 } else { 3634 zRIE(_c, opcode, uint32(p.From.Reg), mask, uint32(v), 0, 0, 0, uint32(regoff(ctxt, p.From3)), asm) 3635 } 3636 3637 case 93: // GOT lookup 3638 v := vregoff(ctxt, &p.To) 3639 if v != 0 { 3640 ctxt.Diag("invalid offset against GOT slot %v", p) 3641 } 3642 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3643 rel := obj.Addrel(ctxt.Cursym) 3644 rel.Off = int32(ctxt.Pc + 2) 3645 rel.Siz = 4 3646 rel.Sym = p.From.Sym 3647 rel.Type = obj.R_GOTPCREL 3648 rel.Add = 2 + int64(rel.Siz) 3649 3650 case 94: // TLS local exec model 3651 zRIL(_b, op_LARL, REGTMP, (sizeRIL+sizeRXY+sizeRI)>>1, asm) 3652 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3653 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm) 3654 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0) 3655 rel := obj.Addrel(ctxt.Cursym) 3656 rel.Off = int32(ctxt.Pc + sizeRIL + sizeRXY + sizeRI) 3657 rel.Siz = 8 3658 rel.Sym = p.From.Sym 3659 rel.Type = obj.R_TLS_LE 3660 rel.Add = 0 3661 3662 case 95: // TLS initial exec model 3663 // Assembly | Relocation symbol | Done Here? 3664 // -------------------------------------------------------------- 3665 // ear %r11, %a0 | | 3666 // sllg %r11, %r11, 32 | | 3667 // ear %r11, %a1 | | 3668 // larl %r10, <var>@indntpoff | R_390_TLS_IEENT | Y 3669 // lg %r10, 0(%r10) | R_390_TLS_LOAD (tag) | Y 3670 // la %r10, 0(%r10, %r11) | | 3671 // -------------------------------------------------------------- 3672 3673 // R_390_TLS_IEENT 3674 zRIL(_b, op_LARL, REGTMP, 0, asm) 3675 ieent := obj.Addrel(ctxt.Cursym) 3676 ieent.Off = int32(ctxt.Pc + 2) 3677 ieent.Siz = 4 3678 ieent.Sym = p.From.Sym 3679 ieent.Type = obj.R_TLS_IE 3680 ieent.Add = 2 + int64(ieent.Siz) 3681 3682 // R_390_TLS_LOAD 3683 zRXY(op_LGF, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3684 // TODO(mundaym): add R_390_TLS_LOAD relocation here 3685 // not strictly required but might allow the linker to optimize 3686 3687 case 96: // clear macro 3688 length := vregoff(ctxt, &p.From) 3689 offset := vregoff(ctxt, &p.To) 3690 reg := p.To.Reg 3691 if reg == 0 { 3692 reg = o.param 3693 } 3694 if length <= 0 { 3695 ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length) 3696 } 3697 for length > 0 { 3698 if offset < 0 || offset >= DISP12 { 3699 if offset >= -DISP20/2 && offset < DISP20/2 { 3700 zRXY(op_LAY, REGTMP, uint32(reg), 0, uint32(offset), asm) 3701 } else { 3702 if reg != REGTMP { 3703 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3704 } 3705 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3706 } 3707 reg = REGTMP 3708 offset = 0 3709 } 3710 size := length 3711 if size > 256 { 3712 size = 256 3713 } 3714 3715 switch size { 3716 case 1: 3717 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm) 3718 case 2: 3719 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm) 3720 case 4: 3721 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm) 3722 case 8: 3723 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm) 3724 default: 3725 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm) 3726 } 3727 3728 length -= size 3729 offset += size 3730 } 3731 3732 case 97: // store multiple 3733 rstart := p.From.Reg 3734 rend := p.Reg 3735 offset := regoff(ctxt, &p.To) 3736 reg := p.To.Reg 3737 if reg == 0 { 3738 reg = o.param 3739 } 3740 if offset < -DISP20/2 || offset >= DISP20/2 { 3741 if reg != REGTMP { 3742 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3743 } 3744 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3745 reg = REGTMP 3746 offset = 0 3747 } 3748 switch p.As { 3749 case ASTMY: 3750 if offset >= 0 && offset < DISP12 { 3751 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3752 } else { 3753 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3754 } 3755 case ASTMG: 3756 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3757 } 3758 3759 case 98: // load multiple 3760 rstart := p.Reg 3761 rend := p.To.Reg 3762 offset := regoff(ctxt, &p.From) 3763 reg := p.From.Reg 3764 if reg == 0 { 3765 reg = o.param 3766 } 3767 if offset < -DISP20/2 || offset >= DISP20/2 { 3768 if reg != REGTMP { 3769 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3770 } 3771 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3772 reg = REGTMP 3773 offset = 0 3774 } 3775 switch p.As { 3776 case ALMY: 3777 if offset >= 0 && offset < DISP12 { 3778 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3779 } else { 3780 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3781 } 3782 case ALMG: 3783 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3784 } 3785 3786 case 100: // VRX STORE 3787 op, m3, _ := vop(p.As) 3788 if p.From3 != nil { 3789 m3 = uint32(vregoff(ctxt, p.From3)) 3790 } 3791 b2 := p.To.Reg 3792 if b2 == 0 { 3793 b2 = o.param 3794 } 3795 d2 := uint32(vregoff(ctxt, &p.To)) 3796 zVRX(op, uint32(p.From.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3797 3798 case 101: // VRX LOAD 3799 op, m3, _ := vop(p.As) 3800 if p.From3 != nil { 3801 m3 = uint32(vregoff(ctxt, p.From3)) 3802 } 3803 b2 := p.From.Reg 3804 if b2 == 0 { 3805 b2 = o.param 3806 } 3807 d2 := uint32(vregoff(ctxt, &p.From)) 3808 zVRX(op, uint32(p.To.Reg), uint32(p.From.Index), uint32(b2), d2, m3, asm) 3809 3810 case 102: // VRV SCATTER 3811 op, m3, _ := vop(p.As) 3812 if p.From3 != nil { 3813 m3 = uint32(vregoff(ctxt, p.From3)) 3814 } 3815 b2 := p.To.Reg 3816 if b2 == 0 { 3817 b2 = o.param 3818 } 3819 d2 := uint32(vregoff(ctxt, &p.To)) 3820 zVRV(op, uint32(p.From.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3821 3822 case 103: // VRV GATHER 3823 op, m3, _ := vop(p.As) 3824 if p.From3 != nil { 3825 m3 = uint32(vregoff(ctxt, p.From3)) 3826 } 3827 b2 := p.From.Reg 3828 if b2 == 0 { 3829 b2 = o.param 3830 } 3831 d2 := uint32(vregoff(ctxt, &p.From)) 3832 zVRV(op, uint32(p.To.Reg), uint32(p.From.Index), uint32(b2), d2, m3, asm) 3833 3834 case 104: // VRS SHIFT/ROTATE and LOAD GR FROM VR ELEMENT 3835 op, m4, _ := vop(p.As) 3836 fr := p.Reg 3837 if fr == 0 { 3838 fr = p.To.Reg 3839 } 3840 bits := uint32(vregoff(ctxt, &p.From)) 3841 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm) 3842 3843 case 105: // VRS STORE MULTIPLE 3844 op, _, _ := vop(p.As) 3845 offset := uint32(vregoff(ctxt, &p.To)) 3846 reg := p.To.Reg 3847 if reg == 0 { 3848 reg = o.param 3849 } 3850 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm) 3851 3852 case 106: // VRS LOAD MULTIPLE 3853 op, _, _ := vop(p.As) 3854 offset := uint32(vregoff(ctxt, &p.From)) 3855 reg := p.From.Reg 3856 if reg == 0 { 3857 reg = o.param 3858 } 3859 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm) 3860 3861 case 107: // VRS STORE WITH LENGTH 3862 op, _, _ := vop(p.As) 3863 offset := uint32(vregoff(ctxt, &p.To)) 3864 reg := p.To.Reg 3865 if reg == 0 { 3866 reg = o.param 3867 } 3868 zVRS(op, uint32(p.From.Reg), uint32(p.From3.Reg), uint32(reg), offset, 0, asm) 3869 3870 case 108: // VRS LOAD WITH LENGTH 3871 op, _, _ := vop(p.As) 3872 offset := uint32(vregoff(ctxt, &p.From)) 3873 reg := p.From.Reg 3874 if reg == 0 { 3875 reg = o.param 3876 } 3877 zVRS(op, uint32(p.To.Reg), uint32(p.From3.Reg), uint32(reg), offset, 0, asm) 3878 3879 case 109: // VRI-a 3880 op, _, _ := vop(p.As) 3881 i2 := uint32(vregoff(ctxt, &p.From)) 3882 switch p.As { 3883 case AVZERO: 3884 i2 = 0 3885 case AVONE: 3886 i2 = 0xffff 3887 } 3888 m3 := uint32(0) 3889 if p.From3 != nil { 3890 m3 = uint32(vregoff(ctxt, p.From3)) 3891 } 3892 zVRIa(op, uint32(p.To.Reg), i2, m3, asm) 3893 3894 case 110: 3895 op, m4, _ := vop(p.As) 3896 i2 := uint32(vregoff(ctxt, p.From3)) 3897 i3 := uint32(vregoff(ctxt, &p.From)) 3898 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm) 3899 3900 case 111: 3901 op, m4, _ := vop(p.As) 3902 i2 := uint32(vregoff(ctxt, &p.From)) 3903 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm) 3904 3905 case 112: 3906 op, m5, _ := vop(p.As) 3907 i4 := uint32(vregoff(ctxt, p.From3)) 3908 zVRId(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), i4, m5, asm) 3909 3910 case 113: 3911 op, m4, _ := vop(p.As) 3912 m5 := singleElementMask(p.As) 3913 i3 := uint32(vregoff(ctxt, &p.From)) 3914 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm) 3915 3916 case 114: // VRR-a 3917 op, m3, m5 := vop(p.As) 3918 m4 := singleElementMask(p.As) 3919 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm) 3920 3921 case 115: // VRR-a COMPARE 3922 op, m3, m5 := vop(p.As) 3923 m4 := singleElementMask(p.As) 3924 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm) 3925 3926 case 116: // VRR-a 3927 3928 case 117: // VRR-b 3929 op, m4, m5 := vop(p.As) 3930 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm) 3931 3932 case 118: // VRR-c 3933 op, m4, m6 := vop(p.As) 3934 m5 := singleElementMask(p.As) 3935 v3 := p.Reg 3936 if v3 == 0 { 3937 v3 = p.To.Reg 3938 } 3939 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm) 3940 3941 case 119: // VRR-c SHIFT/ROTATE/DIVIDE/SUB (rhs value on the left, like SLD, DIV etc.) 3942 op, m4, m6 := vop(p.As) 3943 m5 := singleElementMask(p.As) 3944 v2 := p.Reg 3945 if v2 == 0 { 3946 v2 = p.To.Reg 3947 } 3948 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm) 3949 3950 case 120: // VRR-d 3951 op, m6, _ := vop(p.As) 3952 m5 := singleElementMask(p.As) 3953 v1 := uint32(p.To.Reg) 3954 v2 := uint32(p.From3.Reg) 3955 v3 := uint32(p.From.Reg) 3956 v4 := uint32(p.Reg) 3957 zVRRd(op, v1, v2, v3, m6, m5, v4, asm) 3958 3959 case 121: // VRR-e 3960 op, m6, _ := vop(p.As) 3961 m5 := singleElementMask(p.As) 3962 v1 := uint32(p.To.Reg) 3963 v2 := uint32(p.From3.Reg) 3964 v3 := uint32(p.From.Reg) 3965 v4 := uint32(p.Reg) 3966 zVRRe(op, v1, v2, v3, m5, m6, v4, asm) 3967 3968 case 122: // VRR-f LOAD VRS FROM GRS DISJOINT 3969 op, _, _ := vop(p.As) 3970 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 3971 3972 case 123: // VPDI $m4, V2, V3, V1 3973 op, _, _ := vop(p.As) 3974 m4 := regoff(ctxt, p.From3) 3975 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), 0, 0, uint32(m4), asm) 3976 } 3977 } 3978 3979 func vregoff(ctxt *obj.Link, a *obj.Addr) int64 { 3980 ctxt.Instoffset = 0 3981 if a != nil { 3982 aclass(ctxt, a) 3983 } 3984 return ctxt.Instoffset 3985 } 3986 3987 func regoff(ctxt *obj.Link, a *obj.Addr) int32 { 3988 return int32(vregoff(ctxt, a)) 3989 } 3990 3991 // zopload returns the RXY op for the given load 3992 func zopload(ctxt *obj.Link, a obj.As) uint32 { 3993 switch a { 3994 // fixed point load 3995 case AMOVD: 3996 return op_LG 3997 case AMOVW: 3998 return op_LGF 3999 case AMOVWZ: 4000 return op_LLGF 4001 case AMOVH: 4002 return op_LGH 4003 case AMOVHZ: 4004 return op_LLGH 4005 case AMOVB: 4006 return op_LGB 4007 case AMOVBZ: 4008 return op_LLGC 4009 4010 // floating point load 4011 case AFMOVD: 4012 return op_LDY 4013 case AFMOVS: 4014 return op_LEY 4015 4016 // byte reversed load 4017 case AMOVDBR: 4018 return op_LRVG 4019 case AMOVWBR: 4020 return op_LRV 4021 case AMOVHBR: 4022 return op_LRVH 4023 } 4024 4025 ctxt.Diag("unknown store opcode %v", obj.Aconv(a)) 4026 return 0 4027 } 4028 4029 // zopstore returns the RXY op for the given store 4030 func zopstore(ctxt *obj.Link, a obj.As) uint32 { 4031 switch a { 4032 // fixed point store 4033 case AMOVD: 4034 return op_STG 4035 case AMOVW, AMOVWZ: 4036 return op_STY 4037 case AMOVH, AMOVHZ: 4038 return op_STHY 4039 case AMOVB, AMOVBZ: 4040 return op_STCY 4041 4042 // floating point store 4043 case AFMOVD: 4044 return op_STDY 4045 case AFMOVS: 4046 return op_STEY 4047 4048 // byte reversed store 4049 case AMOVDBR: 4050 return op_STRVG 4051 case AMOVWBR: 4052 return op_STRV 4053 case AMOVHBR: 4054 return op_STRVH 4055 } 4056 4057 ctxt.Diag("unknown store opcode %v", obj.Aconv(a)) 4058 return 0 4059 } 4060 4061 // zoprre returns the RRE op for the given a 4062 func zoprre(ctxt *obj.Link, a obj.As) uint32 { 4063 switch a { 4064 case ACMP: 4065 return op_CGR 4066 case ACMPU: 4067 return op_CLGR 4068 case AFCMPO: //ordered 4069 return op_KDBR 4070 case AFCMPU: //unordered 4071 return op_CDBR 4072 case ACEBR: 4073 return op_CEBR 4074 } 4075 ctxt.Diag("unknown rre opcode %v", obj.Aconv(a)) 4076 return 0 4077 } 4078 4079 // zoprr returns the RR op for the given a 4080 func zoprr(ctxt *obj.Link, a obj.As) uint32 { 4081 switch a { 4082 case ACMPW: 4083 return op_CR 4084 case ACMPWU: 4085 return op_CLR 4086 } 4087 ctxt.Diag("unknown rr opcode %v", obj.Aconv(a)) 4088 return 0 4089 } 4090 4091 // zopril returns the RIL op for the given a 4092 func zopril(ctxt *obj.Link, a obj.As) uint32 { 4093 switch a { 4094 case ACMP: 4095 return op_CGFI 4096 case ACMPU: 4097 return op_CLGFI 4098 case ACMPW: 4099 return op_CFI 4100 case ACMPWU: 4101 return op_CLFI 4102 } 4103 ctxt.Diag("unknown ril opcode %v", obj.Aconv(a)) 4104 return 0 4105 } 4106 4107 // z instructions sizes 4108 const ( 4109 sizeE = 2 4110 sizeI = 2 4111 sizeIE = 4 4112 sizeMII = 6 4113 sizeRI = 4 4114 sizeRI1 = 4 4115 sizeRI2 = 4 4116 sizeRI3 = 4 4117 sizeRIE = 6 4118 sizeRIE1 = 6 4119 sizeRIE2 = 6 4120 sizeRIE3 = 6 4121 sizeRIE4 = 6 4122 sizeRIE5 = 6 4123 sizeRIE6 = 6 4124 sizeRIL = 6 4125 sizeRIL1 = 6 4126 sizeRIL2 = 6 4127 sizeRIL3 = 6 4128 sizeRIS = 6 4129 sizeRR = 2 4130 sizeRRD = 4 4131 sizeRRE = 4 4132 sizeRRF = 4 4133 sizeRRF1 = 4 4134 sizeRRF2 = 4 4135 sizeRRF3 = 4 4136 sizeRRF4 = 4 4137 sizeRRF5 = 4 4138 sizeRRR = 2 4139 sizeRRS = 6 4140 sizeRS = 4 4141 sizeRS1 = 4 4142 sizeRS2 = 4 4143 sizeRSI = 4 4144 sizeRSL = 6 4145 sizeRSY = 6 4146 sizeRSY1 = 6 4147 sizeRSY2 = 6 4148 sizeRX = 4 4149 sizeRX1 = 4 4150 sizeRX2 = 4 4151 sizeRXE = 6 4152 sizeRXF = 6 4153 sizeRXY = 6 4154 sizeRXY1 = 6 4155 sizeRXY2 = 6 4156 sizeS = 4 4157 sizeSI = 4 4158 sizeSIL = 6 4159 sizeSIY = 6 4160 sizeSMI = 6 4161 sizeSS = 6 4162 sizeSS1 = 6 4163 sizeSS2 = 6 4164 sizeSS3 = 6 4165 sizeSS4 = 6 4166 sizeSS5 = 6 4167 sizeSS6 = 6 4168 sizeSSE = 6 4169 sizeSSF = 6 4170 ) 4171 4172 // instruction format variations 4173 type form int 4174 4175 const ( 4176 _a form = iota 4177 _b 4178 _c 4179 _d 4180 _e 4181 _f 4182 ) 4183 4184 func zE(op uint32, asm *[]byte) { 4185 *asm = append(*asm, uint8(op>>8), uint8(op)) 4186 } 4187 4188 func zI(op, i1 uint32, asm *[]byte) { 4189 *asm = append(*asm, uint8(op>>8), uint8(i1)) 4190 } 4191 4192 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) { 4193 *asm = append(*asm, 4194 uint8(op>>8), 4195 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F), 4196 uint8(ri2), 4197 uint8(ri3>>16), 4198 uint8(ri3>>8), 4199 uint8(ri3)) 4200 } 4201 4202 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4203 *asm = append(*asm, 4204 uint8(op>>8), 4205 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4206 uint8(i2_ri2>>8), 4207 uint8(i2_ri2)) 4208 } 4209 4210 // Expected argument values for the instruction formats. 4211 // 4212 // Format a1 a2 a3 a4 a5 a6 a7 4213 // ------------------------------------ 4214 // a r1, 0, i2, 0, 0, m3, 0 4215 // b r1, r2, ri4, 0, 0, m3, 0 4216 // c r1, m3, ri4, 0, 0, 0, i2 4217 // d r1, r3, i2, 0, 0, 0, 0 4218 // e r1, r3, ri2, 0, 0, 0, 0 4219 // f r1, r2, 0, i3, i4, 0, i5 4220 // g r1, m3, i2, 0, 0, 0, 0 4221 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) { 4222 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F)) 4223 4224 switch f { 4225 default: 4226 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2)) 4227 case _f: 4228 *asm = append(*asm, uint8(i3), uint8(i4)) 4229 } 4230 4231 switch f { 4232 case _a, _b: 4233 *asm = append(*asm, uint8(m3)<<4) 4234 default: 4235 *asm = append(*asm, uint8(i2_i5)) 4236 } 4237 4238 *asm = append(*asm, uint8(op)) 4239 } 4240 4241 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4242 if f == _a || f == _b { 4243 r1_m1 = r1_m1 - obj.RBaseS390X // this is a register base 4244 } 4245 *asm = append(*asm, 4246 uint8(op>>8), 4247 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4248 uint8(i2_ri2>>24), 4249 uint8(i2_ri2>>16), 4250 uint8(i2_ri2>>8), 4251 uint8(i2_ri2)) 4252 } 4253 4254 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) { 4255 *asm = append(*asm, 4256 uint8(op>>8), 4257 (uint8(r1)<<4)|uint8(m3&0x0F), 4258 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F), 4259 uint8(d4), 4260 uint8(i2), 4261 uint8(op)) 4262 } 4263 4264 func zRR(op, r1, r2 uint32, asm *[]byte) { 4265 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F)) 4266 } 4267 4268 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) { 4269 *asm = append(*asm, 4270 uint8(op>>8), 4271 uint8(op), 4272 uint8(r1)<<4, 4273 (uint8(r3)<<4)|uint8(r2&0x0F)) 4274 } 4275 4276 func zRRE(op, r1, r2 uint32, asm *[]byte) { 4277 *asm = append(*asm, 4278 uint8(op>>8), 4279 uint8(op), 4280 0, 4281 (uint8(r1)<<4)|uint8(r2&0x0F)) 4282 } 4283 4284 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) { 4285 *asm = append(*asm, 4286 uint8(op>>8), 4287 uint8(op), 4288 (uint8(r3_m3)<<4)|uint8(m4&0x0F), 4289 (uint8(r1)<<4)|uint8(r2&0x0F)) 4290 } 4291 4292 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) { 4293 *asm = append(*asm, 4294 uint8(op>>8), 4295 (uint8(r1)<<4)|uint8(r2&0x0F), 4296 (uint8(b4)<<4)|uint8((d4>>8)&0x0F), 4297 uint8(d4), 4298 uint8(m3)<<4, 4299 uint8(op)) 4300 } 4301 4302 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4303 *asm = append(*asm, 4304 uint8(op>>8), 4305 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4306 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4307 uint8(d2)) 4308 } 4309 4310 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) { 4311 *asm = append(*asm, 4312 uint8(op>>8), 4313 (uint8(r1)<<4)|uint8(r3&0x0F), 4314 uint8(ri2>>8), 4315 uint8(ri2)) 4316 } 4317 4318 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) { 4319 *asm = append(*asm, 4320 uint8(op>>8), 4321 uint8(l1), 4322 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4323 uint8(d2), 4324 uint8(op)) 4325 } 4326 4327 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4328 dl2 := uint16(d2) & 0x0FFF 4329 *asm = append(*asm, 4330 uint8(op>>8), 4331 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4332 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4333 uint8(dl2), 4334 uint8(d2>>12), 4335 uint8(op)) 4336 } 4337 4338 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4339 *asm = append(*asm, 4340 uint8(op>>8), 4341 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4342 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4343 uint8(d2)) 4344 } 4345 4346 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) { 4347 *asm = append(*asm, 4348 uint8(op>>8), 4349 (uint8(r1)<<4)|uint8(x2&0x0F), 4350 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4351 uint8(d2), 4352 uint8(m3)<<4, 4353 uint8(op)) 4354 } 4355 4356 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) { 4357 *asm = append(*asm, 4358 uint8(op>>8), 4359 (uint8(r3)<<4)|uint8(x2&0x0F), 4360 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4361 uint8(d2), 4362 uint8(m1)<<4, 4363 uint8(op)) 4364 } 4365 4366 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4367 dl2 := uint16(d2) & 0x0FFF 4368 *asm = append(*asm, 4369 uint8(op>>8), 4370 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4371 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4372 uint8(dl2), 4373 uint8(d2>>12), 4374 uint8(op)) 4375 } 4376 4377 func zS(op, b2, d2 uint32, asm *[]byte) { 4378 *asm = append(*asm, 4379 uint8(op>>8), 4380 uint8(op), 4381 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4382 uint8(d2)) 4383 } 4384 4385 func zSI(op, i2, b1, d1 uint32, asm *[]byte) { 4386 *asm = append(*asm, 4387 uint8(op>>8), 4388 uint8(i2), 4389 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4390 uint8(d1)) 4391 } 4392 4393 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) { 4394 *asm = append(*asm, 4395 uint8(op>>8), 4396 uint8(op), 4397 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4398 uint8(d1), 4399 uint8(i2>>8), 4400 uint8(i2)) 4401 } 4402 4403 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) { 4404 dl1 := uint16(d1) & 0x0FFF 4405 *asm = append(*asm, 4406 uint8(op>>8), 4407 uint8(i2), 4408 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F), 4409 uint8(dl1), 4410 uint8(d1>>12), 4411 uint8(op)) 4412 } 4413 4414 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) { 4415 *asm = append(*asm, 4416 uint8(op>>8), 4417 uint8(m1)<<4, 4418 (uint8(b3)<<4)|uint8((d3>>8)&0x0F), 4419 uint8(d3), 4420 uint8(ri2>>8), 4421 uint8(ri2)) 4422 } 4423 4424 // Expected argument values for the instruction formats. 4425 // 4426 // Format a1 a2 a3 a4 a5 a6 4427 // ------------------------------- 4428 // a l1, 0, b1, d1, b2, d2 4429 // b l1, l2, b1, d1, b2, d2 4430 // c l1, i3, b1, d1, b2, d2 4431 // d r1, r3, b1, d1, b2, d2 4432 // e r1, r3, b2, d2, b4, d4 4433 // f 0, l2, b1, d1, b2, d2 4434 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) { 4435 *asm = append(*asm, uint8(op>>8)) 4436 4437 switch f { 4438 case _a: 4439 *asm = append(*asm, uint8(l1_r1)) 4440 case _b, _c, _d, _e: 4441 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F)) 4442 case _f: 4443 *asm = append(*asm, uint8(l2_i3_r3)) 4444 } 4445 4446 *asm = append(*asm, 4447 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F), 4448 uint8(d1_d2), 4449 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F), 4450 uint8(d2_d4)) 4451 } 4452 4453 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) { 4454 *asm = append(*asm, 4455 uint8(op>>8), 4456 uint8(op), 4457 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4458 uint8(d1), 4459 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4460 uint8(d2)) 4461 } 4462 4463 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) { 4464 *asm = append(*asm, 4465 uint8(op>>8), 4466 (uint8(r3)<<4)|(uint8(op)&0x0F), 4467 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4468 uint8(d1), 4469 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4470 uint8(d2)) 4471 } 4472 4473 func rxb(va, vb, vc, vd uint32) uint8 { 4474 mask := uint8(0) 4475 if va >= REG_V16 && va <= REG_V31 { 4476 mask |= 0x8 4477 } 4478 if vb >= REG_V16 && vb <= REG_V31 { 4479 mask |= 0x4 4480 } 4481 if vc >= REG_V16 && vc <= REG_V31 { 4482 mask |= 0x2 4483 } 4484 if vd >= REG_V16 && vd <= REG_V31 { 4485 mask |= 0x1 4486 } 4487 return mask 4488 } 4489 4490 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) { 4491 *asm = append(*asm, 4492 uint8(op>>8), 4493 (uint8(v1)<<4)|(uint8(x2)&0xf), 4494 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4495 uint8(d2), 4496 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4497 uint8(op)) 4498 } 4499 4500 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) { 4501 *asm = append(*asm, 4502 uint8(op>>8), 4503 (uint8(v1)<<4)|(uint8(v2)&0xf), 4504 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4505 uint8(d2), 4506 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4507 uint8(op)) 4508 } 4509 4510 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) { 4511 *asm = append(*asm, 4512 uint8(op>>8), 4513 (uint8(v1)<<4)|(uint8(v3_r3)&0xf), 4514 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4515 uint8(d2), 4516 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0), 4517 uint8(op)) 4518 } 4519 4520 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) { 4521 *asm = append(*asm, 4522 uint8(op>>8), 4523 (uint8(v1)<<4)|(uint8(v2)&0xf), 4524 0, 4525 (uint8(m5)<<4)|(uint8(m4)&0xf), 4526 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4527 uint8(op)) 4528 } 4529 4530 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) { 4531 *asm = append(*asm, 4532 uint8(op>>8), 4533 (uint8(v1)<<4)|(uint8(v2)&0xf), 4534 uint8(v3)<<4, 4535 uint8(m5)<<4, 4536 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4537 uint8(op)) 4538 } 4539 4540 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) { 4541 *asm = append(*asm, 4542 uint8(op>>8), 4543 (uint8(v1)<<4)|(uint8(v2)&0xf), 4544 uint8(v3)<<4, 4545 (uint8(m6)<<4)|(uint8(m5)&0xf), 4546 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4547 uint8(op)) 4548 } 4549 4550 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) { 4551 *asm = append(*asm, 4552 uint8(op>>8), 4553 (uint8(v1)<<4)|(uint8(v2)&0xf), 4554 (uint8(v3)<<4)|(uint8(m5)&0xf), 4555 uint8(m6)<<4, 4556 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4557 uint8(op)) 4558 } 4559 4560 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) { 4561 *asm = append(*asm, 4562 uint8(op>>8), 4563 (uint8(v1)<<4)|(uint8(v2)&0xf), 4564 (uint8(v3)<<4)|(uint8(m6)&0xf), 4565 uint8(m5), 4566 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4567 uint8(op)) 4568 } 4569 4570 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) { 4571 *asm = append(*asm, 4572 uint8(op>>8), 4573 (uint8(v1)<<4)|(uint8(r2)&0xf), 4574 uint8(r3)<<4, 4575 0, 4576 rxb(v1, 0, 0, 0), 4577 uint8(op)) 4578 } 4579 4580 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) { 4581 *asm = append(*asm, 4582 uint8(op>>8), 4583 uint8(v1)<<4, 4584 uint8(i2>>8), 4585 uint8(i2), 4586 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4587 uint8(op)) 4588 } 4589 4590 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) { 4591 *asm = append(*asm, 4592 uint8(op>>8), 4593 uint8(v1)<<4, 4594 uint8(i2), 4595 uint8(i3), 4596 (uint8(m4)<<4)|rxb(v1, 0, 0, 0), 4597 uint8(op)) 4598 } 4599 4600 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) { 4601 *asm = append(*asm, 4602 uint8(op>>8), 4603 (uint8(v1)<<4)|(uint8(v3)&0xf), 4604 uint8(i2>>8), 4605 uint8(i2), 4606 (uint8(m4)<<4)|rxb(v1, v3, 0, 0), 4607 uint8(op)) 4608 } 4609 4610 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) { 4611 *asm = append(*asm, 4612 uint8(op>>8), 4613 (uint8(v1)<<4)|(uint8(v2)&0xf), 4614 uint8(v3)<<4, 4615 uint8(i4), 4616 (uint8(m5)<<4)|rxb(v1, v2, v3, 0), 4617 uint8(op)) 4618 } 4619 4620 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) { 4621 *asm = append(*asm, 4622 uint8(op>>8), 4623 (uint8(v1)<<4)|(uint8(v2)&0xf), 4624 uint8(i3>>4), 4625 (uint8(i3)<<4)|(uint8(m5)&0xf), 4626 (uint8(m4)<<4)|rxb(v1, v2, 0, 0), 4627 uint8(op)) 4628 }