github.com/muesli/go@v0.0.0-20170208044820-e410d2a81ef2/src/cmd/compile/internal/ssa/opGen.go (about) 1 // autogenerated: do not edit! 2 // generated from gen/*Ops.go 3 4 package ssa 5 6 import ( 7 "cmd/internal/obj" 8 "cmd/internal/obj/arm" 9 "cmd/internal/obj/arm64" 10 "cmd/internal/obj/mips" 11 "cmd/internal/obj/ppc64" 12 "cmd/internal/obj/s390x" 13 "cmd/internal/obj/x86" 14 ) 15 16 const ( 17 BlockInvalid BlockKind = iota 18 19 Block386EQ 20 Block386NE 21 Block386LT 22 Block386LE 23 Block386GT 24 Block386GE 25 Block386ULT 26 Block386ULE 27 Block386UGT 28 Block386UGE 29 Block386EQF 30 Block386NEF 31 Block386ORD 32 Block386NAN 33 34 BlockAMD64EQ 35 BlockAMD64NE 36 BlockAMD64LT 37 BlockAMD64LE 38 BlockAMD64GT 39 BlockAMD64GE 40 BlockAMD64ULT 41 BlockAMD64ULE 42 BlockAMD64UGT 43 BlockAMD64UGE 44 BlockAMD64EQF 45 BlockAMD64NEF 46 BlockAMD64ORD 47 BlockAMD64NAN 48 49 BlockARMEQ 50 BlockARMNE 51 BlockARMLT 52 BlockARMLE 53 BlockARMGT 54 BlockARMGE 55 BlockARMULT 56 BlockARMULE 57 BlockARMUGT 58 BlockARMUGE 59 60 BlockARM64EQ 61 BlockARM64NE 62 BlockARM64LT 63 BlockARM64LE 64 BlockARM64GT 65 BlockARM64GE 66 BlockARM64ULT 67 BlockARM64ULE 68 BlockARM64UGT 69 BlockARM64UGE 70 BlockARM64Z 71 BlockARM64NZ 72 BlockARM64ZW 73 BlockARM64NZW 74 75 BlockMIPSEQ 76 BlockMIPSNE 77 BlockMIPSLTZ 78 BlockMIPSLEZ 79 BlockMIPSGTZ 80 BlockMIPSGEZ 81 BlockMIPSFPT 82 BlockMIPSFPF 83 84 BlockMIPS64EQ 85 BlockMIPS64NE 86 BlockMIPS64LTZ 87 BlockMIPS64LEZ 88 BlockMIPS64GTZ 89 BlockMIPS64GEZ 90 BlockMIPS64FPT 91 BlockMIPS64FPF 92 93 BlockPPC64EQ 94 BlockPPC64NE 95 BlockPPC64LT 96 BlockPPC64LE 97 BlockPPC64GT 98 BlockPPC64GE 99 BlockPPC64FLT 100 BlockPPC64FLE 101 BlockPPC64FGT 102 BlockPPC64FGE 103 104 BlockS390XEQ 105 BlockS390XNE 106 BlockS390XLT 107 BlockS390XLE 108 BlockS390XGT 109 BlockS390XGE 110 BlockS390XGTF 111 BlockS390XGEF 112 113 BlockPlain 114 BlockIf 115 BlockDefer 116 BlockRet 117 BlockRetJmp 118 BlockExit 119 BlockFirst 120 ) 121 122 var blockString = [...]string{ 123 BlockInvalid: "BlockInvalid", 124 125 Block386EQ: "EQ", 126 Block386NE: "NE", 127 Block386LT: "LT", 128 Block386LE: "LE", 129 Block386GT: "GT", 130 Block386GE: "GE", 131 Block386ULT: "ULT", 132 Block386ULE: "ULE", 133 Block386UGT: "UGT", 134 Block386UGE: "UGE", 135 Block386EQF: "EQF", 136 Block386NEF: "NEF", 137 Block386ORD: "ORD", 138 Block386NAN: "NAN", 139 140 BlockAMD64EQ: "EQ", 141 BlockAMD64NE: "NE", 142 BlockAMD64LT: "LT", 143 BlockAMD64LE: "LE", 144 BlockAMD64GT: "GT", 145 BlockAMD64GE: "GE", 146 BlockAMD64ULT: "ULT", 147 BlockAMD64ULE: "ULE", 148 BlockAMD64UGT: "UGT", 149 BlockAMD64UGE: "UGE", 150 BlockAMD64EQF: "EQF", 151 BlockAMD64NEF: "NEF", 152 BlockAMD64ORD: "ORD", 153 BlockAMD64NAN: "NAN", 154 155 BlockARMEQ: "EQ", 156 BlockARMNE: "NE", 157 BlockARMLT: "LT", 158 BlockARMLE: "LE", 159 BlockARMGT: "GT", 160 BlockARMGE: "GE", 161 BlockARMULT: "ULT", 162 BlockARMULE: "ULE", 163 BlockARMUGT: "UGT", 164 BlockARMUGE: "UGE", 165 166 BlockARM64EQ: "EQ", 167 BlockARM64NE: "NE", 168 BlockARM64LT: "LT", 169 BlockARM64LE: "LE", 170 BlockARM64GT: "GT", 171 BlockARM64GE: "GE", 172 BlockARM64ULT: "ULT", 173 BlockARM64ULE: "ULE", 174 BlockARM64UGT: "UGT", 175 BlockARM64UGE: "UGE", 176 BlockARM64Z: "Z", 177 BlockARM64NZ: "NZ", 178 BlockARM64ZW: "ZW", 179 BlockARM64NZW: "NZW", 180 181 BlockMIPSEQ: "EQ", 182 BlockMIPSNE: "NE", 183 BlockMIPSLTZ: "LTZ", 184 BlockMIPSLEZ: "LEZ", 185 BlockMIPSGTZ: "GTZ", 186 BlockMIPSGEZ: "GEZ", 187 BlockMIPSFPT: "FPT", 188 BlockMIPSFPF: "FPF", 189 190 BlockMIPS64EQ: "EQ", 191 BlockMIPS64NE: "NE", 192 BlockMIPS64LTZ: "LTZ", 193 BlockMIPS64LEZ: "LEZ", 194 BlockMIPS64GTZ: "GTZ", 195 BlockMIPS64GEZ: "GEZ", 196 BlockMIPS64FPT: "FPT", 197 BlockMIPS64FPF: "FPF", 198 199 BlockPPC64EQ: "EQ", 200 BlockPPC64NE: "NE", 201 BlockPPC64LT: "LT", 202 BlockPPC64LE: "LE", 203 BlockPPC64GT: "GT", 204 BlockPPC64GE: "GE", 205 BlockPPC64FLT: "FLT", 206 BlockPPC64FLE: "FLE", 207 BlockPPC64FGT: "FGT", 208 BlockPPC64FGE: "FGE", 209 210 BlockS390XEQ: "EQ", 211 BlockS390XNE: "NE", 212 BlockS390XLT: "LT", 213 BlockS390XLE: "LE", 214 BlockS390XGT: "GT", 215 BlockS390XGE: "GE", 216 BlockS390XGTF: "GTF", 217 BlockS390XGEF: "GEF", 218 219 BlockPlain: "Plain", 220 BlockIf: "If", 221 BlockDefer: "Defer", 222 BlockRet: "Ret", 223 BlockRetJmp: "RetJmp", 224 BlockExit: "Exit", 225 BlockFirst: "First", 226 } 227 228 func (k BlockKind) String() string { return blockString[k] } 229 230 const ( 231 OpInvalid Op = iota 232 233 Op386ADDSS 234 Op386ADDSD 235 Op386SUBSS 236 Op386SUBSD 237 Op386MULSS 238 Op386MULSD 239 Op386DIVSS 240 Op386DIVSD 241 Op386MOVSSload 242 Op386MOVSDload 243 Op386MOVSSconst 244 Op386MOVSDconst 245 Op386MOVSSloadidx1 246 Op386MOVSSloadidx4 247 Op386MOVSDloadidx1 248 Op386MOVSDloadidx8 249 Op386MOVSSstore 250 Op386MOVSDstore 251 Op386MOVSSstoreidx1 252 Op386MOVSSstoreidx4 253 Op386MOVSDstoreidx1 254 Op386MOVSDstoreidx8 255 Op386ADDL 256 Op386ADDLconst 257 Op386ADDLcarry 258 Op386ADDLconstcarry 259 Op386ADCL 260 Op386ADCLconst 261 Op386SUBL 262 Op386SUBLconst 263 Op386SUBLcarry 264 Op386SUBLconstcarry 265 Op386SBBL 266 Op386SBBLconst 267 Op386MULL 268 Op386MULLconst 269 Op386HMULL 270 Op386HMULLU 271 Op386HMULW 272 Op386HMULB 273 Op386HMULWU 274 Op386HMULBU 275 Op386MULLQU 276 Op386DIVL 277 Op386DIVW 278 Op386DIVLU 279 Op386DIVWU 280 Op386MODL 281 Op386MODW 282 Op386MODLU 283 Op386MODWU 284 Op386ANDL 285 Op386ANDLconst 286 Op386ORL 287 Op386ORLconst 288 Op386XORL 289 Op386XORLconst 290 Op386CMPL 291 Op386CMPW 292 Op386CMPB 293 Op386CMPLconst 294 Op386CMPWconst 295 Op386CMPBconst 296 Op386UCOMISS 297 Op386UCOMISD 298 Op386TESTL 299 Op386TESTW 300 Op386TESTB 301 Op386TESTLconst 302 Op386TESTWconst 303 Op386TESTBconst 304 Op386SHLL 305 Op386SHLLconst 306 Op386SHRL 307 Op386SHRW 308 Op386SHRB 309 Op386SHRLconst 310 Op386SHRWconst 311 Op386SHRBconst 312 Op386SARL 313 Op386SARW 314 Op386SARB 315 Op386SARLconst 316 Op386SARWconst 317 Op386SARBconst 318 Op386ROLLconst 319 Op386ROLWconst 320 Op386ROLBconst 321 Op386NEGL 322 Op386NOTL 323 Op386BSFL 324 Op386BSFW 325 Op386BSRL 326 Op386BSRW 327 Op386BSWAPL 328 Op386SQRTSD 329 Op386SBBLcarrymask 330 Op386SETEQ 331 Op386SETNE 332 Op386SETL 333 Op386SETLE 334 Op386SETG 335 Op386SETGE 336 Op386SETB 337 Op386SETBE 338 Op386SETA 339 Op386SETAE 340 Op386SETEQF 341 Op386SETNEF 342 Op386SETORD 343 Op386SETNAN 344 Op386SETGF 345 Op386SETGEF 346 Op386MOVBLSX 347 Op386MOVBLZX 348 Op386MOVWLSX 349 Op386MOVWLZX 350 Op386MOVLconst 351 Op386CVTTSD2SL 352 Op386CVTTSS2SL 353 Op386CVTSL2SS 354 Op386CVTSL2SD 355 Op386CVTSD2SS 356 Op386CVTSS2SD 357 Op386PXOR 358 Op386LEAL 359 Op386LEAL1 360 Op386LEAL2 361 Op386LEAL4 362 Op386LEAL8 363 Op386MOVBload 364 Op386MOVBLSXload 365 Op386MOVWload 366 Op386MOVWLSXload 367 Op386MOVLload 368 Op386MOVBstore 369 Op386MOVWstore 370 Op386MOVLstore 371 Op386MOVBloadidx1 372 Op386MOVWloadidx1 373 Op386MOVWloadidx2 374 Op386MOVLloadidx1 375 Op386MOVLloadidx4 376 Op386MOVBstoreidx1 377 Op386MOVWstoreidx1 378 Op386MOVWstoreidx2 379 Op386MOVLstoreidx1 380 Op386MOVLstoreidx4 381 Op386MOVBstoreconst 382 Op386MOVWstoreconst 383 Op386MOVLstoreconst 384 Op386MOVBstoreconstidx1 385 Op386MOVWstoreconstidx1 386 Op386MOVWstoreconstidx2 387 Op386MOVLstoreconstidx1 388 Op386MOVLstoreconstidx4 389 Op386DUFFZERO 390 Op386REPSTOSL 391 Op386CALLstatic 392 Op386CALLclosure 393 Op386CALLdefer 394 Op386CALLgo 395 Op386CALLinter 396 Op386DUFFCOPY 397 Op386REPMOVSL 398 Op386InvertFlags 399 Op386LoweredGetG 400 Op386LoweredGetClosurePtr 401 Op386LoweredNilCheck 402 Op386MOVLconvert 403 Op386FlagEQ 404 Op386FlagLT_ULT 405 Op386FlagLT_UGT 406 Op386FlagGT_UGT 407 Op386FlagGT_ULT 408 Op386FCHS 409 Op386MOVSSconst1 410 Op386MOVSDconst1 411 Op386MOVSSconst2 412 Op386MOVSDconst2 413 414 OpAMD64ADDSS 415 OpAMD64ADDSD 416 OpAMD64SUBSS 417 OpAMD64SUBSD 418 OpAMD64MULSS 419 OpAMD64MULSD 420 OpAMD64DIVSS 421 OpAMD64DIVSD 422 OpAMD64MOVSSload 423 OpAMD64MOVSDload 424 OpAMD64MOVSSconst 425 OpAMD64MOVSDconst 426 OpAMD64MOVSSloadidx1 427 OpAMD64MOVSSloadidx4 428 OpAMD64MOVSDloadidx1 429 OpAMD64MOVSDloadidx8 430 OpAMD64MOVSSstore 431 OpAMD64MOVSDstore 432 OpAMD64MOVSSstoreidx1 433 OpAMD64MOVSSstoreidx4 434 OpAMD64MOVSDstoreidx1 435 OpAMD64MOVSDstoreidx8 436 OpAMD64ADDQ 437 OpAMD64ADDL 438 OpAMD64ADDQconst 439 OpAMD64ADDLconst 440 OpAMD64SUBQ 441 OpAMD64SUBL 442 OpAMD64SUBQconst 443 OpAMD64SUBLconst 444 OpAMD64MULQ 445 OpAMD64MULL 446 OpAMD64MULQconst 447 OpAMD64MULLconst 448 OpAMD64HMULQ 449 OpAMD64HMULL 450 OpAMD64HMULW 451 OpAMD64HMULB 452 OpAMD64HMULQU 453 OpAMD64HMULLU 454 OpAMD64HMULWU 455 OpAMD64HMULBU 456 OpAMD64AVGQU 457 OpAMD64DIVQ 458 OpAMD64DIVL 459 OpAMD64DIVW 460 OpAMD64DIVQU 461 OpAMD64DIVLU 462 OpAMD64DIVWU 463 OpAMD64MULQU2 464 OpAMD64DIVQU2 465 OpAMD64ANDQ 466 OpAMD64ANDL 467 OpAMD64ANDQconst 468 OpAMD64ANDLconst 469 OpAMD64ORQ 470 OpAMD64ORL 471 OpAMD64ORQconst 472 OpAMD64ORLconst 473 OpAMD64XORQ 474 OpAMD64XORL 475 OpAMD64XORQconst 476 OpAMD64XORLconst 477 OpAMD64CMPQ 478 OpAMD64CMPL 479 OpAMD64CMPW 480 OpAMD64CMPB 481 OpAMD64CMPQconst 482 OpAMD64CMPLconst 483 OpAMD64CMPWconst 484 OpAMD64CMPBconst 485 OpAMD64UCOMISS 486 OpAMD64UCOMISD 487 OpAMD64TESTQ 488 OpAMD64TESTL 489 OpAMD64TESTW 490 OpAMD64TESTB 491 OpAMD64TESTQconst 492 OpAMD64TESTLconst 493 OpAMD64TESTWconst 494 OpAMD64TESTBconst 495 OpAMD64SHLQ 496 OpAMD64SHLL 497 OpAMD64SHLQconst 498 OpAMD64SHLLconst 499 OpAMD64SHRQ 500 OpAMD64SHRL 501 OpAMD64SHRW 502 OpAMD64SHRB 503 OpAMD64SHRQconst 504 OpAMD64SHRLconst 505 OpAMD64SHRWconst 506 OpAMD64SHRBconst 507 OpAMD64SARQ 508 OpAMD64SARL 509 OpAMD64SARW 510 OpAMD64SARB 511 OpAMD64SARQconst 512 OpAMD64SARLconst 513 OpAMD64SARWconst 514 OpAMD64SARBconst 515 OpAMD64ROLQconst 516 OpAMD64ROLLconst 517 OpAMD64ROLWconst 518 OpAMD64ROLBconst 519 OpAMD64NEGQ 520 OpAMD64NEGL 521 OpAMD64NOTQ 522 OpAMD64NOTL 523 OpAMD64BSFQ 524 OpAMD64BSFL 525 OpAMD64CMOVQEQ 526 OpAMD64CMOVLEQ 527 OpAMD64BSWAPQ 528 OpAMD64BSWAPL 529 OpAMD64SQRTSD 530 OpAMD64SBBQcarrymask 531 OpAMD64SBBLcarrymask 532 OpAMD64SETEQ 533 OpAMD64SETNE 534 OpAMD64SETL 535 OpAMD64SETLE 536 OpAMD64SETG 537 OpAMD64SETGE 538 OpAMD64SETB 539 OpAMD64SETBE 540 OpAMD64SETA 541 OpAMD64SETAE 542 OpAMD64SETEQF 543 OpAMD64SETNEF 544 OpAMD64SETORD 545 OpAMD64SETNAN 546 OpAMD64SETGF 547 OpAMD64SETGEF 548 OpAMD64MOVBQSX 549 OpAMD64MOVBQZX 550 OpAMD64MOVWQSX 551 OpAMD64MOVWQZX 552 OpAMD64MOVLQSX 553 OpAMD64MOVLQZX 554 OpAMD64MOVLconst 555 OpAMD64MOVQconst 556 OpAMD64CVTTSD2SL 557 OpAMD64CVTTSD2SQ 558 OpAMD64CVTTSS2SL 559 OpAMD64CVTTSS2SQ 560 OpAMD64CVTSL2SS 561 OpAMD64CVTSL2SD 562 OpAMD64CVTSQ2SS 563 OpAMD64CVTSQ2SD 564 OpAMD64CVTSD2SS 565 OpAMD64CVTSS2SD 566 OpAMD64PXOR 567 OpAMD64LEAQ 568 OpAMD64LEAQ1 569 OpAMD64LEAQ2 570 OpAMD64LEAQ4 571 OpAMD64LEAQ8 572 OpAMD64LEAL 573 OpAMD64MOVBload 574 OpAMD64MOVBQSXload 575 OpAMD64MOVWload 576 OpAMD64MOVWQSXload 577 OpAMD64MOVLload 578 OpAMD64MOVLQSXload 579 OpAMD64MOVQload 580 OpAMD64MOVBstore 581 OpAMD64MOVWstore 582 OpAMD64MOVLstore 583 OpAMD64MOVQstore 584 OpAMD64MOVOload 585 OpAMD64MOVOstore 586 OpAMD64MOVBloadidx1 587 OpAMD64MOVWloadidx1 588 OpAMD64MOVWloadidx2 589 OpAMD64MOVLloadidx1 590 OpAMD64MOVLloadidx4 591 OpAMD64MOVQloadidx1 592 OpAMD64MOVQloadidx8 593 OpAMD64MOVBstoreidx1 594 OpAMD64MOVWstoreidx1 595 OpAMD64MOVWstoreidx2 596 OpAMD64MOVLstoreidx1 597 OpAMD64MOVLstoreidx4 598 OpAMD64MOVQstoreidx1 599 OpAMD64MOVQstoreidx8 600 OpAMD64MOVBstoreconst 601 OpAMD64MOVWstoreconst 602 OpAMD64MOVLstoreconst 603 OpAMD64MOVQstoreconst 604 OpAMD64MOVBstoreconstidx1 605 OpAMD64MOVWstoreconstidx1 606 OpAMD64MOVWstoreconstidx2 607 OpAMD64MOVLstoreconstidx1 608 OpAMD64MOVLstoreconstidx4 609 OpAMD64MOVQstoreconstidx1 610 OpAMD64MOVQstoreconstidx8 611 OpAMD64DUFFZERO 612 OpAMD64MOVOconst 613 OpAMD64REPSTOSQ 614 OpAMD64CALLstatic 615 OpAMD64CALLclosure 616 OpAMD64CALLdefer 617 OpAMD64CALLgo 618 OpAMD64CALLinter 619 OpAMD64DUFFCOPY 620 OpAMD64REPMOVSQ 621 OpAMD64InvertFlags 622 OpAMD64LoweredGetG 623 OpAMD64LoweredGetClosurePtr 624 OpAMD64LoweredNilCheck 625 OpAMD64MOVQconvert 626 OpAMD64MOVLconvert 627 OpAMD64FlagEQ 628 OpAMD64FlagLT_ULT 629 OpAMD64FlagLT_UGT 630 OpAMD64FlagGT_UGT 631 OpAMD64FlagGT_ULT 632 OpAMD64MOVLatomicload 633 OpAMD64MOVQatomicload 634 OpAMD64XCHGL 635 OpAMD64XCHGQ 636 OpAMD64XADDLlock 637 OpAMD64XADDQlock 638 OpAMD64AddTupleFirst32 639 OpAMD64AddTupleFirst64 640 OpAMD64CMPXCHGLlock 641 OpAMD64CMPXCHGQlock 642 OpAMD64ANDBlock 643 OpAMD64ORBlock 644 645 OpARMADD 646 OpARMADDconst 647 OpARMSUB 648 OpARMSUBconst 649 OpARMRSB 650 OpARMRSBconst 651 OpARMMUL 652 OpARMHMUL 653 OpARMHMULU 654 OpARMUDIVrtcall 655 OpARMADDS 656 OpARMADDSconst 657 OpARMADC 658 OpARMADCconst 659 OpARMSUBS 660 OpARMSUBSconst 661 OpARMRSBSconst 662 OpARMSBC 663 OpARMSBCconst 664 OpARMRSCconst 665 OpARMMULLU 666 OpARMMULA 667 OpARMADDF 668 OpARMADDD 669 OpARMSUBF 670 OpARMSUBD 671 OpARMMULF 672 OpARMMULD 673 OpARMDIVF 674 OpARMDIVD 675 OpARMAND 676 OpARMANDconst 677 OpARMOR 678 OpARMORconst 679 OpARMXOR 680 OpARMXORconst 681 OpARMBIC 682 OpARMBICconst 683 OpARMMVN 684 OpARMNEGF 685 OpARMNEGD 686 OpARMSQRTD 687 OpARMCLZ 688 OpARMSLL 689 OpARMSLLconst 690 OpARMSRL 691 OpARMSRLconst 692 OpARMSRA 693 OpARMSRAconst 694 OpARMSRRconst 695 OpARMADDshiftLL 696 OpARMADDshiftRL 697 OpARMADDshiftRA 698 OpARMSUBshiftLL 699 OpARMSUBshiftRL 700 OpARMSUBshiftRA 701 OpARMRSBshiftLL 702 OpARMRSBshiftRL 703 OpARMRSBshiftRA 704 OpARMANDshiftLL 705 OpARMANDshiftRL 706 OpARMANDshiftRA 707 OpARMORshiftLL 708 OpARMORshiftRL 709 OpARMORshiftRA 710 OpARMXORshiftLL 711 OpARMXORshiftRL 712 OpARMXORshiftRA 713 OpARMXORshiftRR 714 OpARMBICshiftLL 715 OpARMBICshiftRL 716 OpARMBICshiftRA 717 OpARMMVNshiftLL 718 OpARMMVNshiftRL 719 OpARMMVNshiftRA 720 OpARMADCshiftLL 721 OpARMADCshiftRL 722 OpARMADCshiftRA 723 OpARMSBCshiftLL 724 OpARMSBCshiftRL 725 OpARMSBCshiftRA 726 OpARMRSCshiftLL 727 OpARMRSCshiftRL 728 OpARMRSCshiftRA 729 OpARMADDSshiftLL 730 OpARMADDSshiftRL 731 OpARMADDSshiftRA 732 OpARMSUBSshiftLL 733 OpARMSUBSshiftRL 734 OpARMSUBSshiftRA 735 OpARMRSBSshiftLL 736 OpARMRSBSshiftRL 737 OpARMRSBSshiftRA 738 OpARMADDshiftLLreg 739 OpARMADDshiftRLreg 740 OpARMADDshiftRAreg 741 OpARMSUBshiftLLreg 742 OpARMSUBshiftRLreg 743 OpARMSUBshiftRAreg 744 OpARMRSBshiftLLreg 745 OpARMRSBshiftRLreg 746 OpARMRSBshiftRAreg 747 OpARMANDshiftLLreg 748 OpARMANDshiftRLreg 749 OpARMANDshiftRAreg 750 OpARMORshiftLLreg 751 OpARMORshiftRLreg 752 OpARMORshiftRAreg 753 OpARMXORshiftLLreg 754 OpARMXORshiftRLreg 755 OpARMXORshiftRAreg 756 OpARMBICshiftLLreg 757 OpARMBICshiftRLreg 758 OpARMBICshiftRAreg 759 OpARMMVNshiftLLreg 760 OpARMMVNshiftRLreg 761 OpARMMVNshiftRAreg 762 OpARMADCshiftLLreg 763 OpARMADCshiftRLreg 764 OpARMADCshiftRAreg 765 OpARMSBCshiftLLreg 766 OpARMSBCshiftRLreg 767 OpARMSBCshiftRAreg 768 OpARMRSCshiftLLreg 769 OpARMRSCshiftRLreg 770 OpARMRSCshiftRAreg 771 OpARMADDSshiftLLreg 772 OpARMADDSshiftRLreg 773 OpARMADDSshiftRAreg 774 OpARMSUBSshiftLLreg 775 OpARMSUBSshiftRLreg 776 OpARMSUBSshiftRAreg 777 OpARMRSBSshiftLLreg 778 OpARMRSBSshiftRLreg 779 OpARMRSBSshiftRAreg 780 OpARMCMP 781 OpARMCMPconst 782 OpARMCMN 783 OpARMCMNconst 784 OpARMTST 785 OpARMTSTconst 786 OpARMTEQ 787 OpARMTEQconst 788 OpARMCMPF 789 OpARMCMPD 790 OpARMCMPshiftLL 791 OpARMCMPshiftRL 792 OpARMCMPshiftRA 793 OpARMCMPshiftLLreg 794 OpARMCMPshiftRLreg 795 OpARMCMPshiftRAreg 796 OpARMCMPF0 797 OpARMCMPD0 798 OpARMMOVWconst 799 OpARMMOVFconst 800 OpARMMOVDconst 801 OpARMMOVWaddr 802 OpARMMOVBload 803 OpARMMOVBUload 804 OpARMMOVHload 805 OpARMMOVHUload 806 OpARMMOVWload 807 OpARMMOVFload 808 OpARMMOVDload 809 OpARMMOVBstore 810 OpARMMOVHstore 811 OpARMMOVWstore 812 OpARMMOVFstore 813 OpARMMOVDstore 814 OpARMMOVWloadidx 815 OpARMMOVWloadshiftLL 816 OpARMMOVWloadshiftRL 817 OpARMMOVWloadshiftRA 818 OpARMMOVWstoreidx 819 OpARMMOVWstoreshiftLL 820 OpARMMOVWstoreshiftRL 821 OpARMMOVWstoreshiftRA 822 OpARMMOVBreg 823 OpARMMOVBUreg 824 OpARMMOVHreg 825 OpARMMOVHUreg 826 OpARMMOVWreg 827 OpARMMOVWnop 828 OpARMMOVWF 829 OpARMMOVWD 830 OpARMMOVWUF 831 OpARMMOVWUD 832 OpARMMOVFW 833 OpARMMOVDW 834 OpARMMOVFWU 835 OpARMMOVDWU 836 OpARMMOVFD 837 OpARMMOVDF 838 OpARMCMOVWHSconst 839 OpARMCMOVWLSconst 840 OpARMSRAcond 841 OpARMCALLstatic 842 OpARMCALLclosure 843 OpARMCALLdefer 844 OpARMCALLgo 845 OpARMCALLinter 846 OpARMLoweredNilCheck 847 OpARMEqual 848 OpARMNotEqual 849 OpARMLessThan 850 OpARMLessEqual 851 OpARMGreaterThan 852 OpARMGreaterEqual 853 OpARMLessThanU 854 OpARMLessEqualU 855 OpARMGreaterThanU 856 OpARMGreaterEqualU 857 OpARMDUFFZERO 858 OpARMDUFFCOPY 859 OpARMLoweredZero 860 OpARMLoweredMove 861 OpARMLoweredGetClosurePtr 862 OpARMMOVWconvert 863 OpARMFlagEQ 864 OpARMFlagLT_ULT 865 OpARMFlagLT_UGT 866 OpARMFlagGT_UGT 867 OpARMFlagGT_ULT 868 OpARMInvertFlags 869 870 OpARM64ADD 871 OpARM64ADDconst 872 OpARM64SUB 873 OpARM64SUBconst 874 OpARM64MUL 875 OpARM64MULW 876 OpARM64MULH 877 OpARM64UMULH 878 OpARM64MULL 879 OpARM64UMULL 880 OpARM64DIV 881 OpARM64UDIV 882 OpARM64DIVW 883 OpARM64UDIVW 884 OpARM64MOD 885 OpARM64UMOD 886 OpARM64MODW 887 OpARM64UMODW 888 OpARM64FADDS 889 OpARM64FADDD 890 OpARM64FSUBS 891 OpARM64FSUBD 892 OpARM64FMULS 893 OpARM64FMULD 894 OpARM64FDIVS 895 OpARM64FDIVD 896 OpARM64AND 897 OpARM64ANDconst 898 OpARM64OR 899 OpARM64ORconst 900 OpARM64XOR 901 OpARM64XORconst 902 OpARM64BIC 903 OpARM64BICconst 904 OpARM64MVN 905 OpARM64NEG 906 OpARM64FNEGS 907 OpARM64FNEGD 908 OpARM64FSQRTD 909 OpARM64REV 910 OpARM64REVW 911 OpARM64REV16W 912 OpARM64RBIT 913 OpARM64RBITW 914 OpARM64CLZ 915 OpARM64CLZW 916 OpARM64SLL 917 OpARM64SLLconst 918 OpARM64SRL 919 OpARM64SRLconst 920 OpARM64SRA 921 OpARM64SRAconst 922 OpARM64RORconst 923 OpARM64RORWconst 924 OpARM64CMP 925 OpARM64CMPconst 926 OpARM64CMPW 927 OpARM64CMPWconst 928 OpARM64CMN 929 OpARM64CMNconst 930 OpARM64CMNW 931 OpARM64CMNWconst 932 OpARM64FCMPS 933 OpARM64FCMPD 934 OpARM64ADDshiftLL 935 OpARM64ADDshiftRL 936 OpARM64ADDshiftRA 937 OpARM64SUBshiftLL 938 OpARM64SUBshiftRL 939 OpARM64SUBshiftRA 940 OpARM64ANDshiftLL 941 OpARM64ANDshiftRL 942 OpARM64ANDshiftRA 943 OpARM64ORshiftLL 944 OpARM64ORshiftRL 945 OpARM64ORshiftRA 946 OpARM64XORshiftLL 947 OpARM64XORshiftRL 948 OpARM64XORshiftRA 949 OpARM64BICshiftLL 950 OpARM64BICshiftRL 951 OpARM64BICshiftRA 952 OpARM64CMPshiftLL 953 OpARM64CMPshiftRL 954 OpARM64CMPshiftRA 955 OpARM64MOVDconst 956 OpARM64FMOVSconst 957 OpARM64FMOVDconst 958 OpARM64MOVDaddr 959 OpARM64MOVBload 960 OpARM64MOVBUload 961 OpARM64MOVHload 962 OpARM64MOVHUload 963 OpARM64MOVWload 964 OpARM64MOVWUload 965 OpARM64MOVDload 966 OpARM64FMOVSload 967 OpARM64FMOVDload 968 OpARM64MOVBstore 969 OpARM64MOVHstore 970 OpARM64MOVWstore 971 OpARM64MOVDstore 972 OpARM64FMOVSstore 973 OpARM64FMOVDstore 974 OpARM64MOVBstorezero 975 OpARM64MOVHstorezero 976 OpARM64MOVWstorezero 977 OpARM64MOVDstorezero 978 OpARM64MOVBreg 979 OpARM64MOVBUreg 980 OpARM64MOVHreg 981 OpARM64MOVHUreg 982 OpARM64MOVWreg 983 OpARM64MOVWUreg 984 OpARM64MOVDreg 985 OpARM64MOVDnop 986 OpARM64SCVTFWS 987 OpARM64SCVTFWD 988 OpARM64UCVTFWS 989 OpARM64UCVTFWD 990 OpARM64SCVTFS 991 OpARM64SCVTFD 992 OpARM64UCVTFS 993 OpARM64UCVTFD 994 OpARM64FCVTZSSW 995 OpARM64FCVTZSDW 996 OpARM64FCVTZUSW 997 OpARM64FCVTZUDW 998 OpARM64FCVTZSS 999 OpARM64FCVTZSD 1000 OpARM64FCVTZUS 1001 OpARM64FCVTZUD 1002 OpARM64FCVTSD 1003 OpARM64FCVTDS 1004 OpARM64CSELULT 1005 OpARM64CSELULT0 1006 OpARM64CALLstatic 1007 OpARM64CALLclosure 1008 OpARM64CALLdefer 1009 OpARM64CALLgo 1010 OpARM64CALLinter 1011 OpARM64LoweredNilCheck 1012 OpARM64Equal 1013 OpARM64NotEqual 1014 OpARM64LessThan 1015 OpARM64LessEqual 1016 OpARM64GreaterThan 1017 OpARM64GreaterEqual 1018 OpARM64LessThanU 1019 OpARM64LessEqualU 1020 OpARM64GreaterThanU 1021 OpARM64GreaterEqualU 1022 OpARM64DUFFZERO 1023 OpARM64LoweredZero 1024 OpARM64DUFFCOPY 1025 OpARM64LoweredMove 1026 OpARM64LoweredGetClosurePtr 1027 OpARM64MOVDconvert 1028 OpARM64FlagEQ 1029 OpARM64FlagLT_ULT 1030 OpARM64FlagLT_UGT 1031 OpARM64FlagGT_UGT 1032 OpARM64FlagGT_ULT 1033 OpARM64InvertFlags 1034 OpARM64LDAR 1035 OpARM64LDARW 1036 OpARM64STLR 1037 OpARM64STLRW 1038 OpARM64LoweredAtomicExchange64 1039 OpARM64LoweredAtomicExchange32 1040 OpARM64LoweredAtomicAdd64 1041 OpARM64LoweredAtomicAdd32 1042 OpARM64LoweredAtomicCas64 1043 OpARM64LoweredAtomicCas32 1044 OpARM64LoweredAtomicAnd8 1045 OpARM64LoweredAtomicOr8 1046 1047 OpMIPSADD 1048 OpMIPSADDconst 1049 OpMIPSSUB 1050 OpMIPSSUBconst 1051 OpMIPSMUL 1052 OpMIPSMULT 1053 OpMIPSMULTU 1054 OpMIPSDIV 1055 OpMIPSDIVU 1056 OpMIPSADDF 1057 OpMIPSADDD 1058 OpMIPSSUBF 1059 OpMIPSSUBD 1060 OpMIPSMULF 1061 OpMIPSMULD 1062 OpMIPSDIVF 1063 OpMIPSDIVD 1064 OpMIPSAND 1065 OpMIPSANDconst 1066 OpMIPSOR 1067 OpMIPSORconst 1068 OpMIPSXOR 1069 OpMIPSXORconst 1070 OpMIPSNOR 1071 OpMIPSNORconst 1072 OpMIPSNEG 1073 OpMIPSNEGF 1074 OpMIPSNEGD 1075 OpMIPSSQRTD 1076 OpMIPSSLL 1077 OpMIPSSLLconst 1078 OpMIPSSRL 1079 OpMIPSSRLconst 1080 OpMIPSSRA 1081 OpMIPSSRAconst 1082 OpMIPSCLZ 1083 OpMIPSSGT 1084 OpMIPSSGTconst 1085 OpMIPSSGTzero 1086 OpMIPSSGTU 1087 OpMIPSSGTUconst 1088 OpMIPSSGTUzero 1089 OpMIPSCMPEQF 1090 OpMIPSCMPEQD 1091 OpMIPSCMPGEF 1092 OpMIPSCMPGED 1093 OpMIPSCMPGTF 1094 OpMIPSCMPGTD 1095 OpMIPSMOVWconst 1096 OpMIPSMOVFconst 1097 OpMIPSMOVDconst 1098 OpMIPSMOVWaddr 1099 OpMIPSMOVBload 1100 OpMIPSMOVBUload 1101 OpMIPSMOVHload 1102 OpMIPSMOVHUload 1103 OpMIPSMOVWload 1104 OpMIPSMOVFload 1105 OpMIPSMOVDload 1106 OpMIPSMOVBstore 1107 OpMIPSMOVHstore 1108 OpMIPSMOVWstore 1109 OpMIPSMOVFstore 1110 OpMIPSMOVDstore 1111 OpMIPSMOVBstorezero 1112 OpMIPSMOVHstorezero 1113 OpMIPSMOVWstorezero 1114 OpMIPSMOVBreg 1115 OpMIPSMOVBUreg 1116 OpMIPSMOVHreg 1117 OpMIPSMOVHUreg 1118 OpMIPSMOVWreg 1119 OpMIPSMOVWnop 1120 OpMIPSCMOVZ 1121 OpMIPSCMOVZzero 1122 OpMIPSMOVWF 1123 OpMIPSMOVWD 1124 OpMIPSTRUNCFW 1125 OpMIPSTRUNCDW 1126 OpMIPSMOVFD 1127 OpMIPSMOVDF 1128 OpMIPSCALLstatic 1129 OpMIPSCALLclosure 1130 OpMIPSCALLdefer 1131 OpMIPSCALLgo 1132 OpMIPSCALLinter 1133 OpMIPSLoweredAtomicLoad 1134 OpMIPSLoweredAtomicStore 1135 OpMIPSLoweredAtomicStorezero 1136 OpMIPSLoweredAtomicExchange 1137 OpMIPSLoweredAtomicAdd 1138 OpMIPSLoweredAtomicAddconst 1139 OpMIPSLoweredAtomicCas 1140 OpMIPSLoweredAtomicAnd 1141 OpMIPSLoweredAtomicOr 1142 OpMIPSLoweredZero 1143 OpMIPSLoweredMove 1144 OpMIPSLoweredNilCheck 1145 OpMIPSFPFlagTrue 1146 OpMIPSFPFlagFalse 1147 OpMIPSLoweredGetClosurePtr 1148 OpMIPSMOVWconvert 1149 1150 OpMIPS64ADDV 1151 OpMIPS64ADDVconst 1152 OpMIPS64SUBV 1153 OpMIPS64SUBVconst 1154 OpMIPS64MULV 1155 OpMIPS64MULVU 1156 OpMIPS64DIVV 1157 OpMIPS64DIVVU 1158 OpMIPS64ADDF 1159 OpMIPS64ADDD 1160 OpMIPS64SUBF 1161 OpMIPS64SUBD 1162 OpMIPS64MULF 1163 OpMIPS64MULD 1164 OpMIPS64DIVF 1165 OpMIPS64DIVD 1166 OpMIPS64AND 1167 OpMIPS64ANDconst 1168 OpMIPS64OR 1169 OpMIPS64ORconst 1170 OpMIPS64XOR 1171 OpMIPS64XORconst 1172 OpMIPS64NOR 1173 OpMIPS64NORconst 1174 OpMIPS64NEGV 1175 OpMIPS64NEGF 1176 OpMIPS64NEGD 1177 OpMIPS64SLLV 1178 OpMIPS64SLLVconst 1179 OpMIPS64SRLV 1180 OpMIPS64SRLVconst 1181 OpMIPS64SRAV 1182 OpMIPS64SRAVconst 1183 OpMIPS64SGT 1184 OpMIPS64SGTconst 1185 OpMIPS64SGTU 1186 OpMIPS64SGTUconst 1187 OpMIPS64CMPEQF 1188 OpMIPS64CMPEQD 1189 OpMIPS64CMPGEF 1190 OpMIPS64CMPGED 1191 OpMIPS64CMPGTF 1192 OpMIPS64CMPGTD 1193 OpMIPS64MOVVconst 1194 OpMIPS64MOVFconst 1195 OpMIPS64MOVDconst 1196 OpMIPS64MOVVaddr 1197 OpMIPS64MOVBload 1198 OpMIPS64MOVBUload 1199 OpMIPS64MOVHload 1200 OpMIPS64MOVHUload 1201 OpMIPS64MOVWload 1202 OpMIPS64MOVWUload 1203 OpMIPS64MOVVload 1204 OpMIPS64MOVFload 1205 OpMIPS64MOVDload 1206 OpMIPS64MOVBstore 1207 OpMIPS64MOVHstore 1208 OpMIPS64MOVWstore 1209 OpMIPS64MOVVstore 1210 OpMIPS64MOVFstore 1211 OpMIPS64MOVDstore 1212 OpMIPS64MOVBstorezero 1213 OpMIPS64MOVHstorezero 1214 OpMIPS64MOVWstorezero 1215 OpMIPS64MOVVstorezero 1216 OpMIPS64MOVBreg 1217 OpMIPS64MOVBUreg 1218 OpMIPS64MOVHreg 1219 OpMIPS64MOVHUreg 1220 OpMIPS64MOVWreg 1221 OpMIPS64MOVWUreg 1222 OpMIPS64MOVVreg 1223 OpMIPS64MOVVnop 1224 OpMIPS64MOVWF 1225 OpMIPS64MOVWD 1226 OpMIPS64MOVVF 1227 OpMIPS64MOVVD 1228 OpMIPS64TRUNCFW 1229 OpMIPS64TRUNCDW 1230 OpMIPS64TRUNCFV 1231 OpMIPS64TRUNCDV 1232 OpMIPS64MOVFD 1233 OpMIPS64MOVDF 1234 OpMIPS64CALLstatic 1235 OpMIPS64CALLclosure 1236 OpMIPS64CALLdefer 1237 OpMIPS64CALLgo 1238 OpMIPS64CALLinter 1239 OpMIPS64DUFFZERO 1240 OpMIPS64LoweredZero 1241 OpMIPS64LoweredMove 1242 OpMIPS64LoweredNilCheck 1243 OpMIPS64FPFlagTrue 1244 OpMIPS64FPFlagFalse 1245 OpMIPS64LoweredGetClosurePtr 1246 OpMIPS64MOVVconvert 1247 1248 OpPPC64ADD 1249 OpPPC64ADDconst 1250 OpPPC64FADD 1251 OpPPC64FADDS 1252 OpPPC64SUB 1253 OpPPC64FSUB 1254 OpPPC64FSUBS 1255 OpPPC64MULLD 1256 OpPPC64MULLW 1257 OpPPC64MULHD 1258 OpPPC64MULHW 1259 OpPPC64MULHDU 1260 OpPPC64MULHWU 1261 OpPPC64FMUL 1262 OpPPC64FMULS 1263 OpPPC64SRAD 1264 OpPPC64SRAW 1265 OpPPC64SRD 1266 OpPPC64SRW 1267 OpPPC64SLD 1268 OpPPC64SLW 1269 OpPPC64ADDconstForCarry 1270 OpPPC64MaskIfNotCarry 1271 OpPPC64SRADconst 1272 OpPPC64SRAWconst 1273 OpPPC64SRDconst 1274 OpPPC64SRWconst 1275 OpPPC64SLDconst 1276 OpPPC64SLWconst 1277 OpPPC64FDIV 1278 OpPPC64FDIVS 1279 OpPPC64DIVD 1280 OpPPC64DIVW 1281 OpPPC64DIVDU 1282 OpPPC64DIVWU 1283 OpPPC64FCTIDZ 1284 OpPPC64FCTIWZ 1285 OpPPC64FCFID 1286 OpPPC64FRSP 1287 OpPPC64Xf2i64 1288 OpPPC64Xi2f64 1289 OpPPC64AND 1290 OpPPC64ANDN 1291 OpPPC64OR 1292 OpPPC64ORN 1293 OpPPC64XOR 1294 OpPPC64EQV 1295 OpPPC64NEG 1296 OpPPC64FNEG 1297 OpPPC64FSQRT 1298 OpPPC64FSQRTS 1299 OpPPC64ORconst 1300 OpPPC64XORconst 1301 OpPPC64ANDconst 1302 OpPPC64ANDCCconst 1303 OpPPC64MOVBreg 1304 OpPPC64MOVBZreg 1305 OpPPC64MOVHreg 1306 OpPPC64MOVHZreg 1307 OpPPC64MOVWreg 1308 OpPPC64MOVWZreg 1309 OpPPC64MOVBZload 1310 OpPPC64MOVHload 1311 OpPPC64MOVHZload 1312 OpPPC64MOVWload 1313 OpPPC64MOVWZload 1314 OpPPC64MOVDload 1315 OpPPC64FMOVDload 1316 OpPPC64FMOVSload 1317 OpPPC64MOVBstore 1318 OpPPC64MOVHstore 1319 OpPPC64MOVWstore 1320 OpPPC64MOVDstore 1321 OpPPC64FMOVDstore 1322 OpPPC64FMOVSstore 1323 OpPPC64MOVBstorezero 1324 OpPPC64MOVHstorezero 1325 OpPPC64MOVWstorezero 1326 OpPPC64MOVDstorezero 1327 OpPPC64MOVDaddr 1328 OpPPC64MOVDconst 1329 OpPPC64FMOVDconst 1330 OpPPC64FMOVSconst 1331 OpPPC64FCMPU 1332 OpPPC64CMP 1333 OpPPC64CMPU 1334 OpPPC64CMPW 1335 OpPPC64CMPWU 1336 OpPPC64CMPconst 1337 OpPPC64CMPUconst 1338 OpPPC64CMPWconst 1339 OpPPC64CMPWUconst 1340 OpPPC64Equal 1341 OpPPC64NotEqual 1342 OpPPC64LessThan 1343 OpPPC64FLessThan 1344 OpPPC64LessEqual 1345 OpPPC64FLessEqual 1346 OpPPC64GreaterThan 1347 OpPPC64FGreaterThan 1348 OpPPC64GreaterEqual 1349 OpPPC64FGreaterEqual 1350 OpPPC64LoweredGetClosurePtr 1351 OpPPC64LoweredNilCheck 1352 OpPPC64MOVDconvert 1353 OpPPC64CALLstatic 1354 OpPPC64CALLclosure 1355 OpPPC64CALLdefer 1356 OpPPC64CALLgo 1357 OpPPC64CALLinter 1358 OpPPC64LoweredZero 1359 OpPPC64LoweredMove 1360 OpPPC64InvertFlags 1361 OpPPC64FlagEQ 1362 OpPPC64FlagLT 1363 OpPPC64FlagGT 1364 1365 OpS390XFADDS 1366 OpS390XFADD 1367 OpS390XFSUBS 1368 OpS390XFSUB 1369 OpS390XFMULS 1370 OpS390XFMUL 1371 OpS390XFDIVS 1372 OpS390XFDIV 1373 OpS390XFNEGS 1374 OpS390XFNEG 1375 OpS390XFMOVSload 1376 OpS390XFMOVDload 1377 OpS390XFMOVSconst 1378 OpS390XFMOVDconst 1379 OpS390XFMOVSloadidx 1380 OpS390XFMOVDloadidx 1381 OpS390XFMOVSstore 1382 OpS390XFMOVDstore 1383 OpS390XFMOVSstoreidx 1384 OpS390XFMOVDstoreidx 1385 OpS390XADD 1386 OpS390XADDW 1387 OpS390XADDconst 1388 OpS390XADDWconst 1389 OpS390XADDload 1390 OpS390XADDWload 1391 OpS390XSUB 1392 OpS390XSUBW 1393 OpS390XSUBconst 1394 OpS390XSUBWconst 1395 OpS390XSUBload 1396 OpS390XSUBWload 1397 OpS390XMULLD 1398 OpS390XMULLW 1399 OpS390XMULLDconst 1400 OpS390XMULLWconst 1401 OpS390XMULLDload 1402 OpS390XMULLWload 1403 OpS390XMULHD 1404 OpS390XMULHDU 1405 OpS390XDIVD 1406 OpS390XDIVW 1407 OpS390XDIVDU 1408 OpS390XDIVWU 1409 OpS390XMODD 1410 OpS390XMODW 1411 OpS390XMODDU 1412 OpS390XMODWU 1413 OpS390XAND 1414 OpS390XANDW 1415 OpS390XANDconst 1416 OpS390XANDWconst 1417 OpS390XANDload 1418 OpS390XANDWload 1419 OpS390XOR 1420 OpS390XORW 1421 OpS390XORconst 1422 OpS390XORWconst 1423 OpS390XORload 1424 OpS390XORWload 1425 OpS390XXOR 1426 OpS390XXORW 1427 OpS390XXORconst 1428 OpS390XXORWconst 1429 OpS390XXORload 1430 OpS390XXORWload 1431 OpS390XCMP 1432 OpS390XCMPW 1433 OpS390XCMPU 1434 OpS390XCMPWU 1435 OpS390XCMPconst 1436 OpS390XCMPWconst 1437 OpS390XCMPUconst 1438 OpS390XCMPWUconst 1439 OpS390XFCMPS 1440 OpS390XFCMP 1441 OpS390XSLD 1442 OpS390XSLW 1443 OpS390XSLDconst 1444 OpS390XSLWconst 1445 OpS390XSRD 1446 OpS390XSRW 1447 OpS390XSRDconst 1448 OpS390XSRWconst 1449 OpS390XSRAD 1450 OpS390XSRAW 1451 OpS390XSRADconst 1452 OpS390XSRAWconst 1453 OpS390XRLLGconst 1454 OpS390XRLLconst 1455 OpS390XNEG 1456 OpS390XNEGW 1457 OpS390XNOT 1458 OpS390XNOTW 1459 OpS390XFSQRT 1460 OpS390XSUBEcarrymask 1461 OpS390XSUBEWcarrymask 1462 OpS390XMOVDEQ 1463 OpS390XMOVDNE 1464 OpS390XMOVDLT 1465 OpS390XMOVDLE 1466 OpS390XMOVDGT 1467 OpS390XMOVDGE 1468 OpS390XMOVDGTnoinv 1469 OpS390XMOVDGEnoinv 1470 OpS390XMOVBreg 1471 OpS390XMOVBZreg 1472 OpS390XMOVHreg 1473 OpS390XMOVHZreg 1474 OpS390XMOVWreg 1475 OpS390XMOVWZreg 1476 OpS390XMOVDreg 1477 OpS390XMOVDnop 1478 OpS390XMOVDconst 1479 OpS390XCFDBRA 1480 OpS390XCGDBRA 1481 OpS390XCFEBRA 1482 OpS390XCGEBRA 1483 OpS390XCEFBRA 1484 OpS390XCDFBRA 1485 OpS390XCEGBRA 1486 OpS390XCDGBRA 1487 OpS390XLEDBR 1488 OpS390XLDEBR 1489 OpS390XMOVDaddr 1490 OpS390XMOVDaddridx 1491 OpS390XMOVBZload 1492 OpS390XMOVBload 1493 OpS390XMOVHZload 1494 OpS390XMOVHload 1495 OpS390XMOVWZload 1496 OpS390XMOVWload 1497 OpS390XMOVDload 1498 OpS390XMOVWBR 1499 OpS390XMOVDBR 1500 OpS390XMOVHBRload 1501 OpS390XMOVWBRload 1502 OpS390XMOVDBRload 1503 OpS390XMOVBstore 1504 OpS390XMOVHstore 1505 OpS390XMOVWstore 1506 OpS390XMOVDstore 1507 OpS390XMOVHBRstore 1508 OpS390XMOVWBRstore 1509 OpS390XMOVDBRstore 1510 OpS390XMVC 1511 OpS390XMOVBZloadidx 1512 OpS390XMOVHZloadidx 1513 OpS390XMOVWZloadidx 1514 OpS390XMOVDloadidx 1515 OpS390XMOVHBRloadidx 1516 OpS390XMOVWBRloadidx 1517 OpS390XMOVDBRloadidx 1518 OpS390XMOVBstoreidx 1519 OpS390XMOVHstoreidx 1520 OpS390XMOVWstoreidx 1521 OpS390XMOVDstoreidx 1522 OpS390XMOVHBRstoreidx 1523 OpS390XMOVWBRstoreidx 1524 OpS390XMOVDBRstoreidx 1525 OpS390XMOVBstoreconst 1526 OpS390XMOVHstoreconst 1527 OpS390XMOVWstoreconst 1528 OpS390XMOVDstoreconst 1529 OpS390XCLEAR 1530 OpS390XCALLstatic 1531 OpS390XCALLclosure 1532 OpS390XCALLdefer 1533 OpS390XCALLgo 1534 OpS390XCALLinter 1535 OpS390XInvertFlags 1536 OpS390XLoweredGetG 1537 OpS390XLoweredGetClosurePtr 1538 OpS390XLoweredNilCheck 1539 OpS390XMOVDconvert 1540 OpS390XFlagEQ 1541 OpS390XFlagLT 1542 OpS390XFlagGT 1543 OpS390XMOVWZatomicload 1544 OpS390XMOVDatomicload 1545 OpS390XMOVWatomicstore 1546 OpS390XMOVDatomicstore 1547 OpS390XLAA 1548 OpS390XLAAG 1549 OpS390XAddTupleFirst32 1550 OpS390XAddTupleFirst64 1551 OpS390XLoweredAtomicCas32 1552 OpS390XLoweredAtomicCas64 1553 OpS390XLoweredAtomicExchange32 1554 OpS390XLoweredAtomicExchange64 1555 OpS390XFLOGR 1556 OpS390XSTMG2 1557 OpS390XSTMG3 1558 OpS390XSTMG4 1559 OpS390XSTM2 1560 OpS390XSTM3 1561 OpS390XSTM4 1562 OpS390XLoweredMove 1563 OpS390XLoweredZero 1564 1565 OpAdd8 1566 OpAdd16 1567 OpAdd32 1568 OpAdd64 1569 OpAddPtr 1570 OpAdd32F 1571 OpAdd64F 1572 OpSub8 1573 OpSub16 1574 OpSub32 1575 OpSub64 1576 OpSubPtr 1577 OpSub32F 1578 OpSub64F 1579 OpMul8 1580 OpMul16 1581 OpMul32 1582 OpMul64 1583 OpMul32F 1584 OpMul64F 1585 OpDiv32F 1586 OpDiv64F 1587 OpHmul8 1588 OpHmul8u 1589 OpHmul16 1590 OpHmul16u 1591 OpHmul32 1592 OpHmul32u 1593 OpHmul64 1594 OpHmul64u 1595 OpMul32uhilo 1596 OpMul64uhilo 1597 OpAvg64u 1598 OpDiv8 1599 OpDiv8u 1600 OpDiv16 1601 OpDiv16u 1602 OpDiv32 1603 OpDiv32u 1604 OpDiv64 1605 OpDiv64u 1606 OpDiv128u 1607 OpMod8 1608 OpMod8u 1609 OpMod16 1610 OpMod16u 1611 OpMod32 1612 OpMod32u 1613 OpMod64 1614 OpMod64u 1615 OpAnd8 1616 OpAnd16 1617 OpAnd32 1618 OpAnd64 1619 OpOr8 1620 OpOr16 1621 OpOr32 1622 OpOr64 1623 OpXor8 1624 OpXor16 1625 OpXor32 1626 OpXor64 1627 OpLsh8x8 1628 OpLsh8x16 1629 OpLsh8x32 1630 OpLsh8x64 1631 OpLsh16x8 1632 OpLsh16x16 1633 OpLsh16x32 1634 OpLsh16x64 1635 OpLsh32x8 1636 OpLsh32x16 1637 OpLsh32x32 1638 OpLsh32x64 1639 OpLsh64x8 1640 OpLsh64x16 1641 OpLsh64x32 1642 OpLsh64x64 1643 OpRsh8x8 1644 OpRsh8x16 1645 OpRsh8x32 1646 OpRsh8x64 1647 OpRsh16x8 1648 OpRsh16x16 1649 OpRsh16x32 1650 OpRsh16x64 1651 OpRsh32x8 1652 OpRsh32x16 1653 OpRsh32x32 1654 OpRsh32x64 1655 OpRsh64x8 1656 OpRsh64x16 1657 OpRsh64x32 1658 OpRsh64x64 1659 OpRsh8Ux8 1660 OpRsh8Ux16 1661 OpRsh8Ux32 1662 OpRsh8Ux64 1663 OpRsh16Ux8 1664 OpRsh16Ux16 1665 OpRsh16Ux32 1666 OpRsh16Ux64 1667 OpRsh32Ux8 1668 OpRsh32Ux16 1669 OpRsh32Ux32 1670 OpRsh32Ux64 1671 OpRsh64Ux8 1672 OpRsh64Ux16 1673 OpRsh64Ux32 1674 OpRsh64Ux64 1675 OpEq8 1676 OpEq16 1677 OpEq32 1678 OpEq64 1679 OpEqPtr 1680 OpEqInter 1681 OpEqSlice 1682 OpEq32F 1683 OpEq64F 1684 OpNeq8 1685 OpNeq16 1686 OpNeq32 1687 OpNeq64 1688 OpNeqPtr 1689 OpNeqInter 1690 OpNeqSlice 1691 OpNeq32F 1692 OpNeq64F 1693 OpLess8 1694 OpLess8U 1695 OpLess16 1696 OpLess16U 1697 OpLess32 1698 OpLess32U 1699 OpLess64 1700 OpLess64U 1701 OpLess32F 1702 OpLess64F 1703 OpLeq8 1704 OpLeq8U 1705 OpLeq16 1706 OpLeq16U 1707 OpLeq32 1708 OpLeq32U 1709 OpLeq64 1710 OpLeq64U 1711 OpLeq32F 1712 OpLeq64F 1713 OpGreater8 1714 OpGreater8U 1715 OpGreater16 1716 OpGreater16U 1717 OpGreater32 1718 OpGreater32U 1719 OpGreater64 1720 OpGreater64U 1721 OpGreater32F 1722 OpGreater64F 1723 OpGeq8 1724 OpGeq8U 1725 OpGeq16 1726 OpGeq16U 1727 OpGeq32 1728 OpGeq32U 1729 OpGeq64 1730 OpGeq64U 1731 OpGeq32F 1732 OpGeq64F 1733 OpAndB 1734 OpOrB 1735 OpEqB 1736 OpNeqB 1737 OpNot 1738 OpNeg8 1739 OpNeg16 1740 OpNeg32 1741 OpNeg64 1742 OpNeg32F 1743 OpNeg64F 1744 OpCom8 1745 OpCom16 1746 OpCom32 1747 OpCom64 1748 OpCtz32 1749 OpCtz64 1750 OpBswap32 1751 OpBswap64 1752 OpSqrt 1753 OpPhi 1754 OpCopy 1755 OpConvert 1756 OpConstBool 1757 OpConstString 1758 OpConstNil 1759 OpConst8 1760 OpConst16 1761 OpConst32 1762 OpConst64 1763 OpConst32F 1764 OpConst64F 1765 OpConstInterface 1766 OpConstSlice 1767 OpInitMem 1768 OpArg 1769 OpAddr 1770 OpSP 1771 OpSB 1772 OpFunc 1773 OpLoad 1774 OpStore 1775 OpMove 1776 OpZero 1777 OpStoreWB 1778 OpMoveWB 1779 OpMoveWBVolatile 1780 OpZeroWB 1781 OpClosureCall 1782 OpStaticCall 1783 OpDeferCall 1784 OpGoCall 1785 OpInterCall 1786 OpSignExt8to16 1787 OpSignExt8to32 1788 OpSignExt8to64 1789 OpSignExt16to32 1790 OpSignExt16to64 1791 OpSignExt32to64 1792 OpZeroExt8to16 1793 OpZeroExt8to32 1794 OpZeroExt8to64 1795 OpZeroExt16to32 1796 OpZeroExt16to64 1797 OpZeroExt32to64 1798 OpTrunc16to8 1799 OpTrunc32to8 1800 OpTrunc32to16 1801 OpTrunc64to8 1802 OpTrunc64to16 1803 OpTrunc64to32 1804 OpCvt32to32F 1805 OpCvt32to64F 1806 OpCvt64to32F 1807 OpCvt64to64F 1808 OpCvt32Fto32 1809 OpCvt32Fto64 1810 OpCvt64Fto32 1811 OpCvt64Fto64 1812 OpCvt32Fto64F 1813 OpCvt64Fto32F 1814 OpIsNonNil 1815 OpIsInBounds 1816 OpIsSliceInBounds 1817 OpNilCheck 1818 OpGetG 1819 OpGetClosurePtr 1820 OpPtrIndex 1821 OpOffPtr 1822 OpSliceMake 1823 OpSlicePtr 1824 OpSliceLen 1825 OpSliceCap 1826 OpComplexMake 1827 OpComplexReal 1828 OpComplexImag 1829 OpStringMake 1830 OpStringPtr 1831 OpStringLen 1832 OpIMake 1833 OpITab 1834 OpIData 1835 OpStructMake0 1836 OpStructMake1 1837 OpStructMake2 1838 OpStructMake3 1839 OpStructMake4 1840 OpStructSelect 1841 OpArrayMake0 1842 OpArrayMake1 1843 OpArraySelect 1844 OpStoreReg 1845 OpLoadReg 1846 OpFwdRef 1847 OpUnknown 1848 OpVarDef 1849 OpVarKill 1850 OpVarLive 1851 OpKeepAlive 1852 OpInt64Make 1853 OpInt64Hi 1854 OpInt64Lo 1855 OpAdd32carry 1856 OpAdd32withcarry 1857 OpSub32carry 1858 OpSub32withcarry 1859 OpSignmask 1860 OpZeromask 1861 OpSlicemask 1862 OpCvt32Uto32F 1863 OpCvt32Uto64F 1864 OpCvt32Fto32U 1865 OpCvt64Fto32U 1866 OpCvt64Uto32F 1867 OpCvt64Uto64F 1868 OpCvt32Fto64U 1869 OpCvt64Fto64U 1870 OpSelect0 1871 OpSelect1 1872 OpAtomicLoad32 1873 OpAtomicLoad64 1874 OpAtomicLoadPtr 1875 OpAtomicStore32 1876 OpAtomicStore64 1877 OpAtomicStorePtrNoWB 1878 OpAtomicExchange32 1879 OpAtomicExchange64 1880 OpAtomicAdd32 1881 OpAtomicAdd64 1882 OpAtomicCompareAndSwap32 1883 OpAtomicCompareAndSwap64 1884 OpAtomicAnd8 1885 OpAtomicOr8 1886 ) 1887 1888 var opcodeTable = [...]opInfo{ 1889 {name: "OpInvalid"}, 1890 1891 { 1892 name: "ADDSS", 1893 argLen: 2, 1894 commutative: true, 1895 resultInArg0: true, 1896 usesScratch: true, 1897 asm: x86.AADDSS, 1898 reg: regInfo{ 1899 inputs: []inputInfo{ 1900 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1901 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1902 }, 1903 outputs: []outputInfo{ 1904 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1905 }, 1906 }, 1907 }, 1908 { 1909 name: "ADDSD", 1910 argLen: 2, 1911 commutative: true, 1912 resultInArg0: true, 1913 asm: x86.AADDSD, 1914 reg: regInfo{ 1915 inputs: []inputInfo{ 1916 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1917 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1918 }, 1919 outputs: []outputInfo{ 1920 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1921 }, 1922 }, 1923 }, 1924 { 1925 name: "SUBSS", 1926 argLen: 2, 1927 resultInArg0: true, 1928 usesScratch: true, 1929 asm: x86.ASUBSS, 1930 reg: regInfo{ 1931 inputs: []inputInfo{ 1932 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1933 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1934 }, 1935 outputs: []outputInfo{ 1936 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1937 }, 1938 }, 1939 }, 1940 { 1941 name: "SUBSD", 1942 argLen: 2, 1943 resultInArg0: true, 1944 asm: x86.ASUBSD, 1945 reg: regInfo{ 1946 inputs: []inputInfo{ 1947 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1948 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1949 }, 1950 outputs: []outputInfo{ 1951 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1952 }, 1953 }, 1954 }, 1955 { 1956 name: "MULSS", 1957 argLen: 2, 1958 commutative: true, 1959 resultInArg0: true, 1960 usesScratch: true, 1961 asm: x86.AMULSS, 1962 reg: regInfo{ 1963 inputs: []inputInfo{ 1964 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1965 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1966 }, 1967 outputs: []outputInfo{ 1968 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1969 }, 1970 }, 1971 }, 1972 { 1973 name: "MULSD", 1974 argLen: 2, 1975 commutative: true, 1976 resultInArg0: true, 1977 asm: x86.AMULSD, 1978 reg: regInfo{ 1979 inputs: []inputInfo{ 1980 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1981 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1982 }, 1983 outputs: []outputInfo{ 1984 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1985 }, 1986 }, 1987 }, 1988 { 1989 name: "DIVSS", 1990 argLen: 2, 1991 resultInArg0: true, 1992 usesScratch: true, 1993 asm: x86.ADIVSS, 1994 reg: regInfo{ 1995 inputs: []inputInfo{ 1996 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1997 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1998 }, 1999 outputs: []outputInfo{ 2000 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2001 }, 2002 }, 2003 }, 2004 { 2005 name: "DIVSD", 2006 argLen: 2, 2007 resultInArg0: true, 2008 asm: x86.ADIVSD, 2009 reg: regInfo{ 2010 inputs: []inputInfo{ 2011 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2012 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2013 }, 2014 outputs: []outputInfo{ 2015 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2016 }, 2017 }, 2018 }, 2019 { 2020 name: "MOVSSload", 2021 auxType: auxSymOff, 2022 argLen: 2, 2023 faultOnNilArg0: true, 2024 asm: x86.AMOVSS, 2025 reg: regInfo{ 2026 inputs: []inputInfo{ 2027 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2028 }, 2029 outputs: []outputInfo{ 2030 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2031 }, 2032 }, 2033 }, 2034 { 2035 name: "MOVSDload", 2036 auxType: auxSymOff, 2037 argLen: 2, 2038 faultOnNilArg0: true, 2039 asm: x86.AMOVSD, 2040 reg: regInfo{ 2041 inputs: []inputInfo{ 2042 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2043 }, 2044 outputs: []outputInfo{ 2045 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2046 }, 2047 }, 2048 }, 2049 { 2050 name: "MOVSSconst", 2051 auxType: auxFloat32, 2052 argLen: 0, 2053 rematerializeable: true, 2054 asm: x86.AMOVSS, 2055 reg: regInfo{ 2056 outputs: []outputInfo{ 2057 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2058 }, 2059 }, 2060 }, 2061 { 2062 name: "MOVSDconst", 2063 auxType: auxFloat64, 2064 argLen: 0, 2065 rematerializeable: true, 2066 asm: x86.AMOVSD, 2067 reg: regInfo{ 2068 outputs: []outputInfo{ 2069 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2070 }, 2071 }, 2072 }, 2073 { 2074 name: "MOVSSloadidx1", 2075 auxType: auxSymOff, 2076 argLen: 3, 2077 asm: x86.AMOVSS, 2078 reg: regInfo{ 2079 inputs: []inputInfo{ 2080 {1, 255}, // AX CX DX BX SP BP SI DI 2081 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2082 }, 2083 outputs: []outputInfo{ 2084 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2085 }, 2086 }, 2087 }, 2088 { 2089 name: "MOVSSloadidx4", 2090 auxType: auxSymOff, 2091 argLen: 3, 2092 asm: x86.AMOVSS, 2093 reg: regInfo{ 2094 inputs: []inputInfo{ 2095 {1, 255}, // AX CX DX BX SP BP SI DI 2096 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2097 }, 2098 outputs: []outputInfo{ 2099 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2100 }, 2101 }, 2102 }, 2103 { 2104 name: "MOVSDloadidx1", 2105 auxType: auxSymOff, 2106 argLen: 3, 2107 asm: x86.AMOVSD, 2108 reg: regInfo{ 2109 inputs: []inputInfo{ 2110 {1, 255}, // AX CX DX BX SP BP SI DI 2111 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2112 }, 2113 outputs: []outputInfo{ 2114 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2115 }, 2116 }, 2117 }, 2118 { 2119 name: "MOVSDloadidx8", 2120 auxType: auxSymOff, 2121 argLen: 3, 2122 asm: x86.AMOVSD, 2123 reg: regInfo{ 2124 inputs: []inputInfo{ 2125 {1, 255}, // AX CX DX BX SP BP SI DI 2126 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2127 }, 2128 outputs: []outputInfo{ 2129 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2130 }, 2131 }, 2132 }, 2133 { 2134 name: "MOVSSstore", 2135 auxType: auxSymOff, 2136 argLen: 3, 2137 faultOnNilArg0: true, 2138 asm: x86.AMOVSS, 2139 reg: regInfo{ 2140 inputs: []inputInfo{ 2141 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2142 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2143 }, 2144 }, 2145 }, 2146 { 2147 name: "MOVSDstore", 2148 auxType: auxSymOff, 2149 argLen: 3, 2150 faultOnNilArg0: true, 2151 asm: x86.AMOVSD, 2152 reg: regInfo{ 2153 inputs: []inputInfo{ 2154 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2155 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2156 }, 2157 }, 2158 }, 2159 { 2160 name: "MOVSSstoreidx1", 2161 auxType: auxSymOff, 2162 argLen: 4, 2163 asm: x86.AMOVSS, 2164 reg: regInfo{ 2165 inputs: []inputInfo{ 2166 {1, 255}, // AX CX DX BX SP BP SI DI 2167 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2168 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2169 }, 2170 }, 2171 }, 2172 { 2173 name: "MOVSSstoreidx4", 2174 auxType: auxSymOff, 2175 argLen: 4, 2176 asm: x86.AMOVSS, 2177 reg: regInfo{ 2178 inputs: []inputInfo{ 2179 {1, 255}, // AX CX DX BX SP BP SI DI 2180 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2181 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2182 }, 2183 }, 2184 }, 2185 { 2186 name: "MOVSDstoreidx1", 2187 auxType: auxSymOff, 2188 argLen: 4, 2189 asm: x86.AMOVSD, 2190 reg: regInfo{ 2191 inputs: []inputInfo{ 2192 {1, 255}, // AX CX DX BX SP BP SI DI 2193 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2194 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2195 }, 2196 }, 2197 }, 2198 { 2199 name: "MOVSDstoreidx8", 2200 auxType: auxSymOff, 2201 argLen: 4, 2202 asm: x86.AMOVSD, 2203 reg: regInfo{ 2204 inputs: []inputInfo{ 2205 {1, 255}, // AX CX DX BX SP BP SI DI 2206 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2207 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2208 }, 2209 }, 2210 }, 2211 { 2212 name: "ADDL", 2213 argLen: 2, 2214 commutative: true, 2215 clobberFlags: true, 2216 asm: x86.AADDL, 2217 reg: regInfo{ 2218 inputs: []inputInfo{ 2219 {1, 239}, // AX CX DX BX BP SI DI 2220 {0, 255}, // AX CX DX BX SP BP SI DI 2221 }, 2222 outputs: []outputInfo{ 2223 {0, 239}, // AX CX DX BX BP SI DI 2224 }, 2225 }, 2226 }, 2227 { 2228 name: "ADDLconst", 2229 auxType: auxInt32, 2230 argLen: 1, 2231 clobberFlags: true, 2232 asm: x86.AADDL, 2233 reg: regInfo{ 2234 inputs: []inputInfo{ 2235 {0, 255}, // AX CX DX BX SP BP SI DI 2236 }, 2237 outputs: []outputInfo{ 2238 {0, 239}, // AX CX DX BX BP SI DI 2239 }, 2240 }, 2241 }, 2242 { 2243 name: "ADDLcarry", 2244 argLen: 2, 2245 commutative: true, 2246 resultInArg0: true, 2247 asm: x86.AADDL, 2248 reg: regInfo{ 2249 inputs: []inputInfo{ 2250 {0, 239}, // AX CX DX BX BP SI DI 2251 {1, 239}, // AX CX DX BX BP SI DI 2252 }, 2253 outputs: []outputInfo{ 2254 {1, 0}, 2255 {0, 239}, // AX CX DX BX BP SI DI 2256 }, 2257 }, 2258 }, 2259 { 2260 name: "ADDLconstcarry", 2261 auxType: auxInt32, 2262 argLen: 1, 2263 resultInArg0: true, 2264 asm: x86.AADDL, 2265 reg: regInfo{ 2266 inputs: []inputInfo{ 2267 {0, 239}, // AX CX DX BX BP SI DI 2268 }, 2269 outputs: []outputInfo{ 2270 {1, 0}, 2271 {0, 239}, // AX CX DX BX BP SI DI 2272 }, 2273 }, 2274 }, 2275 { 2276 name: "ADCL", 2277 argLen: 3, 2278 commutative: true, 2279 resultInArg0: true, 2280 clobberFlags: true, 2281 asm: x86.AADCL, 2282 reg: regInfo{ 2283 inputs: []inputInfo{ 2284 {0, 239}, // AX CX DX BX BP SI DI 2285 {1, 239}, // AX CX DX BX BP SI DI 2286 }, 2287 outputs: []outputInfo{ 2288 {0, 239}, // AX CX DX BX BP SI DI 2289 }, 2290 }, 2291 }, 2292 { 2293 name: "ADCLconst", 2294 auxType: auxInt32, 2295 argLen: 2, 2296 resultInArg0: true, 2297 clobberFlags: true, 2298 asm: x86.AADCL, 2299 reg: regInfo{ 2300 inputs: []inputInfo{ 2301 {0, 239}, // AX CX DX BX BP SI DI 2302 }, 2303 outputs: []outputInfo{ 2304 {0, 239}, // AX CX DX BX BP SI DI 2305 }, 2306 }, 2307 }, 2308 { 2309 name: "SUBL", 2310 argLen: 2, 2311 resultInArg0: true, 2312 clobberFlags: true, 2313 asm: x86.ASUBL, 2314 reg: regInfo{ 2315 inputs: []inputInfo{ 2316 {0, 239}, // AX CX DX BX BP SI DI 2317 {1, 239}, // AX CX DX BX BP SI DI 2318 }, 2319 outputs: []outputInfo{ 2320 {0, 239}, // AX CX DX BX BP SI DI 2321 }, 2322 }, 2323 }, 2324 { 2325 name: "SUBLconst", 2326 auxType: auxInt32, 2327 argLen: 1, 2328 resultInArg0: true, 2329 clobberFlags: true, 2330 asm: x86.ASUBL, 2331 reg: regInfo{ 2332 inputs: []inputInfo{ 2333 {0, 239}, // AX CX DX BX BP SI DI 2334 }, 2335 outputs: []outputInfo{ 2336 {0, 239}, // AX CX DX BX BP SI DI 2337 }, 2338 }, 2339 }, 2340 { 2341 name: "SUBLcarry", 2342 argLen: 2, 2343 resultInArg0: true, 2344 asm: x86.ASUBL, 2345 reg: regInfo{ 2346 inputs: []inputInfo{ 2347 {0, 239}, // AX CX DX BX BP SI DI 2348 {1, 239}, // AX CX DX BX BP SI DI 2349 }, 2350 outputs: []outputInfo{ 2351 {1, 0}, 2352 {0, 239}, // AX CX DX BX BP SI DI 2353 }, 2354 }, 2355 }, 2356 { 2357 name: "SUBLconstcarry", 2358 auxType: auxInt32, 2359 argLen: 1, 2360 resultInArg0: true, 2361 asm: x86.ASUBL, 2362 reg: regInfo{ 2363 inputs: []inputInfo{ 2364 {0, 239}, // AX CX DX BX BP SI DI 2365 }, 2366 outputs: []outputInfo{ 2367 {1, 0}, 2368 {0, 239}, // AX CX DX BX BP SI DI 2369 }, 2370 }, 2371 }, 2372 { 2373 name: "SBBL", 2374 argLen: 3, 2375 resultInArg0: true, 2376 clobberFlags: true, 2377 asm: x86.ASBBL, 2378 reg: regInfo{ 2379 inputs: []inputInfo{ 2380 {0, 239}, // AX CX DX BX BP SI DI 2381 {1, 239}, // AX CX DX BX BP SI DI 2382 }, 2383 outputs: []outputInfo{ 2384 {0, 239}, // AX CX DX BX BP SI DI 2385 }, 2386 }, 2387 }, 2388 { 2389 name: "SBBLconst", 2390 auxType: auxInt32, 2391 argLen: 2, 2392 resultInArg0: true, 2393 clobberFlags: true, 2394 asm: x86.ASBBL, 2395 reg: regInfo{ 2396 inputs: []inputInfo{ 2397 {0, 239}, // AX CX DX BX BP SI DI 2398 }, 2399 outputs: []outputInfo{ 2400 {0, 239}, // AX CX DX BX BP SI DI 2401 }, 2402 }, 2403 }, 2404 { 2405 name: "MULL", 2406 argLen: 2, 2407 commutative: true, 2408 resultInArg0: true, 2409 clobberFlags: true, 2410 asm: x86.AIMULL, 2411 reg: regInfo{ 2412 inputs: []inputInfo{ 2413 {0, 239}, // AX CX DX BX BP SI DI 2414 {1, 239}, // AX CX DX BX BP SI DI 2415 }, 2416 outputs: []outputInfo{ 2417 {0, 239}, // AX CX DX BX BP SI DI 2418 }, 2419 }, 2420 }, 2421 { 2422 name: "MULLconst", 2423 auxType: auxInt32, 2424 argLen: 1, 2425 resultInArg0: true, 2426 clobberFlags: true, 2427 asm: x86.AIMULL, 2428 reg: regInfo{ 2429 inputs: []inputInfo{ 2430 {0, 239}, // AX CX DX BX BP SI DI 2431 }, 2432 outputs: []outputInfo{ 2433 {0, 239}, // AX CX DX BX BP SI DI 2434 }, 2435 }, 2436 }, 2437 { 2438 name: "HMULL", 2439 argLen: 2, 2440 clobberFlags: true, 2441 asm: x86.AIMULL, 2442 reg: regInfo{ 2443 inputs: []inputInfo{ 2444 {0, 1}, // AX 2445 {1, 255}, // AX CX DX BX SP BP SI DI 2446 }, 2447 clobbers: 1, // AX 2448 outputs: []outputInfo{ 2449 {0, 4}, // DX 2450 }, 2451 }, 2452 }, 2453 { 2454 name: "HMULLU", 2455 argLen: 2, 2456 clobberFlags: true, 2457 asm: x86.AMULL, 2458 reg: regInfo{ 2459 inputs: []inputInfo{ 2460 {0, 1}, // AX 2461 {1, 255}, // AX CX DX BX SP BP SI DI 2462 }, 2463 clobbers: 1, // AX 2464 outputs: []outputInfo{ 2465 {0, 4}, // DX 2466 }, 2467 }, 2468 }, 2469 { 2470 name: "HMULW", 2471 argLen: 2, 2472 clobberFlags: true, 2473 asm: x86.AIMULW, 2474 reg: regInfo{ 2475 inputs: []inputInfo{ 2476 {0, 1}, // AX 2477 {1, 255}, // AX CX DX BX SP BP SI DI 2478 }, 2479 clobbers: 1, // AX 2480 outputs: []outputInfo{ 2481 {0, 4}, // DX 2482 }, 2483 }, 2484 }, 2485 { 2486 name: "HMULB", 2487 argLen: 2, 2488 clobberFlags: true, 2489 asm: x86.AIMULB, 2490 reg: regInfo{ 2491 inputs: []inputInfo{ 2492 {0, 1}, // AX 2493 {1, 255}, // AX CX DX BX SP BP SI DI 2494 }, 2495 clobbers: 1, // AX 2496 outputs: []outputInfo{ 2497 {0, 4}, // DX 2498 }, 2499 }, 2500 }, 2501 { 2502 name: "HMULWU", 2503 argLen: 2, 2504 clobberFlags: true, 2505 asm: x86.AMULW, 2506 reg: regInfo{ 2507 inputs: []inputInfo{ 2508 {0, 1}, // AX 2509 {1, 255}, // AX CX DX BX SP BP SI DI 2510 }, 2511 clobbers: 1, // AX 2512 outputs: []outputInfo{ 2513 {0, 4}, // DX 2514 }, 2515 }, 2516 }, 2517 { 2518 name: "HMULBU", 2519 argLen: 2, 2520 clobberFlags: true, 2521 asm: x86.AMULB, 2522 reg: regInfo{ 2523 inputs: []inputInfo{ 2524 {0, 1}, // AX 2525 {1, 255}, // AX CX DX BX SP BP SI DI 2526 }, 2527 clobbers: 1, // AX 2528 outputs: []outputInfo{ 2529 {0, 4}, // DX 2530 }, 2531 }, 2532 }, 2533 { 2534 name: "MULLQU", 2535 argLen: 2, 2536 clobberFlags: true, 2537 asm: x86.AMULL, 2538 reg: regInfo{ 2539 inputs: []inputInfo{ 2540 {0, 1}, // AX 2541 {1, 255}, // AX CX DX BX SP BP SI DI 2542 }, 2543 outputs: []outputInfo{ 2544 {0, 4}, // DX 2545 {1, 1}, // AX 2546 }, 2547 }, 2548 }, 2549 { 2550 name: "DIVL", 2551 argLen: 2, 2552 clobberFlags: true, 2553 asm: x86.AIDIVL, 2554 reg: regInfo{ 2555 inputs: []inputInfo{ 2556 {0, 1}, // AX 2557 {1, 251}, // AX CX BX SP BP SI DI 2558 }, 2559 clobbers: 4, // DX 2560 outputs: []outputInfo{ 2561 {0, 1}, // AX 2562 }, 2563 }, 2564 }, 2565 { 2566 name: "DIVW", 2567 argLen: 2, 2568 clobberFlags: true, 2569 asm: x86.AIDIVW, 2570 reg: regInfo{ 2571 inputs: []inputInfo{ 2572 {0, 1}, // AX 2573 {1, 251}, // AX CX BX SP BP SI DI 2574 }, 2575 clobbers: 4, // DX 2576 outputs: []outputInfo{ 2577 {0, 1}, // AX 2578 }, 2579 }, 2580 }, 2581 { 2582 name: "DIVLU", 2583 argLen: 2, 2584 clobberFlags: true, 2585 asm: x86.ADIVL, 2586 reg: regInfo{ 2587 inputs: []inputInfo{ 2588 {0, 1}, // AX 2589 {1, 251}, // AX CX BX SP BP SI DI 2590 }, 2591 clobbers: 4, // DX 2592 outputs: []outputInfo{ 2593 {0, 1}, // AX 2594 }, 2595 }, 2596 }, 2597 { 2598 name: "DIVWU", 2599 argLen: 2, 2600 clobberFlags: true, 2601 asm: x86.ADIVW, 2602 reg: regInfo{ 2603 inputs: []inputInfo{ 2604 {0, 1}, // AX 2605 {1, 251}, // AX CX BX SP BP SI DI 2606 }, 2607 clobbers: 4, // DX 2608 outputs: []outputInfo{ 2609 {0, 1}, // AX 2610 }, 2611 }, 2612 }, 2613 { 2614 name: "MODL", 2615 argLen: 2, 2616 clobberFlags: true, 2617 asm: x86.AIDIVL, 2618 reg: regInfo{ 2619 inputs: []inputInfo{ 2620 {0, 1}, // AX 2621 {1, 251}, // AX CX BX SP BP SI DI 2622 }, 2623 clobbers: 1, // AX 2624 outputs: []outputInfo{ 2625 {0, 4}, // DX 2626 }, 2627 }, 2628 }, 2629 { 2630 name: "MODW", 2631 argLen: 2, 2632 clobberFlags: true, 2633 asm: x86.AIDIVW, 2634 reg: regInfo{ 2635 inputs: []inputInfo{ 2636 {0, 1}, // AX 2637 {1, 251}, // AX CX BX SP BP SI DI 2638 }, 2639 clobbers: 1, // AX 2640 outputs: []outputInfo{ 2641 {0, 4}, // DX 2642 }, 2643 }, 2644 }, 2645 { 2646 name: "MODLU", 2647 argLen: 2, 2648 clobberFlags: true, 2649 asm: x86.ADIVL, 2650 reg: regInfo{ 2651 inputs: []inputInfo{ 2652 {0, 1}, // AX 2653 {1, 251}, // AX CX BX SP BP SI DI 2654 }, 2655 clobbers: 1, // AX 2656 outputs: []outputInfo{ 2657 {0, 4}, // DX 2658 }, 2659 }, 2660 }, 2661 { 2662 name: "MODWU", 2663 argLen: 2, 2664 clobberFlags: true, 2665 asm: x86.ADIVW, 2666 reg: regInfo{ 2667 inputs: []inputInfo{ 2668 {0, 1}, // AX 2669 {1, 251}, // AX CX BX SP BP SI DI 2670 }, 2671 clobbers: 1, // AX 2672 outputs: []outputInfo{ 2673 {0, 4}, // DX 2674 }, 2675 }, 2676 }, 2677 { 2678 name: "ANDL", 2679 argLen: 2, 2680 commutative: true, 2681 resultInArg0: true, 2682 clobberFlags: true, 2683 asm: x86.AANDL, 2684 reg: regInfo{ 2685 inputs: []inputInfo{ 2686 {0, 239}, // AX CX DX BX BP SI DI 2687 {1, 239}, // AX CX DX BX BP SI DI 2688 }, 2689 outputs: []outputInfo{ 2690 {0, 239}, // AX CX DX BX BP SI DI 2691 }, 2692 }, 2693 }, 2694 { 2695 name: "ANDLconst", 2696 auxType: auxInt32, 2697 argLen: 1, 2698 resultInArg0: true, 2699 clobberFlags: true, 2700 asm: x86.AANDL, 2701 reg: regInfo{ 2702 inputs: []inputInfo{ 2703 {0, 239}, // AX CX DX BX BP SI DI 2704 }, 2705 outputs: []outputInfo{ 2706 {0, 239}, // AX CX DX BX BP SI DI 2707 }, 2708 }, 2709 }, 2710 { 2711 name: "ORL", 2712 argLen: 2, 2713 commutative: true, 2714 resultInArg0: true, 2715 clobberFlags: true, 2716 asm: x86.AORL, 2717 reg: regInfo{ 2718 inputs: []inputInfo{ 2719 {0, 239}, // AX CX DX BX BP SI DI 2720 {1, 239}, // AX CX DX BX BP SI DI 2721 }, 2722 outputs: []outputInfo{ 2723 {0, 239}, // AX CX DX BX BP SI DI 2724 }, 2725 }, 2726 }, 2727 { 2728 name: "ORLconst", 2729 auxType: auxInt32, 2730 argLen: 1, 2731 resultInArg0: true, 2732 clobberFlags: true, 2733 asm: x86.AORL, 2734 reg: regInfo{ 2735 inputs: []inputInfo{ 2736 {0, 239}, // AX CX DX BX BP SI DI 2737 }, 2738 outputs: []outputInfo{ 2739 {0, 239}, // AX CX DX BX BP SI DI 2740 }, 2741 }, 2742 }, 2743 { 2744 name: "XORL", 2745 argLen: 2, 2746 commutative: true, 2747 resultInArg0: true, 2748 clobberFlags: true, 2749 asm: x86.AXORL, 2750 reg: regInfo{ 2751 inputs: []inputInfo{ 2752 {0, 239}, // AX CX DX BX BP SI DI 2753 {1, 239}, // AX CX DX BX BP SI DI 2754 }, 2755 outputs: []outputInfo{ 2756 {0, 239}, // AX CX DX BX BP SI DI 2757 }, 2758 }, 2759 }, 2760 { 2761 name: "XORLconst", 2762 auxType: auxInt32, 2763 argLen: 1, 2764 resultInArg0: true, 2765 clobberFlags: true, 2766 asm: x86.AXORL, 2767 reg: regInfo{ 2768 inputs: []inputInfo{ 2769 {0, 239}, // AX CX DX BX BP SI DI 2770 }, 2771 outputs: []outputInfo{ 2772 {0, 239}, // AX CX DX BX BP SI DI 2773 }, 2774 }, 2775 }, 2776 { 2777 name: "CMPL", 2778 argLen: 2, 2779 asm: x86.ACMPL, 2780 reg: regInfo{ 2781 inputs: []inputInfo{ 2782 {0, 255}, // AX CX DX BX SP BP SI DI 2783 {1, 255}, // AX CX DX BX SP BP SI DI 2784 }, 2785 }, 2786 }, 2787 { 2788 name: "CMPW", 2789 argLen: 2, 2790 asm: x86.ACMPW, 2791 reg: regInfo{ 2792 inputs: []inputInfo{ 2793 {0, 255}, // AX CX DX BX SP BP SI DI 2794 {1, 255}, // AX CX DX BX SP BP SI DI 2795 }, 2796 }, 2797 }, 2798 { 2799 name: "CMPB", 2800 argLen: 2, 2801 asm: x86.ACMPB, 2802 reg: regInfo{ 2803 inputs: []inputInfo{ 2804 {0, 255}, // AX CX DX BX SP BP SI DI 2805 {1, 255}, // AX CX DX BX SP BP SI DI 2806 }, 2807 }, 2808 }, 2809 { 2810 name: "CMPLconst", 2811 auxType: auxInt32, 2812 argLen: 1, 2813 asm: x86.ACMPL, 2814 reg: regInfo{ 2815 inputs: []inputInfo{ 2816 {0, 255}, // AX CX DX BX SP BP SI DI 2817 }, 2818 }, 2819 }, 2820 { 2821 name: "CMPWconst", 2822 auxType: auxInt16, 2823 argLen: 1, 2824 asm: x86.ACMPW, 2825 reg: regInfo{ 2826 inputs: []inputInfo{ 2827 {0, 255}, // AX CX DX BX SP BP SI DI 2828 }, 2829 }, 2830 }, 2831 { 2832 name: "CMPBconst", 2833 auxType: auxInt8, 2834 argLen: 1, 2835 asm: x86.ACMPB, 2836 reg: regInfo{ 2837 inputs: []inputInfo{ 2838 {0, 255}, // AX CX DX BX SP BP SI DI 2839 }, 2840 }, 2841 }, 2842 { 2843 name: "UCOMISS", 2844 argLen: 2, 2845 usesScratch: true, 2846 asm: x86.AUCOMISS, 2847 reg: regInfo{ 2848 inputs: []inputInfo{ 2849 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2850 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2851 }, 2852 }, 2853 }, 2854 { 2855 name: "UCOMISD", 2856 argLen: 2, 2857 usesScratch: true, 2858 asm: x86.AUCOMISD, 2859 reg: regInfo{ 2860 inputs: []inputInfo{ 2861 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2862 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2863 }, 2864 }, 2865 }, 2866 { 2867 name: "TESTL", 2868 argLen: 2, 2869 asm: x86.ATESTL, 2870 reg: regInfo{ 2871 inputs: []inputInfo{ 2872 {0, 255}, // AX CX DX BX SP BP SI DI 2873 {1, 255}, // AX CX DX BX SP BP SI DI 2874 }, 2875 }, 2876 }, 2877 { 2878 name: "TESTW", 2879 argLen: 2, 2880 asm: x86.ATESTW, 2881 reg: regInfo{ 2882 inputs: []inputInfo{ 2883 {0, 255}, // AX CX DX BX SP BP SI DI 2884 {1, 255}, // AX CX DX BX SP BP SI DI 2885 }, 2886 }, 2887 }, 2888 { 2889 name: "TESTB", 2890 argLen: 2, 2891 asm: x86.ATESTB, 2892 reg: regInfo{ 2893 inputs: []inputInfo{ 2894 {0, 255}, // AX CX DX BX SP BP SI DI 2895 {1, 255}, // AX CX DX BX SP BP SI DI 2896 }, 2897 }, 2898 }, 2899 { 2900 name: "TESTLconst", 2901 auxType: auxInt32, 2902 argLen: 1, 2903 asm: x86.ATESTL, 2904 reg: regInfo{ 2905 inputs: []inputInfo{ 2906 {0, 255}, // AX CX DX BX SP BP SI DI 2907 }, 2908 }, 2909 }, 2910 { 2911 name: "TESTWconst", 2912 auxType: auxInt16, 2913 argLen: 1, 2914 asm: x86.ATESTW, 2915 reg: regInfo{ 2916 inputs: []inputInfo{ 2917 {0, 255}, // AX CX DX BX SP BP SI DI 2918 }, 2919 }, 2920 }, 2921 { 2922 name: "TESTBconst", 2923 auxType: auxInt8, 2924 argLen: 1, 2925 asm: x86.ATESTB, 2926 reg: regInfo{ 2927 inputs: []inputInfo{ 2928 {0, 255}, // AX CX DX BX SP BP SI DI 2929 }, 2930 }, 2931 }, 2932 { 2933 name: "SHLL", 2934 argLen: 2, 2935 resultInArg0: true, 2936 clobberFlags: true, 2937 asm: x86.ASHLL, 2938 reg: regInfo{ 2939 inputs: []inputInfo{ 2940 {1, 2}, // CX 2941 {0, 239}, // AX CX DX BX BP SI DI 2942 }, 2943 outputs: []outputInfo{ 2944 {0, 239}, // AX CX DX BX BP SI DI 2945 }, 2946 }, 2947 }, 2948 { 2949 name: "SHLLconst", 2950 auxType: auxInt32, 2951 argLen: 1, 2952 resultInArg0: true, 2953 clobberFlags: true, 2954 asm: x86.ASHLL, 2955 reg: regInfo{ 2956 inputs: []inputInfo{ 2957 {0, 239}, // AX CX DX BX BP SI DI 2958 }, 2959 outputs: []outputInfo{ 2960 {0, 239}, // AX CX DX BX BP SI DI 2961 }, 2962 }, 2963 }, 2964 { 2965 name: "SHRL", 2966 argLen: 2, 2967 resultInArg0: true, 2968 clobberFlags: true, 2969 asm: x86.ASHRL, 2970 reg: regInfo{ 2971 inputs: []inputInfo{ 2972 {1, 2}, // CX 2973 {0, 239}, // AX CX DX BX BP SI DI 2974 }, 2975 outputs: []outputInfo{ 2976 {0, 239}, // AX CX DX BX BP SI DI 2977 }, 2978 }, 2979 }, 2980 { 2981 name: "SHRW", 2982 argLen: 2, 2983 resultInArg0: true, 2984 clobberFlags: true, 2985 asm: x86.ASHRW, 2986 reg: regInfo{ 2987 inputs: []inputInfo{ 2988 {1, 2}, // CX 2989 {0, 239}, // AX CX DX BX BP SI DI 2990 }, 2991 outputs: []outputInfo{ 2992 {0, 239}, // AX CX DX BX BP SI DI 2993 }, 2994 }, 2995 }, 2996 { 2997 name: "SHRB", 2998 argLen: 2, 2999 resultInArg0: true, 3000 clobberFlags: true, 3001 asm: x86.ASHRB, 3002 reg: regInfo{ 3003 inputs: []inputInfo{ 3004 {1, 2}, // CX 3005 {0, 239}, // AX CX DX BX BP SI DI 3006 }, 3007 outputs: []outputInfo{ 3008 {0, 239}, // AX CX DX BX BP SI DI 3009 }, 3010 }, 3011 }, 3012 { 3013 name: "SHRLconst", 3014 auxType: auxInt32, 3015 argLen: 1, 3016 resultInArg0: true, 3017 clobberFlags: true, 3018 asm: x86.ASHRL, 3019 reg: regInfo{ 3020 inputs: []inputInfo{ 3021 {0, 239}, // AX CX DX BX BP SI DI 3022 }, 3023 outputs: []outputInfo{ 3024 {0, 239}, // AX CX DX BX BP SI DI 3025 }, 3026 }, 3027 }, 3028 { 3029 name: "SHRWconst", 3030 auxType: auxInt16, 3031 argLen: 1, 3032 resultInArg0: true, 3033 clobberFlags: true, 3034 asm: x86.ASHRW, 3035 reg: regInfo{ 3036 inputs: []inputInfo{ 3037 {0, 239}, // AX CX DX BX BP SI DI 3038 }, 3039 outputs: []outputInfo{ 3040 {0, 239}, // AX CX DX BX BP SI DI 3041 }, 3042 }, 3043 }, 3044 { 3045 name: "SHRBconst", 3046 auxType: auxInt8, 3047 argLen: 1, 3048 resultInArg0: true, 3049 clobberFlags: true, 3050 asm: x86.ASHRB, 3051 reg: regInfo{ 3052 inputs: []inputInfo{ 3053 {0, 239}, // AX CX DX BX BP SI DI 3054 }, 3055 outputs: []outputInfo{ 3056 {0, 239}, // AX CX DX BX BP SI DI 3057 }, 3058 }, 3059 }, 3060 { 3061 name: "SARL", 3062 argLen: 2, 3063 resultInArg0: true, 3064 clobberFlags: true, 3065 asm: x86.ASARL, 3066 reg: regInfo{ 3067 inputs: []inputInfo{ 3068 {1, 2}, // CX 3069 {0, 239}, // AX CX DX BX BP SI DI 3070 }, 3071 outputs: []outputInfo{ 3072 {0, 239}, // AX CX DX BX BP SI DI 3073 }, 3074 }, 3075 }, 3076 { 3077 name: "SARW", 3078 argLen: 2, 3079 resultInArg0: true, 3080 clobberFlags: true, 3081 asm: x86.ASARW, 3082 reg: regInfo{ 3083 inputs: []inputInfo{ 3084 {1, 2}, // CX 3085 {0, 239}, // AX CX DX BX BP SI DI 3086 }, 3087 outputs: []outputInfo{ 3088 {0, 239}, // AX CX DX BX BP SI DI 3089 }, 3090 }, 3091 }, 3092 { 3093 name: "SARB", 3094 argLen: 2, 3095 resultInArg0: true, 3096 clobberFlags: true, 3097 asm: x86.ASARB, 3098 reg: regInfo{ 3099 inputs: []inputInfo{ 3100 {1, 2}, // CX 3101 {0, 239}, // AX CX DX BX BP SI DI 3102 }, 3103 outputs: []outputInfo{ 3104 {0, 239}, // AX CX DX BX BP SI DI 3105 }, 3106 }, 3107 }, 3108 { 3109 name: "SARLconst", 3110 auxType: auxInt32, 3111 argLen: 1, 3112 resultInArg0: true, 3113 clobberFlags: true, 3114 asm: x86.ASARL, 3115 reg: regInfo{ 3116 inputs: []inputInfo{ 3117 {0, 239}, // AX CX DX BX BP SI DI 3118 }, 3119 outputs: []outputInfo{ 3120 {0, 239}, // AX CX DX BX BP SI DI 3121 }, 3122 }, 3123 }, 3124 { 3125 name: "SARWconst", 3126 auxType: auxInt16, 3127 argLen: 1, 3128 resultInArg0: true, 3129 clobberFlags: true, 3130 asm: x86.ASARW, 3131 reg: regInfo{ 3132 inputs: []inputInfo{ 3133 {0, 239}, // AX CX DX BX BP SI DI 3134 }, 3135 outputs: []outputInfo{ 3136 {0, 239}, // AX CX DX BX BP SI DI 3137 }, 3138 }, 3139 }, 3140 { 3141 name: "SARBconst", 3142 auxType: auxInt8, 3143 argLen: 1, 3144 resultInArg0: true, 3145 clobberFlags: true, 3146 asm: x86.ASARB, 3147 reg: regInfo{ 3148 inputs: []inputInfo{ 3149 {0, 239}, // AX CX DX BX BP SI DI 3150 }, 3151 outputs: []outputInfo{ 3152 {0, 239}, // AX CX DX BX BP SI DI 3153 }, 3154 }, 3155 }, 3156 { 3157 name: "ROLLconst", 3158 auxType: auxInt32, 3159 argLen: 1, 3160 resultInArg0: true, 3161 clobberFlags: true, 3162 asm: x86.AROLL, 3163 reg: regInfo{ 3164 inputs: []inputInfo{ 3165 {0, 239}, // AX CX DX BX BP SI DI 3166 }, 3167 outputs: []outputInfo{ 3168 {0, 239}, // AX CX DX BX BP SI DI 3169 }, 3170 }, 3171 }, 3172 { 3173 name: "ROLWconst", 3174 auxType: auxInt16, 3175 argLen: 1, 3176 resultInArg0: true, 3177 clobberFlags: true, 3178 asm: x86.AROLW, 3179 reg: regInfo{ 3180 inputs: []inputInfo{ 3181 {0, 239}, // AX CX DX BX BP SI DI 3182 }, 3183 outputs: []outputInfo{ 3184 {0, 239}, // AX CX DX BX BP SI DI 3185 }, 3186 }, 3187 }, 3188 { 3189 name: "ROLBconst", 3190 auxType: auxInt8, 3191 argLen: 1, 3192 resultInArg0: true, 3193 clobberFlags: true, 3194 asm: x86.AROLB, 3195 reg: regInfo{ 3196 inputs: []inputInfo{ 3197 {0, 239}, // AX CX DX BX BP SI DI 3198 }, 3199 outputs: []outputInfo{ 3200 {0, 239}, // AX CX DX BX BP SI DI 3201 }, 3202 }, 3203 }, 3204 { 3205 name: "NEGL", 3206 argLen: 1, 3207 resultInArg0: true, 3208 clobberFlags: true, 3209 asm: x86.ANEGL, 3210 reg: regInfo{ 3211 inputs: []inputInfo{ 3212 {0, 239}, // AX CX DX BX BP SI DI 3213 }, 3214 outputs: []outputInfo{ 3215 {0, 239}, // AX CX DX BX BP SI DI 3216 }, 3217 }, 3218 }, 3219 { 3220 name: "NOTL", 3221 argLen: 1, 3222 resultInArg0: true, 3223 clobberFlags: true, 3224 asm: x86.ANOTL, 3225 reg: regInfo{ 3226 inputs: []inputInfo{ 3227 {0, 239}, // AX CX DX BX BP SI DI 3228 }, 3229 outputs: []outputInfo{ 3230 {0, 239}, // AX CX DX BX BP SI DI 3231 }, 3232 }, 3233 }, 3234 { 3235 name: "BSFL", 3236 argLen: 1, 3237 clobberFlags: true, 3238 asm: x86.ABSFL, 3239 reg: regInfo{ 3240 inputs: []inputInfo{ 3241 {0, 239}, // AX CX DX BX BP SI DI 3242 }, 3243 outputs: []outputInfo{ 3244 {0, 239}, // AX CX DX BX BP SI DI 3245 }, 3246 }, 3247 }, 3248 { 3249 name: "BSFW", 3250 argLen: 1, 3251 clobberFlags: true, 3252 asm: x86.ABSFW, 3253 reg: regInfo{ 3254 inputs: []inputInfo{ 3255 {0, 239}, // AX CX DX BX BP SI DI 3256 }, 3257 outputs: []outputInfo{ 3258 {0, 239}, // AX CX DX BX BP SI DI 3259 }, 3260 }, 3261 }, 3262 { 3263 name: "BSRL", 3264 argLen: 1, 3265 clobberFlags: true, 3266 asm: x86.ABSRL, 3267 reg: regInfo{ 3268 inputs: []inputInfo{ 3269 {0, 239}, // AX CX DX BX BP SI DI 3270 }, 3271 outputs: []outputInfo{ 3272 {0, 239}, // AX CX DX BX BP SI DI 3273 }, 3274 }, 3275 }, 3276 { 3277 name: "BSRW", 3278 argLen: 1, 3279 clobberFlags: true, 3280 asm: x86.ABSRW, 3281 reg: regInfo{ 3282 inputs: []inputInfo{ 3283 {0, 239}, // AX CX DX BX BP SI DI 3284 }, 3285 outputs: []outputInfo{ 3286 {0, 239}, // AX CX DX BX BP SI DI 3287 }, 3288 }, 3289 }, 3290 { 3291 name: "BSWAPL", 3292 argLen: 1, 3293 resultInArg0: true, 3294 clobberFlags: true, 3295 asm: x86.ABSWAPL, 3296 reg: regInfo{ 3297 inputs: []inputInfo{ 3298 {0, 239}, // AX CX DX BX BP SI DI 3299 }, 3300 outputs: []outputInfo{ 3301 {0, 239}, // AX CX DX BX BP SI DI 3302 }, 3303 }, 3304 }, 3305 { 3306 name: "SQRTSD", 3307 argLen: 1, 3308 asm: x86.ASQRTSD, 3309 reg: regInfo{ 3310 inputs: []inputInfo{ 3311 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3312 }, 3313 outputs: []outputInfo{ 3314 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3315 }, 3316 }, 3317 }, 3318 { 3319 name: "SBBLcarrymask", 3320 argLen: 1, 3321 asm: x86.ASBBL, 3322 reg: regInfo{ 3323 outputs: []outputInfo{ 3324 {0, 239}, // AX CX DX BX BP SI DI 3325 }, 3326 }, 3327 }, 3328 { 3329 name: "SETEQ", 3330 argLen: 1, 3331 asm: x86.ASETEQ, 3332 reg: regInfo{ 3333 outputs: []outputInfo{ 3334 {0, 239}, // AX CX DX BX BP SI DI 3335 }, 3336 }, 3337 }, 3338 { 3339 name: "SETNE", 3340 argLen: 1, 3341 asm: x86.ASETNE, 3342 reg: regInfo{ 3343 outputs: []outputInfo{ 3344 {0, 239}, // AX CX DX BX BP SI DI 3345 }, 3346 }, 3347 }, 3348 { 3349 name: "SETL", 3350 argLen: 1, 3351 asm: x86.ASETLT, 3352 reg: regInfo{ 3353 outputs: []outputInfo{ 3354 {0, 239}, // AX CX DX BX BP SI DI 3355 }, 3356 }, 3357 }, 3358 { 3359 name: "SETLE", 3360 argLen: 1, 3361 asm: x86.ASETLE, 3362 reg: regInfo{ 3363 outputs: []outputInfo{ 3364 {0, 239}, // AX CX DX BX BP SI DI 3365 }, 3366 }, 3367 }, 3368 { 3369 name: "SETG", 3370 argLen: 1, 3371 asm: x86.ASETGT, 3372 reg: regInfo{ 3373 outputs: []outputInfo{ 3374 {0, 239}, // AX CX DX BX BP SI DI 3375 }, 3376 }, 3377 }, 3378 { 3379 name: "SETGE", 3380 argLen: 1, 3381 asm: x86.ASETGE, 3382 reg: regInfo{ 3383 outputs: []outputInfo{ 3384 {0, 239}, // AX CX DX BX BP SI DI 3385 }, 3386 }, 3387 }, 3388 { 3389 name: "SETB", 3390 argLen: 1, 3391 asm: x86.ASETCS, 3392 reg: regInfo{ 3393 outputs: []outputInfo{ 3394 {0, 239}, // AX CX DX BX BP SI DI 3395 }, 3396 }, 3397 }, 3398 { 3399 name: "SETBE", 3400 argLen: 1, 3401 asm: x86.ASETLS, 3402 reg: regInfo{ 3403 outputs: []outputInfo{ 3404 {0, 239}, // AX CX DX BX BP SI DI 3405 }, 3406 }, 3407 }, 3408 { 3409 name: "SETA", 3410 argLen: 1, 3411 asm: x86.ASETHI, 3412 reg: regInfo{ 3413 outputs: []outputInfo{ 3414 {0, 239}, // AX CX DX BX BP SI DI 3415 }, 3416 }, 3417 }, 3418 { 3419 name: "SETAE", 3420 argLen: 1, 3421 asm: x86.ASETCC, 3422 reg: regInfo{ 3423 outputs: []outputInfo{ 3424 {0, 239}, // AX CX DX BX BP SI DI 3425 }, 3426 }, 3427 }, 3428 { 3429 name: "SETEQF", 3430 argLen: 1, 3431 clobberFlags: true, 3432 asm: x86.ASETEQ, 3433 reg: regInfo{ 3434 clobbers: 1, // AX 3435 outputs: []outputInfo{ 3436 {0, 238}, // CX DX BX BP SI DI 3437 }, 3438 }, 3439 }, 3440 { 3441 name: "SETNEF", 3442 argLen: 1, 3443 clobberFlags: true, 3444 asm: x86.ASETNE, 3445 reg: regInfo{ 3446 clobbers: 1, // AX 3447 outputs: []outputInfo{ 3448 {0, 238}, // CX DX BX BP SI DI 3449 }, 3450 }, 3451 }, 3452 { 3453 name: "SETORD", 3454 argLen: 1, 3455 asm: x86.ASETPC, 3456 reg: regInfo{ 3457 outputs: []outputInfo{ 3458 {0, 239}, // AX CX DX BX BP SI DI 3459 }, 3460 }, 3461 }, 3462 { 3463 name: "SETNAN", 3464 argLen: 1, 3465 asm: x86.ASETPS, 3466 reg: regInfo{ 3467 outputs: []outputInfo{ 3468 {0, 239}, // AX CX DX BX BP SI DI 3469 }, 3470 }, 3471 }, 3472 { 3473 name: "SETGF", 3474 argLen: 1, 3475 asm: x86.ASETHI, 3476 reg: regInfo{ 3477 outputs: []outputInfo{ 3478 {0, 239}, // AX CX DX BX BP SI DI 3479 }, 3480 }, 3481 }, 3482 { 3483 name: "SETGEF", 3484 argLen: 1, 3485 asm: x86.ASETCC, 3486 reg: regInfo{ 3487 outputs: []outputInfo{ 3488 {0, 239}, // AX CX DX BX BP SI DI 3489 }, 3490 }, 3491 }, 3492 { 3493 name: "MOVBLSX", 3494 argLen: 1, 3495 asm: x86.AMOVBLSX, 3496 reg: regInfo{ 3497 inputs: []inputInfo{ 3498 {0, 239}, // AX CX DX BX BP SI DI 3499 }, 3500 outputs: []outputInfo{ 3501 {0, 239}, // AX CX DX BX BP SI DI 3502 }, 3503 }, 3504 }, 3505 { 3506 name: "MOVBLZX", 3507 argLen: 1, 3508 asm: x86.AMOVBLZX, 3509 reg: regInfo{ 3510 inputs: []inputInfo{ 3511 {0, 239}, // AX CX DX BX BP SI DI 3512 }, 3513 outputs: []outputInfo{ 3514 {0, 239}, // AX CX DX BX BP SI DI 3515 }, 3516 }, 3517 }, 3518 { 3519 name: "MOVWLSX", 3520 argLen: 1, 3521 asm: x86.AMOVWLSX, 3522 reg: regInfo{ 3523 inputs: []inputInfo{ 3524 {0, 239}, // AX CX DX BX BP SI DI 3525 }, 3526 outputs: []outputInfo{ 3527 {0, 239}, // AX CX DX BX BP SI DI 3528 }, 3529 }, 3530 }, 3531 { 3532 name: "MOVWLZX", 3533 argLen: 1, 3534 asm: x86.AMOVWLZX, 3535 reg: regInfo{ 3536 inputs: []inputInfo{ 3537 {0, 239}, // AX CX DX BX BP SI DI 3538 }, 3539 outputs: []outputInfo{ 3540 {0, 239}, // AX CX DX BX BP SI DI 3541 }, 3542 }, 3543 }, 3544 { 3545 name: "MOVLconst", 3546 auxType: auxInt32, 3547 argLen: 0, 3548 rematerializeable: true, 3549 asm: x86.AMOVL, 3550 reg: regInfo{ 3551 outputs: []outputInfo{ 3552 {0, 239}, // AX CX DX BX BP SI DI 3553 }, 3554 }, 3555 }, 3556 { 3557 name: "CVTTSD2SL", 3558 argLen: 1, 3559 usesScratch: true, 3560 asm: x86.ACVTTSD2SL, 3561 reg: regInfo{ 3562 inputs: []inputInfo{ 3563 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3564 }, 3565 outputs: []outputInfo{ 3566 {0, 239}, // AX CX DX BX BP SI DI 3567 }, 3568 }, 3569 }, 3570 { 3571 name: "CVTTSS2SL", 3572 argLen: 1, 3573 usesScratch: true, 3574 asm: x86.ACVTTSS2SL, 3575 reg: regInfo{ 3576 inputs: []inputInfo{ 3577 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3578 }, 3579 outputs: []outputInfo{ 3580 {0, 239}, // AX CX DX BX BP SI DI 3581 }, 3582 }, 3583 }, 3584 { 3585 name: "CVTSL2SS", 3586 argLen: 1, 3587 usesScratch: true, 3588 asm: x86.ACVTSL2SS, 3589 reg: regInfo{ 3590 inputs: []inputInfo{ 3591 {0, 239}, // AX CX DX BX BP SI DI 3592 }, 3593 outputs: []outputInfo{ 3594 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3595 }, 3596 }, 3597 }, 3598 { 3599 name: "CVTSL2SD", 3600 argLen: 1, 3601 usesScratch: true, 3602 asm: x86.ACVTSL2SD, 3603 reg: regInfo{ 3604 inputs: []inputInfo{ 3605 {0, 239}, // AX CX DX BX BP SI DI 3606 }, 3607 outputs: []outputInfo{ 3608 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3609 }, 3610 }, 3611 }, 3612 { 3613 name: "CVTSD2SS", 3614 argLen: 1, 3615 usesScratch: true, 3616 asm: x86.ACVTSD2SS, 3617 reg: regInfo{ 3618 inputs: []inputInfo{ 3619 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3620 }, 3621 outputs: []outputInfo{ 3622 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3623 }, 3624 }, 3625 }, 3626 { 3627 name: "CVTSS2SD", 3628 argLen: 1, 3629 asm: x86.ACVTSS2SD, 3630 reg: regInfo{ 3631 inputs: []inputInfo{ 3632 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3633 }, 3634 outputs: []outputInfo{ 3635 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3636 }, 3637 }, 3638 }, 3639 { 3640 name: "PXOR", 3641 argLen: 2, 3642 commutative: true, 3643 resultInArg0: true, 3644 asm: x86.APXOR, 3645 reg: regInfo{ 3646 inputs: []inputInfo{ 3647 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3648 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3649 }, 3650 outputs: []outputInfo{ 3651 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3652 }, 3653 }, 3654 }, 3655 { 3656 name: "LEAL", 3657 auxType: auxSymOff, 3658 argLen: 1, 3659 rematerializeable: true, 3660 reg: regInfo{ 3661 inputs: []inputInfo{ 3662 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3663 }, 3664 outputs: []outputInfo{ 3665 {0, 239}, // AX CX DX BX BP SI DI 3666 }, 3667 }, 3668 }, 3669 { 3670 name: "LEAL1", 3671 auxType: auxSymOff, 3672 argLen: 2, 3673 reg: regInfo{ 3674 inputs: []inputInfo{ 3675 {1, 255}, // AX CX DX BX SP BP SI DI 3676 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3677 }, 3678 outputs: []outputInfo{ 3679 {0, 239}, // AX CX DX BX BP SI DI 3680 }, 3681 }, 3682 }, 3683 { 3684 name: "LEAL2", 3685 auxType: auxSymOff, 3686 argLen: 2, 3687 reg: regInfo{ 3688 inputs: []inputInfo{ 3689 {1, 255}, // AX CX DX BX SP BP SI DI 3690 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3691 }, 3692 outputs: []outputInfo{ 3693 {0, 239}, // AX CX DX BX BP SI DI 3694 }, 3695 }, 3696 }, 3697 { 3698 name: "LEAL4", 3699 auxType: auxSymOff, 3700 argLen: 2, 3701 reg: regInfo{ 3702 inputs: []inputInfo{ 3703 {1, 255}, // AX CX DX BX SP BP SI DI 3704 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3705 }, 3706 outputs: []outputInfo{ 3707 {0, 239}, // AX CX DX BX BP SI DI 3708 }, 3709 }, 3710 }, 3711 { 3712 name: "LEAL8", 3713 auxType: auxSymOff, 3714 argLen: 2, 3715 reg: regInfo{ 3716 inputs: []inputInfo{ 3717 {1, 255}, // AX CX DX BX SP BP SI DI 3718 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3719 }, 3720 outputs: []outputInfo{ 3721 {0, 239}, // AX CX DX BX BP SI DI 3722 }, 3723 }, 3724 }, 3725 { 3726 name: "MOVBload", 3727 auxType: auxSymOff, 3728 argLen: 2, 3729 faultOnNilArg0: true, 3730 asm: x86.AMOVBLZX, 3731 reg: regInfo{ 3732 inputs: []inputInfo{ 3733 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3734 }, 3735 outputs: []outputInfo{ 3736 {0, 239}, // AX CX DX BX BP SI DI 3737 }, 3738 }, 3739 }, 3740 { 3741 name: "MOVBLSXload", 3742 auxType: auxSymOff, 3743 argLen: 2, 3744 faultOnNilArg0: true, 3745 asm: x86.AMOVBLSX, 3746 reg: regInfo{ 3747 inputs: []inputInfo{ 3748 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3749 }, 3750 outputs: []outputInfo{ 3751 {0, 239}, // AX CX DX BX BP SI DI 3752 }, 3753 }, 3754 }, 3755 { 3756 name: "MOVWload", 3757 auxType: auxSymOff, 3758 argLen: 2, 3759 faultOnNilArg0: true, 3760 asm: x86.AMOVWLZX, 3761 reg: regInfo{ 3762 inputs: []inputInfo{ 3763 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3764 }, 3765 outputs: []outputInfo{ 3766 {0, 239}, // AX CX DX BX BP SI DI 3767 }, 3768 }, 3769 }, 3770 { 3771 name: "MOVWLSXload", 3772 auxType: auxSymOff, 3773 argLen: 2, 3774 faultOnNilArg0: true, 3775 asm: x86.AMOVWLSX, 3776 reg: regInfo{ 3777 inputs: []inputInfo{ 3778 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3779 }, 3780 outputs: []outputInfo{ 3781 {0, 239}, // AX CX DX BX BP SI DI 3782 }, 3783 }, 3784 }, 3785 { 3786 name: "MOVLload", 3787 auxType: auxSymOff, 3788 argLen: 2, 3789 faultOnNilArg0: true, 3790 asm: x86.AMOVL, 3791 reg: regInfo{ 3792 inputs: []inputInfo{ 3793 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3794 }, 3795 outputs: []outputInfo{ 3796 {0, 239}, // AX CX DX BX BP SI DI 3797 }, 3798 }, 3799 }, 3800 { 3801 name: "MOVBstore", 3802 auxType: auxSymOff, 3803 argLen: 3, 3804 faultOnNilArg0: true, 3805 asm: x86.AMOVB, 3806 reg: regInfo{ 3807 inputs: []inputInfo{ 3808 {1, 255}, // AX CX DX BX SP BP SI DI 3809 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3810 }, 3811 }, 3812 }, 3813 { 3814 name: "MOVWstore", 3815 auxType: auxSymOff, 3816 argLen: 3, 3817 faultOnNilArg0: true, 3818 asm: x86.AMOVW, 3819 reg: regInfo{ 3820 inputs: []inputInfo{ 3821 {1, 255}, // AX CX DX BX SP BP SI DI 3822 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3823 }, 3824 }, 3825 }, 3826 { 3827 name: "MOVLstore", 3828 auxType: auxSymOff, 3829 argLen: 3, 3830 faultOnNilArg0: true, 3831 asm: x86.AMOVL, 3832 reg: regInfo{ 3833 inputs: []inputInfo{ 3834 {1, 255}, // AX CX DX BX SP BP SI DI 3835 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3836 }, 3837 }, 3838 }, 3839 { 3840 name: "MOVBloadidx1", 3841 auxType: auxSymOff, 3842 argLen: 3, 3843 asm: x86.AMOVBLZX, 3844 reg: regInfo{ 3845 inputs: []inputInfo{ 3846 {1, 255}, // AX CX DX BX SP BP SI DI 3847 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3848 }, 3849 outputs: []outputInfo{ 3850 {0, 239}, // AX CX DX BX BP SI DI 3851 }, 3852 }, 3853 }, 3854 { 3855 name: "MOVWloadidx1", 3856 auxType: auxSymOff, 3857 argLen: 3, 3858 asm: x86.AMOVWLZX, 3859 reg: regInfo{ 3860 inputs: []inputInfo{ 3861 {1, 255}, // AX CX DX BX SP BP SI DI 3862 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3863 }, 3864 outputs: []outputInfo{ 3865 {0, 239}, // AX CX DX BX BP SI DI 3866 }, 3867 }, 3868 }, 3869 { 3870 name: "MOVWloadidx2", 3871 auxType: auxSymOff, 3872 argLen: 3, 3873 asm: x86.AMOVWLZX, 3874 reg: regInfo{ 3875 inputs: []inputInfo{ 3876 {1, 255}, // AX CX DX BX SP BP SI DI 3877 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3878 }, 3879 outputs: []outputInfo{ 3880 {0, 239}, // AX CX DX BX BP SI DI 3881 }, 3882 }, 3883 }, 3884 { 3885 name: "MOVLloadidx1", 3886 auxType: auxSymOff, 3887 argLen: 3, 3888 asm: x86.AMOVL, 3889 reg: regInfo{ 3890 inputs: []inputInfo{ 3891 {1, 255}, // AX CX DX BX SP BP SI DI 3892 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3893 }, 3894 outputs: []outputInfo{ 3895 {0, 239}, // AX CX DX BX BP SI DI 3896 }, 3897 }, 3898 }, 3899 { 3900 name: "MOVLloadidx4", 3901 auxType: auxSymOff, 3902 argLen: 3, 3903 asm: x86.AMOVL, 3904 reg: regInfo{ 3905 inputs: []inputInfo{ 3906 {1, 255}, // AX CX DX BX SP BP SI DI 3907 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3908 }, 3909 outputs: []outputInfo{ 3910 {0, 239}, // AX CX DX BX BP SI DI 3911 }, 3912 }, 3913 }, 3914 { 3915 name: "MOVBstoreidx1", 3916 auxType: auxSymOff, 3917 argLen: 4, 3918 asm: x86.AMOVB, 3919 reg: regInfo{ 3920 inputs: []inputInfo{ 3921 {1, 255}, // AX CX DX BX SP BP SI DI 3922 {2, 255}, // AX CX DX BX SP BP SI DI 3923 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3924 }, 3925 }, 3926 }, 3927 { 3928 name: "MOVWstoreidx1", 3929 auxType: auxSymOff, 3930 argLen: 4, 3931 asm: x86.AMOVW, 3932 reg: regInfo{ 3933 inputs: []inputInfo{ 3934 {1, 255}, // AX CX DX BX SP BP SI DI 3935 {2, 255}, // AX CX DX BX SP BP SI DI 3936 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3937 }, 3938 }, 3939 }, 3940 { 3941 name: "MOVWstoreidx2", 3942 auxType: auxSymOff, 3943 argLen: 4, 3944 asm: x86.AMOVW, 3945 reg: regInfo{ 3946 inputs: []inputInfo{ 3947 {1, 255}, // AX CX DX BX SP BP SI DI 3948 {2, 255}, // AX CX DX BX SP BP SI DI 3949 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3950 }, 3951 }, 3952 }, 3953 { 3954 name: "MOVLstoreidx1", 3955 auxType: auxSymOff, 3956 argLen: 4, 3957 asm: x86.AMOVL, 3958 reg: regInfo{ 3959 inputs: []inputInfo{ 3960 {1, 255}, // AX CX DX BX SP BP SI DI 3961 {2, 255}, // AX CX DX BX SP BP SI DI 3962 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3963 }, 3964 }, 3965 }, 3966 { 3967 name: "MOVLstoreidx4", 3968 auxType: auxSymOff, 3969 argLen: 4, 3970 asm: x86.AMOVL, 3971 reg: regInfo{ 3972 inputs: []inputInfo{ 3973 {1, 255}, // AX CX DX BX SP BP SI DI 3974 {2, 255}, // AX CX DX BX SP BP SI DI 3975 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3976 }, 3977 }, 3978 }, 3979 { 3980 name: "MOVBstoreconst", 3981 auxType: auxSymValAndOff, 3982 argLen: 2, 3983 faultOnNilArg0: true, 3984 asm: x86.AMOVB, 3985 reg: regInfo{ 3986 inputs: []inputInfo{ 3987 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3988 }, 3989 }, 3990 }, 3991 { 3992 name: "MOVWstoreconst", 3993 auxType: auxSymValAndOff, 3994 argLen: 2, 3995 faultOnNilArg0: true, 3996 asm: x86.AMOVW, 3997 reg: regInfo{ 3998 inputs: []inputInfo{ 3999 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4000 }, 4001 }, 4002 }, 4003 { 4004 name: "MOVLstoreconst", 4005 auxType: auxSymValAndOff, 4006 argLen: 2, 4007 faultOnNilArg0: true, 4008 asm: x86.AMOVL, 4009 reg: regInfo{ 4010 inputs: []inputInfo{ 4011 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4012 }, 4013 }, 4014 }, 4015 { 4016 name: "MOVBstoreconstidx1", 4017 auxType: auxSymValAndOff, 4018 argLen: 3, 4019 asm: x86.AMOVB, 4020 reg: regInfo{ 4021 inputs: []inputInfo{ 4022 {1, 255}, // AX CX DX BX SP BP SI DI 4023 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4024 }, 4025 }, 4026 }, 4027 { 4028 name: "MOVWstoreconstidx1", 4029 auxType: auxSymValAndOff, 4030 argLen: 3, 4031 asm: x86.AMOVW, 4032 reg: regInfo{ 4033 inputs: []inputInfo{ 4034 {1, 255}, // AX CX DX BX SP BP SI DI 4035 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4036 }, 4037 }, 4038 }, 4039 { 4040 name: "MOVWstoreconstidx2", 4041 auxType: auxSymValAndOff, 4042 argLen: 3, 4043 asm: x86.AMOVW, 4044 reg: regInfo{ 4045 inputs: []inputInfo{ 4046 {1, 255}, // AX CX DX BX SP BP SI DI 4047 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4048 }, 4049 }, 4050 }, 4051 { 4052 name: "MOVLstoreconstidx1", 4053 auxType: auxSymValAndOff, 4054 argLen: 3, 4055 asm: x86.AMOVL, 4056 reg: regInfo{ 4057 inputs: []inputInfo{ 4058 {1, 255}, // AX CX DX BX SP BP SI DI 4059 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4060 }, 4061 }, 4062 }, 4063 { 4064 name: "MOVLstoreconstidx4", 4065 auxType: auxSymValAndOff, 4066 argLen: 3, 4067 asm: x86.AMOVL, 4068 reg: regInfo{ 4069 inputs: []inputInfo{ 4070 {1, 255}, // AX CX DX BX SP BP SI DI 4071 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4072 }, 4073 }, 4074 }, 4075 { 4076 name: "DUFFZERO", 4077 auxType: auxInt64, 4078 argLen: 3, 4079 faultOnNilArg0: true, 4080 reg: regInfo{ 4081 inputs: []inputInfo{ 4082 {0, 128}, // DI 4083 {1, 1}, // AX 4084 }, 4085 clobbers: 130, // CX DI 4086 }, 4087 }, 4088 { 4089 name: "REPSTOSL", 4090 argLen: 4, 4091 faultOnNilArg0: true, 4092 reg: regInfo{ 4093 inputs: []inputInfo{ 4094 {0, 128}, // DI 4095 {1, 2}, // CX 4096 {2, 1}, // AX 4097 }, 4098 clobbers: 130, // CX DI 4099 }, 4100 }, 4101 { 4102 name: "CALLstatic", 4103 auxType: auxSymOff, 4104 argLen: 1, 4105 clobberFlags: true, 4106 call: true, 4107 reg: regInfo{ 4108 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4109 }, 4110 }, 4111 { 4112 name: "CALLclosure", 4113 auxType: auxInt64, 4114 argLen: 3, 4115 clobberFlags: true, 4116 call: true, 4117 reg: regInfo{ 4118 inputs: []inputInfo{ 4119 {1, 4}, // DX 4120 {0, 255}, // AX CX DX BX SP BP SI DI 4121 }, 4122 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4123 }, 4124 }, 4125 { 4126 name: "CALLdefer", 4127 auxType: auxInt64, 4128 argLen: 1, 4129 clobberFlags: true, 4130 call: true, 4131 reg: regInfo{ 4132 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4133 }, 4134 }, 4135 { 4136 name: "CALLgo", 4137 auxType: auxInt64, 4138 argLen: 1, 4139 clobberFlags: true, 4140 call: true, 4141 reg: regInfo{ 4142 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4143 }, 4144 }, 4145 { 4146 name: "CALLinter", 4147 auxType: auxInt64, 4148 argLen: 2, 4149 clobberFlags: true, 4150 call: true, 4151 reg: regInfo{ 4152 inputs: []inputInfo{ 4153 {0, 239}, // AX CX DX BX BP SI DI 4154 }, 4155 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4156 }, 4157 }, 4158 { 4159 name: "DUFFCOPY", 4160 auxType: auxInt64, 4161 argLen: 3, 4162 clobberFlags: true, 4163 faultOnNilArg0: true, 4164 faultOnNilArg1: true, 4165 reg: regInfo{ 4166 inputs: []inputInfo{ 4167 {0, 128}, // DI 4168 {1, 64}, // SI 4169 }, 4170 clobbers: 194, // CX SI DI 4171 }, 4172 }, 4173 { 4174 name: "REPMOVSL", 4175 argLen: 4, 4176 faultOnNilArg0: true, 4177 faultOnNilArg1: true, 4178 reg: regInfo{ 4179 inputs: []inputInfo{ 4180 {0, 128}, // DI 4181 {1, 64}, // SI 4182 {2, 2}, // CX 4183 }, 4184 clobbers: 194, // CX SI DI 4185 }, 4186 }, 4187 { 4188 name: "InvertFlags", 4189 argLen: 1, 4190 reg: regInfo{}, 4191 }, 4192 { 4193 name: "LoweredGetG", 4194 argLen: 1, 4195 reg: regInfo{ 4196 outputs: []outputInfo{ 4197 {0, 239}, // AX CX DX BX BP SI DI 4198 }, 4199 }, 4200 }, 4201 { 4202 name: "LoweredGetClosurePtr", 4203 argLen: 0, 4204 reg: regInfo{ 4205 outputs: []outputInfo{ 4206 {0, 4}, // DX 4207 }, 4208 }, 4209 }, 4210 { 4211 name: "LoweredNilCheck", 4212 argLen: 2, 4213 clobberFlags: true, 4214 nilCheck: true, 4215 faultOnNilArg0: true, 4216 reg: regInfo{ 4217 inputs: []inputInfo{ 4218 {0, 255}, // AX CX DX BX SP BP SI DI 4219 }, 4220 }, 4221 }, 4222 { 4223 name: "MOVLconvert", 4224 argLen: 2, 4225 asm: x86.AMOVL, 4226 reg: regInfo{ 4227 inputs: []inputInfo{ 4228 {0, 239}, // AX CX DX BX BP SI DI 4229 }, 4230 outputs: []outputInfo{ 4231 {0, 239}, // AX CX DX BX BP SI DI 4232 }, 4233 }, 4234 }, 4235 { 4236 name: "FlagEQ", 4237 argLen: 0, 4238 reg: regInfo{}, 4239 }, 4240 { 4241 name: "FlagLT_ULT", 4242 argLen: 0, 4243 reg: regInfo{}, 4244 }, 4245 { 4246 name: "FlagLT_UGT", 4247 argLen: 0, 4248 reg: regInfo{}, 4249 }, 4250 { 4251 name: "FlagGT_UGT", 4252 argLen: 0, 4253 reg: regInfo{}, 4254 }, 4255 { 4256 name: "FlagGT_ULT", 4257 argLen: 0, 4258 reg: regInfo{}, 4259 }, 4260 { 4261 name: "FCHS", 4262 argLen: 1, 4263 reg: regInfo{ 4264 inputs: []inputInfo{ 4265 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4266 }, 4267 outputs: []outputInfo{ 4268 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4269 }, 4270 }, 4271 }, 4272 { 4273 name: "MOVSSconst1", 4274 auxType: auxFloat32, 4275 argLen: 0, 4276 reg: regInfo{ 4277 outputs: []outputInfo{ 4278 {0, 239}, // AX CX DX BX BP SI DI 4279 }, 4280 }, 4281 }, 4282 { 4283 name: "MOVSDconst1", 4284 auxType: auxFloat64, 4285 argLen: 0, 4286 reg: regInfo{ 4287 outputs: []outputInfo{ 4288 {0, 239}, // AX CX DX BX BP SI DI 4289 }, 4290 }, 4291 }, 4292 { 4293 name: "MOVSSconst2", 4294 argLen: 1, 4295 asm: x86.AMOVSS, 4296 reg: regInfo{ 4297 inputs: []inputInfo{ 4298 {0, 239}, // AX CX DX BX BP SI DI 4299 }, 4300 outputs: []outputInfo{ 4301 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4302 }, 4303 }, 4304 }, 4305 { 4306 name: "MOVSDconst2", 4307 argLen: 1, 4308 asm: x86.AMOVSD, 4309 reg: regInfo{ 4310 inputs: []inputInfo{ 4311 {0, 239}, // AX CX DX BX BP SI DI 4312 }, 4313 outputs: []outputInfo{ 4314 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4315 }, 4316 }, 4317 }, 4318 4319 { 4320 name: "ADDSS", 4321 argLen: 2, 4322 commutative: true, 4323 resultInArg0: true, 4324 asm: x86.AADDSS, 4325 reg: regInfo{ 4326 inputs: []inputInfo{ 4327 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4328 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4329 }, 4330 outputs: []outputInfo{ 4331 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4332 }, 4333 }, 4334 }, 4335 { 4336 name: "ADDSD", 4337 argLen: 2, 4338 commutative: true, 4339 resultInArg0: true, 4340 asm: x86.AADDSD, 4341 reg: regInfo{ 4342 inputs: []inputInfo{ 4343 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4344 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4345 }, 4346 outputs: []outputInfo{ 4347 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4348 }, 4349 }, 4350 }, 4351 { 4352 name: "SUBSS", 4353 argLen: 2, 4354 resultInArg0: true, 4355 asm: x86.ASUBSS, 4356 reg: regInfo{ 4357 inputs: []inputInfo{ 4358 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4359 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4360 }, 4361 outputs: []outputInfo{ 4362 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4363 }, 4364 }, 4365 }, 4366 { 4367 name: "SUBSD", 4368 argLen: 2, 4369 resultInArg0: true, 4370 asm: x86.ASUBSD, 4371 reg: regInfo{ 4372 inputs: []inputInfo{ 4373 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4374 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4375 }, 4376 outputs: []outputInfo{ 4377 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4378 }, 4379 }, 4380 }, 4381 { 4382 name: "MULSS", 4383 argLen: 2, 4384 commutative: true, 4385 resultInArg0: true, 4386 asm: x86.AMULSS, 4387 reg: regInfo{ 4388 inputs: []inputInfo{ 4389 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4390 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4391 }, 4392 outputs: []outputInfo{ 4393 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4394 }, 4395 }, 4396 }, 4397 { 4398 name: "MULSD", 4399 argLen: 2, 4400 commutative: true, 4401 resultInArg0: true, 4402 asm: x86.AMULSD, 4403 reg: regInfo{ 4404 inputs: []inputInfo{ 4405 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4406 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4407 }, 4408 outputs: []outputInfo{ 4409 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4410 }, 4411 }, 4412 }, 4413 { 4414 name: "DIVSS", 4415 argLen: 2, 4416 resultInArg0: true, 4417 asm: x86.ADIVSS, 4418 reg: regInfo{ 4419 inputs: []inputInfo{ 4420 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4421 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4422 }, 4423 outputs: []outputInfo{ 4424 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4425 }, 4426 }, 4427 }, 4428 { 4429 name: "DIVSD", 4430 argLen: 2, 4431 resultInArg0: true, 4432 asm: x86.ADIVSD, 4433 reg: regInfo{ 4434 inputs: []inputInfo{ 4435 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4436 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4437 }, 4438 outputs: []outputInfo{ 4439 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4440 }, 4441 }, 4442 }, 4443 { 4444 name: "MOVSSload", 4445 auxType: auxSymOff, 4446 argLen: 2, 4447 faultOnNilArg0: true, 4448 asm: x86.AMOVSS, 4449 reg: regInfo{ 4450 inputs: []inputInfo{ 4451 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4452 }, 4453 outputs: []outputInfo{ 4454 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4455 }, 4456 }, 4457 }, 4458 { 4459 name: "MOVSDload", 4460 auxType: auxSymOff, 4461 argLen: 2, 4462 faultOnNilArg0: true, 4463 asm: x86.AMOVSD, 4464 reg: regInfo{ 4465 inputs: []inputInfo{ 4466 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4467 }, 4468 outputs: []outputInfo{ 4469 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4470 }, 4471 }, 4472 }, 4473 { 4474 name: "MOVSSconst", 4475 auxType: auxFloat32, 4476 argLen: 0, 4477 rematerializeable: true, 4478 asm: x86.AMOVSS, 4479 reg: regInfo{ 4480 outputs: []outputInfo{ 4481 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4482 }, 4483 }, 4484 }, 4485 { 4486 name: "MOVSDconst", 4487 auxType: auxFloat64, 4488 argLen: 0, 4489 rematerializeable: true, 4490 asm: x86.AMOVSD, 4491 reg: regInfo{ 4492 outputs: []outputInfo{ 4493 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4494 }, 4495 }, 4496 }, 4497 { 4498 name: "MOVSSloadidx1", 4499 auxType: auxSymOff, 4500 argLen: 3, 4501 asm: x86.AMOVSS, 4502 reg: regInfo{ 4503 inputs: []inputInfo{ 4504 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4505 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4506 }, 4507 outputs: []outputInfo{ 4508 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4509 }, 4510 }, 4511 }, 4512 { 4513 name: "MOVSSloadidx4", 4514 auxType: auxSymOff, 4515 argLen: 3, 4516 asm: x86.AMOVSS, 4517 reg: regInfo{ 4518 inputs: []inputInfo{ 4519 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4520 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4521 }, 4522 outputs: []outputInfo{ 4523 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4524 }, 4525 }, 4526 }, 4527 { 4528 name: "MOVSDloadidx1", 4529 auxType: auxSymOff, 4530 argLen: 3, 4531 asm: x86.AMOVSD, 4532 reg: regInfo{ 4533 inputs: []inputInfo{ 4534 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4535 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4536 }, 4537 outputs: []outputInfo{ 4538 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4539 }, 4540 }, 4541 }, 4542 { 4543 name: "MOVSDloadidx8", 4544 auxType: auxSymOff, 4545 argLen: 3, 4546 asm: x86.AMOVSD, 4547 reg: regInfo{ 4548 inputs: []inputInfo{ 4549 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4550 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4551 }, 4552 outputs: []outputInfo{ 4553 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4554 }, 4555 }, 4556 }, 4557 { 4558 name: "MOVSSstore", 4559 auxType: auxSymOff, 4560 argLen: 3, 4561 faultOnNilArg0: true, 4562 asm: x86.AMOVSS, 4563 reg: regInfo{ 4564 inputs: []inputInfo{ 4565 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4566 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4567 }, 4568 }, 4569 }, 4570 { 4571 name: "MOVSDstore", 4572 auxType: auxSymOff, 4573 argLen: 3, 4574 faultOnNilArg0: true, 4575 asm: x86.AMOVSD, 4576 reg: regInfo{ 4577 inputs: []inputInfo{ 4578 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4579 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4580 }, 4581 }, 4582 }, 4583 { 4584 name: "MOVSSstoreidx1", 4585 auxType: auxSymOff, 4586 argLen: 4, 4587 asm: x86.AMOVSS, 4588 reg: regInfo{ 4589 inputs: []inputInfo{ 4590 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4591 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4592 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4593 }, 4594 }, 4595 }, 4596 { 4597 name: "MOVSSstoreidx4", 4598 auxType: auxSymOff, 4599 argLen: 4, 4600 asm: x86.AMOVSS, 4601 reg: regInfo{ 4602 inputs: []inputInfo{ 4603 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4604 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4605 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4606 }, 4607 }, 4608 }, 4609 { 4610 name: "MOVSDstoreidx1", 4611 auxType: auxSymOff, 4612 argLen: 4, 4613 asm: x86.AMOVSD, 4614 reg: regInfo{ 4615 inputs: []inputInfo{ 4616 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4617 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4618 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4619 }, 4620 }, 4621 }, 4622 { 4623 name: "MOVSDstoreidx8", 4624 auxType: auxSymOff, 4625 argLen: 4, 4626 asm: x86.AMOVSD, 4627 reg: regInfo{ 4628 inputs: []inputInfo{ 4629 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4630 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4631 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4632 }, 4633 }, 4634 }, 4635 { 4636 name: "ADDQ", 4637 argLen: 2, 4638 commutative: true, 4639 clobberFlags: true, 4640 asm: x86.AADDQ, 4641 reg: regInfo{ 4642 inputs: []inputInfo{ 4643 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4644 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4645 }, 4646 outputs: []outputInfo{ 4647 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4648 }, 4649 }, 4650 }, 4651 { 4652 name: "ADDL", 4653 argLen: 2, 4654 commutative: true, 4655 clobberFlags: true, 4656 asm: x86.AADDL, 4657 reg: regInfo{ 4658 inputs: []inputInfo{ 4659 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4660 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4661 }, 4662 outputs: []outputInfo{ 4663 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4664 }, 4665 }, 4666 }, 4667 { 4668 name: "ADDQconst", 4669 auxType: auxInt64, 4670 argLen: 1, 4671 clobberFlags: true, 4672 asm: x86.AADDQ, 4673 reg: regInfo{ 4674 inputs: []inputInfo{ 4675 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4676 }, 4677 outputs: []outputInfo{ 4678 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4679 }, 4680 }, 4681 }, 4682 { 4683 name: "ADDLconst", 4684 auxType: auxInt32, 4685 argLen: 1, 4686 clobberFlags: true, 4687 asm: x86.AADDL, 4688 reg: regInfo{ 4689 inputs: []inputInfo{ 4690 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4691 }, 4692 outputs: []outputInfo{ 4693 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4694 }, 4695 }, 4696 }, 4697 { 4698 name: "SUBQ", 4699 argLen: 2, 4700 resultInArg0: true, 4701 clobberFlags: true, 4702 asm: x86.ASUBQ, 4703 reg: regInfo{ 4704 inputs: []inputInfo{ 4705 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4706 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4707 }, 4708 outputs: []outputInfo{ 4709 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4710 }, 4711 }, 4712 }, 4713 { 4714 name: "SUBL", 4715 argLen: 2, 4716 resultInArg0: true, 4717 clobberFlags: true, 4718 asm: x86.ASUBL, 4719 reg: regInfo{ 4720 inputs: []inputInfo{ 4721 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4722 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4723 }, 4724 outputs: []outputInfo{ 4725 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4726 }, 4727 }, 4728 }, 4729 { 4730 name: "SUBQconst", 4731 auxType: auxInt64, 4732 argLen: 1, 4733 resultInArg0: true, 4734 clobberFlags: true, 4735 asm: x86.ASUBQ, 4736 reg: regInfo{ 4737 inputs: []inputInfo{ 4738 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4739 }, 4740 outputs: []outputInfo{ 4741 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4742 }, 4743 }, 4744 }, 4745 { 4746 name: "SUBLconst", 4747 auxType: auxInt32, 4748 argLen: 1, 4749 resultInArg0: true, 4750 clobberFlags: true, 4751 asm: x86.ASUBL, 4752 reg: regInfo{ 4753 inputs: []inputInfo{ 4754 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4755 }, 4756 outputs: []outputInfo{ 4757 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4758 }, 4759 }, 4760 }, 4761 { 4762 name: "MULQ", 4763 argLen: 2, 4764 commutative: true, 4765 resultInArg0: true, 4766 clobberFlags: true, 4767 asm: x86.AIMULQ, 4768 reg: regInfo{ 4769 inputs: []inputInfo{ 4770 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4771 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4772 }, 4773 outputs: []outputInfo{ 4774 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4775 }, 4776 }, 4777 }, 4778 { 4779 name: "MULL", 4780 argLen: 2, 4781 commutative: true, 4782 resultInArg0: true, 4783 clobberFlags: true, 4784 asm: x86.AIMULL, 4785 reg: regInfo{ 4786 inputs: []inputInfo{ 4787 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4788 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4789 }, 4790 outputs: []outputInfo{ 4791 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4792 }, 4793 }, 4794 }, 4795 { 4796 name: "MULQconst", 4797 auxType: auxInt64, 4798 argLen: 1, 4799 resultInArg0: true, 4800 clobberFlags: true, 4801 asm: x86.AIMULQ, 4802 reg: regInfo{ 4803 inputs: []inputInfo{ 4804 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4805 }, 4806 outputs: []outputInfo{ 4807 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4808 }, 4809 }, 4810 }, 4811 { 4812 name: "MULLconst", 4813 auxType: auxInt32, 4814 argLen: 1, 4815 resultInArg0: true, 4816 clobberFlags: true, 4817 asm: x86.AIMULL, 4818 reg: regInfo{ 4819 inputs: []inputInfo{ 4820 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4821 }, 4822 outputs: []outputInfo{ 4823 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4824 }, 4825 }, 4826 }, 4827 { 4828 name: "HMULQ", 4829 argLen: 2, 4830 clobberFlags: true, 4831 asm: x86.AIMULQ, 4832 reg: regInfo{ 4833 inputs: []inputInfo{ 4834 {0, 1}, // AX 4835 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4836 }, 4837 clobbers: 1, // AX 4838 outputs: []outputInfo{ 4839 {0, 4}, // DX 4840 }, 4841 }, 4842 }, 4843 { 4844 name: "HMULL", 4845 argLen: 2, 4846 clobberFlags: true, 4847 asm: x86.AIMULL, 4848 reg: regInfo{ 4849 inputs: []inputInfo{ 4850 {0, 1}, // AX 4851 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4852 }, 4853 clobbers: 1, // AX 4854 outputs: []outputInfo{ 4855 {0, 4}, // DX 4856 }, 4857 }, 4858 }, 4859 { 4860 name: "HMULW", 4861 argLen: 2, 4862 clobberFlags: true, 4863 asm: x86.AIMULW, 4864 reg: regInfo{ 4865 inputs: []inputInfo{ 4866 {0, 1}, // AX 4867 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4868 }, 4869 clobbers: 1, // AX 4870 outputs: []outputInfo{ 4871 {0, 4}, // DX 4872 }, 4873 }, 4874 }, 4875 { 4876 name: "HMULB", 4877 argLen: 2, 4878 clobberFlags: true, 4879 asm: x86.AIMULB, 4880 reg: regInfo{ 4881 inputs: []inputInfo{ 4882 {0, 1}, // AX 4883 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4884 }, 4885 clobbers: 1, // AX 4886 outputs: []outputInfo{ 4887 {0, 4}, // DX 4888 }, 4889 }, 4890 }, 4891 { 4892 name: "HMULQU", 4893 argLen: 2, 4894 clobberFlags: true, 4895 asm: x86.AMULQ, 4896 reg: regInfo{ 4897 inputs: []inputInfo{ 4898 {0, 1}, // AX 4899 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4900 }, 4901 clobbers: 1, // AX 4902 outputs: []outputInfo{ 4903 {0, 4}, // DX 4904 }, 4905 }, 4906 }, 4907 { 4908 name: "HMULLU", 4909 argLen: 2, 4910 clobberFlags: true, 4911 asm: x86.AMULL, 4912 reg: regInfo{ 4913 inputs: []inputInfo{ 4914 {0, 1}, // AX 4915 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4916 }, 4917 clobbers: 1, // AX 4918 outputs: []outputInfo{ 4919 {0, 4}, // DX 4920 }, 4921 }, 4922 }, 4923 { 4924 name: "HMULWU", 4925 argLen: 2, 4926 clobberFlags: true, 4927 asm: x86.AMULW, 4928 reg: regInfo{ 4929 inputs: []inputInfo{ 4930 {0, 1}, // AX 4931 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4932 }, 4933 clobbers: 1, // AX 4934 outputs: []outputInfo{ 4935 {0, 4}, // DX 4936 }, 4937 }, 4938 }, 4939 { 4940 name: "HMULBU", 4941 argLen: 2, 4942 clobberFlags: true, 4943 asm: x86.AMULB, 4944 reg: regInfo{ 4945 inputs: []inputInfo{ 4946 {0, 1}, // AX 4947 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4948 }, 4949 clobbers: 1, // AX 4950 outputs: []outputInfo{ 4951 {0, 4}, // DX 4952 }, 4953 }, 4954 }, 4955 { 4956 name: "AVGQU", 4957 argLen: 2, 4958 commutative: true, 4959 resultInArg0: true, 4960 clobberFlags: true, 4961 reg: regInfo{ 4962 inputs: []inputInfo{ 4963 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4964 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4965 }, 4966 outputs: []outputInfo{ 4967 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4968 }, 4969 }, 4970 }, 4971 { 4972 name: "DIVQ", 4973 argLen: 2, 4974 clobberFlags: true, 4975 asm: x86.AIDIVQ, 4976 reg: regInfo{ 4977 inputs: []inputInfo{ 4978 {0, 1}, // AX 4979 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4980 }, 4981 outputs: []outputInfo{ 4982 {0, 1}, // AX 4983 {1, 4}, // DX 4984 }, 4985 }, 4986 }, 4987 { 4988 name: "DIVL", 4989 argLen: 2, 4990 clobberFlags: true, 4991 asm: x86.AIDIVL, 4992 reg: regInfo{ 4993 inputs: []inputInfo{ 4994 {0, 1}, // AX 4995 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4996 }, 4997 outputs: []outputInfo{ 4998 {0, 1}, // AX 4999 {1, 4}, // DX 5000 }, 5001 }, 5002 }, 5003 { 5004 name: "DIVW", 5005 argLen: 2, 5006 clobberFlags: true, 5007 asm: x86.AIDIVW, 5008 reg: regInfo{ 5009 inputs: []inputInfo{ 5010 {0, 1}, // AX 5011 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5012 }, 5013 outputs: []outputInfo{ 5014 {0, 1}, // AX 5015 {1, 4}, // DX 5016 }, 5017 }, 5018 }, 5019 { 5020 name: "DIVQU", 5021 argLen: 2, 5022 clobberFlags: true, 5023 asm: x86.ADIVQ, 5024 reg: regInfo{ 5025 inputs: []inputInfo{ 5026 {0, 1}, // AX 5027 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5028 }, 5029 outputs: []outputInfo{ 5030 {0, 1}, // AX 5031 {1, 4}, // DX 5032 }, 5033 }, 5034 }, 5035 { 5036 name: "DIVLU", 5037 argLen: 2, 5038 clobberFlags: true, 5039 asm: x86.ADIVL, 5040 reg: regInfo{ 5041 inputs: []inputInfo{ 5042 {0, 1}, // AX 5043 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5044 }, 5045 outputs: []outputInfo{ 5046 {0, 1}, // AX 5047 {1, 4}, // DX 5048 }, 5049 }, 5050 }, 5051 { 5052 name: "DIVWU", 5053 argLen: 2, 5054 clobberFlags: true, 5055 asm: x86.ADIVW, 5056 reg: regInfo{ 5057 inputs: []inputInfo{ 5058 {0, 1}, // AX 5059 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5060 }, 5061 outputs: []outputInfo{ 5062 {0, 1}, // AX 5063 {1, 4}, // DX 5064 }, 5065 }, 5066 }, 5067 { 5068 name: "MULQU2", 5069 argLen: 2, 5070 clobberFlags: true, 5071 asm: x86.AMULQ, 5072 reg: regInfo{ 5073 inputs: []inputInfo{ 5074 {0, 1}, // AX 5075 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5076 }, 5077 outputs: []outputInfo{ 5078 {0, 4}, // DX 5079 {1, 1}, // AX 5080 }, 5081 }, 5082 }, 5083 { 5084 name: "DIVQU2", 5085 argLen: 3, 5086 clobberFlags: true, 5087 asm: x86.ADIVQ, 5088 reg: regInfo{ 5089 inputs: []inputInfo{ 5090 {0, 4}, // DX 5091 {1, 1}, // AX 5092 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5093 }, 5094 outputs: []outputInfo{ 5095 {0, 1}, // AX 5096 {1, 4}, // DX 5097 }, 5098 }, 5099 }, 5100 { 5101 name: "ANDQ", 5102 argLen: 2, 5103 commutative: true, 5104 resultInArg0: true, 5105 clobberFlags: true, 5106 asm: x86.AANDQ, 5107 reg: regInfo{ 5108 inputs: []inputInfo{ 5109 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5110 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5111 }, 5112 outputs: []outputInfo{ 5113 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5114 }, 5115 }, 5116 }, 5117 { 5118 name: "ANDL", 5119 argLen: 2, 5120 commutative: true, 5121 resultInArg0: true, 5122 clobberFlags: true, 5123 asm: x86.AANDL, 5124 reg: regInfo{ 5125 inputs: []inputInfo{ 5126 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5127 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5128 }, 5129 outputs: []outputInfo{ 5130 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5131 }, 5132 }, 5133 }, 5134 { 5135 name: "ANDQconst", 5136 auxType: auxInt64, 5137 argLen: 1, 5138 resultInArg0: true, 5139 clobberFlags: true, 5140 asm: x86.AANDQ, 5141 reg: regInfo{ 5142 inputs: []inputInfo{ 5143 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5144 }, 5145 outputs: []outputInfo{ 5146 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5147 }, 5148 }, 5149 }, 5150 { 5151 name: "ANDLconst", 5152 auxType: auxInt32, 5153 argLen: 1, 5154 resultInArg0: true, 5155 clobberFlags: true, 5156 asm: x86.AANDL, 5157 reg: regInfo{ 5158 inputs: []inputInfo{ 5159 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5160 }, 5161 outputs: []outputInfo{ 5162 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5163 }, 5164 }, 5165 }, 5166 { 5167 name: "ORQ", 5168 argLen: 2, 5169 commutative: true, 5170 resultInArg0: true, 5171 clobberFlags: true, 5172 asm: x86.AORQ, 5173 reg: regInfo{ 5174 inputs: []inputInfo{ 5175 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5176 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5177 }, 5178 outputs: []outputInfo{ 5179 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5180 }, 5181 }, 5182 }, 5183 { 5184 name: "ORL", 5185 argLen: 2, 5186 commutative: true, 5187 resultInArg0: true, 5188 clobberFlags: true, 5189 asm: x86.AORL, 5190 reg: regInfo{ 5191 inputs: []inputInfo{ 5192 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5193 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5194 }, 5195 outputs: []outputInfo{ 5196 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5197 }, 5198 }, 5199 }, 5200 { 5201 name: "ORQconst", 5202 auxType: auxInt64, 5203 argLen: 1, 5204 resultInArg0: true, 5205 clobberFlags: true, 5206 asm: x86.AORQ, 5207 reg: regInfo{ 5208 inputs: []inputInfo{ 5209 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5210 }, 5211 outputs: []outputInfo{ 5212 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5213 }, 5214 }, 5215 }, 5216 { 5217 name: "ORLconst", 5218 auxType: auxInt32, 5219 argLen: 1, 5220 resultInArg0: true, 5221 clobberFlags: true, 5222 asm: x86.AORL, 5223 reg: regInfo{ 5224 inputs: []inputInfo{ 5225 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5226 }, 5227 outputs: []outputInfo{ 5228 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5229 }, 5230 }, 5231 }, 5232 { 5233 name: "XORQ", 5234 argLen: 2, 5235 commutative: true, 5236 resultInArg0: true, 5237 clobberFlags: true, 5238 asm: x86.AXORQ, 5239 reg: regInfo{ 5240 inputs: []inputInfo{ 5241 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5242 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5243 }, 5244 outputs: []outputInfo{ 5245 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5246 }, 5247 }, 5248 }, 5249 { 5250 name: "XORL", 5251 argLen: 2, 5252 commutative: true, 5253 resultInArg0: true, 5254 clobberFlags: true, 5255 asm: x86.AXORL, 5256 reg: regInfo{ 5257 inputs: []inputInfo{ 5258 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5259 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5260 }, 5261 outputs: []outputInfo{ 5262 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5263 }, 5264 }, 5265 }, 5266 { 5267 name: "XORQconst", 5268 auxType: auxInt64, 5269 argLen: 1, 5270 resultInArg0: true, 5271 clobberFlags: true, 5272 asm: x86.AXORQ, 5273 reg: regInfo{ 5274 inputs: []inputInfo{ 5275 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5276 }, 5277 outputs: []outputInfo{ 5278 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5279 }, 5280 }, 5281 }, 5282 { 5283 name: "XORLconst", 5284 auxType: auxInt32, 5285 argLen: 1, 5286 resultInArg0: true, 5287 clobberFlags: true, 5288 asm: x86.AXORL, 5289 reg: regInfo{ 5290 inputs: []inputInfo{ 5291 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5292 }, 5293 outputs: []outputInfo{ 5294 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5295 }, 5296 }, 5297 }, 5298 { 5299 name: "CMPQ", 5300 argLen: 2, 5301 asm: x86.ACMPQ, 5302 reg: regInfo{ 5303 inputs: []inputInfo{ 5304 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5305 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5306 }, 5307 }, 5308 }, 5309 { 5310 name: "CMPL", 5311 argLen: 2, 5312 asm: x86.ACMPL, 5313 reg: regInfo{ 5314 inputs: []inputInfo{ 5315 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5316 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5317 }, 5318 }, 5319 }, 5320 { 5321 name: "CMPW", 5322 argLen: 2, 5323 asm: x86.ACMPW, 5324 reg: regInfo{ 5325 inputs: []inputInfo{ 5326 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5327 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5328 }, 5329 }, 5330 }, 5331 { 5332 name: "CMPB", 5333 argLen: 2, 5334 asm: x86.ACMPB, 5335 reg: regInfo{ 5336 inputs: []inputInfo{ 5337 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5338 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5339 }, 5340 }, 5341 }, 5342 { 5343 name: "CMPQconst", 5344 auxType: auxInt64, 5345 argLen: 1, 5346 asm: x86.ACMPQ, 5347 reg: regInfo{ 5348 inputs: []inputInfo{ 5349 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5350 }, 5351 }, 5352 }, 5353 { 5354 name: "CMPLconst", 5355 auxType: auxInt32, 5356 argLen: 1, 5357 asm: x86.ACMPL, 5358 reg: regInfo{ 5359 inputs: []inputInfo{ 5360 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5361 }, 5362 }, 5363 }, 5364 { 5365 name: "CMPWconst", 5366 auxType: auxInt16, 5367 argLen: 1, 5368 asm: x86.ACMPW, 5369 reg: regInfo{ 5370 inputs: []inputInfo{ 5371 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5372 }, 5373 }, 5374 }, 5375 { 5376 name: "CMPBconst", 5377 auxType: auxInt8, 5378 argLen: 1, 5379 asm: x86.ACMPB, 5380 reg: regInfo{ 5381 inputs: []inputInfo{ 5382 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5383 }, 5384 }, 5385 }, 5386 { 5387 name: "UCOMISS", 5388 argLen: 2, 5389 asm: x86.AUCOMISS, 5390 reg: regInfo{ 5391 inputs: []inputInfo{ 5392 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5393 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5394 }, 5395 }, 5396 }, 5397 { 5398 name: "UCOMISD", 5399 argLen: 2, 5400 asm: x86.AUCOMISD, 5401 reg: regInfo{ 5402 inputs: []inputInfo{ 5403 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5404 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5405 }, 5406 }, 5407 }, 5408 { 5409 name: "TESTQ", 5410 argLen: 2, 5411 asm: x86.ATESTQ, 5412 reg: regInfo{ 5413 inputs: []inputInfo{ 5414 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5415 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5416 }, 5417 }, 5418 }, 5419 { 5420 name: "TESTL", 5421 argLen: 2, 5422 asm: x86.ATESTL, 5423 reg: regInfo{ 5424 inputs: []inputInfo{ 5425 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5426 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5427 }, 5428 }, 5429 }, 5430 { 5431 name: "TESTW", 5432 argLen: 2, 5433 asm: x86.ATESTW, 5434 reg: regInfo{ 5435 inputs: []inputInfo{ 5436 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5437 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5438 }, 5439 }, 5440 }, 5441 { 5442 name: "TESTB", 5443 argLen: 2, 5444 asm: x86.ATESTB, 5445 reg: regInfo{ 5446 inputs: []inputInfo{ 5447 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5448 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5449 }, 5450 }, 5451 }, 5452 { 5453 name: "TESTQconst", 5454 auxType: auxInt64, 5455 argLen: 1, 5456 asm: x86.ATESTQ, 5457 reg: regInfo{ 5458 inputs: []inputInfo{ 5459 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5460 }, 5461 }, 5462 }, 5463 { 5464 name: "TESTLconst", 5465 auxType: auxInt32, 5466 argLen: 1, 5467 asm: x86.ATESTL, 5468 reg: regInfo{ 5469 inputs: []inputInfo{ 5470 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5471 }, 5472 }, 5473 }, 5474 { 5475 name: "TESTWconst", 5476 auxType: auxInt16, 5477 argLen: 1, 5478 asm: x86.ATESTW, 5479 reg: regInfo{ 5480 inputs: []inputInfo{ 5481 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5482 }, 5483 }, 5484 }, 5485 { 5486 name: "TESTBconst", 5487 auxType: auxInt8, 5488 argLen: 1, 5489 asm: x86.ATESTB, 5490 reg: regInfo{ 5491 inputs: []inputInfo{ 5492 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5493 }, 5494 }, 5495 }, 5496 { 5497 name: "SHLQ", 5498 argLen: 2, 5499 resultInArg0: true, 5500 clobberFlags: true, 5501 asm: x86.ASHLQ, 5502 reg: regInfo{ 5503 inputs: []inputInfo{ 5504 {1, 2}, // CX 5505 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5506 }, 5507 outputs: []outputInfo{ 5508 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5509 }, 5510 }, 5511 }, 5512 { 5513 name: "SHLL", 5514 argLen: 2, 5515 resultInArg0: true, 5516 clobberFlags: true, 5517 asm: x86.ASHLL, 5518 reg: regInfo{ 5519 inputs: []inputInfo{ 5520 {1, 2}, // CX 5521 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5522 }, 5523 outputs: []outputInfo{ 5524 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5525 }, 5526 }, 5527 }, 5528 { 5529 name: "SHLQconst", 5530 auxType: auxInt64, 5531 argLen: 1, 5532 resultInArg0: true, 5533 clobberFlags: true, 5534 asm: x86.ASHLQ, 5535 reg: regInfo{ 5536 inputs: []inputInfo{ 5537 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5538 }, 5539 outputs: []outputInfo{ 5540 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5541 }, 5542 }, 5543 }, 5544 { 5545 name: "SHLLconst", 5546 auxType: auxInt32, 5547 argLen: 1, 5548 resultInArg0: true, 5549 clobberFlags: true, 5550 asm: x86.ASHLL, 5551 reg: regInfo{ 5552 inputs: []inputInfo{ 5553 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5554 }, 5555 outputs: []outputInfo{ 5556 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5557 }, 5558 }, 5559 }, 5560 { 5561 name: "SHRQ", 5562 argLen: 2, 5563 resultInArg0: true, 5564 clobberFlags: true, 5565 asm: x86.ASHRQ, 5566 reg: regInfo{ 5567 inputs: []inputInfo{ 5568 {1, 2}, // CX 5569 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5570 }, 5571 outputs: []outputInfo{ 5572 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5573 }, 5574 }, 5575 }, 5576 { 5577 name: "SHRL", 5578 argLen: 2, 5579 resultInArg0: true, 5580 clobberFlags: true, 5581 asm: x86.ASHRL, 5582 reg: regInfo{ 5583 inputs: []inputInfo{ 5584 {1, 2}, // CX 5585 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5586 }, 5587 outputs: []outputInfo{ 5588 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5589 }, 5590 }, 5591 }, 5592 { 5593 name: "SHRW", 5594 argLen: 2, 5595 resultInArg0: true, 5596 clobberFlags: true, 5597 asm: x86.ASHRW, 5598 reg: regInfo{ 5599 inputs: []inputInfo{ 5600 {1, 2}, // CX 5601 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5602 }, 5603 outputs: []outputInfo{ 5604 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5605 }, 5606 }, 5607 }, 5608 { 5609 name: "SHRB", 5610 argLen: 2, 5611 resultInArg0: true, 5612 clobberFlags: true, 5613 asm: x86.ASHRB, 5614 reg: regInfo{ 5615 inputs: []inputInfo{ 5616 {1, 2}, // CX 5617 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5618 }, 5619 outputs: []outputInfo{ 5620 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5621 }, 5622 }, 5623 }, 5624 { 5625 name: "SHRQconst", 5626 auxType: auxInt64, 5627 argLen: 1, 5628 resultInArg0: true, 5629 clobberFlags: true, 5630 asm: x86.ASHRQ, 5631 reg: regInfo{ 5632 inputs: []inputInfo{ 5633 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5634 }, 5635 outputs: []outputInfo{ 5636 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5637 }, 5638 }, 5639 }, 5640 { 5641 name: "SHRLconst", 5642 auxType: auxInt32, 5643 argLen: 1, 5644 resultInArg0: true, 5645 clobberFlags: true, 5646 asm: x86.ASHRL, 5647 reg: regInfo{ 5648 inputs: []inputInfo{ 5649 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5650 }, 5651 outputs: []outputInfo{ 5652 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5653 }, 5654 }, 5655 }, 5656 { 5657 name: "SHRWconst", 5658 auxType: auxInt16, 5659 argLen: 1, 5660 resultInArg0: true, 5661 clobberFlags: true, 5662 asm: x86.ASHRW, 5663 reg: regInfo{ 5664 inputs: []inputInfo{ 5665 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5666 }, 5667 outputs: []outputInfo{ 5668 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5669 }, 5670 }, 5671 }, 5672 { 5673 name: "SHRBconst", 5674 auxType: auxInt8, 5675 argLen: 1, 5676 resultInArg0: true, 5677 clobberFlags: true, 5678 asm: x86.ASHRB, 5679 reg: regInfo{ 5680 inputs: []inputInfo{ 5681 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5682 }, 5683 outputs: []outputInfo{ 5684 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5685 }, 5686 }, 5687 }, 5688 { 5689 name: "SARQ", 5690 argLen: 2, 5691 resultInArg0: true, 5692 clobberFlags: true, 5693 asm: x86.ASARQ, 5694 reg: regInfo{ 5695 inputs: []inputInfo{ 5696 {1, 2}, // CX 5697 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5698 }, 5699 outputs: []outputInfo{ 5700 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5701 }, 5702 }, 5703 }, 5704 { 5705 name: "SARL", 5706 argLen: 2, 5707 resultInArg0: true, 5708 clobberFlags: true, 5709 asm: x86.ASARL, 5710 reg: regInfo{ 5711 inputs: []inputInfo{ 5712 {1, 2}, // CX 5713 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5714 }, 5715 outputs: []outputInfo{ 5716 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5717 }, 5718 }, 5719 }, 5720 { 5721 name: "SARW", 5722 argLen: 2, 5723 resultInArg0: true, 5724 clobberFlags: true, 5725 asm: x86.ASARW, 5726 reg: regInfo{ 5727 inputs: []inputInfo{ 5728 {1, 2}, // CX 5729 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5730 }, 5731 outputs: []outputInfo{ 5732 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5733 }, 5734 }, 5735 }, 5736 { 5737 name: "SARB", 5738 argLen: 2, 5739 resultInArg0: true, 5740 clobberFlags: true, 5741 asm: x86.ASARB, 5742 reg: regInfo{ 5743 inputs: []inputInfo{ 5744 {1, 2}, // CX 5745 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5746 }, 5747 outputs: []outputInfo{ 5748 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5749 }, 5750 }, 5751 }, 5752 { 5753 name: "SARQconst", 5754 auxType: auxInt64, 5755 argLen: 1, 5756 resultInArg0: true, 5757 clobberFlags: true, 5758 asm: x86.ASARQ, 5759 reg: regInfo{ 5760 inputs: []inputInfo{ 5761 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5762 }, 5763 outputs: []outputInfo{ 5764 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5765 }, 5766 }, 5767 }, 5768 { 5769 name: "SARLconst", 5770 auxType: auxInt32, 5771 argLen: 1, 5772 resultInArg0: true, 5773 clobberFlags: true, 5774 asm: x86.ASARL, 5775 reg: regInfo{ 5776 inputs: []inputInfo{ 5777 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5778 }, 5779 outputs: []outputInfo{ 5780 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5781 }, 5782 }, 5783 }, 5784 { 5785 name: "SARWconst", 5786 auxType: auxInt16, 5787 argLen: 1, 5788 resultInArg0: true, 5789 clobberFlags: true, 5790 asm: x86.ASARW, 5791 reg: regInfo{ 5792 inputs: []inputInfo{ 5793 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5794 }, 5795 outputs: []outputInfo{ 5796 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5797 }, 5798 }, 5799 }, 5800 { 5801 name: "SARBconst", 5802 auxType: auxInt8, 5803 argLen: 1, 5804 resultInArg0: true, 5805 clobberFlags: true, 5806 asm: x86.ASARB, 5807 reg: regInfo{ 5808 inputs: []inputInfo{ 5809 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5810 }, 5811 outputs: []outputInfo{ 5812 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5813 }, 5814 }, 5815 }, 5816 { 5817 name: "ROLQconst", 5818 auxType: auxInt64, 5819 argLen: 1, 5820 resultInArg0: true, 5821 clobberFlags: true, 5822 asm: x86.AROLQ, 5823 reg: regInfo{ 5824 inputs: []inputInfo{ 5825 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5826 }, 5827 outputs: []outputInfo{ 5828 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5829 }, 5830 }, 5831 }, 5832 { 5833 name: "ROLLconst", 5834 auxType: auxInt32, 5835 argLen: 1, 5836 resultInArg0: true, 5837 clobberFlags: true, 5838 asm: x86.AROLL, 5839 reg: regInfo{ 5840 inputs: []inputInfo{ 5841 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5842 }, 5843 outputs: []outputInfo{ 5844 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5845 }, 5846 }, 5847 }, 5848 { 5849 name: "ROLWconst", 5850 auxType: auxInt16, 5851 argLen: 1, 5852 resultInArg0: true, 5853 clobberFlags: true, 5854 asm: x86.AROLW, 5855 reg: regInfo{ 5856 inputs: []inputInfo{ 5857 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5858 }, 5859 outputs: []outputInfo{ 5860 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5861 }, 5862 }, 5863 }, 5864 { 5865 name: "ROLBconst", 5866 auxType: auxInt8, 5867 argLen: 1, 5868 resultInArg0: true, 5869 clobberFlags: true, 5870 asm: x86.AROLB, 5871 reg: regInfo{ 5872 inputs: []inputInfo{ 5873 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5874 }, 5875 outputs: []outputInfo{ 5876 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5877 }, 5878 }, 5879 }, 5880 { 5881 name: "NEGQ", 5882 argLen: 1, 5883 resultInArg0: true, 5884 clobberFlags: true, 5885 asm: x86.ANEGQ, 5886 reg: regInfo{ 5887 inputs: []inputInfo{ 5888 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5889 }, 5890 outputs: []outputInfo{ 5891 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5892 }, 5893 }, 5894 }, 5895 { 5896 name: "NEGL", 5897 argLen: 1, 5898 resultInArg0: true, 5899 clobberFlags: true, 5900 asm: x86.ANEGL, 5901 reg: regInfo{ 5902 inputs: []inputInfo{ 5903 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5904 }, 5905 outputs: []outputInfo{ 5906 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5907 }, 5908 }, 5909 }, 5910 { 5911 name: "NOTQ", 5912 argLen: 1, 5913 resultInArg0: true, 5914 clobberFlags: true, 5915 asm: x86.ANOTQ, 5916 reg: regInfo{ 5917 inputs: []inputInfo{ 5918 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5919 }, 5920 outputs: []outputInfo{ 5921 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5922 }, 5923 }, 5924 }, 5925 { 5926 name: "NOTL", 5927 argLen: 1, 5928 resultInArg0: true, 5929 clobberFlags: true, 5930 asm: x86.ANOTL, 5931 reg: regInfo{ 5932 inputs: []inputInfo{ 5933 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5934 }, 5935 outputs: []outputInfo{ 5936 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5937 }, 5938 }, 5939 }, 5940 { 5941 name: "BSFQ", 5942 argLen: 1, 5943 asm: x86.ABSFQ, 5944 reg: regInfo{ 5945 inputs: []inputInfo{ 5946 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5947 }, 5948 outputs: []outputInfo{ 5949 {1, 0}, 5950 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5951 }, 5952 }, 5953 }, 5954 { 5955 name: "BSFL", 5956 argLen: 1, 5957 asm: x86.ABSFL, 5958 reg: regInfo{ 5959 inputs: []inputInfo{ 5960 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5961 }, 5962 outputs: []outputInfo{ 5963 {1, 0}, 5964 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5965 }, 5966 }, 5967 }, 5968 { 5969 name: "CMOVQEQ", 5970 argLen: 3, 5971 resultInArg0: true, 5972 asm: x86.ACMOVQEQ, 5973 reg: regInfo{ 5974 inputs: []inputInfo{ 5975 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5976 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5977 }, 5978 outputs: []outputInfo{ 5979 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5980 }, 5981 }, 5982 }, 5983 { 5984 name: "CMOVLEQ", 5985 argLen: 3, 5986 resultInArg0: true, 5987 asm: x86.ACMOVLEQ, 5988 reg: regInfo{ 5989 inputs: []inputInfo{ 5990 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5991 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5992 }, 5993 outputs: []outputInfo{ 5994 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5995 }, 5996 }, 5997 }, 5998 { 5999 name: "BSWAPQ", 6000 argLen: 1, 6001 resultInArg0: true, 6002 clobberFlags: true, 6003 asm: x86.ABSWAPQ, 6004 reg: regInfo{ 6005 inputs: []inputInfo{ 6006 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6007 }, 6008 outputs: []outputInfo{ 6009 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6010 }, 6011 }, 6012 }, 6013 { 6014 name: "BSWAPL", 6015 argLen: 1, 6016 resultInArg0: true, 6017 clobberFlags: true, 6018 asm: x86.ABSWAPL, 6019 reg: regInfo{ 6020 inputs: []inputInfo{ 6021 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6022 }, 6023 outputs: []outputInfo{ 6024 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6025 }, 6026 }, 6027 }, 6028 { 6029 name: "SQRTSD", 6030 argLen: 1, 6031 asm: x86.ASQRTSD, 6032 reg: regInfo{ 6033 inputs: []inputInfo{ 6034 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6035 }, 6036 outputs: []outputInfo{ 6037 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6038 }, 6039 }, 6040 }, 6041 { 6042 name: "SBBQcarrymask", 6043 argLen: 1, 6044 asm: x86.ASBBQ, 6045 reg: regInfo{ 6046 outputs: []outputInfo{ 6047 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6048 }, 6049 }, 6050 }, 6051 { 6052 name: "SBBLcarrymask", 6053 argLen: 1, 6054 asm: x86.ASBBL, 6055 reg: regInfo{ 6056 outputs: []outputInfo{ 6057 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6058 }, 6059 }, 6060 }, 6061 { 6062 name: "SETEQ", 6063 argLen: 1, 6064 asm: x86.ASETEQ, 6065 reg: regInfo{ 6066 outputs: []outputInfo{ 6067 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6068 }, 6069 }, 6070 }, 6071 { 6072 name: "SETNE", 6073 argLen: 1, 6074 asm: x86.ASETNE, 6075 reg: regInfo{ 6076 outputs: []outputInfo{ 6077 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6078 }, 6079 }, 6080 }, 6081 { 6082 name: "SETL", 6083 argLen: 1, 6084 asm: x86.ASETLT, 6085 reg: regInfo{ 6086 outputs: []outputInfo{ 6087 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6088 }, 6089 }, 6090 }, 6091 { 6092 name: "SETLE", 6093 argLen: 1, 6094 asm: x86.ASETLE, 6095 reg: regInfo{ 6096 outputs: []outputInfo{ 6097 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6098 }, 6099 }, 6100 }, 6101 { 6102 name: "SETG", 6103 argLen: 1, 6104 asm: x86.ASETGT, 6105 reg: regInfo{ 6106 outputs: []outputInfo{ 6107 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6108 }, 6109 }, 6110 }, 6111 { 6112 name: "SETGE", 6113 argLen: 1, 6114 asm: x86.ASETGE, 6115 reg: regInfo{ 6116 outputs: []outputInfo{ 6117 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6118 }, 6119 }, 6120 }, 6121 { 6122 name: "SETB", 6123 argLen: 1, 6124 asm: x86.ASETCS, 6125 reg: regInfo{ 6126 outputs: []outputInfo{ 6127 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6128 }, 6129 }, 6130 }, 6131 { 6132 name: "SETBE", 6133 argLen: 1, 6134 asm: x86.ASETLS, 6135 reg: regInfo{ 6136 outputs: []outputInfo{ 6137 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6138 }, 6139 }, 6140 }, 6141 { 6142 name: "SETA", 6143 argLen: 1, 6144 asm: x86.ASETHI, 6145 reg: regInfo{ 6146 outputs: []outputInfo{ 6147 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6148 }, 6149 }, 6150 }, 6151 { 6152 name: "SETAE", 6153 argLen: 1, 6154 asm: x86.ASETCC, 6155 reg: regInfo{ 6156 outputs: []outputInfo{ 6157 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6158 }, 6159 }, 6160 }, 6161 { 6162 name: "SETEQF", 6163 argLen: 1, 6164 clobberFlags: true, 6165 asm: x86.ASETEQ, 6166 reg: regInfo{ 6167 clobbers: 1, // AX 6168 outputs: []outputInfo{ 6169 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6170 }, 6171 }, 6172 }, 6173 { 6174 name: "SETNEF", 6175 argLen: 1, 6176 clobberFlags: true, 6177 asm: x86.ASETNE, 6178 reg: regInfo{ 6179 clobbers: 1, // AX 6180 outputs: []outputInfo{ 6181 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6182 }, 6183 }, 6184 }, 6185 { 6186 name: "SETORD", 6187 argLen: 1, 6188 asm: x86.ASETPC, 6189 reg: regInfo{ 6190 outputs: []outputInfo{ 6191 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6192 }, 6193 }, 6194 }, 6195 { 6196 name: "SETNAN", 6197 argLen: 1, 6198 asm: x86.ASETPS, 6199 reg: regInfo{ 6200 outputs: []outputInfo{ 6201 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6202 }, 6203 }, 6204 }, 6205 { 6206 name: "SETGF", 6207 argLen: 1, 6208 asm: x86.ASETHI, 6209 reg: regInfo{ 6210 outputs: []outputInfo{ 6211 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6212 }, 6213 }, 6214 }, 6215 { 6216 name: "SETGEF", 6217 argLen: 1, 6218 asm: x86.ASETCC, 6219 reg: regInfo{ 6220 outputs: []outputInfo{ 6221 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6222 }, 6223 }, 6224 }, 6225 { 6226 name: "MOVBQSX", 6227 argLen: 1, 6228 asm: x86.AMOVBQSX, 6229 reg: regInfo{ 6230 inputs: []inputInfo{ 6231 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6232 }, 6233 outputs: []outputInfo{ 6234 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6235 }, 6236 }, 6237 }, 6238 { 6239 name: "MOVBQZX", 6240 argLen: 1, 6241 asm: x86.AMOVBLZX, 6242 reg: regInfo{ 6243 inputs: []inputInfo{ 6244 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6245 }, 6246 outputs: []outputInfo{ 6247 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6248 }, 6249 }, 6250 }, 6251 { 6252 name: "MOVWQSX", 6253 argLen: 1, 6254 asm: x86.AMOVWQSX, 6255 reg: regInfo{ 6256 inputs: []inputInfo{ 6257 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6258 }, 6259 outputs: []outputInfo{ 6260 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6261 }, 6262 }, 6263 }, 6264 { 6265 name: "MOVWQZX", 6266 argLen: 1, 6267 asm: x86.AMOVWLZX, 6268 reg: regInfo{ 6269 inputs: []inputInfo{ 6270 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6271 }, 6272 outputs: []outputInfo{ 6273 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6274 }, 6275 }, 6276 }, 6277 { 6278 name: "MOVLQSX", 6279 argLen: 1, 6280 asm: x86.AMOVLQSX, 6281 reg: regInfo{ 6282 inputs: []inputInfo{ 6283 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6284 }, 6285 outputs: []outputInfo{ 6286 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6287 }, 6288 }, 6289 }, 6290 { 6291 name: "MOVLQZX", 6292 argLen: 1, 6293 asm: x86.AMOVL, 6294 reg: regInfo{ 6295 inputs: []inputInfo{ 6296 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6297 }, 6298 outputs: []outputInfo{ 6299 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6300 }, 6301 }, 6302 }, 6303 { 6304 name: "MOVLconst", 6305 auxType: auxInt32, 6306 argLen: 0, 6307 rematerializeable: true, 6308 asm: x86.AMOVL, 6309 reg: regInfo{ 6310 outputs: []outputInfo{ 6311 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6312 }, 6313 }, 6314 }, 6315 { 6316 name: "MOVQconst", 6317 auxType: auxInt64, 6318 argLen: 0, 6319 rematerializeable: true, 6320 asm: x86.AMOVQ, 6321 reg: regInfo{ 6322 outputs: []outputInfo{ 6323 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6324 }, 6325 }, 6326 }, 6327 { 6328 name: "CVTTSD2SL", 6329 argLen: 1, 6330 asm: x86.ACVTTSD2SL, 6331 reg: regInfo{ 6332 inputs: []inputInfo{ 6333 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6334 }, 6335 outputs: []outputInfo{ 6336 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6337 }, 6338 }, 6339 }, 6340 { 6341 name: "CVTTSD2SQ", 6342 argLen: 1, 6343 asm: x86.ACVTTSD2SQ, 6344 reg: regInfo{ 6345 inputs: []inputInfo{ 6346 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6347 }, 6348 outputs: []outputInfo{ 6349 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6350 }, 6351 }, 6352 }, 6353 { 6354 name: "CVTTSS2SL", 6355 argLen: 1, 6356 asm: x86.ACVTTSS2SL, 6357 reg: regInfo{ 6358 inputs: []inputInfo{ 6359 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6360 }, 6361 outputs: []outputInfo{ 6362 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6363 }, 6364 }, 6365 }, 6366 { 6367 name: "CVTTSS2SQ", 6368 argLen: 1, 6369 asm: x86.ACVTTSS2SQ, 6370 reg: regInfo{ 6371 inputs: []inputInfo{ 6372 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6373 }, 6374 outputs: []outputInfo{ 6375 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6376 }, 6377 }, 6378 }, 6379 { 6380 name: "CVTSL2SS", 6381 argLen: 1, 6382 asm: x86.ACVTSL2SS, 6383 reg: regInfo{ 6384 inputs: []inputInfo{ 6385 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6386 }, 6387 outputs: []outputInfo{ 6388 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6389 }, 6390 }, 6391 }, 6392 { 6393 name: "CVTSL2SD", 6394 argLen: 1, 6395 asm: x86.ACVTSL2SD, 6396 reg: regInfo{ 6397 inputs: []inputInfo{ 6398 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6399 }, 6400 outputs: []outputInfo{ 6401 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6402 }, 6403 }, 6404 }, 6405 { 6406 name: "CVTSQ2SS", 6407 argLen: 1, 6408 asm: x86.ACVTSQ2SS, 6409 reg: regInfo{ 6410 inputs: []inputInfo{ 6411 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6412 }, 6413 outputs: []outputInfo{ 6414 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6415 }, 6416 }, 6417 }, 6418 { 6419 name: "CVTSQ2SD", 6420 argLen: 1, 6421 asm: x86.ACVTSQ2SD, 6422 reg: regInfo{ 6423 inputs: []inputInfo{ 6424 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6425 }, 6426 outputs: []outputInfo{ 6427 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6428 }, 6429 }, 6430 }, 6431 { 6432 name: "CVTSD2SS", 6433 argLen: 1, 6434 asm: x86.ACVTSD2SS, 6435 reg: regInfo{ 6436 inputs: []inputInfo{ 6437 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6438 }, 6439 outputs: []outputInfo{ 6440 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6441 }, 6442 }, 6443 }, 6444 { 6445 name: "CVTSS2SD", 6446 argLen: 1, 6447 asm: x86.ACVTSS2SD, 6448 reg: regInfo{ 6449 inputs: []inputInfo{ 6450 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6451 }, 6452 outputs: []outputInfo{ 6453 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6454 }, 6455 }, 6456 }, 6457 { 6458 name: "PXOR", 6459 argLen: 2, 6460 commutative: true, 6461 resultInArg0: true, 6462 asm: x86.APXOR, 6463 reg: regInfo{ 6464 inputs: []inputInfo{ 6465 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6466 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6467 }, 6468 outputs: []outputInfo{ 6469 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6470 }, 6471 }, 6472 }, 6473 { 6474 name: "LEAQ", 6475 auxType: auxSymOff, 6476 argLen: 1, 6477 rematerializeable: true, 6478 asm: x86.ALEAQ, 6479 reg: regInfo{ 6480 inputs: []inputInfo{ 6481 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6482 }, 6483 outputs: []outputInfo{ 6484 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6485 }, 6486 }, 6487 }, 6488 { 6489 name: "LEAQ1", 6490 auxType: auxSymOff, 6491 argLen: 2, 6492 reg: regInfo{ 6493 inputs: []inputInfo{ 6494 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6495 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6496 }, 6497 outputs: []outputInfo{ 6498 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6499 }, 6500 }, 6501 }, 6502 { 6503 name: "LEAQ2", 6504 auxType: auxSymOff, 6505 argLen: 2, 6506 reg: regInfo{ 6507 inputs: []inputInfo{ 6508 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6509 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6510 }, 6511 outputs: []outputInfo{ 6512 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6513 }, 6514 }, 6515 }, 6516 { 6517 name: "LEAQ4", 6518 auxType: auxSymOff, 6519 argLen: 2, 6520 reg: regInfo{ 6521 inputs: []inputInfo{ 6522 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6523 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6524 }, 6525 outputs: []outputInfo{ 6526 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6527 }, 6528 }, 6529 }, 6530 { 6531 name: "LEAQ8", 6532 auxType: auxSymOff, 6533 argLen: 2, 6534 reg: regInfo{ 6535 inputs: []inputInfo{ 6536 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6537 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6538 }, 6539 outputs: []outputInfo{ 6540 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6541 }, 6542 }, 6543 }, 6544 { 6545 name: "LEAL", 6546 auxType: auxSymOff, 6547 argLen: 1, 6548 rematerializeable: true, 6549 asm: x86.ALEAL, 6550 reg: regInfo{ 6551 inputs: []inputInfo{ 6552 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6553 }, 6554 outputs: []outputInfo{ 6555 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6556 }, 6557 }, 6558 }, 6559 { 6560 name: "MOVBload", 6561 auxType: auxSymOff, 6562 argLen: 2, 6563 faultOnNilArg0: true, 6564 asm: x86.AMOVBLZX, 6565 reg: regInfo{ 6566 inputs: []inputInfo{ 6567 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6568 }, 6569 outputs: []outputInfo{ 6570 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6571 }, 6572 }, 6573 }, 6574 { 6575 name: "MOVBQSXload", 6576 auxType: auxSymOff, 6577 argLen: 2, 6578 faultOnNilArg0: true, 6579 asm: x86.AMOVBQSX, 6580 reg: regInfo{ 6581 inputs: []inputInfo{ 6582 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6583 }, 6584 outputs: []outputInfo{ 6585 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6586 }, 6587 }, 6588 }, 6589 { 6590 name: "MOVWload", 6591 auxType: auxSymOff, 6592 argLen: 2, 6593 faultOnNilArg0: true, 6594 asm: x86.AMOVWLZX, 6595 reg: regInfo{ 6596 inputs: []inputInfo{ 6597 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6598 }, 6599 outputs: []outputInfo{ 6600 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6601 }, 6602 }, 6603 }, 6604 { 6605 name: "MOVWQSXload", 6606 auxType: auxSymOff, 6607 argLen: 2, 6608 faultOnNilArg0: true, 6609 asm: x86.AMOVWQSX, 6610 reg: regInfo{ 6611 inputs: []inputInfo{ 6612 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6613 }, 6614 outputs: []outputInfo{ 6615 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6616 }, 6617 }, 6618 }, 6619 { 6620 name: "MOVLload", 6621 auxType: auxSymOff, 6622 argLen: 2, 6623 faultOnNilArg0: true, 6624 asm: x86.AMOVL, 6625 reg: regInfo{ 6626 inputs: []inputInfo{ 6627 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6628 }, 6629 outputs: []outputInfo{ 6630 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6631 }, 6632 }, 6633 }, 6634 { 6635 name: "MOVLQSXload", 6636 auxType: auxSymOff, 6637 argLen: 2, 6638 faultOnNilArg0: true, 6639 asm: x86.AMOVLQSX, 6640 reg: regInfo{ 6641 inputs: []inputInfo{ 6642 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6643 }, 6644 outputs: []outputInfo{ 6645 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6646 }, 6647 }, 6648 }, 6649 { 6650 name: "MOVQload", 6651 auxType: auxSymOff, 6652 argLen: 2, 6653 faultOnNilArg0: true, 6654 asm: x86.AMOVQ, 6655 reg: regInfo{ 6656 inputs: []inputInfo{ 6657 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6658 }, 6659 outputs: []outputInfo{ 6660 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6661 }, 6662 }, 6663 }, 6664 { 6665 name: "MOVBstore", 6666 auxType: auxSymOff, 6667 argLen: 3, 6668 faultOnNilArg0: true, 6669 asm: x86.AMOVB, 6670 reg: regInfo{ 6671 inputs: []inputInfo{ 6672 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6673 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6674 }, 6675 }, 6676 }, 6677 { 6678 name: "MOVWstore", 6679 auxType: auxSymOff, 6680 argLen: 3, 6681 faultOnNilArg0: true, 6682 asm: x86.AMOVW, 6683 reg: regInfo{ 6684 inputs: []inputInfo{ 6685 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6686 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6687 }, 6688 }, 6689 }, 6690 { 6691 name: "MOVLstore", 6692 auxType: auxSymOff, 6693 argLen: 3, 6694 faultOnNilArg0: true, 6695 asm: x86.AMOVL, 6696 reg: regInfo{ 6697 inputs: []inputInfo{ 6698 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6699 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6700 }, 6701 }, 6702 }, 6703 { 6704 name: "MOVQstore", 6705 auxType: auxSymOff, 6706 argLen: 3, 6707 faultOnNilArg0: true, 6708 asm: x86.AMOVQ, 6709 reg: regInfo{ 6710 inputs: []inputInfo{ 6711 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6712 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6713 }, 6714 }, 6715 }, 6716 { 6717 name: "MOVOload", 6718 auxType: auxSymOff, 6719 argLen: 2, 6720 faultOnNilArg0: true, 6721 asm: x86.AMOVUPS, 6722 reg: regInfo{ 6723 inputs: []inputInfo{ 6724 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6725 }, 6726 outputs: []outputInfo{ 6727 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6728 }, 6729 }, 6730 }, 6731 { 6732 name: "MOVOstore", 6733 auxType: auxSymOff, 6734 argLen: 3, 6735 faultOnNilArg0: true, 6736 asm: x86.AMOVUPS, 6737 reg: regInfo{ 6738 inputs: []inputInfo{ 6739 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6740 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6741 }, 6742 }, 6743 }, 6744 { 6745 name: "MOVBloadidx1", 6746 auxType: auxSymOff, 6747 argLen: 3, 6748 asm: x86.AMOVBLZX, 6749 reg: regInfo{ 6750 inputs: []inputInfo{ 6751 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6752 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6753 }, 6754 outputs: []outputInfo{ 6755 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6756 }, 6757 }, 6758 }, 6759 { 6760 name: "MOVWloadidx1", 6761 auxType: auxSymOff, 6762 argLen: 3, 6763 asm: x86.AMOVWLZX, 6764 reg: regInfo{ 6765 inputs: []inputInfo{ 6766 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6767 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6768 }, 6769 outputs: []outputInfo{ 6770 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6771 }, 6772 }, 6773 }, 6774 { 6775 name: "MOVWloadidx2", 6776 auxType: auxSymOff, 6777 argLen: 3, 6778 asm: x86.AMOVWLZX, 6779 reg: regInfo{ 6780 inputs: []inputInfo{ 6781 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6782 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6783 }, 6784 outputs: []outputInfo{ 6785 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6786 }, 6787 }, 6788 }, 6789 { 6790 name: "MOVLloadidx1", 6791 auxType: auxSymOff, 6792 argLen: 3, 6793 asm: x86.AMOVL, 6794 reg: regInfo{ 6795 inputs: []inputInfo{ 6796 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6797 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6798 }, 6799 outputs: []outputInfo{ 6800 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6801 }, 6802 }, 6803 }, 6804 { 6805 name: "MOVLloadidx4", 6806 auxType: auxSymOff, 6807 argLen: 3, 6808 asm: x86.AMOVL, 6809 reg: regInfo{ 6810 inputs: []inputInfo{ 6811 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6812 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6813 }, 6814 outputs: []outputInfo{ 6815 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6816 }, 6817 }, 6818 }, 6819 { 6820 name: "MOVQloadidx1", 6821 auxType: auxSymOff, 6822 argLen: 3, 6823 asm: x86.AMOVQ, 6824 reg: regInfo{ 6825 inputs: []inputInfo{ 6826 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6827 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6828 }, 6829 outputs: []outputInfo{ 6830 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6831 }, 6832 }, 6833 }, 6834 { 6835 name: "MOVQloadidx8", 6836 auxType: auxSymOff, 6837 argLen: 3, 6838 asm: x86.AMOVQ, 6839 reg: regInfo{ 6840 inputs: []inputInfo{ 6841 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6842 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6843 }, 6844 outputs: []outputInfo{ 6845 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6846 }, 6847 }, 6848 }, 6849 { 6850 name: "MOVBstoreidx1", 6851 auxType: auxSymOff, 6852 argLen: 4, 6853 asm: x86.AMOVB, 6854 reg: regInfo{ 6855 inputs: []inputInfo{ 6856 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6857 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6858 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6859 }, 6860 }, 6861 }, 6862 { 6863 name: "MOVWstoreidx1", 6864 auxType: auxSymOff, 6865 argLen: 4, 6866 asm: x86.AMOVW, 6867 reg: regInfo{ 6868 inputs: []inputInfo{ 6869 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6870 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6871 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6872 }, 6873 }, 6874 }, 6875 { 6876 name: "MOVWstoreidx2", 6877 auxType: auxSymOff, 6878 argLen: 4, 6879 asm: x86.AMOVW, 6880 reg: regInfo{ 6881 inputs: []inputInfo{ 6882 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6883 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6884 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6885 }, 6886 }, 6887 }, 6888 { 6889 name: "MOVLstoreidx1", 6890 auxType: auxSymOff, 6891 argLen: 4, 6892 asm: x86.AMOVL, 6893 reg: regInfo{ 6894 inputs: []inputInfo{ 6895 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6896 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6897 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6898 }, 6899 }, 6900 }, 6901 { 6902 name: "MOVLstoreidx4", 6903 auxType: auxSymOff, 6904 argLen: 4, 6905 asm: x86.AMOVL, 6906 reg: regInfo{ 6907 inputs: []inputInfo{ 6908 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6909 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6910 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6911 }, 6912 }, 6913 }, 6914 { 6915 name: "MOVQstoreidx1", 6916 auxType: auxSymOff, 6917 argLen: 4, 6918 asm: x86.AMOVQ, 6919 reg: regInfo{ 6920 inputs: []inputInfo{ 6921 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6922 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6923 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6924 }, 6925 }, 6926 }, 6927 { 6928 name: "MOVQstoreidx8", 6929 auxType: auxSymOff, 6930 argLen: 4, 6931 asm: x86.AMOVQ, 6932 reg: regInfo{ 6933 inputs: []inputInfo{ 6934 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6935 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6936 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6937 }, 6938 }, 6939 }, 6940 { 6941 name: "MOVBstoreconst", 6942 auxType: auxSymValAndOff, 6943 argLen: 2, 6944 faultOnNilArg0: true, 6945 asm: x86.AMOVB, 6946 reg: regInfo{ 6947 inputs: []inputInfo{ 6948 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6949 }, 6950 }, 6951 }, 6952 { 6953 name: "MOVWstoreconst", 6954 auxType: auxSymValAndOff, 6955 argLen: 2, 6956 faultOnNilArg0: true, 6957 asm: x86.AMOVW, 6958 reg: regInfo{ 6959 inputs: []inputInfo{ 6960 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6961 }, 6962 }, 6963 }, 6964 { 6965 name: "MOVLstoreconst", 6966 auxType: auxSymValAndOff, 6967 argLen: 2, 6968 faultOnNilArg0: true, 6969 asm: x86.AMOVL, 6970 reg: regInfo{ 6971 inputs: []inputInfo{ 6972 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6973 }, 6974 }, 6975 }, 6976 { 6977 name: "MOVQstoreconst", 6978 auxType: auxSymValAndOff, 6979 argLen: 2, 6980 faultOnNilArg0: true, 6981 asm: x86.AMOVQ, 6982 reg: regInfo{ 6983 inputs: []inputInfo{ 6984 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6985 }, 6986 }, 6987 }, 6988 { 6989 name: "MOVBstoreconstidx1", 6990 auxType: auxSymValAndOff, 6991 argLen: 3, 6992 asm: x86.AMOVB, 6993 reg: regInfo{ 6994 inputs: []inputInfo{ 6995 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6996 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6997 }, 6998 }, 6999 }, 7000 { 7001 name: "MOVWstoreconstidx1", 7002 auxType: auxSymValAndOff, 7003 argLen: 3, 7004 asm: x86.AMOVW, 7005 reg: regInfo{ 7006 inputs: []inputInfo{ 7007 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7008 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7009 }, 7010 }, 7011 }, 7012 { 7013 name: "MOVWstoreconstidx2", 7014 auxType: auxSymValAndOff, 7015 argLen: 3, 7016 asm: x86.AMOVW, 7017 reg: regInfo{ 7018 inputs: []inputInfo{ 7019 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7020 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7021 }, 7022 }, 7023 }, 7024 { 7025 name: "MOVLstoreconstidx1", 7026 auxType: auxSymValAndOff, 7027 argLen: 3, 7028 asm: x86.AMOVL, 7029 reg: regInfo{ 7030 inputs: []inputInfo{ 7031 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7032 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7033 }, 7034 }, 7035 }, 7036 { 7037 name: "MOVLstoreconstidx4", 7038 auxType: auxSymValAndOff, 7039 argLen: 3, 7040 asm: x86.AMOVL, 7041 reg: regInfo{ 7042 inputs: []inputInfo{ 7043 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7044 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7045 }, 7046 }, 7047 }, 7048 { 7049 name: "MOVQstoreconstidx1", 7050 auxType: auxSymValAndOff, 7051 argLen: 3, 7052 asm: x86.AMOVQ, 7053 reg: regInfo{ 7054 inputs: []inputInfo{ 7055 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7056 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7057 }, 7058 }, 7059 }, 7060 { 7061 name: "MOVQstoreconstidx8", 7062 auxType: auxSymValAndOff, 7063 argLen: 3, 7064 asm: x86.AMOVQ, 7065 reg: regInfo{ 7066 inputs: []inputInfo{ 7067 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7068 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7069 }, 7070 }, 7071 }, 7072 { 7073 name: "DUFFZERO", 7074 auxType: auxInt64, 7075 argLen: 3, 7076 clobberFlags: true, 7077 faultOnNilArg0: true, 7078 reg: regInfo{ 7079 inputs: []inputInfo{ 7080 {0, 128}, // DI 7081 {1, 65536}, // X0 7082 }, 7083 clobbers: 128, // DI 7084 }, 7085 }, 7086 { 7087 name: "MOVOconst", 7088 auxType: auxInt128, 7089 argLen: 0, 7090 rematerializeable: true, 7091 reg: regInfo{ 7092 outputs: []outputInfo{ 7093 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7094 }, 7095 }, 7096 }, 7097 { 7098 name: "REPSTOSQ", 7099 argLen: 4, 7100 faultOnNilArg0: true, 7101 reg: regInfo{ 7102 inputs: []inputInfo{ 7103 {0, 128}, // DI 7104 {1, 2}, // CX 7105 {2, 1}, // AX 7106 }, 7107 clobbers: 130, // CX DI 7108 }, 7109 }, 7110 { 7111 name: "CALLstatic", 7112 auxType: auxSymOff, 7113 argLen: 1, 7114 clobberFlags: true, 7115 call: true, 7116 reg: regInfo{ 7117 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7118 }, 7119 }, 7120 { 7121 name: "CALLclosure", 7122 auxType: auxInt64, 7123 argLen: 3, 7124 clobberFlags: true, 7125 call: true, 7126 reg: regInfo{ 7127 inputs: []inputInfo{ 7128 {1, 4}, // DX 7129 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7130 }, 7131 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7132 }, 7133 }, 7134 { 7135 name: "CALLdefer", 7136 auxType: auxInt64, 7137 argLen: 1, 7138 clobberFlags: true, 7139 call: true, 7140 reg: regInfo{ 7141 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7142 }, 7143 }, 7144 { 7145 name: "CALLgo", 7146 auxType: auxInt64, 7147 argLen: 1, 7148 clobberFlags: true, 7149 call: true, 7150 reg: regInfo{ 7151 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7152 }, 7153 }, 7154 { 7155 name: "CALLinter", 7156 auxType: auxInt64, 7157 argLen: 2, 7158 clobberFlags: true, 7159 call: true, 7160 reg: regInfo{ 7161 inputs: []inputInfo{ 7162 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7163 }, 7164 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7165 }, 7166 }, 7167 { 7168 name: "DUFFCOPY", 7169 auxType: auxInt64, 7170 argLen: 3, 7171 clobberFlags: true, 7172 faultOnNilArg0: true, 7173 faultOnNilArg1: true, 7174 reg: regInfo{ 7175 inputs: []inputInfo{ 7176 {0, 128}, // DI 7177 {1, 64}, // SI 7178 }, 7179 clobbers: 65728, // SI DI X0 7180 }, 7181 }, 7182 { 7183 name: "REPMOVSQ", 7184 argLen: 4, 7185 faultOnNilArg0: true, 7186 faultOnNilArg1: true, 7187 reg: regInfo{ 7188 inputs: []inputInfo{ 7189 {0, 128}, // DI 7190 {1, 64}, // SI 7191 {2, 2}, // CX 7192 }, 7193 clobbers: 194, // CX SI DI 7194 }, 7195 }, 7196 { 7197 name: "InvertFlags", 7198 argLen: 1, 7199 reg: regInfo{}, 7200 }, 7201 { 7202 name: "LoweredGetG", 7203 argLen: 1, 7204 reg: regInfo{ 7205 outputs: []outputInfo{ 7206 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7207 }, 7208 }, 7209 }, 7210 { 7211 name: "LoweredGetClosurePtr", 7212 argLen: 0, 7213 reg: regInfo{ 7214 outputs: []outputInfo{ 7215 {0, 4}, // DX 7216 }, 7217 }, 7218 }, 7219 { 7220 name: "LoweredNilCheck", 7221 argLen: 2, 7222 clobberFlags: true, 7223 nilCheck: true, 7224 faultOnNilArg0: true, 7225 reg: regInfo{ 7226 inputs: []inputInfo{ 7227 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7228 }, 7229 }, 7230 }, 7231 { 7232 name: "MOVQconvert", 7233 argLen: 2, 7234 asm: x86.AMOVQ, 7235 reg: regInfo{ 7236 inputs: []inputInfo{ 7237 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7238 }, 7239 outputs: []outputInfo{ 7240 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7241 }, 7242 }, 7243 }, 7244 { 7245 name: "MOVLconvert", 7246 argLen: 2, 7247 asm: x86.AMOVL, 7248 reg: regInfo{ 7249 inputs: []inputInfo{ 7250 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7251 }, 7252 outputs: []outputInfo{ 7253 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7254 }, 7255 }, 7256 }, 7257 { 7258 name: "FlagEQ", 7259 argLen: 0, 7260 reg: regInfo{}, 7261 }, 7262 { 7263 name: "FlagLT_ULT", 7264 argLen: 0, 7265 reg: regInfo{}, 7266 }, 7267 { 7268 name: "FlagLT_UGT", 7269 argLen: 0, 7270 reg: regInfo{}, 7271 }, 7272 { 7273 name: "FlagGT_UGT", 7274 argLen: 0, 7275 reg: regInfo{}, 7276 }, 7277 { 7278 name: "FlagGT_ULT", 7279 argLen: 0, 7280 reg: regInfo{}, 7281 }, 7282 { 7283 name: "MOVLatomicload", 7284 auxType: auxSymOff, 7285 argLen: 2, 7286 faultOnNilArg0: true, 7287 asm: x86.AMOVL, 7288 reg: regInfo{ 7289 inputs: []inputInfo{ 7290 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7291 }, 7292 outputs: []outputInfo{ 7293 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7294 }, 7295 }, 7296 }, 7297 { 7298 name: "MOVQatomicload", 7299 auxType: auxSymOff, 7300 argLen: 2, 7301 faultOnNilArg0: true, 7302 asm: x86.AMOVQ, 7303 reg: regInfo{ 7304 inputs: []inputInfo{ 7305 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7306 }, 7307 outputs: []outputInfo{ 7308 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7309 }, 7310 }, 7311 }, 7312 { 7313 name: "XCHGL", 7314 auxType: auxSymOff, 7315 argLen: 3, 7316 resultInArg0: true, 7317 faultOnNilArg1: true, 7318 asm: x86.AXCHGL, 7319 reg: regInfo{ 7320 inputs: []inputInfo{ 7321 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7322 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7323 }, 7324 outputs: []outputInfo{ 7325 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7326 }, 7327 }, 7328 }, 7329 { 7330 name: "XCHGQ", 7331 auxType: auxSymOff, 7332 argLen: 3, 7333 resultInArg0: true, 7334 faultOnNilArg1: true, 7335 asm: x86.AXCHGQ, 7336 reg: regInfo{ 7337 inputs: []inputInfo{ 7338 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7339 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7340 }, 7341 outputs: []outputInfo{ 7342 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7343 }, 7344 }, 7345 }, 7346 { 7347 name: "XADDLlock", 7348 auxType: auxSymOff, 7349 argLen: 3, 7350 resultInArg0: true, 7351 clobberFlags: true, 7352 faultOnNilArg1: true, 7353 asm: x86.AXADDL, 7354 reg: regInfo{ 7355 inputs: []inputInfo{ 7356 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7357 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7358 }, 7359 outputs: []outputInfo{ 7360 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7361 }, 7362 }, 7363 }, 7364 { 7365 name: "XADDQlock", 7366 auxType: auxSymOff, 7367 argLen: 3, 7368 resultInArg0: true, 7369 clobberFlags: true, 7370 faultOnNilArg1: true, 7371 asm: x86.AXADDQ, 7372 reg: regInfo{ 7373 inputs: []inputInfo{ 7374 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7375 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7376 }, 7377 outputs: []outputInfo{ 7378 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7379 }, 7380 }, 7381 }, 7382 { 7383 name: "AddTupleFirst32", 7384 argLen: 2, 7385 reg: regInfo{}, 7386 }, 7387 { 7388 name: "AddTupleFirst64", 7389 argLen: 2, 7390 reg: regInfo{}, 7391 }, 7392 { 7393 name: "CMPXCHGLlock", 7394 auxType: auxSymOff, 7395 argLen: 4, 7396 clobberFlags: true, 7397 faultOnNilArg0: true, 7398 asm: x86.ACMPXCHGL, 7399 reg: regInfo{ 7400 inputs: []inputInfo{ 7401 {1, 1}, // AX 7402 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7403 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7404 }, 7405 clobbers: 1, // AX 7406 outputs: []outputInfo{ 7407 {1, 0}, 7408 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7409 }, 7410 }, 7411 }, 7412 { 7413 name: "CMPXCHGQlock", 7414 auxType: auxSymOff, 7415 argLen: 4, 7416 clobberFlags: true, 7417 faultOnNilArg0: true, 7418 asm: x86.ACMPXCHGQ, 7419 reg: regInfo{ 7420 inputs: []inputInfo{ 7421 {1, 1}, // AX 7422 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7423 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7424 }, 7425 clobbers: 1, // AX 7426 outputs: []outputInfo{ 7427 {1, 0}, 7428 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7429 }, 7430 }, 7431 }, 7432 { 7433 name: "ANDBlock", 7434 auxType: auxSymOff, 7435 argLen: 3, 7436 clobberFlags: true, 7437 faultOnNilArg0: true, 7438 asm: x86.AANDB, 7439 reg: regInfo{ 7440 inputs: []inputInfo{ 7441 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7442 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7443 }, 7444 }, 7445 }, 7446 { 7447 name: "ORBlock", 7448 auxType: auxSymOff, 7449 argLen: 3, 7450 clobberFlags: true, 7451 faultOnNilArg0: true, 7452 asm: x86.AORB, 7453 reg: regInfo{ 7454 inputs: []inputInfo{ 7455 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7456 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7457 }, 7458 }, 7459 }, 7460 7461 { 7462 name: "ADD", 7463 argLen: 2, 7464 commutative: true, 7465 asm: arm.AADD, 7466 reg: regInfo{ 7467 inputs: []inputInfo{ 7468 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7469 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7470 }, 7471 outputs: []outputInfo{ 7472 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7473 }, 7474 }, 7475 }, 7476 { 7477 name: "ADDconst", 7478 auxType: auxInt32, 7479 argLen: 1, 7480 asm: arm.AADD, 7481 reg: regInfo{ 7482 inputs: []inputInfo{ 7483 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 7484 }, 7485 outputs: []outputInfo{ 7486 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7487 }, 7488 }, 7489 }, 7490 { 7491 name: "SUB", 7492 argLen: 2, 7493 asm: arm.ASUB, 7494 reg: regInfo{ 7495 inputs: []inputInfo{ 7496 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7497 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7498 }, 7499 outputs: []outputInfo{ 7500 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7501 }, 7502 }, 7503 }, 7504 { 7505 name: "SUBconst", 7506 auxType: auxInt32, 7507 argLen: 1, 7508 asm: arm.ASUB, 7509 reg: regInfo{ 7510 inputs: []inputInfo{ 7511 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7512 }, 7513 outputs: []outputInfo{ 7514 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7515 }, 7516 }, 7517 }, 7518 { 7519 name: "RSB", 7520 argLen: 2, 7521 asm: arm.ARSB, 7522 reg: regInfo{ 7523 inputs: []inputInfo{ 7524 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7525 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7526 }, 7527 outputs: []outputInfo{ 7528 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7529 }, 7530 }, 7531 }, 7532 { 7533 name: "RSBconst", 7534 auxType: auxInt32, 7535 argLen: 1, 7536 asm: arm.ARSB, 7537 reg: regInfo{ 7538 inputs: []inputInfo{ 7539 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7540 }, 7541 outputs: []outputInfo{ 7542 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7543 }, 7544 }, 7545 }, 7546 { 7547 name: "MUL", 7548 argLen: 2, 7549 commutative: true, 7550 asm: arm.AMUL, 7551 reg: regInfo{ 7552 inputs: []inputInfo{ 7553 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7554 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7555 }, 7556 outputs: []outputInfo{ 7557 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7558 }, 7559 }, 7560 }, 7561 { 7562 name: "HMUL", 7563 argLen: 2, 7564 commutative: true, 7565 asm: arm.AMULL, 7566 reg: regInfo{ 7567 inputs: []inputInfo{ 7568 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7569 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7570 }, 7571 outputs: []outputInfo{ 7572 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7573 }, 7574 }, 7575 }, 7576 { 7577 name: "HMULU", 7578 argLen: 2, 7579 commutative: true, 7580 asm: arm.AMULLU, 7581 reg: regInfo{ 7582 inputs: []inputInfo{ 7583 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7584 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7585 }, 7586 outputs: []outputInfo{ 7587 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7588 }, 7589 }, 7590 }, 7591 { 7592 name: "UDIVrtcall", 7593 argLen: 2, 7594 clobberFlags: true, 7595 reg: regInfo{ 7596 inputs: []inputInfo{ 7597 {0, 2}, // R1 7598 {1, 1}, // R0 7599 }, 7600 clobbers: 16396, // R2 R3 R14 7601 outputs: []outputInfo{ 7602 {0, 1}, // R0 7603 {1, 2}, // R1 7604 }, 7605 }, 7606 }, 7607 { 7608 name: "ADDS", 7609 argLen: 2, 7610 commutative: true, 7611 asm: arm.AADD, 7612 reg: regInfo{ 7613 inputs: []inputInfo{ 7614 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7615 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7616 }, 7617 outputs: []outputInfo{ 7618 {1, 0}, 7619 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7620 }, 7621 }, 7622 }, 7623 { 7624 name: "ADDSconst", 7625 auxType: auxInt32, 7626 argLen: 1, 7627 asm: arm.AADD, 7628 reg: regInfo{ 7629 inputs: []inputInfo{ 7630 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7631 }, 7632 outputs: []outputInfo{ 7633 {1, 0}, 7634 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7635 }, 7636 }, 7637 }, 7638 { 7639 name: "ADC", 7640 argLen: 3, 7641 commutative: true, 7642 asm: arm.AADC, 7643 reg: regInfo{ 7644 inputs: []inputInfo{ 7645 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7646 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7647 }, 7648 outputs: []outputInfo{ 7649 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7650 }, 7651 }, 7652 }, 7653 { 7654 name: "ADCconst", 7655 auxType: auxInt32, 7656 argLen: 2, 7657 asm: arm.AADC, 7658 reg: regInfo{ 7659 inputs: []inputInfo{ 7660 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7661 }, 7662 outputs: []outputInfo{ 7663 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7664 }, 7665 }, 7666 }, 7667 { 7668 name: "SUBS", 7669 argLen: 2, 7670 asm: arm.ASUB, 7671 reg: regInfo{ 7672 inputs: []inputInfo{ 7673 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7674 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7675 }, 7676 outputs: []outputInfo{ 7677 {1, 0}, 7678 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7679 }, 7680 }, 7681 }, 7682 { 7683 name: "SUBSconst", 7684 auxType: auxInt32, 7685 argLen: 1, 7686 asm: arm.ASUB, 7687 reg: regInfo{ 7688 inputs: []inputInfo{ 7689 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7690 }, 7691 outputs: []outputInfo{ 7692 {1, 0}, 7693 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7694 }, 7695 }, 7696 }, 7697 { 7698 name: "RSBSconst", 7699 auxType: auxInt32, 7700 argLen: 1, 7701 asm: arm.ARSB, 7702 reg: regInfo{ 7703 inputs: []inputInfo{ 7704 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7705 }, 7706 outputs: []outputInfo{ 7707 {1, 0}, 7708 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7709 }, 7710 }, 7711 }, 7712 { 7713 name: "SBC", 7714 argLen: 3, 7715 asm: arm.ASBC, 7716 reg: regInfo{ 7717 inputs: []inputInfo{ 7718 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7719 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7720 }, 7721 outputs: []outputInfo{ 7722 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7723 }, 7724 }, 7725 }, 7726 { 7727 name: "SBCconst", 7728 auxType: auxInt32, 7729 argLen: 2, 7730 asm: arm.ASBC, 7731 reg: regInfo{ 7732 inputs: []inputInfo{ 7733 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7734 }, 7735 outputs: []outputInfo{ 7736 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7737 }, 7738 }, 7739 }, 7740 { 7741 name: "RSCconst", 7742 auxType: auxInt32, 7743 argLen: 2, 7744 asm: arm.ARSC, 7745 reg: regInfo{ 7746 inputs: []inputInfo{ 7747 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7748 }, 7749 outputs: []outputInfo{ 7750 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7751 }, 7752 }, 7753 }, 7754 { 7755 name: "MULLU", 7756 argLen: 2, 7757 commutative: true, 7758 asm: arm.AMULLU, 7759 reg: regInfo{ 7760 inputs: []inputInfo{ 7761 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7762 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7763 }, 7764 outputs: []outputInfo{ 7765 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7766 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7767 }, 7768 }, 7769 }, 7770 { 7771 name: "MULA", 7772 argLen: 3, 7773 asm: arm.AMULA, 7774 reg: regInfo{ 7775 inputs: []inputInfo{ 7776 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7777 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7778 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7779 }, 7780 outputs: []outputInfo{ 7781 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7782 }, 7783 }, 7784 }, 7785 { 7786 name: "ADDF", 7787 argLen: 2, 7788 commutative: true, 7789 asm: arm.AADDF, 7790 reg: regInfo{ 7791 inputs: []inputInfo{ 7792 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7793 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7794 }, 7795 outputs: []outputInfo{ 7796 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7797 }, 7798 }, 7799 }, 7800 { 7801 name: "ADDD", 7802 argLen: 2, 7803 commutative: true, 7804 asm: arm.AADDD, 7805 reg: regInfo{ 7806 inputs: []inputInfo{ 7807 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7808 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7809 }, 7810 outputs: []outputInfo{ 7811 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7812 }, 7813 }, 7814 }, 7815 { 7816 name: "SUBF", 7817 argLen: 2, 7818 asm: arm.ASUBF, 7819 reg: regInfo{ 7820 inputs: []inputInfo{ 7821 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7822 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7823 }, 7824 outputs: []outputInfo{ 7825 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7826 }, 7827 }, 7828 }, 7829 { 7830 name: "SUBD", 7831 argLen: 2, 7832 asm: arm.ASUBD, 7833 reg: regInfo{ 7834 inputs: []inputInfo{ 7835 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7836 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7837 }, 7838 outputs: []outputInfo{ 7839 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7840 }, 7841 }, 7842 }, 7843 { 7844 name: "MULF", 7845 argLen: 2, 7846 commutative: true, 7847 asm: arm.AMULF, 7848 reg: regInfo{ 7849 inputs: []inputInfo{ 7850 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7851 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7852 }, 7853 outputs: []outputInfo{ 7854 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7855 }, 7856 }, 7857 }, 7858 { 7859 name: "MULD", 7860 argLen: 2, 7861 commutative: true, 7862 asm: arm.AMULD, 7863 reg: regInfo{ 7864 inputs: []inputInfo{ 7865 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7866 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7867 }, 7868 outputs: []outputInfo{ 7869 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7870 }, 7871 }, 7872 }, 7873 { 7874 name: "DIVF", 7875 argLen: 2, 7876 asm: arm.ADIVF, 7877 reg: regInfo{ 7878 inputs: []inputInfo{ 7879 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7880 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7881 }, 7882 outputs: []outputInfo{ 7883 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7884 }, 7885 }, 7886 }, 7887 { 7888 name: "DIVD", 7889 argLen: 2, 7890 asm: arm.ADIVD, 7891 reg: regInfo{ 7892 inputs: []inputInfo{ 7893 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7894 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7895 }, 7896 outputs: []outputInfo{ 7897 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7898 }, 7899 }, 7900 }, 7901 { 7902 name: "AND", 7903 argLen: 2, 7904 commutative: true, 7905 asm: arm.AAND, 7906 reg: regInfo{ 7907 inputs: []inputInfo{ 7908 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7909 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7910 }, 7911 outputs: []outputInfo{ 7912 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7913 }, 7914 }, 7915 }, 7916 { 7917 name: "ANDconst", 7918 auxType: auxInt32, 7919 argLen: 1, 7920 asm: arm.AAND, 7921 reg: regInfo{ 7922 inputs: []inputInfo{ 7923 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7924 }, 7925 outputs: []outputInfo{ 7926 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7927 }, 7928 }, 7929 }, 7930 { 7931 name: "OR", 7932 argLen: 2, 7933 commutative: true, 7934 asm: arm.AORR, 7935 reg: regInfo{ 7936 inputs: []inputInfo{ 7937 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7938 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7939 }, 7940 outputs: []outputInfo{ 7941 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7942 }, 7943 }, 7944 }, 7945 { 7946 name: "ORconst", 7947 auxType: auxInt32, 7948 argLen: 1, 7949 asm: arm.AORR, 7950 reg: regInfo{ 7951 inputs: []inputInfo{ 7952 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7953 }, 7954 outputs: []outputInfo{ 7955 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7956 }, 7957 }, 7958 }, 7959 { 7960 name: "XOR", 7961 argLen: 2, 7962 commutative: true, 7963 asm: arm.AEOR, 7964 reg: regInfo{ 7965 inputs: []inputInfo{ 7966 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7967 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7968 }, 7969 outputs: []outputInfo{ 7970 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7971 }, 7972 }, 7973 }, 7974 { 7975 name: "XORconst", 7976 auxType: auxInt32, 7977 argLen: 1, 7978 asm: arm.AEOR, 7979 reg: regInfo{ 7980 inputs: []inputInfo{ 7981 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7982 }, 7983 outputs: []outputInfo{ 7984 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7985 }, 7986 }, 7987 }, 7988 { 7989 name: "BIC", 7990 argLen: 2, 7991 asm: arm.ABIC, 7992 reg: regInfo{ 7993 inputs: []inputInfo{ 7994 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7995 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7996 }, 7997 outputs: []outputInfo{ 7998 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7999 }, 8000 }, 8001 }, 8002 { 8003 name: "BICconst", 8004 auxType: auxInt32, 8005 argLen: 1, 8006 asm: arm.ABIC, 8007 reg: regInfo{ 8008 inputs: []inputInfo{ 8009 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8010 }, 8011 outputs: []outputInfo{ 8012 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8013 }, 8014 }, 8015 }, 8016 { 8017 name: "MVN", 8018 argLen: 1, 8019 asm: arm.AMVN, 8020 reg: regInfo{ 8021 inputs: []inputInfo{ 8022 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8023 }, 8024 outputs: []outputInfo{ 8025 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8026 }, 8027 }, 8028 }, 8029 { 8030 name: "NEGF", 8031 argLen: 1, 8032 asm: arm.ANEGF, 8033 reg: regInfo{ 8034 inputs: []inputInfo{ 8035 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8036 }, 8037 outputs: []outputInfo{ 8038 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8039 }, 8040 }, 8041 }, 8042 { 8043 name: "NEGD", 8044 argLen: 1, 8045 asm: arm.ANEGD, 8046 reg: regInfo{ 8047 inputs: []inputInfo{ 8048 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8049 }, 8050 outputs: []outputInfo{ 8051 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8052 }, 8053 }, 8054 }, 8055 { 8056 name: "SQRTD", 8057 argLen: 1, 8058 asm: arm.ASQRTD, 8059 reg: regInfo{ 8060 inputs: []inputInfo{ 8061 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8062 }, 8063 outputs: []outputInfo{ 8064 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8065 }, 8066 }, 8067 }, 8068 { 8069 name: "CLZ", 8070 argLen: 1, 8071 asm: arm.ACLZ, 8072 reg: regInfo{ 8073 inputs: []inputInfo{ 8074 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8075 }, 8076 outputs: []outputInfo{ 8077 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8078 }, 8079 }, 8080 }, 8081 { 8082 name: "SLL", 8083 argLen: 2, 8084 asm: arm.ASLL, 8085 reg: regInfo{ 8086 inputs: []inputInfo{ 8087 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8088 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8089 }, 8090 outputs: []outputInfo{ 8091 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8092 }, 8093 }, 8094 }, 8095 { 8096 name: "SLLconst", 8097 auxType: auxInt32, 8098 argLen: 1, 8099 asm: arm.ASLL, 8100 reg: regInfo{ 8101 inputs: []inputInfo{ 8102 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8103 }, 8104 outputs: []outputInfo{ 8105 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8106 }, 8107 }, 8108 }, 8109 { 8110 name: "SRL", 8111 argLen: 2, 8112 asm: arm.ASRL, 8113 reg: regInfo{ 8114 inputs: []inputInfo{ 8115 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8116 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8117 }, 8118 outputs: []outputInfo{ 8119 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8120 }, 8121 }, 8122 }, 8123 { 8124 name: "SRLconst", 8125 auxType: auxInt32, 8126 argLen: 1, 8127 asm: arm.ASRL, 8128 reg: regInfo{ 8129 inputs: []inputInfo{ 8130 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8131 }, 8132 outputs: []outputInfo{ 8133 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8134 }, 8135 }, 8136 }, 8137 { 8138 name: "SRA", 8139 argLen: 2, 8140 asm: arm.ASRA, 8141 reg: regInfo{ 8142 inputs: []inputInfo{ 8143 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8144 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8145 }, 8146 outputs: []outputInfo{ 8147 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8148 }, 8149 }, 8150 }, 8151 { 8152 name: "SRAconst", 8153 auxType: auxInt32, 8154 argLen: 1, 8155 asm: arm.ASRA, 8156 reg: regInfo{ 8157 inputs: []inputInfo{ 8158 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8159 }, 8160 outputs: []outputInfo{ 8161 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8162 }, 8163 }, 8164 }, 8165 { 8166 name: "SRRconst", 8167 auxType: auxInt32, 8168 argLen: 1, 8169 reg: regInfo{ 8170 inputs: []inputInfo{ 8171 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8172 }, 8173 outputs: []outputInfo{ 8174 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8175 }, 8176 }, 8177 }, 8178 { 8179 name: "ADDshiftLL", 8180 auxType: auxInt32, 8181 argLen: 2, 8182 asm: arm.AADD, 8183 reg: regInfo{ 8184 inputs: []inputInfo{ 8185 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8186 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8187 }, 8188 outputs: []outputInfo{ 8189 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8190 }, 8191 }, 8192 }, 8193 { 8194 name: "ADDshiftRL", 8195 auxType: auxInt32, 8196 argLen: 2, 8197 asm: arm.AADD, 8198 reg: regInfo{ 8199 inputs: []inputInfo{ 8200 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8201 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8202 }, 8203 outputs: []outputInfo{ 8204 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8205 }, 8206 }, 8207 }, 8208 { 8209 name: "ADDshiftRA", 8210 auxType: auxInt32, 8211 argLen: 2, 8212 asm: arm.AADD, 8213 reg: regInfo{ 8214 inputs: []inputInfo{ 8215 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8216 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8217 }, 8218 outputs: []outputInfo{ 8219 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8220 }, 8221 }, 8222 }, 8223 { 8224 name: "SUBshiftLL", 8225 auxType: auxInt32, 8226 argLen: 2, 8227 asm: arm.ASUB, 8228 reg: regInfo{ 8229 inputs: []inputInfo{ 8230 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8231 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8232 }, 8233 outputs: []outputInfo{ 8234 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8235 }, 8236 }, 8237 }, 8238 { 8239 name: "SUBshiftRL", 8240 auxType: auxInt32, 8241 argLen: 2, 8242 asm: arm.ASUB, 8243 reg: regInfo{ 8244 inputs: []inputInfo{ 8245 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8246 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8247 }, 8248 outputs: []outputInfo{ 8249 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8250 }, 8251 }, 8252 }, 8253 { 8254 name: "SUBshiftRA", 8255 auxType: auxInt32, 8256 argLen: 2, 8257 asm: arm.ASUB, 8258 reg: regInfo{ 8259 inputs: []inputInfo{ 8260 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8261 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8262 }, 8263 outputs: []outputInfo{ 8264 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8265 }, 8266 }, 8267 }, 8268 { 8269 name: "RSBshiftLL", 8270 auxType: auxInt32, 8271 argLen: 2, 8272 asm: arm.ARSB, 8273 reg: regInfo{ 8274 inputs: []inputInfo{ 8275 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8276 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8277 }, 8278 outputs: []outputInfo{ 8279 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8280 }, 8281 }, 8282 }, 8283 { 8284 name: "RSBshiftRL", 8285 auxType: auxInt32, 8286 argLen: 2, 8287 asm: arm.ARSB, 8288 reg: regInfo{ 8289 inputs: []inputInfo{ 8290 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8291 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8292 }, 8293 outputs: []outputInfo{ 8294 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8295 }, 8296 }, 8297 }, 8298 { 8299 name: "RSBshiftRA", 8300 auxType: auxInt32, 8301 argLen: 2, 8302 asm: arm.ARSB, 8303 reg: regInfo{ 8304 inputs: []inputInfo{ 8305 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8306 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8307 }, 8308 outputs: []outputInfo{ 8309 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8310 }, 8311 }, 8312 }, 8313 { 8314 name: "ANDshiftLL", 8315 auxType: auxInt32, 8316 argLen: 2, 8317 asm: arm.AAND, 8318 reg: regInfo{ 8319 inputs: []inputInfo{ 8320 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8321 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8322 }, 8323 outputs: []outputInfo{ 8324 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8325 }, 8326 }, 8327 }, 8328 { 8329 name: "ANDshiftRL", 8330 auxType: auxInt32, 8331 argLen: 2, 8332 asm: arm.AAND, 8333 reg: regInfo{ 8334 inputs: []inputInfo{ 8335 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8336 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8337 }, 8338 outputs: []outputInfo{ 8339 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8340 }, 8341 }, 8342 }, 8343 { 8344 name: "ANDshiftRA", 8345 auxType: auxInt32, 8346 argLen: 2, 8347 asm: arm.AAND, 8348 reg: regInfo{ 8349 inputs: []inputInfo{ 8350 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8351 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8352 }, 8353 outputs: []outputInfo{ 8354 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8355 }, 8356 }, 8357 }, 8358 { 8359 name: "ORshiftLL", 8360 auxType: auxInt32, 8361 argLen: 2, 8362 asm: arm.AORR, 8363 reg: regInfo{ 8364 inputs: []inputInfo{ 8365 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8366 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8367 }, 8368 outputs: []outputInfo{ 8369 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8370 }, 8371 }, 8372 }, 8373 { 8374 name: "ORshiftRL", 8375 auxType: auxInt32, 8376 argLen: 2, 8377 asm: arm.AORR, 8378 reg: regInfo{ 8379 inputs: []inputInfo{ 8380 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8381 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8382 }, 8383 outputs: []outputInfo{ 8384 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8385 }, 8386 }, 8387 }, 8388 { 8389 name: "ORshiftRA", 8390 auxType: auxInt32, 8391 argLen: 2, 8392 asm: arm.AORR, 8393 reg: regInfo{ 8394 inputs: []inputInfo{ 8395 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8396 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8397 }, 8398 outputs: []outputInfo{ 8399 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8400 }, 8401 }, 8402 }, 8403 { 8404 name: "XORshiftLL", 8405 auxType: auxInt32, 8406 argLen: 2, 8407 asm: arm.AEOR, 8408 reg: regInfo{ 8409 inputs: []inputInfo{ 8410 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8411 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8412 }, 8413 outputs: []outputInfo{ 8414 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8415 }, 8416 }, 8417 }, 8418 { 8419 name: "XORshiftRL", 8420 auxType: auxInt32, 8421 argLen: 2, 8422 asm: arm.AEOR, 8423 reg: regInfo{ 8424 inputs: []inputInfo{ 8425 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8426 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8427 }, 8428 outputs: []outputInfo{ 8429 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8430 }, 8431 }, 8432 }, 8433 { 8434 name: "XORshiftRA", 8435 auxType: auxInt32, 8436 argLen: 2, 8437 asm: arm.AEOR, 8438 reg: regInfo{ 8439 inputs: []inputInfo{ 8440 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8441 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8442 }, 8443 outputs: []outputInfo{ 8444 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8445 }, 8446 }, 8447 }, 8448 { 8449 name: "XORshiftRR", 8450 auxType: auxInt32, 8451 argLen: 2, 8452 asm: arm.AEOR, 8453 reg: regInfo{ 8454 inputs: []inputInfo{ 8455 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8456 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8457 }, 8458 outputs: []outputInfo{ 8459 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8460 }, 8461 }, 8462 }, 8463 { 8464 name: "BICshiftLL", 8465 auxType: auxInt32, 8466 argLen: 2, 8467 asm: arm.ABIC, 8468 reg: regInfo{ 8469 inputs: []inputInfo{ 8470 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8471 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8472 }, 8473 outputs: []outputInfo{ 8474 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8475 }, 8476 }, 8477 }, 8478 { 8479 name: "BICshiftRL", 8480 auxType: auxInt32, 8481 argLen: 2, 8482 asm: arm.ABIC, 8483 reg: regInfo{ 8484 inputs: []inputInfo{ 8485 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8486 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8487 }, 8488 outputs: []outputInfo{ 8489 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8490 }, 8491 }, 8492 }, 8493 { 8494 name: "BICshiftRA", 8495 auxType: auxInt32, 8496 argLen: 2, 8497 asm: arm.ABIC, 8498 reg: regInfo{ 8499 inputs: []inputInfo{ 8500 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8501 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8502 }, 8503 outputs: []outputInfo{ 8504 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8505 }, 8506 }, 8507 }, 8508 { 8509 name: "MVNshiftLL", 8510 auxType: auxInt32, 8511 argLen: 1, 8512 asm: arm.AMVN, 8513 reg: regInfo{ 8514 inputs: []inputInfo{ 8515 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8516 }, 8517 outputs: []outputInfo{ 8518 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8519 }, 8520 }, 8521 }, 8522 { 8523 name: "MVNshiftRL", 8524 auxType: auxInt32, 8525 argLen: 1, 8526 asm: arm.AMVN, 8527 reg: regInfo{ 8528 inputs: []inputInfo{ 8529 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8530 }, 8531 outputs: []outputInfo{ 8532 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8533 }, 8534 }, 8535 }, 8536 { 8537 name: "MVNshiftRA", 8538 auxType: auxInt32, 8539 argLen: 1, 8540 asm: arm.AMVN, 8541 reg: regInfo{ 8542 inputs: []inputInfo{ 8543 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8544 }, 8545 outputs: []outputInfo{ 8546 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8547 }, 8548 }, 8549 }, 8550 { 8551 name: "ADCshiftLL", 8552 auxType: auxInt32, 8553 argLen: 3, 8554 asm: arm.AADC, 8555 reg: regInfo{ 8556 inputs: []inputInfo{ 8557 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8558 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8559 }, 8560 outputs: []outputInfo{ 8561 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8562 }, 8563 }, 8564 }, 8565 { 8566 name: "ADCshiftRL", 8567 auxType: auxInt32, 8568 argLen: 3, 8569 asm: arm.AADC, 8570 reg: regInfo{ 8571 inputs: []inputInfo{ 8572 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8573 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8574 }, 8575 outputs: []outputInfo{ 8576 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8577 }, 8578 }, 8579 }, 8580 { 8581 name: "ADCshiftRA", 8582 auxType: auxInt32, 8583 argLen: 3, 8584 asm: arm.AADC, 8585 reg: regInfo{ 8586 inputs: []inputInfo{ 8587 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8588 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8589 }, 8590 outputs: []outputInfo{ 8591 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8592 }, 8593 }, 8594 }, 8595 { 8596 name: "SBCshiftLL", 8597 auxType: auxInt32, 8598 argLen: 3, 8599 asm: arm.ASBC, 8600 reg: regInfo{ 8601 inputs: []inputInfo{ 8602 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8603 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8604 }, 8605 outputs: []outputInfo{ 8606 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8607 }, 8608 }, 8609 }, 8610 { 8611 name: "SBCshiftRL", 8612 auxType: auxInt32, 8613 argLen: 3, 8614 asm: arm.ASBC, 8615 reg: regInfo{ 8616 inputs: []inputInfo{ 8617 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8618 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8619 }, 8620 outputs: []outputInfo{ 8621 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8622 }, 8623 }, 8624 }, 8625 { 8626 name: "SBCshiftRA", 8627 auxType: auxInt32, 8628 argLen: 3, 8629 asm: arm.ASBC, 8630 reg: regInfo{ 8631 inputs: []inputInfo{ 8632 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8633 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8634 }, 8635 outputs: []outputInfo{ 8636 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8637 }, 8638 }, 8639 }, 8640 { 8641 name: "RSCshiftLL", 8642 auxType: auxInt32, 8643 argLen: 3, 8644 asm: arm.ARSC, 8645 reg: regInfo{ 8646 inputs: []inputInfo{ 8647 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8648 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8649 }, 8650 outputs: []outputInfo{ 8651 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8652 }, 8653 }, 8654 }, 8655 { 8656 name: "RSCshiftRL", 8657 auxType: auxInt32, 8658 argLen: 3, 8659 asm: arm.ARSC, 8660 reg: regInfo{ 8661 inputs: []inputInfo{ 8662 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8663 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8664 }, 8665 outputs: []outputInfo{ 8666 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8667 }, 8668 }, 8669 }, 8670 { 8671 name: "RSCshiftRA", 8672 auxType: auxInt32, 8673 argLen: 3, 8674 asm: arm.ARSC, 8675 reg: regInfo{ 8676 inputs: []inputInfo{ 8677 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8678 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8679 }, 8680 outputs: []outputInfo{ 8681 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8682 }, 8683 }, 8684 }, 8685 { 8686 name: "ADDSshiftLL", 8687 auxType: auxInt32, 8688 argLen: 2, 8689 asm: arm.AADD, 8690 reg: regInfo{ 8691 inputs: []inputInfo{ 8692 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8693 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8694 }, 8695 outputs: []outputInfo{ 8696 {1, 0}, 8697 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8698 }, 8699 }, 8700 }, 8701 { 8702 name: "ADDSshiftRL", 8703 auxType: auxInt32, 8704 argLen: 2, 8705 asm: arm.AADD, 8706 reg: regInfo{ 8707 inputs: []inputInfo{ 8708 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8709 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8710 }, 8711 outputs: []outputInfo{ 8712 {1, 0}, 8713 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8714 }, 8715 }, 8716 }, 8717 { 8718 name: "ADDSshiftRA", 8719 auxType: auxInt32, 8720 argLen: 2, 8721 asm: arm.AADD, 8722 reg: regInfo{ 8723 inputs: []inputInfo{ 8724 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8725 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8726 }, 8727 outputs: []outputInfo{ 8728 {1, 0}, 8729 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8730 }, 8731 }, 8732 }, 8733 { 8734 name: "SUBSshiftLL", 8735 auxType: auxInt32, 8736 argLen: 2, 8737 asm: arm.ASUB, 8738 reg: regInfo{ 8739 inputs: []inputInfo{ 8740 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8741 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8742 }, 8743 outputs: []outputInfo{ 8744 {1, 0}, 8745 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8746 }, 8747 }, 8748 }, 8749 { 8750 name: "SUBSshiftRL", 8751 auxType: auxInt32, 8752 argLen: 2, 8753 asm: arm.ASUB, 8754 reg: regInfo{ 8755 inputs: []inputInfo{ 8756 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8757 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8758 }, 8759 outputs: []outputInfo{ 8760 {1, 0}, 8761 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8762 }, 8763 }, 8764 }, 8765 { 8766 name: "SUBSshiftRA", 8767 auxType: auxInt32, 8768 argLen: 2, 8769 asm: arm.ASUB, 8770 reg: regInfo{ 8771 inputs: []inputInfo{ 8772 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8773 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8774 }, 8775 outputs: []outputInfo{ 8776 {1, 0}, 8777 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8778 }, 8779 }, 8780 }, 8781 { 8782 name: "RSBSshiftLL", 8783 auxType: auxInt32, 8784 argLen: 2, 8785 asm: arm.ARSB, 8786 reg: regInfo{ 8787 inputs: []inputInfo{ 8788 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8789 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8790 }, 8791 outputs: []outputInfo{ 8792 {1, 0}, 8793 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8794 }, 8795 }, 8796 }, 8797 { 8798 name: "RSBSshiftRL", 8799 auxType: auxInt32, 8800 argLen: 2, 8801 asm: arm.ARSB, 8802 reg: regInfo{ 8803 inputs: []inputInfo{ 8804 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8805 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8806 }, 8807 outputs: []outputInfo{ 8808 {1, 0}, 8809 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8810 }, 8811 }, 8812 }, 8813 { 8814 name: "RSBSshiftRA", 8815 auxType: auxInt32, 8816 argLen: 2, 8817 asm: arm.ARSB, 8818 reg: regInfo{ 8819 inputs: []inputInfo{ 8820 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8821 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8822 }, 8823 outputs: []outputInfo{ 8824 {1, 0}, 8825 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8826 }, 8827 }, 8828 }, 8829 { 8830 name: "ADDshiftLLreg", 8831 argLen: 3, 8832 asm: arm.AADD, 8833 reg: regInfo{ 8834 inputs: []inputInfo{ 8835 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8836 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8837 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8838 }, 8839 outputs: []outputInfo{ 8840 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8841 }, 8842 }, 8843 }, 8844 { 8845 name: "ADDshiftRLreg", 8846 argLen: 3, 8847 asm: arm.AADD, 8848 reg: regInfo{ 8849 inputs: []inputInfo{ 8850 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8851 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8852 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8853 }, 8854 outputs: []outputInfo{ 8855 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8856 }, 8857 }, 8858 }, 8859 { 8860 name: "ADDshiftRAreg", 8861 argLen: 3, 8862 asm: arm.AADD, 8863 reg: regInfo{ 8864 inputs: []inputInfo{ 8865 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8866 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8867 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8868 }, 8869 outputs: []outputInfo{ 8870 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8871 }, 8872 }, 8873 }, 8874 { 8875 name: "SUBshiftLLreg", 8876 argLen: 3, 8877 asm: arm.ASUB, 8878 reg: regInfo{ 8879 inputs: []inputInfo{ 8880 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8881 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8882 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8883 }, 8884 outputs: []outputInfo{ 8885 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8886 }, 8887 }, 8888 }, 8889 { 8890 name: "SUBshiftRLreg", 8891 argLen: 3, 8892 asm: arm.ASUB, 8893 reg: regInfo{ 8894 inputs: []inputInfo{ 8895 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8896 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8897 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8898 }, 8899 outputs: []outputInfo{ 8900 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8901 }, 8902 }, 8903 }, 8904 { 8905 name: "SUBshiftRAreg", 8906 argLen: 3, 8907 asm: arm.ASUB, 8908 reg: regInfo{ 8909 inputs: []inputInfo{ 8910 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8911 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8912 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8913 }, 8914 outputs: []outputInfo{ 8915 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8916 }, 8917 }, 8918 }, 8919 { 8920 name: "RSBshiftLLreg", 8921 argLen: 3, 8922 asm: arm.ARSB, 8923 reg: regInfo{ 8924 inputs: []inputInfo{ 8925 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8926 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8927 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8928 }, 8929 outputs: []outputInfo{ 8930 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8931 }, 8932 }, 8933 }, 8934 { 8935 name: "RSBshiftRLreg", 8936 argLen: 3, 8937 asm: arm.ARSB, 8938 reg: regInfo{ 8939 inputs: []inputInfo{ 8940 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8941 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8942 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8943 }, 8944 outputs: []outputInfo{ 8945 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8946 }, 8947 }, 8948 }, 8949 { 8950 name: "RSBshiftRAreg", 8951 argLen: 3, 8952 asm: arm.ARSB, 8953 reg: regInfo{ 8954 inputs: []inputInfo{ 8955 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8956 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8957 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8958 }, 8959 outputs: []outputInfo{ 8960 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8961 }, 8962 }, 8963 }, 8964 { 8965 name: "ANDshiftLLreg", 8966 argLen: 3, 8967 asm: arm.AAND, 8968 reg: regInfo{ 8969 inputs: []inputInfo{ 8970 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8971 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8972 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8973 }, 8974 outputs: []outputInfo{ 8975 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8976 }, 8977 }, 8978 }, 8979 { 8980 name: "ANDshiftRLreg", 8981 argLen: 3, 8982 asm: arm.AAND, 8983 reg: regInfo{ 8984 inputs: []inputInfo{ 8985 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8986 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8987 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8988 }, 8989 outputs: []outputInfo{ 8990 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8991 }, 8992 }, 8993 }, 8994 { 8995 name: "ANDshiftRAreg", 8996 argLen: 3, 8997 asm: arm.AAND, 8998 reg: regInfo{ 8999 inputs: []inputInfo{ 9000 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9001 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9002 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9003 }, 9004 outputs: []outputInfo{ 9005 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9006 }, 9007 }, 9008 }, 9009 { 9010 name: "ORshiftLLreg", 9011 argLen: 3, 9012 asm: arm.AORR, 9013 reg: regInfo{ 9014 inputs: []inputInfo{ 9015 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9016 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9017 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9018 }, 9019 outputs: []outputInfo{ 9020 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9021 }, 9022 }, 9023 }, 9024 { 9025 name: "ORshiftRLreg", 9026 argLen: 3, 9027 asm: arm.AORR, 9028 reg: regInfo{ 9029 inputs: []inputInfo{ 9030 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9031 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9032 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9033 }, 9034 outputs: []outputInfo{ 9035 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9036 }, 9037 }, 9038 }, 9039 { 9040 name: "ORshiftRAreg", 9041 argLen: 3, 9042 asm: arm.AORR, 9043 reg: regInfo{ 9044 inputs: []inputInfo{ 9045 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9046 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9047 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9048 }, 9049 outputs: []outputInfo{ 9050 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9051 }, 9052 }, 9053 }, 9054 { 9055 name: "XORshiftLLreg", 9056 argLen: 3, 9057 asm: arm.AEOR, 9058 reg: regInfo{ 9059 inputs: []inputInfo{ 9060 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9061 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9062 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9063 }, 9064 outputs: []outputInfo{ 9065 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9066 }, 9067 }, 9068 }, 9069 { 9070 name: "XORshiftRLreg", 9071 argLen: 3, 9072 asm: arm.AEOR, 9073 reg: regInfo{ 9074 inputs: []inputInfo{ 9075 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9076 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9077 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9078 }, 9079 outputs: []outputInfo{ 9080 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9081 }, 9082 }, 9083 }, 9084 { 9085 name: "XORshiftRAreg", 9086 argLen: 3, 9087 asm: arm.AEOR, 9088 reg: regInfo{ 9089 inputs: []inputInfo{ 9090 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9091 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9092 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9093 }, 9094 outputs: []outputInfo{ 9095 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9096 }, 9097 }, 9098 }, 9099 { 9100 name: "BICshiftLLreg", 9101 argLen: 3, 9102 asm: arm.ABIC, 9103 reg: regInfo{ 9104 inputs: []inputInfo{ 9105 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9106 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9107 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9108 }, 9109 outputs: []outputInfo{ 9110 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9111 }, 9112 }, 9113 }, 9114 { 9115 name: "BICshiftRLreg", 9116 argLen: 3, 9117 asm: arm.ABIC, 9118 reg: regInfo{ 9119 inputs: []inputInfo{ 9120 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9121 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9122 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9123 }, 9124 outputs: []outputInfo{ 9125 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9126 }, 9127 }, 9128 }, 9129 { 9130 name: "BICshiftRAreg", 9131 argLen: 3, 9132 asm: arm.ABIC, 9133 reg: regInfo{ 9134 inputs: []inputInfo{ 9135 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9136 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9137 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9138 }, 9139 outputs: []outputInfo{ 9140 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9141 }, 9142 }, 9143 }, 9144 { 9145 name: "MVNshiftLLreg", 9146 argLen: 2, 9147 asm: arm.AMVN, 9148 reg: regInfo{ 9149 inputs: []inputInfo{ 9150 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9151 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9152 }, 9153 outputs: []outputInfo{ 9154 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9155 }, 9156 }, 9157 }, 9158 { 9159 name: "MVNshiftRLreg", 9160 argLen: 2, 9161 asm: arm.AMVN, 9162 reg: regInfo{ 9163 inputs: []inputInfo{ 9164 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9165 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9166 }, 9167 outputs: []outputInfo{ 9168 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9169 }, 9170 }, 9171 }, 9172 { 9173 name: "MVNshiftRAreg", 9174 argLen: 2, 9175 asm: arm.AMVN, 9176 reg: regInfo{ 9177 inputs: []inputInfo{ 9178 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9179 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9180 }, 9181 outputs: []outputInfo{ 9182 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9183 }, 9184 }, 9185 }, 9186 { 9187 name: "ADCshiftLLreg", 9188 argLen: 4, 9189 asm: arm.AADC, 9190 reg: regInfo{ 9191 inputs: []inputInfo{ 9192 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9193 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9194 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9195 }, 9196 outputs: []outputInfo{ 9197 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9198 }, 9199 }, 9200 }, 9201 { 9202 name: "ADCshiftRLreg", 9203 argLen: 4, 9204 asm: arm.AADC, 9205 reg: regInfo{ 9206 inputs: []inputInfo{ 9207 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9208 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9209 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9210 }, 9211 outputs: []outputInfo{ 9212 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9213 }, 9214 }, 9215 }, 9216 { 9217 name: "ADCshiftRAreg", 9218 argLen: 4, 9219 asm: arm.AADC, 9220 reg: regInfo{ 9221 inputs: []inputInfo{ 9222 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9223 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9224 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9225 }, 9226 outputs: []outputInfo{ 9227 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9228 }, 9229 }, 9230 }, 9231 { 9232 name: "SBCshiftLLreg", 9233 argLen: 4, 9234 asm: arm.ASBC, 9235 reg: regInfo{ 9236 inputs: []inputInfo{ 9237 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9238 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9239 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9240 }, 9241 outputs: []outputInfo{ 9242 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9243 }, 9244 }, 9245 }, 9246 { 9247 name: "SBCshiftRLreg", 9248 argLen: 4, 9249 asm: arm.ASBC, 9250 reg: regInfo{ 9251 inputs: []inputInfo{ 9252 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9253 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9254 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9255 }, 9256 outputs: []outputInfo{ 9257 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9258 }, 9259 }, 9260 }, 9261 { 9262 name: "SBCshiftRAreg", 9263 argLen: 4, 9264 asm: arm.ASBC, 9265 reg: regInfo{ 9266 inputs: []inputInfo{ 9267 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9268 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9269 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9270 }, 9271 outputs: []outputInfo{ 9272 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9273 }, 9274 }, 9275 }, 9276 { 9277 name: "RSCshiftLLreg", 9278 argLen: 4, 9279 asm: arm.ARSC, 9280 reg: regInfo{ 9281 inputs: []inputInfo{ 9282 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9283 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9284 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9285 }, 9286 outputs: []outputInfo{ 9287 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9288 }, 9289 }, 9290 }, 9291 { 9292 name: "RSCshiftRLreg", 9293 argLen: 4, 9294 asm: arm.ARSC, 9295 reg: regInfo{ 9296 inputs: []inputInfo{ 9297 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9298 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9299 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9300 }, 9301 outputs: []outputInfo{ 9302 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9303 }, 9304 }, 9305 }, 9306 { 9307 name: "RSCshiftRAreg", 9308 argLen: 4, 9309 asm: arm.ARSC, 9310 reg: regInfo{ 9311 inputs: []inputInfo{ 9312 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9313 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9314 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9315 }, 9316 outputs: []outputInfo{ 9317 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9318 }, 9319 }, 9320 }, 9321 { 9322 name: "ADDSshiftLLreg", 9323 argLen: 3, 9324 asm: arm.AADD, 9325 reg: regInfo{ 9326 inputs: []inputInfo{ 9327 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9328 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9329 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9330 }, 9331 outputs: []outputInfo{ 9332 {1, 0}, 9333 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9334 }, 9335 }, 9336 }, 9337 { 9338 name: "ADDSshiftRLreg", 9339 argLen: 3, 9340 asm: arm.AADD, 9341 reg: regInfo{ 9342 inputs: []inputInfo{ 9343 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9344 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9345 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9346 }, 9347 outputs: []outputInfo{ 9348 {1, 0}, 9349 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9350 }, 9351 }, 9352 }, 9353 { 9354 name: "ADDSshiftRAreg", 9355 argLen: 3, 9356 asm: arm.AADD, 9357 reg: regInfo{ 9358 inputs: []inputInfo{ 9359 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9360 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9361 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9362 }, 9363 outputs: []outputInfo{ 9364 {1, 0}, 9365 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9366 }, 9367 }, 9368 }, 9369 { 9370 name: "SUBSshiftLLreg", 9371 argLen: 3, 9372 asm: arm.ASUB, 9373 reg: regInfo{ 9374 inputs: []inputInfo{ 9375 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9376 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9377 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9378 }, 9379 outputs: []outputInfo{ 9380 {1, 0}, 9381 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9382 }, 9383 }, 9384 }, 9385 { 9386 name: "SUBSshiftRLreg", 9387 argLen: 3, 9388 asm: arm.ASUB, 9389 reg: regInfo{ 9390 inputs: []inputInfo{ 9391 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9392 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9393 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9394 }, 9395 outputs: []outputInfo{ 9396 {1, 0}, 9397 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9398 }, 9399 }, 9400 }, 9401 { 9402 name: "SUBSshiftRAreg", 9403 argLen: 3, 9404 asm: arm.ASUB, 9405 reg: regInfo{ 9406 inputs: []inputInfo{ 9407 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9408 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9409 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9410 }, 9411 outputs: []outputInfo{ 9412 {1, 0}, 9413 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9414 }, 9415 }, 9416 }, 9417 { 9418 name: "RSBSshiftLLreg", 9419 argLen: 3, 9420 asm: arm.ARSB, 9421 reg: regInfo{ 9422 inputs: []inputInfo{ 9423 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9424 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9425 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9426 }, 9427 outputs: []outputInfo{ 9428 {1, 0}, 9429 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9430 }, 9431 }, 9432 }, 9433 { 9434 name: "RSBSshiftRLreg", 9435 argLen: 3, 9436 asm: arm.ARSB, 9437 reg: regInfo{ 9438 inputs: []inputInfo{ 9439 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9440 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9441 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9442 }, 9443 outputs: []outputInfo{ 9444 {1, 0}, 9445 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9446 }, 9447 }, 9448 }, 9449 { 9450 name: "RSBSshiftRAreg", 9451 argLen: 3, 9452 asm: arm.ARSB, 9453 reg: regInfo{ 9454 inputs: []inputInfo{ 9455 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9456 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9457 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9458 }, 9459 outputs: []outputInfo{ 9460 {1, 0}, 9461 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9462 }, 9463 }, 9464 }, 9465 { 9466 name: "CMP", 9467 argLen: 2, 9468 asm: arm.ACMP, 9469 reg: regInfo{ 9470 inputs: []inputInfo{ 9471 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9472 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9473 }, 9474 }, 9475 }, 9476 { 9477 name: "CMPconst", 9478 auxType: auxInt32, 9479 argLen: 1, 9480 asm: arm.ACMP, 9481 reg: regInfo{ 9482 inputs: []inputInfo{ 9483 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9484 }, 9485 }, 9486 }, 9487 { 9488 name: "CMN", 9489 argLen: 2, 9490 asm: arm.ACMN, 9491 reg: regInfo{ 9492 inputs: []inputInfo{ 9493 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9494 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9495 }, 9496 }, 9497 }, 9498 { 9499 name: "CMNconst", 9500 auxType: auxInt32, 9501 argLen: 1, 9502 asm: arm.ACMN, 9503 reg: regInfo{ 9504 inputs: []inputInfo{ 9505 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9506 }, 9507 }, 9508 }, 9509 { 9510 name: "TST", 9511 argLen: 2, 9512 commutative: true, 9513 asm: arm.ATST, 9514 reg: regInfo{ 9515 inputs: []inputInfo{ 9516 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9517 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9518 }, 9519 }, 9520 }, 9521 { 9522 name: "TSTconst", 9523 auxType: auxInt32, 9524 argLen: 1, 9525 asm: arm.ATST, 9526 reg: regInfo{ 9527 inputs: []inputInfo{ 9528 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9529 }, 9530 }, 9531 }, 9532 { 9533 name: "TEQ", 9534 argLen: 2, 9535 commutative: true, 9536 asm: arm.ATEQ, 9537 reg: regInfo{ 9538 inputs: []inputInfo{ 9539 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9540 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9541 }, 9542 }, 9543 }, 9544 { 9545 name: "TEQconst", 9546 auxType: auxInt32, 9547 argLen: 1, 9548 asm: arm.ATEQ, 9549 reg: regInfo{ 9550 inputs: []inputInfo{ 9551 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9552 }, 9553 }, 9554 }, 9555 { 9556 name: "CMPF", 9557 argLen: 2, 9558 asm: arm.ACMPF, 9559 reg: regInfo{ 9560 inputs: []inputInfo{ 9561 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9562 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9563 }, 9564 }, 9565 }, 9566 { 9567 name: "CMPD", 9568 argLen: 2, 9569 asm: arm.ACMPD, 9570 reg: regInfo{ 9571 inputs: []inputInfo{ 9572 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9573 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9574 }, 9575 }, 9576 }, 9577 { 9578 name: "CMPshiftLL", 9579 auxType: auxInt32, 9580 argLen: 2, 9581 asm: arm.ACMP, 9582 reg: regInfo{ 9583 inputs: []inputInfo{ 9584 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9585 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9586 }, 9587 }, 9588 }, 9589 { 9590 name: "CMPshiftRL", 9591 auxType: auxInt32, 9592 argLen: 2, 9593 asm: arm.ACMP, 9594 reg: regInfo{ 9595 inputs: []inputInfo{ 9596 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9597 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9598 }, 9599 }, 9600 }, 9601 { 9602 name: "CMPshiftRA", 9603 auxType: auxInt32, 9604 argLen: 2, 9605 asm: arm.ACMP, 9606 reg: regInfo{ 9607 inputs: []inputInfo{ 9608 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9609 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9610 }, 9611 }, 9612 }, 9613 { 9614 name: "CMPshiftLLreg", 9615 argLen: 3, 9616 asm: arm.ACMP, 9617 reg: regInfo{ 9618 inputs: []inputInfo{ 9619 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9620 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9621 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9622 }, 9623 }, 9624 }, 9625 { 9626 name: "CMPshiftRLreg", 9627 argLen: 3, 9628 asm: arm.ACMP, 9629 reg: regInfo{ 9630 inputs: []inputInfo{ 9631 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9632 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9633 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9634 }, 9635 }, 9636 }, 9637 { 9638 name: "CMPshiftRAreg", 9639 argLen: 3, 9640 asm: arm.ACMP, 9641 reg: regInfo{ 9642 inputs: []inputInfo{ 9643 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9644 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9645 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9646 }, 9647 }, 9648 }, 9649 { 9650 name: "CMPF0", 9651 argLen: 1, 9652 asm: arm.ACMPF, 9653 reg: regInfo{ 9654 inputs: []inputInfo{ 9655 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9656 }, 9657 }, 9658 }, 9659 { 9660 name: "CMPD0", 9661 argLen: 1, 9662 asm: arm.ACMPD, 9663 reg: regInfo{ 9664 inputs: []inputInfo{ 9665 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9666 }, 9667 }, 9668 }, 9669 { 9670 name: "MOVWconst", 9671 auxType: auxInt32, 9672 argLen: 0, 9673 rematerializeable: true, 9674 asm: arm.AMOVW, 9675 reg: regInfo{ 9676 outputs: []outputInfo{ 9677 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9678 }, 9679 }, 9680 }, 9681 { 9682 name: "MOVFconst", 9683 auxType: auxFloat64, 9684 argLen: 0, 9685 rematerializeable: true, 9686 asm: arm.AMOVF, 9687 reg: regInfo{ 9688 outputs: []outputInfo{ 9689 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9690 }, 9691 }, 9692 }, 9693 { 9694 name: "MOVDconst", 9695 auxType: auxFloat64, 9696 argLen: 0, 9697 rematerializeable: true, 9698 asm: arm.AMOVD, 9699 reg: regInfo{ 9700 outputs: []outputInfo{ 9701 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9702 }, 9703 }, 9704 }, 9705 { 9706 name: "MOVWaddr", 9707 auxType: auxSymOff, 9708 argLen: 1, 9709 rematerializeable: true, 9710 asm: arm.AMOVW, 9711 reg: regInfo{ 9712 inputs: []inputInfo{ 9713 {0, 4294975488}, // SP SB 9714 }, 9715 outputs: []outputInfo{ 9716 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9717 }, 9718 }, 9719 }, 9720 { 9721 name: "MOVBload", 9722 auxType: auxSymOff, 9723 argLen: 2, 9724 faultOnNilArg0: true, 9725 asm: arm.AMOVB, 9726 reg: regInfo{ 9727 inputs: []inputInfo{ 9728 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9729 }, 9730 outputs: []outputInfo{ 9731 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9732 }, 9733 }, 9734 }, 9735 { 9736 name: "MOVBUload", 9737 auxType: auxSymOff, 9738 argLen: 2, 9739 faultOnNilArg0: true, 9740 asm: arm.AMOVBU, 9741 reg: regInfo{ 9742 inputs: []inputInfo{ 9743 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9744 }, 9745 outputs: []outputInfo{ 9746 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9747 }, 9748 }, 9749 }, 9750 { 9751 name: "MOVHload", 9752 auxType: auxSymOff, 9753 argLen: 2, 9754 faultOnNilArg0: true, 9755 asm: arm.AMOVH, 9756 reg: regInfo{ 9757 inputs: []inputInfo{ 9758 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9759 }, 9760 outputs: []outputInfo{ 9761 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9762 }, 9763 }, 9764 }, 9765 { 9766 name: "MOVHUload", 9767 auxType: auxSymOff, 9768 argLen: 2, 9769 faultOnNilArg0: true, 9770 asm: arm.AMOVHU, 9771 reg: regInfo{ 9772 inputs: []inputInfo{ 9773 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9774 }, 9775 outputs: []outputInfo{ 9776 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9777 }, 9778 }, 9779 }, 9780 { 9781 name: "MOVWload", 9782 auxType: auxSymOff, 9783 argLen: 2, 9784 faultOnNilArg0: true, 9785 asm: arm.AMOVW, 9786 reg: regInfo{ 9787 inputs: []inputInfo{ 9788 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9789 }, 9790 outputs: []outputInfo{ 9791 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9792 }, 9793 }, 9794 }, 9795 { 9796 name: "MOVFload", 9797 auxType: auxSymOff, 9798 argLen: 2, 9799 faultOnNilArg0: true, 9800 asm: arm.AMOVF, 9801 reg: regInfo{ 9802 inputs: []inputInfo{ 9803 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9804 }, 9805 outputs: []outputInfo{ 9806 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9807 }, 9808 }, 9809 }, 9810 { 9811 name: "MOVDload", 9812 auxType: auxSymOff, 9813 argLen: 2, 9814 faultOnNilArg0: true, 9815 asm: arm.AMOVD, 9816 reg: regInfo{ 9817 inputs: []inputInfo{ 9818 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9819 }, 9820 outputs: []outputInfo{ 9821 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9822 }, 9823 }, 9824 }, 9825 { 9826 name: "MOVBstore", 9827 auxType: auxSymOff, 9828 argLen: 3, 9829 faultOnNilArg0: true, 9830 asm: arm.AMOVB, 9831 reg: regInfo{ 9832 inputs: []inputInfo{ 9833 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9834 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9835 }, 9836 }, 9837 }, 9838 { 9839 name: "MOVHstore", 9840 auxType: auxSymOff, 9841 argLen: 3, 9842 faultOnNilArg0: true, 9843 asm: arm.AMOVH, 9844 reg: regInfo{ 9845 inputs: []inputInfo{ 9846 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9847 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9848 }, 9849 }, 9850 }, 9851 { 9852 name: "MOVWstore", 9853 auxType: auxSymOff, 9854 argLen: 3, 9855 faultOnNilArg0: true, 9856 asm: arm.AMOVW, 9857 reg: regInfo{ 9858 inputs: []inputInfo{ 9859 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9860 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9861 }, 9862 }, 9863 }, 9864 { 9865 name: "MOVFstore", 9866 auxType: auxSymOff, 9867 argLen: 3, 9868 faultOnNilArg0: true, 9869 asm: arm.AMOVF, 9870 reg: regInfo{ 9871 inputs: []inputInfo{ 9872 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9873 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9874 }, 9875 }, 9876 }, 9877 { 9878 name: "MOVDstore", 9879 auxType: auxSymOff, 9880 argLen: 3, 9881 faultOnNilArg0: true, 9882 asm: arm.AMOVD, 9883 reg: regInfo{ 9884 inputs: []inputInfo{ 9885 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9886 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9887 }, 9888 }, 9889 }, 9890 { 9891 name: "MOVWloadidx", 9892 argLen: 3, 9893 asm: arm.AMOVW, 9894 reg: regInfo{ 9895 inputs: []inputInfo{ 9896 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9897 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9898 }, 9899 outputs: []outputInfo{ 9900 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9901 }, 9902 }, 9903 }, 9904 { 9905 name: "MOVWloadshiftLL", 9906 auxType: auxInt32, 9907 argLen: 3, 9908 asm: arm.AMOVW, 9909 reg: regInfo{ 9910 inputs: []inputInfo{ 9911 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9912 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9913 }, 9914 outputs: []outputInfo{ 9915 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9916 }, 9917 }, 9918 }, 9919 { 9920 name: "MOVWloadshiftRL", 9921 auxType: auxInt32, 9922 argLen: 3, 9923 asm: arm.AMOVW, 9924 reg: regInfo{ 9925 inputs: []inputInfo{ 9926 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9927 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9928 }, 9929 outputs: []outputInfo{ 9930 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9931 }, 9932 }, 9933 }, 9934 { 9935 name: "MOVWloadshiftRA", 9936 auxType: auxInt32, 9937 argLen: 3, 9938 asm: arm.AMOVW, 9939 reg: regInfo{ 9940 inputs: []inputInfo{ 9941 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9942 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9943 }, 9944 outputs: []outputInfo{ 9945 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9946 }, 9947 }, 9948 }, 9949 { 9950 name: "MOVWstoreidx", 9951 argLen: 4, 9952 asm: arm.AMOVW, 9953 reg: regInfo{ 9954 inputs: []inputInfo{ 9955 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9956 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9957 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9958 }, 9959 }, 9960 }, 9961 { 9962 name: "MOVWstoreshiftLL", 9963 auxType: auxInt32, 9964 argLen: 4, 9965 asm: arm.AMOVW, 9966 reg: regInfo{ 9967 inputs: []inputInfo{ 9968 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9969 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9970 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9971 }, 9972 }, 9973 }, 9974 { 9975 name: "MOVWstoreshiftRL", 9976 auxType: auxInt32, 9977 argLen: 4, 9978 asm: arm.AMOVW, 9979 reg: regInfo{ 9980 inputs: []inputInfo{ 9981 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9982 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9983 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9984 }, 9985 }, 9986 }, 9987 { 9988 name: "MOVWstoreshiftRA", 9989 auxType: auxInt32, 9990 argLen: 4, 9991 asm: arm.AMOVW, 9992 reg: regInfo{ 9993 inputs: []inputInfo{ 9994 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9995 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9996 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9997 }, 9998 }, 9999 }, 10000 { 10001 name: "MOVBreg", 10002 argLen: 1, 10003 asm: arm.AMOVBS, 10004 reg: regInfo{ 10005 inputs: []inputInfo{ 10006 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10007 }, 10008 outputs: []outputInfo{ 10009 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10010 }, 10011 }, 10012 }, 10013 { 10014 name: "MOVBUreg", 10015 argLen: 1, 10016 asm: arm.AMOVBU, 10017 reg: regInfo{ 10018 inputs: []inputInfo{ 10019 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10020 }, 10021 outputs: []outputInfo{ 10022 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10023 }, 10024 }, 10025 }, 10026 { 10027 name: "MOVHreg", 10028 argLen: 1, 10029 asm: arm.AMOVHS, 10030 reg: regInfo{ 10031 inputs: []inputInfo{ 10032 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10033 }, 10034 outputs: []outputInfo{ 10035 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10036 }, 10037 }, 10038 }, 10039 { 10040 name: "MOVHUreg", 10041 argLen: 1, 10042 asm: arm.AMOVHU, 10043 reg: regInfo{ 10044 inputs: []inputInfo{ 10045 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10046 }, 10047 outputs: []outputInfo{ 10048 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10049 }, 10050 }, 10051 }, 10052 { 10053 name: "MOVWreg", 10054 argLen: 1, 10055 asm: arm.AMOVW, 10056 reg: regInfo{ 10057 inputs: []inputInfo{ 10058 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10059 }, 10060 outputs: []outputInfo{ 10061 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10062 }, 10063 }, 10064 }, 10065 { 10066 name: "MOVWnop", 10067 argLen: 1, 10068 resultInArg0: true, 10069 reg: regInfo{ 10070 inputs: []inputInfo{ 10071 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10072 }, 10073 outputs: []outputInfo{ 10074 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10075 }, 10076 }, 10077 }, 10078 { 10079 name: "MOVWF", 10080 argLen: 1, 10081 asm: arm.AMOVWF, 10082 reg: regInfo{ 10083 inputs: []inputInfo{ 10084 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10085 }, 10086 outputs: []outputInfo{ 10087 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10088 }, 10089 }, 10090 }, 10091 { 10092 name: "MOVWD", 10093 argLen: 1, 10094 asm: arm.AMOVWD, 10095 reg: regInfo{ 10096 inputs: []inputInfo{ 10097 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10098 }, 10099 outputs: []outputInfo{ 10100 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10101 }, 10102 }, 10103 }, 10104 { 10105 name: "MOVWUF", 10106 argLen: 1, 10107 asm: arm.AMOVWF, 10108 reg: regInfo{ 10109 inputs: []inputInfo{ 10110 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10111 }, 10112 outputs: []outputInfo{ 10113 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10114 }, 10115 }, 10116 }, 10117 { 10118 name: "MOVWUD", 10119 argLen: 1, 10120 asm: arm.AMOVWD, 10121 reg: regInfo{ 10122 inputs: []inputInfo{ 10123 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10124 }, 10125 outputs: []outputInfo{ 10126 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10127 }, 10128 }, 10129 }, 10130 { 10131 name: "MOVFW", 10132 argLen: 1, 10133 asm: arm.AMOVFW, 10134 reg: regInfo{ 10135 inputs: []inputInfo{ 10136 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10137 }, 10138 outputs: []outputInfo{ 10139 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10140 }, 10141 }, 10142 }, 10143 { 10144 name: "MOVDW", 10145 argLen: 1, 10146 asm: arm.AMOVDW, 10147 reg: regInfo{ 10148 inputs: []inputInfo{ 10149 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10150 }, 10151 outputs: []outputInfo{ 10152 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10153 }, 10154 }, 10155 }, 10156 { 10157 name: "MOVFWU", 10158 argLen: 1, 10159 asm: arm.AMOVFW, 10160 reg: regInfo{ 10161 inputs: []inputInfo{ 10162 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10163 }, 10164 outputs: []outputInfo{ 10165 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10166 }, 10167 }, 10168 }, 10169 { 10170 name: "MOVDWU", 10171 argLen: 1, 10172 asm: arm.AMOVDW, 10173 reg: regInfo{ 10174 inputs: []inputInfo{ 10175 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10176 }, 10177 outputs: []outputInfo{ 10178 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10179 }, 10180 }, 10181 }, 10182 { 10183 name: "MOVFD", 10184 argLen: 1, 10185 asm: arm.AMOVFD, 10186 reg: regInfo{ 10187 inputs: []inputInfo{ 10188 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10189 }, 10190 outputs: []outputInfo{ 10191 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10192 }, 10193 }, 10194 }, 10195 { 10196 name: "MOVDF", 10197 argLen: 1, 10198 asm: arm.AMOVDF, 10199 reg: regInfo{ 10200 inputs: []inputInfo{ 10201 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10202 }, 10203 outputs: []outputInfo{ 10204 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10205 }, 10206 }, 10207 }, 10208 { 10209 name: "CMOVWHSconst", 10210 auxType: auxInt32, 10211 argLen: 2, 10212 resultInArg0: true, 10213 asm: arm.AMOVW, 10214 reg: regInfo{ 10215 inputs: []inputInfo{ 10216 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10217 }, 10218 outputs: []outputInfo{ 10219 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10220 }, 10221 }, 10222 }, 10223 { 10224 name: "CMOVWLSconst", 10225 auxType: auxInt32, 10226 argLen: 2, 10227 resultInArg0: true, 10228 asm: arm.AMOVW, 10229 reg: regInfo{ 10230 inputs: []inputInfo{ 10231 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10232 }, 10233 outputs: []outputInfo{ 10234 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10235 }, 10236 }, 10237 }, 10238 { 10239 name: "SRAcond", 10240 argLen: 3, 10241 asm: arm.ASRA, 10242 reg: regInfo{ 10243 inputs: []inputInfo{ 10244 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10245 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10246 }, 10247 outputs: []outputInfo{ 10248 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10249 }, 10250 }, 10251 }, 10252 { 10253 name: "CALLstatic", 10254 auxType: auxSymOff, 10255 argLen: 1, 10256 clobberFlags: true, 10257 call: true, 10258 reg: regInfo{ 10259 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10260 }, 10261 }, 10262 { 10263 name: "CALLclosure", 10264 auxType: auxInt64, 10265 argLen: 3, 10266 clobberFlags: true, 10267 call: true, 10268 reg: regInfo{ 10269 inputs: []inputInfo{ 10270 {1, 128}, // R7 10271 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 10272 }, 10273 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10274 }, 10275 }, 10276 { 10277 name: "CALLdefer", 10278 auxType: auxInt64, 10279 argLen: 1, 10280 clobberFlags: true, 10281 call: true, 10282 reg: regInfo{ 10283 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10284 }, 10285 }, 10286 { 10287 name: "CALLgo", 10288 auxType: auxInt64, 10289 argLen: 1, 10290 clobberFlags: true, 10291 call: true, 10292 reg: regInfo{ 10293 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10294 }, 10295 }, 10296 { 10297 name: "CALLinter", 10298 auxType: auxInt64, 10299 argLen: 2, 10300 clobberFlags: true, 10301 call: true, 10302 reg: regInfo{ 10303 inputs: []inputInfo{ 10304 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10305 }, 10306 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10307 }, 10308 }, 10309 { 10310 name: "LoweredNilCheck", 10311 argLen: 2, 10312 nilCheck: true, 10313 faultOnNilArg0: true, 10314 reg: regInfo{ 10315 inputs: []inputInfo{ 10316 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10317 }, 10318 }, 10319 }, 10320 { 10321 name: "Equal", 10322 argLen: 1, 10323 reg: regInfo{ 10324 outputs: []outputInfo{ 10325 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10326 }, 10327 }, 10328 }, 10329 { 10330 name: "NotEqual", 10331 argLen: 1, 10332 reg: regInfo{ 10333 outputs: []outputInfo{ 10334 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10335 }, 10336 }, 10337 }, 10338 { 10339 name: "LessThan", 10340 argLen: 1, 10341 reg: regInfo{ 10342 outputs: []outputInfo{ 10343 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10344 }, 10345 }, 10346 }, 10347 { 10348 name: "LessEqual", 10349 argLen: 1, 10350 reg: regInfo{ 10351 outputs: []outputInfo{ 10352 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10353 }, 10354 }, 10355 }, 10356 { 10357 name: "GreaterThan", 10358 argLen: 1, 10359 reg: regInfo{ 10360 outputs: []outputInfo{ 10361 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10362 }, 10363 }, 10364 }, 10365 { 10366 name: "GreaterEqual", 10367 argLen: 1, 10368 reg: regInfo{ 10369 outputs: []outputInfo{ 10370 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10371 }, 10372 }, 10373 }, 10374 { 10375 name: "LessThanU", 10376 argLen: 1, 10377 reg: regInfo{ 10378 outputs: []outputInfo{ 10379 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10380 }, 10381 }, 10382 }, 10383 { 10384 name: "LessEqualU", 10385 argLen: 1, 10386 reg: regInfo{ 10387 outputs: []outputInfo{ 10388 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10389 }, 10390 }, 10391 }, 10392 { 10393 name: "GreaterThanU", 10394 argLen: 1, 10395 reg: regInfo{ 10396 outputs: []outputInfo{ 10397 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10398 }, 10399 }, 10400 }, 10401 { 10402 name: "GreaterEqualU", 10403 argLen: 1, 10404 reg: regInfo{ 10405 outputs: []outputInfo{ 10406 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10407 }, 10408 }, 10409 }, 10410 { 10411 name: "DUFFZERO", 10412 auxType: auxInt64, 10413 argLen: 3, 10414 faultOnNilArg0: true, 10415 reg: regInfo{ 10416 inputs: []inputInfo{ 10417 {0, 2}, // R1 10418 {1, 1}, // R0 10419 }, 10420 clobbers: 16386, // R1 R14 10421 }, 10422 }, 10423 { 10424 name: "DUFFCOPY", 10425 auxType: auxInt64, 10426 argLen: 3, 10427 faultOnNilArg0: true, 10428 faultOnNilArg1: true, 10429 reg: regInfo{ 10430 inputs: []inputInfo{ 10431 {0, 4}, // R2 10432 {1, 2}, // R1 10433 }, 10434 clobbers: 16391, // R0 R1 R2 R14 10435 }, 10436 }, 10437 { 10438 name: "LoweredZero", 10439 auxType: auxInt64, 10440 argLen: 4, 10441 clobberFlags: true, 10442 faultOnNilArg0: true, 10443 reg: regInfo{ 10444 inputs: []inputInfo{ 10445 {0, 2}, // R1 10446 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10447 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10448 }, 10449 clobbers: 2, // R1 10450 }, 10451 }, 10452 { 10453 name: "LoweredMove", 10454 auxType: auxInt64, 10455 argLen: 4, 10456 clobberFlags: true, 10457 faultOnNilArg0: true, 10458 faultOnNilArg1: true, 10459 reg: regInfo{ 10460 inputs: []inputInfo{ 10461 {0, 4}, // R2 10462 {1, 2}, // R1 10463 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10464 }, 10465 clobbers: 6, // R1 R2 10466 }, 10467 }, 10468 { 10469 name: "LoweredGetClosurePtr", 10470 argLen: 0, 10471 reg: regInfo{ 10472 outputs: []outputInfo{ 10473 {0, 128}, // R7 10474 }, 10475 }, 10476 }, 10477 { 10478 name: "MOVWconvert", 10479 argLen: 2, 10480 asm: arm.AMOVW, 10481 reg: regInfo{ 10482 inputs: []inputInfo{ 10483 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10484 }, 10485 outputs: []outputInfo{ 10486 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10487 }, 10488 }, 10489 }, 10490 { 10491 name: "FlagEQ", 10492 argLen: 0, 10493 reg: regInfo{}, 10494 }, 10495 { 10496 name: "FlagLT_ULT", 10497 argLen: 0, 10498 reg: regInfo{}, 10499 }, 10500 { 10501 name: "FlagLT_UGT", 10502 argLen: 0, 10503 reg: regInfo{}, 10504 }, 10505 { 10506 name: "FlagGT_UGT", 10507 argLen: 0, 10508 reg: regInfo{}, 10509 }, 10510 { 10511 name: "FlagGT_ULT", 10512 argLen: 0, 10513 reg: regInfo{}, 10514 }, 10515 { 10516 name: "InvertFlags", 10517 argLen: 1, 10518 reg: regInfo{}, 10519 }, 10520 10521 { 10522 name: "ADD", 10523 argLen: 2, 10524 commutative: true, 10525 asm: arm64.AADD, 10526 reg: regInfo{ 10527 inputs: []inputInfo{ 10528 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10529 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10530 }, 10531 outputs: []outputInfo{ 10532 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10533 }, 10534 }, 10535 }, 10536 { 10537 name: "ADDconst", 10538 auxType: auxInt64, 10539 argLen: 1, 10540 asm: arm64.AADD, 10541 reg: regInfo{ 10542 inputs: []inputInfo{ 10543 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 10544 }, 10545 outputs: []outputInfo{ 10546 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10547 }, 10548 }, 10549 }, 10550 { 10551 name: "SUB", 10552 argLen: 2, 10553 asm: arm64.ASUB, 10554 reg: regInfo{ 10555 inputs: []inputInfo{ 10556 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10557 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10558 }, 10559 outputs: []outputInfo{ 10560 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10561 }, 10562 }, 10563 }, 10564 { 10565 name: "SUBconst", 10566 auxType: auxInt64, 10567 argLen: 1, 10568 asm: arm64.ASUB, 10569 reg: regInfo{ 10570 inputs: []inputInfo{ 10571 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10572 }, 10573 outputs: []outputInfo{ 10574 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10575 }, 10576 }, 10577 }, 10578 { 10579 name: "MUL", 10580 argLen: 2, 10581 commutative: true, 10582 asm: arm64.AMUL, 10583 reg: regInfo{ 10584 inputs: []inputInfo{ 10585 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10586 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10587 }, 10588 outputs: []outputInfo{ 10589 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10590 }, 10591 }, 10592 }, 10593 { 10594 name: "MULW", 10595 argLen: 2, 10596 commutative: true, 10597 asm: arm64.AMULW, 10598 reg: regInfo{ 10599 inputs: []inputInfo{ 10600 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10601 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10602 }, 10603 outputs: []outputInfo{ 10604 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10605 }, 10606 }, 10607 }, 10608 { 10609 name: "MULH", 10610 argLen: 2, 10611 commutative: true, 10612 asm: arm64.ASMULH, 10613 reg: regInfo{ 10614 inputs: []inputInfo{ 10615 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10616 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10617 }, 10618 outputs: []outputInfo{ 10619 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10620 }, 10621 }, 10622 }, 10623 { 10624 name: "UMULH", 10625 argLen: 2, 10626 commutative: true, 10627 asm: arm64.AUMULH, 10628 reg: regInfo{ 10629 inputs: []inputInfo{ 10630 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10631 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10632 }, 10633 outputs: []outputInfo{ 10634 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10635 }, 10636 }, 10637 }, 10638 { 10639 name: "MULL", 10640 argLen: 2, 10641 commutative: true, 10642 asm: arm64.ASMULL, 10643 reg: regInfo{ 10644 inputs: []inputInfo{ 10645 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10646 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10647 }, 10648 outputs: []outputInfo{ 10649 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10650 }, 10651 }, 10652 }, 10653 { 10654 name: "UMULL", 10655 argLen: 2, 10656 commutative: true, 10657 asm: arm64.AUMULL, 10658 reg: regInfo{ 10659 inputs: []inputInfo{ 10660 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10661 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10662 }, 10663 outputs: []outputInfo{ 10664 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10665 }, 10666 }, 10667 }, 10668 { 10669 name: "DIV", 10670 argLen: 2, 10671 asm: arm64.ASDIV, 10672 reg: regInfo{ 10673 inputs: []inputInfo{ 10674 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10675 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10676 }, 10677 outputs: []outputInfo{ 10678 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10679 }, 10680 }, 10681 }, 10682 { 10683 name: "UDIV", 10684 argLen: 2, 10685 asm: arm64.AUDIV, 10686 reg: regInfo{ 10687 inputs: []inputInfo{ 10688 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10689 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10690 }, 10691 outputs: []outputInfo{ 10692 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10693 }, 10694 }, 10695 }, 10696 { 10697 name: "DIVW", 10698 argLen: 2, 10699 asm: arm64.ASDIVW, 10700 reg: regInfo{ 10701 inputs: []inputInfo{ 10702 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10703 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10704 }, 10705 outputs: []outputInfo{ 10706 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10707 }, 10708 }, 10709 }, 10710 { 10711 name: "UDIVW", 10712 argLen: 2, 10713 asm: arm64.AUDIVW, 10714 reg: regInfo{ 10715 inputs: []inputInfo{ 10716 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10717 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10718 }, 10719 outputs: []outputInfo{ 10720 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10721 }, 10722 }, 10723 }, 10724 { 10725 name: "MOD", 10726 argLen: 2, 10727 asm: arm64.AREM, 10728 reg: regInfo{ 10729 inputs: []inputInfo{ 10730 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10731 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10732 }, 10733 outputs: []outputInfo{ 10734 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10735 }, 10736 }, 10737 }, 10738 { 10739 name: "UMOD", 10740 argLen: 2, 10741 asm: arm64.AUREM, 10742 reg: regInfo{ 10743 inputs: []inputInfo{ 10744 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10745 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10746 }, 10747 outputs: []outputInfo{ 10748 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10749 }, 10750 }, 10751 }, 10752 { 10753 name: "MODW", 10754 argLen: 2, 10755 asm: arm64.AREMW, 10756 reg: regInfo{ 10757 inputs: []inputInfo{ 10758 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10759 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10760 }, 10761 outputs: []outputInfo{ 10762 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10763 }, 10764 }, 10765 }, 10766 { 10767 name: "UMODW", 10768 argLen: 2, 10769 asm: arm64.AUREMW, 10770 reg: regInfo{ 10771 inputs: []inputInfo{ 10772 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10773 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10774 }, 10775 outputs: []outputInfo{ 10776 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10777 }, 10778 }, 10779 }, 10780 { 10781 name: "FADDS", 10782 argLen: 2, 10783 commutative: true, 10784 asm: arm64.AFADDS, 10785 reg: regInfo{ 10786 inputs: []inputInfo{ 10787 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10788 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10789 }, 10790 outputs: []outputInfo{ 10791 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10792 }, 10793 }, 10794 }, 10795 { 10796 name: "FADDD", 10797 argLen: 2, 10798 commutative: true, 10799 asm: arm64.AFADDD, 10800 reg: regInfo{ 10801 inputs: []inputInfo{ 10802 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10803 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10804 }, 10805 outputs: []outputInfo{ 10806 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10807 }, 10808 }, 10809 }, 10810 { 10811 name: "FSUBS", 10812 argLen: 2, 10813 asm: arm64.AFSUBS, 10814 reg: regInfo{ 10815 inputs: []inputInfo{ 10816 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10817 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10818 }, 10819 outputs: []outputInfo{ 10820 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10821 }, 10822 }, 10823 }, 10824 { 10825 name: "FSUBD", 10826 argLen: 2, 10827 asm: arm64.AFSUBD, 10828 reg: regInfo{ 10829 inputs: []inputInfo{ 10830 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10831 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10832 }, 10833 outputs: []outputInfo{ 10834 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10835 }, 10836 }, 10837 }, 10838 { 10839 name: "FMULS", 10840 argLen: 2, 10841 commutative: true, 10842 asm: arm64.AFMULS, 10843 reg: regInfo{ 10844 inputs: []inputInfo{ 10845 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10846 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10847 }, 10848 outputs: []outputInfo{ 10849 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10850 }, 10851 }, 10852 }, 10853 { 10854 name: "FMULD", 10855 argLen: 2, 10856 commutative: true, 10857 asm: arm64.AFMULD, 10858 reg: regInfo{ 10859 inputs: []inputInfo{ 10860 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10861 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10862 }, 10863 outputs: []outputInfo{ 10864 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10865 }, 10866 }, 10867 }, 10868 { 10869 name: "FDIVS", 10870 argLen: 2, 10871 asm: arm64.AFDIVS, 10872 reg: regInfo{ 10873 inputs: []inputInfo{ 10874 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10875 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10876 }, 10877 outputs: []outputInfo{ 10878 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10879 }, 10880 }, 10881 }, 10882 { 10883 name: "FDIVD", 10884 argLen: 2, 10885 asm: arm64.AFDIVD, 10886 reg: regInfo{ 10887 inputs: []inputInfo{ 10888 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10889 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10890 }, 10891 outputs: []outputInfo{ 10892 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10893 }, 10894 }, 10895 }, 10896 { 10897 name: "AND", 10898 argLen: 2, 10899 commutative: true, 10900 asm: arm64.AAND, 10901 reg: regInfo{ 10902 inputs: []inputInfo{ 10903 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10904 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10905 }, 10906 outputs: []outputInfo{ 10907 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10908 }, 10909 }, 10910 }, 10911 { 10912 name: "ANDconst", 10913 auxType: auxInt64, 10914 argLen: 1, 10915 asm: arm64.AAND, 10916 reg: regInfo{ 10917 inputs: []inputInfo{ 10918 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10919 }, 10920 outputs: []outputInfo{ 10921 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10922 }, 10923 }, 10924 }, 10925 { 10926 name: "OR", 10927 argLen: 2, 10928 commutative: true, 10929 asm: arm64.AORR, 10930 reg: regInfo{ 10931 inputs: []inputInfo{ 10932 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10933 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10934 }, 10935 outputs: []outputInfo{ 10936 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10937 }, 10938 }, 10939 }, 10940 { 10941 name: "ORconst", 10942 auxType: auxInt64, 10943 argLen: 1, 10944 asm: arm64.AORR, 10945 reg: regInfo{ 10946 inputs: []inputInfo{ 10947 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10948 }, 10949 outputs: []outputInfo{ 10950 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10951 }, 10952 }, 10953 }, 10954 { 10955 name: "XOR", 10956 argLen: 2, 10957 commutative: true, 10958 asm: arm64.AEOR, 10959 reg: regInfo{ 10960 inputs: []inputInfo{ 10961 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10962 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10963 }, 10964 outputs: []outputInfo{ 10965 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10966 }, 10967 }, 10968 }, 10969 { 10970 name: "XORconst", 10971 auxType: auxInt64, 10972 argLen: 1, 10973 asm: arm64.AEOR, 10974 reg: regInfo{ 10975 inputs: []inputInfo{ 10976 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10977 }, 10978 outputs: []outputInfo{ 10979 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10980 }, 10981 }, 10982 }, 10983 { 10984 name: "BIC", 10985 argLen: 2, 10986 asm: arm64.ABIC, 10987 reg: regInfo{ 10988 inputs: []inputInfo{ 10989 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10990 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10991 }, 10992 outputs: []outputInfo{ 10993 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10994 }, 10995 }, 10996 }, 10997 { 10998 name: "BICconst", 10999 auxType: auxInt64, 11000 argLen: 1, 11001 asm: arm64.ABIC, 11002 reg: regInfo{ 11003 inputs: []inputInfo{ 11004 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11005 }, 11006 outputs: []outputInfo{ 11007 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11008 }, 11009 }, 11010 }, 11011 { 11012 name: "MVN", 11013 argLen: 1, 11014 asm: arm64.AMVN, 11015 reg: regInfo{ 11016 inputs: []inputInfo{ 11017 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11018 }, 11019 outputs: []outputInfo{ 11020 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11021 }, 11022 }, 11023 }, 11024 { 11025 name: "NEG", 11026 argLen: 1, 11027 asm: arm64.ANEG, 11028 reg: regInfo{ 11029 inputs: []inputInfo{ 11030 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11031 }, 11032 outputs: []outputInfo{ 11033 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11034 }, 11035 }, 11036 }, 11037 { 11038 name: "FNEGS", 11039 argLen: 1, 11040 asm: arm64.AFNEGS, 11041 reg: regInfo{ 11042 inputs: []inputInfo{ 11043 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11044 }, 11045 outputs: []outputInfo{ 11046 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11047 }, 11048 }, 11049 }, 11050 { 11051 name: "FNEGD", 11052 argLen: 1, 11053 asm: arm64.AFNEGD, 11054 reg: regInfo{ 11055 inputs: []inputInfo{ 11056 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11057 }, 11058 outputs: []outputInfo{ 11059 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11060 }, 11061 }, 11062 }, 11063 { 11064 name: "FSQRTD", 11065 argLen: 1, 11066 asm: arm64.AFSQRTD, 11067 reg: regInfo{ 11068 inputs: []inputInfo{ 11069 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11070 }, 11071 outputs: []outputInfo{ 11072 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11073 }, 11074 }, 11075 }, 11076 { 11077 name: "REV", 11078 argLen: 1, 11079 asm: arm64.AREV, 11080 reg: regInfo{ 11081 inputs: []inputInfo{ 11082 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11083 }, 11084 outputs: []outputInfo{ 11085 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11086 }, 11087 }, 11088 }, 11089 { 11090 name: "REVW", 11091 argLen: 1, 11092 asm: arm64.AREVW, 11093 reg: regInfo{ 11094 inputs: []inputInfo{ 11095 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11096 }, 11097 outputs: []outputInfo{ 11098 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11099 }, 11100 }, 11101 }, 11102 { 11103 name: "REV16W", 11104 argLen: 1, 11105 asm: arm64.AREV16W, 11106 reg: regInfo{ 11107 inputs: []inputInfo{ 11108 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11109 }, 11110 outputs: []outputInfo{ 11111 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11112 }, 11113 }, 11114 }, 11115 { 11116 name: "RBIT", 11117 argLen: 1, 11118 asm: arm64.ARBIT, 11119 reg: regInfo{ 11120 inputs: []inputInfo{ 11121 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11122 }, 11123 outputs: []outputInfo{ 11124 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11125 }, 11126 }, 11127 }, 11128 { 11129 name: "RBITW", 11130 argLen: 1, 11131 asm: arm64.ARBITW, 11132 reg: regInfo{ 11133 inputs: []inputInfo{ 11134 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11135 }, 11136 outputs: []outputInfo{ 11137 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11138 }, 11139 }, 11140 }, 11141 { 11142 name: "CLZ", 11143 argLen: 1, 11144 asm: arm64.ACLZ, 11145 reg: regInfo{ 11146 inputs: []inputInfo{ 11147 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11148 }, 11149 outputs: []outputInfo{ 11150 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11151 }, 11152 }, 11153 }, 11154 { 11155 name: "CLZW", 11156 argLen: 1, 11157 asm: arm64.ACLZW, 11158 reg: regInfo{ 11159 inputs: []inputInfo{ 11160 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11161 }, 11162 outputs: []outputInfo{ 11163 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11164 }, 11165 }, 11166 }, 11167 { 11168 name: "SLL", 11169 argLen: 2, 11170 asm: arm64.ALSL, 11171 reg: regInfo{ 11172 inputs: []inputInfo{ 11173 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11174 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11175 }, 11176 outputs: []outputInfo{ 11177 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11178 }, 11179 }, 11180 }, 11181 { 11182 name: "SLLconst", 11183 auxType: auxInt64, 11184 argLen: 1, 11185 asm: arm64.ALSL, 11186 reg: regInfo{ 11187 inputs: []inputInfo{ 11188 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11189 }, 11190 outputs: []outputInfo{ 11191 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11192 }, 11193 }, 11194 }, 11195 { 11196 name: "SRL", 11197 argLen: 2, 11198 asm: arm64.ALSR, 11199 reg: regInfo{ 11200 inputs: []inputInfo{ 11201 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11202 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11203 }, 11204 outputs: []outputInfo{ 11205 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11206 }, 11207 }, 11208 }, 11209 { 11210 name: "SRLconst", 11211 auxType: auxInt64, 11212 argLen: 1, 11213 asm: arm64.ALSR, 11214 reg: regInfo{ 11215 inputs: []inputInfo{ 11216 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11217 }, 11218 outputs: []outputInfo{ 11219 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11220 }, 11221 }, 11222 }, 11223 { 11224 name: "SRA", 11225 argLen: 2, 11226 asm: arm64.AASR, 11227 reg: regInfo{ 11228 inputs: []inputInfo{ 11229 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11230 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11231 }, 11232 outputs: []outputInfo{ 11233 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11234 }, 11235 }, 11236 }, 11237 { 11238 name: "SRAconst", 11239 auxType: auxInt64, 11240 argLen: 1, 11241 asm: arm64.AASR, 11242 reg: regInfo{ 11243 inputs: []inputInfo{ 11244 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11245 }, 11246 outputs: []outputInfo{ 11247 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11248 }, 11249 }, 11250 }, 11251 { 11252 name: "RORconst", 11253 auxType: auxInt64, 11254 argLen: 1, 11255 asm: arm64.AROR, 11256 reg: regInfo{ 11257 inputs: []inputInfo{ 11258 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11259 }, 11260 outputs: []outputInfo{ 11261 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11262 }, 11263 }, 11264 }, 11265 { 11266 name: "RORWconst", 11267 auxType: auxInt64, 11268 argLen: 1, 11269 asm: arm64.ARORW, 11270 reg: regInfo{ 11271 inputs: []inputInfo{ 11272 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11273 }, 11274 outputs: []outputInfo{ 11275 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11276 }, 11277 }, 11278 }, 11279 { 11280 name: "CMP", 11281 argLen: 2, 11282 asm: arm64.ACMP, 11283 reg: regInfo{ 11284 inputs: []inputInfo{ 11285 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11286 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11287 }, 11288 }, 11289 }, 11290 { 11291 name: "CMPconst", 11292 auxType: auxInt64, 11293 argLen: 1, 11294 asm: arm64.ACMP, 11295 reg: regInfo{ 11296 inputs: []inputInfo{ 11297 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11298 }, 11299 }, 11300 }, 11301 { 11302 name: "CMPW", 11303 argLen: 2, 11304 asm: arm64.ACMPW, 11305 reg: regInfo{ 11306 inputs: []inputInfo{ 11307 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11308 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11309 }, 11310 }, 11311 }, 11312 { 11313 name: "CMPWconst", 11314 auxType: auxInt32, 11315 argLen: 1, 11316 asm: arm64.ACMPW, 11317 reg: regInfo{ 11318 inputs: []inputInfo{ 11319 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11320 }, 11321 }, 11322 }, 11323 { 11324 name: "CMN", 11325 argLen: 2, 11326 asm: arm64.ACMN, 11327 reg: regInfo{ 11328 inputs: []inputInfo{ 11329 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11330 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11331 }, 11332 }, 11333 }, 11334 { 11335 name: "CMNconst", 11336 auxType: auxInt64, 11337 argLen: 1, 11338 asm: arm64.ACMN, 11339 reg: regInfo{ 11340 inputs: []inputInfo{ 11341 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11342 }, 11343 }, 11344 }, 11345 { 11346 name: "CMNW", 11347 argLen: 2, 11348 asm: arm64.ACMNW, 11349 reg: regInfo{ 11350 inputs: []inputInfo{ 11351 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11352 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11353 }, 11354 }, 11355 }, 11356 { 11357 name: "CMNWconst", 11358 auxType: auxInt32, 11359 argLen: 1, 11360 asm: arm64.ACMNW, 11361 reg: regInfo{ 11362 inputs: []inputInfo{ 11363 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11364 }, 11365 }, 11366 }, 11367 { 11368 name: "FCMPS", 11369 argLen: 2, 11370 asm: arm64.AFCMPS, 11371 reg: regInfo{ 11372 inputs: []inputInfo{ 11373 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11374 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11375 }, 11376 }, 11377 }, 11378 { 11379 name: "FCMPD", 11380 argLen: 2, 11381 asm: arm64.AFCMPD, 11382 reg: regInfo{ 11383 inputs: []inputInfo{ 11384 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11385 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11386 }, 11387 }, 11388 }, 11389 { 11390 name: "ADDshiftLL", 11391 auxType: auxInt64, 11392 argLen: 2, 11393 asm: arm64.AADD, 11394 reg: regInfo{ 11395 inputs: []inputInfo{ 11396 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11397 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11398 }, 11399 outputs: []outputInfo{ 11400 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11401 }, 11402 }, 11403 }, 11404 { 11405 name: "ADDshiftRL", 11406 auxType: auxInt64, 11407 argLen: 2, 11408 asm: arm64.AADD, 11409 reg: regInfo{ 11410 inputs: []inputInfo{ 11411 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11412 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11413 }, 11414 outputs: []outputInfo{ 11415 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11416 }, 11417 }, 11418 }, 11419 { 11420 name: "ADDshiftRA", 11421 auxType: auxInt64, 11422 argLen: 2, 11423 asm: arm64.AADD, 11424 reg: regInfo{ 11425 inputs: []inputInfo{ 11426 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11427 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11428 }, 11429 outputs: []outputInfo{ 11430 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11431 }, 11432 }, 11433 }, 11434 { 11435 name: "SUBshiftLL", 11436 auxType: auxInt64, 11437 argLen: 2, 11438 asm: arm64.ASUB, 11439 reg: regInfo{ 11440 inputs: []inputInfo{ 11441 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11442 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11443 }, 11444 outputs: []outputInfo{ 11445 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11446 }, 11447 }, 11448 }, 11449 { 11450 name: "SUBshiftRL", 11451 auxType: auxInt64, 11452 argLen: 2, 11453 asm: arm64.ASUB, 11454 reg: regInfo{ 11455 inputs: []inputInfo{ 11456 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11457 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11458 }, 11459 outputs: []outputInfo{ 11460 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11461 }, 11462 }, 11463 }, 11464 { 11465 name: "SUBshiftRA", 11466 auxType: auxInt64, 11467 argLen: 2, 11468 asm: arm64.ASUB, 11469 reg: regInfo{ 11470 inputs: []inputInfo{ 11471 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11472 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11473 }, 11474 outputs: []outputInfo{ 11475 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11476 }, 11477 }, 11478 }, 11479 { 11480 name: "ANDshiftLL", 11481 auxType: auxInt64, 11482 argLen: 2, 11483 asm: arm64.AAND, 11484 reg: regInfo{ 11485 inputs: []inputInfo{ 11486 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11487 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11488 }, 11489 outputs: []outputInfo{ 11490 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11491 }, 11492 }, 11493 }, 11494 { 11495 name: "ANDshiftRL", 11496 auxType: auxInt64, 11497 argLen: 2, 11498 asm: arm64.AAND, 11499 reg: regInfo{ 11500 inputs: []inputInfo{ 11501 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11502 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11503 }, 11504 outputs: []outputInfo{ 11505 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11506 }, 11507 }, 11508 }, 11509 { 11510 name: "ANDshiftRA", 11511 auxType: auxInt64, 11512 argLen: 2, 11513 asm: arm64.AAND, 11514 reg: regInfo{ 11515 inputs: []inputInfo{ 11516 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11517 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11518 }, 11519 outputs: []outputInfo{ 11520 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11521 }, 11522 }, 11523 }, 11524 { 11525 name: "ORshiftLL", 11526 auxType: auxInt64, 11527 argLen: 2, 11528 asm: arm64.AORR, 11529 reg: regInfo{ 11530 inputs: []inputInfo{ 11531 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11532 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11533 }, 11534 outputs: []outputInfo{ 11535 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11536 }, 11537 }, 11538 }, 11539 { 11540 name: "ORshiftRL", 11541 auxType: auxInt64, 11542 argLen: 2, 11543 asm: arm64.AORR, 11544 reg: regInfo{ 11545 inputs: []inputInfo{ 11546 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11547 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11548 }, 11549 outputs: []outputInfo{ 11550 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11551 }, 11552 }, 11553 }, 11554 { 11555 name: "ORshiftRA", 11556 auxType: auxInt64, 11557 argLen: 2, 11558 asm: arm64.AORR, 11559 reg: regInfo{ 11560 inputs: []inputInfo{ 11561 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11562 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11563 }, 11564 outputs: []outputInfo{ 11565 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11566 }, 11567 }, 11568 }, 11569 { 11570 name: "XORshiftLL", 11571 auxType: auxInt64, 11572 argLen: 2, 11573 asm: arm64.AEOR, 11574 reg: regInfo{ 11575 inputs: []inputInfo{ 11576 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11577 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11578 }, 11579 outputs: []outputInfo{ 11580 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11581 }, 11582 }, 11583 }, 11584 { 11585 name: "XORshiftRL", 11586 auxType: auxInt64, 11587 argLen: 2, 11588 asm: arm64.AEOR, 11589 reg: regInfo{ 11590 inputs: []inputInfo{ 11591 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11592 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11593 }, 11594 outputs: []outputInfo{ 11595 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11596 }, 11597 }, 11598 }, 11599 { 11600 name: "XORshiftRA", 11601 auxType: auxInt64, 11602 argLen: 2, 11603 asm: arm64.AEOR, 11604 reg: regInfo{ 11605 inputs: []inputInfo{ 11606 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11607 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11608 }, 11609 outputs: []outputInfo{ 11610 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11611 }, 11612 }, 11613 }, 11614 { 11615 name: "BICshiftLL", 11616 auxType: auxInt64, 11617 argLen: 2, 11618 asm: arm64.ABIC, 11619 reg: regInfo{ 11620 inputs: []inputInfo{ 11621 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11622 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11623 }, 11624 outputs: []outputInfo{ 11625 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11626 }, 11627 }, 11628 }, 11629 { 11630 name: "BICshiftRL", 11631 auxType: auxInt64, 11632 argLen: 2, 11633 asm: arm64.ABIC, 11634 reg: regInfo{ 11635 inputs: []inputInfo{ 11636 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11637 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11638 }, 11639 outputs: []outputInfo{ 11640 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11641 }, 11642 }, 11643 }, 11644 { 11645 name: "BICshiftRA", 11646 auxType: auxInt64, 11647 argLen: 2, 11648 asm: arm64.ABIC, 11649 reg: regInfo{ 11650 inputs: []inputInfo{ 11651 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11652 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11653 }, 11654 outputs: []outputInfo{ 11655 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11656 }, 11657 }, 11658 }, 11659 { 11660 name: "CMPshiftLL", 11661 auxType: auxInt64, 11662 argLen: 2, 11663 asm: arm64.ACMP, 11664 reg: regInfo{ 11665 inputs: []inputInfo{ 11666 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11667 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11668 }, 11669 }, 11670 }, 11671 { 11672 name: "CMPshiftRL", 11673 auxType: auxInt64, 11674 argLen: 2, 11675 asm: arm64.ACMP, 11676 reg: regInfo{ 11677 inputs: []inputInfo{ 11678 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11679 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11680 }, 11681 }, 11682 }, 11683 { 11684 name: "CMPshiftRA", 11685 auxType: auxInt64, 11686 argLen: 2, 11687 asm: arm64.ACMP, 11688 reg: regInfo{ 11689 inputs: []inputInfo{ 11690 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11691 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11692 }, 11693 }, 11694 }, 11695 { 11696 name: "MOVDconst", 11697 auxType: auxInt64, 11698 argLen: 0, 11699 rematerializeable: true, 11700 asm: arm64.AMOVD, 11701 reg: regInfo{ 11702 outputs: []outputInfo{ 11703 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11704 }, 11705 }, 11706 }, 11707 { 11708 name: "FMOVSconst", 11709 auxType: auxFloat64, 11710 argLen: 0, 11711 rematerializeable: true, 11712 asm: arm64.AFMOVS, 11713 reg: regInfo{ 11714 outputs: []outputInfo{ 11715 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11716 }, 11717 }, 11718 }, 11719 { 11720 name: "FMOVDconst", 11721 auxType: auxFloat64, 11722 argLen: 0, 11723 rematerializeable: true, 11724 asm: arm64.AFMOVD, 11725 reg: regInfo{ 11726 outputs: []outputInfo{ 11727 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11728 }, 11729 }, 11730 }, 11731 { 11732 name: "MOVDaddr", 11733 auxType: auxSymOff, 11734 argLen: 1, 11735 rematerializeable: true, 11736 asm: arm64.AMOVD, 11737 reg: regInfo{ 11738 inputs: []inputInfo{ 11739 {0, 9223372037928517632}, // SP SB 11740 }, 11741 outputs: []outputInfo{ 11742 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11743 }, 11744 }, 11745 }, 11746 { 11747 name: "MOVBload", 11748 auxType: auxSymOff, 11749 argLen: 2, 11750 faultOnNilArg0: true, 11751 asm: arm64.AMOVB, 11752 reg: regInfo{ 11753 inputs: []inputInfo{ 11754 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11755 }, 11756 outputs: []outputInfo{ 11757 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11758 }, 11759 }, 11760 }, 11761 { 11762 name: "MOVBUload", 11763 auxType: auxSymOff, 11764 argLen: 2, 11765 faultOnNilArg0: true, 11766 asm: arm64.AMOVBU, 11767 reg: regInfo{ 11768 inputs: []inputInfo{ 11769 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11770 }, 11771 outputs: []outputInfo{ 11772 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11773 }, 11774 }, 11775 }, 11776 { 11777 name: "MOVHload", 11778 auxType: auxSymOff, 11779 argLen: 2, 11780 faultOnNilArg0: true, 11781 asm: arm64.AMOVH, 11782 reg: regInfo{ 11783 inputs: []inputInfo{ 11784 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11785 }, 11786 outputs: []outputInfo{ 11787 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11788 }, 11789 }, 11790 }, 11791 { 11792 name: "MOVHUload", 11793 auxType: auxSymOff, 11794 argLen: 2, 11795 faultOnNilArg0: true, 11796 asm: arm64.AMOVHU, 11797 reg: regInfo{ 11798 inputs: []inputInfo{ 11799 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11800 }, 11801 outputs: []outputInfo{ 11802 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11803 }, 11804 }, 11805 }, 11806 { 11807 name: "MOVWload", 11808 auxType: auxSymOff, 11809 argLen: 2, 11810 faultOnNilArg0: true, 11811 asm: arm64.AMOVW, 11812 reg: regInfo{ 11813 inputs: []inputInfo{ 11814 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11815 }, 11816 outputs: []outputInfo{ 11817 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11818 }, 11819 }, 11820 }, 11821 { 11822 name: "MOVWUload", 11823 auxType: auxSymOff, 11824 argLen: 2, 11825 faultOnNilArg0: true, 11826 asm: arm64.AMOVWU, 11827 reg: regInfo{ 11828 inputs: []inputInfo{ 11829 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11830 }, 11831 outputs: []outputInfo{ 11832 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11833 }, 11834 }, 11835 }, 11836 { 11837 name: "MOVDload", 11838 auxType: auxSymOff, 11839 argLen: 2, 11840 faultOnNilArg0: true, 11841 asm: arm64.AMOVD, 11842 reg: regInfo{ 11843 inputs: []inputInfo{ 11844 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11845 }, 11846 outputs: []outputInfo{ 11847 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11848 }, 11849 }, 11850 }, 11851 { 11852 name: "FMOVSload", 11853 auxType: auxSymOff, 11854 argLen: 2, 11855 faultOnNilArg0: true, 11856 asm: arm64.AFMOVS, 11857 reg: regInfo{ 11858 inputs: []inputInfo{ 11859 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11860 }, 11861 outputs: []outputInfo{ 11862 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11863 }, 11864 }, 11865 }, 11866 { 11867 name: "FMOVDload", 11868 auxType: auxSymOff, 11869 argLen: 2, 11870 faultOnNilArg0: true, 11871 asm: arm64.AFMOVD, 11872 reg: regInfo{ 11873 inputs: []inputInfo{ 11874 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11875 }, 11876 outputs: []outputInfo{ 11877 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11878 }, 11879 }, 11880 }, 11881 { 11882 name: "MOVBstore", 11883 auxType: auxSymOff, 11884 argLen: 3, 11885 faultOnNilArg0: true, 11886 asm: arm64.AMOVB, 11887 reg: regInfo{ 11888 inputs: []inputInfo{ 11889 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11890 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11891 }, 11892 }, 11893 }, 11894 { 11895 name: "MOVHstore", 11896 auxType: auxSymOff, 11897 argLen: 3, 11898 faultOnNilArg0: true, 11899 asm: arm64.AMOVH, 11900 reg: regInfo{ 11901 inputs: []inputInfo{ 11902 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11903 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11904 }, 11905 }, 11906 }, 11907 { 11908 name: "MOVWstore", 11909 auxType: auxSymOff, 11910 argLen: 3, 11911 faultOnNilArg0: true, 11912 asm: arm64.AMOVW, 11913 reg: regInfo{ 11914 inputs: []inputInfo{ 11915 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11916 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11917 }, 11918 }, 11919 }, 11920 { 11921 name: "MOVDstore", 11922 auxType: auxSymOff, 11923 argLen: 3, 11924 faultOnNilArg0: true, 11925 asm: arm64.AMOVD, 11926 reg: regInfo{ 11927 inputs: []inputInfo{ 11928 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11929 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11930 }, 11931 }, 11932 }, 11933 { 11934 name: "FMOVSstore", 11935 auxType: auxSymOff, 11936 argLen: 3, 11937 faultOnNilArg0: true, 11938 asm: arm64.AFMOVS, 11939 reg: regInfo{ 11940 inputs: []inputInfo{ 11941 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11942 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11943 }, 11944 }, 11945 }, 11946 { 11947 name: "FMOVDstore", 11948 auxType: auxSymOff, 11949 argLen: 3, 11950 faultOnNilArg0: true, 11951 asm: arm64.AFMOVD, 11952 reg: regInfo{ 11953 inputs: []inputInfo{ 11954 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11955 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11956 }, 11957 }, 11958 }, 11959 { 11960 name: "MOVBstorezero", 11961 auxType: auxSymOff, 11962 argLen: 2, 11963 faultOnNilArg0: true, 11964 asm: arm64.AMOVB, 11965 reg: regInfo{ 11966 inputs: []inputInfo{ 11967 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11968 }, 11969 }, 11970 }, 11971 { 11972 name: "MOVHstorezero", 11973 auxType: auxSymOff, 11974 argLen: 2, 11975 faultOnNilArg0: true, 11976 asm: arm64.AMOVH, 11977 reg: regInfo{ 11978 inputs: []inputInfo{ 11979 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11980 }, 11981 }, 11982 }, 11983 { 11984 name: "MOVWstorezero", 11985 auxType: auxSymOff, 11986 argLen: 2, 11987 faultOnNilArg0: true, 11988 asm: arm64.AMOVW, 11989 reg: regInfo{ 11990 inputs: []inputInfo{ 11991 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11992 }, 11993 }, 11994 }, 11995 { 11996 name: "MOVDstorezero", 11997 auxType: auxSymOff, 11998 argLen: 2, 11999 faultOnNilArg0: true, 12000 asm: arm64.AMOVD, 12001 reg: regInfo{ 12002 inputs: []inputInfo{ 12003 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12004 }, 12005 }, 12006 }, 12007 { 12008 name: "MOVBreg", 12009 argLen: 1, 12010 asm: arm64.AMOVB, 12011 reg: regInfo{ 12012 inputs: []inputInfo{ 12013 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12014 }, 12015 outputs: []outputInfo{ 12016 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12017 }, 12018 }, 12019 }, 12020 { 12021 name: "MOVBUreg", 12022 argLen: 1, 12023 asm: arm64.AMOVBU, 12024 reg: regInfo{ 12025 inputs: []inputInfo{ 12026 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12027 }, 12028 outputs: []outputInfo{ 12029 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12030 }, 12031 }, 12032 }, 12033 { 12034 name: "MOVHreg", 12035 argLen: 1, 12036 asm: arm64.AMOVH, 12037 reg: regInfo{ 12038 inputs: []inputInfo{ 12039 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12040 }, 12041 outputs: []outputInfo{ 12042 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12043 }, 12044 }, 12045 }, 12046 { 12047 name: "MOVHUreg", 12048 argLen: 1, 12049 asm: arm64.AMOVHU, 12050 reg: regInfo{ 12051 inputs: []inputInfo{ 12052 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12053 }, 12054 outputs: []outputInfo{ 12055 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12056 }, 12057 }, 12058 }, 12059 { 12060 name: "MOVWreg", 12061 argLen: 1, 12062 asm: arm64.AMOVW, 12063 reg: regInfo{ 12064 inputs: []inputInfo{ 12065 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12066 }, 12067 outputs: []outputInfo{ 12068 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12069 }, 12070 }, 12071 }, 12072 { 12073 name: "MOVWUreg", 12074 argLen: 1, 12075 asm: arm64.AMOVWU, 12076 reg: regInfo{ 12077 inputs: []inputInfo{ 12078 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12079 }, 12080 outputs: []outputInfo{ 12081 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12082 }, 12083 }, 12084 }, 12085 { 12086 name: "MOVDreg", 12087 argLen: 1, 12088 asm: arm64.AMOVD, 12089 reg: regInfo{ 12090 inputs: []inputInfo{ 12091 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12092 }, 12093 outputs: []outputInfo{ 12094 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12095 }, 12096 }, 12097 }, 12098 { 12099 name: "MOVDnop", 12100 argLen: 1, 12101 resultInArg0: true, 12102 reg: regInfo{ 12103 inputs: []inputInfo{ 12104 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12105 }, 12106 outputs: []outputInfo{ 12107 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12108 }, 12109 }, 12110 }, 12111 { 12112 name: "SCVTFWS", 12113 argLen: 1, 12114 asm: arm64.ASCVTFWS, 12115 reg: regInfo{ 12116 inputs: []inputInfo{ 12117 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12118 }, 12119 outputs: []outputInfo{ 12120 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12121 }, 12122 }, 12123 }, 12124 { 12125 name: "SCVTFWD", 12126 argLen: 1, 12127 asm: arm64.ASCVTFWD, 12128 reg: regInfo{ 12129 inputs: []inputInfo{ 12130 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12131 }, 12132 outputs: []outputInfo{ 12133 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12134 }, 12135 }, 12136 }, 12137 { 12138 name: "UCVTFWS", 12139 argLen: 1, 12140 asm: arm64.AUCVTFWS, 12141 reg: regInfo{ 12142 inputs: []inputInfo{ 12143 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12144 }, 12145 outputs: []outputInfo{ 12146 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12147 }, 12148 }, 12149 }, 12150 { 12151 name: "UCVTFWD", 12152 argLen: 1, 12153 asm: arm64.AUCVTFWD, 12154 reg: regInfo{ 12155 inputs: []inputInfo{ 12156 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12157 }, 12158 outputs: []outputInfo{ 12159 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12160 }, 12161 }, 12162 }, 12163 { 12164 name: "SCVTFS", 12165 argLen: 1, 12166 asm: arm64.ASCVTFS, 12167 reg: regInfo{ 12168 inputs: []inputInfo{ 12169 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12170 }, 12171 outputs: []outputInfo{ 12172 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12173 }, 12174 }, 12175 }, 12176 { 12177 name: "SCVTFD", 12178 argLen: 1, 12179 asm: arm64.ASCVTFD, 12180 reg: regInfo{ 12181 inputs: []inputInfo{ 12182 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12183 }, 12184 outputs: []outputInfo{ 12185 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12186 }, 12187 }, 12188 }, 12189 { 12190 name: "UCVTFS", 12191 argLen: 1, 12192 asm: arm64.AUCVTFS, 12193 reg: regInfo{ 12194 inputs: []inputInfo{ 12195 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12196 }, 12197 outputs: []outputInfo{ 12198 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12199 }, 12200 }, 12201 }, 12202 { 12203 name: "UCVTFD", 12204 argLen: 1, 12205 asm: arm64.AUCVTFD, 12206 reg: regInfo{ 12207 inputs: []inputInfo{ 12208 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12209 }, 12210 outputs: []outputInfo{ 12211 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12212 }, 12213 }, 12214 }, 12215 { 12216 name: "FCVTZSSW", 12217 argLen: 1, 12218 asm: arm64.AFCVTZSSW, 12219 reg: regInfo{ 12220 inputs: []inputInfo{ 12221 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12222 }, 12223 outputs: []outputInfo{ 12224 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12225 }, 12226 }, 12227 }, 12228 { 12229 name: "FCVTZSDW", 12230 argLen: 1, 12231 asm: arm64.AFCVTZSDW, 12232 reg: regInfo{ 12233 inputs: []inputInfo{ 12234 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12235 }, 12236 outputs: []outputInfo{ 12237 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12238 }, 12239 }, 12240 }, 12241 { 12242 name: "FCVTZUSW", 12243 argLen: 1, 12244 asm: arm64.AFCVTZUSW, 12245 reg: regInfo{ 12246 inputs: []inputInfo{ 12247 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12248 }, 12249 outputs: []outputInfo{ 12250 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12251 }, 12252 }, 12253 }, 12254 { 12255 name: "FCVTZUDW", 12256 argLen: 1, 12257 asm: arm64.AFCVTZUDW, 12258 reg: regInfo{ 12259 inputs: []inputInfo{ 12260 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12261 }, 12262 outputs: []outputInfo{ 12263 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12264 }, 12265 }, 12266 }, 12267 { 12268 name: "FCVTZSS", 12269 argLen: 1, 12270 asm: arm64.AFCVTZSS, 12271 reg: regInfo{ 12272 inputs: []inputInfo{ 12273 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12274 }, 12275 outputs: []outputInfo{ 12276 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12277 }, 12278 }, 12279 }, 12280 { 12281 name: "FCVTZSD", 12282 argLen: 1, 12283 asm: arm64.AFCVTZSD, 12284 reg: regInfo{ 12285 inputs: []inputInfo{ 12286 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12287 }, 12288 outputs: []outputInfo{ 12289 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12290 }, 12291 }, 12292 }, 12293 { 12294 name: "FCVTZUS", 12295 argLen: 1, 12296 asm: arm64.AFCVTZUS, 12297 reg: regInfo{ 12298 inputs: []inputInfo{ 12299 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12300 }, 12301 outputs: []outputInfo{ 12302 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12303 }, 12304 }, 12305 }, 12306 { 12307 name: "FCVTZUD", 12308 argLen: 1, 12309 asm: arm64.AFCVTZUD, 12310 reg: regInfo{ 12311 inputs: []inputInfo{ 12312 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12313 }, 12314 outputs: []outputInfo{ 12315 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12316 }, 12317 }, 12318 }, 12319 { 12320 name: "FCVTSD", 12321 argLen: 1, 12322 asm: arm64.AFCVTSD, 12323 reg: regInfo{ 12324 inputs: []inputInfo{ 12325 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12326 }, 12327 outputs: []outputInfo{ 12328 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12329 }, 12330 }, 12331 }, 12332 { 12333 name: "FCVTDS", 12334 argLen: 1, 12335 asm: arm64.AFCVTDS, 12336 reg: regInfo{ 12337 inputs: []inputInfo{ 12338 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12339 }, 12340 outputs: []outputInfo{ 12341 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12342 }, 12343 }, 12344 }, 12345 { 12346 name: "CSELULT", 12347 argLen: 3, 12348 asm: arm64.ACSEL, 12349 reg: regInfo{ 12350 inputs: []inputInfo{ 12351 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12352 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12353 }, 12354 outputs: []outputInfo{ 12355 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12356 }, 12357 }, 12358 }, 12359 { 12360 name: "CSELULT0", 12361 argLen: 2, 12362 asm: arm64.ACSEL, 12363 reg: regInfo{ 12364 inputs: []inputInfo{ 12365 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12366 }, 12367 outputs: []outputInfo{ 12368 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12369 }, 12370 }, 12371 }, 12372 { 12373 name: "CALLstatic", 12374 auxType: auxSymOff, 12375 argLen: 1, 12376 clobberFlags: true, 12377 call: true, 12378 reg: regInfo{ 12379 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12380 }, 12381 }, 12382 { 12383 name: "CALLclosure", 12384 auxType: auxInt64, 12385 argLen: 3, 12386 clobberFlags: true, 12387 call: true, 12388 reg: regInfo{ 12389 inputs: []inputInfo{ 12390 {1, 67108864}, // R26 12391 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 12392 }, 12393 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12394 }, 12395 }, 12396 { 12397 name: "CALLdefer", 12398 auxType: auxInt64, 12399 argLen: 1, 12400 clobberFlags: true, 12401 call: true, 12402 reg: regInfo{ 12403 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12404 }, 12405 }, 12406 { 12407 name: "CALLgo", 12408 auxType: auxInt64, 12409 argLen: 1, 12410 clobberFlags: true, 12411 call: true, 12412 reg: regInfo{ 12413 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12414 }, 12415 }, 12416 { 12417 name: "CALLinter", 12418 auxType: auxInt64, 12419 argLen: 2, 12420 clobberFlags: true, 12421 call: true, 12422 reg: regInfo{ 12423 inputs: []inputInfo{ 12424 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12425 }, 12426 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12427 }, 12428 }, 12429 { 12430 name: "LoweredNilCheck", 12431 argLen: 2, 12432 nilCheck: true, 12433 faultOnNilArg0: true, 12434 reg: regInfo{ 12435 inputs: []inputInfo{ 12436 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12437 }, 12438 }, 12439 }, 12440 { 12441 name: "Equal", 12442 argLen: 1, 12443 reg: regInfo{ 12444 outputs: []outputInfo{ 12445 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12446 }, 12447 }, 12448 }, 12449 { 12450 name: "NotEqual", 12451 argLen: 1, 12452 reg: regInfo{ 12453 outputs: []outputInfo{ 12454 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12455 }, 12456 }, 12457 }, 12458 { 12459 name: "LessThan", 12460 argLen: 1, 12461 reg: regInfo{ 12462 outputs: []outputInfo{ 12463 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12464 }, 12465 }, 12466 }, 12467 { 12468 name: "LessEqual", 12469 argLen: 1, 12470 reg: regInfo{ 12471 outputs: []outputInfo{ 12472 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12473 }, 12474 }, 12475 }, 12476 { 12477 name: "GreaterThan", 12478 argLen: 1, 12479 reg: regInfo{ 12480 outputs: []outputInfo{ 12481 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12482 }, 12483 }, 12484 }, 12485 { 12486 name: "GreaterEqual", 12487 argLen: 1, 12488 reg: regInfo{ 12489 outputs: []outputInfo{ 12490 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12491 }, 12492 }, 12493 }, 12494 { 12495 name: "LessThanU", 12496 argLen: 1, 12497 reg: regInfo{ 12498 outputs: []outputInfo{ 12499 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12500 }, 12501 }, 12502 }, 12503 { 12504 name: "LessEqualU", 12505 argLen: 1, 12506 reg: regInfo{ 12507 outputs: []outputInfo{ 12508 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12509 }, 12510 }, 12511 }, 12512 { 12513 name: "GreaterThanU", 12514 argLen: 1, 12515 reg: regInfo{ 12516 outputs: []outputInfo{ 12517 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12518 }, 12519 }, 12520 }, 12521 { 12522 name: "GreaterEqualU", 12523 argLen: 1, 12524 reg: regInfo{ 12525 outputs: []outputInfo{ 12526 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12527 }, 12528 }, 12529 }, 12530 { 12531 name: "DUFFZERO", 12532 auxType: auxInt64, 12533 argLen: 2, 12534 faultOnNilArg0: true, 12535 reg: regInfo{ 12536 inputs: []inputInfo{ 12537 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12538 }, 12539 clobbers: 536936448, // R16 R30 12540 }, 12541 }, 12542 { 12543 name: "LoweredZero", 12544 argLen: 3, 12545 clobberFlags: true, 12546 faultOnNilArg0: true, 12547 reg: regInfo{ 12548 inputs: []inputInfo{ 12549 {0, 65536}, // R16 12550 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12551 }, 12552 clobbers: 65536, // R16 12553 }, 12554 }, 12555 { 12556 name: "DUFFCOPY", 12557 auxType: auxInt64, 12558 argLen: 3, 12559 faultOnNilArg0: true, 12560 faultOnNilArg1: true, 12561 reg: regInfo{ 12562 inputs: []inputInfo{ 12563 {0, 131072}, // R17 12564 {1, 65536}, // R16 12565 }, 12566 clobbers: 537067520, // R16 R17 R30 12567 }, 12568 }, 12569 { 12570 name: "LoweredMove", 12571 argLen: 4, 12572 clobberFlags: true, 12573 faultOnNilArg0: true, 12574 faultOnNilArg1: true, 12575 reg: regInfo{ 12576 inputs: []inputInfo{ 12577 {0, 131072}, // R17 12578 {1, 65536}, // R16 12579 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12580 }, 12581 clobbers: 196608, // R16 R17 12582 }, 12583 }, 12584 { 12585 name: "LoweredGetClosurePtr", 12586 argLen: 0, 12587 reg: regInfo{ 12588 outputs: []outputInfo{ 12589 {0, 67108864}, // R26 12590 }, 12591 }, 12592 }, 12593 { 12594 name: "MOVDconvert", 12595 argLen: 2, 12596 asm: arm64.AMOVD, 12597 reg: regInfo{ 12598 inputs: []inputInfo{ 12599 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12600 }, 12601 outputs: []outputInfo{ 12602 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12603 }, 12604 }, 12605 }, 12606 { 12607 name: "FlagEQ", 12608 argLen: 0, 12609 reg: regInfo{}, 12610 }, 12611 { 12612 name: "FlagLT_ULT", 12613 argLen: 0, 12614 reg: regInfo{}, 12615 }, 12616 { 12617 name: "FlagLT_UGT", 12618 argLen: 0, 12619 reg: regInfo{}, 12620 }, 12621 { 12622 name: "FlagGT_UGT", 12623 argLen: 0, 12624 reg: regInfo{}, 12625 }, 12626 { 12627 name: "FlagGT_ULT", 12628 argLen: 0, 12629 reg: regInfo{}, 12630 }, 12631 { 12632 name: "InvertFlags", 12633 argLen: 1, 12634 reg: regInfo{}, 12635 }, 12636 { 12637 name: "LDAR", 12638 argLen: 2, 12639 faultOnNilArg0: true, 12640 asm: arm64.ALDAR, 12641 reg: regInfo{ 12642 inputs: []inputInfo{ 12643 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12644 }, 12645 outputs: []outputInfo{ 12646 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12647 }, 12648 }, 12649 }, 12650 { 12651 name: "LDARW", 12652 argLen: 2, 12653 faultOnNilArg0: true, 12654 asm: arm64.ALDARW, 12655 reg: regInfo{ 12656 inputs: []inputInfo{ 12657 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12658 }, 12659 outputs: []outputInfo{ 12660 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12661 }, 12662 }, 12663 }, 12664 { 12665 name: "STLR", 12666 argLen: 3, 12667 faultOnNilArg0: true, 12668 asm: arm64.ASTLR, 12669 reg: regInfo{ 12670 inputs: []inputInfo{ 12671 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12672 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12673 }, 12674 }, 12675 }, 12676 { 12677 name: "STLRW", 12678 argLen: 3, 12679 faultOnNilArg0: true, 12680 asm: arm64.ASTLRW, 12681 reg: regInfo{ 12682 inputs: []inputInfo{ 12683 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12684 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12685 }, 12686 }, 12687 }, 12688 { 12689 name: "LoweredAtomicExchange64", 12690 argLen: 3, 12691 resultNotInArgs: true, 12692 faultOnNilArg0: true, 12693 reg: regInfo{ 12694 inputs: []inputInfo{ 12695 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12696 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12697 }, 12698 outputs: []outputInfo{ 12699 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12700 }, 12701 }, 12702 }, 12703 { 12704 name: "LoweredAtomicExchange32", 12705 argLen: 3, 12706 resultNotInArgs: true, 12707 faultOnNilArg0: true, 12708 reg: regInfo{ 12709 inputs: []inputInfo{ 12710 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12711 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12712 }, 12713 outputs: []outputInfo{ 12714 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12715 }, 12716 }, 12717 }, 12718 { 12719 name: "LoweredAtomicAdd64", 12720 argLen: 3, 12721 resultNotInArgs: true, 12722 faultOnNilArg0: true, 12723 reg: regInfo{ 12724 inputs: []inputInfo{ 12725 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12726 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12727 }, 12728 outputs: []outputInfo{ 12729 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12730 }, 12731 }, 12732 }, 12733 { 12734 name: "LoweredAtomicAdd32", 12735 argLen: 3, 12736 resultNotInArgs: true, 12737 faultOnNilArg0: true, 12738 reg: regInfo{ 12739 inputs: []inputInfo{ 12740 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12741 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12742 }, 12743 outputs: []outputInfo{ 12744 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12745 }, 12746 }, 12747 }, 12748 { 12749 name: "LoweredAtomicCas64", 12750 argLen: 4, 12751 resultNotInArgs: true, 12752 clobberFlags: true, 12753 faultOnNilArg0: true, 12754 reg: regInfo{ 12755 inputs: []inputInfo{ 12756 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12757 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12758 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12759 }, 12760 outputs: []outputInfo{ 12761 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12762 }, 12763 }, 12764 }, 12765 { 12766 name: "LoweredAtomicCas32", 12767 argLen: 4, 12768 resultNotInArgs: true, 12769 clobberFlags: true, 12770 faultOnNilArg0: true, 12771 reg: regInfo{ 12772 inputs: []inputInfo{ 12773 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12774 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12775 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12776 }, 12777 outputs: []outputInfo{ 12778 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12779 }, 12780 }, 12781 }, 12782 { 12783 name: "LoweredAtomicAnd8", 12784 argLen: 3, 12785 faultOnNilArg0: true, 12786 asm: arm64.AAND, 12787 reg: regInfo{ 12788 inputs: []inputInfo{ 12789 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12790 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12791 }, 12792 }, 12793 }, 12794 { 12795 name: "LoweredAtomicOr8", 12796 argLen: 3, 12797 faultOnNilArg0: true, 12798 asm: arm64.AORR, 12799 reg: regInfo{ 12800 inputs: []inputInfo{ 12801 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12802 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12803 }, 12804 }, 12805 }, 12806 12807 { 12808 name: "ADD", 12809 argLen: 2, 12810 commutative: true, 12811 asm: mips.AADDU, 12812 reg: regInfo{ 12813 inputs: []inputInfo{ 12814 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12815 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12816 }, 12817 outputs: []outputInfo{ 12818 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12819 }, 12820 }, 12821 }, 12822 { 12823 name: "ADDconst", 12824 auxType: auxInt32, 12825 argLen: 1, 12826 asm: mips.AADDU, 12827 reg: regInfo{ 12828 inputs: []inputInfo{ 12829 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 12830 }, 12831 outputs: []outputInfo{ 12832 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12833 }, 12834 }, 12835 }, 12836 { 12837 name: "SUB", 12838 argLen: 2, 12839 asm: mips.ASUBU, 12840 reg: regInfo{ 12841 inputs: []inputInfo{ 12842 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12843 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12844 }, 12845 outputs: []outputInfo{ 12846 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12847 }, 12848 }, 12849 }, 12850 { 12851 name: "SUBconst", 12852 auxType: auxInt32, 12853 argLen: 1, 12854 asm: mips.ASUBU, 12855 reg: regInfo{ 12856 inputs: []inputInfo{ 12857 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12858 }, 12859 outputs: []outputInfo{ 12860 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12861 }, 12862 }, 12863 }, 12864 { 12865 name: "MUL", 12866 argLen: 2, 12867 commutative: true, 12868 asm: mips.AMUL, 12869 reg: regInfo{ 12870 inputs: []inputInfo{ 12871 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12872 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12873 }, 12874 clobbers: 105553116266496, // HI LO 12875 outputs: []outputInfo{ 12876 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12877 }, 12878 }, 12879 }, 12880 { 12881 name: "MULT", 12882 argLen: 2, 12883 commutative: true, 12884 asm: mips.AMUL, 12885 reg: regInfo{ 12886 inputs: []inputInfo{ 12887 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12888 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12889 }, 12890 outputs: []outputInfo{ 12891 {0, 35184372088832}, // HI 12892 {1, 70368744177664}, // LO 12893 }, 12894 }, 12895 }, 12896 { 12897 name: "MULTU", 12898 argLen: 2, 12899 commutative: true, 12900 asm: mips.AMULU, 12901 reg: regInfo{ 12902 inputs: []inputInfo{ 12903 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12904 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12905 }, 12906 outputs: []outputInfo{ 12907 {0, 35184372088832}, // HI 12908 {1, 70368744177664}, // LO 12909 }, 12910 }, 12911 }, 12912 { 12913 name: "DIV", 12914 argLen: 2, 12915 asm: mips.ADIV, 12916 reg: regInfo{ 12917 inputs: []inputInfo{ 12918 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12919 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12920 }, 12921 outputs: []outputInfo{ 12922 {0, 35184372088832}, // HI 12923 {1, 70368744177664}, // LO 12924 }, 12925 }, 12926 }, 12927 { 12928 name: "DIVU", 12929 argLen: 2, 12930 asm: mips.ADIVU, 12931 reg: regInfo{ 12932 inputs: []inputInfo{ 12933 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12934 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12935 }, 12936 outputs: []outputInfo{ 12937 {0, 35184372088832}, // HI 12938 {1, 70368744177664}, // LO 12939 }, 12940 }, 12941 }, 12942 { 12943 name: "ADDF", 12944 argLen: 2, 12945 commutative: true, 12946 asm: mips.AADDF, 12947 reg: regInfo{ 12948 inputs: []inputInfo{ 12949 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12950 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12951 }, 12952 outputs: []outputInfo{ 12953 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12954 }, 12955 }, 12956 }, 12957 { 12958 name: "ADDD", 12959 argLen: 2, 12960 commutative: true, 12961 asm: mips.AADDD, 12962 reg: regInfo{ 12963 inputs: []inputInfo{ 12964 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12965 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12966 }, 12967 outputs: []outputInfo{ 12968 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12969 }, 12970 }, 12971 }, 12972 { 12973 name: "SUBF", 12974 argLen: 2, 12975 asm: mips.ASUBF, 12976 reg: regInfo{ 12977 inputs: []inputInfo{ 12978 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12979 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12980 }, 12981 outputs: []outputInfo{ 12982 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12983 }, 12984 }, 12985 }, 12986 { 12987 name: "SUBD", 12988 argLen: 2, 12989 asm: mips.ASUBD, 12990 reg: regInfo{ 12991 inputs: []inputInfo{ 12992 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12993 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12994 }, 12995 outputs: []outputInfo{ 12996 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12997 }, 12998 }, 12999 }, 13000 { 13001 name: "MULF", 13002 argLen: 2, 13003 commutative: true, 13004 asm: mips.AMULF, 13005 reg: regInfo{ 13006 inputs: []inputInfo{ 13007 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13008 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13009 }, 13010 outputs: []outputInfo{ 13011 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13012 }, 13013 }, 13014 }, 13015 { 13016 name: "MULD", 13017 argLen: 2, 13018 commutative: true, 13019 asm: mips.AMULD, 13020 reg: regInfo{ 13021 inputs: []inputInfo{ 13022 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13023 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13024 }, 13025 outputs: []outputInfo{ 13026 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13027 }, 13028 }, 13029 }, 13030 { 13031 name: "DIVF", 13032 argLen: 2, 13033 asm: mips.ADIVF, 13034 reg: regInfo{ 13035 inputs: []inputInfo{ 13036 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13037 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13038 }, 13039 outputs: []outputInfo{ 13040 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13041 }, 13042 }, 13043 }, 13044 { 13045 name: "DIVD", 13046 argLen: 2, 13047 asm: mips.ADIVD, 13048 reg: regInfo{ 13049 inputs: []inputInfo{ 13050 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13051 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13052 }, 13053 outputs: []outputInfo{ 13054 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13055 }, 13056 }, 13057 }, 13058 { 13059 name: "AND", 13060 argLen: 2, 13061 commutative: true, 13062 asm: mips.AAND, 13063 reg: regInfo{ 13064 inputs: []inputInfo{ 13065 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13066 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13067 }, 13068 outputs: []outputInfo{ 13069 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13070 }, 13071 }, 13072 }, 13073 { 13074 name: "ANDconst", 13075 auxType: auxInt32, 13076 argLen: 1, 13077 asm: mips.AAND, 13078 reg: regInfo{ 13079 inputs: []inputInfo{ 13080 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13081 }, 13082 outputs: []outputInfo{ 13083 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13084 }, 13085 }, 13086 }, 13087 { 13088 name: "OR", 13089 argLen: 2, 13090 commutative: true, 13091 asm: mips.AOR, 13092 reg: regInfo{ 13093 inputs: []inputInfo{ 13094 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13095 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13096 }, 13097 outputs: []outputInfo{ 13098 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13099 }, 13100 }, 13101 }, 13102 { 13103 name: "ORconst", 13104 auxType: auxInt32, 13105 argLen: 1, 13106 asm: mips.AOR, 13107 reg: regInfo{ 13108 inputs: []inputInfo{ 13109 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13110 }, 13111 outputs: []outputInfo{ 13112 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13113 }, 13114 }, 13115 }, 13116 { 13117 name: "XOR", 13118 argLen: 2, 13119 commutative: true, 13120 asm: mips.AXOR, 13121 reg: regInfo{ 13122 inputs: []inputInfo{ 13123 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13124 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13125 }, 13126 outputs: []outputInfo{ 13127 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13128 }, 13129 }, 13130 }, 13131 { 13132 name: "XORconst", 13133 auxType: auxInt32, 13134 argLen: 1, 13135 asm: mips.AXOR, 13136 reg: regInfo{ 13137 inputs: []inputInfo{ 13138 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13139 }, 13140 outputs: []outputInfo{ 13141 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13142 }, 13143 }, 13144 }, 13145 { 13146 name: "NOR", 13147 argLen: 2, 13148 commutative: true, 13149 asm: mips.ANOR, 13150 reg: regInfo{ 13151 inputs: []inputInfo{ 13152 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13153 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13154 }, 13155 outputs: []outputInfo{ 13156 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13157 }, 13158 }, 13159 }, 13160 { 13161 name: "NORconst", 13162 auxType: auxInt32, 13163 argLen: 1, 13164 asm: mips.ANOR, 13165 reg: regInfo{ 13166 inputs: []inputInfo{ 13167 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13168 }, 13169 outputs: []outputInfo{ 13170 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13171 }, 13172 }, 13173 }, 13174 { 13175 name: "NEG", 13176 argLen: 1, 13177 reg: regInfo{ 13178 inputs: []inputInfo{ 13179 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13180 }, 13181 outputs: []outputInfo{ 13182 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13183 }, 13184 }, 13185 }, 13186 { 13187 name: "NEGF", 13188 argLen: 1, 13189 asm: mips.ANEGF, 13190 reg: regInfo{ 13191 inputs: []inputInfo{ 13192 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13193 }, 13194 outputs: []outputInfo{ 13195 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13196 }, 13197 }, 13198 }, 13199 { 13200 name: "NEGD", 13201 argLen: 1, 13202 asm: mips.ANEGD, 13203 reg: regInfo{ 13204 inputs: []inputInfo{ 13205 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13206 }, 13207 outputs: []outputInfo{ 13208 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13209 }, 13210 }, 13211 }, 13212 { 13213 name: "SQRTD", 13214 argLen: 1, 13215 asm: mips.ASQRTD, 13216 reg: regInfo{ 13217 inputs: []inputInfo{ 13218 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13219 }, 13220 outputs: []outputInfo{ 13221 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13222 }, 13223 }, 13224 }, 13225 { 13226 name: "SLL", 13227 argLen: 2, 13228 asm: mips.ASLL, 13229 reg: regInfo{ 13230 inputs: []inputInfo{ 13231 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13232 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13233 }, 13234 outputs: []outputInfo{ 13235 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13236 }, 13237 }, 13238 }, 13239 { 13240 name: "SLLconst", 13241 auxType: auxInt32, 13242 argLen: 1, 13243 asm: mips.ASLL, 13244 reg: regInfo{ 13245 inputs: []inputInfo{ 13246 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13247 }, 13248 outputs: []outputInfo{ 13249 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13250 }, 13251 }, 13252 }, 13253 { 13254 name: "SRL", 13255 argLen: 2, 13256 asm: mips.ASRL, 13257 reg: regInfo{ 13258 inputs: []inputInfo{ 13259 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13260 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13261 }, 13262 outputs: []outputInfo{ 13263 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13264 }, 13265 }, 13266 }, 13267 { 13268 name: "SRLconst", 13269 auxType: auxInt32, 13270 argLen: 1, 13271 asm: mips.ASRL, 13272 reg: regInfo{ 13273 inputs: []inputInfo{ 13274 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13275 }, 13276 outputs: []outputInfo{ 13277 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13278 }, 13279 }, 13280 }, 13281 { 13282 name: "SRA", 13283 argLen: 2, 13284 asm: mips.ASRA, 13285 reg: regInfo{ 13286 inputs: []inputInfo{ 13287 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13288 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13289 }, 13290 outputs: []outputInfo{ 13291 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13292 }, 13293 }, 13294 }, 13295 { 13296 name: "SRAconst", 13297 auxType: auxInt32, 13298 argLen: 1, 13299 asm: mips.ASRA, 13300 reg: regInfo{ 13301 inputs: []inputInfo{ 13302 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13303 }, 13304 outputs: []outputInfo{ 13305 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13306 }, 13307 }, 13308 }, 13309 { 13310 name: "CLZ", 13311 argLen: 1, 13312 asm: mips.ACLZ, 13313 reg: regInfo{ 13314 inputs: []inputInfo{ 13315 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13316 }, 13317 outputs: []outputInfo{ 13318 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13319 }, 13320 }, 13321 }, 13322 { 13323 name: "SGT", 13324 argLen: 2, 13325 asm: mips.ASGT, 13326 reg: regInfo{ 13327 inputs: []inputInfo{ 13328 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13329 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13330 }, 13331 outputs: []outputInfo{ 13332 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13333 }, 13334 }, 13335 }, 13336 { 13337 name: "SGTconst", 13338 auxType: auxInt32, 13339 argLen: 1, 13340 asm: mips.ASGT, 13341 reg: regInfo{ 13342 inputs: []inputInfo{ 13343 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13344 }, 13345 outputs: []outputInfo{ 13346 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13347 }, 13348 }, 13349 }, 13350 { 13351 name: "SGTzero", 13352 argLen: 1, 13353 asm: mips.ASGT, 13354 reg: regInfo{ 13355 inputs: []inputInfo{ 13356 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13357 }, 13358 outputs: []outputInfo{ 13359 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13360 }, 13361 }, 13362 }, 13363 { 13364 name: "SGTU", 13365 argLen: 2, 13366 asm: mips.ASGTU, 13367 reg: regInfo{ 13368 inputs: []inputInfo{ 13369 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13370 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13371 }, 13372 outputs: []outputInfo{ 13373 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13374 }, 13375 }, 13376 }, 13377 { 13378 name: "SGTUconst", 13379 auxType: auxInt32, 13380 argLen: 1, 13381 asm: mips.ASGTU, 13382 reg: regInfo{ 13383 inputs: []inputInfo{ 13384 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13385 }, 13386 outputs: []outputInfo{ 13387 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13388 }, 13389 }, 13390 }, 13391 { 13392 name: "SGTUzero", 13393 argLen: 1, 13394 asm: mips.ASGTU, 13395 reg: regInfo{ 13396 inputs: []inputInfo{ 13397 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13398 }, 13399 outputs: []outputInfo{ 13400 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13401 }, 13402 }, 13403 }, 13404 { 13405 name: "CMPEQF", 13406 argLen: 2, 13407 asm: mips.ACMPEQF, 13408 reg: regInfo{ 13409 inputs: []inputInfo{ 13410 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13411 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13412 }, 13413 }, 13414 }, 13415 { 13416 name: "CMPEQD", 13417 argLen: 2, 13418 asm: mips.ACMPEQD, 13419 reg: regInfo{ 13420 inputs: []inputInfo{ 13421 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13422 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13423 }, 13424 }, 13425 }, 13426 { 13427 name: "CMPGEF", 13428 argLen: 2, 13429 asm: mips.ACMPGEF, 13430 reg: regInfo{ 13431 inputs: []inputInfo{ 13432 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13433 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13434 }, 13435 }, 13436 }, 13437 { 13438 name: "CMPGED", 13439 argLen: 2, 13440 asm: mips.ACMPGED, 13441 reg: regInfo{ 13442 inputs: []inputInfo{ 13443 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13444 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13445 }, 13446 }, 13447 }, 13448 { 13449 name: "CMPGTF", 13450 argLen: 2, 13451 asm: mips.ACMPGTF, 13452 reg: regInfo{ 13453 inputs: []inputInfo{ 13454 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13455 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13456 }, 13457 }, 13458 }, 13459 { 13460 name: "CMPGTD", 13461 argLen: 2, 13462 asm: mips.ACMPGTD, 13463 reg: regInfo{ 13464 inputs: []inputInfo{ 13465 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13466 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13467 }, 13468 }, 13469 }, 13470 { 13471 name: "MOVWconst", 13472 auxType: auxInt32, 13473 argLen: 0, 13474 rematerializeable: true, 13475 asm: mips.AMOVW, 13476 reg: regInfo{ 13477 outputs: []outputInfo{ 13478 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13479 }, 13480 }, 13481 }, 13482 { 13483 name: "MOVFconst", 13484 auxType: auxFloat32, 13485 argLen: 0, 13486 rematerializeable: true, 13487 asm: mips.AMOVF, 13488 reg: regInfo{ 13489 outputs: []outputInfo{ 13490 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13491 }, 13492 }, 13493 }, 13494 { 13495 name: "MOVDconst", 13496 auxType: auxFloat64, 13497 argLen: 0, 13498 rematerializeable: true, 13499 asm: mips.AMOVD, 13500 reg: regInfo{ 13501 outputs: []outputInfo{ 13502 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13503 }, 13504 }, 13505 }, 13506 { 13507 name: "MOVWaddr", 13508 auxType: auxSymOff, 13509 argLen: 1, 13510 rematerializeable: true, 13511 asm: mips.AMOVW, 13512 reg: regInfo{ 13513 inputs: []inputInfo{ 13514 {0, 140737555464192}, // SP SB 13515 }, 13516 outputs: []outputInfo{ 13517 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13518 }, 13519 }, 13520 }, 13521 { 13522 name: "MOVBload", 13523 auxType: auxSymOff, 13524 argLen: 2, 13525 faultOnNilArg0: true, 13526 asm: mips.AMOVB, 13527 reg: regInfo{ 13528 inputs: []inputInfo{ 13529 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13530 }, 13531 outputs: []outputInfo{ 13532 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13533 }, 13534 }, 13535 }, 13536 { 13537 name: "MOVBUload", 13538 auxType: auxSymOff, 13539 argLen: 2, 13540 faultOnNilArg0: true, 13541 asm: mips.AMOVBU, 13542 reg: regInfo{ 13543 inputs: []inputInfo{ 13544 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13545 }, 13546 outputs: []outputInfo{ 13547 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13548 }, 13549 }, 13550 }, 13551 { 13552 name: "MOVHload", 13553 auxType: auxSymOff, 13554 argLen: 2, 13555 faultOnNilArg0: true, 13556 asm: mips.AMOVH, 13557 reg: regInfo{ 13558 inputs: []inputInfo{ 13559 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13560 }, 13561 outputs: []outputInfo{ 13562 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13563 }, 13564 }, 13565 }, 13566 { 13567 name: "MOVHUload", 13568 auxType: auxSymOff, 13569 argLen: 2, 13570 faultOnNilArg0: true, 13571 asm: mips.AMOVHU, 13572 reg: regInfo{ 13573 inputs: []inputInfo{ 13574 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13575 }, 13576 outputs: []outputInfo{ 13577 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13578 }, 13579 }, 13580 }, 13581 { 13582 name: "MOVWload", 13583 auxType: auxSymOff, 13584 argLen: 2, 13585 faultOnNilArg0: true, 13586 asm: mips.AMOVW, 13587 reg: regInfo{ 13588 inputs: []inputInfo{ 13589 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13590 }, 13591 outputs: []outputInfo{ 13592 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13593 }, 13594 }, 13595 }, 13596 { 13597 name: "MOVFload", 13598 auxType: auxSymOff, 13599 argLen: 2, 13600 faultOnNilArg0: true, 13601 asm: mips.AMOVF, 13602 reg: regInfo{ 13603 inputs: []inputInfo{ 13604 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13605 }, 13606 outputs: []outputInfo{ 13607 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13608 }, 13609 }, 13610 }, 13611 { 13612 name: "MOVDload", 13613 auxType: auxSymOff, 13614 argLen: 2, 13615 faultOnNilArg0: true, 13616 asm: mips.AMOVD, 13617 reg: regInfo{ 13618 inputs: []inputInfo{ 13619 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13620 }, 13621 outputs: []outputInfo{ 13622 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13623 }, 13624 }, 13625 }, 13626 { 13627 name: "MOVBstore", 13628 auxType: auxSymOff, 13629 argLen: 3, 13630 faultOnNilArg0: true, 13631 asm: mips.AMOVB, 13632 reg: regInfo{ 13633 inputs: []inputInfo{ 13634 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13635 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13636 }, 13637 }, 13638 }, 13639 { 13640 name: "MOVHstore", 13641 auxType: auxSymOff, 13642 argLen: 3, 13643 faultOnNilArg0: true, 13644 asm: mips.AMOVH, 13645 reg: regInfo{ 13646 inputs: []inputInfo{ 13647 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13648 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13649 }, 13650 }, 13651 }, 13652 { 13653 name: "MOVWstore", 13654 auxType: auxSymOff, 13655 argLen: 3, 13656 faultOnNilArg0: true, 13657 asm: mips.AMOVW, 13658 reg: regInfo{ 13659 inputs: []inputInfo{ 13660 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13661 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13662 }, 13663 }, 13664 }, 13665 { 13666 name: "MOVFstore", 13667 auxType: auxSymOff, 13668 argLen: 3, 13669 faultOnNilArg0: true, 13670 asm: mips.AMOVF, 13671 reg: regInfo{ 13672 inputs: []inputInfo{ 13673 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13674 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13675 }, 13676 }, 13677 }, 13678 { 13679 name: "MOVDstore", 13680 auxType: auxSymOff, 13681 argLen: 3, 13682 faultOnNilArg0: true, 13683 asm: mips.AMOVD, 13684 reg: regInfo{ 13685 inputs: []inputInfo{ 13686 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13687 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13688 }, 13689 }, 13690 }, 13691 { 13692 name: "MOVBstorezero", 13693 auxType: auxSymOff, 13694 argLen: 2, 13695 faultOnNilArg0: true, 13696 asm: mips.AMOVB, 13697 reg: regInfo{ 13698 inputs: []inputInfo{ 13699 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13700 }, 13701 }, 13702 }, 13703 { 13704 name: "MOVHstorezero", 13705 auxType: auxSymOff, 13706 argLen: 2, 13707 faultOnNilArg0: true, 13708 asm: mips.AMOVH, 13709 reg: regInfo{ 13710 inputs: []inputInfo{ 13711 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13712 }, 13713 }, 13714 }, 13715 { 13716 name: "MOVWstorezero", 13717 auxType: auxSymOff, 13718 argLen: 2, 13719 faultOnNilArg0: true, 13720 asm: mips.AMOVW, 13721 reg: regInfo{ 13722 inputs: []inputInfo{ 13723 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13724 }, 13725 }, 13726 }, 13727 { 13728 name: "MOVBreg", 13729 argLen: 1, 13730 asm: mips.AMOVB, 13731 reg: regInfo{ 13732 inputs: []inputInfo{ 13733 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13734 }, 13735 outputs: []outputInfo{ 13736 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13737 }, 13738 }, 13739 }, 13740 { 13741 name: "MOVBUreg", 13742 argLen: 1, 13743 asm: mips.AMOVBU, 13744 reg: regInfo{ 13745 inputs: []inputInfo{ 13746 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13747 }, 13748 outputs: []outputInfo{ 13749 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13750 }, 13751 }, 13752 }, 13753 { 13754 name: "MOVHreg", 13755 argLen: 1, 13756 asm: mips.AMOVH, 13757 reg: regInfo{ 13758 inputs: []inputInfo{ 13759 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13760 }, 13761 outputs: []outputInfo{ 13762 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13763 }, 13764 }, 13765 }, 13766 { 13767 name: "MOVHUreg", 13768 argLen: 1, 13769 asm: mips.AMOVHU, 13770 reg: regInfo{ 13771 inputs: []inputInfo{ 13772 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13773 }, 13774 outputs: []outputInfo{ 13775 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13776 }, 13777 }, 13778 }, 13779 { 13780 name: "MOVWreg", 13781 argLen: 1, 13782 asm: mips.AMOVW, 13783 reg: regInfo{ 13784 inputs: []inputInfo{ 13785 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13786 }, 13787 outputs: []outputInfo{ 13788 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13789 }, 13790 }, 13791 }, 13792 { 13793 name: "MOVWnop", 13794 argLen: 1, 13795 resultInArg0: true, 13796 reg: regInfo{ 13797 inputs: []inputInfo{ 13798 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13799 }, 13800 outputs: []outputInfo{ 13801 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13802 }, 13803 }, 13804 }, 13805 { 13806 name: "CMOVZ", 13807 argLen: 3, 13808 resultInArg0: true, 13809 asm: mips.ACMOVZ, 13810 reg: regInfo{ 13811 inputs: []inputInfo{ 13812 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13813 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13814 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13815 }, 13816 outputs: []outputInfo{ 13817 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13818 }, 13819 }, 13820 }, 13821 { 13822 name: "CMOVZzero", 13823 argLen: 2, 13824 resultInArg0: true, 13825 asm: mips.ACMOVZ, 13826 reg: regInfo{ 13827 inputs: []inputInfo{ 13828 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13829 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13830 }, 13831 outputs: []outputInfo{ 13832 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13833 }, 13834 }, 13835 }, 13836 { 13837 name: "MOVWF", 13838 argLen: 1, 13839 asm: mips.AMOVWF, 13840 reg: regInfo{ 13841 inputs: []inputInfo{ 13842 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13843 }, 13844 outputs: []outputInfo{ 13845 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13846 }, 13847 }, 13848 }, 13849 { 13850 name: "MOVWD", 13851 argLen: 1, 13852 asm: mips.AMOVWD, 13853 reg: regInfo{ 13854 inputs: []inputInfo{ 13855 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13856 }, 13857 outputs: []outputInfo{ 13858 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13859 }, 13860 }, 13861 }, 13862 { 13863 name: "TRUNCFW", 13864 argLen: 1, 13865 asm: mips.ATRUNCFW, 13866 reg: regInfo{ 13867 inputs: []inputInfo{ 13868 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13869 }, 13870 outputs: []outputInfo{ 13871 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13872 }, 13873 }, 13874 }, 13875 { 13876 name: "TRUNCDW", 13877 argLen: 1, 13878 asm: mips.ATRUNCDW, 13879 reg: regInfo{ 13880 inputs: []inputInfo{ 13881 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13882 }, 13883 outputs: []outputInfo{ 13884 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13885 }, 13886 }, 13887 }, 13888 { 13889 name: "MOVFD", 13890 argLen: 1, 13891 asm: mips.AMOVFD, 13892 reg: regInfo{ 13893 inputs: []inputInfo{ 13894 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13895 }, 13896 outputs: []outputInfo{ 13897 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13898 }, 13899 }, 13900 }, 13901 { 13902 name: "MOVDF", 13903 argLen: 1, 13904 asm: mips.AMOVDF, 13905 reg: regInfo{ 13906 inputs: []inputInfo{ 13907 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13908 }, 13909 outputs: []outputInfo{ 13910 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13911 }, 13912 }, 13913 }, 13914 { 13915 name: "CALLstatic", 13916 auxType: auxSymOff, 13917 argLen: 1, 13918 clobberFlags: true, 13919 call: true, 13920 reg: regInfo{ 13921 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13922 }, 13923 }, 13924 { 13925 name: "CALLclosure", 13926 auxType: auxInt32, 13927 argLen: 3, 13928 clobberFlags: true, 13929 call: true, 13930 reg: regInfo{ 13931 inputs: []inputInfo{ 13932 {1, 4194304}, // R22 13933 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 13934 }, 13935 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13936 }, 13937 }, 13938 { 13939 name: "CALLdefer", 13940 auxType: auxInt32, 13941 argLen: 1, 13942 clobberFlags: true, 13943 call: true, 13944 reg: regInfo{ 13945 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13946 }, 13947 }, 13948 { 13949 name: "CALLgo", 13950 auxType: auxInt32, 13951 argLen: 1, 13952 clobberFlags: true, 13953 call: true, 13954 reg: regInfo{ 13955 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13956 }, 13957 }, 13958 { 13959 name: "CALLinter", 13960 auxType: auxInt32, 13961 argLen: 2, 13962 clobberFlags: true, 13963 call: true, 13964 reg: regInfo{ 13965 inputs: []inputInfo{ 13966 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13967 }, 13968 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13969 }, 13970 }, 13971 { 13972 name: "LoweredAtomicLoad", 13973 argLen: 2, 13974 faultOnNilArg0: true, 13975 reg: regInfo{ 13976 inputs: []inputInfo{ 13977 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13978 }, 13979 outputs: []outputInfo{ 13980 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13981 }, 13982 }, 13983 }, 13984 { 13985 name: "LoweredAtomicStore", 13986 argLen: 3, 13987 faultOnNilArg0: true, 13988 reg: regInfo{ 13989 inputs: []inputInfo{ 13990 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13991 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13992 }, 13993 }, 13994 }, 13995 { 13996 name: "LoweredAtomicStorezero", 13997 argLen: 2, 13998 faultOnNilArg0: true, 13999 reg: regInfo{ 14000 inputs: []inputInfo{ 14001 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14002 }, 14003 }, 14004 }, 14005 { 14006 name: "LoweredAtomicExchange", 14007 argLen: 3, 14008 resultNotInArgs: true, 14009 faultOnNilArg0: true, 14010 reg: regInfo{ 14011 inputs: []inputInfo{ 14012 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14013 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14014 }, 14015 outputs: []outputInfo{ 14016 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14017 }, 14018 }, 14019 }, 14020 { 14021 name: "LoweredAtomicAdd", 14022 argLen: 3, 14023 resultNotInArgs: true, 14024 faultOnNilArg0: true, 14025 reg: regInfo{ 14026 inputs: []inputInfo{ 14027 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14028 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14029 }, 14030 outputs: []outputInfo{ 14031 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14032 }, 14033 }, 14034 }, 14035 { 14036 name: "LoweredAtomicAddconst", 14037 auxType: auxInt32, 14038 argLen: 2, 14039 resultNotInArgs: true, 14040 faultOnNilArg0: true, 14041 reg: regInfo{ 14042 inputs: []inputInfo{ 14043 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14044 }, 14045 outputs: []outputInfo{ 14046 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14047 }, 14048 }, 14049 }, 14050 { 14051 name: "LoweredAtomicCas", 14052 argLen: 4, 14053 resultNotInArgs: true, 14054 faultOnNilArg0: true, 14055 reg: regInfo{ 14056 inputs: []inputInfo{ 14057 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14058 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14059 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14060 }, 14061 outputs: []outputInfo{ 14062 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14063 }, 14064 }, 14065 }, 14066 { 14067 name: "LoweredAtomicAnd", 14068 argLen: 3, 14069 faultOnNilArg0: true, 14070 asm: mips.AAND, 14071 reg: regInfo{ 14072 inputs: []inputInfo{ 14073 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14074 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14075 }, 14076 }, 14077 }, 14078 { 14079 name: "LoweredAtomicOr", 14080 argLen: 3, 14081 faultOnNilArg0: true, 14082 asm: mips.AOR, 14083 reg: regInfo{ 14084 inputs: []inputInfo{ 14085 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14086 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14087 }, 14088 }, 14089 }, 14090 { 14091 name: "LoweredZero", 14092 auxType: auxInt32, 14093 argLen: 3, 14094 faultOnNilArg0: true, 14095 reg: regInfo{ 14096 inputs: []inputInfo{ 14097 {0, 2}, // R1 14098 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14099 }, 14100 clobbers: 2, // R1 14101 }, 14102 }, 14103 { 14104 name: "LoweredMove", 14105 auxType: auxInt32, 14106 argLen: 4, 14107 faultOnNilArg0: true, 14108 faultOnNilArg1: true, 14109 reg: regInfo{ 14110 inputs: []inputInfo{ 14111 {0, 4}, // R2 14112 {1, 2}, // R1 14113 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14114 }, 14115 clobbers: 6, // R1 R2 14116 }, 14117 }, 14118 { 14119 name: "LoweredNilCheck", 14120 argLen: 2, 14121 nilCheck: true, 14122 faultOnNilArg0: true, 14123 reg: regInfo{ 14124 inputs: []inputInfo{ 14125 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14126 }, 14127 }, 14128 }, 14129 { 14130 name: "FPFlagTrue", 14131 argLen: 1, 14132 reg: regInfo{ 14133 outputs: []outputInfo{ 14134 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14135 }, 14136 }, 14137 }, 14138 { 14139 name: "FPFlagFalse", 14140 argLen: 1, 14141 reg: regInfo{ 14142 outputs: []outputInfo{ 14143 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14144 }, 14145 }, 14146 }, 14147 { 14148 name: "LoweredGetClosurePtr", 14149 argLen: 0, 14150 reg: regInfo{ 14151 outputs: []outputInfo{ 14152 {0, 4194304}, // R22 14153 }, 14154 }, 14155 }, 14156 { 14157 name: "MOVWconvert", 14158 argLen: 2, 14159 asm: mips.AMOVW, 14160 reg: regInfo{ 14161 inputs: []inputInfo{ 14162 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14163 }, 14164 outputs: []outputInfo{ 14165 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14166 }, 14167 }, 14168 }, 14169 14170 { 14171 name: "ADDV", 14172 argLen: 2, 14173 commutative: true, 14174 asm: mips.AADDVU, 14175 reg: regInfo{ 14176 inputs: []inputInfo{ 14177 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14178 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14179 }, 14180 outputs: []outputInfo{ 14181 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14182 }, 14183 }, 14184 }, 14185 { 14186 name: "ADDVconst", 14187 auxType: auxInt64, 14188 argLen: 1, 14189 asm: mips.AADDVU, 14190 reg: regInfo{ 14191 inputs: []inputInfo{ 14192 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 14193 }, 14194 outputs: []outputInfo{ 14195 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14196 }, 14197 }, 14198 }, 14199 { 14200 name: "SUBV", 14201 argLen: 2, 14202 asm: mips.ASUBVU, 14203 reg: regInfo{ 14204 inputs: []inputInfo{ 14205 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14206 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14207 }, 14208 outputs: []outputInfo{ 14209 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14210 }, 14211 }, 14212 }, 14213 { 14214 name: "SUBVconst", 14215 auxType: auxInt64, 14216 argLen: 1, 14217 asm: mips.ASUBVU, 14218 reg: regInfo{ 14219 inputs: []inputInfo{ 14220 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14221 }, 14222 outputs: []outputInfo{ 14223 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14224 }, 14225 }, 14226 }, 14227 { 14228 name: "MULV", 14229 argLen: 2, 14230 commutative: true, 14231 asm: mips.AMULV, 14232 reg: regInfo{ 14233 inputs: []inputInfo{ 14234 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14235 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14236 }, 14237 outputs: []outputInfo{ 14238 {0, 1152921504606846976}, // HI 14239 {1, 2305843009213693952}, // LO 14240 }, 14241 }, 14242 }, 14243 { 14244 name: "MULVU", 14245 argLen: 2, 14246 commutative: true, 14247 asm: mips.AMULVU, 14248 reg: regInfo{ 14249 inputs: []inputInfo{ 14250 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14251 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14252 }, 14253 outputs: []outputInfo{ 14254 {0, 1152921504606846976}, // HI 14255 {1, 2305843009213693952}, // LO 14256 }, 14257 }, 14258 }, 14259 { 14260 name: "DIVV", 14261 argLen: 2, 14262 asm: mips.ADIVV, 14263 reg: regInfo{ 14264 inputs: []inputInfo{ 14265 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14266 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14267 }, 14268 outputs: []outputInfo{ 14269 {0, 1152921504606846976}, // HI 14270 {1, 2305843009213693952}, // LO 14271 }, 14272 }, 14273 }, 14274 { 14275 name: "DIVVU", 14276 argLen: 2, 14277 asm: mips.ADIVVU, 14278 reg: regInfo{ 14279 inputs: []inputInfo{ 14280 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14281 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14282 }, 14283 outputs: []outputInfo{ 14284 {0, 1152921504606846976}, // HI 14285 {1, 2305843009213693952}, // LO 14286 }, 14287 }, 14288 }, 14289 { 14290 name: "ADDF", 14291 argLen: 2, 14292 commutative: true, 14293 asm: mips.AADDF, 14294 reg: regInfo{ 14295 inputs: []inputInfo{ 14296 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14297 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14298 }, 14299 outputs: []outputInfo{ 14300 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14301 }, 14302 }, 14303 }, 14304 { 14305 name: "ADDD", 14306 argLen: 2, 14307 commutative: true, 14308 asm: mips.AADDD, 14309 reg: regInfo{ 14310 inputs: []inputInfo{ 14311 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14312 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14313 }, 14314 outputs: []outputInfo{ 14315 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14316 }, 14317 }, 14318 }, 14319 { 14320 name: "SUBF", 14321 argLen: 2, 14322 asm: mips.ASUBF, 14323 reg: regInfo{ 14324 inputs: []inputInfo{ 14325 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14326 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14327 }, 14328 outputs: []outputInfo{ 14329 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14330 }, 14331 }, 14332 }, 14333 { 14334 name: "SUBD", 14335 argLen: 2, 14336 asm: mips.ASUBD, 14337 reg: regInfo{ 14338 inputs: []inputInfo{ 14339 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14340 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14341 }, 14342 outputs: []outputInfo{ 14343 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14344 }, 14345 }, 14346 }, 14347 { 14348 name: "MULF", 14349 argLen: 2, 14350 commutative: true, 14351 asm: mips.AMULF, 14352 reg: regInfo{ 14353 inputs: []inputInfo{ 14354 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14355 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14356 }, 14357 outputs: []outputInfo{ 14358 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14359 }, 14360 }, 14361 }, 14362 { 14363 name: "MULD", 14364 argLen: 2, 14365 commutative: true, 14366 asm: mips.AMULD, 14367 reg: regInfo{ 14368 inputs: []inputInfo{ 14369 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14370 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14371 }, 14372 outputs: []outputInfo{ 14373 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14374 }, 14375 }, 14376 }, 14377 { 14378 name: "DIVF", 14379 argLen: 2, 14380 asm: mips.ADIVF, 14381 reg: regInfo{ 14382 inputs: []inputInfo{ 14383 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14384 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14385 }, 14386 outputs: []outputInfo{ 14387 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14388 }, 14389 }, 14390 }, 14391 { 14392 name: "DIVD", 14393 argLen: 2, 14394 asm: mips.ADIVD, 14395 reg: regInfo{ 14396 inputs: []inputInfo{ 14397 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14398 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14399 }, 14400 outputs: []outputInfo{ 14401 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14402 }, 14403 }, 14404 }, 14405 { 14406 name: "AND", 14407 argLen: 2, 14408 commutative: true, 14409 asm: mips.AAND, 14410 reg: regInfo{ 14411 inputs: []inputInfo{ 14412 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14413 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14414 }, 14415 outputs: []outputInfo{ 14416 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14417 }, 14418 }, 14419 }, 14420 { 14421 name: "ANDconst", 14422 auxType: auxInt64, 14423 argLen: 1, 14424 asm: mips.AAND, 14425 reg: regInfo{ 14426 inputs: []inputInfo{ 14427 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14428 }, 14429 outputs: []outputInfo{ 14430 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14431 }, 14432 }, 14433 }, 14434 { 14435 name: "OR", 14436 argLen: 2, 14437 commutative: true, 14438 asm: mips.AOR, 14439 reg: regInfo{ 14440 inputs: []inputInfo{ 14441 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14442 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14443 }, 14444 outputs: []outputInfo{ 14445 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14446 }, 14447 }, 14448 }, 14449 { 14450 name: "ORconst", 14451 auxType: auxInt64, 14452 argLen: 1, 14453 asm: mips.AOR, 14454 reg: regInfo{ 14455 inputs: []inputInfo{ 14456 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14457 }, 14458 outputs: []outputInfo{ 14459 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14460 }, 14461 }, 14462 }, 14463 { 14464 name: "XOR", 14465 argLen: 2, 14466 commutative: true, 14467 asm: mips.AXOR, 14468 reg: regInfo{ 14469 inputs: []inputInfo{ 14470 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14471 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14472 }, 14473 outputs: []outputInfo{ 14474 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14475 }, 14476 }, 14477 }, 14478 { 14479 name: "XORconst", 14480 auxType: auxInt64, 14481 argLen: 1, 14482 asm: mips.AXOR, 14483 reg: regInfo{ 14484 inputs: []inputInfo{ 14485 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14486 }, 14487 outputs: []outputInfo{ 14488 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14489 }, 14490 }, 14491 }, 14492 { 14493 name: "NOR", 14494 argLen: 2, 14495 commutative: true, 14496 asm: mips.ANOR, 14497 reg: regInfo{ 14498 inputs: []inputInfo{ 14499 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14500 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14501 }, 14502 outputs: []outputInfo{ 14503 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14504 }, 14505 }, 14506 }, 14507 { 14508 name: "NORconst", 14509 auxType: auxInt64, 14510 argLen: 1, 14511 asm: mips.ANOR, 14512 reg: regInfo{ 14513 inputs: []inputInfo{ 14514 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14515 }, 14516 outputs: []outputInfo{ 14517 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14518 }, 14519 }, 14520 }, 14521 { 14522 name: "NEGV", 14523 argLen: 1, 14524 reg: regInfo{ 14525 inputs: []inputInfo{ 14526 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14527 }, 14528 outputs: []outputInfo{ 14529 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14530 }, 14531 }, 14532 }, 14533 { 14534 name: "NEGF", 14535 argLen: 1, 14536 asm: mips.ANEGF, 14537 reg: regInfo{ 14538 inputs: []inputInfo{ 14539 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14540 }, 14541 outputs: []outputInfo{ 14542 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14543 }, 14544 }, 14545 }, 14546 { 14547 name: "NEGD", 14548 argLen: 1, 14549 asm: mips.ANEGD, 14550 reg: regInfo{ 14551 inputs: []inputInfo{ 14552 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14553 }, 14554 outputs: []outputInfo{ 14555 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14556 }, 14557 }, 14558 }, 14559 { 14560 name: "SLLV", 14561 argLen: 2, 14562 asm: mips.ASLLV, 14563 reg: regInfo{ 14564 inputs: []inputInfo{ 14565 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14566 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14567 }, 14568 outputs: []outputInfo{ 14569 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14570 }, 14571 }, 14572 }, 14573 { 14574 name: "SLLVconst", 14575 auxType: auxInt64, 14576 argLen: 1, 14577 asm: mips.ASLLV, 14578 reg: regInfo{ 14579 inputs: []inputInfo{ 14580 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14581 }, 14582 outputs: []outputInfo{ 14583 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14584 }, 14585 }, 14586 }, 14587 { 14588 name: "SRLV", 14589 argLen: 2, 14590 asm: mips.ASRLV, 14591 reg: regInfo{ 14592 inputs: []inputInfo{ 14593 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14594 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14595 }, 14596 outputs: []outputInfo{ 14597 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14598 }, 14599 }, 14600 }, 14601 { 14602 name: "SRLVconst", 14603 auxType: auxInt64, 14604 argLen: 1, 14605 asm: mips.ASRLV, 14606 reg: regInfo{ 14607 inputs: []inputInfo{ 14608 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14609 }, 14610 outputs: []outputInfo{ 14611 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14612 }, 14613 }, 14614 }, 14615 { 14616 name: "SRAV", 14617 argLen: 2, 14618 asm: mips.ASRAV, 14619 reg: regInfo{ 14620 inputs: []inputInfo{ 14621 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14622 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14623 }, 14624 outputs: []outputInfo{ 14625 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14626 }, 14627 }, 14628 }, 14629 { 14630 name: "SRAVconst", 14631 auxType: auxInt64, 14632 argLen: 1, 14633 asm: mips.ASRAV, 14634 reg: regInfo{ 14635 inputs: []inputInfo{ 14636 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14637 }, 14638 outputs: []outputInfo{ 14639 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14640 }, 14641 }, 14642 }, 14643 { 14644 name: "SGT", 14645 argLen: 2, 14646 asm: mips.ASGT, 14647 reg: regInfo{ 14648 inputs: []inputInfo{ 14649 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14650 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14651 }, 14652 outputs: []outputInfo{ 14653 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14654 }, 14655 }, 14656 }, 14657 { 14658 name: "SGTconst", 14659 auxType: auxInt64, 14660 argLen: 1, 14661 asm: mips.ASGT, 14662 reg: regInfo{ 14663 inputs: []inputInfo{ 14664 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14665 }, 14666 outputs: []outputInfo{ 14667 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14668 }, 14669 }, 14670 }, 14671 { 14672 name: "SGTU", 14673 argLen: 2, 14674 asm: mips.ASGTU, 14675 reg: regInfo{ 14676 inputs: []inputInfo{ 14677 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14678 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14679 }, 14680 outputs: []outputInfo{ 14681 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14682 }, 14683 }, 14684 }, 14685 { 14686 name: "SGTUconst", 14687 auxType: auxInt64, 14688 argLen: 1, 14689 asm: mips.ASGTU, 14690 reg: regInfo{ 14691 inputs: []inputInfo{ 14692 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14693 }, 14694 outputs: []outputInfo{ 14695 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14696 }, 14697 }, 14698 }, 14699 { 14700 name: "CMPEQF", 14701 argLen: 2, 14702 asm: mips.ACMPEQF, 14703 reg: regInfo{ 14704 inputs: []inputInfo{ 14705 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14706 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14707 }, 14708 }, 14709 }, 14710 { 14711 name: "CMPEQD", 14712 argLen: 2, 14713 asm: mips.ACMPEQD, 14714 reg: regInfo{ 14715 inputs: []inputInfo{ 14716 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14717 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14718 }, 14719 }, 14720 }, 14721 { 14722 name: "CMPGEF", 14723 argLen: 2, 14724 asm: mips.ACMPGEF, 14725 reg: regInfo{ 14726 inputs: []inputInfo{ 14727 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14728 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14729 }, 14730 }, 14731 }, 14732 { 14733 name: "CMPGED", 14734 argLen: 2, 14735 asm: mips.ACMPGED, 14736 reg: regInfo{ 14737 inputs: []inputInfo{ 14738 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14739 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14740 }, 14741 }, 14742 }, 14743 { 14744 name: "CMPGTF", 14745 argLen: 2, 14746 asm: mips.ACMPGTF, 14747 reg: regInfo{ 14748 inputs: []inputInfo{ 14749 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14750 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14751 }, 14752 }, 14753 }, 14754 { 14755 name: "CMPGTD", 14756 argLen: 2, 14757 asm: mips.ACMPGTD, 14758 reg: regInfo{ 14759 inputs: []inputInfo{ 14760 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14761 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14762 }, 14763 }, 14764 }, 14765 { 14766 name: "MOVVconst", 14767 auxType: auxInt64, 14768 argLen: 0, 14769 rematerializeable: true, 14770 asm: mips.AMOVV, 14771 reg: regInfo{ 14772 outputs: []outputInfo{ 14773 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14774 }, 14775 }, 14776 }, 14777 { 14778 name: "MOVFconst", 14779 auxType: auxFloat64, 14780 argLen: 0, 14781 rematerializeable: true, 14782 asm: mips.AMOVF, 14783 reg: regInfo{ 14784 outputs: []outputInfo{ 14785 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14786 }, 14787 }, 14788 }, 14789 { 14790 name: "MOVDconst", 14791 auxType: auxFloat64, 14792 argLen: 0, 14793 rematerializeable: true, 14794 asm: mips.AMOVD, 14795 reg: regInfo{ 14796 outputs: []outputInfo{ 14797 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14798 }, 14799 }, 14800 }, 14801 { 14802 name: "MOVVaddr", 14803 auxType: auxSymOff, 14804 argLen: 1, 14805 rematerializeable: true, 14806 asm: mips.AMOVV, 14807 reg: regInfo{ 14808 inputs: []inputInfo{ 14809 {0, 4611686018460942336}, // SP SB 14810 }, 14811 outputs: []outputInfo{ 14812 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14813 }, 14814 }, 14815 }, 14816 { 14817 name: "MOVBload", 14818 auxType: auxSymOff, 14819 argLen: 2, 14820 faultOnNilArg0: true, 14821 asm: mips.AMOVB, 14822 reg: regInfo{ 14823 inputs: []inputInfo{ 14824 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14825 }, 14826 outputs: []outputInfo{ 14827 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14828 }, 14829 }, 14830 }, 14831 { 14832 name: "MOVBUload", 14833 auxType: auxSymOff, 14834 argLen: 2, 14835 faultOnNilArg0: true, 14836 asm: mips.AMOVBU, 14837 reg: regInfo{ 14838 inputs: []inputInfo{ 14839 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14840 }, 14841 outputs: []outputInfo{ 14842 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14843 }, 14844 }, 14845 }, 14846 { 14847 name: "MOVHload", 14848 auxType: auxSymOff, 14849 argLen: 2, 14850 faultOnNilArg0: true, 14851 asm: mips.AMOVH, 14852 reg: regInfo{ 14853 inputs: []inputInfo{ 14854 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14855 }, 14856 outputs: []outputInfo{ 14857 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14858 }, 14859 }, 14860 }, 14861 { 14862 name: "MOVHUload", 14863 auxType: auxSymOff, 14864 argLen: 2, 14865 faultOnNilArg0: true, 14866 asm: mips.AMOVHU, 14867 reg: regInfo{ 14868 inputs: []inputInfo{ 14869 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14870 }, 14871 outputs: []outputInfo{ 14872 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14873 }, 14874 }, 14875 }, 14876 { 14877 name: "MOVWload", 14878 auxType: auxSymOff, 14879 argLen: 2, 14880 faultOnNilArg0: true, 14881 asm: mips.AMOVW, 14882 reg: regInfo{ 14883 inputs: []inputInfo{ 14884 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14885 }, 14886 outputs: []outputInfo{ 14887 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14888 }, 14889 }, 14890 }, 14891 { 14892 name: "MOVWUload", 14893 auxType: auxSymOff, 14894 argLen: 2, 14895 faultOnNilArg0: true, 14896 asm: mips.AMOVWU, 14897 reg: regInfo{ 14898 inputs: []inputInfo{ 14899 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14900 }, 14901 outputs: []outputInfo{ 14902 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14903 }, 14904 }, 14905 }, 14906 { 14907 name: "MOVVload", 14908 auxType: auxSymOff, 14909 argLen: 2, 14910 faultOnNilArg0: true, 14911 asm: mips.AMOVV, 14912 reg: regInfo{ 14913 inputs: []inputInfo{ 14914 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14915 }, 14916 outputs: []outputInfo{ 14917 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14918 }, 14919 }, 14920 }, 14921 { 14922 name: "MOVFload", 14923 auxType: auxSymOff, 14924 argLen: 2, 14925 faultOnNilArg0: true, 14926 asm: mips.AMOVF, 14927 reg: regInfo{ 14928 inputs: []inputInfo{ 14929 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14930 }, 14931 outputs: []outputInfo{ 14932 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14933 }, 14934 }, 14935 }, 14936 { 14937 name: "MOVDload", 14938 auxType: auxSymOff, 14939 argLen: 2, 14940 faultOnNilArg0: true, 14941 asm: mips.AMOVD, 14942 reg: regInfo{ 14943 inputs: []inputInfo{ 14944 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14945 }, 14946 outputs: []outputInfo{ 14947 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14948 }, 14949 }, 14950 }, 14951 { 14952 name: "MOVBstore", 14953 auxType: auxSymOff, 14954 argLen: 3, 14955 faultOnNilArg0: true, 14956 asm: mips.AMOVB, 14957 reg: regInfo{ 14958 inputs: []inputInfo{ 14959 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14960 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14961 }, 14962 }, 14963 }, 14964 { 14965 name: "MOVHstore", 14966 auxType: auxSymOff, 14967 argLen: 3, 14968 faultOnNilArg0: true, 14969 asm: mips.AMOVH, 14970 reg: regInfo{ 14971 inputs: []inputInfo{ 14972 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14973 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14974 }, 14975 }, 14976 }, 14977 { 14978 name: "MOVWstore", 14979 auxType: auxSymOff, 14980 argLen: 3, 14981 faultOnNilArg0: true, 14982 asm: mips.AMOVW, 14983 reg: regInfo{ 14984 inputs: []inputInfo{ 14985 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14986 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14987 }, 14988 }, 14989 }, 14990 { 14991 name: "MOVVstore", 14992 auxType: auxSymOff, 14993 argLen: 3, 14994 faultOnNilArg0: true, 14995 asm: mips.AMOVV, 14996 reg: regInfo{ 14997 inputs: []inputInfo{ 14998 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14999 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15000 }, 15001 }, 15002 }, 15003 { 15004 name: "MOVFstore", 15005 auxType: auxSymOff, 15006 argLen: 3, 15007 faultOnNilArg0: true, 15008 asm: mips.AMOVF, 15009 reg: regInfo{ 15010 inputs: []inputInfo{ 15011 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15012 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15013 }, 15014 }, 15015 }, 15016 { 15017 name: "MOVDstore", 15018 auxType: auxSymOff, 15019 argLen: 3, 15020 faultOnNilArg0: true, 15021 asm: mips.AMOVD, 15022 reg: regInfo{ 15023 inputs: []inputInfo{ 15024 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15025 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15026 }, 15027 }, 15028 }, 15029 { 15030 name: "MOVBstorezero", 15031 auxType: auxSymOff, 15032 argLen: 2, 15033 faultOnNilArg0: true, 15034 asm: mips.AMOVB, 15035 reg: regInfo{ 15036 inputs: []inputInfo{ 15037 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15038 }, 15039 }, 15040 }, 15041 { 15042 name: "MOVHstorezero", 15043 auxType: auxSymOff, 15044 argLen: 2, 15045 faultOnNilArg0: true, 15046 asm: mips.AMOVH, 15047 reg: regInfo{ 15048 inputs: []inputInfo{ 15049 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15050 }, 15051 }, 15052 }, 15053 { 15054 name: "MOVWstorezero", 15055 auxType: auxSymOff, 15056 argLen: 2, 15057 faultOnNilArg0: true, 15058 asm: mips.AMOVW, 15059 reg: regInfo{ 15060 inputs: []inputInfo{ 15061 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15062 }, 15063 }, 15064 }, 15065 { 15066 name: "MOVVstorezero", 15067 auxType: auxSymOff, 15068 argLen: 2, 15069 faultOnNilArg0: true, 15070 asm: mips.AMOVV, 15071 reg: regInfo{ 15072 inputs: []inputInfo{ 15073 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15074 }, 15075 }, 15076 }, 15077 { 15078 name: "MOVBreg", 15079 argLen: 1, 15080 asm: mips.AMOVB, 15081 reg: regInfo{ 15082 inputs: []inputInfo{ 15083 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15084 }, 15085 outputs: []outputInfo{ 15086 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15087 }, 15088 }, 15089 }, 15090 { 15091 name: "MOVBUreg", 15092 argLen: 1, 15093 asm: mips.AMOVBU, 15094 reg: regInfo{ 15095 inputs: []inputInfo{ 15096 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15097 }, 15098 outputs: []outputInfo{ 15099 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15100 }, 15101 }, 15102 }, 15103 { 15104 name: "MOVHreg", 15105 argLen: 1, 15106 asm: mips.AMOVH, 15107 reg: regInfo{ 15108 inputs: []inputInfo{ 15109 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15110 }, 15111 outputs: []outputInfo{ 15112 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15113 }, 15114 }, 15115 }, 15116 { 15117 name: "MOVHUreg", 15118 argLen: 1, 15119 asm: mips.AMOVHU, 15120 reg: regInfo{ 15121 inputs: []inputInfo{ 15122 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15123 }, 15124 outputs: []outputInfo{ 15125 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15126 }, 15127 }, 15128 }, 15129 { 15130 name: "MOVWreg", 15131 argLen: 1, 15132 asm: mips.AMOVW, 15133 reg: regInfo{ 15134 inputs: []inputInfo{ 15135 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15136 }, 15137 outputs: []outputInfo{ 15138 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15139 }, 15140 }, 15141 }, 15142 { 15143 name: "MOVWUreg", 15144 argLen: 1, 15145 asm: mips.AMOVWU, 15146 reg: regInfo{ 15147 inputs: []inputInfo{ 15148 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15149 }, 15150 outputs: []outputInfo{ 15151 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15152 }, 15153 }, 15154 }, 15155 { 15156 name: "MOVVreg", 15157 argLen: 1, 15158 asm: mips.AMOVV, 15159 reg: regInfo{ 15160 inputs: []inputInfo{ 15161 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15162 }, 15163 outputs: []outputInfo{ 15164 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15165 }, 15166 }, 15167 }, 15168 { 15169 name: "MOVVnop", 15170 argLen: 1, 15171 resultInArg0: true, 15172 reg: regInfo{ 15173 inputs: []inputInfo{ 15174 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15175 }, 15176 outputs: []outputInfo{ 15177 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15178 }, 15179 }, 15180 }, 15181 { 15182 name: "MOVWF", 15183 argLen: 1, 15184 asm: mips.AMOVWF, 15185 reg: regInfo{ 15186 inputs: []inputInfo{ 15187 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15188 }, 15189 outputs: []outputInfo{ 15190 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15191 }, 15192 }, 15193 }, 15194 { 15195 name: "MOVWD", 15196 argLen: 1, 15197 asm: mips.AMOVWD, 15198 reg: regInfo{ 15199 inputs: []inputInfo{ 15200 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15201 }, 15202 outputs: []outputInfo{ 15203 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15204 }, 15205 }, 15206 }, 15207 { 15208 name: "MOVVF", 15209 argLen: 1, 15210 asm: mips.AMOVVF, 15211 reg: regInfo{ 15212 inputs: []inputInfo{ 15213 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15214 }, 15215 outputs: []outputInfo{ 15216 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15217 }, 15218 }, 15219 }, 15220 { 15221 name: "MOVVD", 15222 argLen: 1, 15223 asm: mips.AMOVVD, 15224 reg: regInfo{ 15225 inputs: []inputInfo{ 15226 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15227 }, 15228 outputs: []outputInfo{ 15229 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15230 }, 15231 }, 15232 }, 15233 { 15234 name: "TRUNCFW", 15235 argLen: 1, 15236 asm: mips.ATRUNCFW, 15237 reg: regInfo{ 15238 inputs: []inputInfo{ 15239 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15240 }, 15241 outputs: []outputInfo{ 15242 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15243 }, 15244 }, 15245 }, 15246 { 15247 name: "TRUNCDW", 15248 argLen: 1, 15249 asm: mips.ATRUNCDW, 15250 reg: regInfo{ 15251 inputs: []inputInfo{ 15252 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15253 }, 15254 outputs: []outputInfo{ 15255 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15256 }, 15257 }, 15258 }, 15259 { 15260 name: "TRUNCFV", 15261 argLen: 1, 15262 asm: mips.ATRUNCFV, 15263 reg: regInfo{ 15264 inputs: []inputInfo{ 15265 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15266 }, 15267 outputs: []outputInfo{ 15268 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15269 }, 15270 }, 15271 }, 15272 { 15273 name: "TRUNCDV", 15274 argLen: 1, 15275 asm: mips.ATRUNCDV, 15276 reg: regInfo{ 15277 inputs: []inputInfo{ 15278 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15279 }, 15280 outputs: []outputInfo{ 15281 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15282 }, 15283 }, 15284 }, 15285 { 15286 name: "MOVFD", 15287 argLen: 1, 15288 asm: mips.AMOVFD, 15289 reg: regInfo{ 15290 inputs: []inputInfo{ 15291 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15292 }, 15293 outputs: []outputInfo{ 15294 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15295 }, 15296 }, 15297 }, 15298 { 15299 name: "MOVDF", 15300 argLen: 1, 15301 asm: mips.AMOVDF, 15302 reg: regInfo{ 15303 inputs: []inputInfo{ 15304 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15305 }, 15306 outputs: []outputInfo{ 15307 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15308 }, 15309 }, 15310 }, 15311 { 15312 name: "CALLstatic", 15313 auxType: auxSymOff, 15314 argLen: 1, 15315 clobberFlags: true, 15316 call: true, 15317 reg: regInfo{ 15318 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15319 }, 15320 }, 15321 { 15322 name: "CALLclosure", 15323 auxType: auxInt64, 15324 argLen: 3, 15325 clobberFlags: true, 15326 call: true, 15327 reg: regInfo{ 15328 inputs: []inputInfo{ 15329 {1, 4194304}, // R22 15330 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 15331 }, 15332 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15333 }, 15334 }, 15335 { 15336 name: "CALLdefer", 15337 auxType: auxInt64, 15338 argLen: 1, 15339 clobberFlags: true, 15340 call: true, 15341 reg: regInfo{ 15342 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15343 }, 15344 }, 15345 { 15346 name: "CALLgo", 15347 auxType: auxInt64, 15348 argLen: 1, 15349 clobberFlags: true, 15350 call: true, 15351 reg: regInfo{ 15352 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15353 }, 15354 }, 15355 { 15356 name: "CALLinter", 15357 auxType: auxInt64, 15358 argLen: 2, 15359 clobberFlags: true, 15360 call: true, 15361 reg: regInfo{ 15362 inputs: []inputInfo{ 15363 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15364 }, 15365 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15366 }, 15367 }, 15368 { 15369 name: "DUFFZERO", 15370 auxType: auxInt64, 15371 argLen: 2, 15372 faultOnNilArg0: true, 15373 reg: regInfo{ 15374 inputs: []inputInfo{ 15375 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15376 }, 15377 clobbers: 134217730, // R1 R31 15378 }, 15379 }, 15380 { 15381 name: "LoweredZero", 15382 auxType: auxInt64, 15383 argLen: 3, 15384 clobberFlags: true, 15385 faultOnNilArg0: true, 15386 reg: regInfo{ 15387 inputs: []inputInfo{ 15388 {0, 2}, // R1 15389 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15390 }, 15391 clobbers: 2, // R1 15392 }, 15393 }, 15394 { 15395 name: "LoweredMove", 15396 auxType: auxInt64, 15397 argLen: 4, 15398 clobberFlags: true, 15399 faultOnNilArg0: true, 15400 faultOnNilArg1: true, 15401 reg: regInfo{ 15402 inputs: []inputInfo{ 15403 {0, 4}, // R2 15404 {1, 2}, // R1 15405 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15406 }, 15407 clobbers: 6, // R1 R2 15408 }, 15409 }, 15410 { 15411 name: "LoweredNilCheck", 15412 argLen: 2, 15413 nilCheck: true, 15414 faultOnNilArg0: true, 15415 reg: regInfo{ 15416 inputs: []inputInfo{ 15417 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15418 }, 15419 }, 15420 }, 15421 { 15422 name: "FPFlagTrue", 15423 argLen: 1, 15424 reg: regInfo{ 15425 outputs: []outputInfo{ 15426 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15427 }, 15428 }, 15429 }, 15430 { 15431 name: "FPFlagFalse", 15432 argLen: 1, 15433 reg: regInfo{ 15434 outputs: []outputInfo{ 15435 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15436 }, 15437 }, 15438 }, 15439 { 15440 name: "LoweredGetClosurePtr", 15441 argLen: 0, 15442 reg: regInfo{ 15443 outputs: []outputInfo{ 15444 {0, 4194304}, // R22 15445 }, 15446 }, 15447 }, 15448 { 15449 name: "MOVVconvert", 15450 argLen: 2, 15451 asm: mips.AMOVV, 15452 reg: regInfo{ 15453 inputs: []inputInfo{ 15454 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15455 }, 15456 outputs: []outputInfo{ 15457 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15458 }, 15459 }, 15460 }, 15461 15462 { 15463 name: "ADD", 15464 argLen: 2, 15465 commutative: true, 15466 asm: ppc64.AADD, 15467 reg: regInfo{ 15468 inputs: []inputInfo{ 15469 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15470 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15471 }, 15472 outputs: []outputInfo{ 15473 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15474 }, 15475 }, 15476 }, 15477 { 15478 name: "ADDconst", 15479 auxType: auxSymOff, 15480 argLen: 1, 15481 asm: ppc64.AADD, 15482 reg: regInfo{ 15483 inputs: []inputInfo{ 15484 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15485 }, 15486 outputs: []outputInfo{ 15487 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15488 }, 15489 }, 15490 }, 15491 { 15492 name: "FADD", 15493 argLen: 2, 15494 commutative: true, 15495 asm: ppc64.AFADD, 15496 reg: regInfo{ 15497 inputs: []inputInfo{ 15498 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15499 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15500 }, 15501 outputs: []outputInfo{ 15502 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15503 }, 15504 }, 15505 }, 15506 { 15507 name: "FADDS", 15508 argLen: 2, 15509 commutative: true, 15510 asm: ppc64.AFADDS, 15511 reg: regInfo{ 15512 inputs: []inputInfo{ 15513 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15514 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15515 }, 15516 outputs: []outputInfo{ 15517 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15518 }, 15519 }, 15520 }, 15521 { 15522 name: "SUB", 15523 argLen: 2, 15524 asm: ppc64.ASUB, 15525 reg: regInfo{ 15526 inputs: []inputInfo{ 15527 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15528 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15529 }, 15530 outputs: []outputInfo{ 15531 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15532 }, 15533 }, 15534 }, 15535 { 15536 name: "FSUB", 15537 argLen: 2, 15538 asm: ppc64.AFSUB, 15539 reg: regInfo{ 15540 inputs: []inputInfo{ 15541 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15542 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15543 }, 15544 outputs: []outputInfo{ 15545 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15546 }, 15547 }, 15548 }, 15549 { 15550 name: "FSUBS", 15551 argLen: 2, 15552 asm: ppc64.AFSUBS, 15553 reg: regInfo{ 15554 inputs: []inputInfo{ 15555 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15556 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15557 }, 15558 outputs: []outputInfo{ 15559 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15560 }, 15561 }, 15562 }, 15563 { 15564 name: "MULLD", 15565 argLen: 2, 15566 commutative: true, 15567 asm: ppc64.AMULLD, 15568 reg: regInfo{ 15569 inputs: []inputInfo{ 15570 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15571 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15572 }, 15573 outputs: []outputInfo{ 15574 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15575 }, 15576 }, 15577 }, 15578 { 15579 name: "MULLW", 15580 argLen: 2, 15581 commutative: true, 15582 asm: ppc64.AMULLW, 15583 reg: regInfo{ 15584 inputs: []inputInfo{ 15585 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15586 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15587 }, 15588 outputs: []outputInfo{ 15589 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15590 }, 15591 }, 15592 }, 15593 { 15594 name: "MULHD", 15595 argLen: 2, 15596 commutative: true, 15597 asm: ppc64.AMULHD, 15598 reg: regInfo{ 15599 inputs: []inputInfo{ 15600 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15601 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15602 }, 15603 outputs: []outputInfo{ 15604 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15605 }, 15606 }, 15607 }, 15608 { 15609 name: "MULHW", 15610 argLen: 2, 15611 commutative: true, 15612 asm: ppc64.AMULHW, 15613 reg: regInfo{ 15614 inputs: []inputInfo{ 15615 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15616 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15617 }, 15618 outputs: []outputInfo{ 15619 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15620 }, 15621 }, 15622 }, 15623 { 15624 name: "MULHDU", 15625 argLen: 2, 15626 commutative: true, 15627 asm: ppc64.AMULHDU, 15628 reg: regInfo{ 15629 inputs: []inputInfo{ 15630 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15631 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15632 }, 15633 outputs: []outputInfo{ 15634 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15635 }, 15636 }, 15637 }, 15638 { 15639 name: "MULHWU", 15640 argLen: 2, 15641 commutative: true, 15642 asm: ppc64.AMULHWU, 15643 reg: regInfo{ 15644 inputs: []inputInfo{ 15645 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15646 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15647 }, 15648 outputs: []outputInfo{ 15649 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15650 }, 15651 }, 15652 }, 15653 { 15654 name: "FMUL", 15655 argLen: 2, 15656 commutative: true, 15657 asm: ppc64.AFMUL, 15658 reg: regInfo{ 15659 inputs: []inputInfo{ 15660 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15661 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15662 }, 15663 outputs: []outputInfo{ 15664 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15665 }, 15666 }, 15667 }, 15668 { 15669 name: "FMULS", 15670 argLen: 2, 15671 commutative: true, 15672 asm: ppc64.AFMULS, 15673 reg: regInfo{ 15674 inputs: []inputInfo{ 15675 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15676 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15677 }, 15678 outputs: []outputInfo{ 15679 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15680 }, 15681 }, 15682 }, 15683 { 15684 name: "SRAD", 15685 argLen: 2, 15686 asm: ppc64.ASRAD, 15687 reg: regInfo{ 15688 inputs: []inputInfo{ 15689 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15690 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15691 }, 15692 outputs: []outputInfo{ 15693 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15694 }, 15695 }, 15696 }, 15697 { 15698 name: "SRAW", 15699 argLen: 2, 15700 asm: ppc64.ASRAW, 15701 reg: regInfo{ 15702 inputs: []inputInfo{ 15703 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15704 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15705 }, 15706 outputs: []outputInfo{ 15707 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15708 }, 15709 }, 15710 }, 15711 { 15712 name: "SRD", 15713 argLen: 2, 15714 asm: ppc64.ASRD, 15715 reg: regInfo{ 15716 inputs: []inputInfo{ 15717 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15718 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15719 }, 15720 outputs: []outputInfo{ 15721 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15722 }, 15723 }, 15724 }, 15725 { 15726 name: "SRW", 15727 argLen: 2, 15728 asm: ppc64.ASRW, 15729 reg: regInfo{ 15730 inputs: []inputInfo{ 15731 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15732 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15733 }, 15734 outputs: []outputInfo{ 15735 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15736 }, 15737 }, 15738 }, 15739 { 15740 name: "SLD", 15741 argLen: 2, 15742 asm: ppc64.ASLD, 15743 reg: regInfo{ 15744 inputs: []inputInfo{ 15745 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15746 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15747 }, 15748 outputs: []outputInfo{ 15749 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15750 }, 15751 }, 15752 }, 15753 { 15754 name: "SLW", 15755 argLen: 2, 15756 asm: ppc64.ASLW, 15757 reg: regInfo{ 15758 inputs: []inputInfo{ 15759 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15760 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15761 }, 15762 outputs: []outputInfo{ 15763 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15764 }, 15765 }, 15766 }, 15767 { 15768 name: "ADDconstForCarry", 15769 auxType: auxInt16, 15770 argLen: 1, 15771 asm: ppc64.AADDC, 15772 reg: regInfo{ 15773 inputs: []inputInfo{ 15774 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15775 }, 15776 clobbers: 2147483648, // R31 15777 }, 15778 }, 15779 { 15780 name: "MaskIfNotCarry", 15781 argLen: 1, 15782 asm: ppc64.AADDME, 15783 reg: regInfo{ 15784 outputs: []outputInfo{ 15785 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15786 }, 15787 }, 15788 }, 15789 { 15790 name: "SRADconst", 15791 auxType: auxInt64, 15792 argLen: 1, 15793 asm: ppc64.ASRAD, 15794 reg: regInfo{ 15795 inputs: []inputInfo{ 15796 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15797 }, 15798 outputs: []outputInfo{ 15799 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15800 }, 15801 }, 15802 }, 15803 { 15804 name: "SRAWconst", 15805 auxType: auxInt64, 15806 argLen: 1, 15807 asm: ppc64.ASRAW, 15808 reg: regInfo{ 15809 inputs: []inputInfo{ 15810 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15811 }, 15812 outputs: []outputInfo{ 15813 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15814 }, 15815 }, 15816 }, 15817 { 15818 name: "SRDconst", 15819 auxType: auxInt64, 15820 argLen: 1, 15821 asm: ppc64.ASRD, 15822 reg: regInfo{ 15823 inputs: []inputInfo{ 15824 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15825 }, 15826 outputs: []outputInfo{ 15827 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15828 }, 15829 }, 15830 }, 15831 { 15832 name: "SRWconst", 15833 auxType: auxInt64, 15834 argLen: 1, 15835 asm: ppc64.ASRW, 15836 reg: regInfo{ 15837 inputs: []inputInfo{ 15838 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15839 }, 15840 outputs: []outputInfo{ 15841 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15842 }, 15843 }, 15844 }, 15845 { 15846 name: "SLDconst", 15847 auxType: auxInt64, 15848 argLen: 1, 15849 asm: ppc64.ASLD, 15850 reg: regInfo{ 15851 inputs: []inputInfo{ 15852 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15853 }, 15854 outputs: []outputInfo{ 15855 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15856 }, 15857 }, 15858 }, 15859 { 15860 name: "SLWconst", 15861 auxType: auxInt64, 15862 argLen: 1, 15863 asm: ppc64.ASLW, 15864 reg: regInfo{ 15865 inputs: []inputInfo{ 15866 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15867 }, 15868 outputs: []outputInfo{ 15869 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15870 }, 15871 }, 15872 }, 15873 { 15874 name: "FDIV", 15875 argLen: 2, 15876 asm: ppc64.AFDIV, 15877 reg: regInfo{ 15878 inputs: []inputInfo{ 15879 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15880 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15881 }, 15882 outputs: []outputInfo{ 15883 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15884 }, 15885 }, 15886 }, 15887 { 15888 name: "FDIVS", 15889 argLen: 2, 15890 asm: ppc64.AFDIVS, 15891 reg: regInfo{ 15892 inputs: []inputInfo{ 15893 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15894 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15895 }, 15896 outputs: []outputInfo{ 15897 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15898 }, 15899 }, 15900 }, 15901 { 15902 name: "DIVD", 15903 argLen: 2, 15904 asm: ppc64.ADIVD, 15905 reg: regInfo{ 15906 inputs: []inputInfo{ 15907 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15908 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15909 }, 15910 outputs: []outputInfo{ 15911 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15912 }, 15913 }, 15914 }, 15915 { 15916 name: "DIVW", 15917 argLen: 2, 15918 asm: ppc64.ADIVW, 15919 reg: regInfo{ 15920 inputs: []inputInfo{ 15921 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15922 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15923 }, 15924 outputs: []outputInfo{ 15925 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15926 }, 15927 }, 15928 }, 15929 { 15930 name: "DIVDU", 15931 argLen: 2, 15932 asm: ppc64.ADIVDU, 15933 reg: regInfo{ 15934 inputs: []inputInfo{ 15935 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15936 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15937 }, 15938 outputs: []outputInfo{ 15939 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15940 }, 15941 }, 15942 }, 15943 { 15944 name: "DIVWU", 15945 argLen: 2, 15946 asm: ppc64.ADIVWU, 15947 reg: regInfo{ 15948 inputs: []inputInfo{ 15949 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15950 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15951 }, 15952 outputs: []outputInfo{ 15953 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15954 }, 15955 }, 15956 }, 15957 { 15958 name: "FCTIDZ", 15959 argLen: 1, 15960 asm: ppc64.AFCTIDZ, 15961 reg: regInfo{ 15962 inputs: []inputInfo{ 15963 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15964 }, 15965 outputs: []outputInfo{ 15966 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15967 }, 15968 }, 15969 }, 15970 { 15971 name: "FCTIWZ", 15972 argLen: 1, 15973 asm: ppc64.AFCTIWZ, 15974 reg: regInfo{ 15975 inputs: []inputInfo{ 15976 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15977 }, 15978 outputs: []outputInfo{ 15979 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15980 }, 15981 }, 15982 }, 15983 { 15984 name: "FCFID", 15985 argLen: 1, 15986 asm: ppc64.AFCFID, 15987 reg: regInfo{ 15988 inputs: []inputInfo{ 15989 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15990 }, 15991 outputs: []outputInfo{ 15992 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15993 }, 15994 }, 15995 }, 15996 { 15997 name: "FRSP", 15998 argLen: 1, 15999 asm: ppc64.AFRSP, 16000 reg: regInfo{ 16001 inputs: []inputInfo{ 16002 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16003 }, 16004 outputs: []outputInfo{ 16005 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16006 }, 16007 }, 16008 }, 16009 { 16010 name: "Xf2i64", 16011 argLen: 1, 16012 usesScratch: true, 16013 reg: regInfo{ 16014 inputs: []inputInfo{ 16015 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16016 }, 16017 outputs: []outputInfo{ 16018 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16019 }, 16020 }, 16021 }, 16022 { 16023 name: "Xi2f64", 16024 argLen: 1, 16025 usesScratch: true, 16026 reg: regInfo{ 16027 inputs: []inputInfo{ 16028 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16029 }, 16030 outputs: []outputInfo{ 16031 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16032 }, 16033 }, 16034 }, 16035 { 16036 name: "AND", 16037 argLen: 2, 16038 commutative: true, 16039 asm: ppc64.AAND, 16040 reg: regInfo{ 16041 inputs: []inputInfo{ 16042 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16043 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16044 }, 16045 outputs: []outputInfo{ 16046 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16047 }, 16048 }, 16049 }, 16050 { 16051 name: "ANDN", 16052 argLen: 2, 16053 asm: ppc64.AANDN, 16054 reg: regInfo{ 16055 inputs: []inputInfo{ 16056 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16057 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16058 }, 16059 outputs: []outputInfo{ 16060 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16061 }, 16062 }, 16063 }, 16064 { 16065 name: "OR", 16066 argLen: 2, 16067 commutative: true, 16068 asm: ppc64.AOR, 16069 reg: regInfo{ 16070 inputs: []inputInfo{ 16071 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16072 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16073 }, 16074 outputs: []outputInfo{ 16075 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16076 }, 16077 }, 16078 }, 16079 { 16080 name: "ORN", 16081 argLen: 2, 16082 asm: ppc64.AORN, 16083 reg: regInfo{ 16084 inputs: []inputInfo{ 16085 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16086 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16087 }, 16088 outputs: []outputInfo{ 16089 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16090 }, 16091 }, 16092 }, 16093 { 16094 name: "XOR", 16095 argLen: 2, 16096 commutative: true, 16097 asm: ppc64.AXOR, 16098 reg: regInfo{ 16099 inputs: []inputInfo{ 16100 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16101 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16102 }, 16103 outputs: []outputInfo{ 16104 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16105 }, 16106 }, 16107 }, 16108 { 16109 name: "EQV", 16110 argLen: 2, 16111 commutative: true, 16112 asm: ppc64.AEQV, 16113 reg: regInfo{ 16114 inputs: []inputInfo{ 16115 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16116 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16117 }, 16118 outputs: []outputInfo{ 16119 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16120 }, 16121 }, 16122 }, 16123 { 16124 name: "NEG", 16125 argLen: 1, 16126 asm: ppc64.ANEG, 16127 reg: regInfo{ 16128 inputs: []inputInfo{ 16129 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16130 }, 16131 outputs: []outputInfo{ 16132 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16133 }, 16134 }, 16135 }, 16136 { 16137 name: "FNEG", 16138 argLen: 1, 16139 asm: ppc64.AFNEG, 16140 reg: regInfo{ 16141 inputs: []inputInfo{ 16142 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16143 }, 16144 outputs: []outputInfo{ 16145 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16146 }, 16147 }, 16148 }, 16149 { 16150 name: "FSQRT", 16151 argLen: 1, 16152 asm: ppc64.AFSQRT, 16153 reg: regInfo{ 16154 inputs: []inputInfo{ 16155 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16156 }, 16157 outputs: []outputInfo{ 16158 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16159 }, 16160 }, 16161 }, 16162 { 16163 name: "FSQRTS", 16164 argLen: 1, 16165 asm: ppc64.AFSQRTS, 16166 reg: regInfo{ 16167 inputs: []inputInfo{ 16168 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16169 }, 16170 outputs: []outputInfo{ 16171 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16172 }, 16173 }, 16174 }, 16175 { 16176 name: "ORconst", 16177 auxType: auxInt64, 16178 argLen: 1, 16179 asm: ppc64.AOR, 16180 reg: regInfo{ 16181 inputs: []inputInfo{ 16182 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16183 }, 16184 outputs: []outputInfo{ 16185 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16186 }, 16187 }, 16188 }, 16189 { 16190 name: "XORconst", 16191 auxType: auxInt64, 16192 argLen: 1, 16193 asm: ppc64.AXOR, 16194 reg: regInfo{ 16195 inputs: []inputInfo{ 16196 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16197 }, 16198 outputs: []outputInfo{ 16199 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16200 }, 16201 }, 16202 }, 16203 { 16204 name: "ANDconst", 16205 auxType: auxInt64, 16206 argLen: 1, 16207 clobberFlags: true, 16208 asm: ppc64.AANDCC, 16209 reg: regInfo{ 16210 inputs: []inputInfo{ 16211 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16212 }, 16213 outputs: []outputInfo{ 16214 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16215 }, 16216 }, 16217 }, 16218 { 16219 name: "ANDCCconst", 16220 auxType: auxInt64, 16221 argLen: 1, 16222 asm: ppc64.AANDCC, 16223 reg: regInfo{ 16224 inputs: []inputInfo{ 16225 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16226 }, 16227 }, 16228 }, 16229 { 16230 name: "MOVBreg", 16231 argLen: 1, 16232 asm: ppc64.AMOVB, 16233 reg: regInfo{ 16234 inputs: []inputInfo{ 16235 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16236 }, 16237 outputs: []outputInfo{ 16238 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16239 }, 16240 }, 16241 }, 16242 { 16243 name: "MOVBZreg", 16244 argLen: 1, 16245 asm: ppc64.AMOVBZ, 16246 reg: regInfo{ 16247 inputs: []inputInfo{ 16248 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16249 }, 16250 outputs: []outputInfo{ 16251 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16252 }, 16253 }, 16254 }, 16255 { 16256 name: "MOVHreg", 16257 argLen: 1, 16258 asm: ppc64.AMOVH, 16259 reg: regInfo{ 16260 inputs: []inputInfo{ 16261 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16262 }, 16263 outputs: []outputInfo{ 16264 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16265 }, 16266 }, 16267 }, 16268 { 16269 name: "MOVHZreg", 16270 argLen: 1, 16271 asm: ppc64.AMOVHZ, 16272 reg: regInfo{ 16273 inputs: []inputInfo{ 16274 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16275 }, 16276 outputs: []outputInfo{ 16277 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16278 }, 16279 }, 16280 }, 16281 { 16282 name: "MOVWreg", 16283 argLen: 1, 16284 asm: ppc64.AMOVW, 16285 reg: regInfo{ 16286 inputs: []inputInfo{ 16287 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16288 }, 16289 outputs: []outputInfo{ 16290 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16291 }, 16292 }, 16293 }, 16294 { 16295 name: "MOVWZreg", 16296 argLen: 1, 16297 asm: ppc64.AMOVWZ, 16298 reg: regInfo{ 16299 inputs: []inputInfo{ 16300 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16301 }, 16302 outputs: []outputInfo{ 16303 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16304 }, 16305 }, 16306 }, 16307 { 16308 name: "MOVBZload", 16309 auxType: auxSymOff, 16310 argLen: 2, 16311 faultOnNilArg0: true, 16312 asm: ppc64.AMOVBZ, 16313 reg: regInfo{ 16314 inputs: []inputInfo{ 16315 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16316 }, 16317 outputs: []outputInfo{ 16318 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16319 }, 16320 }, 16321 }, 16322 { 16323 name: "MOVHload", 16324 auxType: auxSymOff, 16325 argLen: 2, 16326 faultOnNilArg0: true, 16327 asm: ppc64.AMOVH, 16328 reg: regInfo{ 16329 inputs: []inputInfo{ 16330 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16331 }, 16332 outputs: []outputInfo{ 16333 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16334 }, 16335 }, 16336 }, 16337 { 16338 name: "MOVHZload", 16339 auxType: auxSymOff, 16340 argLen: 2, 16341 faultOnNilArg0: true, 16342 asm: ppc64.AMOVHZ, 16343 reg: regInfo{ 16344 inputs: []inputInfo{ 16345 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16346 }, 16347 outputs: []outputInfo{ 16348 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16349 }, 16350 }, 16351 }, 16352 { 16353 name: "MOVWload", 16354 auxType: auxSymOff, 16355 argLen: 2, 16356 faultOnNilArg0: true, 16357 asm: ppc64.AMOVW, 16358 reg: regInfo{ 16359 inputs: []inputInfo{ 16360 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16361 }, 16362 outputs: []outputInfo{ 16363 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16364 }, 16365 }, 16366 }, 16367 { 16368 name: "MOVWZload", 16369 auxType: auxSymOff, 16370 argLen: 2, 16371 faultOnNilArg0: true, 16372 asm: ppc64.AMOVWZ, 16373 reg: regInfo{ 16374 inputs: []inputInfo{ 16375 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16376 }, 16377 outputs: []outputInfo{ 16378 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16379 }, 16380 }, 16381 }, 16382 { 16383 name: "MOVDload", 16384 auxType: auxSymOff, 16385 argLen: 2, 16386 faultOnNilArg0: true, 16387 asm: ppc64.AMOVD, 16388 reg: regInfo{ 16389 inputs: []inputInfo{ 16390 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16391 }, 16392 outputs: []outputInfo{ 16393 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16394 }, 16395 }, 16396 }, 16397 { 16398 name: "FMOVDload", 16399 auxType: auxSymOff, 16400 argLen: 2, 16401 faultOnNilArg0: true, 16402 asm: ppc64.AFMOVD, 16403 reg: regInfo{ 16404 inputs: []inputInfo{ 16405 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16406 }, 16407 outputs: []outputInfo{ 16408 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16409 }, 16410 }, 16411 }, 16412 { 16413 name: "FMOVSload", 16414 auxType: auxSymOff, 16415 argLen: 2, 16416 faultOnNilArg0: true, 16417 asm: ppc64.AFMOVS, 16418 reg: regInfo{ 16419 inputs: []inputInfo{ 16420 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16421 }, 16422 outputs: []outputInfo{ 16423 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16424 }, 16425 }, 16426 }, 16427 { 16428 name: "MOVBstore", 16429 auxType: auxSymOff, 16430 argLen: 3, 16431 faultOnNilArg0: true, 16432 asm: ppc64.AMOVB, 16433 reg: regInfo{ 16434 inputs: []inputInfo{ 16435 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16436 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16437 }, 16438 }, 16439 }, 16440 { 16441 name: "MOVHstore", 16442 auxType: auxSymOff, 16443 argLen: 3, 16444 faultOnNilArg0: true, 16445 asm: ppc64.AMOVH, 16446 reg: regInfo{ 16447 inputs: []inputInfo{ 16448 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16449 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16450 }, 16451 }, 16452 }, 16453 { 16454 name: "MOVWstore", 16455 auxType: auxSymOff, 16456 argLen: 3, 16457 faultOnNilArg0: true, 16458 asm: ppc64.AMOVW, 16459 reg: regInfo{ 16460 inputs: []inputInfo{ 16461 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16462 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16463 }, 16464 }, 16465 }, 16466 { 16467 name: "MOVDstore", 16468 auxType: auxSymOff, 16469 argLen: 3, 16470 faultOnNilArg0: true, 16471 asm: ppc64.AMOVD, 16472 reg: regInfo{ 16473 inputs: []inputInfo{ 16474 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16475 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16476 }, 16477 }, 16478 }, 16479 { 16480 name: "FMOVDstore", 16481 auxType: auxSymOff, 16482 argLen: 3, 16483 faultOnNilArg0: true, 16484 asm: ppc64.AFMOVD, 16485 reg: regInfo{ 16486 inputs: []inputInfo{ 16487 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16488 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16489 }, 16490 }, 16491 }, 16492 { 16493 name: "FMOVSstore", 16494 auxType: auxSymOff, 16495 argLen: 3, 16496 faultOnNilArg0: true, 16497 asm: ppc64.AFMOVS, 16498 reg: regInfo{ 16499 inputs: []inputInfo{ 16500 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16501 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16502 }, 16503 }, 16504 }, 16505 { 16506 name: "MOVBstorezero", 16507 auxType: auxSymOff, 16508 argLen: 2, 16509 faultOnNilArg0: true, 16510 asm: ppc64.AMOVB, 16511 reg: regInfo{ 16512 inputs: []inputInfo{ 16513 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16514 }, 16515 }, 16516 }, 16517 { 16518 name: "MOVHstorezero", 16519 auxType: auxSymOff, 16520 argLen: 2, 16521 faultOnNilArg0: true, 16522 asm: ppc64.AMOVH, 16523 reg: regInfo{ 16524 inputs: []inputInfo{ 16525 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16526 }, 16527 }, 16528 }, 16529 { 16530 name: "MOVWstorezero", 16531 auxType: auxSymOff, 16532 argLen: 2, 16533 faultOnNilArg0: true, 16534 asm: ppc64.AMOVW, 16535 reg: regInfo{ 16536 inputs: []inputInfo{ 16537 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16538 }, 16539 }, 16540 }, 16541 { 16542 name: "MOVDstorezero", 16543 auxType: auxSymOff, 16544 argLen: 2, 16545 faultOnNilArg0: true, 16546 asm: ppc64.AMOVD, 16547 reg: regInfo{ 16548 inputs: []inputInfo{ 16549 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16550 }, 16551 }, 16552 }, 16553 { 16554 name: "MOVDaddr", 16555 auxType: auxSymOff, 16556 argLen: 1, 16557 rematerializeable: true, 16558 asm: ppc64.AMOVD, 16559 reg: regInfo{ 16560 inputs: []inputInfo{ 16561 {0, 6}, // SP SB 16562 }, 16563 outputs: []outputInfo{ 16564 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16565 }, 16566 }, 16567 }, 16568 { 16569 name: "MOVDconst", 16570 auxType: auxInt64, 16571 argLen: 0, 16572 rematerializeable: true, 16573 asm: ppc64.AMOVD, 16574 reg: regInfo{ 16575 outputs: []outputInfo{ 16576 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16577 }, 16578 }, 16579 }, 16580 { 16581 name: "FMOVDconst", 16582 auxType: auxFloat64, 16583 argLen: 0, 16584 rematerializeable: true, 16585 asm: ppc64.AFMOVD, 16586 reg: regInfo{ 16587 outputs: []outputInfo{ 16588 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16589 }, 16590 }, 16591 }, 16592 { 16593 name: "FMOVSconst", 16594 auxType: auxFloat32, 16595 argLen: 0, 16596 rematerializeable: true, 16597 asm: ppc64.AFMOVS, 16598 reg: regInfo{ 16599 outputs: []outputInfo{ 16600 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16601 }, 16602 }, 16603 }, 16604 { 16605 name: "FCMPU", 16606 argLen: 2, 16607 asm: ppc64.AFCMPU, 16608 reg: regInfo{ 16609 inputs: []inputInfo{ 16610 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16611 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16612 }, 16613 }, 16614 }, 16615 { 16616 name: "CMP", 16617 argLen: 2, 16618 asm: ppc64.ACMP, 16619 reg: regInfo{ 16620 inputs: []inputInfo{ 16621 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16622 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16623 }, 16624 }, 16625 }, 16626 { 16627 name: "CMPU", 16628 argLen: 2, 16629 asm: ppc64.ACMPU, 16630 reg: regInfo{ 16631 inputs: []inputInfo{ 16632 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16633 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16634 }, 16635 }, 16636 }, 16637 { 16638 name: "CMPW", 16639 argLen: 2, 16640 asm: ppc64.ACMPW, 16641 reg: regInfo{ 16642 inputs: []inputInfo{ 16643 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16644 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16645 }, 16646 }, 16647 }, 16648 { 16649 name: "CMPWU", 16650 argLen: 2, 16651 asm: ppc64.ACMPWU, 16652 reg: regInfo{ 16653 inputs: []inputInfo{ 16654 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16655 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16656 }, 16657 }, 16658 }, 16659 { 16660 name: "CMPconst", 16661 auxType: auxInt64, 16662 argLen: 1, 16663 asm: ppc64.ACMP, 16664 reg: regInfo{ 16665 inputs: []inputInfo{ 16666 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16667 }, 16668 }, 16669 }, 16670 { 16671 name: "CMPUconst", 16672 auxType: auxInt64, 16673 argLen: 1, 16674 asm: ppc64.ACMPU, 16675 reg: regInfo{ 16676 inputs: []inputInfo{ 16677 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16678 }, 16679 }, 16680 }, 16681 { 16682 name: "CMPWconst", 16683 auxType: auxInt32, 16684 argLen: 1, 16685 asm: ppc64.ACMPW, 16686 reg: regInfo{ 16687 inputs: []inputInfo{ 16688 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16689 }, 16690 }, 16691 }, 16692 { 16693 name: "CMPWUconst", 16694 auxType: auxInt32, 16695 argLen: 1, 16696 asm: ppc64.ACMPWU, 16697 reg: regInfo{ 16698 inputs: []inputInfo{ 16699 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16700 }, 16701 }, 16702 }, 16703 { 16704 name: "Equal", 16705 argLen: 1, 16706 reg: regInfo{ 16707 outputs: []outputInfo{ 16708 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16709 }, 16710 }, 16711 }, 16712 { 16713 name: "NotEqual", 16714 argLen: 1, 16715 reg: regInfo{ 16716 outputs: []outputInfo{ 16717 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16718 }, 16719 }, 16720 }, 16721 { 16722 name: "LessThan", 16723 argLen: 1, 16724 reg: regInfo{ 16725 outputs: []outputInfo{ 16726 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16727 }, 16728 }, 16729 }, 16730 { 16731 name: "FLessThan", 16732 argLen: 1, 16733 reg: regInfo{ 16734 outputs: []outputInfo{ 16735 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16736 }, 16737 }, 16738 }, 16739 { 16740 name: "LessEqual", 16741 argLen: 1, 16742 reg: regInfo{ 16743 outputs: []outputInfo{ 16744 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16745 }, 16746 }, 16747 }, 16748 { 16749 name: "FLessEqual", 16750 argLen: 1, 16751 reg: regInfo{ 16752 outputs: []outputInfo{ 16753 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16754 }, 16755 }, 16756 }, 16757 { 16758 name: "GreaterThan", 16759 argLen: 1, 16760 reg: regInfo{ 16761 outputs: []outputInfo{ 16762 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16763 }, 16764 }, 16765 }, 16766 { 16767 name: "FGreaterThan", 16768 argLen: 1, 16769 reg: regInfo{ 16770 outputs: []outputInfo{ 16771 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16772 }, 16773 }, 16774 }, 16775 { 16776 name: "GreaterEqual", 16777 argLen: 1, 16778 reg: regInfo{ 16779 outputs: []outputInfo{ 16780 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16781 }, 16782 }, 16783 }, 16784 { 16785 name: "FGreaterEqual", 16786 argLen: 1, 16787 reg: regInfo{ 16788 outputs: []outputInfo{ 16789 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16790 }, 16791 }, 16792 }, 16793 { 16794 name: "LoweredGetClosurePtr", 16795 argLen: 0, 16796 reg: regInfo{ 16797 outputs: []outputInfo{ 16798 {0, 2048}, // R11 16799 }, 16800 }, 16801 }, 16802 { 16803 name: "LoweredNilCheck", 16804 argLen: 2, 16805 clobberFlags: true, 16806 nilCheck: true, 16807 faultOnNilArg0: true, 16808 reg: regInfo{ 16809 inputs: []inputInfo{ 16810 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16811 }, 16812 clobbers: 2147483648, // R31 16813 }, 16814 }, 16815 { 16816 name: "MOVDconvert", 16817 argLen: 2, 16818 asm: ppc64.AMOVD, 16819 reg: regInfo{ 16820 inputs: []inputInfo{ 16821 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16822 }, 16823 outputs: []outputInfo{ 16824 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16825 }, 16826 }, 16827 }, 16828 { 16829 name: "CALLstatic", 16830 auxType: auxSymOff, 16831 argLen: 1, 16832 clobberFlags: true, 16833 call: true, 16834 reg: regInfo{ 16835 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16836 }, 16837 }, 16838 { 16839 name: "CALLclosure", 16840 auxType: auxInt64, 16841 argLen: 3, 16842 clobberFlags: true, 16843 call: true, 16844 reg: regInfo{ 16845 inputs: []inputInfo{ 16846 {1, 2048}, // R11 16847 {0, 1073733626}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16848 }, 16849 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16850 }, 16851 }, 16852 { 16853 name: "CALLdefer", 16854 auxType: auxInt64, 16855 argLen: 1, 16856 clobberFlags: true, 16857 call: true, 16858 reg: regInfo{ 16859 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16860 }, 16861 }, 16862 { 16863 name: "CALLgo", 16864 auxType: auxInt64, 16865 argLen: 1, 16866 clobberFlags: true, 16867 call: true, 16868 reg: regInfo{ 16869 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16870 }, 16871 }, 16872 { 16873 name: "CALLinter", 16874 auxType: auxInt64, 16875 argLen: 2, 16876 clobberFlags: true, 16877 call: true, 16878 reg: regInfo{ 16879 inputs: []inputInfo{ 16880 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16881 }, 16882 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16883 }, 16884 }, 16885 { 16886 name: "LoweredZero", 16887 auxType: auxInt64, 16888 argLen: 3, 16889 clobberFlags: true, 16890 faultOnNilArg0: true, 16891 reg: regInfo{ 16892 inputs: []inputInfo{ 16893 {0, 8}, // R3 16894 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16895 }, 16896 clobbers: 8, // R3 16897 }, 16898 }, 16899 { 16900 name: "LoweredMove", 16901 auxType: auxInt64, 16902 argLen: 4, 16903 clobberFlags: true, 16904 faultOnNilArg0: true, 16905 faultOnNilArg1: true, 16906 reg: regInfo{ 16907 inputs: []inputInfo{ 16908 {0, 8}, // R3 16909 {1, 16}, // R4 16910 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16911 }, 16912 clobbers: 24, // R3 R4 16913 }, 16914 }, 16915 { 16916 name: "InvertFlags", 16917 argLen: 1, 16918 reg: regInfo{}, 16919 }, 16920 { 16921 name: "FlagEQ", 16922 argLen: 0, 16923 reg: regInfo{}, 16924 }, 16925 { 16926 name: "FlagLT", 16927 argLen: 0, 16928 reg: regInfo{}, 16929 }, 16930 { 16931 name: "FlagGT", 16932 argLen: 0, 16933 reg: regInfo{}, 16934 }, 16935 16936 { 16937 name: "FADDS", 16938 argLen: 2, 16939 commutative: true, 16940 resultInArg0: true, 16941 clobberFlags: true, 16942 asm: s390x.AFADDS, 16943 reg: regInfo{ 16944 inputs: []inputInfo{ 16945 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16946 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16947 }, 16948 outputs: []outputInfo{ 16949 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16950 }, 16951 }, 16952 }, 16953 { 16954 name: "FADD", 16955 argLen: 2, 16956 commutative: true, 16957 resultInArg0: true, 16958 clobberFlags: true, 16959 asm: s390x.AFADD, 16960 reg: regInfo{ 16961 inputs: []inputInfo{ 16962 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16963 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16964 }, 16965 outputs: []outputInfo{ 16966 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16967 }, 16968 }, 16969 }, 16970 { 16971 name: "FSUBS", 16972 argLen: 2, 16973 resultInArg0: true, 16974 clobberFlags: true, 16975 asm: s390x.AFSUBS, 16976 reg: regInfo{ 16977 inputs: []inputInfo{ 16978 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16979 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16980 }, 16981 outputs: []outputInfo{ 16982 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16983 }, 16984 }, 16985 }, 16986 { 16987 name: "FSUB", 16988 argLen: 2, 16989 resultInArg0: true, 16990 clobberFlags: true, 16991 asm: s390x.AFSUB, 16992 reg: regInfo{ 16993 inputs: []inputInfo{ 16994 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16995 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16996 }, 16997 outputs: []outputInfo{ 16998 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16999 }, 17000 }, 17001 }, 17002 { 17003 name: "FMULS", 17004 argLen: 2, 17005 commutative: true, 17006 resultInArg0: true, 17007 asm: s390x.AFMULS, 17008 reg: regInfo{ 17009 inputs: []inputInfo{ 17010 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17011 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17012 }, 17013 outputs: []outputInfo{ 17014 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17015 }, 17016 }, 17017 }, 17018 { 17019 name: "FMUL", 17020 argLen: 2, 17021 commutative: true, 17022 resultInArg0: true, 17023 asm: s390x.AFMUL, 17024 reg: regInfo{ 17025 inputs: []inputInfo{ 17026 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17027 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17028 }, 17029 outputs: []outputInfo{ 17030 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17031 }, 17032 }, 17033 }, 17034 { 17035 name: "FDIVS", 17036 argLen: 2, 17037 resultInArg0: true, 17038 asm: s390x.AFDIVS, 17039 reg: regInfo{ 17040 inputs: []inputInfo{ 17041 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17042 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17043 }, 17044 outputs: []outputInfo{ 17045 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17046 }, 17047 }, 17048 }, 17049 { 17050 name: "FDIV", 17051 argLen: 2, 17052 resultInArg0: true, 17053 asm: s390x.AFDIV, 17054 reg: regInfo{ 17055 inputs: []inputInfo{ 17056 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17057 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17058 }, 17059 outputs: []outputInfo{ 17060 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17061 }, 17062 }, 17063 }, 17064 { 17065 name: "FNEGS", 17066 argLen: 1, 17067 clobberFlags: true, 17068 asm: s390x.AFNEGS, 17069 reg: regInfo{ 17070 inputs: []inputInfo{ 17071 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17072 }, 17073 outputs: []outputInfo{ 17074 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17075 }, 17076 }, 17077 }, 17078 { 17079 name: "FNEG", 17080 argLen: 1, 17081 clobberFlags: true, 17082 asm: s390x.AFNEG, 17083 reg: regInfo{ 17084 inputs: []inputInfo{ 17085 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17086 }, 17087 outputs: []outputInfo{ 17088 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17089 }, 17090 }, 17091 }, 17092 { 17093 name: "FMOVSload", 17094 auxType: auxSymOff, 17095 argLen: 2, 17096 faultOnNilArg0: true, 17097 asm: s390x.AFMOVS, 17098 reg: regInfo{ 17099 inputs: []inputInfo{ 17100 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17101 }, 17102 outputs: []outputInfo{ 17103 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17104 }, 17105 }, 17106 }, 17107 { 17108 name: "FMOVDload", 17109 auxType: auxSymOff, 17110 argLen: 2, 17111 faultOnNilArg0: true, 17112 asm: s390x.AFMOVD, 17113 reg: regInfo{ 17114 inputs: []inputInfo{ 17115 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17116 }, 17117 outputs: []outputInfo{ 17118 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17119 }, 17120 }, 17121 }, 17122 { 17123 name: "FMOVSconst", 17124 auxType: auxFloat32, 17125 argLen: 0, 17126 rematerializeable: true, 17127 asm: s390x.AFMOVS, 17128 reg: regInfo{ 17129 outputs: []outputInfo{ 17130 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17131 }, 17132 }, 17133 }, 17134 { 17135 name: "FMOVDconst", 17136 auxType: auxFloat64, 17137 argLen: 0, 17138 rematerializeable: true, 17139 asm: s390x.AFMOVD, 17140 reg: regInfo{ 17141 outputs: []outputInfo{ 17142 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17143 }, 17144 }, 17145 }, 17146 { 17147 name: "FMOVSloadidx", 17148 auxType: auxSymOff, 17149 argLen: 3, 17150 asm: s390x.AFMOVS, 17151 reg: regInfo{ 17152 inputs: []inputInfo{ 17153 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17154 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17155 }, 17156 outputs: []outputInfo{ 17157 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17158 }, 17159 }, 17160 }, 17161 { 17162 name: "FMOVDloadidx", 17163 auxType: auxSymOff, 17164 argLen: 3, 17165 asm: s390x.AFMOVD, 17166 reg: regInfo{ 17167 inputs: []inputInfo{ 17168 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17169 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17170 }, 17171 outputs: []outputInfo{ 17172 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17173 }, 17174 }, 17175 }, 17176 { 17177 name: "FMOVSstore", 17178 auxType: auxSymOff, 17179 argLen: 3, 17180 faultOnNilArg0: true, 17181 asm: s390x.AFMOVS, 17182 reg: regInfo{ 17183 inputs: []inputInfo{ 17184 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17185 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17186 }, 17187 }, 17188 }, 17189 { 17190 name: "FMOVDstore", 17191 auxType: auxSymOff, 17192 argLen: 3, 17193 faultOnNilArg0: true, 17194 asm: s390x.AFMOVD, 17195 reg: regInfo{ 17196 inputs: []inputInfo{ 17197 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17198 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17199 }, 17200 }, 17201 }, 17202 { 17203 name: "FMOVSstoreidx", 17204 auxType: auxSymOff, 17205 argLen: 4, 17206 asm: s390x.AFMOVS, 17207 reg: regInfo{ 17208 inputs: []inputInfo{ 17209 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17210 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17211 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17212 }, 17213 }, 17214 }, 17215 { 17216 name: "FMOVDstoreidx", 17217 auxType: auxSymOff, 17218 argLen: 4, 17219 asm: s390x.AFMOVD, 17220 reg: regInfo{ 17221 inputs: []inputInfo{ 17222 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17223 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17224 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17225 }, 17226 }, 17227 }, 17228 { 17229 name: "ADD", 17230 argLen: 2, 17231 commutative: true, 17232 clobberFlags: true, 17233 asm: s390x.AADD, 17234 reg: regInfo{ 17235 inputs: []inputInfo{ 17236 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17237 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17238 }, 17239 outputs: []outputInfo{ 17240 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17241 }, 17242 }, 17243 }, 17244 { 17245 name: "ADDW", 17246 argLen: 2, 17247 commutative: true, 17248 clobberFlags: true, 17249 asm: s390x.AADDW, 17250 reg: regInfo{ 17251 inputs: []inputInfo{ 17252 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17253 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17254 }, 17255 outputs: []outputInfo{ 17256 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17257 }, 17258 }, 17259 }, 17260 { 17261 name: "ADDconst", 17262 auxType: auxInt64, 17263 argLen: 1, 17264 clobberFlags: true, 17265 asm: s390x.AADD, 17266 reg: regInfo{ 17267 inputs: []inputInfo{ 17268 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17269 }, 17270 outputs: []outputInfo{ 17271 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17272 }, 17273 }, 17274 }, 17275 { 17276 name: "ADDWconst", 17277 auxType: auxInt32, 17278 argLen: 1, 17279 clobberFlags: true, 17280 asm: s390x.AADDW, 17281 reg: regInfo{ 17282 inputs: []inputInfo{ 17283 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17284 }, 17285 outputs: []outputInfo{ 17286 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17287 }, 17288 }, 17289 }, 17290 { 17291 name: "ADDload", 17292 auxType: auxSymOff, 17293 argLen: 3, 17294 resultInArg0: true, 17295 clobberFlags: true, 17296 faultOnNilArg1: true, 17297 asm: s390x.AADD, 17298 reg: regInfo{ 17299 inputs: []inputInfo{ 17300 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17301 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17302 }, 17303 outputs: []outputInfo{ 17304 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17305 }, 17306 }, 17307 }, 17308 { 17309 name: "ADDWload", 17310 auxType: auxSymOff, 17311 argLen: 3, 17312 resultInArg0: true, 17313 clobberFlags: true, 17314 faultOnNilArg1: true, 17315 asm: s390x.AADDW, 17316 reg: regInfo{ 17317 inputs: []inputInfo{ 17318 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17319 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17320 }, 17321 outputs: []outputInfo{ 17322 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17323 }, 17324 }, 17325 }, 17326 { 17327 name: "SUB", 17328 argLen: 2, 17329 clobberFlags: true, 17330 asm: s390x.ASUB, 17331 reg: regInfo{ 17332 inputs: []inputInfo{ 17333 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17334 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17335 }, 17336 outputs: []outputInfo{ 17337 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17338 }, 17339 }, 17340 }, 17341 { 17342 name: "SUBW", 17343 argLen: 2, 17344 clobberFlags: true, 17345 asm: s390x.ASUBW, 17346 reg: regInfo{ 17347 inputs: []inputInfo{ 17348 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17349 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17350 }, 17351 outputs: []outputInfo{ 17352 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17353 }, 17354 }, 17355 }, 17356 { 17357 name: "SUBconst", 17358 auxType: auxInt64, 17359 argLen: 1, 17360 resultInArg0: true, 17361 clobberFlags: true, 17362 asm: s390x.ASUB, 17363 reg: regInfo{ 17364 inputs: []inputInfo{ 17365 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17366 }, 17367 outputs: []outputInfo{ 17368 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17369 }, 17370 }, 17371 }, 17372 { 17373 name: "SUBWconst", 17374 auxType: auxInt32, 17375 argLen: 1, 17376 resultInArg0: true, 17377 clobberFlags: true, 17378 asm: s390x.ASUBW, 17379 reg: regInfo{ 17380 inputs: []inputInfo{ 17381 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17382 }, 17383 outputs: []outputInfo{ 17384 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17385 }, 17386 }, 17387 }, 17388 { 17389 name: "SUBload", 17390 auxType: auxSymOff, 17391 argLen: 3, 17392 resultInArg0: true, 17393 clobberFlags: true, 17394 faultOnNilArg1: true, 17395 asm: s390x.ASUB, 17396 reg: regInfo{ 17397 inputs: []inputInfo{ 17398 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17399 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17400 }, 17401 outputs: []outputInfo{ 17402 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17403 }, 17404 }, 17405 }, 17406 { 17407 name: "SUBWload", 17408 auxType: auxSymOff, 17409 argLen: 3, 17410 resultInArg0: true, 17411 clobberFlags: true, 17412 faultOnNilArg1: true, 17413 asm: s390x.ASUBW, 17414 reg: regInfo{ 17415 inputs: []inputInfo{ 17416 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17417 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17418 }, 17419 outputs: []outputInfo{ 17420 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17421 }, 17422 }, 17423 }, 17424 { 17425 name: "MULLD", 17426 argLen: 2, 17427 commutative: true, 17428 resultInArg0: true, 17429 clobberFlags: true, 17430 asm: s390x.AMULLD, 17431 reg: regInfo{ 17432 inputs: []inputInfo{ 17433 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17434 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17435 }, 17436 outputs: []outputInfo{ 17437 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17438 }, 17439 }, 17440 }, 17441 { 17442 name: "MULLW", 17443 argLen: 2, 17444 commutative: true, 17445 resultInArg0: true, 17446 clobberFlags: true, 17447 asm: s390x.AMULLW, 17448 reg: regInfo{ 17449 inputs: []inputInfo{ 17450 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17451 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17452 }, 17453 outputs: []outputInfo{ 17454 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17455 }, 17456 }, 17457 }, 17458 { 17459 name: "MULLDconst", 17460 auxType: auxInt64, 17461 argLen: 1, 17462 resultInArg0: true, 17463 clobberFlags: true, 17464 asm: s390x.AMULLD, 17465 reg: regInfo{ 17466 inputs: []inputInfo{ 17467 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17468 }, 17469 outputs: []outputInfo{ 17470 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17471 }, 17472 }, 17473 }, 17474 { 17475 name: "MULLWconst", 17476 auxType: auxInt32, 17477 argLen: 1, 17478 resultInArg0: true, 17479 clobberFlags: true, 17480 asm: s390x.AMULLW, 17481 reg: regInfo{ 17482 inputs: []inputInfo{ 17483 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17484 }, 17485 outputs: []outputInfo{ 17486 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17487 }, 17488 }, 17489 }, 17490 { 17491 name: "MULLDload", 17492 auxType: auxSymOff, 17493 argLen: 3, 17494 resultInArg0: true, 17495 clobberFlags: true, 17496 faultOnNilArg1: true, 17497 asm: s390x.AMULLD, 17498 reg: regInfo{ 17499 inputs: []inputInfo{ 17500 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17501 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17502 }, 17503 outputs: []outputInfo{ 17504 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17505 }, 17506 }, 17507 }, 17508 { 17509 name: "MULLWload", 17510 auxType: auxSymOff, 17511 argLen: 3, 17512 resultInArg0: true, 17513 clobberFlags: true, 17514 faultOnNilArg1: true, 17515 asm: s390x.AMULLW, 17516 reg: regInfo{ 17517 inputs: []inputInfo{ 17518 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17519 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17520 }, 17521 outputs: []outputInfo{ 17522 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17523 }, 17524 }, 17525 }, 17526 { 17527 name: "MULHD", 17528 argLen: 2, 17529 resultInArg0: true, 17530 clobberFlags: true, 17531 asm: s390x.AMULHD, 17532 reg: regInfo{ 17533 inputs: []inputInfo{ 17534 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17535 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17536 }, 17537 outputs: []outputInfo{ 17538 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17539 }, 17540 }, 17541 }, 17542 { 17543 name: "MULHDU", 17544 argLen: 2, 17545 resultInArg0: true, 17546 clobberFlags: true, 17547 asm: s390x.AMULHDU, 17548 reg: regInfo{ 17549 inputs: []inputInfo{ 17550 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17551 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17552 }, 17553 outputs: []outputInfo{ 17554 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17555 }, 17556 }, 17557 }, 17558 { 17559 name: "DIVD", 17560 argLen: 2, 17561 resultInArg0: true, 17562 clobberFlags: true, 17563 asm: s390x.ADIVD, 17564 reg: regInfo{ 17565 inputs: []inputInfo{ 17566 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17567 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17568 }, 17569 outputs: []outputInfo{ 17570 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17571 }, 17572 }, 17573 }, 17574 { 17575 name: "DIVW", 17576 argLen: 2, 17577 resultInArg0: true, 17578 clobberFlags: true, 17579 asm: s390x.ADIVW, 17580 reg: regInfo{ 17581 inputs: []inputInfo{ 17582 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17583 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17584 }, 17585 outputs: []outputInfo{ 17586 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17587 }, 17588 }, 17589 }, 17590 { 17591 name: "DIVDU", 17592 argLen: 2, 17593 resultInArg0: true, 17594 clobberFlags: true, 17595 asm: s390x.ADIVDU, 17596 reg: regInfo{ 17597 inputs: []inputInfo{ 17598 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17599 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17600 }, 17601 outputs: []outputInfo{ 17602 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17603 }, 17604 }, 17605 }, 17606 { 17607 name: "DIVWU", 17608 argLen: 2, 17609 resultInArg0: true, 17610 clobberFlags: true, 17611 asm: s390x.ADIVWU, 17612 reg: regInfo{ 17613 inputs: []inputInfo{ 17614 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17615 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17616 }, 17617 outputs: []outputInfo{ 17618 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17619 }, 17620 }, 17621 }, 17622 { 17623 name: "MODD", 17624 argLen: 2, 17625 resultInArg0: true, 17626 clobberFlags: true, 17627 asm: s390x.AMODD, 17628 reg: regInfo{ 17629 inputs: []inputInfo{ 17630 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17631 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17632 }, 17633 outputs: []outputInfo{ 17634 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17635 }, 17636 }, 17637 }, 17638 { 17639 name: "MODW", 17640 argLen: 2, 17641 resultInArg0: true, 17642 clobberFlags: true, 17643 asm: s390x.AMODW, 17644 reg: regInfo{ 17645 inputs: []inputInfo{ 17646 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17647 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17648 }, 17649 outputs: []outputInfo{ 17650 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17651 }, 17652 }, 17653 }, 17654 { 17655 name: "MODDU", 17656 argLen: 2, 17657 resultInArg0: true, 17658 clobberFlags: true, 17659 asm: s390x.AMODDU, 17660 reg: regInfo{ 17661 inputs: []inputInfo{ 17662 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17663 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17664 }, 17665 outputs: []outputInfo{ 17666 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17667 }, 17668 }, 17669 }, 17670 { 17671 name: "MODWU", 17672 argLen: 2, 17673 resultInArg0: true, 17674 clobberFlags: true, 17675 asm: s390x.AMODWU, 17676 reg: regInfo{ 17677 inputs: []inputInfo{ 17678 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17679 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17680 }, 17681 outputs: []outputInfo{ 17682 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17683 }, 17684 }, 17685 }, 17686 { 17687 name: "AND", 17688 argLen: 2, 17689 commutative: true, 17690 clobberFlags: true, 17691 asm: s390x.AAND, 17692 reg: regInfo{ 17693 inputs: []inputInfo{ 17694 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17695 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17696 }, 17697 outputs: []outputInfo{ 17698 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17699 }, 17700 }, 17701 }, 17702 { 17703 name: "ANDW", 17704 argLen: 2, 17705 commutative: true, 17706 clobberFlags: true, 17707 asm: s390x.AANDW, 17708 reg: regInfo{ 17709 inputs: []inputInfo{ 17710 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17711 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17712 }, 17713 outputs: []outputInfo{ 17714 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17715 }, 17716 }, 17717 }, 17718 { 17719 name: "ANDconst", 17720 auxType: auxInt64, 17721 argLen: 1, 17722 resultInArg0: true, 17723 clobberFlags: true, 17724 asm: s390x.AAND, 17725 reg: regInfo{ 17726 inputs: []inputInfo{ 17727 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17728 }, 17729 outputs: []outputInfo{ 17730 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17731 }, 17732 }, 17733 }, 17734 { 17735 name: "ANDWconst", 17736 auxType: auxInt32, 17737 argLen: 1, 17738 resultInArg0: true, 17739 clobberFlags: true, 17740 asm: s390x.AANDW, 17741 reg: regInfo{ 17742 inputs: []inputInfo{ 17743 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17744 }, 17745 outputs: []outputInfo{ 17746 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17747 }, 17748 }, 17749 }, 17750 { 17751 name: "ANDload", 17752 auxType: auxSymOff, 17753 argLen: 3, 17754 resultInArg0: true, 17755 clobberFlags: true, 17756 faultOnNilArg1: true, 17757 asm: s390x.AAND, 17758 reg: regInfo{ 17759 inputs: []inputInfo{ 17760 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17761 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17762 }, 17763 outputs: []outputInfo{ 17764 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17765 }, 17766 }, 17767 }, 17768 { 17769 name: "ANDWload", 17770 auxType: auxSymOff, 17771 argLen: 3, 17772 resultInArg0: true, 17773 clobberFlags: true, 17774 faultOnNilArg1: true, 17775 asm: s390x.AANDW, 17776 reg: regInfo{ 17777 inputs: []inputInfo{ 17778 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17779 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17780 }, 17781 outputs: []outputInfo{ 17782 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17783 }, 17784 }, 17785 }, 17786 { 17787 name: "OR", 17788 argLen: 2, 17789 commutative: true, 17790 clobberFlags: true, 17791 asm: s390x.AOR, 17792 reg: regInfo{ 17793 inputs: []inputInfo{ 17794 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17795 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17796 }, 17797 outputs: []outputInfo{ 17798 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17799 }, 17800 }, 17801 }, 17802 { 17803 name: "ORW", 17804 argLen: 2, 17805 commutative: true, 17806 clobberFlags: true, 17807 asm: s390x.AORW, 17808 reg: regInfo{ 17809 inputs: []inputInfo{ 17810 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17811 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17812 }, 17813 outputs: []outputInfo{ 17814 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17815 }, 17816 }, 17817 }, 17818 { 17819 name: "ORconst", 17820 auxType: auxInt64, 17821 argLen: 1, 17822 resultInArg0: true, 17823 clobberFlags: true, 17824 asm: s390x.AOR, 17825 reg: regInfo{ 17826 inputs: []inputInfo{ 17827 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17828 }, 17829 outputs: []outputInfo{ 17830 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17831 }, 17832 }, 17833 }, 17834 { 17835 name: "ORWconst", 17836 auxType: auxInt32, 17837 argLen: 1, 17838 resultInArg0: true, 17839 clobberFlags: true, 17840 asm: s390x.AORW, 17841 reg: regInfo{ 17842 inputs: []inputInfo{ 17843 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17844 }, 17845 outputs: []outputInfo{ 17846 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17847 }, 17848 }, 17849 }, 17850 { 17851 name: "ORload", 17852 auxType: auxSymOff, 17853 argLen: 3, 17854 resultInArg0: true, 17855 clobberFlags: true, 17856 faultOnNilArg1: true, 17857 asm: s390x.AOR, 17858 reg: regInfo{ 17859 inputs: []inputInfo{ 17860 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17861 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17862 }, 17863 outputs: []outputInfo{ 17864 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17865 }, 17866 }, 17867 }, 17868 { 17869 name: "ORWload", 17870 auxType: auxSymOff, 17871 argLen: 3, 17872 resultInArg0: true, 17873 clobberFlags: true, 17874 faultOnNilArg1: true, 17875 asm: s390x.AORW, 17876 reg: regInfo{ 17877 inputs: []inputInfo{ 17878 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17879 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17880 }, 17881 outputs: []outputInfo{ 17882 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17883 }, 17884 }, 17885 }, 17886 { 17887 name: "XOR", 17888 argLen: 2, 17889 commutative: true, 17890 clobberFlags: true, 17891 asm: s390x.AXOR, 17892 reg: regInfo{ 17893 inputs: []inputInfo{ 17894 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17895 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17896 }, 17897 outputs: []outputInfo{ 17898 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17899 }, 17900 }, 17901 }, 17902 { 17903 name: "XORW", 17904 argLen: 2, 17905 commutative: true, 17906 clobberFlags: true, 17907 asm: s390x.AXORW, 17908 reg: regInfo{ 17909 inputs: []inputInfo{ 17910 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17911 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17912 }, 17913 outputs: []outputInfo{ 17914 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17915 }, 17916 }, 17917 }, 17918 { 17919 name: "XORconst", 17920 auxType: auxInt64, 17921 argLen: 1, 17922 resultInArg0: true, 17923 clobberFlags: true, 17924 asm: s390x.AXOR, 17925 reg: regInfo{ 17926 inputs: []inputInfo{ 17927 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17928 }, 17929 outputs: []outputInfo{ 17930 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17931 }, 17932 }, 17933 }, 17934 { 17935 name: "XORWconst", 17936 auxType: auxInt32, 17937 argLen: 1, 17938 resultInArg0: true, 17939 clobberFlags: true, 17940 asm: s390x.AXORW, 17941 reg: regInfo{ 17942 inputs: []inputInfo{ 17943 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17944 }, 17945 outputs: []outputInfo{ 17946 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17947 }, 17948 }, 17949 }, 17950 { 17951 name: "XORload", 17952 auxType: auxSymOff, 17953 argLen: 3, 17954 resultInArg0: true, 17955 clobberFlags: true, 17956 faultOnNilArg1: true, 17957 asm: s390x.AXOR, 17958 reg: regInfo{ 17959 inputs: []inputInfo{ 17960 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17961 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17962 }, 17963 outputs: []outputInfo{ 17964 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17965 }, 17966 }, 17967 }, 17968 { 17969 name: "XORWload", 17970 auxType: auxSymOff, 17971 argLen: 3, 17972 resultInArg0: true, 17973 clobberFlags: true, 17974 faultOnNilArg1: true, 17975 asm: s390x.AXORW, 17976 reg: regInfo{ 17977 inputs: []inputInfo{ 17978 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17979 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17980 }, 17981 outputs: []outputInfo{ 17982 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17983 }, 17984 }, 17985 }, 17986 { 17987 name: "CMP", 17988 argLen: 2, 17989 asm: s390x.ACMP, 17990 reg: regInfo{ 17991 inputs: []inputInfo{ 17992 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17993 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17994 }, 17995 }, 17996 }, 17997 { 17998 name: "CMPW", 17999 argLen: 2, 18000 asm: s390x.ACMPW, 18001 reg: regInfo{ 18002 inputs: []inputInfo{ 18003 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18004 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18005 }, 18006 }, 18007 }, 18008 { 18009 name: "CMPU", 18010 argLen: 2, 18011 asm: s390x.ACMPU, 18012 reg: regInfo{ 18013 inputs: []inputInfo{ 18014 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18015 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18016 }, 18017 }, 18018 }, 18019 { 18020 name: "CMPWU", 18021 argLen: 2, 18022 asm: s390x.ACMPWU, 18023 reg: regInfo{ 18024 inputs: []inputInfo{ 18025 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18026 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18027 }, 18028 }, 18029 }, 18030 { 18031 name: "CMPconst", 18032 auxType: auxInt64, 18033 argLen: 1, 18034 asm: s390x.ACMP, 18035 reg: regInfo{ 18036 inputs: []inputInfo{ 18037 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18038 }, 18039 }, 18040 }, 18041 { 18042 name: "CMPWconst", 18043 auxType: auxInt32, 18044 argLen: 1, 18045 asm: s390x.ACMPW, 18046 reg: regInfo{ 18047 inputs: []inputInfo{ 18048 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18049 }, 18050 }, 18051 }, 18052 { 18053 name: "CMPUconst", 18054 auxType: auxInt64, 18055 argLen: 1, 18056 asm: s390x.ACMPU, 18057 reg: regInfo{ 18058 inputs: []inputInfo{ 18059 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18060 }, 18061 }, 18062 }, 18063 { 18064 name: "CMPWUconst", 18065 auxType: auxInt32, 18066 argLen: 1, 18067 asm: s390x.ACMPWU, 18068 reg: regInfo{ 18069 inputs: []inputInfo{ 18070 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18071 }, 18072 }, 18073 }, 18074 { 18075 name: "FCMPS", 18076 argLen: 2, 18077 asm: s390x.ACEBR, 18078 reg: regInfo{ 18079 inputs: []inputInfo{ 18080 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18081 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18082 }, 18083 }, 18084 }, 18085 { 18086 name: "FCMP", 18087 argLen: 2, 18088 asm: s390x.AFCMPU, 18089 reg: regInfo{ 18090 inputs: []inputInfo{ 18091 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18092 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18093 }, 18094 }, 18095 }, 18096 { 18097 name: "SLD", 18098 argLen: 2, 18099 asm: s390x.ASLD, 18100 reg: regInfo{ 18101 inputs: []inputInfo{ 18102 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18103 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18104 }, 18105 outputs: []outputInfo{ 18106 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18107 }, 18108 }, 18109 }, 18110 { 18111 name: "SLW", 18112 argLen: 2, 18113 asm: s390x.ASLW, 18114 reg: regInfo{ 18115 inputs: []inputInfo{ 18116 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18117 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18118 }, 18119 outputs: []outputInfo{ 18120 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18121 }, 18122 }, 18123 }, 18124 { 18125 name: "SLDconst", 18126 auxType: auxInt64, 18127 argLen: 1, 18128 asm: s390x.ASLD, 18129 reg: regInfo{ 18130 inputs: []inputInfo{ 18131 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18132 }, 18133 outputs: []outputInfo{ 18134 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18135 }, 18136 }, 18137 }, 18138 { 18139 name: "SLWconst", 18140 auxType: auxInt32, 18141 argLen: 1, 18142 asm: s390x.ASLW, 18143 reg: regInfo{ 18144 inputs: []inputInfo{ 18145 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18146 }, 18147 outputs: []outputInfo{ 18148 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18149 }, 18150 }, 18151 }, 18152 { 18153 name: "SRD", 18154 argLen: 2, 18155 asm: s390x.ASRD, 18156 reg: regInfo{ 18157 inputs: []inputInfo{ 18158 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18159 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18160 }, 18161 outputs: []outputInfo{ 18162 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18163 }, 18164 }, 18165 }, 18166 { 18167 name: "SRW", 18168 argLen: 2, 18169 asm: s390x.ASRW, 18170 reg: regInfo{ 18171 inputs: []inputInfo{ 18172 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18173 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18174 }, 18175 outputs: []outputInfo{ 18176 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18177 }, 18178 }, 18179 }, 18180 { 18181 name: "SRDconst", 18182 auxType: auxInt64, 18183 argLen: 1, 18184 asm: s390x.ASRD, 18185 reg: regInfo{ 18186 inputs: []inputInfo{ 18187 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18188 }, 18189 outputs: []outputInfo{ 18190 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18191 }, 18192 }, 18193 }, 18194 { 18195 name: "SRWconst", 18196 auxType: auxInt32, 18197 argLen: 1, 18198 asm: s390x.ASRW, 18199 reg: regInfo{ 18200 inputs: []inputInfo{ 18201 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18202 }, 18203 outputs: []outputInfo{ 18204 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18205 }, 18206 }, 18207 }, 18208 { 18209 name: "SRAD", 18210 argLen: 2, 18211 clobberFlags: true, 18212 asm: s390x.ASRAD, 18213 reg: regInfo{ 18214 inputs: []inputInfo{ 18215 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18216 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18217 }, 18218 outputs: []outputInfo{ 18219 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18220 }, 18221 }, 18222 }, 18223 { 18224 name: "SRAW", 18225 argLen: 2, 18226 clobberFlags: true, 18227 asm: s390x.ASRAW, 18228 reg: regInfo{ 18229 inputs: []inputInfo{ 18230 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18231 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18232 }, 18233 outputs: []outputInfo{ 18234 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18235 }, 18236 }, 18237 }, 18238 { 18239 name: "SRADconst", 18240 auxType: auxInt64, 18241 argLen: 1, 18242 clobberFlags: true, 18243 asm: s390x.ASRAD, 18244 reg: regInfo{ 18245 inputs: []inputInfo{ 18246 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18247 }, 18248 outputs: []outputInfo{ 18249 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18250 }, 18251 }, 18252 }, 18253 { 18254 name: "SRAWconst", 18255 auxType: auxInt32, 18256 argLen: 1, 18257 clobberFlags: true, 18258 asm: s390x.ASRAW, 18259 reg: regInfo{ 18260 inputs: []inputInfo{ 18261 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18262 }, 18263 outputs: []outputInfo{ 18264 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18265 }, 18266 }, 18267 }, 18268 { 18269 name: "RLLGconst", 18270 auxType: auxInt64, 18271 argLen: 1, 18272 asm: s390x.ARLLG, 18273 reg: regInfo{ 18274 inputs: []inputInfo{ 18275 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18276 }, 18277 outputs: []outputInfo{ 18278 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18279 }, 18280 }, 18281 }, 18282 { 18283 name: "RLLconst", 18284 auxType: auxInt32, 18285 argLen: 1, 18286 asm: s390x.ARLL, 18287 reg: regInfo{ 18288 inputs: []inputInfo{ 18289 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18290 }, 18291 outputs: []outputInfo{ 18292 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18293 }, 18294 }, 18295 }, 18296 { 18297 name: "NEG", 18298 argLen: 1, 18299 clobberFlags: true, 18300 asm: s390x.ANEG, 18301 reg: regInfo{ 18302 inputs: []inputInfo{ 18303 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18304 }, 18305 outputs: []outputInfo{ 18306 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18307 }, 18308 }, 18309 }, 18310 { 18311 name: "NEGW", 18312 argLen: 1, 18313 clobberFlags: true, 18314 asm: s390x.ANEGW, 18315 reg: regInfo{ 18316 inputs: []inputInfo{ 18317 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18318 }, 18319 outputs: []outputInfo{ 18320 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18321 }, 18322 }, 18323 }, 18324 { 18325 name: "NOT", 18326 argLen: 1, 18327 resultInArg0: true, 18328 clobberFlags: true, 18329 reg: regInfo{ 18330 inputs: []inputInfo{ 18331 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18332 }, 18333 outputs: []outputInfo{ 18334 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18335 }, 18336 }, 18337 }, 18338 { 18339 name: "NOTW", 18340 argLen: 1, 18341 resultInArg0: true, 18342 clobberFlags: true, 18343 reg: regInfo{ 18344 inputs: []inputInfo{ 18345 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18346 }, 18347 outputs: []outputInfo{ 18348 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18349 }, 18350 }, 18351 }, 18352 { 18353 name: "FSQRT", 18354 argLen: 1, 18355 asm: s390x.AFSQRT, 18356 reg: regInfo{ 18357 inputs: []inputInfo{ 18358 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18359 }, 18360 outputs: []outputInfo{ 18361 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18362 }, 18363 }, 18364 }, 18365 { 18366 name: "SUBEcarrymask", 18367 argLen: 1, 18368 asm: s390x.ASUBE, 18369 reg: regInfo{ 18370 outputs: []outputInfo{ 18371 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18372 }, 18373 }, 18374 }, 18375 { 18376 name: "SUBEWcarrymask", 18377 argLen: 1, 18378 asm: s390x.ASUBE, 18379 reg: regInfo{ 18380 outputs: []outputInfo{ 18381 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18382 }, 18383 }, 18384 }, 18385 { 18386 name: "MOVDEQ", 18387 argLen: 3, 18388 resultInArg0: true, 18389 asm: s390x.AMOVDEQ, 18390 reg: regInfo{ 18391 inputs: []inputInfo{ 18392 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18393 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18394 }, 18395 outputs: []outputInfo{ 18396 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18397 }, 18398 }, 18399 }, 18400 { 18401 name: "MOVDNE", 18402 argLen: 3, 18403 resultInArg0: true, 18404 asm: s390x.AMOVDNE, 18405 reg: regInfo{ 18406 inputs: []inputInfo{ 18407 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18408 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18409 }, 18410 outputs: []outputInfo{ 18411 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18412 }, 18413 }, 18414 }, 18415 { 18416 name: "MOVDLT", 18417 argLen: 3, 18418 resultInArg0: true, 18419 asm: s390x.AMOVDLT, 18420 reg: regInfo{ 18421 inputs: []inputInfo{ 18422 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18423 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18424 }, 18425 outputs: []outputInfo{ 18426 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18427 }, 18428 }, 18429 }, 18430 { 18431 name: "MOVDLE", 18432 argLen: 3, 18433 resultInArg0: true, 18434 asm: s390x.AMOVDLE, 18435 reg: regInfo{ 18436 inputs: []inputInfo{ 18437 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18438 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18439 }, 18440 outputs: []outputInfo{ 18441 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18442 }, 18443 }, 18444 }, 18445 { 18446 name: "MOVDGT", 18447 argLen: 3, 18448 resultInArg0: true, 18449 asm: s390x.AMOVDGT, 18450 reg: regInfo{ 18451 inputs: []inputInfo{ 18452 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18453 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18454 }, 18455 outputs: []outputInfo{ 18456 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18457 }, 18458 }, 18459 }, 18460 { 18461 name: "MOVDGE", 18462 argLen: 3, 18463 resultInArg0: true, 18464 asm: s390x.AMOVDGE, 18465 reg: regInfo{ 18466 inputs: []inputInfo{ 18467 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18468 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18469 }, 18470 outputs: []outputInfo{ 18471 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18472 }, 18473 }, 18474 }, 18475 { 18476 name: "MOVDGTnoinv", 18477 argLen: 3, 18478 resultInArg0: true, 18479 asm: s390x.AMOVDGT, 18480 reg: regInfo{ 18481 inputs: []inputInfo{ 18482 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18483 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18484 }, 18485 outputs: []outputInfo{ 18486 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18487 }, 18488 }, 18489 }, 18490 { 18491 name: "MOVDGEnoinv", 18492 argLen: 3, 18493 resultInArg0: true, 18494 asm: s390x.AMOVDGE, 18495 reg: regInfo{ 18496 inputs: []inputInfo{ 18497 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18498 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18499 }, 18500 outputs: []outputInfo{ 18501 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18502 }, 18503 }, 18504 }, 18505 { 18506 name: "MOVBreg", 18507 argLen: 1, 18508 asm: s390x.AMOVB, 18509 reg: regInfo{ 18510 inputs: []inputInfo{ 18511 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18512 }, 18513 outputs: []outputInfo{ 18514 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18515 }, 18516 }, 18517 }, 18518 { 18519 name: "MOVBZreg", 18520 argLen: 1, 18521 asm: s390x.AMOVBZ, 18522 reg: regInfo{ 18523 inputs: []inputInfo{ 18524 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18525 }, 18526 outputs: []outputInfo{ 18527 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18528 }, 18529 }, 18530 }, 18531 { 18532 name: "MOVHreg", 18533 argLen: 1, 18534 asm: s390x.AMOVH, 18535 reg: regInfo{ 18536 inputs: []inputInfo{ 18537 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18538 }, 18539 outputs: []outputInfo{ 18540 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18541 }, 18542 }, 18543 }, 18544 { 18545 name: "MOVHZreg", 18546 argLen: 1, 18547 asm: s390x.AMOVHZ, 18548 reg: regInfo{ 18549 inputs: []inputInfo{ 18550 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18551 }, 18552 outputs: []outputInfo{ 18553 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18554 }, 18555 }, 18556 }, 18557 { 18558 name: "MOVWreg", 18559 argLen: 1, 18560 asm: s390x.AMOVW, 18561 reg: regInfo{ 18562 inputs: []inputInfo{ 18563 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18564 }, 18565 outputs: []outputInfo{ 18566 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18567 }, 18568 }, 18569 }, 18570 { 18571 name: "MOVWZreg", 18572 argLen: 1, 18573 asm: s390x.AMOVWZ, 18574 reg: regInfo{ 18575 inputs: []inputInfo{ 18576 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18577 }, 18578 outputs: []outputInfo{ 18579 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18580 }, 18581 }, 18582 }, 18583 { 18584 name: "MOVDreg", 18585 argLen: 1, 18586 asm: s390x.AMOVD, 18587 reg: regInfo{ 18588 inputs: []inputInfo{ 18589 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18590 }, 18591 outputs: []outputInfo{ 18592 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18593 }, 18594 }, 18595 }, 18596 { 18597 name: "MOVDnop", 18598 argLen: 1, 18599 resultInArg0: true, 18600 reg: regInfo{ 18601 inputs: []inputInfo{ 18602 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18603 }, 18604 outputs: []outputInfo{ 18605 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18606 }, 18607 }, 18608 }, 18609 { 18610 name: "MOVDconst", 18611 auxType: auxInt64, 18612 argLen: 0, 18613 rematerializeable: true, 18614 asm: s390x.AMOVD, 18615 reg: regInfo{ 18616 outputs: []outputInfo{ 18617 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18618 }, 18619 }, 18620 }, 18621 { 18622 name: "CFDBRA", 18623 argLen: 1, 18624 asm: s390x.ACFDBRA, 18625 reg: regInfo{ 18626 inputs: []inputInfo{ 18627 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18628 }, 18629 outputs: []outputInfo{ 18630 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18631 }, 18632 }, 18633 }, 18634 { 18635 name: "CGDBRA", 18636 argLen: 1, 18637 asm: s390x.ACGDBRA, 18638 reg: regInfo{ 18639 inputs: []inputInfo{ 18640 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18641 }, 18642 outputs: []outputInfo{ 18643 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18644 }, 18645 }, 18646 }, 18647 { 18648 name: "CFEBRA", 18649 argLen: 1, 18650 asm: s390x.ACFEBRA, 18651 reg: regInfo{ 18652 inputs: []inputInfo{ 18653 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18654 }, 18655 outputs: []outputInfo{ 18656 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18657 }, 18658 }, 18659 }, 18660 { 18661 name: "CGEBRA", 18662 argLen: 1, 18663 asm: s390x.ACGEBRA, 18664 reg: regInfo{ 18665 inputs: []inputInfo{ 18666 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18667 }, 18668 outputs: []outputInfo{ 18669 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18670 }, 18671 }, 18672 }, 18673 { 18674 name: "CEFBRA", 18675 argLen: 1, 18676 asm: s390x.ACEFBRA, 18677 reg: regInfo{ 18678 inputs: []inputInfo{ 18679 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18680 }, 18681 outputs: []outputInfo{ 18682 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18683 }, 18684 }, 18685 }, 18686 { 18687 name: "CDFBRA", 18688 argLen: 1, 18689 asm: s390x.ACDFBRA, 18690 reg: regInfo{ 18691 inputs: []inputInfo{ 18692 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18693 }, 18694 outputs: []outputInfo{ 18695 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18696 }, 18697 }, 18698 }, 18699 { 18700 name: "CEGBRA", 18701 argLen: 1, 18702 asm: s390x.ACEGBRA, 18703 reg: regInfo{ 18704 inputs: []inputInfo{ 18705 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18706 }, 18707 outputs: []outputInfo{ 18708 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18709 }, 18710 }, 18711 }, 18712 { 18713 name: "CDGBRA", 18714 argLen: 1, 18715 asm: s390x.ACDGBRA, 18716 reg: regInfo{ 18717 inputs: []inputInfo{ 18718 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18719 }, 18720 outputs: []outputInfo{ 18721 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18722 }, 18723 }, 18724 }, 18725 { 18726 name: "LEDBR", 18727 argLen: 1, 18728 asm: s390x.ALEDBR, 18729 reg: regInfo{ 18730 inputs: []inputInfo{ 18731 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18732 }, 18733 outputs: []outputInfo{ 18734 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18735 }, 18736 }, 18737 }, 18738 { 18739 name: "LDEBR", 18740 argLen: 1, 18741 asm: s390x.ALDEBR, 18742 reg: regInfo{ 18743 inputs: []inputInfo{ 18744 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18745 }, 18746 outputs: []outputInfo{ 18747 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18748 }, 18749 }, 18750 }, 18751 { 18752 name: "MOVDaddr", 18753 auxType: auxSymOff, 18754 argLen: 1, 18755 rematerializeable: true, 18756 clobberFlags: true, 18757 reg: regInfo{ 18758 inputs: []inputInfo{ 18759 {0, 4295000064}, // SP SB 18760 }, 18761 outputs: []outputInfo{ 18762 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18763 }, 18764 }, 18765 }, 18766 { 18767 name: "MOVDaddridx", 18768 auxType: auxSymOff, 18769 argLen: 2, 18770 clobberFlags: true, 18771 reg: regInfo{ 18772 inputs: []inputInfo{ 18773 {0, 4295000064}, // SP SB 18774 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18775 }, 18776 outputs: []outputInfo{ 18777 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18778 }, 18779 }, 18780 }, 18781 { 18782 name: "MOVBZload", 18783 auxType: auxSymOff, 18784 argLen: 2, 18785 clobberFlags: true, 18786 faultOnNilArg0: true, 18787 asm: s390x.AMOVBZ, 18788 reg: regInfo{ 18789 inputs: []inputInfo{ 18790 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18791 }, 18792 outputs: []outputInfo{ 18793 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18794 }, 18795 }, 18796 }, 18797 { 18798 name: "MOVBload", 18799 auxType: auxSymOff, 18800 argLen: 2, 18801 clobberFlags: true, 18802 faultOnNilArg0: true, 18803 asm: s390x.AMOVB, 18804 reg: regInfo{ 18805 inputs: []inputInfo{ 18806 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18807 }, 18808 outputs: []outputInfo{ 18809 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18810 }, 18811 }, 18812 }, 18813 { 18814 name: "MOVHZload", 18815 auxType: auxSymOff, 18816 argLen: 2, 18817 clobberFlags: true, 18818 faultOnNilArg0: true, 18819 asm: s390x.AMOVHZ, 18820 reg: regInfo{ 18821 inputs: []inputInfo{ 18822 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18823 }, 18824 outputs: []outputInfo{ 18825 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18826 }, 18827 }, 18828 }, 18829 { 18830 name: "MOVHload", 18831 auxType: auxSymOff, 18832 argLen: 2, 18833 clobberFlags: true, 18834 faultOnNilArg0: true, 18835 asm: s390x.AMOVH, 18836 reg: regInfo{ 18837 inputs: []inputInfo{ 18838 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18839 }, 18840 outputs: []outputInfo{ 18841 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18842 }, 18843 }, 18844 }, 18845 { 18846 name: "MOVWZload", 18847 auxType: auxSymOff, 18848 argLen: 2, 18849 clobberFlags: true, 18850 faultOnNilArg0: true, 18851 asm: s390x.AMOVWZ, 18852 reg: regInfo{ 18853 inputs: []inputInfo{ 18854 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18855 }, 18856 outputs: []outputInfo{ 18857 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18858 }, 18859 }, 18860 }, 18861 { 18862 name: "MOVWload", 18863 auxType: auxSymOff, 18864 argLen: 2, 18865 clobberFlags: true, 18866 faultOnNilArg0: true, 18867 asm: s390x.AMOVW, 18868 reg: regInfo{ 18869 inputs: []inputInfo{ 18870 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18871 }, 18872 outputs: []outputInfo{ 18873 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18874 }, 18875 }, 18876 }, 18877 { 18878 name: "MOVDload", 18879 auxType: auxSymOff, 18880 argLen: 2, 18881 clobberFlags: true, 18882 faultOnNilArg0: true, 18883 asm: s390x.AMOVD, 18884 reg: regInfo{ 18885 inputs: []inputInfo{ 18886 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18887 }, 18888 outputs: []outputInfo{ 18889 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18890 }, 18891 }, 18892 }, 18893 { 18894 name: "MOVWBR", 18895 argLen: 1, 18896 asm: s390x.AMOVWBR, 18897 reg: regInfo{ 18898 inputs: []inputInfo{ 18899 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18900 }, 18901 outputs: []outputInfo{ 18902 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18903 }, 18904 }, 18905 }, 18906 { 18907 name: "MOVDBR", 18908 argLen: 1, 18909 asm: s390x.AMOVDBR, 18910 reg: regInfo{ 18911 inputs: []inputInfo{ 18912 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18913 }, 18914 outputs: []outputInfo{ 18915 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18916 }, 18917 }, 18918 }, 18919 { 18920 name: "MOVHBRload", 18921 auxType: auxSymOff, 18922 argLen: 2, 18923 clobberFlags: true, 18924 faultOnNilArg0: true, 18925 asm: s390x.AMOVHBR, 18926 reg: regInfo{ 18927 inputs: []inputInfo{ 18928 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18929 }, 18930 outputs: []outputInfo{ 18931 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18932 }, 18933 }, 18934 }, 18935 { 18936 name: "MOVWBRload", 18937 auxType: auxSymOff, 18938 argLen: 2, 18939 clobberFlags: true, 18940 faultOnNilArg0: true, 18941 asm: s390x.AMOVWBR, 18942 reg: regInfo{ 18943 inputs: []inputInfo{ 18944 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18945 }, 18946 outputs: []outputInfo{ 18947 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18948 }, 18949 }, 18950 }, 18951 { 18952 name: "MOVDBRload", 18953 auxType: auxSymOff, 18954 argLen: 2, 18955 clobberFlags: true, 18956 faultOnNilArg0: true, 18957 asm: s390x.AMOVDBR, 18958 reg: regInfo{ 18959 inputs: []inputInfo{ 18960 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18961 }, 18962 outputs: []outputInfo{ 18963 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18964 }, 18965 }, 18966 }, 18967 { 18968 name: "MOVBstore", 18969 auxType: auxSymOff, 18970 argLen: 3, 18971 clobberFlags: true, 18972 faultOnNilArg0: true, 18973 asm: s390x.AMOVB, 18974 reg: regInfo{ 18975 inputs: []inputInfo{ 18976 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18977 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18978 }, 18979 }, 18980 }, 18981 { 18982 name: "MOVHstore", 18983 auxType: auxSymOff, 18984 argLen: 3, 18985 clobberFlags: true, 18986 faultOnNilArg0: true, 18987 asm: s390x.AMOVH, 18988 reg: regInfo{ 18989 inputs: []inputInfo{ 18990 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18991 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18992 }, 18993 }, 18994 }, 18995 { 18996 name: "MOVWstore", 18997 auxType: auxSymOff, 18998 argLen: 3, 18999 clobberFlags: true, 19000 faultOnNilArg0: true, 19001 asm: s390x.AMOVW, 19002 reg: regInfo{ 19003 inputs: []inputInfo{ 19004 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19005 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19006 }, 19007 }, 19008 }, 19009 { 19010 name: "MOVDstore", 19011 auxType: auxSymOff, 19012 argLen: 3, 19013 clobberFlags: true, 19014 faultOnNilArg0: true, 19015 asm: s390x.AMOVD, 19016 reg: regInfo{ 19017 inputs: []inputInfo{ 19018 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19019 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19020 }, 19021 }, 19022 }, 19023 { 19024 name: "MOVHBRstore", 19025 auxType: auxSymOff, 19026 argLen: 3, 19027 clobberFlags: true, 19028 faultOnNilArg0: true, 19029 asm: s390x.AMOVHBR, 19030 reg: regInfo{ 19031 inputs: []inputInfo{ 19032 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19033 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19034 }, 19035 }, 19036 }, 19037 { 19038 name: "MOVWBRstore", 19039 auxType: auxSymOff, 19040 argLen: 3, 19041 clobberFlags: true, 19042 faultOnNilArg0: true, 19043 asm: s390x.AMOVWBR, 19044 reg: regInfo{ 19045 inputs: []inputInfo{ 19046 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19047 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19048 }, 19049 }, 19050 }, 19051 { 19052 name: "MOVDBRstore", 19053 auxType: auxSymOff, 19054 argLen: 3, 19055 clobberFlags: true, 19056 faultOnNilArg0: true, 19057 asm: s390x.AMOVDBR, 19058 reg: regInfo{ 19059 inputs: []inputInfo{ 19060 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19061 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19062 }, 19063 }, 19064 }, 19065 { 19066 name: "MVC", 19067 auxType: auxSymValAndOff, 19068 argLen: 3, 19069 clobberFlags: true, 19070 faultOnNilArg0: true, 19071 faultOnNilArg1: true, 19072 asm: s390x.AMVC, 19073 reg: regInfo{ 19074 inputs: []inputInfo{ 19075 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19076 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19077 }, 19078 }, 19079 }, 19080 { 19081 name: "MOVBZloadidx", 19082 auxType: auxSymOff, 19083 argLen: 3, 19084 clobberFlags: true, 19085 asm: s390x.AMOVBZ, 19086 reg: regInfo{ 19087 inputs: []inputInfo{ 19088 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19089 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19090 }, 19091 outputs: []outputInfo{ 19092 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19093 }, 19094 }, 19095 }, 19096 { 19097 name: "MOVHZloadidx", 19098 auxType: auxSymOff, 19099 argLen: 3, 19100 clobberFlags: true, 19101 asm: s390x.AMOVHZ, 19102 reg: regInfo{ 19103 inputs: []inputInfo{ 19104 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19105 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19106 }, 19107 outputs: []outputInfo{ 19108 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19109 }, 19110 }, 19111 }, 19112 { 19113 name: "MOVWZloadidx", 19114 auxType: auxSymOff, 19115 argLen: 3, 19116 clobberFlags: true, 19117 asm: s390x.AMOVWZ, 19118 reg: regInfo{ 19119 inputs: []inputInfo{ 19120 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19121 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19122 }, 19123 outputs: []outputInfo{ 19124 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19125 }, 19126 }, 19127 }, 19128 { 19129 name: "MOVDloadidx", 19130 auxType: auxSymOff, 19131 argLen: 3, 19132 clobberFlags: true, 19133 asm: s390x.AMOVD, 19134 reg: regInfo{ 19135 inputs: []inputInfo{ 19136 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19137 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19138 }, 19139 outputs: []outputInfo{ 19140 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19141 }, 19142 }, 19143 }, 19144 { 19145 name: "MOVHBRloadidx", 19146 auxType: auxSymOff, 19147 argLen: 3, 19148 clobberFlags: true, 19149 asm: s390x.AMOVHBR, 19150 reg: regInfo{ 19151 inputs: []inputInfo{ 19152 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19153 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19154 }, 19155 outputs: []outputInfo{ 19156 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19157 }, 19158 }, 19159 }, 19160 { 19161 name: "MOVWBRloadidx", 19162 auxType: auxSymOff, 19163 argLen: 3, 19164 clobberFlags: true, 19165 asm: s390x.AMOVWBR, 19166 reg: regInfo{ 19167 inputs: []inputInfo{ 19168 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19169 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19170 }, 19171 outputs: []outputInfo{ 19172 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19173 }, 19174 }, 19175 }, 19176 { 19177 name: "MOVDBRloadidx", 19178 auxType: auxSymOff, 19179 argLen: 3, 19180 clobberFlags: true, 19181 asm: s390x.AMOVDBR, 19182 reg: regInfo{ 19183 inputs: []inputInfo{ 19184 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19185 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19186 }, 19187 outputs: []outputInfo{ 19188 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19189 }, 19190 }, 19191 }, 19192 { 19193 name: "MOVBstoreidx", 19194 auxType: auxSymOff, 19195 argLen: 4, 19196 clobberFlags: true, 19197 asm: s390x.AMOVB, 19198 reg: regInfo{ 19199 inputs: []inputInfo{ 19200 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19201 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19202 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19203 }, 19204 }, 19205 }, 19206 { 19207 name: "MOVHstoreidx", 19208 auxType: auxSymOff, 19209 argLen: 4, 19210 clobberFlags: true, 19211 asm: s390x.AMOVH, 19212 reg: regInfo{ 19213 inputs: []inputInfo{ 19214 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19215 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19216 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19217 }, 19218 }, 19219 }, 19220 { 19221 name: "MOVWstoreidx", 19222 auxType: auxSymOff, 19223 argLen: 4, 19224 clobberFlags: true, 19225 asm: s390x.AMOVW, 19226 reg: regInfo{ 19227 inputs: []inputInfo{ 19228 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19229 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19230 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19231 }, 19232 }, 19233 }, 19234 { 19235 name: "MOVDstoreidx", 19236 auxType: auxSymOff, 19237 argLen: 4, 19238 clobberFlags: true, 19239 asm: s390x.AMOVD, 19240 reg: regInfo{ 19241 inputs: []inputInfo{ 19242 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19243 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19244 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19245 }, 19246 }, 19247 }, 19248 { 19249 name: "MOVHBRstoreidx", 19250 auxType: auxSymOff, 19251 argLen: 4, 19252 clobberFlags: true, 19253 asm: s390x.AMOVHBR, 19254 reg: regInfo{ 19255 inputs: []inputInfo{ 19256 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19257 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19258 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19259 }, 19260 }, 19261 }, 19262 { 19263 name: "MOVWBRstoreidx", 19264 auxType: auxSymOff, 19265 argLen: 4, 19266 clobberFlags: true, 19267 asm: s390x.AMOVWBR, 19268 reg: regInfo{ 19269 inputs: []inputInfo{ 19270 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19271 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19272 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19273 }, 19274 }, 19275 }, 19276 { 19277 name: "MOVDBRstoreidx", 19278 auxType: auxSymOff, 19279 argLen: 4, 19280 clobberFlags: true, 19281 asm: s390x.AMOVDBR, 19282 reg: regInfo{ 19283 inputs: []inputInfo{ 19284 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19285 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19286 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19287 }, 19288 }, 19289 }, 19290 { 19291 name: "MOVBstoreconst", 19292 auxType: auxSymValAndOff, 19293 argLen: 2, 19294 clobberFlags: true, 19295 faultOnNilArg0: true, 19296 asm: s390x.AMOVB, 19297 reg: regInfo{ 19298 inputs: []inputInfo{ 19299 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19300 }, 19301 }, 19302 }, 19303 { 19304 name: "MOVHstoreconst", 19305 auxType: auxSymValAndOff, 19306 argLen: 2, 19307 clobberFlags: true, 19308 faultOnNilArg0: true, 19309 asm: s390x.AMOVH, 19310 reg: regInfo{ 19311 inputs: []inputInfo{ 19312 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19313 }, 19314 }, 19315 }, 19316 { 19317 name: "MOVWstoreconst", 19318 auxType: auxSymValAndOff, 19319 argLen: 2, 19320 clobberFlags: true, 19321 faultOnNilArg0: true, 19322 asm: s390x.AMOVW, 19323 reg: regInfo{ 19324 inputs: []inputInfo{ 19325 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19326 }, 19327 }, 19328 }, 19329 { 19330 name: "MOVDstoreconst", 19331 auxType: auxSymValAndOff, 19332 argLen: 2, 19333 clobberFlags: true, 19334 faultOnNilArg0: true, 19335 asm: s390x.AMOVD, 19336 reg: regInfo{ 19337 inputs: []inputInfo{ 19338 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19339 }, 19340 }, 19341 }, 19342 { 19343 name: "CLEAR", 19344 auxType: auxSymValAndOff, 19345 argLen: 2, 19346 clobberFlags: true, 19347 faultOnNilArg0: true, 19348 asm: s390x.ACLEAR, 19349 reg: regInfo{ 19350 inputs: []inputInfo{ 19351 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19352 }, 19353 }, 19354 }, 19355 { 19356 name: "CALLstatic", 19357 auxType: auxSymOff, 19358 argLen: 1, 19359 clobberFlags: true, 19360 call: true, 19361 reg: regInfo{ 19362 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19363 }, 19364 }, 19365 { 19366 name: "CALLclosure", 19367 auxType: auxInt64, 19368 argLen: 3, 19369 clobberFlags: true, 19370 call: true, 19371 reg: regInfo{ 19372 inputs: []inputInfo{ 19373 {1, 4096}, // R12 19374 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19375 }, 19376 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19377 }, 19378 }, 19379 { 19380 name: "CALLdefer", 19381 auxType: auxInt64, 19382 argLen: 1, 19383 clobberFlags: true, 19384 call: true, 19385 reg: regInfo{ 19386 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19387 }, 19388 }, 19389 { 19390 name: "CALLgo", 19391 auxType: auxInt64, 19392 argLen: 1, 19393 clobberFlags: true, 19394 call: true, 19395 reg: regInfo{ 19396 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19397 }, 19398 }, 19399 { 19400 name: "CALLinter", 19401 auxType: auxInt64, 19402 argLen: 2, 19403 clobberFlags: true, 19404 call: true, 19405 reg: regInfo{ 19406 inputs: []inputInfo{ 19407 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19408 }, 19409 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19410 }, 19411 }, 19412 { 19413 name: "InvertFlags", 19414 argLen: 1, 19415 reg: regInfo{}, 19416 }, 19417 { 19418 name: "LoweredGetG", 19419 argLen: 1, 19420 reg: regInfo{ 19421 outputs: []outputInfo{ 19422 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19423 }, 19424 }, 19425 }, 19426 { 19427 name: "LoweredGetClosurePtr", 19428 argLen: 0, 19429 reg: regInfo{ 19430 outputs: []outputInfo{ 19431 {0, 4096}, // R12 19432 }, 19433 }, 19434 }, 19435 { 19436 name: "LoweredNilCheck", 19437 argLen: 2, 19438 clobberFlags: true, 19439 nilCheck: true, 19440 faultOnNilArg0: true, 19441 reg: regInfo{ 19442 inputs: []inputInfo{ 19443 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19444 }, 19445 }, 19446 }, 19447 { 19448 name: "MOVDconvert", 19449 argLen: 2, 19450 asm: s390x.AMOVD, 19451 reg: regInfo{ 19452 inputs: []inputInfo{ 19453 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19454 }, 19455 outputs: []outputInfo{ 19456 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19457 }, 19458 }, 19459 }, 19460 { 19461 name: "FlagEQ", 19462 argLen: 0, 19463 reg: regInfo{}, 19464 }, 19465 { 19466 name: "FlagLT", 19467 argLen: 0, 19468 reg: regInfo{}, 19469 }, 19470 { 19471 name: "FlagGT", 19472 argLen: 0, 19473 reg: regInfo{}, 19474 }, 19475 { 19476 name: "MOVWZatomicload", 19477 auxType: auxSymOff, 19478 argLen: 2, 19479 faultOnNilArg0: true, 19480 asm: s390x.AMOVWZ, 19481 reg: regInfo{ 19482 inputs: []inputInfo{ 19483 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19484 }, 19485 outputs: []outputInfo{ 19486 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19487 }, 19488 }, 19489 }, 19490 { 19491 name: "MOVDatomicload", 19492 auxType: auxSymOff, 19493 argLen: 2, 19494 faultOnNilArg0: true, 19495 asm: s390x.AMOVD, 19496 reg: regInfo{ 19497 inputs: []inputInfo{ 19498 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19499 }, 19500 outputs: []outputInfo{ 19501 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19502 }, 19503 }, 19504 }, 19505 { 19506 name: "MOVWatomicstore", 19507 auxType: auxSymOff, 19508 argLen: 3, 19509 clobberFlags: true, 19510 faultOnNilArg0: true, 19511 asm: s390x.AMOVW, 19512 reg: regInfo{ 19513 inputs: []inputInfo{ 19514 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19515 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19516 }, 19517 }, 19518 }, 19519 { 19520 name: "MOVDatomicstore", 19521 auxType: auxSymOff, 19522 argLen: 3, 19523 clobberFlags: true, 19524 faultOnNilArg0: true, 19525 asm: s390x.AMOVD, 19526 reg: regInfo{ 19527 inputs: []inputInfo{ 19528 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19529 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19530 }, 19531 }, 19532 }, 19533 { 19534 name: "LAA", 19535 auxType: auxSymOff, 19536 argLen: 3, 19537 faultOnNilArg0: true, 19538 asm: s390x.ALAA, 19539 reg: regInfo{ 19540 inputs: []inputInfo{ 19541 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19542 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19543 }, 19544 outputs: []outputInfo{ 19545 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19546 }, 19547 }, 19548 }, 19549 { 19550 name: "LAAG", 19551 auxType: auxSymOff, 19552 argLen: 3, 19553 faultOnNilArg0: true, 19554 asm: s390x.ALAAG, 19555 reg: regInfo{ 19556 inputs: []inputInfo{ 19557 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19558 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19559 }, 19560 outputs: []outputInfo{ 19561 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19562 }, 19563 }, 19564 }, 19565 { 19566 name: "AddTupleFirst32", 19567 argLen: 2, 19568 reg: regInfo{}, 19569 }, 19570 { 19571 name: "AddTupleFirst64", 19572 argLen: 2, 19573 reg: regInfo{}, 19574 }, 19575 { 19576 name: "LoweredAtomicCas32", 19577 auxType: auxSymOff, 19578 argLen: 4, 19579 clobberFlags: true, 19580 faultOnNilArg0: true, 19581 asm: s390x.ACS, 19582 reg: regInfo{ 19583 inputs: []inputInfo{ 19584 {1, 1}, // R0 19585 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19586 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19587 }, 19588 clobbers: 1, // R0 19589 outputs: []outputInfo{ 19590 {1, 0}, 19591 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19592 }, 19593 }, 19594 }, 19595 { 19596 name: "LoweredAtomicCas64", 19597 auxType: auxSymOff, 19598 argLen: 4, 19599 clobberFlags: true, 19600 faultOnNilArg0: true, 19601 asm: s390x.ACSG, 19602 reg: regInfo{ 19603 inputs: []inputInfo{ 19604 {1, 1}, // R0 19605 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19606 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19607 }, 19608 clobbers: 1, // R0 19609 outputs: []outputInfo{ 19610 {1, 0}, 19611 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19612 }, 19613 }, 19614 }, 19615 { 19616 name: "LoweredAtomicExchange32", 19617 auxType: auxSymOff, 19618 argLen: 3, 19619 clobberFlags: true, 19620 faultOnNilArg0: true, 19621 asm: s390x.ACS, 19622 reg: regInfo{ 19623 inputs: []inputInfo{ 19624 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19625 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19626 }, 19627 outputs: []outputInfo{ 19628 {1, 0}, 19629 {0, 1}, // R0 19630 }, 19631 }, 19632 }, 19633 { 19634 name: "LoweredAtomicExchange64", 19635 auxType: auxSymOff, 19636 argLen: 3, 19637 clobberFlags: true, 19638 faultOnNilArg0: true, 19639 asm: s390x.ACSG, 19640 reg: regInfo{ 19641 inputs: []inputInfo{ 19642 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19643 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19644 }, 19645 outputs: []outputInfo{ 19646 {1, 0}, 19647 {0, 1}, // R0 19648 }, 19649 }, 19650 }, 19651 { 19652 name: "FLOGR", 19653 argLen: 1, 19654 clobberFlags: true, 19655 asm: s390x.AFLOGR, 19656 reg: regInfo{ 19657 inputs: []inputInfo{ 19658 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19659 }, 19660 clobbers: 2, // R1 19661 outputs: []outputInfo{ 19662 {0, 1}, // R0 19663 }, 19664 }, 19665 }, 19666 { 19667 name: "STMG2", 19668 auxType: auxSymOff, 19669 argLen: 4, 19670 faultOnNilArg0: true, 19671 asm: s390x.ASTMG, 19672 reg: regInfo{ 19673 inputs: []inputInfo{ 19674 {1, 2}, // R1 19675 {2, 4}, // R2 19676 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19677 }, 19678 }, 19679 }, 19680 { 19681 name: "STMG3", 19682 auxType: auxSymOff, 19683 argLen: 5, 19684 faultOnNilArg0: true, 19685 asm: s390x.ASTMG, 19686 reg: regInfo{ 19687 inputs: []inputInfo{ 19688 {1, 2}, // R1 19689 {2, 4}, // R2 19690 {3, 8}, // R3 19691 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19692 }, 19693 }, 19694 }, 19695 { 19696 name: "STMG4", 19697 auxType: auxSymOff, 19698 argLen: 6, 19699 faultOnNilArg0: true, 19700 asm: s390x.ASTMG, 19701 reg: regInfo{ 19702 inputs: []inputInfo{ 19703 {1, 2}, // R1 19704 {2, 4}, // R2 19705 {3, 8}, // R3 19706 {4, 16}, // R4 19707 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19708 }, 19709 }, 19710 }, 19711 { 19712 name: "STM2", 19713 auxType: auxSymOff, 19714 argLen: 4, 19715 faultOnNilArg0: true, 19716 asm: s390x.ASTMY, 19717 reg: regInfo{ 19718 inputs: []inputInfo{ 19719 {1, 2}, // R1 19720 {2, 4}, // R2 19721 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19722 }, 19723 }, 19724 }, 19725 { 19726 name: "STM3", 19727 auxType: auxSymOff, 19728 argLen: 5, 19729 faultOnNilArg0: true, 19730 asm: s390x.ASTMY, 19731 reg: regInfo{ 19732 inputs: []inputInfo{ 19733 {1, 2}, // R1 19734 {2, 4}, // R2 19735 {3, 8}, // R3 19736 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19737 }, 19738 }, 19739 }, 19740 { 19741 name: "STM4", 19742 auxType: auxSymOff, 19743 argLen: 6, 19744 faultOnNilArg0: true, 19745 asm: s390x.ASTMY, 19746 reg: regInfo{ 19747 inputs: []inputInfo{ 19748 {1, 2}, // R1 19749 {2, 4}, // R2 19750 {3, 8}, // R3 19751 {4, 16}, // R4 19752 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19753 }, 19754 }, 19755 }, 19756 { 19757 name: "LoweredMove", 19758 auxType: auxInt64, 19759 argLen: 4, 19760 clobberFlags: true, 19761 faultOnNilArg0: true, 19762 faultOnNilArg1: true, 19763 reg: regInfo{ 19764 inputs: []inputInfo{ 19765 {0, 2}, // R1 19766 {1, 4}, // R2 19767 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19768 }, 19769 clobbers: 6, // R1 R2 19770 }, 19771 }, 19772 { 19773 name: "LoweredZero", 19774 auxType: auxInt64, 19775 argLen: 3, 19776 clobberFlags: true, 19777 faultOnNilArg0: true, 19778 reg: regInfo{ 19779 inputs: []inputInfo{ 19780 {0, 2}, // R1 19781 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19782 }, 19783 clobbers: 2, // R1 19784 }, 19785 }, 19786 19787 { 19788 name: "Add8", 19789 argLen: 2, 19790 commutative: true, 19791 generic: true, 19792 }, 19793 { 19794 name: "Add16", 19795 argLen: 2, 19796 commutative: true, 19797 generic: true, 19798 }, 19799 { 19800 name: "Add32", 19801 argLen: 2, 19802 commutative: true, 19803 generic: true, 19804 }, 19805 { 19806 name: "Add64", 19807 argLen: 2, 19808 commutative: true, 19809 generic: true, 19810 }, 19811 { 19812 name: "AddPtr", 19813 argLen: 2, 19814 generic: true, 19815 }, 19816 { 19817 name: "Add32F", 19818 argLen: 2, 19819 generic: true, 19820 }, 19821 { 19822 name: "Add64F", 19823 argLen: 2, 19824 generic: true, 19825 }, 19826 { 19827 name: "Sub8", 19828 argLen: 2, 19829 generic: true, 19830 }, 19831 { 19832 name: "Sub16", 19833 argLen: 2, 19834 generic: true, 19835 }, 19836 { 19837 name: "Sub32", 19838 argLen: 2, 19839 generic: true, 19840 }, 19841 { 19842 name: "Sub64", 19843 argLen: 2, 19844 generic: true, 19845 }, 19846 { 19847 name: "SubPtr", 19848 argLen: 2, 19849 generic: true, 19850 }, 19851 { 19852 name: "Sub32F", 19853 argLen: 2, 19854 generic: true, 19855 }, 19856 { 19857 name: "Sub64F", 19858 argLen: 2, 19859 generic: true, 19860 }, 19861 { 19862 name: "Mul8", 19863 argLen: 2, 19864 commutative: true, 19865 generic: true, 19866 }, 19867 { 19868 name: "Mul16", 19869 argLen: 2, 19870 commutative: true, 19871 generic: true, 19872 }, 19873 { 19874 name: "Mul32", 19875 argLen: 2, 19876 commutative: true, 19877 generic: true, 19878 }, 19879 { 19880 name: "Mul64", 19881 argLen: 2, 19882 commutative: true, 19883 generic: true, 19884 }, 19885 { 19886 name: "Mul32F", 19887 argLen: 2, 19888 generic: true, 19889 }, 19890 { 19891 name: "Mul64F", 19892 argLen: 2, 19893 generic: true, 19894 }, 19895 { 19896 name: "Div32F", 19897 argLen: 2, 19898 generic: true, 19899 }, 19900 { 19901 name: "Div64F", 19902 argLen: 2, 19903 generic: true, 19904 }, 19905 { 19906 name: "Hmul8", 19907 argLen: 2, 19908 generic: true, 19909 }, 19910 { 19911 name: "Hmul8u", 19912 argLen: 2, 19913 generic: true, 19914 }, 19915 { 19916 name: "Hmul16", 19917 argLen: 2, 19918 generic: true, 19919 }, 19920 { 19921 name: "Hmul16u", 19922 argLen: 2, 19923 generic: true, 19924 }, 19925 { 19926 name: "Hmul32", 19927 argLen: 2, 19928 generic: true, 19929 }, 19930 { 19931 name: "Hmul32u", 19932 argLen: 2, 19933 generic: true, 19934 }, 19935 { 19936 name: "Hmul64", 19937 argLen: 2, 19938 generic: true, 19939 }, 19940 { 19941 name: "Hmul64u", 19942 argLen: 2, 19943 generic: true, 19944 }, 19945 { 19946 name: "Mul32uhilo", 19947 argLen: 2, 19948 generic: true, 19949 }, 19950 { 19951 name: "Mul64uhilo", 19952 argLen: 2, 19953 generic: true, 19954 }, 19955 { 19956 name: "Avg64u", 19957 argLen: 2, 19958 generic: true, 19959 }, 19960 { 19961 name: "Div8", 19962 argLen: 2, 19963 generic: true, 19964 }, 19965 { 19966 name: "Div8u", 19967 argLen: 2, 19968 generic: true, 19969 }, 19970 { 19971 name: "Div16", 19972 argLen: 2, 19973 generic: true, 19974 }, 19975 { 19976 name: "Div16u", 19977 argLen: 2, 19978 generic: true, 19979 }, 19980 { 19981 name: "Div32", 19982 argLen: 2, 19983 generic: true, 19984 }, 19985 { 19986 name: "Div32u", 19987 argLen: 2, 19988 generic: true, 19989 }, 19990 { 19991 name: "Div64", 19992 argLen: 2, 19993 generic: true, 19994 }, 19995 { 19996 name: "Div64u", 19997 argLen: 2, 19998 generic: true, 19999 }, 20000 { 20001 name: "Div128u", 20002 argLen: 3, 20003 generic: true, 20004 }, 20005 { 20006 name: "Mod8", 20007 argLen: 2, 20008 generic: true, 20009 }, 20010 { 20011 name: "Mod8u", 20012 argLen: 2, 20013 generic: true, 20014 }, 20015 { 20016 name: "Mod16", 20017 argLen: 2, 20018 generic: true, 20019 }, 20020 { 20021 name: "Mod16u", 20022 argLen: 2, 20023 generic: true, 20024 }, 20025 { 20026 name: "Mod32", 20027 argLen: 2, 20028 generic: true, 20029 }, 20030 { 20031 name: "Mod32u", 20032 argLen: 2, 20033 generic: true, 20034 }, 20035 { 20036 name: "Mod64", 20037 argLen: 2, 20038 generic: true, 20039 }, 20040 { 20041 name: "Mod64u", 20042 argLen: 2, 20043 generic: true, 20044 }, 20045 { 20046 name: "And8", 20047 argLen: 2, 20048 commutative: true, 20049 generic: true, 20050 }, 20051 { 20052 name: "And16", 20053 argLen: 2, 20054 commutative: true, 20055 generic: true, 20056 }, 20057 { 20058 name: "And32", 20059 argLen: 2, 20060 commutative: true, 20061 generic: true, 20062 }, 20063 { 20064 name: "And64", 20065 argLen: 2, 20066 commutative: true, 20067 generic: true, 20068 }, 20069 { 20070 name: "Or8", 20071 argLen: 2, 20072 commutative: true, 20073 generic: true, 20074 }, 20075 { 20076 name: "Or16", 20077 argLen: 2, 20078 commutative: true, 20079 generic: true, 20080 }, 20081 { 20082 name: "Or32", 20083 argLen: 2, 20084 commutative: true, 20085 generic: true, 20086 }, 20087 { 20088 name: "Or64", 20089 argLen: 2, 20090 commutative: true, 20091 generic: true, 20092 }, 20093 { 20094 name: "Xor8", 20095 argLen: 2, 20096 commutative: true, 20097 generic: true, 20098 }, 20099 { 20100 name: "Xor16", 20101 argLen: 2, 20102 commutative: true, 20103 generic: true, 20104 }, 20105 { 20106 name: "Xor32", 20107 argLen: 2, 20108 commutative: true, 20109 generic: true, 20110 }, 20111 { 20112 name: "Xor64", 20113 argLen: 2, 20114 commutative: true, 20115 generic: true, 20116 }, 20117 { 20118 name: "Lsh8x8", 20119 argLen: 2, 20120 generic: true, 20121 }, 20122 { 20123 name: "Lsh8x16", 20124 argLen: 2, 20125 generic: true, 20126 }, 20127 { 20128 name: "Lsh8x32", 20129 argLen: 2, 20130 generic: true, 20131 }, 20132 { 20133 name: "Lsh8x64", 20134 argLen: 2, 20135 generic: true, 20136 }, 20137 { 20138 name: "Lsh16x8", 20139 argLen: 2, 20140 generic: true, 20141 }, 20142 { 20143 name: "Lsh16x16", 20144 argLen: 2, 20145 generic: true, 20146 }, 20147 { 20148 name: "Lsh16x32", 20149 argLen: 2, 20150 generic: true, 20151 }, 20152 { 20153 name: "Lsh16x64", 20154 argLen: 2, 20155 generic: true, 20156 }, 20157 { 20158 name: "Lsh32x8", 20159 argLen: 2, 20160 generic: true, 20161 }, 20162 { 20163 name: "Lsh32x16", 20164 argLen: 2, 20165 generic: true, 20166 }, 20167 { 20168 name: "Lsh32x32", 20169 argLen: 2, 20170 generic: true, 20171 }, 20172 { 20173 name: "Lsh32x64", 20174 argLen: 2, 20175 generic: true, 20176 }, 20177 { 20178 name: "Lsh64x8", 20179 argLen: 2, 20180 generic: true, 20181 }, 20182 { 20183 name: "Lsh64x16", 20184 argLen: 2, 20185 generic: true, 20186 }, 20187 { 20188 name: "Lsh64x32", 20189 argLen: 2, 20190 generic: true, 20191 }, 20192 { 20193 name: "Lsh64x64", 20194 argLen: 2, 20195 generic: true, 20196 }, 20197 { 20198 name: "Rsh8x8", 20199 argLen: 2, 20200 generic: true, 20201 }, 20202 { 20203 name: "Rsh8x16", 20204 argLen: 2, 20205 generic: true, 20206 }, 20207 { 20208 name: "Rsh8x32", 20209 argLen: 2, 20210 generic: true, 20211 }, 20212 { 20213 name: "Rsh8x64", 20214 argLen: 2, 20215 generic: true, 20216 }, 20217 { 20218 name: "Rsh16x8", 20219 argLen: 2, 20220 generic: true, 20221 }, 20222 { 20223 name: "Rsh16x16", 20224 argLen: 2, 20225 generic: true, 20226 }, 20227 { 20228 name: "Rsh16x32", 20229 argLen: 2, 20230 generic: true, 20231 }, 20232 { 20233 name: "Rsh16x64", 20234 argLen: 2, 20235 generic: true, 20236 }, 20237 { 20238 name: "Rsh32x8", 20239 argLen: 2, 20240 generic: true, 20241 }, 20242 { 20243 name: "Rsh32x16", 20244 argLen: 2, 20245 generic: true, 20246 }, 20247 { 20248 name: "Rsh32x32", 20249 argLen: 2, 20250 generic: true, 20251 }, 20252 { 20253 name: "Rsh32x64", 20254 argLen: 2, 20255 generic: true, 20256 }, 20257 { 20258 name: "Rsh64x8", 20259 argLen: 2, 20260 generic: true, 20261 }, 20262 { 20263 name: "Rsh64x16", 20264 argLen: 2, 20265 generic: true, 20266 }, 20267 { 20268 name: "Rsh64x32", 20269 argLen: 2, 20270 generic: true, 20271 }, 20272 { 20273 name: "Rsh64x64", 20274 argLen: 2, 20275 generic: true, 20276 }, 20277 { 20278 name: "Rsh8Ux8", 20279 argLen: 2, 20280 generic: true, 20281 }, 20282 { 20283 name: "Rsh8Ux16", 20284 argLen: 2, 20285 generic: true, 20286 }, 20287 { 20288 name: "Rsh8Ux32", 20289 argLen: 2, 20290 generic: true, 20291 }, 20292 { 20293 name: "Rsh8Ux64", 20294 argLen: 2, 20295 generic: true, 20296 }, 20297 { 20298 name: "Rsh16Ux8", 20299 argLen: 2, 20300 generic: true, 20301 }, 20302 { 20303 name: "Rsh16Ux16", 20304 argLen: 2, 20305 generic: true, 20306 }, 20307 { 20308 name: "Rsh16Ux32", 20309 argLen: 2, 20310 generic: true, 20311 }, 20312 { 20313 name: "Rsh16Ux64", 20314 argLen: 2, 20315 generic: true, 20316 }, 20317 { 20318 name: "Rsh32Ux8", 20319 argLen: 2, 20320 generic: true, 20321 }, 20322 { 20323 name: "Rsh32Ux16", 20324 argLen: 2, 20325 generic: true, 20326 }, 20327 { 20328 name: "Rsh32Ux32", 20329 argLen: 2, 20330 generic: true, 20331 }, 20332 { 20333 name: "Rsh32Ux64", 20334 argLen: 2, 20335 generic: true, 20336 }, 20337 { 20338 name: "Rsh64Ux8", 20339 argLen: 2, 20340 generic: true, 20341 }, 20342 { 20343 name: "Rsh64Ux16", 20344 argLen: 2, 20345 generic: true, 20346 }, 20347 { 20348 name: "Rsh64Ux32", 20349 argLen: 2, 20350 generic: true, 20351 }, 20352 { 20353 name: "Rsh64Ux64", 20354 argLen: 2, 20355 generic: true, 20356 }, 20357 { 20358 name: "Eq8", 20359 argLen: 2, 20360 commutative: true, 20361 generic: true, 20362 }, 20363 { 20364 name: "Eq16", 20365 argLen: 2, 20366 commutative: true, 20367 generic: true, 20368 }, 20369 { 20370 name: "Eq32", 20371 argLen: 2, 20372 commutative: true, 20373 generic: true, 20374 }, 20375 { 20376 name: "Eq64", 20377 argLen: 2, 20378 commutative: true, 20379 generic: true, 20380 }, 20381 { 20382 name: "EqPtr", 20383 argLen: 2, 20384 commutative: true, 20385 generic: true, 20386 }, 20387 { 20388 name: "EqInter", 20389 argLen: 2, 20390 generic: true, 20391 }, 20392 { 20393 name: "EqSlice", 20394 argLen: 2, 20395 generic: true, 20396 }, 20397 { 20398 name: "Eq32F", 20399 argLen: 2, 20400 generic: true, 20401 }, 20402 { 20403 name: "Eq64F", 20404 argLen: 2, 20405 generic: true, 20406 }, 20407 { 20408 name: "Neq8", 20409 argLen: 2, 20410 commutative: true, 20411 generic: true, 20412 }, 20413 { 20414 name: "Neq16", 20415 argLen: 2, 20416 commutative: true, 20417 generic: true, 20418 }, 20419 { 20420 name: "Neq32", 20421 argLen: 2, 20422 commutative: true, 20423 generic: true, 20424 }, 20425 { 20426 name: "Neq64", 20427 argLen: 2, 20428 commutative: true, 20429 generic: true, 20430 }, 20431 { 20432 name: "NeqPtr", 20433 argLen: 2, 20434 commutative: true, 20435 generic: true, 20436 }, 20437 { 20438 name: "NeqInter", 20439 argLen: 2, 20440 generic: true, 20441 }, 20442 { 20443 name: "NeqSlice", 20444 argLen: 2, 20445 generic: true, 20446 }, 20447 { 20448 name: "Neq32F", 20449 argLen: 2, 20450 generic: true, 20451 }, 20452 { 20453 name: "Neq64F", 20454 argLen: 2, 20455 generic: true, 20456 }, 20457 { 20458 name: "Less8", 20459 argLen: 2, 20460 generic: true, 20461 }, 20462 { 20463 name: "Less8U", 20464 argLen: 2, 20465 generic: true, 20466 }, 20467 { 20468 name: "Less16", 20469 argLen: 2, 20470 generic: true, 20471 }, 20472 { 20473 name: "Less16U", 20474 argLen: 2, 20475 generic: true, 20476 }, 20477 { 20478 name: "Less32", 20479 argLen: 2, 20480 generic: true, 20481 }, 20482 { 20483 name: "Less32U", 20484 argLen: 2, 20485 generic: true, 20486 }, 20487 { 20488 name: "Less64", 20489 argLen: 2, 20490 generic: true, 20491 }, 20492 { 20493 name: "Less64U", 20494 argLen: 2, 20495 generic: true, 20496 }, 20497 { 20498 name: "Less32F", 20499 argLen: 2, 20500 generic: true, 20501 }, 20502 { 20503 name: "Less64F", 20504 argLen: 2, 20505 generic: true, 20506 }, 20507 { 20508 name: "Leq8", 20509 argLen: 2, 20510 generic: true, 20511 }, 20512 { 20513 name: "Leq8U", 20514 argLen: 2, 20515 generic: true, 20516 }, 20517 { 20518 name: "Leq16", 20519 argLen: 2, 20520 generic: true, 20521 }, 20522 { 20523 name: "Leq16U", 20524 argLen: 2, 20525 generic: true, 20526 }, 20527 { 20528 name: "Leq32", 20529 argLen: 2, 20530 generic: true, 20531 }, 20532 { 20533 name: "Leq32U", 20534 argLen: 2, 20535 generic: true, 20536 }, 20537 { 20538 name: "Leq64", 20539 argLen: 2, 20540 generic: true, 20541 }, 20542 { 20543 name: "Leq64U", 20544 argLen: 2, 20545 generic: true, 20546 }, 20547 { 20548 name: "Leq32F", 20549 argLen: 2, 20550 generic: true, 20551 }, 20552 { 20553 name: "Leq64F", 20554 argLen: 2, 20555 generic: true, 20556 }, 20557 { 20558 name: "Greater8", 20559 argLen: 2, 20560 generic: true, 20561 }, 20562 { 20563 name: "Greater8U", 20564 argLen: 2, 20565 generic: true, 20566 }, 20567 { 20568 name: "Greater16", 20569 argLen: 2, 20570 generic: true, 20571 }, 20572 { 20573 name: "Greater16U", 20574 argLen: 2, 20575 generic: true, 20576 }, 20577 { 20578 name: "Greater32", 20579 argLen: 2, 20580 generic: true, 20581 }, 20582 { 20583 name: "Greater32U", 20584 argLen: 2, 20585 generic: true, 20586 }, 20587 { 20588 name: "Greater64", 20589 argLen: 2, 20590 generic: true, 20591 }, 20592 { 20593 name: "Greater64U", 20594 argLen: 2, 20595 generic: true, 20596 }, 20597 { 20598 name: "Greater32F", 20599 argLen: 2, 20600 generic: true, 20601 }, 20602 { 20603 name: "Greater64F", 20604 argLen: 2, 20605 generic: true, 20606 }, 20607 { 20608 name: "Geq8", 20609 argLen: 2, 20610 generic: true, 20611 }, 20612 { 20613 name: "Geq8U", 20614 argLen: 2, 20615 generic: true, 20616 }, 20617 { 20618 name: "Geq16", 20619 argLen: 2, 20620 generic: true, 20621 }, 20622 { 20623 name: "Geq16U", 20624 argLen: 2, 20625 generic: true, 20626 }, 20627 { 20628 name: "Geq32", 20629 argLen: 2, 20630 generic: true, 20631 }, 20632 { 20633 name: "Geq32U", 20634 argLen: 2, 20635 generic: true, 20636 }, 20637 { 20638 name: "Geq64", 20639 argLen: 2, 20640 generic: true, 20641 }, 20642 { 20643 name: "Geq64U", 20644 argLen: 2, 20645 generic: true, 20646 }, 20647 { 20648 name: "Geq32F", 20649 argLen: 2, 20650 generic: true, 20651 }, 20652 { 20653 name: "Geq64F", 20654 argLen: 2, 20655 generic: true, 20656 }, 20657 { 20658 name: "AndB", 20659 argLen: 2, 20660 generic: true, 20661 }, 20662 { 20663 name: "OrB", 20664 argLen: 2, 20665 generic: true, 20666 }, 20667 { 20668 name: "EqB", 20669 argLen: 2, 20670 generic: true, 20671 }, 20672 { 20673 name: "NeqB", 20674 argLen: 2, 20675 generic: true, 20676 }, 20677 { 20678 name: "Not", 20679 argLen: 1, 20680 generic: true, 20681 }, 20682 { 20683 name: "Neg8", 20684 argLen: 1, 20685 generic: true, 20686 }, 20687 { 20688 name: "Neg16", 20689 argLen: 1, 20690 generic: true, 20691 }, 20692 { 20693 name: "Neg32", 20694 argLen: 1, 20695 generic: true, 20696 }, 20697 { 20698 name: "Neg64", 20699 argLen: 1, 20700 generic: true, 20701 }, 20702 { 20703 name: "Neg32F", 20704 argLen: 1, 20705 generic: true, 20706 }, 20707 { 20708 name: "Neg64F", 20709 argLen: 1, 20710 generic: true, 20711 }, 20712 { 20713 name: "Com8", 20714 argLen: 1, 20715 generic: true, 20716 }, 20717 { 20718 name: "Com16", 20719 argLen: 1, 20720 generic: true, 20721 }, 20722 { 20723 name: "Com32", 20724 argLen: 1, 20725 generic: true, 20726 }, 20727 { 20728 name: "Com64", 20729 argLen: 1, 20730 generic: true, 20731 }, 20732 { 20733 name: "Ctz32", 20734 argLen: 1, 20735 generic: true, 20736 }, 20737 { 20738 name: "Ctz64", 20739 argLen: 1, 20740 generic: true, 20741 }, 20742 { 20743 name: "Bswap32", 20744 argLen: 1, 20745 generic: true, 20746 }, 20747 { 20748 name: "Bswap64", 20749 argLen: 1, 20750 generic: true, 20751 }, 20752 { 20753 name: "Sqrt", 20754 argLen: 1, 20755 generic: true, 20756 }, 20757 { 20758 name: "Phi", 20759 argLen: -1, 20760 generic: true, 20761 }, 20762 { 20763 name: "Copy", 20764 argLen: 1, 20765 generic: true, 20766 }, 20767 { 20768 name: "Convert", 20769 argLen: 2, 20770 generic: true, 20771 }, 20772 { 20773 name: "ConstBool", 20774 auxType: auxBool, 20775 argLen: 0, 20776 generic: true, 20777 }, 20778 { 20779 name: "ConstString", 20780 auxType: auxString, 20781 argLen: 0, 20782 generic: true, 20783 }, 20784 { 20785 name: "ConstNil", 20786 argLen: 0, 20787 generic: true, 20788 }, 20789 { 20790 name: "Const8", 20791 auxType: auxInt8, 20792 argLen: 0, 20793 generic: true, 20794 }, 20795 { 20796 name: "Const16", 20797 auxType: auxInt16, 20798 argLen: 0, 20799 generic: true, 20800 }, 20801 { 20802 name: "Const32", 20803 auxType: auxInt32, 20804 argLen: 0, 20805 generic: true, 20806 }, 20807 { 20808 name: "Const64", 20809 auxType: auxInt64, 20810 argLen: 0, 20811 generic: true, 20812 }, 20813 { 20814 name: "Const32F", 20815 auxType: auxFloat32, 20816 argLen: 0, 20817 generic: true, 20818 }, 20819 { 20820 name: "Const64F", 20821 auxType: auxFloat64, 20822 argLen: 0, 20823 generic: true, 20824 }, 20825 { 20826 name: "ConstInterface", 20827 argLen: 0, 20828 generic: true, 20829 }, 20830 { 20831 name: "ConstSlice", 20832 argLen: 0, 20833 generic: true, 20834 }, 20835 { 20836 name: "InitMem", 20837 argLen: 0, 20838 generic: true, 20839 }, 20840 { 20841 name: "Arg", 20842 auxType: auxSymOff, 20843 argLen: 0, 20844 generic: true, 20845 }, 20846 { 20847 name: "Addr", 20848 auxType: auxSym, 20849 argLen: 1, 20850 generic: true, 20851 }, 20852 { 20853 name: "SP", 20854 argLen: 0, 20855 generic: true, 20856 }, 20857 { 20858 name: "SB", 20859 argLen: 0, 20860 generic: true, 20861 }, 20862 { 20863 name: "Func", 20864 auxType: auxSym, 20865 argLen: 0, 20866 generic: true, 20867 }, 20868 { 20869 name: "Load", 20870 argLen: 2, 20871 generic: true, 20872 }, 20873 { 20874 name: "Store", 20875 auxType: auxInt64, 20876 argLen: 3, 20877 generic: true, 20878 }, 20879 { 20880 name: "Move", 20881 auxType: auxSizeAndAlign, 20882 argLen: 3, 20883 generic: true, 20884 }, 20885 { 20886 name: "Zero", 20887 auxType: auxSizeAndAlign, 20888 argLen: 2, 20889 generic: true, 20890 }, 20891 { 20892 name: "StoreWB", 20893 auxType: auxInt64, 20894 argLen: 3, 20895 generic: true, 20896 }, 20897 { 20898 name: "MoveWB", 20899 auxType: auxSymSizeAndAlign, 20900 argLen: 3, 20901 generic: true, 20902 }, 20903 { 20904 name: "MoveWBVolatile", 20905 auxType: auxSymSizeAndAlign, 20906 argLen: 3, 20907 generic: true, 20908 }, 20909 { 20910 name: "ZeroWB", 20911 auxType: auxSymSizeAndAlign, 20912 argLen: 2, 20913 generic: true, 20914 }, 20915 { 20916 name: "ClosureCall", 20917 auxType: auxInt64, 20918 argLen: 3, 20919 call: true, 20920 generic: true, 20921 }, 20922 { 20923 name: "StaticCall", 20924 auxType: auxSymOff, 20925 argLen: 1, 20926 call: true, 20927 generic: true, 20928 }, 20929 { 20930 name: "DeferCall", 20931 auxType: auxInt64, 20932 argLen: 1, 20933 call: true, 20934 generic: true, 20935 }, 20936 { 20937 name: "GoCall", 20938 auxType: auxInt64, 20939 argLen: 1, 20940 call: true, 20941 generic: true, 20942 }, 20943 { 20944 name: "InterCall", 20945 auxType: auxInt64, 20946 argLen: 2, 20947 call: true, 20948 generic: true, 20949 }, 20950 { 20951 name: "SignExt8to16", 20952 argLen: 1, 20953 generic: true, 20954 }, 20955 { 20956 name: "SignExt8to32", 20957 argLen: 1, 20958 generic: true, 20959 }, 20960 { 20961 name: "SignExt8to64", 20962 argLen: 1, 20963 generic: true, 20964 }, 20965 { 20966 name: "SignExt16to32", 20967 argLen: 1, 20968 generic: true, 20969 }, 20970 { 20971 name: "SignExt16to64", 20972 argLen: 1, 20973 generic: true, 20974 }, 20975 { 20976 name: "SignExt32to64", 20977 argLen: 1, 20978 generic: true, 20979 }, 20980 { 20981 name: "ZeroExt8to16", 20982 argLen: 1, 20983 generic: true, 20984 }, 20985 { 20986 name: "ZeroExt8to32", 20987 argLen: 1, 20988 generic: true, 20989 }, 20990 { 20991 name: "ZeroExt8to64", 20992 argLen: 1, 20993 generic: true, 20994 }, 20995 { 20996 name: "ZeroExt16to32", 20997 argLen: 1, 20998 generic: true, 20999 }, 21000 { 21001 name: "ZeroExt16to64", 21002 argLen: 1, 21003 generic: true, 21004 }, 21005 { 21006 name: "ZeroExt32to64", 21007 argLen: 1, 21008 generic: true, 21009 }, 21010 { 21011 name: "Trunc16to8", 21012 argLen: 1, 21013 generic: true, 21014 }, 21015 { 21016 name: "Trunc32to8", 21017 argLen: 1, 21018 generic: true, 21019 }, 21020 { 21021 name: "Trunc32to16", 21022 argLen: 1, 21023 generic: true, 21024 }, 21025 { 21026 name: "Trunc64to8", 21027 argLen: 1, 21028 generic: true, 21029 }, 21030 { 21031 name: "Trunc64to16", 21032 argLen: 1, 21033 generic: true, 21034 }, 21035 { 21036 name: "Trunc64to32", 21037 argLen: 1, 21038 generic: true, 21039 }, 21040 { 21041 name: "Cvt32to32F", 21042 argLen: 1, 21043 generic: true, 21044 }, 21045 { 21046 name: "Cvt32to64F", 21047 argLen: 1, 21048 generic: true, 21049 }, 21050 { 21051 name: "Cvt64to32F", 21052 argLen: 1, 21053 generic: true, 21054 }, 21055 { 21056 name: "Cvt64to64F", 21057 argLen: 1, 21058 generic: true, 21059 }, 21060 { 21061 name: "Cvt32Fto32", 21062 argLen: 1, 21063 generic: true, 21064 }, 21065 { 21066 name: "Cvt32Fto64", 21067 argLen: 1, 21068 generic: true, 21069 }, 21070 { 21071 name: "Cvt64Fto32", 21072 argLen: 1, 21073 generic: true, 21074 }, 21075 { 21076 name: "Cvt64Fto64", 21077 argLen: 1, 21078 generic: true, 21079 }, 21080 { 21081 name: "Cvt32Fto64F", 21082 argLen: 1, 21083 generic: true, 21084 }, 21085 { 21086 name: "Cvt64Fto32F", 21087 argLen: 1, 21088 generic: true, 21089 }, 21090 { 21091 name: "IsNonNil", 21092 argLen: 1, 21093 generic: true, 21094 }, 21095 { 21096 name: "IsInBounds", 21097 argLen: 2, 21098 generic: true, 21099 }, 21100 { 21101 name: "IsSliceInBounds", 21102 argLen: 2, 21103 generic: true, 21104 }, 21105 { 21106 name: "NilCheck", 21107 argLen: 2, 21108 generic: true, 21109 }, 21110 { 21111 name: "GetG", 21112 argLen: 1, 21113 generic: true, 21114 }, 21115 { 21116 name: "GetClosurePtr", 21117 argLen: 0, 21118 generic: true, 21119 }, 21120 { 21121 name: "PtrIndex", 21122 argLen: 2, 21123 generic: true, 21124 }, 21125 { 21126 name: "OffPtr", 21127 auxType: auxInt64, 21128 argLen: 1, 21129 generic: true, 21130 }, 21131 { 21132 name: "SliceMake", 21133 argLen: 3, 21134 generic: true, 21135 }, 21136 { 21137 name: "SlicePtr", 21138 argLen: 1, 21139 generic: true, 21140 }, 21141 { 21142 name: "SliceLen", 21143 argLen: 1, 21144 generic: true, 21145 }, 21146 { 21147 name: "SliceCap", 21148 argLen: 1, 21149 generic: true, 21150 }, 21151 { 21152 name: "ComplexMake", 21153 argLen: 2, 21154 generic: true, 21155 }, 21156 { 21157 name: "ComplexReal", 21158 argLen: 1, 21159 generic: true, 21160 }, 21161 { 21162 name: "ComplexImag", 21163 argLen: 1, 21164 generic: true, 21165 }, 21166 { 21167 name: "StringMake", 21168 argLen: 2, 21169 generic: true, 21170 }, 21171 { 21172 name: "StringPtr", 21173 argLen: 1, 21174 generic: true, 21175 }, 21176 { 21177 name: "StringLen", 21178 argLen: 1, 21179 generic: true, 21180 }, 21181 { 21182 name: "IMake", 21183 argLen: 2, 21184 generic: true, 21185 }, 21186 { 21187 name: "ITab", 21188 argLen: 1, 21189 generic: true, 21190 }, 21191 { 21192 name: "IData", 21193 argLen: 1, 21194 generic: true, 21195 }, 21196 { 21197 name: "StructMake0", 21198 argLen: 0, 21199 generic: true, 21200 }, 21201 { 21202 name: "StructMake1", 21203 argLen: 1, 21204 generic: true, 21205 }, 21206 { 21207 name: "StructMake2", 21208 argLen: 2, 21209 generic: true, 21210 }, 21211 { 21212 name: "StructMake3", 21213 argLen: 3, 21214 generic: true, 21215 }, 21216 { 21217 name: "StructMake4", 21218 argLen: 4, 21219 generic: true, 21220 }, 21221 { 21222 name: "StructSelect", 21223 auxType: auxInt64, 21224 argLen: 1, 21225 generic: true, 21226 }, 21227 { 21228 name: "ArrayMake0", 21229 argLen: 0, 21230 generic: true, 21231 }, 21232 { 21233 name: "ArrayMake1", 21234 argLen: 1, 21235 generic: true, 21236 }, 21237 { 21238 name: "ArraySelect", 21239 auxType: auxInt64, 21240 argLen: 1, 21241 generic: true, 21242 }, 21243 { 21244 name: "StoreReg", 21245 argLen: 1, 21246 generic: true, 21247 }, 21248 { 21249 name: "LoadReg", 21250 argLen: 1, 21251 generic: true, 21252 }, 21253 { 21254 name: "FwdRef", 21255 auxType: auxSym, 21256 argLen: 0, 21257 generic: true, 21258 }, 21259 { 21260 name: "Unknown", 21261 argLen: 0, 21262 generic: true, 21263 }, 21264 { 21265 name: "VarDef", 21266 auxType: auxSym, 21267 argLen: 1, 21268 generic: true, 21269 }, 21270 { 21271 name: "VarKill", 21272 auxType: auxSym, 21273 argLen: 1, 21274 generic: true, 21275 }, 21276 { 21277 name: "VarLive", 21278 auxType: auxSym, 21279 argLen: 1, 21280 generic: true, 21281 }, 21282 { 21283 name: "KeepAlive", 21284 argLen: 2, 21285 generic: true, 21286 }, 21287 { 21288 name: "Int64Make", 21289 argLen: 2, 21290 generic: true, 21291 }, 21292 { 21293 name: "Int64Hi", 21294 argLen: 1, 21295 generic: true, 21296 }, 21297 { 21298 name: "Int64Lo", 21299 argLen: 1, 21300 generic: true, 21301 }, 21302 { 21303 name: "Add32carry", 21304 argLen: 2, 21305 commutative: true, 21306 generic: true, 21307 }, 21308 { 21309 name: "Add32withcarry", 21310 argLen: 3, 21311 commutative: true, 21312 generic: true, 21313 }, 21314 { 21315 name: "Sub32carry", 21316 argLen: 2, 21317 generic: true, 21318 }, 21319 { 21320 name: "Sub32withcarry", 21321 argLen: 3, 21322 generic: true, 21323 }, 21324 { 21325 name: "Signmask", 21326 argLen: 1, 21327 generic: true, 21328 }, 21329 { 21330 name: "Zeromask", 21331 argLen: 1, 21332 generic: true, 21333 }, 21334 { 21335 name: "Slicemask", 21336 argLen: 1, 21337 generic: true, 21338 }, 21339 { 21340 name: "Cvt32Uto32F", 21341 argLen: 1, 21342 generic: true, 21343 }, 21344 { 21345 name: "Cvt32Uto64F", 21346 argLen: 1, 21347 generic: true, 21348 }, 21349 { 21350 name: "Cvt32Fto32U", 21351 argLen: 1, 21352 generic: true, 21353 }, 21354 { 21355 name: "Cvt64Fto32U", 21356 argLen: 1, 21357 generic: true, 21358 }, 21359 { 21360 name: "Cvt64Uto32F", 21361 argLen: 1, 21362 generic: true, 21363 }, 21364 { 21365 name: "Cvt64Uto64F", 21366 argLen: 1, 21367 generic: true, 21368 }, 21369 { 21370 name: "Cvt32Fto64U", 21371 argLen: 1, 21372 generic: true, 21373 }, 21374 { 21375 name: "Cvt64Fto64U", 21376 argLen: 1, 21377 generic: true, 21378 }, 21379 { 21380 name: "Select0", 21381 argLen: 1, 21382 generic: true, 21383 }, 21384 { 21385 name: "Select1", 21386 argLen: 1, 21387 generic: true, 21388 }, 21389 { 21390 name: "AtomicLoad32", 21391 argLen: 2, 21392 generic: true, 21393 }, 21394 { 21395 name: "AtomicLoad64", 21396 argLen: 2, 21397 generic: true, 21398 }, 21399 { 21400 name: "AtomicLoadPtr", 21401 argLen: 2, 21402 generic: true, 21403 }, 21404 { 21405 name: "AtomicStore32", 21406 argLen: 3, 21407 generic: true, 21408 }, 21409 { 21410 name: "AtomicStore64", 21411 argLen: 3, 21412 generic: true, 21413 }, 21414 { 21415 name: "AtomicStorePtrNoWB", 21416 argLen: 3, 21417 generic: true, 21418 }, 21419 { 21420 name: "AtomicExchange32", 21421 argLen: 3, 21422 generic: true, 21423 }, 21424 { 21425 name: "AtomicExchange64", 21426 argLen: 3, 21427 generic: true, 21428 }, 21429 { 21430 name: "AtomicAdd32", 21431 argLen: 3, 21432 generic: true, 21433 }, 21434 { 21435 name: "AtomicAdd64", 21436 argLen: 3, 21437 generic: true, 21438 }, 21439 { 21440 name: "AtomicCompareAndSwap32", 21441 argLen: 4, 21442 generic: true, 21443 }, 21444 { 21445 name: "AtomicCompareAndSwap64", 21446 argLen: 4, 21447 generic: true, 21448 }, 21449 { 21450 name: "AtomicAnd8", 21451 argLen: 3, 21452 generic: true, 21453 }, 21454 { 21455 name: "AtomicOr8", 21456 argLen: 3, 21457 generic: true, 21458 }, 21459 } 21460 21461 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 21462 func (o Op) String() string { return opcodeTable[o].name } 21463 func (o Op) UsesScratch() bool { return opcodeTable[o].usesScratch } 21464 21465 var registers386 = [...]Register{ 21466 {0, x86.REG_AX, "AX"}, 21467 {1, x86.REG_CX, "CX"}, 21468 {2, x86.REG_DX, "DX"}, 21469 {3, x86.REG_BX, "BX"}, 21470 {4, x86.REGSP, "SP"}, 21471 {5, x86.REG_BP, "BP"}, 21472 {6, x86.REG_SI, "SI"}, 21473 {7, x86.REG_DI, "DI"}, 21474 {8, x86.REG_X0, "X0"}, 21475 {9, x86.REG_X1, "X1"}, 21476 {10, x86.REG_X2, "X2"}, 21477 {11, x86.REG_X3, "X3"}, 21478 {12, x86.REG_X4, "X4"}, 21479 {13, x86.REG_X5, "X5"}, 21480 {14, x86.REG_X6, "X6"}, 21481 {15, x86.REG_X7, "X7"}, 21482 {16, 0, "SB"}, 21483 } 21484 var gpRegMask386 = regMask(239) 21485 var fpRegMask386 = regMask(65280) 21486 var specialRegMask386 = regMask(0) 21487 var framepointerReg386 = int8(5) 21488 var linkReg386 = int8(-1) 21489 var registersAMD64 = [...]Register{ 21490 {0, x86.REG_AX, "AX"}, 21491 {1, x86.REG_CX, "CX"}, 21492 {2, x86.REG_DX, "DX"}, 21493 {3, x86.REG_BX, "BX"}, 21494 {4, x86.REGSP, "SP"}, 21495 {5, x86.REG_BP, "BP"}, 21496 {6, x86.REG_SI, "SI"}, 21497 {7, x86.REG_DI, "DI"}, 21498 {8, x86.REG_R8, "R8"}, 21499 {9, x86.REG_R9, "R9"}, 21500 {10, x86.REG_R10, "R10"}, 21501 {11, x86.REG_R11, "R11"}, 21502 {12, x86.REG_R12, "R12"}, 21503 {13, x86.REG_R13, "R13"}, 21504 {14, x86.REG_R14, "R14"}, 21505 {15, x86.REG_R15, "R15"}, 21506 {16, x86.REG_X0, "X0"}, 21507 {17, x86.REG_X1, "X1"}, 21508 {18, x86.REG_X2, "X2"}, 21509 {19, x86.REG_X3, "X3"}, 21510 {20, x86.REG_X4, "X4"}, 21511 {21, x86.REG_X5, "X5"}, 21512 {22, x86.REG_X6, "X6"}, 21513 {23, x86.REG_X7, "X7"}, 21514 {24, x86.REG_X8, "X8"}, 21515 {25, x86.REG_X9, "X9"}, 21516 {26, x86.REG_X10, "X10"}, 21517 {27, x86.REG_X11, "X11"}, 21518 {28, x86.REG_X12, "X12"}, 21519 {29, x86.REG_X13, "X13"}, 21520 {30, x86.REG_X14, "X14"}, 21521 {31, x86.REG_X15, "X15"}, 21522 {32, 0, "SB"}, 21523 } 21524 var gpRegMaskAMD64 = regMask(65519) 21525 var fpRegMaskAMD64 = regMask(4294901760) 21526 var specialRegMaskAMD64 = regMask(0) 21527 var framepointerRegAMD64 = int8(5) 21528 var linkRegAMD64 = int8(-1) 21529 var registersARM = [...]Register{ 21530 {0, arm.REG_R0, "R0"}, 21531 {1, arm.REG_R1, "R1"}, 21532 {2, arm.REG_R2, "R2"}, 21533 {3, arm.REG_R3, "R3"}, 21534 {4, arm.REG_R4, "R4"}, 21535 {5, arm.REG_R5, "R5"}, 21536 {6, arm.REG_R6, "R6"}, 21537 {7, arm.REG_R7, "R7"}, 21538 {8, arm.REG_R8, "R8"}, 21539 {9, arm.REG_R9, "R9"}, 21540 {10, arm.REGG, "g"}, 21541 {11, arm.REG_R11, "R11"}, 21542 {12, arm.REG_R12, "R12"}, 21543 {13, arm.REGSP, "SP"}, 21544 {14, arm.REG_R14, "R14"}, 21545 {15, arm.REG_R15, "R15"}, 21546 {16, arm.REG_F0, "F0"}, 21547 {17, arm.REG_F1, "F1"}, 21548 {18, arm.REG_F2, "F2"}, 21549 {19, arm.REG_F3, "F3"}, 21550 {20, arm.REG_F4, "F4"}, 21551 {21, arm.REG_F5, "F5"}, 21552 {22, arm.REG_F6, "F6"}, 21553 {23, arm.REG_F7, "F7"}, 21554 {24, arm.REG_F8, "F8"}, 21555 {25, arm.REG_F9, "F9"}, 21556 {26, arm.REG_F10, "F10"}, 21557 {27, arm.REG_F11, "F11"}, 21558 {28, arm.REG_F12, "F12"}, 21559 {29, arm.REG_F13, "F13"}, 21560 {30, arm.REG_F14, "F14"}, 21561 {31, arm.REG_F15, "F15"}, 21562 {32, 0, "SB"}, 21563 } 21564 var gpRegMaskARM = regMask(21503) 21565 var fpRegMaskARM = regMask(4294901760) 21566 var specialRegMaskARM = regMask(0) 21567 var framepointerRegARM = int8(-1) 21568 var linkRegARM = int8(14) 21569 var registersARM64 = [...]Register{ 21570 {0, arm64.REG_R0, "R0"}, 21571 {1, arm64.REG_R1, "R1"}, 21572 {2, arm64.REG_R2, "R2"}, 21573 {3, arm64.REG_R3, "R3"}, 21574 {4, arm64.REG_R4, "R4"}, 21575 {5, arm64.REG_R5, "R5"}, 21576 {6, arm64.REG_R6, "R6"}, 21577 {7, arm64.REG_R7, "R7"}, 21578 {8, arm64.REG_R8, "R8"}, 21579 {9, arm64.REG_R9, "R9"}, 21580 {10, arm64.REG_R10, "R10"}, 21581 {11, arm64.REG_R11, "R11"}, 21582 {12, arm64.REG_R12, "R12"}, 21583 {13, arm64.REG_R13, "R13"}, 21584 {14, arm64.REG_R14, "R14"}, 21585 {15, arm64.REG_R15, "R15"}, 21586 {16, arm64.REG_R16, "R16"}, 21587 {17, arm64.REG_R17, "R17"}, 21588 {18, arm64.REG_R18, "R18"}, 21589 {19, arm64.REG_R19, "R19"}, 21590 {20, arm64.REG_R20, "R20"}, 21591 {21, arm64.REG_R21, "R21"}, 21592 {22, arm64.REG_R22, "R22"}, 21593 {23, arm64.REG_R23, "R23"}, 21594 {24, arm64.REG_R24, "R24"}, 21595 {25, arm64.REG_R25, "R25"}, 21596 {26, arm64.REG_R26, "R26"}, 21597 {27, arm64.REGG, "g"}, 21598 {28, arm64.REG_R29, "R29"}, 21599 {29, arm64.REG_R30, "R30"}, 21600 {30, arm64.REGSP, "SP"}, 21601 {31, arm64.REG_F0, "F0"}, 21602 {32, arm64.REG_F1, "F1"}, 21603 {33, arm64.REG_F2, "F2"}, 21604 {34, arm64.REG_F3, "F3"}, 21605 {35, arm64.REG_F4, "F4"}, 21606 {36, arm64.REG_F5, "F5"}, 21607 {37, arm64.REG_F6, "F6"}, 21608 {38, arm64.REG_F7, "F7"}, 21609 {39, arm64.REG_F8, "F8"}, 21610 {40, arm64.REG_F9, "F9"}, 21611 {41, arm64.REG_F10, "F10"}, 21612 {42, arm64.REG_F11, "F11"}, 21613 {43, arm64.REG_F12, "F12"}, 21614 {44, arm64.REG_F13, "F13"}, 21615 {45, arm64.REG_F14, "F14"}, 21616 {46, arm64.REG_F15, "F15"}, 21617 {47, arm64.REG_F16, "F16"}, 21618 {48, arm64.REG_F17, "F17"}, 21619 {49, arm64.REG_F18, "F18"}, 21620 {50, arm64.REG_F19, "F19"}, 21621 {51, arm64.REG_F20, "F20"}, 21622 {52, arm64.REG_F21, "F21"}, 21623 {53, arm64.REG_F22, "F22"}, 21624 {54, arm64.REG_F23, "F23"}, 21625 {55, arm64.REG_F24, "F24"}, 21626 {56, arm64.REG_F25, "F25"}, 21627 {57, arm64.REG_F26, "F26"}, 21628 {58, arm64.REG_F27, "F27"}, 21629 {59, arm64.REG_F28, "F28"}, 21630 {60, arm64.REG_F29, "F29"}, 21631 {61, arm64.REG_F30, "F30"}, 21632 {62, arm64.REG_F31, "F31"}, 21633 {63, 0, "SB"}, 21634 } 21635 var gpRegMaskARM64 = regMask(670826495) 21636 var fpRegMaskARM64 = regMask(9223372034707292160) 21637 var specialRegMaskARM64 = regMask(0) 21638 var framepointerRegARM64 = int8(-1) 21639 var linkRegARM64 = int8(29) 21640 var registersMIPS = [...]Register{ 21641 {0, mips.REG_R0, "R0"}, 21642 {1, mips.REG_R1, "R1"}, 21643 {2, mips.REG_R2, "R2"}, 21644 {3, mips.REG_R3, "R3"}, 21645 {4, mips.REG_R4, "R4"}, 21646 {5, mips.REG_R5, "R5"}, 21647 {6, mips.REG_R6, "R6"}, 21648 {7, mips.REG_R7, "R7"}, 21649 {8, mips.REG_R8, "R8"}, 21650 {9, mips.REG_R9, "R9"}, 21651 {10, mips.REG_R10, "R10"}, 21652 {11, mips.REG_R11, "R11"}, 21653 {12, mips.REG_R12, "R12"}, 21654 {13, mips.REG_R13, "R13"}, 21655 {14, mips.REG_R14, "R14"}, 21656 {15, mips.REG_R15, "R15"}, 21657 {16, mips.REG_R16, "R16"}, 21658 {17, mips.REG_R17, "R17"}, 21659 {18, mips.REG_R18, "R18"}, 21660 {19, mips.REG_R19, "R19"}, 21661 {20, mips.REG_R20, "R20"}, 21662 {21, mips.REG_R21, "R21"}, 21663 {22, mips.REG_R22, "R22"}, 21664 {23, mips.REG_R24, "R24"}, 21665 {24, mips.REG_R25, "R25"}, 21666 {25, mips.REG_R28, "R28"}, 21667 {26, mips.REGSP, "SP"}, 21668 {27, mips.REGG, "g"}, 21669 {28, mips.REG_R31, "R31"}, 21670 {29, mips.REG_F0, "F0"}, 21671 {30, mips.REG_F2, "F2"}, 21672 {31, mips.REG_F4, "F4"}, 21673 {32, mips.REG_F6, "F6"}, 21674 {33, mips.REG_F8, "F8"}, 21675 {34, mips.REG_F10, "F10"}, 21676 {35, mips.REG_F12, "F12"}, 21677 {36, mips.REG_F14, "F14"}, 21678 {37, mips.REG_F16, "F16"}, 21679 {38, mips.REG_F18, "F18"}, 21680 {39, mips.REG_F20, "F20"}, 21681 {40, mips.REG_F22, "F22"}, 21682 {41, mips.REG_F24, "F24"}, 21683 {42, mips.REG_F26, "F26"}, 21684 {43, mips.REG_F28, "F28"}, 21685 {44, mips.REG_F30, "F30"}, 21686 {45, mips.REG_HI, "HI"}, 21687 {46, mips.REG_LO, "LO"}, 21688 {47, 0, "SB"}, 21689 } 21690 var gpRegMaskMIPS = regMask(335544318) 21691 var fpRegMaskMIPS = regMask(35183835217920) 21692 var specialRegMaskMIPS = regMask(105553116266496) 21693 var framepointerRegMIPS = int8(-1) 21694 var linkRegMIPS = int8(28) 21695 var registersMIPS64 = [...]Register{ 21696 {0, mips.REG_R0, "R0"}, 21697 {1, mips.REG_R1, "R1"}, 21698 {2, mips.REG_R2, "R2"}, 21699 {3, mips.REG_R3, "R3"}, 21700 {4, mips.REG_R4, "R4"}, 21701 {5, mips.REG_R5, "R5"}, 21702 {6, mips.REG_R6, "R6"}, 21703 {7, mips.REG_R7, "R7"}, 21704 {8, mips.REG_R8, "R8"}, 21705 {9, mips.REG_R9, "R9"}, 21706 {10, mips.REG_R10, "R10"}, 21707 {11, mips.REG_R11, "R11"}, 21708 {12, mips.REG_R12, "R12"}, 21709 {13, mips.REG_R13, "R13"}, 21710 {14, mips.REG_R14, "R14"}, 21711 {15, mips.REG_R15, "R15"}, 21712 {16, mips.REG_R16, "R16"}, 21713 {17, mips.REG_R17, "R17"}, 21714 {18, mips.REG_R18, "R18"}, 21715 {19, mips.REG_R19, "R19"}, 21716 {20, mips.REG_R20, "R20"}, 21717 {21, mips.REG_R21, "R21"}, 21718 {22, mips.REG_R22, "R22"}, 21719 {23, mips.REG_R24, "R24"}, 21720 {24, mips.REG_R25, "R25"}, 21721 {25, mips.REGSP, "SP"}, 21722 {26, mips.REGG, "g"}, 21723 {27, mips.REG_R31, "R31"}, 21724 {28, mips.REG_F0, "F0"}, 21725 {29, mips.REG_F1, "F1"}, 21726 {30, mips.REG_F2, "F2"}, 21727 {31, mips.REG_F3, "F3"}, 21728 {32, mips.REG_F4, "F4"}, 21729 {33, mips.REG_F5, "F5"}, 21730 {34, mips.REG_F6, "F6"}, 21731 {35, mips.REG_F7, "F7"}, 21732 {36, mips.REG_F8, "F8"}, 21733 {37, mips.REG_F9, "F9"}, 21734 {38, mips.REG_F10, "F10"}, 21735 {39, mips.REG_F11, "F11"}, 21736 {40, mips.REG_F12, "F12"}, 21737 {41, mips.REG_F13, "F13"}, 21738 {42, mips.REG_F14, "F14"}, 21739 {43, mips.REG_F15, "F15"}, 21740 {44, mips.REG_F16, "F16"}, 21741 {45, mips.REG_F17, "F17"}, 21742 {46, mips.REG_F18, "F18"}, 21743 {47, mips.REG_F19, "F19"}, 21744 {48, mips.REG_F20, "F20"}, 21745 {49, mips.REG_F21, "F21"}, 21746 {50, mips.REG_F22, "F22"}, 21747 {51, mips.REG_F23, "F23"}, 21748 {52, mips.REG_F24, "F24"}, 21749 {53, mips.REG_F25, "F25"}, 21750 {54, mips.REG_F26, "F26"}, 21751 {55, mips.REG_F27, "F27"}, 21752 {56, mips.REG_F28, "F28"}, 21753 {57, mips.REG_F29, "F29"}, 21754 {58, mips.REG_F30, "F30"}, 21755 {59, mips.REG_F31, "F31"}, 21756 {60, mips.REG_HI, "HI"}, 21757 {61, mips.REG_LO, "LO"}, 21758 {62, 0, "SB"}, 21759 } 21760 var gpRegMaskMIPS64 = regMask(167772158) 21761 var fpRegMaskMIPS64 = regMask(1152921504338411520) 21762 var specialRegMaskMIPS64 = regMask(3458764513820540928) 21763 var framepointerRegMIPS64 = int8(-1) 21764 var linkRegMIPS64 = int8(27) 21765 var registersPPC64 = [...]Register{ 21766 {0, ppc64.REG_R0, "R0"}, 21767 {1, ppc64.REGSP, "SP"}, 21768 {2, 0, "SB"}, 21769 {3, ppc64.REG_R3, "R3"}, 21770 {4, ppc64.REG_R4, "R4"}, 21771 {5, ppc64.REG_R5, "R5"}, 21772 {6, ppc64.REG_R6, "R6"}, 21773 {7, ppc64.REG_R7, "R7"}, 21774 {8, ppc64.REG_R8, "R8"}, 21775 {9, ppc64.REG_R9, "R9"}, 21776 {10, ppc64.REG_R10, "R10"}, 21777 {11, ppc64.REG_R11, "R11"}, 21778 {12, ppc64.REG_R12, "R12"}, 21779 {13, ppc64.REG_R13, "R13"}, 21780 {14, ppc64.REG_R14, "R14"}, 21781 {15, ppc64.REG_R15, "R15"}, 21782 {16, ppc64.REG_R16, "R16"}, 21783 {17, ppc64.REG_R17, "R17"}, 21784 {18, ppc64.REG_R18, "R18"}, 21785 {19, ppc64.REG_R19, "R19"}, 21786 {20, ppc64.REG_R20, "R20"}, 21787 {21, ppc64.REG_R21, "R21"}, 21788 {22, ppc64.REG_R22, "R22"}, 21789 {23, ppc64.REG_R23, "R23"}, 21790 {24, ppc64.REG_R24, "R24"}, 21791 {25, ppc64.REG_R25, "R25"}, 21792 {26, ppc64.REG_R26, "R26"}, 21793 {27, ppc64.REG_R27, "R27"}, 21794 {28, ppc64.REG_R28, "R28"}, 21795 {29, ppc64.REG_R29, "R29"}, 21796 {30, ppc64.REGG, "g"}, 21797 {31, ppc64.REG_R31, "R31"}, 21798 {32, ppc64.REG_F0, "F0"}, 21799 {33, ppc64.REG_F1, "F1"}, 21800 {34, ppc64.REG_F2, "F2"}, 21801 {35, ppc64.REG_F3, "F3"}, 21802 {36, ppc64.REG_F4, "F4"}, 21803 {37, ppc64.REG_F5, "F5"}, 21804 {38, ppc64.REG_F6, "F6"}, 21805 {39, ppc64.REG_F7, "F7"}, 21806 {40, ppc64.REG_F8, "F8"}, 21807 {41, ppc64.REG_F9, "F9"}, 21808 {42, ppc64.REG_F10, "F10"}, 21809 {43, ppc64.REG_F11, "F11"}, 21810 {44, ppc64.REG_F12, "F12"}, 21811 {45, ppc64.REG_F13, "F13"}, 21812 {46, ppc64.REG_F14, "F14"}, 21813 {47, ppc64.REG_F15, "F15"}, 21814 {48, ppc64.REG_F16, "F16"}, 21815 {49, ppc64.REG_F17, "F17"}, 21816 {50, ppc64.REG_F18, "F18"}, 21817 {51, ppc64.REG_F19, "F19"}, 21818 {52, ppc64.REG_F20, "F20"}, 21819 {53, ppc64.REG_F21, "F21"}, 21820 {54, ppc64.REG_F22, "F22"}, 21821 {55, ppc64.REG_F23, "F23"}, 21822 {56, ppc64.REG_F24, "F24"}, 21823 {57, ppc64.REG_F25, "F25"}, 21824 {58, ppc64.REG_F26, "F26"}, 21825 {59, ppc64.REG_F27, "F27"}, 21826 {60, ppc64.REG_F28, "F28"}, 21827 {61, ppc64.REG_F29, "F29"}, 21828 {62, ppc64.REG_F30, "F30"}, 21829 {63, ppc64.REG_F31, "F31"}, 21830 } 21831 var gpRegMaskPPC64 = regMask(1073733624) 21832 var fpRegMaskPPC64 = regMask(576460743713488896) 21833 var specialRegMaskPPC64 = regMask(0) 21834 var framepointerRegPPC64 = int8(1) 21835 var linkRegPPC64 = int8(-1) 21836 var registersS390X = [...]Register{ 21837 {0, s390x.REG_R0, "R0"}, 21838 {1, s390x.REG_R1, "R1"}, 21839 {2, s390x.REG_R2, "R2"}, 21840 {3, s390x.REG_R3, "R3"}, 21841 {4, s390x.REG_R4, "R4"}, 21842 {5, s390x.REG_R5, "R5"}, 21843 {6, s390x.REG_R6, "R6"}, 21844 {7, s390x.REG_R7, "R7"}, 21845 {8, s390x.REG_R8, "R8"}, 21846 {9, s390x.REG_R9, "R9"}, 21847 {10, s390x.REG_R10, "R10"}, 21848 {11, s390x.REG_R11, "R11"}, 21849 {12, s390x.REG_R12, "R12"}, 21850 {13, s390x.REGG, "g"}, 21851 {14, s390x.REG_R14, "R14"}, 21852 {15, s390x.REGSP, "SP"}, 21853 {16, s390x.REG_F0, "F0"}, 21854 {17, s390x.REG_F1, "F1"}, 21855 {18, s390x.REG_F2, "F2"}, 21856 {19, s390x.REG_F3, "F3"}, 21857 {20, s390x.REG_F4, "F4"}, 21858 {21, s390x.REG_F5, "F5"}, 21859 {22, s390x.REG_F6, "F6"}, 21860 {23, s390x.REG_F7, "F7"}, 21861 {24, s390x.REG_F8, "F8"}, 21862 {25, s390x.REG_F9, "F9"}, 21863 {26, s390x.REG_F10, "F10"}, 21864 {27, s390x.REG_F11, "F11"}, 21865 {28, s390x.REG_F12, "F12"}, 21866 {29, s390x.REG_F13, "F13"}, 21867 {30, s390x.REG_F14, "F14"}, 21868 {31, s390x.REG_F15, "F15"}, 21869 {32, 0, "SB"}, 21870 } 21871 var gpRegMaskS390X = regMask(21503) 21872 var fpRegMaskS390X = regMask(4294901760) 21873 var specialRegMaskS390X = regMask(0) 21874 var framepointerRegS390X = int8(-1) 21875 var linkRegS390X = int8(14)