github.com/mvdan/u-root-coreutils@v0.0.0-20230122170626-c2eef2898555/pkg/pci/const.go (about)

     1  // Copyright 2021 the u-root Authors. All rights reserved
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package pci
     6  
     7  // Constants for Linux kernel access.
     8  const (
     9  	// StdConfigSize is a PCI name -- standard?
    10  	StdConfigSize = 64
    11  	// ConfigSize is the pre-PCIE config size
    12  	ConfigSize = 256
    13  	// FullConfigSize is the PCIE 4k config size.
    14  	FullConfigSize = 4096
    15  )
    16  
    17  // Values defining config space.
    18  const (
    19  	StdNumBARS = 6
    20  )
    21  
    22  // Config space registers
    23  const (
    24  	VID = 0
    25  	DID = 2
    26  
    27  	Cmd            = 4
    28  	CmdIO          = 1
    29  	CmdMem         = 2
    30  	CmdBME         = 4
    31  	CmdSpecial     = 8
    32  	CmdMWINV       = 0x10
    33  	CmdVGA         = 0x20
    34  	CmdParity      = 0x40
    35  	CmdStep        = 0x80
    36  	CmdSERR        = 0x100
    37  	CmdFastB2B     = 0x200
    38  	CmdINTXDisable = 0x400
    39  
    40  	ClassRevision = 8
    41  	RevisionID    = 8
    42  	ClassProg     = 9
    43  	ClassDevice   = 10
    44  
    45  	CacheLineSize = 0xc
    46  
    47  	LatencyTimer = 0xd
    48  
    49  	HeaderType       = 0xe
    50  	HeaderTypeMask   = 0x7f
    51  	HeaderTypeNormal = 0
    52  	HeaderTypeBridge = 1
    53  
    54  	BAR0 = 0x10
    55  	BAR1 = 0x14
    56  	BAR2 = 0x18
    57  	BAR3 = 0x1c
    58  	BAR4 = 0x20
    59  	BAR5 = 0x24
    60  
    61  	// The low 3 bits tell you what type of space it is.
    62  	BARTypeMask = 7
    63  	BARMem32    = 0
    64  	BARIO       = 1
    65  	BARMem64    = 4
    66  	BARPrefetch = 8
    67  	BARMemMask  = ^0xf
    68  	BARIOMask   = ^3
    69  
    70  	// Type 0 devices
    71  	SubSystemVID   = 0x2c
    72  	SubSystemID    = 0x2e
    73  	ROMAddress     = 0x30
    74  	ROMEnabled     = 1
    75  	ROMAddressMask = ^0x7ff
    76  
    77  	IRQLine = 0x3c
    78  	IRQPin  = 0x3d
    79  	MinGnt  = 0x3e
    80  	MaxLat  = 0x3f
    81  
    82  	// Type 1
    83  	Primary          = 0x18 // our bus
    84  	Secondary        = 0x19 // first bus behind bridge
    85  	Subordinate      = 0x1a // last bus behind bridge, inclusive
    86  	SecondaryLatency = 0x1b
    87  	IOBase           = 0x1c
    88  	IOLimit          = 0x1d
    89  	IOHighBase       = 0x30
    90  	IOHighLimit      = 0x32
    91  	IOTypeMask       = 0xf
    92  	IOType16         = 0
    93  	IOType32         = 1
    94  	IORangeMask4k    = 0xf
    95  	IORangeMaskIntel = 3 // Intel has ever been ready to "improve" PCI
    96  
    97  	SecStatus = 0x1e // bit 14 only
    98  
    99  	MemBase          = 0x20
   100  	MemLimit         = 0x22
   101  	MemTypeMask      = 0xf
   102  	MemMask          = ^MemTypeMask
   103  	PrefMemBase      = 0x24
   104  	PrefMemLimit     = 0x26
   105  	PrefMemTypeMask  = 0xf
   106  	PrefMemType32    = 0
   107  	PrefMemType64    = 1
   108  	PrefMemHighBase  = 0x28
   109  	PrefMemHighLimit = 0x30
   110  
   111  	BridgeRomAddress = 0x38
   112  
   113  	BridgeControl     = 0x3e
   114  	BridgeParity      = 1
   115  	BridgeSERR        = 2
   116  	BridgeISA         = 4
   117  	BridgeVGA         = 8
   118  	BridgeMasterAbort = 0x20
   119  	BridgeBusReset    = 0x40
   120  	BridgeFastB2B     = 0x80
   121  )