github.com/panjjo/go@v0.0.0-20161104043856-d62b31386338/src/cmd/asm/internal/arch/arch.go (about) 1 // Copyright 2015 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 package arch 6 7 import ( 8 "cmd/internal/obj" 9 "cmd/internal/obj/arm" 10 "cmd/internal/obj/arm64" 11 "cmd/internal/obj/mips" 12 "cmd/internal/obj/ppc64" 13 "cmd/internal/obj/s390x" 14 "cmd/internal/obj/x86" 15 "fmt" 16 "strings" 17 ) 18 19 // Pseudo-registers whose names are the constant name without the leading R. 20 const ( 21 RFP = -(iota + 1) 22 RSB 23 RSP 24 RPC 25 ) 26 27 // Arch wraps the link architecture object with more architecture-specific information. 28 type Arch struct { 29 *obj.LinkArch 30 // Map of instruction names to enumeration. 31 Instructions map[string]obj.As 32 // Map of register names to enumeration. 33 Register map[string]int16 34 // Table of register prefix names. These are things like R for R(0) and SPR for SPR(268). 35 RegisterPrefix map[string]bool 36 // RegisterNumber converts R(10) into arm.REG_R10. 37 RegisterNumber func(string, int16) (int16, bool) 38 // Instruction is a jump. 39 IsJump func(word string) bool 40 } 41 42 // nilRegisterNumber is the register number function for architectures 43 // that do not accept the R(N) notation. It always returns failure. 44 func nilRegisterNumber(name string, n int16) (int16, bool) { 45 return 0, false 46 } 47 48 // Set configures the architecture specified by GOARCH and returns its representation. 49 // It returns nil if GOARCH is not recognized. 50 func Set(GOARCH string) *Arch { 51 switch GOARCH { 52 case "386": 53 return archX86(&x86.Link386) 54 case "amd64": 55 return archX86(&x86.Linkamd64) 56 case "amd64p32": 57 return archX86(&x86.Linkamd64p32) 58 case "arm": 59 return archArm() 60 case "arm64": 61 return archArm64() 62 case "mips64": 63 a := archMips64() 64 a.LinkArch = &mips.Linkmips64 65 return a 66 case "mips64le": 67 a := archMips64() 68 a.LinkArch = &mips.Linkmips64le 69 return a 70 case "ppc64": 71 a := archPPC64() 72 a.LinkArch = &ppc64.Linkppc64 73 return a 74 case "ppc64le": 75 a := archPPC64() 76 a.LinkArch = &ppc64.Linkppc64le 77 return a 78 case "s390x": 79 a := archS390x() 80 a.LinkArch = &s390x.Links390x 81 return a 82 } 83 return nil 84 } 85 86 func jumpX86(word string) bool { 87 return word[0] == 'J' || word == "CALL" || strings.HasPrefix(word, "LOOP") || word == "XBEGIN" 88 } 89 90 func archX86(linkArch *obj.LinkArch) *Arch { 91 register := make(map[string]int16) 92 // Create maps for easy lookup of instruction names etc. 93 for i, s := range x86.Register { 94 register[s] = int16(i + x86.REG_AL) 95 } 96 // Pseudo-registers. 97 register["SB"] = RSB 98 register["FP"] = RFP 99 register["PC"] = RPC 100 // Register prefix not used on this architecture. 101 102 instructions := make(map[string]obj.As) 103 for i, s := range obj.Anames { 104 instructions[s] = obj.As(i) 105 } 106 for i, s := range x86.Anames { 107 if obj.As(i) >= obj.A_ARCHSPECIFIC { 108 instructions[s] = obj.As(i) + obj.ABaseAMD64 109 } 110 } 111 // Annoying aliases. 112 instructions["JA"] = x86.AJHI /* alternate */ 113 instructions["JAE"] = x86.AJCC /* alternate */ 114 instructions["JB"] = x86.AJCS /* alternate */ 115 instructions["JBE"] = x86.AJLS /* alternate */ 116 instructions["JC"] = x86.AJCS /* alternate */ 117 instructions["JCC"] = x86.AJCC /* carry clear (CF = 0) */ 118 instructions["JCS"] = x86.AJCS /* carry set (CF = 1) */ 119 instructions["JE"] = x86.AJEQ /* alternate */ 120 instructions["JEQ"] = x86.AJEQ /* equal (ZF = 1) */ 121 instructions["JG"] = x86.AJGT /* alternate */ 122 instructions["JGE"] = x86.AJGE /* greater than or equal (signed) (SF = OF) */ 123 instructions["JGT"] = x86.AJGT /* greater than (signed) (ZF = 0 && SF = OF) */ 124 instructions["JHI"] = x86.AJHI /* higher (unsigned) (CF = 0 && ZF = 0) */ 125 instructions["JHS"] = x86.AJCC /* alternate */ 126 instructions["JL"] = x86.AJLT /* alternate */ 127 instructions["JLE"] = x86.AJLE /* less than or equal (signed) (ZF = 1 || SF != OF) */ 128 instructions["JLO"] = x86.AJCS /* alternate */ 129 instructions["JLS"] = x86.AJLS /* lower or same (unsigned) (CF = 1 || ZF = 1) */ 130 instructions["JLT"] = x86.AJLT /* less than (signed) (SF != OF) */ 131 instructions["JMI"] = x86.AJMI /* negative (minus) (SF = 1) */ 132 instructions["JNA"] = x86.AJLS /* alternate */ 133 instructions["JNAE"] = x86.AJCS /* alternate */ 134 instructions["JNB"] = x86.AJCC /* alternate */ 135 instructions["JNBE"] = x86.AJHI /* alternate */ 136 instructions["JNC"] = x86.AJCC /* alternate */ 137 instructions["JNE"] = x86.AJNE /* not equal (ZF = 0) */ 138 instructions["JNG"] = x86.AJLE /* alternate */ 139 instructions["JNGE"] = x86.AJLT /* alternate */ 140 instructions["JNL"] = x86.AJGE /* alternate */ 141 instructions["JNLE"] = x86.AJGT /* alternate */ 142 instructions["JNO"] = x86.AJOC /* alternate */ 143 instructions["JNP"] = x86.AJPC /* alternate */ 144 instructions["JNS"] = x86.AJPL /* alternate */ 145 instructions["JNZ"] = x86.AJNE /* alternate */ 146 instructions["JO"] = x86.AJOS /* alternate */ 147 instructions["JOC"] = x86.AJOC /* overflow clear (OF = 0) */ 148 instructions["JOS"] = x86.AJOS /* overflow set (OF = 1) */ 149 instructions["JP"] = x86.AJPS /* alternate */ 150 instructions["JPC"] = x86.AJPC /* parity clear (PF = 0) */ 151 instructions["JPE"] = x86.AJPS /* alternate */ 152 instructions["JPL"] = x86.AJPL /* non-negative (plus) (SF = 0) */ 153 instructions["JPO"] = x86.AJPC /* alternate */ 154 instructions["JPS"] = x86.AJPS /* parity set (PF = 1) */ 155 instructions["JS"] = x86.AJMI /* alternate */ 156 instructions["JZ"] = x86.AJEQ /* alternate */ 157 instructions["MASKMOVDQU"] = x86.AMASKMOVOU 158 instructions["MOVD"] = x86.AMOVQ 159 instructions["MOVDQ2Q"] = x86.AMOVQ 160 instructions["MOVNTDQ"] = x86.AMOVNTO 161 instructions["MOVOA"] = x86.AMOVO 162 instructions["PSLLDQ"] = x86.APSLLO 163 instructions["PSRLDQ"] = x86.APSRLO 164 instructions["PADDD"] = x86.APADDL 165 166 return &Arch{ 167 LinkArch: linkArch, 168 Instructions: instructions, 169 Register: register, 170 RegisterPrefix: nil, 171 RegisterNumber: nilRegisterNumber, 172 IsJump: jumpX86, 173 } 174 } 175 176 func archArm() *Arch { 177 register := make(map[string]int16) 178 // Create maps for easy lookup of instruction names etc. 179 // Note that there is no list of names as there is for x86. 180 for i := arm.REG_R0; i < arm.REG_SPSR; i++ { 181 register[obj.Rconv(i)] = int16(i) 182 } 183 // Avoid unintentionally clobbering g using R10. 184 delete(register, "R10") 185 register["g"] = arm.REG_R10 186 for i := 0; i < 16; i++ { 187 register[fmt.Sprintf("C%d", i)] = int16(i) 188 } 189 190 // Pseudo-registers. 191 register["SB"] = RSB 192 register["FP"] = RFP 193 register["PC"] = RPC 194 register["SP"] = RSP 195 registerPrefix := map[string]bool{ 196 "F": true, 197 "R": true, 198 } 199 200 instructions := make(map[string]obj.As) 201 for i, s := range obj.Anames { 202 instructions[s] = obj.As(i) 203 } 204 for i, s := range arm.Anames { 205 if obj.As(i) >= obj.A_ARCHSPECIFIC { 206 instructions[s] = obj.As(i) + obj.ABaseARM 207 } 208 } 209 // Annoying aliases. 210 instructions["B"] = obj.AJMP 211 instructions["BL"] = obj.ACALL 212 // MCR differs from MRC by the way fields of the word are encoded. 213 // (Details in arm.go). Here we add the instruction so parse will find 214 // it, but give it an opcode number known only to us. 215 instructions["MCR"] = aMCR 216 217 return &Arch{ 218 LinkArch: &arm.Linkarm, 219 Instructions: instructions, 220 Register: register, 221 RegisterPrefix: registerPrefix, 222 RegisterNumber: armRegisterNumber, 223 IsJump: jumpArm, 224 } 225 } 226 227 func archArm64() *Arch { 228 register := make(map[string]int16) 229 // Create maps for easy lookup of instruction names etc. 230 // Note that there is no list of names as there is for 386 and amd64. 231 register[arm64.Rconv(arm64.REGSP)] = int16(arm64.REGSP) 232 for i := arm64.REG_R0; i <= arm64.REG_R31; i++ { 233 register[arm64.Rconv(i)] = int16(i) 234 } 235 for i := arm64.REG_F0; i <= arm64.REG_F31; i++ { 236 register[arm64.Rconv(i)] = int16(i) 237 } 238 for i := arm64.REG_V0; i <= arm64.REG_V31; i++ { 239 register[arm64.Rconv(i)] = int16(i) 240 } 241 register["LR"] = arm64.REGLINK 242 register["DAIF"] = arm64.REG_DAIF 243 register["NZCV"] = arm64.REG_NZCV 244 register["FPSR"] = arm64.REG_FPSR 245 register["FPCR"] = arm64.REG_FPCR 246 register["SPSR_EL1"] = arm64.REG_SPSR_EL1 247 register["ELR_EL1"] = arm64.REG_ELR_EL1 248 register["SPSR_EL2"] = arm64.REG_SPSR_EL2 249 register["ELR_EL2"] = arm64.REG_ELR_EL2 250 register["CurrentEL"] = arm64.REG_CurrentEL 251 register["SP_EL0"] = arm64.REG_SP_EL0 252 register["SPSel"] = arm64.REG_SPSel 253 register["DAIFSet"] = arm64.REG_DAIFSet 254 register["DAIFClr"] = arm64.REG_DAIFClr 255 // Conditional operators, like EQ, NE, etc. 256 register["EQ"] = arm64.COND_EQ 257 register["NE"] = arm64.COND_NE 258 register["HS"] = arm64.COND_HS 259 register["CS"] = arm64.COND_HS 260 register["LO"] = arm64.COND_LO 261 register["CC"] = arm64.COND_LO 262 register["MI"] = arm64.COND_MI 263 register["PL"] = arm64.COND_PL 264 register["VS"] = arm64.COND_VS 265 register["VC"] = arm64.COND_VC 266 register["HI"] = arm64.COND_HI 267 register["LS"] = arm64.COND_LS 268 register["GE"] = arm64.COND_GE 269 register["LT"] = arm64.COND_LT 270 register["GT"] = arm64.COND_GT 271 register["LE"] = arm64.COND_LE 272 register["AL"] = arm64.COND_AL 273 register["NV"] = arm64.COND_NV 274 // Pseudo-registers. 275 register["SB"] = RSB 276 register["FP"] = RFP 277 register["PC"] = RPC 278 register["SP"] = RSP 279 // Avoid unintentionally clobbering g using R28. 280 delete(register, "R28") 281 register["g"] = arm64.REG_R28 282 registerPrefix := map[string]bool{ 283 "F": true, 284 "R": true, 285 "V": true, 286 } 287 288 instructions := make(map[string]obj.As) 289 for i, s := range obj.Anames { 290 instructions[s] = obj.As(i) 291 } 292 for i, s := range arm64.Anames { 293 if obj.As(i) >= obj.A_ARCHSPECIFIC { 294 instructions[s] = obj.As(i) + obj.ABaseARM64 295 } 296 } 297 // Annoying aliases. 298 instructions["B"] = arm64.AB 299 instructions["BL"] = arm64.ABL 300 301 return &Arch{ 302 LinkArch: &arm64.Linkarm64, 303 Instructions: instructions, 304 Register: register, 305 RegisterPrefix: registerPrefix, 306 RegisterNumber: arm64RegisterNumber, 307 IsJump: jumpArm64, 308 } 309 310 } 311 312 func archPPC64() *Arch { 313 register := make(map[string]int16) 314 // Create maps for easy lookup of instruction names etc. 315 // Note that there is no list of names as there is for x86. 316 for i := ppc64.REG_R0; i <= ppc64.REG_R31; i++ { 317 register[obj.Rconv(i)] = int16(i) 318 } 319 for i := ppc64.REG_F0; i <= ppc64.REG_F31; i++ { 320 register[obj.Rconv(i)] = int16(i) 321 } 322 for i := ppc64.REG_V0; i <= ppc64.REG_V31; i++ { 323 register[obj.Rconv(i)] = int16(i) 324 } 325 for i := ppc64.REG_VS0; i <= ppc64.REG_VS63; i++ { 326 register[obj.Rconv(i)] = int16(i) 327 } 328 for i := ppc64.REG_CR0; i <= ppc64.REG_CR7; i++ { 329 register[obj.Rconv(i)] = int16(i) 330 } 331 for i := ppc64.REG_MSR; i <= ppc64.REG_CR; i++ { 332 register[obj.Rconv(i)] = int16(i) 333 } 334 register["CR"] = ppc64.REG_CR 335 register["XER"] = ppc64.REG_XER 336 register["LR"] = ppc64.REG_LR 337 register["CTR"] = ppc64.REG_CTR 338 register["FPSCR"] = ppc64.REG_FPSCR 339 register["MSR"] = ppc64.REG_MSR 340 // Pseudo-registers. 341 register["SB"] = RSB 342 register["FP"] = RFP 343 register["PC"] = RPC 344 // Avoid unintentionally clobbering g using R30. 345 delete(register, "R30") 346 register["g"] = ppc64.REG_R30 347 registerPrefix := map[string]bool{ 348 "CR": true, 349 "F": true, 350 "R": true, 351 "SPR": true, 352 } 353 354 instructions := make(map[string]obj.As) 355 for i, s := range obj.Anames { 356 instructions[s] = obj.As(i) 357 } 358 for i, s := range ppc64.Anames { 359 if obj.As(i) >= obj.A_ARCHSPECIFIC { 360 instructions[s] = obj.As(i) + obj.ABasePPC64 361 } 362 } 363 // Annoying aliases. 364 instructions["BR"] = ppc64.ABR 365 instructions["BL"] = ppc64.ABL 366 367 return &Arch{ 368 LinkArch: &ppc64.Linkppc64, 369 Instructions: instructions, 370 Register: register, 371 RegisterPrefix: registerPrefix, 372 RegisterNumber: ppc64RegisterNumber, 373 IsJump: jumpPPC64, 374 } 375 } 376 377 func archMips64() *Arch { 378 register := make(map[string]int16) 379 // Create maps for easy lookup of instruction names etc. 380 // Note that there is no list of names as there is for x86. 381 for i := mips.REG_R0; i <= mips.REG_R31; i++ { 382 register[obj.Rconv(i)] = int16(i) 383 } 384 for i := mips.REG_F0; i <= mips.REG_F31; i++ { 385 register[obj.Rconv(i)] = int16(i) 386 } 387 for i := mips.REG_M0; i <= mips.REG_M31; i++ { 388 register[obj.Rconv(i)] = int16(i) 389 } 390 for i := mips.REG_FCR0; i <= mips.REG_FCR31; i++ { 391 register[obj.Rconv(i)] = int16(i) 392 } 393 register["HI"] = mips.REG_HI 394 register["LO"] = mips.REG_LO 395 // Pseudo-registers. 396 register["SB"] = RSB 397 register["FP"] = RFP 398 register["PC"] = RPC 399 // Avoid unintentionally clobbering g using R30. 400 delete(register, "R30") 401 register["g"] = mips.REG_R30 402 // Avoid unintentionally clobbering RSB using R28. 403 delete(register, "R28") 404 register["RSB"] = mips.REG_R28 405 registerPrefix := map[string]bool{ 406 "F": true, 407 "FCR": true, 408 "M": true, 409 "R": true, 410 } 411 412 instructions := make(map[string]obj.As) 413 for i, s := range obj.Anames { 414 instructions[s] = obj.As(i) 415 } 416 for i, s := range mips.Anames { 417 if obj.As(i) >= obj.A_ARCHSPECIFIC { 418 instructions[s] = obj.As(i) + obj.ABaseMIPS64 419 } 420 } 421 // Annoying alias. 422 instructions["JAL"] = mips.AJAL 423 424 return &Arch{ 425 LinkArch: &mips.Linkmips64, 426 Instructions: instructions, 427 Register: register, 428 RegisterPrefix: registerPrefix, 429 RegisterNumber: mipsRegisterNumber, 430 IsJump: jumpMIPS64, 431 } 432 } 433 434 func archS390x() *Arch { 435 register := make(map[string]int16) 436 // Create maps for easy lookup of instruction names etc. 437 // Note that there is no list of names as there is for x86. 438 for i := s390x.REG_R0; i <= s390x.REG_R15; i++ { 439 register[obj.Rconv(i)] = int16(i) 440 } 441 for i := s390x.REG_F0; i <= s390x.REG_F15; i++ { 442 register[obj.Rconv(i)] = int16(i) 443 } 444 for i := s390x.REG_V0; i <= s390x.REG_V31; i++ { 445 register[obj.Rconv(i)] = int16(i) 446 } 447 for i := s390x.REG_AR0; i <= s390x.REG_AR15; i++ { 448 register[obj.Rconv(i)] = int16(i) 449 } 450 register["LR"] = s390x.REG_LR 451 // Pseudo-registers. 452 register["SB"] = RSB 453 register["FP"] = RFP 454 register["PC"] = RPC 455 // Avoid unintentionally clobbering g using R13. 456 delete(register, "R13") 457 register["g"] = s390x.REG_R13 458 registerPrefix := map[string]bool{ 459 "AR": true, 460 "F": true, 461 "R": true, 462 } 463 464 instructions := make(map[string]obj.As) 465 for i, s := range obj.Anames { 466 instructions[s] = obj.As(i) 467 } 468 for i, s := range s390x.Anames { 469 if obj.As(i) >= obj.A_ARCHSPECIFIC { 470 instructions[s] = obj.As(i) + obj.ABaseS390X 471 } 472 } 473 // Annoying aliases. 474 instructions["BR"] = s390x.ABR 475 instructions["BL"] = s390x.ABL 476 477 return &Arch{ 478 LinkArch: &s390x.Links390x, 479 Instructions: instructions, 480 Register: register, 481 RegisterPrefix: registerPrefix, 482 RegisterNumber: s390xRegisterNumber, 483 IsJump: jumpS390x, 484 } 485 }