github.com/panjjo/go@v0.0.0-20161104043856-d62b31386338/src/cmd/compile/internal/ssa/opGen.go (about) 1 // autogenerated: do not edit! 2 // generated from gen/*Ops.go 3 4 package ssa 5 6 import ( 7 "cmd/internal/obj" 8 "cmd/internal/obj/arm" 9 "cmd/internal/obj/arm64" 10 "cmd/internal/obj/mips" 11 "cmd/internal/obj/ppc64" 12 "cmd/internal/obj/s390x" 13 "cmd/internal/obj/x86" 14 ) 15 16 const ( 17 BlockInvalid BlockKind = iota 18 19 Block386EQ 20 Block386NE 21 Block386LT 22 Block386LE 23 Block386GT 24 Block386GE 25 Block386ULT 26 Block386ULE 27 Block386UGT 28 Block386UGE 29 Block386EQF 30 Block386NEF 31 Block386ORD 32 Block386NAN 33 34 BlockAMD64EQ 35 BlockAMD64NE 36 BlockAMD64LT 37 BlockAMD64LE 38 BlockAMD64GT 39 BlockAMD64GE 40 BlockAMD64ULT 41 BlockAMD64ULE 42 BlockAMD64UGT 43 BlockAMD64UGE 44 BlockAMD64EQF 45 BlockAMD64NEF 46 BlockAMD64ORD 47 BlockAMD64NAN 48 49 BlockARMEQ 50 BlockARMNE 51 BlockARMLT 52 BlockARMLE 53 BlockARMGT 54 BlockARMGE 55 BlockARMULT 56 BlockARMULE 57 BlockARMUGT 58 BlockARMUGE 59 60 BlockARM64EQ 61 BlockARM64NE 62 BlockARM64LT 63 BlockARM64LE 64 BlockARM64GT 65 BlockARM64GE 66 BlockARM64ULT 67 BlockARM64ULE 68 BlockARM64UGT 69 BlockARM64UGE 70 BlockARM64Z 71 BlockARM64NZ 72 BlockARM64ZW 73 BlockARM64NZW 74 75 BlockMIPS64EQ 76 BlockMIPS64NE 77 BlockMIPS64LTZ 78 BlockMIPS64LEZ 79 BlockMIPS64GTZ 80 BlockMIPS64GEZ 81 BlockMIPS64FPT 82 BlockMIPS64FPF 83 84 BlockPPC64EQ 85 BlockPPC64NE 86 BlockPPC64LT 87 BlockPPC64LE 88 BlockPPC64GT 89 BlockPPC64GE 90 BlockPPC64FLT 91 BlockPPC64FLE 92 BlockPPC64FGT 93 BlockPPC64FGE 94 95 BlockS390XEQ 96 BlockS390XNE 97 BlockS390XLT 98 BlockS390XLE 99 BlockS390XGT 100 BlockS390XGE 101 BlockS390XGTF 102 BlockS390XGEF 103 104 BlockPlain 105 BlockIf 106 BlockDefer 107 BlockRet 108 BlockRetJmp 109 BlockExit 110 BlockFirst 111 ) 112 113 var blockString = [...]string{ 114 BlockInvalid: "BlockInvalid", 115 116 Block386EQ: "EQ", 117 Block386NE: "NE", 118 Block386LT: "LT", 119 Block386LE: "LE", 120 Block386GT: "GT", 121 Block386GE: "GE", 122 Block386ULT: "ULT", 123 Block386ULE: "ULE", 124 Block386UGT: "UGT", 125 Block386UGE: "UGE", 126 Block386EQF: "EQF", 127 Block386NEF: "NEF", 128 Block386ORD: "ORD", 129 Block386NAN: "NAN", 130 131 BlockAMD64EQ: "EQ", 132 BlockAMD64NE: "NE", 133 BlockAMD64LT: "LT", 134 BlockAMD64LE: "LE", 135 BlockAMD64GT: "GT", 136 BlockAMD64GE: "GE", 137 BlockAMD64ULT: "ULT", 138 BlockAMD64ULE: "ULE", 139 BlockAMD64UGT: "UGT", 140 BlockAMD64UGE: "UGE", 141 BlockAMD64EQF: "EQF", 142 BlockAMD64NEF: "NEF", 143 BlockAMD64ORD: "ORD", 144 BlockAMD64NAN: "NAN", 145 146 BlockARMEQ: "EQ", 147 BlockARMNE: "NE", 148 BlockARMLT: "LT", 149 BlockARMLE: "LE", 150 BlockARMGT: "GT", 151 BlockARMGE: "GE", 152 BlockARMULT: "ULT", 153 BlockARMULE: "ULE", 154 BlockARMUGT: "UGT", 155 BlockARMUGE: "UGE", 156 157 BlockARM64EQ: "EQ", 158 BlockARM64NE: "NE", 159 BlockARM64LT: "LT", 160 BlockARM64LE: "LE", 161 BlockARM64GT: "GT", 162 BlockARM64GE: "GE", 163 BlockARM64ULT: "ULT", 164 BlockARM64ULE: "ULE", 165 BlockARM64UGT: "UGT", 166 BlockARM64UGE: "UGE", 167 BlockARM64Z: "Z", 168 BlockARM64NZ: "NZ", 169 BlockARM64ZW: "ZW", 170 BlockARM64NZW: "NZW", 171 172 BlockMIPS64EQ: "EQ", 173 BlockMIPS64NE: "NE", 174 BlockMIPS64LTZ: "LTZ", 175 BlockMIPS64LEZ: "LEZ", 176 BlockMIPS64GTZ: "GTZ", 177 BlockMIPS64GEZ: "GEZ", 178 BlockMIPS64FPT: "FPT", 179 BlockMIPS64FPF: "FPF", 180 181 BlockPPC64EQ: "EQ", 182 BlockPPC64NE: "NE", 183 BlockPPC64LT: "LT", 184 BlockPPC64LE: "LE", 185 BlockPPC64GT: "GT", 186 BlockPPC64GE: "GE", 187 BlockPPC64FLT: "FLT", 188 BlockPPC64FLE: "FLE", 189 BlockPPC64FGT: "FGT", 190 BlockPPC64FGE: "FGE", 191 192 BlockS390XEQ: "EQ", 193 BlockS390XNE: "NE", 194 BlockS390XLT: "LT", 195 BlockS390XLE: "LE", 196 BlockS390XGT: "GT", 197 BlockS390XGE: "GE", 198 BlockS390XGTF: "GTF", 199 BlockS390XGEF: "GEF", 200 201 BlockPlain: "Plain", 202 BlockIf: "If", 203 BlockDefer: "Defer", 204 BlockRet: "Ret", 205 BlockRetJmp: "RetJmp", 206 BlockExit: "Exit", 207 BlockFirst: "First", 208 } 209 210 func (k BlockKind) String() string { return blockString[k] } 211 212 const ( 213 OpInvalid Op = iota 214 215 Op386ADDSS 216 Op386ADDSD 217 Op386SUBSS 218 Op386SUBSD 219 Op386MULSS 220 Op386MULSD 221 Op386DIVSS 222 Op386DIVSD 223 Op386MOVSSload 224 Op386MOVSDload 225 Op386MOVSSconst 226 Op386MOVSDconst 227 Op386MOVSSloadidx1 228 Op386MOVSSloadidx4 229 Op386MOVSDloadidx1 230 Op386MOVSDloadidx8 231 Op386MOVSSstore 232 Op386MOVSDstore 233 Op386MOVSSstoreidx1 234 Op386MOVSSstoreidx4 235 Op386MOVSDstoreidx1 236 Op386MOVSDstoreidx8 237 Op386ADDL 238 Op386ADDLconst 239 Op386ADDLcarry 240 Op386ADDLconstcarry 241 Op386ADCL 242 Op386ADCLconst 243 Op386SUBL 244 Op386SUBLconst 245 Op386SUBLcarry 246 Op386SUBLconstcarry 247 Op386SBBL 248 Op386SBBLconst 249 Op386MULL 250 Op386MULLconst 251 Op386HMULL 252 Op386HMULLU 253 Op386HMULW 254 Op386HMULB 255 Op386HMULWU 256 Op386HMULBU 257 Op386MULLQU 258 Op386DIVL 259 Op386DIVW 260 Op386DIVLU 261 Op386DIVWU 262 Op386MODL 263 Op386MODW 264 Op386MODLU 265 Op386MODWU 266 Op386ANDL 267 Op386ANDLconst 268 Op386ORL 269 Op386ORLconst 270 Op386XORL 271 Op386XORLconst 272 Op386CMPL 273 Op386CMPW 274 Op386CMPB 275 Op386CMPLconst 276 Op386CMPWconst 277 Op386CMPBconst 278 Op386UCOMISS 279 Op386UCOMISD 280 Op386TESTL 281 Op386TESTW 282 Op386TESTB 283 Op386TESTLconst 284 Op386TESTWconst 285 Op386TESTBconst 286 Op386SHLL 287 Op386SHLLconst 288 Op386SHRL 289 Op386SHRW 290 Op386SHRB 291 Op386SHRLconst 292 Op386SHRWconst 293 Op386SHRBconst 294 Op386SARL 295 Op386SARW 296 Op386SARB 297 Op386SARLconst 298 Op386SARWconst 299 Op386SARBconst 300 Op386ROLLconst 301 Op386ROLWconst 302 Op386ROLBconst 303 Op386NEGL 304 Op386NOTL 305 Op386BSFL 306 Op386BSFW 307 Op386BSRL 308 Op386BSRW 309 Op386BSWAPL 310 Op386SQRTSD 311 Op386SBBLcarrymask 312 Op386SETEQ 313 Op386SETNE 314 Op386SETL 315 Op386SETLE 316 Op386SETG 317 Op386SETGE 318 Op386SETB 319 Op386SETBE 320 Op386SETA 321 Op386SETAE 322 Op386SETEQF 323 Op386SETNEF 324 Op386SETORD 325 Op386SETNAN 326 Op386SETGF 327 Op386SETGEF 328 Op386MOVBLSX 329 Op386MOVBLZX 330 Op386MOVWLSX 331 Op386MOVWLZX 332 Op386MOVLconst 333 Op386CVTTSD2SL 334 Op386CVTTSS2SL 335 Op386CVTSL2SS 336 Op386CVTSL2SD 337 Op386CVTSD2SS 338 Op386CVTSS2SD 339 Op386PXOR 340 Op386LEAL 341 Op386LEAL1 342 Op386LEAL2 343 Op386LEAL4 344 Op386LEAL8 345 Op386MOVBload 346 Op386MOVBLSXload 347 Op386MOVWload 348 Op386MOVWLSXload 349 Op386MOVLload 350 Op386MOVBstore 351 Op386MOVWstore 352 Op386MOVLstore 353 Op386MOVBloadidx1 354 Op386MOVWloadidx1 355 Op386MOVWloadidx2 356 Op386MOVLloadidx1 357 Op386MOVLloadidx4 358 Op386MOVBstoreidx1 359 Op386MOVWstoreidx1 360 Op386MOVWstoreidx2 361 Op386MOVLstoreidx1 362 Op386MOVLstoreidx4 363 Op386MOVBstoreconst 364 Op386MOVWstoreconst 365 Op386MOVLstoreconst 366 Op386MOVBstoreconstidx1 367 Op386MOVWstoreconstidx1 368 Op386MOVWstoreconstidx2 369 Op386MOVLstoreconstidx1 370 Op386MOVLstoreconstidx4 371 Op386DUFFZERO 372 Op386REPSTOSL 373 Op386CALLstatic 374 Op386CALLclosure 375 Op386CALLdefer 376 Op386CALLgo 377 Op386CALLinter 378 Op386DUFFCOPY 379 Op386REPMOVSL 380 Op386InvertFlags 381 Op386LoweredGetG 382 Op386LoweredGetClosurePtr 383 Op386LoweredNilCheck 384 Op386MOVLconvert 385 Op386FlagEQ 386 Op386FlagLT_ULT 387 Op386FlagLT_UGT 388 Op386FlagGT_UGT 389 Op386FlagGT_ULT 390 Op386FCHS 391 Op386MOVSSconst1 392 Op386MOVSDconst1 393 Op386MOVSSconst2 394 Op386MOVSDconst2 395 396 OpAMD64ADDSS 397 OpAMD64ADDSD 398 OpAMD64SUBSS 399 OpAMD64SUBSD 400 OpAMD64MULSS 401 OpAMD64MULSD 402 OpAMD64DIVSS 403 OpAMD64DIVSD 404 OpAMD64MOVSSload 405 OpAMD64MOVSDload 406 OpAMD64MOVSSconst 407 OpAMD64MOVSDconst 408 OpAMD64MOVSSloadidx1 409 OpAMD64MOVSSloadidx4 410 OpAMD64MOVSDloadidx1 411 OpAMD64MOVSDloadidx8 412 OpAMD64MOVSSstore 413 OpAMD64MOVSDstore 414 OpAMD64MOVSSstoreidx1 415 OpAMD64MOVSSstoreidx4 416 OpAMD64MOVSDstoreidx1 417 OpAMD64MOVSDstoreidx8 418 OpAMD64ADDQ 419 OpAMD64ADDL 420 OpAMD64ADDQconst 421 OpAMD64ADDLconst 422 OpAMD64SUBQ 423 OpAMD64SUBL 424 OpAMD64SUBQconst 425 OpAMD64SUBLconst 426 OpAMD64MULQ 427 OpAMD64MULL 428 OpAMD64MULQconst 429 OpAMD64MULLconst 430 OpAMD64HMULQ 431 OpAMD64HMULL 432 OpAMD64HMULW 433 OpAMD64HMULB 434 OpAMD64HMULQU 435 OpAMD64HMULLU 436 OpAMD64HMULWU 437 OpAMD64HMULBU 438 OpAMD64AVGQU 439 OpAMD64DIVQ 440 OpAMD64DIVL 441 OpAMD64DIVW 442 OpAMD64DIVQU 443 OpAMD64DIVLU 444 OpAMD64DIVWU 445 OpAMD64MULQU2 446 OpAMD64DIVQU2 447 OpAMD64ANDQ 448 OpAMD64ANDL 449 OpAMD64ANDQconst 450 OpAMD64ANDLconst 451 OpAMD64ORQ 452 OpAMD64ORL 453 OpAMD64ORQconst 454 OpAMD64ORLconst 455 OpAMD64XORQ 456 OpAMD64XORL 457 OpAMD64XORQconst 458 OpAMD64XORLconst 459 OpAMD64CMPQ 460 OpAMD64CMPL 461 OpAMD64CMPW 462 OpAMD64CMPB 463 OpAMD64CMPQconst 464 OpAMD64CMPLconst 465 OpAMD64CMPWconst 466 OpAMD64CMPBconst 467 OpAMD64UCOMISS 468 OpAMD64UCOMISD 469 OpAMD64TESTQ 470 OpAMD64TESTL 471 OpAMD64TESTW 472 OpAMD64TESTB 473 OpAMD64TESTQconst 474 OpAMD64TESTLconst 475 OpAMD64TESTWconst 476 OpAMD64TESTBconst 477 OpAMD64SHLQ 478 OpAMD64SHLL 479 OpAMD64SHLQconst 480 OpAMD64SHLLconst 481 OpAMD64SHRQ 482 OpAMD64SHRL 483 OpAMD64SHRW 484 OpAMD64SHRB 485 OpAMD64SHRQconst 486 OpAMD64SHRLconst 487 OpAMD64SHRWconst 488 OpAMD64SHRBconst 489 OpAMD64SARQ 490 OpAMD64SARL 491 OpAMD64SARW 492 OpAMD64SARB 493 OpAMD64SARQconst 494 OpAMD64SARLconst 495 OpAMD64SARWconst 496 OpAMD64SARBconst 497 OpAMD64ROLQconst 498 OpAMD64ROLLconst 499 OpAMD64ROLWconst 500 OpAMD64ROLBconst 501 OpAMD64NEGQ 502 OpAMD64NEGL 503 OpAMD64NOTQ 504 OpAMD64NOTL 505 OpAMD64BSFQ 506 OpAMD64BSFL 507 OpAMD64CMOVQEQ 508 OpAMD64CMOVLEQ 509 OpAMD64BSWAPQ 510 OpAMD64BSWAPL 511 OpAMD64SQRTSD 512 OpAMD64SBBQcarrymask 513 OpAMD64SBBLcarrymask 514 OpAMD64SETEQ 515 OpAMD64SETNE 516 OpAMD64SETL 517 OpAMD64SETLE 518 OpAMD64SETG 519 OpAMD64SETGE 520 OpAMD64SETB 521 OpAMD64SETBE 522 OpAMD64SETA 523 OpAMD64SETAE 524 OpAMD64SETEQF 525 OpAMD64SETNEF 526 OpAMD64SETORD 527 OpAMD64SETNAN 528 OpAMD64SETGF 529 OpAMD64SETGEF 530 OpAMD64MOVBQSX 531 OpAMD64MOVBQZX 532 OpAMD64MOVWQSX 533 OpAMD64MOVWQZX 534 OpAMD64MOVLQSX 535 OpAMD64MOVLQZX 536 OpAMD64MOVLconst 537 OpAMD64MOVQconst 538 OpAMD64CVTTSD2SL 539 OpAMD64CVTTSD2SQ 540 OpAMD64CVTTSS2SL 541 OpAMD64CVTTSS2SQ 542 OpAMD64CVTSL2SS 543 OpAMD64CVTSL2SD 544 OpAMD64CVTSQ2SS 545 OpAMD64CVTSQ2SD 546 OpAMD64CVTSD2SS 547 OpAMD64CVTSS2SD 548 OpAMD64PXOR 549 OpAMD64LEAQ 550 OpAMD64LEAQ1 551 OpAMD64LEAQ2 552 OpAMD64LEAQ4 553 OpAMD64LEAQ8 554 OpAMD64LEAL 555 OpAMD64MOVBload 556 OpAMD64MOVBQSXload 557 OpAMD64MOVWload 558 OpAMD64MOVWQSXload 559 OpAMD64MOVLload 560 OpAMD64MOVLQSXload 561 OpAMD64MOVQload 562 OpAMD64MOVBstore 563 OpAMD64MOVWstore 564 OpAMD64MOVLstore 565 OpAMD64MOVQstore 566 OpAMD64MOVOload 567 OpAMD64MOVOstore 568 OpAMD64MOVBloadidx1 569 OpAMD64MOVWloadidx1 570 OpAMD64MOVWloadidx2 571 OpAMD64MOVLloadidx1 572 OpAMD64MOVLloadidx4 573 OpAMD64MOVQloadidx1 574 OpAMD64MOVQloadidx8 575 OpAMD64MOVBstoreidx1 576 OpAMD64MOVWstoreidx1 577 OpAMD64MOVWstoreidx2 578 OpAMD64MOVLstoreidx1 579 OpAMD64MOVLstoreidx4 580 OpAMD64MOVQstoreidx1 581 OpAMD64MOVQstoreidx8 582 OpAMD64MOVBstoreconst 583 OpAMD64MOVWstoreconst 584 OpAMD64MOVLstoreconst 585 OpAMD64MOVQstoreconst 586 OpAMD64MOVBstoreconstidx1 587 OpAMD64MOVWstoreconstidx1 588 OpAMD64MOVWstoreconstidx2 589 OpAMD64MOVLstoreconstidx1 590 OpAMD64MOVLstoreconstidx4 591 OpAMD64MOVQstoreconstidx1 592 OpAMD64MOVQstoreconstidx8 593 OpAMD64DUFFZERO 594 OpAMD64MOVOconst 595 OpAMD64REPSTOSQ 596 OpAMD64CALLstatic 597 OpAMD64CALLclosure 598 OpAMD64CALLdefer 599 OpAMD64CALLgo 600 OpAMD64CALLinter 601 OpAMD64DUFFCOPY 602 OpAMD64REPMOVSQ 603 OpAMD64InvertFlags 604 OpAMD64LoweredGetG 605 OpAMD64LoweredGetClosurePtr 606 OpAMD64LoweredNilCheck 607 OpAMD64MOVQconvert 608 OpAMD64MOVLconvert 609 OpAMD64FlagEQ 610 OpAMD64FlagLT_ULT 611 OpAMD64FlagLT_UGT 612 OpAMD64FlagGT_UGT 613 OpAMD64FlagGT_ULT 614 OpAMD64MOVLatomicload 615 OpAMD64MOVQatomicload 616 OpAMD64XCHGL 617 OpAMD64XCHGQ 618 OpAMD64XADDLlock 619 OpAMD64XADDQlock 620 OpAMD64AddTupleFirst32 621 OpAMD64AddTupleFirst64 622 OpAMD64CMPXCHGLlock 623 OpAMD64CMPXCHGQlock 624 OpAMD64ANDBlock 625 OpAMD64ORBlock 626 627 OpARMADD 628 OpARMADDconst 629 OpARMSUB 630 OpARMSUBconst 631 OpARMRSB 632 OpARMRSBconst 633 OpARMMUL 634 OpARMHMUL 635 OpARMHMULU 636 OpARMUDIVrtcall 637 OpARMADDS 638 OpARMADDSconst 639 OpARMADC 640 OpARMADCconst 641 OpARMSUBS 642 OpARMSUBSconst 643 OpARMRSBSconst 644 OpARMSBC 645 OpARMSBCconst 646 OpARMRSCconst 647 OpARMMULLU 648 OpARMMULA 649 OpARMADDF 650 OpARMADDD 651 OpARMSUBF 652 OpARMSUBD 653 OpARMMULF 654 OpARMMULD 655 OpARMDIVF 656 OpARMDIVD 657 OpARMAND 658 OpARMANDconst 659 OpARMOR 660 OpARMORconst 661 OpARMXOR 662 OpARMXORconst 663 OpARMBIC 664 OpARMBICconst 665 OpARMMVN 666 OpARMNEGF 667 OpARMNEGD 668 OpARMSQRTD 669 OpARMCLZ 670 OpARMSLL 671 OpARMSLLconst 672 OpARMSRL 673 OpARMSRLconst 674 OpARMSRA 675 OpARMSRAconst 676 OpARMSRRconst 677 OpARMADDshiftLL 678 OpARMADDshiftRL 679 OpARMADDshiftRA 680 OpARMSUBshiftLL 681 OpARMSUBshiftRL 682 OpARMSUBshiftRA 683 OpARMRSBshiftLL 684 OpARMRSBshiftRL 685 OpARMRSBshiftRA 686 OpARMANDshiftLL 687 OpARMANDshiftRL 688 OpARMANDshiftRA 689 OpARMORshiftLL 690 OpARMORshiftRL 691 OpARMORshiftRA 692 OpARMXORshiftLL 693 OpARMXORshiftRL 694 OpARMXORshiftRA 695 OpARMXORshiftRR 696 OpARMBICshiftLL 697 OpARMBICshiftRL 698 OpARMBICshiftRA 699 OpARMMVNshiftLL 700 OpARMMVNshiftRL 701 OpARMMVNshiftRA 702 OpARMADCshiftLL 703 OpARMADCshiftRL 704 OpARMADCshiftRA 705 OpARMSBCshiftLL 706 OpARMSBCshiftRL 707 OpARMSBCshiftRA 708 OpARMRSCshiftLL 709 OpARMRSCshiftRL 710 OpARMRSCshiftRA 711 OpARMADDSshiftLL 712 OpARMADDSshiftRL 713 OpARMADDSshiftRA 714 OpARMSUBSshiftLL 715 OpARMSUBSshiftRL 716 OpARMSUBSshiftRA 717 OpARMRSBSshiftLL 718 OpARMRSBSshiftRL 719 OpARMRSBSshiftRA 720 OpARMADDshiftLLreg 721 OpARMADDshiftRLreg 722 OpARMADDshiftRAreg 723 OpARMSUBshiftLLreg 724 OpARMSUBshiftRLreg 725 OpARMSUBshiftRAreg 726 OpARMRSBshiftLLreg 727 OpARMRSBshiftRLreg 728 OpARMRSBshiftRAreg 729 OpARMANDshiftLLreg 730 OpARMANDshiftRLreg 731 OpARMANDshiftRAreg 732 OpARMORshiftLLreg 733 OpARMORshiftRLreg 734 OpARMORshiftRAreg 735 OpARMXORshiftLLreg 736 OpARMXORshiftRLreg 737 OpARMXORshiftRAreg 738 OpARMBICshiftLLreg 739 OpARMBICshiftRLreg 740 OpARMBICshiftRAreg 741 OpARMMVNshiftLLreg 742 OpARMMVNshiftRLreg 743 OpARMMVNshiftRAreg 744 OpARMADCshiftLLreg 745 OpARMADCshiftRLreg 746 OpARMADCshiftRAreg 747 OpARMSBCshiftLLreg 748 OpARMSBCshiftRLreg 749 OpARMSBCshiftRAreg 750 OpARMRSCshiftLLreg 751 OpARMRSCshiftRLreg 752 OpARMRSCshiftRAreg 753 OpARMADDSshiftLLreg 754 OpARMADDSshiftRLreg 755 OpARMADDSshiftRAreg 756 OpARMSUBSshiftLLreg 757 OpARMSUBSshiftRLreg 758 OpARMSUBSshiftRAreg 759 OpARMRSBSshiftLLreg 760 OpARMRSBSshiftRLreg 761 OpARMRSBSshiftRAreg 762 OpARMCMP 763 OpARMCMPconst 764 OpARMCMN 765 OpARMCMNconst 766 OpARMTST 767 OpARMTSTconst 768 OpARMTEQ 769 OpARMTEQconst 770 OpARMCMPF 771 OpARMCMPD 772 OpARMCMPshiftLL 773 OpARMCMPshiftRL 774 OpARMCMPshiftRA 775 OpARMCMPshiftLLreg 776 OpARMCMPshiftRLreg 777 OpARMCMPshiftRAreg 778 OpARMCMPF0 779 OpARMCMPD0 780 OpARMMOVWconst 781 OpARMMOVFconst 782 OpARMMOVDconst 783 OpARMMOVWaddr 784 OpARMMOVBload 785 OpARMMOVBUload 786 OpARMMOVHload 787 OpARMMOVHUload 788 OpARMMOVWload 789 OpARMMOVFload 790 OpARMMOVDload 791 OpARMMOVBstore 792 OpARMMOVHstore 793 OpARMMOVWstore 794 OpARMMOVFstore 795 OpARMMOVDstore 796 OpARMMOVWloadidx 797 OpARMMOVWloadshiftLL 798 OpARMMOVWloadshiftRL 799 OpARMMOVWloadshiftRA 800 OpARMMOVWstoreidx 801 OpARMMOVWstoreshiftLL 802 OpARMMOVWstoreshiftRL 803 OpARMMOVWstoreshiftRA 804 OpARMMOVBreg 805 OpARMMOVBUreg 806 OpARMMOVHreg 807 OpARMMOVHUreg 808 OpARMMOVWreg 809 OpARMMOVWnop 810 OpARMMOVWF 811 OpARMMOVWD 812 OpARMMOVWUF 813 OpARMMOVWUD 814 OpARMMOVFW 815 OpARMMOVDW 816 OpARMMOVFWU 817 OpARMMOVDWU 818 OpARMMOVFD 819 OpARMMOVDF 820 OpARMCMOVWHSconst 821 OpARMCMOVWLSconst 822 OpARMSRAcond 823 OpARMCALLstatic 824 OpARMCALLclosure 825 OpARMCALLdefer 826 OpARMCALLgo 827 OpARMCALLinter 828 OpARMLoweredNilCheck 829 OpARMEqual 830 OpARMNotEqual 831 OpARMLessThan 832 OpARMLessEqual 833 OpARMGreaterThan 834 OpARMGreaterEqual 835 OpARMLessThanU 836 OpARMLessEqualU 837 OpARMGreaterThanU 838 OpARMGreaterEqualU 839 OpARMDUFFZERO 840 OpARMDUFFCOPY 841 OpARMLoweredZero 842 OpARMLoweredMove 843 OpARMLoweredGetClosurePtr 844 OpARMMOVWconvert 845 OpARMFlagEQ 846 OpARMFlagLT_ULT 847 OpARMFlagLT_UGT 848 OpARMFlagGT_UGT 849 OpARMFlagGT_ULT 850 OpARMInvertFlags 851 852 OpARM64ADD 853 OpARM64ADDconst 854 OpARM64SUB 855 OpARM64SUBconst 856 OpARM64MUL 857 OpARM64MULW 858 OpARM64MULH 859 OpARM64UMULH 860 OpARM64MULL 861 OpARM64UMULL 862 OpARM64DIV 863 OpARM64UDIV 864 OpARM64DIVW 865 OpARM64UDIVW 866 OpARM64MOD 867 OpARM64UMOD 868 OpARM64MODW 869 OpARM64UMODW 870 OpARM64FADDS 871 OpARM64FADDD 872 OpARM64FSUBS 873 OpARM64FSUBD 874 OpARM64FMULS 875 OpARM64FMULD 876 OpARM64FDIVS 877 OpARM64FDIVD 878 OpARM64AND 879 OpARM64ANDconst 880 OpARM64OR 881 OpARM64ORconst 882 OpARM64XOR 883 OpARM64XORconst 884 OpARM64BIC 885 OpARM64BICconst 886 OpARM64MVN 887 OpARM64NEG 888 OpARM64FNEGS 889 OpARM64FNEGD 890 OpARM64FSQRTD 891 OpARM64REV 892 OpARM64REVW 893 OpARM64REV16W 894 OpARM64RBIT 895 OpARM64RBITW 896 OpARM64CLZ 897 OpARM64CLZW 898 OpARM64SLL 899 OpARM64SLLconst 900 OpARM64SRL 901 OpARM64SRLconst 902 OpARM64SRA 903 OpARM64SRAconst 904 OpARM64RORconst 905 OpARM64RORWconst 906 OpARM64CMP 907 OpARM64CMPconst 908 OpARM64CMPW 909 OpARM64CMPWconst 910 OpARM64CMN 911 OpARM64CMNconst 912 OpARM64CMNW 913 OpARM64CMNWconst 914 OpARM64FCMPS 915 OpARM64FCMPD 916 OpARM64ADDshiftLL 917 OpARM64ADDshiftRL 918 OpARM64ADDshiftRA 919 OpARM64SUBshiftLL 920 OpARM64SUBshiftRL 921 OpARM64SUBshiftRA 922 OpARM64ANDshiftLL 923 OpARM64ANDshiftRL 924 OpARM64ANDshiftRA 925 OpARM64ORshiftLL 926 OpARM64ORshiftRL 927 OpARM64ORshiftRA 928 OpARM64XORshiftLL 929 OpARM64XORshiftRL 930 OpARM64XORshiftRA 931 OpARM64BICshiftLL 932 OpARM64BICshiftRL 933 OpARM64BICshiftRA 934 OpARM64CMPshiftLL 935 OpARM64CMPshiftRL 936 OpARM64CMPshiftRA 937 OpARM64MOVDconst 938 OpARM64FMOVSconst 939 OpARM64FMOVDconst 940 OpARM64MOVDaddr 941 OpARM64MOVBload 942 OpARM64MOVBUload 943 OpARM64MOVHload 944 OpARM64MOVHUload 945 OpARM64MOVWload 946 OpARM64MOVWUload 947 OpARM64MOVDload 948 OpARM64FMOVSload 949 OpARM64FMOVDload 950 OpARM64MOVBstore 951 OpARM64MOVHstore 952 OpARM64MOVWstore 953 OpARM64MOVDstore 954 OpARM64FMOVSstore 955 OpARM64FMOVDstore 956 OpARM64MOVBstorezero 957 OpARM64MOVHstorezero 958 OpARM64MOVWstorezero 959 OpARM64MOVDstorezero 960 OpARM64MOVBreg 961 OpARM64MOVBUreg 962 OpARM64MOVHreg 963 OpARM64MOVHUreg 964 OpARM64MOVWreg 965 OpARM64MOVWUreg 966 OpARM64MOVDreg 967 OpARM64MOVDnop 968 OpARM64SCVTFWS 969 OpARM64SCVTFWD 970 OpARM64UCVTFWS 971 OpARM64UCVTFWD 972 OpARM64SCVTFS 973 OpARM64SCVTFD 974 OpARM64UCVTFS 975 OpARM64UCVTFD 976 OpARM64FCVTZSSW 977 OpARM64FCVTZSDW 978 OpARM64FCVTZUSW 979 OpARM64FCVTZUDW 980 OpARM64FCVTZSS 981 OpARM64FCVTZSD 982 OpARM64FCVTZUS 983 OpARM64FCVTZUD 984 OpARM64FCVTSD 985 OpARM64FCVTDS 986 OpARM64CSELULT 987 OpARM64CSELULT0 988 OpARM64CALLstatic 989 OpARM64CALLclosure 990 OpARM64CALLdefer 991 OpARM64CALLgo 992 OpARM64CALLinter 993 OpARM64LoweredNilCheck 994 OpARM64Equal 995 OpARM64NotEqual 996 OpARM64LessThan 997 OpARM64LessEqual 998 OpARM64GreaterThan 999 OpARM64GreaterEqual 1000 OpARM64LessThanU 1001 OpARM64LessEqualU 1002 OpARM64GreaterThanU 1003 OpARM64GreaterEqualU 1004 OpARM64DUFFZERO 1005 OpARM64LoweredZero 1006 OpARM64DUFFCOPY 1007 OpARM64LoweredMove 1008 OpARM64LoweredGetClosurePtr 1009 OpARM64MOVDconvert 1010 OpARM64FlagEQ 1011 OpARM64FlagLT_ULT 1012 OpARM64FlagLT_UGT 1013 OpARM64FlagGT_UGT 1014 OpARM64FlagGT_ULT 1015 OpARM64InvertFlags 1016 OpARM64LDAR 1017 OpARM64LDARW 1018 OpARM64STLR 1019 OpARM64STLRW 1020 OpARM64LoweredAtomicExchange64 1021 OpARM64LoweredAtomicExchange32 1022 OpARM64LoweredAtomicAdd64 1023 OpARM64LoweredAtomicAdd32 1024 OpARM64LoweredAtomicCas64 1025 OpARM64LoweredAtomicCas32 1026 OpARM64LoweredAtomicAnd8 1027 OpARM64LoweredAtomicOr8 1028 1029 OpMIPS64ADDV 1030 OpMIPS64ADDVconst 1031 OpMIPS64SUBV 1032 OpMIPS64SUBVconst 1033 OpMIPS64MULV 1034 OpMIPS64MULVU 1035 OpMIPS64DIVV 1036 OpMIPS64DIVVU 1037 OpMIPS64ADDF 1038 OpMIPS64ADDD 1039 OpMIPS64SUBF 1040 OpMIPS64SUBD 1041 OpMIPS64MULF 1042 OpMIPS64MULD 1043 OpMIPS64DIVF 1044 OpMIPS64DIVD 1045 OpMIPS64AND 1046 OpMIPS64ANDconst 1047 OpMIPS64OR 1048 OpMIPS64ORconst 1049 OpMIPS64XOR 1050 OpMIPS64XORconst 1051 OpMIPS64NOR 1052 OpMIPS64NORconst 1053 OpMIPS64NEGV 1054 OpMIPS64NEGF 1055 OpMIPS64NEGD 1056 OpMIPS64SLLV 1057 OpMIPS64SLLVconst 1058 OpMIPS64SRLV 1059 OpMIPS64SRLVconst 1060 OpMIPS64SRAV 1061 OpMIPS64SRAVconst 1062 OpMIPS64SGT 1063 OpMIPS64SGTconst 1064 OpMIPS64SGTU 1065 OpMIPS64SGTUconst 1066 OpMIPS64CMPEQF 1067 OpMIPS64CMPEQD 1068 OpMIPS64CMPGEF 1069 OpMIPS64CMPGED 1070 OpMIPS64CMPGTF 1071 OpMIPS64CMPGTD 1072 OpMIPS64MOVVconst 1073 OpMIPS64MOVFconst 1074 OpMIPS64MOVDconst 1075 OpMIPS64MOVVaddr 1076 OpMIPS64MOVBload 1077 OpMIPS64MOVBUload 1078 OpMIPS64MOVHload 1079 OpMIPS64MOVHUload 1080 OpMIPS64MOVWload 1081 OpMIPS64MOVWUload 1082 OpMIPS64MOVVload 1083 OpMIPS64MOVFload 1084 OpMIPS64MOVDload 1085 OpMIPS64MOVBstore 1086 OpMIPS64MOVHstore 1087 OpMIPS64MOVWstore 1088 OpMIPS64MOVVstore 1089 OpMIPS64MOVFstore 1090 OpMIPS64MOVDstore 1091 OpMIPS64MOVBstorezero 1092 OpMIPS64MOVHstorezero 1093 OpMIPS64MOVWstorezero 1094 OpMIPS64MOVVstorezero 1095 OpMIPS64MOVBreg 1096 OpMIPS64MOVBUreg 1097 OpMIPS64MOVHreg 1098 OpMIPS64MOVHUreg 1099 OpMIPS64MOVWreg 1100 OpMIPS64MOVWUreg 1101 OpMIPS64MOVVreg 1102 OpMIPS64MOVVnop 1103 OpMIPS64MOVWF 1104 OpMIPS64MOVWD 1105 OpMIPS64MOVVF 1106 OpMIPS64MOVVD 1107 OpMIPS64TRUNCFW 1108 OpMIPS64TRUNCDW 1109 OpMIPS64TRUNCFV 1110 OpMIPS64TRUNCDV 1111 OpMIPS64MOVFD 1112 OpMIPS64MOVDF 1113 OpMIPS64CALLstatic 1114 OpMIPS64CALLclosure 1115 OpMIPS64CALLdefer 1116 OpMIPS64CALLgo 1117 OpMIPS64CALLinter 1118 OpMIPS64DUFFZERO 1119 OpMIPS64LoweredZero 1120 OpMIPS64LoweredMove 1121 OpMIPS64LoweredNilCheck 1122 OpMIPS64FPFlagTrue 1123 OpMIPS64FPFlagFalse 1124 OpMIPS64LoweredGetClosurePtr 1125 OpMIPS64MOVVconvert 1126 1127 OpPPC64ADD 1128 OpPPC64ADDconst 1129 OpPPC64FADD 1130 OpPPC64FADDS 1131 OpPPC64SUB 1132 OpPPC64FSUB 1133 OpPPC64FSUBS 1134 OpPPC64MULLD 1135 OpPPC64MULLW 1136 OpPPC64MULHD 1137 OpPPC64MULHW 1138 OpPPC64MULHDU 1139 OpPPC64MULHWU 1140 OpPPC64FMUL 1141 OpPPC64FMULS 1142 OpPPC64SRAD 1143 OpPPC64SRAW 1144 OpPPC64SRD 1145 OpPPC64SRW 1146 OpPPC64SLD 1147 OpPPC64SLW 1148 OpPPC64ADDconstForCarry 1149 OpPPC64MaskIfNotCarry 1150 OpPPC64SRADconst 1151 OpPPC64SRAWconst 1152 OpPPC64SRDconst 1153 OpPPC64SRWconst 1154 OpPPC64SLDconst 1155 OpPPC64SLWconst 1156 OpPPC64FDIV 1157 OpPPC64FDIVS 1158 OpPPC64DIVD 1159 OpPPC64DIVW 1160 OpPPC64DIVDU 1161 OpPPC64DIVWU 1162 OpPPC64FCTIDZ 1163 OpPPC64FCTIWZ 1164 OpPPC64FCFID 1165 OpPPC64FRSP 1166 OpPPC64Xf2i64 1167 OpPPC64Xi2f64 1168 OpPPC64AND 1169 OpPPC64ANDN 1170 OpPPC64OR 1171 OpPPC64ORN 1172 OpPPC64XOR 1173 OpPPC64EQV 1174 OpPPC64NEG 1175 OpPPC64FNEG 1176 OpPPC64FSQRT 1177 OpPPC64FSQRTS 1178 OpPPC64ORconst 1179 OpPPC64XORconst 1180 OpPPC64ANDconst 1181 OpPPC64ANDCCconst 1182 OpPPC64MOVBreg 1183 OpPPC64MOVBZreg 1184 OpPPC64MOVHreg 1185 OpPPC64MOVHZreg 1186 OpPPC64MOVWreg 1187 OpPPC64MOVWZreg 1188 OpPPC64MOVBZload 1189 OpPPC64MOVHload 1190 OpPPC64MOVHZload 1191 OpPPC64MOVWload 1192 OpPPC64MOVWZload 1193 OpPPC64MOVDload 1194 OpPPC64FMOVDload 1195 OpPPC64FMOVSload 1196 OpPPC64MOVBstore 1197 OpPPC64MOVHstore 1198 OpPPC64MOVWstore 1199 OpPPC64MOVDstore 1200 OpPPC64FMOVDstore 1201 OpPPC64FMOVSstore 1202 OpPPC64MOVBstorezero 1203 OpPPC64MOVHstorezero 1204 OpPPC64MOVWstorezero 1205 OpPPC64MOVDstorezero 1206 OpPPC64MOVDaddr 1207 OpPPC64MOVDconst 1208 OpPPC64FMOVDconst 1209 OpPPC64FMOVSconst 1210 OpPPC64FCMPU 1211 OpPPC64CMP 1212 OpPPC64CMPU 1213 OpPPC64CMPW 1214 OpPPC64CMPWU 1215 OpPPC64CMPconst 1216 OpPPC64CMPUconst 1217 OpPPC64CMPWconst 1218 OpPPC64CMPWUconst 1219 OpPPC64Equal 1220 OpPPC64NotEqual 1221 OpPPC64LessThan 1222 OpPPC64FLessThan 1223 OpPPC64LessEqual 1224 OpPPC64FLessEqual 1225 OpPPC64GreaterThan 1226 OpPPC64FGreaterThan 1227 OpPPC64GreaterEqual 1228 OpPPC64FGreaterEqual 1229 OpPPC64LoweredGetClosurePtr 1230 OpPPC64LoweredNilCheck 1231 OpPPC64MOVDconvert 1232 OpPPC64CALLstatic 1233 OpPPC64CALLclosure 1234 OpPPC64CALLdefer 1235 OpPPC64CALLgo 1236 OpPPC64CALLinter 1237 OpPPC64LoweredZero 1238 OpPPC64LoweredMove 1239 OpPPC64InvertFlags 1240 OpPPC64FlagEQ 1241 OpPPC64FlagLT 1242 OpPPC64FlagGT 1243 1244 OpS390XFADDS 1245 OpS390XFADD 1246 OpS390XFSUBS 1247 OpS390XFSUB 1248 OpS390XFMULS 1249 OpS390XFMUL 1250 OpS390XFDIVS 1251 OpS390XFDIV 1252 OpS390XFNEGS 1253 OpS390XFNEG 1254 OpS390XFMOVSload 1255 OpS390XFMOVDload 1256 OpS390XFMOVSconst 1257 OpS390XFMOVDconst 1258 OpS390XFMOVSloadidx 1259 OpS390XFMOVDloadidx 1260 OpS390XFMOVSstore 1261 OpS390XFMOVDstore 1262 OpS390XFMOVSstoreidx 1263 OpS390XFMOVDstoreidx 1264 OpS390XADD 1265 OpS390XADDW 1266 OpS390XADDconst 1267 OpS390XADDWconst 1268 OpS390XADDload 1269 OpS390XADDWload 1270 OpS390XSUB 1271 OpS390XSUBW 1272 OpS390XSUBconst 1273 OpS390XSUBWconst 1274 OpS390XSUBload 1275 OpS390XSUBWload 1276 OpS390XMULLD 1277 OpS390XMULLW 1278 OpS390XMULLDconst 1279 OpS390XMULLWconst 1280 OpS390XMULLDload 1281 OpS390XMULLWload 1282 OpS390XMULHD 1283 OpS390XMULHDU 1284 OpS390XDIVD 1285 OpS390XDIVW 1286 OpS390XDIVDU 1287 OpS390XDIVWU 1288 OpS390XMODD 1289 OpS390XMODW 1290 OpS390XMODDU 1291 OpS390XMODWU 1292 OpS390XAND 1293 OpS390XANDW 1294 OpS390XANDconst 1295 OpS390XANDWconst 1296 OpS390XANDload 1297 OpS390XANDWload 1298 OpS390XOR 1299 OpS390XORW 1300 OpS390XORconst 1301 OpS390XORWconst 1302 OpS390XORload 1303 OpS390XORWload 1304 OpS390XXOR 1305 OpS390XXORW 1306 OpS390XXORconst 1307 OpS390XXORWconst 1308 OpS390XXORload 1309 OpS390XXORWload 1310 OpS390XCMP 1311 OpS390XCMPW 1312 OpS390XCMPU 1313 OpS390XCMPWU 1314 OpS390XCMPconst 1315 OpS390XCMPWconst 1316 OpS390XCMPUconst 1317 OpS390XCMPWUconst 1318 OpS390XFCMPS 1319 OpS390XFCMP 1320 OpS390XSLD 1321 OpS390XSLW 1322 OpS390XSLDconst 1323 OpS390XSLWconst 1324 OpS390XSRD 1325 OpS390XSRW 1326 OpS390XSRDconst 1327 OpS390XSRWconst 1328 OpS390XSRAD 1329 OpS390XSRAW 1330 OpS390XSRADconst 1331 OpS390XSRAWconst 1332 OpS390XRLLGconst 1333 OpS390XRLLconst 1334 OpS390XNEG 1335 OpS390XNEGW 1336 OpS390XNOT 1337 OpS390XNOTW 1338 OpS390XFSQRT 1339 OpS390XSUBEcarrymask 1340 OpS390XSUBEWcarrymask 1341 OpS390XMOVDEQ 1342 OpS390XMOVDNE 1343 OpS390XMOVDLT 1344 OpS390XMOVDLE 1345 OpS390XMOVDGT 1346 OpS390XMOVDGE 1347 OpS390XMOVDGTnoinv 1348 OpS390XMOVDGEnoinv 1349 OpS390XMOVBreg 1350 OpS390XMOVBZreg 1351 OpS390XMOVHreg 1352 OpS390XMOVHZreg 1353 OpS390XMOVWreg 1354 OpS390XMOVWZreg 1355 OpS390XMOVDconst 1356 OpS390XCFDBRA 1357 OpS390XCGDBRA 1358 OpS390XCFEBRA 1359 OpS390XCGEBRA 1360 OpS390XCEFBRA 1361 OpS390XCDFBRA 1362 OpS390XCEGBRA 1363 OpS390XCDGBRA 1364 OpS390XLEDBR 1365 OpS390XLDEBR 1366 OpS390XMOVDaddr 1367 OpS390XMOVDaddridx 1368 OpS390XMOVBZload 1369 OpS390XMOVBload 1370 OpS390XMOVHZload 1371 OpS390XMOVHload 1372 OpS390XMOVWZload 1373 OpS390XMOVWload 1374 OpS390XMOVDload 1375 OpS390XMOVWBR 1376 OpS390XMOVDBR 1377 OpS390XMOVHBRload 1378 OpS390XMOVWBRload 1379 OpS390XMOVDBRload 1380 OpS390XMOVBstore 1381 OpS390XMOVHstore 1382 OpS390XMOVWstore 1383 OpS390XMOVDstore 1384 OpS390XMOVHBRstore 1385 OpS390XMOVWBRstore 1386 OpS390XMOVDBRstore 1387 OpS390XMVC 1388 OpS390XMOVBZloadidx 1389 OpS390XMOVHZloadidx 1390 OpS390XMOVWZloadidx 1391 OpS390XMOVDloadidx 1392 OpS390XMOVHBRloadidx 1393 OpS390XMOVWBRloadidx 1394 OpS390XMOVDBRloadidx 1395 OpS390XMOVBstoreidx 1396 OpS390XMOVHstoreidx 1397 OpS390XMOVWstoreidx 1398 OpS390XMOVDstoreidx 1399 OpS390XMOVHBRstoreidx 1400 OpS390XMOVWBRstoreidx 1401 OpS390XMOVDBRstoreidx 1402 OpS390XMOVBstoreconst 1403 OpS390XMOVHstoreconst 1404 OpS390XMOVWstoreconst 1405 OpS390XMOVDstoreconst 1406 OpS390XCLEAR 1407 OpS390XCALLstatic 1408 OpS390XCALLclosure 1409 OpS390XCALLdefer 1410 OpS390XCALLgo 1411 OpS390XCALLinter 1412 OpS390XInvertFlags 1413 OpS390XLoweredGetG 1414 OpS390XLoweredGetClosurePtr 1415 OpS390XLoweredNilCheck 1416 OpS390XMOVDconvert 1417 OpS390XFlagEQ 1418 OpS390XFlagLT 1419 OpS390XFlagGT 1420 OpS390XMOVWZatomicload 1421 OpS390XMOVDatomicload 1422 OpS390XMOVWatomicstore 1423 OpS390XMOVDatomicstore 1424 OpS390XLAA 1425 OpS390XLAAG 1426 OpS390XAddTupleFirst32 1427 OpS390XAddTupleFirst64 1428 OpS390XLoweredAtomicCas32 1429 OpS390XLoweredAtomicCas64 1430 OpS390XLoweredAtomicExchange32 1431 OpS390XLoweredAtomicExchange64 1432 OpS390XFLOGR 1433 OpS390XSTMG2 1434 OpS390XSTMG3 1435 OpS390XSTMG4 1436 OpS390XSTM2 1437 OpS390XSTM3 1438 OpS390XSTM4 1439 OpS390XLoweredMove 1440 OpS390XLoweredZero 1441 1442 OpAdd8 1443 OpAdd16 1444 OpAdd32 1445 OpAdd64 1446 OpAddPtr 1447 OpAdd32F 1448 OpAdd64F 1449 OpSub8 1450 OpSub16 1451 OpSub32 1452 OpSub64 1453 OpSubPtr 1454 OpSub32F 1455 OpSub64F 1456 OpMul8 1457 OpMul16 1458 OpMul32 1459 OpMul64 1460 OpMul32F 1461 OpMul64F 1462 OpDiv32F 1463 OpDiv64F 1464 OpHmul8 1465 OpHmul8u 1466 OpHmul16 1467 OpHmul16u 1468 OpHmul32 1469 OpHmul32u 1470 OpHmul64 1471 OpHmul64u 1472 OpMul32uhilo 1473 OpMul64uhilo 1474 OpAvg64u 1475 OpDiv8 1476 OpDiv8u 1477 OpDiv16 1478 OpDiv16u 1479 OpDiv32 1480 OpDiv32u 1481 OpDiv64 1482 OpDiv64u 1483 OpDiv128u 1484 OpMod8 1485 OpMod8u 1486 OpMod16 1487 OpMod16u 1488 OpMod32 1489 OpMod32u 1490 OpMod64 1491 OpMod64u 1492 OpAnd8 1493 OpAnd16 1494 OpAnd32 1495 OpAnd64 1496 OpOr8 1497 OpOr16 1498 OpOr32 1499 OpOr64 1500 OpXor8 1501 OpXor16 1502 OpXor32 1503 OpXor64 1504 OpLsh8x8 1505 OpLsh8x16 1506 OpLsh8x32 1507 OpLsh8x64 1508 OpLsh16x8 1509 OpLsh16x16 1510 OpLsh16x32 1511 OpLsh16x64 1512 OpLsh32x8 1513 OpLsh32x16 1514 OpLsh32x32 1515 OpLsh32x64 1516 OpLsh64x8 1517 OpLsh64x16 1518 OpLsh64x32 1519 OpLsh64x64 1520 OpRsh8x8 1521 OpRsh8x16 1522 OpRsh8x32 1523 OpRsh8x64 1524 OpRsh16x8 1525 OpRsh16x16 1526 OpRsh16x32 1527 OpRsh16x64 1528 OpRsh32x8 1529 OpRsh32x16 1530 OpRsh32x32 1531 OpRsh32x64 1532 OpRsh64x8 1533 OpRsh64x16 1534 OpRsh64x32 1535 OpRsh64x64 1536 OpRsh8Ux8 1537 OpRsh8Ux16 1538 OpRsh8Ux32 1539 OpRsh8Ux64 1540 OpRsh16Ux8 1541 OpRsh16Ux16 1542 OpRsh16Ux32 1543 OpRsh16Ux64 1544 OpRsh32Ux8 1545 OpRsh32Ux16 1546 OpRsh32Ux32 1547 OpRsh32Ux64 1548 OpRsh64Ux8 1549 OpRsh64Ux16 1550 OpRsh64Ux32 1551 OpRsh64Ux64 1552 OpLrot8 1553 OpLrot16 1554 OpLrot32 1555 OpLrot64 1556 OpEq8 1557 OpEq16 1558 OpEq32 1559 OpEq64 1560 OpEqPtr 1561 OpEqInter 1562 OpEqSlice 1563 OpEq32F 1564 OpEq64F 1565 OpNeq8 1566 OpNeq16 1567 OpNeq32 1568 OpNeq64 1569 OpNeqPtr 1570 OpNeqInter 1571 OpNeqSlice 1572 OpNeq32F 1573 OpNeq64F 1574 OpLess8 1575 OpLess8U 1576 OpLess16 1577 OpLess16U 1578 OpLess32 1579 OpLess32U 1580 OpLess64 1581 OpLess64U 1582 OpLess32F 1583 OpLess64F 1584 OpLeq8 1585 OpLeq8U 1586 OpLeq16 1587 OpLeq16U 1588 OpLeq32 1589 OpLeq32U 1590 OpLeq64 1591 OpLeq64U 1592 OpLeq32F 1593 OpLeq64F 1594 OpGreater8 1595 OpGreater8U 1596 OpGreater16 1597 OpGreater16U 1598 OpGreater32 1599 OpGreater32U 1600 OpGreater64 1601 OpGreater64U 1602 OpGreater32F 1603 OpGreater64F 1604 OpGeq8 1605 OpGeq8U 1606 OpGeq16 1607 OpGeq16U 1608 OpGeq32 1609 OpGeq32U 1610 OpGeq64 1611 OpGeq64U 1612 OpGeq32F 1613 OpGeq64F 1614 OpAndB 1615 OpOrB 1616 OpEqB 1617 OpNeqB 1618 OpNot 1619 OpNeg8 1620 OpNeg16 1621 OpNeg32 1622 OpNeg64 1623 OpNeg32F 1624 OpNeg64F 1625 OpCom8 1626 OpCom16 1627 OpCom32 1628 OpCom64 1629 OpCtz32 1630 OpCtz64 1631 OpBswap32 1632 OpBswap64 1633 OpSqrt 1634 OpPhi 1635 OpCopy 1636 OpConvert 1637 OpConstBool 1638 OpConstString 1639 OpConstNil 1640 OpConst8 1641 OpConst16 1642 OpConst32 1643 OpConst64 1644 OpConst32F 1645 OpConst64F 1646 OpConstInterface 1647 OpConstSlice 1648 OpInitMem 1649 OpArg 1650 OpAddr 1651 OpSP 1652 OpSB 1653 OpFunc 1654 OpLoad 1655 OpStore 1656 OpMove 1657 OpZero 1658 OpStoreWB 1659 OpMoveWB 1660 OpMoveWBVolatile 1661 OpZeroWB 1662 OpClosureCall 1663 OpStaticCall 1664 OpDeferCall 1665 OpGoCall 1666 OpInterCall 1667 OpSignExt8to16 1668 OpSignExt8to32 1669 OpSignExt8to64 1670 OpSignExt16to32 1671 OpSignExt16to64 1672 OpSignExt32to64 1673 OpZeroExt8to16 1674 OpZeroExt8to32 1675 OpZeroExt8to64 1676 OpZeroExt16to32 1677 OpZeroExt16to64 1678 OpZeroExt32to64 1679 OpTrunc16to8 1680 OpTrunc32to8 1681 OpTrunc32to16 1682 OpTrunc64to8 1683 OpTrunc64to16 1684 OpTrunc64to32 1685 OpCvt32to32F 1686 OpCvt32to64F 1687 OpCvt64to32F 1688 OpCvt64to64F 1689 OpCvt32Fto32 1690 OpCvt32Fto64 1691 OpCvt64Fto32 1692 OpCvt64Fto64 1693 OpCvt32Fto64F 1694 OpCvt64Fto32F 1695 OpIsNonNil 1696 OpIsInBounds 1697 OpIsSliceInBounds 1698 OpNilCheck 1699 OpGetG 1700 OpGetClosurePtr 1701 OpPtrIndex 1702 OpOffPtr 1703 OpSliceMake 1704 OpSlicePtr 1705 OpSliceLen 1706 OpSliceCap 1707 OpComplexMake 1708 OpComplexReal 1709 OpComplexImag 1710 OpStringMake 1711 OpStringPtr 1712 OpStringLen 1713 OpIMake 1714 OpITab 1715 OpIData 1716 OpStructMake0 1717 OpStructMake1 1718 OpStructMake2 1719 OpStructMake3 1720 OpStructMake4 1721 OpStructSelect 1722 OpArrayMake0 1723 OpArrayMake1 1724 OpArraySelect 1725 OpStoreReg 1726 OpLoadReg 1727 OpFwdRef 1728 OpUnknown 1729 OpVarDef 1730 OpVarKill 1731 OpVarLive 1732 OpKeepAlive 1733 OpInt64Make 1734 OpInt64Hi 1735 OpInt64Lo 1736 OpAdd32carry 1737 OpAdd32withcarry 1738 OpSub32carry 1739 OpSub32withcarry 1740 OpSignmask 1741 OpZeromask 1742 OpSlicemask 1743 OpCvt32Uto32F 1744 OpCvt32Uto64F 1745 OpCvt32Fto32U 1746 OpCvt64Fto32U 1747 OpCvt64Uto32F 1748 OpCvt64Uto64F 1749 OpCvt32Fto64U 1750 OpCvt64Fto64U 1751 OpSelect0 1752 OpSelect1 1753 OpAtomicLoad32 1754 OpAtomicLoad64 1755 OpAtomicLoadPtr 1756 OpAtomicStore32 1757 OpAtomicStore64 1758 OpAtomicStorePtrNoWB 1759 OpAtomicExchange32 1760 OpAtomicExchange64 1761 OpAtomicAdd32 1762 OpAtomicAdd64 1763 OpAtomicCompareAndSwap32 1764 OpAtomicCompareAndSwap64 1765 OpAtomicAnd8 1766 OpAtomicOr8 1767 ) 1768 1769 var opcodeTable = [...]opInfo{ 1770 {name: "OpInvalid"}, 1771 1772 { 1773 name: "ADDSS", 1774 argLen: 2, 1775 commutative: true, 1776 resultInArg0: true, 1777 usesScratch: true, 1778 asm: x86.AADDSS, 1779 reg: regInfo{ 1780 inputs: []inputInfo{ 1781 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1782 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1783 }, 1784 outputs: []outputInfo{ 1785 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1786 }, 1787 }, 1788 }, 1789 { 1790 name: "ADDSD", 1791 argLen: 2, 1792 commutative: true, 1793 resultInArg0: true, 1794 asm: x86.AADDSD, 1795 reg: regInfo{ 1796 inputs: []inputInfo{ 1797 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1798 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1799 }, 1800 outputs: []outputInfo{ 1801 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1802 }, 1803 }, 1804 }, 1805 { 1806 name: "SUBSS", 1807 argLen: 2, 1808 resultInArg0: true, 1809 usesScratch: true, 1810 asm: x86.ASUBSS, 1811 reg: regInfo{ 1812 inputs: []inputInfo{ 1813 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1814 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1815 }, 1816 outputs: []outputInfo{ 1817 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1818 }, 1819 }, 1820 }, 1821 { 1822 name: "SUBSD", 1823 argLen: 2, 1824 resultInArg0: true, 1825 asm: x86.ASUBSD, 1826 reg: regInfo{ 1827 inputs: []inputInfo{ 1828 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1829 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1830 }, 1831 outputs: []outputInfo{ 1832 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1833 }, 1834 }, 1835 }, 1836 { 1837 name: "MULSS", 1838 argLen: 2, 1839 commutative: true, 1840 resultInArg0: true, 1841 usesScratch: true, 1842 asm: x86.AMULSS, 1843 reg: regInfo{ 1844 inputs: []inputInfo{ 1845 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1846 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1847 }, 1848 outputs: []outputInfo{ 1849 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1850 }, 1851 }, 1852 }, 1853 { 1854 name: "MULSD", 1855 argLen: 2, 1856 commutative: true, 1857 resultInArg0: true, 1858 asm: x86.AMULSD, 1859 reg: regInfo{ 1860 inputs: []inputInfo{ 1861 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1862 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1863 }, 1864 outputs: []outputInfo{ 1865 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1866 }, 1867 }, 1868 }, 1869 { 1870 name: "DIVSS", 1871 argLen: 2, 1872 resultInArg0: true, 1873 usesScratch: true, 1874 asm: x86.ADIVSS, 1875 reg: regInfo{ 1876 inputs: []inputInfo{ 1877 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1878 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1879 }, 1880 outputs: []outputInfo{ 1881 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1882 }, 1883 }, 1884 }, 1885 { 1886 name: "DIVSD", 1887 argLen: 2, 1888 resultInArg0: true, 1889 asm: x86.ADIVSD, 1890 reg: regInfo{ 1891 inputs: []inputInfo{ 1892 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1893 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1894 }, 1895 outputs: []outputInfo{ 1896 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1897 }, 1898 }, 1899 }, 1900 { 1901 name: "MOVSSload", 1902 auxType: auxSymOff, 1903 argLen: 2, 1904 faultOnNilArg0: true, 1905 asm: x86.AMOVSS, 1906 reg: regInfo{ 1907 inputs: []inputInfo{ 1908 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1909 }, 1910 outputs: []outputInfo{ 1911 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1912 }, 1913 }, 1914 }, 1915 { 1916 name: "MOVSDload", 1917 auxType: auxSymOff, 1918 argLen: 2, 1919 faultOnNilArg0: true, 1920 asm: x86.AMOVSD, 1921 reg: regInfo{ 1922 inputs: []inputInfo{ 1923 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1924 }, 1925 outputs: []outputInfo{ 1926 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1927 }, 1928 }, 1929 }, 1930 { 1931 name: "MOVSSconst", 1932 auxType: auxFloat32, 1933 argLen: 0, 1934 rematerializeable: true, 1935 asm: x86.AMOVSS, 1936 reg: regInfo{ 1937 outputs: []outputInfo{ 1938 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1939 }, 1940 }, 1941 }, 1942 { 1943 name: "MOVSDconst", 1944 auxType: auxFloat64, 1945 argLen: 0, 1946 rematerializeable: true, 1947 asm: x86.AMOVSD, 1948 reg: regInfo{ 1949 outputs: []outputInfo{ 1950 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1951 }, 1952 }, 1953 }, 1954 { 1955 name: "MOVSSloadidx1", 1956 auxType: auxSymOff, 1957 argLen: 3, 1958 asm: x86.AMOVSS, 1959 reg: regInfo{ 1960 inputs: []inputInfo{ 1961 {1, 255}, // AX CX DX BX SP BP SI DI 1962 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1963 }, 1964 outputs: []outputInfo{ 1965 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1966 }, 1967 }, 1968 }, 1969 { 1970 name: "MOVSSloadidx4", 1971 auxType: auxSymOff, 1972 argLen: 3, 1973 asm: x86.AMOVSS, 1974 reg: regInfo{ 1975 inputs: []inputInfo{ 1976 {1, 255}, // AX CX DX BX SP BP SI DI 1977 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1978 }, 1979 outputs: []outputInfo{ 1980 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1981 }, 1982 }, 1983 }, 1984 { 1985 name: "MOVSDloadidx1", 1986 auxType: auxSymOff, 1987 argLen: 3, 1988 asm: x86.AMOVSD, 1989 reg: regInfo{ 1990 inputs: []inputInfo{ 1991 {1, 255}, // AX CX DX BX SP BP SI DI 1992 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1993 }, 1994 outputs: []outputInfo{ 1995 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1996 }, 1997 }, 1998 }, 1999 { 2000 name: "MOVSDloadidx8", 2001 auxType: auxSymOff, 2002 argLen: 3, 2003 asm: x86.AMOVSD, 2004 reg: regInfo{ 2005 inputs: []inputInfo{ 2006 {1, 255}, // AX CX DX BX SP BP SI DI 2007 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2008 }, 2009 outputs: []outputInfo{ 2010 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2011 }, 2012 }, 2013 }, 2014 { 2015 name: "MOVSSstore", 2016 auxType: auxSymOff, 2017 argLen: 3, 2018 faultOnNilArg0: true, 2019 asm: x86.AMOVSS, 2020 reg: regInfo{ 2021 inputs: []inputInfo{ 2022 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2023 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2024 }, 2025 }, 2026 }, 2027 { 2028 name: "MOVSDstore", 2029 auxType: auxSymOff, 2030 argLen: 3, 2031 faultOnNilArg0: true, 2032 asm: x86.AMOVSD, 2033 reg: regInfo{ 2034 inputs: []inputInfo{ 2035 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2036 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2037 }, 2038 }, 2039 }, 2040 { 2041 name: "MOVSSstoreidx1", 2042 auxType: auxSymOff, 2043 argLen: 4, 2044 asm: x86.AMOVSS, 2045 reg: regInfo{ 2046 inputs: []inputInfo{ 2047 {1, 255}, // AX CX DX BX SP BP SI DI 2048 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2049 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2050 }, 2051 }, 2052 }, 2053 { 2054 name: "MOVSSstoreidx4", 2055 auxType: auxSymOff, 2056 argLen: 4, 2057 asm: x86.AMOVSS, 2058 reg: regInfo{ 2059 inputs: []inputInfo{ 2060 {1, 255}, // AX CX DX BX SP BP SI DI 2061 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2062 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2063 }, 2064 }, 2065 }, 2066 { 2067 name: "MOVSDstoreidx1", 2068 auxType: auxSymOff, 2069 argLen: 4, 2070 asm: x86.AMOVSD, 2071 reg: regInfo{ 2072 inputs: []inputInfo{ 2073 {1, 255}, // AX CX DX BX SP BP SI DI 2074 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2075 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2076 }, 2077 }, 2078 }, 2079 { 2080 name: "MOVSDstoreidx8", 2081 auxType: auxSymOff, 2082 argLen: 4, 2083 asm: x86.AMOVSD, 2084 reg: regInfo{ 2085 inputs: []inputInfo{ 2086 {1, 255}, // AX CX DX BX SP BP SI DI 2087 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2088 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2089 }, 2090 }, 2091 }, 2092 { 2093 name: "ADDL", 2094 argLen: 2, 2095 commutative: true, 2096 clobberFlags: true, 2097 asm: x86.AADDL, 2098 reg: regInfo{ 2099 inputs: []inputInfo{ 2100 {1, 239}, // AX CX DX BX BP SI DI 2101 {0, 255}, // AX CX DX BX SP BP SI DI 2102 }, 2103 outputs: []outputInfo{ 2104 {0, 239}, // AX CX DX BX BP SI DI 2105 }, 2106 }, 2107 }, 2108 { 2109 name: "ADDLconst", 2110 auxType: auxInt32, 2111 argLen: 1, 2112 clobberFlags: true, 2113 asm: x86.AADDL, 2114 reg: regInfo{ 2115 inputs: []inputInfo{ 2116 {0, 255}, // AX CX DX BX SP BP SI DI 2117 }, 2118 outputs: []outputInfo{ 2119 {0, 239}, // AX CX DX BX BP SI DI 2120 }, 2121 }, 2122 }, 2123 { 2124 name: "ADDLcarry", 2125 argLen: 2, 2126 commutative: true, 2127 resultInArg0: true, 2128 asm: x86.AADDL, 2129 reg: regInfo{ 2130 inputs: []inputInfo{ 2131 {0, 239}, // AX CX DX BX BP SI DI 2132 {1, 239}, // AX CX DX BX BP SI DI 2133 }, 2134 outputs: []outputInfo{ 2135 {1, 0}, 2136 {0, 239}, // AX CX DX BX BP SI DI 2137 }, 2138 }, 2139 }, 2140 { 2141 name: "ADDLconstcarry", 2142 auxType: auxInt32, 2143 argLen: 1, 2144 resultInArg0: true, 2145 asm: x86.AADDL, 2146 reg: regInfo{ 2147 inputs: []inputInfo{ 2148 {0, 239}, // AX CX DX BX BP SI DI 2149 }, 2150 outputs: []outputInfo{ 2151 {1, 0}, 2152 {0, 239}, // AX CX DX BX BP SI DI 2153 }, 2154 }, 2155 }, 2156 { 2157 name: "ADCL", 2158 argLen: 3, 2159 commutative: true, 2160 resultInArg0: true, 2161 clobberFlags: true, 2162 asm: x86.AADCL, 2163 reg: regInfo{ 2164 inputs: []inputInfo{ 2165 {0, 239}, // AX CX DX BX BP SI DI 2166 {1, 239}, // AX CX DX BX BP SI DI 2167 }, 2168 outputs: []outputInfo{ 2169 {0, 239}, // AX CX DX BX BP SI DI 2170 }, 2171 }, 2172 }, 2173 { 2174 name: "ADCLconst", 2175 auxType: auxInt32, 2176 argLen: 2, 2177 resultInArg0: true, 2178 clobberFlags: true, 2179 asm: x86.AADCL, 2180 reg: regInfo{ 2181 inputs: []inputInfo{ 2182 {0, 239}, // AX CX DX BX BP SI DI 2183 }, 2184 outputs: []outputInfo{ 2185 {0, 239}, // AX CX DX BX BP SI DI 2186 }, 2187 }, 2188 }, 2189 { 2190 name: "SUBL", 2191 argLen: 2, 2192 resultInArg0: true, 2193 clobberFlags: true, 2194 asm: x86.ASUBL, 2195 reg: regInfo{ 2196 inputs: []inputInfo{ 2197 {0, 239}, // AX CX DX BX BP SI DI 2198 {1, 239}, // AX CX DX BX BP SI DI 2199 }, 2200 outputs: []outputInfo{ 2201 {0, 239}, // AX CX DX BX BP SI DI 2202 }, 2203 }, 2204 }, 2205 { 2206 name: "SUBLconst", 2207 auxType: auxInt32, 2208 argLen: 1, 2209 resultInArg0: true, 2210 clobberFlags: true, 2211 asm: x86.ASUBL, 2212 reg: regInfo{ 2213 inputs: []inputInfo{ 2214 {0, 239}, // AX CX DX BX BP SI DI 2215 }, 2216 outputs: []outputInfo{ 2217 {0, 239}, // AX CX DX BX BP SI DI 2218 }, 2219 }, 2220 }, 2221 { 2222 name: "SUBLcarry", 2223 argLen: 2, 2224 resultInArg0: true, 2225 asm: x86.ASUBL, 2226 reg: regInfo{ 2227 inputs: []inputInfo{ 2228 {0, 239}, // AX CX DX BX BP SI DI 2229 {1, 239}, // AX CX DX BX BP SI DI 2230 }, 2231 outputs: []outputInfo{ 2232 {1, 0}, 2233 {0, 239}, // AX CX DX BX BP SI DI 2234 }, 2235 }, 2236 }, 2237 { 2238 name: "SUBLconstcarry", 2239 auxType: auxInt32, 2240 argLen: 1, 2241 resultInArg0: true, 2242 asm: x86.ASUBL, 2243 reg: regInfo{ 2244 inputs: []inputInfo{ 2245 {0, 239}, // AX CX DX BX BP SI DI 2246 }, 2247 outputs: []outputInfo{ 2248 {1, 0}, 2249 {0, 239}, // AX CX DX BX BP SI DI 2250 }, 2251 }, 2252 }, 2253 { 2254 name: "SBBL", 2255 argLen: 3, 2256 resultInArg0: true, 2257 clobberFlags: true, 2258 asm: x86.ASBBL, 2259 reg: regInfo{ 2260 inputs: []inputInfo{ 2261 {0, 239}, // AX CX DX BX BP SI DI 2262 {1, 239}, // AX CX DX BX BP SI DI 2263 }, 2264 outputs: []outputInfo{ 2265 {0, 239}, // AX CX DX BX BP SI DI 2266 }, 2267 }, 2268 }, 2269 { 2270 name: "SBBLconst", 2271 auxType: auxInt32, 2272 argLen: 2, 2273 resultInArg0: true, 2274 clobberFlags: true, 2275 asm: x86.ASBBL, 2276 reg: regInfo{ 2277 inputs: []inputInfo{ 2278 {0, 239}, // AX CX DX BX BP SI DI 2279 }, 2280 outputs: []outputInfo{ 2281 {0, 239}, // AX CX DX BX BP SI DI 2282 }, 2283 }, 2284 }, 2285 { 2286 name: "MULL", 2287 argLen: 2, 2288 commutative: true, 2289 resultInArg0: true, 2290 clobberFlags: true, 2291 asm: x86.AIMULL, 2292 reg: regInfo{ 2293 inputs: []inputInfo{ 2294 {0, 239}, // AX CX DX BX BP SI DI 2295 {1, 239}, // AX CX DX BX BP SI DI 2296 }, 2297 outputs: []outputInfo{ 2298 {0, 239}, // AX CX DX BX BP SI DI 2299 }, 2300 }, 2301 }, 2302 { 2303 name: "MULLconst", 2304 auxType: auxInt32, 2305 argLen: 1, 2306 resultInArg0: true, 2307 clobberFlags: true, 2308 asm: x86.AIMULL, 2309 reg: regInfo{ 2310 inputs: []inputInfo{ 2311 {0, 239}, // AX CX DX BX BP SI DI 2312 }, 2313 outputs: []outputInfo{ 2314 {0, 239}, // AX CX DX BX BP SI DI 2315 }, 2316 }, 2317 }, 2318 { 2319 name: "HMULL", 2320 argLen: 2, 2321 clobberFlags: true, 2322 asm: x86.AIMULL, 2323 reg: regInfo{ 2324 inputs: []inputInfo{ 2325 {0, 1}, // AX 2326 {1, 255}, // AX CX DX BX SP BP SI DI 2327 }, 2328 clobbers: 1, // AX 2329 outputs: []outputInfo{ 2330 {0, 4}, // DX 2331 }, 2332 }, 2333 }, 2334 { 2335 name: "HMULLU", 2336 argLen: 2, 2337 clobberFlags: true, 2338 asm: x86.AMULL, 2339 reg: regInfo{ 2340 inputs: []inputInfo{ 2341 {0, 1}, // AX 2342 {1, 255}, // AX CX DX BX SP BP SI DI 2343 }, 2344 clobbers: 1, // AX 2345 outputs: []outputInfo{ 2346 {0, 4}, // DX 2347 }, 2348 }, 2349 }, 2350 { 2351 name: "HMULW", 2352 argLen: 2, 2353 clobberFlags: true, 2354 asm: x86.AIMULW, 2355 reg: regInfo{ 2356 inputs: []inputInfo{ 2357 {0, 1}, // AX 2358 {1, 255}, // AX CX DX BX SP BP SI DI 2359 }, 2360 clobbers: 1, // AX 2361 outputs: []outputInfo{ 2362 {0, 4}, // DX 2363 }, 2364 }, 2365 }, 2366 { 2367 name: "HMULB", 2368 argLen: 2, 2369 clobberFlags: true, 2370 asm: x86.AIMULB, 2371 reg: regInfo{ 2372 inputs: []inputInfo{ 2373 {0, 1}, // AX 2374 {1, 255}, // AX CX DX BX SP BP SI DI 2375 }, 2376 clobbers: 1, // AX 2377 outputs: []outputInfo{ 2378 {0, 4}, // DX 2379 }, 2380 }, 2381 }, 2382 { 2383 name: "HMULWU", 2384 argLen: 2, 2385 clobberFlags: true, 2386 asm: x86.AMULW, 2387 reg: regInfo{ 2388 inputs: []inputInfo{ 2389 {0, 1}, // AX 2390 {1, 255}, // AX CX DX BX SP BP SI DI 2391 }, 2392 clobbers: 1, // AX 2393 outputs: []outputInfo{ 2394 {0, 4}, // DX 2395 }, 2396 }, 2397 }, 2398 { 2399 name: "HMULBU", 2400 argLen: 2, 2401 clobberFlags: true, 2402 asm: x86.AMULB, 2403 reg: regInfo{ 2404 inputs: []inputInfo{ 2405 {0, 1}, // AX 2406 {1, 255}, // AX CX DX BX SP BP SI DI 2407 }, 2408 clobbers: 1, // AX 2409 outputs: []outputInfo{ 2410 {0, 4}, // DX 2411 }, 2412 }, 2413 }, 2414 { 2415 name: "MULLQU", 2416 argLen: 2, 2417 clobberFlags: true, 2418 asm: x86.AMULL, 2419 reg: regInfo{ 2420 inputs: []inputInfo{ 2421 {0, 1}, // AX 2422 {1, 255}, // AX CX DX BX SP BP SI DI 2423 }, 2424 outputs: []outputInfo{ 2425 {0, 4}, // DX 2426 {1, 1}, // AX 2427 }, 2428 }, 2429 }, 2430 { 2431 name: "DIVL", 2432 argLen: 2, 2433 clobberFlags: true, 2434 asm: x86.AIDIVL, 2435 reg: regInfo{ 2436 inputs: []inputInfo{ 2437 {0, 1}, // AX 2438 {1, 251}, // AX CX BX SP BP SI DI 2439 }, 2440 clobbers: 4, // DX 2441 outputs: []outputInfo{ 2442 {0, 1}, // AX 2443 }, 2444 }, 2445 }, 2446 { 2447 name: "DIVW", 2448 argLen: 2, 2449 clobberFlags: true, 2450 asm: x86.AIDIVW, 2451 reg: regInfo{ 2452 inputs: []inputInfo{ 2453 {0, 1}, // AX 2454 {1, 251}, // AX CX BX SP BP SI DI 2455 }, 2456 clobbers: 4, // DX 2457 outputs: []outputInfo{ 2458 {0, 1}, // AX 2459 }, 2460 }, 2461 }, 2462 { 2463 name: "DIVLU", 2464 argLen: 2, 2465 clobberFlags: true, 2466 asm: x86.ADIVL, 2467 reg: regInfo{ 2468 inputs: []inputInfo{ 2469 {0, 1}, // AX 2470 {1, 251}, // AX CX BX SP BP SI DI 2471 }, 2472 clobbers: 4, // DX 2473 outputs: []outputInfo{ 2474 {0, 1}, // AX 2475 }, 2476 }, 2477 }, 2478 { 2479 name: "DIVWU", 2480 argLen: 2, 2481 clobberFlags: true, 2482 asm: x86.ADIVW, 2483 reg: regInfo{ 2484 inputs: []inputInfo{ 2485 {0, 1}, // AX 2486 {1, 251}, // AX CX BX SP BP SI DI 2487 }, 2488 clobbers: 4, // DX 2489 outputs: []outputInfo{ 2490 {0, 1}, // AX 2491 }, 2492 }, 2493 }, 2494 { 2495 name: "MODL", 2496 argLen: 2, 2497 clobberFlags: true, 2498 asm: x86.AIDIVL, 2499 reg: regInfo{ 2500 inputs: []inputInfo{ 2501 {0, 1}, // AX 2502 {1, 251}, // AX CX BX SP BP SI DI 2503 }, 2504 clobbers: 1, // AX 2505 outputs: []outputInfo{ 2506 {0, 4}, // DX 2507 }, 2508 }, 2509 }, 2510 { 2511 name: "MODW", 2512 argLen: 2, 2513 clobberFlags: true, 2514 asm: x86.AIDIVW, 2515 reg: regInfo{ 2516 inputs: []inputInfo{ 2517 {0, 1}, // AX 2518 {1, 251}, // AX CX BX SP BP SI DI 2519 }, 2520 clobbers: 1, // AX 2521 outputs: []outputInfo{ 2522 {0, 4}, // DX 2523 }, 2524 }, 2525 }, 2526 { 2527 name: "MODLU", 2528 argLen: 2, 2529 clobberFlags: true, 2530 asm: x86.ADIVL, 2531 reg: regInfo{ 2532 inputs: []inputInfo{ 2533 {0, 1}, // AX 2534 {1, 251}, // AX CX BX SP BP SI DI 2535 }, 2536 clobbers: 1, // AX 2537 outputs: []outputInfo{ 2538 {0, 4}, // DX 2539 }, 2540 }, 2541 }, 2542 { 2543 name: "MODWU", 2544 argLen: 2, 2545 clobberFlags: true, 2546 asm: x86.ADIVW, 2547 reg: regInfo{ 2548 inputs: []inputInfo{ 2549 {0, 1}, // AX 2550 {1, 251}, // AX CX BX SP BP SI DI 2551 }, 2552 clobbers: 1, // AX 2553 outputs: []outputInfo{ 2554 {0, 4}, // DX 2555 }, 2556 }, 2557 }, 2558 { 2559 name: "ANDL", 2560 argLen: 2, 2561 commutative: true, 2562 resultInArg0: true, 2563 clobberFlags: true, 2564 asm: x86.AANDL, 2565 reg: regInfo{ 2566 inputs: []inputInfo{ 2567 {0, 239}, // AX CX DX BX BP SI DI 2568 {1, 239}, // AX CX DX BX BP SI DI 2569 }, 2570 outputs: []outputInfo{ 2571 {0, 239}, // AX CX DX BX BP SI DI 2572 }, 2573 }, 2574 }, 2575 { 2576 name: "ANDLconst", 2577 auxType: auxInt32, 2578 argLen: 1, 2579 resultInArg0: true, 2580 clobberFlags: true, 2581 asm: x86.AANDL, 2582 reg: regInfo{ 2583 inputs: []inputInfo{ 2584 {0, 239}, // AX CX DX BX BP SI DI 2585 }, 2586 outputs: []outputInfo{ 2587 {0, 239}, // AX CX DX BX BP SI DI 2588 }, 2589 }, 2590 }, 2591 { 2592 name: "ORL", 2593 argLen: 2, 2594 commutative: true, 2595 resultInArg0: true, 2596 clobberFlags: true, 2597 asm: x86.AORL, 2598 reg: regInfo{ 2599 inputs: []inputInfo{ 2600 {0, 239}, // AX CX DX BX BP SI DI 2601 {1, 239}, // AX CX DX BX BP SI DI 2602 }, 2603 outputs: []outputInfo{ 2604 {0, 239}, // AX CX DX BX BP SI DI 2605 }, 2606 }, 2607 }, 2608 { 2609 name: "ORLconst", 2610 auxType: auxInt32, 2611 argLen: 1, 2612 resultInArg0: true, 2613 clobberFlags: true, 2614 asm: x86.AORL, 2615 reg: regInfo{ 2616 inputs: []inputInfo{ 2617 {0, 239}, // AX CX DX BX BP SI DI 2618 }, 2619 outputs: []outputInfo{ 2620 {0, 239}, // AX CX DX BX BP SI DI 2621 }, 2622 }, 2623 }, 2624 { 2625 name: "XORL", 2626 argLen: 2, 2627 commutative: true, 2628 resultInArg0: true, 2629 clobberFlags: true, 2630 asm: x86.AXORL, 2631 reg: regInfo{ 2632 inputs: []inputInfo{ 2633 {0, 239}, // AX CX DX BX BP SI DI 2634 {1, 239}, // AX CX DX BX BP SI DI 2635 }, 2636 outputs: []outputInfo{ 2637 {0, 239}, // AX CX DX BX BP SI DI 2638 }, 2639 }, 2640 }, 2641 { 2642 name: "XORLconst", 2643 auxType: auxInt32, 2644 argLen: 1, 2645 resultInArg0: true, 2646 clobberFlags: true, 2647 asm: x86.AXORL, 2648 reg: regInfo{ 2649 inputs: []inputInfo{ 2650 {0, 239}, // AX CX DX BX BP SI DI 2651 }, 2652 outputs: []outputInfo{ 2653 {0, 239}, // AX CX DX BX BP SI DI 2654 }, 2655 }, 2656 }, 2657 { 2658 name: "CMPL", 2659 argLen: 2, 2660 asm: x86.ACMPL, 2661 reg: regInfo{ 2662 inputs: []inputInfo{ 2663 {0, 255}, // AX CX DX BX SP BP SI DI 2664 {1, 255}, // AX CX DX BX SP BP SI DI 2665 }, 2666 }, 2667 }, 2668 { 2669 name: "CMPW", 2670 argLen: 2, 2671 asm: x86.ACMPW, 2672 reg: regInfo{ 2673 inputs: []inputInfo{ 2674 {0, 255}, // AX CX DX BX SP BP SI DI 2675 {1, 255}, // AX CX DX BX SP BP SI DI 2676 }, 2677 }, 2678 }, 2679 { 2680 name: "CMPB", 2681 argLen: 2, 2682 asm: x86.ACMPB, 2683 reg: regInfo{ 2684 inputs: []inputInfo{ 2685 {0, 255}, // AX CX DX BX SP BP SI DI 2686 {1, 255}, // AX CX DX BX SP BP SI DI 2687 }, 2688 }, 2689 }, 2690 { 2691 name: "CMPLconst", 2692 auxType: auxInt32, 2693 argLen: 1, 2694 asm: x86.ACMPL, 2695 reg: regInfo{ 2696 inputs: []inputInfo{ 2697 {0, 255}, // AX CX DX BX SP BP SI DI 2698 }, 2699 }, 2700 }, 2701 { 2702 name: "CMPWconst", 2703 auxType: auxInt16, 2704 argLen: 1, 2705 asm: x86.ACMPW, 2706 reg: regInfo{ 2707 inputs: []inputInfo{ 2708 {0, 255}, // AX CX DX BX SP BP SI DI 2709 }, 2710 }, 2711 }, 2712 { 2713 name: "CMPBconst", 2714 auxType: auxInt8, 2715 argLen: 1, 2716 asm: x86.ACMPB, 2717 reg: regInfo{ 2718 inputs: []inputInfo{ 2719 {0, 255}, // AX CX DX BX SP BP SI DI 2720 }, 2721 }, 2722 }, 2723 { 2724 name: "UCOMISS", 2725 argLen: 2, 2726 usesScratch: true, 2727 asm: x86.AUCOMISS, 2728 reg: regInfo{ 2729 inputs: []inputInfo{ 2730 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2731 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2732 }, 2733 }, 2734 }, 2735 { 2736 name: "UCOMISD", 2737 argLen: 2, 2738 usesScratch: true, 2739 asm: x86.AUCOMISD, 2740 reg: regInfo{ 2741 inputs: []inputInfo{ 2742 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2743 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2744 }, 2745 }, 2746 }, 2747 { 2748 name: "TESTL", 2749 argLen: 2, 2750 asm: x86.ATESTL, 2751 reg: regInfo{ 2752 inputs: []inputInfo{ 2753 {0, 255}, // AX CX DX BX SP BP SI DI 2754 {1, 255}, // AX CX DX BX SP BP SI DI 2755 }, 2756 }, 2757 }, 2758 { 2759 name: "TESTW", 2760 argLen: 2, 2761 asm: x86.ATESTW, 2762 reg: regInfo{ 2763 inputs: []inputInfo{ 2764 {0, 255}, // AX CX DX BX SP BP SI DI 2765 {1, 255}, // AX CX DX BX SP BP SI DI 2766 }, 2767 }, 2768 }, 2769 { 2770 name: "TESTB", 2771 argLen: 2, 2772 asm: x86.ATESTB, 2773 reg: regInfo{ 2774 inputs: []inputInfo{ 2775 {0, 255}, // AX CX DX BX SP BP SI DI 2776 {1, 255}, // AX CX DX BX SP BP SI DI 2777 }, 2778 }, 2779 }, 2780 { 2781 name: "TESTLconst", 2782 auxType: auxInt32, 2783 argLen: 1, 2784 asm: x86.ATESTL, 2785 reg: regInfo{ 2786 inputs: []inputInfo{ 2787 {0, 255}, // AX CX DX BX SP BP SI DI 2788 }, 2789 }, 2790 }, 2791 { 2792 name: "TESTWconst", 2793 auxType: auxInt16, 2794 argLen: 1, 2795 asm: x86.ATESTW, 2796 reg: regInfo{ 2797 inputs: []inputInfo{ 2798 {0, 255}, // AX CX DX BX SP BP SI DI 2799 }, 2800 }, 2801 }, 2802 { 2803 name: "TESTBconst", 2804 auxType: auxInt8, 2805 argLen: 1, 2806 asm: x86.ATESTB, 2807 reg: regInfo{ 2808 inputs: []inputInfo{ 2809 {0, 255}, // AX CX DX BX SP BP SI DI 2810 }, 2811 }, 2812 }, 2813 { 2814 name: "SHLL", 2815 argLen: 2, 2816 resultInArg0: true, 2817 clobberFlags: true, 2818 asm: x86.ASHLL, 2819 reg: regInfo{ 2820 inputs: []inputInfo{ 2821 {1, 2}, // CX 2822 {0, 239}, // AX CX DX BX BP SI DI 2823 }, 2824 outputs: []outputInfo{ 2825 {0, 239}, // AX CX DX BX BP SI DI 2826 }, 2827 }, 2828 }, 2829 { 2830 name: "SHLLconst", 2831 auxType: auxInt32, 2832 argLen: 1, 2833 resultInArg0: true, 2834 clobberFlags: true, 2835 asm: x86.ASHLL, 2836 reg: regInfo{ 2837 inputs: []inputInfo{ 2838 {0, 239}, // AX CX DX BX BP SI DI 2839 }, 2840 outputs: []outputInfo{ 2841 {0, 239}, // AX CX DX BX BP SI DI 2842 }, 2843 }, 2844 }, 2845 { 2846 name: "SHRL", 2847 argLen: 2, 2848 resultInArg0: true, 2849 clobberFlags: true, 2850 asm: x86.ASHRL, 2851 reg: regInfo{ 2852 inputs: []inputInfo{ 2853 {1, 2}, // CX 2854 {0, 239}, // AX CX DX BX BP SI DI 2855 }, 2856 outputs: []outputInfo{ 2857 {0, 239}, // AX CX DX BX BP SI DI 2858 }, 2859 }, 2860 }, 2861 { 2862 name: "SHRW", 2863 argLen: 2, 2864 resultInArg0: true, 2865 clobberFlags: true, 2866 asm: x86.ASHRW, 2867 reg: regInfo{ 2868 inputs: []inputInfo{ 2869 {1, 2}, // CX 2870 {0, 239}, // AX CX DX BX BP SI DI 2871 }, 2872 outputs: []outputInfo{ 2873 {0, 239}, // AX CX DX BX BP SI DI 2874 }, 2875 }, 2876 }, 2877 { 2878 name: "SHRB", 2879 argLen: 2, 2880 resultInArg0: true, 2881 clobberFlags: true, 2882 asm: x86.ASHRB, 2883 reg: regInfo{ 2884 inputs: []inputInfo{ 2885 {1, 2}, // CX 2886 {0, 239}, // AX CX DX BX BP SI DI 2887 }, 2888 outputs: []outputInfo{ 2889 {0, 239}, // AX CX DX BX BP SI DI 2890 }, 2891 }, 2892 }, 2893 { 2894 name: "SHRLconst", 2895 auxType: auxInt32, 2896 argLen: 1, 2897 resultInArg0: true, 2898 clobberFlags: true, 2899 asm: x86.ASHRL, 2900 reg: regInfo{ 2901 inputs: []inputInfo{ 2902 {0, 239}, // AX CX DX BX BP SI DI 2903 }, 2904 outputs: []outputInfo{ 2905 {0, 239}, // AX CX DX BX BP SI DI 2906 }, 2907 }, 2908 }, 2909 { 2910 name: "SHRWconst", 2911 auxType: auxInt16, 2912 argLen: 1, 2913 resultInArg0: true, 2914 clobberFlags: true, 2915 asm: x86.ASHRW, 2916 reg: regInfo{ 2917 inputs: []inputInfo{ 2918 {0, 239}, // AX CX DX BX BP SI DI 2919 }, 2920 outputs: []outputInfo{ 2921 {0, 239}, // AX CX DX BX BP SI DI 2922 }, 2923 }, 2924 }, 2925 { 2926 name: "SHRBconst", 2927 auxType: auxInt8, 2928 argLen: 1, 2929 resultInArg0: true, 2930 clobberFlags: true, 2931 asm: x86.ASHRB, 2932 reg: regInfo{ 2933 inputs: []inputInfo{ 2934 {0, 239}, // AX CX DX BX BP SI DI 2935 }, 2936 outputs: []outputInfo{ 2937 {0, 239}, // AX CX DX BX BP SI DI 2938 }, 2939 }, 2940 }, 2941 { 2942 name: "SARL", 2943 argLen: 2, 2944 resultInArg0: true, 2945 clobberFlags: true, 2946 asm: x86.ASARL, 2947 reg: regInfo{ 2948 inputs: []inputInfo{ 2949 {1, 2}, // CX 2950 {0, 239}, // AX CX DX BX BP SI DI 2951 }, 2952 outputs: []outputInfo{ 2953 {0, 239}, // AX CX DX BX BP SI DI 2954 }, 2955 }, 2956 }, 2957 { 2958 name: "SARW", 2959 argLen: 2, 2960 resultInArg0: true, 2961 clobberFlags: true, 2962 asm: x86.ASARW, 2963 reg: regInfo{ 2964 inputs: []inputInfo{ 2965 {1, 2}, // CX 2966 {0, 239}, // AX CX DX BX BP SI DI 2967 }, 2968 outputs: []outputInfo{ 2969 {0, 239}, // AX CX DX BX BP SI DI 2970 }, 2971 }, 2972 }, 2973 { 2974 name: "SARB", 2975 argLen: 2, 2976 resultInArg0: true, 2977 clobberFlags: true, 2978 asm: x86.ASARB, 2979 reg: regInfo{ 2980 inputs: []inputInfo{ 2981 {1, 2}, // CX 2982 {0, 239}, // AX CX DX BX BP SI DI 2983 }, 2984 outputs: []outputInfo{ 2985 {0, 239}, // AX CX DX BX BP SI DI 2986 }, 2987 }, 2988 }, 2989 { 2990 name: "SARLconst", 2991 auxType: auxInt32, 2992 argLen: 1, 2993 resultInArg0: true, 2994 clobberFlags: true, 2995 asm: x86.ASARL, 2996 reg: regInfo{ 2997 inputs: []inputInfo{ 2998 {0, 239}, // AX CX DX BX BP SI DI 2999 }, 3000 outputs: []outputInfo{ 3001 {0, 239}, // AX CX DX BX BP SI DI 3002 }, 3003 }, 3004 }, 3005 { 3006 name: "SARWconst", 3007 auxType: auxInt16, 3008 argLen: 1, 3009 resultInArg0: true, 3010 clobberFlags: true, 3011 asm: x86.ASARW, 3012 reg: regInfo{ 3013 inputs: []inputInfo{ 3014 {0, 239}, // AX CX DX BX BP SI DI 3015 }, 3016 outputs: []outputInfo{ 3017 {0, 239}, // AX CX DX BX BP SI DI 3018 }, 3019 }, 3020 }, 3021 { 3022 name: "SARBconst", 3023 auxType: auxInt8, 3024 argLen: 1, 3025 resultInArg0: true, 3026 clobberFlags: true, 3027 asm: x86.ASARB, 3028 reg: regInfo{ 3029 inputs: []inputInfo{ 3030 {0, 239}, // AX CX DX BX BP SI DI 3031 }, 3032 outputs: []outputInfo{ 3033 {0, 239}, // AX CX DX BX BP SI DI 3034 }, 3035 }, 3036 }, 3037 { 3038 name: "ROLLconst", 3039 auxType: auxInt32, 3040 argLen: 1, 3041 resultInArg0: true, 3042 clobberFlags: true, 3043 asm: x86.AROLL, 3044 reg: regInfo{ 3045 inputs: []inputInfo{ 3046 {0, 239}, // AX CX DX BX BP SI DI 3047 }, 3048 outputs: []outputInfo{ 3049 {0, 239}, // AX CX DX BX BP SI DI 3050 }, 3051 }, 3052 }, 3053 { 3054 name: "ROLWconst", 3055 auxType: auxInt16, 3056 argLen: 1, 3057 resultInArg0: true, 3058 clobberFlags: true, 3059 asm: x86.AROLW, 3060 reg: regInfo{ 3061 inputs: []inputInfo{ 3062 {0, 239}, // AX CX DX BX BP SI DI 3063 }, 3064 outputs: []outputInfo{ 3065 {0, 239}, // AX CX DX BX BP SI DI 3066 }, 3067 }, 3068 }, 3069 { 3070 name: "ROLBconst", 3071 auxType: auxInt8, 3072 argLen: 1, 3073 resultInArg0: true, 3074 clobberFlags: true, 3075 asm: x86.AROLB, 3076 reg: regInfo{ 3077 inputs: []inputInfo{ 3078 {0, 239}, // AX CX DX BX BP SI DI 3079 }, 3080 outputs: []outputInfo{ 3081 {0, 239}, // AX CX DX BX BP SI DI 3082 }, 3083 }, 3084 }, 3085 { 3086 name: "NEGL", 3087 argLen: 1, 3088 resultInArg0: true, 3089 clobberFlags: true, 3090 asm: x86.ANEGL, 3091 reg: regInfo{ 3092 inputs: []inputInfo{ 3093 {0, 239}, // AX CX DX BX BP SI DI 3094 }, 3095 outputs: []outputInfo{ 3096 {0, 239}, // AX CX DX BX BP SI DI 3097 }, 3098 }, 3099 }, 3100 { 3101 name: "NOTL", 3102 argLen: 1, 3103 resultInArg0: true, 3104 clobberFlags: true, 3105 asm: x86.ANOTL, 3106 reg: regInfo{ 3107 inputs: []inputInfo{ 3108 {0, 239}, // AX CX DX BX BP SI DI 3109 }, 3110 outputs: []outputInfo{ 3111 {0, 239}, // AX CX DX BX BP SI DI 3112 }, 3113 }, 3114 }, 3115 { 3116 name: "BSFL", 3117 argLen: 1, 3118 clobberFlags: true, 3119 asm: x86.ABSFL, 3120 reg: regInfo{ 3121 inputs: []inputInfo{ 3122 {0, 239}, // AX CX DX BX BP SI DI 3123 }, 3124 outputs: []outputInfo{ 3125 {0, 239}, // AX CX DX BX BP SI DI 3126 }, 3127 }, 3128 }, 3129 { 3130 name: "BSFW", 3131 argLen: 1, 3132 clobberFlags: true, 3133 asm: x86.ABSFW, 3134 reg: regInfo{ 3135 inputs: []inputInfo{ 3136 {0, 239}, // AX CX DX BX BP SI DI 3137 }, 3138 outputs: []outputInfo{ 3139 {0, 239}, // AX CX DX BX BP SI DI 3140 }, 3141 }, 3142 }, 3143 { 3144 name: "BSRL", 3145 argLen: 1, 3146 clobberFlags: true, 3147 asm: x86.ABSRL, 3148 reg: regInfo{ 3149 inputs: []inputInfo{ 3150 {0, 239}, // AX CX DX BX BP SI DI 3151 }, 3152 outputs: []outputInfo{ 3153 {0, 239}, // AX CX DX BX BP SI DI 3154 }, 3155 }, 3156 }, 3157 { 3158 name: "BSRW", 3159 argLen: 1, 3160 clobberFlags: true, 3161 asm: x86.ABSRW, 3162 reg: regInfo{ 3163 inputs: []inputInfo{ 3164 {0, 239}, // AX CX DX BX BP SI DI 3165 }, 3166 outputs: []outputInfo{ 3167 {0, 239}, // AX CX DX BX BP SI DI 3168 }, 3169 }, 3170 }, 3171 { 3172 name: "BSWAPL", 3173 argLen: 1, 3174 resultInArg0: true, 3175 clobberFlags: true, 3176 asm: x86.ABSWAPL, 3177 reg: regInfo{ 3178 inputs: []inputInfo{ 3179 {0, 239}, // AX CX DX BX BP SI DI 3180 }, 3181 outputs: []outputInfo{ 3182 {0, 239}, // AX CX DX BX BP SI DI 3183 }, 3184 }, 3185 }, 3186 { 3187 name: "SQRTSD", 3188 argLen: 1, 3189 asm: x86.ASQRTSD, 3190 reg: regInfo{ 3191 inputs: []inputInfo{ 3192 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3193 }, 3194 outputs: []outputInfo{ 3195 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3196 }, 3197 }, 3198 }, 3199 { 3200 name: "SBBLcarrymask", 3201 argLen: 1, 3202 asm: x86.ASBBL, 3203 reg: regInfo{ 3204 outputs: []outputInfo{ 3205 {0, 239}, // AX CX DX BX BP SI DI 3206 }, 3207 }, 3208 }, 3209 { 3210 name: "SETEQ", 3211 argLen: 1, 3212 asm: x86.ASETEQ, 3213 reg: regInfo{ 3214 outputs: []outputInfo{ 3215 {0, 239}, // AX CX DX BX BP SI DI 3216 }, 3217 }, 3218 }, 3219 { 3220 name: "SETNE", 3221 argLen: 1, 3222 asm: x86.ASETNE, 3223 reg: regInfo{ 3224 outputs: []outputInfo{ 3225 {0, 239}, // AX CX DX BX BP SI DI 3226 }, 3227 }, 3228 }, 3229 { 3230 name: "SETL", 3231 argLen: 1, 3232 asm: x86.ASETLT, 3233 reg: regInfo{ 3234 outputs: []outputInfo{ 3235 {0, 239}, // AX CX DX BX BP SI DI 3236 }, 3237 }, 3238 }, 3239 { 3240 name: "SETLE", 3241 argLen: 1, 3242 asm: x86.ASETLE, 3243 reg: regInfo{ 3244 outputs: []outputInfo{ 3245 {0, 239}, // AX CX DX BX BP SI DI 3246 }, 3247 }, 3248 }, 3249 { 3250 name: "SETG", 3251 argLen: 1, 3252 asm: x86.ASETGT, 3253 reg: regInfo{ 3254 outputs: []outputInfo{ 3255 {0, 239}, // AX CX DX BX BP SI DI 3256 }, 3257 }, 3258 }, 3259 { 3260 name: "SETGE", 3261 argLen: 1, 3262 asm: x86.ASETGE, 3263 reg: regInfo{ 3264 outputs: []outputInfo{ 3265 {0, 239}, // AX CX DX BX BP SI DI 3266 }, 3267 }, 3268 }, 3269 { 3270 name: "SETB", 3271 argLen: 1, 3272 asm: x86.ASETCS, 3273 reg: regInfo{ 3274 outputs: []outputInfo{ 3275 {0, 239}, // AX CX DX BX BP SI DI 3276 }, 3277 }, 3278 }, 3279 { 3280 name: "SETBE", 3281 argLen: 1, 3282 asm: x86.ASETLS, 3283 reg: regInfo{ 3284 outputs: []outputInfo{ 3285 {0, 239}, // AX CX DX BX BP SI DI 3286 }, 3287 }, 3288 }, 3289 { 3290 name: "SETA", 3291 argLen: 1, 3292 asm: x86.ASETHI, 3293 reg: regInfo{ 3294 outputs: []outputInfo{ 3295 {0, 239}, // AX CX DX BX BP SI DI 3296 }, 3297 }, 3298 }, 3299 { 3300 name: "SETAE", 3301 argLen: 1, 3302 asm: x86.ASETCC, 3303 reg: regInfo{ 3304 outputs: []outputInfo{ 3305 {0, 239}, // AX CX DX BX BP SI DI 3306 }, 3307 }, 3308 }, 3309 { 3310 name: "SETEQF", 3311 argLen: 1, 3312 clobberFlags: true, 3313 asm: x86.ASETEQ, 3314 reg: regInfo{ 3315 clobbers: 1, // AX 3316 outputs: []outputInfo{ 3317 {0, 238}, // CX DX BX BP SI DI 3318 }, 3319 }, 3320 }, 3321 { 3322 name: "SETNEF", 3323 argLen: 1, 3324 clobberFlags: true, 3325 asm: x86.ASETNE, 3326 reg: regInfo{ 3327 clobbers: 1, // AX 3328 outputs: []outputInfo{ 3329 {0, 238}, // CX DX BX BP SI DI 3330 }, 3331 }, 3332 }, 3333 { 3334 name: "SETORD", 3335 argLen: 1, 3336 asm: x86.ASETPC, 3337 reg: regInfo{ 3338 outputs: []outputInfo{ 3339 {0, 239}, // AX CX DX BX BP SI DI 3340 }, 3341 }, 3342 }, 3343 { 3344 name: "SETNAN", 3345 argLen: 1, 3346 asm: x86.ASETPS, 3347 reg: regInfo{ 3348 outputs: []outputInfo{ 3349 {0, 239}, // AX CX DX BX BP SI DI 3350 }, 3351 }, 3352 }, 3353 { 3354 name: "SETGF", 3355 argLen: 1, 3356 asm: x86.ASETHI, 3357 reg: regInfo{ 3358 outputs: []outputInfo{ 3359 {0, 239}, // AX CX DX BX BP SI DI 3360 }, 3361 }, 3362 }, 3363 { 3364 name: "SETGEF", 3365 argLen: 1, 3366 asm: x86.ASETCC, 3367 reg: regInfo{ 3368 outputs: []outputInfo{ 3369 {0, 239}, // AX CX DX BX BP SI DI 3370 }, 3371 }, 3372 }, 3373 { 3374 name: "MOVBLSX", 3375 argLen: 1, 3376 asm: x86.AMOVBLSX, 3377 reg: regInfo{ 3378 inputs: []inputInfo{ 3379 {0, 239}, // AX CX DX BX BP SI DI 3380 }, 3381 outputs: []outputInfo{ 3382 {0, 239}, // AX CX DX BX BP SI DI 3383 }, 3384 }, 3385 }, 3386 { 3387 name: "MOVBLZX", 3388 argLen: 1, 3389 asm: x86.AMOVBLZX, 3390 reg: regInfo{ 3391 inputs: []inputInfo{ 3392 {0, 239}, // AX CX DX BX BP SI DI 3393 }, 3394 outputs: []outputInfo{ 3395 {0, 239}, // AX CX DX BX BP SI DI 3396 }, 3397 }, 3398 }, 3399 { 3400 name: "MOVWLSX", 3401 argLen: 1, 3402 asm: x86.AMOVWLSX, 3403 reg: regInfo{ 3404 inputs: []inputInfo{ 3405 {0, 239}, // AX CX DX BX BP SI DI 3406 }, 3407 outputs: []outputInfo{ 3408 {0, 239}, // AX CX DX BX BP SI DI 3409 }, 3410 }, 3411 }, 3412 { 3413 name: "MOVWLZX", 3414 argLen: 1, 3415 asm: x86.AMOVWLZX, 3416 reg: regInfo{ 3417 inputs: []inputInfo{ 3418 {0, 239}, // AX CX DX BX BP SI DI 3419 }, 3420 outputs: []outputInfo{ 3421 {0, 239}, // AX CX DX BX BP SI DI 3422 }, 3423 }, 3424 }, 3425 { 3426 name: "MOVLconst", 3427 auxType: auxInt32, 3428 argLen: 0, 3429 rematerializeable: true, 3430 asm: x86.AMOVL, 3431 reg: regInfo{ 3432 outputs: []outputInfo{ 3433 {0, 239}, // AX CX DX BX BP SI DI 3434 }, 3435 }, 3436 }, 3437 { 3438 name: "CVTTSD2SL", 3439 argLen: 1, 3440 usesScratch: true, 3441 asm: x86.ACVTTSD2SL, 3442 reg: regInfo{ 3443 inputs: []inputInfo{ 3444 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3445 }, 3446 outputs: []outputInfo{ 3447 {0, 239}, // AX CX DX BX BP SI DI 3448 }, 3449 }, 3450 }, 3451 { 3452 name: "CVTTSS2SL", 3453 argLen: 1, 3454 usesScratch: true, 3455 asm: x86.ACVTTSS2SL, 3456 reg: regInfo{ 3457 inputs: []inputInfo{ 3458 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3459 }, 3460 outputs: []outputInfo{ 3461 {0, 239}, // AX CX DX BX BP SI DI 3462 }, 3463 }, 3464 }, 3465 { 3466 name: "CVTSL2SS", 3467 argLen: 1, 3468 usesScratch: true, 3469 asm: x86.ACVTSL2SS, 3470 reg: regInfo{ 3471 inputs: []inputInfo{ 3472 {0, 239}, // AX CX DX BX BP SI DI 3473 }, 3474 outputs: []outputInfo{ 3475 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3476 }, 3477 }, 3478 }, 3479 { 3480 name: "CVTSL2SD", 3481 argLen: 1, 3482 usesScratch: true, 3483 asm: x86.ACVTSL2SD, 3484 reg: regInfo{ 3485 inputs: []inputInfo{ 3486 {0, 239}, // AX CX DX BX BP SI DI 3487 }, 3488 outputs: []outputInfo{ 3489 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3490 }, 3491 }, 3492 }, 3493 { 3494 name: "CVTSD2SS", 3495 argLen: 1, 3496 usesScratch: true, 3497 asm: x86.ACVTSD2SS, 3498 reg: regInfo{ 3499 inputs: []inputInfo{ 3500 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3501 }, 3502 outputs: []outputInfo{ 3503 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3504 }, 3505 }, 3506 }, 3507 { 3508 name: "CVTSS2SD", 3509 argLen: 1, 3510 asm: x86.ACVTSS2SD, 3511 reg: regInfo{ 3512 inputs: []inputInfo{ 3513 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3514 }, 3515 outputs: []outputInfo{ 3516 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3517 }, 3518 }, 3519 }, 3520 { 3521 name: "PXOR", 3522 argLen: 2, 3523 commutative: true, 3524 resultInArg0: true, 3525 asm: x86.APXOR, 3526 reg: regInfo{ 3527 inputs: []inputInfo{ 3528 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3529 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3530 }, 3531 outputs: []outputInfo{ 3532 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3533 }, 3534 }, 3535 }, 3536 { 3537 name: "LEAL", 3538 auxType: auxSymOff, 3539 argLen: 1, 3540 rematerializeable: true, 3541 reg: regInfo{ 3542 inputs: []inputInfo{ 3543 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3544 }, 3545 outputs: []outputInfo{ 3546 {0, 239}, // AX CX DX BX BP SI DI 3547 }, 3548 }, 3549 }, 3550 { 3551 name: "LEAL1", 3552 auxType: auxSymOff, 3553 argLen: 2, 3554 reg: regInfo{ 3555 inputs: []inputInfo{ 3556 {1, 255}, // AX CX DX BX SP BP SI DI 3557 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3558 }, 3559 outputs: []outputInfo{ 3560 {0, 239}, // AX CX DX BX BP SI DI 3561 }, 3562 }, 3563 }, 3564 { 3565 name: "LEAL2", 3566 auxType: auxSymOff, 3567 argLen: 2, 3568 reg: regInfo{ 3569 inputs: []inputInfo{ 3570 {1, 255}, // AX CX DX BX SP BP SI DI 3571 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3572 }, 3573 outputs: []outputInfo{ 3574 {0, 239}, // AX CX DX BX BP SI DI 3575 }, 3576 }, 3577 }, 3578 { 3579 name: "LEAL4", 3580 auxType: auxSymOff, 3581 argLen: 2, 3582 reg: regInfo{ 3583 inputs: []inputInfo{ 3584 {1, 255}, // AX CX DX BX SP BP SI DI 3585 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3586 }, 3587 outputs: []outputInfo{ 3588 {0, 239}, // AX CX DX BX BP SI DI 3589 }, 3590 }, 3591 }, 3592 { 3593 name: "LEAL8", 3594 auxType: auxSymOff, 3595 argLen: 2, 3596 reg: regInfo{ 3597 inputs: []inputInfo{ 3598 {1, 255}, // AX CX DX BX SP BP SI DI 3599 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3600 }, 3601 outputs: []outputInfo{ 3602 {0, 239}, // AX CX DX BX BP SI DI 3603 }, 3604 }, 3605 }, 3606 { 3607 name: "MOVBload", 3608 auxType: auxSymOff, 3609 argLen: 2, 3610 faultOnNilArg0: true, 3611 asm: x86.AMOVBLZX, 3612 reg: regInfo{ 3613 inputs: []inputInfo{ 3614 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3615 }, 3616 outputs: []outputInfo{ 3617 {0, 239}, // AX CX DX BX BP SI DI 3618 }, 3619 }, 3620 }, 3621 { 3622 name: "MOVBLSXload", 3623 auxType: auxSymOff, 3624 argLen: 2, 3625 faultOnNilArg0: true, 3626 asm: x86.AMOVBLSX, 3627 reg: regInfo{ 3628 inputs: []inputInfo{ 3629 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3630 }, 3631 outputs: []outputInfo{ 3632 {0, 239}, // AX CX DX BX BP SI DI 3633 }, 3634 }, 3635 }, 3636 { 3637 name: "MOVWload", 3638 auxType: auxSymOff, 3639 argLen: 2, 3640 faultOnNilArg0: true, 3641 asm: x86.AMOVWLZX, 3642 reg: regInfo{ 3643 inputs: []inputInfo{ 3644 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3645 }, 3646 outputs: []outputInfo{ 3647 {0, 239}, // AX CX DX BX BP SI DI 3648 }, 3649 }, 3650 }, 3651 { 3652 name: "MOVWLSXload", 3653 auxType: auxSymOff, 3654 argLen: 2, 3655 faultOnNilArg0: true, 3656 asm: x86.AMOVWLSX, 3657 reg: regInfo{ 3658 inputs: []inputInfo{ 3659 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3660 }, 3661 outputs: []outputInfo{ 3662 {0, 239}, // AX CX DX BX BP SI DI 3663 }, 3664 }, 3665 }, 3666 { 3667 name: "MOVLload", 3668 auxType: auxSymOff, 3669 argLen: 2, 3670 faultOnNilArg0: true, 3671 asm: x86.AMOVL, 3672 reg: regInfo{ 3673 inputs: []inputInfo{ 3674 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3675 }, 3676 outputs: []outputInfo{ 3677 {0, 239}, // AX CX DX BX BP SI DI 3678 }, 3679 }, 3680 }, 3681 { 3682 name: "MOVBstore", 3683 auxType: auxSymOff, 3684 argLen: 3, 3685 faultOnNilArg0: true, 3686 asm: x86.AMOVB, 3687 reg: regInfo{ 3688 inputs: []inputInfo{ 3689 {1, 255}, // AX CX DX BX SP BP SI DI 3690 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3691 }, 3692 }, 3693 }, 3694 { 3695 name: "MOVWstore", 3696 auxType: auxSymOff, 3697 argLen: 3, 3698 faultOnNilArg0: true, 3699 asm: x86.AMOVW, 3700 reg: regInfo{ 3701 inputs: []inputInfo{ 3702 {1, 255}, // AX CX DX BX SP BP SI DI 3703 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3704 }, 3705 }, 3706 }, 3707 { 3708 name: "MOVLstore", 3709 auxType: auxSymOff, 3710 argLen: 3, 3711 faultOnNilArg0: true, 3712 asm: x86.AMOVL, 3713 reg: regInfo{ 3714 inputs: []inputInfo{ 3715 {1, 255}, // AX CX DX BX SP BP SI DI 3716 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3717 }, 3718 }, 3719 }, 3720 { 3721 name: "MOVBloadidx1", 3722 auxType: auxSymOff, 3723 argLen: 3, 3724 asm: x86.AMOVBLZX, 3725 reg: regInfo{ 3726 inputs: []inputInfo{ 3727 {1, 255}, // AX CX DX BX SP BP SI DI 3728 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3729 }, 3730 outputs: []outputInfo{ 3731 {0, 239}, // AX CX DX BX BP SI DI 3732 }, 3733 }, 3734 }, 3735 { 3736 name: "MOVWloadidx1", 3737 auxType: auxSymOff, 3738 argLen: 3, 3739 asm: x86.AMOVWLZX, 3740 reg: regInfo{ 3741 inputs: []inputInfo{ 3742 {1, 255}, // AX CX DX BX SP BP SI DI 3743 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3744 }, 3745 outputs: []outputInfo{ 3746 {0, 239}, // AX CX DX BX BP SI DI 3747 }, 3748 }, 3749 }, 3750 { 3751 name: "MOVWloadidx2", 3752 auxType: auxSymOff, 3753 argLen: 3, 3754 asm: x86.AMOVWLZX, 3755 reg: regInfo{ 3756 inputs: []inputInfo{ 3757 {1, 255}, // AX CX DX BX SP BP SI DI 3758 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3759 }, 3760 outputs: []outputInfo{ 3761 {0, 239}, // AX CX DX BX BP SI DI 3762 }, 3763 }, 3764 }, 3765 { 3766 name: "MOVLloadidx1", 3767 auxType: auxSymOff, 3768 argLen: 3, 3769 asm: x86.AMOVL, 3770 reg: regInfo{ 3771 inputs: []inputInfo{ 3772 {1, 255}, // AX CX DX BX SP BP SI DI 3773 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3774 }, 3775 outputs: []outputInfo{ 3776 {0, 239}, // AX CX DX BX BP SI DI 3777 }, 3778 }, 3779 }, 3780 { 3781 name: "MOVLloadidx4", 3782 auxType: auxSymOff, 3783 argLen: 3, 3784 asm: x86.AMOVL, 3785 reg: regInfo{ 3786 inputs: []inputInfo{ 3787 {1, 255}, // AX CX DX BX SP BP SI DI 3788 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3789 }, 3790 outputs: []outputInfo{ 3791 {0, 239}, // AX CX DX BX BP SI DI 3792 }, 3793 }, 3794 }, 3795 { 3796 name: "MOVBstoreidx1", 3797 auxType: auxSymOff, 3798 argLen: 4, 3799 asm: x86.AMOVB, 3800 reg: regInfo{ 3801 inputs: []inputInfo{ 3802 {1, 255}, // AX CX DX BX SP BP SI DI 3803 {2, 255}, // AX CX DX BX SP BP SI DI 3804 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3805 }, 3806 }, 3807 }, 3808 { 3809 name: "MOVWstoreidx1", 3810 auxType: auxSymOff, 3811 argLen: 4, 3812 asm: x86.AMOVW, 3813 reg: regInfo{ 3814 inputs: []inputInfo{ 3815 {1, 255}, // AX CX DX BX SP BP SI DI 3816 {2, 255}, // AX CX DX BX SP BP SI DI 3817 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3818 }, 3819 }, 3820 }, 3821 { 3822 name: "MOVWstoreidx2", 3823 auxType: auxSymOff, 3824 argLen: 4, 3825 asm: x86.AMOVW, 3826 reg: regInfo{ 3827 inputs: []inputInfo{ 3828 {1, 255}, // AX CX DX BX SP BP SI DI 3829 {2, 255}, // AX CX DX BX SP BP SI DI 3830 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3831 }, 3832 }, 3833 }, 3834 { 3835 name: "MOVLstoreidx1", 3836 auxType: auxSymOff, 3837 argLen: 4, 3838 asm: x86.AMOVL, 3839 reg: regInfo{ 3840 inputs: []inputInfo{ 3841 {1, 255}, // AX CX DX BX SP BP SI DI 3842 {2, 255}, // AX CX DX BX SP BP SI DI 3843 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3844 }, 3845 }, 3846 }, 3847 { 3848 name: "MOVLstoreidx4", 3849 auxType: auxSymOff, 3850 argLen: 4, 3851 asm: x86.AMOVL, 3852 reg: regInfo{ 3853 inputs: []inputInfo{ 3854 {1, 255}, // AX CX DX BX SP BP SI DI 3855 {2, 255}, // AX CX DX BX SP BP SI DI 3856 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3857 }, 3858 }, 3859 }, 3860 { 3861 name: "MOVBstoreconst", 3862 auxType: auxSymValAndOff, 3863 argLen: 2, 3864 faultOnNilArg0: true, 3865 asm: x86.AMOVB, 3866 reg: regInfo{ 3867 inputs: []inputInfo{ 3868 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3869 }, 3870 }, 3871 }, 3872 { 3873 name: "MOVWstoreconst", 3874 auxType: auxSymValAndOff, 3875 argLen: 2, 3876 faultOnNilArg0: true, 3877 asm: x86.AMOVW, 3878 reg: regInfo{ 3879 inputs: []inputInfo{ 3880 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3881 }, 3882 }, 3883 }, 3884 { 3885 name: "MOVLstoreconst", 3886 auxType: auxSymValAndOff, 3887 argLen: 2, 3888 faultOnNilArg0: true, 3889 asm: x86.AMOVL, 3890 reg: regInfo{ 3891 inputs: []inputInfo{ 3892 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3893 }, 3894 }, 3895 }, 3896 { 3897 name: "MOVBstoreconstidx1", 3898 auxType: auxSymValAndOff, 3899 argLen: 3, 3900 asm: x86.AMOVB, 3901 reg: regInfo{ 3902 inputs: []inputInfo{ 3903 {1, 255}, // AX CX DX BX SP BP SI DI 3904 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3905 }, 3906 }, 3907 }, 3908 { 3909 name: "MOVWstoreconstidx1", 3910 auxType: auxSymValAndOff, 3911 argLen: 3, 3912 asm: x86.AMOVW, 3913 reg: regInfo{ 3914 inputs: []inputInfo{ 3915 {1, 255}, // AX CX DX BX SP BP SI DI 3916 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3917 }, 3918 }, 3919 }, 3920 { 3921 name: "MOVWstoreconstidx2", 3922 auxType: auxSymValAndOff, 3923 argLen: 3, 3924 asm: x86.AMOVW, 3925 reg: regInfo{ 3926 inputs: []inputInfo{ 3927 {1, 255}, // AX CX DX BX SP BP SI DI 3928 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3929 }, 3930 }, 3931 }, 3932 { 3933 name: "MOVLstoreconstidx1", 3934 auxType: auxSymValAndOff, 3935 argLen: 3, 3936 asm: x86.AMOVL, 3937 reg: regInfo{ 3938 inputs: []inputInfo{ 3939 {1, 255}, // AX CX DX BX SP BP SI DI 3940 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3941 }, 3942 }, 3943 }, 3944 { 3945 name: "MOVLstoreconstidx4", 3946 auxType: auxSymValAndOff, 3947 argLen: 3, 3948 asm: x86.AMOVL, 3949 reg: regInfo{ 3950 inputs: []inputInfo{ 3951 {1, 255}, // AX CX DX BX SP BP SI DI 3952 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3953 }, 3954 }, 3955 }, 3956 { 3957 name: "DUFFZERO", 3958 auxType: auxInt64, 3959 argLen: 3, 3960 reg: regInfo{ 3961 inputs: []inputInfo{ 3962 {0, 128}, // DI 3963 {1, 1}, // AX 3964 }, 3965 clobbers: 130, // CX DI 3966 }, 3967 }, 3968 { 3969 name: "REPSTOSL", 3970 argLen: 4, 3971 reg: regInfo{ 3972 inputs: []inputInfo{ 3973 {0, 128}, // DI 3974 {1, 2}, // CX 3975 {2, 1}, // AX 3976 }, 3977 clobbers: 130, // CX DI 3978 }, 3979 }, 3980 { 3981 name: "CALLstatic", 3982 auxType: auxSymOff, 3983 argLen: 1, 3984 clobberFlags: true, 3985 call: true, 3986 reg: regInfo{ 3987 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 3988 }, 3989 }, 3990 { 3991 name: "CALLclosure", 3992 auxType: auxInt64, 3993 argLen: 3, 3994 clobberFlags: true, 3995 call: true, 3996 reg: regInfo{ 3997 inputs: []inputInfo{ 3998 {1, 4}, // DX 3999 {0, 255}, // AX CX DX BX SP BP SI DI 4000 }, 4001 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4002 }, 4003 }, 4004 { 4005 name: "CALLdefer", 4006 auxType: auxInt64, 4007 argLen: 1, 4008 clobberFlags: true, 4009 call: true, 4010 reg: regInfo{ 4011 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4012 }, 4013 }, 4014 { 4015 name: "CALLgo", 4016 auxType: auxInt64, 4017 argLen: 1, 4018 clobberFlags: true, 4019 call: true, 4020 reg: regInfo{ 4021 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4022 }, 4023 }, 4024 { 4025 name: "CALLinter", 4026 auxType: auxInt64, 4027 argLen: 2, 4028 clobberFlags: true, 4029 call: true, 4030 reg: regInfo{ 4031 inputs: []inputInfo{ 4032 {0, 239}, // AX CX DX BX BP SI DI 4033 }, 4034 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4035 }, 4036 }, 4037 { 4038 name: "DUFFCOPY", 4039 auxType: auxInt64, 4040 argLen: 3, 4041 clobberFlags: true, 4042 reg: regInfo{ 4043 inputs: []inputInfo{ 4044 {0, 128}, // DI 4045 {1, 64}, // SI 4046 }, 4047 clobbers: 194, // CX SI DI 4048 }, 4049 }, 4050 { 4051 name: "REPMOVSL", 4052 argLen: 4, 4053 reg: regInfo{ 4054 inputs: []inputInfo{ 4055 {0, 128}, // DI 4056 {1, 64}, // SI 4057 {2, 2}, // CX 4058 }, 4059 clobbers: 194, // CX SI DI 4060 }, 4061 }, 4062 { 4063 name: "InvertFlags", 4064 argLen: 1, 4065 reg: regInfo{}, 4066 }, 4067 { 4068 name: "LoweredGetG", 4069 argLen: 1, 4070 reg: regInfo{ 4071 outputs: []outputInfo{ 4072 {0, 239}, // AX CX DX BX BP SI DI 4073 }, 4074 }, 4075 }, 4076 { 4077 name: "LoweredGetClosurePtr", 4078 argLen: 0, 4079 reg: regInfo{ 4080 outputs: []outputInfo{ 4081 {0, 4}, // DX 4082 }, 4083 }, 4084 }, 4085 { 4086 name: "LoweredNilCheck", 4087 argLen: 2, 4088 clobberFlags: true, 4089 nilCheck: true, 4090 faultOnNilArg0: true, 4091 reg: regInfo{ 4092 inputs: []inputInfo{ 4093 {0, 255}, // AX CX DX BX SP BP SI DI 4094 }, 4095 }, 4096 }, 4097 { 4098 name: "MOVLconvert", 4099 argLen: 2, 4100 asm: x86.AMOVL, 4101 reg: regInfo{ 4102 inputs: []inputInfo{ 4103 {0, 239}, // AX CX DX BX BP SI DI 4104 }, 4105 outputs: []outputInfo{ 4106 {0, 239}, // AX CX DX BX BP SI DI 4107 }, 4108 }, 4109 }, 4110 { 4111 name: "FlagEQ", 4112 argLen: 0, 4113 reg: regInfo{}, 4114 }, 4115 { 4116 name: "FlagLT_ULT", 4117 argLen: 0, 4118 reg: regInfo{}, 4119 }, 4120 { 4121 name: "FlagLT_UGT", 4122 argLen: 0, 4123 reg: regInfo{}, 4124 }, 4125 { 4126 name: "FlagGT_UGT", 4127 argLen: 0, 4128 reg: regInfo{}, 4129 }, 4130 { 4131 name: "FlagGT_ULT", 4132 argLen: 0, 4133 reg: regInfo{}, 4134 }, 4135 { 4136 name: "FCHS", 4137 argLen: 1, 4138 reg: regInfo{ 4139 inputs: []inputInfo{ 4140 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4141 }, 4142 outputs: []outputInfo{ 4143 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4144 }, 4145 }, 4146 }, 4147 { 4148 name: "MOVSSconst1", 4149 auxType: auxFloat32, 4150 argLen: 0, 4151 reg: regInfo{ 4152 outputs: []outputInfo{ 4153 {0, 239}, // AX CX DX BX BP SI DI 4154 }, 4155 }, 4156 }, 4157 { 4158 name: "MOVSDconst1", 4159 auxType: auxFloat64, 4160 argLen: 0, 4161 reg: regInfo{ 4162 outputs: []outputInfo{ 4163 {0, 239}, // AX CX DX BX BP SI DI 4164 }, 4165 }, 4166 }, 4167 { 4168 name: "MOVSSconst2", 4169 argLen: 1, 4170 asm: x86.AMOVSS, 4171 reg: regInfo{ 4172 inputs: []inputInfo{ 4173 {0, 239}, // AX CX DX BX BP SI DI 4174 }, 4175 outputs: []outputInfo{ 4176 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4177 }, 4178 }, 4179 }, 4180 { 4181 name: "MOVSDconst2", 4182 argLen: 1, 4183 asm: x86.AMOVSD, 4184 reg: regInfo{ 4185 inputs: []inputInfo{ 4186 {0, 239}, // AX CX DX BX BP SI DI 4187 }, 4188 outputs: []outputInfo{ 4189 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4190 }, 4191 }, 4192 }, 4193 4194 { 4195 name: "ADDSS", 4196 argLen: 2, 4197 commutative: true, 4198 resultInArg0: true, 4199 asm: x86.AADDSS, 4200 reg: regInfo{ 4201 inputs: []inputInfo{ 4202 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4203 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4204 }, 4205 outputs: []outputInfo{ 4206 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4207 }, 4208 }, 4209 }, 4210 { 4211 name: "ADDSD", 4212 argLen: 2, 4213 commutative: true, 4214 resultInArg0: true, 4215 asm: x86.AADDSD, 4216 reg: regInfo{ 4217 inputs: []inputInfo{ 4218 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4219 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4220 }, 4221 outputs: []outputInfo{ 4222 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4223 }, 4224 }, 4225 }, 4226 { 4227 name: "SUBSS", 4228 argLen: 2, 4229 resultInArg0: true, 4230 asm: x86.ASUBSS, 4231 reg: regInfo{ 4232 inputs: []inputInfo{ 4233 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4234 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4235 }, 4236 outputs: []outputInfo{ 4237 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4238 }, 4239 }, 4240 }, 4241 { 4242 name: "SUBSD", 4243 argLen: 2, 4244 resultInArg0: true, 4245 asm: x86.ASUBSD, 4246 reg: regInfo{ 4247 inputs: []inputInfo{ 4248 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4249 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4250 }, 4251 outputs: []outputInfo{ 4252 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4253 }, 4254 }, 4255 }, 4256 { 4257 name: "MULSS", 4258 argLen: 2, 4259 commutative: true, 4260 resultInArg0: true, 4261 asm: x86.AMULSS, 4262 reg: regInfo{ 4263 inputs: []inputInfo{ 4264 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4265 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4266 }, 4267 outputs: []outputInfo{ 4268 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4269 }, 4270 }, 4271 }, 4272 { 4273 name: "MULSD", 4274 argLen: 2, 4275 commutative: true, 4276 resultInArg0: true, 4277 asm: x86.AMULSD, 4278 reg: regInfo{ 4279 inputs: []inputInfo{ 4280 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4281 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4282 }, 4283 outputs: []outputInfo{ 4284 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4285 }, 4286 }, 4287 }, 4288 { 4289 name: "DIVSS", 4290 argLen: 2, 4291 resultInArg0: true, 4292 asm: x86.ADIVSS, 4293 reg: regInfo{ 4294 inputs: []inputInfo{ 4295 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4296 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4297 }, 4298 outputs: []outputInfo{ 4299 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4300 }, 4301 }, 4302 }, 4303 { 4304 name: "DIVSD", 4305 argLen: 2, 4306 resultInArg0: true, 4307 asm: x86.ADIVSD, 4308 reg: regInfo{ 4309 inputs: []inputInfo{ 4310 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4311 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4312 }, 4313 outputs: []outputInfo{ 4314 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4315 }, 4316 }, 4317 }, 4318 { 4319 name: "MOVSSload", 4320 auxType: auxSymOff, 4321 argLen: 2, 4322 faultOnNilArg0: true, 4323 asm: x86.AMOVSS, 4324 reg: regInfo{ 4325 inputs: []inputInfo{ 4326 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4327 }, 4328 outputs: []outputInfo{ 4329 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4330 }, 4331 }, 4332 }, 4333 { 4334 name: "MOVSDload", 4335 auxType: auxSymOff, 4336 argLen: 2, 4337 faultOnNilArg0: true, 4338 asm: x86.AMOVSD, 4339 reg: regInfo{ 4340 inputs: []inputInfo{ 4341 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4342 }, 4343 outputs: []outputInfo{ 4344 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4345 }, 4346 }, 4347 }, 4348 { 4349 name: "MOVSSconst", 4350 auxType: auxFloat32, 4351 argLen: 0, 4352 rematerializeable: true, 4353 asm: x86.AMOVSS, 4354 reg: regInfo{ 4355 outputs: []outputInfo{ 4356 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4357 }, 4358 }, 4359 }, 4360 { 4361 name: "MOVSDconst", 4362 auxType: auxFloat64, 4363 argLen: 0, 4364 rematerializeable: true, 4365 asm: x86.AMOVSD, 4366 reg: regInfo{ 4367 outputs: []outputInfo{ 4368 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4369 }, 4370 }, 4371 }, 4372 { 4373 name: "MOVSSloadidx1", 4374 auxType: auxSymOff, 4375 argLen: 3, 4376 asm: x86.AMOVSS, 4377 reg: regInfo{ 4378 inputs: []inputInfo{ 4379 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4380 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4381 }, 4382 outputs: []outputInfo{ 4383 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4384 }, 4385 }, 4386 }, 4387 { 4388 name: "MOVSSloadidx4", 4389 auxType: auxSymOff, 4390 argLen: 3, 4391 asm: x86.AMOVSS, 4392 reg: regInfo{ 4393 inputs: []inputInfo{ 4394 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4395 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4396 }, 4397 outputs: []outputInfo{ 4398 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4399 }, 4400 }, 4401 }, 4402 { 4403 name: "MOVSDloadidx1", 4404 auxType: auxSymOff, 4405 argLen: 3, 4406 asm: x86.AMOVSD, 4407 reg: regInfo{ 4408 inputs: []inputInfo{ 4409 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4410 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4411 }, 4412 outputs: []outputInfo{ 4413 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4414 }, 4415 }, 4416 }, 4417 { 4418 name: "MOVSDloadidx8", 4419 auxType: auxSymOff, 4420 argLen: 3, 4421 asm: x86.AMOVSD, 4422 reg: regInfo{ 4423 inputs: []inputInfo{ 4424 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4425 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4426 }, 4427 outputs: []outputInfo{ 4428 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4429 }, 4430 }, 4431 }, 4432 { 4433 name: "MOVSSstore", 4434 auxType: auxSymOff, 4435 argLen: 3, 4436 faultOnNilArg0: true, 4437 asm: x86.AMOVSS, 4438 reg: regInfo{ 4439 inputs: []inputInfo{ 4440 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4441 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4442 }, 4443 }, 4444 }, 4445 { 4446 name: "MOVSDstore", 4447 auxType: auxSymOff, 4448 argLen: 3, 4449 faultOnNilArg0: true, 4450 asm: x86.AMOVSD, 4451 reg: regInfo{ 4452 inputs: []inputInfo{ 4453 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4454 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4455 }, 4456 }, 4457 }, 4458 { 4459 name: "MOVSSstoreidx1", 4460 auxType: auxSymOff, 4461 argLen: 4, 4462 asm: x86.AMOVSS, 4463 reg: regInfo{ 4464 inputs: []inputInfo{ 4465 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4466 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4467 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4468 }, 4469 }, 4470 }, 4471 { 4472 name: "MOVSSstoreidx4", 4473 auxType: auxSymOff, 4474 argLen: 4, 4475 asm: x86.AMOVSS, 4476 reg: regInfo{ 4477 inputs: []inputInfo{ 4478 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4479 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4480 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4481 }, 4482 }, 4483 }, 4484 { 4485 name: "MOVSDstoreidx1", 4486 auxType: auxSymOff, 4487 argLen: 4, 4488 asm: x86.AMOVSD, 4489 reg: regInfo{ 4490 inputs: []inputInfo{ 4491 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4492 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4493 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4494 }, 4495 }, 4496 }, 4497 { 4498 name: "MOVSDstoreidx8", 4499 auxType: auxSymOff, 4500 argLen: 4, 4501 asm: x86.AMOVSD, 4502 reg: regInfo{ 4503 inputs: []inputInfo{ 4504 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4505 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4506 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4507 }, 4508 }, 4509 }, 4510 { 4511 name: "ADDQ", 4512 argLen: 2, 4513 commutative: true, 4514 clobberFlags: true, 4515 asm: x86.AADDQ, 4516 reg: regInfo{ 4517 inputs: []inputInfo{ 4518 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4519 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4520 }, 4521 outputs: []outputInfo{ 4522 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4523 }, 4524 }, 4525 }, 4526 { 4527 name: "ADDL", 4528 argLen: 2, 4529 commutative: true, 4530 clobberFlags: true, 4531 asm: x86.AADDL, 4532 reg: regInfo{ 4533 inputs: []inputInfo{ 4534 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4535 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4536 }, 4537 outputs: []outputInfo{ 4538 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4539 }, 4540 }, 4541 }, 4542 { 4543 name: "ADDQconst", 4544 auxType: auxInt64, 4545 argLen: 1, 4546 clobberFlags: true, 4547 asm: x86.AADDQ, 4548 reg: regInfo{ 4549 inputs: []inputInfo{ 4550 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4551 }, 4552 outputs: []outputInfo{ 4553 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4554 }, 4555 }, 4556 }, 4557 { 4558 name: "ADDLconst", 4559 auxType: auxInt32, 4560 argLen: 1, 4561 clobberFlags: true, 4562 asm: x86.AADDL, 4563 reg: regInfo{ 4564 inputs: []inputInfo{ 4565 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4566 }, 4567 outputs: []outputInfo{ 4568 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4569 }, 4570 }, 4571 }, 4572 { 4573 name: "SUBQ", 4574 argLen: 2, 4575 resultInArg0: true, 4576 clobberFlags: true, 4577 asm: x86.ASUBQ, 4578 reg: regInfo{ 4579 inputs: []inputInfo{ 4580 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4581 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4582 }, 4583 outputs: []outputInfo{ 4584 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4585 }, 4586 }, 4587 }, 4588 { 4589 name: "SUBL", 4590 argLen: 2, 4591 resultInArg0: true, 4592 clobberFlags: true, 4593 asm: x86.ASUBL, 4594 reg: regInfo{ 4595 inputs: []inputInfo{ 4596 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4597 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4598 }, 4599 outputs: []outputInfo{ 4600 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4601 }, 4602 }, 4603 }, 4604 { 4605 name: "SUBQconst", 4606 auxType: auxInt64, 4607 argLen: 1, 4608 resultInArg0: true, 4609 clobberFlags: true, 4610 asm: x86.ASUBQ, 4611 reg: regInfo{ 4612 inputs: []inputInfo{ 4613 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4614 }, 4615 outputs: []outputInfo{ 4616 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4617 }, 4618 }, 4619 }, 4620 { 4621 name: "SUBLconst", 4622 auxType: auxInt32, 4623 argLen: 1, 4624 resultInArg0: true, 4625 clobberFlags: true, 4626 asm: x86.ASUBL, 4627 reg: regInfo{ 4628 inputs: []inputInfo{ 4629 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4630 }, 4631 outputs: []outputInfo{ 4632 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4633 }, 4634 }, 4635 }, 4636 { 4637 name: "MULQ", 4638 argLen: 2, 4639 commutative: true, 4640 resultInArg0: true, 4641 clobberFlags: true, 4642 asm: x86.AIMULQ, 4643 reg: regInfo{ 4644 inputs: []inputInfo{ 4645 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4646 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4647 }, 4648 outputs: []outputInfo{ 4649 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4650 }, 4651 }, 4652 }, 4653 { 4654 name: "MULL", 4655 argLen: 2, 4656 commutative: true, 4657 resultInArg0: true, 4658 clobberFlags: true, 4659 asm: x86.AIMULL, 4660 reg: regInfo{ 4661 inputs: []inputInfo{ 4662 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4663 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4664 }, 4665 outputs: []outputInfo{ 4666 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4667 }, 4668 }, 4669 }, 4670 { 4671 name: "MULQconst", 4672 auxType: auxInt64, 4673 argLen: 1, 4674 resultInArg0: true, 4675 clobberFlags: true, 4676 asm: x86.AIMULQ, 4677 reg: regInfo{ 4678 inputs: []inputInfo{ 4679 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4680 }, 4681 outputs: []outputInfo{ 4682 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4683 }, 4684 }, 4685 }, 4686 { 4687 name: "MULLconst", 4688 auxType: auxInt32, 4689 argLen: 1, 4690 resultInArg0: true, 4691 clobberFlags: true, 4692 asm: x86.AIMULL, 4693 reg: regInfo{ 4694 inputs: []inputInfo{ 4695 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4696 }, 4697 outputs: []outputInfo{ 4698 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4699 }, 4700 }, 4701 }, 4702 { 4703 name: "HMULQ", 4704 argLen: 2, 4705 clobberFlags: true, 4706 asm: x86.AIMULQ, 4707 reg: regInfo{ 4708 inputs: []inputInfo{ 4709 {0, 1}, // AX 4710 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4711 }, 4712 clobbers: 1, // AX 4713 outputs: []outputInfo{ 4714 {0, 4}, // DX 4715 }, 4716 }, 4717 }, 4718 { 4719 name: "HMULL", 4720 argLen: 2, 4721 clobberFlags: true, 4722 asm: x86.AIMULL, 4723 reg: regInfo{ 4724 inputs: []inputInfo{ 4725 {0, 1}, // AX 4726 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4727 }, 4728 clobbers: 1, // AX 4729 outputs: []outputInfo{ 4730 {0, 4}, // DX 4731 }, 4732 }, 4733 }, 4734 { 4735 name: "HMULW", 4736 argLen: 2, 4737 clobberFlags: true, 4738 asm: x86.AIMULW, 4739 reg: regInfo{ 4740 inputs: []inputInfo{ 4741 {0, 1}, // AX 4742 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4743 }, 4744 clobbers: 1, // AX 4745 outputs: []outputInfo{ 4746 {0, 4}, // DX 4747 }, 4748 }, 4749 }, 4750 { 4751 name: "HMULB", 4752 argLen: 2, 4753 clobberFlags: true, 4754 asm: x86.AIMULB, 4755 reg: regInfo{ 4756 inputs: []inputInfo{ 4757 {0, 1}, // AX 4758 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4759 }, 4760 clobbers: 1, // AX 4761 outputs: []outputInfo{ 4762 {0, 4}, // DX 4763 }, 4764 }, 4765 }, 4766 { 4767 name: "HMULQU", 4768 argLen: 2, 4769 clobberFlags: true, 4770 asm: x86.AMULQ, 4771 reg: regInfo{ 4772 inputs: []inputInfo{ 4773 {0, 1}, // AX 4774 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4775 }, 4776 clobbers: 1, // AX 4777 outputs: []outputInfo{ 4778 {0, 4}, // DX 4779 }, 4780 }, 4781 }, 4782 { 4783 name: "HMULLU", 4784 argLen: 2, 4785 clobberFlags: true, 4786 asm: x86.AMULL, 4787 reg: regInfo{ 4788 inputs: []inputInfo{ 4789 {0, 1}, // AX 4790 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4791 }, 4792 clobbers: 1, // AX 4793 outputs: []outputInfo{ 4794 {0, 4}, // DX 4795 }, 4796 }, 4797 }, 4798 { 4799 name: "HMULWU", 4800 argLen: 2, 4801 clobberFlags: true, 4802 asm: x86.AMULW, 4803 reg: regInfo{ 4804 inputs: []inputInfo{ 4805 {0, 1}, // AX 4806 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4807 }, 4808 clobbers: 1, // AX 4809 outputs: []outputInfo{ 4810 {0, 4}, // DX 4811 }, 4812 }, 4813 }, 4814 { 4815 name: "HMULBU", 4816 argLen: 2, 4817 clobberFlags: true, 4818 asm: x86.AMULB, 4819 reg: regInfo{ 4820 inputs: []inputInfo{ 4821 {0, 1}, // AX 4822 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4823 }, 4824 clobbers: 1, // AX 4825 outputs: []outputInfo{ 4826 {0, 4}, // DX 4827 }, 4828 }, 4829 }, 4830 { 4831 name: "AVGQU", 4832 argLen: 2, 4833 commutative: true, 4834 resultInArg0: true, 4835 clobberFlags: true, 4836 reg: regInfo{ 4837 inputs: []inputInfo{ 4838 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4839 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4840 }, 4841 outputs: []outputInfo{ 4842 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4843 }, 4844 }, 4845 }, 4846 { 4847 name: "DIVQ", 4848 argLen: 2, 4849 clobberFlags: true, 4850 asm: x86.AIDIVQ, 4851 reg: regInfo{ 4852 inputs: []inputInfo{ 4853 {0, 1}, // AX 4854 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4855 }, 4856 outputs: []outputInfo{ 4857 {0, 1}, // AX 4858 {1, 4}, // DX 4859 }, 4860 }, 4861 }, 4862 { 4863 name: "DIVL", 4864 argLen: 2, 4865 clobberFlags: true, 4866 asm: x86.AIDIVL, 4867 reg: regInfo{ 4868 inputs: []inputInfo{ 4869 {0, 1}, // AX 4870 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4871 }, 4872 outputs: []outputInfo{ 4873 {0, 1}, // AX 4874 {1, 4}, // DX 4875 }, 4876 }, 4877 }, 4878 { 4879 name: "DIVW", 4880 argLen: 2, 4881 clobberFlags: true, 4882 asm: x86.AIDIVW, 4883 reg: regInfo{ 4884 inputs: []inputInfo{ 4885 {0, 1}, // AX 4886 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4887 }, 4888 outputs: []outputInfo{ 4889 {0, 1}, // AX 4890 {1, 4}, // DX 4891 }, 4892 }, 4893 }, 4894 { 4895 name: "DIVQU", 4896 argLen: 2, 4897 clobberFlags: true, 4898 asm: x86.ADIVQ, 4899 reg: regInfo{ 4900 inputs: []inputInfo{ 4901 {0, 1}, // AX 4902 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4903 }, 4904 outputs: []outputInfo{ 4905 {0, 1}, // AX 4906 {1, 4}, // DX 4907 }, 4908 }, 4909 }, 4910 { 4911 name: "DIVLU", 4912 argLen: 2, 4913 clobberFlags: true, 4914 asm: x86.ADIVL, 4915 reg: regInfo{ 4916 inputs: []inputInfo{ 4917 {0, 1}, // AX 4918 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4919 }, 4920 outputs: []outputInfo{ 4921 {0, 1}, // AX 4922 {1, 4}, // DX 4923 }, 4924 }, 4925 }, 4926 { 4927 name: "DIVWU", 4928 argLen: 2, 4929 clobberFlags: true, 4930 asm: x86.ADIVW, 4931 reg: regInfo{ 4932 inputs: []inputInfo{ 4933 {0, 1}, // AX 4934 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4935 }, 4936 outputs: []outputInfo{ 4937 {0, 1}, // AX 4938 {1, 4}, // DX 4939 }, 4940 }, 4941 }, 4942 { 4943 name: "MULQU2", 4944 argLen: 2, 4945 clobberFlags: true, 4946 asm: x86.AMULQ, 4947 reg: regInfo{ 4948 inputs: []inputInfo{ 4949 {0, 1}, // AX 4950 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4951 }, 4952 outputs: []outputInfo{ 4953 {0, 4}, // DX 4954 {1, 1}, // AX 4955 }, 4956 }, 4957 }, 4958 { 4959 name: "DIVQU2", 4960 argLen: 3, 4961 clobberFlags: true, 4962 asm: x86.ADIVQ, 4963 reg: regInfo{ 4964 inputs: []inputInfo{ 4965 {0, 4}, // DX 4966 {1, 1}, // AX 4967 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4968 }, 4969 outputs: []outputInfo{ 4970 {0, 1}, // AX 4971 {1, 4}, // DX 4972 }, 4973 }, 4974 }, 4975 { 4976 name: "ANDQ", 4977 argLen: 2, 4978 commutative: true, 4979 resultInArg0: true, 4980 clobberFlags: true, 4981 asm: x86.AANDQ, 4982 reg: regInfo{ 4983 inputs: []inputInfo{ 4984 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4985 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4986 }, 4987 outputs: []outputInfo{ 4988 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4989 }, 4990 }, 4991 }, 4992 { 4993 name: "ANDL", 4994 argLen: 2, 4995 commutative: true, 4996 resultInArg0: true, 4997 clobberFlags: true, 4998 asm: x86.AANDL, 4999 reg: regInfo{ 5000 inputs: []inputInfo{ 5001 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5002 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5003 }, 5004 outputs: []outputInfo{ 5005 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5006 }, 5007 }, 5008 }, 5009 { 5010 name: "ANDQconst", 5011 auxType: auxInt64, 5012 argLen: 1, 5013 resultInArg0: true, 5014 clobberFlags: true, 5015 asm: x86.AANDQ, 5016 reg: regInfo{ 5017 inputs: []inputInfo{ 5018 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5019 }, 5020 outputs: []outputInfo{ 5021 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5022 }, 5023 }, 5024 }, 5025 { 5026 name: "ANDLconst", 5027 auxType: auxInt32, 5028 argLen: 1, 5029 resultInArg0: true, 5030 clobberFlags: true, 5031 asm: x86.AANDL, 5032 reg: regInfo{ 5033 inputs: []inputInfo{ 5034 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5035 }, 5036 outputs: []outputInfo{ 5037 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5038 }, 5039 }, 5040 }, 5041 { 5042 name: "ORQ", 5043 argLen: 2, 5044 commutative: true, 5045 resultInArg0: true, 5046 clobberFlags: true, 5047 asm: x86.AORQ, 5048 reg: regInfo{ 5049 inputs: []inputInfo{ 5050 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5051 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5052 }, 5053 outputs: []outputInfo{ 5054 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5055 }, 5056 }, 5057 }, 5058 { 5059 name: "ORL", 5060 argLen: 2, 5061 commutative: true, 5062 resultInArg0: true, 5063 clobberFlags: true, 5064 asm: x86.AORL, 5065 reg: regInfo{ 5066 inputs: []inputInfo{ 5067 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5068 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5069 }, 5070 outputs: []outputInfo{ 5071 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5072 }, 5073 }, 5074 }, 5075 { 5076 name: "ORQconst", 5077 auxType: auxInt64, 5078 argLen: 1, 5079 resultInArg0: true, 5080 clobberFlags: true, 5081 asm: x86.AORQ, 5082 reg: regInfo{ 5083 inputs: []inputInfo{ 5084 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5085 }, 5086 outputs: []outputInfo{ 5087 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5088 }, 5089 }, 5090 }, 5091 { 5092 name: "ORLconst", 5093 auxType: auxInt32, 5094 argLen: 1, 5095 resultInArg0: true, 5096 clobberFlags: true, 5097 asm: x86.AORL, 5098 reg: regInfo{ 5099 inputs: []inputInfo{ 5100 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5101 }, 5102 outputs: []outputInfo{ 5103 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5104 }, 5105 }, 5106 }, 5107 { 5108 name: "XORQ", 5109 argLen: 2, 5110 commutative: true, 5111 resultInArg0: true, 5112 clobberFlags: true, 5113 asm: x86.AXORQ, 5114 reg: regInfo{ 5115 inputs: []inputInfo{ 5116 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5117 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5118 }, 5119 outputs: []outputInfo{ 5120 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5121 }, 5122 }, 5123 }, 5124 { 5125 name: "XORL", 5126 argLen: 2, 5127 commutative: true, 5128 resultInArg0: true, 5129 clobberFlags: true, 5130 asm: x86.AXORL, 5131 reg: regInfo{ 5132 inputs: []inputInfo{ 5133 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5134 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5135 }, 5136 outputs: []outputInfo{ 5137 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5138 }, 5139 }, 5140 }, 5141 { 5142 name: "XORQconst", 5143 auxType: auxInt64, 5144 argLen: 1, 5145 resultInArg0: true, 5146 clobberFlags: true, 5147 asm: x86.AXORQ, 5148 reg: regInfo{ 5149 inputs: []inputInfo{ 5150 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5151 }, 5152 outputs: []outputInfo{ 5153 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5154 }, 5155 }, 5156 }, 5157 { 5158 name: "XORLconst", 5159 auxType: auxInt32, 5160 argLen: 1, 5161 resultInArg0: true, 5162 clobberFlags: true, 5163 asm: x86.AXORL, 5164 reg: regInfo{ 5165 inputs: []inputInfo{ 5166 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5167 }, 5168 outputs: []outputInfo{ 5169 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5170 }, 5171 }, 5172 }, 5173 { 5174 name: "CMPQ", 5175 argLen: 2, 5176 asm: x86.ACMPQ, 5177 reg: regInfo{ 5178 inputs: []inputInfo{ 5179 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5180 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5181 }, 5182 }, 5183 }, 5184 { 5185 name: "CMPL", 5186 argLen: 2, 5187 asm: x86.ACMPL, 5188 reg: regInfo{ 5189 inputs: []inputInfo{ 5190 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5191 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5192 }, 5193 }, 5194 }, 5195 { 5196 name: "CMPW", 5197 argLen: 2, 5198 asm: x86.ACMPW, 5199 reg: regInfo{ 5200 inputs: []inputInfo{ 5201 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5202 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5203 }, 5204 }, 5205 }, 5206 { 5207 name: "CMPB", 5208 argLen: 2, 5209 asm: x86.ACMPB, 5210 reg: regInfo{ 5211 inputs: []inputInfo{ 5212 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5213 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5214 }, 5215 }, 5216 }, 5217 { 5218 name: "CMPQconst", 5219 auxType: auxInt64, 5220 argLen: 1, 5221 asm: x86.ACMPQ, 5222 reg: regInfo{ 5223 inputs: []inputInfo{ 5224 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5225 }, 5226 }, 5227 }, 5228 { 5229 name: "CMPLconst", 5230 auxType: auxInt32, 5231 argLen: 1, 5232 asm: x86.ACMPL, 5233 reg: regInfo{ 5234 inputs: []inputInfo{ 5235 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5236 }, 5237 }, 5238 }, 5239 { 5240 name: "CMPWconst", 5241 auxType: auxInt16, 5242 argLen: 1, 5243 asm: x86.ACMPW, 5244 reg: regInfo{ 5245 inputs: []inputInfo{ 5246 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5247 }, 5248 }, 5249 }, 5250 { 5251 name: "CMPBconst", 5252 auxType: auxInt8, 5253 argLen: 1, 5254 asm: x86.ACMPB, 5255 reg: regInfo{ 5256 inputs: []inputInfo{ 5257 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5258 }, 5259 }, 5260 }, 5261 { 5262 name: "UCOMISS", 5263 argLen: 2, 5264 asm: x86.AUCOMISS, 5265 reg: regInfo{ 5266 inputs: []inputInfo{ 5267 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5268 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5269 }, 5270 }, 5271 }, 5272 { 5273 name: "UCOMISD", 5274 argLen: 2, 5275 asm: x86.AUCOMISD, 5276 reg: regInfo{ 5277 inputs: []inputInfo{ 5278 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5279 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5280 }, 5281 }, 5282 }, 5283 { 5284 name: "TESTQ", 5285 argLen: 2, 5286 asm: x86.ATESTQ, 5287 reg: regInfo{ 5288 inputs: []inputInfo{ 5289 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5290 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5291 }, 5292 }, 5293 }, 5294 { 5295 name: "TESTL", 5296 argLen: 2, 5297 asm: x86.ATESTL, 5298 reg: regInfo{ 5299 inputs: []inputInfo{ 5300 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5301 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5302 }, 5303 }, 5304 }, 5305 { 5306 name: "TESTW", 5307 argLen: 2, 5308 asm: x86.ATESTW, 5309 reg: regInfo{ 5310 inputs: []inputInfo{ 5311 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5312 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5313 }, 5314 }, 5315 }, 5316 { 5317 name: "TESTB", 5318 argLen: 2, 5319 asm: x86.ATESTB, 5320 reg: regInfo{ 5321 inputs: []inputInfo{ 5322 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5323 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5324 }, 5325 }, 5326 }, 5327 { 5328 name: "TESTQconst", 5329 auxType: auxInt64, 5330 argLen: 1, 5331 asm: x86.ATESTQ, 5332 reg: regInfo{ 5333 inputs: []inputInfo{ 5334 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5335 }, 5336 }, 5337 }, 5338 { 5339 name: "TESTLconst", 5340 auxType: auxInt32, 5341 argLen: 1, 5342 asm: x86.ATESTL, 5343 reg: regInfo{ 5344 inputs: []inputInfo{ 5345 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5346 }, 5347 }, 5348 }, 5349 { 5350 name: "TESTWconst", 5351 auxType: auxInt16, 5352 argLen: 1, 5353 asm: x86.ATESTW, 5354 reg: regInfo{ 5355 inputs: []inputInfo{ 5356 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5357 }, 5358 }, 5359 }, 5360 { 5361 name: "TESTBconst", 5362 auxType: auxInt8, 5363 argLen: 1, 5364 asm: x86.ATESTB, 5365 reg: regInfo{ 5366 inputs: []inputInfo{ 5367 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5368 }, 5369 }, 5370 }, 5371 { 5372 name: "SHLQ", 5373 argLen: 2, 5374 resultInArg0: true, 5375 clobberFlags: true, 5376 asm: x86.ASHLQ, 5377 reg: regInfo{ 5378 inputs: []inputInfo{ 5379 {1, 2}, // CX 5380 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5381 }, 5382 outputs: []outputInfo{ 5383 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5384 }, 5385 }, 5386 }, 5387 { 5388 name: "SHLL", 5389 argLen: 2, 5390 resultInArg0: true, 5391 clobberFlags: true, 5392 asm: x86.ASHLL, 5393 reg: regInfo{ 5394 inputs: []inputInfo{ 5395 {1, 2}, // CX 5396 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5397 }, 5398 outputs: []outputInfo{ 5399 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5400 }, 5401 }, 5402 }, 5403 { 5404 name: "SHLQconst", 5405 auxType: auxInt64, 5406 argLen: 1, 5407 resultInArg0: true, 5408 clobberFlags: true, 5409 asm: x86.ASHLQ, 5410 reg: regInfo{ 5411 inputs: []inputInfo{ 5412 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5413 }, 5414 outputs: []outputInfo{ 5415 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5416 }, 5417 }, 5418 }, 5419 { 5420 name: "SHLLconst", 5421 auxType: auxInt32, 5422 argLen: 1, 5423 resultInArg0: true, 5424 clobberFlags: true, 5425 asm: x86.ASHLL, 5426 reg: regInfo{ 5427 inputs: []inputInfo{ 5428 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5429 }, 5430 outputs: []outputInfo{ 5431 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5432 }, 5433 }, 5434 }, 5435 { 5436 name: "SHRQ", 5437 argLen: 2, 5438 resultInArg0: true, 5439 clobberFlags: true, 5440 asm: x86.ASHRQ, 5441 reg: regInfo{ 5442 inputs: []inputInfo{ 5443 {1, 2}, // CX 5444 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5445 }, 5446 outputs: []outputInfo{ 5447 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5448 }, 5449 }, 5450 }, 5451 { 5452 name: "SHRL", 5453 argLen: 2, 5454 resultInArg0: true, 5455 clobberFlags: true, 5456 asm: x86.ASHRL, 5457 reg: regInfo{ 5458 inputs: []inputInfo{ 5459 {1, 2}, // CX 5460 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5461 }, 5462 outputs: []outputInfo{ 5463 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5464 }, 5465 }, 5466 }, 5467 { 5468 name: "SHRW", 5469 argLen: 2, 5470 resultInArg0: true, 5471 clobberFlags: true, 5472 asm: x86.ASHRW, 5473 reg: regInfo{ 5474 inputs: []inputInfo{ 5475 {1, 2}, // CX 5476 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5477 }, 5478 outputs: []outputInfo{ 5479 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5480 }, 5481 }, 5482 }, 5483 { 5484 name: "SHRB", 5485 argLen: 2, 5486 resultInArg0: true, 5487 clobberFlags: true, 5488 asm: x86.ASHRB, 5489 reg: regInfo{ 5490 inputs: []inputInfo{ 5491 {1, 2}, // CX 5492 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5493 }, 5494 outputs: []outputInfo{ 5495 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5496 }, 5497 }, 5498 }, 5499 { 5500 name: "SHRQconst", 5501 auxType: auxInt64, 5502 argLen: 1, 5503 resultInArg0: true, 5504 clobberFlags: true, 5505 asm: x86.ASHRQ, 5506 reg: regInfo{ 5507 inputs: []inputInfo{ 5508 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5509 }, 5510 outputs: []outputInfo{ 5511 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5512 }, 5513 }, 5514 }, 5515 { 5516 name: "SHRLconst", 5517 auxType: auxInt32, 5518 argLen: 1, 5519 resultInArg0: true, 5520 clobberFlags: true, 5521 asm: x86.ASHRL, 5522 reg: regInfo{ 5523 inputs: []inputInfo{ 5524 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5525 }, 5526 outputs: []outputInfo{ 5527 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5528 }, 5529 }, 5530 }, 5531 { 5532 name: "SHRWconst", 5533 auxType: auxInt16, 5534 argLen: 1, 5535 resultInArg0: true, 5536 clobberFlags: true, 5537 asm: x86.ASHRW, 5538 reg: regInfo{ 5539 inputs: []inputInfo{ 5540 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5541 }, 5542 outputs: []outputInfo{ 5543 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5544 }, 5545 }, 5546 }, 5547 { 5548 name: "SHRBconst", 5549 auxType: auxInt8, 5550 argLen: 1, 5551 resultInArg0: true, 5552 clobberFlags: true, 5553 asm: x86.ASHRB, 5554 reg: regInfo{ 5555 inputs: []inputInfo{ 5556 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5557 }, 5558 outputs: []outputInfo{ 5559 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5560 }, 5561 }, 5562 }, 5563 { 5564 name: "SARQ", 5565 argLen: 2, 5566 resultInArg0: true, 5567 clobberFlags: true, 5568 asm: x86.ASARQ, 5569 reg: regInfo{ 5570 inputs: []inputInfo{ 5571 {1, 2}, // CX 5572 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5573 }, 5574 outputs: []outputInfo{ 5575 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5576 }, 5577 }, 5578 }, 5579 { 5580 name: "SARL", 5581 argLen: 2, 5582 resultInArg0: true, 5583 clobberFlags: true, 5584 asm: x86.ASARL, 5585 reg: regInfo{ 5586 inputs: []inputInfo{ 5587 {1, 2}, // CX 5588 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5589 }, 5590 outputs: []outputInfo{ 5591 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5592 }, 5593 }, 5594 }, 5595 { 5596 name: "SARW", 5597 argLen: 2, 5598 resultInArg0: true, 5599 clobberFlags: true, 5600 asm: x86.ASARW, 5601 reg: regInfo{ 5602 inputs: []inputInfo{ 5603 {1, 2}, // CX 5604 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5605 }, 5606 outputs: []outputInfo{ 5607 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5608 }, 5609 }, 5610 }, 5611 { 5612 name: "SARB", 5613 argLen: 2, 5614 resultInArg0: true, 5615 clobberFlags: true, 5616 asm: x86.ASARB, 5617 reg: regInfo{ 5618 inputs: []inputInfo{ 5619 {1, 2}, // CX 5620 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5621 }, 5622 outputs: []outputInfo{ 5623 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5624 }, 5625 }, 5626 }, 5627 { 5628 name: "SARQconst", 5629 auxType: auxInt64, 5630 argLen: 1, 5631 resultInArg0: true, 5632 clobberFlags: true, 5633 asm: x86.ASARQ, 5634 reg: regInfo{ 5635 inputs: []inputInfo{ 5636 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5637 }, 5638 outputs: []outputInfo{ 5639 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5640 }, 5641 }, 5642 }, 5643 { 5644 name: "SARLconst", 5645 auxType: auxInt32, 5646 argLen: 1, 5647 resultInArg0: true, 5648 clobberFlags: true, 5649 asm: x86.ASARL, 5650 reg: regInfo{ 5651 inputs: []inputInfo{ 5652 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5653 }, 5654 outputs: []outputInfo{ 5655 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5656 }, 5657 }, 5658 }, 5659 { 5660 name: "SARWconst", 5661 auxType: auxInt16, 5662 argLen: 1, 5663 resultInArg0: true, 5664 clobberFlags: true, 5665 asm: x86.ASARW, 5666 reg: regInfo{ 5667 inputs: []inputInfo{ 5668 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5669 }, 5670 outputs: []outputInfo{ 5671 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5672 }, 5673 }, 5674 }, 5675 { 5676 name: "SARBconst", 5677 auxType: auxInt8, 5678 argLen: 1, 5679 resultInArg0: true, 5680 clobberFlags: true, 5681 asm: x86.ASARB, 5682 reg: regInfo{ 5683 inputs: []inputInfo{ 5684 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5685 }, 5686 outputs: []outputInfo{ 5687 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5688 }, 5689 }, 5690 }, 5691 { 5692 name: "ROLQconst", 5693 auxType: auxInt64, 5694 argLen: 1, 5695 resultInArg0: true, 5696 clobberFlags: true, 5697 asm: x86.AROLQ, 5698 reg: regInfo{ 5699 inputs: []inputInfo{ 5700 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5701 }, 5702 outputs: []outputInfo{ 5703 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5704 }, 5705 }, 5706 }, 5707 { 5708 name: "ROLLconst", 5709 auxType: auxInt32, 5710 argLen: 1, 5711 resultInArg0: true, 5712 clobberFlags: true, 5713 asm: x86.AROLL, 5714 reg: regInfo{ 5715 inputs: []inputInfo{ 5716 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5717 }, 5718 outputs: []outputInfo{ 5719 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5720 }, 5721 }, 5722 }, 5723 { 5724 name: "ROLWconst", 5725 auxType: auxInt16, 5726 argLen: 1, 5727 resultInArg0: true, 5728 clobberFlags: true, 5729 asm: x86.AROLW, 5730 reg: regInfo{ 5731 inputs: []inputInfo{ 5732 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5733 }, 5734 outputs: []outputInfo{ 5735 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5736 }, 5737 }, 5738 }, 5739 { 5740 name: "ROLBconst", 5741 auxType: auxInt8, 5742 argLen: 1, 5743 resultInArg0: true, 5744 clobberFlags: true, 5745 asm: x86.AROLB, 5746 reg: regInfo{ 5747 inputs: []inputInfo{ 5748 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5749 }, 5750 outputs: []outputInfo{ 5751 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5752 }, 5753 }, 5754 }, 5755 { 5756 name: "NEGQ", 5757 argLen: 1, 5758 resultInArg0: true, 5759 clobberFlags: true, 5760 asm: x86.ANEGQ, 5761 reg: regInfo{ 5762 inputs: []inputInfo{ 5763 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5764 }, 5765 outputs: []outputInfo{ 5766 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5767 }, 5768 }, 5769 }, 5770 { 5771 name: "NEGL", 5772 argLen: 1, 5773 resultInArg0: true, 5774 clobberFlags: true, 5775 asm: x86.ANEGL, 5776 reg: regInfo{ 5777 inputs: []inputInfo{ 5778 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5779 }, 5780 outputs: []outputInfo{ 5781 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5782 }, 5783 }, 5784 }, 5785 { 5786 name: "NOTQ", 5787 argLen: 1, 5788 resultInArg0: true, 5789 clobberFlags: true, 5790 asm: x86.ANOTQ, 5791 reg: regInfo{ 5792 inputs: []inputInfo{ 5793 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5794 }, 5795 outputs: []outputInfo{ 5796 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5797 }, 5798 }, 5799 }, 5800 { 5801 name: "NOTL", 5802 argLen: 1, 5803 resultInArg0: true, 5804 clobberFlags: true, 5805 asm: x86.ANOTL, 5806 reg: regInfo{ 5807 inputs: []inputInfo{ 5808 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5809 }, 5810 outputs: []outputInfo{ 5811 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5812 }, 5813 }, 5814 }, 5815 { 5816 name: "BSFQ", 5817 argLen: 1, 5818 asm: x86.ABSFQ, 5819 reg: regInfo{ 5820 inputs: []inputInfo{ 5821 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5822 }, 5823 outputs: []outputInfo{ 5824 {1, 0}, 5825 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5826 }, 5827 }, 5828 }, 5829 { 5830 name: "BSFL", 5831 argLen: 1, 5832 asm: x86.ABSFL, 5833 reg: regInfo{ 5834 inputs: []inputInfo{ 5835 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5836 }, 5837 outputs: []outputInfo{ 5838 {1, 0}, 5839 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5840 }, 5841 }, 5842 }, 5843 { 5844 name: "CMOVQEQ", 5845 argLen: 3, 5846 resultInArg0: true, 5847 asm: x86.ACMOVQEQ, 5848 reg: regInfo{ 5849 inputs: []inputInfo{ 5850 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5851 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5852 }, 5853 outputs: []outputInfo{ 5854 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5855 }, 5856 }, 5857 }, 5858 { 5859 name: "CMOVLEQ", 5860 argLen: 3, 5861 resultInArg0: true, 5862 asm: x86.ACMOVLEQ, 5863 reg: regInfo{ 5864 inputs: []inputInfo{ 5865 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5866 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5867 }, 5868 outputs: []outputInfo{ 5869 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5870 }, 5871 }, 5872 }, 5873 { 5874 name: "BSWAPQ", 5875 argLen: 1, 5876 resultInArg0: true, 5877 clobberFlags: true, 5878 asm: x86.ABSWAPQ, 5879 reg: regInfo{ 5880 inputs: []inputInfo{ 5881 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5882 }, 5883 outputs: []outputInfo{ 5884 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5885 }, 5886 }, 5887 }, 5888 { 5889 name: "BSWAPL", 5890 argLen: 1, 5891 resultInArg0: true, 5892 clobberFlags: true, 5893 asm: x86.ABSWAPL, 5894 reg: regInfo{ 5895 inputs: []inputInfo{ 5896 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5897 }, 5898 outputs: []outputInfo{ 5899 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5900 }, 5901 }, 5902 }, 5903 { 5904 name: "SQRTSD", 5905 argLen: 1, 5906 asm: x86.ASQRTSD, 5907 reg: regInfo{ 5908 inputs: []inputInfo{ 5909 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5910 }, 5911 outputs: []outputInfo{ 5912 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5913 }, 5914 }, 5915 }, 5916 { 5917 name: "SBBQcarrymask", 5918 argLen: 1, 5919 asm: x86.ASBBQ, 5920 reg: regInfo{ 5921 outputs: []outputInfo{ 5922 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5923 }, 5924 }, 5925 }, 5926 { 5927 name: "SBBLcarrymask", 5928 argLen: 1, 5929 asm: x86.ASBBL, 5930 reg: regInfo{ 5931 outputs: []outputInfo{ 5932 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5933 }, 5934 }, 5935 }, 5936 { 5937 name: "SETEQ", 5938 argLen: 1, 5939 asm: x86.ASETEQ, 5940 reg: regInfo{ 5941 outputs: []outputInfo{ 5942 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5943 }, 5944 }, 5945 }, 5946 { 5947 name: "SETNE", 5948 argLen: 1, 5949 asm: x86.ASETNE, 5950 reg: regInfo{ 5951 outputs: []outputInfo{ 5952 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5953 }, 5954 }, 5955 }, 5956 { 5957 name: "SETL", 5958 argLen: 1, 5959 asm: x86.ASETLT, 5960 reg: regInfo{ 5961 outputs: []outputInfo{ 5962 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5963 }, 5964 }, 5965 }, 5966 { 5967 name: "SETLE", 5968 argLen: 1, 5969 asm: x86.ASETLE, 5970 reg: regInfo{ 5971 outputs: []outputInfo{ 5972 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5973 }, 5974 }, 5975 }, 5976 { 5977 name: "SETG", 5978 argLen: 1, 5979 asm: x86.ASETGT, 5980 reg: regInfo{ 5981 outputs: []outputInfo{ 5982 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5983 }, 5984 }, 5985 }, 5986 { 5987 name: "SETGE", 5988 argLen: 1, 5989 asm: x86.ASETGE, 5990 reg: regInfo{ 5991 outputs: []outputInfo{ 5992 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5993 }, 5994 }, 5995 }, 5996 { 5997 name: "SETB", 5998 argLen: 1, 5999 asm: x86.ASETCS, 6000 reg: regInfo{ 6001 outputs: []outputInfo{ 6002 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6003 }, 6004 }, 6005 }, 6006 { 6007 name: "SETBE", 6008 argLen: 1, 6009 asm: x86.ASETLS, 6010 reg: regInfo{ 6011 outputs: []outputInfo{ 6012 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6013 }, 6014 }, 6015 }, 6016 { 6017 name: "SETA", 6018 argLen: 1, 6019 asm: x86.ASETHI, 6020 reg: regInfo{ 6021 outputs: []outputInfo{ 6022 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6023 }, 6024 }, 6025 }, 6026 { 6027 name: "SETAE", 6028 argLen: 1, 6029 asm: x86.ASETCC, 6030 reg: regInfo{ 6031 outputs: []outputInfo{ 6032 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6033 }, 6034 }, 6035 }, 6036 { 6037 name: "SETEQF", 6038 argLen: 1, 6039 clobberFlags: true, 6040 asm: x86.ASETEQ, 6041 reg: regInfo{ 6042 clobbers: 1, // AX 6043 outputs: []outputInfo{ 6044 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6045 }, 6046 }, 6047 }, 6048 { 6049 name: "SETNEF", 6050 argLen: 1, 6051 clobberFlags: true, 6052 asm: x86.ASETNE, 6053 reg: regInfo{ 6054 clobbers: 1, // AX 6055 outputs: []outputInfo{ 6056 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6057 }, 6058 }, 6059 }, 6060 { 6061 name: "SETORD", 6062 argLen: 1, 6063 asm: x86.ASETPC, 6064 reg: regInfo{ 6065 outputs: []outputInfo{ 6066 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6067 }, 6068 }, 6069 }, 6070 { 6071 name: "SETNAN", 6072 argLen: 1, 6073 asm: x86.ASETPS, 6074 reg: regInfo{ 6075 outputs: []outputInfo{ 6076 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6077 }, 6078 }, 6079 }, 6080 { 6081 name: "SETGF", 6082 argLen: 1, 6083 asm: x86.ASETHI, 6084 reg: regInfo{ 6085 outputs: []outputInfo{ 6086 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6087 }, 6088 }, 6089 }, 6090 { 6091 name: "SETGEF", 6092 argLen: 1, 6093 asm: x86.ASETCC, 6094 reg: regInfo{ 6095 outputs: []outputInfo{ 6096 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6097 }, 6098 }, 6099 }, 6100 { 6101 name: "MOVBQSX", 6102 argLen: 1, 6103 asm: x86.AMOVBQSX, 6104 reg: regInfo{ 6105 inputs: []inputInfo{ 6106 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6107 }, 6108 outputs: []outputInfo{ 6109 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6110 }, 6111 }, 6112 }, 6113 { 6114 name: "MOVBQZX", 6115 argLen: 1, 6116 asm: x86.AMOVBLZX, 6117 reg: regInfo{ 6118 inputs: []inputInfo{ 6119 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6120 }, 6121 outputs: []outputInfo{ 6122 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6123 }, 6124 }, 6125 }, 6126 { 6127 name: "MOVWQSX", 6128 argLen: 1, 6129 asm: x86.AMOVWQSX, 6130 reg: regInfo{ 6131 inputs: []inputInfo{ 6132 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6133 }, 6134 outputs: []outputInfo{ 6135 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6136 }, 6137 }, 6138 }, 6139 { 6140 name: "MOVWQZX", 6141 argLen: 1, 6142 asm: x86.AMOVWLZX, 6143 reg: regInfo{ 6144 inputs: []inputInfo{ 6145 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6146 }, 6147 outputs: []outputInfo{ 6148 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6149 }, 6150 }, 6151 }, 6152 { 6153 name: "MOVLQSX", 6154 argLen: 1, 6155 asm: x86.AMOVLQSX, 6156 reg: regInfo{ 6157 inputs: []inputInfo{ 6158 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6159 }, 6160 outputs: []outputInfo{ 6161 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6162 }, 6163 }, 6164 }, 6165 { 6166 name: "MOVLQZX", 6167 argLen: 1, 6168 asm: x86.AMOVL, 6169 reg: regInfo{ 6170 inputs: []inputInfo{ 6171 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6172 }, 6173 outputs: []outputInfo{ 6174 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6175 }, 6176 }, 6177 }, 6178 { 6179 name: "MOVLconst", 6180 auxType: auxInt32, 6181 argLen: 0, 6182 rematerializeable: true, 6183 asm: x86.AMOVL, 6184 reg: regInfo{ 6185 outputs: []outputInfo{ 6186 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6187 }, 6188 }, 6189 }, 6190 { 6191 name: "MOVQconst", 6192 auxType: auxInt64, 6193 argLen: 0, 6194 rematerializeable: true, 6195 asm: x86.AMOVQ, 6196 reg: regInfo{ 6197 outputs: []outputInfo{ 6198 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6199 }, 6200 }, 6201 }, 6202 { 6203 name: "CVTTSD2SL", 6204 argLen: 1, 6205 asm: x86.ACVTTSD2SL, 6206 reg: regInfo{ 6207 inputs: []inputInfo{ 6208 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6209 }, 6210 outputs: []outputInfo{ 6211 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6212 }, 6213 }, 6214 }, 6215 { 6216 name: "CVTTSD2SQ", 6217 argLen: 1, 6218 asm: x86.ACVTTSD2SQ, 6219 reg: regInfo{ 6220 inputs: []inputInfo{ 6221 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6222 }, 6223 outputs: []outputInfo{ 6224 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6225 }, 6226 }, 6227 }, 6228 { 6229 name: "CVTTSS2SL", 6230 argLen: 1, 6231 asm: x86.ACVTTSS2SL, 6232 reg: regInfo{ 6233 inputs: []inputInfo{ 6234 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6235 }, 6236 outputs: []outputInfo{ 6237 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6238 }, 6239 }, 6240 }, 6241 { 6242 name: "CVTTSS2SQ", 6243 argLen: 1, 6244 asm: x86.ACVTTSS2SQ, 6245 reg: regInfo{ 6246 inputs: []inputInfo{ 6247 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6248 }, 6249 outputs: []outputInfo{ 6250 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6251 }, 6252 }, 6253 }, 6254 { 6255 name: "CVTSL2SS", 6256 argLen: 1, 6257 asm: x86.ACVTSL2SS, 6258 reg: regInfo{ 6259 inputs: []inputInfo{ 6260 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6261 }, 6262 outputs: []outputInfo{ 6263 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6264 }, 6265 }, 6266 }, 6267 { 6268 name: "CVTSL2SD", 6269 argLen: 1, 6270 asm: x86.ACVTSL2SD, 6271 reg: regInfo{ 6272 inputs: []inputInfo{ 6273 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6274 }, 6275 outputs: []outputInfo{ 6276 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6277 }, 6278 }, 6279 }, 6280 { 6281 name: "CVTSQ2SS", 6282 argLen: 1, 6283 asm: x86.ACVTSQ2SS, 6284 reg: regInfo{ 6285 inputs: []inputInfo{ 6286 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6287 }, 6288 outputs: []outputInfo{ 6289 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6290 }, 6291 }, 6292 }, 6293 { 6294 name: "CVTSQ2SD", 6295 argLen: 1, 6296 asm: x86.ACVTSQ2SD, 6297 reg: regInfo{ 6298 inputs: []inputInfo{ 6299 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6300 }, 6301 outputs: []outputInfo{ 6302 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6303 }, 6304 }, 6305 }, 6306 { 6307 name: "CVTSD2SS", 6308 argLen: 1, 6309 asm: x86.ACVTSD2SS, 6310 reg: regInfo{ 6311 inputs: []inputInfo{ 6312 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6313 }, 6314 outputs: []outputInfo{ 6315 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6316 }, 6317 }, 6318 }, 6319 { 6320 name: "CVTSS2SD", 6321 argLen: 1, 6322 asm: x86.ACVTSS2SD, 6323 reg: regInfo{ 6324 inputs: []inputInfo{ 6325 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6326 }, 6327 outputs: []outputInfo{ 6328 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6329 }, 6330 }, 6331 }, 6332 { 6333 name: "PXOR", 6334 argLen: 2, 6335 commutative: true, 6336 resultInArg0: true, 6337 asm: x86.APXOR, 6338 reg: regInfo{ 6339 inputs: []inputInfo{ 6340 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6341 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6342 }, 6343 outputs: []outputInfo{ 6344 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6345 }, 6346 }, 6347 }, 6348 { 6349 name: "LEAQ", 6350 auxType: auxSymOff, 6351 argLen: 1, 6352 rematerializeable: true, 6353 asm: x86.ALEAQ, 6354 reg: regInfo{ 6355 inputs: []inputInfo{ 6356 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6357 }, 6358 outputs: []outputInfo{ 6359 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6360 }, 6361 }, 6362 }, 6363 { 6364 name: "LEAQ1", 6365 auxType: auxSymOff, 6366 argLen: 2, 6367 reg: regInfo{ 6368 inputs: []inputInfo{ 6369 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6370 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6371 }, 6372 outputs: []outputInfo{ 6373 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6374 }, 6375 }, 6376 }, 6377 { 6378 name: "LEAQ2", 6379 auxType: auxSymOff, 6380 argLen: 2, 6381 reg: regInfo{ 6382 inputs: []inputInfo{ 6383 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6384 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6385 }, 6386 outputs: []outputInfo{ 6387 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6388 }, 6389 }, 6390 }, 6391 { 6392 name: "LEAQ4", 6393 auxType: auxSymOff, 6394 argLen: 2, 6395 reg: regInfo{ 6396 inputs: []inputInfo{ 6397 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6398 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6399 }, 6400 outputs: []outputInfo{ 6401 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6402 }, 6403 }, 6404 }, 6405 { 6406 name: "LEAQ8", 6407 auxType: auxSymOff, 6408 argLen: 2, 6409 reg: regInfo{ 6410 inputs: []inputInfo{ 6411 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6412 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6413 }, 6414 outputs: []outputInfo{ 6415 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6416 }, 6417 }, 6418 }, 6419 { 6420 name: "LEAL", 6421 auxType: auxSymOff, 6422 argLen: 1, 6423 rematerializeable: true, 6424 asm: x86.ALEAL, 6425 reg: regInfo{ 6426 inputs: []inputInfo{ 6427 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6428 }, 6429 outputs: []outputInfo{ 6430 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6431 }, 6432 }, 6433 }, 6434 { 6435 name: "MOVBload", 6436 auxType: auxSymOff, 6437 argLen: 2, 6438 faultOnNilArg0: true, 6439 asm: x86.AMOVBLZX, 6440 reg: regInfo{ 6441 inputs: []inputInfo{ 6442 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6443 }, 6444 outputs: []outputInfo{ 6445 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6446 }, 6447 }, 6448 }, 6449 { 6450 name: "MOVBQSXload", 6451 auxType: auxSymOff, 6452 argLen: 2, 6453 faultOnNilArg0: true, 6454 asm: x86.AMOVBQSX, 6455 reg: regInfo{ 6456 inputs: []inputInfo{ 6457 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6458 }, 6459 outputs: []outputInfo{ 6460 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6461 }, 6462 }, 6463 }, 6464 { 6465 name: "MOVWload", 6466 auxType: auxSymOff, 6467 argLen: 2, 6468 faultOnNilArg0: true, 6469 asm: x86.AMOVWLZX, 6470 reg: regInfo{ 6471 inputs: []inputInfo{ 6472 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6473 }, 6474 outputs: []outputInfo{ 6475 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6476 }, 6477 }, 6478 }, 6479 { 6480 name: "MOVWQSXload", 6481 auxType: auxSymOff, 6482 argLen: 2, 6483 faultOnNilArg0: true, 6484 asm: x86.AMOVWQSX, 6485 reg: regInfo{ 6486 inputs: []inputInfo{ 6487 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6488 }, 6489 outputs: []outputInfo{ 6490 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6491 }, 6492 }, 6493 }, 6494 { 6495 name: "MOVLload", 6496 auxType: auxSymOff, 6497 argLen: 2, 6498 faultOnNilArg0: true, 6499 asm: x86.AMOVL, 6500 reg: regInfo{ 6501 inputs: []inputInfo{ 6502 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6503 }, 6504 outputs: []outputInfo{ 6505 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6506 }, 6507 }, 6508 }, 6509 { 6510 name: "MOVLQSXload", 6511 auxType: auxSymOff, 6512 argLen: 2, 6513 faultOnNilArg0: true, 6514 asm: x86.AMOVLQSX, 6515 reg: regInfo{ 6516 inputs: []inputInfo{ 6517 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6518 }, 6519 outputs: []outputInfo{ 6520 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6521 }, 6522 }, 6523 }, 6524 { 6525 name: "MOVQload", 6526 auxType: auxSymOff, 6527 argLen: 2, 6528 faultOnNilArg0: true, 6529 asm: x86.AMOVQ, 6530 reg: regInfo{ 6531 inputs: []inputInfo{ 6532 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6533 }, 6534 outputs: []outputInfo{ 6535 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6536 }, 6537 }, 6538 }, 6539 { 6540 name: "MOVBstore", 6541 auxType: auxSymOff, 6542 argLen: 3, 6543 faultOnNilArg0: true, 6544 asm: x86.AMOVB, 6545 reg: regInfo{ 6546 inputs: []inputInfo{ 6547 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6548 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6549 }, 6550 }, 6551 }, 6552 { 6553 name: "MOVWstore", 6554 auxType: auxSymOff, 6555 argLen: 3, 6556 faultOnNilArg0: true, 6557 asm: x86.AMOVW, 6558 reg: regInfo{ 6559 inputs: []inputInfo{ 6560 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6561 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6562 }, 6563 }, 6564 }, 6565 { 6566 name: "MOVLstore", 6567 auxType: auxSymOff, 6568 argLen: 3, 6569 faultOnNilArg0: true, 6570 asm: x86.AMOVL, 6571 reg: regInfo{ 6572 inputs: []inputInfo{ 6573 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6574 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6575 }, 6576 }, 6577 }, 6578 { 6579 name: "MOVQstore", 6580 auxType: auxSymOff, 6581 argLen: 3, 6582 faultOnNilArg0: true, 6583 asm: x86.AMOVQ, 6584 reg: regInfo{ 6585 inputs: []inputInfo{ 6586 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6587 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6588 }, 6589 }, 6590 }, 6591 { 6592 name: "MOVOload", 6593 auxType: auxSymOff, 6594 argLen: 2, 6595 faultOnNilArg0: true, 6596 asm: x86.AMOVUPS, 6597 reg: regInfo{ 6598 inputs: []inputInfo{ 6599 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6600 }, 6601 outputs: []outputInfo{ 6602 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6603 }, 6604 }, 6605 }, 6606 { 6607 name: "MOVOstore", 6608 auxType: auxSymOff, 6609 argLen: 3, 6610 faultOnNilArg0: true, 6611 asm: x86.AMOVUPS, 6612 reg: regInfo{ 6613 inputs: []inputInfo{ 6614 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6615 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6616 }, 6617 }, 6618 }, 6619 { 6620 name: "MOVBloadidx1", 6621 auxType: auxSymOff, 6622 argLen: 3, 6623 asm: x86.AMOVBLZX, 6624 reg: regInfo{ 6625 inputs: []inputInfo{ 6626 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6627 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6628 }, 6629 outputs: []outputInfo{ 6630 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6631 }, 6632 }, 6633 }, 6634 { 6635 name: "MOVWloadidx1", 6636 auxType: auxSymOff, 6637 argLen: 3, 6638 asm: x86.AMOVWLZX, 6639 reg: regInfo{ 6640 inputs: []inputInfo{ 6641 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6642 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6643 }, 6644 outputs: []outputInfo{ 6645 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6646 }, 6647 }, 6648 }, 6649 { 6650 name: "MOVWloadidx2", 6651 auxType: auxSymOff, 6652 argLen: 3, 6653 asm: x86.AMOVWLZX, 6654 reg: regInfo{ 6655 inputs: []inputInfo{ 6656 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6657 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6658 }, 6659 outputs: []outputInfo{ 6660 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6661 }, 6662 }, 6663 }, 6664 { 6665 name: "MOVLloadidx1", 6666 auxType: auxSymOff, 6667 argLen: 3, 6668 asm: x86.AMOVL, 6669 reg: regInfo{ 6670 inputs: []inputInfo{ 6671 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6672 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6673 }, 6674 outputs: []outputInfo{ 6675 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6676 }, 6677 }, 6678 }, 6679 { 6680 name: "MOVLloadidx4", 6681 auxType: auxSymOff, 6682 argLen: 3, 6683 asm: x86.AMOVL, 6684 reg: regInfo{ 6685 inputs: []inputInfo{ 6686 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6687 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6688 }, 6689 outputs: []outputInfo{ 6690 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6691 }, 6692 }, 6693 }, 6694 { 6695 name: "MOVQloadidx1", 6696 auxType: auxSymOff, 6697 argLen: 3, 6698 asm: x86.AMOVQ, 6699 reg: regInfo{ 6700 inputs: []inputInfo{ 6701 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6702 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6703 }, 6704 outputs: []outputInfo{ 6705 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6706 }, 6707 }, 6708 }, 6709 { 6710 name: "MOVQloadidx8", 6711 auxType: auxSymOff, 6712 argLen: 3, 6713 asm: x86.AMOVQ, 6714 reg: regInfo{ 6715 inputs: []inputInfo{ 6716 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6717 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6718 }, 6719 outputs: []outputInfo{ 6720 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6721 }, 6722 }, 6723 }, 6724 { 6725 name: "MOVBstoreidx1", 6726 auxType: auxSymOff, 6727 argLen: 4, 6728 asm: x86.AMOVB, 6729 reg: regInfo{ 6730 inputs: []inputInfo{ 6731 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6732 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6733 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6734 }, 6735 }, 6736 }, 6737 { 6738 name: "MOVWstoreidx1", 6739 auxType: auxSymOff, 6740 argLen: 4, 6741 asm: x86.AMOVW, 6742 reg: regInfo{ 6743 inputs: []inputInfo{ 6744 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6745 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6746 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6747 }, 6748 }, 6749 }, 6750 { 6751 name: "MOVWstoreidx2", 6752 auxType: auxSymOff, 6753 argLen: 4, 6754 asm: x86.AMOVW, 6755 reg: regInfo{ 6756 inputs: []inputInfo{ 6757 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6758 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6759 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6760 }, 6761 }, 6762 }, 6763 { 6764 name: "MOVLstoreidx1", 6765 auxType: auxSymOff, 6766 argLen: 4, 6767 asm: x86.AMOVL, 6768 reg: regInfo{ 6769 inputs: []inputInfo{ 6770 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6771 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6772 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6773 }, 6774 }, 6775 }, 6776 { 6777 name: "MOVLstoreidx4", 6778 auxType: auxSymOff, 6779 argLen: 4, 6780 asm: x86.AMOVL, 6781 reg: regInfo{ 6782 inputs: []inputInfo{ 6783 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6784 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6785 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6786 }, 6787 }, 6788 }, 6789 { 6790 name: "MOVQstoreidx1", 6791 auxType: auxSymOff, 6792 argLen: 4, 6793 asm: x86.AMOVQ, 6794 reg: regInfo{ 6795 inputs: []inputInfo{ 6796 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6797 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6798 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6799 }, 6800 }, 6801 }, 6802 { 6803 name: "MOVQstoreidx8", 6804 auxType: auxSymOff, 6805 argLen: 4, 6806 asm: x86.AMOVQ, 6807 reg: regInfo{ 6808 inputs: []inputInfo{ 6809 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6810 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6811 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6812 }, 6813 }, 6814 }, 6815 { 6816 name: "MOVBstoreconst", 6817 auxType: auxSymValAndOff, 6818 argLen: 2, 6819 faultOnNilArg0: true, 6820 asm: x86.AMOVB, 6821 reg: regInfo{ 6822 inputs: []inputInfo{ 6823 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6824 }, 6825 }, 6826 }, 6827 { 6828 name: "MOVWstoreconst", 6829 auxType: auxSymValAndOff, 6830 argLen: 2, 6831 faultOnNilArg0: true, 6832 asm: x86.AMOVW, 6833 reg: regInfo{ 6834 inputs: []inputInfo{ 6835 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6836 }, 6837 }, 6838 }, 6839 { 6840 name: "MOVLstoreconst", 6841 auxType: auxSymValAndOff, 6842 argLen: 2, 6843 faultOnNilArg0: true, 6844 asm: x86.AMOVL, 6845 reg: regInfo{ 6846 inputs: []inputInfo{ 6847 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6848 }, 6849 }, 6850 }, 6851 { 6852 name: "MOVQstoreconst", 6853 auxType: auxSymValAndOff, 6854 argLen: 2, 6855 faultOnNilArg0: true, 6856 asm: x86.AMOVQ, 6857 reg: regInfo{ 6858 inputs: []inputInfo{ 6859 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6860 }, 6861 }, 6862 }, 6863 { 6864 name: "MOVBstoreconstidx1", 6865 auxType: auxSymValAndOff, 6866 argLen: 3, 6867 asm: x86.AMOVB, 6868 reg: regInfo{ 6869 inputs: []inputInfo{ 6870 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6871 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6872 }, 6873 }, 6874 }, 6875 { 6876 name: "MOVWstoreconstidx1", 6877 auxType: auxSymValAndOff, 6878 argLen: 3, 6879 asm: x86.AMOVW, 6880 reg: regInfo{ 6881 inputs: []inputInfo{ 6882 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6883 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6884 }, 6885 }, 6886 }, 6887 { 6888 name: "MOVWstoreconstidx2", 6889 auxType: auxSymValAndOff, 6890 argLen: 3, 6891 asm: x86.AMOVW, 6892 reg: regInfo{ 6893 inputs: []inputInfo{ 6894 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6895 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6896 }, 6897 }, 6898 }, 6899 { 6900 name: "MOVLstoreconstidx1", 6901 auxType: auxSymValAndOff, 6902 argLen: 3, 6903 asm: x86.AMOVL, 6904 reg: regInfo{ 6905 inputs: []inputInfo{ 6906 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6907 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6908 }, 6909 }, 6910 }, 6911 { 6912 name: "MOVLstoreconstidx4", 6913 auxType: auxSymValAndOff, 6914 argLen: 3, 6915 asm: x86.AMOVL, 6916 reg: regInfo{ 6917 inputs: []inputInfo{ 6918 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6919 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6920 }, 6921 }, 6922 }, 6923 { 6924 name: "MOVQstoreconstidx1", 6925 auxType: auxSymValAndOff, 6926 argLen: 3, 6927 asm: x86.AMOVQ, 6928 reg: regInfo{ 6929 inputs: []inputInfo{ 6930 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6931 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6932 }, 6933 }, 6934 }, 6935 { 6936 name: "MOVQstoreconstidx8", 6937 auxType: auxSymValAndOff, 6938 argLen: 3, 6939 asm: x86.AMOVQ, 6940 reg: regInfo{ 6941 inputs: []inputInfo{ 6942 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6943 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6944 }, 6945 }, 6946 }, 6947 { 6948 name: "DUFFZERO", 6949 auxType: auxInt64, 6950 argLen: 3, 6951 clobberFlags: true, 6952 reg: regInfo{ 6953 inputs: []inputInfo{ 6954 {0, 128}, // DI 6955 {1, 65536}, // X0 6956 }, 6957 clobbers: 128, // DI 6958 }, 6959 }, 6960 { 6961 name: "MOVOconst", 6962 auxType: auxInt128, 6963 argLen: 0, 6964 rematerializeable: true, 6965 reg: regInfo{ 6966 outputs: []outputInfo{ 6967 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6968 }, 6969 }, 6970 }, 6971 { 6972 name: "REPSTOSQ", 6973 argLen: 4, 6974 reg: regInfo{ 6975 inputs: []inputInfo{ 6976 {0, 128}, // DI 6977 {1, 2}, // CX 6978 {2, 1}, // AX 6979 }, 6980 clobbers: 130, // CX DI 6981 }, 6982 }, 6983 { 6984 name: "CALLstatic", 6985 auxType: auxSymOff, 6986 argLen: 1, 6987 clobberFlags: true, 6988 call: true, 6989 reg: regInfo{ 6990 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6991 }, 6992 }, 6993 { 6994 name: "CALLclosure", 6995 auxType: auxInt64, 6996 argLen: 3, 6997 clobberFlags: true, 6998 call: true, 6999 reg: regInfo{ 7000 inputs: []inputInfo{ 7001 {1, 4}, // DX 7002 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7003 }, 7004 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7005 }, 7006 }, 7007 { 7008 name: "CALLdefer", 7009 auxType: auxInt64, 7010 argLen: 1, 7011 clobberFlags: true, 7012 call: true, 7013 reg: regInfo{ 7014 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7015 }, 7016 }, 7017 { 7018 name: "CALLgo", 7019 auxType: auxInt64, 7020 argLen: 1, 7021 clobberFlags: true, 7022 call: true, 7023 reg: regInfo{ 7024 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7025 }, 7026 }, 7027 { 7028 name: "CALLinter", 7029 auxType: auxInt64, 7030 argLen: 2, 7031 clobberFlags: true, 7032 call: true, 7033 reg: regInfo{ 7034 inputs: []inputInfo{ 7035 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7036 }, 7037 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7038 }, 7039 }, 7040 { 7041 name: "DUFFCOPY", 7042 auxType: auxInt64, 7043 argLen: 3, 7044 clobberFlags: true, 7045 reg: regInfo{ 7046 inputs: []inputInfo{ 7047 {0, 128}, // DI 7048 {1, 64}, // SI 7049 }, 7050 clobbers: 65728, // SI DI X0 7051 }, 7052 }, 7053 { 7054 name: "REPMOVSQ", 7055 argLen: 4, 7056 reg: regInfo{ 7057 inputs: []inputInfo{ 7058 {0, 128}, // DI 7059 {1, 64}, // SI 7060 {2, 2}, // CX 7061 }, 7062 clobbers: 194, // CX SI DI 7063 }, 7064 }, 7065 { 7066 name: "InvertFlags", 7067 argLen: 1, 7068 reg: regInfo{}, 7069 }, 7070 { 7071 name: "LoweredGetG", 7072 argLen: 1, 7073 reg: regInfo{ 7074 outputs: []outputInfo{ 7075 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7076 }, 7077 }, 7078 }, 7079 { 7080 name: "LoweredGetClosurePtr", 7081 argLen: 0, 7082 reg: regInfo{ 7083 outputs: []outputInfo{ 7084 {0, 4}, // DX 7085 }, 7086 }, 7087 }, 7088 { 7089 name: "LoweredNilCheck", 7090 argLen: 2, 7091 clobberFlags: true, 7092 nilCheck: true, 7093 faultOnNilArg0: true, 7094 reg: regInfo{ 7095 inputs: []inputInfo{ 7096 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7097 }, 7098 }, 7099 }, 7100 { 7101 name: "MOVQconvert", 7102 argLen: 2, 7103 asm: x86.AMOVQ, 7104 reg: regInfo{ 7105 inputs: []inputInfo{ 7106 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7107 }, 7108 outputs: []outputInfo{ 7109 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7110 }, 7111 }, 7112 }, 7113 { 7114 name: "MOVLconvert", 7115 argLen: 2, 7116 asm: x86.AMOVL, 7117 reg: regInfo{ 7118 inputs: []inputInfo{ 7119 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7120 }, 7121 outputs: []outputInfo{ 7122 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7123 }, 7124 }, 7125 }, 7126 { 7127 name: "FlagEQ", 7128 argLen: 0, 7129 reg: regInfo{}, 7130 }, 7131 { 7132 name: "FlagLT_ULT", 7133 argLen: 0, 7134 reg: regInfo{}, 7135 }, 7136 { 7137 name: "FlagLT_UGT", 7138 argLen: 0, 7139 reg: regInfo{}, 7140 }, 7141 { 7142 name: "FlagGT_UGT", 7143 argLen: 0, 7144 reg: regInfo{}, 7145 }, 7146 { 7147 name: "FlagGT_ULT", 7148 argLen: 0, 7149 reg: regInfo{}, 7150 }, 7151 { 7152 name: "MOVLatomicload", 7153 auxType: auxSymOff, 7154 argLen: 2, 7155 faultOnNilArg0: true, 7156 asm: x86.AMOVL, 7157 reg: regInfo{ 7158 inputs: []inputInfo{ 7159 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7160 }, 7161 outputs: []outputInfo{ 7162 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7163 }, 7164 }, 7165 }, 7166 { 7167 name: "MOVQatomicload", 7168 auxType: auxSymOff, 7169 argLen: 2, 7170 faultOnNilArg0: true, 7171 asm: x86.AMOVQ, 7172 reg: regInfo{ 7173 inputs: []inputInfo{ 7174 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7175 }, 7176 outputs: []outputInfo{ 7177 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7178 }, 7179 }, 7180 }, 7181 { 7182 name: "XCHGL", 7183 auxType: auxSymOff, 7184 argLen: 3, 7185 resultInArg0: true, 7186 faultOnNilArg1: true, 7187 asm: x86.AXCHGL, 7188 reg: regInfo{ 7189 inputs: []inputInfo{ 7190 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7191 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7192 }, 7193 outputs: []outputInfo{ 7194 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7195 }, 7196 }, 7197 }, 7198 { 7199 name: "XCHGQ", 7200 auxType: auxSymOff, 7201 argLen: 3, 7202 resultInArg0: true, 7203 faultOnNilArg1: true, 7204 asm: x86.AXCHGQ, 7205 reg: regInfo{ 7206 inputs: []inputInfo{ 7207 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7208 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7209 }, 7210 outputs: []outputInfo{ 7211 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7212 }, 7213 }, 7214 }, 7215 { 7216 name: "XADDLlock", 7217 auxType: auxSymOff, 7218 argLen: 3, 7219 resultInArg0: true, 7220 clobberFlags: true, 7221 faultOnNilArg1: true, 7222 asm: x86.AXADDL, 7223 reg: regInfo{ 7224 inputs: []inputInfo{ 7225 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7226 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7227 }, 7228 outputs: []outputInfo{ 7229 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7230 }, 7231 }, 7232 }, 7233 { 7234 name: "XADDQlock", 7235 auxType: auxSymOff, 7236 argLen: 3, 7237 resultInArg0: true, 7238 clobberFlags: true, 7239 faultOnNilArg1: true, 7240 asm: x86.AXADDQ, 7241 reg: regInfo{ 7242 inputs: []inputInfo{ 7243 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7244 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7245 }, 7246 outputs: []outputInfo{ 7247 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7248 }, 7249 }, 7250 }, 7251 { 7252 name: "AddTupleFirst32", 7253 argLen: 2, 7254 reg: regInfo{}, 7255 }, 7256 { 7257 name: "AddTupleFirst64", 7258 argLen: 2, 7259 reg: regInfo{}, 7260 }, 7261 { 7262 name: "CMPXCHGLlock", 7263 auxType: auxSymOff, 7264 argLen: 4, 7265 clobberFlags: true, 7266 faultOnNilArg0: true, 7267 asm: x86.ACMPXCHGL, 7268 reg: regInfo{ 7269 inputs: []inputInfo{ 7270 {1, 1}, // AX 7271 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7272 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7273 }, 7274 clobbers: 1, // AX 7275 outputs: []outputInfo{ 7276 {1, 0}, 7277 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7278 }, 7279 }, 7280 }, 7281 { 7282 name: "CMPXCHGQlock", 7283 auxType: auxSymOff, 7284 argLen: 4, 7285 clobberFlags: true, 7286 faultOnNilArg0: true, 7287 asm: x86.ACMPXCHGQ, 7288 reg: regInfo{ 7289 inputs: []inputInfo{ 7290 {1, 1}, // AX 7291 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7292 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7293 }, 7294 clobbers: 1, // AX 7295 outputs: []outputInfo{ 7296 {1, 0}, 7297 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7298 }, 7299 }, 7300 }, 7301 { 7302 name: "ANDBlock", 7303 auxType: auxSymOff, 7304 argLen: 3, 7305 clobberFlags: true, 7306 faultOnNilArg0: true, 7307 asm: x86.AANDB, 7308 reg: regInfo{ 7309 inputs: []inputInfo{ 7310 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7311 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7312 }, 7313 }, 7314 }, 7315 { 7316 name: "ORBlock", 7317 auxType: auxSymOff, 7318 argLen: 3, 7319 clobberFlags: true, 7320 faultOnNilArg0: true, 7321 asm: x86.AORB, 7322 reg: regInfo{ 7323 inputs: []inputInfo{ 7324 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7325 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7326 }, 7327 }, 7328 }, 7329 7330 { 7331 name: "ADD", 7332 argLen: 2, 7333 commutative: true, 7334 asm: arm.AADD, 7335 reg: regInfo{ 7336 inputs: []inputInfo{ 7337 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7338 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7339 }, 7340 outputs: []outputInfo{ 7341 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7342 }, 7343 }, 7344 }, 7345 { 7346 name: "ADDconst", 7347 auxType: auxInt32, 7348 argLen: 1, 7349 asm: arm.AADD, 7350 reg: regInfo{ 7351 inputs: []inputInfo{ 7352 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 7353 }, 7354 outputs: []outputInfo{ 7355 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7356 }, 7357 }, 7358 }, 7359 { 7360 name: "SUB", 7361 argLen: 2, 7362 asm: arm.ASUB, 7363 reg: regInfo{ 7364 inputs: []inputInfo{ 7365 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7366 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7367 }, 7368 outputs: []outputInfo{ 7369 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7370 }, 7371 }, 7372 }, 7373 { 7374 name: "SUBconst", 7375 auxType: auxInt32, 7376 argLen: 1, 7377 asm: arm.ASUB, 7378 reg: regInfo{ 7379 inputs: []inputInfo{ 7380 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7381 }, 7382 outputs: []outputInfo{ 7383 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7384 }, 7385 }, 7386 }, 7387 { 7388 name: "RSB", 7389 argLen: 2, 7390 asm: arm.ARSB, 7391 reg: regInfo{ 7392 inputs: []inputInfo{ 7393 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7394 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7395 }, 7396 outputs: []outputInfo{ 7397 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7398 }, 7399 }, 7400 }, 7401 { 7402 name: "RSBconst", 7403 auxType: auxInt32, 7404 argLen: 1, 7405 asm: arm.ARSB, 7406 reg: regInfo{ 7407 inputs: []inputInfo{ 7408 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7409 }, 7410 outputs: []outputInfo{ 7411 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7412 }, 7413 }, 7414 }, 7415 { 7416 name: "MUL", 7417 argLen: 2, 7418 commutative: true, 7419 asm: arm.AMUL, 7420 reg: regInfo{ 7421 inputs: []inputInfo{ 7422 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7423 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7424 }, 7425 outputs: []outputInfo{ 7426 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7427 }, 7428 }, 7429 }, 7430 { 7431 name: "HMUL", 7432 argLen: 2, 7433 commutative: true, 7434 asm: arm.AMULL, 7435 reg: regInfo{ 7436 inputs: []inputInfo{ 7437 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7438 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7439 }, 7440 outputs: []outputInfo{ 7441 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7442 }, 7443 }, 7444 }, 7445 { 7446 name: "HMULU", 7447 argLen: 2, 7448 commutative: true, 7449 asm: arm.AMULLU, 7450 reg: regInfo{ 7451 inputs: []inputInfo{ 7452 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7453 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7454 }, 7455 outputs: []outputInfo{ 7456 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7457 }, 7458 }, 7459 }, 7460 { 7461 name: "UDIVrtcall", 7462 argLen: 2, 7463 clobberFlags: true, 7464 reg: regInfo{ 7465 inputs: []inputInfo{ 7466 {0, 2}, // R1 7467 {1, 1}, // R0 7468 }, 7469 clobbers: 16396, // R2 R3 R14 7470 outputs: []outputInfo{ 7471 {0, 1}, // R0 7472 {1, 2}, // R1 7473 }, 7474 }, 7475 }, 7476 { 7477 name: "ADDS", 7478 argLen: 2, 7479 commutative: true, 7480 asm: arm.AADD, 7481 reg: regInfo{ 7482 inputs: []inputInfo{ 7483 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7484 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7485 }, 7486 outputs: []outputInfo{ 7487 {1, 0}, 7488 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7489 }, 7490 }, 7491 }, 7492 { 7493 name: "ADDSconst", 7494 auxType: auxInt32, 7495 argLen: 1, 7496 asm: arm.AADD, 7497 reg: regInfo{ 7498 inputs: []inputInfo{ 7499 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7500 }, 7501 outputs: []outputInfo{ 7502 {1, 0}, 7503 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7504 }, 7505 }, 7506 }, 7507 { 7508 name: "ADC", 7509 argLen: 3, 7510 commutative: true, 7511 asm: arm.AADC, 7512 reg: regInfo{ 7513 inputs: []inputInfo{ 7514 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7515 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7516 }, 7517 outputs: []outputInfo{ 7518 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7519 }, 7520 }, 7521 }, 7522 { 7523 name: "ADCconst", 7524 auxType: auxInt32, 7525 argLen: 2, 7526 asm: arm.AADC, 7527 reg: regInfo{ 7528 inputs: []inputInfo{ 7529 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7530 }, 7531 outputs: []outputInfo{ 7532 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7533 }, 7534 }, 7535 }, 7536 { 7537 name: "SUBS", 7538 argLen: 2, 7539 asm: arm.ASUB, 7540 reg: regInfo{ 7541 inputs: []inputInfo{ 7542 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7543 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7544 }, 7545 outputs: []outputInfo{ 7546 {1, 0}, 7547 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7548 }, 7549 }, 7550 }, 7551 { 7552 name: "SUBSconst", 7553 auxType: auxInt32, 7554 argLen: 1, 7555 asm: arm.ASUB, 7556 reg: regInfo{ 7557 inputs: []inputInfo{ 7558 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7559 }, 7560 outputs: []outputInfo{ 7561 {1, 0}, 7562 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7563 }, 7564 }, 7565 }, 7566 { 7567 name: "RSBSconst", 7568 auxType: auxInt32, 7569 argLen: 1, 7570 asm: arm.ARSB, 7571 reg: regInfo{ 7572 inputs: []inputInfo{ 7573 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7574 }, 7575 outputs: []outputInfo{ 7576 {1, 0}, 7577 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7578 }, 7579 }, 7580 }, 7581 { 7582 name: "SBC", 7583 argLen: 3, 7584 asm: arm.ASBC, 7585 reg: regInfo{ 7586 inputs: []inputInfo{ 7587 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7588 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7589 }, 7590 outputs: []outputInfo{ 7591 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7592 }, 7593 }, 7594 }, 7595 { 7596 name: "SBCconst", 7597 auxType: auxInt32, 7598 argLen: 2, 7599 asm: arm.ASBC, 7600 reg: regInfo{ 7601 inputs: []inputInfo{ 7602 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7603 }, 7604 outputs: []outputInfo{ 7605 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7606 }, 7607 }, 7608 }, 7609 { 7610 name: "RSCconst", 7611 auxType: auxInt32, 7612 argLen: 2, 7613 asm: arm.ARSC, 7614 reg: regInfo{ 7615 inputs: []inputInfo{ 7616 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7617 }, 7618 outputs: []outputInfo{ 7619 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7620 }, 7621 }, 7622 }, 7623 { 7624 name: "MULLU", 7625 argLen: 2, 7626 commutative: true, 7627 asm: arm.AMULLU, 7628 reg: regInfo{ 7629 inputs: []inputInfo{ 7630 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7631 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7632 }, 7633 outputs: []outputInfo{ 7634 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7635 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7636 }, 7637 }, 7638 }, 7639 { 7640 name: "MULA", 7641 argLen: 3, 7642 asm: arm.AMULA, 7643 reg: regInfo{ 7644 inputs: []inputInfo{ 7645 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7646 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7647 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7648 }, 7649 outputs: []outputInfo{ 7650 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7651 }, 7652 }, 7653 }, 7654 { 7655 name: "ADDF", 7656 argLen: 2, 7657 commutative: true, 7658 asm: arm.AADDF, 7659 reg: regInfo{ 7660 inputs: []inputInfo{ 7661 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7662 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7663 }, 7664 outputs: []outputInfo{ 7665 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7666 }, 7667 }, 7668 }, 7669 { 7670 name: "ADDD", 7671 argLen: 2, 7672 commutative: true, 7673 asm: arm.AADDD, 7674 reg: regInfo{ 7675 inputs: []inputInfo{ 7676 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7677 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7678 }, 7679 outputs: []outputInfo{ 7680 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7681 }, 7682 }, 7683 }, 7684 { 7685 name: "SUBF", 7686 argLen: 2, 7687 asm: arm.ASUBF, 7688 reg: regInfo{ 7689 inputs: []inputInfo{ 7690 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7691 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7692 }, 7693 outputs: []outputInfo{ 7694 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7695 }, 7696 }, 7697 }, 7698 { 7699 name: "SUBD", 7700 argLen: 2, 7701 asm: arm.ASUBD, 7702 reg: regInfo{ 7703 inputs: []inputInfo{ 7704 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7705 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7706 }, 7707 outputs: []outputInfo{ 7708 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7709 }, 7710 }, 7711 }, 7712 { 7713 name: "MULF", 7714 argLen: 2, 7715 commutative: true, 7716 asm: arm.AMULF, 7717 reg: regInfo{ 7718 inputs: []inputInfo{ 7719 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7720 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7721 }, 7722 outputs: []outputInfo{ 7723 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7724 }, 7725 }, 7726 }, 7727 { 7728 name: "MULD", 7729 argLen: 2, 7730 commutative: true, 7731 asm: arm.AMULD, 7732 reg: regInfo{ 7733 inputs: []inputInfo{ 7734 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7735 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7736 }, 7737 outputs: []outputInfo{ 7738 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7739 }, 7740 }, 7741 }, 7742 { 7743 name: "DIVF", 7744 argLen: 2, 7745 asm: arm.ADIVF, 7746 reg: regInfo{ 7747 inputs: []inputInfo{ 7748 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7749 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7750 }, 7751 outputs: []outputInfo{ 7752 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7753 }, 7754 }, 7755 }, 7756 { 7757 name: "DIVD", 7758 argLen: 2, 7759 asm: arm.ADIVD, 7760 reg: regInfo{ 7761 inputs: []inputInfo{ 7762 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7763 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7764 }, 7765 outputs: []outputInfo{ 7766 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7767 }, 7768 }, 7769 }, 7770 { 7771 name: "AND", 7772 argLen: 2, 7773 commutative: true, 7774 asm: arm.AAND, 7775 reg: regInfo{ 7776 inputs: []inputInfo{ 7777 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7778 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7779 }, 7780 outputs: []outputInfo{ 7781 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7782 }, 7783 }, 7784 }, 7785 { 7786 name: "ANDconst", 7787 auxType: auxInt32, 7788 argLen: 1, 7789 asm: arm.AAND, 7790 reg: regInfo{ 7791 inputs: []inputInfo{ 7792 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7793 }, 7794 outputs: []outputInfo{ 7795 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7796 }, 7797 }, 7798 }, 7799 { 7800 name: "OR", 7801 argLen: 2, 7802 commutative: true, 7803 asm: arm.AORR, 7804 reg: regInfo{ 7805 inputs: []inputInfo{ 7806 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7807 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7808 }, 7809 outputs: []outputInfo{ 7810 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7811 }, 7812 }, 7813 }, 7814 { 7815 name: "ORconst", 7816 auxType: auxInt32, 7817 argLen: 1, 7818 asm: arm.AORR, 7819 reg: regInfo{ 7820 inputs: []inputInfo{ 7821 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7822 }, 7823 outputs: []outputInfo{ 7824 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7825 }, 7826 }, 7827 }, 7828 { 7829 name: "XOR", 7830 argLen: 2, 7831 commutative: true, 7832 asm: arm.AEOR, 7833 reg: regInfo{ 7834 inputs: []inputInfo{ 7835 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7836 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7837 }, 7838 outputs: []outputInfo{ 7839 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7840 }, 7841 }, 7842 }, 7843 { 7844 name: "XORconst", 7845 auxType: auxInt32, 7846 argLen: 1, 7847 asm: arm.AEOR, 7848 reg: regInfo{ 7849 inputs: []inputInfo{ 7850 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7851 }, 7852 outputs: []outputInfo{ 7853 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7854 }, 7855 }, 7856 }, 7857 { 7858 name: "BIC", 7859 argLen: 2, 7860 asm: arm.ABIC, 7861 reg: regInfo{ 7862 inputs: []inputInfo{ 7863 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7864 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7865 }, 7866 outputs: []outputInfo{ 7867 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7868 }, 7869 }, 7870 }, 7871 { 7872 name: "BICconst", 7873 auxType: auxInt32, 7874 argLen: 1, 7875 asm: arm.ABIC, 7876 reg: regInfo{ 7877 inputs: []inputInfo{ 7878 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7879 }, 7880 outputs: []outputInfo{ 7881 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7882 }, 7883 }, 7884 }, 7885 { 7886 name: "MVN", 7887 argLen: 1, 7888 asm: arm.AMVN, 7889 reg: regInfo{ 7890 inputs: []inputInfo{ 7891 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7892 }, 7893 outputs: []outputInfo{ 7894 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7895 }, 7896 }, 7897 }, 7898 { 7899 name: "NEGF", 7900 argLen: 1, 7901 asm: arm.ANEGF, 7902 reg: regInfo{ 7903 inputs: []inputInfo{ 7904 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7905 }, 7906 outputs: []outputInfo{ 7907 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7908 }, 7909 }, 7910 }, 7911 { 7912 name: "NEGD", 7913 argLen: 1, 7914 asm: arm.ANEGD, 7915 reg: regInfo{ 7916 inputs: []inputInfo{ 7917 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7918 }, 7919 outputs: []outputInfo{ 7920 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7921 }, 7922 }, 7923 }, 7924 { 7925 name: "SQRTD", 7926 argLen: 1, 7927 asm: arm.ASQRTD, 7928 reg: regInfo{ 7929 inputs: []inputInfo{ 7930 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7931 }, 7932 outputs: []outputInfo{ 7933 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7934 }, 7935 }, 7936 }, 7937 { 7938 name: "CLZ", 7939 argLen: 1, 7940 asm: arm.ACLZ, 7941 reg: regInfo{ 7942 inputs: []inputInfo{ 7943 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7944 }, 7945 outputs: []outputInfo{ 7946 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7947 }, 7948 }, 7949 }, 7950 { 7951 name: "SLL", 7952 argLen: 2, 7953 asm: arm.ASLL, 7954 reg: regInfo{ 7955 inputs: []inputInfo{ 7956 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7957 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7958 }, 7959 outputs: []outputInfo{ 7960 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7961 }, 7962 }, 7963 }, 7964 { 7965 name: "SLLconst", 7966 auxType: auxInt32, 7967 argLen: 1, 7968 asm: arm.ASLL, 7969 reg: regInfo{ 7970 inputs: []inputInfo{ 7971 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7972 }, 7973 outputs: []outputInfo{ 7974 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7975 }, 7976 }, 7977 }, 7978 { 7979 name: "SRL", 7980 argLen: 2, 7981 asm: arm.ASRL, 7982 reg: regInfo{ 7983 inputs: []inputInfo{ 7984 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7985 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7986 }, 7987 outputs: []outputInfo{ 7988 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7989 }, 7990 }, 7991 }, 7992 { 7993 name: "SRLconst", 7994 auxType: auxInt32, 7995 argLen: 1, 7996 asm: arm.ASRL, 7997 reg: regInfo{ 7998 inputs: []inputInfo{ 7999 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8000 }, 8001 outputs: []outputInfo{ 8002 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8003 }, 8004 }, 8005 }, 8006 { 8007 name: "SRA", 8008 argLen: 2, 8009 asm: arm.ASRA, 8010 reg: regInfo{ 8011 inputs: []inputInfo{ 8012 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8013 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8014 }, 8015 outputs: []outputInfo{ 8016 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8017 }, 8018 }, 8019 }, 8020 { 8021 name: "SRAconst", 8022 auxType: auxInt32, 8023 argLen: 1, 8024 asm: arm.ASRA, 8025 reg: regInfo{ 8026 inputs: []inputInfo{ 8027 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8028 }, 8029 outputs: []outputInfo{ 8030 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8031 }, 8032 }, 8033 }, 8034 { 8035 name: "SRRconst", 8036 auxType: auxInt32, 8037 argLen: 1, 8038 reg: regInfo{ 8039 inputs: []inputInfo{ 8040 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8041 }, 8042 outputs: []outputInfo{ 8043 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8044 }, 8045 }, 8046 }, 8047 { 8048 name: "ADDshiftLL", 8049 auxType: auxInt32, 8050 argLen: 2, 8051 asm: arm.AADD, 8052 reg: regInfo{ 8053 inputs: []inputInfo{ 8054 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8055 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8056 }, 8057 outputs: []outputInfo{ 8058 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8059 }, 8060 }, 8061 }, 8062 { 8063 name: "ADDshiftRL", 8064 auxType: auxInt32, 8065 argLen: 2, 8066 asm: arm.AADD, 8067 reg: regInfo{ 8068 inputs: []inputInfo{ 8069 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8070 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8071 }, 8072 outputs: []outputInfo{ 8073 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8074 }, 8075 }, 8076 }, 8077 { 8078 name: "ADDshiftRA", 8079 auxType: auxInt32, 8080 argLen: 2, 8081 asm: arm.AADD, 8082 reg: regInfo{ 8083 inputs: []inputInfo{ 8084 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8085 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8086 }, 8087 outputs: []outputInfo{ 8088 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8089 }, 8090 }, 8091 }, 8092 { 8093 name: "SUBshiftLL", 8094 auxType: auxInt32, 8095 argLen: 2, 8096 asm: arm.ASUB, 8097 reg: regInfo{ 8098 inputs: []inputInfo{ 8099 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8100 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8101 }, 8102 outputs: []outputInfo{ 8103 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8104 }, 8105 }, 8106 }, 8107 { 8108 name: "SUBshiftRL", 8109 auxType: auxInt32, 8110 argLen: 2, 8111 asm: arm.ASUB, 8112 reg: regInfo{ 8113 inputs: []inputInfo{ 8114 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8115 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8116 }, 8117 outputs: []outputInfo{ 8118 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8119 }, 8120 }, 8121 }, 8122 { 8123 name: "SUBshiftRA", 8124 auxType: auxInt32, 8125 argLen: 2, 8126 asm: arm.ASUB, 8127 reg: regInfo{ 8128 inputs: []inputInfo{ 8129 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8130 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8131 }, 8132 outputs: []outputInfo{ 8133 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8134 }, 8135 }, 8136 }, 8137 { 8138 name: "RSBshiftLL", 8139 auxType: auxInt32, 8140 argLen: 2, 8141 asm: arm.ARSB, 8142 reg: regInfo{ 8143 inputs: []inputInfo{ 8144 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8145 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8146 }, 8147 outputs: []outputInfo{ 8148 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8149 }, 8150 }, 8151 }, 8152 { 8153 name: "RSBshiftRL", 8154 auxType: auxInt32, 8155 argLen: 2, 8156 asm: arm.ARSB, 8157 reg: regInfo{ 8158 inputs: []inputInfo{ 8159 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8160 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8161 }, 8162 outputs: []outputInfo{ 8163 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8164 }, 8165 }, 8166 }, 8167 { 8168 name: "RSBshiftRA", 8169 auxType: auxInt32, 8170 argLen: 2, 8171 asm: arm.ARSB, 8172 reg: regInfo{ 8173 inputs: []inputInfo{ 8174 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8175 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8176 }, 8177 outputs: []outputInfo{ 8178 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8179 }, 8180 }, 8181 }, 8182 { 8183 name: "ANDshiftLL", 8184 auxType: auxInt32, 8185 argLen: 2, 8186 asm: arm.AAND, 8187 reg: regInfo{ 8188 inputs: []inputInfo{ 8189 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8190 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8191 }, 8192 outputs: []outputInfo{ 8193 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8194 }, 8195 }, 8196 }, 8197 { 8198 name: "ANDshiftRL", 8199 auxType: auxInt32, 8200 argLen: 2, 8201 asm: arm.AAND, 8202 reg: regInfo{ 8203 inputs: []inputInfo{ 8204 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8205 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8206 }, 8207 outputs: []outputInfo{ 8208 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8209 }, 8210 }, 8211 }, 8212 { 8213 name: "ANDshiftRA", 8214 auxType: auxInt32, 8215 argLen: 2, 8216 asm: arm.AAND, 8217 reg: regInfo{ 8218 inputs: []inputInfo{ 8219 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8220 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8221 }, 8222 outputs: []outputInfo{ 8223 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8224 }, 8225 }, 8226 }, 8227 { 8228 name: "ORshiftLL", 8229 auxType: auxInt32, 8230 argLen: 2, 8231 asm: arm.AORR, 8232 reg: regInfo{ 8233 inputs: []inputInfo{ 8234 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8235 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8236 }, 8237 outputs: []outputInfo{ 8238 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8239 }, 8240 }, 8241 }, 8242 { 8243 name: "ORshiftRL", 8244 auxType: auxInt32, 8245 argLen: 2, 8246 asm: arm.AORR, 8247 reg: regInfo{ 8248 inputs: []inputInfo{ 8249 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8250 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8251 }, 8252 outputs: []outputInfo{ 8253 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8254 }, 8255 }, 8256 }, 8257 { 8258 name: "ORshiftRA", 8259 auxType: auxInt32, 8260 argLen: 2, 8261 asm: arm.AORR, 8262 reg: regInfo{ 8263 inputs: []inputInfo{ 8264 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8265 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8266 }, 8267 outputs: []outputInfo{ 8268 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8269 }, 8270 }, 8271 }, 8272 { 8273 name: "XORshiftLL", 8274 auxType: auxInt32, 8275 argLen: 2, 8276 asm: arm.AEOR, 8277 reg: regInfo{ 8278 inputs: []inputInfo{ 8279 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8280 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8281 }, 8282 outputs: []outputInfo{ 8283 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8284 }, 8285 }, 8286 }, 8287 { 8288 name: "XORshiftRL", 8289 auxType: auxInt32, 8290 argLen: 2, 8291 asm: arm.AEOR, 8292 reg: regInfo{ 8293 inputs: []inputInfo{ 8294 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8295 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8296 }, 8297 outputs: []outputInfo{ 8298 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8299 }, 8300 }, 8301 }, 8302 { 8303 name: "XORshiftRA", 8304 auxType: auxInt32, 8305 argLen: 2, 8306 asm: arm.AEOR, 8307 reg: regInfo{ 8308 inputs: []inputInfo{ 8309 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8310 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8311 }, 8312 outputs: []outputInfo{ 8313 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8314 }, 8315 }, 8316 }, 8317 { 8318 name: "XORshiftRR", 8319 auxType: auxInt32, 8320 argLen: 2, 8321 asm: arm.AEOR, 8322 reg: regInfo{ 8323 inputs: []inputInfo{ 8324 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8325 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8326 }, 8327 outputs: []outputInfo{ 8328 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8329 }, 8330 }, 8331 }, 8332 { 8333 name: "BICshiftLL", 8334 auxType: auxInt32, 8335 argLen: 2, 8336 asm: arm.ABIC, 8337 reg: regInfo{ 8338 inputs: []inputInfo{ 8339 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8340 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8341 }, 8342 outputs: []outputInfo{ 8343 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8344 }, 8345 }, 8346 }, 8347 { 8348 name: "BICshiftRL", 8349 auxType: auxInt32, 8350 argLen: 2, 8351 asm: arm.ABIC, 8352 reg: regInfo{ 8353 inputs: []inputInfo{ 8354 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8355 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8356 }, 8357 outputs: []outputInfo{ 8358 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8359 }, 8360 }, 8361 }, 8362 { 8363 name: "BICshiftRA", 8364 auxType: auxInt32, 8365 argLen: 2, 8366 asm: arm.ABIC, 8367 reg: regInfo{ 8368 inputs: []inputInfo{ 8369 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8370 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8371 }, 8372 outputs: []outputInfo{ 8373 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8374 }, 8375 }, 8376 }, 8377 { 8378 name: "MVNshiftLL", 8379 auxType: auxInt32, 8380 argLen: 1, 8381 asm: arm.AMVN, 8382 reg: regInfo{ 8383 inputs: []inputInfo{ 8384 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8385 }, 8386 outputs: []outputInfo{ 8387 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8388 }, 8389 }, 8390 }, 8391 { 8392 name: "MVNshiftRL", 8393 auxType: auxInt32, 8394 argLen: 1, 8395 asm: arm.AMVN, 8396 reg: regInfo{ 8397 inputs: []inputInfo{ 8398 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8399 }, 8400 outputs: []outputInfo{ 8401 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8402 }, 8403 }, 8404 }, 8405 { 8406 name: "MVNshiftRA", 8407 auxType: auxInt32, 8408 argLen: 1, 8409 asm: arm.AMVN, 8410 reg: regInfo{ 8411 inputs: []inputInfo{ 8412 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8413 }, 8414 outputs: []outputInfo{ 8415 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8416 }, 8417 }, 8418 }, 8419 { 8420 name: "ADCshiftLL", 8421 auxType: auxInt32, 8422 argLen: 3, 8423 asm: arm.AADC, 8424 reg: regInfo{ 8425 inputs: []inputInfo{ 8426 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8427 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8428 }, 8429 outputs: []outputInfo{ 8430 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8431 }, 8432 }, 8433 }, 8434 { 8435 name: "ADCshiftRL", 8436 auxType: auxInt32, 8437 argLen: 3, 8438 asm: arm.AADC, 8439 reg: regInfo{ 8440 inputs: []inputInfo{ 8441 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8442 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8443 }, 8444 outputs: []outputInfo{ 8445 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8446 }, 8447 }, 8448 }, 8449 { 8450 name: "ADCshiftRA", 8451 auxType: auxInt32, 8452 argLen: 3, 8453 asm: arm.AADC, 8454 reg: regInfo{ 8455 inputs: []inputInfo{ 8456 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8457 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8458 }, 8459 outputs: []outputInfo{ 8460 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8461 }, 8462 }, 8463 }, 8464 { 8465 name: "SBCshiftLL", 8466 auxType: auxInt32, 8467 argLen: 3, 8468 asm: arm.ASBC, 8469 reg: regInfo{ 8470 inputs: []inputInfo{ 8471 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8472 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8473 }, 8474 outputs: []outputInfo{ 8475 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8476 }, 8477 }, 8478 }, 8479 { 8480 name: "SBCshiftRL", 8481 auxType: auxInt32, 8482 argLen: 3, 8483 asm: arm.ASBC, 8484 reg: regInfo{ 8485 inputs: []inputInfo{ 8486 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8487 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8488 }, 8489 outputs: []outputInfo{ 8490 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8491 }, 8492 }, 8493 }, 8494 { 8495 name: "SBCshiftRA", 8496 auxType: auxInt32, 8497 argLen: 3, 8498 asm: arm.ASBC, 8499 reg: regInfo{ 8500 inputs: []inputInfo{ 8501 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8502 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8503 }, 8504 outputs: []outputInfo{ 8505 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8506 }, 8507 }, 8508 }, 8509 { 8510 name: "RSCshiftLL", 8511 auxType: auxInt32, 8512 argLen: 3, 8513 asm: arm.ARSC, 8514 reg: regInfo{ 8515 inputs: []inputInfo{ 8516 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8517 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8518 }, 8519 outputs: []outputInfo{ 8520 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8521 }, 8522 }, 8523 }, 8524 { 8525 name: "RSCshiftRL", 8526 auxType: auxInt32, 8527 argLen: 3, 8528 asm: arm.ARSC, 8529 reg: regInfo{ 8530 inputs: []inputInfo{ 8531 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8532 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8533 }, 8534 outputs: []outputInfo{ 8535 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8536 }, 8537 }, 8538 }, 8539 { 8540 name: "RSCshiftRA", 8541 auxType: auxInt32, 8542 argLen: 3, 8543 asm: arm.ARSC, 8544 reg: regInfo{ 8545 inputs: []inputInfo{ 8546 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8547 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8548 }, 8549 outputs: []outputInfo{ 8550 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8551 }, 8552 }, 8553 }, 8554 { 8555 name: "ADDSshiftLL", 8556 auxType: auxInt32, 8557 argLen: 2, 8558 asm: arm.AADD, 8559 reg: regInfo{ 8560 inputs: []inputInfo{ 8561 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8562 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8563 }, 8564 outputs: []outputInfo{ 8565 {1, 0}, 8566 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8567 }, 8568 }, 8569 }, 8570 { 8571 name: "ADDSshiftRL", 8572 auxType: auxInt32, 8573 argLen: 2, 8574 asm: arm.AADD, 8575 reg: regInfo{ 8576 inputs: []inputInfo{ 8577 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8578 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8579 }, 8580 outputs: []outputInfo{ 8581 {1, 0}, 8582 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8583 }, 8584 }, 8585 }, 8586 { 8587 name: "ADDSshiftRA", 8588 auxType: auxInt32, 8589 argLen: 2, 8590 asm: arm.AADD, 8591 reg: regInfo{ 8592 inputs: []inputInfo{ 8593 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8594 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8595 }, 8596 outputs: []outputInfo{ 8597 {1, 0}, 8598 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8599 }, 8600 }, 8601 }, 8602 { 8603 name: "SUBSshiftLL", 8604 auxType: auxInt32, 8605 argLen: 2, 8606 asm: arm.ASUB, 8607 reg: regInfo{ 8608 inputs: []inputInfo{ 8609 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8610 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8611 }, 8612 outputs: []outputInfo{ 8613 {1, 0}, 8614 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8615 }, 8616 }, 8617 }, 8618 { 8619 name: "SUBSshiftRL", 8620 auxType: auxInt32, 8621 argLen: 2, 8622 asm: arm.ASUB, 8623 reg: regInfo{ 8624 inputs: []inputInfo{ 8625 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8626 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8627 }, 8628 outputs: []outputInfo{ 8629 {1, 0}, 8630 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8631 }, 8632 }, 8633 }, 8634 { 8635 name: "SUBSshiftRA", 8636 auxType: auxInt32, 8637 argLen: 2, 8638 asm: arm.ASUB, 8639 reg: regInfo{ 8640 inputs: []inputInfo{ 8641 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8642 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8643 }, 8644 outputs: []outputInfo{ 8645 {1, 0}, 8646 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8647 }, 8648 }, 8649 }, 8650 { 8651 name: "RSBSshiftLL", 8652 auxType: auxInt32, 8653 argLen: 2, 8654 asm: arm.ARSB, 8655 reg: regInfo{ 8656 inputs: []inputInfo{ 8657 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8658 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8659 }, 8660 outputs: []outputInfo{ 8661 {1, 0}, 8662 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8663 }, 8664 }, 8665 }, 8666 { 8667 name: "RSBSshiftRL", 8668 auxType: auxInt32, 8669 argLen: 2, 8670 asm: arm.ARSB, 8671 reg: regInfo{ 8672 inputs: []inputInfo{ 8673 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8674 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8675 }, 8676 outputs: []outputInfo{ 8677 {1, 0}, 8678 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8679 }, 8680 }, 8681 }, 8682 { 8683 name: "RSBSshiftRA", 8684 auxType: auxInt32, 8685 argLen: 2, 8686 asm: arm.ARSB, 8687 reg: regInfo{ 8688 inputs: []inputInfo{ 8689 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8690 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8691 }, 8692 outputs: []outputInfo{ 8693 {1, 0}, 8694 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8695 }, 8696 }, 8697 }, 8698 { 8699 name: "ADDshiftLLreg", 8700 argLen: 3, 8701 asm: arm.AADD, 8702 reg: regInfo{ 8703 inputs: []inputInfo{ 8704 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8705 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8706 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8707 }, 8708 outputs: []outputInfo{ 8709 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8710 }, 8711 }, 8712 }, 8713 { 8714 name: "ADDshiftRLreg", 8715 argLen: 3, 8716 asm: arm.AADD, 8717 reg: regInfo{ 8718 inputs: []inputInfo{ 8719 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8720 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8721 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8722 }, 8723 outputs: []outputInfo{ 8724 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8725 }, 8726 }, 8727 }, 8728 { 8729 name: "ADDshiftRAreg", 8730 argLen: 3, 8731 asm: arm.AADD, 8732 reg: regInfo{ 8733 inputs: []inputInfo{ 8734 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8735 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8736 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8737 }, 8738 outputs: []outputInfo{ 8739 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8740 }, 8741 }, 8742 }, 8743 { 8744 name: "SUBshiftLLreg", 8745 argLen: 3, 8746 asm: arm.ASUB, 8747 reg: regInfo{ 8748 inputs: []inputInfo{ 8749 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8750 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8751 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8752 }, 8753 outputs: []outputInfo{ 8754 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8755 }, 8756 }, 8757 }, 8758 { 8759 name: "SUBshiftRLreg", 8760 argLen: 3, 8761 asm: arm.ASUB, 8762 reg: regInfo{ 8763 inputs: []inputInfo{ 8764 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8765 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8766 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8767 }, 8768 outputs: []outputInfo{ 8769 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8770 }, 8771 }, 8772 }, 8773 { 8774 name: "SUBshiftRAreg", 8775 argLen: 3, 8776 asm: arm.ASUB, 8777 reg: regInfo{ 8778 inputs: []inputInfo{ 8779 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8780 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8781 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8782 }, 8783 outputs: []outputInfo{ 8784 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8785 }, 8786 }, 8787 }, 8788 { 8789 name: "RSBshiftLLreg", 8790 argLen: 3, 8791 asm: arm.ARSB, 8792 reg: regInfo{ 8793 inputs: []inputInfo{ 8794 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8795 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8796 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8797 }, 8798 outputs: []outputInfo{ 8799 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8800 }, 8801 }, 8802 }, 8803 { 8804 name: "RSBshiftRLreg", 8805 argLen: 3, 8806 asm: arm.ARSB, 8807 reg: regInfo{ 8808 inputs: []inputInfo{ 8809 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8810 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8811 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8812 }, 8813 outputs: []outputInfo{ 8814 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8815 }, 8816 }, 8817 }, 8818 { 8819 name: "RSBshiftRAreg", 8820 argLen: 3, 8821 asm: arm.ARSB, 8822 reg: regInfo{ 8823 inputs: []inputInfo{ 8824 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8825 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8826 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8827 }, 8828 outputs: []outputInfo{ 8829 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8830 }, 8831 }, 8832 }, 8833 { 8834 name: "ANDshiftLLreg", 8835 argLen: 3, 8836 asm: arm.AAND, 8837 reg: regInfo{ 8838 inputs: []inputInfo{ 8839 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8840 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8841 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8842 }, 8843 outputs: []outputInfo{ 8844 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8845 }, 8846 }, 8847 }, 8848 { 8849 name: "ANDshiftRLreg", 8850 argLen: 3, 8851 asm: arm.AAND, 8852 reg: regInfo{ 8853 inputs: []inputInfo{ 8854 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8855 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8856 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8857 }, 8858 outputs: []outputInfo{ 8859 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8860 }, 8861 }, 8862 }, 8863 { 8864 name: "ANDshiftRAreg", 8865 argLen: 3, 8866 asm: arm.AAND, 8867 reg: regInfo{ 8868 inputs: []inputInfo{ 8869 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8870 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8871 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8872 }, 8873 outputs: []outputInfo{ 8874 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8875 }, 8876 }, 8877 }, 8878 { 8879 name: "ORshiftLLreg", 8880 argLen: 3, 8881 asm: arm.AORR, 8882 reg: regInfo{ 8883 inputs: []inputInfo{ 8884 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8885 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8886 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8887 }, 8888 outputs: []outputInfo{ 8889 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8890 }, 8891 }, 8892 }, 8893 { 8894 name: "ORshiftRLreg", 8895 argLen: 3, 8896 asm: arm.AORR, 8897 reg: regInfo{ 8898 inputs: []inputInfo{ 8899 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8900 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8901 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8902 }, 8903 outputs: []outputInfo{ 8904 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8905 }, 8906 }, 8907 }, 8908 { 8909 name: "ORshiftRAreg", 8910 argLen: 3, 8911 asm: arm.AORR, 8912 reg: regInfo{ 8913 inputs: []inputInfo{ 8914 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8915 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8916 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8917 }, 8918 outputs: []outputInfo{ 8919 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8920 }, 8921 }, 8922 }, 8923 { 8924 name: "XORshiftLLreg", 8925 argLen: 3, 8926 asm: arm.AEOR, 8927 reg: regInfo{ 8928 inputs: []inputInfo{ 8929 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8930 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8931 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8932 }, 8933 outputs: []outputInfo{ 8934 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8935 }, 8936 }, 8937 }, 8938 { 8939 name: "XORshiftRLreg", 8940 argLen: 3, 8941 asm: arm.AEOR, 8942 reg: regInfo{ 8943 inputs: []inputInfo{ 8944 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8945 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8946 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8947 }, 8948 outputs: []outputInfo{ 8949 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8950 }, 8951 }, 8952 }, 8953 { 8954 name: "XORshiftRAreg", 8955 argLen: 3, 8956 asm: arm.AEOR, 8957 reg: regInfo{ 8958 inputs: []inputInfo{ 8959 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8960 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8961 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8962 }, 8963 outputs: []outputInfo{ 8964 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8965 }, 8966 }, 8967 }, 8968 { 8969 name: "BICshiftLLreg", 8970 argLen: 3, 8971 asm: arm.ABIC, 8972 reg: regInfo{ 8973 inputs: []inputInfo{ 8974 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8975 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8976 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8977 }, 8978 outputs: []outputInfo{ 8979 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8980 }, 8981 }, 8982 }, 8983 { 8984 name: "BICshiftRLreg", 8985 argLen: 3, 8986 asm: arm.ABIC, 8987 reg: regInfo{ 8988 inputs: []inputInfo{ 8989 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8990 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8991 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8992 }, 8993 outputs: []outputInfo{ 8994 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8995 }, 8996 }, 8997 }, 8998 { 8999 name: "BICshiftRAreg", 9000 argLen: 3, 9001 asm: arm.ABIC, 9002 reg: regInfo{ 9003 inputs: []inputInfo{ 9004 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9005 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9006 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9007 }, 9008 outputs: []outputInfo{ 9009 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9010 }, 9011 }, 9012 }, 9013 { 9014 name: "MVNshiftLLreg", 9015 argLen: 2, 9016 asm: arm.AMVN, 9017 reg: regInfo{ 9018 inputs: []inputInfo{ 9019 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9020 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9021 }, 9022 outputs: []outputInfo{ 9023 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9024 }, 9025 }, 9026 }, 9027 { 9028 name: "MVNshiftRLreg", 9029 argLen: 2, 9030 asm: arm.AMVN, 9031 reg: regInfo{ 9032 inputs: []inputInfo{ 9033 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9034 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9035 }, 9036 outputs: []outputInfo{ 9037 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9038 }, 9039 }, 9040 }, 9041 { 9042 name: "MVNshiftRAreg", 9043 argLen: 2, 9044 asm: arm.AMVN, 9045 reg: regInfo{ 9046 inputs: []inputInfo{ 9047 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9048 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9049 }, 9050 outputs: []outputInfo{ 9051 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9052 }, 9053 }, 9054 }, 9055 { 9056 name: "ADCshiftLLreg", 9057 argLen: 4, 9058 asm: arm.AADC, 9059 reg: regInfo{ 9060 inputs: []inputInfo{ 9061 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9062 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9063 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9064 }, 9065 outputs: []outputInfo{ 9066 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9067 }, 9068 }, 9069 }, 9070 { 9071 name: "ADCshiftRLreg", 9072 argLen: 4, 9073 asm: arm.AADC, 9074 reg: regInfo{ 9075 inputs: []inputInfo{ 9076 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9077 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9078 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9079 }, 9080 outputs: []outputInfo{ 9081 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9082 }, 9083 }, 9084 }, 9085 { 9086 name: "ADCshiftRAreg", 9087 argLen: 4, 9088 asm: arm.AADC, 9089 reg: regInfo{ 9090 inputs: []inputInfo{ 9091 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9092 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9093 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9094 }, 9095 outputs: []outputInfo{ 9096 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9097 }, 9098 }, 9099 }, 9100 { 9101 name: "SBCshiftLLreg", 9102 argLen: 4, 9103 asm: arm.ASBC, 9104 reg: regInfo{ 9105 inputs: []inputInfo{ 9106 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9107 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9108 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9109 }, 9110 outputs: []outputInfo{ 9111 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9112 }, 9113 }, 9114 }, 9115 { 9116 name: "SBCshiftRLreg", 9117 argLen: 4, 9118 asm: arm.ASBC, 9119 reg: regInfo{ 9120 inputs: []inputInfo{ 9121 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9122 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9123 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9124 }, 9125 outputs: []outputInfo{ 9126 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9127 }, 9128 }, 9129 }, 9130 { 9131 name: "SBCshiftRAreg", 9132 argLen: 4, 9133 asm: arm.ASBC, 9134 reg: regInfo{ 9135 inputs: []inputInfo{ 9136 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9137 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9138 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9139 }, 9140 outputs: []outputInfo{ 9141 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9142 }, 9143 }, 9144 }, 9145 { 9146 name: "RSCshiftLLreg", 9147 argLen: 4, 9148 asm: arm.ARSC, 9149 reg: regInfo{ 9150 inputs: []inputInfo{ 9151 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9152 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9153 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9154 }, 9155 outputs: []outputInfo{ 9156 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9157 }, 9158 }, 9159 }, 9160 { 9161 name: "RSCshiftRLreg", 9162 argLen: 4, 9163 asm: arm.ARSC, 9164 reg: regInfo{ 9165 inputs: []inputInfo{ 9166 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9167 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9168 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9169 }, 9170 outputs: []outputInfo{ 9171 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9172 }, 9173 }, 9174 }, 9175 { 9176 name: "RSCshiftRAreg", 9177 argLen: 4, 9178 asm: arm.ARSC, 9179 reg: regInfo{ 9180 inputs: []inputInfo{ 9181 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9182 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9183 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9184 }, 9185 outputs: []outputInfo{ 9186 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9187 }, 9188 }, 9189 }, 9190 { 9191 name: "ADDSshiftLLreg", 9192 argLen: 3, 9193 asm: arm.AADD, 9194 reg: regInfo{ 9195 inputs: []inputInfo{ 9196 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9197 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9198 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9199 }, 9200 outputs: []outputInfo{ 9201 {1, 0}, 9202 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9203 }, 9204 }, 9205 }, 9206 { 9207 name: "ADDSshiftRLreg", 9208 argLen: 3, 9209 asm: arm.AADD, 9210 reg: regInfo{ 9211 inputs: []inputInfo{ 9212 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9213 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9214 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9215 }, 9216 outputs: []outputInfo{ 9217 {1, 0}, 9218 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9219 }, 9220 }, 9221 }, 9222 { 9223 name: "ADDSshiftRAreg", 9224 argLen: 3, 9225 asm: arm.AADD, 9226 reg: regInfo{ 9227 inputs: []inputInfo{ 9228 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9229 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9230 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9231 }, 9232 outputs: []outputInfo{ 9233 {1, 0}, 9234 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9235 }, 9236 }, 9237 }, 9238 { 9239 name: "SUBSshiftLLreg", 9240 argLen: 3, 9241 asm: arm.ASUB, 9242 reg: regInfo{ 9243 inputs: []inputInfo{ 9244 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9245 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9246 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9247 }, 9248 outputs: []outputInfo{ 9249 {1, 0}, 9250 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9251 }, 9252 }, 9253 }, 9254 { 9255 name: "SUBSshiftRLreg", 9256 argLen: 3, 9257 asm: arm.ASUB, 9258 reg: regInfo{ 9259 inputs: []inputInfo{ 9260 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9261 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9262 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9263 }, 9264 outputs: []outputInfo{ 9265 {1, 0}, 9266 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9267 }, 9268 }, 9269 }, 9270 { 9271 name: "SUBSshiftRAreg", 9272 argLen: 3, 9273 asm: arm.ASUB, 9274 reg: regInfo{ 9275 inputs: []inputInfo{ 9276 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9277 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9278 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9279 }, 9280 outputs: []outputInfo{ 9281 {1, 0}, 9282 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9283 }, 9284 }, 9285 }, 9286 { 9287 name: "RSBSshiftLLreg", 9288 argLen: 3, 9289 asm: arm.ARSB, 9290 reg: regInfo{ 9291 inputs: []inputInfo{ 9292 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9293 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9294 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9295 }, 9296 outputs: []outputInfo{ 9297 {1, 0}, 9298 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9299 }, 9300 }, 9301 }, 9302 { 9303 name: "RSBSshiftRLreg", 9304 argLen: 3, 9305 asm: arm.ARSB, 9306 reg: regInfo{ 9307 inputs: []inputInfo{ 9308 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9309 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9310 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9311 }, 9312 outputs: []outputInfo{ 9313 {1, 0}, 9314 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9315 }, 9316 }, 9317 }, 9318 { 9319 name: "RSBSshiftRAreg", 9320 argLen: 3, 9321 asm: arm.ARSB, 9322 reg: regInfo{ 9323 inputs: []inputInfo{ 9324 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9325 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9326 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9327 }, 9328 outputs: []outputInfo{ 9329 {1, 0}, 9330 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9331 }, 9332 }, 9333 }, 9334 { 9335 name: "CMP", 9336 argLen: 2, 9337 asm: arm.ACMP, 9338 reg: regInfo{ 9339 inputs: []inputInfo{ 9340 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9341 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9342 }, 9343 }, 9344 }, 9345 { 9346 name: "CMPconst", 9347 auxType: auxInt32, 9348 argLen: 1, 9349 asm: arm.ACMP, 9350 reg: regInfo{ 9351 inputs: []inputInfo{ 9352 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9353 }, 9354 }, 9355 }, 9356 { 9357 name: "CMN", 9358 argLen: 2, 9359 asm: arm.ACMN, 9360 reg: regInfo{ 9361 inputs: []inputInfo{ 9362 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9363 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9364 }, 9365 }, 9366 }, 9367 { 9368 name: "CMNconst", 9369 auxType: auxInt32, 9370 argLen: 1, 9371 asm: arm.ACMN, 9372 reg: regInfo{ 9373 inputs: []inputInfo{ 9374 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9375 }, 9376 }, 9377 }, 9378 { 9379 name: "TST", 9380 argLen: 2, 9381 commutative: true, 9382 asm: arm.ATST, 9383 reg: regInfo{ 9384 inputs: []inputInfo{ 9385 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9386 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9387 }, 9388 }, 9389 }, 9390 { 9391 name: "TSTconst", 9392 auxType: auxInt32, 9393 argLen: 1, 9394 asm: arm.ATST, 9395 reg: regInfo{ 9396 inputs: []inputInfo{ 9397 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9398 }, 9399 }, 9400 }, 9401 { 9402 name: "TEQ", 9403 argLen: 2, 9404 commutative: true, 9405 asm: arm.ATEQ, 9406 reg: regInfo{ 9407 inputs: []inputInfo{ 9408 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9409 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9410 }, 9411 }, 9412 }, 9413 { 9414 name: "TEQconst", 9415 auxType: auxInt32, 9416 argLen: 1, 9417 asm: arm.ATEQ, 9418 reg: regInfo{ 9419 inputs: []inputInfo{ 9420 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9421 }, 9422 }, 9423 }, 9424 { 9425 name: "CMPF", 9426 argLen: 2, 9427 asm: arm.ACMPF, 9428 reg: regInfo{ 9429 inputs: []inputInfo{ 9430 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9431 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9432 }, 9433 }, 9434 }, 9435 { 9436 name: "CMPD", 9437 argLen: 2, 9438 asm: arm.ACMPD, 9439 reg: regInfo{ 9440 inputs: []inputInfo{ 9441 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9442 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9443 }, 9444 }, 9445 }, 9446 { 9447 name: "CMPshiftLL", 9448 auxType: auxInt32, 9449 argLen: 2, 9450 asm: arm.ACMP, 9451 reg: regInfo{ 9452 inputs: []inputInfo{ 9453 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9454 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9455 }, 9456 }, 9457 }, 9458 { 9459 name: "CMPshiftRL", 9460 auxType: auxInt32, 9461 argLen: 2, 9462 asm: arm.ACMP, 9463 reg: regInfo{ 9464 inputs: []inputInfo{ 9465 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9466 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9467 }, 9468 }, 9469 }, 9470 { 9471 name: "CMPshiftRA", 9472 auxType: auxInt32, 9473 argLen: 2, 9474 asm: arm.ACMP, 9475 reg: regInfo{ 9476 inputs: []inputInfo{ 9477 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9478 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9479 }, 9480 }, 9481 }, 9482 { 9483 name: "CMPshiftLLreg", 9484 argLen: 3, 9485 asm: arm.ACMP, 9486 reg: regInfo{ 9487 inputs: []inputInfo{ 9488 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9489 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9490 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9491 }, 9492 }, 9493 }, 9494 { 9495 name: "CMPshiftRLreg", 9496 argLen: 3, 9497 asm: arm.ACMP, 9498 reg: regInfo{ 9499 inputs: []inputInfo{ 9500 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9501 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9502 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9503 }, 9504 }, 9505 }, 9506 { 9507 name: "CMPshiftRAreg", 9508 argLen: 3, 9509 asm: arm.ACMP, 9510 reg: regInfo{ 9511 inputs: []inputInfo{ 9512 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9513 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9514 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9515 }, 9516 }, 9517 }, 9518 { 9519 name: "CMPF0", 9520 argLen: 1, 9521 asm: arm.ACMPF, 9522 reg: regInfo{ 9523 inputs: []inputInfo{ 9524 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9525 }, 9526 }, 9527 }, 9528 { 9529 name: "CMPD0", 9530 argLen: 1, 9531 asm: arm.ACMPD, 9532 reg: regInfo{ 9533 inputs: []inputInfo{ 9534 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9535 }, 9536 }, 9537 }, 9538 { 9539 name: "MOVWconst", 9540 auxType: auxInt32, 9541 argLen: 0, 9542 rematerializeable: true, 9543 asm: arm.AMOVW, 9544 reg: regInfo{ 9545 outputs: []outputInfo{ 9546 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9547 }, 9548 }, 9549 }, 9550 { 9551 name: "MOVFconst", 9552 auxType: auxFloat64, 9553 argLen: 0, 9554 rematerializeable: true, 9555 asm: arm.AMOVF, 9556 reg: regInfo{ 9557 outputs: []outputInfo{ 9558 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9559 }, 9560 }, 9561 }, 9562 { 9563 name: "MOVDconst", 9564 auxType: auxFloat64, 9565 argLen: 0, 9566 rematerializeable: true, 9567 asm: arm.AMOVD, 9568 reg: regInfo{ 9569 outputs: []outputInfo{ 9570 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9571 }, 9572 }, 9573 }, 9574 { 9575 name: "MOVWaddr", 9576 auxType: auxSymOff, 9577 argLen: 1, 9578 rematerializeable: true, 9579 asm: arm.AMOVW, 9580 reg: regInfo{ 9581 inputs: []inputInfo{ 9582 {0, 4294975488}, // SP SB 9583 }, 9584 outputs: []outputInfo{ 9585 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9586 }, 9587 }, 9588 }, 9589 { 9590 name: "MOVBload", 9591 auxType: auxSymOff, 9592 argLen: 2, 9593 faultOnNilArg0: true, 9594 asm: arm.AMOVB, 9595 reg: regInfo{ 9596 inputs: []inputInfo{ 9597 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9598 }, 9599 outputs: []outputInfo{ 9600 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9601 }, 9602 }, 9603 }, 9604 { 9605 name: "MOVBUload", 9606 auxType: auxSymOff, 9607 argLen: 2, 9608 faultOnNilArg0: true, 9609 asm: arm.AMOVBU, 9610 reg: regInfo{ 9611 inputs: []inputInfo{ 9612 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9613 }, 9614 outputs: []outputInfo{ 9615 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9616 }, 9617 }, 9618 }, 9619 { 9620 name: "MOVHload", 9621 auxType: auxSymOff, 9622 argLen: 2, 9623 faultOnNilArg0: true, 9624 asm: arm.AMOVH, 9625 reg: regInfo{ 9626 inputs: []inputInfo{ 9627 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9628 }, 9629 outputs: []outputInfo{ 9630 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9631 }, 9632 }, 9633 }, 9634 { 9635 name: "MOVHUload", 9636 auxType: auxSymOff, 9637 argLen: 2, 9638 faultOnNilArg0: true, 9639 asm: arm.AMOVHU, 9640 reg: regInfo{ 9641 inputs: []inputInfo{ 9642 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9643 }, 9644 outputs: []outputInfo{ 9645 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9646 }, 9647 }, 9648 }, 9649 { 9650 name: "MOVWload", 9651 auxType: auxSymOff, 9652 argLen: 2, 9653 faultOnNilArg0: true, 9654 asm: arm.AMOVW, 9655 reg: regInfo{ 9656 inputs: []inputInfo{ 9657 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9658 }, 9659 outputs: []outputInfo{ 9660 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9661 }, 9662 }, 9663 }, 9664 { 9665 name: "MOVFload", 9666 auxType: auxSymOff, 9667 argLen: 2, 9668 faultOnNilArg0: true, 9669 asm: arm.AMOVF, 9670 reg: regInfo{ 9671 inputs: []inputInfo{ 9672 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9673 }, 9674 outputs: []outputInfo{ 9675 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9676 }, 9677 }, 9678 }, 9679 { 9680 name: "MOVDload", 9681 auxType: auxSymOff, 9682 argLen: 2, 9683 faultOnNilArg0: true, 9684 asm: arm.AMOVD, 9685 reg: regInfo{ 9686 inputs: []inputInfo{ 9687 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9688 }, 9689 outputs: []outputInfo{ 9690 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9691 }, 9692 }, 9693 }, 9694 { 9695 name: "MOVBstore", 9696 auxType: auxSymOff, 9697 argLen: 3, 9698 faultOnNilArg0: true, 9699 asm: arm.AMOVB, 9700 reg: regInfo{ 9701 inputs: []inputInfo{ 9702 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9703 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9704 }, 9705 }, 9706 }, 9707 { 9708 name: "MOVHstore", 9709 auxType: auxSymOff, 9710 argLen: 3, 9711 faultOnNilArg0: true, 9712 asm: arm.AMOVH, 9713 reg: regInfo{ 9714 inputs: []inputInfo{ 9715 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9716 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9717 }, 9718 }, 9719 }, 9720 { 9721 name: "MOVWstore", 9722 auxType: auxSymOff, 9723 argLen: 3, 9724 faultOnNilArg0: true, 9725 asm: arm.AMOVW, 9726 reg: regInfo{ 9727 inputs: []inputInfo{ 9728 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9729 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9730 }, 9731 }, 9732 }, 9733 { 9734 name: "MOVFstore", 9735 auxType: auxSymOff, 9736 argLen: 3, 9737 faultOnNilArg0: true, 9738 asm: arm.AMOVF, 9739 reg: regInfo{ 9740 inputs: []inputInfo{ 9741 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9742 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9743 }, 9744 }, 9745 }, 9746 { 9747 name: "MOVDstore", 9748 auxType: auxSymOff, 9749 argLen: 3, 9750 faultOnNilArg0: true, 9751 asm: arm.AMOVD, 9752 reg: regInfo{ 9753 inputs: []inputInfo{ 9754 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9755 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9756 }, 9757 }, 9758 }, 9759 { 9760 name: "MOVWloadidx", 9761 argLen: 3, 9762 asm: arm.AMOVW, 9763 reg: regInfo{ 9764 inputs: []inputInfo{ 9765 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9766 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9767 }, 9768 outputs: []outputInfo{ 9769 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9770 }, 9771 }, 9772 }, 9773 { 9774 name: "MOVWloadshiftLL", 9775 auxType: auxInt32, 9776 argLen: 3, 9777 asm: arm.AMOVW, 9778 reg: regInfo{ 9779 inputs: []inputInfo{ 9780 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9781 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9782 }, 9783 outputs: []outputInfo{ 9784 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9785 }, 9786 }, 9787 }, 9788 { 9789 name: "MOVWloadshiftRL", 9790 auxType: auxInt32, 9791 argLen: 3, 9792 asm: arm.AMOVW, 9793 reg: regInfo{ 9794 inputs: []inputInfo{ 9795 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9796 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9797 }, 9798 outputs: []outputInfo{ 9799 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9800 }, 9801 }, 9802 }, 9803 { 9804 name: "MOVWloadshiftRA", 9805 auxType: auxInt32, 9806 argLen: 3, 9807 asm: arm.AMOVW, 9808 reg: regInfo{ 9809 inputs: []inputInfo{ 9810 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9811 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9812 }, 9813 outputs: []outputInfo{ 9814 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9815 }, 9816 }, 9817 }, 9818 { 9819 name: "MOVWstoreidx", 9820 argLen: 4, 9821 asm: arm.AMOVW, 9822 reg: regInfo{ 9823 inputs: []inputInfo{ 9824 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9825 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9826 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9827 }, 9828 }, 9829 }, 9830 { 9831 name: "MOVWstoreshiftLL", 9832 auxType: auxInt32, 9833 argLen: 4, 9834 asm: arm.AMOVW, 9835 reg: regInfo{ 9836 inputs: []inputInfo{ 9837 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9838 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9839 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9840 }, 9841 }, 9842 }, 9843 { 9844 name: "MOVWstoreshiftRL", 9845 auxType: auxInt32, 9846 argLen: 4, 9847 asm: arm.AMOVW, 9848 reg: regInfo{ 9849 inputs: []inputInfo{ 9850 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9851 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9852 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9853 }, 9854 }, 9855 }, 9856 { 9857 name: "MOVWstoreshiftRA", 9858 auxType: auxInt32, 9859 argLen: 4, 9860 asm: arm.AMOVW, 9861 reg: regInfo{ 9862 inputs: []inputInfo{ 9863 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9864 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9865 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9866 }, 9867 }, 9868 }, 9869 { 9870 name: "MOVBreg", 9871 argLen: 1, 9872 asm: arm.AMOVBS, 9873 reg: regInfo{ 9874 inputs: []inputInfo{ 9875 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9876 }, 9877 outputs: []outputInfo{ 9878 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9879 }, 9880 }, 9881 }, 9882 { 9883 name: "MOVBUreg", 9884 argLen: 1, 9885 asm: arm.AMOVBU, 9886 reg: regInfo{ 9887 inputs: []inputInfo{ 9888 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9889 }, 9890 outputs: []outputInfo{ 9891 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9892 }, 9893 }, 9894 }, 9895 { 9896 name: "MOVHreg", 9897 argLen: 1, 9898 asm: arm.AMOVHS, 9899 reg: regInfo{ 9900 inputs: []inputInfo{ 9901 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9902 }, 9903 outputs: []outputInfo{ 9904 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9905 }, 9906 }, 9907 }, 9908 { 9909 name: "MOVHUreg", 9910 argLen: 1, 9911 asm: arm.AMOVHU, 9912 reg: regInfo{ 9913 inputs: []inputInfo{ 9914 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9915 }, 9916 outputs: []outputInfo{ 9917 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9918 }, 9919 }, 9920 }, 9921 { 9922 name: "MOVWreg", 9923 argLen: 1, 9924 asm: arm.AMOVW, 9925 reg: regInfo{ 9926 inputs: []inputInfo{ 9927 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9928 }, 9929 outputs: []outputInfo{ 9930 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9931 }, 9932 }, 9933 }, 9934 { 9935 name: "MOVWnop", 9936 argLen: 1, 9937 resultInArg0: true, 9938 reg: regInfo{ 9939 inputs: []inputInfo{ 9940 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9941 }, 9942 outputs: []outputInfo{ 9943 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9944 }, 9945 }, 9946 }, 9947 { 9948 name: "MOVWF", 9949 argLen: 1, 9950 asm: arm.AMOVWF, 9951 reg: regInfo{ 9952 inputs: []inputInfo{ 9953 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9954 }, 9955 outputs: []outputInfo{ 9956 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9957 }, 9958 }, 9959 }, 9960 { 9961 name: "MOVWD", 9962 argLen: 1, 9963 asm: arm.AMOVWD, 9964 reg: regInfo{ 9965 inputs: []inputInfo{ 9966 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9967 }, 9968 outputs: []outputInfo{ 9969 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9970 }, 9971 }, 9972 }, 9973 { 9974 name: "MOVWUF", 9975 argLen: 1, 9976 asm: arm.AMOVWF, 9977 reg: regInfo{ 9978 inputs: []inputInfo{ 9979 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9980 }, 9981 outputs: []outputInfo{ 9982 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9983 }, 9984 }, 9985 }, 9986 { 9987 name: "MOVWUD", 9988 argLen: 1, 9989 asm: arm.AMOVWD, 9990 reg: regInfo{ 9991 inputs: []inputInfo{ 9992 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9993 }, 9994 outputs: []outputInfo{ 9995 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9996 }, 9997 }, 9998 }, 9999 { 10000 name: "MOVFW", 10001 argLen: 1, 10002 asm: arm.AMOVFW, 10003 reg: regInfo{ 10004 inputs: []inputInfo{ 10005 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10006 }, 10007 outputs: []outputInfo{ 10008 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10009 }, 10010 }, 10011 }, 10012 { 10013 name: "MOVDW", 10014 argLen: 1, 10015 asm: arm.AMOVDW, 10016 reg: regInfo{ 10017 inputs: []inputInfo{ 10018 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10019 }, 10020 outputs: []outputInfo{ 10021 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10022 }, 10023 }, 10024 }, 10025 { 10026 name: "MOVFWU", 10027 argLen: 1, 10028 asm: arm.AMOVFW, 10029 reg: regInfo{ 10030 inputs: []inputInfo{ 10031 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10032 }, 10033 outputs: []outputInfo{ 10034 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10035 }, 10036 }, 10037 }, 10038 { 10039 name: "MOVDWU", 10040 argLen: 1, 10041 asm: arm.AMOVDW, 10042 reg: regInfo{ 10043 inputs: []inputInfo{ 10044 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10045 }, 10046 outputs: []outputInfo{ 10047 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10048 }, 10049 }, 10050 }, 10051 { 10052 name: "MOVFD", 10053 argLen: 1, 10054 asm: arm.AMOVFD, 10055 reg: regInfo{ 10056 inputs: []inputInfo{ 10057 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10058 }, 10059 outputs: []outputInfo{ 10060 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10061 }, 10062 }, 10063 }, 10064 { 10065 name: "MOVDF", 10066 argLen: 1, 10067 asm: arm.AMOVDF, 10068 reg: regInfo{ 10069 inputs: []inputInfo{ 10070 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10071 }, 10072 outputs: []outputInfo{ 10073 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10074 }, 10075 }, 10076 }, 10077 { 10078 name: "CMOVWHSconst", 10079 auxType: auxInt32, 10080 argLen: 2, 10081 resultInArg0: true, 10082 asm: arm.AMOVW, 10083 reg: regInfo{ 10084 inputs: []inputInfo{ 10085 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10086 }, 10087 outputs: []outputInfo{ 10088 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10089 }, 10090 }, 10091 }, 10092 { 10093 name: "CMOVWLSconst", 10094 auxType: auxInt32, 10095 argLen: 2, 10096 resultInArg0: true, 10097 asm: arm.AMOVW, 10098 reg: regInfo{ 10099 inputs: []inputInfo{ 10100 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10101 }, 10102 outputs: []outputInfo{ 10103 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10104 }, 10105 }, 10106 }, 10107 { 10108 name: "SRAcond", 10109 argLen: 3, 10110 asm: arm.ASRA, 10111 reg: regInfo{ 10112 inputs: []inputInfo{ 10113 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10114 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10115 }, 10116 outputs: []outputInfo{ 10117 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10118 }, 10119 }, 10120 }, 10121 { 10122 name: "CALLstatic", 10123 auxType: auxSymOff, 10124 argLen: 1, 10125 clobberFlags: true, 10126 call: true, 10127 reg: regInfo{ 10128 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10129 }, 10130 }, 10131 { 10132 name: "CALLclosure", 10133 auxType: auxInt64, 10134 argLen: 3, 10135 clobberFlags: true, 10136 call: true, 10137 reg: regInfo{ 10138 inputs: []inputInfo{ 10139 {1, 128}, // R7 10140 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 10141 }, 10142 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10143 }, 10144 }, 10145 { 10146 name: "CALLdefer", 10147 auxType: auxInt64, 10148 argLen: 1, 10149 clobberFlags: true, 10150 call: true, 10151 reg: regInfo{ 10152 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10153 }, 10154 }, 10155 { 10156 name: "CALLgo", 10157 auxType: auxInt64, 10158 argLen: 1, 10159 clobberFlags: true, 10160 call: true, 10161 reg: regInfo{ 10162 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10163 }, 10164 }, 10165 { 10166 name: "CALLinter", 10167 auxType: auxInt64, 10168 argLen: 2, 10169 clobberFlags: true, 10170 call: true, 10171 reg: regInfo{ 10172 inputs: []inputInfo{ 10173 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10174 }, 10175 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10176 }, 10177 }, 10178 { 10179 name: "LoweredNilCheck", 10180 argLen: 2, 10181 nilCheck: true, 10182 faultOnNilArg0: true, 10183 reg: regInfo{ 10184 inputs: []inputInfo{ 10185 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10186 }, 10187 }, 10188 }, 10189 { 10190 name: "Equal", 10191 argLen: 1, 10192 reg: regInfo{ 10193 outputs: []outputInfo{ 10194 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10195 }, 10196 }, 10197 }, 10198 { 10199 name: "NotEqual", 10200 argLen: 1, 10201 reg: regInfo{ 10202 outputs: []outputInfo{ 10203 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10204 }, 10205 }, 10206 }, 10207 { 10208 name: "LessThan", 10209 argLen: 1, 10210 reg: regInfo{ 10211 outputs: []outputInfo{ 10212 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10213 }, 10214 }, 10215 }, 10216 { 10217 name: "LessEqual", 10218 argLen: 1, 10219 reg: regInfo{ 10220 outputs: []outputInfo{ 10221 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10222 }, 10223 }, 10224 }, 10225 { 10226 name: "GreaterThan", 10227 argLen: 1, 10228 reg: regInfo{ 10229 outputs: []outputInfo{ 10230 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10231 }, 10232 }, 10233 }, 10234 { 10235 name: "GreaterEqual", 10236 argLen: 1, 10237 reg: regInfo{ 10238 outputs: []outputInfo{ 10239 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10240 }, 10241 }, 10242 }, 10243 { 10244 name: "LessThanU", 10245 argLen: 1, 10246 reg: regInfo{ 10247 outputs: []outputInfo{ 10248 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10249 }, 10250 }, 10251 }, 10252 { 10253 name: "LessEqualU", 10254 argLen: 1, 10255 reg: regInfo{ 10256 outputs: []outputInfo{ 10257 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10258 }, 10259 }, 10260 }, 10261 { 10262 name: "GreaterThanU", 10263 argLen: 1, 10264 reg: regInfo{ 10265 outputs: []outputInfo{ 10266 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10267 }, 10268 }, 10269 }, 10270 { 10271 name: "GreaterEqualU", 10272 argLen: 1, 10273 reg: regInfo{ 10274 outputs: []outputInfo{ 10275 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10276 }, 10277 }, 10278 }, 10279 { 10280 name: "DUFFZERO", 10281 auxType: auxInt64, 10282 argLen: 3, 10283 faultOnNilArg0: true, 10284 reg: regInfo{ 10285 inputs: []inputInfo{ 10286 {0, 2}, // R1 10287 {1, 1}, // R0 10288 }, 10289 clobbers: 16386, // R1 R14 10290 }, 10291 }, 10292 { 10293 name: "DUFFCOPY", 10294 auxType: auxInt64, 10295 argLen: 3, 10296 faultOnNilArg0: true, 10297 faultOnNilArg1: true, 10298 reg: regInfo{ 10299 inputs: []inputInfo{ 10300 {0, 4}, // R2 10301 {1, 2}, // R1 10302 }, 10303 clobbers: 16391, // R0 R1 R2 R14 10304 }, 10305 }, 10306 { 10307 name: "LoweredZero", 10308 auxType: auxInt64, 10309 argLen: 4, 10310 clobberFlags: true, 10311 faultOnNilArg0: true, 10312 reg: regInfo{ 10313 inputs: []inputInfo{ 10314 {0, 2}, // R1 10315 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10316 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10317 }, 10318 clobbers: 2, // R1 10319 }, 10320 }, 10321 { 10322 name: "LoweredMove", 10323 auxType: auxInt64, 10324 argLen: 4, 10325 clobberFlags: true, 10326 faultOnNilArg0: true, 10327 faultOnNilArg1: true, 10328 reg: regInfo{ 10329 inputs: []inputInfo{ 10330 {0, 4}, // R2 10331 {1, 2}, // R1 10332 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10333 }, 10334 clobbers: 6, // R1 R2 10335 }, 10336 }, 10337 { 10338 name: "LoweredGetClosurePtr", 10339 argLen: 0, 10340 reg: regInfo{ 10341 outputs: []outputInfo{ 10342 {0, 128}, // R7 10343 }, 10344 }, 10345 }, 10346 { 10347 name: "MOVWconvert", 10348 argLen: 2, 10349 asm: arm.AMOVW, 10350 reg: regInfo{ 10351 inputs: []inputInfo{ 10352 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10353 }, 10354 outputs: []outputInfo{ 10355 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10356 }, 10357 }, 10358 }, 10359 { 10360 name: "FlagEQ", 10361 argLen: 0, 10362 reg: regInfo{}, 10363 }, 10364 { 10365 name: "FlagLT_ULT", 10366 argLen: 0, 10367 reg: regInfo{}, 10368 }, 10369 { 10370 name: "FlagLT_UGT", 10371 argLen: 0, 10372 reg: regInfo{}, 10373 }, 10374 { 10375 name: "FlagGT_UGT", 10376 argLen: 0, 10377 reg: regInfo{}, 10378 }, 10379 { 10380 name: "FlagGT_ULT", 10381 argLen: 0, 10382 reg: regInfo{}, 10383 }, 10384 { 10385 name: "InvertFlags", 10386 argLen: 1, 10387 reg: regInfo{}, 10388 }, 10389 10390 { 10391 name: "ADD", 10392 argLen: 2, 10393 commutative: true, 10394 asm: arm64.AADD, 10395 reg: regInfo{ 10396 inputs: []inputInfo{ 10397 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10398 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10399 }, 10400 outputs: []outputInfo{ 10401 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10402 }, 10403 }, 10404 }, 10405 { 10406 name: "ADDconst", 10407 auxType: auxInt64, 10408 argLen: 1, 10409 asm: arm64.AADD, 10410 reg: regInfo{ 10411 inputs: []inputInfo{ 10412 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 10413 }, 10414 outputs: []outputInfo{ 10415 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10416 }, 10417 }, 10418 }, 10419 { 10420 name: "SUB", 10421 argLen: 2, 10422 asm: arm64.ASUB, 10423 reg: regInfo{ 10424 inputs: []inputInfo{ 10425 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10426 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10427 }, 10428 outputs: []outputInfo{ 10429 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10430 }, 10431 }, 10432 }, 10433 { 10434 name: "SUBconst", 10435 auxType: auxInt64, 10436 argLen: 1, 10437 asm: arm64.ASUB, 10438 reg: regInfo{ 10439 inputs: []inputInfo{ 10440 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10441 }, 10442 outputs: []outputInfo{ 10443 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10444 }, 10445 }, 10446 }, 10447 { 10448 name: "MUL", 10449 argLen: 2, 10450 commutative: true, 10451 asm: arm64.AMUL, 10452 reg: regInfo{ 10453 inputs: []inputInfo{ 10454 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10455 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10456 }, 10457 outputs: []outputInfo{ 10458 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10459 }, 10460 }, 10461 }, 10462 { 10463 name: "MULW", 10464 argLen: 2, 10465 commutative: true, 10466 asm: arm64.AMULW, 10467 reg: regInfo{ 10468 inputs: []inputInfo{ 10469 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10470 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10471 }, 10472 outputs: []outputInfo{ 10473 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10474 }, 10475 }, 10476 }, 10477 { 10478 name: "MULH", 10479 argLen: 2, 10480 commutative: true, 10481 asm: arm64.ASMULH, 10482 reg: regInfo{ 10483 inputs: []inputInfo{ 10484 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10485 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10486 }, 10487 outputs: []outputInfo{ 10488 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10489 }, 10490 }, 10491 }, 10492 { 10493 name: "UMULH", 10494 argLen: 2, 10495 commutative: true, 10496 asm: arm64.AUMULH, 10497 reg: regInfo{ 10498 inputs: []inputInfo{ 10499 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10500 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10501 }, 10502 outputs: []outputInfo{ 10503 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10504 }, 10505 }, 10506 }, 10507 { 10508 name: "MULL", 10509 argLen: 2, 10510 commutative: true, 10511 asm: arm64.ASMULL, 10512 reg: regInfo{ 10513 inputs: []inputInfo{ 10514 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10515 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10516 }, 10517 outputs: []outputInfo{ 10518 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10519 }, 10520 }, 10521 }, 10522 { 10523 name: "UMULL", 10524 argLen: 2, 10525 commutative: true, 10526 asm: arm64.AUMULL, 10527 reg: regInfo{ 10528 inputs: []inputInfo{ 10529 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10530 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10531 }, 10532 outputs: []outputInfo{ 10533 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10534 }, 10535 }, 10536 }, 10537 { 10538 name: "DIV", 10539 argLen: 2, 10540 asm: arm64.ASDIV, 10541 reg: regInfo{ 10542 inputs: []inputInfo{ 10543 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10544 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10545 }, 10546 outputs: []outputInfo{ 10547 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10548 }, 10549 }, 10550 }, 10551 { 10552 name: "UDIV", 10553 argLen: 2, 10554 asm: arm64.AUDIV, 10555 reg: regInfo{ 10556 inputs: []inputInfo{ 10557 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10558 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10559 }, 10560 outputs: []outputInfo{ 10561 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10562 }, 10563 }, 10564 }, 10565 { 10566 name: "DIVW", 10567 argLen: 2, 10568 asm: arm64.ASDIVW, 10569 reg: regInfo{ 10570 inputs: []inputInfo{ 10571 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10572 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10573 }, 10574 outputs: []outputInfo{ 10575 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10576 }, 10577 }, 10578 }, 10579 { 10580 name: "UDIVW", 10581 argLen: 2, 10582 asm: arm64.AUDIVW, 10583 reg: regInfo{ 10584 inputs: []inputInfo{ 10585 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10586 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10587 }, 10588 outputs: []outputInfo{ 10589 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10590 }, 10591 }, 10592 }, 10593 { 10594 name: "MOD", 10595 argLen: 2, 10596 asm: arm64.AREM, 10597 reg: regInfo{ 10598 inputs: []inputInfo{ 10599 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10600 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10601 }, 10602 outputs: []outputInfo{ 10603 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10604 }, 10605 }, 10606 }, 10607 { 10608 name: "UMOD", 10609 argLen: 2, 10610 asm: arm64.AUREM, 10611 reg: regInfo{ 10612 inputs: []inputInfo{ 10613 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10614 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10615 }, 10616 outputs: []outputInfo{ 10617 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10618 }, 10619 }, 10620 }, 10621 { 10622 name: "MODW", 10623 argLen: 2, 10624 asm: arm64.AREMW, 10625 reg: regInfo{ 10626 inputs: []inputInfo{ 10627 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10628 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10629 }, 10630 outputs: []outputInfo{ 10631 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10632 }, 10633 }, 10634 }, 10635 { 10636 name: "UMODW", 10637 argLen: 2, 10638 asm: arm64.AUREMW, 10639 reg: regInfo{ 10640 inputs: []inputInfo{ 10641 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10642 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10643 }, 10644 outputs: []outputInfo{ 10645 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10646 }, 10647 }, 10648 }, 10649 { 10650 name: "FADDS", 10651 argLen: 2, 10652 commutative: true, 10653 asm: arm64.AFADDS, 10654 reg: regInfo{ 10655 inputs: []inputInfo{ 10656 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10657 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10658 }, 10659 outputs: []outputInfo{ 10660 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10661 }, 10662 }, 10663 }, 10664 { 10665 name: "FADDD", 10666 argLen: 2, 10667 commutative: true, 10668 asm: arm64.AFADDD, 10669 reg: regInfo{ 10670 inputs: []inputInfo{ 10671 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10672 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10673 }, 10674 outputs: []outputInfo{ 10675 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10676 }, 10677 }, 10678 }, 10679 { 10680 name: "FSUBS", 10681 argLen: 2, 10682 asm: arm64.AFSUBS, 10683 reg: regInfo{ 10684 inputs: []inputInfo{ 10685 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10686 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10687 }, 10688 outputs: []outputInfo{ 10689 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10690 }, 10691 }, 10692 }, 10693 { 10694 name: "FSUBD", 10695 argLen: 2, 10696 asm: arm64.AFSUBD, 10697 reg: regInfo{ 10698 inputs: []inputInfo{ 10699 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10700 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10701 }, 10702 outputs: []outputInfo{ 10703 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10704 }, 10705 }, 10706 }, 10707 { 10708 name: "FMULS", 10709 argLen: 2, 10710 commutative: true, 10711 asm: arm64.AFMULS, 10712 reg: regInfo{ 10713 inputs: []inputInfo{ 10714 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10715 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10716 }, 10717 outputs: []outputInfo{ 10718 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10719 }, 10720 }, 10721 }, 10722 { 10723 name: "FMULD", 10724 argLen: 2, 10725 commutative: true, 10726 asm: arm64.AFMULD, 10727 reg: regInfo{ 10728 inputs: []inputInfo{ 10729 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10730 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10731 }, 10732 outputs: []outputInfo{ 10733 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10734 }, 10735 }, 10736 }, 10737 { 10738 name: "FDIVS", 10739 argLen: 2, 10740 asm: arm64.AFDIVS, 10741 reg: regInfo{ 10742 inputs: []inputInfo{ 10743 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10744 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10745 }, 10746 outputs: []outputInfo{ 10747 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10748 }, 10749 }, 10750 }, 10751 { 10752 name: "FDIVD", 10753 argLen: 2, 10754 asm: arm64.AFDIVD, 10755 reg: regInfo{ 10756 inputs: []inputInfo{ 10757 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10758 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10759 }, 10760 outputs: []outputInfo{ 10761 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10762 }, 10763 }, 10764 }, 10765 { 10766 name: "AND", 10767 argLen: 2, 10768 commutative: true, 10769 asm: arm64.AAND, 10770 reg: regInfo{ 10771 inputs: []inputInfo{ 10772 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10773 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10774 }, 10775 outputs: []outputInfo{ 10776 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10777 }, 10778 }, 10779 }, 10780 { 10781 name: "ANDconst", 10782 auxType: auxInt64, 10783 argLen: 1, 10784 asm: arm64.AAND, 10785 reg: regInfo{ 10786 inputs: []inputInfo{ 10787 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10788 }, 10789 outputs: []outputInfo{ 10790 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10791 }, 10792 }, 10793 }, 10794 { 10795 name: "OR", 10796 argLen: 2, 10797 commutative: true, 10798 asm: arm64.AORR, 10799 reg: regInfo{ 10800 inputs: []inputInfo{ 10801 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10802 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10803 }, 10804 outputs: []outputInfo{ 10805 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10806 }, 10807 }, 10808 }, 10809 { 10810 name: "ORconst", 10811 auxType: auxInt64, 10812 argLen: 1, 10813 asm: arm64.AORR, 10814 reg: regInfo{ 10815 inputs: []inputInfo{ 10816 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10817 }, 10818 outputs: []outputInfo{ 10819 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10820 }, 10821 }, 10822 }, 10823 { 10824 name: "XOR", 10825 argLen: 2, 10826 commutative: true, 10827 asm: arm64.AEOR, 10828 reg: regInfo{ 10829 inputs: []inputInfo{ 10830 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10831 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10832 }, 10833 outputs: []outputInfo{ 10834 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10835 }, 10836 }, 10837 }, 10838 { 10839 name: "XORconst", 10840 auxType: auxInt64, 10841 argLen: 1, 10842 asm: arm64.AEOR, 10843 reg: regInfo{ 10844 inputs: []inputInfo{ 10845 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10846 }, 10847 outputs: []outputInfo{ 10848 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10849 }, 10850 }, 10851 }, 10852 { 10853 name: "BIC", 10854 argLen: 2, 10855 asm: arm64.ABIC, 10856 reg: regInfo{ 10857 inputs: []inputInfo{ 10858 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10859 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10860 }, 10861 outputs: []outputInfo{ 10862 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10863 }, 10864 }, 10865 }, 10866 { 10867 name: "BICconst", 10868 auxType: auxInt64, 10869 argLen: 1, 10870 asm: arm64.ABIC, 10871 reg: regInfo{ 10872 inputs: []inputInfo{ 10873 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10874 }, 10875 outputs: []outputInfo{ 10876 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10877 }, 10878 }, 10879 }, 10880 { 10881 name: "MVN", 10882 argLen: 1, 10883 asm: arm64.AMVN, 10884 reg: regInfo{ 10885 inputs: []inputInfo{ 10886 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10887 }, 10888 outputs: []outputInfo{ 10889 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10890 }, 10891 }, 10892 }, 10893 { 10894 name: "NEG", 10895 argLen: 1, 10896 asm: arm64.ANEG, 10897 reg: regInfo{ 10898 inputs: []inputInfo{ 10899 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10900 }, 10901 outputs: []outputInfo{ 10902 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10903 }, 10904 }, 10905 }, 10906 { 10907 name: "FNEGS", 10908 argLen: 1, 10909 asm: arm64.AFNEGS, 10910 reg: regInfo{ 10911 inputs: []inputInfo{ 10912 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10913 }, 10914 outputs: []outputInfo{ 10915 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10916 }, 10917 }, 10918 }, 10919 { 10920 name: "FNEGD", 10921 argLen: 1, 10922 asm: arm64.AFNEGD, 10923 reg: regInfo{ 10924 inputs: []inputInfo{ 10925 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10926 }, 10927 outputs: []outputInfo{ 10928 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10929 }, 10930 }, 10931 }, 10932 { 10933 name: "FSQRTD", 10934 argLen: 1, 10935 asm: arm64.AFSQRTD, 10936 reg: regInfo{ 10937 inputs: []inputInfo{ 10938 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10939 }, 10940 outputs: []outputInfo{ 10941 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10942 }, 10943 }, 10944 }, 10945 { 10946 name: "REV", 10947 argLen: 1, 10948 asm: arm64.AREV, 10949 reg: regInfo{ 10950 inputs: []inputInfo{ 10951 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10952 }, 10953 outputs: []outputInfo{ 10954 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10955 }, 10956 }, 10957 }, 10958 { 10959 name: "REVW", 10960 argLen: 1, 10961 asm: arm64.AREVW, 10962 reg: regInfo{ 10963 inputs: []inputInfo{ 10964 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10965 }, 10966 outputs: []outputInfo{ 10967 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10968 }, 10969 }, 10970 }, 10971 { 10972 name: "REV16W", 10973 argLen: 1, 10974 asm: arm64.AREV16W, 10975 reg: regInfo{ 10976 inputs: []inputInfo{ 10977 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10978 }, 10979 outputs: []outputInfo{ 10980 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10981 }, 10982 }, 10983 }, 10984 { 10985 name: "RBIT", 10986 argLen: 1, 10987 asm: arm64.ARBIT, 10988 reg: regInfo{ 10989 inputs: []inputInfo{ 10990 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10991 }, 10992 outputs: []outputInfo{ 10993 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10994 }, 10995 }, 10996 }, 10997 { 10998 name: "RBITW", 10999 argLen: 1, 11000 asm: arm64.ARBITW, 11001 reg: regInfo{ 11002 inputs: []inputInfo{ 11003 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11004 }, 11005 outputs: []outputInfo{ 11006 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11007 }, 11008 }, 11009 }, 11010 { 11011 name: "CLZ", 11012 argLen: 1, 11013 asm: arm64.ACLZ, 11014 reg: regInfo{ 11015 inputs: []inputInfo{ 11016 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11017 }, 11018 outputs: []outputInfo{ 11019 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11020 }, 11021 }, 11022 }, 11023 { 11024 name: "CLZW", 11025 argLen: 1, 11026 asm: arm64.ACLZW, 11027 reg: regInfo{ 11028 inputs: []inputInfo{ 11029 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11030 }, 11031 outputs: []outputInfo{ 11032 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11033 }, 11034 }, 11035 }, 11036 { 11037 name: "SLL", 11038 argLen: 2, 11039 asm: arm64.ALSL, 11040 reg: regInfo{ 11041 inputs: []inputInfo{ 11042 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11043 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11044 }, 11045 outputs: []outputInfo{ 11046 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11047 }, 11048 }, 11049 }, 11050 { 11051 name: "SLLconst", 11052 auxType: auxInt64, 11053 argLen: 1, 11054 asm: arm64.ALSL, 11055 reg: regInfo{ 11056 inputs: []inputInfo{ 11057 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11058 }, 11059 outputs: []outputInfo{ 11060 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11061 }, 11062 }, 11063 }, 11064 { 11065 name: "SRL", 11066 argLen: 2, 11067 asm: arm64.ALSR, 11068 reg: regInfo{ 11069 inputs: []inputInfo{ 11070 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11071 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11072 }, 11073 outputs: []outputInfo{ 11074 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11075 }, 11076 }, 11077 }, 11078 { 11079 name: "SRLconst", 11080 auxType: auxInt64, 11081 argLen: 1, 11082 asm: arm64.ALSR, 11083 reg: regInfo{ 11084 inputs: []inputInfo{ 11085 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11086 }, 11087 outputs: []outputInfo{ 11088 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11089 }, 11090 }, 11091 }, 11092 { 11093 name: "SRA", 11094 argLen: 2, 11095 asm: arm64.AASR, 11096 reg: regInfo{ 11097 inputs: []inputInfo{ 11098 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11099 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11100 }, 11101 outputs: []outputInfo{ 11102 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11103 }, 11104 }, 11105 }, 11106 { 11107 name: "SRAconst", 11108 auxType: auxInt64, 11109 argLen: 1, 11110 asm: arm64.AASR, 11111 reg: regInfo{ 11112 inputs: []inputInfo{ 11113 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11114 }, 11115 outputs: []outputInfo{ 11116 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11117 }, 11118 }, 11119 }, 11120 { 11121 name: "RORconst", 11122 auxType: auxInt64, 11123 argLen: 1, 11124 asm: arm64.AROR, 11125 reg: regInfo{ 11126 inputs: []inputInfo{ 11127 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11128 }, 11129 outputs: []outputInfo{ 11130 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11131 }, 11132 }, 11133 }, 11134 { 11135 name: "RORWconst", 11136 auxType: auxInt64, 11137 argLen: 1, 11138 asm: arm64.ARORW, 11139 reg: regInfo{ 11140 inputs: []inputInfo{ 11141 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11142 }, 11143 outputs: []outputInfo{ 11144 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11145 }, 11146 }, 11147 }, 11148 { 11149 name: "CMP", 11150 argLen: 2, 11151 asm: arm64.ACMP, 11152 reg: regInfo{ 11153 inputs: []inputInfo{ 11154 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11155 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11156 }, 11157 }, 11158 }, 11159 { 11160 name: "CMPconst", 11161 auxType: auxInt64, 11162 argLen: 1, 11163 asm: arm64.ACMP, 11164 reg: regInfo{ 11165 inputs: []inputInfo{ 11166 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11167 }, 11168 }, 11169 }, 11170 { 11171 name: "CMPW", 11172 argLen: 2, 11173 asm: arm64.ACMPW, 11174 reg: regInfo{ 11175 inputs: []inputInfo{ 11176 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11177 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11178 }, 11179 }, 11180 }, 11181 { 11182 name: "CMPWconst", 11183 auxType: auxInt32, 11184 argLen: 1, 11185 asm: arm64.ACMPW, 11186 reg: regInfo{ 11187 inputs: []inputInfo{ 11188 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11189 }, 11190 }, 11191 }, 11192 { 11193 name: "CMN", 11194 argLen: 2, 11195 asm: arm64.ACMN, 11196 reg: regInfo{ 11197 inputs: []inputInfo{ 11198 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11199 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11200 }, 11201 }, 11202 }, 11203 { 11204 name: "CMNconst", 11205 auxType: auxInt64, 11206 argLen: 1, 11207 asm: arm64.ACMN, 11208 reg: regInfo{ 11209 inputs: []inputInfo{ 11210 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11211 }, 11212 }, 11213 }, 11214 { 11215 name: "CMNW", 11216 argLen: 2, 11217 asm: arm64.ACMNW, 11218 reg: regInfo{ 11219 inputs: []inputInfo{ 11220 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11221 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11222 }, 11223 }, 11224 }, 11225 { 11226 name: "CMNWconst", 11227 auxType: auxInt32, 11228 argLen: 1, 11229 asm: arm64.ACMNW, 11230 reg: regInfo{ 11231 inputs: []inputInfo{ 11232 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11233 }, 11234 }, 11235 }, 11236 { 11237 name: "FCMPS", 11238 argLen: 2, 11239 asm: arm64.AFCMPS, 11240 reg: regInfo{ 11241 inputs: []inputInfo{ 11242 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11243 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11244 }, 11245 }, 11246 }, 11247 { 11248 name: "FCMPD", 11249 argLen: 2, 11250 asm: arm64.AFCMPD, 11251 reg: regInfo{ 11252 inputs: []inputInfo{ 11253 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11254 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11255 }, 11256 }, 11257 }, 11258 { 11259 name: "ADDshiftLL", 11260 auxType: auxInt64, 11261 argLen: 2, 11262 asm: arm64.AADD, 11263 reg: regInfo{ 11264 inputs: []inputInfo{ 11265 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11266 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11267 }, 11268 outputs: []outputInfo{ 11269 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11270 }, 11271 }, 11272 }, 11273 { 11274 name: "ADDshiftRL", 11275 auxType: auxInt64, 11276 argLen: 2, 11277 asm: arm64.AADD, 11278 reg: regInfo{ 11279 inputs: []inputInfo{ 11280 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11281 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11282 }, 11283 outputs: []outputInfo{ 11284 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11285 }, 11286 }, 11287 }, 11288 { 11289 name: "ADDshiftRA", 11290 auxType: auxInt64, 11291 argLen: 2, 11292 asm: arm64.AADD, 11293 reg: regInfo{ 11294 inputs: []inputInfo{ 11295 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11296 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11297 }, 11298 outputs: []outputInfo{ 11299 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11300 }, 11301 }, 11302 }, 11303 { 11304 name: "SUBshiftLL", 11305 auxType: auxInt64, 11306 argLen: 2, 11307 asm: arm64.ASUB, 11308 reg: regInfo{ 11309 inputs: []inputInfo{ 11310 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11311 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11312 }, 11313 outputs: []outputInfo{ 11314 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11315 }, 11316 }, 11317 }, 11318 { 11319 name: "SUBshiftRL", 11320 auxType: auxInt64, 11321 argLen: 2, 11322 asm: arm64.ASUB, 11323 reg: regInfo{ 11324 inputs: []inputInfo{ 11325 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11326 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11327 }, 11328 outputs: []outputInfo{ 11329 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11330 }, 11331 }, 11332 }, 11333 { 11334 name: "SUBshiftRA", 11335 auxType: auxInt64, 11336 argLen: 2, 11337 asm: arm64.ASUB, 11338 reg: regInfo{ 11339 inputs: []inputInfo{ 11340 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11341 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11342 }, 11343 outputs: []outputInfo{ 11344 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11345 }, 11346 }, 11347 }, 11348 { 11349 name: "ANDshiftLL", 11350 auxType: auxInt64, 11351 argLen: 2, 11352 asm: arm64.AAND, 11353 reg: regInfo{ 11354 inputs: []inputInfo{ 11355 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11356 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11357 }, 11358 outputs: []outputInfo{ 11359 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11360 }, 11361 }, 11362 }, 11363 { 11364 name: "ANDshiftRL", 11365 auxType: auxInt64, 11366 argLen: 2, 11367 asm: arm64.AAND, 11368 reg: regInfo{ 11369 inputs: []inputInfo{ 11370 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11371 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11372 }, 11373 outputs: []outputInfo{ 11374 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11375 }, 11376 }, 11377 }, 11378 { 11379 name: "ANDshiftRA", 11380 auxType: auxInt64, 11381 argLen: 2, 11382 asm: arm64.AAND, 11383 reg: regInfo{ 11384 inputs: []inputInfo{ 11385 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11386 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11387 }, 11388 outputs: []outputInfo{ 11389 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11390 }, 11391 }, 11392 }, 11393 { 11394 name: "ORshiftLL", 11395 auxType: auxInt64, 11396 argLen: 2, 11397 asm: arm64.AORR, 11398 reg: regInfo{ 11399 inputs: []inputInfo{ 11400 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11401 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11402 }, 11403 outputs: []outputInfo{ 11404 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11405 }, 11406 }, 11407 }, 11408 { 11409 name: "ORshiftRL", 11410 auxType: auxInt64, 11411 argLen: 2, 11412 asm: arm64.AORR, 11413 reg: regInfo{ 11414 inputs: []inputInfo{ 11415 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11416 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11417 }, 11418 outputs: []outputInfo{ 11419 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11420 }, 11421 }, 11422 }, 11423 { 11424 name: "ORshiftRA", 11425 auxType: auxInt64, 11426 argLen: 2, 11427 asm: arm64.AORR, 11428 reg: regInfo{ 11429 inputs: []inputInfo{ 11430 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11431 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11432 }, 11433 outputs: []outputInfo{ 11434 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11435 }, 11436 }, 11437 }, 11438 { 11439 name: "XORshiftLL", 11440 auxType: auxInt64, 11441 argLen: 2, 11442 asm: arm64.AEOR, 11443 reg: regInfo{ 11444 inputs: []inputInfo{ 11445 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11446 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11447 }, 11448 outputs: []outputInfo{ 11449 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11450 }, 11451 }, 11452 }, 11453 { 11454 name: "XORshiftRL", 11455 auxType: auxInt64, 11456 argLen: 2, 11457 asm: arm64.AEOR, 11458 reg: regInfo{ 11459 inputs: []inputInfo{ 11460 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11461 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11462 }, 11463 outputs: []outputInfo{ 11464 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11465 }, 11466 }, 11467 }, 11468 { 11469 name: "XORshiftRA", 11470 auxType: auxInt64, 11471 argLen: 2, 11472 asm: arm64.AEOR, 11473 reg: regInfo{ 11474 inputs: []inputInfo{ 11475 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11476 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11477 }, 11478 outputs: []outputInfo{ 11479 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11480 }, 11481 }, 11482 }, 11483 { 11484 name: "BICshiftLL", 11485 auxType: auxInt64, 11486 argLen: 2, 11487 asm: arm64.ABIC, 11488 reg: regInfo{ 11489 inputs: []inputInfo{ 11490 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11491 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11492 }, 11493 outputs: []outputInfo{ 11494 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11495 }, 11496 }, 11497 }, 11498 { 11499 name: "BICshiftRL", 11500 auxType: auxInt64, 11501 argLen: 2, 11502 asm: arm64.ABIC, 11503 reg: regInfo{ 11504 inputs: []inputInfo{ 11505 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11506 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11507 }, 11508 outputs: []outputInfo{ 11509 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11510 }, 11511 }, 11512 }, 11513 { 11514 name: "BICshiftRA", 11515 auxType: auxInt64, 11516 argLen: 2, 11517 asm: arm64.ABIC, 11518 reg: regInfo{ 11519 inputs: []inputInfo{ 11520 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11521 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11522 }, 11523 outputs: []outputInfo{ 11524 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11525 }, 11526 }, 11527 }, 11528 { 11529 name: "CMPshiftLL", 11530 auxType: auxInt64, 11531 argLen: 2, 11532 asm: arm64.ACMP, 11533 reg: regInfo{ 11534 inputs: []inputInfo{ 11535 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11536 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11537 }, 11538 }, 11539 }, 11540 { 11541 name: "CMPshiftRL", 11542 auxType: auxInt64, 11543 argLen: 2, 11544 asm: arm64.ACMP, 11545 reg: regInfo{ 11546 inputs: []inputInfo{ 11547 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11548 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11549 }, 11550 }, 11551 }, 11552 { 11553 name: "CMPshiftRA", 11554 auxType: auxInt64, 11555 argLen: 2, 11556 asm: arm64.ACMP, 11557 reg: regInfo{ 11558 inputs: []inputInfo{ 11559 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11560 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11561 }, 11562 }, 11563 }, 11564 { 11565 name: "MOVDconst", 11566 auxType: auxInt64, 11567 argLen: 0, 11568 rematerializeable: true, 11569 asm: arm64.AMOVD, 11570 reg: regInfo{ 11571 outputs: []outputInfo{ 11572 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11573 }, 11574 }, 11575 }, 11576 { 11577 name: "FMOVSconst", 11578 auxType: auxFloat64, 11579 argLen: 0, 11580 rematerializeable: true, 11581 asm: arm64.AFMOVS, 11582 reg: regInfo{ 11583 outputs: []outputInfo{ 11584 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11585 }, 11586 }, 11587 }, 11588 { 11589 name: "FMOVDconst", 11590 auxType: auxFloat64, 11591 argLen: 0, 11592 rematerializeable: true, 11593 asm: arm64.AFMOVD, 11594 reg: regInfo{ 11595 outputs: []outputInfo{ 11596 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11597 }, 11598 }, 11599 }, 11600 { 11601 name: "MOVDaddr", 11602 auxType: auxSymOff, 11603 argLen: 1, 11604 rematerializeable: true, 11605 asm: arm64.AMOVD, 11606 reg: regInfo{ 11607 inputs: []inputInfo{ 11608 {0, 9223372037928517632}, // SP SB 11609 }, 11610 outputs: []outputInfo{ 11611 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11612 }, 11613 }, 11614 }, 11615 { 11616 name: "MOVBload", 11617 auxType: auxSymOff, 11618 argLen: 2, 11619 faultOnNilArg0: true, 11620 asm: arm64.AMOVB, 11621 reg: regInfo{ 11622 inputs: []inputInfo{ 11623 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11624 }, 11625 outputs: []outputInfo{ 11626 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11627 }, 11628 }, 11629 }, 11630 { 11631 name: "MOVBUload", 11632 auxType: auxSymOff, 11633 argLen: 2, 11634 faultOnNilArg0: true, 11635 asm: arm64.AMOVBU, 11636 reg: regInfo{ 11637 inputs: []inputInfo{ 11638 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11639 }, 11640 outputs: []outputInfo{ 11641 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11642 }, 11643 }, 11644 }, 11645 { 11646 name: "MOVHload", 11647 auxType: auxSymOff, 11648 argLen: 2, 11649 faultOnNilArg0: true, 11650 asm: arm64.AMOVH, 11651 reg: regInfo{ 11652 inputs: []inputInfo{ 11653 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11654 }, 11655 outputs: []outputInfo{ 11656 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11657 }, 11658 }, 11659 }, 11660 { 11661 name: "MOVHUload", 11662 auxType: auxSymOff, 11663 argLen: 2, 11664 faultOnNilArg0: true, 11665 asm: arm64.AMOVHU, 11666 reg: regInfo{ 11667 inputs: []inputInfo{ 11668 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11669 }, 11670 outputs: []outputInfo{ 11671 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11672 }, 11673 }, 11674 }, 11675 { 11676 name: "MOVWload", 11677 auxType: auxSymOff, 11678 argLen: 2, 11679 faultOnNilArg0: true, 11680 asm: arm64.AMOVW, 11681 reg: regInfo{ 11682 inputs: []inputInfo{ 11683 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11684 }, 11685 outputs: []outputInfo{ 11686 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11687 }, 11688 }, 11689 }, 11690 { 11691 name: "MOVWUload", 11692 auxType: auxSymOff, 11693 argLen: 2, 11694 faultOnNilArg0: true, 11695 asm: arm64.AMOVWU, 11696 reg: regInfo{ 11697 inputs: []inputInfo{ 11698 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11699 }, 11700 outputs: []outputInfo{ 11701 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11702 }, 11703 }, 11704 }, 11705 { 11706 name: "MOVDload", 11707 auxType: auxSymOff, 11708 argLen: 2, 11709 faultOnNilArg0: true, 11710 asm: arm64.AMOVD, 11711 reg: regInfo{ 11712 inputs: []inputInfo{ 11713 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11714 }, 11715 outputs: []outputInfo{ 11716 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11717 }, 11718 }, 11719 }, 11720 { 11721 name: "FMOVSload", 11722 auxType: auxSymOff, 11723 argLen: 2, 11724 faultOnNilArg0: true, 11725 asm: arm64.AFMOVS, 11726 reg: regInfo{ 11727 inputs: []inputInfo{ 11728 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11729 }, 11730 outputs: []outputInfo{ 11731 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11732 }, 11733 }, 11734 }, 11735 { 11736 name: "FMOVDload", 11737 auxType: auxSymOff, 11738 argLen: 2, 11739 faultOnNilArg0: true, 11740 asm: arm64.AFMOVD, 11741 reg: regInfo{ 11742 inputs: []inputInfo{ 11743 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11744 }, 11745 outputs: []outputInfo{ 11746 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11747 }, 11748 }, 11749 }, 11750 { 11751 name: "MOVBstore", 11752 auxType: auxSymOff, 11753 argLen: 3, 11754 faultOnNilArg0: true, 11755 asm: arm64.AMOVB, 11756 reg: regInfo{ 11757 inputs: []inputInfo{ 11758 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11759 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11760 }, 11761 }, 11762 }, 11763 { 11764 name: "MOVHstore", 11765 auxType: auxSymOff, 11766 argLen: 3, 11767 faultOnNilArg0: true, 11768 asm: arm64.AMOVH, 11769 reg: regInfo{ 11770 inputs: []inputInfo{ 11771 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11772 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11773 }, 11774 }, 11775 }, 11776 { 11777 name: "MOVWstore", 11778 auxType: auxSymOff, 11779 argLen: 3, 11780 faultOnNilArg0: true, 11781 asm: arm64.AMOVW, 11782 reg: regInfo{ 11783 inputs: []inputInfo{ 11784 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11785 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11786 }, 11787 }, 11788 }, 11789 { 11790 name: "MOVDstore", 11791 auxType: auxSymOff, 11792 argLen: 3, 11793 faultOnNilArg0: true, 11794 asm: arm64.AMOVD, 11795 reg: regInfo{ 11796 inputs: []inputInfo{ 11797 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11798 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11799 }, 11800 }, 11801 }, 11802 { 11803 name: "FMOVSstore", 11804 auxType: auxSymOff, 11805 argLen: 3, 11806 faultOnNilArg0: true, 11807 asm: arm64.AFMOVS, 11808 reg: regInfo{ 11809 inputs: []inputInfo{ 11810 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11811 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11812 }, 11813 }, 11814 }, 11815 { 11816 name: "FMOVDstore", 11817 auxType: auxSymOff, 11818 argLen: 3, 11819 faultOnNilArg0: true, 11820 asm: arm64.AFMOVD, 11821 reg: regInfo{ 11822 inputs: []inputInfo{ 11823 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11824 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11825 }, 11826 }, 11827 }, 11828 { 11829 name: "MOVBstorezero", 11830 auxType: auxSymOff, 11831 argLen: 2, 11832 faultOnNilArg0: true, 11833 asm: arm64.AMOVB, 11834 reg: regInfo{ 11835 inputs: []inputInfo{ 11836 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11837 }, 11838 }, 11839 }, 11840 { 11841 name: "MOVHstorezero", 11842 auxType: auxSymOff, 11843 argLen: 2, 11844 faultOnNilArg0: true, 11845 asm: arm64.AMOVH, 11846 reg: regInfo{ 11847 inputs: []inputInfo{ 11848 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11849 }, 11850 }, 11851 }, 11852 { 11853 name: "MOVWstorezero", 11854 auxType: auxSymOff, 11855 argLen: 2, 11856 faultOnNilArg0: true, 11857 asm: arm64.AMOVW, 11858 reg: regInfo{ 11859 inputs: []inputInfo{ 11860 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11861 }, 11862 }, 11863 }, 11864 { 11865 name: "MOVDstorezero", 11866 auxType: auxSymOff, 11867 argLen: 2, 11868 faultOnNilArg0: true, 11869 asm: arm64.AMOVD, 11870 reg: regInfo{ 11871 inputs: []inputInfo{ 11872 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11873 }, 11874 }, 11875 }, 11876 { 11877 name: "MOVBreg", 11878 argLen: 1, 11879 asm: arm64.AMOVB, 11880 reg: regInfo{ 11881 inputs: []inputInfo{ 11882 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11883 }, 11884 outputs: []outputInfo{ 11885 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11886 }, 11887 }, 11888 }, 11889 { 11890 name: "MOVBUreg", 11891 argLen: 1, 11892 asm: arm64.AMOVBU, 11893 reg: regInfo{ 11894 inputs: []inputInfo{ 11895 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11896 }, 11897 outputs: []outputInfo{ 11898 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11899 }, 11900 }, 11901 }, 11902 { 11903 name: "MOVHreg", 11904 argLen: 1, 11905 asm: arm64.AMOVH, 11906 reg: regInfo{ 11907 inputs: []inputInfo{ 11908 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11909 }, 11910 outputs: []outputInfo{ 11911 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11912 }, 11913 }, 11914 }, 11915 { 11916 name: "MOVHUreg", 11917 argLen: 1, 11918 asm: arm64.AMOVHU, 11919 reg: regInfo{ 11920 inputs: []inputInfo{ 11921 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11922 }, 11923 outputs: []outputInfo{ 11924 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11925 }, 11926 }, 11927 }, 11928 { 11929 name: "MOVWreg", 11930 argLen: 1, 11931 asm: arm64.AMOVW, 11932 reg: regInfo{ 11933 inputs: []inputInfo{ 11934 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11935 }, 11936 outputs: []outputInfo{ 11937 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11938 }, 11939 }, 11940 }, 11941 { 11942 name: "MOVWUreg", 11943 argLen: 1, 11944 asm: arm64.AMOVWU, 11945 reg: regInfo{ 11946 inputs: []inputInfo{ 11947 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11948 }, 11949 outputs: []outputInfo{ 11950 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11951 }, 11952 }, 11953 }, 11954 { 11955 name: "MOVDreg", 11956 argLen: 1, 11957 asm: arm64.AMOVD, 11958 reg: regInfo{ 11959 inputs: []inputInfo{ 11960 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11961 }, 11962 outputs: []outputInfo{ 11963 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11964 }, 11965 }, 11966 }, 11967 { 11968 name: "MOVDnop", 11969 argLen: 1, 11970 resultInArg0: true, 11971 reg: regInfo{ 11972 inputs: []inputInfo{ 11973 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11974 }, 11975 outputs: []outputInfo{ 11976 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11977 }, 11978 }, 11979 }, 11980 { 11981 name: "SCVTFWS", 11982 argLen: 1, 11983 asm: arm64.ASCVTFWS, 11984 reg: regInfo{ 11985 inputs: []inputInfo{ 11986 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11987 }, 11988 outputs: []outputInfo{ 11989 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11990 }, 11991 }, 11992 }, 11993 { 11994 name: "SCVTFWD", 11995 argLen: 1, 11996 asm: arm64.ASCVTFWD, 11997 reg: regInfo{ 11998 inputs: []inputInfo{ 11999 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12000 }, 12001 outputs: []outputInfo{ 12002 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12003 }, 12004 }, 12005 }, 12006 { 12007 name: "UCVTFWS", 12008 argLen: 1, 12009 asm: arm64.AUCVTFWS, 12010 reg: regInfo{ 12011 inputs: []inputInfo{ 12012 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12013 }, 12014 outputs: []outputInfo{ 12015 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12016 }, 12017 }, 12018 }, 12019 { 12020 name: "UCVTFWD", 12021 argLen: 1, 12022 asm: arm64.AUCVTFWD, 12023 reg: regInfo{ 12024 inputs: []inputInfo{ 12025 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12026 }, 12027 outputs: []outputInfo{ 12028 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12029 }, 12030 }, 12031 }, 12032 { 12033 name: "SCVTFS", 12034 argLen: 1, 12035 asm: arm64.ASCVTFS, 12036 reg: regInfo{ 12037 inputs: []inputInfo{ 12038 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12039 }, 12040 outputs: []outputInfo{ 12041 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12042 }, 12043 }, 12044 }, 12045 { 12046 name: "SCVTFD", 12047 argLen: 1, 12048 asm: arm64.ASCVTFD, 12049 reg: regInfo{ 12050 inputs: []inputInfo{ 12051 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12052 }, 12053 outputs: []outputInfo{ 12054 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12055 }, 12056 }, 12057 }, 12058 { 12059 name: "UCVTFS", 12060 argLen: 1, 12061 asm: arm64.AUCVTFS, 12062 reg: regInfo{ 12063 inputs: []inputInfo{ 12064 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12065 }, 12066 outputs: []outputInfo{ 12067 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12068 }, 12069 }, 12070 }, 12071 { 12072 name: "UCVTFD", 12073 argLen: 1, 12074 asm: arm64.AUCVTFD, 12075 reg: regInfo{ 12076 inputs: []inputInfo{ 12077 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12078 }, 12079 outputs: []outputInfo{ 12080 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12081 }, 12082 }, 12083 }, 12084 { 12085 name: "FCVTZSSW", 12086 argLen: 1, 12087 asm: arm64.AFCVTZSSW, 12088 reg: regInfo{ 12089 inputs: []inputInfo{ 12090 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12091 }, 12092 outputs: []outputInfo{ 12093 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12094 }, 12095 }, 12096 }, 12097 { 12098 name: "FCVTZSDW", 12099 argLen: 1, 12100 asm: arm64.AFCVTZSDW, 12101 reg: regInfo{ 12102 inputs: []inputInfo{ 12103 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12104 }, 12105 outputs: []outputInfo{ 12106 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12107 }, 12108 }, 12109 }, 12110 { 12111 name: "FCVTZUSW", 12112 argLen: 1, 12113 asm: arm64.AFCVTZUSW, 12114 reg: regInfo{ 12115 inputs: []inputInfo{ 12116 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12117 }, 12118 outputs: []outputInfo{ 12119 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12120 }, 12121 }, 12122 }, 12123 { 12124 name: "FCVTZUDW", 12125 argLen: 1, 12126 asm: arm64.AFCVTZUDW, 12127 reg: regInfo{ 12128 inputs: []inputInfo{ 12129 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12130 }, 12131 outputs: []outputInfo{ 12132 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12133 }, 12134 }, 12135 }, 12136 { 12137 name: "FCVTZSS", 12138 argLen: 1, 12139 asm: arm64.AFCVTZSS, 12140 reg: regInfo{ 12141 inputs: []inputInfo{ 12142 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12143 }, 12144 outputs: []outputInfo{ 12145 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12146 }, 12147 }, 12148 }, 12149 { 12150 name: "FCVTZSD", 12151 argLen: 1, 12152 asm: arm64.AFCVTZSD, 12153 reg: regInfo{ 12154 inputs: []inputInfo{ 12155 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12156 }, 12157 outputs: []outputInfo{ 12158 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12159 }, 12160 }, 12161 }, 12162 { 12163 name: "FCVTZUS", 12164 argLen: 1, 12165 asm: arm64.AFCVTZUS, 12166 reg: regInfo{ 12167 inputs: []inputInfo{ 12168 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12169 }, 12170 outputs: []outputInfo{ 12171 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12172 }, 12173 }, 12174 }, 12175 { 12176 name: "FCVTZUD", 12177 argLen: 1, 12178 asm: arm64.AFCVTZUD, 12179 reg: regInfo{ 12180 inputs: []inputInfo{ 12181 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12182 }, 12183 outputs: []outputInfo{ 12184 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12185 }, 12186 }, 12187 }, 12188 { 12189 name: "FCVTSD", 12190 argLen: 1, 12191 asm: arm64.AFCVTSD, 12192 reg: regInfo{ 12193 inputs: []inputInfo{ 12194 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12195 }, 12196 outputs: []outputInfo{ 12197 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12198 }, 12199 }, 12200 }, 12201 { 12202 name: "FCVTDS", 12203 argLen: 1, 12204 asm: arm64.AFCVTDS, 12205 reg: regInfo{ 12206 inputs: []inputInfo{ 12207 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12208 }, 12209 outputs: []outputInfo{ 12210 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12211 }, 12212 }, 12213 }, 12214 { 12215 name: "CSELULT", 12216 argLen: 3, 12217 asm: arm64.ACSEL, 12218 reg: regInfo{ 12219 inputs: []inputInfo{ 12220 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12221 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12222 }, 12223 outputs: []outputInfo{ 12224 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12225 }, 12226 }, 12227 }, 12228 { 12229 name: "CSELULT0", 12230 argLen: 2, 12231 asm: arm64.ACSEL, 12232 reg: regInfo{ 12233 inputs: []inputInfo{ 12234 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12235 }, 12236 outputs: []outputInfo{ 12237 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12238 }, 12239 }, 12240 }, 12241 { 12242 name: "CALLstatic", 12243 auxType: auxSymOff, 12244 argLen: 1, 12245 clobberFlags: true, 12246 call: true, 12247 reg: regInfo{ 12248 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12249 }, 12250 }, 12251 { 12252 name: "CALLclosure", 12253 auxType: auxInt64, 12254 argLen: 3, 12255 clobberFlags: true, 12256 call: true, 12257 reg: regInfo{ 12258 inputs: []inputInfo{ 12259 {1, 67108864}, // R26 12260 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 12261 }, 12262 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12263 }, 12264 }, 12265 { 12266 name: "CALLdefer", 12267 auxType: auxInt64, 12268 argLen: 1, 12269 clobberFlags: true, 12270 call: true, 12271 reg: regInfo{ 12272 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12273 }, 12274 }, 12275 { 12276 name: "CALLgo", 12277 auxType: auxInt64, 12278 argLen: 1, 12279 clobberFlags: true, 12280 call: true, 12281 reg: regInfo{ 12282 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12283 }, 12284 }, 12285 { 12286 name: "CALLinter", 12287 auxType: auxInt64, 12288 argLen: 2, 12289 clobberFlags: true, 12290 call: true, 12291 reg: regInfo{ 12292 inputs: []inputInfo{ 12293 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12294 }, 12295 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12296 }, 12297 }, 12298 { 12299 name: "LoweredNilCheck", 12300 argLen: 2, 12301 nilCheck: true, 12302 faultOnNilArg0: true, 12303 reg: regInfo{ 12304 inputs: []inputInfo{ 12305 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12306 }, 12307 }, 12308 }, 12309 { 12310 name: "Equal", 12311 argLen: 1, 12312 reg: regInfo{ 12313 outputs: []outputInfo{ 12314 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12315 }, 12316 }, 12317 }, 12318 { 12319 name: "NotEqual", 12320 argLen: 1, 12321 reg: regInfo{ 12322 outputs: []outputInfo{ 12323 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12324 }, 12325 }, 12326 }, 12327 { 12328 name: "LessThan", 12329 argLen: 1, 12330 reg: regInfo{ 12331 outputs: []outputInfo{ 12332 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12333 }, 12334 }, 12335 }, 12336 { 12337 name: "LessEqual", 12338 argLen: 1, 12339 reg: regInfo{ 12340 outputs: []outputInfo{ 12341 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12342 }, 12343 }, 12344 }, 12345 { 12346 name: "GreaterThan", 12347 argLen: 1, 12348 reg: regInfo{ 12349 outputs: []outputInfo{ 12350 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12351 }, 12352 }, 12353 }, 12354 { 12355 name: "GreaterEqual", 12356 argLen: 1, 12357 reg: regInfo{ 12358 outputs: []outputInfo{ 12359 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12360 }, 12361 }, 12362 }, 12363 { 12364 name: "LessThanU", 12365 argLen: 1, 12366 reg: regInfo{ 12367 outputs: []outputInfo{ 12368 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12369 }, 12370 }, 12371 }, 12372 { 12373 name: "LessEqualU", 12374 argLen: 1, 12375 reg: regInfo{ 12376 outputs: []outputInfo{ 12377 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12378 }, 12379 }, 12380 }, 12381 { 12382 name: "GreaterThanU", 12383 argLen: 1, 12384 reg: regInfo{ 12385 outputs: []outputInfo{ 12386 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12387 }, 12388 }, 12389 }, 12390 { 12391 name: "GreaterEqualU", 12392 argLen: 1, 12393 reg: regInfo{ 12394 outputs: []outputInfo{ 12395 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12396 }, 12397 }, 12398 }, 12399 { 12400 name: "DUFFZERO", 12401 auxType: auxInt64, 12402 argLen: 2, 12403 faultOnNilArg0: true, 12404 reg: regInfo{ 12405 inputs: []inputInfo{ 12406 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12407 }, 12408 clobbers: 536936448, // R16 R30 12409 }, 12410 }, 12411 { 12412 name: "LoweredZero", 12413 argLen: 3, 12414 clobberFlags: true, 12415 faultOnNilArg0: true, 12416 reg: regInfo{ 12417 inputs: []inputInfo{ 12418 {0, 65536}, // R16 12419 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12420 }, 12421 clobbers: 65536, // R16 12422 }, 12423 }, 12424 { 12425 name: "DUFFCOPY", 12426 auxType: auxInt64, 12427 argLen: 3, 12428 faultOnNilArg0: true, 12429 faultOnNilArg1: true, 12430 reg: regInfo{ 12431 inputs: []inputInfo{ 12432 {0, 131072}, // R17 12433 {1, 65536}, // R16 12434 }, 12435 clobbers: 537067520, // R16 R17 R30 12436 }, 12437 }, 12438 { 12439 name: "LoweredMove", 12440 argLen: 4, 12441 clobberFlags: true, 12442 faultOnNilArg0: true, 12443 faultOnNilArg1: true, 12444 reg: regInfo{ 12445 inputs: []inputInfo{ 12446 {0, 131072}, // R17 12447 {1, 65536}, // R16 12448 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12449 }, 12450 clobbers: 196608, // R16 R17 12451 }, 12452 }, 12453 { 12454 name: "LoweredGetClosurePtr", 12455 argLen: 0, 12456 reg: regInfo{ 12457 outputs: []outputInfo{ 12458 {0, 67108864}, // R26 12459 }, 12460 }, 12461 }, 12462 { 12463 name: "MOVDconvert", 12464 argLen: 2, 12465 asm: arm64.AMOVD, 12466 reg: regInfo{ 12467 inputs: []inputInfo{ 12468 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12469 }, 12470 outputs: []outputInfo{ 12471 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12472 }, 12473 }, 12474 }, 12475 { 12476 name: "FlagEQ", 12477 argLen: 0, 12478 reg: regInfo{}, 12479 }, 12480 { 12481 name: "FlagLT_ULT", 12482 argLen: 0, 12483 reg: regInfo{}, 12484 }, 12485 { 12486 name: "FlagLT_UGT", 12487 argLen: 0, 12488 reg: regInfo{}, 12489 }, 12490 { 12491 name: "FlagGT_UGT", 12492 argLen: 0, 12493 reg: regInfo{}, 12494 }, 12495 { 12496 name: "FlagGT_ULT", 12497 argLen: 0, 12498 reg: regInfo{}, 12499 }, 12500 { 12501 name: "InvertFlags", 12502 argLen: 1, 12503 reg: regInfo{}, 12504 }, 12505 { 12506 name: "LDAR", 12507 argLen: 2, 12508 faultOnNilArg0: true, 12509 asm: arm64.ALDAR, 12510 reg: regInfo{ 12511 inputs: []inputInfo{ 12512 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12513 }, 12514 outputs: []outputInfo{ 12515 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12516 }, 12517 }, 12518 }, 12519 { 12520 name: "LDARW", 12521 argLen: 2, 12522 faultOnNilArg0: true, 12523 asm: arm64.ALDARW, 12524 reg: regInfo{ 12525 inputs: []inputInfo{ 12526 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12527 }, 12528 outputs: []outputInfo{ 12529 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12530 }, 12531 }, 12532 }, 12533 { 12534 name: "STLR", 12535 argLen: 3, 12536 faultOnNilArg0: true, 12537 asm: arm64.ASTLR, 12538 reg: regInfo{ 12539 inputs: []inputInfo{ 12540 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12541 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12542 }, 12543 }, 12544 }, 12545 { 12546 name: "STLRW", 12547 argLen: 3, 12548 faultOnNilArg0: true, 12549 asm: arm64.ASTLRW, 12550 reg: regInfo{ 12551 inputs: []inputInfo{ 12552 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12553 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12554 }, 12555 }, 12556 }, 12557 { 12558 name: "LoweredAtomicExchange64", 12559 argLen: 3, 12560 resultNotInArgs: true, 12561 faultOnNilArg0: true, 12562 reg: regInfo{ 12563 inputs: []inputInfo{ 12564 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12565 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12566 }, 12567 outputs: []outputInfo{ 12568 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12569 }, 12570 }, 12571 }, 12572 { 12573 name: "LoweredAtomicExchange32", 12574 argLen: 3, 12575 resultNotInArgs: true, 12576 faultOnNilArg0: true, 12577 reg: regInfo{ 12578 inputs: []inputInfo{ 12579 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12580 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12581 }, 12582 outputs: []outputInfo{ 12583 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12584 }, 12585 }, 12586 }, 12587 { 12588 name: "LoweredAtomicAdd64", 12589 argLen: 3, 12590 resultNotInArgs: true, 12591 faultOnNilArg0: true, 12592 reg: regInfo{ 12593 inputs: []inputInfo{ 12594 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12595 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12596 }, 12597 outputs: []outputInfo{ 12598 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12599 }, 12600 }, 12601 }, 12602 { 12603 name: "LoweredAtomicAdd32", 12604 argLen: 3, 12605 resultNotInArgs: true, 12606 faultOnNilArg0: true, 12607 reg: regInfo{ 12608 inputs: []inputInfo{ 12609 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12610 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12611 }, 12612 outputs: []outputInfo{ 12613 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12614 }, 12615 }, 12616 }, 12617 { 12618 name: "LoweredAtomicCas64", 12619 argLen: 4, 12620 resultNotInArgs: true, 12621 clobberFlags: true, 12622 faultOnNilArg0: true, 12623 reg: regInfo{ 12624 inputs: []inputInfo{ 12625 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12626 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12627 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12628 }, 12629 outputs: []outputInfo{ 12630 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12631 }, 12632 }, 12633 }, 12634 { 12635 name: "LoweredAtomicCas32", 12636 argLen: 4, 12637 resultNotInArgs: true, 12638 clobberFlags: true, 12639 faultOnNilArg0: true, 12640 reg: regInfo{ 12641 inputs: []inputInfo{ 12642 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12643 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12644 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12645 }, 12646 outputs: []outputInfo{ 12647 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12648 }, 12649 }, 12650 }, 12651 { 12652 name: "LoweredAtomicAnd8", 12653 argLen: 3, 12654 faultOnNilArg0: true, 12655 asm: arm64.AAND, 12656 reg: regInfo{ 12657 inputs: []inputInfo{ 12658 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12659 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12660 }, 12661 }, 12662 }, 12663 { 12664 name: "LoweredAtomicOr8", 12665 argLen: 3, 12666 faultOnNilArg0: true, 12667 asm: arm64.AORR, 12668 reg: regInfo{ 12669 inputs: []inputInfo{ 12670 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12671 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12672 }, 12673 }, 12674 }, 12675 12676 { 12677 name: "ADDV", 12678 argLen: 2, 12679 commutative: true, 12680 asm: mips.AADDVU, 12681 reg: regInfo{ 12682 inputs: []inputInfo{ 12683 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12684 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12685 }, 12686 outputs: []outputInfo{ 12687 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 12688 }, 12689 }, 12690 }, 12691 { 12692 name: "ADDVconst", 12693 auxType: auxInt64, 12694 argLen: 1, 12695 asm: mips.AADDVU, 12696 reg: regInfo{ 12697 inputs: []inputInfo{ 12698 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 12699 }, 12700 outputs: []outputInfo{ 12701 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 12702 }, 12703 }, 12704 }, 12705 { 12706 name: "SUBV", 12707 argLen: 2, 12708 asm: mips.ASUBVU, 12709 reg: regInfo{ 12710 inputs: []inputInfo{ 12711 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12712 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12713 }, 12714 outputs: []outputInfo{ 12715 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 12716 }, 12717 }, 12718 }, 12719 { 12720 name: "SUBVconst", 12721 auxType: auxInt64, 12722 argLen: 1, 12723 asm: mips.ASUBVU, 12724 reg: regInfo{ 12725 inputs: []inputInfo{ 12726 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12727 }, 12728 outputs: []outputInfo{ 12729 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 12730 }, 12731 }, 12732 }, 12733 { 12734 name: "MULV", 12735 argLen: 2, 12736 commutative: true, 12737 asm: mips.AMULV, 12738 reg: regInfo{ 12739 inputs: []inputInfo{ 12740 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12741 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12742 }, 12743 outputs: []outputInfo{ 12744 {0, 1152921504606846976}, // HI 12745 {1, 2305843009213693952}, // LO 12746 }, 12747 }, 12748 }, 12749 { 12750 name: "MULVU", 12751 argLen: 2, 12752 commutative: true, 12753 asm: mips.AMULVU, 12754 reg: regInfo{ 12755 inputs: []inputInfo{ 12756 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12757 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12758 }, 12759 outputs: []outputInfo{ 12760 {0, 1152921504606846976}, // HI 12761 {1, 2305843009213693952}, // LO 12762 }, 12763 }, 12764 }, 12765 { 12766 name: "DIVV", 12767 argLen: 2, 12768 asm: mips.ADIVV, 12769 reg: regInfo{ 12770 inputs: []inputInfo{ 12771 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12772 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12773 }, 12774 outputs: []outputInfo{ 12775 {0, 1152921504606846976}, // HI 12776 {1, 2305843009213693952}, // LO 12777 }, 12778 }, 12779 }, 12780 { 12781 name: "DIVVU", 12782 argLen: 2, 12783 asm: mips.ADIVVU, 12784 reg: regInfo{ 12785 inputs: []inputInfo{ 12786 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12787 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12788 }, 12789 outputs: []outputInfo{ 12790 {0, 1152921504606846976}, // HI 12791 {1, 2305843009213693952}, // LO 12792 }, 12793 }, 12794 }, 12795 { 12796 name: "ADDF", 12797 argLen: 2, 12798 commutative: true, 12799 asm: mips.AADDF, 12800 reg: regInfo{ 12801 inputs: []inputInfo{ 12802 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12803 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12804 }, 12805 outputs: []outputInfo{ 12806 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12807 }, 12808 }, 12809 }, 12810 { 12811 name: "ADDD", 12812 argLen: 2, 12813 commutative: true, 12814 asm: mips.AADDD, 12815 reg: regInfo{ 12816 inputs: []inputInfo{ 12817 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12818 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12819 }, 12820 outputs: []outputInfo{ 12821 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12822 }, 12823 }, 12824 }, 12825 { 12826 name: "SUBF", 12827 argLen: 2, 12828 asm: mips.ASUBF, 12829 reg: regInfo{ 12830 inputs: []inputInfo{ 12831 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12832 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12833 }, 12834 outputs: []outputInfo{ 12835 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12836 }, 12837 }, 12838 }, 12839 { 12840 name: "SUBD", 12841 argLen: 2, 12842 asm: mips.ASUBD, 12843 reg: regInfo{ 12844 inputs: []inputInfo{ 12845 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12846 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12847 }, 12848 outputs: []outputInfo{ 12849 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12850 }, 12851 }, 12852 }, 12853 { 12854 name: "MULF", 12855 argLen: 2, 12856 commutative: true, 12857 asm: mips.AMULF, 12858 reg: regInfo{ 12859 inputs: []inputInfo{ 12860 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12861 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12862 }, 12863 outputs: []outputInfo{ 12864 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12865 }, 12866 }, 12867 }, 12868 { 12869 name: "MULD", 12870 argLen: 2, 12871 commutative: true, 12872 asm: mips.AMULD, 12873 reg: regInfo{ 12874 inputs: []inputInfo{ 12875 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12876 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12877 }, 12878 outputs: []outputInfo{ 12879 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12880 }, 12881 }, 12882 }, 12883 { 12884 name: "DIVF", 12885 argLen: 2, 12886 asm: mips.ADIVF, 12887 reg: regInfo{ 12888 inputs: []inputInfo{ 12889 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12890 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12891 }, 12892 outputs: []outputInfo{ 12893 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12894 }, 12895 }, 12896 }, 12897 { 12898 name: "DIVD", 12899 argLen: 2, 12900 asm: mips.ADIVD, 12901 reg: regInfo{ 12902 inputs: []inputInfo{ 12903 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12904 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12905 }, 12906 outputs: []outputInfo{ 12907 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12908 }, 12909 }, 12910 }, 12911 { 12912 name: "AND", 12913 argLen: 2, 12914 commutative: true, 12915 asm: mips.AAND, 12916 reg: regInfo{ 12917 inputs: []inputInfo{ 12918 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12919 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12920 }, 12921 outputs: []outputInfo{ 12922 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 12923 }, 12924 }, 12925 }, 12926 { 12927 name: "ANDconst", 12928 auxType: auxInt64, 12929 argLen: 1, 12930 asm: mips.AAND, 12931 reg: regInfo{ 12932 inputs: []inputInfo{ 12933 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12934 }, 12935 outputs: []outputInfo{ 12936 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 12937 }, 12938 }, 12939 }, 12940 { 12941 name: "OR", 12942 argLen: 2, 12943 commutative: true, 12944 asm: mips.AOR, 12945 reg: regInfo{ 12946 inputs: []inputInfo{ 12947 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12948 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12949 }, 12950 outputs: []outputInfo{ 12951 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 12952 }, 12953 }, 12954 }, 12955 { 12956 name: "ORconst", 12957 auxType: auxInt64, 12958 argLen: 1, 12959 asm: mips.AOR, 12960 reg: regInfo{ 12961 inputs: []inputInfo{ 12962 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12963 }, 12964 outputs: []outputInfo{ 12965 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 12966 }, 12967 }, 12968 }, 12969 { 12970 name: "XOR", 12971 argLen: 2, 12972 commutative: true, 12973 asm: mips.AXOR, 12974 reg: regInfo{ 12975 inputs: []inputInfo{ 12976 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12977 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12978 }, 12979 outputs: []outputInfo{ 12980 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 12981 }, 12982 }, 12983 }, 12984 { 12985 name: "XORconst", 12986 auxType: auxInt64, 12987 argLen: 1, 12988 asm: mips.AXOR, 12989 reg: regInfo{ 12990 inputs: []inputInfo{ 12991 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 12992 }, 12993 outputs: []outputInfo{ 12994 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 12995 }, 12996 }, 12997 }, 12998 { 12999 name: "NOR", 13000 argLen: 2, 13001 commutative: true, 13002 asm: mips.ANOR, 13003 reg: regInfo{ 13004 inputs: []inputInfo{ 13005 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13006 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13007 }, 13008 outputs: []outputInfo{ 13009 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13010 }, 13011 }, 13012 }, 13013 { 13014 name: "NORconst", 13015 auxType: auxInt64, 13016 argLen: 1, 13017 asm: mips.ANOR, 13018 reg: regInfo{ 13019 inputs: []inputInfo{ 13020 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13021 }, 13022 outputs: []outputInfo{ 13023 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13024 }, 13025 }, 13026 }, 13027 { 13028 name: "NEGV", 13029 argLen: 1, 13030 reg: regInfo{ 13031 inputs: []inputInfo{ 13032 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13033 }, 13034 outputs: []outputInfo{ 13035 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13036 }, 13037 }, 13038 }, 13039 { 13040 name: "NEGF", 13041 argLen: 1, 13042 asm: mips.ANEGF, 13043 reg: regInfo{ 13044 inputs: []inputInfo{ 13045 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13046 }, 13047 outputs: []outputInfo{ 13048 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13049 }, 13050 }, 13051 }, 13052 { 13053 name: "NEGD", 13054 argLen: 1, 13055 asm: mips.ANEGD, 13056 reg: regInfo{ 13057 inputs: []inputInfo{ 13058 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13059 }, 13060 outputs: []outputInfo{ 13061 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13062 }, 13063 }, 13064 }, 13065 { 13066 name: "SLLV", 13067 argLen: 2, 13068 asm: mips.ASLLV, 13069 reg: regInfo{ 13070 inputs: []inputInfo{ 13071 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13072 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13073 }, 13074 outputs: []outputInfo{ 13075 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13076 }, 13077 }, 13078 }, 13079 { 13080 name: "SLLVconst", 13081 auxType: auxInt64, 13082 argLen: 1, 13083 asm: mips.ASLLV, 13084 reg: regInfo{ 13085 inputs: []inputInfo{ 13086 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13087 }, 13088 outputs: []outputInfo{ 13089 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13090 }, 13091 }, 13092 }, 13093 { 13094 name: "SRLV", 13095 argLen: 2, 13096 asm: mips.ASRLV, 13097 reg: regInfo{ 13098 inputs: []inputInfo{ 13099 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13100 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13101 }, 13102 outputs: []outputInfo{ 13103 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13104 }, 13105 }, 13106 }, 13107 { 13108 name: "SRLVconst", 13109 auxType: auxInt64, 13110 argLen: 1, 13111 asm: mips.ASRLV, 13112 reg: regInfo{ 13113 inputs: []inputInfo{ 13114 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13115 }, 13116 outputs: []outputInfo{ 13117 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13118 }, 13119 }, 13120 }, 13121 { 13122 name: "SRAV", 13123 argLen: 2, 13124 asm: mips.ASRAV, 13125 reg: regInfo{ 13126 inputs: []inputInfo{ 13127 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13128 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13129 }, 13130 outputs: []outputInfo{ 13131 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13132 }, 13133 }, 13134 }, 13135 { 13136 name: "SRAVconst", 13137 auxType: auxInt64, 13138 argLen: 1, 13139 asm: mips.ASRAV, 13140 reg: regInfo{ 13141 inputs: []inputInfo{ 13142 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13143 }, 13144 outputs: []outputInfo{ 13145 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13146 }, 13147 }, 13148 }, 13149 { 13150 name: "SGT", 13151 argLen: 2, 13152 asm: mips.ASGT, 13153 reg: regInfo{ 13154 inputs: []inputInfo{ 13155 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13156 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13157 }, 13158 outputs: []outputInfo{ 13159 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13160 }, 13161 }, 13162 }, 13163 { 13164 name: "SGTconst", 13165 auxType: auxInt64, 13166 argLen: 1, 13167 asm: mips.ASGT, 13168 reg: regInfo{ 13169 inputs: []inputInfo{ 13170 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13171 }, 13172 outputs: []outputInfo{ 13173 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13174 }, 13175 }, 13176 }, 13177 { 13178 name: "SGTU", 13179 argLen: 2, 13180 asm: mips.ASGTU, 13181 reg: regInfo{ 13182 inputs: []inputInfo{ 13183 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13184 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13185 }, 13186 outputs: []outputInfo{ 13187 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13188 }, 13189 }, 13190 }, 13191 { 13192 name: "SGTUconst", 13193 auxType: auxInt64, 13194 argLen: 1, 13195 asm: mips.ASGTU, 13196 reg: regInfo{ 13197 inputs: []inputInfo{ 13198 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13199 }, 13200 outputs: []outputInfo{ 13201 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13202 }, 13203 }, 13204 }, 13205 { 13206 name: "CMPEQF", 13207 argLen: 2, 13208 asm: mips.ACMPEQF, 13209 reg: regInfo{ 13210 inputs: []inputInfo{ 13211 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13212 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13213 }, 13214 }, 13215 }, 13216 { 13217 name: "CMPEQD", 13218 argLen: 2, 13219 asm: mips.ACMPEQD, 13220 reg: regInfo{ 13221 inputs: []inputInfo{ 13222 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13223 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13224 }, 13225 }, 13226 }, 13227 { 13228 name: "CMPGEF", 13229 argLen: 2, 13230 asm: mips.ACMPGEF, 13231 reg: regInfo{ 13232 inputs: []inputInfo{ 13233 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13234 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13235 }, 13236 }, 13237 }, 13238 { 13239 name: "CMPGED", 13240 argLen: 2, 13241 asm: mips.ACMPGED, 13242 reg: regInfo{ 13243 inputs: []inputInfo{ 13244 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13245 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13246 }, 13247 }, 13248 }, 13249 { 13250 name: "CMPGTF", 13251 argLen: 2, 13252 asm: mips.ACMPGTF, 13253 reg: regInfo{ 13254 inputs: []inputInfo{ 13255 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13256 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13257 }, 13258 }, 13259 }, 13260 { 13261 name: "CMPGTD", 13262 argLen: 2, 13263 asm: mips.ACMPGTD, 13264 reg: regInfo{ 13265 inputs: []inputInfo{ 13266 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13267 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13268 }, 13269 }, 13270 }, 13271 { 13272 name: "MOVVconst", 13273 auxType: auxInt64, 13274 argLen: 0, 13275 rematerializeable: true, 13276 asm: mips.AMOVV, 13277 reg: regInfo{ 13278 outputs: []outputInfo{ 13279 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13280 }, 13281 }, 13282 }, 13283 { 13284 name: "MOVFconst", 13285 auxType: auxFloat64, 13286 argLen: 0, 13287 rematerializeable: true, 13288 asm: mips.AMOVF, 13289 reg: regInfo{ 13290 outputs: []outputInfo{ 13291 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13292 }, 13293 }, 13294 }, 13295 { 13296 name: "MOVDconst", 13297 auxType: auxFloat64, 13298 argLen: 0, 13299 rematerializeable: true, 13300 asm: mips.AMOVD, 13301 reg: regInfo{ 13302 outputs: []outputInfo{ 13303 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13304 }, 13305 }, 13306 }, 13307 { 13308 name: "MOVVaddr", 13309 auxType: auxSymOff, 13310 argLen: 1, 13311 rematerializeable: true, 13312 asm: mips.AMOVV, 13313 reg: regInfo{ 13314 inputs: []inputInfo{ 13315 {0, 4611686018460942336}, // SP SB 13316 }, 13317 outputs: []outputInfo{ 13318 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13319 }, 13320 }, 13321 }, 13322 { 13323 name: "MOVBload", 13324 auxType: auxSymOff, 13325 argLen: 2, 13326 faultOnNilArg0: true, 13327 asm: mips.AMOVB, 13328 reg: regInfo{ 13329 inputs: []inputInfo{ 13330 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13331 }, 13332 outputs: []outputInfo{ 13333 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13334 }, 13335 }, 13336 }, 13337 { 13338 name: "MOVBUload", 13339 auxType: auxSymOff, 13340 argLen: 2, 13341 faultOnNilArg0: true, 13342 asm: mips.AMOVBU, 13343 reg: regInfo{ 13344 inputs: []inputInfo{ 13345 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13346 }, 13347 outputs: []outputInfo{ 13348 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13349 }, 13350 }, 13351 }, 13352 { 13353 name: "MOVHload", 13354 auxType: auxSymOff, 13355 argLen: 2, 13356 faultOnNilArg0: true, 13357 asm: mips.AMOVH, 13358 reg: regInfo{ 13359 inputs: []inputInfo{ 13360 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13361 }, 13362 outputs: []outputInfo{ 13363 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13364 }, 13365 }, 13366 }, 13367 { 13368 name: "MOVHUload", 13369 auxType: auxSymOff, 13370 argLen: 2, 13371 faultOnNilArg0: true, 13372 asm: mips.AMOVHU, 13373 reg: regInfo{ 13374 inputs: []inputInfo{ 13375 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13376 }, 13377 outputs: []outputInfo{ 13378 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13379 }, 13380 }, 13381 }, 13382 { 13383 name: "MOVWload", 13384 auxType: auxSymOff, 13385 argLen: 2, 13386 faultOnNilArg0: true, 13387 asm: mips.AMOVW, 13388 reg: regInfo{ 13389 inputs: []inputInfo{ 13390 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13391 }, 13392 outputs: []outputInfo{ 13393 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13394 }, 13395 }, 13396 }, 13397 { 13398 name: "MOVWUload", 13399 auxType: auxSymOff, 13400 argLen: 2, 13401 faultOnNilArg0: true, 13402 asm: mips.AMOVWU, 13403 reg: regInfo{ 13404 inputs: []inputInfo{ 13405 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13406 }, 13407 outputs: []outputInfo{ 13408 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13409 }, 13410 }, 13411 }, 13412 { 13413 name: "MOVVload", 13414 auxType: auxSymOff, 13415 argLen: 2, 13416 faultOnNilArg0: true, 13417 asm: mips.AMOVV, 13418 reg: regInfo{ 13419 inputs: []inputInfo{ 13420 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13421 }, 13422 outputs: []outputInfo{ 13423 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13424 }, 13425 }, 13426 }, 13427 { 13428 name: "MOVFload", 13429 auxType: auxSymOff, 13430 argLen: 2, 13431 faultOnNilArg0: true, 13432 asm: mips.AMOVF, 13433 reg: regInfo{ 13434 inputs: []inputInfo{ 13435 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13436 }, 13437 outputs: []outputInfo{ 13438 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13439 }, 13440 }, 13441 }, 13442 { 13443 name: "MOVDload", 13444 auxType: auxSymOff, 13445 argLen: 2, 13446 faultOnNilArg0: true, 13447 asm: mips.AMOVD, 13448 reg: regInfo{ 13449 inputs: []inputInfo{ 13450 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13451 }, 13452 outputs: []outputInfo{ 13453 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13454 }, 13455 }, 13456 }, 13457 { 13458 name: "MOVBstore", 13459 auxType: auxSymOff, 13460 argLen: 3, 13461 faultOnNilArg0: true, 13462 asm: mips.AMOVB, 13463 reg: regInfo{ 13464 inputs: []inputInfo{ 13465 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13466 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13467 }, 13468 }, 13469 }, 13470 { 13471 name: "MOVHstore", 13472 auxType: auxSymOff, 13473 argLen: 3, 13474 faultOnNilArg0: true, 13475 asm: mips.AMOVH, 13476 reg: regInfo{ 13477 inputs: []inputInfo{ 13478 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13479 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13480 }, 13481 }, 13482 }, 13483 { 13484 name: "MOVWstore", 13485 auxType: auxSymOff, 13486 argLen: 3, 13487 faultOnNilArg0: true, 13488 asm: mips.AMOVW, 13489 reg: regInfo{ 13490 inputs: []inputInfo{ 13491 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13492 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13493 }, 13494 }, 13495 }, 13496 { 13497 name: "MOVVstore", 13498 auxType: auxSymOff, 13499 argLen: 3, 13500 faultOnNilArg0: true, 13501 asm: mips.AMOVV, 13502 reg: regInfo{ 13503 inputs: []inputInfo{ 13504 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13505 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13506 }, 13507 }, 13508 }, 13509 { 13510 name: "MOVFstore", 13511 auxType: auxSymOff, 13512 argLen: 3, 13513 faultOnNilArg0: true, 13514 asm: mips.AMOVF, 13515 reg: regInfo{ 13516 inputs: []inputInfo{ 13517 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13518 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13519 }, 13520 }, 13521 }, 13522 { 13523 name: "MOVDstore", 13524 auxType: auxSymOff, 13525 argLen: 3, 13526 faultOnNilArg0: true, 13527 asm: mips.AMOVD, 13528 reg: regInfo{ 13529 inputs: []inputInfo{ 13530 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13531 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13532 }, 13533 }, 13534 }, 13535 { 13536 name: "MOVBstorezero", 13537 auxType: auxSymOff, 13538 argLen: 2, 13539 faultOnNilArg0: true, 13540 asm: mips.AMOVB, 13541 reg: regInfo{ 13542 inputs: []inputInfo{ 13543 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13544 }, 13545 }, 13546 }, 13547 { 13548 name: "MOVHstorezero", 13549 auxType: auxSymOff, 13550 argLen: 2, 13551 faultOnNilArg0: true, 13552 asm: mips.AMOVH, 13553 reg: regInfo{ 13554 inputs: []inputInfo{ 13555 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13556 }, 13557 }, 13558 }, 13559 { 13560 name: "MOVWstorezero", 13561 auxType: auxSymOff, 13562 argLen: 2, 13563 faultOnNilArg0: true, 13564 asm: mips.AMOVW, 13565 reg: regInfo{ 13566 inputs: []inputInfo{ 13567 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13568 }, 13569 }, 13570 }, 13571 { 13572 name: "MOVVstorezero", 13573 auxType: auxSymOff, 13574 argLen: 2, 13575 faultOnNilArg0: true, 13576 asm: mips.AMOVV, 13577 reg: regInfo{ 13578 inputs: []inputInfo{ 13579 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 13580 }, 13581 }, 13582 }, 13583 { 13584 name: "MOVBreg", 13585 argLen: 1, 13586 asm: mips.AMOVB, 13587 reg: regInfo{ 13588 inputs: []inputInfo{ 13589 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13590 }, 13591 outputs: []outputInfo{ 13592 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13593 }, 13594 }, 13595 }, 13596 { 13597 name: "MOVBUreg", 13598 argLen: 1, 13599 asm: mips.AMOVBU, 13600 reg: regInfo{ 13601 inputs: []inputInfo{ 13602 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13603 }, 13604 outputs: []outputInfo{ 13605 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13606 }, 13607 }, 13608 }, 13609 { 13610 name: "MOVHreg", 13611 argLen: 1, 13612 asm: mips.AMOVH, 13613 reg: regInfo{ 13614 inputs: []inputInfo{ 13615 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13616 }, 13617 outputs: []outputInfo{ 13618 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13619 }, 13620 }, 13621 }, 13622 { 13623 name: "MOVHUreg", 13624 argLen: 1, 13625 asm: mips.AMOVHU, 13626 reg: regInfo{ 13627 inputs: []inputInfo{ 13628 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13629 }, 13630 outputs: []outputInfo{ 13631 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13632 }, 13633 }, 13634 }, 13635 { 13636 name: "MOVWreg", 13637 argLen: 1, 13638 asm: mips.AMOVW, 13639 reg: regInfo{ 13640 inputs: []inputInfo{ 13641 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13642 }, 13643 outputs: []outputInfo{ 13644 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13645 }, 13646 }, 13647 }, 13648 { 13649 name: "MOVWUreg", 13650 argLen: 1, 13651 asm: mips.AMOVWU, 13652 reg: regInfo{ 13653 inputs: []inputInfo{ 13654 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13655 }, 13656 outputs: []outputInfo{ 13657 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13658 }, 13659 }, 13660 }, 13661 { 13662 name: "MOVVreg", 13663 argLen: 1, 13664 asm: mips.AMOVV, 13665 reg: regInfo{ 13666 inputs: []inputInfo{ 13667 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13668 }, 13669 outputs: []outputInfo{ 13670 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13671 }, 13672 }, 13673 }, 13674 { 13675 name: "MOVVnop", 13676 argLen: 1, 13677 resultInArg0: true, 13678 reg: regInfo{ 13679 inputs: []inputInfo{ 13680 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13681 }, 13682 outputs: []outputInfo{ 13683 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13684 }, 13685 }, 13686 }, 13687 { 13688 name: "MOVWF", 13689 argLen: 1, 13690 asm: mips.AMOVWF, 13691 reg: regInfo{ 13692 inputs: []inputInfo{ 13693 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13694 }, 13695 outputs: []outputInfo{ 13696 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13697 }, 13698 }, 13699 }, 13700 { 13701 name: "MOVWD", 13702 argLen: 1, 13703 asm: mips.AMOVWD, 13704 reg: regInfo{ 13705 inputs: []inputInfo{ 13706 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13707 }, 13708 outputs: []outputInfo{ 13709 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13710 }, 13711 }, 13712 }, 13713 { 13714 name: "MOVVF", 13715 argLen: 1, 13716 asm: mips.AMOVVF, 13717 reg: regInfo{ 13718 inputs: []inputInfo{ 13719 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13720 }, 13721 outputs: []outputInfo{ 13722 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13723 }, 13724 }, 13725 }, 13726 { 13727 name: "MOVVD", 13728 argLen: 1, 13729 asm: mips.AMOVVD, 13730 reg: regInfo{ 13731 inputs: []inputInfo{ 13732 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13733 }, 13734 outputs: []outputInfo{ 13735 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13736 }, 13737 }, 13738 }, 13739 { 13740 name: "TRUNCFW", 13741 argLen: 1, 13742 asm: mips.ATRUNCFW, 13743 reg: regInfo{ 13744 inputs: []inputInfo{ 13745 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13746 }, 13747 outputs: []outputInfo{ 13748 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13749 }, 13750 }, 13751 }, 13752 { 13753 name: "TRUNCDW", 13754 argLen: 1, 13755 asm: mips.ATRUNCDW, 13756 reg: regInfo{ 13757 inputs: []inputInfo{ 13758 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13759 }, 13760 outputs: []outputInfo{ 13761 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13762 }, 13763 }, 13764 }, 13765 { 13766 name: "TRUNCFV", 13767 argLen: 1, 13768 asm: mips.ATRUNCFV, 13769 reg: regInfo{ 13770 inputs: []inputInfo{ 13771 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13772 }, 13773 outputs: []outputInfo{ 13774 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13775 }, 13776 }, 13777 }, 13778 { 13779 name: "TRUNCDV", 13780 argLen: 1, 13781 asm: mips.ATRUNCDV, 13782 reg: regInfo{ 13783 inputs: []inputInfo{ 13784 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13785 }, 13786 outputs: []outputInfo{ 13787 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13788 }, 13789 }, 13790 }, 13791 { 13792 name: "MOVFD", 13793 argLen: 1, 13794 asm: mips.AMOVFD, 13795 reg: regInfo{ 13796 inputs: []inputInfo{ 13797 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13798 }, 13799 outputs: []outputInfo{ 13800 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13801 }, 13802 }, 13803 }, 13804 { 13805 name: "MOVDF", 13806 argLen: 1, 13807 asm: mips.AMOVDF, 13808 reg: regInfo{ 13809 inputs: []inputInfo{ 13810 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13811 }, 13812 outputs: []outputInfo{ 13813 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13814 }, 13815 }, 13816 }, 13817 { 13818 name: "CALLstatic", 13819 auxType: auxSymOff, 13820 argLen: 1, 13821 clobberFlags: true, 13822 call: true, 13823 reg: regInfo{ 13824 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 13825 }, 13826 }, 13827 { 13828 name: "CALLclosure", 13829 auxType: auxInt64, 13830 argLen: 3, 13831 clobberFlags: true, 13832 call: true, 13833 reg: regInfo{ 13834 inputs: []inputInfo{ 13835 {1, 4194304}, // R22 13836 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 13837 }, 13838 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 13839 }, 13840 }, 13841 { 13842 name: "CALLdefer", 13843 auxType: auxInt64, 13844 argLen: 1, 13845 clobberFlags: true, 13846 call: true, 13847 reg: regInfo{ 13848 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 13849 }, 13850 }, 13851 { 13852 name: "CALLgo", 13853 auxType: auxInt64, 13854 argLen: 1, 13855 clobberFlags: true, 13856 call: true, 13857 reg: regInfo{ 13858 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 13859 }, 13860 }, 13861 { 13862 name: "CALLinter", 13863 auxType: auxInt64, 13864 argLen: 2, 13865 clobberFlags: true, 13866 call: true, 13867 reg: regInfo{ 13868 inputs: []inputInfo{ 13869 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13870 }, 13871 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 13872 }, 13873 }, 13874 { 13875 name: "DUFFZERO", 13876 auxType: auxInt64, 13877 argLen: 2, 13878 faultOnNilArg0: true, 13879 reg: regInfo{ 13880 inputs: []inputInfo{ 13881 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13882 }, 13883 clobbers: 134217730, // R1 R31 13884 }, 13885 }, 13886 { 13887 name: "LoweredZero", 13888 auxType: auxInt64, 13889 argLen: 3, 13890 clobberFlags: true, 13891 faultOnNilArg0: true, 13892 reg: regInfo{ 13893 inputs: []inputInfo{ 13894 {0, 2}, // R1 13895 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13896 }, 13897 clobbers: 2, // R1 13898 }, 13899 }, 13900 { 13901 name: "LoweredMove", 13902 auxType: auxInt64, 13903 argLen: 4, 13904 clobberFlags: true, 13905 faultOnNilArg0: true, 13906 faultOnNilArg1: true, 13907 reg: regInfo{ 13908 inputs: []inputInfo{ 13909 {0, 4}, // R2 13910 {1, 2}, // R1 13911 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13912 }, 13913 clobbers: 6, // R1 R2 13914 }, 13915 }, 13916 { 13917 name: "LoweredNilCheck", 13918 argLen: 2, 13919 nilCheck: true, 13920 faultOnNilArg0: true, 13921 reg: regInfo{ 13922 inputs: []inputInfo{ 13923 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13924 }, 13925 }, 13926 }, 13927 { 13928 name: "FPFlagTrue", 13929 argLen: 1, 13930 reg: regInfo{ 13931 outputs: []outputInfo{ 13932 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13933 }, 13934 }, 13935 }, 13936 { 13937 name: "FPFlagFalse", 13938 argLen: 1, 13939 reg: regInfo{ 13940 outputs: []outputInfo{ 13941 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13942 }, 13943 }, 13944 }, 13945 { 13946 name: "LoweredGetClosurePtr", 13947 argLen: 0, 13948 reg: regInfo{ 13949 outputs: []outputInfo{ 13950 {0, 4194304}, // R22 13951 }, 13952 }, 13953 }, 13954 { 13955 name: "MOVVconvert", 13956 argLen: 2, 13957 asm: mips.AMOVV, 13958 reg: regInfo{ 13959 inputs: []inputInfo{ 13960 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 13961 }, 13962 outputs: []outputInfo{ 13963 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 13964 }, 13965 }, 13966 }, 13967 13968 { 13969 name: "ADD", 13970 argLen: 2, 13971 commutative: true, 13972 asm: ppc64.AADD, 13973 reg: regInfo{ 13974 inputs: []inputInfo{ 13975 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13976 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13977 }, 13978 outputs: []outputInfo{ 13979 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13980 }, 13981 }, 13982 }, 13983 { 13984 name: "ADDconst", 13985 auxType: auxSymOff, 13986 argLen: 1, 13987 asm: ppc64.AADD, 13988 reg: regInfo{ 13989 inputs: []inputInfo{ 13990 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13991 }, 13992 outputs: []outputInfo{ 13993 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13994 }, 13995 }, 13996 }, 13997 { 13998 name: "FADD", 13999 argLen: 2, 14000 commutative: true, 14001 asm: ppc64.AFADD, 14002 reg: regInfo{ 14003 inputs: []inputInfo{ 14004 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14005 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14006 }, 14007 outputs: []outputInfo{ 14008 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14009 }, 14010 }, 14011 }, 14012 { 14013 name: "FADDS", 14014 argLen: 2, 14015 commutative: true, 14016 asm: ppc64.AFADDS, 14017 reg: regInfo{ 14018 inputs: []inputInfo{ 14019 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14020 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14021 }, 14022 outputs: []outputInfo{ 14023 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14024 }, 14025 }, 14026 }, 14027 { 14028 name: "SUB", 14029 argLen: 2, 14030 asm: ppc64.ASUB, 14031 reg: regInfo{ 14032 inputs: []inputInfo{ 14033 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14034 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14035 }, 14036 outputs: []outputInfo{ 14037 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14038 }, 14039 }, 14040 }, 14041 { 14042 name: "FSUB", 14043 argLen: 2, 14044 asm: ppc64.AFSUB, 14045 reg: regInfo{ 14046 inputs: []inputInfo{ 14047 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14048 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14049 }, 14050 outputs: []outputInfo{ 14051 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14052 }, 14053 }, 14054 }, 14055 { 14056 name: "FSUBS", 14057 argLen: 2, 14058 asm: ppc64.AFSUBS, 14059 reg: regInfo{ 14060 inputs: []inputInfo{ 14061 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14062 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14063 }, 14064 outputs: []outputInfo{ 14065 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14066 }, 14067 }, 14068 }, 14069 { 14070 name: "MULLD", 14071 argLen: 2, 14072 commutative: true, 14073 asm: ppc64.AMULLD, 14074 reg: regInfo{ 14075 inputs: []inputInfo{ 14076 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14077 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14078 }, 14079 outputs: []outputInfo{ 14080 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14081 }, 14082 }, 14083 }, 14084 { 14085 name: "MULLW", 14086 argLen: 2, 14087 commutative: true, 14088 asm: ppc64.AMULLW, 14089 reg: regInfo{ 14090 inputs: []inputInfo{ 14091 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14092 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14093 }, 14094 outputs: []outputInfo{ 14095 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14096 }, 14097 }, 14098 }, 14099 { 14100 name: "MULHD", 14101 argLen: 2, 14102 commutative: true, 14103 asm: ppc64.AMULHD, 14104 reg: regInfo{ 14105 inputs: []inputInfo{ 14106 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14107 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14108 }, 14109 outputs: []outputInfo{ 14110 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14111 }, 14112 }, 14113 }, 14114 { 14115 name: "MULHW", 14116 argLen: 2, 14117 commutative: true, 14118 asm: ppc64.AMULHW, 14119 reg: regInfo{ 14120 inputs: []inputInfo{ 14121 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14122 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14123 }, 14124 outputs: []outputInfo{ 14125 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14126 }, 14127 }, 14128 }, 14129 { 14130 name: "MULHDU", 14131 argLen: 2, 14132 commutative: true, 14133 asm: ppc64.AMULHDU, 14134 reg: regInfo{ 14135 inputs: []inputInfo{ 14136 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14137 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14138 }, 14139 outputs: []outputInfo{ 14140 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14141 }, 14142 }, 14143 }, 14144 { 14145 name: "MULHWU", 14146 argLen: 2, 14147 commutative: true, 14148 asm: ppc64.AMULHWU, 14149 reg: regInfo{ 14150 inputs: []inputInfo{ 14151 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14152 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14153 }, 14154 outputs: []outputInfo{ 14155 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14156 }, 14157 }, 14158 }, 14159 { 14160 name: "FMUL", 14161 argLen: 2, 14162 commutative: true, 14163 asm: ppc64.AFMUL, 14164 reg: regInfo{ 14165 inputs: []inputInfo{ 14166 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14167 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14168 }, 14169 outputs: []outputInfo{ 14170 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14171 }, 14172 }, 14173 }, 14174 { 14175 name: "FMULS", 14176 argLen: 2, 14177 commutative: true, 14178 asm: ppc64.AFMULS, 14179 reg: regInfo{ 14180 inputs: []inputInfo{ 14181 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14182 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14183 }, 14184 outputs: []outputInfo{ 14185 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14186 }, 14187 }, 14188 }, 14189 { 14190 name: "SRAD", 14191 argLen: 2, 14192 asm: ppc64.ASRAD, 14193 reg: regInfo{ 14194 inputs: []inputInfo{ 14195 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14196 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14197 }, 14198 outputs: []outputInfo{ 14199 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14200 }, 14201 }, 14202 }, 14203 { 14204 name: "SRAW", 14205 argLen: 2, 14206 asm: ppc64.ASRAW, 14207 reg: regInfo{ 14208 inputs: []inputInfo{ 14209 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14210 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14211 }, 14212 outputs: []outputInfo{ 14213 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14214 }, 14215 }, 14216 }, 14217 { 14218 name: "SRD", 14219 argLen: 2, 14220 asm: ppc64.ASRD, 14221 reg: regInfo{ 14222 inputs: []inputInfo{ 14223 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14224 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14225 }, 14226 outputs: []outputInfo{ 14227 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14228 }, 14229 }, 14230 }, 14231 { 14232 name: "SRW", 14233 argLen: 2, 14234 asm: ppc64.ASRW, 14235 reg: regInfo{ 14236 inputs: []inputInfo{ 14237 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14238 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14239 }, 14240 outputs: []outputInfo{ 14241 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14242 }, 14243 }, 14244 }, 14245 { 14246 name: "SLD", 14247 argLen: 2, 14248 asm: ppc64.ASLD, 14249 reg: regInfo{ 14250 inputs: []inputInfo{ 14251 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14252 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14253 }, 14254 outputs: []outputInfo{ 14255 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14256 }, 14257 }, 14258 }, 14259 { 14260 name: "SLW", 14261 argLen: 2, 14262 asm: ppc64.ASLW, 14263 reg: regInfo{ 14264 inputs: []inputInfo{ 14265 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14266 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14267 }, 14268 outputs: []outputInfo{ 14269 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14270 }, 14271 }, 14272 }, 14273 { 14274 name: "ADDconstForCarry", 14275 auxType: auxInt16, 14276 argLen: 1, 14277 asm: ppc64.AADDC, 14278 reg: regInfo{ 14279 inputs: []inputInfo{ 14280 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14281 }, 14282 clobbers: 2147483648, // R31 14283 }, 14284 }, 14285 { 14286 name: "MaskIfNotCarry", 14287 argLen: 1, 14288 asm: ppc64.AADDME, 14289 reg: regInfo{ 14290 outputs: []outputInfo{ 14291 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14292 }, 14293 }, 14294 }, 14295 { 14296 name: "SRADconst", 14297 auxType: auxInt64, 14298 argLen: 1, 14299 asm: ppc64.ASRAD, 14300 reg: regInfo{ 14301 inputs: []inputInfo{ 14302 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14303 }, 14304 outputs: []outputInfo{ 14305 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14306 }, 14307 }, 14308 }, 14309 { 14310 name: "SRAWconst", 14311 auxType: auxInt64, 14312 argLen: 1, 14313 asm: ppc64.ASRAW, 14314 reg: regInfo{ 14315 inputs: []inputInfo{ 14316 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14317 }, 14318 outputs: []outputInfo{ 14319 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14320 }, 14321 }, 14322 }, 14323 { 14324 name: "SRDconst", 14325 auxType: auxInt64, 14326 argLen: 1, 14327 asm: ppc64.ASRD, 14328 reg: regInfo{ 14329 inputs: []inputInfo{ 14330 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14331 }, 14332 outputs: []outputInfo{ 14333 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14334 }, 14335 }, 14336 }, 14337 { 14338 name: "SRWconst", 14339 auxType: auxInt64, 14340 argLen: 1, 14341 asm: ppc64.ASRW, 14342 reg: regInfo{ 14343 inputs: []inputInfo{ 14344 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14345 }, 14346 outputs: []outputInfo{ 14347 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14348 }, 14349 }, 14350 }, 14351 { 14352 name: "SLDconst", 14353 auxType: auxInt64, 14354 argLen: 1, 14355 asm: ppc64.ASLD, 14356 reg: regInfo{ 14357 inputs: []inputInfo{ 14358 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14359 }, 14360 outputs: []outputInfo{ 14361 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14362 }, 14363 }, 14364 }, 14365 { 14366 name: "SLWconst", 14367 auxType: auxInt64, 14368 argLen: 1, 14369 asm: ppc64.ASLW, 14370 reg: regInfo{ 14371 inputs: []inputInfo{ 14372 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14373 }, 14374 outputs: []outputInfo{ 14375 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14376 }, 14377 }, 14378 }, 14379 { 14380 name: "FDIV", 14381 argLen: 2, 14382 asm: ppc64.AFDIV, 14383 reg: regInfo{ 14384 inputs: []inputInfo{ 14385 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14386 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14387 }, 14388 outputs: []outputInfo{ 14389 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14390 }, 14391 }, 14392 }, 14393 { 14394 name: "FDIVS", 14395 argLen: 2, 14396 asm: ppc64.AFDIVS, 14397 reg: regInfo{ 14398 inputs: []inputInfo{ 14399 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14400 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14401 }, 14402 outputs: []outputInfo{ 14403 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14404 }, 14405 }, 14406 }, 14407 { 14408 name: "DIVD", 14409 argLen: 2, 14410 asm: ppc64.ADIVD, 14411 reg: regInfo{ 14412 inputs: []inputInfo{ 14413 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14414 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14415 }, 14416 outputs: []outputInfo{ 14417 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14418 }, 14419 }, 14420 }, 14421 { 14422 name: "DIVW", 14423 argLen: 2, 14424 asm: ppc64.ADIVW, 14425 reg: regInfo{ 14426 inputs: []inputInfo{ 14427 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14428 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14429 }, 14430 outputs: []outputInfo{ 14431 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14432 }, 14433 }, 14434 }, 14435 { 14436 name: "DIVDU", 14437 argLen: 2, 14438 asm: ppc64.ADIVDU, 14439 reg: regInfo{ 14440 inputs: []inputInfo{ 14441 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14442 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14443 }, 14444 outputs: []outputInfo{ 14445 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14446 }, 14447 }, 14448 }, 14449 { 14450 name: "DIVWU", 14451 argLen: 2, 14452 asm: ppc64.ADIVWU, 14453 reg: regInfo{ 14454 inputs: []inputInfo{ 14455 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14456 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14457 }, 14458 outputs: []outputInfo{ 14459 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14460 }, 14461 }, 14462 }, 14463 { 14464 name: "FCTIDZ", 14465 argLen: 1, 14466 asm: ppc64.AFCTIDZ, 14467 reg: regInfo{ 14468 inputs: []inputInfo{ 14469 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14470 }, 14471 outputs: []outputInfo{ 14472 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14473 }, 14474 }, 14475 }, 14476 { 14477 name: "FCTIWZ", 14478 argLen: 1, 14479 asm: ppc64.AFCTIWZ, 14480 reg: regInfo{ 14481 inputs: []inputInfo{ 14482 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14483 }, 14484 outputs: []outputInfo{ 14485 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14486 }, 14487 }, 14488 }, 14489 { 14490 name: "FCFID", 14491 argLen: 1, 14492 asm: ppc64.AFCFID, 14493 reg: regInfo{ 14494 inputs: []inputInfo{ 14495 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14496 }, 14497 outputs: []outputInfo{ 14498 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14499 }, 14500 }, 14501 }, 14502 { 14503 name: "FRSP", 14504 argLen: 1, 14505 asm: ppc64.AFRSP, 14506 reg: regInfo{ 14507 inputs: []inputInfo{ 14508 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14509 }, 14510 outputs: []outputInfo{ 14511 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14512 }, 14513 }, 14514 }, 14515 { 14516 name: "Xf2i64", 14517 argLen: 1, 14518 usesScratch: true, 14519 reg: regInfo{ 14520 inputs: []inputInfo{ 14521 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14522 }, 14523 outputs: []outputInfo{ 14524 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14525 }, 14526 }, 14527 }, 14528 { 14529 name: "Xi2f64", 14530 argLen: 1, 14531 usesScratch: true, 14532 reg: regInfo{ 14533 inputs: []inputInfo{ 14534 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14535 }, 14536 outputs: []outputInfo{ 14537 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14538 }, 14539 }, 14540 }, 14541 { 14542 name: "AND", 14543 argLen: 2, 14544 commutative: true, 14545 asm: ppc64.AAND, 14546 reg: regInfo{ 14547 inputs: []inputInfo{ 14548 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14549 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14550 }, 14551 outputs: []outputInfo{ 14552 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14553 }, 14554 }, 14555 }, 14556 { 14557 name: "ANDN", 14558 argLen: 2, 14559 asm: ppc64.AANDN, 14560 reg: regInfo{ 14561 inputs: []inputInfo{ 14562 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14563 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14564 }, 14565 outputs: []outputInfo{ 14566 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14567 }, 14568 }, 14569 }, 14570 { 14571 name: "OR", 14572 argLen: 2, 14573 commutative: true, 14574 asm: ppc64.AOR, 14575 reg: regInfo{ 14576 inputs: []inputInfo{ 14577 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14578 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14579 }, 14580 outputs: []outputInfo{ 14581 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14582 }, 14583 }, 14584 }, 14585 { 14586 name: "ORN", 14587 argLen: 2, 14588 asm: ppc64.AORN, 14589 reg: regInfo{ 14590 inputs: []inputInfo{ 14591 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14592 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14593 }, 14594 outputs: []outputInfo{ 14595 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14596 }, 14597 }, 14598 }, 14599 { 14600 name: "XOR", 14601 argLen: 2, 14602 commutative: true, 14603 asm: ppc64.AXOR, 14604 reg: regInfo{ 14605 inputs: []inputInfo{ 14606 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14607 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14608 }, 14609 outputs: []outputInfo{ 14610 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14611 }, 14612 }, 14613 }, 14614 { 14615 name: "EQV", 14616 argLen: 2, 14617 commutative: true, 14618 asm: ppc64.AEQV, 14619 reg: regInfo{ 14620 inputs: []inputInfo{ 14621 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14622 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14623 }, 14624 outputs: []outputInfo{ 14625 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14626 }, 14627 }, 14628 }, 14629 { 14630 name: "NEG", 14631 argLen: 1, 14632 asm: ppc64.ANEG, 14633 reg: regInfo{ 14634 inputs: []inputInfo{ 14635 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14636 }, 14637 outputs: []outputInfo{ 14638 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14639 }, 14640 }, 14641 }, 14642 { 14643 name: "FNEG", 14644 argLen: 1, 14645 asm: ppc64.AFNEG, 14646 reg: regInfo{ 14647 inputs: []inputInfo{ 14648 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14649 }, 14650 outputs: []outputInfo{ 14651 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14652 }, 14653 }, 14654 }, 14655 { 14656 name: "FSQRT", 14657 argLen: 1, 14658 asm: ppc64.AFSQRT, 14659 reg: regInfo{ 14660 inputs: []inputInfo{ 14661 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14662 }, 14663 outputs: []outputInfo{ 14664 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14665 }, 14666 }, 14667 }, 14668 { 14669 name: "FSQRTS", 14670 argLen: 1, 14671 asm: ppc64.AFSQRTS, 14672 reg: regInfo{ 14673 inputs: []inputInfo{ 14674 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14675 }, 14676 outputs: []outputInfo{ 14677 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14678 }, 14679 }, 14680 }, 14681 { 14682 name: "ORconst", 14683 auxType: auxInt64, 14684 argLen: 1, 14685 asm: ppc64.AOR, 14686 reg: regInfo{ 14687 inputs: []inputInfo{ 14688 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14689 }, 14690 outputs: []outputInfo{ 14691 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14692 }, 14693 }, 14694 }, 14695 { 14696 name: "XORconst", 14697 auxType: auxInt64, 14698 argLen: 1, 14699 asm: ppc64.AXOR, 14700 reg: regInfo{ 14701 inputs: []inputInfo{ 14702 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14703 }, 14704 outputs: []outputInfo{ 14705 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14706 }, 14707 }, 14708 }, 14709 { 14710 name: "ANDconst", 14711 auxType: auxInt64, 14712 argLen: 1, 14713 clobberFlags: true, 14714 asm: ppc64.AANDCC, 14715 reg: regInfo{ 14716 inputs: []inputInfo{ 14717 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14718 }, 14719 outputs: []outputInfo{ 14720 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14721 }, 14722 }, 14723 }, 14724 { 14725 name: "ANDCCconst", 14726 auxType: auxInt64, 14727 argLen: 1, 14728 asm: ppc64.AANDCC, 14729 reg: regInfo{ 14730 inputs: []inputInfo{ 14731 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14732 }, 14733 }, 14734 }, 14735 { 14736 name: "MOVBreg", 14737 argLen: 1, 14738 asm: ppc64.AMOVB, 14739 reg: regInfo{ 14740 inputs: []inputInfo{ 14741 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14742 }, 14743 outputs: []outputInfo{ 14744 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14745 }, 14746 }, 14747 }, 14748 { 14749 name: "MOVBZreg", 14750 argLen: 1, 14751 asm: ppc64.AMOVBZ, 14752 reg: regInfo{ 14753 inputs: []inputInfo{ 14754 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14755 }, 14756 outputs: []outputInfo{ 14757 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14758 }, 14759 }, 14760 }, 14761 { 14762 name: "MOVHreg", 14763 argLen: 1, 14764 asm: ppc64.AMOVH, 14765 reg: regInfo{ 14766 inputs: []inputInfo{ 14767 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14768 }, 14769 outputs: []outputInfo{ 14770 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14771 }, 14772 }, 14773 }, 14774 { 14775 name: "MOVHZreg", 14776 argLen: 1, 14777 asm: ppc64.AMOVHZ, 14778 reg: regInfo{ 14779 inputs: []inputInfo{ 14780 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14781 }, 14782 outputs: []outputInfo{ 14783 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14784 }, 14785 }, 14786 }, 14787 { 14788 name: "MOVWreg", 14789 argLen: 1, 14790 asm: ppc64.AMOVW, 14791 reg: regInfo{ 14792 inputs: []inputInfo{ 14793 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14794 }, 14795 outputs: []outputInfo{ 14796 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14797 }, 14798 }, 14799 }, 14800 { 14801 name: "MOVWZreg", 14802 argLen: 1, 14803 asm: ppc64.AMOVWZ, 14804 reg: regInfo{ 14805 inputs: []inputInfo{ 14806 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14807 }, 14808 outputs: []outputInfo{ 14809 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14810 }, 14811 }, 14812 }, 14813 { 14814 name: "MOVBZload", 14815 auxType: auxSymOff, 14816 argLen: 2, 14817 faultOnNilArg0: true, 14818 asm: ppc64.AMOVBZ, 14819 reg: regInfo{ 14820 inputs: []inputInfo{ 14821 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14822 }, 14823 outputs: []outputInfo{ 14824 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14825 }, 14826 }, 14827 }, 14828 { 14829 name: "MOVHload", 14830 auxType: auxSymOff, 14831 argLen: 2, 14832 faultOnNilArg0: true, 14833 asm: ppc64.AMOVH, 14834 reg: regInfo{ 14835 inputs: []inputInfo{ 14836 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14837 }, 14838 outputs: []outputInfo{ 14839 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14840 }, 14841 }, 14842 }, 14843 { 14844 name: "MOVHZload", 14845 auxType: auxSymOff, 14846 argLen: 2, 14847 faultOnNilArg0: true, 14848 asm: ppc64.AMOVHZ, 14849 reg: regInfo{ 14850 inputs: []inputInfo{ 14851 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14852 }, 14853 outputs: []outputInfo{ 14854 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14855 }, 14856 }, 14857 }, 14858 { 14859 name: "MOVWload", 14860 auxType: auxSymOff, 14861 argLen: 2, 14862 faultOnNilArg0: true, 14863 asm: ppc64.AMOVW, 14864 reg: regInfo{ 14865 inputs: []inputInfo{ 14866 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14867 }, 14868 outputs: []outputInfo{ 14869 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14870 }, 14871 }, 14872 }, 14873 { 14874 name: "MOVWZload", 14875 auxType: auxSymOff, 14876 argLen: 2, 14877 faultOnNilArg0: true, 14878 asm: ppc64.AMOVWZ, 14879 reg: regInfo{ 14880 inputs: []inputInfo{ 14881 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14882 }, 14883 outputs: []outputInfo{ 14884 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14885 }, 14886 }, 14887 }, 14888 { 14889 name: "MOVDload", 14890 auxType: auxSymOff, 14891 argLen: 2, 14892 faultOnNilArg0: true, 14893 asm: ppc64.AMOVD, 14894 reg: regInfo{ 14895 inputs: []inputInfo{ 14896 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14897 }, 14898 outputs: []outputInfo{ 14899 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14900 }, 14901 }, 14902 }, 14903 { 14904 name: "FMOVDload", 14905 auxType: auxSymOff, 14906 argLen: 2, 14907 faultOnNilArg0: true, 14908 asm: ppc64.AFMOVD, 14909 reg: regInfo{ 14910 inputs: []inputInfo{ 14911 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14912 }, 14913 outputs: []outputInfo{ 14914 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14915 }, 14916 }, 14917 }, 14918 { 14919 name: "FMOVSload", 14920 auxType: auxSymOff, 14921 argLen: 2, 14922 faultOnNilArg0: true, 14923 asm: ppc64.AFMOVS, 14924 reg: regInfo{ 14925 inputs: []inputInfo{ 14926 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14927 }, 14928 outputs: []outputInfo{ 14929 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14930 }, 14931 }, 14932 }, 14933 { 14934 name: "MOVBstore", 14935 auxType: auxSymOff, 14936 argLen: 3, 14937 faultOnNilArg0: true, 14938 asm: ppc64.AMOVB, 14939 reg: regInfo{ 14940 inputs: []inputInfo{ 14941 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14942 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14943 }, 14944 }, 14945 }, 14946 { 14947 name: "MOVHstore", 14948 auxType: auxSymOff, 14949 argLen: 3, 14950 faultOnNilArg0: true, 14951 asm: ppc64.AMOVH, 14952 reg: regInfo{ 14953 inputs: []inputInfo{ 14954 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14955 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14956 }, 14957 }, 14958 }, 14959 { 14960 name: "MOVWstore", 14961 auxType: auxSymOff, 14962 argLen: 3, 14963 faultOnNilArg0: true, 14964 asm: ppc64.AMOVW, 14965 reg: regInfo{ 14966 inputs: []inputInfo{ 14967 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14968 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14969 }, 14970 }, 14971 }, 14972 { 14973 name: "MOVDstore", 14974 auxType: auxSymOff, 14975 argLen: 3, 14976 faultOnNilArg0: true, 14977 asm: ppc64.AMOVD, 14978 reg: regInfo{ 14979 inputs: []inputInfo{ 14980 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14981 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14982 }, 14983 }, 14984 }, 14985 { 14986 name: "FMOVDstore", 14987 auxType: auxSymOff, 14988 argLen: 3, 14989 faultOnNilArg0: true, 14990 asm: ppc64.AFMOVD, 14991 reg: regInfo{ 14992 inputs: []inputInfo{ 14993 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14994 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14995 }, 14996 }, 14997 }, 14998 { 14999 name: "FMOVSstore", 15000 auxType: auxSymOff, 15001 argLen: 3, 15002 faultOnNilArg0: true, 15003 asm: ppc64.AFMOVS, 15004 reg: regInfo{ 15005 inputs: []inputInfo{ 15006 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15007 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15008 }, 15009 }, 15010 }, 15011 { 15012 name: "MOVBstorezero", 15013 auxType: auxSymOff, 15014 argLen: 2, 15015 faultOnNilArg0: true, 15016 asm: ppc64.AMOVB, 15017 reg: regInfo{ 15018 inputs: []inputInfo{ 15019 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15020 }, 15021 }, 15022 }, 15023 { 15024 name: "MOVHstorezero", 15025 auxType: auxSymOff, 15026 argLen: 2, 15027 faultOnNilArg0: true, 15028 asm: ppc64.AMOVH, 15029 reg: regInfo{ 15030 inputs: []inputInfo{ 15031 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15032 }, 15033 }, 15034 }, 15035 { 15036 name: "MOVWstorezero", 15037 auxType: auxSymOff, 15038 argLen: 2, 15039 faultOnNilArg0: true, 15040 asm: ppc64.AMOVW, 15041 reg: regInfo{ 15042 inputs: []inputInfo{ 15043 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15044 }, 15045 }, 15046 }, 15047 { 15048 name: "MOVDstorezero", 15049 auxType: auxSymOff, 15050 argLen: 2, 15051 faultOnNilArg0: true, 15052 asm: ppc64.AMOVD, 15053 reg: regInfo{ 15054 inputs: []inputInfo{ 15055 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15056 }, 15057 }, 15058 }, 15059 { 15060 name: "MOVDaddr", 15061 auxType: auxSymOff, 15062 argLen: 1, 15063 rematerializeable: true, 15064 asm: ppc64.AMOVD, 15065 reg: regInfo{ 15066 inputs: []inputInfo{ 15067 {0, 6}, // SP SB 15068 }, 15069 outputs: []outputInfo{ 15070 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15071 }, 15072 }, 15073 }, 15074 { 15075 name: "MOVDconst", 15076 auxType: auxInt64, 15077 argLen: 0, 15078 rematerializeable: true, 15079 asm: ppc64.AMOVD, 15080 reg: regInfo{ 15081 outputs: []outputInfo{ 15082 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15083 }, 15084 }, 15085 }, 15086 { 15087 name: "FMOVDconst", 15088 auxType: auxFloat64, 15089 argLen: 0, 15090 rematerializeable: true, 15091 asm: ppc64.AFMOVD, 15092 reg: regInfo{ 15093 outputs: []outputInfo{ 15094 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15095 }, 15096 }, 15097 }, 15098 { 15099 name: "FMOVSconst", 15100 auxType: auxFloat32, 15101 argLen: 0, 15102 rematerializeable: true, 15103 asm: ppc64.AFMOVS, 15104 reg: regInfo{ 15105 outputs: []outputInfo{ 15106 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15107 }, 15108 }, 15109 }, 15110 { 15111 name: "FCMPU", 15112 argLen: 2, 15113 asm: ppc64.AFCMPU, 15114 reg: regInfo{ 15115 inputs: []inputInfo{ 15116 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15117 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15118 }, 15119 }, 15120 }, 15121 { 15122 name: "CMP", 15123 argLen: 2, 15124 asm: ppc64.ACMP, 15125 reg: regInfo{ 15126 inputs: []inputInfo{ 15127 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15128 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15129 }, 15130 }, 15131 }, 15132 { 15133 name: "CMPU", 15134 argLen: 2, 15135 asm: ppc64.ACMPU, 15136 reg: regInfo{ 15137 inputs: []inputInfo{ 15138 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15139 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15140 }, 15141 }, 15142 }, 15143 { 15144 name: "CMPW", 15145 argLen: 2, 15146 asm: ppc64.ACMPW, 15147 reg: regInfo{ 15148 inputs: []inputInfo{ 15149 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15150 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15151 }, 15152 }, 15153 }, 15154 { 15155 name: "CMPWU", 15156 argLen: 2, 15157 asm: ppc64.ACMPWU, 15158 reg: regInfo{ 15159 inputs: []inputInfo{ 15160 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15161 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15162 }, 15163 }, 15164 }, 15165 { 15166 name: "CMPconst", 15167 auxType: auxInt64, 15168 argLen: 1, 15169 asm: ppc64.ACMP, 15170 reg: regInfo{ 15171 inputs: []inputInfo{ 15172 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15173 }, 15174 }, 15175 }, 15176 { 15177 name: "CMPUconst", 15178 auxType: auxInt64, 15179 argLen: 1, 15180 asm: ppc64.ACMPU, 15181 reg: regInfo{ 15182 inputs: []inputInfo{ 15183 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15184 }, 15185 }, 15186 }, 15187 { 15188 name: "CMPWconst", 15189 auxType: auxInt32, 15190 argLen: 1, 15191 asm: ppc64.ACMPW, 15192 reg: regInfo{ 15193 inputs: []inputInfo{ 15194 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15195 }, 15196 }, 15197 }, 15198 { 15199 name: "CMPWUconst", 15200 auxType: auxInt32, 15201 argLen: 1, 15202 asm: ppc64.ACMPWU, 15203 reg: regInfo{ 15204 inputs: []inputInfo{ 15205 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15206 }, 15207 }, 15208 }, 15209 { 15210 name: "Equal", 15211 argLen: 1, 15212 reg: regInfo{ 15213 outputs: []outputInfo{ 15214 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15215 }, 15216 }, 15217 }, 15218 { 15219 name: "NotEqual", 15220 argLen: 1, 15221 reg: regInfo{ 15222 outputs: []outputInfo{ 15223 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15224 }, 15225 }, 15226 }, 15227 { 15228 name: "LessThan", 15229 argLen: 1, 15230 reg: regInfo{ 15231 outputs: []outputInfo{ 15232 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15233 }, 15234 }, 15235 }, 15236 { 15237 name: "FLessThan", 15238 argLen: 1, 15239 reg: regInfo{ 15240 outputs: []outputInfo{ 15241 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15242 }, 15243 }, 15244 }, 15245 { 15246 name: "LessEqual", 15247 argLen: 1, 15248 reg: regInfo{ 15249 outputs: []outputInfo{ 15250 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15251 }, 15252 }, 15253 }, 15254 { 15255 name: "FLessEqual", 15256 argLen: 1, 15257 reg: regInfo{ 15258 outputs: []outputInfo{ 15259 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15260 }, 15261 }, 15262 }, 15263 { 15264 name: "GreaterThan", 15265 argLen: 1, 15266 reg: regInfo{ 15267 outputs: []outputInfo{ 15268 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15269 }, 15270 }, 15271 }, 15272 { 15273 name: "FGreaterThan", 15274 argLen: 1, 15275 reg: regInfo{ 15276 outputs: []outputInfo{ 15277 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15278 }, 15279 }, 15280 }, 15281 { 15282 name: "GreaterEqual", 15283 argLen: 1, 15284 reg: regInfo{ 15285 outputs: []outputInfo{ 15286 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15287 }, 15288 }, 15289 }, 15290 { 15291 name: "FGreaterEqual", 15292 argLen: 1, 15293 reg: regInfo{ 15294 outputs: []outputInfo{ 15295 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15296 }, 15297 }, 15298 }, 15299 { 15300 name: "LoweredGetClosurePtr", 15301 argLen: 0, 15302 reg: regInfo{ 15303 outputs: []outputInfo{ 15304 {0, 2048}, // R11 15305 }, 15306 }, 15307 }, 15308 { 15309 name: "LoweredNilCheck", 15310 argLen: 2, 15311 clobberFlags: true, 15312 nilCheck: true, 15313 faultOnNilArg0: true, 15314 reg: regInfo{ 15315 inputs: []inputInfo{ 15316 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15317 }, 15318 clobbers: 2147483648, // R31 15319 }, 15320 }, 15321 { 15322 name: "MOVDconvert", 15323 argLen: 2, 15324 asm: ppc64.AMOVD, 15325 reg: regInfo{ 15326 inputs: []inputInfo{ 15327 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15328 }, 15329 outputs: []outputInfo{ 15330 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15331 }, 15332 }, 15333 }, 15334 { 15335 name: "CALLstatic", 15336 auxType: auxSymOff, 15337 argLen: 1, 15338 clobberFlags: true, 15339 call: true, 15340 reg: regInfo{ 15341 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15342 }, 15343 }, 15344 { 15345 name: "CALLclosure", 15346 auxType: auxInt64, 15347 argLen: 3, 15348 clobberFlags: true, 15349 call: true, 15350 reg: regInfo{ 15351 inputs: []inputInfo{ 15352 {1, 2048}, // R11 15353 {0, 1073733626}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15354 }, 15355 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15356 }, 15357 }, 15358 { 15359 name: "CALLdefer", 15360 auxType: auxInt64, 15361 argLen: 1, 15362 clobberFlags: true, 15363 call: true, 15364 reg: regInfo{ 15365 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15366 }, 15367 }, 15368 { 15369 name: "CALLgo", 15370 auxType: auxInt64, 15371 argLen: 1, 15372 clobberFlags: true, 15373 call: true, 15374 reg: regInfo{ 15375 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15376 }, 15377 }, 15378 { 15379 name: "CALLinter", 15380 auxType: auxInt64, 15381 argLen: 2, 15382 clobberFlags: true, 15383 call: true, 15384 reg: regInfo{ 15385 inputs: []inputInfo{ 15386 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15387 }, 15388 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15389 }, 15390 }, 15391 { 15392 name: "LoweredZero", 15393 auxType: auxInt64, 15394 argLen: 3, 15395 clobberFlags: true, 15396 faultOnNilArg0: true, 15397 reg: regInfo{ 15398 inputs: []inputInfo{ 15399 {0, 8}, // R3 15400 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15401 }, 15402 clobbers: 8, // R3 15403 }, 15404 }, 15405 { 15406 name: "LoweredMove", 15407 auxType: auxInt64, 15408 argLen: 4, 15409 clobberFlags: true, 15410 faultOnNilArg0: true, 15411 faultOnNilArg1: true, 15412 reg: regInfo{ 15413 inputs: []inputInfo{ 15414 {0, 8}, // R3 15415 {1, 16}, // R4 15416 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15417 }, 15418 clobbers: 24, // R3 R4 15419 }, 15420 }, 15421 { 15422 name: "InvertFlags", 15423 argLen: 1, 15424 reg: regInfo{}, 15425 }, 15426 { 15427 name: "FlagEQ", 15428 argLen: 0, 15429 reg: regInfo{}, 15430 }, 15431 { 15432 name: "FlagLT", 15433 argLen: 0, 15434 reg: regInfo{}, 15435 }, 15436 { 15437 name: "FlagGT", 15438 argLen: 0, 15439 reg: regInfo{}, 15440 }, 15441 15442 { 15443 name: "FADDS", 15444 argLen: 2, 15445 commutative: true, 15446 resultInArg0: true, 15447 clobberFlags: true, 15448 asm: s390x.AFADDS, 15449 reg: regInfo{ 15450 inputs: []inputInfo{ 15451 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15452 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15453 }, 15454 outputs: []outputInfo{ 15455 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15456 }, 15457 }, 15458 }, 15459 { 15460 name: "FADD", 15461 argLen: 2, 15462 commutative: true, 15463 resultInArg0: true, 15464 clobberFlags: true, 15465 asm: s390x.AFADD, 15466 reg: regInfo{ 15467 inputs: []inputInfo{ 15468 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15469 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15470 }, 15471 outputs: []outputInfo{ 15472 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15473 }, 15474 }, 15475 }, 15476 { 15477 name: "FSUBS", 15478 argLen: 2, 15479 resultInArg0: true, 15480 clobberFlags: true, 15481 asm: s390x.AFSUBS, 15482 reg: regInfo{ 15483 inputs: []inputInfo{ 15484 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15485 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15486 }, 15487 outputs: []outputInfo{ 15488 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15489 }, 15490 }, 15491 }, 15492 { 15493 name: "FSUB", 15494 argLen: 2, 15495 resultInArg0: true, 15496 clobberFlags: true, 15497 asm: s390x.AFSUB, 15498 reg: regInfo{ 15499 inputs: []inputInfo{ 15500 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15501 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15502 }, 15503 outputs: []outputInfo{ 15504 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15505 }, 15506 }, 15507 }, 15508 { 15509 name: "FMULS", 15510 argLen: 2, 15511 commutative: true, 15512 resultInArg0: true, 15513 asm: s390x.AFMULS, 15514 reg: regInfo{ 15515 inputs: []inputInfo{ 15516 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15517 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15518 }, 15519 outputs: []outputInfo{ 15520 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15521 }, 15522 }, 15523 }, 15524 { 15525 name: "FMUL", 15526 argLen: 2, 15527 commutative: true, 15528 resultInArg0: true, 15529 asm: s390x.AFMUL, 15530 reg: regInfo{ 15531 inputs: []inputInfo{ 15532 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15533 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15534 }, 15535 outputs: []outputInfo{ 15536 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15537 }, 15538 }, 15539 }, 15540 { 15541 name: "FDIVS", 15542 argLen: 2, 15543 resultInArg0: true, 15544 asm: s390x.AFDIVS, 15545 reg: regInfo{ 15546 inputs: []inputInfo{ 15547 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15548 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15549 }, 15550 outputs: []outputInfo{ 15551 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15552 }, 15553 }, 15554 }, 15555 { 15556 name: "FDIV", 15557 argLen: 2, 15558 resultInArg0: true, 15559 asm: s390x.AFDIV, 15560 reg: regInfo{ 15561 inputs: []inputInfo{ 15562 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15563 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15564 }, 15565 outputs: []outputInfo{ 15566 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15567 }, 15568 }, 15569 }, 15570 { 15571 name: "FNEGS", 15572 argLen: 1, 15573 clobberFlags: true, 15574 asm: s390x.AFNEGS, 15575 reg: regInfo{ 15576 inputs: []inputInfo{ 15577 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15578 }, 15579 outputs: []outputInfo{ 15580 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15581 }, 15582 }, 15583 }, 15584 { 15585 name: "FNEG", 15586 argLen: 1, 15587 clobberFlags: true, 15588 asm: s390x.AFNEG, 15589 reg: regInfo{ 15590 inputs: []inputInfo{ 15591 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15592 }, 15593 outputs: []outputInfo{ 15594 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15595 }, 15596 }, 15597 }, 15598 { 15599 name: "FMOVSload", 15600 auxType: auxSymOff, 15601 argLen: 2, 15602 faultOnNilArg0: true, 15603 asm: s390x.AFMOVS, 15604 reg: regInfo{ 15605 inputs: []inputInfo{ 15606 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 15607 }, 15608 outputs: []outputInfo{ 15609 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15610 }, 15611 }, 15612 }, 15613 { 15614 name: "FMOVDload", 15615 auxType: auxSymOff, 15616 argLen: 2, 15617 faultOnNilArg0: true, 15618 asm: s390x.AFMOVD, 15619 reg: regInfo{ 15620 inputs: []inputInfo{ 15621 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 15622 }, 15623 outputs: []outputInfo{ 15624 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15625 }, 15626 }, 15627 }, 15628 { 15629 name: "FMOVSconst", 15630 auxType: auxFloat32, 15631 argLen: 0, 15632 rematerializeable: true, 15633 asm: s390x.AFMOVS, 15634 reg: regInfo{ 15635 outputs: []outputInfo{ 15636 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15637 }, 15638 }, 15639 }, 15640 { 15641 name: "FMOVDconst", 15642 auxType: auxFloat64, 15643 argLen: 0, 15644 rematerializeable: true, 15645 asm: s390x.AFMOVD, 15646 reg: regInfo{ 15647 outputs: []outputInfo{ 15648 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15649 }, 15650 }, 15651 }, 15652 { 15653 name: "FMOVSloadidx", 15654 auxType: auxSymOff, 15655 argLen: 3, 15656 asm: s390x.AFMOVS, 15657 reg: regInfo{ 15658 inputs: []inputInfo{ 15659 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 15660 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 15661 }, 15662 outputs: []outputInfo{ 15663 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15664 }, 15665 }, 15666 }, 15667 { 15668 name: "FMOVDloadidx", 15669 auxType: auxSymOff, 15670 argLen: 3, 15671 asm: s390x.AFMOVD, 15672 reg: regInfo{ 15673 inputs: []inputInfo{ 15674 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 15675 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 15676 }, 15677 outputs: []outputInfo{ 15678 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15679 }, 15680 }, 15681 }, 15682 { 15683 name: "FMOVSstore", 15684 auxType: auxSymOff, 15685 argLen: 3, 15686 faultOnNilArg0: true, 15687 asm: s390x.AFMOVS, 15688 reg: regInfo{ 15689 inputs: []inputInfo{ 15690 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 15691 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15692 }, 15693 }, 15694 }, 15695 { 15696 name: "FMOVDstore", 15697 auxType: auxSymOff, 15698 argLen: 3, 15699 faultOnNilArg0: true, 15700 asm: s390x.AFMOVD, 15701 reg: regInfo{ 15702 inputs: []inputInfo{ 15703 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 15704 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15705 }, 15706 }, 15707 }, 15708 { 15709 name: "FMOVSstoreidx", 15710 auxType: auxSymOff, 15711 argLen: 4, 15712 asm: s390x.AFMOVS, 15713 reg: regInfo{ 15714 inputs: []inputInfo{ 15715 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 15716 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 15717 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15718 }, 15719 }, 15720 }, 15721 { 15722 name: "FMOVDstoreidx", 15723 auxType: auxSymOff, 15724 argLen: 4, 15725 asm: s390x.AFMOVD, 15726 reg: regInfo{ 15727 inputs: []inputInfo{ 15728 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 15729 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 15730 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15731 }, 15732 }, 15733 }, 15734 { 15735 name: "ADD", 15736 argLen: 2, 15737 commutative: true, 15738 clobberFlags: true, 15739 asm: s390x.AADD, 15740 reg: regInfo{ 15741 inputs: []inputInfo{ 15742 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15743 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 15744 }, 15745 outputs: []outputInfo{ 15746 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15747 }, 15748 }, 15749 }, 15750 { 15751 name: "ADDW", 15752 argLen: 2, 15753 commutative: true, 15754 clobberFlags: true, 15755 asm: s390x.AADDW, 15756 reg: regInfo{ 15757 inputs: []inputInfo{ 15758 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15759 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 15760 }, 15761 outputs: []outputInfo{ 15762 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15763 }, 15764 }, 15765 }, 15766 { 15767 name: "ADDconst", 15768 auxType: auxInt64, 15769 argLen: 1, 15770 clobberFlags: true, 15771 asm: s390x.AADD, 15772 reg: regInfo{ 15773 inputs: []inputInfo{ 15774 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 15775 }, 15776 outputs: []outputInfo{ 15777 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15778 }, 15779 }, 15780 }, 15781 { 15782 name: "ADDWconst", 15783 auxType: auxInt32, 15784 argLen: 1, 15785 clobberFlags: true, 15786 asm: s390x.AADDW, 15787 reg: regInfo{ 15788 inputs: []inputInfo{ 15789 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 15790 }, 15791 outputs: []outputInfo{ 15792 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15793 }, 15794 }, 15795 }, 15796 { 15797 name: "ADDload", 15798 auxType: auxSymOff, 15799 argLen: 3, 15800 resultInArg0: true, 15801 clobberFlags: true, 15802 faultOnNilArg1: true, 15803 asm: s390x.AADD, 15804 reg: regInfo{ 15805 inputs: []inputInfo{ 15806 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15807 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 15808 }, 15809 outputs: []outputInfo{ 15810 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15811 }, 15812 }, 15813 }, 15814 { 15815 name: "ADDWload", 15816 auxType: auxSymOff, 15817 argLen: 3, 15818 resultInArg0: true, 15819 clobberFlags: true, 15820 faultOnNilArg1: true, 15821 asm: s390x.AADDW, 15822 reg: regInfo{ 15823 inputs: []inputInfo{ 15824 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15825 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 15826 }, 15827 outputs: []outputInfo{ 15828 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15829 }, 15830 }, 15831 }, 15832 { 15833 name: "SUB", 15834 argLen: 2, 15835 clobberFlags: true, 15836 asm: s390x.ASUB, 15837 reg: regInfo{ 15838 inputs: []inputInfo{ 15839 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15840 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15841 }, 15842 outputs: []outputInfo{ 15843 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15844 }, 15845 }, 15846 }, 15847 { 15848 name: "SUBW", 15849 argLen: 2, 15850 clobberFlags: true, 15851 asm: s390x.ASUBW, 15852 reg: regInfo{ 15853 inputs: []inputInfo{ 15854 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15855 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15856 }, 15857 outputs: []outputInfo{ 15858 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15859 }, 15860 }, 15861 }, 15862 { 15863 name: "SUBconst", 15864 auxType: auxInt64, 15865 argLen: 1, 15866 resultInArg0: true, 15867 clobberFlags: true, 15868 asm: s390x.ASUB, 15869 reg: regInfo{ 15870 inputs: []inputInfo{ 15871 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15872 }, 15873 outputs: []outputInfo{ 15874 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15875 }, 15876 }, 15877 }, 15878 { 15879 name: "SUBWconst", 15880 auxType: auxInt32, 15881 argLen: 1, 15882 resultInArg0: true, 15883 clobberFlags: true, 15884 asm: s390x.ASUBW, 15885 reg: regInfo{ 15886 inputs: []inputInfo{ 15887 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15888 }, 15889 outputs: []outputInfo{ 15890 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15891 }, 15892 }, 15893 }, 15894 { 15895 name: "SUBload", 15896 auxType: auxSymOff, 15897 argLen: 3, 15898 resultInArg0: true, 15899 clobberFlags: true, 15900 faultOnNilArg1: true, 15901 asm: s390x.ASUB, 15902 reg: regInfo{ 15903 inputs: []inputInfo{ 15904 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15905 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 15906 }, 15907 outputs: []outputInfo{ 15908 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15909 }, 15910 }, 15911 }, 15912 { 15913 name: "SUBWload", 15914 auxType: auxSymOff, 15915 argLen: 3, 15916 resultInArg0: true, 15917 clobberFlags: true, 15918 faultOnNilArg1: true, 15919 asm: s390x.ASUBW, 15920 reg: regInfo{ 15921 inputs: []inputInfo{ 15922 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15923 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 15924 }, 15925 outputs: []outputInfo{ 15926 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15927 }, 15928 }, 15929 }, 15930 { 15931 name: "MULLD", 15932 argLen: 2, 15933 commutative: true, 15934 resultInArg0: true, 15935 clobberFlags: true, 15936 asm: s390x.AMULLD, 15937 reg: regInfo{ 15938 inputs: []inputInfo{ 15939 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15940 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15941 }, 15942 outputs: []outputInfo{ 15943 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15944 }, 15945 }, 15946 }, 15947 { 15948 name: "MULLW", 15949 argLen: 2, 15950 commutative: true, 15951 resultInArg0: true, 15952 clobberFlags: true, 15953 asm: s390x.AMULLW, 15954 reg: regInfo{ 15955 inputs: []inputInfo{ 15956 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15957 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15958 }, 15959 outputs: []outputInfo{ 15960 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15961 }, 15962 }, 15963 }, 15964 { 15965 name: "MULLDconst", 15966 auxType: auxInt64, 15967 argLen: 1, 15968 resultInArg0: true, 15969 clobberFlags: true, 15970 asm: s390x.AMULLD, 15971 reg: regInfo{ 15972 inputs: []inputInfo{ 15973 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15974 }, 15975 outputs: []outputInfo{ 15976 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15977 }, 15978 }, 15979 }, 15980 { 15981 name: "MULLWconst", 15982 auxType: auxInt32, 15983 argLen: 1, 15984 resultInArg0: true, 15985 clobberFlags: true, 15986 asm: s390x.AMULLW, 15987 reg: regInfo{ 15988 inputs: []inputInfo{ 15989 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15990 }, 15991 outputs: []outputInfo{ 15992 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15993 }, 15994 }, 15995 }, 15996 { 15997 name: "MULLDload", 15998 auxType: auxSymOff, 15999 argLen: 3, 16000 resultInArg0: true, 16001 clobberFlags: true, 16002 faultOnNilArg1: true, 16003 asm: s390x.AMULLD, 16004 reg: regInfo{ 16005 inputs: []inputInfo{ 16006 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16007 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16008 }, 16009 outputs: []outputInfo{ 16010 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16011 }, 16012 }, 16013 }, 16014 { 16015 name: "MULLWload", 16016 auxType: auxSymOff, 16017 argLen: 3, 16018 resultInArg0: true, 16019 clobberFlags: true, 16020 faultOnNilArg1: true, 16021 asm: s390x.AMULLW, 16022 reg: regInfo{ 16023 inputs: []inputInfo{ 16024 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16025 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16026 }, 16027 outputs: []outputInfo{ 16028 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16029 }, 16030 }, 16031 }, 16032 { 16033 name: "MULHD", 16034 argLen: 2, 16035 resultInArg0: true, 16036 clobberFlags: true, 16037 asm: s390x.AMULHD, 16038 reg: regInfo{ 16039 inputs: []inputInfo{ 16040 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16041 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16042 }, 16043 outputs: []outputInfo{ 16044 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16045 }, 16046 }, 16047 }, 16048 { 16049 name: "MULHDU", 16050 argLen: 2, 16051 resultInArg0: true, 16052 clobberFlags: true, 16053 asm: s390x.AMULHDU, 16054 reg: regInfo{ 16055 inputs: []inputInfo{ 16056 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16057 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16058 }, 16059 outputs: []outputInfo{ 16060 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16061 }, 16062 }, 16063 }, 16064 { 16065 name: "DIVD", 16066 argLen: 2, 16067 resultInArg0: true, 16068 clobberFlags: true, 16069 asm: s390x.ADIVD, 16070 reg: regInfo{ 16071 inputs: []inputInfo{ 16072 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16073 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16074 }, 16075 outputs: []outputInfo{ 16076 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16077 }, 16078 }, 16079 }, 16080 { 16081 name: "DIVW", 16082 argLen: 2, 16083 resultInArg0: true, 16084 clobberFlags: true, 16085 asm: s390x.ADIVW, 16086 reg: regInfo{ 16087 inputs: []inputInfo{ 16088 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16089 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16090 }, 16091 outputs: []outputInfo{ 16092 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16093 }, 16094 }, 16095 }, 16096 { 16097 name: "DIVDU", 16098 argLen: 2, 16099 resultInArg0: true, 16100 clobberFlags: true, 16101 asm: s390x.ADIVDU, 16102 reg: regInfo{ 16103 inputs: []inputInfo{ 16104 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16105 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16106 }, 16107 outputs: []outputInfo{ 16108 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16109 }, 16110 }, 16111 }, 16112 { 16113 name: "DIVWU", 16114 argLen: 2, 16115 resultInArg0: true, 16116 clobberFlags: true, 16117 asm: s390x.ADIVWU, 16118 reg: regInfo{ 16119 inputs: []inputInfo{ 16120 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16121 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16122 }, 16123 outputs: []outputInfo{ 16124 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16125 }, 16126 }, 16127 }, 16128 { 16129 name: "MODD", 16130 argLen: 2, 16131 resultInArg0: true, 16132 clobberFlags: true, 16133 asm: s390x.AMODD, 16134 reg: regInfo{ 16135 inputs: []inputInfo{ 16136 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16137 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16138 }, 16139 outputs: []outputInfo{ 16140 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16141 }, 16142 }, 16143 }, 16144 { 16145 name: "MODW", 16146 argLen: 2, 16147 resultInArg0: true, 16148 clobberFlags: true, 16149 asm: s390x.AMODW, 16150 reg: regInfo{ 16151 inputs: []inputInfo{ 16152 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16153 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16154 }, 16155 outputs: []outputInfo{ 16156 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16157 }, 16158 }, 16159 }, 16160 { 16161 name: "MODDU", 16162 argLen: 2, 16163 resultInArg0: true, 16164 clobberFlags: true, 16165 asm: s390x.AMODDU, 16166 reg: regInfo{ 16167 inputs: []inputInfo{ 16168 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16169 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16170 }, 16171 outputs: []outputInfo{ 16172 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16173 }, 16174 }, 16175 }, 16176 { 16177 name: "MODWU", 16178 argLen: 2, 16179 resultInArg0: true, 16180 clobberFlags: true, 16181 asm: s390x.AMODWU, 16182 reg: regInfo{ 16183 inputs: []inputInfo{ 16184 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16185 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16186 }, 16187 outputs: []outputInfo{ 16188 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16189 }, 16190 }, 16191 }, 16192 { 16193 name: "AND", 16194 argLen: 2, 16195 commutative: true, 16196 clobberFlags: true, 16197 asm: s390x.AAND, 16198 reg: regInfo{ 16199 inputs: []inputInfo{ 16200 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16201 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16202 }, 16203 outputs: []outputInfo{ 16204 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16205 }, 16206 }, 16207 }, 16208 { 16209 name: "ANDW", 16210 argLen: 2, 16211 commutative: true, 16212 clobberFlags: true, 16213 asm: s390x.AANDW, 16214 reg: regInfo{ 16215 inputs: []inputInfo{ 16216 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16217 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16218 }, 16219 outputs: []outputInfo{ 16220 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16221 }, 16222 }, 16223 }, 16224 { 16225 name: "ANDconst", 16226 auxType: auxInt64, 16227 argLen: 1, 16228 resultInArg0: true, 16229 clobberFlags: true, 16230 asm: s390x.AAND, 16231 reg: regInfo{ 16232 inputs: []inputInfo{ 16233 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16234 }, 16235 outputs: []outputInfo{ 16236 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16237 }, 16238 }, 16239 }, 16240 { 16241 name: "ANDWconst", 16242 auxType: auxInt32, 16243 argLen: 1, 16244 resultInArg0: true, 16245 clobberFlags: true, 16246 asm: s390x.AANDW, 16247 reg: regInfo{ 16248 inputs: []inputInfo{ 16249 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16250 }, 16251 outputs: []outputInfo{ 16252 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16253 }, 16254 }, 16255 }, 16256 { 16257 name: "ANDload", 16258 auxType: auxSymOff, 16259 argLen: 3, 16260 resultInArg0: true, 16261 clobberFlags: true, 16262 faultOnNilArg1: true, 16263 asm: s390x.AAND, 16264 reg: regInfo{ 16265 inputs: []inputInfo{ 16266 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16267 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16268 }, 16269 outputs: []outputInfo{ 16270 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16271 }, 16272 }, 16273 }, 16274 { 16275 name: "ANDWload", 16276 auxType: auxSymOff, 16277 argLen: 3, 16278 resultInArg0: true, 16279 clobberFlags: true, 16280 faultOnNilArg1: true, 16281 asm: s390x.AANDW, 16282 reg: regInfo{ 16283 inputs: []inputInfo{ 16284 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16285 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16286 }, 16287 outputs: []outputInfo{ 16288 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16289 }, 16290 }, 16291 }, 16292 { 16293 name: "OR", 16294 argLen: 2, 16295 commutative: true, 16296 clobberFlags: true, 16297 asm: s390x.AOR, 16298 reg: regInfo{ 16299 inputs: []inputInfo{ 16300 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16301 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16302 }, 16303 outputs: []outputInfo{ 16304 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16305 }, 16306 }, 16307 }, 16308 { 16309 name: "ORW", 16310 argLen: 2, 16311 commutative: true, 16312 clobberFlags: true, 16313 asm: s390x.AORW, 16314 reg: regInfo{ 16315 inputs: []inputInfo{ 16316 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16317 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16318 }, 16319 outputs: []outputInfo{ 16320 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16321 }, 16322 }, 16323 }, 16324 { 16325 name: "ORconst", 16326 auxType: auxInt64, 16327 argLen: 1, 16328 resultInArg0: true, 16329 clobberFlags: true, 16330 asm: s390x.AOR, 16331 reg: regInfo{ 16332 inputs: []inputInfo{ 16333 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16334 }, 16335 outputs: []outputInfo{ 16336 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16337 }, 16338 }, 16339 }, 16340 { 16341 name: "ORWconst", 16342 auxType: auxInt32, 16343 argLen: 1, 16344 resultInArg0: true, 16345 clobberFlags: true, 16346 asm: s390x.AORW, 16347 reg: regInfo{ 16348 inputs: []inputInfo{ 16349 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16350 }, 16351 outputs: []outputInfo{ 16352 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16353 }, 16354 }, 16355 }, 16356 { 16357 name: "ORload", 16358 auxType: auxSymOff, 16359 argLen: 3, 16360 resultInArg0: true, 16361 clobberFlags: true, 16362 faultOnNilArg1: true, 16363 asm: s390x.AOR, 16364 reg: regInfo{ 16365 inputs: []inputInfo{ 16366 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16367 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16368 }, 16369 outputs: []outputInfo{ 16370 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16371 }, 16372 }, 16373 }, 16374 { 16375 name: "ORWload", 16376 auxType: auxSymOff, 16377 argLen: 3, 16378 resultInArg0: true, 16379 clobberFlags: true, 16380 faultOnNilArg1: true, 16381 asm: s390x.AORW, 16382 reg: regInfo{ 16383 inputs: []inputInfo{ 16384 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16385 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16386 }, 16387 outputs: []outputInfo{ 16388 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16389 }, 16390 }, 16391 }, 16392 { 16393 name: "XOR", 16394 argLen: 2, 16395 commutative: true, 16396 clobberFlags: true, 16397 asm: s390x.AXOR, 16398 reg: regInfo{ 16399 inputs: []inputInfo{ 16400 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16401 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16402 }, 16403 outputs: []outputInfo{ 16404 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16405 }, 16406 }, 16407 }, 16408 { 16409 name: "XORW", 16410 argLen: 2, 16411 commutative: true, 16412 clobberFlags: true, 16413 asm: s390x.AXORW, 16414 reg: regInfo{ 16415 inputs: []inputInfo{ 16416 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16417 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16418 }, 16419 outputs: []outputInfo{ 16420 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16421 }, 16422 }, 16423 }, 16424 { 16425 name: "XORconst", 16426 auxType: auxInt64, 16427 argLen: 1, 16428 resultInArg0: true, 16429 clobberFlags: true, 16430 asm: s390x.AXOR, 16431 reg: regInfo{ 16432 inputs: []inputInfo{ 16433 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16434 }, 16435 outputs: []outputInfo{ 16436 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16437 }, 16438 }, 16439 }, 16440 { 16441 name: "XORWconst", 16442 auxType: auxInt32, 16443 argLen: 1, 16444 resultInArg0: true, 16445 clobberFlags: true, 16446 asm: s390x.AXORW, 16447 reg: regInfo{ 16448 inputs: []inputInfo{ 16449 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16450 }, 16451 outputs: []outputInfo{ 16452 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16453 }, 16454 }, 16455 }, 16456 { 16457 name: "XORload", 16458 auxType: auxSymOff, 16459 argLen: 3, 16460 resultInArg0: true, 16461 clobberFlags: true, 16462 faultOnNilArg1: true, 16463 asm: s390x.AXOR, 16464 reg: regInfo{ 16465 inputs: []inputInfo{ 16466 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16467 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16468 }, 16469 outputs: []outputInfo{ 16470 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16471 }, 16472 }, 16473 }, 16474 { 16475 name: "XORWload", 16476 auxType: auxSymOff, 16477 argLen: 3, 16478 resultInArg0: true, 16479 clobberFlags: true, 16480 faultOnNilArg1: true, 16481 asm: s390x.AXORW, 16482 reg: regInfo{ 16483 inputs: []inputInfo{ 16484 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16485 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16486 }, 16487 outputs: []outputInfo{ 16488 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16489 }, 16490 }, 16491 }, 16492 { 16493 name: "CMP", 16494 argLen: 2, 16495 asm: s390x.ACMP, 16496 reg: regInfo{ 16497 inputs: []inputInfo{ 16498 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16499 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16500 }, 16501 }, 16502 }, 16503 { 16504 name: "CMPW", 16505 argLen: 2, 16506 asm: s390x.ACMPW, 16507 reg: regInfo{ 16508 inputs: []inputInfo{ 16509 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16510 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16511 }, 16512 }, 16513 }, 16514 { 16515 name: "CMPU", 16516 argLen: 2, 16517 asm: s390x.ACMPU, 16518 reg: regInfo{ 16519 inputs: []inputInfo{ 16520 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16521 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16522 }, 16523 }, 16524 }, 16525 { 16526 name: "CMPWU", 16527 argLen: 2, 16528 asm: s390x.ACMPWU, 16529 reg: regInfo{ 16530 inputs: []inputInfo{ 16531 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16532 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16533 }, 16534 }, 16535 }, 16536 { 16537 name: "CMPconst", 16538 auxType: auxInt64, 16539 argLen: 1, 16540 asm: s390x.ACMP, 16541 reg: regInfo{ 16542 inputs: []inputInfo{ 16543 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16544 }, 16545 }, 16546 }, 16547 { 16548 name: "CMPWconst", 16549 auxType: auxInt32, 16550 argLen: 1, 16551 asm: s390x.ACMPW, 16552 reg: regInfo{ 16553 inputs: []inputInfo{ 16554 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16555 }, 16556 }, 16557 }, 16558 { 16559 name: "CMPUconst", 16560 auxType: auxInt64, 16561 argLen: 1, 16562 asm: s390x.ACMPU, 16563 reg: regInfo{ 16564 inputs: []inputInfo{ 16565 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16566 }, 16567 }, 16568 }, 16569 { 16570 name: "CMPWUconst", 16571 auxType: auxInt32, 16572 argLen: 1, 16573 asm: s390x.ACMPWU, 16574 reg: regInfo{ 16575 inputs: []inputInfo{ 16576 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 16577 }, 16578 }, 16579 }, 16580 { 16581 name: "FCMPS", 16582 argLen: 2, 16583 asm: s390x.ACEBR, 16584 reg: regInfo{ 16585 inputs: []inputInfo{ 16586 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16587 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16588 }, 16589 }, 16590 }, 16591 { 16592 name: "FCMP", 16593 argLen: 2, 16594 asm: s390x.AFCMPU, 16595 reg: regInfo{ 16596 inputs: []inputInfo{ 16597 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16598 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16599 }, 16600 }, 16601 }, 16602 { 16603 name: "SLD", 16604 argLen: 2, 16605 asm: s390x.ASLD, 16606 reg: regInfo{ 16607 inputs: []inputInfo{ 16608 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16609 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16610 }, 16611 outputs: []outputInfo{ 16612 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16613 }, 16614 }, 16615 }, 16616 { 16617 name: "SLW", 16618 argLen: 2, 16619 asm: s390x.ASLW, 16620 reg: regInfo{ 16621 inputs: []inputInfo{ 16622 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16623 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16624 }, 16625 outputs: []outputInfo{ 16626 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16627 }, 16628 }, 16629 }, 16630 { 16631 name: "SLDconst", 16632 auxType: auxInt64, 16633 argLen: 1, 16634 asm: s390x.ASLD, 16635 reg: regInfo{ 16636 inputs: []inputInfo{ 16637 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16638 }, 16639 outputs: []outputInfo{ 16640 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16641 }, 16642 }, 16643 }, 16644 { 16645 name: "SLWconst", 16646 auxType: auxInt32, 16647 argLen: 1, 16648 asm: s390x.ASLW, 16649 reg: regInfo{ 16650 inputs: []inputInfo{ 16651 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16652 }, 16653 outputs: []outputInfo{ 16654 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16655 }, 16656 }, 16657 }, 16658 { 16659 name: "SRD", 16660 argLen: 2, 16661 asm: s390x.ASRD, 16662 reg: regInfo{ 16663 inputs: []inputInfo{ 16664 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16665 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16666 }, 16667 outputs: []outputInfo{ 16668 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16669 }, 16670 }, 16671 }, 16672 { 16673 name: "SRW", 16674 argLen: 2, 16675 asm: s390x.ASRW, 16676 reg: regInfo{ 16677 inputs: []inputInfo{ 16678 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16679 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16680 }, 16681 outputs: []outputInfo{ 16682 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16683 }, 16684 }, 16685 }, 16686 { 16687 name: "SRDconst", 16688 auxType: auxInt64, 16689 argLen: 1, 16690 asm: s390x.ASRD, 16691 reg: regInfo{ 16692 inputs: []inputInfo{ 16693 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16694 }, 16695 outputs: []outputInfo{ 16696 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16697 }, 16698 }, 16699 }, 16700 { 16701 name: "SRWconst", 16702 auxType: auxInt32, 16703 argLen: 1, 16704 asm: s390x.ASRW, 16705 reg: regInfo{ 16706 inputs: []inputInfo{ 16707 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16708 }, 16709 outputs: []outputInfo{ 16710 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16711 }, 16712 }, 16713 }, 16714 { 16715 name: "SRAD", 16716 argLen: 2, 16717 clobberFlags: true, 16718 asm: s390x.ASRAD, 16719 reg: regInfo{ 16720 inputs: []inputInfo{ 16721 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16722 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16723 }, 16724 outputs: []outputInfo{ 16725 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16726 }, 16727 }, 16728 }, 16729 { 16730 name: "SRAW", 16731 argLen: 2, 16732 clobberFlags: true, 16733 asm: s390x.ASRAW, 16734 reg: regInfo{ 16735 inputs: []inputInfo{ 16736 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16737 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16738 }, 16739 outputs: []outputInfo{ 16740 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16741 }, 16742 }, 16743 }, 16744 { 16745 name: "SRADconst", 16746 auxType: auxInt64, 16747 argLen: 1, 16748 clobberFlags: true, 16749 asm: s390x.ASRAD, 16750 reg: regInfo{ 16751 inputs: []inputInfo{ 16752 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16753 }, 16754 outputs: []outputInfo{ 16755 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16756 }, 16757 }, 16758 }, 16759 { 16760 name: "SRAWconst", 16761 auxType: auxInt32, 16762 argLen: 1, 16763 clobberFlags: true, 16764 asm: s390x.ASRAW, 16765 reg: regInfo{ 16766 inputs: []inputInfo{ 16767 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16768 }, 16769 outputs: []outputInfo{ 16770 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16771 }, 16772 }, 16773 }, 16774 { 16775 name: "RLLGconst", 16776 auxType: auxInt64, 16777 argLen: 1, 16778 asm: s390x.ARLLG, 16779 reg: regInfo{ 16780 inputs: []inputInfo{ 16781 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16782 }, 16783 outputs: []outputInfo{ 16784 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16785 }, 16786 }, 16787 }, 16788 { 16789 name: "RLLconst", 16790 auxType: auxInt32, 16791 argLen: 1, 16792 asm: s390x.ARLL, 16793 reg: regInfo{ 16794 inputs: []inputInfo{ 16795 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16796 }, 16797 outputs: []outputInfo{ 16798 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16799 }, 16800 }, 16801 }, 16802 { 16803 name: "NEG", 16804 argLen: 1, 16805 clobberFlags: true, 16806 asm: s390x.ANEG, 16807 reg: regInfo{ 16808 inputs: []inputInfo{ 16809 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16810 }, 16811 outputs: []outputInfo{ 16812 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16813 }, 16814 }, 16815 }, 16816 { 16817 name: "NEGW", 16818 argLen: 1, 16819 clobberFlags: true, 16820 asm: s390x.ANEGW, 16821 reg: regInfo{ 16822 inputs: []inputInfo{ 16823 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16824 }, 16825 outputs: []outputInfo{ 16826 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16827 }, 16828 }, 16829 }, 16830 { 16831 name: "NOT", 16832 argLen: 1, 16833 resultInArg0: true, 16834 clobberFlags: true, 16835 reg: regInfo{ 16836 inputs: []inputInfo{ 16837 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16838 }, 16839 outputs: []outputInfo{ 16840 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16841 }, 16842 }, 16843 }, 16844 { 16845 name: "NOTW", 16846 argLen: 1, 16847 resultInArg0: true, 16848 clobberFlags: true, 16849 reg: regInfo{ 16850 inputs: []inputInfo{ 16851 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16852 }, 16853 outputs: []outputInfo{ 16854 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16855 }, 16856 }, 16857 }, 16858 { 16859 name: "FSQRT", 16860 argLen: 1, 16861 asm: s390x.AFSQRT, 16862 reg: regInfo{ 16863 inputs: []inputInfo{ 16864 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16865 }, 16866 outputs: []outputInfo{ 16867 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16868 }, 16869 }, 16870 }, 16871 { 16872 name: "SUBEcarrymask", 16873 argLen: 1, 16874 asm: s390x.ASUBE, 16875 reg: regInfo{ 16876 outputs: []outputInfo{ 16877 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16878 }, 16879 }, 16880 }, 16881 { 16882 name: "SUBEWcarrymask", 16883 argLen: 1, 16884 asm: s390x.ASUBE, 16885 reg: regInfo{ 16886 outputs: []outputInfo{ 16887 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16888 }, 16889 }, 16890 }, 16891 { 16892 name: "MOVDEQ", 16893 argLen: 3, 16894 resultInArg0: true, 16895 asm: s390x.AMOVDEQ, 16896 reg: regInfo{ 16897 inputs: []inputInfo{ 16898 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16899 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16900 }, 16901 outputs: []outputInfo{ 16902 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16903 }, 16904 }, 16905 }, 16906 { 16907 name: "MOVDNE", 16908 argLen: 3, 16909 resultInArg0: true, 16910 asm: s390x.AMOVDNE, 16911 reg: regInfo{ 16912 inputs: []inputInfo{ 16913 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16914 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16915 }, 16916 outputs: []outputInfo{ 16917 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16918 }, 16919 }, 16920 }, 16921 { 16922 name: "MOVDLT", 16923 argLen: 3, 16924 resultInArg0: true, 16925 asm: s390x.AMOVDLT, 16926 reg: regInfo{ 16927 inputs: []inputInfo{ 16928 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16929 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16930 }, 16931 outputs: []outputInfo{ 16932 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16933 }, 16934 }, 16935 }, 16936 { 16937 name: "MOVDLE", 16938 argLen: 3, 16939 resultInArg0: true, 16940 asm: s390x.AMOVDLE, 16941 reg: regInfo{ 16942 inputs: []inputInfo{ 16943 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16944 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16945 }, 16946 outputs: []outputInfo{ 16947 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16948 }, 16949 }, 16950 }, 16951 { 16952 name: "MOVDGT", 16953 argLen: 3, 16954 resultInArg0: true, 16955 asm: s390x.AMOVDGT, 16956 reg: regInfo{ 16957 inputs: []inputInfo{ 16958 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16959 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16960 }, 16961 outputs: []outputInfo{ 16962 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16963 }, 16964 }, 16965 }, 16966 { 16967 name: "MOVDGE", 16968 argLen: 3, 16969 resultInArg0: true, 16970 asm: s390x.AMOVDGE, 16971 reg: regInfo{ 16972 inputs: []inputInfo{ 16973 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16974 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16975 }, 16976 outputs: []outputInfo{ 16977 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16978 }, 16979 }, 16980 }, 16981 { 16982 name: "MOVDGTnoinv", 16983 argLen: 3, 16984 resultInArg0: true, 16985 asm: s390x.AMOVDGT, 16986 reg: regInfo{ 16987 inputs: []inputInfo{ 16988 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16989 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16990 }, 16991 outputs: []outputInfo{ 16992 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16993 }, 16994 }, 16995 }, 16996 { 16997 name: "MOVDGEnoinv", 16998 argLen: 3, 16999 resultInArg0: true, 17000 asm: s390x.AMOVDGE, 17001 reg: regInfo{ 17002 inputs: []inputInfo{ 17003 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17004 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17005 }, 17006 outputs: []outputInfo{ 17007 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17008 }, 17009 }, 17010 }, 17011 { 17012 name: "MOVBreg", 17013 argLen: 1, 17014 asm: s390x.AMOVB, 17015 reg: regInfo{ 17016 inputs: []inputInfo{ 17017 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17018 }, 17019 outputs: []outputInfo{ 17020 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17021 }, 17022 }, 17023 }, 17024 { 17025 name: "MOVBZreg", 17026 argLen: 1, 17027 asm: s390x.AMOVBZ, 17028 reg: regInfo{ 17029 inputs: []inputInfo{ 17030 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17031 }, 17032 outputs: []outputInfo{ 17033 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17034 }, 17035 }, 17036 }, 17037 { 17038 name: "MOVHreg", 17039 argLen: 1, 17040 asm: s390x.AMOVH, 17041 reg: regInfo{ 17042 inputs: []inputInfo{ 17043 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17044 }, 17045 outputs: []outputInfo{ 17046 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17047 }, 17048 }, 17049 }, 17050 { 17051 name: "MOVHZreg", 17052 argLen: 1, 17053 asm: s390x.AMOVHZ, 17054 reg: regInfo{ 17055 inputs: []inputInfo{ 17056 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17057 }, 17058 outputs: []outputInfo{ 17059 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17060 }, 17061 }, 17062 }, 17063 { 17064 name: "MOVWreg", 17065 argLen: 1, 17066 asm: s390x.AMOVW, 17067 reg: regInfo{ 17068 inputs: []inputInfo{ 17069 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17070 }, 17071 outputs: []outputInfo{ 17072 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17073 }, 17074 }, 17075 }, 17076 { 17077 name: "MOVWZreg", 17078 argLen: 1, 17079 asm: s390x.AMOVWZ, 17080 reg: regInfo{ 17081 inputs: []inputInfo{ 17082 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17083 }, 17084 outputs: []outputInfo{ 17085 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17086 }, 17087 }, 17088 }, 17089 { 17090 name: "MOVDconst", 17091 auxType: auxInt64, 17092 argLen: 0, 17093 rematerializeable: true, 17094 asm: s390x.AMOVD, 17095 reg: regInfo{ 17096 outputs: []outputInfo{ 17097 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17098 }, 17099 }, 17100 }, 17101 { 17102 name: "CFDBRA", 17103 argLen: 1, 17104 asm: s390x.ACFDBRA, 17105 reg: regInfo{ 17106 inputs: []inputInfo{ 17107 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17108 }, 17109 outputs: []outputInfo{ 17110 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17111 }, 17112 }, 17113 }, 17114 { 17115 name: "CGDBRA", 17116 argLen: 1, 17117 asm: s390x.ACGDBRA, 17118 reg: regInfo{ 17119 inputs: []inputInfo{ 17120 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17121 }, 17122 outputs: []outputInfo{ 17123 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17124 }, 17125 }, 17126 }, 17127 { 17128 name: "CFEBRA", 17129 argLen: 1, 17130 asm: s390x.ACFEBRA, 17131 reg: regInfo{ 17132 inputs: []inputInfo{ 17133 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17134 }, 17135 outputs: []outputInfo{ 17136 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17137 }, 17138 }, 17139 }, 17140 { 17141 name: "CGEBRA", 17142 argLen: 1, 17143 asm: s390x.ACGEBRA, 17144 reg: regInfo{ 17145 inputs: []inputInfo{ 17146 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17147 }, 17148 outputs: []outputInfo{ 17149 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17150 }, 17151 }, 17152 }, 17153 { 17154 name: "CEFBRA", 17155 argLen: 1, 17156 asm: s390x.ACEFBRA, 17157 reg: regInfo{ 17158 inputs: []inputInfo{ 17159 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17160 }, 17161 outputs: []outputInfo{ 17162 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17163 }, 17164 }, 17165 }, 17166 { 17167 name: "CDFBRA", 17168 argLen: 1, 17169 asm: s390x.ACDFBRA, 17170 reg: regInfo{ 17171 inputs: []inputInfo{ 17172 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17173 }, 17174 outputs: []outputInfo{ 17175 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17176 }, 17177 }, 17178 }, 17179 { 17180 name: "CEGBRA", 17181 argLen: 1, 17182 asm: s390x.ACEGBRA, 17183 reg: regInfo{ 17184 inputs: []inputInfo{ 17185 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17186 }, 17187 outputs: []outputInfo{ 17188 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17189 }, 17190 }, 17191 }, 17192 { 17193 name: "CDGBRA", 17194 argLen: 1, 17195 asm: s390x.ACDGBRA, 17196 reg: regInfo{ 17197 inputs: []inputInfo{ 17198 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17199 }, 17200 outputs: []outputInfo{ 17201 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17202 }, 17203 }, 17204 }, 17205 { 17206 name: "LEDBR", 17207 argLen: 1, 17208 asm: s390x.ALEDBR, 17209 reg: regInfo{ 17210 inputs: []inputInfo{ 17211 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17212 }, 17213 outputs: []outputInfo{ 17214 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17215 }, 17216 }, 17217 }, 17218 { 17219 name: "LDEBR", 17220 argLen: 1, 17221 asm: s390x.ALDEBR, 17222 reg: regInfo{ 17223 inputs: []inputInfo{ 17224 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17225 }, 17226 outputs: []outputInfo{ 17227 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17228 }, 17229 }, 17230 }, 17231 { 17232 name: "MOVDaddr", 17233 auxType: auxSymOff, 17234 argLen: 1, 17235 rematerializeable: true, 17236 clobberFlags: true, 17237 reg: regInfo{ 17238 inputs: []inputInfo{ 17239 {0, 4295000064}, // SP SB 17240 }, 17241 outputs: []outputInfo{ 17242 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17243 }, 17244 }, 17245 }, 17246 { 17247 name: "MOVDaddridx", 17248 auxType: auxSymOff, 17249 argLen: 2, 17250 clobberFlags: true, 17251 reg: regInfo{ 17252 inputs: []inputInfo{ 17253 {0, 4295000064}, // SP SB 17254 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17255 }, 17256 outputs: []outputInfo{ 17257 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17258 }, 17259 }, 17260 }, 17261 { 17262 name: "MOVBZload", 17263 auxType: auxSymOff, 17264 argLen: 2, 17265 clobberFlags: true, 17266 faultOnNilArg0: true, 17267 asm: s390x.AMOVBZ, 17268 reg: regInfo{ 17269 inputs: []inputInfo{ 17270 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17271 }, 17272 outputs: []outputInfo{ 17273 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17274 }, 17275 }, 17276 }, 17277 { 17278 name: "MOVBload", 17279 auxType: auxSymOff, 17280 argLen: 2, 17281 clobberFlags: true, 17282 faultOnNilArg0: true, 17283 asm: s390x.AMOVB, 17284 reg: regInfo{ 17285 inputs: []inputInfo{ 17286 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17287 }, 17288 outputs: []outputInfo{ 17289 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17290 }, 17291 }, 17292 }, 17293 { 17294 name: "MOVHZload", 17295 auxType: auxSymOff, 17296 argLen: 2, 17297 clobberFlags: true, 17298 faultOnNilArg0: true, 17299 asm: s390x.AMOVHZ, 17300 reg: regInfo{ 17301 inputs: []inputInfo{ 17302 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17303 }, 17304 outputs: []outputInfo{ 17305 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17306 }, 17307 }, 17308 }, 17309 { 17310 name: "MOVHload", 17311 auxType: auxSymOff, 17312 argLen: 2, 17313 clobberFlags: true, 17314 faultOnNilArg0: true, 17315 asm: s390x.AMOVH, 17316 reg: regInfo{ 17317 inputs: []inputInfo{ 17318 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17319 }, 17320 outputs: []outputInfo{ 17321 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17322 }, 17323 }, 17324 }, 17325 { 17326 name: "MOVWZload", 17327 auxType: auxSymOff, 17328 argLen: 2, 17329 clobberFlags: true, 17330 faultOnNilArg0: true, 17331 asm: s390x.AMOVWZ, 17332 reg: regInfo{ 17333 inputs: []inputInfo{ 17334 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17335 }, 17336 outputs: []outputInfo{ 17337 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17338 }, 17339 }, 17340 }, 17341 { 17342 name: "MOVWload", 17343 auxType: auxSymOff, 17344 argLen: 2, 17345 clobberFlags: true, 17346 faultOnNilArg0: true, 17347 asm: s390x.AMOVW, 17348 reg: regInfo{ 17349 inputs: []inputInfo{ 17350 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17351 }, 17352 outputs: []outputInfo{ 17353 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17354 }, 17355 }, 17356 }, 17357 { 17358 name: "MOVDload", 17359 auxType: auxSymOff, 17360 argLen: 2, 17361 clobberFlags: true, 17362 faultOnNilArg0: true, 17363 asm: s390x.AMOVD, 17364 reg: regInfo{ 17365 inputs: []inputInfo{ 17366 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17367 }, 17368 outputs: []outputInfo{ 17369 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17370 }, 17371 }, 17372 }, 17373 { 17374 name: "MOVWBR", 17375 argLen: 1, 17376 asm: s390x.AMOVWBR, 17377 reg: regInfo{ 17378 inputs: []inputInfo{ 17379 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17380 }, 17381 outputs: []outputInfo{ 17382 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17383 }, 17384 }, 17385 }, 17386 { 17387 name: "MOVDBR", 17388 argLen: 1, 17389 asm: s390x.AMOVDBR, 17390 reg: regInfo{ 17391 inputs: []inputInfo{ 17392 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17393 }, 17394 outputs: []outputInfo{ 17395 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17396 }, 17397 }, 17398 }, 17399 { 17400 name: "MOVHBRload", 17401 auxType: auxSymOff, 17402 argLen: 2, 17403 clobberFlags: true, 17404 faultOnNilArg0: true, 17405 asm: s390x.AMOVHBR, 17406 reg: regInfo{ 17407 inputs: []inputInfo{ 17408 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17409 }, 17410 outputs: []outputInfo{ 17411 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17412 }, 17413 }, 17414 }, 17415 { 17416 name: "MOVWBRload", 17417 auxType: auxSymOff, 17418 argLen: 2, 17419 clobberFlags: true, 17420 faultOnNilArg0: true, 17421 asm: s390x.AMOVWBR, 17422 reg: regInfo{ 17423 inputs: []inputInfo{ 17424 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17425 }, 17426 outputs: []outputInfo{ 17427 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17428 }, 17429 }, 17430 }, 17431 { 17432 name: "MOVDBRload", 17433 auxType: auxSymOff, 17434 argLen: 2, 17435 clobberFlags: true, 17436 faultOnNilArg0: true, 17437 asm: s390x.AMOVDBR, 17438 reg: regInfo{ 17439 inputs: []inputInfo{ 17440 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17441 }, 17442 outputs: []outputInfo{ 17443 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17444 }, 17445 }, 17446 }, 17447 { 17448 name: "MOVBstore", 17449 auxType: auxSymOff, 17450 argLen: 3, 17451 clobberFlags: true, 17452 faultOnNilArg0: true, 17453 asm: s390x.AMOVB, 17454 reg: regInfo{ 17455 inputs: []inputInfo{ 17456 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17457 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17458 }, 17459 }, 17460 }, 17461 { 17462 name: "MOVHstore", 17463 auxType: auxSymOff, 17464 argLen: 3, 17465 clobberFlags: true, 17466 faultOnNilArg0: true, 17467 asm: s390x.AMOVH, 17468 reg: regInfo{ 17469 inputs: []inputInfo{ 17470 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17471 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17472 }, 17473 }, 17474 }, 17475 { 17476 name: "MOVWstore", 17477 auxType: auxSymOff, 17478 argLen: 3, 17479 clobberFlags: true, 17480 faultOnNilArg0: true, 17481 asm: s390x.AMOVW, 17482 reg: regInfo{ 17483 inputs: []inputInfo{ 17484 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17485 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17486 }, 17487 }, 17488 }, 17489 { 17490 name: "MOVDstore", 17491 auxType: auxSymOff, 17492 argLen: 3, 17493 clobberFlags: true, 17494 faultOnNilArg0: true, 17495 asm: s390x.AMOVD, 17496 reg: regInfo{ 17497 inputs: []inputInfo{ 17498 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17499 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17500 }, 17501 }, 17502 }, 17503 { 17504 name: "MOVHBRstore", 17505 auxType: auxSymOff, 17506 argLen: 3, 17507 clobberFlags: true, 17508 faultOnNilArg0: true, 17509 asm: s390x.AMOVHBR, 17510 reg: regInfo{ 17511 inputs: []inputInfo{ 17512 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17513 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17514 }, 17515 }, 17516 }, 17517 { 17518 name: "MOVWBRstore", 17519 auxType: auxSymOff, 17520 argLen: 3, 17521 clobberFlags: true, 17522 faultOnNilArg0: true, 17523 asm: s390x.AMOVWBR, 17524 reg: regInfo{ 17525 inputs: []inputInfo{ 17526 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17527 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17528 }, 17529 }, 17530 }, 17531 { 17532 name: "MOVDBRstore", 17533 auxType: auxSymOff, 17534 argLen: 3, 17535 clobberFlags: true, 17536 faultOnNilArg0: true, 17537 asm: s390x.AMOVDBR, 17538 reg: regInfo{ 17539 inputs: []inputInfo{ 17540 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17541 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17542 }, 17543 }, 17544 }, 17545 { 17546 name: "MVC", 17547 auxType: auxSymValAndOff, 17548 argLen: 3, 17549 clobberFlags: true, 17550 faultOnNilArg0: true, 17551 faultOnNilArg1: true, 17552 asm: s390x.AMVC, 17553 reg: regInfo{ 17554 inputs: []inputInfo{ 17555 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17556 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17557 }, 17558 }, 17559 }, 17560 { 17561 name: "MOVBZloadidx", 17562 auxType: auxSymOff, 17563 argLen: 3, 17564 clobberFlags: true, 17565 asm: s390x.AMOVBZ, 17566 reg: regInfo{ 17567 inputs: []inputInfo{ 17568 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17569 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17570 }, 17571 outputs: []outputInfo{ 17572 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17573 }, 17574 }, 17575 }, 17576 { 17577 name: "MOVHZloadidx", 17578 auxType: auxSymOff, 17579 argLen: 3, 17580 clobberFlags: true, 17581 asm: s390x.AMOVHZ, 17582 reg: regInfo{ 17583 inputs: []inputInfo{ 17584 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17585 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17586 }, 17587 outputs: []outputInfo{ 17588 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17589 }, 17590 }, 17591 }, 17592 { 17593 name: "MOVWZloadidx", 17594 auxType: auxSymOff, 17595 argLen: 3, 17596 clobberFlags: true, 17597 asm: s390x.AMOVWZ, 17598 reg: regInfo{ 17599 inputs: []inputInfo{ 17600 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17601 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17602 }, 17603 outputs: []outputInfo{ 17604 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17605 }, 17606 }, 17607 }, 17608 { 17609 name: "MOVDloadidx", 17610 auxType: auxSymOff, 17611 argLen: 3, 17612 clobberFlags: true, 17613 asm: s390x.AMOVD, 17614 reg: regInfo{ 17615 inputs: []inputInfo{ 17616 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17617 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17618 }, 17619 outputs: []outputInfo{ 17620 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17621 }, 17622 }, 17623 }, 17624 { 17625 name: "MOVHBRloadidx", 17626 auxType: auxSymOff, 17627 argLen: 3, 17628 clobberFlags: true, 17629 asm: s390x.AMOVHBR, 17630 reg: regInfo{ 17631 inputs: []inputInfo{ 17632 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17633 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17634 }, 17635 outputs: []outputInfo{ 17636 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17637 }, 17638 }, 17639 }, 17640 { 17641 name: "MOVWBRloadidx", 17642 auxType: auxSymOff, 17643 argLen: 3, 17644 clobberFlags: true, 17645 asm: s390x.AMOVWBR, 17646 reg: regInfo{ 17647 inputs: []inputInfo{ 17648 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17649 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17650 }, 17651 outputs: []outputInfo{ 17652 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17653 }, 17654 }, 17655 }, 17656 { 17657 name: "MOVDBRloadidx", 17658 auxType: auxSymOff, 17659 argLen: 3, 17660 clobberFlags: true, 17661 asm: s390x.AMOVDBR, 17662 reg: regInfo{ 17663 inputs: []inputInfo{ 17664 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17665 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17666 }, 17667 outputs: []outputInfo{ 17668 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17669 }, 17670 }, 17671 }, 17672 { 17673 name: "MOVBstoreidx", 17674 auxType: auxSymOff, 17675 argLen: 4, 17676 clobberFlags: true, 17677 asm: s390x.AMOVB, 17678 reg: regInfo{ 17679 inputs: []inputInfo{ 17680 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17681 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17682 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17683 }, 17684 }, 17685 }, 17686 { 17687 name: "MOVHstoreidx", 17688 auxType: auxSymOff, 17689 argLen: 4, 17690 clobberFlags: true, 17691 asm: s390x.AMOVH, 17692 reg: regInfo{ 17693 inputs: []inputInfo{ 17694 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17695 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17696 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17697 }, 17698 }, 17699 }, 17700 { 17701 name: "MOVWstoreidx", 17702 auxType: auxSymOff, 17703 argLen: 4, 17704 clobberFlags: true, 17705 asm: s390x.AMOVW, 17706 reg: regInfo{ 17707 inputs: []inputInfo{ 17708 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17709 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17710 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17711 }, 17712 }, 17713 }, 17714 { 17715 name: "MOVDstoreidx", 17716 auxType: auxSymOff, 17717 argLen: 4, 17718 clobberFlags: true, 17719 asm: s390x.AMOVD, 17720 reg: regInfo{ 17721 inputs: []inputInfo{ 17722 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17723 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17724 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17725 }, 17726 }, 17727 }, 17728 { 17729 name: "MOVHBRstoreidx", 17730 auxType: auxSymOff, 17731 argLen: 4, 17732 clobberFlags: true, 17733 asm: s390x.AMOVHBR, 17734 reg: regInfo{ 17735 inputs: []inputInfo{ 17736 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17737 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17738 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17739 }, 17740 }, 17741 }, 17742 { 17743 name: "MOVWBRstoreidx", 17744 auxType: auxSymOff, 17745 argLen: 4, 17746 clobberFlags: true, 17747 asm: s390x.AMOVWBR, 17748 reg: regInfo{ 17749 inputs: []inputInfo{ 17750 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17751 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17752 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17753 }, 17754 }, 17755 }, 17756 { 17757 name: "MOVDBRstoreidx", 17758 auxType: auxSymOff, 17759 argLen: 4, 17760 clobberFlags: true, 17761 asm: s390x.AMOVDBR, 17762 reg: regInfo{ 17763 inputs: []inputInfo{ 17764 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17765 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17766 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17767 }, 17768 }, 17769 }, 17770 { 17771 name: "MOVBstoreconst", 17772 auxType: auxSymValAndOff, 17773 argLen: 2, 17774 clobberFlags: true, 17775 faultOnNilArg0: true, 17776 asm: s390x.AMOVB, 17777 reg: regInfo{ 17778 inputs: []inputInfo{ 17779 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17780 }, 17781 }, 17782 }, 17783 { 17784 name: "MOVHstoreconst", 17785 auxType: auxSymValAndOff, 17786 argLen: 2, 17787 clobberFlags: true, 17788 faultOnNilArg0: true, 17789 asm: s390x.AMOVH, 17790 reg: regInfo{ 17791 inputs: []inputInfo{ 17792 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17793 }, 17794 }, 17795 }, 17796 { 17797 name: "MOVWstoreconst", 17798 auxType: auxSymValAndOff, 17799 argLen: 2, 17800 clobberFlags: true, 17801 faultOnNilArg0: true, 17802 asm: s390x.AMOVW, 17803 reg: regInfo{ 17804 inputs: []inputInfo{ 17805 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17806 }, 17807 }, 17808 }, 17809 { 17810 name: "MOVDstoreconst", 17811 auxType: auxSymValAndOff, 17812 argLen: 2, 17813 clobberFlags: true, 17814 faultOnNilArg0: true, 17815 asm: s390x.AMOVD, 17816 reg: regInfo{ 17817 inputs: []inputInfo{ 17818 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17819 }, 17820 }, 17821 }, 17822 { 17823 name: "CLEAR", 17824 auxType: auxSymValAndOff, 17825 argLen: 2, 17826 clobberFlags: true, 17827 faultOnNilArg0: true, 17828 asm: s390x.ACLEAR, 17829 reg: regInfo{ 17830 inputs: []inputInfo{ 17831 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17832 }, 17833 }, 17834 }, 17835 { 17836 name: "CALLstatic", 17837 auxType: auxSymOff, 17838 argLen: 1, 17839 clobberFlags: true, 17840 call: true, 17841 reg: regInfo{ 17842 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17843 }, 17844 }, 17845 { 17846 name: "CALLclosure", 17847 auxType: auxInt64, 17848 argLen: 3, 17849 clobberFlags: true, 17850 call: true, 17851 reg: regInfo{ 17852 inputs: []inputInfo{ 17853 {1, 4096}, // R12 17854 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17855 }, 17856 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17857 }, 17858 }, 17859 { 17860 name: "CALLdefer", 17861 auxType: auxInt64, 17862 argLen: 1, 17863 clobberFlags: true, 17864 call: true, 17865 reg: regInfo{ 17866 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17867 }, 17868 }, 17869 { 17870 name: "CALLgo", 17871 auxType: auxInt64, 17872 argLen: 1, 17873 clobberFlags: true, 17874 call: true, 17875 reg: regInfo{ 17876 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17877 }, 17878 }, 17879 { 17880 name: "CALLinter", 17881 auxType: auxInt64, 17882 argLen: 2, 17883 clobberFlags: true, 17884 call: true, 17885 reg: regInfo{ 17886 inputs: []inputInfo{ 17887 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17888 }, 17889 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17890 }, 17891 }, 17892 { 17893 name: "InvertFlags", 17894 argLen: 1, 17895 reg: regInfo{}, 17896 }, 17897 { 17898 name: "LoweredGetG", 17899 argLen: 1, 17900 reg: regInfo{ 17901 outputs: []outputInfo{ 17902 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17903 }, 17904 }, 17905 }, 17906 { 17907 name: "LoweredGetClosurePtr", 17908 argLen: 0, 17909 reg: regInfo{ 17910 outputs: []outputInfo{ 17911 {0, 4096}, // R12 17912 }, 17913 }, 17914 }, 17915 { 17916 name: "LoweredNilCheck", 17917 argLen: 2, 17918 clobberFlags: true, 17919 nilCheck: true, 17920 faultOnNilArg0: true, 17921 reg: regInfo{ 17922 inputs: []inputInfo{ 17923 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17924 }, 17925 }, 17926 }, 17927 { 17928 name: "MOVDconvert", 17929 argLen: 2, 17930 asm: s390x.AMOVD, 17931 reg: regInfo{ 17932 inputs: []inputInfo{ 17933 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17934 }, 17935 outputs: []outputInfo{ 17936 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17937 }, 17938 }, 17939 }, 17940 { 17941 name: "FlagEQ", 17942 argLen: 0, 17943 reg: regInfo{}, 17944 }, 17945 { 17946 name: "FlagLT", 17947 argLen: 0, 17948 reg: regInfo{}, 17949 }, 17950 { 17951 name: "FlagGT", 17952 argLen: 0, 17953 reg: regInfo{}, 17954 }, 17955 { 17956 name: "MOVWZatomicload", 17957 auxType: auxSymOff, 17958 argLen: 2, 17959 faultOnNilArg0: true, 17960 asm: s390x.AMOVWZ, 17961 reg: regInfo{ 17962 inputs: []inputInfo{ 17963 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17964 }, 17965 outputs: []outputInfo{ 17966 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17967 }, 17968 }, 17969 }, 17970 { 17971 name: "MOVDatomicload", 17972 auxType: auxSymOff, 17973 argLen: 2, 17974 faultOnNilArg0: true, 17975 asm: s390x.AMOVD, 17976 reg: regInfo{ 17977 inputs: []inputInfo{ 17978 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17979 }, 17980 outputs: []outputInfo{ 17981 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17982 }, 17983 }, 17984 }, 17985 { 17986 name: "MOVWatomicstore", 17987 auxType: auxSymOff, 17988 argLen: 3, 17989 clobberFlags: true, 17990 faultOnNilArg0: true, 17991 asm: s390x.AMOVW, 17992 reg: regInfo{ 17993 inputs: []inputInfo{ 17994 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17995 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17996 }, 17997 }, 17998 }, 17999 { 18000 name: "MOVDatomicstore", 18001 auxType: auxSymOff, 18002 argLen: 3, 18003 clobberFlags: true, 18004 faultOnNilArg0: true, 18005 asm: s390x.AMOVD, 18006 reg: regInfo{ 18007 inputs: []inputInfo{ 18008 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18009 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18010 }, 18011 }, 18012 }, 18013 { 18014 name: "LAA", 18015 auxType: auxSymOff, 18016 argLen: 3, 18017 faultOnNilArg0: true, 18018 asm: s390x.ALAA, 18019 reg: regInfo{ 18020 inputs: []inputInfo{ 18021 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18022 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18023 }, 18024 outputs: []outputInfo{ 18025 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18026 }, 18027 }, 18028 }, 18029 { 18030 name: "LAAG", 18031 auxType: auxSymOff, 18032 argLen: 3, 18033 faultOnNilArg0: true, 18034 asm: s390x.ALAAG, 18035 reg: regInfo{ 18036 inputs: []inputInfo{ 18037 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18038 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18039 }, 18040 outputs: []outputInfo{ 18041 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18042 }, 18043 }, 18044 }, 18045 { 18046 name: "AddTupleFirst32", 18047 argLen: 2, 18048 reg: regInfo{}, 18049 }, 18050 { 18051 name: "AddTupleFirst64", 18052 argLen: 2, 18053 reg: regInfo{}, 18054 }, 18055 { 18056 name: "LoweredAtomicCas32", 18057 auxType: auxSymOff, 18058 argLen: 4, 18059 clobberFlags: true, 18060 faultOnNilArg0: true, 18061 asm: s390x.ACS, 18062 reg: regInfo{ 18063 inputs: []inputInfo{ 18064 {1, 1}, // R0 18065 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18066 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18067 }, 18068 clobbers: 1, // R0 18069 outputs: []outputInfo{ 18070 {1, 0}, 18071 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18072 }, 18073 }, 18074 }, 18075 { 18076 name: "LoweredAtomicCas64", 18077 auxType: auxSymOff, 18078 argLen: 4, 18079 clobberFlags: true, 18080 faultOnNilArg0: true, 18081 asm: s390x.ACSG, 18082 reg: regInfo{ 18083 inputs: []inputInfo{ 18084 {1, 1}, // R0 18085 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18086 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18087 }, 18088 clobbers: 1, // R0 18089 outputs: []outputInfo{ 18090 {1, 0}, 18091 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18092 }, 18093 }, 18094 }, 18095 { 18096 name: "LoweredAtomicExchange32", 18097 auxType: auxSymOff, 18098 argLen: 3, 18099 clobberFlags: true, 18100 faultOnNilArg0: true, 18101 asm: s390x.ACS, 18102 reg: regInfo{ 18103 inputs: []inputInfo{ 18104 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18105 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18106 }, 18107 outputs: []outputInfo{ 18108 {1, 0}, 18109 {0, 1}, // R0 18110 }, 18111 }, 18112 }, 18113 { 18114 name: "LoweredAtomicExchange64", 18115 auxType: auxSymOff, 18116 argLen: 3, 18117 clobberFlags: true, 18118 faultOnNilArg0: true, 18119 asm: s390x.ACSG, 18120 reg: regInfo{ 18121 inputs: []inputInfo{ 18122 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18123 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18124 }, 18125 outputs: []outputInfo{ 18126 {1, 0}, 18127 {0, 1}, // R0 18128 }, 18129 }, 18130 }, 18131 { 18132 name: "FLOGR", 18133 argLen: 1, 18134 clobberFlags: true, 18135 asm: s390x.AFLOGR, 18136 reg: regInfo{ 18137 inputs: []inputInfo{ 18138 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18139 }, 18140 clobbers: 2, // R1 18141 outputs: []outputInfo{ 18142 {0, 1}, // R0 18143 }, 18144 }, 18145 }, 18146 { 18147 name: "STMG2", 18148 auxType: auxSymOff, 18149 argLen: 4, 18150 faultOnNilArg0: true, 18151 asm: s390x.ASTMG, 18152 reg: regInfo{ 18153 inputs: []inputInfo{ 18154 {1, 2}, // R1 18155 {2, 4}, // R2 18156 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18157 }, 18158 }, 18159 }, 18160 { 18161 name: "STMG3", 18162 auxType: auxSymOff, 18163 argLen: 5, 18164 faultOnNilArg0: true, 18165 asm: s390x.ASTMG, 18166 reg: regInfo{ 18167 inputs: []inputInfo{ 18168 {1, 2}, // R1 18169 {2, 4}, // R2 18170 {3, 8}, // R3 18171 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18172 }, 18173 }, 18174 }, 18175 { 18176 name: "STMG4", 18177 auxType: auxSymOff, 18178 argLen: 6, 18179 faultOnNilArg0: true, 18180 asm: s390x.ASTMG, 18181 reg: regInfo{ 18182 inputs: []inputInfo{ 18183 {1, 2}, // R1 18184 {2, 4}, // R2 18185 {3, 8}, // R3 18186 {4, 16}, // R4 18187 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18188 }, 18189 }, 18190 }, 18191 { 18192 name: "STM2", 18193 auxType: auxSymOff, 18194 argLen: 4, 18195 faultOnNilArg0: true, 18196 asm: s390x.ASTMY, 18197 reg: regInfo{ 18198 inputs: []inputInfo{ 18199 {1, 2}, // R1 18200 {2, 4}, // R2 18201 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18202 }, 18203 }, 18204 }, 18205 { 18206 name: "STM3", 18207 auxType: auxSymOff, 18208 argLen: 5, 18209 faultOnNilArg0: true, 18210 asm: s390x.ASTMY, 18211 reg: regInfo{ 18212 inputs: []inputInfo{ 18213 {1, 2}, // R1 18214 {2, 4}, // R2 18215 {3, 8}, // R3 18216 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18217 }, 18218 }, 18219 }, 18220 { 18221 name: "STM4", 18222 auxType: auxSymOff, 18223 argLen: 6, 18224 faultOnNilArg0: true, 18225 asm: s390x.ASTMY, 18226 reg: regInfo{ 18227 inputs: []inputInfo{ 18228 {1, 2}, // R1 18229 {2, 4}, // R2 18230 {3, 8}, // R3 18231 {4, 16}, // R4 18232 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18233 }, 18234 }, 18235 }, 18236 { 18237 name: "LoweredMove", 18238 auxType: auxInt64, 18239 argLen: 4, 18240 clobberFlags: true, 18241 reg: regInfo{ 18242 inputs: []inputInfo{ 18243 {0, 2}, // R1 18244 {1, 4}, // R2 18245 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18246 }, 18247 clobbers: 6, // R1 R2 18248 }, 18249 }, 18250 { 18251 name: "LoweredZero", 18252 auxType: auxInt64, 18253 argLen: 3, 18254 clobberFlags: true, 18255 reg: regInfo{ 18256 inputs: []inputInfo{ 18257 {0, 2}, // R1 18258 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18259 }, 18260 clobbers: 2, // R1 18261 }, 18262 }, 18263 18264 { 18265 name: "Add8", 18266 argLen: 2, 18267 commutative: true, 18268 generic: true, 18269 }, 18270 { 18271 name: "Add16", 18272 argLen: 2, 18273 commutative: true, 18274 generic: true, 18275 }, 18276 { 18277 name: "Add32", 18278 argLen: 2, 18279 commutative: true, 18280 generic: true, 18281 }, 18282 { 18283 name: "Add64", 18284 argLen: 2, 18285 commutative: true, 18286 generic: true, 18287 }, 18288 { 18289 name: "AddPtr", 18290 argLen: 2, 18291 generic: true, 18292 }, 18293 { 18294 name: "Add32F", 18295 argLen: 2, 18296 generic: true, 18297 }, 18298 { 18299 name: "Add64F", 18300 argLen: 2, 18301 generic: true, 18302 }, 18303 { 18304 name: "Sub8", 18305 argLen: 2, 18306 generic: true, 18307 }, 18308 { 18309 name: "Sub16", 18310 argLen: 2, 18311 generic: true, 18312 }, 18313 { 18314 name: "Sub32", 18315 argLen: 2, 18316 generic: true, 18317 }, 18318 { 18319 name: "Sub64", 18320 argLen: 2, 18321 generic: true, 18322 }, 18323 { 18324 name: "SubPtr", 18325 argLen: 2, 18326 generic: true, 18327 }, 18328 { 18329 name: "Sub32F", 18330 argLen: 2, 18331 generic: true, 18332 }, 18333 { 18334 name: "Sub64F", 18335 argLen: 2, 18336 generic: true, 18337 }, 18338 { 18339 name: "Mul8", 18340 argLen: 2, 18341 commutative: true, 18342 generic: true, 18343 }, 18344 { 18345 name: "Mul16", 18346 argLen: 2, 18347 commutative: true, 18348 generic: true, 18349 }, 18350 { 18351 name: "Mul32", 18352 argLen: 2, 18353 commutative: true, 18354 generic: true, 18355 }, 18356 { 18357 name: "Mul64", 18358 argLen: 2, 18359 commutative: true, 18360 generic: true, 18361 }, 18362 { 18363 name: "Mul32F", 18364 argLen: 2, 18365 generic: true, 18366 }, 18367 { 18368 name: "Mul64F", 18369 argLen: 2, 18370 generic: true, 18371 }, 18372 { 18373 name: "Div32F", 18374 argLen: 2, 18375 generic: true, 18376 }, 18377 { 18378 name: "Div64F", 18379 argLen: 2, 18380 generic: true, 18381 }, 18382 { 18383 name: "Hmul8", 18384 argLen: 2, 18385 generic: true, 18386 }, 18387 { 18388 name: "Hmul8u", 18389 argLen: 2, 18390 generic: true, 18391 }, 18392 { 18393 name: "Hmul16", 18394 argLen: 2, 18395 generic: true, 18396 }, 18397 { 18398 name: "Hmul16u", 18399 argLen: 2, 18400 generic: true, 18401 }, 18402 { 18403 name: "Hmul32", 18404 argLen: 2, 18405 generic: true, 18406 }, 18407 { 18408 name: "Hmul32u", 18409 argLen: 2, 18410 generic: true, 18411 }, 18412 { 18413 name: "Hmul64", 18414 argLen: 2, 18415 generic: true, 18416 }, 18417 { 18418 name: "Hmul64u", 18419 argLen: 2, 18420 generic: true, 18421 }, 18422 { 18423 name: "Mul32uhilo", 18424 argLen: 2, 18425 generic: true, 18426 }, 18427 { 18428 name: "Mul64uhilo", 18429 argLen: 2, 18430 generic: true, 18431 }, 18432 { 18433 name: "Avg64u", 18434 argLen: 2, 18435 generic: true, 18436 }, 18437 { 18438 name: "Div8", 18439 argLen: 2, 18440 generic: true, 18441 }, 18442 { 18443 name: "Div8u", 18444 argLen: 2, 18445 generic: true, 18446 }, 18447 { 18448 name: "Div16", 18449 argLen: 2, 18450 generic: true, 18451 }, 18452 { 18453 name: "Div16u", 18454 argLen: 2, 18455 generic: true, 18456 }, 18457 { 18458 name: "Div32", 18459 argLen: 2, 18460 generic: true, 18461 }, 18462 { 18463 name: "Div32u", 18464 argLen: 2, 18465 generic: true, 18466 }, 18467 { 18468 name: "Div64", 18469 argLen: 2, 18470 generic: true, 18471 }, 18472 { 18473 name: "Div64u", 18474 argLen: 2, 18475 generic: true, 18476 }, 18477 { 18478 name: "Div128u", 18479 argLen: 3, 18480 generic: true, 18481 }, 18482 { 18483 name: "Mod8", 18484 argLen: 2, 18485 generic: true, 18486 }, 18487 { 18488 name: "Mod8u", 18489 argLen: 2, 18490 generic: true, 18491 }, 18492 { 18493 name: "Mod16", 18494 argLen: 2, 18495 generic: true, 18496 }, 18497 { 18498 name: "Mod16u", 18499 argLen: 2, 18500 generic: true, 18501 }, 18502 { 18503 name: "Mod32", 18504 argLen: 2, 18505 generic: true, 18506 }, 18507 { 18508 name: "Mod32u", 18509 argLen: 2, 18510 generic: true, 18511 }, 18512 { 18513 name: "Mod64", 18514 argLen: 2, 18515 generic: true, 18516 }, 18517 { 18518 name: "Mod64u", 18519 argLen: 2, 18520 generic: true, 18521 }, 18522 { 18523 name: "And8", 18524 argLen: 2, 18525 commutative: true, 18526 generic: true, 18527 }, 18528 { 18529 name: "And16", 18530 argLen: 2, 18531 commutative: true, 18532 generic: true, 18533 }, 18534 { 18535 name: "And32", 18536 argLen: 2, 18537 commutative: true, 18538 generic: true, 18539 }, 18540 { 18541 name: "And64", 18542 argLen: 2, 18543 commutative: true, 18544 generic: true, 18545 }, 18546 { 18547 name: "Or8", 18548 argLen: 2, 18549 commutative: true, 18550 generic: true, 18551 }, 18552 { 18553 name: "Or16", 18554 argLen: 2, 18555 commutative: true, 18556 generic: true, 18557 }, 18558 { 18559 name: "Or32", 18560 argLen: 2, 18561 commutative: true, 18562 generic: true, 18563 }, 18564 { 18565 name: "Or64", 18566 argLen: 2, 18567 commutative: true, 18568 generic: true, 18569 }, 18570 { 18571 name: "Xor8", 18572 argLen: 2, 18573 commutative: true, 18574 generic: true, 18575 }, 18576 { 18577 name: "Xor16", 18578 argLen: 2, 18579 commutative: true, 18580 generic: true, 18581 }, 18582 { 18583 name: "Xor32", 18584 argLen: 2, 18585 commutative: true, 18586 generic: true, 18587 }, 18588 { 18589 name: "Xor64", 18590 argLen: 2, 18591 commutative: true, 18592 generic: true, 18593 }, 18594 { 18595 name: "Lsh8x8", 18596 argLen: 2, 18597 generic: true, 18598 }, 18599 { 18600 name: "Lsh8x16", 18601 argLen: 2, 18602 generic: true, 18603 }, 18604 { 18605 name: "Lsh8x32", 18606 argLen: 2, 18607 generic: true, 18608 }, 18609 { 18610 name: "Lsh8x64", 18611 argLen: 2, 18612 generic: true, 18613 }, 18614 { 18615 name: "Lsh16x8", 18616 argLen: 2, 18617 generic: true, 18618 }, 18619 { 18620 name: "Lsh16x16", 18621 argLen: 2, 18622 generic: true, 18623 }, 18624 { 18625 name: "Lsh16x32", 18626 argLen: 2, 18627 generic: true, 18628 }, 18629 { 18630 name: "Lsh16x64", 18631 argLen: 2, 18632 generic: true, 18633 }, 18634 { 18635 name: "Lsh32x8", 18636 argLen: 2, 18637 generic: true, 18638 }, 18639 { 18640 name: "Lsh32x16", 18641 argLen: 2, 18642 generic: true, 18643 }, 18644 { 18645 name: "Lsh32x32", 18646 argLen: 2, 18647 generic: true, 18648 }, 18649 { 18650 name: "Lsh32x64", 18651 argLen: 2, 18652 generic: true, 18653 }, 18654 { 18655 name: "Lsh64x8", 18656 argLen: 2, 18657 generic: true, 18658 }, 18659 { 18660 name: "Lsh64x16", 18661 argLen: 2, 18662 generic: true, 18663 }, 18664 { 18665 name: "Lsh64x32", 18666 argLen: 2, 18667 generic: true, 18668 }, 18669 { 18670 name: "Lsh64x64", 18671 argLen: 2, 18672 generic: true, 18673 }, 18674 { 18675 name: "Rsh8x8", 18676 argLen: 2, 18677 generic: true, 18678 }, 18679 { 18680 name: "Rsh8x16", 18681 argLen: 2, 18682 generic: true, 18683 }, 18684 { 18685 name: "Rsh8x32", 18686 argLen: 2, 18687 generic: true, 18688 }, 18689 { 18690 name: "Rsh8x64", 18691 argLen: 2, 18692 generic: true, 18693 }, 18694 { 18695 name: "Rsh16x8", 18696 argLen: 2, 18697 generic: true, 18698 }, 18699 { 18700 name: "Rsh16x16", 18701 argLen: 2, 18702 generic: true, 18703 }, 18704 { 18705 name: "Rsh16x32", 18706 argLen: 2, 18707 generic: true, 18708 }, 18709 { 18710 name: "Rsh16x64", 18711 argLen: 2, 18712 generic: true, 18713 }, 18714 { 18715 name: "Rsh32x8", 18716 argLen: 2, 18717 generic: true, 18718 }, 18719 { 18720 name: "Rsh32x16", 18721 argLen: 2, 18722 generic: true, 18723 }, 18724 { 18725 name: "Rsh32x32", 18726 argLen: 2, 18727 generic: true, 18728 }, 18729 { 18730 name: "Rsh32x64", 18731 argLen: 2, 18732 generic: true, 18733 }, 18734 { 18735 name: "Rsh64x8", 18736 argLen: 2, 18737 generic: true, 18738 }, 18739 { 18740 name: "Rsh64x16", 18741 argLen: 2, 18742 generic: true, 18743 }, 18744 { 18745 name: "Rsh64x32", 18746 argLen: 2, 18747 generic: true, 18748 }, 18749 { 18750 name: "Rsh64x64", 18751 argLen: 2, 18752 generic: true, 18753 }, 18754 { 18755 name: "Rsh8Ux8", 18756 argLen: 2, 18757 generic: true, 18758 }, 18759 { 18760 name: "Rsh8Ux16", 18761 argLen: 2, 18762 generic: true, 18763 }, 18764 { 18765 name: "Rsh8Ux32", 18766 argLen: 2, 18767 generic: true, 18768 }, 18769 { 18770 name: "Rsh8Ux64", 18771 argLen: 2, 18772 generic: true, 18773 }, 18774 { 18775 name: "Rsh16Ux8", 18776 argLen: 2, 18777 generic: true, 18778 }, 18779 { 18780 name: "Rsh16Ux16", 18781 argLen: 2, 18782 generic: true, 18783 }, 18784 { 18785 name: "Rsh16Ux32", 18786 argLen: 2, 18787 generic: true, 18788 }, 18789 { 18790 name: "Rsh16Ux64", 18791 argLen: 2, 18792 generic: true, 18793 }, 18794 { 18795 name: "Rsh32Ux8", 18796 argLen: 2, 18797 generic: true, 18798 }, 18799 { 18800 name: "Rsh32Ux16", 18801 argLen: 2, 18802 generic: true, 18803 }, 18804 { 18805 name: "Rsh32Ux32", 18806 argLen: 2, 18807 generic: true, 18808 }, 18809 { 18810 name: "Rsh32Ux64", 18811 argLen: 2, 18812 generic: true, 18813 }, 18814 { 18815 name: "Rsh64Ux8", 18816 argLen: 2, 18817 generic: true, 18818 }, 18819 { 18820 name: "Rsh64Ux16", 18821 argLen: 2, 18822 generic: true, 18823 }, 18824 { 18825 name: "Rsh64Ux32", 18826 argLen: 2, 18827 generic: true, 18828 }, 18829 { 18830 name: "Rsh64Ux64", 18831 argLen: 2, 18832 generic: true, 18833 }, 18834 { 18835 name: "Lrot8", 18836 auxType: auxInt64, 18837 argLen: 1, 18838 generic: true, 18839 }, 18840 { 18841 name: "Lrot16", 18842 auxType: auxInt64, 18843 argLen: 1, 18844 generic: true, 18845 }, 18846 { 18847 name: "Lrot32", 18848 auxType: auxInt64, 18849 argLen: 1, 18850 generic: true, 18851 }, 18852 { 18853 name: "Lrot64", 18854 auxType: auxInt64, 18855 argLen: 1, 18856 generic: true, 18857 }, 18858 { 18859 name: "Eq8", 18860 argLen: 2, 18861 commutative: true, 18862 generic: true, 18863 }, 18864 { 18865 name: "Eq16", 18866 argLen: 2, 18867 commutative: true, 18868 generic: true, 18869 }, 18870 { 18871 name: "Eq32", 18872 argLen: 2, 18873 commutative: true, 18874 generic: true, 18875 }, 18876 { 18877 name: "Eq64", 18878 argLen: 2, 18879 commutative: true, 18880 generic: true, 18881 }, 18882 { 18883 name: "EqPtr", 18884 argLen: 2, 18885 commutative: true, 18886 generic: true, 18887 }, 18888 { 18889 name: "EqInter", 18890 argLen: 2, 18891 generic: true, 18892 }, 18893 { 18894 name: "EqSlice", 18895 argLen: 2, 18896 generic: true, 18897 }, 18898 { 18899 name: "Eq32F", 18900 argLen: 2, 18901 generic: true, 18902 }, 18903 { 18904 name: "Eq64F", 18905 argLen: 2, 18906 generic: true, 18907 }, 18908 { 18909 name: "Neq8", 18910 argLen: 2, 18911 commutative: true, 18912 generic: true, 18913 }, 18914 { 18915 name: "Neq16", 18916 argLen: 2, 18917 commutative: true, 18918 generic: true, 18919 }, 18920 { 18921 name: "Neq32", 18922 argLen: 2, 18923 commutative: true, 18924 generic: true, 18925 }, 18926 { 18927 name: "Neq64", 18928 argLen: 2, 18929 commutative: true, 18930 generic: true, 18931 }, 18932 { 18933 name: "NeqPtr", 18934 argLen: 2, 18935 commutative: true, 18936 generic: true, 18937 }, 18938 { 18939 name: "NeqInter", 18940 argLen: 2, 18941 generic: true, 18942 }, 18943 { 18944 name: "NeqSlice", 18945 argLen: 2, 18946 generic: true, 18947 }, 18948 { 18949 name: "Neq32F", 18950 argLen: 2, 18951 generic: true, 18952 }, 18953 { 18954 name: "Neq64F", 18955 argLen: 2, 18956 generic: true, 18957 }, 18958 { 18959 name: "Less8", 18960 argLen: 2, 18961 generic: true, 18962 }, 18963 { 18964 name: "Less8U", 18965 argLen: 2, 18966 generic: true, 18967 }, 18968 { 18969 name: "Less16", 18970 argLen: 2, 18971 generic: true, 18972 }, 18973 { 18974 name: "Less16U", 18975 argLen: 2, 18976 generic: true, 18977 }, 18978 { 18979 name: "Less32", 18980 argLen: 2, 18981 generic: true, 18982 }, 18983 { 18984 name: "Less32U", 18985 argLen: 2, 18986 generic: true, 18987 }, 18988 { 18989 name: "Less64", 18990 argLen: 2, 18991 generic: true, 18992 }, 18993 { 18994 name: "Less64U", 18995 argLen: 2, 18996 generic: true, 18997 }, 18998 { 18999 name: "Less32F", 19000 argLen: 2, 19001 generic: true, 19002 }, 19003 { 19004 name: "Less64F", 19005 argLen: 2, 19006 generic: true, 19007 }, 19008 { 19009 name: "Leq8", 19010 argLen: 2, 19011 generic: true, 19012 }, 19013 { 19014 name: "Leq8U", 19015 argLen: 2, 19016 generic: true, 19017 }, 19018 { 19019 name: "Leq16", 19020 argLen: 2, 19021 generic: true, 19022 }, 19023 { 19024 name: "Leq16U", 19025 argLen: 2, 19026 generic: true, 19027 }, 19028 { 19029 name: "Leq32", 19030 argLen: 2, 19031 generic: true, 19032 }, 19033 { 19034 name: "Leq32U", 19035 argLen: 2, 19036 generic: true, 19037 }, 19038 { 19039 name: "Leq64", 19040 argLen: 2, 19041 generic: true, 19042 }, 19043 { 19044 name: "Leq64U", 19045 argLen: 2, 19046 generic: true, 19047 }, 19048 { 19049 name: "Leq32F", 19050 argLen: 2, 19051 generic: true, 19052 }, 19053 { 19054 name: "Leq64F", 19055 argLen: 2, 19056 generic: true, 19057 }, 19058 { 19059 name: "Greater8", 19060 argLen: 2, 19061 generic: true, 19062 }, 19063 { 19064 name: "Greater8U", 19065 argLen: 2, 19066 generic: true, 19067 }, 19068 { 19069 name: "Greater16", 19070 argLen: 2, 19071 generic: true, 19072 }, 19073 { 19074 name: "Greater16U", 19075 argLen: 2, 19076 generic: true, 19077 }, 19078 { 19079 name: "Greater32", 19080 argLen: 2, 19081 generic: true, 19082 }, 19083 { 19084 name: "Greater32U", 19085 argLen: 2, 19086 generic: true, 19087 }, 19088 { 19089 name: "Greater64", 19090 argLen: 2, 19091 generic: true, 19092 }, 19093 { 19094 name: "Greater64U", 19095 argLen: 2, 19096 generic: true, 19097 }, 19098 { 19099 name: "Greater32F", 19100 argLen: 2, 19101 generic: true, 19102 }, 19103 { 19104 name: "Greater64F", 19105 argLen: 2, 19106 generic: true, 19107 }, 19108 { 19109 name: "Geq8", 19110 argLen: 2, 19111 generic: true, 19112 }, 19113 { 19114 name: "Geq8U", 19115 argLen: 2, 19116 generic: true, 19117 }, 19118 { 19119 name: "Geq16", 19120 argLen: 2, 19121 generic: true, 19122 }, 19123 { 19124 name: "Geq16U", 19125 argLen: 2, 19126 generic: true, 19127 }, 19128 { 19129 name: "Geq32", 19130 argLen: 2, 19131 generic: true, 19132 }, 19133 { 19134 name: "Geq32U", 19135 argLen: 2, 19136 generic: true, 19137 }, 19138 { 19139 name: "Geq64", 19140 argLen: 2, 19141 generic: true, 19142 }, 19143 { 19144 name: "Geq64U", 19145 argLen: 2, 19146 generic: true, 19147 }, 19148 { 19149 name: "Geq32F", 19150 argLen: 2, 19151 generic: true, 19152 }, 19153 { 19154 name: "Geq64F", 19155 argLen: 2, 19156 generic: true, 19157 }, 19158 { 19159 name: "AndB", 19160 argLen: 2, 19161 generic: true, 19162 }, 19163 { 19164 name: "OrB", 19165 argLen: 2, 19166 generic: true, 19167 }, 19168 { 19169 name: "EqB", 19170 argLen: 2, 19171 generic: true, 19172 }, 19173 { 19174 name: "NeqB", 19175 argLen: 2, 19176 generic: true, 19177 }, 19178 { 19179 name: "Not", 19180 argLen: 1, 19181 generic: true, 19182 }, 19183 { 19184 name: "Neg8", 19185 argLen: 1, 19186 generic: true, 19187 }, 19188 { 19189 name: "Neg16", 19190 argLen: 1, 19191 generic: true, 19192 }, 19193 { 19194 name: "Neg32", 19195 argLen: 1, 19196 generic: true, 19197 }, 19198 { 19199 name: "Neg64", 19200 argLen: 1, 19201 generic: true, 19202 }, 19203 { 19204 name: "Neg32F", 19205 argLen: 1, 19206 generic: true, 19207 }, 19208 { 19209 name: "Neg64F", 19210 argLen: 1, 19211 generic: true, 19212 }, 19213 { 19214 name: "Com8", 19215 argLen: 1, 19216 generic: true, 19217 }, 19218 { 19219 name: "Com16", 19220 argLen: 1, 19221 generic: true, 19222 }, 19223 { 19224 name: "Com32", 19225 argLen: 1, 19226 generic: true, 19227 }, 19228 { 19229 name: "Com64", 19230 argLen: 1, 19231 generic: true, 19232 }, 19233 { 19234 name: "Ctz32", 19235 argLen: 1, 19236 generic: true, 19237 }, 19238 { 19239 name: "Ctz64", 19240 argLen: 1, 19241 generic: true, 19242 }, 19243 { 19244 name: "Bswap32", 19245 argLen: 1, 19246 generic: true, 19247 }, 19248 { 19249 name: "Bswap64", 19250 argLen: 1, 19251 generic: true, 19252 }, 19253 { 19254 name: "Sqrt", 19255 argLen: 1, 19256 generic: true, 19257 }, 19258 { 19259 name: "Phi", 19260 argLen: -1, 19261 generic: true, 19262 }, 19263 { 19264 name: "Copy", 19265 argLen: 1, 19266 generic: true, 19267 }, 19268 { 19269 name: "Convert", 19270 argLen: 2, 19271 generic: true, 19272 }, 19273 { 19274 name: "ConstBool", 19275 auxType: auxBool, 19276 argLen: 0, 19277 generic: true, 19278 }, 19279 { 19280 name: "ConstString", 19281 auxType: auxString, 19282 argLen: 0, 19283 generic: true, 19284 }, 19285 { 19286 name: "ConstNil", 19287 argLen: 0, 19288 generic: true, 19289 }, 19290 { 19291 name: "Const8", 19292 auxType: auxInt8, 19293 argLen: 0, 19294 generic: true, 19295 }, 19296 { 19297 name: "Const16", 19298 auxType: auxInt16, 19299 argLen: 0, 19300 generic: true, 19301 }, 19302 { 19303 name: "Const32", 19304 auxType: auxInt32, 19305 argLen: 0, 19306 generic: true, 19307 }, 19308 { 19309 name: "Const64", 19310 auxType: auxInt64, 19311 argLen: 0, 19312 generic: true, 19313 }, 19314 { 19315 name: "Const32F", 19316 auxType: auxFloat32, 19317 argLen: 0, 19318 generic: true, 19319 }, 19320 { 19321 name: "Const64F", 19322 auxType: auxFloat64, 19323 argLen: 0, 19324 generic: true, 19325 }, 19326 { 19327 name: "ConstInterface", 19328 argLen: 0, 19329 generic: true, 19330 }, 19331 { 19332 name: "ConstSlice", 19333 argLen: 0, 19334 generic: true, 19335 }, 19336 { 19337 name: "InitMem", 19338 argLen: 0, 19339 generic: true, 19340 }, 19341 { 19342 name: "Arg", 19343 auxType: auxSymOff, 19344 argLen: 0, 19345 generic: true, 19346 }, 19347 { 19348 name: "Addr", 19349 auxType: auxSym, 19350 argLen: 1, 19351 generic: true, 19352 }, 19353 { 19354 name: "SP", 19355 argLen: 0, 19356 generic: true, 19357 }, 19358 { 19359 name: "SB", 19360 argLen: 0, 19361 generic: true, 19362 }, 19363 { 19364 name: "Func", 19365 auxType: auxSym, 19366 argLen: 0, 19367 generic: true, 19368 }, 19369 { 19370 name: "Load", 19371 argLen: 2, 19372 generic: true, 19373 }, 19374 { 19375 name: "Store", 19376 auxType: auxInt64, 19377 argLen: 3, 19378 generic: true, 19379 }, 19380 { 19381 name: "Move", 19382 auxType: auxSizeAndAlign, 19383 argLen: 3, 19384 generic: true, 19385 }, 19386 { 19387 name: "Zero", 19388 auxType: auxSizeAndAlign, 19389 argLen: 2, 19390 generic: true, 19391 }, 19392 { 19393 name: "StoreWB", 19394 auxType: auxInt64, 19395 argLen: 3, 19396 generic: true, 19397 }, 19398 { 19399 name: "MoveWB", 19400 auxType: auxSymSizeAndAlign, 19401 argLen: 3, 19402 generic: true, 19403 }, 19404 { 19405 name: "MoveWBVolatile", 19406 auxType: auxSymSizeAndAlign, 19407 argLen: 3, 19408 generic: true, 19409 }, 19410 { 19411 name: "ZeroWB", 19412 auxType: auxSymSizeAndAlign, 19413 argLen: 2, 19414 generic: true, 19415 }, 19416 { 19417 name: "ClosureCall", 19418 auxType: auxInt64, 19419 argLen: 3, 19420 call: true, 19421 generic: true, 19422 }, 19423 { 19424 name: "StaticCall", 19425 auxType: auxSymOff, 19426 argLen: 1, 19427 call: true, 19428 generic: true, 19429 }, 19430 { 19431 name: "DeferCall", 19432 auxType: auxInt64, 19433 argLen: 1, 19434 call: true, 19435 generic: true, 19436 }, 19437 { 19438 name: "GoCall", 19439 auxType: auxInt64, 19440 argLen: 1, 19441 call: true, 19442 generic: true, 19443 }, 19444 { 19445 name: "InterCall", 19446 auxType: auxInt64, 19447 argLen: 2, 19448 call: true, 19449 generic: true, 19450 }, 19451 { 19452 name: "SignExt8to16", 19453 argLen: 1, 19454 generic: true, 19455 }, 19456 { 19457 name: "SignExt8to32", 19458 argLen: 1, 19459 generic: true, 19460 }, 19461 { 19462 name: "SignExt8to64", 19463 argLen: 1, 19464 generic: true, 19465 }, 19466 { 19467 name: "SignExt16to32", 19468 argLen: 1, 19469 generic: true, 19470 }, 19471 { 19472 name: "SignExt16to64", 19473 argLen: 1, 19474 generic: true, 19475 }, 19476 { 19477 name: "SignExt32to64", 19478 argLen: 1, 19479 generic: true, 19480 }, 19481 { 19482 name: "ZeroExt8to16", 19483 argLen: 1, 19484 generic: true, 19485 }, 19486 { 19487 name: "ZeroExt8to32", 19488 argLen: 1, 19489 generic: true, 19490 }, 19491 { 19492 name: "ZeroExt8to64", 19493 argLen: 1, 19494 generic: true, 19495 }, 19496 { 19497 name: "ZeroExt16to32", 19498 argLen: 1, 19499 generic: true, 19500 }, 19501 { 19502 name: "ZeroExt16to64", 19503 argLen: 1, 19504 generic: true, 19505 }, 19506 { 19507 name: "ZeroExt32to64", 19508 argLen: 1, 19509 generic: true, 19510 }, 19511 { 19512 name: "Trunc16to8", 19513 argLen: 1, 19514 generic: true, 19515 }, 19516 { 19517 name: "Trunc32to8", 19518 argLen: 1, 19519 generic: true, 19520 }, 19521 { 19522 name: "Trunc32to16", 19523 argLen: 1, 19524 generic: true, 19525 }, 19526 { 19527 name: "Trunc64to8", 19528 argLen: 1, 19529 generic: true, 19530 }, 19531 { 19532 name: "Trunc64to16", 19533 argLen: 1, 19534 generic: true, 19535 }, 19536 { 19537 name: "Trunc64to32", 19538 argLen: 1, 19539 generic: true, 19540 }, 19541 { 19542 name: "Cvt32to32F", 19543 argLen: 1, 19544 generic: true, 19545 }, 19546 { 19547 name: "Cvt32to64F", 19548 argLen: 1, 19549 generic: true, 19550 }, 19551 { 19552 name: "Cvt64to32F", 19553 argLen: 1, 19554 generic: true, 19555 }, 19556 { 19557 name: "Cvt64to64F", 19558 argLen: 1, 19559 generic: true, 19560 }, 19561 { 19562 name: "Cvt32Fto32", 19563 argLen: 1, 19564 generic: true, 19565 }, 19566 { 19567 name: "Cvt32Fto64", 19568 argLen: 1, 19569 generic: true, 19570 }, 19571 { 19572 name: "Cvt64Fto32", 19573 argLen: 1, 19574 generic: true, 19575 }, 19576 { 19577 name: "Cvt64Fto64", 19578 argLen: 1, 19579 generic: true, 19580 }, 19581 { 19582 name: "Cvt32Fto64F", 19583 argLen: 1, 19584 generic: true, 19585 }, 19586 { 19587 name: "Cvt64Fto32F", 19588 argLen: 1, 19589 generic: true, 19590 }, 19591 { 19592 name: "IsNonNil", 19593 argLen: 1, 19594 generic: true, 19595 }, 19596 { 19597 name: "IsInBounds", 19598 argLen: 2, 19599 generic: true, 19600 }, 19601 { 19602 name: "IsSliceInBounds", 19603 argLen: 2, 19604 generic: true, 19605 }, 19606 { 19607 name: "NilCheck", 19608 argLen: 2, 19609 generic: true, 19610 }, 19611 { 19612 name: "GetG", 19613 argLen: 1, 19614 generic: true, 19615 }, 19616 { 19617 name: "GetClosurePtr", 19618 argLen: 0, 19619 generic: true, 19620 }, 19621 { 19622 name: "PtrIndex", 19623 argLen: 2, 19624 generic: true, 19625 }, 19626 { 19627 name: "OffPtr", 19628 auxType: auxInt64, 19629 argLen: 1, 19630 generic: true, 19631 }, 19632 { 19633 name: "SliceMake", 19634 argLen: 3, 19635 generic: true, 19636 }, 19637 { 19638 name: "SlicePtr", 19639 argLen: 1, 19640 generic: true, 19641 }, 19642 { 19643 name: "SliceLen", 19644 argLen: 1, 19645 generic: true, 19646 }, 19647 { 19648 name: "SliceCap", 19649 argLen: 1, 19650 generic: true, 19651 }, 19652 { 19653 name: "ComplexMake", 19654 argLen: 2, 19655 generic: true, 19656 }, 19657 { 19658 name: "ComplexReal", 19659 argLen: 1, 19660 generic: true, 19661 }, 19662 { 19663 name: "ComplexImag", 19664 argLen: 1, 19665 generic: true, 19666 }, 19667 { 19668 name: "StringMake", 19669 argLen: 2, 19670 generic: true, 19671 }, 19672 { 19673 name: "StringPtr", 19674 argLen: 1, 19675 generic: true, 19676 }, 19677 { 19678 name: "StringLen", 19679 argLen: 1, 19680 generic: true, 19681 }, 19682 { 19683 name: "IMake", 19684 argLen: 2, 19685 generic: true, 19686 }, 19687 { 19688 name: "ITab", 19689 argLen: 1, 19690 generic: true, 19691 }, 19692 { 19693 name: "IData", 19694 argLen: 1, 19695 generic: true, 19696 }, 19697 { 19698 name: "StructMake0", 19699 argLen: 0, 19700 generic: true, 19701 }, 19702 { 19703 name: "StructMake1", 19704 argLen: 1, 19705 generic: true, 19706 }, 19707 { 19708 name: "StructMake2", 19709 argLen: 2, 19710 generic: true, 19711 }, 19712 { 19713 name: "StructMake3", 19714 argLen: 3, 19715 generic: true, 19716 }, 19717 { 19718 name: "StructMake4", 19719 argLen: 4, 19720 generic: true, 19721 }, 19722 { 19723 name: "StructSelect", 19724 auxType: auxInt64, 19725 argLen: 1, 19726 generic: true, 19727 }, 19728 { 19729 name: "ArrayMake0", 19730 argLen: 0, 19731 generic: true, 19732 }, 19733 { 19734 name: "ArrayMake1", 19735 argLen: 1, 19736 generic: true, 19737 }, 19738 { 19739 name: "ArraySelect", 19740 auxType: auxInt64, 19741 argLen: 1, 19742 generic: true, 19743 }, 19744 { 19745 name: "StoreReg", 19746 argLen: 1, 19747 generic: true, 19748 }, 19749 { 19750 name: "LoadReg", 19751 argLen: 1, 19752 generic: true, 19753 }, 19754 { 19755 name: "FwdRef", 19756 auxType: auxSym, 19757 argLen: 0, 19758 generic: true, 19759 }, 19760 { 19761 name: "Unknown", 19762 argLen: 0, 19763 generic: true, 19764 }, 19765 { 19766 name: "VarDef", 19767 auxType: auxSym, 19768 argLen: 1, 19769 generic: true, 19770 }, 19771 { 19772 name: "VarKill", 19773 auxType: auxSym, 19774 argLen: 1, 19775 generic: true, 19776 }, 19777 { 19778 name: "VarLive", 19779 auxType: auxSym, 19780 argLen: 1, 19781 generic: true, 19782 }, 19783 { 19784 name: "KeepAlive", 19785 argLen: 2, 19786 generic: true, 19787 }, 19788 { 19789 name: "Int64Make", 19790 argLen: 2, 19791 generic: true, 19792 }, 19793 { 19794 name: "Int64Hi", 19795 argLen: 1, 19796 generic: true, 19797 }, 19798 { 19799 name: "Int64Lo", 19800 argLen: 1, 19801 generic: true, 19802 }, 19803 { 19804 name: "Add32carry", 19805 argLen: 2, 19806 commutative: true, 19807 generic: true, 19808 }, 19809 { 19810 name: "Add32withcarry", 19811 argLen: 3, 19812 commutative: true, 19813 generic: true, 19814 }, 19815 { 19816 name: "Sub32carry", 19817 argLen: 2, 19818 generic: true, 19819 }, 19820 { 19821 name: "Sub32withcarry", 19822 argLen: 3, 19823 generic: true, 19824 }, 19825 { 19826 name: "Signmask", 19827 argLen: 1, 19828 generic: true, 19829 }, 19830 { 19831 name: "Zeromask", 19832 argLen: 1, 19833 generic: true, 19834 }, 19835 { 19836 name: "Slicemask", 19837 argLen: 1, 19838 generic: true, 19839 }, 19840 { 19841 name: "Cvt32Uto32F", 19842 argLen: 1, 19843 generic: true, 19844 }, 19845 { 19846 name: "Cvt32Uto64F", 19847 argLen: 1, 19848 generic: true, 19849 }, 19850 { 19851 name: "Cvt32Fto32U", 19852 argLen: 1, 19853 generic: true, 19854 }, 19855 { 19856 name: "Cvt64Fto32U", 19857 argLen: 1, 19858 generic: true, 19859 }, 19860 { 19861 name: "Cvt64Uto32F", 19862 argLen: 1, 19863 generic: true, 19864 }, 19865 { 19866 name: "Cvt64Uto64F", 19867 argLen: 1, 19868 generic: true, 19869 }, 19870 { 19871 name: "Cvt32Fto64U", 19872 argLen: 1, 19873 generic: true, 19874 }, 19875 { 19876 name: "Cvt64Fto64U", 19877 argLen: 1, 19878 generic: true, 19879 }, 19880 { 19881 name: "Select0", 19882 argLen: 1, 19883 generic: true, 19884 }, 19885 { 19886 name: "Select1", 19887 argLen: 1, 19888 generic: true, 19889 }, 19890 { 19891 name: "AtomicLoad32", 19892 argLen: 2, 19893 generic: true, 19894 }, 19895 { 19896 name: "AtomicLoad64", 19897 argLen: 2, 19898 generic: true, 19899 }, 19900 { 19901 name: "AtomicLoadPtr", 19902 argLen: 2, 19903 generic: true, 19904 }, 19905 { 19906 name: "AtomicStore32", 19907 argLen: 3, 19908 generic: true, 19909 }, 19910 { 19911 name: "AtomicStore64", 19912 argLen: 3, 19913 generic: true, 19914 }, 19915 { 19916 name: "AtomicStorePtrNoWB", 19917 argLen: 3, 19918 generic: true, 19919 }, 19920 { 19921 name: "AtomicExchange32", 19922 argLen: 3, 19923 generic: true, 19924 }, 19925 { 19926 name: "AtomicExchange64", 19927 argLen: 3, 19928 generic: true, 19929 }, 19930 { 19931 name: "AtomicAdd32", 19932 argLen: 3, 19933 generic: true, 19934 }, 19935 { 19936 name: "AtomicAdd64", 19937 argLen: 3, 19938 generic: true, 19939 }, 19940 { 19941 name: "AtomicCompareAndSwap32", 19942 argLen: 4, 19943 generic: true, 19944 }, 19945 { 19946 name: "AtomicCompareAndSwap64", 19947 argLen: 4, 19948 generic: true, 19949 }, 19950 { 19951 name: "AtomicAnd8", 19952 argLen: 3, 19953 generic: true, 19954 }, 19955 { 19956 name: "AtomicOr8", 19957 argLen: 3, 19958 generic: true, 19959 }, 19960 } 19961 19962 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 19963 func (o Op) String() string { return opcodeTable[o].name } 19964 func (o Op) UsesScratch() bool { return opcodeTable[o].usesScratch } 19965 19966 var registers386 = [...]Register{ 19967 {0, x86.REG_AX, "AX"}, 19968 {1, x86.REG_CX, "CX"}, 19969 {2, x86.REG_DX, "DX"}, 19970 {3, x86.REG_BX, "BX"}, 19971 {4, x86.REGSP, "SP"}, 19972 {5, x86.REG_BP, "BP"}, 19973 {6, x86.REG_SI, "SI"}, 19974 {7, x86.REG_DI, "DI"}, 19975 {8, x86.REG_X0, "X0"}, 19976 {9, x86.REG_X1, "X1"}, 19977 {10, x86.REG_X2, "X2"}, 19978 {11, x86.REG_X3, "X3"}, 19979 {12, x86.REG_X4, "X4"}, 19980 {13, x86.REG_X5, "X5"}, 19981 {14, x86.REG_X6, "X6"}, 19982 {15, x86.REG_X7, "X7"}, 19983 {16, 0, "SB"}, 19984 } 19985 var gpRegMask386 = regMask(239) 19986 var fpRegMask386 = regMask(65280) 19987 var specialRegMask386 = regMask(0) 19988 var framepointerReg386 = int8(5) 19989 var linkReg386 = int8(-1) 19990 var registersAMD64 = [...]Register{ 19991 {0, x86.REG_AX, "AX"}, 19992 {1, x86.REG_CX, "CX"}, 19993 {2, x86.REG_DX, "DX"}, 19994 {3, x86.REG_BX, "BX"}, 19995 {4, x86.REGSP, "SP"}, 19996 {5, x86.REG_BP, "BP"}, 19997 {6, x86.REG_SI, "SI"}, 19998 {7, x86.REG_DI, "DI"}, 19999 {8, x86.REG_R8, "R8"}, 20000 {9, x86.REG_R9, "R9"}, 20001 {10, x86.REG_R10, "R10"}, 20002 {11, x86.REG_R11, "R11"}, 20003 {12, x86.REG_R12, "R12"}, 20004 {13, x86.REG_R13, "R13"}, 20005 {14, x86.REG_R14, "R14"}, 20006 {15, x86.REG_R15, "R15"}, 20007 {16, x86.REG_X0, "X0"}, 20008 {17, x86.REG_X1, "X1"}, 20009 {18, x86.REG_X2, "X2"}, 20010 {19, x86.REG_X3, "X3"}, 20011 {20, x86.REG_X4, "X4"}, 20012 {21, x86.REG_X5, "X5"}, 20013 {22, x86.REG_X6, "X6"}, 20014 {23, x86.REG_X7, "X7"}, 20015 {24, x86.REG_X8, "X8"}, 20016 {25, x86.REG_X9, "X9"}, 20017 {26, x86.REG_X10, "X10"}, 20018 {27, x86.REG_X11, "X11"}, 20019 {28, x86.REG_X12, "X12"}, 20020 {29, x86.REG_X13, "X13"}, 20021 {30, x86.REG_X14, "X14"}, 20022 {31, x86.REG_X15, "X15"}, 20023 {32, 0, "SB"}, 20024 } 20025 var gpRegMaskAMD64 = regMask(65519) 20026 var fpRegMaskAMD64 = regMask(4294901760) 20027 var specialRegMaskAMD64 = regMask(0) 20028 var framepointerRegAMD64 = int8(5) 20029 var linkRegAMD64 = int8(-1) 20030 var registersARM = [...]Register{ 20031 {0, arm.REG_R0, "R0"}, 20032 {1, arm.REG_R1, "R1"}, 20033 {2, arm.REG_R2, "R2"}, 20034 {3, arm.REG_R3, "R3"}, 20035 {4, arm.REG_R4, "R4"}, 20036 {5, arm.REG_R5, "R5"}, 20037 {6, arm.REG_R6, "R6"}, 20038 {7, arm.REG_R7, "R7"}, 20039 {8, arm.REG_R8, "R8"}, 20040 {9, arm.REG_R9, "R9"}, 20041 {10, arm.REGG, "g"}, 20042 {11, arm.REG_R11, "R11"}, 20043 {12, arm.REG_R12, "R12"}, 20044 {13, arm.REGSP, "SP"}, 20045 {14, arm.REG_R14, "R14"}, 20046 {15, arm.REG_R15, "R15"}, 20047 {16, arm.REG_F0, "F0"}, 20048 {17, arm.REG_F1, "F1"}, 20049 {18, arm.REG_F2, "F2"}, 20050 {19, arm.REG_F3, "F3"}, 20051 {20, arm.REG_F4, "F4"}, 20052 {21, arm.REG_F5, "F5"}, 20053 {22, arm.REG_F6, "F6"}, 20054 {23, arm.REG_F7, "F7"}, 20055 {24, arm.REG_F8, "F8"}, 20056 {25, arm.REG_F9, "F9"}, 20057 {26, arm.REG_F10, "F10"}, 20058 {27, arm.REG_F11, "F11"}, 20059 {28, arm.REG_F12, "F12"}, 20060 {29, arm.REG_F13, "F13"}, 20061 {30, arm.REG_F14, "F14"}, 20062 {31, arm.REG_F15, "F15"}, 20063 {32, 0, "SB"}, 20064 } 20065 var gpRegMaskARM = regMask(21503) 20066 var fpRegMaskARM = regMask(4294901760) 20067 var specialRegMaskARM = regMask(0) 20068 var framepointerRegARM = int8(-1) 20069 var linkRegARM = int8(14) 20070 var registersARM64 = [...]Register{ 20071 {0, arm64.REG_R0, "R0"}, 20072 {1, arm64.REG_R1, "R1"}, 20073 {2, arm64.REG_R2, "R2"}, 20074 {3, arm64.REG_R3, "R3"}, 20075 {4, arm64.REG_R4, "R4"}, 20076 {5, arm64.REG_R5, "R5"}, 20077 {6, arm64.REG_R6, "R6"}, 20078 {7, arm64.REG_R7, "R7"}, 20079 {8, arm64.REG_R8, "R8"}, 20080 {9, arm64.REG_R9, "R9"}, 20081 {10, arm64.REG_R10, "R10"}, 20082 {11, arm64.REG_R11, "R11"}, 20083 {12, arm64.REG_R12, "R12"}, 20084 {13, arm64.REG_R13, "R13"}, 20085 {14, arm64.REG_R14, "R14"}, 20086 {15, arm64.REG_R15, "R15"}, 20087 {16, arm64.REG_R16, "R16"}, 20088 {17, arm64.REG_R17, "R17"}, 20089 {18, arm64.REG_R18, "R18"}, 20090 {19, arm64.REG_R19, "R19"}, 20091 {20, arm64.REG_R20, "R20"}, 20092 {21, arm64.REG_R21, "R21"}, 20093 {22, arm64.REG_R22, "R22"}, 20094 {23, arm64.REG_R23, "R23"}, 20095 {24, arm64.REG_R24, "R24"}, 20096 {25, arm64.REG_R25, "R25"}, 20097 {26, arm64.REG_R26, "R26"}, 20098 {27, arm64.REGG, "g"}, 20099 {28, arm64.REG_R29, "R29"}, 20100 {29, arm64.REG_R30, "R30"}, 20101 {30, arm64.REGSP, "SP"}, 20102 {31, arm64.REG_F0, "F0"}, 20103 {32, arm64.REG_F1, "F1"}, 20104 {33, arm64.REG_F2, "F2"}, 20105 {34, arm64.REG_F3, "F3"}, 20106 {35, arm64.REG_F4, "F4"}, 20107 {36, arm64.REG_F5, "F5"}, 20108 {37, arm64.REG_F6, "F6"}, 20109 {38, arm64.REG_F7, "F7"}, 20110 {39, arm64.REG_F8, "F8"}, 20111 {40, arm64.REG_F9, "F9"}, 20112 {41, arm64.REG_F10, "F10"}, 20113 {42, arm64.REG_F11, "F11"}, 20114 {43, arm64.REG_F12, "F12"}, 20115 {44, arm64.REG_F13, "F13"}, 20116 {45, arm64.REG_F14, "F14"}, 20117 {46, arm64.REG_F15, "F15"}, 20118 {47, arm64.REG_F16, "F16"}, 20119 {48, arm64.REG_F17, "F17"}, 20120 {49, arm64.REG_F18, "F18"}, 20121 {50, arm64.REG_F19, "F19"}, 20122 {51, arm64.REG_F20, "F20"}, 20123 {52, arm64.REG_F21, "F21"}, 20124 {53, arm64.REG_F22, "F22"}, 20125 {54, arm64.REG_F23, "F23"}, 20126 {55, arm64.REG_F24, "F24"}, 20127 {56, arm64.REG_F25, "F25"}, 20128 {57, arm64.REG_F26, "F26"}, 20129 {58, arm64.REG_F27, "F27"}, 20130 {59, arm64.REG_F28, "F28"}, 20131 {60, arm64.REG_F29, "F29"}, 20132 {61, arm64.REG_F30, "F30"}, 20133 {62, arm64.REG_F31, "F31"}, 20134 {63, 0, "SB"}, 20135 } 20136 var gpRegMaskARM64 = regMask(670826495) 20137 var fpRegMaskARM64 = regMask(9223372034707292160) 20138 var specialRegMaskARM64 = regMask(0) 20139 var framepointerRegARM64 = int8(-1) 20140 var linkRegARM64 = int8(29) 20141 var registersMIPS64 = [...]Register{ 20142 {0, mips.REG_R0, "R0"}, 20143 {1, mips.REG_R1, "R1"}, 20144 {2, mips.REG_R2, "R2"}, 20145 {3, mips.REG_R3, "R3"}, 20146 {4, mips.REG_R4, "R4"}, 20147 {5, mips.REG_R5, "R5"}, 20148 {6, mips.REG_R6, "R6"}, 20149 {7, mips.REG_R7, "R7"}, 20150 {8, mips.REG_R8, "R8"}, 20151 {9, mips.REG_R9, "R9"}, 20152 {10, mips.REG_R10, "R10"}, 20153 {11, mips.REG_R11, "R11"}, 20154 {12, mips.REG_R12, "R12"}, 20155 {13, mips.REG_R13, "R13"}, 20156 {14, mips.REG_R14, "R14"}, 20157 {15, mips.REG_R15, "R15"}, 20158 {16, mips.REG_R16, "R16"}, 20159 {17, mips.REG_R17, "R17"}, 20160 {18, mips.REG_R18, "R18"}, 20161 {19, mips.REG_R19, "R19"}, 20162 {20, mips.REG_R20, "R20"}, 20163 {21, mips.REG_R21, "R21"}, 20164 {22, mips.REG_R22, "R22"}, 20165 {23, mips.REG_R24, "R24"}, 20166 {24, mips.REG_R25, "R25"}, 20167 {25, mips.REGSP, "SP"}, 20168 {26, mips.REGG, "g"}, 20169 {27, mips.REG_R31, "R31"}, 20170 {28, mips.REG_F0, "F0"}, 20171 {29, mips.REG_F1, "F1"}, 20172 {30, mips.REG_F2, "F2"}, 20173 {31, mips.REG_F3, "F3"}, 20174 {32, mips.REG_F4, "F4"}, 20175 {33, mips.REG_F5, "F5"}, 20176 {34, mips.REG_F6, "F6"}, 20177 {35, mips.REG_F7, "F7"}, 20178 {36, mips.REG_F8, "F8"}, 20179 {37, mips.REG_F9, "F9"}, 20180 {38, mips.REG_F10, "F10"}, 20181 {39, mips.REG_F11, "F11"}, 20182 {40, mips.REG_F12, "F12"}, 20183 {41, mips.REG_F13, "F13"}, 20184 {42, mips.REG_F14, "F14"}, 20185 {43, mips.REG_F15, "F15"}, 20186 {44, mips.REG_F16, "F16"}, 20187 {45, mips.REG_F17, "F17"}, 20188 {46, mips.REG_F18, "F18"}, 20189 {47, mips.REG_F19, "F19"}, 20190 {48, mips.REG_F20, "F20"}, 20191 {49, mips.REG_F21, "F21"}, 20192 {50, mips.REG_F22, "F22"}, 20193 {51, mips.REG_F23, "F23"}, 20194 {52, mips.REG_F24, "F24"}, 20195 {53, mips.REG_F25, "F25"}, 20196 {54, mips.REG_F26, "F26"}, 20197 {55, mips.REG_F27, "F27"}, 20198 {56, mips.REG_F28, "F28"}, 20199 {57, mips.REG_F29, "F29"}, 20200 {58, mips.REG_F30, "F30"}, 20201 {59, mips.REG_F31, "F31"}, 20202 {60, mips.REG_HI, "HI"}, 20203 {61, mips.REG_LO, "LO"}, 20204 {62, 0, "SB"}, 20205 } 20206 var gpRegMaskMIPS64 = regMask(167772158) 20207 var fpRegMaskMIPS64 = regMask(1152921504338411520) 20208 var specialRegMaskMIPS64 = regMask(3458764513820540928) 20209 var framepointerRegMIPS64 = int8(-1) 20210 var linkRegMIPS64 = int8(27) 20211 var registersPPC64 = [...]Register{ 20212 {0, ppc64.REG_R0, "R0"}, 20213 {1, ppc64.REGSP, "SP"}, 20214 {2, 0, "SB"}, 20215 {3, ppc64.REG_R3, "R3"}, 20216 {4, ppc64.REG_R4, "R4"}, 20217 {5, ppc64.REG_R5, "R5"}, 20218 {6, ppc64.REG_R6, "R6"}, 20219 {7, ppc64.REG_R7, "R7"}, 20220 {8, ppc64.REG_R8, "R8"}, 20221 {9, ppc64.REG_R9, "R9"}, 20222 {10, ppc64.REG_R10, "R10"}, 20223 {11, ppc64.REG_R11, "R11"}, 20224 {12, ppc64.REG_R12, "R12"}, 20225 {13, ppc64.REG_R13, "R13"}, 20226 {14, ppc64.REG_R14, "R14"}, 20227 {15, ppc64.REG_R15, "R15"}, 20228 {16, ppc64.REG_R16, "R16"}, 20229 {17, ppc64.REG_R17, "R17"}, 20230 {18, ppc64.REG_R18, "R18"}, 20231 {19, ppc64.REG_R19, "R19"}, 20232 {20, ppc64.REG_R20, "R20"}, 20233 {21, ppc64.REG_R21, "R21"}, 20234 {22, ppc64.REG_R22, "R22"}, 20235 {23, ppc64.REG_R23, "R23"}, 20236 {24, ppc64.REG_R24, "R24"}, 20237 {25, ppc64.REG_R25, "R25"}, 20238 {26, ppc64.REG_R26, "R26"}, 20239 {27, ppc64.REG_R27, "R27"}, 20240 {28, ppc64.REG_R28, "R28"}, 20241 {29, ppc64.REG_R29, "R29"}, 20242 {30, ppc64.REGG, "g"}, 20243 {31, ppc64.REG_R31, "R31"}, 20244 {32, ppc64.REG_F0, "F0"}, 20245 {33, ppc64.REG_F1, "F1"}, 20246 {34, ppc64.REG_F2, "F2"}, 20247 {35, ppc64.REG_F3, "F3"}, 20248 {36, ppc64.REG_F4, "F4"}, 20249 {37, ppc64.REG_F5, "F5"}, 20250 {38, ppc64.REG_F6, "F6"}, 20251 {39, ppc64.REG_F7, "F7"}, 20252 {40, ppc64.REG_F8, "F8"}, 20253 {41, ppc64.REG_F9, "F9"}, 20254 {42, ppc64.REG_F10, "F10"}, 20255 {43, ppc64.REG_F11, "F11"}, 20256 {44, ppc64.REG_F12, "F12"}, 20257 {45, ppc64.REG_F13, "F13"}, 20258 {46, ppc64.REG_F14, "F14"}, 20259 {47, ppc64.REG_F15, "F15"}, 20260 {48, ppc64.REG_F16, "F16"}, 20261 {49, ppc64.REG_F17, "F17"}, 20262 {50, ppc64.REG_F18, "F18"}, 20263 {51, ppc64.REG_F19, "F19"}, 20264 {52, ppc64.REG_F20, "F20"}, 20265 {53, ppc64.REG_F21, "F21"}, 20266 {54, ppc64.REG_F22, "F22"}, 20267 {55, ppc64.REG_F23, "F23"}, 20268 {56, ppc64.REG_F24, "F24"}, 20269 {57, ppc64.REG_F25, "F25"}, 20270 {58, ppc64.REG_F26, "F26"}, 20271 {59, ppc64.REG_F27, "F27"}, 20272 {60, ppc64.REG_F28, "F28"}, 20273 {61, ppc64.REG_F29, "F29"}, 20274 {62, ppc64.REG_F30, "F30"}, 20275 {63, ppc64.REG_F31, "F31"}, 20276 } 20277 var gpRegMaskPPC64 = regMask(1073733624) 20278 var fpRegMaskPPC64 = regMask(576460743713488896) 20279 var specialRegMaskPPC64 = regMask(0) 20280 var framepointerRegPPC64 = int8(1) 20281 var linkRegPPC64 = int8(-1) 20282 var registersS390X = [...]Register{ 20283 {0, s390x.REG_R0, "R0"}, 20284 {1, s390x.REG_R1, "R1"}, 20285 {2, s390x.REG_R2, "R2"}, 20286 {3, s390x.REG_R3, "R3"}, 20287 {4, s390x.REG_R4, "R4"}, 20288 {5, s390x.REG_R5, "R5"}, 20289 {6, s390x.REG_R6, "R6"}, 20290 {7, s390x.REG_R7, "R7"}, 20291 {8, s390x.REG_R8, "R8"}, 20292 {9, s390x.REG_R9, "R9"}, 20293 {10, s390x.REG_R10, "R10"}, 20294 {11, s390x.REG_R11, "R11"}, 20295 {12, s390x.REG_R12, "R12"}, 20296 {13, s390x.REGG, "g"}, 20297 {14, s390x.REG_R14, "R14"}, 20298 {15, s390x.REGSP, "SP"}, 20299 {16, s390x.REG_F0, "F0"}, 20300 {17, s390x.REG_F1, "F1"}, 20301 {18, s390x.REG_F2, "F2"}, 20302 {19, s390x.REG_F3, "F3"}, 20303 {20, s390x.REG_F4, "F4"}, 20304 {21, s390x.REG_F5, "F5"}, 20305 {22, s390x.REG_F6, "F6"}, 20306 {23, s390x.REG_F7, "F7"}, 20307 {24, s390x.REG_F8, "F8"}, 20308 {25, s390x.REG_F9, "F9"}, 20309 {26, s390x.REG_F10, "F10"}, 20310 {27, s390x.REG_F11, "F11"}, 20311 {28, s390x.REG_F12, "F12"}, 20312 {29, s390x.REG_F13, "F13"}, 20313 {30, s390x.REG_F14, "F14"}, 20314 {31, s390x.REG_F15, "F15"}, 20315 {32, 0, "SB"}, 20316 } 20317 var gpRegMaskS390X = regMask(21503) 20318 var fpRegMaskS390X = regMask(4294901760) 20319 var specialRegMaskS390X = regMask(0) 20320 var framepointerRegS390X = int8(-1) 20321 var linkRegS390X = int8(14)