github.com/q45/go@v0.0.0-20151101211701-a4fb8c13db3f/src/cmd/compile/internal/arm/prog.go (about) 1 // Copyright 2013 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 package arm 6 7 import ( 8 "cmd/compile/internal/gc" 9 "cmd/internal/obj" 10 "cmd/internal/obj/arm" 11 ) 12 13 const ( 14 RightRdwr = gc.RightRead | gc.RightWrite 15 ) 16 17 // This table gives the basic information about instruction 18 // generated by the compiler and processed in the optimizer. 19 // See opt.h for bit definitions. 20 // 21 // Instructions not generated need not be listed. 22 // As an exception to that rule, we typically write down all the 23 // size variants of an operation even if we just use a subset. 24 // 25 // The table is formatted for 8-space tabs. 26 var progtable = [arm.ALAST]obj.ProgInfo{ 27 obj.ATYPE: {Flags: gc.Pseudo | gc.Skip}, 28 obj.ATEXT: {Flags: gc.Pseudo}, 29 obj.AFUNCDATA: {Flags: gc.Pseudo}, 30 obj.APCDATA: {Flags: gc.Pseudo}, 31 obj.AUNDEF: {Flags: gc.Break}, 32 obj.AUSEFIELD: {Flags: gc.OK}, 33 obj.ACHECKNIL: {Flags: gc.LeftRead}, 34 obj.AVARDEF: {Flags: gc.Pseudo | gc.RightWrite}, 35 obj.AVARKILL: {Flags: gc.Pseudo | gc.RightWrite}, 36 37 // NOP is an internal no-op that also stands 38 // for USED and SET annotations, not the Intel opcode. 39 obj.ANOP: {Flags: gc.LeftRead | gc.RightWrite}, 40 41 // Integer. 42 arm.AADC: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 43 arm.AADD: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 44 arm.AAND: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 45 arm.ABIC: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 46 arm.ACMN: {Flags: gc.SizeL | gc.LeftRead | gc.RightRead}, 47 arm.ACMP: {Flags: gc.SizeL | gc.LeftRead | gc.RightRead}, 48 arm.ADIVU: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 49 arm.ADIV: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 50 arm.AEOR: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 51 arm.AMODU: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 52 arm.AMOD: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 53 arm.AMULALU: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | RightRdwr}, 54 arm.AMULAL: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | RightRdwr}, 55 arm.AMULA: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | RightRdwr}, 56 arm.AMULU: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 57 arm.AMUL: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 58 arm.AMULL: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 59 arm.AMULLU: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 60 arm.AMVN: {Flags: gc.SizeL | gc.LeftRead | gc.RightWrite}, 61 arm.AORR: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 62 arm.ARSB: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 63 arm.ARSC: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 64 arm.ASBC: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 65 arm.ASLL: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 66 arm.ASRA: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 67 arm.ASRL: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 68 arm.ASUB: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 69 arm.ATEQ: {Flags: gc.SizeL | gc.LeftRead | gc.RightRead}, 70 arm.ATST: {Flags: gc.SizeL | gc.LeftRead | gc.RightRead}, 71 72 // Floating point. 73 arm.AADDD: {Flags: gc.SizeD | gc.LeftRead | RightRdwr}, 74 arm.AADDF: {Flags: gc.SizeF | gc.LeftRead | RightRdwr}, 75 arm.ACMPD: {Flags: gc.SizeD | gc.LeftRead | gc.RightRead}, 76 arm.ACMPF: {Flags: gc.SizeF | gc.LeftRead | gc.RightRead}, 77 arm.ADIVD: {Flags: gc.SizeD | gc.LeftRead | RightRdwr}, 78 arm.ADIVF: {Flags: gc.SizeF | gc.LeftRead | RightRdwr}, 79 arm.AMULD: {Flags: gc.SizeD | gc.LeftRead | RightRdwr}, 80 arm.AMULF: {Flags: gc.SizeF | gc.LeftRead | RightRdwr}, 81 arm.ASUBD: {Flags: gc.SizeD | gc.LeftRead | RightRdwr}, 82 arm.ASUBF: {Flags: gc.SizeF | gc.LeftRead | RightRdwr}, 83 arm.ASQRTD: {Flags: gc.SizeD | gc.LeftRead | RightRdwr}, 84 85 // Conversions. 86 arm.AMOVWD: {Flags: gc.SizeD | gc.LeftRead | gc.RightWrite | gc.Conv}, 87 arm.AMOVWF: {Flags: gc.SizeF | gc.LeftRead | gc.RightWrite | gc.Conv}, 88 arm.AMOVDF: {Flags: gc.SizeF | gc.LeftRead | gc.RightWrite | gc.Conv}, 89 arm.AMOVDW: {Flags: gc.SizeL | gc.LeftRead | gc.RightWrite | gc.Conv}, 90 arm.AMOVFD: {Flags: gc.SizeD | gc.LeftRead | gc.RightWrite | gc.Conv}, 91 arm.AMOVFW: {Flags: gc.SizeL | gc.LeftRead | gc.RightWrite | gc.Conv}, 92 93 // Moves. 94 arm.AMOVB: {Flags: gc.SizeB | gc.LeftRead | gc.RightWrite | gc.Move}, 95 arm.AMOVD: {Flags: gc.SizeD | gc.LeftRead | gc.RightWrite | gc.Move}, 96 arm.AMOVF: {Flags: gc.SizeF | gc.LeftRead | gc.RightWrite | gc.Move}, 97 arm.AMOVH: {Flags: gc.SizeW | gc.LeftRead | gc.RightWrite | gc.Move}, 98 arm.AMOVW: {Flags: gc.SizeL | gc.LeftRead | gc.RightWrite | gc.Move}, 99 100 // In addtion, duffzero reads R0,R1 and writes R1. This fact is 101 // encoded in peep.c 102 obj.ADUFFZERO: {Flags: gc.Call}, 103 104 // In addtion, duffcopy reads R1,R2 and writes R0,R1,R2. This fact is 105 // encoded in peep.c 106 obj.ADUFFCOPY: {Flags: gc.Call}, 107 108 // These should be split into the two different conversions instead 109 // of overloading the one. 110 arm.AMOVBS: {Flags: gc.SizeB | gc.LeftRead | gc.RightWrite | gc.Conv}, 111 arm.AMOVBU: {Flags: gc.SizeB | gc.LeftRead | gc.RightWrite | gc.Conv}, 112 arm.AMOVHS: {Flags: gc.SizeW | gc.LeftRead | gc.RightWrite | gc.Conv}, 113 arm.AMOVHU: {Flags: gc.SizeW | gc.LeftRead | gc.RightWrite | gc.Conv}, 114 115 // Jumps. 116 arm.AB: {Flags: gc.Jump | gc.Break}, 117 arm.ABL: {Flags: gc.Call}, 118 arm.ABEQ: {Flags: gc.Cjmp}, 119 arm.ABNE: {Flags: gc.Cjmp}, 120 arm.ABCS: {Flags: gc.Cjmp}, 121 arm.ABHS: {Flags: gc.Cjmp}, 122 arm.ABCC: {Flags: gc.Cjmp}, 123 arm.ABLO: {Flags: gc.Cjmp}, 124 arm.ABMI: {Flags: gc.Cjmp}, 125 arm.ABPL: {Flags: gc.Cjmp}, 126 arm.ABVS: {Flags: gc.Cjmp}, 127 arm.ABVC: {Flags: gc.Cjmp}, 128 arm.ABHI: {Flags: gc.Cjmp}, 129 arm.ABLS: {Flags: gc.Cjmp}, 130 arm.ABGE: {Flags: gc.Cjmp}, 131 arm.ABLT: {Flags: gc.Cjmp}, 132 arm.ABGT: {Flags: gc.Cjmp}, 133 arm.ABLE: {Flags: gc.Cjmp}, 134 obj.ARET: {Flags: gc.Break}, 135 } 136 137 func proginfo(p *obj.Prog) { 138 info := &p.Info 139 *info = progtable[p.As] 140 if info.Flags == 0 { 141 gc.Fatalf("unknown instruction %v", p) 142 } 143 144 if p.From.Type == obj.TYPE_ADDR && p.From.Sym != nil && (info.Flags&gc.LeftRead != 0) { 145 info.Flags &^= gc.LeftRead 146 info.Flags |= gc.LeftAddr 147 } 148 149 if (info.Flags&gc.RegRead != 0) && p.Reg == 0 { 150 info.Flags &^= gc.RegRead 151 info.Flags |= gc.CanRegRead | gc.RightRead 152 } 153 154 if (p.Scond&arm.C_SCOND != arm.C_SCOND_NONE) && (info.Flags&gc.RightWrite != 0) { 155 info.Flags |= gc.RightRead 156 } 157 158 switch p.As { 159 case arm.ADIV, 160 arm.ADIVU, 161 arm.AMOD, 162 arm.AMODU: 163 info.Regset |= RtoB(arm.REG_R12) 164 } 165 }