github.com/rakyll/go@v0.0.0-20170216000551-64c02460d703/src/cmd/compile/internal/ssa/opGen.go (about) 1 // autogenerated: do not edit! 2 // generated from gen/*Ops.go 3 4 package ssa 5 6 import ( 7 "cmd/internal/obj" 8 "cmd/internal/obj/arm" 9 "cmd/internal/obj/arm64" 10 "cmd/internal/obj/mips" 11 "cmd/internal/obj/ppc64" 12 "cmd/internal/obj/s390x" 13 "cmd/internal/obj/x86" 14 ) 15 16 const ( 17 BlockInvalid BlockKind = iota 18 19 Block386EQ 20 Block386NE 21 Block386LT 22 Block386LE 23 Block386GT 24 Block386GE 25 Block386ULT 26 Block386ULE 27 Block386UGT 28 Block386UGE 29 Block386EQF 30 Block386NEF 31 Block386ORD 32 Block386NAN 33 34 BlockAMD64EQ 35 BlockAMD64NE 36 BlockAMD64LT 37 BlockAMD64LE 38 BlockAMD64GT 39 BlockAMD64GE 40 BlockAMD64ULT 41 BlockAMD64ULE 42 BlockAMD64UGT 43 BlockAMD64UGE 44 BlockAMD64EQF 45 BlockAMD64NEF 46 BlockAMD64ORD 47 BlockAMD64NAN 48 49 BlockARMEQ 50 BlockARMNE 51 BlockARMLT 52 BlockARMLE 53 BlockARMGT 54 BlockARMGE 55 BlockARMULT 56 BlockARMULE 57 BlockARMUGT 58 BlockARMUGE 59 60 BlockARM64EQ 61 BlockARM64NE 62 BlockARM64LT 63 BlockARM64LE 64 BlockARM64GT 65 BlockARM64GE 66 BlockARM64ULT 67 BlockARM64ULE 68 BlockARM64UGT 69 BlockARM64UGE 70 BlockARM64Z 71 BlockARM64NZ 72 BlockARM64ZW 73 BlockARM64NZW 74 75 BlockMIPSEQ 76 BlockMIPSNE 77 BlockMIPSLTZ 78 BlockMIPSLEZ 79 BlockMIPSGTZ 80 BlockMIPSGEZ 81 BlockMIPSFPT 82 BlockMIPSFPF 83 84 BlockMIPS64EQ 85 BlockMIPS64NE 86 BlockMIPS64LTZ 87 BlockMIPS64LEZ 88 BlockMIPS64GTZ 89 BlockMIPS64GEZ 90 BlockMIPS64FPT 91 BlockMIPS64FPF 92 93 BlockPPC64EQ 94 BlockPPC64NE 95 BlockPPC64LT 96 BlockPPC64LE 97 BlockPPC64GT 98 BlockPPC64GE 99 BlockPPC64FLT 100 BlockPPC64FLE 101 BlockPPC64FGT 102 BlockPPC64FGE 103 104 BlockS390XEQ 105 BlockS390XNE 106 BlockS390XLT 107 BlockS390XLE 108 BlockS390XGT 109 BlockS390XGE 110 BlockS390XGTF 111 BlockS390XGEF 112 113 BlockPlain 114 BlockIf 115 BlockDefer 116 BlockRet 117 BlockRetJmp 118 BlockExit 119 BlockFirst 120 ) 121 122 var blockString = [...]string{ 123 BlockInvalid: "BlockInvalid", 124 125 Block386EQ: "EQ", 126 Block386NE: "NE", 127 Block386LT: "LT", 128 Block386LE: "LE", 129 Block386GT: "GT", 130 Block386GE: "GE", 131 Block386ULT: "ULT", 132 Block386ULE: "ULE", 133 Block386UGT: "UGT", 134 Block386UGE: "UGE", 135 Block386EQF: "EQF", 136 Block386NEF: "NEF", 137 Block386ORD: "ORD", 138 Block386NAN: "NAN", 139 140 BlockAMD64EQ: "EQ", 141 BlockAMD64NE: "NE", 142 BlockAMD64LT: "LT", 143 BlockAMD64LE: "LE", 144 BlockAMD64GT: "GT", 145 BlockAMD64GE: "GE", 146 BlockAMD64ULT: "ULT", 147 BlockAMD64ULE: "ULE", 148 BlockAMD64UGT: "UGT", 149 BlockAMD64UGE: "UGE", 150 BlockAMD64EQF: "EQF", 151 BlockAMD64NEF: "NEF", 152 BlockAMD64ORD: "ORD", 153 BlockAMD64NAN: "NAN", 154 155 BlockARMEQ: "EQ", 156 BlockARMNE: "NE", 157 BlockARMLT: "LT", 158 BlockARMLE: "LE", 159 BlockARMGT: "GT", 160 BlockARMGE: "GE", 161 BlockARMULT: "ULT", 162 BlockARMULE: "ULE", 163 BlockARMUGT: "UGT", 164 BlockARMUGE: "UGE", 165 166 BlockARM64EQ: "EQ", 167 BlockARM64NE: "NE", 168 BlockARM64LT: "LT", 169 BlockARM64LE: "LE", 170 BlockARM64GT: "GT", 171 BlockARM64GE: "GE", 172 BlockARM64ULT: "ULT", 173 BlockARM64ULE: "ULE", 174 BlockARM64UGT: "UGT", 175 BlockARM64UGE: "UGE", 176 BlockARM64Z: "Z", 177 BlockARM64NZ: "NZ", 178 BlockARM64ZW: "ZW", 179 BlockARM64NZW: "NZW", 180 181 BlockMIPSEQ: "EQ", 182 BlockMIPSNE: "NE", 183 BlockMIPSLTZ: "LTZ", 184 BlockMIPSLEZ: "LEZ", 185 BlockMIPSGTZ: "GTZ", 186 BlockMIPSGEZ: "GEZ", 187 BlockMIPSFPT: "FPT", 188 BlockMIPSFPF: "FPF", 189 190 BlockMIPS64EQ: "EQ", 191 BlockMIPS64NE: "NE", 192 BlockMIPS64LTZ: "LTZ", 193 BlockMIPS64LEZ: "LEZ", 194 BlockMIPS64GTZ: "GTZ", 195 BlockMIPS64GEZ: "GEZ", 196 BlockMIPS64FPT: "FPT", 197 BlockMIPS64FPF: "FPF", 198 199 BlockPPC64EQ: "EQ", 200 BlockPPC64NE: "NE", 201 BlockPPC64LT: "LT", 202 BlockPPC64LE: "LE", 203 BlockPPC64GT: "GT", 204 BlockPPC64GE: "GE", 205 BlockPPC64FLT: "FLT", 206 BlockPPC64FLE: "FLE", 207 BlockPPC64FGT: "FGT", 208 BlockPPC64FGE: "FGE", 209 210 BlockS390XEQ: "EQ", 211 BlockS390XNE: "NE", 212 BlockS390XLT: "LT", 213 BlockS390XLE: "LE", 214 BlockS390XGT: "GT", 215 BlockS390XGE: "GE", 216 BlockS390XGTF: "GTF", 217 BlockS390XGEF: "GEF", 218 219 BlockPlain: "Plain", 220 BlockIf: "If", 221 BlockDefer: "Defer", 222 BlockRet: "Ret", 223 BlockRetJmp: "RetJmp", 224 BlockExit: "Exit", 225 BlockFirst: "First", 226 } 227 228 func (k BlockKind) String() string { return blockString[k] } 229 230 const ( 231 OpInvalid Op = iota 232 233 Op386ADDSS 234 Op386ADDSD 235 Op386SUBSS 236 Op386SUBSD 237 Op386MULSS 238 Op386MULSD 239 Op386DIVSS 240 Op386DIVSD 241 Op386MOVSSload 242 Op386MOVSDload 243 Op386MOVSSconst 244 Op386MOVSDconst 245 Op386MOVSSloadidx1 246 Op386MOVSSloadidx4 247 Op386MOVSDloadidx1 248 Op386MOVSDloadidx8 249 Op386MOVSSstore 250 Op386MOVSDstore 251 Op386MOVSSstoreidx1 252 Op386MOVSSstoreidx4 253 Op386MOVSDstoreidx1 254 Op386MOVSDstoreidx8 255 Op386ADDL 256 Op386ADDLconst 257 Op386ADDLcarry 258 Op386ADDLconstcarry 259 Op386ADCL 260 Op386ADCLconst 261 Op386SUBL 262 Op386SUBLconst 263 Op386SUBLcarry 264 Op386SUBLconstcarry 265 Op386SBBL 266 Op386SBBLconst 267 Op386MULL 268 Op386MULLconst 269 Op386HMULL 270 Op386HMULLU 271 Op386HMULW 272 Op386HMULB 273 Op386HMULWU 274 Op386HMULBU 275 Op386MULLQU 276 Op386DIVL 277 Op386DIVW 278 Op386DIVLU 279 Op386DIVWU 280 Op386MODL 281 Op386MODW 282 Op386MODLU 283 Op386MODWU 284 Op386ANDL 285 Op386ANDLconst 286 Op386ORL 287 Op386ORLconst 288 Op386XORL 289 Op386XORLconst 290 Op386CMPL 291 Op386CMPW 292 Op386CMPB 293 Op386CMPLconst 294 Op386CMPWconst 295 Op386CMPBconst 296 Op386UCOMISS 297 Op386UCOMISD 298 Op386TESTL 299 Op386TESTW 300 Op386TESTB 301 Op386TESTLconst 302 Op386TESTWconst 303 Op386TESTBconst 304 Op386SHLL 305 Op386SHLLconst 306 Op386SHRL 307 Op386SHRW 308 Op386SHRB 309 Op386SHRLconst 310 Op386SHRWconst 311 Op386SHRBconst 312 Op386SARL 313 Op386SARW 314 Op386SARB 315 Op386SARLconst 316 Op386SARWconst 317 Op386SARBconst 318 Op386ROLLconst 319 Op386ROLWconst 320 Op386ROLBconst 321 Op386NEGL 322 Op386NOTL 323 Op386BSFL 324 Op386BSFW 325 Op386BSRL 326 Op386BSRW 327 Op386BSWAPL 328 Op386SQRTSD 329 Op386SBBLcarrymask 330 Op386SETEQ 331 Op386SETNE 332 Op386SETL 333 Op386SETLE 334 Op386SETG 335 Op386SETGE 336 Op386SETB 337 Op386SETBE 338 Op386SETA 339 Op386SETAE 340 Op386SETEQF 341 Op386SETNEF 342 Op386SETORD 343 Op386SETNAN 344 Op386SETGF 345 Op386SETGEF 346 Op386MOVBLSX 347 Op386MOVBLZX 348 Op386MOVWLSX 349 Op386MOVWLZX 350 Op386MOVLconst 351 Op386CVTTSD2SL 352 Op386CVTTSS2SL 353 Op386CVTSL2SS 354 Op386CVTSL2SD 355 Op386CVTSD2SS 356 Op386CVTSS2SD 357 Op386PXOR 358 Op386LEAL 359 Op386LEAL1 360 Op386LEAL2 361 Op386LEAL4 362 Op386LEAL8 363 Op386MOVBload 364 Op386MOVBLSXload 365 Op386MOVWload 366 Op386MOVWLSXload 367 Op386MOVLload 368 Op386MOVBstore 369 Op386MOVWstore 370 Op386MOVLstore 371 Op386MOVBloadidx1 372 Op386MOVWloadidx1 373 Op386MOVWloadidx2 374 Op386MOVLloadidx1 375 Op386MOVLloadidx4 376 Op386MOVBstoreidx1 377 Op386MOVWstoreidx1 378 Op386MOVWstoreidx2 379 Op386MOVLstoreidx1 380 Op386MOVLstoreidx4 381 Op386MOVBstoreconst 382 Op386MOVWstoreconst 383 Op386MOVLstoreconst 384 Op386MOVBstoreconstidx1 385 Op386MOVWstoreconstidx1 386 Op386MOVWstoreconstidx2 387 Op386MOVLstoreconstidx1 388 Op386MOVLstoreconstidx4 389 Op386DUFFZERO 390 Op386REPSTOSL 391 Op386CALLstatic 392 Op386CALLclosure 393 Op386CALLdefer 394 Op386CALLgo 395 Op386CALLinter 396 Op386DUFFCOPY 397 Op386REPMOVSL 398 Op386InvertFlags 399 Op386LoweredGetG 400 Op386LoweredGetClosurePtr 401 Op386LoweredNilCheck 402 Op386MOVLconvert 403 Op386FlagEQ 404 Op386FlagLT_ULT 405 Op386FlagLT_UGT 406 Op386FlagGT_UGT 407 Op386FlagGT_ULT 408 Op386FCHS 409 Op386MOVSSconst1 410 Op386MOVSDconst1 411 Op386MOVSSconst2 412 Op386MOVSDconst2 413 414 OpAMD64ADDSS 415 OpAMD64ADDSD 416 OpAMD64SUBSS 417 OpAMD64SUBSD 418 OpAMD64MULSS 419 OpAMD64MULSD 420 OpAMD64DIVSS 421 OpAMD64DIVSD 422 OpAMD64MOVSSload 423 OpAMD64MOVSDload 424 OpAMD64MOVSSconst 425 OpAMD64MOVSDconst 426 OpAMD64MOVSSloadidx1 427 OpAMD64MOVSSloadidx4 428 OpAMD64MOVSDloadidx1 429 OpAMD64MOVSDloadidx8 430 OpAMD64MOVSSstore 431 OpAMD64MOVSDstore 432 OpAMD64MOVSSstoreidx1 433 OpAMD64MOVSSstoreidx4 434 OpAMD64MOVSDstoreidx1 435 OpAMD64MOVSDstoreidx8 436 OpAMD64ADDQ 437 OpAMD64ADDL 438 OpAMD64ADDQconst 439 OpAMD64ADDLconst 440 OpAMD64SUBQ 441 OpAMD64SUBL 442 OpAMD64SUBQconst 443 OpAMD64SUBLconst 444 OpAMD64MULQ 445 OpAMD64MULL 446 OpAMD64MULQconst 447 OpAMD64MULLconst 448 OpAMD64HMULQ 449 OpAMD64HMULL 450 OpAMD64HMULW 451 OpAMD64HMULB 452 OpAMD64HMULQU 453 OpAMD64HMULLU 454 OpAMD64HMULWU 455 OpAMD64HMULBU 456 OpAMD64AVGQU 457 OpAMD64DIVQ 458 OpAMD64DIVL 459 OpAMD64DIVW 460 OpAMD64DIVQU 461 OpAMD64DIVLU 462 OpAMD64DIVWU 463 OpAMD64MULQU2 464 OpAMD64DIVQU2 465 OpAMD64ANDQ 466 OpAMD64ANDL 467 OpAMD64ANDQconst 468 OpAMD64ANDLconst 469 OpAMD64ORQ 470 OpAMD64ORL 471 OpAMD64ORQconst 472 OpAMD64ORLconst 473 OpAMD64XORQ 474 OpAMD64XORL 475 OpAMD64XORQconst 476 OpAMD64XORLconst 477 OpAMD64CMPQ 478 OpAMD64CMPL 479 OpAMD64CMPW 480 OpAMD64CMPB 481 OpAMD64CMPQconst 482 OpAMD64CMPLconst 483 OpAMD64CMPWconst 484 OpAMD64CMPBconst 485 OpAMD64UCOMISS 486 OpAMD64UCOMISD 487 OpAMD64TESTQ 488 OpAMD64TESTL 489 OpAMD64TESTW 490 OpAMD64TESTB 491 OpAMD64TESTQconst 492 OpAMD64TESTLconst 493 OpAMD64TESTWconst 494 OpAMD64TESTBconst 495 OpAMD64SHLQ 496 OpAMD64SHLL 497 OpAMD64SHLQconst 498 OpAMD64SHLLconst 499 OpAMD64SHRQ 500 OpAMD64SHRL 501 OpAMD64SHRW 502 OpAMD64SHRB 503 OpAMD64SHRQconst 504 OpAMD64SHRLconst 505 OpAMD64SHRWconst 506 OpAMD64SHRBconst 507 OpAMD64SARQ 508 OpAMD64SARL 509 OpAMD64SARW 510 OpAMD64SARB 511 OpAMD64SARQconst 512 OpAMD64SARLconst 513 OpAMD64SARWconst 514 OpAMD64SARBconst 515 OpAMD64ROLQconst 516 OpAMD64ROLLconst 517 OpAMD64ROLWconst 518 OpAMD64ROLBconst 519 OpAMD64NEGQ 520 OpAMD64NEGL 521 OpAMD64NOTQ 522 OpAMD64NOTL 523 OpAMD64BSFQ 524 OpAMD64BSFL 525 OpAMD64CMOVQEQ 526 OpAMD64CMOVLEQ 527 OpAMD64BSWAPQ 528 OpAMD64BSWAPL 529 OpAMD64SQRTSD 530 OpAMD64SBBQcarrymask 531 OpAMD64SBBLcarrymask 532 OpAMD64SETEQ 533 OpAMD64SETNE 534 OpAMD64SETL 535 OpAMD64SETLE 536 OpAMD64SETG 537 OpAMD64SETGE 538 OpAMD64SETB 539 OpAMD64SETBE 540 OpAMD64SETA 541 OpAMD64SETAE 542 OpAMD64SETEQF 543 OpAMD64SETNEF 544 OpAMD64SETORD 545 OpAMD64SETNAN 546 OpAMD64SETGF 547 OpAMD64SETGEF 548 OpAMD64MOVBQSX 549 OpAMD64MOVBQZX 550 OpAMD64MOVWQSX 551 OpAMD64MOVWQZX 552 OpAMD64MOVLQSX 553 OpAMD64MOVLQZX 554 OpAMD64MOVLconst 555 OpAMD64MOVQconst 556 OpAMD64CVTTSD2SL 557 OpAMD64CVTTSD2SQ 558 OpAMD64CVTTSS2SL 559 OpAMD64CVTTSS2SQ 560 OpAMD64CVTSL2SS 561 OpAMD64CVTSL2SD 562 OpAMD64CVTSQ2SS 563 OpAMD64CVTSQ2SD 564 OpAMD64CVTSD2SS 565 OpAMD64CVTSS2SD 566 OpAMD64PXOR 567 OpAMD64LEAQ 568 OpAMD64LEAQ1 569 OpAMD64LEAQ2 570 OpAMD64LEAQ4 571 OpAMD64LEAQ8 572 OpAMD64LEAL 573 OpAMD64MOVBload 574 OpAMD64MOVBQSXload 575 OpAMD64MOVWload 576 OpAMD64MOVWQSXload 577 OpAMD64MOVLload 578 OpAMD64MOVLQSXload 579 OpAMD64MOVQload 580 OpAMD64MOVBstore 581 OpAMD64MOVWstore 582 OpAMD64MOVLstore 583 OpAMD64MOVQstore 584 OpAMD64MOVOload 585 OpAMD64MOVOstore 586 OpAMD64MOVBloadidx1 587 OpAMD64MOVWloadidx1 588 OpAMD64MOVWloadidx2 589 OpAMD64MOVLloadidx1 590 OpAMD64MOVLloadidx4 591 OpAMD64MOVQloadidx1 592 OpAMD64MOVQloadidx8 593 OpAMD64MOVBstoreidx1 594 OpAMD64MOVWstoreidx1 595 OpAMD64MOVWstoreidx2 596 OpAMD64MOVLstoreidx1 597 OpAMD64MOVLstoreidx4 598 OpAMD64MOVQstoreidx1 599 OpAMD64MOVQstoreidx8 600 OpAMD64MOVBstoreconst 601 OpAMD64MOVWstoreconst 602 OpAMD64MOVLstoreconst 603 OpAMD64MOVQstoreconst 604 OpAMD64MOVBstoreconstidx1 605 OpAMD64MOVWstoreconstidx1 606 OpAMD64MOVWstoreconstidx2 607 OpAMD64MOVLstoreconstidx1 608 OpAMD64MOVLstoreconstidx4 609 OpAMD64MOVQstoreconstidx1 610 OpAMD64MOVQstoreconstidx8 611 OpAMD64DUFFZERO 612 OpAMD64MOVOconst 613 OpAMD64REPSTOSQ 614 OpAMD64CALLstatic 615 OpAMD64CALLclosure 616 OpAMD64CALLdefer 617 OpAMD64CALLgo 618 OpAMD64CALLinter 619 OpAMD64DUFFCOPY 620 OpAMD64REPMOVSQ 621 OpAMD64InvertFlags 622 OpAMD64LoweredGetG 623 OpAMD64LoweredGetClosurePtr 624 OpAMD64LoweredNilCheck 625 OpAMD64MOVQconvert 626 OpAMD64MOVLconvert 627 OpAMD64FlagEQ 628 OpAMD64FlagLT_ULT 629 OpAMD64FlagLT_UGT 630 OpAMD64FlagGT_UGT 631 OpAMD64FlagGT_ULT 632 OpAMD64MOVLatomicload 633 OpAMD64MOVQatomicload 634 OpAMD64XCHGL 635 OpAMD64XCHGQ 636 OpAMD64XADDLlock 637 OpAMD64XADDQlock 638 OpAMD64AddTupleFirst32 639 OpAMD64AddTupleFirst64 640 OpAMD64CMPXCHGLlock 641 OpAMD64CMPXCHGQlock 642 OpAMD64ANDBlock 643 OpAMD64ORBlock 644 645 OpARMADD 646 OpARMADDconst 647 OpARMSUB 648 OpARMSUBconst 649 OpARMRSB 650 OpARMRSBconst 651 OpARMMUL 652 OpARMHMUL 653 OpARMHMULU 654 OpARMUDIVrtcall 655 OpARMADDS 656 OpARMADDSconst 657 OpARMADC 658 OpARMADCconst 659 OpARMSUBS 660 OpARMSUBSconst 661 OpARMRSBSconst 662 OpARMSBC 663 OpARMSBCconst 664 OpARMRSCconst 665 OpARMMULLU 666 OpARMMULA 667 OpARMADDF 668 OpARMADDD 669 OpARMSUBF 670 OpARMSUBD 671 OpARMMULF 672 OpARMMULD 673 OpARMDIVF 674 OpARMDIVD 675 OpARMAND 676 OpARMANDconst 677 OpARMOR 678 OpARMORconst 679 OpARMXOR 680 OpARMXORconst 681 OpARMBIC 682 OpARMBICconst 683 OpARMMVN 684 OpARMNEGF 685 OpARMNEGD 686 OpARMSQRTD 687 OpARMCLZ 688 OpARMSLL 689 OpARMSLLconst 690 OpARMSRL 691 OpARMSRLconst 692 OpARMSRA 693 OpARMSRAconst 694 OpARMSRRconst 695 OpARMADDshiftLL 696 OpARMADDshiftRL 697 OpARMADDshiftRA 698 OpARMSUBshiftLL 699 OpARMSUBshiftRL 700 OpARMSUBshiftRA 701 OpARMRSBshiftLL 702 OpARMRSBshiftRL 703 OpARMRSBshiftRA 704 OpARMANDshiftLL 705 OpARMANDshiftRL 706 OpARMANDshiftRA 707 OpARMORshiftLL 708 OpARMORshiftRL 709 OpARMORshiftRA 710 OpARMXORshiftLL 711 OpARMXORshiftRL 712 OpARMXORshiftRA 713 OpARMXORshiftRR 714 OpARMBICshiftLL 715 OpARMBICshiftRL 716 OpARMBICshiftRA 717 OpARMMVNshiftLL 718 OpARMMVNshiftRL 719 OpARMMVNshiftRA 720 OpARMADCshiftLL 721 OpARMADCshiftRL 722 OpARMADCshiftRA 723 OpARMSBCshiftLL 724 OpARMSBCshiftRL 725 OpARMSBCshiftRA 726 OpARMRSCshiftLL 727 OpARMRSCshiftRL 728 OpARMRSCshiftRA 729 OpARMADDSshiftLL 730 OpARMADDSshiftRL 731 OpARMADDSshiftRA 732 OpARMSUBSshiftLL 733 OpARMSUBSshiftRL 734 OpARMSUBSshiftRA 735 OpARMRSBSshiftLL 736 OpARMRSBSshiftRL 737 OpARMRSBSshiftRA 738 OpARMADDshiftLLreg 739 OpARMADDshiftRLreg 740 OpARMADDshiftRAreg 741 OpARMSUBshiftLLreg 742 OpARMSUBshiftRLreg 743 OpARMSUBshiftRAreg 744 OpARMRSBshiftLLreg 745 OpARMRSBshiftRLreg 746 OpARMRSBshiftRAreg 747 OpARMANDshiftLLreg 748 OpARMANDshiftRLreg 749 OpARMANDshiftRAreg 750 OpARMORshiftLLreg 751 OpARMORshiftRLreg 752 OpARMORshiftRAreg 753 OpARMXORshiftLLreg 754 OpARMXORshiftRLreg 755 OpARMXORshiftRAreg 756 OpARMBICshiftLLreg 757 OpARMBICshiftRLreg 758 OpARMBICshiftRAreg 759 OpARMMVNshiftLLreg 760 OpARMMVNshiftRLreg 761 OpARMMVNshiftRAreg 762 OpARMADCshiftLLreg 763 OpARMADCshiftRLreg 764 OpARMADCshiftRAreg 765 OpARMSBCshiftLLreg 766 OpARMSBCshiftRLreg 767 OpARMSBCshiftRAreg 768 OpARMRSCshiftLLreg 769 OpARMRSCshiftRLreg 770 OpARMRSCshiftRAreg 771 OpARMADDSshiftLLreg 772 OpARMADDSshiftRLreg 773 OpARMADDSshiftRAreg 774 OpARMSUBSshiftLLreg 775 OpARMSUBSshiftRLreg 776 OpARMSUBSshiftRAreg 777 OpARMRSBSshiftLLreg 778 OpARMRSBSshiftRLreg 779 OpARMRSBSshiftRAreg 780 OpARMCMP 781 OpARMCMPconst 782 OpARMCMN 783 OpARMCMNconst 784 OpARMTST 785 OpARMTSTconst 786 OpARMTEQ 787 OpARMTEQconst 788 OpARMCMPF 789 OpARMCMPD 790 OpARMCMPshiftLL 791 OpARMCMPshiftRL 792 OpARMCMPshiftRA 793 OpARMCMPshiftLLreg 794 OpARMCMPshiftRLreg 795 OpARMCMPshiftRAreg 796 OpARMCMPF0 797 OpARMCMPD0 798 OpARMMOVWconst 799 OpARMMOVFconst 800 OpARMMOVDconst 801 OpARMMOVWaddr 802 OpARMMOVBload 803 OpARMMOVBUload 804 OpARMMOVHload 805 OpARMMOVHUload 806 OpARMMOVWload 807 OpARMMOVFload 808 OpARMMOVDload 809 OpARMMOVBstore 810 OpARMMOVHstore 811 OpARMMOVWstore 812 OpARMMOVFstore 813 OpARMMOVDstore 814 OpARMMOVWloadidx 815 OpARMMOVWloadshiftLL 816 OpARMMOVWloadshiftRL 817 OpARMMOVWloadshiftRA 818 OpARMMOVWstoreidx 819 OpARMMOVWstoreshiftLL 820 OpARMMOVWstoreshiftRL 821 OpARMMOVWstoreshiftRA 822 OpARMMOVBreg 823 OpARMMOVBUreg 824 OpARMMOVHreg 825 OpARMMOVHUreg 826 OpARMMOVWreg 827 OpARMMOVWnop 828 OpARMMOVWF 829 OpARMMOVWD 830 OpARMMOVWUF 831 OpARMMOVWUD 832 OpARMMOVFW 833 OpARMMOVDW 834 OpARMMOVFWU 835 OpARMMOVDWU 836 OpARMMOVFD 837 OpARMMOVDF 838 OpARMCMOVWHSconst 839 OpARMCMOVWLSconst 840 OpARMSRAcond 841 OpARMCALLstatic 842 OpARMCALLclosure 843 OpARMCALLdefer 844 OpARMCALLgo 845 OpARMCALLinter 846 OpARMLoweredNilCheck 847 OpARMEqual 848 OpARMNotEqual 849 OpARMLessThan 850 OpARMLessEqual 851 OpARMGreaterThan 852 OpARMGreaterEqual 853 OpARMLessThanU 854 OpARMLessEqualU 855 OpARMGreaterThanU 856 OpARMGreaterEqualU 857 OpARMDUFFZERO 858 OpARMDUFFCOPY 859 OpARMLoweredZero 860 OpARMLoweredMove 861 OpARMLoweredGetClosurePtr 862 OpARMMOVWconvert 863 OpARMFlagEQ 864 OpARMFlagLT_ULT 865 OpARMFlagLT_UGT 866 OpARMFlagGT_UGT 867 OpARMFlagGT_ULT 868 OpARMInvertFlags 869 870 OpARM64ADD 871 OpARM64ADDconst 872 OpARM64SUB 873 OpARM64SUBconst 874 OpARM64MUL 875 OpARM64MULW 876 OpARM64MULH 877 OpARM64UMULH 878 OpARM64MULL 879 OpARM64UMULL 880 OpARM64DIV 881 OpARM64UDIV 882 OpARM64DIVW 883 OpARM64UDIVW 884 OpARM64MOD 885 OpARM64UMOD 886 OpARM64MODW 887 OpARM64UMODW 888 OpARM64FADDS 889 OpARM64FADDD 890 OpARM64FSUBS 891 OpARM64FSUBD 892 OpARM64FMULS 893 OpARM64FMULD 894 OpARM64FDIVS 895 OpARM64FDIVD 896 OpARM64AND 897 OpARM64ANDconst 898 OpARM64OR 899 OpARM64ORconst 900 OpARM64XOR 901 OpARM64XORconst 902 OpARM64BIC 903 OpARM64BICconst 904 OpARM64MVN 905 OpARM64NEG 906 OpARM64FNEGS 907 OpARM64FNEGD 908 OpARM64FSQRTD 909 OpARM64REV 910 OpARM64REVW 911 OpARM64REV16W 912 OpARM64RBIT 913 OpARM64RBITW 914 OpARM64CLZ 915 OpARM64CLZW 916 OpARM64SLL 917 OpARM64SLLconst 918 OpARM64SRL 919 OpARM64SRLconst 920 OpARM64SRA 921 OpARM64SRAconst 922 OpARM64RORconst 923 OpARM64RORWconst 924 OpARM64CMP 925 OpARM64CMPconst 926 OpARM64CMPW 927 OpARM64CMPWconst 928 OpARM64CMN 929 OpARM64CMNconst 930 OpARM64CMNW 931 OpARM64CMNWconst 932 OpARM64FCMPS 933 OpARM64FCMPD 934 OpARM64ADDshiftLL 935 OpARM64ADDshiftRL 936 OpARM64ADDshiftRA 937 OpARM64SUBshiftLL 938 OpARM64SUBshiftRL 939 OpARM64SUBshiftRA 940 OpARM64ANDshiftLL 941 OpARM64ANDshiftRL 942 OpARM64ANDshiftRA 943 OpARM64ORshiftLL 944 OpARM64ORshiftRL 945 OpARM64ORshiftRA 946 OpARM64XORshiftLL 947 OpARM64XORshiftRL 948 OpARM64XORshiftRA 949 OpARM64BICshiftLL 950 OpARM64BICshiftRL 951 OpARM64BICshiftRA 952 OpARM64CMPshiftLL 953 OpARM64CMPshiftRL 954 OpARM64CMPshiftRA 955 OpARM64MOVDconst 956 OpARM64FMOVSconst 957 OpARM64FMOVDconst 958 OpARM64MOVDaddr 959 OpARM64MOVBload 960 OpARM64MOVBUload 961 OpARM64MOVHload 962 OpARM64MOVHUload 963 OpARM64MOVWload 964 OpARM64MOVWUload 965 OpARM64MOVDload 966 OpARM64FMOVSload 967 OpARM64FMOVDload 968 OpARM64MOVBstore 969 OpARM64MOVHstore 970 OpARM64MOVWstore 971 OpARM64MOVDstore 972 OpARM64FMOVSstore 973 OpARM64FMOVDstore 974 OpARM64MOVBstorezero 975 OpARM64MOVHstorezero 976 OpARM64MOVWstorezero 977 OpARM64MOVDstorezero 978 OpARM64MOVBreg 979 OpARM64MOVBUreg 980 OpARM64MOVHreg 981 OpARM64MOVHUreg 982 OpARM64MOVWreg 983 OpARM64MOVWUreg 984 OpARM64MOVDreg 985 OpARM64MOVDnop 986 OpARM64SCVTFWS 987 OpARM64SCVTFWD 988 OpARM64UCVTFWS 989 OpARM64UCVTFWD 990 OpARM64SCVTFS 991 OpARM64SCVTFD 992 OpARM64UCVTFS 993 OpARM64UCVTFD 994 OpARM64FCVTZSSW 995 OpARM64FCVTZSDW 996 OpARM64FCVTZUSW 997 OpARM64FCVTZUDW 998 OpARM64FCVTZSS 999 OpARM64FCVTZSD 1000 OpARM64FCVTZUS 1001 OpARM64FCVTZUD 1002 OpARM64FCVTSD 1003 OpARM64FCVTDS 1004 OpARM64CSELULT 1005 OpARM64CSELULT0 1006 OpARM64CALLstatic 1007 OpARM64CALLclosure 1008 OpARM64CALLdefer 1009 OpARM64CALLgo 1010 OpARM64CALLinter 1011 OpARM64LoweredNilCheck 1012 OpARM64Equal 1013 OpARM64NotEqual 1014 OpARM64LessThan 1015 OpARM64LessEqual 1016 OpARM64GreaterThan 1017 OpARM64GreaterEqual 1018 OpARM64LessThanU 1019 OpARM64LessEqualU 1020 OpARM64GreaterThanU 1021 OpARM64GreaterEqualU 1022 OpARM64DUFFZERO 1023 OpARM64LoweredZero 1024 OpARM64DUFFCOPY 1025 OpARM64LoweredMove 1026 OpARM64LoweredGetClosurePtr 1027 OpARM64MOVDconvert 1028 OpARM64FlagEQ 1029 OpARM64FlagLT_ULT 1030 OpARM64FlagLT_UGT 1031 OpARM64FlagGT_UGT 1032 OpARM64FlagGT_ULT 1033 OpARM64InvertFlags 1034 OpARM64LDAR 1035 OpARM64LDARW 1036 OpARM64STLR 1037 OpARM64STLRW 1038 OpARM64LoweredAtomicExchange64 1039 OpARM64LoweredAtomicExchange32 1040 OpARM64LoweredAtomicAdd64 1041 OpARM64LoweredAtomicAdd32 1042 OpARM64LoweredAtomicCas64 1043 OpARM64LoweredAtomicCas32 1044 OpARM64LoweredAtomicAnd8 1045 OpARM64LoweredAtomicOr8 1046 1047 OpMIPSADD 1048 OpMIPSADDconst 1049 OpMIPSSUB 1050 OpMIPSSUBconst 1051 OpMIPSMUL 1052 OpMIPSMULT 1053 OpMIPSMULTU 1054 OpMIPSDIV 1055 OpMIPSDIVU 1056 OpMIPSADDF 1057 OpMIPSADDD 1058 OpMIPSSUBF 1059 OpMIPSSUBD 1060 OpMIPSMULF 1061 OpMIPSMULD 1062 OpMIPSDIVF 1063 OpMIPSDIVD 1064 OpMIPSAND 1065 OpMIPSANDconst 1066 OpMIPSOR 1067 OpMIPSORconst 1068 OpMIPSXOR 1069 OpMIPSXORconst 1070 OpMIPSNOR 1071 OpMIPSNORconst 1072 OpMIPSNEG 1073 OpMIPSNEGF 1074 OpMIPSNEGD 1075 OpMIPSSQRTD 1076 OpMIPSSLL 1077 OpMIPSSLLconst 1078 OpMIPSSRL 1079 OpMIPSSRLconst 1080 OpMIPSSRA 1081 OpMIPSSRAconst 1082 OpMIPSCLZ 1083 OpMIPSSGT 1084 OpMIPSSGTconst 1085 OpMIPSSGTzero 1086 OpMIPSSGTU 1087 OpMIPSSGTUconst 1088 OpMIPSSGTUzero 1089 OpMIPSCMPEQF 1090 OpMIPSCMPEQD 1091 OpMIPSCMPGEF 1092 OpMIPSCMPGED 1093 OpMIPSCMPGTF 1094 OpMIPSCMPGTD 1095 OpMIPSMOVWconst 1096 OpMIPSMOVFconst 1097 OpMIPSMOVDconst 1098 OpMIPSMOVWaddr 1099 OpMIPSMOVBload 1100 OpMIPSMOVBUload 1101 OpMIPSMOVHload 1102 OpMIPSMOVHUload 1103 OpMIPSMOVWload 1104 OpMIPSMOVFload 1105 OpMIPSMOVDload 1106 OpMIPSMOVBstore 1107 OpMIPSMOVHstore 1108 OpMIPSMOVWstore 1109 OpMIPSMOVFstore 1110 OpMIPSMOVDstore 1111 OpMIPSMOVBstorezero 1112 OpMIPSMOVHstorezero 1113 OpMIPSMOVWstorezero 1114 OpMIPSMOVBreg 1115 OpMIPSMOVBUreg 1116 OpMIPSMOVHreg 1117 OpMIPSMOVHUreg 1118 OpMIPSMOVWreg 1119 OpMIPSMOVWnop 1120 OpMIPSCMOVZ 1121 OpMIPSCMOVZzero 1122 OpMIPSMOVWF 1123 OpMIPSMOVWD 1124 OpMIPSTRUNCFW 1125 OpMIPSTRUNCDW 1126 OpMIPSMOVFD 1127 OpMIPSMOVDF 1128 OpMIPSCALLstatic 1129 OpMIPSCALLclosure 1130 OpMIPSCALLdefer 1131 OpMIPSCALLgo 1132 OpMIPSCALLinter 1133 OpMIPSLoweredAtomicLoad 1134 OpMIPSLoweredAtomicStore 1135 OpMIPSLoweredAtomicStorezero 1136 OpMIPSLoweredAtomicExchange 1137 OpMIPSLoweredAtomicAdd 1138 OpMIPSLoweredAtomicAddconst 1139 OpMIPSLoweredAtomicCas 1140 OpMIPSLoweredAtomicAnd 1141 OpMIPSLoweredAtomicOr 1142 OpMIPSLoweredZero 1143 OpMIPSLoweredMove 1144 OpMIPSLoweredNilCheck 1145 OpMIPSFPFlagTrue 1146 OpMIPSFPFlagFalse 1147 OpMIPSLoweredGetClosurePtr 1148 OpMIPSMOVWconvert 1149 1150 OpMIPS64ADDV 1151 OpMIPS64ADDVconst 1152 OpMIPS64SUBV 1153 OpMIPS64SUBVconst 1154 OpMIPS64MULV 1155 OpMIPS64MULVU 1156 OpMIPS64DIVV 1157 OpMIPS64DIVVU 1158 OpMIPS64ADDF 1159 OpMIPS64ADDD 1160 OpMIPS64SUBF 1161 OpMIPS64SUBD 1162 OpMIPS64MULF 1163 OpMIPS64MULD 1164 OpMIPS64DIVF 1165 OpMIPS64DIVD 1166 OpMIPS64AND 1167 OpMIPS64ANDconst 1168 OpMIPS64OR 1169 OpMIPS64ORconst 1170 OpMIPS64XOR 1171 OpMIPS64XORconst 1172 OpMIPS64NOR 1173 OpMIPS64NORconst 1174 OpMIPS64NEGV 1175 OpMIPS64NEGF 1176 OpMIPS64NEGD 1177 OpMIPS64SLLV 1178 OpMIPS64SLLVconst 1179 OpMIPS64SRLV 1180 OpMIPS64SRLVconst 1181 OpMIPS64SRAV 1182 OpMIPS64SRAVconst 1183 OpMIPS64SGT 1184 OpMIPS64SGTconst 1185 OpMIPS64SGTU 1186 OpMIPS64SGTUconst 1187 OpMIPS64CMPEQF 1188 OpMIPS64CMPEQD 1189 OpMIPS64CMPGEF 1190 OpMIPS64CMPGED 1191 OpMIPS64CMPGTF 1192 OpMIPS64CMPGTD 1193 OpMIPS64MOVVconst 1194 OpMIPS64MOVFconst 1195 OpMIPS64MOVDconst 1196 OpMIPS64MOVVaddr 1197 OpMIPS64MOVBload 1198 OpMIPS64MOVBUload 1199 OpMIPS64MOVHload 1200 OpMIPS64MOVHUload 1201 OpMIPS64MOVWload 1202 OpMIPS64MOVWUload 1203 OpMIPS64MOVVload 1204 OpMIPS64MOVFload 1205 OpMIPS64MOVDload 1206 OpMIPS64MOVBstore 1207 OpMIPS64MOVHstore 1208 OpMIPS64MOVWstore 1209 OpMIPS64MOVVstore 1210 OpMIPS64MOVFstore 1211 OpMIPS64MOVDstore 1212 OpMIPS64MOVBstorezero 1213 OpMIPS64MOVHstorezero 1214 OpMIPS64MOVWstorezero 1215 OpMIPS64MOVVstorezero 1216 OpMIPS64MOVBreg 1217 OpMIPS64MOVBUreg 1218 OpMIPS64MOVHreg 1219 OpMIPS64MOVHUreg 1220 OpMIPS64MOVWreg 1221 OpMIPS64MOVWUreg 1222 OpMIPS64MOVVreg 1223 OpMIPS64MOVVnop 1224 OpMIPS64MOVWF 1225 OpMIPS64MOVWD 1226 OpMIPS64MOVVF 1227 OpMIPS64MOVVD 1228 OpMIPS64TRUNCFW 1229 OpMIPS64TRUNCDW 1230 OpMIPS64TRUNCFV 1231 OpMIPS64TRUNCDV 1232 OpMIPS64MOVFD 1233 OpMIPS64MOVDF 1234 OpMIPS64CALLstatic 1235 OpMIPS64CALLclosure 1236 OpMIPS64CALLdefer 1237 OpMIPS64CALLgo 1238 OpMIPS64CALLinter 1239 OpMIPS64DUFFZERO 1240 OpMIPS64LoweredZero 1241 OpMIPS64LoweredMove 1242 OpMIPS64LoweredNilCheck 1243 OpMIPS64FPFlagTrue 1244 OpMIPS64FPFlagFalse 1245 OpMIPS64LoweredGetClosurePtr 1246 OpMIPS64MOVVconvert 1247 1248 OpPPC64ADD 1249 OpPPC64ADDconst 1250 OpPPC64FADD 1251 OpPPC64FADDS 1252 OpPPC64SUB 1253 OpPPC64FSUB 1254 OpPPC64FSUBS 1255 OpPPC64MULLD 1256 OpPPC64MULLW 1257 OpPPC64MULHD 1258 OpPPC64MULHW 1259 OpPPC64MULHDU 1260 OpPPC64MULHWU 1261 OpPPC64FMUL 1262 OpPPC64FMULS 1263 OpPPC64SRAD 1264 OpPPC64SRAW 1265 OpPPC64SRD 1266 OpPPC64SRW 1267 OpPPC64SLD 1268 OpPPC64SLW 1269 OpPPC64ADDconstForCarry 1270 OpPPC64MaskIfNotCarry 1271 OpPPC64SRADconst 1272 OpPPC64SRAWconst 1273 OpPPC64SRDconst 1274 OpPPC64SRWconst 1275 OpPPC64SLDconst 1276 OpPPC64SLWconst 1277 OpPPC64FDIV 1278 OpPPC64FDIVS 1279 OpPPC64DIVD 1280 OpPPC64DIVW 1281 OpPPC64DIVDU 1282 OpPPC64DIVWU 1283 OpPPC64FCTIDZ 1284 OpPPC64FCTIWZ 1285 OpPPC64FCFID 1286 OpPPC64FRSP 1287 OpPPC64Xf2i64 1288 OpPPC64Xi2f64 1289 OpPPC64AND 1290 OpPPC64ANDN 1291 OpPPC64OR 1292 OpPPC64ORN 1293 OpPPC64NOR 1294 OpPPC64XOR 1295 OpPPC64EQV 1296 OpPPC64NEG 1297 OpPPC64FNEG 1298 OpPPC64FSQRT 1299 OpPPC64FSQRTS 1300 OpPPC64ORconst 1301 OpPPC64XORconst 1302 OpPPC64ANDconst 1303 OpPPC64ANDCCconst 1304 OpPPC64MOVBreg 1305 OpPPC64MOVBZreg 1306 OpPPC64MOVHreg 1307 OpPPC64MOVHZreg 1308 OpPPC64MOVWreg 1309 OpPPC64MOVWZreg 1310 OpPPC64MOVBZload 1311 OpPPC64MOVHload 1312 OpPPC64MOVHZload 1313 OpPPC64MOVWload 1314 OpPPC64MOVWZload 1315 OpPPC64MOVDload 1316 OpPPC64FMOVDload 1317 OpPPC64FMOVSload 1318 OpPPC64MOVBstore 1319 OpPPC64MOVHstore 1320 OpPPC64MOVWstore 1321 OpPPC64MOVDstore 1322 OpPPC64FMOVDstore 1323 OpPPC64FMOVSstore 1324 OpPPC64MOVBstorezero 1325 OpPPC64MOVHstorezero 1326 OpPPC64MOVWstorezero 1327 OpPPC64MOVDstorezero 1328 OpPPC64MOVDaddr 1329 OpPPC64MOVDconst 1330 OpPPC64FMOVDconst 1331 OpPPC64FMOVSconst 1332 OpPPC64FCMPU 1333 OpPPC64CMP 1334 OpPPC64CMPU 1335 OpPPC64CMPW 1336 OpPPC64CMPWU 1337 OpPPC64CMPconst 1338 OpPPC64CMPUconst 1339 OpPPC64CMPWconst 1340 OpPPC64CMPWUconst 1341 OpPPC64Equal 1342 OpPPC64NotEqual 1343 OpPPC64LessThan 1344 OpPPC64FLessThan 1345 OpPPC64LessEqual 1346 OpPPC64FLessEqual 1347 OpPPC64GreaterThan 1348 OpPPC64FGreaterThan 1349 OpPPC64GreaterEqual 1350 OpPPC64FGreaterEqual 1351 OpPPC64LoweredGetClosurePtr 1352 OpPPC64LoweredNilCheck 1353 OpPPC64MOVDconvert 1354 OpPPC64CALLstatic 1355 OpPPC64CALLclosure 1356 OpPPC64CALLdefer 1357 OpPPC64CALLgo 1358 OpPPC64CALLinter 1359 OpPPC64LoweredZero 1360 OpPPC64LoweredMove 1361 OpPPC64InvertFlags 1362 OpPPC64FlagEQ 1363 OpPPC64FlagLT 1364 OpPPC64FlagGT 1365 1366 OpS390XFADDS 1367 OpS390XFADD 1368 OpS390XFSUBS 1369 OpS390XFSUB 1370 OpS390XFMULS 1371 OpS390XFMUL 1372 OpS390XFDIVS 1373 OpS390XFDIV 1374 OpS390XFNEGS 1375 OpS390XFNEG 1376 OpS390XFMOVSload 1377 OpS390XFMOVDload 1378 OpS390XFMOVSconst 1379 OpS390XFMOVDconst 1380 OpS390XFMOVSloadidx 1381 OpS390XFMOVDloadidx 1382 OpS390XFMOVSstore 1383 OpS390XFMOVDstore 1384 OpS390XFMOVSstoreidx 1385 OpS390XFMOVDstoreidx 1386 OpS390XADD 1387 OpS390XADDW 1388 OpS390XADDconst 1389 OpS390XADDWconst 1390 OpS390XADDload 1391 OpS390XADDWload 1392 OpS390XSUB 1393 OpS390XSUBW 1394 OpS390XSUBconst 1395 OpS390XSUBWconst 1396 OpS390XSUBload 1397 OpS390XSUBWload 1398 OpS390XMULLD 1399 OpS390XMULLW 1400 OpS390XMULLDconst 1401 OpS390XMULLWconst 1402 OpS390XMULLDload 1403 OpS390XMULLWload 1404 OpS390XMULHD 1405 OpS390XMULHDU 1406 OpS390XDIVD 1407 OpS390XDIVW 1408 OpS390XDIVDU 1409 OpS390XDIVWU 1410 OpS390XMODD 1411 OpS390XMODW 1412 OpS390XMODDU 1413 OpS390XMODWU 1414 OpS390XAND 1415 OpS390XANDW 1416 OpS390XANDconst 1417 OpS390XANDWconst 1418 OpS390XANDload 1419 OpS390XANDWload 1420 OpS390XOR 1421 OpS390XORW 1422 OpS390XORconst 1423 OpS390XORWconst 1424 OpS390XORload 1425 OpS390XORWload 1426 OpS390XXOR 1427 OpS390XXORW 1428 OpS390XXORconst 1429 OpS390XXORWconst 1430 OpS390XXORload 1431 OpS390XXORWload 1432 OpS390XCMP 1433 OpS390XCMPW 1434 OpS390XCMPU 1435 OpS390XCMPWU 1436 OpS390XCMPconst 1437 OpS390XCMPWconst 1438 OpS390XCMPUconst 1439 OpS390XCMPWUconst 1440 OpS390XFCMPS 1441 OpS390XFCMP 1442 OpS390XSLD 1443 OpS390XSLW 1444 OpS390XSLDconst 1445 OpS390XSLWconst 1446 OpS390XSRD 1447 OpS390XSRW 1448 OpS390XSRDconst 1449 OpS390XSRWconst 1450 OpS390XSRAD 1451 OpS390XSRAW 1452 OpS390XSRADconst 1453 OpS390XSRAWconst 1454 OpS390XRLLGconst 1455 OpS390XRLLconst 1456 OpS390XNEG 1457 OpS390XNEGW 1458 OpS390XNOT 1459 OpS390XNOTW 1460 OpS390XFSQRT 1461 OpS390XSUBEcarrymask 1462 OpS390XSUBEWcarrymask 1463 OpS390XMOVDEQ 1464 OpS390XMOVDNE 1465 OpS390XMOVDLT 1466 OpS390XMOVDLE 1467 OpS390XMOVDGT 1468 OpS390XMOVDGE 1469 OpS390XMOVDGTnoinv 1470 OpS390XMOVDGEnoinv 1471 OpS390XMOVBreg 1472 OpS390XMOVBZreg 1473 OpS390XMOVHreg 1474 OpS390XMOVHZreg 1475 OpS390XMOVWreg 1476 OpS390XMOVWZreg 1477 OpS390XMOVDreg 1478 OpS390XMOVDnop 1479 OpS390XMOVDconst 1480 OpS390XCFDBRA 1481 OpS390XCGDBRA 1482 OpS390XCFEBRA 1483 OpS390XCGEBRA 1484 OpS390XCEFBRA 1485 OpS390XCDFBRA 1486 OpS390XCEGBRA 1487 OpS390XCDGBRA 1488 OpS390XLEDBR 1489 OpS390XLDEBR 1490 OpS390XMOVDaddr 1491 OpS390XMOVDaddridx 1492 OpS390XMOVBZload 1493 OpS390XMOVBload 1494 OpS390XMOVHZload 1495 OpS390XMOVHload 1496 OpS390XMOVWZload 1497 OpS390XMOVWload 1498 OpS390XMOVDload 1499 OpS390XMOVWBR 1500 OpS390XMOVDBR 1501 OpS390XMOVHBRload 1502 OpS390XMOVWBRload 1503 OpS390XMOVDBRload 1504 OpS390XMOVBstore 1505 OpS390XMOVHstore 1506 OpS390XMOVWstore 1507 OpS390XMOVDstore 1508 OpS390XMOVHBRstore 1509 OpS390XMOVWBRstore 1510 OpS390XMOVDBRstore 1511 OpS390XMVC 1512 OpS390XMOVBZloadidx 1513 OpS390XMOVHZloadidx 1514 OpS390XMOVWZloadidx 1515 OpS390XMOVDloadidx 1516 OpS390XMOVHBRloadidx 1517 OpS390XMOVWBRloadidx 1518 OpS390XMOVDBRloadidx 1519 OpS390XMOVBstoreidx 1520 OpS390XMOVHstoreidx 1521 OpS390XMOVWstoreidx 1522 OpS390XMOVDstoreidx 1523 OpS390XMOVHBRstoreidx 1524 OpS390XMOVWBRstoreidx 1525 OpS390XMOVDBRstoreidx 1526 OpS390XMOVBstoreconst 1527 OpS390XMOVHstoreconst 1528 OpS390XMOVWstoreconst 1529 OpS390XMOVDstoreconst 1530 OpS390XCLEAR 1531 OpS390XCALLstatic 1532 OpS390XCALLclosure 1533 OpS390XCALLdefer 1534 OpS390XCALLgo 1535 OpS390XCALLinter 1536 OpS390XInvertFlags 1537 OpS390XLoweredGetG 1538 OpS390XLoweredGetClosurePtr 1539 OpS390XLoweredNilCheck 1540 OpS390XMOVDconvert 1541 OpS390XFlagEQ 1542 OpS390XFlagLT 1543 OpS390XFlagGT 1544 OpS390XMOVWZatomicload 1545 OpS390XMOVDatomicload 1546 OpS390XMOVWatomicstore 1547 OpS390XMOVDatomicstore 1548 OpS390XLAA 1549 OpS390XLAAG 1550 OpS390XAddTupleFirst32 1551 OpS390XAddTupleFirst64 1552 OpS390XLoweredAtomicCas32 1553 OpS390XLoweredAtomicCas64 1554 OpS390XLoweredAtomicExchange32 1555 OpS390XLoweredAtomicExchange64 1556 OpS390XFLOGR 1557 OpS390XSTMG2 1558 OpS390XSTMG3 1559 OpS390XSTMG4 1560 OpS390XSTM2 1561 OpS390XSTM3 1562 OpS390XSTM4 1563 OpS390XLoweredMove 1564 OpS390XLoweredZero 1565 1566 OpAdd8 1567 OpAdd16 1568 OpAdd32 1569 OpAdd64 1570 OpAddPtr 1571 OpAdd32F 1572 OpAdd64F 1573 OpSub8 1574 OpSub16 1575 OpSub32 1576 OpSub64 1577 OpSubPtr 1578 OpSub32F 1579 OpSub64F 1580 OpMul8 1581 OpMul16 1582 OpMul32 1583 OpMul64 1584 OpMul32F 1585 OpMul64F 1586 OpDiv32F 1587 OpDiv64F 1588 OpHmul8 1589 OpHmul8u 1590 OpHmul16 1591 OpHmul16u 1592 OpHmul32 1593 OpHmul32u 1594 OpHmul64 1595 OpHmul64u 1596 OpMul32uhilo 1597 OpMul64uhilo 1598 OpAvg64u 1599 OpDiv8 1600 OpDiv8u 1601 OpDiv16 1602 OpDiv16u 1603 OpDiv32 1604 OpDiv32u 1605 OpDiv64 1606 OpDiv64u 1607 OpDiv128u 1608 OpMod8 1609 OpMod8u 1610 OpMod16 1611 OpMod16u 1612 OpMod32 1613 OpMod32u 1614 OpMod64 1615 OpMod64u 1616 OpAnd8 1617 OpAnd16 1618 OpAnd32 1619 OpAnd64 1620 OpOr8 1621 OpOr16 1622 OpOr32 1623 OpOr64 1624 OpXor8 1625 OpXor16 1626 OpXor32 1627 OpXor64 1628 OpLsh8x8 1629 OpLsh8x16 1630 OpLsh8x32 1631 OpLsh8x64 1632 OpLsh16x8 1633 OpLsh16x16 1634 OpLsh16x32 1635 OpLsh16x64 1636 OpLsh32x8 1637 OpLsh32x16 1638 OpLsh32x32 1639 OpLsh32x64 1640 OpLsh64x8 1641 OpLsh64x16 1642 OpLsh64x32 1643 OpLsh64x64 1644 OpRsh8x8 1645 OpRsh8x16 1646 OpRsh8x32 1647 OpRsh8x64 1648 OpRsh16x8 1649 OpRsh16x16 1650 OpRsh16x32 1651 OpRsh16x64 1652 OpRsh32x8 1653 OpRsh32x16 1654 OpRsh32x32 1655 OpRsh32x64 1656 OpRsh64x8 1657 OpRsh64x16 1658 OpRsh64x32 1659 OpRsh64x64 1660 OpRsh8Ux8 1661 OpRsh8Ux16 1662 OpRsh8Ux32 1663 OpRsh8Ux64 1664 OpRsh16Ux8 1665 OpRsh16Ux16 1666 OpRsh16Ux32 1667 OpRsh16Ux64 1668 OpRsh32Ux8 1669 OpRsh32Ux16 1670 OpRsh32Ux32 1671 OpRsh32Ux64 1672 OpRsh64Ux8 1673 OpRsh64Ux16 1674 OpRsh64Ux32 1675 OpRsh64Ux64 1676 OpEq8 1677 OpEq16 1678 OpEq32 1679 OpEq64 1680 OpEqPtr 1681 OpEqInter 1682 OpEqSlice 1683 OpEq32F 1684 OpEq64F 1685 OpNeq8 1686 OpNeq16 1687 OpNeq32 1688 OpNeq64 1689 OpNeqPtr 1690 OpNeqInter 1691 OpNeqSlice 1692 OpNeq32F 1693 OpNeq64F 1694 OpLess8 1695 OpLess8U 1696 OpLess16 1697 OpLess16U 1698 OpLess32 1699 OpLess32U 1700 OpLess64 1701 OpLess64U 1702 OpLess32F 1703 OpLess64F 1704 OpLeq8 1705 OpLeq8U 1706 OpLeq16 1707 OpLeq16U 1708 OpLeq32 1709 OpLeq32U 1710 OpLeq64 1711 OpLeq64U 1712 OpLeq32F 1713 OpLeq64F 1714 OpGreater8 1715 OpGreater8U 1716 OpGreater16 1717 OpGreater16U 1718 OpGreater32 1719 OpGreater32U 1720 OpGreater64 1721 OpGreater64U 1722 OpGreater32F 1723 OpGreater64F 1724 OpGeq8 1725 OpGeq8U 1726 OpGeq16 1727 OpGeq16U 1728 OpGeq32 1729 OpGeq32U 1730 OpGeq64 1731 OpGeq64U 1732 OpGeq32F 1733 OpGeq64F 1734 OpAndB 1735 OpOrB 1736 OpEqB 1737 OpNeqB 1738 OpNot 1739 OpNeg8 1740 OpNeg16 1741 OpNeg32 1742 OpNeg64 1743 OpNeg32F 1744 OpNeg64F 1745 OpCom8 1746 OpCom16 1747 OpCom32 1748 OpCom64 1749 OpCtz32 1750 OpCtz64 1751 OpBswap32 1752 OpBswap64 1753 OpSqrt 1754 OpPhi 1755 OpCopy 1756 OpConvert 1757 OpConstBool 1758 OpConstString 1759 OpConstNil 1760 OpConst8 1761 OpConst16 1762 OpConst32 1763 OpConst64 1764 OpConst32F 1765 OpConst64F 1766 OpConstInterface 1767 OpConstSlice 1768 OpInitMem 1769 OpArg 1770 OpAddr 1771 OpSP 1772 OpSB 1773 OpFunc 1774 OpLoad 1775 OpStore 1776 OpMove 1777 OpZero 1778 OpStoreWB 1779 OpMoveWB 1780 OpMoveWBVolatile 1781 OpZeroWB 1782 OpClosureCall 1783 OpStaticCall 1784 OpDeferCall 1785 OpGoCall 1786 OpInterCall 1787 OpSignExt8to16 1788 OpSignExt8to32 1789 OpSignExt8to64 1790 OpSignExt16to32 1791 OpSignExt16to64 1792 OpSignExt32to64 1793 OpZeroExt8to16 1794 OpZeroExt8to32 1795 OpZeroExt8to64 1796 OpZeroExt16to32 1797 OpZeroExt16to64 1798 OpZeroExt32to64 1799 OpTrunc16to8 1800 OpTrunc32to8 1801 OpTrunc32to16 1802 OpTrunc64to8 1803 OpTrunc64to16 1804 OpTrunc64to32 1805 OpCvt32to32F 1806 OpCvt32to64F 1807 OpCvt64to32F 1808 OpCvt64to64F 1809 OpCvt32Fto32 1810 OpCvt32Fto64 1811 OpCvt64Fto32 1812 OpCvt64Fto64 1813 OpCvt32Fto64F 1814 OpCvt64Fto32F 1815 OpIsNonNil 1816 OpIsInBounds 1817 OpIsSliceInBounds 1818 OpNilCheck 1819 OpGetG 1820 OpGetClosurePtr 1821 OpPtrIndex 1822 OpOffPtr 1823 OpSliceMake 1824 OpSlicePtr 1825 OpSliceLen 1826 OpSliceCap 1827 OpComplexMake 1828 OpComplexReal 1829 OpComplexImag 1830 OpStringMake 1831 OpStringPtr 1832 OpStringLen 1833 OpIMake 1834 OpITab 1835 OpIData 1836 OpStructMake0 1837 OpStructMake1 1838 OpStructMake2 1839 OpStructMake3 1840 OpStructMake4 1841 OpStructSelect 1842 OpArrayMake0 1843 OpArrayMake1 1844 OpArraySelect 1845 OpStoreReg 1846 OpLoadReg 1847 OpFwdRef 1848 OpUnknown 1849 OpVarDef 1850 OpVarKill 1851 OpVarLive 1852 OpKeepAlive 1853 OpInt64Make 1854 OpInt64Hi 1855 OpInt64Lo 1856 OpAdd32carry 1857 OpAdd32withcarry 1858 OpSub32carry 1859 OpSub32withcarry 1860 OpSignmask 1861 OpZeromask 1862 OpSlicemask 1863 OpCvt32Uto32F 1864 OpCvt32Uto64F 1865 OpCvt32Fto32U 1866 OpCvt64Fto32U 1867 OpCvt64Uto32F 1868 OpCvt64Uto64F 1869 OpCvt32Fto64U 1870 OpCvt64Fto64U 1871 OpSelect0 1872 OpSelect1 1873 OpAtomicLoad32 1874 OpAtomicLoad64 1875 OpAtomicLoadPtr 1876 OpAtomicStore32 1877 OpAtomicStore64 1878 OpAtomicStorePtrNoWB 1879 OpAtomicExchange32 1880 OpAtomicExchange64 1881 OpAtomicAdd32 1882 OpAtomicAdd64 1883 OpAtomicCompareAndSwap32 1884 OpAtomicCompareAndSwap64 1885 OpAtomicAnd8 1886 OpAtomicOr8 1887 ) 1888 1889 var opcodeTable = [...]opInfo{ 1890 {name: "OpInvalid"}, 1891 1892 { 1893 name: "ADDSS", 1894 argLen: 2, 1895 commutative: true, 1896 resultInArg0: true, 1897 usesScratch: true, 1898 asm: x86.AADDSS, 1899 reg: regInfo{ 1900 inputs: []inputInfo{ 1901 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1902 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1903 }, 1904 outputs: []outputInfo{ 1905 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1906 }, 1907 }, 1908 }, 1909 { 1910 name: "ADDSD", 1911 argLen: 2, 1912 commutative: true, 1913 resultInArg0: true, 1914 asm: x86.AADDSD, 1915 reg: regInfo{ 1916 inputs: []inputInfo{ 1917 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1918 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1919 }, 1920 outputs: []outputInfo{ 1921 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1922 }, 1923 }, 1924 }, 1925 { 1926 name: "SUBSS", 1927 argLen: 2, 1928 resultInArg0: true, 1929 usesScratch: true, 1930 asm: x86.ASUBSS, 1931 reg: regInfo{ 1932 inputs: []inputInfo{ 1933 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1934 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1935 }, 1936 outputs: []outputInfo{ 1937 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1938 }, 1939 }, 1940 }, 1941 { 1942 name: "SUBSD", 1943 argLen: 2, 1944 resultInArg0: true, 1945 asm: x86.ASUBSD, 1946 reg: regInfo{ 1947 inputs: []inputInfo{ 1948 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1949 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1950 }, 1951 outputs: []outputInfo{ 1952 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1953 }, 1954 }, 1955 }, 1956 { 1957 name: "MULSS", 1958 argLen: 2, 1959 commutative: true, 1960 resultInArg0: true, 1961 usesScratch: true, 1962 asm: x86.AMULSS, 1963 reg: regInfo{ 1964 inputs: []inputInfo{ 1965 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1966 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1967 }, 1968 outputs: []outputInfo{ 1969 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1970 }, 1971 }, 1972 }, 1973 { 1974 name: "MULSD", 1975 argLen: 2, 1976 commutative: true, 1977 resultInArg0: true, 1978 asm: x86.AMULSD, 1979 reg: regInfo{ 1980 inputs: []inputInfo{ 1981 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1982 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1983 }, 1984 outputs: []outputInfo{ 1985 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1986 }, 1987 }, 1988 }, 1989 { 1990 name: "DIVSS", 1991 argLen: 2, 1992 resultInArg0: true, 1993 usesScratch: true, 1994 asm: x86.ADIVSS, 1995 reg: regInfo{ 1996 inputs: []inputInfo{ 1997 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1998 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1999 }, 2000 outputs: []outputInfo{ 2001 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2002 }, 2003 }, 2004 }, 2005 { 2006 name: "DIVSD", 2007 argLen: 2, 2008 resultInArg0: true, 2009 asm: x86.ADIVSD, 2010 reg: regInfo{ 2011 inputs: []inputInfo{ 2012 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2013 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2014 }, 2015 outputs: []outputInfo{ 2016 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2017 }, 2018 }, 2019 }, 2020 { 2021 name: "MOVSSload", 2022 auxType: auxSymOff, 2023 argLen: 2, 2024 faultOnNilArg0: true, 2025 asm: x86.AMOVSS, 2026 reg: regInfo{ 2027 inputs: []inputInfo{ 2028 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2029 }, 2030 outputs: []outputInfo{ 2031 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2032 }, 2033 }, 2034 }, 2035 { 2036 name: "MOVSDload", 2037 auxType: auxSymOff, 2038 argLen: 2, 2039 faultOnNilArg0: true, 2040 asm: x86.AMOVSD, 2041 reg: regInfo{ 2042 inputs: []inputInfo{ 2043 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2044 }, 2045 outputs: []outputInfo{ 2046 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2047 }, 2048 }, 2049 }, 2050 { 2051 name: "MOVSSconst", 2052 auxType: auxFloat32, 2053 argLen: 0, 2054 rematerializeable: true, 2055 asm: x86.AMOVSS, 2056 reg: regInfo{ 2057 outputs: []outputInfo{ 2058 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2059 }, 2060 }, 2061 }, 2062 { 2063 name: "MOVSDconst", 2064 auxType: auxFloat64, 2065 argLen: 0, 2066 rematerializeable: true, 2067 asm: x86.AMOVSD, 2068 reg: regInfo{ 2069 outputs: []outputInfo{ 2070 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2071 }, 2072 }, 2073 }, 2074 { 2075 name: "MOVSSloadidx1", 2076 auxType: auxSymOff, 2077 argLen: 3, 2078 asm: x86.AMOVSS, 2079 reg: regInfo{ 2080 inputs: []inputInfo{ 2081 {1, 255}, // AX CX DX BX SP BP SI DI 2082 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2083 }, 2084 outputs: []outputInfo{ 2085 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2086 }, 2087 }, 2088 }, 2089 { 2090 name: "MOVSSloadidx4", 2091 auxType: auxSymOff, 2092 argLen: 3, 2093 asm: x86.AMOVSS, 2094 reg: regInfo{ 2095 inputs: []inputInfo{ 2096 {1, 255}, // AX CX DX BX SP BP SI DI 2097 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2098 }, 2099 outputs: []outputInfo{ 2100 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2101 }, 2102 }, 2103 }, 2104 { 2105 name: "MOVSDloadidx1", 2106 auxType: auxSymOff, 2107 argLen: 3, 2108 asm: x86.AMOVSD, 2109 reg: regInfo{ 2110 inputs: []inputInfo{ 2111 {1, 255}, // AX CX DX BX SP BP SI DI 2112 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2113 }, 2114 outputs: []outputInfo{ 2115 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2116 }, 2117 }, 2118 }, 2119 { 2120 name: "MOVSDloadidx8", 2121 auxType: auxSymOff, 2122 argLen: 3, 2123 asm: x86.AMOVSD, 2124 reg: regInfo{ 2125 inputs: []inputInfo{ 2126 {1, 255}, // AX CX DX BX SP BP SI DI 2127 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2128 }, 2129 outputs: []outputInfo{ 2130 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2131 }, 2132 }, 2133 }, 2134 { 2135 name: "MOVSSstore", 2136 auxType: auxSymOff, 2137 argLen: 3, 2138 faultOnNilArg0: true, 2139 asm: x86.AMOVSS, 2140 reg: regInfo{ 2141 inputs: []inputInfo{ 2142 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2143 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2144 }, 2145 }, 2146 }, 2147 { 2148 name: "MOVSDstore", 2149 auxType: auxSymOff, 2150 argLen: 3, 2151 faultOnNilArg0: true, 2152 asm: x86.AMOVSD, 2153 reg: regInfo{ 2154 inputs: []inputInfo{ 2155 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2156 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2157 }, 2158 }, 2159 }, 2160 { 2161 name: "MOVSSstoreidx1", 2162 auxType: auxSymOff, 2163 argLen: 4, 2164 asm: x86.AMOVSS, 2165 reg: regInfo{ 2166 inputs: []inputInfo{ 2167 {1, 255}, // AX CX DX BX SP BP SI DI 2168 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2169 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2170 }, 2171 }, 2172 }, 2173 { 2174 name: "MOVSSstoreidx4", 2175 auxType: auxSymOff, 2176 argLen: 4, 2177 asm: x86.AMOVSS, 2178 reg: regInfo{ 2179 inputs: []inputInfo{ 2180 {1, 255}, // AX CX DX BX SP BP SI DI 2181 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2182 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2183 }, 2184 }, 2185 }, 2186 { 2187 name: "MOVSDstoreidx1", 2188 auxType: auxSymOff, 2189 argLen: 4, 2190 asm: x86.AMOVSD, 2191 reg: regInfo{ 2192 inputs: []inputInfo{ 2193 {1, 255}, // AX CX DX BX SP BP SI DI 2194 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2195 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2196 }, 2197 }, 2198 }, 2199 { 2200 name: "MOVSDstoreidx8", 2201 auxType: auxSymOff, 2202 argLen: 4, 2203 asm: x86.AMOVSD, 2204 reg: regInfo{ 2205 inputs: []inputInfo{ 2206 {1, 255}, // AX CX DX BX SP BP SI DI 2207 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2208 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2209 }, 2210 }, 2211 }, 2212 { 2213 name: "ADDL", 2214 argLen: 2, 2215 commutative: true, 2216 clobberFlags: true, 2217 asm: x86.AADDL, 2218 reg: regInfo{ 2219 inputs: []inputInfo{ 2220 {1, 239}, // AX CX DX BX BP SI DI 2221 {0, 255}, // AX CX DX BX SP BP SI DI 2222 }, 2223 outputs: []outputInfo{ 2224 {0, 239}, // AX CX DX BX BP SI DI 2225 }, 2226 }, 2227 }, 2228 { 2229 name: "ADDLconst", 2230 auxType: auxInt32, 2231 argLen: 1, 2232 clobberFlags: true, 2233 asm: x86.AADDL, 2234 reg: regInfo{ 2235 inputs: []inputInfo{ 2236 {0, 255}, // AX CX DX BX SP BP SI DI 2237 }, 2238 outputs: []outputInfo{ 2239 {0, 239}, // AX CX DX BX BP SI DI 2240 }, 2241 }, 2242 }, 2243 { 2244 name: "ADDLcarry", 2245 argLen: 2, 2246 commutative: true, 2247 resultInArg0: true, 2248 asm: x86.AADDL, 2249 reg: regInfo{ 2250 inputs: []inputInfo{ 2251 {0, 239}, // AX CX DX BX BP SI DI 2252 {1, 239}, // AX CX DX BX BP SI DI 2253 }, 2254 outputs: []outputInfo{ 2255 {1, 0}, 2256 {0, 239}, // AX CX DX BX BP SI DI 2257 }, 2258 }, 2259 }, 2260 { 2261 name: "ADDLconstcarry", 2262 auxType: auxInt32, 2263 argLen: 1, 2264 resultInArg0: true, 2265 asm: x86.AADDL, 2266 reg: regInfo{ 2267 inputs: []inputInfo{ 2268 {0, 239}, // AX CX DX BX BP SI DI 2269 }, 2270 outputs: []outputInfo{ 2271 {1, 0}, 2272 {0, 239}, // AX CX DX BX BP SI DI 2273 }, 2274 }, 2275 }, 2276 { 2277 name: "ADCL", 2278 argLen: 3, 2279 commutative: true, 2280 resultInArg0: true, 2281 clobberFlags: true, 2282 asm: x86.AADCL, 2283 reg: regInfo{ 2284 inputs: []inputInfo{ 2285 {0, 239}, // AX CX DX BX BP SI DI 2286 {1, 239}, // AX CX DX BX BP SI DI 2287 }, 2288 outputs: []outputInfo{ 2289 {0, 239}, // AX CX DX BX BP SI DI 2290 }, 2291 }, 2292 }, 2293 { 2294 name: "ADCLconst", 2295 auxType: auxInt32, 2296 argLen: 2, 2297 resultInArg0: true, 2298 clobberFlags: true, 2299 asm: x86.AADCL, 2300 reg: regInfo{ 2301 inputs: []inputInfo{ 2302 {0, 239}, // AX CX DX BX BP SI DI 2303 }, 2304 outputs: []outputInfo{ 2305 {0, 239}, // AX CX DX BX BP SI DI 2306 }, 2307 }, 2308 }, 2309 { 2310 name: "SUBL", 2311 argLen: 2, 2312 resultInArg0: true, 2313 clobberFlags: true, 2314 asm: x86.ASUBL, 2315 reg: regInfo{ 2316 inputs: []inputInfo{ 2317 {0, 239}, // AX CX DX BX BP SI DI 2318 {1, 239}, // AX CX DX BX BP SI DI 2319 }, 2320 outputs: []outputInfo{ 2321 {0, 239}, // AX CX DX BX BP SI DI 2322 }, 2323 }, 2324 }, 2325 { 2326 name: "SUBLconst", 2327 auxType: auxInt32, 2328 argLen: 1, 2329 resultInArg0: true, 2330 clobberFlags: true, 2331 asm: x86.ASUBL, 2332 reg: regInfo{ 2333 inputs: []inputInfo{ 2334 {0, 239}, // AX CX DX BX BP SI DI 2335 }, 2336 outputs: []outputInfo{ 2337 {0, 239}, // AX CX DX BX BP SI DI 2338 }, 2339 }, 2340 }, 2341 { 2342 name: "SUBLcarry", 2343 argLen: 2, 2344 resultInArg0: true, 2345 asm: x86.ASUBL, 2346 reg: regInfo{ 2347 inputs: []inputInfo{ 2348 {0, 239}, // AX CX DX BX BP SI DI 2349 {1, 239}, // AX CX DX BX BP SI DI 2350 }, 2351 outputs: []outputInfo{ 2352 {1, 0}, 2353 {0, 239}, // AX CX DX BX BP SI DI 2354 }, 2355 }, 2356 }, 2357 { 2358 name: "SUBLconstcarry", 2359 auxType: auxInt32, 2360 argLen: 1, 2361 resultInArg0: true, 2362 asm: x86.ASUBL, 2363 reg: regInfo{ 2364 inputs: []inputInfo{ 2365 {0, 239}, // AX CX DX BX BP SI DI 2366 }, 2367 outputs: []outputInfo{ 2368 {1, 0}, 2369 {0, 239}, // AX CX DX BX BP SI DI 2370 }, 2371 }, 2372 }, 2373 { 2374 name: "SBBL", 2375 argLen: 3, 2376 resultInArg0: true, 2377 clobberFlags: true, 2378 asm: x86.ASBBL, 2379 reg: regInfo{ 2380 inputs: []inputInfo{ 2381 {0, 239}, // AX CX DX BX BP SI DI 2382 {1, 239}, // AX CX DX BX BP SI DI 2383 }, 2384 outputs: []outputInfo{ 2385 {0, 239}, // AX CX DX BX BP SI DI 2386 }, 2387 }, 2388 }, 2389 { 2390 name: "SBBLconst", 2391 auxType: auxInt32, 2392 argLen: 2, 2393 resultInArg0: true, 2394 clobberFlags: true, 2395 asm: x86.ASBBL, 2396 reg: regInfo{ 2397 inputs: []inputInfo{ 2398 {0, 239}, // AX CX DX BX BP SI DI 2399 }, 2400 outputs: []outputInfo{ 2401 {0, 239}, // AX CX DX BX BP SI DI 2402 }, 2403 }, 2404 }, 2405 { 2406 name: "MULL", 2407 argLen: 2, 2408 commutative: true, 2409 resultInArg0: true, 2410 clobberFlags: true, 2411 asm: x86.AIMULL, 2412 reg: regInfo{ 2413 inputs: []inputInfo{ 2414 {0, 239}, // AX CX DX BX BP SI DI 2415 {1, 239}, // AX CX DX BX BP SI DI 2416 }, 2417 outputs: []outputInfo{ 2418 {0, 239}, // AX CX DX BX BP SI DI 2419 }, 2420 }, 2421 }, 2422 { 2423 name: "MULLconst", 2424 auxType: auxInt32, 2425 argLen: 1, 2426 resultInArg0: true, 2427 clobberFlags: true, 2428 asm: x86.AIMULL, 2429 reg: regInfo{ 2430 inputs: []inputInfo{ 2431 {0, 239}, // AX CX DX BX BP SI DI 2432 }, 2433 outputs: []outputInfo{ 2434 {0, 239}, // AX CX DX BX BP SI DI 2435 }, 2436 }, 2437 }, 2438 { 2439 name: "HMULL", 2440 argLen: 2, 2441 clobberFlags: true, 2442 asm: x86.AIMULL, 2443 reg: regInfo{ 2444 inputs: []inputInfo{ 2445 {0, 1}, // AX 2446 {1, 255}, // AX CX DX BX SP BP SI DI 2447 }, 2448 clobbers: 1, // AX 2449 outputs: []outputInfo{ 2450 {0, 4}, // DX 2451 }, 2452 }, 2453 }, 2454 { 2455 name: "HMULLU", 2456 argLen: 2, 2457 clobberFlags: true, 2458 asm: x86.AMULL, 2459 reg: regInfo{ 2460 inputs: []inputInfo{ 2461 {0, 1}, // AX 2462 {1, 255}, // AX CX DX BX SP BP SI DI 2463 }, 2464 clobbers: 1, // AX 2465 outputs: []outputInfo{ 2466 {0, 4}, // DX 2467 }, 2468 }, 2469 }, 2470 { 2471 name: "HMULW", 2472 argLen: 2, 2473 clobberFlags: true, 2474 asm: x86.AIMULW, 2475 reg: regInfo{ 2476 inputs: []inputInfo{ 2477 {0, 1}, // AX 2478 {1, 255}, // AX CX DX BX SP BP SI DI 2479 }, 2480 clobbers: 1, // AX 2481 outputs: []outputInfo{ 2482 {0, 4}, // DX 2483 }, 2484 }, 2485 }, 2486 { 2487 name: "HMULB", 2488 argLen: 2, 2489 clobberFlags: true, 2490 asm: x86.AIMULB, 2491 reg: regInfo{ 2492 inputs: []inputInfo{ 2493 {0, 1}, // AX 2494 {1, 255}, // AX CX DX BX SP BP SI DI 2495 }, 2496 clobbers: 1, // AX 2497 outputs: []outputInfo{ 2498 {0, 4}, // DX 2499 }, 2500 }, 2501 }, 2502 { 2503 name: "HMULWU", 2504 argLen: 2, 2505 clobberFlags: true, 2506 asm: x86.AMULW, 2507 reg: regInfo{ 2508 inputs: []inputInfo{ 2509 {0, 1}, // AX 2510 {1, 255}, // AX CX DX BX SP BP SI DI 2511 }, 2512 clobbers: 1, // AX 2513 outputs: []outputInfo{ 2514 {0, 4}, // DX 2515 }, 2516 }, 2517 }, 2518 { 2519 name: "HMULBU", 2520 argLen: 2, 2521 clobberFlags: true, 2522 asm: x86.AMULB, 2523 reg: regInfo{ 2524 inputs: []inputInfo{ 2525 {0, 1}, // AX 2526 {1, 255}, // AX CX DX BX SP BP SI DI 2527 }, 2528 clobbers: 1, // AX 2529 outputs: []outputInfo{ 2530 {0, 4}, // DX 2531 }, 2532 }, 2533 }, 2534 { 2535 name: "MULLQU", 2536 argLen: 2, 2537 clobberFlags: true, 2538 asm: x86.AMULL, 2539 reg: regInfo{ 2540 inputs: []inputInfo{ 2541 {0, 1}, // AX 2542 {1, 255}, // AX CX DX BX SP BP SI DI 2543 }, 2544 outputs: []outputInfo{ 2545 {0, 4}, // DX 2546 {1, 1}, // AX 2547 }, 2548 }, 2549 }, 2550 { 2551 name: "DIVL", 2552 argLen: 2, 2553 clobberFlags: true, 2554 asm: x86.AIDIVL, 2555 reg: regInfo{ 2556 inputs: []inputInfo{ 2557 {0, 1}, // AX 2558 {1, 251}, // AX CX BX SP BP SI DI 2559 }, 2560 clobbers: 4, // DX 2561 outputs: []outputInfo{ 2562 {0, 1}, // AX 2563 }, 2564 }, 2565 }, 2566 { 2567 name: "DIVW", 2568 argLen: 2, 2569 clobberFlags: true, 2570 asm: x86.AIDIVW, 2571 reg: regInfo{ 2572 inputs: []inputInfo{ 2573 {0, 1}, // AX 2574 {1, 251}, // AX CX BX SP BP SI DI 2575 }, 2576 clobbers: 4, // DX 2577 outputs: []outputInfo{ 2578 {0, 1}, // AX 2579 }, 2580 }, 2581 }, 2582 { 2583 name: "DIVLU", 2584 argLen: 2, 2585 clobberFlags: true, 2586 asm: x86.ADIVL, 2587 reg: regInfo{ 2588 inputs: []inputInfo{ 2589 {0, 1}, // AX 2590 {1, 251}, // AX CX BX SP BP SI DI 2591 }, 2592 clobbers: 4, // DX 2593 outputs: []outputInfo{ 2594 {0, 1}, // AX 2595 }, 2596 }, 2597 }, 2598 { 2599 name: "DIVWU", 2600 argLen: 2, 2601 clobberFlags: true, 2602 asm: x86.ADIVW, 2603 reg: regInfo{ 2604 inputs: []inputInfo{ 2605 {0, 1}, // AX 2606 {1, 251}, // AX CX BX SP BP SI DI 2607 }, 2608 clobbers: 4, // DX 2609 outputs: []outputInfo{ 2610 {0, 1}, // AX 2611 }, 2612 }, 2613 }, 2614 { 2615 name: "MODL", 2616 argLen: 2, 2617 clobberFlags: true, 2618 asm: x86.AIDIVL, 2619 reg: regInfo{ 2620 inputs: []inputInfo{ 2621 {0, 1}, // AX 2622 {1, 251}, // AX CX BX SP BP SI DI 2623 }, 2624 clobbers: 1, // AX 2625 outputs: []outputInfo{ 2626 {0, 4}, // DX 2627 }, 2628 }, 2629 }, 2630 { 2631 name: "MODW", 2632 argLen: 2, 2633 clobberFlags: true, 2634 asm: x86.AIDIVW, 2635 reg: regInfo{ 2636 inputs: []inputInfo{ 2637 {0, 1}, // AX 2638 {1, 251}, // AX CX BX SP BP SI DI 2639 }, 2640 clobbers: 1, // AX 2641 outputs: []outputInfo{ 2642 {0, 4}, // DX 2643 }, 2644 }, 2645 }, 2646 { 2647 name: "MODLU", 2648 argLen: 2, 2649 clobberFlags: true, 2650 asm: x86.ADIVL, 2651 reg: regInfo{ 2652 inputs: []inputInfo{ 2653 {0, 1}, // AX 2654 {1, 251}, // AX CX BX SP BP SI DI 2655 }, 2656 clobbers: 1, // AX 2657 outputs: []outputInfo{ 2658 {0, 4}, // DX 2659 }, 2660 }, 2661 }, 2662 { 2663 name: "MODWU", 2664 argLen: 2, 2665 clobberFlags: true, 2666 asm: x86.ADIVW, 2667 reg: regInfo{ 2668 inputs: []inputInfo{ 2669 {0, 1}, // AX 2670 {1, 251}, // AX CX BX SP BP SI DI 2671 }, 2672 clobbers: 1, // AX 2673 outputs: []outputInfo{ 2674 {0, 4}, // DX 2675 }, 2676 }, 2677 }, 2678 { 2679 name: "ANDL", 2680 argLen: 2, 2681 commutative: true, 2682 resultInArg0: true, 2683 clobberFlags: true, 2684 asm: x86.AANDL, 2685 reg: regInfo{ 2686 inputs: []inputInfo{ 2687 {0, 239}, // AX CX DX BX BP SI DI 2688 {1, 239}, // AX CX DX BX BP SI DI 2689 }, 2690 outputs: []outputInfo{ 2691 {0, 239}, // AX CX DX BX BP SI DI 2692 }, 2693 }, 2694 }, 2695 { 2696 name: "ANDLconst", 2697 auxType: auxInt32, 2698 argLen: 1, 2699 resultInArg0: true, 2700 clobberFlags: true, 2701 asm: x86.AANDL, 2702 reg: regInfo{ 2703 inputs: []inputInfo{ 2704 {0, 239}, // AX CX DX BX BP SI DI 2705 }, 2706 outputs: []outputInfo{ 2707 {0, 239}, // AX CX DX BX BP SI DI 2708 }, 2709 }, 2710 }, 2711 { 2712 name: "ORL", 2713 argLen: 2, 2714 commutative: true, 2715 resultInArg0: true, 2716 clobberFlags: true, 2717 asm: x86.AORL, 2718 reg: regInfo{ 2719 inputs: []inputInfo{ 2720 {0, 239}, // AX CX DX BX BP SI DI 2721 {1, 239}, // AX CX DX BX BP SI DI 2722 }, 2723 outputs: []outputInfo{ 2724 {0, 239}, // AX CX DX BX BP SI DI 2725 }, 2726 }, 2727 }, 2728 { 2729 name: "ORLconst", 2730 auxType: auxInt32, 2731 argLen: 1, 2732 resultInArg0: true, 2733 clobberFlags: true, 2734 asm: x86.AORL, 2735 reg: regInfo{ 2736 inputs: []inputInfo{ 2737 {0, 239}, // AX CX DX BX BP SI DI 2738 }, 2739 outputs: []outputInfo{ 2740 {0, 239}, // AX CX DX BX BP SI DI 2741 }, 2742 }, 2743 }, 2744 { 2745 name: "XORL", 2746 argLen: 2, 2747 commutative: true, 2748 resultInArg0: true, 2749 clobberFlags: true, 2750 asm: x86.AXORL, 2751 reg: regInfo{ 2752 inputs: []inputInfo{ 2753 {0, 239}, // AX CX DX BX BP SI DI 2754 {1, 239}, // AX CX DX BX BP SI DI 2755 }, 2756 outputs: []outputInfo{ 2757 {0, 239}, // AX CX DX BX BP SI DI 2758 }, 2759 }, 2760 }, 2761 { 2762 name: "XORLconst", 2763 auxType: auxInt32, 2764 argLen: 1, 2765 resultInArg0: true, 2766 clobberFlags: true, 2767 asm: x86.AXORL, 2768 reg: regInfo{ 2769 inputs: []inputInfo{ 2770 {0, 239}, // AX CX DX BX BP SI DI 2771 }, 2772 outputs: []outputInfo{ 2773 {0, 239}, // AX CX DX BX BP SI DI 2774 }, 2775 }, 2776 }, 2777 { 2778 name: "CMPL", 2779 argLen: 2, 2780 asm: x86.ACMPL, 2781 reg: regInfo{ 2782 inputs: []inputInfo{ 2783 {0, 255}, // AX CX DX BX SP BP SI DI 2784 {1, 255}, // AX CX DX BX SP BP SI DI 2785 }, 2786 }, 2787 }, 2788 { 2789 name: "CMPW", 2790 argLen: 2, 2791 asm: x86.ACMPW, 2792 reg: regInfo{ 2793 inputs: []inputInfo{ 2794 {0, 255}, // AX CX DX BX SP BP SI DI 2795 {1, 255}, // AX CX DX BX SP BP SI DI 2796 }, 2797 }, 2798 }, 2799 { 2800 name: "CMPB", 2801 argLen: 2, 2802 asm: x86.ACMPB, 2803 reg: regInfo{ 2804 inputs: []inputInfo{ 2805 {0, 255}, // AX CX DX BX SP BP SI DI 2806 {1, 255}, // AX CX DX BX SP BP SI DI 2807 }, 2808 }, 2809 }, 2810 { 2811 name: "CMPLconst", 2812 auxType: auxInt32, 2813 argLen: 1, 2814 asm: x86.ACMPL, 2815 reg: regInfo{ 2816 inputs: []inputInfo{ 2817 {0, 255}, // AX CX DX BX SP BP SI DI 2818 }, 2819 }, 2820 }, 2821 { 2822 name: "CMPWconst", 2823 auxType: auxInt16, 2824 argLen: 1, 2825 asm: x86.ACMPW, 2826 reg: regInfo{ 2827 inputs: []inputInfo{ 2828 {0, 255}, // AX CX DX BX SP BP SI DI 2829 }, 2830 }, 2831 }, 2832 { 2833 name: "CMPBconst", 2834 auxType: auxInt8, 2835 argLen: 1, 2836 asm: x86.ACMPB, 2837 reg: regInfo{ 2838 inputs: []inputInfo{ 2839 {0, 255}, // AX CX DX BX SP BP SI DI 2840 }, 2841 }, 2842 }, 2843 { 2844 name: "UCOMISS", 2845 argLen: 2, 2846 usesScratch: true, 2847 asm: x86.AUCOMISS, 2848 reg: regInfo{ 2849 inputs: []inputInfo{ 2850 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2851 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2852 }, 2853 }, 2854 }, 2855 { 2856 name: "UCOMISD", 2857 argLen: 2, 2858 usesScratch: true, 2859 asm: x86.AUCOMISD, 2860 reg: regInfo{ 2861 inputs: []inputInfo{ 2862 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2863 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2864 }, 2865 }, 2866 }, 2867 { 2868 name: "TESTL", 2869 argLen: 2, 2870 asm: x86.ATESTL, 2871 reg: regInfo{ 2872 inputs: []inputInfo{ 2873 {0, 255}, // AX CX DX BX SP BP SI DI 2874 {1, 255}, // AX CX DX BX SP BP SI DI 2875 }, 2876 }, 2877 }, 2878 { 2879 name: "TESTW", 2880 argLen: 2, 2881 asm: x86.ATESTW, 2882 reg: regInfo{ 2883 inputs: []inputInfo{ 2884 {0, 255}, // AX CX DX BX SP BP SI DI 2885 {1, 255}, // AX CX DX BX SP BP SI DI 2886 }, 2887 }, 2888 }, 2889 { 2890 name: "TESTB", 2891 argLen: 2, 2892 asm: x86.ATESTB, 2893 reg: regInfo{ 2894 inputs: []inputInfo{ 2895 {0, 255}, // AX CX DX BX SP BP SI DI 2896 {1, 255}, // AX CX DX BX SP BP SI DI 2897 }, 2898 }, 2899 }, 2900 { 2901 name: "TESTLconst", 2902 auxType: auxInt32, 2903 argLen: 1, 2904 asm: x86.ATESTL, 2905 reg: regInfo{ 2906 inputs: []inputInfo{ 2907 {0, 255}, // AX CX DX BX SP BP SI DI 2908 }, 2909 }, 2910 }, 2911 { 2912 name: "TESTWconst", 2913 auxType: auxInt16, 2914 argLen: 1, 2915 asm: x86.ATESTW, 2916 reg: regInfo{ 2917 inputs: []inputInfo{ 2918 {0, 255}, // AX CX DX BX SP BP SI DI 2919 }, 2920 }, 2921 }, 2922 { 2923 name: "TESTBconst", 2924 auxType: auxInt8, 2925 argLen: 1, 2926 asm: x86.ATESTB, 2927 reg: regInfo{ 2928 inputs: []inputInfo{ 2929 {0, 255}, // AX CX DX BX SP BP SI DI 2930 }, 2931 }, 2932 }, 2933 { 2934 name: "SHLL", 2935 argLen: 2, 2936 resultInArg0: true, 2937 clobberFlags: true, 2938 asm: x86.ASHLL, 2939 reg: regInfo{ 2940 inputs: []inputInfo{ 2941 {1, 2}, // CX 2942 {0, 239}, // AX CX DX BX BP SI DI 2943 }, 2944 outputs: []outputInfo{ 2945 {0, 239}, // AX CX DX BX BP SI DI 2946 }, 2947 }, 2948 }, 2949 { 2950 name: "SHLLconst", 2951 auxType: auxInt32, 2952 argLen: 1, 2953 resultInArg0: true, 2954 clobberFlags: true, 2955 asm: x86.ASHLL, 2956 reg: regInfo{ 2957 inputs: []inputInfo{ 2958 {0, 239}, // AX CX DX BX BP SI DI 2959 }, 2960 outputs: []outputInfo{ 2961 {0, 239}, // AX CX DX BX BP SI DI 2962 }, 2963 }, 2964 }, 2965 { 2966 name: "SHRL", 2967 argLen: 2, 2968 resultInArg0: true, 2969 clobberFlags: true, 2970 asm: x86.ASHRL, 2971 reg: regInfo{ 2972 inputs: []inputInfo{ 2973 {1, 2}, // CX 2974 {0, 239}, // AX CX DX BX BP SI DI 2975 }, 2976 outputs: []outputInfo{ 2977 {0, 239}, // AX CX DX BX BP SI DI 2978 }, 2979 }, 2980 }, 2981 { 2982 name: "SHRW", 2983 argLen: 2, 2984 resultInArg0: true, 2985 clobberFlags: true, 2986 asm: x86.ASHRW, 2987 reg: regInfo{ 2988 inputs: []inputInfo{ 2989 {1, 2}, // CX 2990 {0, 239}, // AX CX DX BX BP SI DI 2991 }, 2992 outputs: []outputInfo{ 2993 {0, 239}, // AX CX DX BX BP SI DI 2994 }, 2995 }, 2996 }, 2997 { 2998 name: "SHRB", 2999 argLen: 2, 3000 resultInArg0: true, 3001 clobberFlags: true, 3002 asm: x86.ASHRB, 3003 reg: regInfo{ 3004 inputs: []inputInfo{ 3005 {1, 2}, // CX 3006 {0, 239}, // AX CX DX BX BP SI DI 3007 }, 3008 outputs: []outputInfo{ 3009 {0, 239}, // AX CX DX BX BP SI DI 3010 }, 3011 }, 3012 }, 3013 { 3014 name: "SHRLconst", 3015 auxType: auxInt32, 3016 argLen: 1, 3017 resultInArg0: true, 3018 clobberFlags: true, 3019 asm: x86.ASHRL, 3020 reg: regInfo{ 3021 inputs: []inputInfo{ 3022 {0, 239}, // AX CX DX BX BP SI DI 3023 }, 3024 outputs: []outputInfo{ 3025 {0, 239}, // AX CX DX BX BP SI DI 3026 }, 3027 }, 3028 }, 3029 { 3030 name: "SHRWconst", 3031 auxType: auxInt16, 3032 argLen: 1, 3033 resultInArg0: true, 3034 clobberFlags: true, 3035 asm: x86.ASHRW, 3036 reg: regInfo{ 3037 inputs: []inputInfo{ 3038 {0, 239}, // AX CX DX BX BP SI DI 3039 }, 3040 outputs: []outputInfo{ 3041 {0, 239}, // AX CX DX BX BP SI DI 3042 }, 3043 }, 3044 }, 3045 { 3046 name: "SHRBconst", 3047 auxType: auxInt8, 3048 argLen: 1, 3049 resultInArg0: true, 3050 clobberFlags: true, 3051 asm: x86.ASHRB, 3052 reg: regInfo{ 3053 inputs: []inputInfo{ 3054 {0, 239}, // AX CX DX BX BP SI DI 3055 }, 3056 outputs: []outputInfo{ 3057 {0, 239}, // AX CX DX BX BP SI DI 3058 }, 3059 }, 3060 }, 3061 { 3062 name: "SARL", 3063 argLen: 2, 3064 resultInArg0: true, 3065 clobberFlags: true, 3066 asm: x86.ASARL, 3067 reg: regInfo{ 3068 inputs: []inputInfo{ 3069 {1, 2}, // CX 3070 {0, 239}, // AX CX DX BX BP SI DI 3071 }, 3072 outputs: []outputInfo{ 3073 {0, 239}, // AX CX DX BX BP SI DI 3074 }, 3075 }, 3076 }, 3077 { 3078 name: "SARW", 3079 argLen: 2, 3080 resultInArg0: true, 3081 clobberFlags: true, 3082 asm: x86.ASARW, 3083 reg: regInfo{ 3084 inputs: []inputInfo{ 3085 {1, 2}, // CX 3086 {0, 239}, // AX CX DX BX BP SI DI 3087 }, 3088 outputs: []outputInfo{ 3089 {0, 239}, // AX CX DX BX BP SI DI 3090 }, 3091 }, 3092 }, 3093 { 3094 name: "SARB", 3095 argLen: 2, 3096 resultInArg0: true, 3097 clobberFlags: true, 3098 asm: x86.ASARB, 3099 reg: regInfo{ 3100 inputs: []inputInfo{ 3101 {1, 2}, // CX 3102 {0, 239}, // AX CX DX BX BP SI DI 3103 }, 3104 outputs: []outputInfo{ 3105 {0, 239}, // AX CX DX BX BP SI DI 3106 }, 3107 }, 3108 }, 3109 { 3110 name: "SARLconst", 3111 auxType: auxInt32, 3112 argLen: 1, 3113 resultInArg0: true, 3114 clobberFlags: true, 3115 asm: x86.ASARL, 3116 reg: regInfo{ 3117 inputs: []inputInfo{ 3118 {0, 239}, // AX CX DX BX BP SI DI 3119 }, 3120 outputs: []outputInfo{ 3121 {0, 239}, // AX CX DX BX BP SI DI 3122 }, 3123 }, 3124 }, 3125 { 3126 name: "SARWconst", 3127 auxType: auxInt16, 3128 argLen: 1, 3129 resultInArg0: true, 3130 clobberFlags: true, 3131 asm: x86.ASARW, 3132 reg: regInfo{ 3133 inputs: []inputInfo{ 3134 {0, 239}, // AX CX DX BX BP SI DI 3135 }, 3136 outputs: []outputInfo{ 3137 {0, 239}, // AX CX DX BX BP SI DI 3138 }, 3139 }, 3140 }, 3141 { 3142 name: "SARBconst", 3143 auxType: auxInt8, 3144 argLen: 1, 3145 resultInArg0: true, 3146 clobberFlags: true, 3147 asm: x86.ASARB, 3148 reg: regInfo{ 3149 inputs: []inputInfo{ 3150 {0, 239}, // AX CX DX BX BP SI DI 3151 }, 3152 outputs: []outputInfo{ 3153 {0, 239}, // AX CX DX BX BP SI DI 3154 }, 3155 }, 3156 }, 3157 { 3158 name: "ROLLconst", 3159 auxType: auxInt32, 3160 argLen: 1, 3161 resultInArg0: true, 3162 clobberFlags: true, 3163 asm: x86.AROLL, 3164 reg: regInfo{ 3165 inputs: []inputInfo{ 3166 {0, 239}, // AX CX DX BX BP SI DI 3167 }, 3168 outputs: []outputInfo{ 3169 {0, 239}, // AX CX DX BX BP SI DI 3170 }, 3171 }, 3172 }, 3173 { 3174 name: "ROLWconst", 3175 auxType: auxInt16, 3176 argLen: 1, 3177 resultInArg0: true, 3178 clobberFlags: true, 3179 asm: x86.AROLW, 3180 reg: regInfo{ 3181 inputs: []inputInfo{ 3182 {0, 239}, // AX CX DX BX BP SI DI 3183 }, 3184 outputs: []outputInfo{ 3185 {0, 239}, // AX CX DX BX BP SI DI 3186 }, 3187 }, 3188 }, 3189 { 3190 name: "ROLBconst", 3191 auxType: auxInt8, 3192 argLen: 1, 3193 resultInArg0: true, 3194 clobberFlags: true, 3195 asm: x86.AROLB, 3196 reg: regInfo{ 3197 inputs: []inputInfo{ 3198 {0, 239}, // AX CX DX BX BP SI DI 3199 }, 3200 outputs: []outputInfo{ 3201 {0, 239}, // AX CX DX BX BP SI DI 3202 }, 3203 }, 3204 }, 3205 { 3206 name: "NEGL", 3207 argLen: 1, 3208 resultInArg0: true, 3209 clobberFlags: true, 3210 asm: x86.ANEGL, 3211 reg: regInfo{ 3212 inputs: []inputInfo{ 3213 {0, 239}, // AX CX DX BX BP SI DI 3214 }, 3215 outputs: []outputInfo{ 3216 {0, 239}, // AX CX DX BX BP SI DI 3217 }, 3218 }, 3219 }, 3220 { 3221 name: "NOTL", 3222 argLen: 1, 3223 resultInArg0: true, 3224 clobberFlags: true, 3225 asm: x86.ANOTL, 3226 reg: regInfo{ 3227 inputs: []inputInfo{ 3228 {0, 239}, // AX CX DX BX BP SI DI 3229 }, 3230 outputs: []outputInfo{ 3231 {0, 239}, // AX CX DX BX BP SI DI 3232 }, 3233 }, 3234 }, 3235 { 3236 name: "BSFL", 3237 argLen: 1, 3238 clobberFlags: true, 3239 asm: x86.ABSFL, 3240 reg: regInfo{ 3241 inputs: []inputInfo{ 3242 {0, 239}, // AX CX DX BX BP SI DI 3243 }, 3244 outputs: []outputInfo{ 3245 {0, 239}, // AX CX DX BX BP SI DI 3246 }, 3247 }, 3248 }, 3249 { 3250 name: "BSFW", 3251 argLen: 1, 3252 clobberFlags: true, 3253 asm: x86.ABSFW, 3254 reg: regInfo{ 3255 inputs: []inputInfo{ 3256 {0, 239}, // AX CX DX BX BP SI DI 3257 }, 3258 outputs: []outputInfo{ 3259 {0, 239}, // AX CX DX BX BP SI DI 3260 }, 3261 }, 3262 }, 3263 { 3264 name: "BSRL", 3265 argLen: 1, 3266 clobberFlags: true, 3267 asm: x86.ABSRL, 3268 reg: regInfo{ 3269 inputs: []inputInfo{ 3270 {0, 239}, // AX CX DX BX BP SI DI 3271 }, 3272 outputs: []outputInfo{ 3273 {0, 239}, // AX CX DX BX BP SI DI 3274 }, 3275 }, 3276 }, 3277 { 3278 name: "BSRW", 3279 argLen: 1, 3280 clobberFlags: true, 3281 asm: x86.ABSRW, 3282 reg: regInfo{ 3283 inputs: []inputInfo{ 3284 {0, 239}, // AX CX DX BX BP SI DI 3285 }, 3286 outputs: []outputInfo{ 3287 {0, 239}, // AX CX DX BX BP SI DI 3288 }, 3289 }, 3290 }, 3291 { 3292 name: "BSWAPL", 3293 argLen: 1, 3294 resultInArg0: true, 3295 clobberFlags: true, 3296 asm: x86.ABSWAPL, 3297 reg: regInfo{ 3298 inputs: []inputInfo{ 3299 {0, 239}, // AX CX DX BX BP SI DI 3300 }, 3301 outputs: []outputInfo{ 3302 {0, 239}, // AX CX DX BX BP SI DI 3303 }, 3304 }, 3305 }, 3306 { 3307 name: "SQRTSD", 3308 argLen: 1, 3309 asm: x86.ASQRTSD, 3310 reg: regInfo{ 3311 inputs: []inputInfo{ 3312 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3313 }, 3314 outputs: []outputInfo{ 3315 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3316 }, 3317 }, 3318 }, 3319 { 3320 name: "SBBLcarrymask", 3321 argLen: 1, 3322 asm: x86.ASBBL, 3323 reg: regInfo{ 3324 outputs: []outputInfo{ 3325 {0, 239}, // AX CX DX BX BP SI DI 3326 }, 3327 }, 3328 }, 3329 { 3330 name: "SETEQ", 3331 argLen: 1, 3332 asm: x86.ASETEQ, 3333 reg: regInfo{ 3334 outputs: []outputInfo{ 3335 {0, 239}, // AX CX DX BX BP SI DI 3336 }, 3337 }, 3338 }, 3339 { 3340 name: "SETNE", 3341 argLen: 1, 3342 asm: x86.ASETNE, 3343 reg: regInfo{ 3344 outputs: []outputInfo{ 3345 {0, 239}, // AX CX DX BX BP SI DI 3346 }, 3347 }, 3348 }, 3349 { 3350 name: "SETL", 3351 argLen: 1, 3352 asm: x86.ASETLT, 3353 reg: regInfo{ 3354 outputs: []outputInfo{ 3355 {0, 239}, // AX CX DX BX BP SI DI 3356 }, 3357 }, 3358 }, 3359 { 3360 name: "SETLE", 3361 argLen: 1, 3362 asm: x86.ASETLE, 3363 reg: regInfo{ 3364 outputs: []outputInfo{ 3365 {0, 239}, // AX CX DX BX BP SI DI 3366 }, 3367 }, 3368 }, 3369 { 3370 name: "SETG", 3371 argLen: 1, 3372 asm: x86.ASETGT, 3373 reg: regInfo{ 3374 outputs: []outputInfo{ 3375 {0, 239}, // AX CX DX BX BP SI DI 3376 }, 3377 }, 3378 }, 3379 { 3380 name: "SETGE", 3381 argLen: 1, 3382 asm: x86.ASETGE, 3383 reg: regInfo{ 3384 outputs: []outputInfo{ 3385 {0, 239}, // AX CX DX BX BP SI DI 3386 }, 3387 }, 3388 }, 3389 { 3390 name: "SETB", 3391 argLen: 1, 3392 asm: x86.ASETCS, 3393 reg: regInfo{ 3394 outputs: []outputInfo{ 3395 {0, 239}, // AX CX DX BX BP SI DI 3396 }, 3397 }, 3398 }, 3399 { 3400 name: "SETBE", 3401 argLen: 1, 3402 asm: x86.ASETLS, 3403 reg: regInfo{ 3404 outputs: []outputInfo{ 3405 {0, 239}, // AX CX DX BX BP SI DI 3406 }, 3407 }, 3408 }, 3409 { 3410 name: "SETA", 3411 argLen: 1, 3412 asm: x86.ASETHI, 3413 reg: regInfo{ 3414 outputs: []outputInfo{ 3415 {0, 239}, // AX CX DX BX BP SI DI 3416 }, 3417 }, 3418 }, 3419 { 3420 name: "SETAE", 3421 argLen: 1, 3422 asm: x86.ASETCC, 3423 reg: regInfo{ 3424 outputs: []outputInfo{ 3425 {0, 239}, // AX CX DX BX BP SI DI 3426 }, 3427 }, 3428 }, 3429 { 3430 name: "SETEQF", 3431 argLen: 1, 3432 clobberFlags: true, 3433 asm: x86.ASETEQ, 3434 reg: regInfo{ 3435 clobbers: 1, // AX 3436 outputs: []outputInfo{ 3437 {0, 238}, // CX DX BX BP SI DI 3438 }, 3439 }, 3440 }, 3441 { 3442 name: "SETNEF", 3443 argLen: 1, 3444 clobberFlags: true, 3445 asm: x86.ASETNE, 3446 reg: regInfo{ 3447 clobbers: 1, // AX 3448 outputs: []outputInfo{ 3449 {0, 238}, // CX DX BX BP SI DI 3450 }, 3451 }, 3452 }, 3453 { 3454 name: "SETORD", 3455 argLen: 1, 3456 asm: x86.ASETPC, 3457 reg: regInfo{ 3458 outputs: []outputInfo{ 3459 {0, 239}, // AX CX DX BX BP SI DI 3460 }, 3461 }, 3462 }, 3463 { 3464 name: "SETNAN", 3465 argLen: 1, 3466 asm: x86.ASETPS, 3467 reg: regInfo{ 3468 outputs: []outputInfo{ 3469 {0, 239}, // AX CX DX BX BP SI DI 3470 }, 3471 }, 3472 }, 3473 { 3474 name: "SETGF", 3475 argLen: 1, 3476 asm: x86.ASETHI, 3477 reg: regInfo{ 3478 outputs: []outputInfo{ 3479 {0, 239}, // AX CX DX BX BP SI DI 3480 }, 3481 }, 3482 }, 3483 { 3484 name: "SETGEF", 3485 argLen: 1, 3486 asm: x86.ASETCC, 3487 reg: regInfo{ 3488 outputs: []outputInfo{ 3489 {0, 239}, // AX CX DX BX BP SI DI 3490 }, 3491 }, 3492 }, 3493 { 3494 name: "MOVBLSX", 3495 argLen: 1, 3496 asm: x86.AMOVBLSX, 3497 reg: regInfo{ 3498 inputs: []inputInfo{ 3499 {0, 239}, // AX CX DX BX BP SI DI 3500 }, 3501 outputs: []outputInfo{ 3502 {0, 239}, // AX CX DX BX BP SI DI 3503 }, 3504 }, 3505 }, 3506 { 3507 name: "MOVBLZX", 3508 argLen: 1, 3509 asm: x86.AMOVBLZX, 3510 reg: regInfo{ 3511 inputs: []inputInfo{ 3512 {0, 239}, // AX CX DX BX BP SI DI 3513 }, 3514 outputs: []outputInfo{ 3515 {0, 239}, // AX CX DX BX BP SI DI 3516 }, 3517 }, 3518 }, 3519 { 3520 name: "MOVWLSX", 3521 argLen: 1, 3522 asm: x86.AMOVWLSX, 3523 reg: regInfo{ 3524 inputs: []inputInfo{ 3525 {0, 239}, // AX CX DX BX BP SI DI 3526 }, 3527 outputs: []outputInfo{ 3528 {0, 239}, // AX CX DX BX BP SI DI 3529 }, 3530 }, 3531 }, 3532 { 3533 name: "MOVWLZX", 3534 argLen: 1, 3535 asm: x86.AMOVWLZX, 3536 reg: regInfo{ 3537 inputs: []inputInfo{ 3538 {0, 239}, // AX CX DX BX BP SI DI 3539 }, 3540 outputs: []outputInfo{ 3541 {0, 239}, // AX CX DX BX BP SI DI 3542 }, 3543 }, 3544 }, 3545 { 3546 name: "MOVLconst", 3547 auxType: auxInt32, 3548 argLen: 0, 3549 rematerializeable: true, 3550 asm: x86.AMOVL, 3551 reg: regInfo{ 3552 outputs: []outputInfo{ 3553 {0, 239}, // AX CX DX BX BP SI DI 3554 }, 3555 }, 3556 }, 3557 { 3558 name: "CVTTSD2SL", 3559 argLen: 1, 3560 usesScratch: true, 3561 asm: x86.ACVTTSD2SL, 3562 reg: regInfo{ 3563 inputs: []inputInfo{ 3564 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3565 }, 3566 outputs: []outputInfo{ 3567 {0, 239}, // AX CX DX BX BP SI DI 3568 }, 3569 }, 3570 }, 3571 { 3572 name: "CVTTSS2SL", 3573 argLen: 1, 3574 usesScratch: true, 3575 asm: x86.ACVTTSS2SL, 3576 reg: regInfo{ 3577 inputs: []inputInfo{ 3578 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3579 }, 3580 outputs: []outputInfo{ 3581 {0, 239}, // AX CX DX BX BP SI DI 3582 }, 3583 }, 3584 }, 3585 { 3586 name: "CVTSL2SS", 3587 argLen: 1, 3588 usesScratch: true, 3589 asm: x86.ACVTSL2SS, 3590 reg: regInfo{ 3591 inputs: []inputInfo{ 3592 {0, 239}, // AX CX DX BX BP SI DI 3593 }, 3594 outputs: []outputInfo{ 3595 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3596 }, 3597 }, 3598 }, 3599 { 3600 name: "CVTSL2SD", 3601 argLen: 1, 3602 usesScratch: true, 3603 asm: x86.ACVTSL2SD, 3604 reg: regInfo{ 3605 inputs: []inputInfo{ 3606 {0, 239}, // AX CX DX BX BP SI DI 3607 }, 3608 outputs: []outputInfo{ 3609 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3610 }, 3611 }, 3612 }, 3613 { 3614 name: "CVTSD2SS", 3615 argLen: 1, 3616 usesScratch: true, 3617 asm: x86.ACVTSD2SS, 3618 reg: regInfo{ 3619 inputs: []inputInfo{ 3620 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3621 }, 3622 outputs: []outputInfo{ 3623 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3624 }, 3625 }, 3626 }, 3627 { 3628 name: "CVTSS2SD", 3629 argLen: 1, 3630 asm: x86.ACVTSS2SD, 3631 reg: regInfo{ 3632 inputs: []inputInfo{ 3633 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3634 }, 3635 outputs: []outputInfo{ 3636 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3637 }, 3638 }, 3639 }, 3640 { 3641 name: "PXOR", 3642 argLen: 2, 3643 commutative: true, 3644 resultInArg0: true, 3645 asm: x86.APXOR, 3646 reg: regInfo{ 3647 inputs: []inputInfo{ 3648 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3649 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3650 }, 3651 outputs: []outputInfo{ 3652 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3653 }, 3654 }, 3655 }, 3656 { 3657 name: "LEAL", 3658 auxType: auxSymOff, 3659 argLen: 1, 3660 rematerializeable: true, 3661 reg: regInfo{ 3662 inputs: []inputInfo{ 3663 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3664 }, 3665 outputs: []outputInfo{ 3666 {0, 239}, // AX CX DX BX BP SI DI 3667 }, 3668 }, 3669 }, 3670 { 3671 name: "LEAL1", 3672 auxType: auxSymOff, 3673 argLen: 2, 3674 reg: regInfo{ 3675 inputs: []inputInfo{ 3676 {1, 255}, // AX CX DX BX SP BP SI DI 3677 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3678 }, 3679 outputs: []outputInfo{ 3680 {0, 239}, // AX CX DX BX BP SI DI 3681 }, 3682 }, 3683 }, 3684 { 3685 name: "LEAL2", 3686 auxType: auxSymOff, 3687 argLen: 2, 3688 reg: regInfo{ 3689 inputs: []inputInfo{ 3690 {1, 255}, // AX CX DX BX SP BP SI DI 3691 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3692 }, 3693 outputs: []outputInfo{ 3694 {0, 239}, // AX CX DX BX BP SI DI 3695 }, 3696 }, 3697 }, 3698 { 3699 name: "LEAL4", 3700 auxType: auxSymOff, 3701 argLen: 2, 3702 reg: regInfo{ 3703 inputs: []inputInfo{ 3704 {1, 255}, // AX CX DX BX SP BP SI DI 3705 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3706 }, 3707 outputs: []outputInfo{ 3708 {0, 239}, // AX CX DX BX BP SI DI 3709 }, 3710 }, 3711 }, 3712 { 3713 name: "LEAL8", 3714 auxType: auxSymOff, 3715 argLen: 2, 3716 reg: regInfo{ 3717 inputs: []inputInfo{ 3718 {1, 255}, // AX CX DX BX SP BP SI DI 3719 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3720 }, 3721 outputs: []outputInfo{ 3722 {0, 239}, // AX CX DX BX BP SI DI 3723 }, 3724 }, 3725 }, 3726 { 3727 name: "MOVBload", 3728 auxType: auxSymOff, 3729 argLen: 2, 3730 faultOnNilArg0: true, 3731 asm: x86.AMOVBLZX, 3732 reg: regInfo{ 3733 inputs: []inputInfo{ 3734 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3735 }, 3736 outputs: []outputInfo{ 3737 {0, 239}, // AX CX DX BX BP SI DI 3738 }, 3739 }, 3740 }, 3741 { 3742 name: "MOVBLSXload", 3743 auxType: auxSymOff, 3744 argLen: 2, 3745 faultOnNilArg0: true, 3746 asm: x86.AMOVBLSX, 3747 reg: regInfo{ 3748 inputs: []inputInfo{ 3749 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3750 }, 3751 outputs: []outputInfo{ 3752 {0, 239}, // AX CX DX BX BP SI DI 3753 }, 3754 }, 3755 }, 3756 { 3757 name: "MOVWload", 3758 auxType: auxSymOff, 3759 argLen: 2, 3760 faultOnNilArg0: true, 3761 asm: x86.AMOVWLZX, 3762 reg: regInfo{ 3763 inputs: []inputInfo{ 3764 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3765 }, 3766 outputs: []outputInfo{ 3767 {0, 239}, // AX CX DX BX BP SI DI 3768 }, 3769 }, 3770 }, 3771 { 3772 name: "MOVWLSXload", 3773 auxType: auxSymOff, 3774 argLen: 2, 3775 faultOnNilArg0: true, 3776 asm: x86.AMOVWLSX, 3777 reg: regInfo{ 3778 inputs: []inputInfo{ 3779 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3780 }, 3781 outputs: []outputInfo{ 3782 {0, 239}, // AX CX DX BX BP SI DI 3783 }, 3784 }, 3785 }, 3786 { 3787 name: "MOVLload", 3788 auxType: auxSymOff, 3789 argLen: 2, 3790 faultOnNilArg0: true, 3791 asm: x86.AMOVL, 3792 reg: regInfo{ 3793 inputs: []inputInfo{ 3794 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3795 }, 3796 outputs: []outputInfo{ 3797 {0, 239}, // AX CX DX BX BP SI DI 3798 }, 3799 }, 3800 }, 3801 { 3802 name: "MOVBstore", 3803 auxType: auxSymOff, 3804 argLen: 3, 3805 faultOnNilArg0: true, 3806 asm: x86.AMOVB, 3807 reg: regInfo{ 3808 inputs: []inputInfo{ 3809 {1, 255}, // AX CX DX BX SP BP SI DI 3810 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3811 }, 3812 }, 3813 }, 3814 { 3815 name: "MOVWstore", 3816 auxType: auxSymOff, 3817 argLen: 3, 3818 faultOnNilArg0: true, 3819 asm: x86.AMOVW, 3820 reg: regInfo{ 3821 inputs: []inputInfo{ 3822 {1, 255}, // AX CX DX BX SP BP SI DI 3823 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3824 }, 3825 }, 3826 }, 3827 { 3828 name: "MOVLstore", 3829 auxType: auxSymOff, 3830 argLen: 3, 3831 faultOnNilArg0: true, 3832 asm: x86.AMOVL, 3833 reg: regInfo{ 3834 inputs: []inputInfo{ 3835 {1, 255}, // AX CX DX BX SP BP SI DI 3836 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3837 }, 3838 }, 3839 }, 3840 { 3841 name: "MOVBloadidx1", 3842 auxType: auxSymOff, 3843 argLen: 3, 3844 asm: x86.AMOVBLZX, 3845 reg: regInfo{ 3846 inputs: []inputInfo{ 3847 {1, 255}, // AX CX DX BX SP BP SI DI 3848 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3849 }, 3850 outputs: []outputInfo{ 3851 {0, 239}, // AX CX DX BX BP SI DI 3852 }, 3853 }, 3854 }, 3855 { 3856 name: "MOVWloadidx1", 3857 auxType: auxSymOff, 3858 argLen: 3, 3859 asm: x86.AMOVWLZX, 3860 reg: regInfo{ 3861 inputs: []inputInfo{ 3862 {1, 255}, // AX CX DX BX SP BP SI DI 3863 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3864 }, 3865 outputs: []outputInfo{ 3866 {0, 239}, // AX CX DX BX BP SI DI 3867 }, 3868 }, 3869 }, 3870 { 3871 name: "MOVWloadidx2", 3872 auxType: auxSymOff, 3873 argLen: 3, 3874 asm: x86.AMOVWLZX, 3875 reg: regInfo{ 3876 inputs: []inputInfo{ 3877 {1, 255}, // AX CX DX BX SP BP SI DI 3878 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3879 }, 3880 outputs: []outputInfo{ 3881 {0, 239}, // AX CX DX BX BP SI DI 3882 }, 3883 }, 3884 }, 3885 { 3886 name: "MOVLloadidx1", 3887 auxType: auxSymOff, 3888 argLen: 3, 3889 asm: x86.AMOVL, 3890 reg: regInfo{ 3891 inputs: []inputInfo{ 3892 {1, 255}, // AX CX DX BX SP BP SI DI 3893 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3894 }, 3895 outputs: []outputInfo{ 3896 {0, 239}, // AX CX DX BX BP SI DI 3897 }, 3898 }, 3899 }, 3900 { 3901 name: "MOVLloadidx4", 3902 auxType: auxSymOff, 3903 argLen: 3, 3904 asm: x86.AMOVL, 3905 reg: regInfo{ 3906 inputs: []inputInfo{ 3907 {1, 255}, // AX CX DX BX SP BP SI DI 3908 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3909 }, 3910 outputs: []outputInfo{ 3911 {0, 239}, // AX CX DX BX BP SI DI 3912 }, 3913 }, 3914 }, 3915 { 3916 name: "MOVBstoreidx1", 3917 auxType: auxSymOff, 3918 argLen: 4, 3919 asm: x86.AMOVB, 3920 reg: regInfo{ 3921 inputs: []inputInfo{ 3922 {1, 255}, // AX CX DX BX SP BP SI DI 3923 {2, 255}, // AX CX DX BX SP BP SI DI 3924 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3925 }, 3926 }, 3927 }, 3928 { 3929 name: "MOVWstoreidx1", 3930 auxType: auxSymOff, 3931 argLen: 4, 3932 asm: x86.AMOVW, 3933 reg: regInfo{ 3934 inputs: []inputInfo{ 3935 {1, 255}, // AX CX DX BX SP BP SI DI 3936 {2, 255}, // AX CX DX BX SP BP SI DI 3937 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3938 }, 3939 }, 3940 }, 3941 { 3942 name: "MOVWstoreidx2", 3943 auxType: auxSymOff, 3944 argLen: 4, 3945 asm: x86.AMOVW, 3946 reg: regInfo{ 3947 inputs: []inputInfo{ 3948 {1, 255}, // AX CX DX BX SP BP SI DI 3949 {2, 255}, // AX CX DX BX SP BP SI DI 3950 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3951 }, 3952 }, 3953 }, 3954 { 3955 name: "MOVLstoreidx1", 3956 auxType: auxSymOff, 3957 argLen: 4, 3958 asm: x86.AMOVL, 3959 reg: regInfo{ 3960 inputs: []inputInfo{ 3961 {1, 255}, // AX CX DX BX SP BP SI DI 3962 {2, 255}, // AX CX DX BX SP BP SI DI 3963 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3964 }, 3965 }, 3966 }, 3967 { 3968 name: "MOVLstoreidx4", 3969 auxType: auxSymOff, 3970 argLen: 4, 3971 asm: x86.AMOVL, 3972 reg: regInfo{ 3973 inputs: []inputInfo{ 3974 {1, 255}, // AX CX DX BX SP BP SI DI 3975 {2, 255}, // AX CX DX BX SP BP SI DI 3976 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3977 }, 3978 }, 3979 }, 3980 { 3981 name: "MOVBstoreconst", 3982 auxType: auxSymValAndOff, 3983 argLen: 2, 3984 faultOnNilArg0: true, 3985 asm: x86.AMOVB, 3986 reg: regInfo{ 3987 inputs: []inputInfo{ 3988 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3989 }, 3990 }, 3991 }, 3992 { 3993 name: "MOVWstoreconst", 3994 auxType: auxSymValAndOff, 3995 argLen: 2, 3996 faultOnNilArg0: true, 3997 asm: x86.AMOVW, 3998 reg: regInfo{ 3999 inputs: []inputInfo{ 4000 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4001 }, 4002 }, 4003 }, 4004 { 4005 name: "MOVLstoreconst", 4006 auxType: auxSymValAndOff, 4007 argLen: 2, 4008 faultOnNilArg0: true, 4009 asm: x86.AMOVL, 4010 reg: regInfo{ 4011 inputs: []inputInfo{ 4012 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4013 }, 4014 }, 4015 }, 4016 { 4017 name: "MOVBstoreconstidx1", 4018 auxType: auxSymValAndOff, 4019 argLen: 3, 4020 asm: x86.AMOVB, 4021 reg: regInfo{ 4022 inputs: []inputInfo{ 4023 {1, 255}, // AX CX DX BX SP BP SI DI 4024 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4025 }, 4026 }, 4027 }, 4028 { 4029 name: "MOVWstoreconstidx1", 4030 auxType: auxSymValAndOff, 4031 argLen: 3, 4032 asm: x86.AMOVW, 4033 reg: regInfo{ 4034 inputs: []inputInfo{ 4035 {1, 255}, // AX CX DX BX SP BP SI DI 4036 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4037 }, 4038 }, 4039 }, 4040 { 4041 name: "MOVWstoreconstidx2", 4042 auxType: auxSymValAndOff, 4043 argLen: 3, 4044 asm: x86.AMOVW, 4045 reg: regInfo{ 4046 inputs: []inputInfo{ 4047 {1, 255}, // AX CX DX BX SP BP SI DI 4048 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4049 }, 4050 }, 4051 }, 4052 { 4053 name: "MOVLstoreconstidx1", 4054 auxType: auxSymValAndOff, 4055 argLen: 3, 4056 asm: x86.AMOVL, 4057 reg: regInfo{ 4058 inputs: []inputInfo{ 4059 {1, 255}, // AX CX DX BX SP BP SI DI 4060 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4061 }, 4062 }, 4063 }, 4064 { 4065 name: "MOVLstoreconstidx4", 4066 auxType: auxSymValAndOff, 4067 argLen: 3, 4068 asm: x86.AMOVL, 4069 reg: regInfo{ 4070 inputs: []inputInfo{ 4071 {1, 255}, // AX CX DX BX SP BP SI DI 4072 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4073 }, 4074 }, 4075 }, 4076 { 4077 name: "DUFFZERO", 4078 auxType: auxInt64, 4079 argLen: 3, 4080 faultOnNilArg0: true, 4081 reg: regInfo{ 4082 inputs: []inputInfo{ 4083 {0, 128}, // DI 4084 {1, 1}, // AX 4085 }, 4086 clobbers: 130, // CX DI 4087 }, 4088 }, 4089 { 4090 name: "REPSTOSL", 4091 argLen: 4, 4092 faultOnNilArg0: true, 4093 reg: regInfo{ 4094 inputs: []inputInfo{ 4095 {0, 128}, // DI 4096 {1, 2}, // CX 4097 {2, 1}, // AX 4098 }, 4099 clobbers: 130, // CX DI 4100 }, 4101 }, 4102 { 4103 name: "CALLstatic", 4104 auxType: auxSymOff, 4105 argLen: 1, 4106 clobberFlags: true, 4107 call: true, 4108 reg: regInfo{ 4109 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4110 }, 4111 }, 4112 { 4113 name: "CALLclosure", 4114 auxType: auxInt64, 4115 argLen: 3, 4116 clobberFlags: true, 4117 call: true, 4118 reg: regInfo{ 4119 inputs: []inputInfo{ 4120 {1, 4}, // DX 4121 {0, 255}, // AX CX DX BX SP BP SI DI 4122 }, 4123 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4124 }, 4125 }, 4126 { 4127 name: "CALLdefer", 4128 auxType: auxInt64, 4129 argLen: 1, 4130 clobberFlags: true, 4131 call: true, 4132 reg: regInfo{ 4133 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4134 }, 4135 }, 4136 { 4137 name: "CALLgo", 4138 auxType: auxInt64, 4139 argLen: 1, 4140 clobberFlags: true, 4141 call: true, 4142 reg: regInfo{ 4143 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4144 }, 4145 }, 4146 { 4147 name: "CALLinter", 4148 auxType: auxInt64, 4149 argLen: 2, 4150 clobberFlags: true, 4151 call: true, 4152 reg: regInfo{ 4153 inputs: []inputInfo{ 4154 {0, 239}, // AX CX DX BX BP SI DI 4155 }, 4156 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4157 }, 4158 }, 4159 { 4160 name: "DUFFCOPY", 4161 auxType: auxInt64, 4162 argLen: 3, 4163 clobberFlags: true, 4164 faultOnNilArg0: true, 4165 faultOnNilArg1: true, 4166 reg: regInfo{ 4167 inputs: []inputInfo{ 4168 {0, 128}, // DI 4169 {1, 64}, // SI 4170 }, 4171 clobbers: 194, // CX SI DI 4172 }, 4173 }, 4174 { 4175 name: "REPMOVSL", 4176 argLen: 4, 4177 faultOnNilArg0: true, 4178 faultOnNilArg1: true, 4179 reg: regInfo{ 4180 inputs: []inputInfo{ 4181 {0, 128}, // DI 4182 {1, 64}, // SI 4183 {2, 2}, // CX 4184 }, 4185 clobbers: 194, // CX SI DI 4186 }, 4187 }, 4188 { 4189 name: "InvertFlags", 4190 argLen: 1, 4191 reg: regInfo{}, 4192 }, 4193 { 4194 name: "LoweredGetG", 4195 argLen: 1, 4196 reg: regInfo{ 4197 outputs: []outputInfo{ 4198 {0, 239}, // AX CX DX BX BP SI DI 4199 }, 4200 }, 4201 }, 4202 { 4203 name: "LoweredGetClosurePtr", 4204 argLen: 0, 4205 reg: regInfo{ 4206 outputs: []outputInfo{ 4207 {0, 4}, // DX 4208 }, 4209 }, 4210 }, 4211 { 4212 name: "LoweredNilCheck", 4213 argLen: 2, 4214 clobberFlags: true, 4215 nilCheck: true, 4216 faultOnNilArg0: true, 4217 reg: regInfo{ 4218 inputs: []inputInfo{ 4219 {0, 255}, // AX CX DX BX SP BP SI DI 4220 }, 4221 }, 4222 }, 4223 { 4224 name: "MOVLconvert", 4225 argLen: 2, 4226 asm: x86.AMOVL, 4227 reg: regInfo{ 4228 inputs: []inputInfo{ 4229 {0, 239}, // AX CX DX BX BP SI DI 4230 }, 4231 outputs: []outputInfo{ 4232 {0, 239}, // AX CX DX BX BP SI DI 4233 }, 4234 }, 4235 }, 4236 { 4237 name: "FlagEQ", 4238 argLen: 0, 4239 reg: regInfo{}, 4240 }, 4241 { 4242 name: "FlagLT_ULT", 4243 argLen: 0, 4244 reg: regInfo{}, 4245 }, 4246 { 4247 name: "FlagLT_UGT", 4248 argLen: 0, 4249 reg: regInfo{}, 4250 }, 4251 { 4252 name: "FlagGT_UGT", 4253 argLen: 0, 4254 reg: regInfo{}, 4255 }, 4256 { 4257 name: "FlagGT_ULT", 4258 argLen: 0, 4259 reg: regInfo{}, 4260 }, 4261 { 4262 name: "FCHS", 4263 argLen: 1, 4264 reg: regInfo{ 4265 inputs: []inputInfo{ 4266 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4267 }, 4268 outputs: []outputInfo{ 4269 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4270 }, 4271 }, 4272 }, 4273 { 4274 name: "MOVSSconst1", 4275 auxType: auxFloat32, 4276 argLen: 0, 4277 reg: regInfo{ 4278 outputs: []outputInfo{ 4279 {0, 239}, // AX CX DX BX BP SI DI 4280 }, 4281 }, 4282 }, 4283 { 4284 name: "MOVSDconst1", 4285 auxType: auxFloat64, 4286 argLen: 0, 4287 reg: regInfo{ 4288 outputs: []outputInfo{ 4289 {0, 239}, // AX CX DX BX BP SI DI 4290 }, 4291 }, 4292 }, 4293 { 4294 name: "MOVSSconst2", 4295 argLen: 1, 4296 asm: x86.AMOVSS, 4297 reg: regInfo{ 4298 inputs: []inputInfo{ 4299 {0, 239}, // AX CX DX BX BP SI DI 4300 }, 4301 outputs: []outputInfo{ 4302 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4303 }, 4304 }, 4305 }, 4306 { 4307 name: "MOVSDconst2", 4308 argLen: 1, 4309 asm: x86.AMOVSD, 4310 reg: regInfo{ 4311 inputs: []inputInfo{ 4312 {0, 239}, // AX CX DX BX BP SI DI 4313 }, 4314 outputs: []outputInfo{ 4315 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4316 }, 4317 }, 4318 }, 4319 4320 { 4321 name: "ADDSS", 4322 argLen: 2, 4323 commutative: true, 4324 resultInArg0: true, 4325 asm: x86.AADDSS, 4326 reg: regInfo{ 4327 inputs: []inputInfo{ 4328 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4329 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4330 }, 4331 outputs: []outputInfo{ 4332 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4333 }, 4334 }, 4335 }, 4336 { 4337 name: "ADDSD", 4338 argLen: 2, 4339 commutative: true, 4340 resultInArg0: true, 4341 asm: x86.AADDSD, 4342 reg: regInfo{ 4343 inputs: []inputInfo{ 4344 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4345 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4346 }, 4347 outputs: []outputInfo{ 4348 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4349 }, 4350 }, 4351 }, 4352 { 4353 name: "SUBSS", 4354 argLen: 2, 4355 resultInArg0: true, 4356 asm: x86.ASUBSS, 4357 reg: regInfo{ 4358 inputs: []inputInfo{ 4359 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4360 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4361 }, 4362 outputs: []outputInfo{ 4363 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4364 }, 4365 }, 4366 }, 4367 { 4368 name: "SUBSD", 4369 argLen: 2, 4370 resultInArg0: true, 4371 asm: x86.ASUBSD, 4372 reg: regInfo{ 4373 inputs: []inputInfo{ 4374 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4375 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4376 }, 4377 outputs: []outputInfo{ 4378 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4379 }, 4380 }, 4381 }, 4382 { 4383 name: "MULSS", 4384 argLen: 2, 4385 commutative: true, 4386 resultInArg0: true, 4387 asm: x86.AMULSS, 4388 reg: regInfo{ 4389 inputs: []inputInfo{ 4390 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4391 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4392 }, 4393 outputs: []outputInfo{ 4394 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4395 }, 4396 }, 4397 }, 4398 { 4399 name: "MULSD", 4400 argLen: 2, 4401 commutative: true, 4402 resultInArg0: true, 4403 asm: x86.AMULSD, 4404 reg: regInfo{ 4405 inputs: []inputInfo{ 4406 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4407 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4408 }, 4409 outputs: []outputInfo{ 4410 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4411 }, 4412 }, 4413 }, 4414 { 4415 name: "DIVSS", 4416 argLen: 2, 4417 resultInArg0: true, 4418 asm: x86.ADIVSS, 4419 reg: regInfo{ 4420 inputs: []inputInfo{ 4421 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4422 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4423 }, 4424 outputs: []outputInfo{ 4425 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4426 }, 4427 }, 4428 }, 4429 { 4430 name: "DIVSD", 4431 argLen: 2, 4432 resultInArg0: true, 4433 asm: x86.ADIVSD, 4434 reg: regInfo{ 4435 inputs: []inputInfo{ 4436 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4437 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4438 }, 4439 outputs: []outputInfo{ 4440 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4441 }, 4442 }, 4443 }, 4444 { 4445 name: "MOVSSload", 4446 auxType: auxSymOff, 4447 argLen: 2, 4448 faultOnNilArg0: true, 4449 asm: x86.AMOVSS, 4450 reg: regInfo{ 4451 inputs: []inputInfo{ 4452 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4453 }, 4454 outputs: []outputInfo{ 4455 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4456 }, 4457 }, 4458 }, 4459 { 4460 name: "MOVSDload", 4461 auxType: auxSymOff, 4462 argLen: 2, 4463 faultOnNilArg0: true, 4464 asm: x86.AMOVSD, 4465 reg: regInfo{ 4466 inputs: []inputInfo{ 4467 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4468 }, 4469 outputs: []outputInfo{ 4470 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4471 }, 4472 }, 4473 }, 4474 { 4475 name: "MOVSSconst", 4476 auxType: auxFloat32, 4477 argLen: 0, 4478 rematerializeable: true, 4479 asm: x86.AMOVSS, 4480 reg: regInfo{ 4481 outputs: []outputInfo{ 4482 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4483 }, 4484 }, 4485 }, 4486 { 4487 name: "MOVSDconst", 4488 auxType: auxFloat64, 4489 argLen: 0, 4490 rematerializeable: true, 4491 asm: x86.AMOVSD, 4492 reg: regInfo{ 4493 outputs: []outputInfo{ 4494 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4495 }, 4496 }, 4497 }, 4498 { 4499 name: "MOVSSloadidx1", 4500 auxType: auxSymOff, 4501 argLen: 3, 4502 asm: x86.AMOVSS, 4503 reg: regInfo{ 4504 inputs: []inputInfo{ 4505 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4506 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4507 }, 4508 outputs: []outputInfo{ 4509 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4510 }, 4511 }, 4512 }, 4513 { 4514 name: "MOVSSloadidx4", 4515 auxType: auxSymOff, 4516 argLen: 3, 4517 asm: x86.AMOVSS, 4518 reg: regInfo{ 4519 inputs: []inputInfo{ 4520 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4521 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4522 }, 4523 outputs: []outputInfo{ 4524 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4525 }, 4526 }, 4527 }, 4528 { 4529 name: "MOVSDloadidx1", 4530 auxType: auxSymOff, 4531 argLen: 3, 4532 asm: x86.AMOVSD, 4533 reg: regInfo{ 4534 inputs: []inputInfo{ 4535 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4536 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4537 }, 4538 outputs: []outputInfo{ 4539 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4540 }, 4541 }, 4542 }, 4543 { 4544 name: "MOVSDloadidx8", 4545 auxType: auxSymOff, 4546 argLen: 3, 4547 asm: x86.AMOVSD, 4548 reg: regInfo{ 4549 inputs: []inputInfo{ 4550 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4551 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4552 }, 4553 outputs: []outputInfo{ 4554 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4555 }, 4556 }, 4557 }, 4558 { 4559 name: "MOVSSstore", 4560 auxType: auxSymOff, 4561 argLen: 3, 4562 faultOnNilArg0: true, 4563 asm: x86.AMOVSS, 4564 reg: regInfo{ 4565 inputs: []inputInfo{ 4566 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4567 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4568 }, 4569 }, 4570 }, 4571 { 4572 name: "MOVSDstore", 4573 auxType: auxSymOff, 4574 argLen: 3, 4575 faultOnNilArg0: true, 4576 asm: x86.AMOVSD, 4577 reg: regInfo{ 4578 inputs: []inputInfo{ 4579 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4580 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4581 }, 4582 }, 4583 }, 4584 { 4585 name: "MOVSSstoreidx1", 4586 auxType: auxSymOff, 4587 argLen: 4, 4588 asm: x86.AMOVSS, 4589 reg: regInfo{ 4590 inputs: []inputInfo{ 4591 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4592 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4593 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4594 }, 4595 }, 4596 }, 4597 { 4598 name: "MOVSSstoreidx4", 4599 auxType: auxSymOff, 4600 argLen: 4, 4601 asm: x86.AMOVSS, 4602 reg: regInfo{ 4603 inputs: []inputInfo{ 4604 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4605 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4606 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4607 }, 4608 }, 4609 }, 4610 { 4611 name: "MOVSDstoreidx1", 4612 auxType: auxSymOff, 4613 argLen: 4, 4614 asm: x86.AMOVSD, 4615 reg: regInfo{ 4616 inputs: []inputInfo{ 4617 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4618 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4619 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4620 }, 4621 }, 4622 }, 4623 { 4624 name: "MOVSDstoreidx8", 4625 auxType: auxSymOff, 4626 argLen: 4, 4627 asm: x86.AMOVSD, 4628 reg: regInfo{ 4629 inputs: []inputInfo{ 4630 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4631 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4632 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4633 }, 4634 }, 4635 }, 4636 { 4637 name: "ADDQ", 4638 argLen: 2, 4639 commutative: true, 4640 clobberFlags: true, 4641 asm: x86.AADDQ, 4642 reg: regInfo{ 4643 inputs: []inputInfo{ 4644 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4645 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4646 }, 4647 outputs: []outputInfo{ 4648 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4649 }, 4650 }, 4651 }, 4652 { 4653 name: "ADDL", 4654 argLen: 2, 4655 commutative: true, 4656 clobberFlags: true, 4657 asm: x86.AADDL, 4658 reg: regInfo{ 4659 inputs: []inputInfo{ 4660 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4661 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4662 }, 4663 outputs: []outputInfo{ 4664 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4665 }, 4666 }, 4667 }, 4668 { 4669 name: "ADDQconst", 4670 auxType: auxInt64, 4671 argLen: 1, 4672 clobberFlags: true, 4673 asm: x86.AADDQ, 4674 reg: regInfo{ 4675 inputs: []inputInfo{ 4676 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4677 }, 4678 outputs: []outputInfo{ 4679 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4680 }, 4681 }, 4682 }, 4683 { 4684 name: "ADDLconst", 4685 auxType: auxInt32, 4686 argLen: 1, 4687 clobberFlags: true, 4688 asm: x86.AADDL, 4689 reg: regInfo{ 4690 inputs: []inputInfo{ 4691 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4692 }, 4693 outputs: []outputInfo{ 4694 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4695 }, 4696 }, 4697 }, 4698 { 4699 name: "SUBQ", 4700 argLen: 2, 4701 resultInArg0: true, 4702 clobberFlags: true, 4703 asm: x86.ASUBQ, 4704 reg: regInfo{ 4705 inputs: []inputInfo{ 4706 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4707 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4708 }, 4709 outputs: []outputInfo{ 4710 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4711 }, 4712 }, 4713 }, 4714 { 4715 name: "SUBL", 4716 argLen: 2, 4717 resultInArg0: true, 4718 clobberFlags: true, 4719 asm: x86.ASUBL, 4720 reg: regInfo{ 4721 inputs: []inputInfo{ 4722 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4723 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4724 }, 4725 outputs: []outputInfo{ 4726 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4727 }, 4728 }, 4729 }, 4730 { 4731 name: "SUBQconst", 4732 auxType: auxInt64, 4733 argLen: 1, 4734 resultInArg0: true, 4735 clobberFlags: true, 4736 asm: x86.ASUBQ, 4737 reg: regInfo{ 4738 inputs: []inputInfo{ 4739 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4740 }, 4741 outputs: []outputInfo{ 4742 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4743 }, 4744 }, 4745 }, 4746 { 4747 name: "SUBLconst", 4748 auxType: auxInt32, 4749 argLen: 1, 4750 resultInArg0: true, 4751 clobberFlags: true, 4752 asm: x86.ASUBL, 4753 reg: regInfo{ 4754 inputs: []inputInfo{ 4755 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4756 }, 4757 outputs: []outputInfo{ 4758 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4759 }, 4760 }, 4761 }, 4762 { 4763 name: "MULQ", 4764 argLen: 2, 4765 commutative: true, 4766 resultInArg0: true, 4767 clobberFlags: true, 4768 asm: x86.AIMULQ, 4769 reg: regInfo{ 4770 inputs: []inputInfo{ 4771 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4772 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4773 }, 4774 outputs: []outputInfo{ 4775 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4776 }, 4777 }, 4778 }, 4779 { 4780 name: "MULL", 4781 argLen: 2, 4782 commutative: true, 4783 resultInArg0: true, 4784 clobberFlags: true, 4785 asm: x86.AIMULL, 4786 reg: regInfo{ 4787 inputs: []inputInfo{ 4788 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4789 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4790 }, 4791 outputs: []outputInfo{ 4792 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4793 }, 4794 }, 4795 }, 4796 { 4797 name: "MULQconst", 4798 auxType: auxInt64, 4799 argLen: 1, 4800 resultInArg0: true, 4801 clobberFlags: true, 4802 asm: x86.AIMULQ, 4803 reg: regInfo{ 4804 inputs: []inputInfo{ 4805 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4806 }, 4807 outputs: []outputInfo{ 4808 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4809 }, 4810 }, 4811 }, 4812 { 4813 name: "MULLconst", 4814 auxType: auxInt32, 4815 argLen: 1, 4816 resultInArg0: true, 4817 clobberFlags: true, 4818 asm: x86.AIMULL, 4819 reg: regInfo{ 4820 inputs: []inputInfo{ 4821 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4822 }, 4823 outputs: []outputInfo{ 4824 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4825 }, 4826 }, 4827 }, 4828 { 4829 name: "HMULQ", 4830 argLen: 2, 4831 clobberFlags: true, 4832 asm: x86.AIMULQ, 4833 reg: regInfo{ 4834 inputs: []inputInfo{ 4835 {0, 1}, // AX 4836 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4837 }, 4838 clobbers: 1, // AX 4839 outputs: []outputInfo{ 4840 {0, 4}, // DX 4841 }, 4842 }, 4843 }, 4844 { 4845 name: "HMULL", 4846 argLen: 2, 4847 clobberFlags: true, 4848 asm: x86.AIMULL, 4849 reg: regInfo{ 4850 inputs: []inputInfo{ 4851 {0, 1}, // AX 4852 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4853 }, 4854 clobbers: 1, // AX 4855 outputs: []outputInfo{ 4856 {0, 4}, // DX 4857 }, 4858 }, 4859 }, 4860 { 4861 name: "HMULW", 4862 argLen: 2, 4863 clobberFlags: true, 4864 asm: x86.AIMULW, 4865 reg: regInfo{ 4866 inputs: []inputInfo{ 4867 {0, 1}, // AX 4868 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4869 }, 4870 clobbers: 1, // AX 4871 outputs: []outputInfo{ 4872 {0, 4}, // DX 4873 }, 4874 }, 4875 }, 4876 { 4877 name: "HMULB", 4878 argLen: 2, 4879 clobberFlags: true, 4880 asm: x86.AIMULB, 4881 reg: regInfo{ 4882 inputs: []inputInfo{ 4883 {0, 1}, // AX 4884 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4885 }, 4886 clobbers: 1, // AX 4887 outputs: []outputInfo{ 4888 {0, 4}, // DX 4889 }, 4890 }, 4891 }, 4892 { 4893 name: "HMULQU", 4894 argLen: 2, 4895 clobberFlags: true, 4896 asm: x86.AMULQ, 4897 reg: regInfo{ 4898 inputs: []inputInfo{ 4899 {0, 1}, // AX 4900 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4901 }, 4902 clobbers: 1, // AX 4903 outputs: []outputInfo{ 4904 {0, 4}, // DX 4905 }, 4906 }, 4907 }, 4908 { 4909 name: "HMULLU", 4910 argLen: 2, 4911 clobberFlags: true, 4912 asm: x86.AMULL, 4913 reg: regInfo{ 4914 inputs: []inputInfo{ 4915 {0, 1}, // AX 4916 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4917 }, 4918 clobbers: 1, // AX 4919 outputs: []outputInfo{ 4920 {0, 4}, // DX 4921 }, 4922 }, 4923 }, 4924 { 4925 name: "HMULWU", 4926 argLen: 2, 4927 clobberFlags: true, 4928 asm: x86.AMULW, 4929 reg: regInfo{ 4930 inputs: []inputInfo{ 4931 {0, 1}, // AX 4932 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4933 }, 4934 clobbers: 1, // AX 4935 outputs: []outputInfo{ 4936 {0, 4}, // DX 4937 }, 4938 }, 4939 }, 4940 { 4941 name: "HMULBU", 4942 argLen: 2, 4943 clobberFlags: true, 4944 asm: x86.AMULB, 4945 reg: regInfo{ 4946 inputs: []inputInfo{ 4947 {0, 1}, // AX 4948 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4949 }, 4950 clobbers: 1, // AX 4951 outputs: []outputInfo{ 4952 {0, 4}, // DX 4953 }, 4954 }, 4955 }, 4956 { 4957 name: "AVGQU", 4958 argLen: 2, 4959 commutative: true, 4960 resultInArg0: true, 4961 clobberFlags: true, 4962 reg: regInfo{ 4963 inputs: []inputInfo{ 4964 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4965 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4966 }, 4967 outputs: []outputInfo{ 4968 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4969 }, 4970 }, 4971 }, 4972 { 4973 name: "DIVQ", 4974 argLen: 2, 4975 clobberFlags: true, 4976 asm: x86.AIDIVQ, 4977 reg: regInfo{ 4978 inputs: []inputInfo{ 4979 {0, 1}, // AX 4980 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4981 }, 4982 outputs: []outputInfo{ 4983 {0, 1}, // AX 4984 {1, 4}, // DX 4985 }, 4986 }, 4987 }, 4988 { 4989 name: "DIVL", 4990 argLen: 2, 4991 clobberFlags: true, 4992 asm: x86.AIDIVL, 4993 reg: regInfo{ 4994 inputs: []inputInfo{ 4995 {0, 1}, // AX 4996 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4997 }, 4998 outputs: []outputInfo{ 4999 {0, 1}, // AX 5000 {1, 4}, // DX 5001 }, 5002 }, 5003 }, 5004 { 5005 name: "DIVW", 5006 argLen: 2, 5007 clobberFlags: true, 5008 asm: x86.AIDIVW, 5009 reg: regInfo{ 5010 inputs: []inputInfo{ 5011 {0, 1}, // AX 5012 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5013 }, 5014 outputs: []outputInfo{ 5015 {0, 1}, // AX 5016 {1, 4}, // DX 5017 }, 5018 }, 5019 }, 5020 { 5021 name: "DIVQU", 5022 argLen: 2, 5023 clobberFlags: true, 5024 asm: x86.ADIVQ, 5025 reg: regInfo{ 5026 inputs: []inputInfo{ 5027 {0, 1}, // AX 5028 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5029 }, 5030 outputs: []outputInfo{ 5031 {0, 1}, // AX 5032 {1, 4}, // DX 5033 }, 5034 }, 5035 }, 5036 { 5037 name: "DIVLU", 5038 argLen: 2, 5039 clobberFlags: true, 5040 asm: x86.ADIVL, 5041 reg: regInfo{ 5042 inputs: []inputInfo{ 5043 {0, 1}, // AX 5044 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5045 }, 5046 outputs: []outputInfo{ 5047 {0, 1}, // AX 5048 {1, 4}, // DX 5049 }, 5050 }, 5051 }, 5052 { 5053 name: "DIVWU", 5054 argLen: 2, 5055 clobberFlags: true, 5056 asm: x86.ADIVW, 5057 reg: regInfo{ 5058 inputs: []inputInfo{ 5059 {0, 1}, // AX 5060 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5061 }, 5062 outputs: []outputInfo{ 5063 {0, 1}, // AX 5064 {1, 4}, // DX 5065 }, 5066 }, 5067 }, 5068 { 5069 name: "MULQU2", 5070 argLen: 2, 5071 clobberFlags: true, 5072 asm: x86.AMULQ, 5073 reg: regInfo{ 5074 inputs: []inputInfo{ 5075 {0, 1}, // AX 5076 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5077 }, 5078 outputs: []outputInfo{ 5079 {0, 4}, // DX 5080 {1, 1}, // AX 5081 }, 5082 }, 5083 }, 5084 { 5085 name: "DIVQU2", 5086 argLen: 3, 5087 clobberFlags: true, 5088 asm: x86.ADIVQ, 5089 reg: regInfo{ 5090 inputs: []inputInfo{ 5091 {0, 4}, // DX 5092 {1, 1}, // AX 5093 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5094 }, 5095 outputs: []outputInfo{ 5096 {0, 1}, // AX 5097 {1, 4}, // DX 5098 }, 5099 }, 5100 }, 5101 { 5102 name: "ANDQ", 5103 argLen: 2, 5104 commutative: true, 5105 resultInArg0: true, 5106 clobberFlags: true, 5107 asm: x86.AANDQ, 5108 reg: regInfo{ 5109 inputs: []inputInfo{ 5110 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5111 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5112 }, 5113 outputs: []outputInfo{ 5114 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5115 }, 5116 }, 5117 }, 5118 { 5119 name: "ANDL", 5120 argLen: 2, 5121 commutative: true, 5122 resultInArg0: true, 5123 clobberFlags: true, 5124 asm: x86.AANDL, 5125 reg: regInfo{ 5126 inputs: []inputInfo{ 5127 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5128 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5129 }, 5130 outputs: []outputInfo{ 5131 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5132 }, 5133 }, 5134 }, 5135 { 5136 name: "ANDQconst", 5137 auxType: auxInt64, 5138 argLen: 1, 5139 resultInArg0: true, 5140 clobberFlags: true, 5141 asm: x86.AANDQ, 5142 reg: regInfo{ 5143 inputs: []inputInfo{ 5144 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5145 }, 5146 outputs: []outputInfo{ 5147 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5148 }, 5149 }, 5150 }, 5151 { 5152 name: "ANDLconst", 5153 auxType: auxInt32, 5154 argLen: 1, 5155 resultInArg0: true, 5156 clobberFlags: true, 5157 asm: x86.AANDL, 5158 reg: regInfo{ 5159 inputs: []inputInfo{ 5160 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5161 }, 5162 outputs: []outputInfo{ 5163 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5164 }, 5165 }, 5166 }, 5167 { 5168 name: "ORQ", 5169 argLen: 2, 5170 commutative: true, 5171 resultInArg0: true, 5172 clobberFlags: true, 5173 asm: x86.AORQ, 5174 reg: regInfo{ 5175 inputs: []inputInfo{ 5176 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5177 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5178 }, 5179 outputs: []outputInfo{ 5180 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5181 }, 5182 }, 5183 }, 5184 { 5185 name: "ORL", 5186 argLen: 2, 5187 commutative: true, 5188 resultInArg0: true, 5189 clobberFlags: true, 5190 asm: x86.AORL, 5191 reg: regInfo{ 5192 inputs: []inputInfo{ 5193 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5194 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5195 }, 5196 outputs: []outputInfo{ 5197 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5198 }, 5199 }, 5200 }, 5201 { 5202 name: "ORQconst", 5203 auxType: auxInt64, 5204 argLen: 1, 5205 resultInArg0: true, 5206 clobberFlags: true, 5207 asm: x86.AORQ, 5208 reg: regInfo{ 5209 inputs: []inputInfo{ 5210 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5211 }, 5212 outputs: []outputInfo{ 5213 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5214 }, 5215 }, 5216 }, 5217 { 5218 name: "ORLconst", 5219 auxType: auxInt32, 5220 argLen: 1, 5221 resultInArg0: true, 5222 clobberFlags: true, 5223 asm: x86.AORL, 5224 reg: regInfo{ 5225 inputs: []inputInfo{ 5226 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5227 }, 5228 outputs: []outputInfo{ 5229 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5230 }, 5231 }, 5232 }, 5233 { 5234 name: "XORQ", 5235 argLen: 2, 5236 commutative: true, 5237 resultInArg0: true, 5238 clobberFlags: true, 5239 asm: x86.AXORQ, 5240 reg: regInfo{ 5241 inputs: []inputInfo{ 5242 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5243 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5244 }, 5245 outputs: []outputInfo{ 5246 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5247 }, 5248 }, 5249 }, 5250 { 5251 name: "XORL", 5252 argLen: 2, 5253 commutative: true, 5254 resultInArg0: true, 5255 clobberFlags: true, 5256 asm: x86.AXORL, 5257 reg: regInfo{ 5258 inputs: []inputInfo{ 5259 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5260 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5261 }, 5262 outputs: []outputInfo{ 5263 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5264 }, 5265 }, 5266 }, 5267 { 5268 name: "XORQconst", 5269 auxType: auxInt64, 5270 argLen: 1, 5271 resultInArg0: true, 5272 clobberFlags: true, 5273 asm: x86.AXORQ, 5274 reg: regInfo{ 5275 inputs: []inputInfo{ 5276 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5277 }, 5278 outputs: []outputInfo{ 5279 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5280 }, 5281 }, 5282 }, 5283 { 5284 name: "XORLconst", 5285 auxType: auxInt32, 5286 argLen: 1, 5287 resultInArg0: true, 5288 clobberFlags: true, 5289 asm: x86.AXORL, 5290 reg: regInfo{ 5291 inputs: []inputInfo{ 5292 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5293 }, 5294 outputs: []outputInfo{ 5295 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5296 }, 5297 }, 5298 }, 5299 { 5300 name: "CMPQ", 5301 argLen: 2, 5302 asm: x86.ACMPQ, 5303 reg: regInfo{ 5304 inputs: []inputInfo{ 5305 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5306 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5307 }, 5308 }, 5309 }, 5310 { 5311 name: "CMPL", 5312 argLen: 2, 5313 asm: x86.ACMPL, 5314 reg: regInfo{ 5315 inputs: []inputInfo{ 5316 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5317 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5318 }, 5319 }, 5320 }, 5321 { 5322 name: "CMPW", 5323 argLen: 2, 5324 asm: x86.ACMPW, 5325 reg: regInfo{ 5326 inputs: []inputInfo{ 5327 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5328 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5329 }, 5330 }, 5331 }, 5332 { 5333 name: "CMPB", 5334 argLen: 2, 5335 asm: x86.ACMPB, 5336 reg: regInfo{ 5337 inputs: []inputInfo{ 5338 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5339 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5340 }, 5341 }, 5342 }, 5343 { 5344 name: "CMPQconst", 5345 auxType: auxInt64, 5346 argLen: 1, 5347 asm: x86.ACMPQ, 5348 reg: regInfo{ 5349 inputs: []inputInfo{ 5350 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5351 }, 5352 }, 5353 }, 5354 { 5355 name: "CMPLconst", 5356 auxType: auxInt32, 5357 argLen: 1, 5358 asm: x86.ACMPL, 5359 reg: regInfo{ 5360 inputs: []inputInfo{ 5361 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5362 }, 5363 }, 5364 }, 5365 { 5366 name: "CMPWconst", 5367 auxType: auxInt16, 5368 argLen: 1, 5369 asm: x86.ACMPW, 5370 reg: regInfo{ 5371 inputs: []inputInfo{ 5372 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5373 }, 5374 }, 5375 }, 5376 { 5377 name: "CMPBconst", 5378 auxType: auxInt8, 5379 argLen: 1, 5380 asm: x86.ACMPB, 5381 reg: regInfo{ 5382 inputs: []inputInfo{ 5383 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5384 }, 5385 }, 5386 }, 5387 { 5388 name: "UCOMISS", 5389 argLen: 2, 5390 asm: x86.AUCOMISS, 5391 reg: regInfo{ 5392 inputs: []inputInfo{ 5393 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5394 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5395 }, 5396 }, 5397 }, 5398 { 5399 name: "UCOMISD", 5400 argLen: 2, 5401 asm: x86.AUCOMISD, 5402 reg: regInfo{ 5403 inputs: []inputInfo{ 5404 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5405 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5406 }, 5407 }, 5408 }, 5409 { 5410 name: "TESTQ", 5411 argLen: 2, 5412 asm: x86.ATESTQ, 5413 reg: regInfo{ 5414 inputs: []inputInfo{ 5415 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5416 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5417 }, 5418 }, 5419 }, 5420 { 5421 name: "TESTL", 5422 argLen: 2, 5423 asm: x86.ATESTL, 5424 reg: regInfo{ 5425 inputs: []inputInfo{ 5426 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5427 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5428 }, 5429 }, 5430 }, 5431 { 5432 name: "TESTW", 5433 argLen: 2, 5434 asm: x86.ATESTW, 5435 reg: regInfo{ 5436 inputs: []inputInfo{ 5437 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5438 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5439 }, 5440 }, 5441 }, 5442 { 5443 name: "TESTB", 5444 argLen: 2, 5445 asm: x86.ATESTB, 5446 reg: regInfo{ 5447 inputs: []inputInfo{ 5448 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5449 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5450 }, 5451 }, 5452 }, 5453 { 5454 name: "TESTQconst", 5455 auxType: auxInt64, 5456 argLen: 1, 5457 asm: x86.ATESTQ, 5458 reg: regInfo{ 5459 inputs: []inputInfo{ 5460 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5461 }, 5462 }, 5463 }, 5464 { 5465 name: "TESTLconst", 5466 auxType: auxInt32, 5467 argLen: 1, 5468 asm: x86.ATESTL, 5469 reg: regInfo{ 5470 inputs: []inputInfo{ 5471 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5472 }, 5473 }, 5474 }, 5475 { 5476 name: "TESTWconst", 5477 auxType: auxInt16, 5478 argLen: 1, 5479 asm: x86.ATESTW, 5480 reg: regInfo{ 5481 inputs: []inputInfo{ 5482 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5483 }, 5484 }, 5485 }, 5486 { 5487 name: "TESTBconst", 5488 auxType: auxInt8, 5489 argLen: 1, 5490 asm: x86.ATESTB, 5491 reg: regInfo{ 5492 inputs: []inputInfo{ 5493 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5494 }, 5495 }, 5496 }, 5497 { 5498 name: "SHLQ", 5499 argLen: 2, 5500 resultInArg0: true, 5501 clobberFlags: true, 5502 asm: x86.ASHLQ, 5503 reg: regInfo{ 5504 inputs: []inputInfo{ 5505 {1, 2}, // CX 5506 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5507 }, 5508 outputs: []outputInfo{ 5509 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5510 }, 5511 }, 5512 }, 5513 { 5514 name: "SHLL", 5515 argLen: 2, 5516 resultInArg0: true, 5517 clobberFlags: true, 5518 asm: x86.ASHLL, 5519 reg: regInfo{ 5520 inputs: []inputInfo{ 5521 {1, 2}, // CX 5522 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5523 }, 5524 outputs: []outputInfo{ 5525 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5526 }, 5527 }, 5528 }, 5529 { 5530 name: "SHLQconst", 5531 auxType: auxInt64, 5532 argLen: 1, 5533 resultInArg0: true, 5534 clobberFlags: true, 5535 asm: x86.ASHLQ, 5536 reg: regInfo{ 5537 inputs: []inputInfo{ 5538 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5539 }, 5540 outputs: []outputInfo{ 5541 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5542 }, 5543 }, 5544 }, 5545 { 5546 name: "SHLLconst", 5547 auxType: auxInt32, 5548 argLen: 1, 5549 resultInArg0: true, 5550 clobberFlags: true, 5551 asm: x86.ASHLL, 5552 reg: regInfo{ 5553 inputs: []inputInfo{ 5554 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5555 }, 5556 outputs: []outputInfo{ 5557 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5558 }, 5559 }, 5560 }, 5561 { 5562 name: "SHRQ", 5563 argLen: 2, 5564 resultInArg0: true, 5565 clobberFlags: true, 5566 asm: x86.ASHRQ, 5567 reg: regInfo{ 5568 inputs: []inputInfo{ 5569 {1, 2}, // CX 5570 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5571 }, 5572 outputs: []outputInfo{ 5573 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5574 }, 5575 }, 5576 }, 5577 { 5578 name: "SHRL", 5579 argLen: 2, 5580 resultInArg0: true, 5581 clobberFlags: true, 5582 asm: x86.ASHRL, 5583 reg: regInfo{ 5584 inputs: []inputInfo{ 5585 {1, 2}, // CX 5586 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5587 }, 5588 outputs: []outputInfo{ 5589 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5590 }, 5591 }, 5592 }, 5593 { 5594 name: "SHRW", 5595 argLen: 2, 5596 resultInArg0: true, 5597 clobberFlags: true, 5598 asm: x86.ASHRW, 5599 reg: regInfo{ 5600 inputs: []inputInfo{ 5601 {1, 2}, // CX 5602 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5603 }, 5604 outputs: []outputInfo{ 5605 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5606 }, 5607 }, 5608 }, 5609 { 5610 name: "SHRB", 5611 argLen: 2, 5612 resultInArg0: true, 5613 clobberFlags: true, 5614 asm: x86.ASHRB, 5615 reg: regInfo{ 5616 inputs: []inputInfo{ 5617 {1, 2}, // CX 5618 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5619 }, 5620 outputs: []outputInfo{ 5621 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5622 }, 5623 }, 5624 }, 5625 { 5626 name: "SHRQconst", 5627 auxType: auxInt64, 5628 argLen: 1, 5629 resultInArg0: true, 5630 clobberFlags: true, 5631 asm: x86.ASHRQ, 5632 reg: regInfo{ 5633 inputs: []inputInfo{ 5634 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5635 }, 5636 outputs: []outputInfo{ 5637 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5638 }, 5639 }, 5640 }, 5641 { 5642 name: "SHRLconst", 5643 auxType: auxInt32, 5644 argLen: 1, 5645 resultInArg0: true, 5646 clobberFlags: true, 5647 asm: x86.ASHRL, 5648 reg: regInfo{ 5649 inputs: []inputInfo{ 5650 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5651 }, 5652 outputs: []outputInfo{ 5653 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5654 }, 5655 }, 5656 }, 5657 { 5658 name: "SHRWconst", 5659 auxType: auxInt16, 5660 argLen: 1, 5661 resultInArg0: true, 5662 clobberFlags: true, 5663 asm: x86.ASHRW, 5664 reg: regInfo{ 5665 inputs: []inputInfo{ 5666 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5667 }, 5668 outputs: []outputInfo{ 5669 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5670 }, 5671 }, 5672 }, 5673 { 5674 name: "SHRBconst", 5675 auxType: auxInt8, 5676 argLen: 1, 5677 resultInArg0: true, 5678 clobberFlags: true, 5679 asm: x86.ASHRB, 5680 reg: regInfo{ 5681 inputs: []inputInfo{ 5682 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5683 }, 5684 outputs: []outputInfo{ 5685 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5686 }, 5687 }, 5688 }, 5689 { 5690 name: "SARQ", 5691 argLen: 2, 5692 resultInArg0: true, 5693 clobberFlags: true, 5694 asm: x86.ASARQ, 5695 reg: regInfo{ 5696 inputs: []inputInfo{ 5697 {1, 2}, // CX 5698 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5699 }, 5700 outputs: []outputInfo{ 5701 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5702 }, 5703 }, 5704 }, 5705 { 5706 name: "SARL", 5707 argLen: 2, 5708 resultInArg0: true, 5709 clobberFlags: true, 5710 asm: x86.ASARL, 5711 reg: regInfo{ 5712 inputs: []inputInfo{ 5713 {1, 2}, // CX 5714 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5715 }, 5716 outputs: []outputInfo{ 5717 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5718 }, 5719 }, 5720 }, 5721 { 5722 name: "SARW", 5723 argLen: 2, 5724 resultInArg0: true, 5725 clobberFlags: true, 5726 asm: x86.ASARW, 5727 reg: regInfo{ 5728 inputs: []inputInfo{ 5729 {1, 2}, // CX 5730 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5731 }, 5732 outputs: []outputInfo{ 5733 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5734 }, 5735 }, 5736 }, 5737 { 5738 name: "SARB", 5739 argLen: 2, 5740 resultInArg0: true, 5741 clobberFlags: true, 5742 asm: x86.ASARB, 5743 reg: regInfo{ 5744 inputs: []inputInfo{ 5745 {1, 2}, // CX 5746 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5747 }, 5748 outputs: []outputInfo{ 5749 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5750 }, 5751 }, 5752 }, 5753 { 5754 name: "SARQconst", 5755 auxType: auxInt64, 5756 argLen: 1, 5757 resultInArg0: true, 5758 clobberFlags: true, 5759 asm: x86.ASARQ, 5760 reg: regInfo{ 5761 inputs: []inputInfo{ 5762 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5763 }, 5764 outputs: []outputInfo{ 5765 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5766 }, 5767 }, 5768 }, 5769 { 5770 name: "SARLconst", 5771 auxType: auxInt32, 5772 argLen: 1, 5773 resultInArg0: true, 5774 clobberFlags: true, 5775 asm: x86.ASARL, 5776 reg: regInfo{ 5777 inputs: []inputInfo{ 5778 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5779 }, 5780 outputs: []outputInfo{ 5781 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5782 }, 5783 }, 5784 }, 5785 { 5786 name: "SARWconst", 5787 auxType: auxInt16, 5788 argLen: 1, 5789 resultInArg0: true, 5790 clobberFlags: true, 5791 asm: x86.ASARW, 5792 reg: regInfo{ 5793 inputs: []inputInfo{ 5794 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5795 }, 5796 outputs: []outputInfo{ 5797 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5798 }, 5799 }, 5800 }, 5801 { 5802 name: "SARBconst", 5803 auxType: auxInt8, 5804 argLen: 1, 5805 resultInArg0: true, 5806 clobberFlags: true, 5807 asm: x86.ASARB, 5808 reg: regInfo{ 5809 inputs: []inputInfo{ 5810 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5811 }, 5812 outputs: []outputInfo{ 5813 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5814 }, 5815 }, 5816 }, 5817 { 5818 name: "ROLQconst", 5819 auxType: auxInt64, 5820 argLen: 1, 5821 resultInArg0: true, 5822 clobberFlags: true, 5823 asm: x86.AROLQ, 5824 reg: regInfo{ 5825 inputs: []inputInfo{ 5826 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5827 }, 5828 outputs: []outputInfo{ 5829 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5830 }, 5831 }, 5832 }, 5833 { 5834 name: "ROLLconst", 5835 auxType: auxInt32, 5836 argLen: 1, 5837 resultInArg0: true, 5838 clobberFlags: true, 5839 asm: x86.AROLL, 5840 reg: regInfo{ 5841 inputs: []inputInfo{ 5842 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5843 }, 5844 outputs: []outputInfo{ 5845 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5846 }, 5847 }, 5848 }, 5849 { 5850 name: "ROLWconst", 5851 auxType: auxInt16, 5852 argLen: 1, 5853 resultInArg0: true, 5854 clobberFlags: true, 5855 asm: x86.AROLW, 5856 reg: regInfo{ 5857 inputs: []inputInfo{ 5858 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5859 }, 5860 outputs: []outputInfo{ 5861 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5862 }, 5863 }, 5864 }, 5865 { 5866 name: "ROLBconst", 5867 auxType: auxInt8, 5868 argLen: 1, 5869 resultInArg0: true, 5870 clobberFlags: true, 5871 asm: x86.AROLB, 5872 reg: regInfo{ 5873 inputs: []inputInfo{ 5874 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5875 }, 5876 outputs: []outputInfo{ 5877 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5878 }, 5879 }, 5880 }, 5881 { 5882 name: "NEGQ", 5883 argLen: 1, 5884 resultInArg0: true, 5885 clobberFlags: true, 5886 asm: x86.ANEGQ, 5887 reg: regInfo{ 5888 inputs: []inputInfo{ 5889 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5890 }, 5891 outputs: []outputInfo{ 5892 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5893 }, 5894 }, 5895 }, 5896 { 5897 name: "NEGL", 5898 argLen: 1, 5899 resultInArg0: true, 5900 clobberFlags: true, 5901 asm: x86.ANEGL, 5902 reg: regInfo{ 5903 inputs: []inputInfo{ 5904 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5905 }, 5906 outputs: []outputInfo{ 5907 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5908 }, 5909 }, 5910 }, 5911 { 5912 name: "NOTQ", 5913 argLen: 1, 5914 resultInArg0: true, 5915 clobberFlags: true, 5916 asm: x86.ANOTQ, 5917 reg: regInfo{ 5918 inputs: []inputInfo{ 5919 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5920 }, 5921 outputs: []outputInfo{ 5922 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5923 }, 5924 }, 5925 }, 5926 { 5927 name: "NOTL", 5928 argLen: 1, 5929 resultInArg0: true, 5930 clobberFlags: true, 5931 asm: x86.ANOTL, 5932 reg: regInfo{ 5933 inputs: []inputInfo{ 5934 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5935 }, 5936 outputs: []outputInfo{ 5937 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5938 }, 5939 }, 5940 }, 5941 { 5942 name: "BSFQ", 5943 argLen: 1, 5944 asm: x86.ABSFQ, 5945 reg: regInfo{ 5946 inputs: []inputInfo{ 5947 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5948 }, 5949 outputs: []outputInfo{ 5950 {1, 0}, 5951 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5952 }, 5953 }, 5954 }, 5955 { 5956 name: "BSFL", 5957 argLen: 1, 5958 asm: x86.ABSFL, 5959 reg: regInfo{ 5960 inputs: []inputInfo{ 5961 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5962 }, 5963 outputs: []outputInfo{ 5964 {1, 0}, 5965 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5966 }, 5967 }, 5968 }, 5969 { 5970 name: "CMOVQEQ", 5971 argLen: 3, 5972 resultInArg0: true, 5973 asm: x86.ACMOVQEQ, 5974 reg: regInfo{ 5975 inputs: []inputInfo{ 5976 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5977 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5978 }, 5979 outputs: []outputInfo{ 5980 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5981 }, 5982 }, 5983 }, 5984 { 5985 name: "CMOVLEQ", 5986 argLen: 3, 5987 resultInArg0: true, 5988 asm: x86.ACMOVLEQ, 5989 reg: regInfo{ 5990 inputs: []inputInfo{ 5991 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5992 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5993 }, 5994 outputs: []outputInfo{ 5995 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5996 }, 5997 }, 5998 }, 5999 { 6000 name: "BSWAPQ", 6001 argLen: 1, 6002 resultInArg0: true, 6003 clobberFlags: true, 6004 asm: x86.ABSWAPQ, 6005 reg: regInfo{ 6006 inputs: []inputInfo{ 6007 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6008 }, 6009 outputs: []outputInfo{ 6010 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6011 }, 6012 }, 6013 }, 6014 { 6015 name: "BSWAPL", 6016 argLen: 1, 6017 resultInArg0: true, 6018 clobberFlags: true, 6019 asm: x86.ABSWAPL, 6020 reg: regInfo{ 6021 inputs: []inputInfo{ 6022 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6023 }, 6024 outputs: []outputInfo{ 6025 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6026 }, 6027 }, 6028 }, 6029 { 6030 name: "SQRTSD", 6031 argLen: 1, 6032 asm: x86.ASQRTSD, 6033 reg: regInfo{ 6034 inputs: []inputInfo{ 6035 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6036 }, 6037 outputs: []outputInfo{ 6038 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6039 }, 6040 }, 6041 }, 6042 { 6043 name: "SBBQcarrymask", 6044 argLen: 1, 6045 asm: x86.ASBBQ, 6046 reg: regInfo{ 6047 outputs: []outputInfo{ 6048 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6049 }, 6050 }, 6051 }, 6052 { 6053 name: "SBBLcarrymask", 6054 argLen: 1, 6055 asm: x86.ASBBL, 6056 reg: regInfo{ 6057 outputs: []outputInfo{ 6058 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6059 }, 6060 }, 6061 }, 6062 { 6063 name: "SETEQ", 6064 argLen: 1, 6065 asm: x86.ASETEQ, 6066 reg: regInfo{ 6067 outputs: []outputInfo{ 6068 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6069 }, 6070 }, 6071 }, 6072 { 6073 name: "SETNE", 6074 argLen: 1, 6075 asm: x86.ASETNE, 6076 reg: regInfo{ 6077 outputs: []outputInfo{ 6078 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6079 }, 6080 }, 6081 }, 6082 { 6083 name: "SETL", 6084 argLen: 1, 6085 asm: x86.ASETLT, 6086 reg: regInfo{ 6087 outputs: []outputInfo{ 6088 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6089 }, 6090 }, 6091 }, 6092 { 6093 name: "SETLE", 6094 argLen: 1, 6095 asm: x86.ASETLE, 6096 reg: regInfo{ 6097 outputs: []outputInfo{ 6098 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6099 }, 6100 }, 6101 }, 6102 { 6103 name: "SETG", 6104 argLen: 1, 6105 asm: x86.ASETGT, 6106 reg: regInfo{ 6107 outputs: []outputInfo{ 6108 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6109 }, 6110 }, 6111 }, 6112 { 6113 name: "SETGE", 6114 argLen: 1, 6115 asm: x86.ASETGE, 6116 reg: regInfo{ 6117 outputs: []outputInfo{ 6118 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6119 }, 6120 }, 6121 }, 6122 { 6123 name: "SETB", 6124 argLen: 1, 6125 asm: x86.ASETCS, 6126 reg: regInfo{ 6127 outputs: []outputInfo{ 6128 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6129 }, 6130 }, 6131 }, 6132 { 6133 name: "SETBE", 6134 argLen: 1, 6135 asm: x86.ASETLS, 6136 reg: regInfo{ 6137 outputs: []outputInfo{ 6138 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6139 }, 6140 }, 6141 }, 6142 { 6143 name: "SETA", 6144 argLen: 1, 6145 asm: x86.ASETHI, 6146 reg: regInfo{ 6147 outputs: []outputInfo{ 6148 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6149 }, 6150 }, 6151 }, 6152 { 6153 name: "SETAE", 6154 argLen: 1, 6155 asm: x86.ASETCC, 6156 reg: regInfo{ 6157 outputs: []outputInfo{ 6158 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6159 }, 6160 }, 6161 }, 6162 { 6163 name: "SETEQF", 6164 argLen: 1, 6165 clobberFlags: true, 6166 asm: x86.ASETEQ, 6167 reg: regInfo{ 6168 clobbers: 1, // AX 6169 outputs: []outputInfo{ 6170 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6171 }, 6172 }, 6173 }, 6174 { 6175 name: "SETNEF", 6176 argLen: 1, 6177 clobberFlags: true, 6178 asm: x86.ASETNE, 6179 reg: regInfo{ 6180 clobbers: 1, // AX 6181 outputs: []outputInfo{ 6182 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6183 }, 6184 }, 6185 }, 6186 { 6187 name: "SETORD", 6188 argLen: 1, 6189 asm: x86.ASETPC, 6190 reg: regInfo{ 6191 outputs: []outputInfo{ 6192 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6193 }, 6194 }, 6195 }, 6196 { 6197 name: "SETNAN", 6198 argLen: 1, 6199 asm: x86.ASETPS, 6200 reg: regInfo{ 6201 outputs: []outputInfo{ 6202 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6203 }, 6204 }, 6205 }, 6206 { 6207 name: "SETGF", 6208 argLen: 1, 6209 asm: x86.ASETHI, 6210 reg: regInfo{ 6211 outputs: []outputInfo{ 6212 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6213 }, 6214 }, 6215 }, 6216 { 6217 name: "SETGEF", 6218 argLen: 1, 6219 asm: x86.ASETCC, 6220 reg: regInfo{ 6221 outputs: []outputInfo{ 6222 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6223 }, 6224 }, 6225 }, 6226 { 6227 name: "MOVBQSX", 6228 argLen: 1, 6229 asm: x86.AMOVBQSX, 6230 reg: regInfo{ 6231 inputs: []inputInfo{ 6232 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6233 }, 6234 outputs: []outputInfo{ 6235 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6236 }, 6237 }, 6238 }, 6239 { 6240 name: "MOVBQZX", 6241 argLen: 1, 6242 asm: x86.AMOVBLZX, 6243 reg: regInfo{ 6244 inputs: []inputInfo{ 6245 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6246 }, 6247 outputs: []outputInfo{ 6248 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6249 }, 6250 }, 6251 }, 6252 { 6253 name: "MOVWQSX", 6254 argLen: 1, 6255 asm: x86.AMOVWQSX, 6256 reg: regInfo{ 6257 inputs: []inputInfo{ 6258 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6259 }, 6260 outputs: []outputInfo{ 6261 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6262 }, 6263 }, 6264 }, 6265 { 6266 name: "MOVWQZX", 6267 argLen: 1, 6268 asm: x86.AMOVWLZX, 6269 reg: regInfo{ 6270 inputs: []inputInfo{ 6271 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6272 }, 6273 outputs: []outputInfo{ 6274 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6275 }, 6276 }, 6277 }, 6278 { 6279 name: "MOVLQSX", 6280 argLen: 1, 6281 asm: x86.AMOVLQSX, 6282 reg: regInfo{ 6283 inputs: []inputInfo{ 6284 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6285 }, 6286 outputs: []outputInfo{ 6287 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6288 }, 6289 }, 6290 }, 6291 { 6292 name: "MOVLQZX", 6293 argLen: 1, 6294 asm: x86.AMOVL, 6295 reg: regInfo{ 6296 inputs: []inputInfo{ 6297 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6298 }, 6299 outputs: []outputInfo{ 6300 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6301 }, 6302 }, 6303 }, 6304 { 6305 name: "MOVLconst", 6306 auxType: auxInt32, 6307 argLen: 0, 6308 rematerializeable: true, 6309 asm: x86.AMOVL, 6310 reg: regInfo{ 6311 outputs: []outputInfo{ 6312 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6313 }, 6314 }, 6315 }, 6316 { 6317 name: "MOVQconst", 6318 auxType: auxInt64, 6319 argLen: 0, 6320 rematerializeable: true, 6321 asm: x86.AMOVQ, 6322 reg: regInfo{ 6323 outputs: []outputInfo{ 6324 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6325 }, 6326 }, 6327 }, 6328 { 6329 name: "CVTTSD2SL", 6330 argLen: 1, 6331 asm: x86.ACVTTSD2SL, 6332 reg: regInfo{ 6333 inputs: []inputInfo{ 6334 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6335 }, 6336 outputs: []outputInfo{ 6337 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6338 }, 6339 }, 6340 }, 6341 { 6342 name: "CVTTSD2SQ", 6343 argLen: 1, 6344 asm: x86.ACVTTSD2SQ, 6345 reg: regInfo{ 6346 inputs: []inputInfo{ 6347 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6348 }, 6349 outputs: []outputInfo{ 6350 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6351 }, 6352 }, 6353 }, 6354 { 6355 name: "CVTTSS2SL", 6356 argLen: 1, 6357 asm: x86.ACVTTSS2SL, 6358 reg: regInfo{ 6359 inputs: []inputInfo{ 6360 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6361 }, 6362 outputs: []outputInfo{ 6363 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6364 }, 6365 }, 6366 }, 6367 { 6368 name: "CVTTSS2SQ", 6369 argLen: 1, 6370 asm: x86.ACVTTSS2SQ, 6371 reg: regInfo{ 6372 inputs: []inputInfo{ 6373 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6374 }, 6375 outputs: []outputInfo{ 6376 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6377 }, 6378 }, 6379 }, 6380 { 6381 name: "CVTSL2SS", 6382 argLen: 1, 6383 asm: x86.ACVTSL2SS, 6384 reg: regInfo{ 6385 inputs: []inputInfo{ 6386 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6387 }, 6388 outputs: []outputInfo{ 6389 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6390 }, 6391 }, 6392 }, 6393 { 6394 name: "CVTSL2SD", 6395 argLen: 1, 6396 asm: x86.ACVTSL2SD, 6397 reg: regInfo{ 6398 inputs: []inputInfo{ 6399 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6400 }, 6401 outputs: []outputInfo{ 6402 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6403 }, 6404 }, 6405 }, 6406 { 6407 name: "CVTSQ2SS", 6408 argLen: 1, 6409 asm: x86.ACVTSQ2SS, 6410 reg: regInfo{ 6411 inputs: []inputInfo{ 6412 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6413 }, 6414 outputs: []outputInfo{ 6415 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6416 }, 6417 }, 6418 }, 6419 { 6420 name: "CVTSQ2SD", 6421 argLen: 1, 6422 asm: x86.ACVTSQ2SD, 6423 reg: regInfo{ 6424 inputs: []inputInfo{ 6425 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6426 }, 6427 outputs: []outputInfo{ 6428 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6429 }, 6430 }, 6431 }, 6432 { 6433 name: "CVTSD2SS", 6434 argLen: 1, 6435 asm: x86.ACVTSD2SS, 6436 reg: regInfo{ 6437 inputs: []inputInfo{ 6438 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6439 }, 6440 outputs: []outputInfo{ 6441 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6442 }, 6443 }, 6444 }, 6445 { 6446 name: "CVTSS2SD", 6447 argLen: 1, 6448 asm: x86.ACVTSS2SD, 6449 reg: regInfo{ 6450 inputs: []inputInfo{ 6451 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6452 }, 6453 outputs: []outputInfo{ 6454 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6455 }, 6456 }, 6457 }, 6458 { 6459 name: "PXOR", 6460 argLen: 2, 6461 commutative: true, 6462 resultInArg0: true, 6463 asm: x86.APXOR, 6464 reg: regInfo{ 6465 inputs: []inputInfo{ 6466 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6467 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6468 }, 6469 outputs: []outputInfo{ 6470 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6471 }, 6472 }, 6473 }, 6474 { 6475 name: "LEAQ", 6476 auxType: auxSymOff, 6477 argLen: 1, 6478 rematerializeable: true, 6479 asm: x86.ALEAQ, 6480 reg: regInfo{ 6481 inputs: []inputInfo{ 6482 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6483 }, 6484 outputs: []outputInfo{ 6485 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6486 }, 6487 }, 6488 }, 6489 { 6490 name: "LEAQ1", 6491 auxType: auxSymOff, 6492 argLen: 2, 6493 reg: regInfo{ 6494 inputs: []inputInfo{ 6495 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6496 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6497 }, 6498 outputs: []outputInfo{ 6499 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6500 }, 6501 }, 6502 }, 6503 { 6504 name: "LEAQ2", 6505 auxType: auxSymOff, 6506 argLen: 2, 6507 reg: regInfo{ 6508 inputs: []inputInfo{ 6509 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6510 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6511 }, 6512 outputs: []outputInfo{ 6513 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6514 }, 6515 }, 6516 }, 6517 { 6518 name: "LEAQ4", 6519 auxType: auxSymOff, 6520 argLen: 2, 6521 reg: regInfo{ 6522 inputs: []inputInfo{ 6523 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6524 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6525 }, 6526 outputs: []outputInfo{ 6527 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6528 }, 6529 }, 6530 }, 6531 { 6532 name: "LEAQ8", 6533 auxType: auxSymOff, 6534 argLen: 2, 6535 reg: regInfo{ 6536 inputs: []inputInfo{ 6537 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6538 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6539 }, 6540 outputs: []outputInfo{ 6541 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6542 }, 6543 }, 6544 }, 6545 { 6546 name: "LEAL", 6547 auxType: auxSymOff, 6548 argLen: 1, 6549 rematerializeable: true, 6550 asm: x86.ALEAL, 6551 reg: regInfo{ 6552 inputs: []inputInfo{ 6553 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6554 }, 6555 outputs: []outputInfo{ 6556 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6557 }, 6558 }, 6559 }, 6560 { 6561 name: "MOVBload", 6562 auxType: auxSymOff, 6563 argLen: 2, 6564 faultOnNilArg0: true, 6565 asm: x86.AMOVBLZX, 6566 reg: regInfo{ 6567 inputs: []inputInfo{ 6568 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6569 }, 6570 outputs: []outputInfo{ 6571 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6572 }, 6573 }, 6574 }, 6575 { 6576 name: "MOVBQSXload", 6577 auxType: auxSymOff, 6578 argLen: 2, 6579 faultOnNilArg0: true, 6580 asm: x86.AMOVBQSX, 6581 reg: regInfo{ 6582 inputs: []inputInfo{ 6583 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6584 }, 6585 outputs: []outputInfo{ 6586 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6587 }, 6588 }, 6589 }, 6590 { 6591 name: "MOVWload", 6592 auxType: auxSymOff, 6593 argLen: 2, 6594 faultOnNilArg0: true, 6595 asm: x86.AMOVWLZX, 6596 reg: regInfo{ 6597 inputs: []inputInfo{ 6598 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6599 }, 6600 outputs: []outputInfo{ 6601 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6602 }, 6603 }, 6604 }, 6605 { 6606 name: "MOVWQSXload", 6607 auxType: auxSymOff, 6608 argLen: 2, 6609 faultOnNilArg0: true, 6610 asm: x86.AMOVWQSX, 6611 reg: regInfo{ 6612 inputs: []inputInfo{ 6613 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6614 }, 6615 outputs: []outputInfo{ 6616 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6617 }, 6618 }, 6619 }, 6620 { 6621 name: "MOVLload", 6622 auxType: auxSymOff, 6623 argLen: 2, 6624 faultOnNilArg0: true, 6625 asm: x86.AMOVL, 6626 reg: regInfo{ 6627 inputs: []inputInfo{ 6628 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6629 }, 6630 outputs: []outputInfo{ 6631 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6632 }, 6633 }, 6634 }, 6635 { 6636 name: "MOVLQSXload", 6637 auxType: auxSymOff, 6638 argLen: 2, 6639 faultOnNilArg0: true, 6640 asm: x86.AMOVLQSX, 6641 reg: regInfo{ 6642 inputs: []inputInfo{ 6643 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6644 }, 6645 outputs: []outputInfo{ 6646 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6647 }, 6648 }, 6649 }, 6650 { 6651 name: "MOVQload", 6652 auxType: auxSymOff, 6653 argLen: 2, 6654 faultOnNilArg0: true, 6655 asm: x86.AMOVQ, 6656 reg: regInfo{ 6657 inputs: []inputInfo{ 6658 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6659 }, 6660 outputs: []outputInfo{ 6661 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6662 }, 6663 }, 6664 }, 6665 { 6666 name: "MOVBstore", 6667 auxType: auxSymOff, 6668 argLen: 3, 6669 faultOnNilArg0: true, 6670 asm: x86.AMOVB, 6671 reg: regInfo{ 6672 inputs: []inputInfo{ 6673 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6674 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6675 }, 6676 }, 6677 }, 6678 { 6679 name: "MOVWstore", 6680 auxType: auxSymOff, 6681 argLen: 3, 6682 faultOnNilArg0: true, 6683 asm: x86.AMOVW, 6684 reg: regInfo{ 6685 inputs: []inputInfo{ 6686 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6687 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6688 }, 6689 }, 6690 }, 6691 { 6692 name: "MOVLstore", 6693 auxType: auxSymOff, 6694 argLen: 3, 6695 faultOnNilArg0: true, 6696 asm: x86.AMOVL, 6697 reg: regInfo{ 6698 inputs: []inputInfo{ 6699 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6700 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6701 }, 6702 }, 6703 }, 6704 { 6705 name: "MOVQstore", 6706 auxType: auxSymOff, 6707 argLen: 3, 6708 faultOnNilArg0: true, 6709 asm: x86.AMOVQ, 6710 reg: regInfo{ 6711 inputs: []inputInfo{ 6712 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6713 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6714 }, 6715 }, 6716 }, 6717 { 6718 name: "MOVOload", 6719 auxType: auxSymOff, 6720 argLen: 2, 6721 faultOnNilArg0: true, 6722 asm: x86.AMOVUPS, 6723 reg: regInfo{ 6724 inputs: []inputInfo{ 6725 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6726 }, 6727 outputs: []outputInfo{ 6728 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6729 }, 6730 }, 6731 }, 6732 { 6733 name: "MOVOstore", 6734 auxType: auxSymOff, 6735 argLen: 3, 6736 faultOnNilArg0: true, 6737 asm: x86.AMOVUPS, 6738 reg: regInfo{ 6739 inputs: []inputInfo{ 6740 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6741 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6742 }, 6743 }, 6744 }, 6745 { 6746 name: "MOVBloadidx1", 6747 auxType: auxSymOff, 6748 argLen: 3, 6749 asm: x86.AMOVBLZX, 6750 reg: regInfo{ 6751 inputs: []inputInfo{ 6752 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6753 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6754 }, 6755 outputs: []outputInfo{ 6756 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6757 }, 6758 }, 6759 }, 6760 { 6761 name: "MOVWloadidx1", 6762 auxType: auxSymOff, 6763 argLen: 3, 6764 asm: x86.AMOVWLZX, 6765 reg: regInfo{ 6766 inputs: []inputInfo{ 6767 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6768 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6769 }, 6770 outputs: []outputInfo{ 6771 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6772 }, 6773 }, 6774 }, 6775 { 6776 name: "MOVWloadidx2", 6777 auxType: auxSymOff, 6778 argLen: 3, 6779 asm: x86.AMOVWLZX, 6780 reg: regInfo{ 6781 inputs: []inputInfo{ 6782 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6783 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6784 }, 6785 outputs: []outputInfo{ 6786 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6787 }, 6788 }, 6789 }, 6790 { 6791 name: "MOVLloadidx1", 6792 auxType: auxSymOff, 6793 argLen: 3, 6794 asm: x86.AMOVL, 6795 reg: regInfo{ 6796 inputs: []inputInfo{ 6797 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6798 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6799 }, 6800 outputs: []outputInfo{ 6801 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6802 }, 6803 }, 6804 }, 6805 { 6806 name: "MOVLloadidx4", 6807 auxType: auxSymOff, 6808 argLen: 3, 6809 asm: x86.AMOVL, 6810 reg: regInfo{ 6811 inputs: []inputInfo{ 6812 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6813 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6814 }, 6815 outputs: []outputInfo{ 6816 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6817 }, 6818 }, 6819 }, 6820 { 6821 name: "MOVQloadidx1", 6822 auxType: auxSymOff, 6823 argLen: 3, 6824 asm: x86.AMOVQ, 6825 reg: regInfo{ 6826 inputs: []inputInfo{ 6827 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6828 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6829 }, 6830 outputs: []outputInfo{ 6831 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6832 }, 6833 }, 6834 }, 6835 { 6836 name: "MOVQloadidx8", 6837 auxType: auxSymOff, 6838 argLen: 3, 6839 asm: x86.AMOVQ, 6840 reg: regInfo{ 6841 inputs: []inputInfo{ 6842 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6843 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6844 }, 6845 outputs: []outputInfo{ 6846 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6847 }, 6848 }, 6849 }, 6850 { 6851 name: "MOVBstoreidx1", 6852 auxType: auxSymOff, 6853 argLen: 4, 6854 asm: x86.AMOVB, 6855 reg: regInfo{ 6856 inputs: []inputInfo{ 6857 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6858 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6859 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6860 }, 6861 }, 6862 }, 6863 { 6864 name: "MOVWstoreidx1", 6865 auxType: auxSymOff, 6866 argLen: 4, 6867 asm: x86.AMOVW, 6868 reg: regInfo{ 6869 inputs: []inputInfo{ 6870 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6871 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6872 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6873 }, 6874 }, 6875 }, 6876 { 6877 name: "MOVWstoreidx2", 6878 auxType: auxSymOff, 6879 argLen: 4, 6880 asm: x86.AMOVW, 6881 reg: regInfo{ 6882 inputs: []inputInfo{ 6883 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6884 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6885 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6886 }, 6887 }, 6888 }, 6889 { 6890 name: "MOVLstoreidx1", 6891 auxType: auxSymOff, 6892 argLen: 4, 6893 asm: x86.AMOVL, 6894 reg: regInfo{ 6895 inputs: []inputInfo{ 6896 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6897 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6898 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6899 }, 6900 }, 6901 }, 6902 { 6903 name: "MOVLstoreidx4", 6904 auxType: auxSymOff, 6905 argLen: 4, 6906 asm: x86.AMOVL, 6907 reg: regInfo{ 6908 inputs: []inputInfo{ 6909 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6910 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6911 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6912 }, 6913 }, 6914 }, 6915 { 6916 name: "MOVQstoreidx1", 6917 auxType: auxSymOff, 6918 argLen: 4, 6919 asm: x86.AMOVQ, 6920 reg: regInfo{ 6921 inputs: []inputInfo{ 6922 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6923 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6924 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6925 }, 6926 }, 6927 }, 6928 { 6929 name: "MOVQstoreidx8", 6930 auxType: auxSymOff, 6931 argLen: 4, 6932 asm: x86.AMOVQ, 6933 reg: regInfo{ 6934 inputs: []inputInfo{ 6935 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6936 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6937 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6938 }, 6939 }, 6940 }, 6941 { 6942 name: "MOVBstoreconst", 6943 auxType: auxSymValAndOff, 6944 argLen: 2, 6945 faultOnNilArg0: true, 6946 asm: x86.AMOVB, 6947 reg: regInfo{ 6948 inputs: []inputInfo{ 6949 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6950 }, 6951 }, 6952 }, 6953 { 6954 name: "MOVWstoreconst", 6955 auxType: auxSymValAndOff, 6956 argLen: 2, 6957 faultOnNilArg0: true, 6958 asm: x86.AMOVW, 6959 reg: regInfo{ 6960 inputs: []inputInfo{ 6961 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6962 }, 6963 }, 6964 }, 6965 { 6966 name: "MOVLstoreconst", 6967 auxType: auxSymValAndOff, 6968 argLen: 2, 6969 faultOnNilArg0: true, 6970 asm: x86.AMOVL, 6971 reg: regInfo{ 6972 inputs: []inputInfo{ 6973 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6974 }, 6975 }, 6976 }, 6977 { 6978 name: "MOVQstoreconst", 6979 auxType: auxSymValAndOff, 6980 argLen: 2, 6981 faultOnNilArg0: true, 6982 asm: x86.AMOVQ, 6983 reg: regInfo{ 6984 inputs: []inputInfo{ 6985 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6986 }, 6987 }, 6988 }, 6989 { 6990 name: "MOVBstoreconstidx1", 6991 auxType: auxSymValAndOff, 6992 argLen: 3, 6993 asm: x86.AMOVB, 6994 reg: regInfo{ 6995 inputs: []inputInfo{ 6996 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6997 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6998 }, 6999 }, 7000 }, 7001 { 7002 name: "MOVWstoreconstidx1", 7003 auxType: auxSymValAndOff, 7004 argLen: 3, 7005 asm: x86.AMOVW, 7006 reg: regInfo{ 7007 inputs: []inputInfo{ 7008 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7009 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7010 }, 7011 }, 7012 }, 7013 { 7014 name: "MOVWstoreconstidx2", 7015 auxType: auxSymValAndOff, 7016 argLen: 3, 7017 asm: x86.AMOVW, 7018 reg: regInfo{ 7019 inputs: []inputInfo{ 7020 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7021 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7022 }, 7023 }, 7024 }, 7025 { 7026 name: "MOVLstoreconstidx1", 7027 auxType: auxSymValAndOff, 7028 argLen: 3, 7029 asm: x86.AMOVL, 7030 reg: regInfo{ 7031 inputs: []inputInfo{ 7032 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7033 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7034 }, 7035 }, 7036 }, 7037 { 7038 name: "MOVLstoreconstidx4", 7039 auxType: auxSymValAndOff, 7040 argLen: 3, 7041 asm: x86.AMOVL, 7042 reg: regInfo{ 7043 inputs: []inputInfo{ 7044 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7045 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7046 }, 7047 }, 7048 }, 7049 { 7050 name: "MOVQstoreconstidx1", 7051 auxType: auxSymValAndOff, 7052 argLen: 3, 7053 asm: x86.AMOVQ, 7054 reg: regInfo{ 7055 inputs: []inputInfo{ 7056 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7057 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7058 }, 7059 }, 7060 }, 7061 { 7062 name: "MOVQstoreconstidx8", 7063 auxType: auxSymValAndOff, 7064 argLen: 3, 7065 asm: x86.AMOVQ, 7066 reg: regInfo{ 7067 inputs: []inputInfo{ 7068 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7069 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7070 }, 7071 }, 7072 }, 7073 { 7074 name: "DUFFZERO", 7075 auxType: auxInt64, 7076 argLen: 3, 7077 clobberFlags: true, 7078 faultOnNilArg0: true, 7079 reg: regInfo{ 7080 inputs: []inputInfo{ 7081 {0, 128}, // DI 7082 {1, 65536}, // X0 7083 }, 7084 clobbers: 128, // DI 7085 }, 7086 }, 7087 { 7088 name: "MOVOconst", 7089 auxType: auxInt128, 7090 argLen: 0, 7091 rematerializeable: true, 7092 reg: regInfo{ 7093 outputs: []outputInfo{ 7094 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7095 }, 7096 }, 7097 }, 7098 { 7099 name: "REPSTOSQ", 7100 argLen: 4, 7101 faultOnNilArg0: true, 7102 reg: regInfo{ 7103 inputs: []inputInfo{ 7104 {0, 128}, // DI 7105 {1, 2}, // CX 7106 {2, 1}, // AX 7107 }, 7108 clobbers: 130, // CX DI 7109 }, 7110 }, 7111 { 7112 name: "CALLstatic", 7113 auxType: auxSymOff, 7114 argLen: 1, 7115 clobberFlags: true, 7116 call: true, 7117 reg: regInfo{ 7118 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7119 }, 7120 }, 7121 { 7122 name: "CALLclosure", 7123 auxType: auxInt64, 7124 argLen: 3, 7125 clobberFlags: true, 7126 call: true, 7127 reg: regInfo{ 7128 inputs: []inputInfo{ 7129 {1, 4}, // DX 7130 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7131 }, 7132 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7133 }, 7134 }, 7135 { 7136 name: "CALLdefer", 7137 auxType: auxInt64, 7138 argLen: 1, 7139 clobberFlags: true, 7140 call: true, 7141 reg: regInfo{ 7142 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7143 }, 7144 }, 7145 { 7146 name: "CALLgo", 7147 auxType: auxInt64, 7148 argLen: 1, 7149 clobberFlags: true, 7150 call: true, 7151 reg: regInfo{ 7152 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7153 }, 7154 }, 7155 { 7156 name: "CALLinter", 7157 auxType: auxInt64, 7158 argLen: 2, 7159 clobberFlags: true, 7160 call: true, 7161 reg: regInfo{ 7162 inputs: []inputInfo{ 7163 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7164 }, 7165 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7166 }, 7167 }, 7168 { 7169 name: "DUFFCOPY", 7170 auxType: auxInt64, 7171 argLen: 3, 7172 clobberFlags: true, 7173 faultOnNilArg0: true, 7174 faultOnNilArg1: true, 7175 reg: regInfo{ 7176 inputs: []inputInfo{ 7177 {0, 128}, // DI 7178 {1, 64}, // SI 7179 }, 7180 clobbers: 65728, // SI DI X0 7181 }, 7182 }, 7183 { 7184 name: "REPMOVSQ", 7185 argLen: 4, 7186 faultOnNilArg0: true, 7187 faultOnNilArg1: true, 7188 reg: regInfo{ 7189 inputs: []inputInfo{ 7190 {0, 128}, // DI 7191 {1, 64}, // SI 7192 {2, 2}, // CX 7193 }, 7194 clobbers: 194, // CX SI DI 7195 }, 7196 }, 7197 { 7198 name: "InvertFlags", 7199 argLen: 1, 7200 reg: regInfo{}, 7201 }, 7202 { 7203 name: "LoweredGetG", 7204 argLen: 1, 7205 reg: regInfo{ 7206 outputs: []outputInfo{ 7207 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7208 }, 7209 }, 7210 }, 7211 { 7212 name: "LoweredGetClosurePtr", 7213 argLen: 0, 7214 reg: regInfo{ 7215 outputs: []outputInfo{ 7216 {0, 4}, // DX 7217 }, 7218 }, 7219 }, 7220 { 7221 name: "LoweredNilCheck", 7222 argLen: 2, 7223 clobberFlags: true, 7224 nilCheck: true, 7225 faultOnNilArg0: true, 7226 reg: regInfo{ 7227 inputs: []inputInfo{ 7228 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7229 }, 7230 }, 7231 }, 7232 { 7233 name: "MOVQconvert", 7234 argLen: 2, 7235 asm: x86.AMOVQ, 7236 reg: regInfo{ 7237 inputs: []inputInfo{ 7238 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7239 }, 7240 outputs: []outputInfo{ 7241 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7242 }, 7243 }, 7244 }, 7245 { 7246 name: "MOVLconvert", 7247 argLen: 2, 7248 asm: x86.AMOVL, 7249 reg: regInfo{ 7250 inputs: []inputInfo{ 7251 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7252 }, 7253 outputs: []outputInfo{ 7254 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7255 }, 7256 }, 7257 }, 7258 { 7259 name: "FlagEQ", 7260 argLen: 0, 7261 reg: regInfo{}, 7262 }, 7263 { 7264 name: "FlagLT_ULT", 7265 argLen: 0, 7266 reg: regInfo{}, 7267 }, 7268 { 7269 name: "FlagLT_UGT", 7270 argLen: 0, 7271 reg: regInfo{}, 7272 }, 7273 { 7274 name: "FlagGT_UGT", 7275 argLen: 0, 7276 reg: regInfo{}, 7277 }, 7278 { 7279 name: "FlagGT_ULT", 7280 argLen: 0, 7281 reg: regInfo{}, 7282 }, 7283 { 7284 name: "MOVLatomicload", 7285 auxType: auxSymOff, 7286 argLen: 2, 7287 faultOnNilArg0: true, 7288 asm: x86.AMOVL, 7289 reg: regInfo{ 7290 inputs: []inputInfo{ 7291 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7292 }, 7293 outputs: []outputInfo{ 7294 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7295 }, 7296 }, 7297 }, 7298 { 7299 name: "MOVQatomicload", 7300 auxType: auxSymOff, 7301 argLen: 2, 7302 faultOnNilArg0: true, 7303 asm: x86.AMOVQ, 7304 reg: regInfo{ 7305 inputs: []inputInfo{ 7306 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7307 }, 7308 outputs: []outputInfo{ 7309 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7310 }, 7311 }, 7312 }, 7313 { 7314 name: "XCHGL", 7315 auxType: auxSymOff, 7316 argLen: 3, 7317 resultInArg0: true, 7318 faultOnNilArg1: true, 7319 asm: x86.AXCHGL, 7320 reg: regInfo{ 7321 inputs: []inputInfo{ 7322 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7323 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7324 }, 7325 outputs: []outputInfo{ 7326 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7327 }, 7328 }, 7329 }, 7330 { 7331 name: "XCHGQ", 7332 auxType: auxSymOff, 7333 argLen: 3, 7334 resultInArg0: true, 7335 faultOnNilArg1: true, 7336 asm: x86.AXCHGQ, 7337 reg: regInfo{ 7338 inputs: []inputInfo{ 7339 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7340 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7341 }, 7342 outputs: []outputInfo{ 7343 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7344 }, 7345 }, 7346 }, 7347 { 7348 name: "XADDLlock", 7349 auxType: auxSymOff, 7350 argLen: 3, 7351 resultInArg0: true, 7352 clobberFlags: true, 7353 faultOnNilArg1: true, 7354 asm: x86.AXADDL, 7355 reg: regInfo{ 7356 inputs: []inputInfo{ 7357 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7358 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7359 }, 7360 outputs: []outputInfo{ 7361 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7362 }, 7363 }, 7364 }, 7365 { 7366 name: "XADDQlock", 7367 auxType: auxSymOff, 7368 argLen: 3, 7369 resultInArg0: true, 7370 clobberFlags: true, 7371 faultOnNilArg1: true, 7372 asm: x86.AXADDQ, 7373 reg: regInfo{ 7374 inputs: []inputInfo{ 7375 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7376 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7377 }, 7378 outputs: []outputInfo{ 7379 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7380 }, 7381 }, 7382 }, 7383 { 7384 name: "AddTupleFirst32", 7385 argLen: 2, 7386 reg: regInfo{}, 7387 }, 7388 { 7389 name: "AddTupleFirst64", 7390 argLen: 2, 7391 reg: regInfo{}, 7392 }, 7393 { 7394 name: "CMPXCHGLlock", 7395 auxType: auxSymOff, 7396 argLen: 4, 7397 clobberFlags: true, 7398 faultOnNilArg0: true, 7399 asm: x86.ACMPXCHGL, 7400 reg: regInfo{ 7401 inputs: []inputInfo{ 7402 {1, 1}, // AX 7403 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7404 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7405 }, 7406 clobbers: 1, // AX 7407 outputs: []outputInfo{ 7408 {1, 0}, 7409 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7410 }, 7411 }, 7412 }, 7413 { 7414 name: "CMPXCHGQlock", 7415 auxType: auxSymOff, 7416 argLen: 4, 7417 clobberFlags: true, 7418 faultOnNilArg0: true, 7419 asm: x86.ACMPXCHGQ, 7420 reg: regInfo{ 7421 inputs: []inputInfo{ 7422 {1, 1}, // AX 7423 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7424 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7425 }, 7426 clobbers: 1, // AX 7427 outputs: []outputInfo{ 7428 {1, 0}, 7429 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7430 }, 7431 }, 7432 }, 7433 { 7434 name: "ANDBlock", 7435 auxType: auxSymOff, 7436 argLen: 3, 7437 clobberFlags: true, 7438 faultOnNilArg0: true, 7439 asm: x86.AANDB, 7440 reg: regInfo{ 7441 inputs: []inputInfo{ 7442 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7443 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7444 }, 7445 }, 7446 }, 7447 { 7448 name: "ORBlock", 7449 auxType: auxSymOff, 7450 argLen: 3, 7451 clobberFlags: true, 7452 faultOnNilArg0: true, 7453 asm: x86.AORB, 7454 reg: regInfo{ 7455 inputs: []inputInfo{ 7456 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7457 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7458 }, 7459 }, 7460 }, 7461 7462 { 7463 name: "ADD", 7464 argLen: 2, 7465 commutative: true, 7466 asm: arm.AADD, 7467 reg: regInfo{ 7468 inputs: []inputInfo{ 7469 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7470 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7471 }, 7472 outputs: []outputInfo{ 7473 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7474 }, 7475 }, 7476 }, 7477 { 7478 name: "ADDconst", 7479 auxType: auxInt32, 7480 argLen: 1, 7481 asm: arm.AADD, 7482 reg: regInfo{ 7483 inputs: []inputInfo{ 7484 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 7485 }, 7486 outputs: []outputInfo{ 7487 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7488 }, 7489 }, 7490 }, 7491 { 7492 name: "SUB", 7493 argLen: 2, 7494 asm: arm.ASUB, 7495 reg: regInfo{ 7496 inputs: []inputInfo{ 7497 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7498 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7499 }, 7500 outputs: []outputInfo{ 7501 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7502 }, 7503 }, 7504 }, 7505 { 7506 name: "SUBconst", 7507 auxType: auxInt32, 7508 argLen: 1, 7509 asm: arm.ASUB, 7510 reg: regInfo{ 7511 inputs: []inputInfo{ 7512 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7513 }, 7514 outputs: []outputInfo{ 7515 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7516 }, 7517 }, 7518 }, 7519 { 7520 name: "RSB", 7521 argLen: 2, 7522 asm: arm.ARSB, 7523 reg: regInfo{ 7524 inputs: []inputInfo{ 7525 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7526 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7527 }, 7528 outputs: []outputInfo{ 7529 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7530 }, 7531 }, 7532 }, 7533 { 7534 name: "RSBconst", 7535 auxType: auxInt32, 7536 argLen: 1, 7537 asm: arm.ARSB, 7538 reg: regInfo{ 7539 inputs: []inputInfo{ 7540 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7541 }, 7542 outputs: []outputInfo{ 7543 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7544 }, 7545 }, 7546 }, 7547 { 7548 name: "MUL", 7549 argLen: 2, 7550 commutative: true, 7551 asm: arm.AMUL, 7552 reg: regInfo{ 7553 inputs: []inputInfo{ 7554 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7555 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7556 }, 7557 outputs: []outputInfo{ 7558 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7559 }, 7560 }, 7561 }, 7562 { 7563 name: "HMUL", 7564 argLen: 2, 7565 commutative: true, 7566 asm: arm.AMULL, 7567 reg: regInfo{ 7568 inputs: []inputInfo{ 7569 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7570 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7571 }, 7572 outputs: []outputInfo{ 7573 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7574 }, 7575 }, 7576 }, 7577 { 7578 name: "HMULU", 7579 argLen: 2, 7580 commutative: true, 7581 asm: arm.AMULLU, 7582 reg: regInfo{ 7583 inputs: []inputInfo{ 7584 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7585 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7586 }, 7587 outputs: []outputInfo{ 7588 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7589 }, 7590 }, 7591 }, 7592 { 7593 name: "UDIVrtcall", 7594 argLen: 2, 7595 clobberFlags: true, 7596 reg: regInfo{ 7597 inputs: []inputInfo{ 7598 {0, 2}, // R1 7599 {1, 1}, // R0 7600 }, 7601 clobbers: 16396, // R2 R3 R14 7602 outputs: []outputInfo{ 7603 {0, 1}, // R0 7604 {1, 2}, // R1 7605 }, 7606 }, 7607 }, 7608 { 7609 name: "ADDS", 7610 argLen: 2, 7611 commutative: true, 7612 asm: arm.AADD, 7613 reg: regInfo{ 7614 inputs: []inputInfo{ 7615 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7616 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7617 }, 7618 outputs: []outputInfo{ 7619 {1, 0}, 7620 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7621 }, 7622 }, 7623 }, 7624 { 7625 name: "ADDSconst", 7626 auxType: auxInt32, 7627 argLen: 1, 7628 asm: arm.AADD, 7629 reg: regInfo{ 7630 inputs: []inputInfo{ 7631 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7632 }, 7633 outputs: []outputInfo{ 7634 {1, 0}, 7635 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7636 }, 7637 }, 7638 }, 7639 { 7640 name: "ADC", 7641 argLen: 3, 7642 commutative: true, 7643 asm: arm.AADC, 7644 reg: regInfo{ 7645 inputs: []inputInfo{ 7646 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7647 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7648 }, 7649 outputs: []outputInfo{ 7650 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7651 }, 7652 }, 7653 }, 7654 { 7655 name: "ADCconst", 7656 auxType: auxInt32, 7657 argLen: 2, 7658 asm: arm.AADC, 7659 reg: regInfo{ 7660 inputs: []inputInfo{ 7661 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7662 }, 7663 outputs: []outputInfo{ 7664 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7665 }, 7666 }, 7667 }, 7668 { 7669 name: "SUBS", 7670 argLen: 2, 7671 asm: arm.ASUB, 7672 reg: regInfo{ 7673 inputs: []inputInfo{ 7674 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7675 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7676 }, 7677 outputs: []outputInfo{ 7678 {1, 0}, 7679 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7680 }, 7681 }, 7682 }, 7683 { 7684 name: "SUBSconst", 7685 auxType: auxInt32, 7686 argLen: 1, 7687 asm: arm.ASUB, 7688 reg: regInfo{ 7689 inputs: []inputInfo{ 7690 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7691 }, 7692 outputs: []outputInfo{ 7693 {1, 0}, 7694 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7695 }, 7696 }, 7697 }, 7698 { 7699 name: "RSBSconst", 7700 auxType: auxInt32, 7701 argLen: 1, 7702 asm: arm.ARSB, 7703 reg: regInfo{ 7704 inputs: []inputInfo{ 7705 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7706 }, 7707 outputs: []outputInfo{ 7708 {1, 0}, 7709 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7710 }, 7711 }, 7712 }, 7713 { 7714 name: "SBC", 7715 argLen: 3, 7716 asm: arm.ASBC, 7717 reg: regInfo{ 7718 inputs: []inputInfo{ 7719 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7720 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7721 }, 7722 outputs: []outputInfo{ 7723 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7724 }, 7725 }, 7726 }, 7727 { 7728 name: "SBCconst", 7729 auxType: auxInt32, 7730 argLen: 2, 7731 asm: arm.ASBC, 7732 reg: regInfo{ 7733 inputs: []inputInfo{ 7734 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7735 }, 7736 outputs: []outputInfo{ 7737 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7738 }, 7739 }, 7740 }, 7741 { 7742 name: "RSCconst", 7743 auxType: auxInt32, 7744 argLen: 2, 7745 asm: arm.ARSC, 7746 reg: regInfo{ 7747 inputs: []inputInfo{ 7748 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7749 }, 7750 outputs: []outputInfo{ 7751 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7752 }, 7753 }, 7754 }, 7755 { 7756 name: "MULLU", 7757 argLen: 2, 7758 commutative: true, 7759 asm: arm.AMULLU, 7760 reg: regInfo{ 7761 inputs: []inputInfo{ 7762 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7763 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7764 }, 7765 outputs: []outputInfo{ 7766 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7767 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7768 }, 7769 }, 7770 }, 7771 { 7772 name: "MULA", 7773 argLen: 3, 7774 asm: arm.AMULA, 7775 reg: regInfo{ 7776 inputs: []inputInfo{ 7777 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7778 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7779 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7780 }, 7781 outputs: []outputInfo{ 7782 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7783 }, 7784 }, 7785 }, 7786 { 7787 name: "ADDF", 7788 argLen: 2, 7789 commutative: true, 7790 asm: arm.AADDF, 7791 reg: regInfo{ 7792 inputs: []inputInfo{ 7793 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7794 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7795 }, 7796 outputs: []outputInfo{ 7797 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7798 }, 7799 }, 7800 }, 7801 { 7802 name: "ADDD", 7803 argLen: 2, 7804 commutative: true, 7805 asm: arm.AADDD, 7806 reg: regInfo{ 7807 inputs: []inputInfo{ 7808 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7809 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7810 }, 7811 outputs: []outputInfo{ 7812 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7813 }, 7814 }, 7815 }, 7816 { 7817 name: "SUBF", 7818 argLen: 2, 7819 asm: arm.ASUBF, 7820 reg: regInfo{ 7821 inputs: []inputInfo{ 7822 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7823 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7824 }, 7825 outputs: []outputInfo{ 7826 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7827 }, 7828 }, 7829 }, 7830 { 7831 name: "SUBD", 7832 argLen: 2, 7833 asm: arm.ASUBD, 7834 reg: regInfo{ 7835 inputs: []inputInfo{ 7836 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7837 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7838 }, 7839 outputs: []outputInfo{ 7840 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7841 }, 7842 }, 7843 }, 7844 { 7845 name: "MULF", 7846 argLen: 2, 7847 commutative: true, 7848 asm: arm.AMULF, 7849 reg: regInfo{ 7850 inputs: []inputInfo{ 7851 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7852 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7853 }, 7854 outputs: []outputInfo{ 7855 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7856 }, 7857 }, 7858 }, 7859 { 7860 name: "MULD", 7861 argLen: 2, 7862 commutative: true, 7863 asm: arm.AMULD, 7864 reg: regInfo{ 7865 inputs: []inputInfo{ 7866 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7867 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7868 }, 7869 outputs: []outputInfo{ 7870 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7871 }, 7872 }, 7873 }, 7874 { 7875 name: "DIVF", 7876 argLen: 2, 7877 asm: arm.ADIVF, 7878 reg: regInfo{ 7879 inputs: []inputInfo{ 7880 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7881 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7882 }, 7883 outputs: []outputInfo{ 7884 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7885 }, 7886 }, 7887 }, 7888 { 7889 name: "DIVD", 7890 argLen: 2, 7891 asm: arm.ADIVD, 7892 reg: regInfo{ 7893 inputs: []inputInfo{ 7894 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7895 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7896 }, 7897 outputs: []outputInfo{ 7898 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7899 }, 7900 }, 7901 }, 7902 { 7903 name: "AND", 7904 argLen: 2, 7905 commutative: true, 7906 asm: arm.AAND, 7907 reg: regInfo{ 7908 inputs: []inputInfo{ 7909 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7910 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7911 }, 7912 outputs: []outputInfo{ 7913 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7914 }, 7915 }, 7916 }, 7917 { 7918 name: "ANDconst", 7919 auxType: auxInt32, 7920 argLen: 1, 7921 asm: arm.AAND, 7922 reg: regInfo{ 7923 inputs: []inputInfo{ 7924 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7925 }, 7926 outputs: []outputInfo{ 7927 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7928 }, 7929 }, 7930 }, 7931 { 7932 name: "OR", 7933 argLen: 2, 7934 commutative: true, 7935 asm: arm.AORR, 7936 reg: regInfo{ 7937 inputs: []inputInfo{ 7938 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7939 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7940 }, 7941 outputs: []outputInfo{ 7942 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7943 }, 7944 }, 7945 }, 7946 { 7947 name: "ORconst", 7948 auxType: auxInt32, 7949 argLen: 1, 7950 asm: arm.AORR, 7951 reg: regInfo{ 7952 inputs: []inputInfo{ 7953 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7954 }, 7955 outputs: []outputInfo{ 7956 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7957 }, 7958 }, 7959 }, 7960 { 7961 name: "XOR", 7962 argLen: 2, 7963 commutative: true, 7964 asm: arm.AEOR, 7965 reg: regInfo{ 7966 inputs: []inputInfo{ 7967 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7968 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7969 }, 7970 outputs: []outputInfo{ 7971 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7972 }, 7973 }, 7974 }, 7975 { 7976 name: "XORconst", 7977 auxType: auxInt32, 7978 argLen: 1, 7979 asm: arm.AEOR, 7980 reg: regInfo{ 7981 inputs: []inputInfo{ 7982 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7983 }, 7984 outputs: []outputInfo{ 7985 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7986 }, 7987 }, 7988 }, 7989 { 7990 name: "BIC", 7991 argLen: 2, 7992 asm: arm.ABIC, 7993 reg: regInfo{ 7994 inputs: []inputInfo{ 7995 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7996 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7997 }, 7998 outputs: []outputInfo{ 7999 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8000 }, 8001 }, 8002 }, 8003 { 8004 name: "BICconst", 8005 auxType: auxInt32, 8006 argLen: 1, 8007 asm: arm.ABIC, 8008 reg: regInfo{ 8009 inputs: []inputInfo{ 8010 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8011 }, 8012 outputs: []outputInfo{ 8013 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8014 }, 8015 }, 8016 }, 8017 { 8018 name: "MVN", 8019 argLen: 1, 8020 asm: arm.AMVN, 8021 reg: regInfo{ 8022 inputs: []inputInfo{ 8023 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8024 }, 8025 outputs: []outputInfo{ 8026 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8027 }, 8028 }, 8029 }, 8030 { 8031 name: "NEGF", 8032 argLen: 1, 8033 asm: arm.ANEGF, 8034 reg: regInfo{ 8035 inputs: []inputInfo{ 8036 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8037 }, 8038 outputs: []outputInfo{ 8039 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8040 }, 8041 }, 8042 }, 8043 { 8044 name: "NEGD", 8045 argLen: 1, 8046 asm: arm.ANEGD, 8047 reg: regInfo{ 8048 inputs: []inputInfo{ 8049 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8050 }, 8051 outputs: []outputInfo{ 8052 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8053 }, 8054 }, 8055 }, 8056 { 8057 name: "SQRTD", 8058 argLen: 1, 8059 asm: arm.ASQRTD, 8060 reg: regInfo{ 8061 inputs: []inputInfo{ 8062 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8063 }, 8064 outputs: []outputInfo{ 8065 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8066 }, 8067 }, 8068 }, 8069 { 8070 name: "CLZ", 8071 argLen: 1, 8072 asm: arm.ACLZ, 8073 reg: regInfo{ 8074 inputs: []inputInfo{ 8075 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8076 }, 8077 outputs: []outputInfo{ 8078 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8079 }, 8080 }, 8081 }, 8082 { 8083 name: "SLL", 8084 argLen: 2, 8085 asm: arm.ASLL, 8086 reg: regInfo{ 8087 inputs: []inputInfo{ 8088 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8089 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8090 }, 8091 outputs: []outputInfo{ 8092 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8093 }, 8094 }, 8095 }, 8096 { 8097 name: "SLLconst", 8098 auxType: auxInt32, 8099 argLen: 1, 8100 asm: arm.ASLL, 8101 reg: regInfo{ 8102 inputs: []inputInfo{ 8103 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8104 }, 8105 outputs: []outputInfo{ 8106 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8107 }, 8108 }, 8109 }, 8110 { 8111 name: "SRL", 8112 argLen: 2, 8113 asm: arm.ASRL, 8114 reg: regInfo{ 8115 inputs: []inputInfo{ 8116 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8117 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8118 }, 8119 outputs: []outputInfo{ 8120 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8121 }, 8122 }, 8123 }, 8124 { 8125 name: "SRLconst", 8126 auxType: auxInt32, 8127 argLen: 1, 8128 asm: arm.ASRL, 8129 reg: regInfo{ 8130 inputs: []inputInfo{ 8131 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8132 }, 8133 outputs: []outputInfo{ 8134 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8135 }, 8136 }, 8137 }, 8138 { 8139 name: "SRA", 8140 argLen: 2, 8141 asm: arm.ASRA, 8142 reg: regInfo{ 8143 inputs: []inputInfo{ 8144 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8145 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8146 }, 8147 outputs: []outputInfo{ 8148 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8149 }, 8150 }, 8151 }, 8152 { 8153 name: "SRAconst", 8154 auxType: auxInt32, 8155 argLen: 1, 8156 asm: arm.ASRA, 8157 reg: regInfo{ 8158 inputs: []inputInfo{ 8159 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8160 }, 8161 outputs: []outputInfo{ 8162 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8163 }, 8164 }, 8165 }, 8166 { 8167 name: "SRRconst", 8168 auxType: auxInt32, 8169 argLen: 1, 8170 reg: regInfo{ 8171 inputs: []inputInfo{ 8172 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8173 }, 8174 outputs: []outputInfo{ 8175 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8176 }, 8177 }, 8178 }, 8179 { 8180 name: "ADDshiftLL", 8181 auxType: auxInt32, 8182 argLen: 2, 8183 asm: arm.AADD, 8184 reg: regInfo{ 8185 inputs: []inputInfo{ 8186 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8187 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8188 }, 8189 outputs: []outputInfo{ 8190 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8191 }, 8192 }, 8193 }, 8194 { 8195 name: "ADDshiftRL", 8196 auxType: auxInt32, 8197 argLen: 2, 8198 asm: arm.AADD, 8199 reg: regInfo{ 8200 inputs: []inputInfo{ 8201 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8202 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8203 }, 8204 outputs: []outputInfo{ 8205 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8206 }, 8207 }, 8208 }, 8209 { 8210 name: "ADDshiftRA", 8211 auxType: auxInt32, 8212 argLen: 2, 8213 asm: arm.AADD, 8214 reg: regInfo{ 8215 inputs: []inputInfo{ 8216 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8217 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8218 }, 8219 outputs: []outputInfo{ 8220 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8221 }, 8222 }, 8223 }, 8224 { 8225 name: "SUBshiftLL", 8226 auxType: auxInt32, 8227 argLen: 2, 8228 asm: arm.ASUB, 8229 reg: regInfo{ 8230 inputs: []inputInfo{ 8231 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8232 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8233 }, 8234 outputs: []outputInfo{ 8235 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8236 }, 8237 }, 8238 }, 8239 { 8240 name: "SUBshiftRL", 8241 auxType: auxInt32, 8242 argLen: 2, 8243 asm: arm.ASUB, 8244 reg: regInfo{ 8245 inputs: []inputInfo{ 8246 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8247 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8248 }, 8249 outputs: []outputInfo{ 8250 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8251 }, 8252 }, 8253 }, 8254 { 8255 name: "SUBshiftRA", 8256 auxType: auxInt32, 8257 argLen: 2, 8258 asm: arm.ASUB, 8259 reg: regInfo{ 8260 inputs: []inputInfo{ 8261 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8262 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8263 }, 8264 outputs: []outputInfo{ 8265 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8266 }, 8267 }, 8268 }, 8269 { 8270 name: "RSBshiftLL", 8271 auxType: auxInt32, 8272 argLen: 2, 8273 asm: arm.ARSB, 8274 reg: regInfo{ 8275 inputs: []inputInfo{ 8276 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8277 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8278 }, 8279 outputs: []outputInfo{ 8280 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8281 }, 8282 }, 8283 }, 8284 { 8285 name: "RSBshiftRL", 8286 auxType: auxInt32, 8287 argLen: 2, 8288 asm: arm.ARSB, 8289 reg: regInfo{ 8290 inputs: []inputInfo{ 8291 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8292 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8293 }, 8294 outputs: []outputInfo{ 8295 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8296 }, 8297 }, 8298 }, 8299 { 8300 name: "RSBshiftRA", 8301 auxType: auxInt32, 8302 argLen: 2, 8303 asm: arm.ARSB, 8304 reg: regInfo{ 8305 inputs: []inputInfo{ 8306 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8307 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8308 }, 8309 outputs: []outputInfo{ 8310 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8311 }, 8312 }, 8313 }, 8314 { 8315 name: "ANDshiftLL", 8316 auxType: auxInt32, 8317 argLen: 2, 8318 asm: arm.AAND, 8319 reg: regInfo{ 8320 inputs: []inputInfo{ 8321 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8322 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8323 }, 8324 outputs: []outputInfo{ 8325 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8326 }, 8327 }, 8328 }, 8329 { 8330 name: "ANDshiftRL", 8331 auxType: auxInt32, 8332 argLen: 2, 8333 asm: arm.AAND, 8334 reg: regInfo{ 8335 inputs: []inputInfo{ 8336 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8337 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8338 }, 8339 outputs: []outputInfo{ 8340 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8341 }, 8342 }, 8343 }, 8344 { 8345 name: "ANDshiftRA", 8346 auxType: auxInt32, 8347 argLen: 2, 8348 asm: arm.AAND, 8349 reg: regInfo{ 8350 inputs: []inputInfo{ 8351 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8352 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8353 }, 8354 outputs: []outputInfo{ 8355 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8356 }, 8357 }, 8358 }, 8359 { 8360 name: "ORshiftLL", 8361 auxType: auxInt32, 8362 argLen: 2, 8363 asm: arm.AORR, 8364 reg: regInfo{ 8365 inputs: []inputInfo{ 8366 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8367 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8368 }, 8369 outputs: []outputInfo{ 8370 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8371 }, 8372 }, 8373 }, 8374 { 8375 name: "ORshiftRL", 8376 auxType: auxInt32, 8377 argLen: 2, 8378 asm: arm.AORR, 8379 reg: regInfo{ 8380 inputs: []inputInfo{ 8381 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8382 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8383 }, 8384 outputs: []outputInfo{ 8385 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8386 }, 8387 }, 8388 }, 8389 { 8390 name: "ORshiftRA", 8391 auxType: auxInt32, 8392 argLen: 2, 8393 asm: arm.AORR, 8394 reg: regInfo{ 8395 inputs: []inputInfo{ 8396 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8397 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8398 }, 8399 outputs: []outputInfo{ 8400 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8401 }, 8402 }, 8403 }, 8404 { 8405 name: "XORshiftLL", 8406 auxType: auxInt32, 8407 argLen: 2, 8408 asm: arm.AEOR, 8409 reg: regInfo{ 8410 inputs: []inputInfo{ 8411 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8412 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8413 }, 8414 outputs: []outputInfo{ 8415 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8416 }, 8417 }, 8418 }, 8419 { 8420 name: "XORshiftRL", 8421 auxType: auxInt32, 8422 argLen: 2, 8423 asm: arm.AEOR, 8424 reg: regInfo{ 8425 inputs: []inputInfo{ 8426 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8427 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8428 }, 8429 outputs: []outputInfo{ 8430 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8431 }, 8432 }, 8433 }, 8434 { 8435 name: "XORshiftRA", 8436 auxType: auxInt32, 8437 argLen: 2, 8438 asm: arm.AEOR, 8439 reg: regInfo{ 8440 inputs: []inputInfo{ 8441 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8442 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8443 }, 8444 outputs: []outputInfo{ 8445 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8446 }, 8447 }, 8448 }, 8449 { 8450 name: "XORshiftRR", 8451 auxType: auxInt32, 8452 argLen: 2, 8453 asm: arm.AEOR, 8454 reg: regInfo{ 8455 inputs: []inputInfo{ 8456 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8457 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8458 }, 8459 outputs: []outputInfo{ 8460 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8461 }, 8462 }, 8463 }, 8464 { 8465 name: "BICshiftLL", 8466 auxType: auxInt32, 8467 argLen: 2, 8468 asm: arm.ABIC, 8469 reg: regInfo{ 8470 inputs: []inputInfo{ 8471 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8472 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8473 }, 8474 outputs: []outputInfo{ 8475 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8476 }, 8477 }, 8478 }, 8479 { 8480 name: "BICshiftRL", 8481 auxType: auxInt32, 8482 argLen: 2, 8483 asm: arm.ABIC, 8484 reg: regInfo{ 8485 inputs: []inputInfo{ 8486 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8487 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8488 }, 8489 outputs: []outputInfo{ 8490 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8491 }, 8492 }, 8493 }, 8494 { 8495 name: "BICshiftRA", 8496 auxType: auxInt32, 8497 argLen: 2, 8498 asm: arm.ABIC, 8499 reg: regInfo{ 8500 inputs: []inputInfo{ 8501 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8502 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8503 }, 8504 outputs: []outputInfo{ 8505 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8506 }, 8507 }, 8508 }, 8509 { 8510 name: "MVNshiftLL", 8511 auxType: auxInt32, 8512 argLen: 1, 8513 asm: arm.AMVN, 8514 reg: regInfo{ 8515 inputs: []inputInfo{ 8516 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8517 }, 8518 outputs: []outputInfo{ 8519 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8520 }, 8521 }, 8522 }, 8523 { 8524 name: "MVNshiftRL", 8525 auxType: auxInt32, 8526 argLen: 1, 8527 asm: arm.AMVN, 8528 reg: regInfo{ 8529 inputs: []inputInfo{ 8530 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8531 }, 8532 outputs: []outputInfo{ 8533 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8534 }, 8535 }, 8536 }, 8537 { 8538 name: "MVNshiftRA", 8539 auxType: auxInt32, 8540 argLen: 1, 8541 asm: arm.AMVN, 8542 reg: regInfo{ 8543 inputs: []inputInfo{ 8544 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8545 }, 8546 outputs: []outputInfo{ 8547 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8548 }, 8549 }, 8550 }, 8551 { 8552 name: "ADCshiftLL", 8553 auxType: auxInt32, 8554 argLen: 3, 8555 asm: arm.AADC, 8556 reg: regInfo{ 8557 inputs: []inputInfo{ 8558 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8559 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8560 }, 8561 outputs: []outputInfo{ 8562 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8563 }, 8564 }, 8565 }, 8566 { 8567 name: "ADCshiftRL", 8568 auxType: auxInt32, 8569 argLen: 3, 8570 asm: arm.AADC, 8571 reg: regInfo{ 8572 inputs: []inputInfo{ 8573 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8574 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8575 }, 8576 outputs: []outputInfo{ 8577 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8578 }, 8579 }, 8580 }, 8581 { 8582 name: "ADCshiftRA", 8583 auxType: auxInt32, 8584 argLen: 3, 8585 asm: arm.AADC, 8586 reg: regInfo{ 8587 inputs: []inputInfo{ 8588 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8589 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8590 }, 8591 outputs: []outputInfo{ 8592 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8593 }, 8594 }, 8595 }, 8596 { 8597 name: "SBCshiftLL", 8598 auxType: auxInt32, 8599 argLen: 3, 8600 asm: arm.ASBC, 8601 reg: regInfo{ 8602 inputs: []inputInfo{ 8603 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8604 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8605 }, 8606 outputs: []outputInfo{ 8607 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8608 }, 8609 }, 8610 }, 8611 { 8612 name: "SBCshiftRL", 8613 auxType: auxInt32, 8614 argLen: 3, 8615 asm: arm.ASBC, 8616 reg: regInfo{ 8617 inputs: []inputInfo{ 8618 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8619 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8620 }, 8621 outputs: []outputInfo{ 8622 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8623 }, 8624 }, 8625 }, 8626 { 8627 name: "SBCshiftRA", 8628 auxType: auxInt32, 8629 argLen: 3, 8630 asm: arm.ASBC, 8631 reg: regInfo{ 8632 inputs: []inputInfo{ 8633 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8634 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8635 }, 8636 outputs: []outputInfo{ 8637 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8638 }, 8639 }, 8640 }, 8641 { 8642 name: "RSCshiftLL", 8643 auxType: auxInt32, 8644 argLen: 3, 8645 asm: arm.ARSC, 8646 reg: regInfo{ 8647 inputs: []inputInfo{ 8648 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8649 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8650 }, 8651 outputs: []outputInfo{ 8652 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8653 }, 8654 }, 8655 }, 8656 { 8657 name: "RSCshiftRL", 8658 auxType: auxInt32, 8659 argLen: 3, 8660 asm: arm.ARSC, 8661 reg: regInfo{ 8662 inputs: []inputInfo{ 8663 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8664 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8665 }, 8666 outputs: []outputInfo{ 8667 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8668 }, 8669 }, 8670 }, 8671 { 8672 name: "RSCshiftRA", 8673 auxType: auxInt32, 8674 argLen: 3, 8675 asm: arm.ARSC, 8676 reg: regInfo{ 8677 inputs: []inputInfo{ 8678 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8679 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8680 }, 8681 outputs: []outputInfo{ 8682 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8683 }, 8684 }, 8685 }, 8686 { 8687 name: "ADDSshiftLL", 8688 auxType: auxInt32, 8689 argLen: 2, 8690 asm: arm.AADD, 8691 reg: regInfo{ 8692 inputs: []inputInfo{ 8693 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8694 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8695 }, 8696 outputs: []outputInfo{ 8697 {1, 0}, 8698 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8699 }, 8700 }, 8701 }, 8702 { 8703 name: "ADDSshiftRL", 8704 auxType: auxInt32, 8705 argLen: 2, 8706 asm: arm.AADD, 8707 reg: regInfo{ 8708 inputs: []inputInfo{ 8709 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8710 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8711 }, 8712 outputs: []outputInfo{ 8713 {1, 0}, 8714 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8715 }, 8716 }, 8717 }, 8718 { 8719 name: "ADDSshiftRA", 8720 auxType: auxInt32, 8721 argLen: 2, 8722 asm: arm.AADD, 8723 reg: regInfo{ 8724 inputs: []inputInfo{ 8725 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8726 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8727 }, 8728 outputs: []outputInfo{ 8729 {1, 0}, 8730 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8731 }, 8732 }, 8733 }, 8734 { 8735 name: "SUBSshiftLL", 8736 auxType: auxInt32, 8737 argLen: 2, 8738 asm: arm.ASUB, 8739 reg: regInfo{ 8740 inputs: []inputInfo{ 8741 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8742 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8743 }, 8744 outputs: []outputInfo{ 8745 {1, 0}, 8746 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8747 }, 8748 }, 8749 }, 8750 { 8751 name: "SUBSshiftRL", 8752 auxType: auxInt32, 8753 argLen: 2, 8754 asm: arm.ASUB, 8755 reg: regInfo{ 8756 inputs: []inputInfo{ 8757 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8758 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8759 }, 8760 outputs: []outputInfo{ 8761 {1, 0}, 8762 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8763 }, 8764 }, 8765 }, 8766 { 8767 name: "SUBSshiftRA", 8768 auxType: auxInt32, 8769 argLen: 2, 8770 asm: arm.ASUB, 8771 reg: regInfo{ 8772 inputs: []inputInfo{ 8773 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8774 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8775 }, 8776 outputs: []outputInfo{ 8777 {1, 0}, 8778 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8779 }, 8780 }, 8781 }, 8782 { 8783 name: "RSBSshiftLL", 8784 auxType: auxInt32, 8785 argLen: 2, 8786 asm: arm.ARSB, 8787 reg: regInfo{ 8788 inputs: []inputInfo{ 8789 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8790 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8791 }, 8792 outputs: []outputInfo{ 8793 {1, 0}, 8794 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8795 }, 8796 }, 8797 }, 8798 { 8799 name: "RSBSshiftRL", 8800 auxType: auxInt32, 8801 argLen: 2, 8802 asm: arm.ARSB, 8803 reg: regInfo{ 8804 inputs: []inputInfo{ 8805 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8806 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8807 }, 8808 outputs: []outputInfo{ 8809 {1, 0}, 8810 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8811 }, 8812 }, 8813 }, 8814 { 8815 name: "RSBSshiftRA", 8816 auxType: auxInt32, 8817 argLen: 2, 8818 asm: arm.ARSB, 8819 reg: regInfo{ 8820 inputs: []inputInfo{ 8821 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8822 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8823 }, 8824 outputs: []outputInfo{ 8825 {1, 0}, 8826 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8827 }, 8828 }, 8829 }, 8830 { 8831 name: "ADDshiftLLreg", 8832 argLen: 3, 8833 asm: arm.AADD, 8834 reg: regInfo{ 8835 inputs: []inputInfo{ 8836 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8837 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8838 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8839 }, 8840 outputs: []outputInfo{ 8841 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8842 }, 8843 }, 8844 }, 8845 { 8846 name: "ADDshiftRLreg", 8847 argLen: 3, 8848 asm: arm.AADD, 8849 reg: regInfo{ 8850 inputs: []inputInfo{ 8851 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8852 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8853 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8854 }, 8855 outputs: []outputInfo{ 8856 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8857 }, 8858 }, 8859 }, 8860 { 8861 name: "ADDshiftRAreg", 8862 argLen: 3, 8863 asm: arm.AADD, 8864 reg: regInfo{ 8865 inputs: []inputInfo{ 8866 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8867 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8868 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8869 }, 8870 outputs: []outputInfo{ 8871 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8872 }, 8873 }, 8874 }, 8875 { 8876 name: "SUBshiftLLreg", 8877 argLen: 3, 8878 asm: arm.ASUB, 8879 reg: regInfo{ 8880 inputs: []inputInfo{ 8881 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8882 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8883 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8884 }, 8885 outputs: []outputInfo{ 8886 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8887 }, 8888 }, 8889 }, 8890 { 8891 name: "SUBshiftRLreg", 8892 argLen: 3, 8893 asm: arm.ASUB, 8894 reg: regInfo{ 8895 inputs: []inputInfo{ 8896 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8897 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8898 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8899 }, 8900 outputs: []outputInfo{ 8901 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8902 }, 8903 }, 8904 }, 8905 { 8906 name: "SUBshiftRAreg", 8907 argLen: 3, 8908 asm: arm.ASUB, 8909 reg: regInfo{ 8910 inputs: []inputInfo{ 8911 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8912 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8913 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8914 }, 8915 outputs: []outputInfo{ 8916 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8917 }, 8918 }, 8919 }, 8920 { 8921 name: "RSBshiftLLreg", 8922 argLen: 3, 8923 asm: arm.ARSB, 8924 reg: regInfo{ 8925 inputs: []inputInfo{ 8926 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8927 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8928 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8929 }, 8930 outputs: []outputInfo{ 8931 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8932 }, 8933 }, 8934 }, 8935 { 8936 name: "RSBshiftRLreg", 8937 argLen: 3, 8938 asm: arm.ARSB, 8939 reg: regInfo{ 8940 inputs: []inputInfo{ 8941 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8942 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8943 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8944 }, 8945 outputs: []outputInfo{ 8946 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8947 }, 8948 }, 8949 }, 8950 { 8951 name: "RSBshiftRAreg", 8952 argLen: 3, 8953 asm: arm.ARSB, 8954 reg: regInfo{ 8955 inputs: []inputInfo{ 8956 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8957 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8958 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8959 }, 8960 outputs: []outputInfo{ 8961 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8962 }, 8963 }, 8964 }, 8965 { 8966 name: "ANDshiftLLreg", 8967 argLen: 3, 8968 asm: arm.AAND, 8969 reg: regInfo{ 8970 inputs: []inputInfo{ 8971 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8972 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8973 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8974 }, 8975 outputs: []outputInfo{ 8976 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8977 }, 8978 }, 8979 }, 8980 { 8981 name: "ANDshiftRLreg", 8982 argLen: 3, 8983 asm: arm.AAND, 8984 reg: regInfo{ 8985 inputs: []inputInfo{ 8986 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8987 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8988 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8989 }, 8990 outputs: []outputInfo{ 8991 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8992 }, 8993 }, 8994 }, 8995 { 8996 name: "ANDshiftRAreg", 8997 argLen: 3, 8998 asm: arm.AAND, 8999 reg: regInfo{ 9000 inputs: []inputInfo{ 9001 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9002 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9003 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9004 }, 9005 outputs: []outputInfo{ 9006 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9007 }, 9008 }, 9009 }, 9010 { 9011 name: "ORshiftLLreg", 9012 argLen: 3, 9013 asm: arm.AORR, 9014 reg: regInfo{ 9015 inputs: []inputInfo{ 9016 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9017 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9018 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9019 }, 9020 outputs: []outputInfo{ 9021 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9022 }, 9023 }, 9024 }, 9025 { 9026 name: "ORshiftRLreg", 9027 argLen: 3, 9028 asm: arm.AORR, 9029 reg: regInfo{ 9030 inputs: []inputInfo{ 9031 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9032 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9033 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9034 }, 9035 outputs: []outputInfo{ 9036 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9037 }, 9038 }, 9039 }, 9040 { 9041 name: "ORshiftRAreg", 9042 argLen: 3, 9043 asm: arm.AORR, 9044 reg: regInfo{ 9045 inputs: []inputInfo{ 9046 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9047 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9048 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9049 }, 9050 outputs: []outputInfo{ 9051 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9052 }, 9053 }, 9054 }, 9055 { 9056 name: "XORshiftLLreg", 9057 argLen: 3, 9058 asm: arm.AEOR, 9059 reg: regInfo{ 9060 inputs: []inputInfo{ 9061 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9062 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9063 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9064 }, 9065 outputs: []outputInfo{ 9066 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9067 }, 9068 }, 9069 }, 9070 { 9071 name: "XORshiftRLreg", 9072 argLen: 3, 9073 asm: arm.AEOR, 9074 reg: regInfo{ 9075 inputs: []inputInfo{ 9076 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9077 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9078 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9079 }, 9080 outputs: []outputInfo{ 9081 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9082 }, 9083 }, 9084 }, 9085 { 9086 name: "XORshiftRAreg", 9087 argLen: 3, 9088 asm: arm.AEOR, 9089 reg: regInfo{ 9090 inputs: []inputInfo{ 9091 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9092 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9093 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9094 }, 9095 outputs: []outputInfo{ 9096 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9097 }, 9098 }, 9099 }, 9100 { 9101 name: "BICshiftLLreg", 9102 argLen: 3, 9103 asm: arm.ABIC, 9104 reg: regInfo{ 9105 inputs: []inputInfo{ 9106 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9107 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9108 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9109 }, 9110 outputs: []outputInfo{ 9111 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9112 }, 9113 }, 9114 }, 9115 { 9116 name: "BICshiftRLreg", 9117 argLen: 3, 9118 asm: arm.ABIC, 9119 reg: regInfo{ 9120 inputs: []inputInfo{ 9121 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9122 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9123 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9124 }, 9125 outputs: []outputInfo{ 9126 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9127 }, 9128 }, 9129 }, 9130 { 9131 name: "BICshiftRAreg", 9132 argLen: 3, 9133 asm: arm.ABIC, 9134 reg: regInfo{ 9135 inputs: []inputInfo{ 9136 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9137 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9138 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9139 }, 9140 outputs: []outputInfo{ 9141 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9142 }, 9143 }, 9144 }, 9145 { 9146 name: "MVNshiftLLreg", 9147 argLen: 2, 9148 asm: arm.AMVN, 9149 reg: regInfo{ 9150 inputs: []inputInfo{ 9151 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9152 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9153 }, 9154 outputs: []outputInfo{ 9155 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9156 }, 9157 }, 9158 }, 9159 { 9160 name: "MVNshiftRLreg", 9161 argLen: 2, 9162 asm: arm.AMVN, 9163 reg: regInfo{ 9164 inputs: []inputInfo{ 9165 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9166 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9167 }, 9168 outputs: []outputInfo{ 9169 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9170 }, 9171 }, 9172 }, 9173 { 9174 name: "MVNshiftRAreg", 9175 argLen: 2, 9176 asm: arm.AMVN, 9177 reg: regInfo{ 9178 inputs: []inputInfo{ 9179 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9180 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9181 }, 9182 outputs: []outputInfo{ 9183 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9184 }, 9185 }, 9186 }, 9187 { 9188 name: "ADCshiftLLreg", 9189 argLen: 4, 9190 asm: arm.AADC, 9191 reg: regInfo{ 9192 inputs: []inputInfo{ 9193 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9194 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9195 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9196 }, 9197 outputs: []outputInfo{ 9198 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9199 }, 9200 }, 9201 }, 9202 { 9203 name: "ADCshiftRLreg", 9204 argLen: 4, 9205 asm: arm.AADC, 9206 reg: regInfo{ 9207 inputs: []inputInfo{ 9208 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9209 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9210 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9211 }, 9212 outputs: []outputInfo{ 9213 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9214 }, 9215 }, 9216 }, 9217 { 9218 name: "ADCshiftRAreg", 9219 argLen: 4, 9220 asm: arm.AADC, 9221 reg: regInfo{ 9222 inputs: []inputInfo{ 9223 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9224 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9225 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9226 }, 9227 outputs: []outputInfo{ 9228 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9229 }, 9230 }, 9231 }, 9232 { 9233 name: "SBCshiftLLreg", 9234 argLen: 4, 9235 asm: arm.ASBC, 9236 reg: regInfo{ 9237 inputs: []inputInfo{ 9238 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9239 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9240 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9241 }, 9242 outputs: []outputInfo{ 9243 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9244 }, 9245 }, 9246 }, 9247 { 9248 name: "SBCshiftRLreg", 9249 argLen: 4, 9250 asm: arm.ASBC, 9251 reg: regInfo{ 9252 inputs: []inputInfo{ 9253 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9254 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9255 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9256 }, 9257 outputs: []outputInfo{ 9258 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9259 }, 9260 }, 9261 }, 9262 { 9263 name: "SBCshiftRAreg", 9264 argLen: 4, 9265 asm: arm.ASBC, 9266 reg: regInfo{ 9267 inputs: []inputInfo{ 9268 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9269 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9270 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9271 }, 9272 outputs: []outputInfo{ 9273 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9274 }, 9275 }, 9276 }, 9277 { 9278 name: "RSCshiftLLreg", 9279 argLen: 4, 9280 asm: arm.ARSC, 9281 reg: regInfo{ 9282 inputs: []inputInfo{ 9283 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9284 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9285 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9286 }, 9287 outputs: []outputInfo{ 9288 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9289 }, 9290 }, 9291 }, 9292 { 9293 name: "RSCshiftRLreg", 9294 argLen: 4, 9295 asm: arm.ARSC, 9296 reg: regInfo{ 9297 inputs: []inputInfo{ 9298 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9299 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9300 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9301 }, 9302 outputs: []outputInfo{ 9303 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9304 }, 9305 }, 9306 }, 9307 { 9308 name: "RSCshiftRAreg", 9309 argLen: 4, 9310 asm: arm.ARSC, 9311 reg: regInfo{ 9312 inputs: []inputInfo{ 9313 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9314 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9315 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9316 }, 9317 outputs: []outputInfo{ 9318 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9319 }, 9320 }, 9321 }, 9322 { 9323 name: "ADDSshiftLLreg", 9324 argLen: 3, 9325 asm: arm.AADD, 9326 reg: regInfo{ 9327 inputs: []inputInfo{ 9328 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9329 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9330 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9331 }, 9332 outputs: []outputInfo{ 9333 {1, 0}, 9334 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9335 }, 9336 }, 9337 }, 9338 { 9339 name: "ADDSshiftRLreg", 9340 argLen: 3, 9341 asm: arm.AADD, 9342 reg: regInfo{ 9343 inputs: []inputInfo{ 9344 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9345 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9346 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9347 }, 9348 outputs: []outputInfo{ 9349 {1, 0}, 9350 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9351 }, 9352 }, 9353 }, 9354 { 9355 name: "ADDSshiftRAreg", 9356 argLen: 3, 9357 asm: arm.AADD, 9358 reg: regInfo{ 9359 inputs: []inputInfo{ 9360 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9361 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9362 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9363 }, 9364 outputs: []outputInfo{ 9365 {1, 0}, 9366 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9367 }, 9368 }, 9369 }, 9370 { 9371 name: "SUBSshiftLLreg", 9372 argLen: 3, 9373 asm: arm.ASUB, 9374 reg: regInfo{ 9375 inputs: []inputInfo{ 9376 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9377 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9378 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9379 }, 9380 outputs: []outputInfo{ 9381 {1, 0}, 9382 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9383 }, 9384 }, 9385 }, 9386 { 9387 name: "SUBSshiftRLreg", 9388 argLen: 3, 9389 asm: arm.ASUB, 9390 reg: regInfo{ 9391 inputs: []inputInfo{ 9392 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9393 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9394 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9395 }, 9396 outputs: []outputInfo{ 9397 {1, 0}, 9398 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9399 }, 9400 }, 9401 }, 9402 { 9403 name: "SUBSshiftRAreg", 9404 argLen: 3, 9405 asm: arm.ASUB, 9406 reg: regInfo{ 9407 inputs: []inputInfo{ 9408 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9409 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9410 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9411 }, 9412 outputs: []outputInfo{ 9413 {1, 0}, 9414 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9415 }, 9416 }, 9417 }, 9418 { 9419 name: "RSBSshiftLLreg", 9420 argLen: 3, 9421 asm: arm.ARSB, 9422 reg: regInfo{ 9423 inputs: []inputInfo{ 9424 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9425 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9426 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9427 }, 9428 outputs: []outputInfo{ 9429 {1, 0}, 9430 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9431 }, 9432 }, 9433 }, 9434 { 9435 name: "RSBSshiftRLreg", 9436 argLen: 3, 9437 asm: arm.ARSB, 9438 reg: regInfo{ 9439 inputs: []inputInfo{ 9440 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9441 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9442 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9443 }, 9444 outputs: []outputInfo{ 9445 {1, 0}, 9446 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9447 }, 9448 }, 9449 }, 9450 { 9451 name: "RSBSshiftRAreg", 9452 argLen: 3, 9453 asm: arm.ARSB, 9454 reg: regInfo{ 9455 inputs: []inputInfo{ 9456 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9457 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9458 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9459 }, 9460 outputs: []outputInfo{ 9461 {1, 0}, 9462 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9463 }, 9464 }, 9465 }, 9466 { 9467 name: "CMP", 9468 argLen: 2, 9469 asm: arm.ACMP, 9470 reg: regInfo{ 9471 inputs: []inputInfo{ 9472 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9473 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9474 }, 9475 }, 9476 }, 9477 { 9478 name: "CMPconst", 9479 auxType: auxInt32, 9480 argLen: 1, 9481 asm: arm.ACMP, 9482 reg: regInfo{ 9483 inputs: []inputInfo{ 9484 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9485 }, 9486 }, 9487 }, 9488 { 9489 name: "CMN", 9490 argLen: 2, 9491 asm: arm.ACMN, 9492 reg: regInfo{ 9493 inputs: []inputInfo{ 9494 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9495 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9496 }, 9497 }, 9498 }, 9499 { 9500 name: "CMNconst", 9501 auxType: auxInt32, 9502 argLen: 1, 9503 asm: arm.ACMN, 9504 reg: regInfo{ 9505 inputs: []inputInfo{ 9506 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9507 }, 9508 }, 9509 }, 9510 { 9511 name: "TST", 9512 argLen: 2, 9513 commutative: true, 9514 asm: arm.ATST, 9515 reg: regInfo{ 9516 inputs: []inputInfo{ 9517 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9518 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9519 }, 9520 }, 9521 }, 9522 { 9523 name: "TSTconst", 9524 auxType: auxInt32, 9525 argLen: 1, 9526 asm: arm.ATST, 9527 reg: regInfo{ 9528 inputs: []inputInfo{ 9529 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9530 }, 9531 }, 9532 }, 9533 { 9534 name: "TEQ", 9535 argLen: 2, 9536 commutative: true, 9537 asm: arm.ATEQ, 9538 reg: regInfo{ 9539 inputs: []inputInfo{ 9540 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9541 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9542 }, 9543 }, 9544 }, 9545 { 9546 name: "TEQconst", 9547 auxType: auxInt32, 9548 argLen: 1, 9549 asm: arm.ATEQ, 9550 reg: regInfo{ 9551 inputs: []inputInfo{ 9552 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9553 }, 9554 }, 9555 }, 9556 { 9557 name: "CMPF", 9558 argLen: 2, 9559 asm: arm.ACMPF, 9560 reg: regInfo{ 9561 inputs: []inputInfo{ 9562 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9563 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9564 }, 9565 }, 9566 }, 9567 { 9568 name: "CMPD", 9569 argLen: 2, 9570 asm: arm.ACMPD, 9571 reg: regInfo{ 9572 inputs: []inputInfo{ 9573 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9574 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9575 }, 9576 }, 9577 }, 9578 { 9579 name: "CMPshiftLL", 9580 auxType: auxInt32, 9581 argLen: 2, 9582 asm: arm.ACMP, 9583 reg: regInfo{ 9584 inputs: []inputInfo{ 9585 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9586 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9587 }, 9588 }, 9589 }, 9590 { 9591 name: "CMPshiftRL", 9592 auxType: auxInt32, 9593 argLen: 2, 9594 asm: arm.ACMP, 9595 reg: regInfo{ 9596 inputs: []inputInfo{ 9597 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9598 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9599 }, 9600 }, 9601 }, 9602 { 9603 name: "CMPshiftRA", 9604 auxType: auxInt32, 9605 argLen: 2, 9606 asm: arm.ACMP, 9607 reg: regInfo{ 9608 inputs: []inputInfo{ 9609 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9610 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9611 }, 9612 }, 9613 }, 9614 { 9615 name: "CMPshiftLLreg", 9616 argLen: 3, 9617 asm: arm.ACMP, 9618 reg: regInfo{ 9619 inputs: []inputInfo{ 9620 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9621 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9622 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9623 }, 9624 }, 9625 }, 9626 { 9627 name: "CMPshiftRLreg", 9628 argLen: 3, 9629 asm: arm.ACMP, 9630 reg: regInfo{ 9631 inputs: []inputInfo{ 9632 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9633 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9634 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9635 }, 9636 }, 9637 }, 9638 { 9639 name: "CMPshiftRAreg", 9640 argLen: 3, 9641 asm: arm.ACMP, 9642 reg: regInfo{ 9643 inputs: []inputInfo{ 9644 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9645 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9646 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9647 }, 9648 }, 9649 }, 9650 { 9651 name: "CMPF0", 9652 argLen: 1, 9653 asm: arm.ACMPF, 9654 reg: regInfo{ 9655 inputs: []inputInfo{ 9656 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9657 }, 9658 }, 9659 }, 9660 { 9661 name: "CMPD0", 9662 argLen: 1, 9663 asm: arm.ACMPD, 9664 reg: regInfo{ 9665 inputs: []inputInfo{ 9666 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9667 }, 9668 }, 9669 }, 9670 { 9671 name: "MOVWconst", 9672 auxType: auxInt32, 9673 argLen: 0, 9674 rematerializeable: true, 9675 asm: arm.AMOVW, 9676 reg: regInfo{ 9677 outputs: []outputInfo{ 9678 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9679 }, 9680 }, 9681 }, 9682 { 9683 name: "MOVFconst", 9684 auxType: auxFloat64, 9685 argLen: 0, 9686 rematerializeable: true, 9687 asm: arm.AMOVF, 9688 reg: regInfo{ 9689 outputs: []outputInfo{ 9690 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9691 }, 9692 }, 9693 }, 9694 { 9695 name: "MOVDconst", 9696 auxType: auxFloat64, 9697 argLen: 0, 9698 rematerializeable: true, 9699 asm: arm.AMOVD, 9700 reg: regInfo{ 9701 outputs: []outputInfo{ 9702 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9703 }, 9704 }, 9705 }, 9706 { 9707 name: "MOVWaddr", 9708 auxType: auxSymOff, 9709 argLen: 1, 9710 rematerializeable: true, 9711 asm: arm.AMOVW, 9712 reg: regInfo{ 9713 inputs: []inputInfo{ 9714 {0, 4294975488}, // SP SB 9715 }, 9716 outputs: []outputInfo{ 9717 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9718 }, 9719 }, 9720 }, 9721 { 9722 name: "MOVBload", 9723 auxType: auxSymOff, 9724 argLen: 2, 9725 faultOnNilArg0: true, 9726 asm: arm.AMOVB, 9727 reg: regInfo{ 9728 inputs: []inputInfo{ 9729 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9730 }, 9731 outputs: []outputInfo{ 9732 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9733 }, 9734 }, 9735 }, 9736 { 9737 name: "MOVBUload", 9738 auxType: auxSymOff, 9739 argLen: 2, 9740 faultOnNilArg0: true, 9741 asm: arm.AMOVBU, 9742 reg: regInfo{ 9743 inputs: []inputInfo{ 9744 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9745 }, 9746 outputs: []outputInfo{ 9747 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9748 }, 9749 }, 9750 }, 9751 { 9752 name: "MOVHload", 9753 auxType: auxSymOff, 9754 argLen: 2, 9755 faultOnNilArg0: true, 9756 asm: arm.AMOVH, 9757 reg: regInfo{ 9758 inputs: []inputInfo{ 9759 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9760 }, 9761 outputs: []outputInfo{ 9762 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9763 }, 9764 }, 9765 }, 9766 { 9767 name: "MOVHUload", 9768 auxType: auxSymOff, 9769 argLen: 2, 9770 faultOnNilArg0: true, 9771 asm: arm.AMOVHU, 9772 reg: regInfo{ 9773 inputs: []inputInfo{ 9774 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9775 }, 9776 outputs: []outputInfo{ 9777 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9778 }, 9779 }, 9780 }, 9781 { 9782 name: "MOVWload", 9783 auxType: auxSymOff, 9784 argLen: 2, 9785 faultOnNilArg0: true, 9786 asm: arm.AMOVW, 9787 reg: regInfo{ 9788 inputs: []inputInfo{ 9789 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9790 }, 9791 outputs: []outputInfo{ 9792 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9793 }, 9794 }, 9795 }, 9796 { 9797 name: "MOVFload", 9798 auxType: auxSymOff, 9799 argLen: 2, 9800 faultOnNilArg0: true, 9801 asm: arm.AMOVF, 9802 reg: regInfo{ 9803 inputs: []inputInfo{ 9804 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9805 }, 9806 outputs: []outputInfo{ 9807 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9808 }, 9809 }, 9810 }, 9811 { 9812 name: "MOVDload", 9813 auxType: auxSymOff, 9814 argLen: 2, 9815 faultOnNilArg0: true, 9816 asm: arm.AMOVD, 9817 reg: regInfo{ 9818 inputs: []inputInfo{ 9819 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9820 }, 9821 outputs: []outputInfo{ 9822 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9823 }, 9824 }, 9825 }, 9826 { 9827 name: "MOVBstore", 9828 auxType: auxSymOff, 9829 argLen: 3, 9830 faultOnNilArg0: true, 9831 asm: arm.AMOVB, 9832 reg: regInfo{ 9833 inputs: []inputInfo{ 9834 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9835 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9836 }, 9837 }, 9838 }, 9839 { 9840 name: "MOVHstore", 9841 auxType: auxSymOff, 9842 argLen: 3, 9843 faultOnNilArg0: true, 9844 asm: arm.AMOVH, 9845 reg: regInfo{ 9846 inputs: []inputInfo{ 9847 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9848 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9849 }, 9850 }, 9851 }, 9852 { 9853 name: "MOVWstore", 9854 auxType: auxSymOff, 9855 argLen: 3, 9856 faultOnNilArg0: true, 9857 asm: arm.AMOVW, 9858 reg: regInfo{ 9859 inputs: []inputInfo{ 9860 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9861 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9862 }, 9863 }, 9864 }, 9865 { 9866 name: "MOVFstore", 9867 auxType: auxSymOff, 9868 argLen: 3, 9869 faultOnNilArg0: true, 9870 asm: arm.AMOVF, 9871 reg: regInfo{ 9872 inputs: []inputInfo{ 9873 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9874 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9875 }, 9876 }, 9877 }, 9878 { 9879 name: "MOVDstore", 9880 auxType: auxSymOff, 9881 argLen: 3, 9882 faultOnNilArg0: true, 9883 asm: arm.AMOVD, 9884 reg: regInfo{ 9885 inputs: []inputInfo{ 9886 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9887 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9888 }, 9889 }, 9890 }, 9891 { 9892 name: "MOVWloadidx", 9893 argLen: 3, 9894 asm: arm.AMOVW, 9895 reg: regInfo{ 9896 inputs: []inputInfo{ 9897 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9898 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9899 }, 9900 outputs: []outputInfo{ 9901 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9902 }, 9903 }, 9904 }, 9905 { 9906 name: "MOVWloadshiftLL", 9907 auxType: auxInt32, 9908 argLen: 3, 9909 asm: arm.AMOVW, 9910 reg: regInfo{ 9911 inputs: []inputInfo{ 9912 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9913 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9914 }, 9915 outputs: []outputInfo{ 9916 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9917 }, 9918 }, 9919 }, 9920 { 9921 name: "MOVWloadshiftRL", 9922 auxType: auxInt32, 9923 argLen: 3, 9924 asm: arm.AMOVW, 9925 reg: regInfo{ 9926 inputs: []inputInfo{ 9927 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9928 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9929 }, 9930 outputs: []outputInfo{ 9931 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9932 }, 9933 }, 9934 }, 9935 { 9936 name: "MOVWloadshiftRA", 9937 auxType: auxInt32, 9938 argLen: 3, 9939 asm: arm.AMOVW, 9940 reg: regInfo{ 9941 inputs: []inputInfo{ 9942 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9943 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9944 }, 9945 outputs: []outputInfo{ 9946 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9947 }, 9948 }, 9949 }, 9950 { 9951 name: "MOVWstoreidx", 9952 argLen: 4, 9953 asm: arm.AMOVW, 9954 reg: regInfo{ 9955 inputs: []inputInfo{ 9956 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9957 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9958 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9959 }, 9960 }, 9961 }, 9962 { 9963 name: "MOVWstoreshiftLL", 9964 auxType: auxInt32, 9965 argLen: 4, 9966 asm: arm.AMOVW, 9967 reg: regInfo{ 9968 inputs: []inputInfo{ 9969 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9970 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9971 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9972 }, 9973 }, 9974 }, 9975 { 9976 name: "MOVWstoreshiftRL", 9977 auxType: auxInt32, 9978 argLen: 4, 9979 asm: arm.AMOVW, 9980 reg: regInfo{ 9981 inputs: []inputInfo{ 9982 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9983 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9984 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9985 }, 9986 }, 9987 }, 9988 { 9989 name: "MOVWstoreshiftRA", 9990 auxType: auxInt32, 9991 argLen: 4, 9992 asm: arm.AMOVW, 9993 reg: regInfo{ 9994 inputs: []inputInfo{ 9995 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9996 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9997 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9998 }, 9999 }, 10000 }, 10001 { 10002 name: "MOVBreg", 10003 argLen: 1, 10004 asm: arm.AMOVBS, 10005 reg: regInfo{ 10006 inputs: []inputInfo{ 10007 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10008 }, 10009 outputs: []outputInfo{ 10010 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10011 }, 10012 }, 10013 }, 10014 { 10015 name: "MOVBUreg", 10016 argLen: 1, 10017 asm: arm.AMOVBU, 10018 reg: regInfo{ 10019 inputs: []inputInfo{ 10020 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10021 }, 10022 outputs: []outputInfo{ 10023 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10024 }, 10025 }, 10026 }, 10027 { 10028 name: "MOVHreg", 10029 argLen: 1, 10030 asm: arm.AMOVHS, 10031 reg: regInfo{ 10032 inputs: []inputInfo{ 10033 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10034 }, 10035 outputs: []outputInfo{ 10036 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10037 }, 10038 }, 10039 }, 10040 { 10041 name: "MOVHUreg", 10042 argLen: 1, 10043 asm: arm.AMOVHU, 10044 reg: regInfo{ 10045 inputs: []inputInfo{ 10046 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10047 }, 10048 outputs: []outputInfo{ 10049 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10050 }, 10051 }, 10052 }, 10053 { 10054 name: "MOVWreg", 10055 argLen: 1, 10056 asm: arm.AMOVW, 10057 reg: regInfo{ 10058 inputs: []inputInfo{ 10059 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10060 }, 10061 outputs: []outputInfo{ 10062 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10063 }, 10064 }, 10065 }, 10066 { 10067 name: "MOVWnop", 10068 argLen: 1, 10069 resultInArg0: true, 10070 reg: regInfo{ 10071 inputs: []inputInfo{ 10072 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10073 }, 10074 outputs: []outputInfo{ 10075 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10076 }, 10077 }, 10078 }, 10079 { 10080 name: "MOVWF", 10081 argLen: 1, 10082 asm: arm.AMOVWF, 10083 reg: regInfo{ 10084 inputs: []inputInfo{ 10085 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10086 }, 10087 outputs: []outputInfo{ 10088 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10089 }, 10090 }, 10091 }, 10092 { 10093 name: "MOVWD", 10094 argLen: 1, 10095 asm: arm.AMOVWD, 10096 reg: regInfo{ 10097 inputs: []inputInfo{ 10098 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10099 }, 10100 outputs: []outputInfo{ 10101 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10102 }, 10103 }, 10104 }, 10105 { 10106 name: "MOVWUF", 10107 argLen: 1, 10108 asm: arm.AMOVWF, 10109 reg: regInfo{ 10110 inputs: []inputInfo{ 10111 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10112 }, 10113 outputs: []outputInfo{ 10114 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10115 }, 10116 }, 10117 }, 10118 { 10119 name: "MOVWUD", 10120 argLen: 1, 10121 asm: arm.AMOVWD, 10122 reg: regInfo{ 10123 inputs: []inputInfo{ 10124 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10125 }, 10126 outputs: []outputInfo{ 10127 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10128 }, 10129 }, 10130 }, 10131 { 10132 name: "MOVFW", 10133 argLen: 1, 10134 asm: arm.AMOVFW, 10135 reg: regInfo{ 10136 inputs: []inputInfo{ 10137 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10138 }, 10139 outputs: []outputInfo{ 10140 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10141 }, 10142 }, 10143 }, 10144 { 10145 name: "MOVDW", 10146 argLen: 1, 10147 asm: arm.AMOVDW, 10148 reg: regInfo{ 10149 inputs: []inputInfo{ 10150 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10151 }, 10152 outputs: []outputInfo{ 10153 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10154 }, 10155 }, 10156 }, 10157 { 10158 name: "MOVFWU", 10159 argLen: 1, 10160 asm: arm.AMOVFW, 10161 reg: regInfo{ 10162 inputs: []inputInfo{ 10163 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10164 }, 10165 outputs: []outputInfo{ 10166 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10167 }, 10168 }, 10169 }, 10170 { 10171 name: "MOVDWU", 10172 argLen: 1, 10173 asm: arm.AMOVDW, 10174 reg: regInfo{ 10175 inputs: []inputInfo{ 10176 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10177 }, 10178 outputs: []outputInfo{ 10179 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10180 }, 10181 }, 10182 }, 10183 { 10184 name: "MOVFD", 10185 argLen: 1, 10186 asm: arm.AMOVFD, 10187 reg: regInfo{ 10188 inputs: []inputInfo{ 10189 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10190 }, 10191 outputs: []outputInfo{ 10192 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10193 }, 10194 }, 10195 }, 10196 { 10197 name: "MOVDF", 10198 argLen: 1, 10199 asm: arm.AMOVDF, 10200 reg: regInfo{ 10201 inputs: []inputInfo{ 10202 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10203 }, 10204 outputs: []outputInfo{ 10205 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10206 }, 10207 }, 10208 }, 10209 { 10210 name: "CMOVWHSconst", 10211 auxType: auxInt32, 10212 argLen: 2, 10213 resultInArg0: true, 10214 asm: arm.AMOVW, 10215 reg: regInfo{ 10216 inputs: []inputInfo{ 10217 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10218 }, 10219 outputs: []outputInfo{ 10220 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10221 }, 10222 }, 10223 }, 10224 { 10225 name: "CMOVWLSconst", 10226 auxType: auxInt32, 10227 argLen: 2, 10228 resultInArg0: true, 10229 asm: arm.AMOVW, 10230 reg: regInfo{ 10231 inputs: []inputInfo{ 10232 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10233 }, 10234 outputs: []outputInfo{ 10235 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10236 }, 10237 }, 10238 }, 10239 { 10240 name: "SRAcond", 10241 argLen: 3, 10242 asm: arm.ASRA, 10243 reg: regInfo{ 10244 inputs: []inputInfo{ 10245 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10246 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10247 }, 10248 outputs: []outputInfo{ 10249 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10250 }, 10251 }, 10252 }, 10253 { 10254 name: "CALLstatic", 10255 auxType: auxSymOff, 10256 argLen: 1, 10257 clobberFlags: true, 10258 call: true, 10259 reg: regInfo{ 10260 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10261 }, 10262 }, 10263 { 10264 name: "CALLclosure", 10265 auxType: auxInt64, 10266 argLen: 3, 10267 clobberFlags: true, 10268 call: true, 10269 reg: regInfo{ 10270 inputs: []inputInfo{ 10271 {1, 128}, // R7 10272 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 10273 }, 10274 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10275 }, 10276 }, 10277 { 10278 name: "CALLdefer", 10279 auxType: auxInt64, 10280 argLen: 1, 10281 clobberFlags: true, 10282 call: true, 10283 reg: regInfo{ 10284 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10285 }, 10286 }, 10287 { 10288 name: "CALLgo", 10289 auxType: auxInt64, 10290 argLen: 1, 10291 clobberFlags: true, 10292 call: true, 10293 reg: regInfo{ 10294 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10295 }, 10296 }, 10297 { 10298 name: "CALLinter", 10299 auxType: auxInt64, 10300 argLen: 2, 10301 clobberFlags: true, 10302 call: true, 10303 reg: regInfo{ 10304 inputs: []inputInfo{ 10305 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10306 }, 10307 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10308 }, 10309 }, 10310 { 10311 name: "LoweredNilCheck", 10312 argLen: 2, 10313 nilCheck: true, 10314 faultOnNilArg0: true, 10315 reg: regInfo{ 10316 inputs: []inputInfo{ 10317 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10318 }, 10319 }, 10320 }, 10321 { 10322 name: "Equal", 10323 argLen: 1, 10324 reg: regInfo{ 10325 outputs: []outputInfo{ 10326 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10327 }, 10328 }, 10329 }, 10330 { 10331 name: "NotEqual", 10332 argLen: 1, 10333 reg: regInfo{ 10334 outputs: []outputInfo{ 10335 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10336 }, 10337 }, 10338 }, 10339 { 10340 name: "LessThan", 10341 argLen: 1, 10342 reg: regInfo{ 10343 outputs: []outputInfo{ 10344 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10345 }, 10346 }, 10347 }, 10348 { 10349 name: "LessEqual", 10350 argLen: 1, 10351 reg: regInfo{ 10352 outputs: []outputInfo{ 10353 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10354 }, 10355 }, 10356 }, 10357 { 10358 name: "GreaterThan", 10359 argLen: 1, 10360 reg: regInfo{ 10361 outputs: []outputInfo{ 10362 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10363 }, 10364 }, 10365 }, 10366 { 10367 name: "GreaterEqual", 10368 argLen: 1, 10369 reg: regInfo{ 10370 outputs: []outputInfo{ 10371 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10372 }, 10373 }, 10374 }, 10375 { 10376 name: "LessThanU", 10377 argLen: 1, 10378 reg: regInfo{ 10379 outputs: []outputInfo{ 10380 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10381 }, 10382 }, 10383 }, 10384 { 10385 name: "LessEqualU", 10386 argLen: 1, 10387 reg: regInfo{ 10388 outputs: []outputInfo{ 10389 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10390 }, 10391 }, 10392 }, 10393 { 10394 name: "GreaterThanU", 10395 argLen: 1, 10396 reg: regInfo{ 10397 outputs: []outputInfo{ 10398 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10399 }, 10400 }, 10401 }, 10402 { 10403 name: "GreaterEqualU", 10404 argLen: 1, 10405 reg: regInfo{ 10406 outputs: []outputInfo{ 10407 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10408 }, 10409 }, 10410 }, 10411 { 10412 name: "DUFFZERO", 10413 auxType: auxInt64, 10414 argLen: 3, 10415 faultOnNilArg0: true, 10416 reg: regInfo{ 10417 inputs: []inputInfo{ 10418 {0, 2}, // R1 10419 {1, 1}, // R0 10420 }, 10421 clobbers: 16386, // R1 R14 10422 }, 10423 }, 10424 { 10425 name: "DUFFCOPY", 10426 auxType: auxInt64, 10427 argLen: 3, 10428 faultOnNilArg0: true, 10429 faultOnNilArg1: true, 10430 reg: regInfo{ 10431 inputs: []inputInfo{ 10432 {0, 4}, // R2 10433 {1, 2}, // R1 10434 }, 10435 clobbers: 16391, // R0 R1 R2 R14 10436 }, 10437 }, 10438 { 10439 name: "LoweredZero", 10440 auxType: auxInt64, 10441 argLen: 4, 10442 clobberFlags: true, 10443 faultOnNilArg0: true, 10444 reg: regInfo{ 10445 inputs: []inputInfo{ 10446 {0, 2}, // R1 10447 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10448 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10449 }, 10450 clobbers: 2, // R1 10451 }, 10452 }, 10453 { 10454 name: "LoweredMove", 10455 auxType: auxInt64, 10456 argLen: 4, 10457 clobberFlags: true, 10458 faultOnNilArg0: true, 10459 faultOnNilArg1: true, 10460 reg: regInfo{ 10461 inputs: []inputInfo{ 10462 {0, 4}, // R2 10463 {1, 2}, // R1 10464 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10465 }, 10466 clobbers: 6, // R1 R2 10467 }, 10468 }, 10469 { 10470 name: "LoweredGetClosurePtr", 10471 argLen: 0, 10472 reg: regInfo{ 10473 outputs: []outputInfo{ 10474 {0, 128}, // R7 10475 }, 10476 }, 10477 }, 10478 { 10479 name: "MOVWconvert", 10480 argLen: 2, 10481 asm: arm.AMOVW, 10482 reg: regInfo{ 10483 inputs: []inputInfo{ 10484 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10485 }, 10486 outputs: []outputInfo{ 10487 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10488 }, 10489 }, 10490 }, 10491 { 10492 name: "FlagEQ", 10493 argLen: 0, 10494 reg: regInfo{}, 10495 }, 10496 { 10497 name: "FlagLT_ULT", 10498 argLen: 0, 10499 reg: regInfo{}, 10500 }, 10501 { 10502 name: "FlagLT_UGT", 10503 argLen: 0, 10504 reg: regInfo{}, 10505 }, 10506 { 10507 name: "FlagGT_UGT", 10508 argLen: 0, 10509 reg: regInfo{}, 10510 }, 10511 { 10512 name: "FlagGT_ULT", 10513 argLen: 0, 10514 reg: regInfo{}, 10515 }, 10516 { 10517 name: "InvertFlags", 10518 argLen: 1, 10519 reg: regInfo{}, 10520 }, 10521 10522 { 10523 name: "ADD", 10524 argLen: 2, 10525 commutative: true, 10526 asm: arm64.AADD, 10527 reg: regInfo{ 10528 inputs: []inputInfo{ 10529 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10530 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10531 }, 10532 outputs: []outputInfo{ 10533 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10534 }, 10535 }, 10536 }, 10537 { 10538 name: "ADDconst", 10539 auxType: auxInt64, 10540 argLen: 1, 10541 asm: arm64.AADD, 10542 reg: regInfo{ 10543 inputs: []inputInfo{ 10544 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 10545 }, 10546 outputs: []outputInfo{ 10547 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10548 }, 10549 }, 10550 }, 10551 { 10552 name: "SUB", 10553 argLen: 2, 10554 asm: arm64.ASUB, 10555 reg: regInfo{ 10556 inputs: []inputInfo{ 10557 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10558 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10559 }, 10560 outputs: []outputInfo{ 10561 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10562 }, 10563 }, 10564 }, 10565 { 10566 name: "SUBconst", 10567 auxType: auxInt64, 10568 argLen: 1, 10569 asm: arm64.ASUB, 10570 reg: regInfo{ 10571 inputs: []inputInfo{ 10572 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10573 }, 10574 outputs: []outputInfo{ 10575 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10576 }, 10577 }, 10578 }, 10579 { 10580 name: "MUL", 10581 argLen: 2, 10582 commutative: true, 10583 asm: arm64.AMUL, 10584 reg: regInfo{ 10585 inputs: []inputInfo{ 10586 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10587 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10588 }, 10589 outputs: []outputInfo{ 10590 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10591 }, 10592 }, 10593 }, 10594 { 10595 name: "MULW", 10596 argLen: 2, 10597 commutative: true, 10598 asm: arm64.AMULW, 10599 reg: regInfo{ 10600 inputs: []inputInfo{ 10601 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10602 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10603 }, 10604 outputs: []outputInfo{ 10605 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10606 }, 10607 }, 10608 }, 10609 { 10610 name: "MULH", 10611 argLen: 2, 10612 commutative: true, 10613 asm: arm64.ASMULH, 10614 reg: regInfo{ 10615 inputs: []inputInfo{ 10616 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10617 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10618 }, 10619 outputs: []outputInfo{ 10620 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10621 }, 10622 }, 10623 }, 10624 { 10625 name: "UMULH", 10626 argLen: 2, 10627 commutative: true, 10628 asm: arm64.AUMULH, 10629 reg: regInfo{ 10630 inputs: []inputInfo{ 10631 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10632 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10633 }, 10634 outputs: []outputInfo{ 10635 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10636 }, 10637 }, 10638 }, 10639 { 10640 name: "MULL", 10641 argLen: 2, 10642 commutative: true, 10643 asm: arm64.ASMULL, 10644 reg: regInfo{ 10645 inputs: []inputInfo{ 10646 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10647 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10648 }, 10649 outputs: []outputInfo{ 10650 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10651 }, 10652 }, 10653 }, 10654 { 10655 name: "UMULL", 10656 argLen: 2, 10657 commutative: true, 10658 asm: arm64.AUMULL, 10659 reg: regInfo{ 10660 inputs: []inputInfo{ 10661 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10662 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10663 }, 10664 outputs: []outputInfo{ 10665 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10666 }, 10667 }, 10668 }, 10669 { 10670 name: "DIV", 10671 argLen: 2, 10672 asm: arm64.ASDIV, 10673 reg: regInfo{ 10674 inputs: []inputInfo{ 10675 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10676 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10677 }, 10678 outputs: []outputInfo{ 10679 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10680 }, 10681 }, 10682 }, 10683 { 10684 name: "UDIV", 10685 argLen: 2, 10686 asm: arm64.AUDIV, 10687 reg: regInfo{ 10688 inputs: []inputInfo{ 10689 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10690 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10691 }, 10692 outputs: []outputInfo{ 10693 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10694 }, 10695 }, 10696 }, 10697 { 10698 name: "DIVW", 10699 argLen: 2, 10700 asm: arm64.ASDIVW, 10701 reg: regInfo{ 10702 inputs: []inputInfo{ 10703 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10704 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10705 }, 10706 outputs: []outputInfo{ 10707 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10708 }, 10709 }, 10710 }, 10711 { 10712 name: "UDIVW", 10713 argLen: 2, 10714 asm: arm64.AUDIVW, 10715 reg: regInfo{ 10716 inputs: []inputInfo{ 10717 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10718 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10719 }, 10720 outputs: []outputInfo{ 10721 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10722 }, 10723 }, 10724 }, 10725 { 10726 name: "MOD", 10727 argLen: 2, 10728 asm: arm64.AREM, 10729 reg: regInfo{ 10730 inputs: []inputInfo{ 10731 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10732 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10733 }, 10734 outputs: []outputInfo{ 10735 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10736 }, 10737 }, 10738 }, 10739 { 10740 name: "UMOD", 10741 argLen: 2, 10742 asm: arm64.AUREM, 10743 reg: regInfo{ 10744 inputs: []inputInfo{ 10745 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10746 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10747 }, 10748 outputs: []outputInfo{ 10749 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10750 }, 10751 }, 10752 }, 10753 { 10754 name: "MODW", 10755 argLen: 2, 10756 asm: arm64.AREMW, 10757 reg: regInfo{ 10758 inputs: []inputInfo{ 10759 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10760 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10761 }, 10762 outputs: []outputInfo{ 10763 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10764 }, 10765 }, 10766 }, 10767 { 10768 name: "UMODW", 10769 argLen: 2, 10770 asm: arm64.AUREMW, 10771 reg: regInfo{ 10772 inputs: []inputInfo{ 10773 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10774 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10775 }, 10776 outputs: []outputInfo{ 10777 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10778 }, 10779 }, 10780 }, 10781 { 10782 name: "FADDS", 10783 argLen: 2, 10784 commutative: true, 10785 asm: arm64.AFADDS, 10786 reg: regInfo{ 10787 inputs: []inputInfo{ 10788 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10789 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10790 }, 10791 outputs: []outputInfo{ 10792 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10793 }, 10794 }, 10795 }, 10796 { 10797 name: "FADDD", 10798 argLen: 2, 10799 commutative: true, 10800 asm: arm64.AFADDD, 10801 reg: regInfo{ 10802 inputs: []inputInfo{ 10803 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10804 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10805 }, 10806 outputs: []outputInfo{ 10807 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10808 }, 10809 }, 10810 }, 10811 { 10812 name: "FSUBS", 10813 argLen: 2, 10814 asm: arm64.AFSUBS, 10815 reg: regInfo{ 10816 inputs: []inputInfo{ 10817 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10818 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10819 }, 10820 outputs: []outputInfo{ 10821 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10822 }, 10823 }, 10824 }, 10825 { 10826 name: "FSUBD", 10827 argLen: 2, 10828 asm: arm64.AFSUBD, 10829 reg: regInfo{ 10830 inputs: []inputInfo{ 10831 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10832 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10833 }, 10834 outputs: []outputInfo{ 10835 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10836 }, 10837 }, 10838 }, 10839 { 10840 name: "FMULS", 10841 argLen: 2, 10842 commutative: true, 10843 asm: arm64.AFMULS, 10844 reg: regInfo{ 10845 inputs: []inputInfo{ 10846 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10847 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10848 }, 10849 outputs: []outputInfo{ 10850 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10851 }, 10852 }, 10853 }, 10854 { 10855 name: "FMULD", 10856 argLen: 2, 10857 commutative: true, 10858 asm: arm64.AFMULD, 10859 reg: regInfo{ 10860 inputs: []inputInfo{ 10861 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10862 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10863 }, 10864 outputs: []outputInfo{ 10865 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10866 }, 10867 }, 10868 }, 10869 { 10870 name: "FDIVS", 10871 argLen: 2, 10872 asm: arm64.AFDIVS, 10873 reg: regInfo{ 10874 inputs: []inputInfo{ 10875 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10876 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10877 }, 10878 outputs: []outputInfo{ 10879 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10880 }, 10881 }, 10882 }, 10883 { 10884 name: "FDIVD", 10885 argLen: 2, 10886 asm: arm64.AFDIVD, 10887 reg: regInfo{ 10888 inputs: []inputInfo{ 10889 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10890 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10891 }, 10892 outputs: []outputInfo{ 10893 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10894 }, 10895 }, 10896 }, 10897 { 10898 name: "AND", 10899 argLen: 2, 10900 commutative: true, 10901 asm: arm64.AAND, 10902 reg: regInfo{ 10903 inputs: []inputInfo{ 10904 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10905 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10906 }, 10907 outputs: []outputInfo{ 10908 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10909 }, 10910 }, 10911 }, 10912 { 10913 name: "ANDconst", 10914 auxType: auxInt64, 10915 argLen: 1, 10916 asm: arm64.AAND, 10917 reg: regInfo{ 10918 inputs: []inputInfo{ 10919 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10920 }, 10921 outputs: []outputInfo{ 10922 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10923 }, 10924 }, 10925 }, 10926 { 10927 name: "OR", 10928 argLen: 2, 10929 commutative: true, 10930 asm: arm64.AORR, 10931 reg: regInfo{ 10932 inputs: []inputInfo{ 10933 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10934 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10935 }, 10936 outputs: []outputInfo{ 10937 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10938 }, 10939 }, 10940 }, 10941 { 10942 name: "ORconst", 10943 auxType: auxInt64, 10944 argLen: 1, 10945 asm: arm64.AORR, 10946 reg: regInfo{ 10947 inputs: []inputInfo{ 10948 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10949 }, 10950 outputs: []outputInfo{ 10951 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10952 }, 10953 }, 10954 }, 10955 { 10956 name: "XOR", 10957 argLen: 2, 10958 commutative: true, 10959 asm: arm64.AEOR, 10960 reg: regInfo{ 10961 inputs: []inputInfo{ 10962 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10963 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10964 }, 10965 outputs: []outputInfo{ 10966 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10967 }, 10968 }, 10969 }, 10970 { 10971 name: "XORconst", 10972 auxType: auxInt64, 10973 argLen: 1, 10974 asm: arm64.AEOR, 10975 reg: regInfo{ 10976 inputs: []inputInfo{ 10977 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10978 }, 10979 outputs: []outputInfo{ 10980 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10981 }, 10982 }, 10983 }, 10984 { 10985 name: "BIC", 10986 argLen: 2, 10987 asm: arm64.ABIC, 10988 reg: regInfo{ 10989 inputs: []inputInfo{ 10990 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10991 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10992 }, 10993 outputs: []outputInfo{ 10994 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10995 }, 10996 }, 10997 }, 10998 { 10999 name: "BICconst", 11000 auxType: auxInt64, 11001 argLen: 1, 11002 asm: arm64.ABIC, 11003 reg: regInfo{ 11004 inputs: []inputInfo{ 11005 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11006 }, 11007 outputs: []outputInfo{ 11008 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11009 }, 11010 }, 11011 }, 11012 { 11013 name: "MVN", 11014 argLen: 1, 11015 asm: arm64.AMVN, 11016 reg: regInfo{ 11017 inputs: []inputInfo{ 11018 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11019 }, 11020 outputs: []outputInfo{ 11021 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11022 }, 11023 }, 11024 }, 11025 { 11026 name: "NEG", 11027 argLen: 1, 11028 asm: arm64.ANEG, 11029 reg: regInfo{ 11030 inputs: []inputInfo{ 11031 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11032 }, 11033 outputs: []outputInfo{ 11034 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11035 }, 11036 }, 11037 }, 11038 { 11039 name: "FNEGS", 11040 argLen: 1, 11041 asm: arm64.AFNEGS, 11042 reg: regInfo{ 11043 inputs: []inputInfo{ 11044 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11045 }, 11046 outputs: []outputInfo{ 11047 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11048 }, 11049 }, 11050 }, 11051 { 11052 name: "FNEGD", 11053 argLen: 1, 11054 asm: arm64.AFNEGD, 11055 reg: regInfo{ 11056 inputs: []inputInfo{ 11057 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11058 }, 11059 outputs: []outputInfo{ 11060 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11061 }, 11062 }, 11063 }, 11064 { 11065 name: "FSQRTD", 11066 argLen: 1, 11067 asm: arm64.AFSQRTD, 11068 reg: regInfo{ 11069 inputs: []inputInfo{ 11070 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11071 }, 11072 outputs: []outputInfo{ 11073 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11074 }, 11075 }, 11076 }, 11077 { 11078 name: "REV", 11079 argLen: 1, 11080 asm: arm64.AREV, 11081 reg: regInfo{ 11082 inputs: []inputInfo{ 11083 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11084 }, 11085 outputs: []outputInfo{ 11086 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11087 }, 11088 }, 11089 }, 11090 { 11091 name: "REVW", 11092 argLen: 1, 11093 asm: arm64.AREVW, 11094 reg: regInfo{ 11095 inputs: []inputInfo{ 11096 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11097 }, 11098 outputs: []outputInfo{ 11099 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11100 }, 11101 }, 11102 }, 11103 { 11104 name: "REV16W", 11105 argLen: 1, 11106 asm: arm64.AREV16W, 11107 reg: regInfo{ 11108 inputs: []inputInfo{ 11109 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11110 }, 11111 outputs: []outputInfo{ 11112 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11113 }, 11114 }, 11115 }, 11116 { 11117 name: "RBIT", 11118 argLen: 1, 11119 asm: arm64.ARBIT, 11120 reg: regInfo{ 11121 inputs: []inputInfo{ 11122 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11123 }, 11124 outputs: []outputInfo{ 11125 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11126 }, 11127 }, 11128 }, 11129 { 11130 name: "RBITW", 11131 argLen: 1, 11132 asm: arm64.ARBITW, 11133 reg: regInfo{ 11134 inputs: []inputInfo{ 11135 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11136 }, 11137 outputs: []outputInfo{ 11138 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11139 }, 11140 }, 11141 }, 11142 { 11143 name: "CLZ", 11144 argLen: 1, 11145 asm: arm64.ACLZ, 11146 reg: regInfo{ 11147 inputs: []inputInfo{ 11148 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11149 }, 11150 outputs: []outputInfo{ 11151 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11152 }, 11153 }, 11154 }, 11155 { 11156 name: "CLZW", 11157 argLen: 1, 11158 asm: arm64.ACLZW, 11159 reg: regInfo{ 11160 inputs: []inputInfo{ 11161 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11162 }, 11163 outputs: []outputInfo{ 11164 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11165 }, 11166 }, 11167 }, 11168 { 11169 name: "SLL", 11170 argLen: 2, 11171 asm: arm64.ALSL, 11172 reg: regInfo{ 11173 inputs: []inputInfo{ 11174 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11175 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11176 }, 11177 outputs: []outputInfo{ 11178 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11179 }, 11180 }, 11181 }, 11182 { 11183 name: "SLLconst", 11184 auxType: auxInt64, 11185 argLen: 1, 11186 asm: arm64.ALSL, 11187 reg: regInfo{ 11188 inputs: []inputInfo{ 11189 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11190 }, 11191 outputs: []outputInfo{ 11192 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11193 }, 11194 }, 11195 }, 11196 { 11197 name: "SRL", 11198 argLen: 2, 11199 asm: arm64.ALSR, 11200 reg: regInfo{ 11201 inputs: []inputInfo{ 11202 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11203 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11204 }, 11205 outputs: []outputInfo{ 11206 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11207 }, 11208 }, 11209 }, 11210 { 11211 name: "SRLconst", 11212 auxType: auxInt64, 11213 argLen: 1, 11214 asm: arm64.ALSR, 11215 reg: regInfo{ 11216 inputs: []inputInfo{ 11217 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11218 }, 11219 outputs: []outputInfo{ 11220 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11221 }, 11222 }, 11223 }, 11224 { 11225 name: "SRA", 11226 argLen: 2, 11227 asm: arm64.AASR, 11228 reg: regInfo{ 11229 inputs: []inputInfo{ 11230 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11231 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11232 }, 11233 outputs: []outputInfo{ 11234 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11235 }, 11236 }, 11237 }, 11238 { 11239 name: "SRAconst", 11240 auxType: auxInt64, 11241 argLen: 1, 11242 asm: arm64.AASR, 11243 reg: regInfo{ 11244 inputs: []inputInfo{ 11245 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11246 }, 11247 outputs: []outputInfo{ 11248 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11249 }, 11250 }, 11251 }, 11252 { 11253 name: "RORconst", 11254 auxType: auxInt64, 11255 argLen: 1, 11256 asm: arm64.AROR, 11257 reg: regInfo{ 11258 inputs: []inputInfo{ 11259 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11260 }, 11261 outputs: []outputInfo{ 11262 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11263 }, 11264 }, 11265 }, 11266 { 11267 name: "RORWconst", 11268 auxType: auxInt64, 11269 argLen: 1, 11270 asm: arm64.ARORW, 11271 reg: regInfo{ 11272 inputs: []inputInfo{ 11273 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11274 }, 11275 outputs: []outputInfo{ 11276 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11277 }, 11278 }, 11279 }, 11280 { 11281 name: "CMP", 11282 argLen: 2, 11283 asm: arm64.ACMP, 11284 reg: regInfo{ 11285 inputs: []inputInfo{ 11286 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11287 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11288 }, 11289 }, 11290 }, 11291 { 11292 name: "CMPconst", 11293 auxType: auxInt64, 11294 argLen: 1, 11295 asm: arm64.ACMP, 11296 reg: regInfo{ 11297 inputs: []inputInfo{ 11298 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11299 }, 11300 }, 11301 }, 11302 { 11303 name: "CMPW", 11304 argLen: 2, 11305 asm: arm64.ACMPW, 11306 reg: regInfo{ 11307 inputs: []inputInfo{ 11308 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11309 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11310 }, 11311 }, 11312 }, 11313 { 11314 name: "CMPWconst", 11315 auxType: auxInt32, 11316 argLen: 1, 11317 asm: arm64.ACMPW, 11318 reg: regInfo{ 11319 inputs: []inputInfo{ 11320 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11321 }, 11322 }, 11323 }, 11324 { 11325 name: "CMN", 11326 argLen: 2, 11327 asm: arm64.ACMN, 11328 reg: regInfo{ 11329 inputs: []inputInfo{ 11330 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11331 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11332 }, 11333 }, 11334 }, 11335 { 11336 name: "CMNconst", 11337 auxType: auxInt64, 11338 argLen: 1, 11339 asm: arm64.ACMN, 11340 reg: regInfo{ 11341 inputs: []inputInfo{ 11342 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11343 }, 11344 }, 11345 }, 11346 { 11347 name: "CMNW", 11348 argLen: 2, 11349 asm: arm64.ACMNW, 11350 reg: regInfo{ 11351 inputs: []inputInfo{ 11352 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11353 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11354 }, 11355 }, 11356 }, 11357 { 11358 name: "CMNWconst", 11359 auxType: auxInt32, 11360 argLen: 1, 11361 asm: arm64.ACMNW, 11362 reg: regInfo{ 11363 inputs: []inputInfo{ 11364 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11365 }, 11366 }, 11367 }, 11368 { 11369 name: "FCMPS", 11370 argLen: 2, 11371 asm: arm64.AFCMPS, 11372 reg: regInfo{ 11373 inputs: []inputInfo{ 11374 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11375 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11376 }, 11377 }, 11378 }, 11379 { 11380 name: "FCMPD", 11381 argLen: 2, 11382 asm: arm64.AFCMPD, 11383 reg: regInfo{ 11384 inputs: []inputInfo{ 11385 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11386 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11387 }, 11388 }, 11389 }, 11390 { 11391 name: "ADDshiftLL", 11392 auxType: auxInt64, 11393 argLen: 2, 11394 asm: arm64.AADD, 11395 reg: regInfo{ 11396 inputs: []inputInfo{ 11397 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11398 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11399 }, 11400 outputs: []outputInfo{ 11401 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11402 }, 11403 }, 11404 }, 11405 { 11406 name: "ADDshiftRL", 11407 auxType: auxInt64, 11408 argLen: 2, 11409 asm: arm64.AADD, 11410 reg: regInfo{ 11411 inputs: []inputInfo{ 11412 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11413 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11414 }, 11415 outputs: []outputInfo{ 11416 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11417 }, 11418 }, 11419 }, 11420 { 11421 name: "ADDshiftRA", 11422 auxType: auxInt64, 11423 argLen: 2, 11424 asm: arm64.AADD, 11425 reg: regInfo{ 11426 inputs: []inputInfo{ 11427 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11428 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11429 }, 11430 outputs: []outputInfo{ 11431 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11432 }, 11433 }, 11434 }, 11435 { 11436 name: "SUBshiftLL", 11437 auxType: auxInt64, 11438 argLen: 2, 11439 asm: arm64.ASUB, 11440 reg: regInfo{ 11441 inputs: []inputInfo{ 11442 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11443 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11444 }, 11445 outputs: []outputInfo{ 11446 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11447 }, 11448 }, 11449 }, 11450 { 11451 name: "SUBshiftRL", 11452 auxType: auxInt64, 11453 argLen: 2, 11454 asm: arm64.ASUB, 11455 reg: regInfo{ 11456 inputs: []inputInfo{ 11457 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11458 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11459 }, 11460 outputs: []outputInfo{ 11461 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11462 }, 11463 }, 11464 }, 11465 { 11466 name: "SUBshiftRA", 11467 auxType: auxInt64, 11468 argLen: 2, 11469 asm: arm64.ASUB, 11470 reg: regInfo{ 11471 inputs: []inputInfo{ 11472 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11473 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11474 }, 11475 outputs: []outputInfo{ 11476 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11477 }, 11478 }, 11479 }, 11480 { 11481 name: "ANDshiftLL", 11482 auxType: auxInt64, 11483 argLen: 2, 11484 asm: arm64.AAND, 11485 reg: regInfo{ 11486 inputs: []inputInfo{ 11487 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11488 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11489 }, 11490 outputs: []outputInfo{ 11491 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11492 }, 11493 }, 11494 }, 11495 { 11496 name: "ANDshiftRL", 11497 auxType: auxInt64, 11498 argLen: 2, 11499 asm: arm64.AAND, 11500 reg: regInfo{ 11501 inputs: []inputInfo{ 11502 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11503 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11504 }, 11505 outputs: []outputInfo{ 11506 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11507 }, 11508 }, 11509 }, 11510 { 11511 name: "ANDshiftRA", 11512 auxType: auxInt64, 11513 argLen: 2, 11514 asm: arm64.AAND, 11515 reg: regInfo{ 11516 inputs: []inputInfo{ 11517 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11518 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11519 }, 11520 outputs: []outputInfo{ 11521 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11522 }, 11523 }, 11524 }, 11525 { 11526 name: "ORshiftLL", 11527 auxType: auxInt64, 11528 argLen: 2, 11529 asm: arm64.AORR, 11530 reg: regInfo{ 11531 inputs: []inputInfo{ 11532 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11533 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11534 }, 11535 outputs: []outputInfo{ 11536 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11537 }, 11538 }, 11539 }, 11540 { 11541 name: "ORshiftRL", 11542 auxType: auxInt64, 11543 argLen: 2, 11544 asm: arm64.AORR, 11545 reg: regInfo{ 11546 inputs: []inputInfo{ 11547 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11548 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11549 }, 11550 outputs: []outputInfo{ 11551 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11552 }, 11553 }, 11554 }, 11555 { 11556 name: "ORshiftRA", 11557 auxType: auxInt64, 11558 argLen: 2, 11559 asm: arm64.AORR, 11560 reg: regInfo{ 11561 inputs: []inputInfo{ 11562 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11563 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11564 }, 11565 outputs: []outputInfo{ 11566 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11567 }, 11568 }, 11569 }, 11570 { 11571 name: "XORshiftLL", 11572 auxType: auxInt64, 11573 argLen: 2, 11574 asm: arm64.AEOR, 11575 reg: regInfo{ 11576 inputs: []inputInfo{ 11577 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11578 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11579 }, 11580 outputs: []outputInfo{ 11581 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11582 }, 11583 }, 11584 }, 11585 { 11586 name: "XORshiftRL", 11587 auxType: auxInt64, 11588 argLen: 2, 11589 asm: arm64.AEOR, 11590 reg: regInfo{ 11591 inputs: []inputInfo{ 11592 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11593 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11594 }, 11595 outputs: []outputInfo{ 11596 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11597 }, 11598 }, 11599 }, 11600 { 11601 name: "XORshiftRA", 11602 auxType: auxInt64, 11603 argLen: 2, 11604 asm: arm64.AEOR, 11605 reg: regInfo{ 11606 inputs: []inputInfo{ 11607 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11608 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11609 }, 11610 outputs: []outputInfo{ 11611 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11612 }, 11613 }, 11614 }, 11615 { 11616 name: "BICshiftLL", 11617 auxType: auxInt64, 11618 argLen: 2, 11619 asm: arm64.ABIC, 11620 reg: regInfo{ 11621 inputs: []inputInfo{ 11622 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11623 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11624 }, 11625 outputs: []outputInfo{ 11626 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11627 }, 11628 }, 11629 }, 11630 { 11631 name: "BICshiftRL", 11632 auxType: auxInt64, 11633 argLen: 2, 11634 asm: arm64.ABIC, 11635 reg: regInfo{ 11636 inputs: []inputInfo{ 11637 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11638 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11639 }, 11640 outputs: []outputInfo{ 11641 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11642 }, 11643 }, 11644 }, 11645 { 11646 name: "BICshiftRA", 11647 auxType: auxInt64, 11648 argLen: 2, 11649 asm: arm64.ABIC, 11650 reg: regInfo{ 11651 inputs: []inputInfo{ 11652 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11653 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11654 }, 11655 outputs: []outputInfo{ 11656 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11657 }, 11658 }, 11659 }, 11660 { 11661 name: "CMPshiftLL", 11662 auxType: auxInt64, 11663 argLen: 2, 11664 asm: arm64.ACMP, 11665 reg: regInfo{ 11666 inputs: []inputInfo{ 11667 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11668 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11669 }, 11670 }, 11671 }, 11672 { 11673 name: "CMPshiftRL", 11674 auxType: auxInt64, 11675 argLen: 2, 11676 asm: arm64.ACMP, 11677 reg: regInfo{ 11678 inputs: []inputInfo{ 11679 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11680 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11681 }, 11682 }, 11683 }, 11684 { 11685 name: "CMPshiftRA", 11686 auxType: auxInt64, 11687 argLen: 2, 11688 asm: arm64.ACMP, 11689 reg: regInfo{ 11690 inputs: []inputInfo{ 11691 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11692 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11693 }, 11694 }, 11695 }, 11696 { 11697 name: "MOVDconst", 11698 auxType: auxInt64, 11699 argLen: 0, 11700 rematerializeable: true, 11701 asm: arm64.AMOVD, 11702 reg: regInfo{ 11703 outputs: []outputInfo{ 11704 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11705 }, 11706 }, 11707 }, 11708 { 11709 name: "FMOVSconst", 11710 auxType: auxFloat64, 11711 argLen: 0, 11712 rematerializeable: true, 11713 asm: arm64.AFMOVS, 11714 reg: regInfo{ 11715 outputs: []outputInfo{ 11716 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11717 }, 11718 }, 11719 }, 11720 { 11721 name: "FMOVDconst", 11722 auxType: auxFloat64, 11723 argLen: 0, 11724 rematerializeable: true, 11725 asm: arm64.AFMOVD, 11726 reg: regInfo{ 11727 outputs: []outputInfo{ 11728 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11729 }, 11730 }, 11731 }, 11732 { 11733 name: "MOVDaddr", 11734 auxType: auxSymOff, 11735 argLen: 1, 11736 rematerializeable: true, 11737 asm: arm64.AMOVD, 11738 reg: regInfo{ 11739 inputs: []inputInfo{ 11740 {0, 9223372037928517632}, // SP SB 11741 }, 11742 outputs: []outputInfo{ 11743 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11744 }, 11745 }, 11746 }, 11747 { 11748 name: "MOVBload", 11749 auxType: auxSymOff, 11750 argLen: 2, 11751 faultOnNilArg0: true, 11752 asm: arm64.AMOVB, 11753 reg: regInfo{ 11754 inputs: []inputInfo{ 11755 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11756 }, 11757 outputs: []outputInfo{ 11758 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11759 }, 11760 }, 11761 }, 11762 { 11763 name: "MOVBUload", 11764 auxType: auxSymOff, 11765 argLen: 2, 11766 faultOnNilArg0: true, 11767 asm: arm64.AMOVBU, 11768 reg: regInfo{ 11769 inputs: []inputInfo{ 11770 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11771 }, 11772 outputs: []outputInfo{ 11773 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11774 }, 11775 }, 11776 }, 11777 { 11778 name: "MOVHload", 11779 auxType: auxSymOff, 11780 argLen: 2, 11781 faultOnNilArg0: true, 11782 asm: arm64.AMOVH, 11783 reg: regInfo{ 11784 inputs: []inputInfo{ 11785 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11786 }, 11787 outputs: []outputInfo{ 11788 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11789 }, 11790 }, 11791 }, 11792 { 11793 name: "MOVHUload", 11794 auxType: auxSymOff, 11795 argLen: 2, 11796 faultOnNilArg0: true, 11797 asm: arm64.AMOVHU, 11798 reg: regInfo{ 11799 inputs: []inputInfo{ 11800 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11801 }, 11802 outputs: []outputInfo{ 11803 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11804 }, 11805 }, 11806 }, 11807 { 11808 name: "MOVWload", 11809 auxType: auxSymOff, 11810 argLen: 2, 11811 faultOnNilArg0: true, 11812 asm: arm64.AMOVW, 11813 reg: regInfo{ 11814 inputs: []inputInfo{ 11815 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11816 }, 11817 outputs: []outputInfo{ 11818 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11819 }, 11820 }, 11821 }, 11822 { 11823 name: "MOVWUload", 11824 auxType: auxSymOff, 11825 argLen: 2, 11826 faultOnNilArg0: true, 11827 asm: arm64.AMOVWU, 11828 reg: regInfo{ 11829 inputs: []inputInfo{ 11830 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11831 }, 11832 outputs: []outputInfo{ 11833 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11834 }, 11835 }, 11836 }, 11837 { 11838 name: "MOVDload", 11839 auxType: auxSymOff, 11840 argLen: 2, 11841 faultOnNilArg0: true, 11842 asm: arm64.AMOVD, 11843 reg: regInfo{ 11844 inputs: []inputInfo{ 11845 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11846 }, 11847 outputs: []outputInfo{ 11848 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11849 }, 11850 }, 11851 }, 11852 { 11853 name: "FMOVSload", 11854 auxType: auxSymOff, 11855 argLen: 2, 11856 faultOnNilArg0: true, 11857 asm: arm64.AFMOVS, 11858 reg: regInfo{ 11859 inputs: []inputInfo{ 11860 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11861 }, 11862 outputs: []outputInfo{ 11863 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11864 }, 11865 }, 11866 }, 11867 { 11868 name: "FMOVDload", 11869 auxType: auxSymOff, 11870 argLen: 2, 11871 faultOnNilArg0: true, 11872 asm: arm64.AFMOVD, 11873 reg: regInfo{ 11874 inputs: []inputInfo{ 11875 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11876 }, 11877 outputs: []outputInfo{ 11878 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11879 }, 11880 }, 11881 }, 11882 { 11883 name: "MOVBstore", 11884 auxType: auxSymOff, 11885 argLen: 3, 11886 faultOnNilArg0: true, 11887 asm: arm64.AMOVB, 11888 reg: regInfo{ 11889 inputs: []inputInfo{ 11890 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11891 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11892 }, 11893 }, 11894 }, 11895 { 11896 name: "MOVHstore", 11897 auxType: auxSymOff, 11898 argLen: 3, 11899 faultOnNilArg0: true, 11900 asm: arm64.AMOVH, 11901 reg: regInfo{ 11902 inputs: []inputInfo{ 11903 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11904 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11905 }, 11906 }, 11907 }, 11908 { 11909 name: "MOVWstore", 11910 auxType: auxSymOff, 11911 argLen: 3, 11912 faultOnNilArg0: true, 11913 asm: arm64.AMOVW, 11914 reg: regInfo{ 11915 inputs: []inputInfo{ 11916 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11917 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11918 }, 11919 }, 11920 }, 11921 { 11922 name: "MOVDstore", 11923 auxType: auxSymOff, 11924 argLen: 3, 11925 faultOnNilArg0: true, 11926 asm: arm64.AMOVD, 11927 reg: regInfo{ 11928 inputs: []inputInfo{ 11929 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11930 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11931 }, 11932 }, 11933 }, 11934 { 11935 name: "FMOVSstore", 11936 auxType: auxSymOff, 11937 argLen: 3, 11938 faultOnNilArg0: true, 11939 asm: arm64.AFMOVS, 11940 reg: regInfo{ 11941 inputs: []inputInfo{ 11942 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11943 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11944 }, 11945 }, 11946 }, 11947 { 11948 name: "FMOVDstore", 11949 auxType: auxSymOff, 11950 argLen: 3, 11951 faultOnNilArg0: true, 11952 asm: arm64.AFMOVD, 11953 reg: regInfo{ 11954 inputs: []inputInfo{ 11955 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11956 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11957 }, 11958 }, 11959 }, 11960 { 11961 name: "MOVBstorezero", 11962 auxType: auxSymOff, 11963 argLen: 2, 11964 faultOnNilArg0: true, 11965 asm: arm64.AMOVB, 11966 reg: regInfo{ 11967 inputs: []inputInfo{ 11968 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11969 }, 11970 }, 11971 }, 11972 { 11973 name: "MOVHstorezero", 11974 auxType: auxSymOff, 11975 argLen: 2, 11976 faultOnNilArg0: true, 11977 asm: arm64.AMOVH, 11978 reg: regInfo{ 11979 inputs: []inputInfo{ 11980 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11981 }, 11982 }, 11983 }, 11984 { 11985 name: "MOVWstorezero", 11986 auxType: auxSymOff, 11987 argLen: 2, 11988 faultOnNilArg0: true, 11989 asm: arm64.AMOVW, 11990 reg: regInfo{ 11991 inputs: []inputInfo{ 11992 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11993 }, 11994 }, 11995 }, 11996 { 11997 name: "MOVDstorezero", 11998 auxType: auxSymOff, 11999 argLen: 2, 12000 faultOnNilArg0: true, 12001 asm: arm64.AMOVD, 12002 reg: regInfo{ 12003 inputs: []inputInfo{ 12004 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12005 }, 12006 }, 12007 }, 12008 { 12009 name: "MOVBreg", 12010 argLen: 1, 12011 asm: arm64.AMOVB, 12012 reg: regInfo{ 12013 inputs: []inputInfo{ 12014 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12015 }, 12016 outputs: []outputInfo{ 12017 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12018 }, 12019 }, 12020 }, 12021 { 12022 name: "MOVBUreg", 12023 argLen: 1, 12024 asm: arm64.AMOVBU, 12025 reg: regInfo{ 12026 inputs: []inputInfo{ 12027 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12028 }, 12029 outputs: []outputInfo{ 12030 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12031 }, 12032 }, 12033 }, 12034 { 12035 name: "MOVHreg", 12036 argLen: 1, 12037 asm: arm64.AMOVH, 12038 reg: regInfo{ 12039 inputs: []inputInfo{ 12040 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12041 }, 12042 outputs: []outputInfo{ 12043 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12044 }, 12045 }, 12046 }, 12047 { 12048 name: "MOVHUreg", 12049 argLen: 1, 12050 asm: arm64.AMOVHU, 12051 reg: regInfo{ 12052 inputs: []inputInfo{ 12053 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12054 }, 12055 outputs: []outputInfo{ 12056 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12057 }, 12058 }, 12059 }, 12060 { 12061 name: "MOVWreg", 12062 argLen: 1, 12063 asm: arm64.AMOVW, 12064 reg: regInfo{ 12065 inputs: []inputInfo{ 12066 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12067 }, 12068 outputs: []outputInfo{ 12069 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12070 }, 12071 }, 12072 }, 12073 { 12074 name: "MOVWUreg", 12075 argLen: 1, 12076 asm: arm64.AMOVWU, 12077 reg: regInfo{ 12078 inputs: []inputInfo{ 12079 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12080 }, 12081 outputs: []outputInfo{ 12082 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12083 }, 12084 }, 12085 }, 12086 { 12087 name: "MOVDreg", 12088 argLen: 1, 12089 asm: arm64.AMOVD, 12090 reg: regInfo{ 12091 inputs: []inputInfo{ 12092 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12093 }, 12094 outputs: []outputInfo{ 12095 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12096 }, 12097 }, 12098 }, 12099 { 12100 name: "MOVDnop", 12101 argLen: 1, 12102 resultInArg0: true, 12103 reg: regInfo{ 12104 inputs: []inputInfo{ 12105 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12106 }, 12107 outputs: []outputInfo{ 12108 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12109 }, 12110 }, 12111 }, 12112 { 12113 name: "SCVTFWS", 12114 argLen: 1, 12115 asm: arm64.ASCVTFWS, 12116 reg: regInfo{ 12117 inputs: []inputInfo{ 12118 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12119 }, 12120 outputs: []outputInfo{ 12121 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12122 }, 12123 }, 12124 }, 12125 { 12126 name: "SCVTFWD", 12127 argLen: 1, 12128 asm: arm64.ASCVTFWD, 12129 reg: regInfo{ 12130 inputs: []inputInfo{ 12131 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12132 }, 12133 outputs: []outputInfo{ 12134 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12135 }, 12136 }, 12137 }, 12138 { 12139 name: "UCVTFWS", 12140 argLen: 1, 12141 asm: arm64.AUCVTFWS, 12142 reg: regInfo{ 12143 inputs: []inputInfo{ 12144 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12145 }, 12146 outputs: []outputInfo{ 12147 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12148 }, 12149 }, 12150 }, 12151 { 12152 name: "UCVTFWD", 12153 argLen: 1, 12154 asm: arm64.AUCVTFWD, 12155 reg: regInfo{ 12156 inputs: []inputInfo{ 12157 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12158 }, 12159 outputs: []outputInfo{ 12160 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12161 }, 12162 }, 12163 }, 12164 { 12165 name: "SCVTFS", 12166 argLen: 1, 12167 asm: arm64.ASCVTFS, 12168 reg: regInfo{ 12169 inputs: []inputInfo{ 12170 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12171 }, 12172 outputs: []outputInfo{ 12173 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12174 }, 12175 }, 12176 }, 12177 { 12178 name: "SCVTFD", 12179 argLen: 1, 12180 asm: arm64.ASCVTFD, 12181 reg: regInfo{ 12182 inputs: []inputInfo{ 12183 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12184 }, 12185 outputs: []outputInfo{ 12186 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12187 }, 12188 }, 12189 }, 12190 { 12191 name: "UCVTFS", 12192 argLen: 1, 12193 asm: arm64.AUCVTFS, 12194 reg: regInfo{ 12195 inputs: []inputInfo{ 12196 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12197 }, 12198 outputs: []outputInfo{ 12199 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12200 }, 12201 }, 12202 }, 12203 { 12204 name: "UCVTFD", 12205 argLen: 1, 12206 asm: arm64.AUCVTFD, 12207 reg: regInfo{ 12208 inputs: []inputInfo{ 12209 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12210 }, 12211 outputs: []outputInfo{ 12212 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12213 }, 12214 }, 12215 }, 12216 { 12217 name: "FCVTZSSW", 12218 argLen: 1, 12219 asm: arm64.AFCVTZSSW, 12220 reg: regInfo{ 12221 inputs: []inputInfo{ 12222 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12223 }, 12224 outputs: []outputInfo{ 12225 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12226 }, 12227 }, 12228 }, 12229 { 12230 name: "FCVTZSDW", 12231 argLen: 1, 12232 asm: arm64.AFCVTZSDW, 12233 reg: regInfo{ 12234 inputs: []inputInfo{ 12235 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12236 }, 12237 outputs: []outputInfo{ 12238 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12239 }, 12240 }, 12241 }, 12242 { 12243 name: "FCVTZUSW", 12244 argLen: 1, 12245 asm: arm64.AFCVTZUSW, 12246 reg: regInfo{ 12247 inputs: []inputInfo{ 12248 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12249 }, 12250 outputs: []outputInfo{ 12251 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12252 }, 12253 }, 12254 }, 12255 { 12256 name: "FCVTZUDW", 12257 argLen: 1, 12258 asm: arm64.AFCVTZUDW, 12259 reg: regInfo{ 12260 inputs: []inputInfo{ 12261 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12262 }, 12263 outputs: []outputInfo{ 12264 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12265 }, 12266 }, 12267 }, 12268 { 12269 name: "FCVTZSS", 12270 argLen: 1, 12271 asm: arm64.AFCVTZSS, 12272 reg: regInfo{ 12273 inputs: []inputInfo{ 12274 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12275 }, 12276 outputs: []outputInfo{ 12277 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12278 }, 12279 }, 12280 }, 12281 { 12282 name: "FCVTZSD", 12283 argLen: 1, 12284 asm: arm64.AFCVTZSD, 12285 reg: regInfo{ 12286 inputs: []inputInfo{ 12287 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12288 }, 12289 outputs: []outputInfo{ 12290 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12291 }, 12292 }, 12293 }, 12294 { 12295 name: "FCVTZUS", 12296 argLen: 1, 12297 asm: arm64.AFCVTZUS, 12298 reg: regInfo{ 12299 inputs: []inputInfo{ 12300 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12301 }, 12302 outputs: []outputInfo{ 12303 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12304 }, 12305 }, 12306 }, 12307 { 12308 name: "FCVTZUD", 12309 argLen: 1, 12310 asm: arm64.AFCVTZUD, 12311 reg: regInfo{ 12312 inputs: []inputInfo{ 12313 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12314 }, 12315 outputs: []outputInfo{ 12316 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12317 }, 12318 }, 12319 }, 12320 { 12321 name: "FCVTSD", 12322 argLen: 1, 12323 asm: arm64.AFCVTSD, 12324 reg: regInfo{ 12325 inputs: []inputInfo{ 12326 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12327 }, 12328 outputs: []outputInfo{ 12329 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12330 }, 12331 }, 12332 }, 12333 { 12334 name: "FCVTDS", 12335 argLen: 1, 12336 asm: arm64.AFCVTDS, 12337 reg: regInfo{ 12338 inputs: []inputInfo{ 12339 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12340 }, 12341 outputs: []outputInfo{ 12342 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12343 }, 12344 }, 12345 }, 12346 { 12347 name: "CSELULT", 12348 argLen: 3, 12349 asm: arm64.ACSEL, 12350 reg: regInfo{ 12351 inputs: []inputInfo{ 12352 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12353 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12354 }, 12355 outputs: []outputInfo{ 12356 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12357 }, 12358 }, 12359 }, 12360 { 12361 name: "CSELULT0", 12362 argLen: 2, 12363 asm: arm64.ACSEL, 12364 reg: regInfo{ 12365 inputs: []inputInfo{ 12366 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12367 }, 12368 outputs: []outputInfo{ 12369 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12370 }, 12371 }, 12372 }, 12373 { 12374 name: "CALLstatic", 12375 auxType: auxSymOff, 12376 argLen: 1, 12377 clobberFlags: true, 12378 call: true, 12379 reg: regInfo{ 12380 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12381 }, 12382 }, 12383 { 12384 name: "CALLclosure", 12385 auxType: auxInt64, 12386 argLen: 3, 12387 clobberFlags: true, 12388 call: true, 12389 reg: regInfo{ 12390 inputs: []inputInfo{ 12391 {1, 67108864}, // R26 12392 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 12393 }, 12394 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12395 }, 12396 }, 12397 { 12398 name: "CALLdefer", 12399 auxType: auxInt64, 12400 argLen: 1, 12401 clobberFlags: true, 12402 call: true, 12403 reg: regInfo{ 12404 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12405 }, 12406 }, 12407 { 12408 name: "CALLgo", 12409 auxType: auxInt64, 12410 argLen: 1, 12411 clobberFlags: true, 12412 call: true, 12413 reg: regInfo{ 12414 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12415 }, 12416 }, 12417 { 12418 name: "CALLinter", 12419 auxType: auxInt64, 12420 argLen: 2, 12421 clobberFlags: true, 12422 call: true, 12423 reg: regInfo{ 12424 inputs: []inputInfo{ 12425 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12426 }, 12427 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12428 }, 12429 }, 12430 { 12431 name: "LoweredNilCheck", 12432 argLen: 2, 12433 nilCheck: true, 12434 faultOnNilArg0: true, 12435 reg: regInfo{ 12436 inputs: []inputInfo{ 12437 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12438 }, 12439 }, 12440 }, 12441 { 12442 name: "Equal", 12443 argLen: 1, 12444 reg: regInfo{ 12445 outputs: []outputInfo{ 12446 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12447 }, 12448 }, 12449 }, 12450 { 12451 name: "NotEqual", 12452 argLen: 1, 12453 reg: regInfo{ 12454 outputs: []outputInfo{ 12455 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12456 }, 12457 }, 12458 }, 12459 { 12460 name: "LessThan", 12461 argLen: 1, 12462 reg: regInfo{ 12463 outputs: []outputInfo{ 12464 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12465 }, 12466 }, 12467 }, 12468 { 12469 name: "LessEqual", 12470 argLen: 1, 12471 reg: regInfo{ 12472 outputs: []outputInfo{ 12473 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12474 }, 12475 }, 12476 }, 12477 { 12478 name: "GreaterThan", 12479 argLen: 1, 12480 reg: regInfo{ 12481 outputs: []outputInfo{ 12482 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12483 }, 12484 }, 12485 }, 12486 { 12487 name: "GreaterEqual", 12488 argLen: 1, 12489 reg: regInfo{ 12490 outputs: []outputInfo{ 12491 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12492 }, 12493 }, 12494 }, 12495 { 12496 name: "LessThanU", 12497 argLen: 1, 12498 reg: regInfo{ 12499 outputs: []outputInfo{ 12500 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12501 }, 12502 }, 12503 }, 12504 { 12505 name: "LessEqualU", 12506 argLen: 1, 12507 reg: regInfo{ 12508 outputs: []outputInfo{ 12509 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12510 }, 12511 }, 12512 }, 12513 { 12514 name: "GreaterThanU", 12515 argLen: 1, 12516 reg: regInfo{ 12517 outputs: []outputInfo{ 12518 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12519 }, 12520 }, 12521 }, 12522 { 12523 name: "GreaterEqualU", 12524 argLen: 1, 12525 reg: regInfo{ 12526 outputs: []outputInfo{ 12527 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12528 }, 12529 }, 12530 }, 12531 { 12532 name: "DUFFZERO", 12533 auxType: auxInt64, 12534 argLen: 2, 12535 faultOnNilArg0: true, 12536 reg: regInfo{ 12537 inputs: []inputInfo{ 12538 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12539 }, 12540 clobbers: 536936448, // R16 R30 12541 }, 12542 }, 12543 { 12544 name: "LoweredZero", 12545 argLen: 3, 12546 clobberFlags: true, 12547 faultOnNilArg0: true, 12548 reg: regInfo{ 12549 inputs: []inputInfo{ 12550 {0, 65536}, // R16 12551 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12552 }, 12553 clobbers: 65536, // R16 12554 }, 12555 }, 12556 { 12557 name: "DUFFCOPY", 12558 auxType: auxInt64, 12559 argLen: 3, 12560 faultOnNilArg0: true, 12561 faultOnNilArg1: true, 12562 reg: regInfo{ 12563 inputs: []inputInfo{ 12564 {0, 131072}, // R17 12565 {1, 65536}, // R16 12566 }, 12567 clobbers: 537067520, // R16 R17 R30 12568 }, 12569 }, 12570 { 12571 name: "LoweredMove", 12572 argLen: 4, 12573 clobberFlags: true, 12574 faultOnNilArg0: true, 12575 faultOnNilArg1: true, 12576 reg: regInfo{ 12577 inputs: []inputInfo{ 12578 {0, 131072}, // R17 12579 {1, 65536}, // R16 12580 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12581 }, 12582 clobbers: 196608, // R16 R17 12583 }, 12584 }, 12585 { 12586 name: "LoweredGetClosurePtr", 12587 argLen: 0, 12588 reg: regInfo{ 12589 outputs: []outputInfo{ 12590 {0, 67108864}, // R26 12591 }, 12592 }, 12593 }, 12594 { 12595 name: "MOVDconvert", 12596 argLen: 2, 12597 asm: arm64.AMOVD, 12598 reg: regInfo{ 12599 inputs: []inputInfo{ 12600 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12601 }, 12602 outputs: []outputInfo{ 12603 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12604 }, 12605 }, 12606 }, 12607 { 12608 name: "FlagEQ", 12609 argLen: 0, 12610 reg: regInfo{}, 12611 }, 12612 { 12613 name: "FlagLT_ULT", 12614 argLen: 0, 12615 reg: regInfo{}, 12616 }, 12617 { 12618 name: "FlagLT_UGT", 12619 argLen: 0, 12620 reg: regInfo{}, 12621 }, 12622 { 12623 name: "FlagGT_UGT", 12624 argLen: 0, 12625 reg: regInfo{}, 12626 }, 12627 { 12628 name: "FlagGT_ULT", 12629 argLen: 0, 12630 reg: regInfo{}, 12631 }, 12632 { 12633 name: "InvertFlags", 12634 argLen: 1, 12635 reg: regInfo{}, 12636 }, 12637 { 12638 name: "LDAR", 12639 argLen: 2, 12640 faultOnNilArg0: true, 12641 asm: arm64.ALDAR, 12642 reg: regInfo{ 12643 inputs: []inputInfo{ 12644 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12645 }, 12646 outputs: []outputInfo{ 12647 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12648 }, 12649 }, 12650 }, 12651 { 12652 name: "LDARW", 12653 argLen: 2, 12654 faultOnNilArg0: true, 12655 asm: arm64.ALDARW, 12656 reg: regInfo{ 12657 inputs: []inputInfo{ 12658 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12659 }, 12660 outputs: []outputInfo{ 12661 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12662 }, 12663 }, 12664 }, 12665 { 12666 name: "STLR", 12667 argLen: 3, 12668 faultOnNilArg0: true, 12669 asm: arm64.ASTLR, 12670 reg: regInfo{ 12671 inputs: []inputInfo{ 12672 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12673 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12674 }, 12675 }, 12676 }, 12677 { 12678 name: "STLRW", 12679 argLen: 3, 12680 faultOnNilArg0: true, 12681 asm: arm64.ASTLRW, 12682 reg: regInfo{ 12683 inputs: []inputInfo{ 12684 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12685 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12686 }, 12687 }, 12688 }, 12689 { 12690 name: "LoweredAtomicExchange64", 12691 argLen: 3, 12692 resultNotInArgs: true, 12693 faultOnNilArg0: true, 12694 reg: regInfo{ 12695 inputs: []inputInfo{ 12696 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12697 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12698 }, 12699 outputs: []outputInfo{ 12700 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12701 }, 12702 }, 12703 }, 12704 { 12705 name: "LoweredAtomicExchange32", 12706 argLen: 3, 12707 resultNotInArgs: true, 12708 faultOnNilArg0: true, 12709 reg: regInfo{ 12710 inputs: []inputInfo{ 12711 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12712 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12713 }, 12714 outputs: []outputInfo{ 12715 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12716 }, 12717 }, 12718 }, 12719 { 12720 name: "LoweredAtomicAdd64", 12721 argLen: 3, 12722 resultNotInArgs: true, 12723 faultOnNilArg0: true, 12724 reg: regInfo{ 12725 inputs: []inputInfo{ 12726 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12727 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12728 }, 12729 outputs: []outputInfo{ 12730 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12731 }, 12732 }, 12733 }, 12734 { 12735 name: "LoweredAtomicAdd32", 12736 argLen: 3, 12737 resultNotInArgs: true, 12738 faultOnNilArg0: true, 12739 reg: regInfo{ 12740 inputs: []inputInfo{ 12741 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12742 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12743 }, 12744 outputs: []outputInfo{ 12745 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12746 }, 12747 }, 12748 }, 12749 { 12750 name: "LoweredAtomicCas64", 12751 argLen: 4, 12752 resultNotInArgs: true, 12753 clobberFlags: true, 12754 faultOnNilArg0: true, 12755 reg: regInfo{ 12756 inputs: []inputInfo{ 12757 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12758 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12759 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12760 }, 12761 outputs: []outputInfo{ 12762 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12763 }, 12764 }, 12765 }, 12766 { 12767 name: "LoweredAtomicCas32", 12768 argLen: 4, 12769 resultNotInArgs: true, 12770 clobberFlags: true, 12771 faultOnNilArg0: true, 12772 reg: regInfo{ 12773 inputs: []inputInfo{ 12774 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12775 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12776 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12777 }, 12778 outputs: []outputInfo{ 12779 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12780 }, 12781 }, 12782 }, 12783 { 12784 name: "LoweredAtomicAnd8", 12785 argLen: 3, 12786 faultOnNilArg0: true, 12787 asm: arm64.AAND, 12788 reg: regInfo{ 12789 inputs: []inputInfo{ 12790 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12791 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12792 }, 12793 }, 12794 }, 12795 { 12796 name: "LoweredAtomicOr8", 12797 argLen: 3, 12798 faultOnNilArg0: true, 12799 asm: arm64.AORR, 12800 reg: regInfo{ 12801 inputs: []inputInfo{ 12802 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12803 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12804 }, 12805 }, 12806 }, 12807 12808 { 12809 name: "ADD", 12810 argLen: 2, 12811 commutative: true, 12812 asm: mips.AADDU, 12813 reg: regInfo{ 12814 inputs: []inputInfo{ 12815 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12816 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12817 }, 12818 outputs: []outputInfo{ 12819 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12820 }, 12821 }, 12822 }, 12823 { 12824 name: "ADDconst", 12825 auxType: auxInt32, 12826 argLen: 1, 12827 asm: mips.AADDU, 12828 reg: regInfo{ 12829 inputs: []inputInfo{ 12830 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 12831 }, 12832 outputs: []outputInfo{ 12833 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12834 }, 12835 }, 12836 }, 12837 { 12838 name: "SUB", 12839 argLen: 2, 12840 asm: mips.ASUBU, 12841 reg: regInfo{ 12842 inputs: []inputInfo{ 12843 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12844 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12845 }, 12846 outputs: []outputInfo{ 12847 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12848 }, 12849 }, 12850 }, 12851 { 12852 name: "SUBconst", 12853 auxType: auxInt32, 12854 argLen: 1, 12855 asm: mips.ASUBU, 12856 reg: regInfo{ 12857 inputs: []inputInfo{ 12858 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12859 }, 12860 outputs: []outputInfo{ 12861 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12862 }, 12863 }, 12864 }, 12865 { 12866 name: "MUL", 12867 argLen: 2, 12868 commutative: true, 12869 asm: mips.AMUL, 12870 reg: regInfo{ 12871 inputs: []inputInfo{ 12872 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12873 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12874 }, 12875 clobbers: 105553116266496, // HI LO 12876 outputs: []outputInfo{ 12877 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12878 }, 12879 }, 12880 }, 12881 { 12882 name: "MULT", 12883 argLen: 2, 12884 commutative: true, 12885 asm: mips.AMUL, 12886 reg: regInfo{ 12887 inputs: []inputInfo{ 12888 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12889 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12890 }, 12891 outputs: []outputInfo{ 12892 {0, 35184372088832}, // HI 12893 {1, 70368744177664}, // LO 12894 }, 12895 }, 12896 }, 12897 { 12898 name: "MULTU", 12899 argLen: 2, 12900 commutative: true, 12901 asm: mips.AMULU, 12902 reg: regInfo{ 12903 inputs: []inputInfo{ 12904 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12905 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12906 }, 12907 outputs: []outputInfo{ 12908 {0, 35184372088832}, // HI 12909 {1, 70368744177664}, // LO 12910 }, 12911 }, 12912 }, 12913 { 12914 name: "DIV", 12915 argLen: 2, 12916 asm: mips.ADIV, 12917 reg: regInfo{ 12918 inputs: []inputInfo{ 12919 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12920 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12921 }, 12922 outputs: []outputInfo{ 12923 {0, 35184372088832}, // HI 12924 {1, 70368744177664}, // LO 12925 }, 12926 }, 12927 }, 12928 { 12929 name: "DIVU", 12930 argLen: 2, 12931 asm: mips.ADIVU, 12932 reg: regInfo{ 12933 inputs: []inputInfo{ 12934 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12935 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12936 }, 12937 outputs: []outputInfo{ 12938 {0, 35184372088832}, // HI 12939 {1, 70368744177664}, // LO 12940 }, 12941 }, 12942 }, 12943 { 12944 name: "ADDF", 12945 argLen: 2, 12946 commutative: true, 12947 asm: mips.AADDF, 12948 reg: regInfo{ 12949 inputs: []inputInfo{ 12950 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12951 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12952 }, 12953 outputs: []outputInfo{ 12954 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12955 }, 12956 }, 12957 }, 12958 { 12959 name: "ADDD", 12960 argLen: 2, 12961 commutative: true, 12962 asm: mips.AADDD, 12963 reg: regInfo{ 12964 inputs: []inputInfo{ 12965 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12966 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12967 }, 12968 outputs: []outputInfo{ 12969 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12970 }, 12971 }, 12972 }, 12973 { 12974 name: "SUBF", 12975 argLen: 2, 12976 asm: mips.ASUBF, 12977 reg: regInfo{ 12978 inputs: []inputInfo{ 12979 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12980 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12981 }, 12982 outputs: []outputInfo{ 12983 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12984 }, 12985 }, 12986 }, 12987 { 12988 name: "SUBD", 12989 argLen: 2, 12990 asm: mips.ASUBD, 12991 reg: regInfo{ 12992 inputs: []inputInfo{ 12993 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12994 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12995 }, 12996 outputs: []outputInfo{ 12997 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12998 }, 12999 }, 13000 }, 13001 { 13002 name: "MULF", 13003 argLen: 2, 13004 commutative: true, 13005 asm: mips.AMULF, 13006 reg: regInfo{ 13007 inputs: []inputInfo{ 13008 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13009 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13010 }, 13011 outputs: []outputInfo{ 13012 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13013 }, 13014 }, 13015 }, 13016 { 13017 name: "MULD", 13018 argLen: 2, 13019 commutative: true, 13020 asm: mips.AMULD, 13021 reg: regInfo{ 13022 inputs: []inputInfo{ 13023 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13024 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13025 }, 13026 outputs: []outputInfo{ 13027 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13028 }, 13029 }, 13030 }, 13031 { 13032 name: "DIVF", 13033 argLen: 2, 13034 asm: mips.ADIVF, 13035 reg: regInfo{ 13036 inputs: []inputInfo{ 13037 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13038 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13039 }, 13040 outputs: []outputInfo{ 13041 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13042 }, 13043 }, 13044 }, 13045 { 13046 name: "DIVD", 13047 argLen: 2, 13048 asm: mips.ADIVD, 13049 reg: regInfo{ 13050 inputs: []inputInfo{ 13051 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13052 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13053 }, 13054 outputs: []outputInfo{ 13055 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13056 }, 13057 }, 13058 }, 13059 { 13060 name: "AND", 13061 argLen: 2, 13062 commutative: true, 13063 asm: mips.AAND, 13064 reg: regInfo{ 13065 inputs: []inputInfo{ 13066 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13067 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13068 }, 13069 outputs: []outputInfo{ 13070 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13071 }, 13072 }, 13073 }, 13074 { 13075 name: "ANDconst", 13076 auxType: auxInt32, 13077 argLen: 1, 13078 asm: mips.AAND, 13079 reg: regInfo{ 13080 inputs: []inputInfo{ 13081 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13082 }, 13083 outputs: []outputInfo{ 13084 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13085 }, 13086 }, 13087 }, 13088 { 13089 name: "OR", 13090 argLen: 2, 13091 commutative: true, 13092 asm: mips.AOR, 13093 reg: regInfo{ 13094 inputs: []inputInfo{ 13095 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13096 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13097 }, 13098 outputs: []outputInfo{ 13099 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13100 }, 13101 }, 13102 }, 13103 { 13104 name: "ORconst", 13105 auxType: auxInt32, 13106 argLen: 1, 13107 asm: mips.AOR, 13108 reg: regInfo{ 13109 inputs: []inputInfo{ 13110 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13111 }, 13112 outputs: []outputInfo{ 13113 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13114 }, 13115 }, 13116 }, 13117 { 13118 name: "XOR", 13119 argLen: 2, 13120 commutative: true, 13121 asm: mips.AXOR, 13122 reg: regInfo{ 13123 inputs: []inputInfo{ 13124 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13125 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13126 }, 13127 outputs: []outputInfo{ 13128 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13129 }, 13130 }, 13131 }, 13132 { 13133 name: "XORconst", 13134 auxType: auxInt32, 13135 argLen: 1, 13136 asm: mips.AXOR, 13137 reg: regInfo{ 13138 inputs: []inputInfo{ 13139 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13140 }, 13141 outputs: []outputInfo{ 13142 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13143 }, 13144 }, 13145 }, 13146 { 13147 name: "NOR", 13148 argLen: 2, 13149 commutative: true, 13150 asm: mips.ANOR, 13151 reg: regInfo{ 13152 inputs: []inputInfo{ 13153 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13154 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13155 }, 13156 outputs: []outputInfo{ 13157 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13158 }, 13159 }, 13160 }, 13161 { 13162 name: "NORconst", 13163 auxType: auxInt32, 13164 argLen: 1, 13165 asm: mips.ANOR, 13166 reg: regInfo{ 13167 inputs: []inputInfo{ 13168 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13169 }, 13170 outputs: []outputInfo{ 13171 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13172 }, 13173 }, 13174 }, 13175 { 13176 name: "NEG", 13177 argLen: 1, 13178 reg: regInfo{ 13179 inputs: []inputInfo{ 13180 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13181 }, 13182 outputs: []outputInfo{ 13183 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13184 }, 13185 }, 13186 }, 13187 { 13188 name: "NEGF", 13189 argLen: 1, 13190 asm: mips.ANEGF, 13191 reg: regInfo{ 13192 inputs: []inputInfo{ 13193 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13194 }, 13195 outputs: []outputInfo{ 13196 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13197 }, 13198 }, 13199 }, 13200 { 13201 name: "NEGD", 13202 argLen: 1, 13203 asm: mips.ANEGD, 13204 reg: regInfo{ 13205 inputs: []inputInfo{ 13206 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13207 }, 13208 outputs: []outputInfo{ 13209 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13210 }, 13211 }, 13212 }, 13213 { 13214 name: "SQRTD", 13215 argLen: 1, 13216 asm: mips.ASQRTD, 13217 reg: regInfo{ 13218 inputs: []inputInfo{ 13219 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13220 }, 13221 outputs: []outputInfo{ 13222 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13223 }, 13224 }, 13225 }, 13226 { 13227 name: "SLL", 13228 argLen: 2, 13229 asm: mips.ASLL, 13230 reg: regInfo{ 13231 inputs: []inputInfo{ 13232 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13233 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13234 }, 13235 outputs: []outputInfo{ 13236 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13237 }, 13238 }, 13239 }, 13240 { 13241 name: "SLLconst", 13242 auxType: auxInt32, 13243 argLen: 1, 13244 asm: mips.ASLL, 13245 reg: regInfo{ 13246 inputs: []inputInfo{ 13247 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13248 }, 13249 outputs: []outputInfo{ 13250 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13251 }, 13252 }, 13253 }, 13254 { 13255 name: "SRL", 13256 argLen: 2, 13257 asm: mips.ASRL, 13258 reg: regInfo{ 13259 inputs: []inputInfo{ 13260 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13261 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13262 }, 13263 outputs: []outputInfo{ 13264 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13265 }, 13266 }, 13267 }, 13268 { 13269 name: "SRLconst", 13270 auxType: auxInt32, 13271 argLen: 1, 13272 asm: mips.ASRL, 13273 reg: regInfo{ 13274 inputs: []inputInfo{ 13275 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13276 }, 13277 outputs: []outputInfo{ 13278 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13279 }, 13280 }, 13281 }, 13282 { 13283 name: "SRA", 13284 argLen: 2, 13285 asm: mips.ASRA, 13286 reg: regInfo{ 13287 inputs: []inputInfo{ 13288 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13289 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13290 }, 13291 outputs: []outputInfo{ 13292 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13293 }, 13294 }, 13295 }, 13296 { 13297 name: "SRAconst", 13298 auxType: auxInt32, 13299 argLen: 1, 13300 asm: mips.ASRA, 13301 reg: regInfo{ 13302 inputs: []inputInfo{ 13303 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13304 }, 13305 outputs: []outputInfo{ 13306 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13307 }, 13308 }, 13309 }, 13310 { 13311 name: "CLZ", 13312 argLen: 1, 13313 asm: mips.ACLZ, 13314 reg: regInfo{ 13315 inputs: []inputInfo{ 13316 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13317 }, 13318 outputs: []outputInfo{ 13319 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13320 }, 13321 }, 13322 }, 13323 { 13324 name: "SGT", 13325 argLen: 2, 13326 asm: mips.ASGT, 13327 reg: regInfo{ 13328 inputs: []inputInfo{ 13329 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13330 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13331 }, 13332 outputs: []outputInfo{ 13333 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13334 }, 13335 }, 13336 }, 13337 { 13338 name: "SGTconst", 13339 auxType: auxInt32, 13340 argLen: 1, 13341 asm: mips.ASGT, 13342 reg: regInfo{ 13343 inputs: []inputInfo{ 13344 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13345 }, 13346 outputs: []outputInfo{ 13347 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13348 }, 13349 }, 13350 }, 13351 { 13352 name: "SGTzero", 13353 argLen: 1, 13354 asm: mips.ASGT, 13355 reg: regInfo{ 13356 inputs: []inputInfo{ 13357 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13358 }, 13359 outputs: []outputInfo{ 13360 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13361 }, 13362 }, 13363 }, 13364 { 13365 name: "SGTU", 13366 argLen: 2, 13367 asm: mips.ASGTU, 13368 reg: regInfo{ 13369 inputs: []inputInfo{ 13370 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13371 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13372 }, 13373 outputs: []outputInfo{ 13374 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13375 }, 13376 }, 13377 }, 13378 { 13379 name: "SGTUconst", 13380 auxType: auxInt32, 13381 argLen: 1, 13382 asm: mips.ASGTU, 13383 reg: regInfo{ 13384 inputs: []inputInfo{ 13385 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13386 }, 13387 outputs: []outputInfo{ 13388 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13389 }, 13390 }, 13391 }, 13392 { 13393 name: "SGTUzero", 13394 argLen: 1, 13395 asm: mips.ASGTU, 13396 reg: regInfo{ 13397 inputs: []inputInfo{ 13398 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13399 }, 13400 outputs: []outputInfo{ 13401 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13402 }, 13403 }, 13404 }, 13405 { 13406 name: "CMPEQF", 13407 argLen: 2, 13408 asm: mips.ACMPEQF, 13409 reg: regInfo{ 13410 inputs: []inputInfo{ 13411 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13412 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13413 }, 13414 }, 13415 }, 13416 { 13417 name: "CMPEQD", 13418 argLen: 2, 13419 asm: mips.ACMPEQD, 13420 reg: regInfo{ 13421 inputs: []inputInfo{ 13422 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13423 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13424 }, 13425 }, 13426 }, 13427 { 13428 name: "CMPGEF", 13429 argLen: 2, 13430 asm: mips.ACMPGEF, 13431 reg: regInfo{ 13432 inputs: []inputInfo{ 13433 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13434 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13435 }, 13436 }, 13437 }, 13438 { 13439 name: "CMPGED", 13440 argLen: 2, 13441 asm: mips.ACMPGED, 13442 reg: regInfo{ 13443 inputs: []inputInfo{ 13444 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13445 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13446 }, 13447 }, 13448 }, 13449 { 13450 name: "CMPGTF", 13451 argLen: 2, 13452 asm: mips.ACMPGTF, 13453 reg: regInfo{ 13454 inputs: []inputInfo{ 13455 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13456 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13457 }, 13458 }, 13459 }, 13460 { 13461 name: "CMPGTD", 13462 argLen: 2, 13463 asm: mips.ACMPGTD, 13464 reg: regInfo{ 13465 inputs: []inputInfo{ 13466 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13467 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13468 }, 13469 }, 13470 }, 13471 { 13472 name: "MOVWconst", 13473 auxType: auxInt32, 13474 argLen: 0, 13475 rematerializeable: true, 13476 asm: mips.AMOVW, 13477 reg: regInfo{ 13478 outputs: []outputInfo{ 13479 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13480 }, 13481 }, 13482 }, 13483 { 13484 name: "MOVFconst", 13485 auxType: auxFloat32, 13486 argLen: 0, 13487 rematerializeable: true, 13488 asm: mips.AMOVF, 13489 reg: regInfo{ 13490 outputs: []outputInfo{ 13491 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13492 }, 13493 }, 13494 }, 13495 { 13496 name: "MOVDconst", 13497 auxType: auxFloat64, 13498 argLen: 0, 13499 rematerializeable: true, 13500 asm: mips.AMOVD, 13501 reg: regInfo{ 13502 outputs: []outputInfo{ 13503 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13504 }, 13505 }, 13506 }, 13507 { 13508 name: "MOVWaddr", 13509 auxType: auxSymOff, 13510 argLen: 1, 13511 rematerializeable: true, 13512 asm: mips.AMOVW, 13513 reg: regInfo{ 13514 inputs: []inputInfo{ 13515 {0, 140737555464192}, // SP SB 13516 }, 13517 outputs: []outputInfo{ 13518 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13519 }, 13520 }, 13521 }, 13522 { 13523 name: "MOVBload", 13524 auxType: auxSymOff, 13525 argLen: 2, 13526 faultOnNilArg0: true, 13527 asm: mips.AMOVB, 13528 reg: regInfo{ 13529 inputs: []inputInfo{ 13530 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13531 }, 13532 outputs: []outputInfo{ 13533 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13534 }, 13535 }, 13536 }, 13537 { 13538 name: "MOVBUload", 13539 auxType: auxSymOff, 13540 argLen: 2, 13541 faultOnNilArg0: true, 13542 asm: mips.AMOVBU, 13543 reg: regInfo{ 13544 inputs: []inputInfo{ 13545 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13546 }, 13547 outputs: []outputInfo{ 13548 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13549 }, 13550 }, 13551 }, 13552 { 13553 name: "MOVHload", 13554 auxType: auxSymOff, 13555 argLen: 2, 13556 faultOnNilArg0: true, 13557 asm: mips.AMOVH, 13558 reg: regInfo{ 13559 inputs: []inputInfo{ 13560 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13561 }, 13562 outputs: []outputInfo{ 13563 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13564 }, 13565 }, 13566 }, 13567 { 13568 name: "MOVHUload", 13569 auxType: auxSymOff, 13570 argLen: 2, 13571 faultOnNilArg0: true, 13572 asm: mips.AMOVHU, 13573 reg: regInfo{ 13574 inputs: []inputInfo{ 13575 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13576 }, 13577 outputs: []outputInfo{ 13578 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13579 }, 13580 }, 13581 }, 13582 { 13583 name: "MOVWload", 13584 auxType: auxSymOff, 13585 argLen: 2, 13586 faultOnNilArg0: true, 13587 asm: mips.AMOVW, 13588 reg: regInfo{ 13589 inputs: []inputInfo{ 13590 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13591 }, 13592 outputs: []outputInfo{ 13593 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13594 }, 13595 }, 13596 }, 13597 { 13598 name: "MOVFload", 13599 auxType: auxSymOff, 13600 argLen: 2, 13601 faultOnNilArg0: true, 13602 asm: mips.AMOVF, 13603 reg: regInfo{ 13604 inputs: []inputInfo{ 13605 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13606 }, 13607 outputs: []outputInfo{ 13608 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13609 }, 13610 }, 13611 }, 13612 { 13613 name: "MOVDload", 13614 auxType: auxSymOff, 13615 argLen: 2, 13616 faultOnNilArg0: true, 13617 asm: mips.AMOVD, 13618 reg: regInfo{ 13619 inputs: []inputInfo{ 13620 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13621 }, 13622 outputs: []outputInfo{ 13623 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13624 }, 13625 }, 13626 }, 13627 { 13628 name: "MOVBstore", 13629 auxType: auxSymOff, 13630 argLen: 3, 13631 faultOnNilArg0: true, 13632 asm: mips.AMOVB, 13633 reg: regInfo{ 13634 inputs: []inputInfo{ 13635 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13636 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13637 }, 13638 }, 13639 }, 13640 { 13641 name: "MOVHstore", 13642 auxType: auxSymOff, 13643 argLen: 3, 13644 faultOnNilArg0: true, 13645 asm: mips.AMOVH, 13646 reg: regInfo{ 13647 inputs: []inputInfo{ 13648 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13649 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13650 }, 13651 }, 13652 }, 13653 { 13654 name: "MOVWstore", 13655 auxType: auxSymOff, 13656 argLen: 3, 13657 faultOnNilArg0: true, 13658 asm: mips.AMOVW, 13659 reg: regInfo{ 13660 inputs: []inputInfo{ 13661 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13662 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13663 }, 13664 }, 13665 }, 13666 { 13667 name: "MOVFstore", 13668 auxType: auxSymOff, 13669 argLen: 3, 13670 faultOnNilArg0: true, 13671 asm: mips.AMOVF, 13672 reg: regInfo{ 13673 inputs: []inputInfo{ 13674 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13675 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13676 }, 13677 }, 13678 }, 13679 { 13680 name: "MOVDstore", 13681 auxType: auxSymOff, 13682 argLen: 3, 13683 faultOnNilArg0: true, 13684 asm: mips.AMOVD, 13685 reg: regInfo{ 13686 inputs: []inputInfo{ 13687 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13688 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13689 }, 13690 }, 13691 }, 13692 { 13693 name: "MOVBstorezero", 13694 auxType: auxSymOff, 13695 argLen: 2, 13696 faultOnNilArg0: true, 13697 asm: mips.AMOVB, 13698 reg: regInfo{ 13699 inputs: []inputInfo{ 13700 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13701 }, 13702 }, 13703 }, 13704 { 13705 name: "MOVHstorezero", 13706 auxType: auxSymOff, 13707 argLen: 2, 13708 faultOnNilArg0: true, 13709 asm: mips.AMOVH, 13710 reg: regInfo{ 13711 inputs: []inputInfo{ 13712 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13713 }, 13714 }, 13715 }, 13716 { 13717 name: "MOVWstorezero", 13718 auxType: auxSymOff, 13719 argLen: 2, 13720 faultOnNilArg0: true, 13721 asm: mips.AMOVW, 13722 reg: regInfo{ 13723 inputs: []inputInfo{ 13724 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13725 }, 13726 }, 13727 }, 13728 { 13729 name: "MOVBreg", 13730 argLen: 1, 13731 asm: mips.AMOVB, 13732 reg: regInfo{ 13733 inputs: []inputInfo{ 13734 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13735 }, 13736 outputs: []outputInfo{ 13737 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13738 }, 13739 }, 13740 }, 13741 { 13742 name: "MOVBUreg", 13743 argLen: 1, 13744 asm: mips.AMOVBU, 13745 reg: regInfo{ 13746 inputs: []inputInfo{ 13747 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13748 }, 13749 outputs: []outputInfo{ 13750 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13751 }, 13752 }, 13753 }, 13754 { 13755 name: "MOVHreg", 13756 argLen: 1, 13757 asm: mips.AMOVH, 13758 reg: regInfo{ 13759 inputs: []inputInfo{ 13760 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13761 }, 13762 outputs: []outputInfo{ 13763 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13764 }, 13765 }, 13766 }, 13767 { 13768 name: "MOVHUreg", 13769 argLen: 1, 13770 asm: mips.AMOVHU, 13771 reg: regInfo{ 13772 inputs: []inputInfo{ 13773 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13774 }, 13775 outputs: []outputInfo{ 13776 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13777 }, 13778 }, 13779 }, 13780 { 13781 name: "MOVWreg", 13782 argLen: 1, 13783 asm: mips.AMOVW, 13784 reg: regInfo{ 13785 inputs: []inputInfo{ 13786 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13787 }, 13788 outputs: []outputInfo{ 13789 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13790 }, 13791 }, 13792 }, 13793 { 13794 name: "MOVWnop", 13795 argLen: 1, 13796 resultInArg0: true, 13797 reg: regInfo{ 13798 inputs: []inputInfo{ 13799 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13800 }, 13801 outputs: []outputInfo{ 13802 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13803 }, 13804 }, 13805 }, 13806 { 13807 name: "CMOVZ", 13808 argLen: 3, 13809 resultInArg0: true, 13810 asm: mips.ACMOVZ, 13811 reg: regInfo{ 13812 inputs: []inputInfo{ 13813 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13814 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13815 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13816 }, 13817 outputs: []outputInfo{ 13818 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13819 }, 13820 }, 13821 }, 13822 { 13823 name: "CMOVZzero", 13824 argLen: 2, 13825 resultInArg0: true, 13826 asm: mips.ACMOVZ, 13827 reg: regInfo{ 13828 inputs: []inputInfo{ 13829 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13830 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13831 }, 13832 outputs: []outputInfo{ 13833 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13834 }, 13835 }, 13836 }, 13837 { 13838 name: "MOVWF", 13839 argLen: 1, 13840 asm: mips.AMOVWF, 13841 reg: regInfo{ 13842 inputs: []inputInfo{ 13843 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13844 }, 13845 outputs: []outputInfo{ 13846 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13847 }, 13848 }, 13849 }, 13850 { 13851 name: "MOVWD", 13852 argLen: 1, 13853 asm: mips.AMOVWD, 13854 reg: regInfo{ 13855 inputs: []inputInfo{ 13856 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13857 }, 13858 outputs: []outputInfo{ 13859 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13860 }, 13861 }, 13862 }, 13863 { 13864 name: "TRUNCFW", 13865 argLen: 1, 13866 asm: mips.ATRUNCFW, 13867 reg: regInfo{ 13868 inputs: []inputInfo{ 13869 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13870 }, 13871 outputs: []outputInfo{ 13872 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13873 }, 13874 }, 13875 }, 13876 { 13877 name: "TRUNCDW", 13878 argLen: 1, 13879 asm: mips.ATRUNCDW, 13880 reg: regInfo{ 13881 inputs: []inputInfo{ 13882 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13883 }, 13884 outputs: []outputInfo{ 13885 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13886 }, 13887 }, 13888 }, 13889 { 13890 name: "MOVFD", 13891 argLen: 1, 13892 asm: mips.AMOVFD, 13893 reg: regInfo{ 13894 inputs: []inputInfo{ 13895 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13896 }, 13897 outputs: []outputInfo{ 13898 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13899 }, 13900 }, 13901 }, 13902 { 13903 name: "MOVDF", 13904 argLen: 1, 13905 asm: mips.AMOVDF, 13906 reg: regInfo{ 13907 inputs: []inputInfo{ 13908 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13909 }, 13910 outputs: []outputInfo{ 13911 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13912 }, 13913 }, 13914 }, 13915 { 13916 name: "CALLstatic", 13917 auxType: auxSymOff, 13918 argLen: 1, 13919 clobberFlags: true, 13920 call: true, 13921 reg: regInfo{ 13922 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13923 }, 13924 }, 13925 { 13926 name: "CALLclosure", 13927 auxType: auxInt32, 13928 argLen: 3, 13929 clobberFlags: true, 13930 call: true, 13931 reg: regInfo{ 13932 inputs: []inputInfo{ 13933 {1, 4194304}, // R22 13934 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 13935 }, 13936 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13937 }, 13938 }, 13939 { 13940 name: "CALLdefer", 13941 auxType: auxInt32, 13942 argLen: 1, 13943 clobberFlags: true, 13944 call: true, 13945 reg: regInfo{ 13946 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13947 }, 13948 }, 13949 { 13950 name: "CALLgo", 13951 auxType: auxInt32, 13952 argLen: 1, 13953 clobberFlags: true, 13954 call: true, 13955 reg: regInfo{ 13956 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13957 }, 13958 }, 13959 { 13960 name: "CALLinter", 13961 auxType: auxInt32, 13962 argLen: 2, 13963 clobberFlags: true, 13964 call: true, 13965 reg: regInfo{ 13966 inputs: []inputInfo{ 13967 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13968 }, 13969 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13970 }, 13971 }, 13972 { 13973 name: "LoweredAtomicLoad", 13974 argLen: 2, 13975 faultOnNilArg0: true, 13976 reg: regInfo{ 13977 inputs: []inputInfo{ 13978 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13979 }, 13980 outputs: []outputInfo{ 13981 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13982 }, 13983 }, 13984 }, 13985 { 13986 name: "LoweredAtomicStore", 13987 argLen: 3, 13988 faultOnNilArg0: true, 13989 reg: regInfo{ 13990 inputs: []inputInfo{ 13991 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13992 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13993 }, 13994 }, 13995 }, 13996 { 13997 name: "LoweredAtomicStorezero", 13998 argLen: 2, 13999 faultOnNilArg0: true, 14000 reg: regInfo{ 14001 inputs: []inputInfo{ 14002 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14003 }, 14004 }, 14005 }, 14006 { 14007 name: "LoweredAtomicExchange", 14008 argLen: 3, 14009 resultNotInArgs: true, 14010 faultOnNilArg0: true, 14011 reg: regInfo{ 14012 inputs: []inputInfo{ 14013 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14014 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14015 }, 14016 outputs: []outputInfo{ 14017 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14018 }, 14019 }, 14020 }, 14021 { 14022 name: "LoweredAtomicAdd", 14023 argLen: 3, 14024 resultNotInArgs: true, 14025 faultOnNilArg0: true, 14026 reg: regInfo{ 14027 inputs: []inputInfo{ 14028 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14029 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14030 }, 14031 outputs: []outputInfo{ 14032 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14033 }, 14034 }, 14035 }, 14036 { 14037 name: "LoweredAtomicAddconst", 14038 auxType: auxInt32, 14039 argLen: 2, 14040 resultNotInArgs: true, 14041 faultOnNilArg0: true, 14042 reg: regInfo{ 14043 inputs: []inputInfo{ 14044 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14045 }, 14046 outputs: []outputInfo{ 14047 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14048 }, 14049 }, 14050 }, 14051 { 14052 name: "LoweredAtomicCas", 14053 argLen: 4, 14054 resultNotInArgs: true, 14055 faultOnNilArg0: true, 14056 reg: regInfo{ 14057 inputs: []inputInfo{ 14058 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14059 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14060 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14061 }, 14062 outputs: []outputInfo{ 14063 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14064 }, 14065 }, 14066 }, 14067 { 14068 name: "LoweredAtomicAnd", 14069 argLen: 3, 14070 faultOnNilArg0: true, 14071 asm: mips.AAND, 14072 reg: regInfo{ 14073 inputs: []inputInfo{ 14074 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14075 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14076 }, 14077 }, 14078 }, 14079 { 14080 name: "LoweredAtomicOr", 14081 argLen: 3, 14082 faultOnNilArg0: true, 14083 asm: mips.AOR, 14084 reg: regInfo{ 14085 inputs: []inputInfo{ 14086 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14087 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14088 }, 14089 }, 14090 }, 14091 { 14092 name: "LoweredZero", 14093 auxType: auxInt32, 14094 argLen: 3, 14095 faultOnNilArg0: true, 14096 reg: regInfo{ 14097 inputs: []inputInfo{ 14098 {0, 2}, // R1 14099 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14100 }, 14101 clobbers: 2, // R1 14102 }, 14103 }, 14104 { 14105 name: "LoweredMove", 14106 auxType: auxInt32, 14107 argLen: 4, 14108 faultOnNilArg0: true, 14109 faultOnNilArg1: true, 14110 reg: regInfo{ 14111 inputs: []inputInfo{ 14112 {0, 4}, // R2 14113 {1, 2}, // R1 14114 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14115 }, 14116 clobbers: 6, // R1 R2 14117 }, 14118 }, 14119 { 14120 name: "LoweredNilCheck", 14121 argLen: 2, 14122 nilCheck: true, 14123 faultOnNilArg0: true, 14124 reg: regInfo{ 14125 inputs: []inputInfo{ 14126 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14127 }, 14128 }, 14129 }, 14130 { 14131 name: "FPFlagTrue", 14132 argLen: 1, 14133 reg: regInfo{ 14134 outputs: []outputInfo{ 14135 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14136 }, 14137 }, 14138 }, 14139 { 14140 name: "FPFlagFalse", 14141 argLen: 1, 14142 reg: regInfo{ 14143 outputs: []outputInfo{ 14144 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14145 }, 14146 }, 14147 }, 14148 { 14149 name: "LoweredGetClosurePtr", 14150 argLen: 0, 14151 reg: regInfo{ 14152 outputs: []outputInfo{ 14153 {0, 4194304}, // R22 14154 }, 14155 }, 14156 }, 14157 { 14158 name: "MOVWconvert", 14159 argLen: 2, 14160 asm: mips.AMOVW, 14161 reg: regInfo{ 14162 inputs: []inputInfo{ 14163 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14164 }, 14165 outputs: []outputInfo{ 14166 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14167 }, 14168 }, 14169 }, 14170 14171 { 14172 name: "ADDV", 14173 argLen: 2, 14174 commutative: true, 14175 asm: mips.AADDVU, 14176 reg: regInfo{ 14177 inputs: []inputInfo{ 14178 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14179 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14180 }, 14181 outputs: []outputInfo{ 14182 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14183 }, 14184 }, 14185 }, 14186 { 14187 name: "ADDVconst", 14188 auxType: auxInt64, 14189 argLen: 1, 14190 asm: mips.AADDVU, 14191 reg: regInfo{ 14192 inputs: []inputInfo{ 14193 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 14194 }, 14195 outputs: []outputInfo{ 14196 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14197 }, 14198 }, 14199 }, 14200 { 14201 name: "SUBV", 14202 argLen: 2, 14203 asm: mips.ASUBVU, 14204 reg: regInfo{ 14205 inputs: []inputInfo{ 14206 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14207 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14208 }, 14209 outputs: []outputInfo{ 14210 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14211 }, 14212 }, 14213 }, 14214 { 14215 name: "SUBVconst", 14216 auxType: auxInt64, 14217 argLen: 1, 14218 asm: mips.ASUBVU, 14219 reg: regInfo{ 14220 inputs: []inputInfo{ 14221 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14222 }, 14223 outputs: []outputInfo{ 14224 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14225 }, 14226 }, 14227 }, 14228 { 14229 name: "MULV", 14230 argLen: 2, 14231 commutative: true, 14232 asm: mips.AMULV, 14233 reg: regInfo{ 14234 inputs: []inputInfo{ 14235 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14236 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14237 }, 14238 outputs: []outputInfo{ 14239 {0, 1152921504606846976}, // HI 14240 {1, 2305843009213693952}, // LO 14241 }, 14242 }, 14243 }, 14244 { 14245 name: "MULVU", 14246 argLen: 2, 14247 commutative: true, 14248 asm: mips.AMULVU, 14249 reg: regInfo{ 14250 inputs: []inputInfo{ 14251 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14252 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14253 }, 14254 outputs: []outputInfo{ 14255 {0, 1152921504606846976}, // HI 14256 {1, 2305843009213693952}, // LO 14257 }, 14258 }, 14259 }, 14260 { 14261 name: "DIVV", 14262 argLen: 2, 14263 asm: mips.ADIVV, 14264 reg: regInfo{ 14265 inputs: []inputInfo{ 14266 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14267 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14268 }, 14269 outputs: []outputInfo{ 14270 {0, 1152921504606846976}, // HI 14271 {1, 2305843009213693952}, // LO 14272 }, 14273 }, 14274 }, 14275 { 14276 name: "DIVVU", 14277 argLen: 2, 14278 asm: mips.ADIVVU, 14279 reg: regInfo{ 14280 inputs: []inputInfo{ 14281 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14282 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14283 }, 14284 outputs: []outputInfo{ 14285 {0, 1152921504606846976}, // HI 14286 {1, 2305843009213693952}, // LO 14287 }, 14288 }, 14289 }, 14290 { 14291 name: "ADDF", 14292 argLen: 2, 14293 commutative: true, 14294 asm: mips.AADDF, 14295 reg: regInfo{ 14296 inputs: []inputInfo{ 14297 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14298 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14299 }, 14300 outputs: []outputInfo{ 14301 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14302 }, 14303 }, 14304 }, 14305 { 14306 name: "ADDD", 14307 argLen: 2, 14308 commutative: true, 14309 asm: mips.AADDD, 14310 reg: regInfo{ 14311 inputs: []inputInfo{ 14312 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14313 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14314 }, 14315 outputs: []outputInfo{ 14316 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14317 }, 14318 }, 14319 }, 14320 { 14321 name: "SUBF", 14322 argLen: 2, 14323 asm: mips.ASUBF, 14324 reg: regInfo{ 14325 inputs: []inputInfo{ 14326 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14327 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14328 }, 14329 outputs: []outputInfo{ 14330 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14331 }, 14332 }, 14333 }, 14334 { 14335 name: "SUBD", 14336 argLen: 2, 14337 asm: mips.ASUBD, 14338 reg: regInfo{ 14339 inputs: []inputInfo{ 14340 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14341 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14342 }, 14343 outputs: []outputInfo{ 14344 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14345 }, 14346 }, 14347 }, 14348 { 14349 name: "MULF", 14350 argLen: 2, 14351 commutative: true, 14352 asm: mips.AMULF, 14353 reg: regInfo{ 14354 inputs: []inputInfo{ 14355 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14356 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14357 }, 14358 outputs: []outputInfo{ 14359 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14360 }, 14361 }, 14362 }, 14363 { 14364 name: "MULD", 14365 argLen: 2, 14366 commutative: true, 14367 asm: mips.AMULD, 14368 reg: regInfo{ 14369 inputs: []inputInfo{ 14370 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14371 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14372 }, 14373 outputs: []outputInfo{ 14374 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14375 }, 14376 }, 14377 }, 14378 { 14379 name: "DIVF", 14380 argLen: 2, 14381 asm: mips.ADIVF, 14382 reg: regInfo{ 14383 inputs: []inputInfo{ 14384 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14385 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14386 }, 14387 outputs: []outputInfo{ 14388 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14389 }, 14390 }, 14391 }, 14392 { 14393 name: "DIVD", 14394 argLen: 2, 14395 asm: mips.ADIVD, 14396 reg: regInfo{ 14397 inputs: []inputInfo{ 14398 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14399 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14400 }, 14401 outputs: []outputInfo{ 14402 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14403 }, 14404 }, 14405 }, 14406 { 14407 name: "AND", 14408 argLen: 2, 14409 commutative: true, 14410 asm: mips.AAND, 14411 reg: regInfo{ 14412 inputs: []inputInfo{ 14413 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14414 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14415 }, 14416 outputs: []outputInfo{ 14417 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14418 }, 14419 }, 14420 }, 14421 { 14422 name: "ANDconst", 14423 auxType: auxInt64, 14424 argLen: 1, 14425 asm: mips.AAND, 14426 reg: regInfo{ 14427 inputs: []inputInfo{ 14428 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14429 }, 14430 outputs: []outputInfo{ 14431 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14432 }, 14433 }, 14434 }, 14435 { 14436 name: "OR", 14437 argLen: 2, 14438 commutative: true, 14439 asm: mips.AOR, 14440 reg: regInfo{ 14441 inputs: []inputInfo{ 14442 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14443 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14444 }, 14445 outputs: []outputInfo{ 14446 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14447 }, 14448 }, 14449 }, 14450 { 14451 name: "ORconst", 14452 auxType: auxInt64, 14453 argLen: 1, 14454 asm: mips.AOR, 14455 reg: regInfo{ 14456 inputs: []inputInfo{ 14457 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14458 }, 14459 outputs: []outputInfo{ 14460 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14461 }, 14462 }, 14463 }, 14464 { 14465 name: "XOR", 14466 argLen: 2, 14467 commutative: true, 14468 asm: mips.AXOR, 14469 reg: regInfo{ 14470 inputs: []inputInfo{ 14471 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14472 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14473 }, 14474 outputs: []outputInfo{ 14475 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14476 }, 14477 }, 14478 }, 14479 { 14480 name: "XORconst", 14481 auxType: auxInt64, 14482 argLen: 1, 14483 asm: mips.AXOR, 14484 reg: regInfo{ 14485 inputs: []inputInfo{ 14486 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14487 }, 14488 outputs: []outputInfo{ 14489 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14490 }, 14491 }, 14492 }, 14493 { 14494 name: "NOR", 14495 argLen: 2, 14496 commutative: true, 14497 asm: mips.ANOR, 14498 reg: regInfo{ 14499 inputs: []inputInfo{ 14500 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14501 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14502 }, 14503 outputs: []outputInfo{ 14504 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14505 }, 14506 }, 14507 }, 14508 { 14509 name: "NORconst", 14510 auxType: auxInt64, 14511 argLen: 1, 14512 asm: mips.ANOR, 14513 reg: regInfo{ 14514 inputs: []inputInfo{ 14515 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14516 }, 14517 outputs: []outputInfo{ 14518 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14519 }, 14520 }, 14521 }, 14522 { 14523 name: "NEGV", 14524 argLen: 1, 14525 reg: regInfo{ 14526 inputs: []inputInfo{ 14527 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14528 }, 14529 outputs: []outputInfo{ 14530 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14531 }, 14532 }, 14533 }, 14534 { 14535 name: "NEGF", 14536 argLen: 1, 14537 asm: mips.ANEGF, 14538 reg: regInfo{ 14539 inputs: []inputInfo{ 14540 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14541 }, 14542 outputs: []outputInfo{ 14543 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14544 }, 14545 }, 14546 }, 14547 { 14548 name: "NEGD", 14549 argLen: 1, 14550 asm: mips.ANEGD, 14551 reg: regInfo{ 14552 inputs: []inputInfo{ 14553 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14554 }, 14555 outputs: []outputInfo{ 14556 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14557 }, 14558 }, 14559 }, 14560 { 14561 name: "SLLV", 14562 argLen: 2, 14563 asm: mips.ASLLV, 14564 reg: regInfo{ 14565 inputs: []inputInfo{ 14566 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14567 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14568 }, 14569 outputs: []outputInfo{ 14570 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14571 }, 14572 }, 14573 }, 14574 { 14575 name: "SLLVconst", 14576 auxType: auxInt64, 14577 argLen: 1, 14578 asm: mips.ASLLV, 14579 reg: regInfo{ 14580 inputs: []inputInfo{ 14581 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14582 }, 14583 outputs: []outputInfo{ 14584 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14585 }, 14586 }, 14587 }, 14588 { 14589 name: "SRLV", 14590 argLen: 2, 14591 asm: mips.ASRLV, 14592 reg: regInfo{ 14593 inputs: []inputInfo{ 14594 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14595 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14596 }, 14597 outputs: []outputInfo{ 14598 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14599 }, 14600 }, 14601 }, 14602 { 14603 name: "SRLVconst", 14604 auxType: auxInt64, 14605 argLen: 1, 14606 asm: mips.ASRLV, 14607 reg: regInfo{ 14608 inputs: []inputInfo{ 14609 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14610 }, 14611 outputs: []outputInfo{ 14612 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14613 }, 14614 }, 14615 }, 14616 { 14617 name: "SRAV", 14618 argLen: 2, 14619 asm: mips.ASRAV, 14620 reg: regInfo{ 14621 inputs: []inputInfo{ 14622 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14623 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14624 }, 14625 outputs: []outputInfo{ 14626 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14627 }, 14628 }, 14629 }, 14630 { 14631 name: "SRAVconst", 14632 auxType: auxInt64, 14633 argLen: 1, 14634 asm: mips.ASRAV, 14635 reg: regInfo{ 14636 inputs: []inputInfo{ 14637 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14638 }, 14639 outputs: []outputInfo{ 14640 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14641 }, 14642 }, 14643 }, 14644 { 14645 name: "SGT", 14646 argLen: 2, 14647 asm: mips.ASGT, 14648 reg: regInfo{ 14649 inputs: []inputInfo{ 14650 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14651 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14652 }, 14653 outputs: []outputInfo{ 14654 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14655 }, 14656 }, 14657 }, 14658 { 14659 name: "SGTconst", 14660 auxType: auxInt64, 14661 argLen: 1, 14662 asm: mips.ASGT, 14663 reg: regInfo{ 14664 inputs: []inputInfo{ 14665 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14666 }, 14667 outputs: []outputInfo{ 14668 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14669 }, 14670 }, 14671 }, 14672 { 14673 name: "SGTU", 14674 argLen: 2, 14675 asm: mips.ASGTU, 14676 reg: regInfo{ 14677 inputs: []inputInfo{ 14678 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14679 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14680 }, 14681 outputs: []outputInfo{ 14682 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14683 }, 14684 }, 14685 }, 14686 { 14687 name: "SGTUconst", 14688 auxType: auxInt64, 14689 argLen: 1, 14690 asm: mips.ASGTU, 14691 reg: regInfo{ 14692 inputs: []inputInfo{ 14693 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14694 }, 14695 outputs: []outputInfo{ 14696 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14697 }, 14698 }, 14699 }, 14700 { 14701 name: "CMPEQF", 14702 argLen: 2, 14703 asm: mips.ACMPEQF, 14704 reg: regInfo{ 14705 inputs: []inputInfo{ 14706 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14707 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14708 }, 14709 }, 14710 }, 14711 { 14712 name: "CMPEQD", 14713 argLen: 2, 14714 asm: mips.ACMPEQD, 14715 reg: regInfo{ 14716 inputs: []inputInfo{ 14717 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14718 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14719 }, 14720 }, 14721 }, 14722 { 14723 name: "CMPGEF", 14724 argLen: 2, 14725 asm: mips.ACMPGEF, 14726 reg: regInfo{ 14727 inputs: []inputInfo{ 14728 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14729 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14730 }, 14731 }, 14732 }, 14733 { 14734 name: "CMPGED", 14735 argLen: 2, 14736 asm: mips.ACMPGED, 14737 reg: regInfo{ 14738 inputs: []inputInfo{ 14739 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14740 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14741 }, 14742 }, 14743 }, 14744 { 14745 name: "CMPGTF", 14746 argLen: 2, 14747 asm: mips.ACMPGTF, 14748 reg: regInfo{ 14749 inputs: []inputInfo{ 14750 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14751 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14752 }, 14753 }, 14754 }, 14755 { 14756 name: "CMPGTD", 14757 argLen: 2, 14758 asm: mips.ACMPGTD, 14759 reg: regInfo{ 14760 inputs: []inputInfo{ 14761 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14762 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14763 }, 14764 }, 14765 }, 14766 { 14767 name: "MOVVconst", 14768 auxType: auxInt64, 14769 argLen: 0, 14770 rematerializeable: true, 14771 asm: mips.AMOVV, 14772 reg: regInfo{ 14773 outputs: []outputInfo{ 14774 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14775 }, 14776 }, 14777 }, 14778 { 14779 name: "MOVFconst", 14780 auxType: auxFloat64, 14781 argLen: 0, 14782 rematerializeable: true, 14783 asm: mips.AMOVF, 14784 reg: regInfo{ 14785 outputs: []outputInfo{ 14786 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14787 }, 14788 }, 14789 }, 14790 { 14791 name: "MOVDconst", 14792 auxType: auxFloat64, 14793 argLen: 0, 14794 rematerializeable: true, 14795 asm: mips.AMOVD, 14796 reg: regInfo{ 14797 outputs: []outputInfo{ 14798 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14799 }, 14800 }, 14801 }, 14802 { 14803 name: "MOVVaddr", 14804 auxType: auxSymOff, 14805 argLen: 1, 14806 rematerializeable: true, 14807 asm: mips.AMOVV, 14808 reg: regInfo{ 14809 inputs: []inputInfo{ 14810 {0, 4611686018460942336}, // SP SB 14811 }, 14812 outputs: []outputInfo{ 14813 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14814 }, 14815 }, 14816 }, 14817 { 14818 name: "MOVBload", 14819 auxType: auxSymOff, 14820 argLen: 2, 14821 faultOnNilArg0: true, 14822 asm: mips.AMOVB, 14823 reg: regInfo{ 14824 inputs: []inputInfo{ 14825 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14826 }, 14827 outputs: []outputInfo{ 14828 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14829 }, 14830 }, 14831 }, 14832 { 14833 name: "MOVBUload", 14834 auxType: auxSymOff, 14835 argLen: 2, 14836 faultOnNilArg0: true, 14837 asm: mips.AMOVBU, 14838 reg: regInfo{ 14839 inputs: []inputInfo{ 14840 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14841 }, 14842 outputs: []outputInfo{ 14843 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14844 }, 14845 }, 14846 }, 14847 { 14848 name: "MOVHload", 14849 auxType: auxSymOff, 14850 argLen: 2, 14851 faultOnNilArg0: true, 14852 asm: mips.AMOVH, 14853 reg: regInfo{ 14854 inputs: []inputInfo{ 14855 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14856 }, 14857 outputs: []outputInfo{ 14858 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14859 }, 14860 }, 14861 }, 14862 { 14863 name: "MOVHUload", 14864 auxType: auxSymOff, 14865 argLen: 2, 14866 faultOnNilArg0: true, 14867 asm: mips.AMOVHU, 14868 reg: regInfo{ 14869 inputs: []inputInfo{ 14870 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14871 }, 14872 outputs: []outputInfo{ 14873 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14874 }, 14875 }, 14876 }, 14877 { 14878 name: "MOVWload", 14879 auxType: auxSymOff, 14880 argLen: 2, 14881 faultOnNilArg0: true, 14882 asm: mips.AMOVW, 14883 reg: regInfo{ 14884 inputs: []inputInfo{ 14885 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14886 }, 14887 outputs: []outputInfo{ 14888 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14889 }, 14890 }, 14891 }, 14892 { 14893 name: "MOVWUload", 14894 auxType: auxSymOff, 14895 argLen: 2, 14896 faultOnNilArg0: true, 14897 asm: mips.AMOVWU, 14898 reg: regInfo{ 14899 inputs: []inputInfo{ 14900 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14901 }, 14902 outputs: []outputInfo{ 14903 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14904 }, 14905 }, 14906 }, 14907 { 14908 name: "MOVVload", 14909 auxType: auxSymOff, 14910 argLen: 2, 14911 faultOnNilArg0: true, 14912 asm: mips.AMOVV, 14913 reg: regInfo{ 14914 inputs: []inputInfo{ 14915 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14916 }, 14917 outputs: []outputInfo{ 14918 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14919 }, 14920 }, 14921 }, 14922 { 14923 name: "MOVFload", 14924 auxType: auxSymOff, 14925 argLen: 2, 14926 faultOnNilArg0: true, 14927 asm: mips.AMOVF, 14928 reg: regInfo{ 14929 inputs: []inputInfo{ 14930 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14931 }, 14932 outputs: []outputInfo{ 14933 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14934 }, 14935 }, 14936 }, 14937 { 14938 name: "MOVDload", 14939 auxType: auxSymOff, 14940 argLen: 2, 14941 faultOnNilArg0: true, 14942 asm: mips.AMOVD, 14943 reg: regInfo{ 14944 inputs: []inputInfo{ 14945 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14946 }, 14947 outputs: []outputInfo{ 14948 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14949 }, 14950 }, 14951 }, 14952 { 14953 name: "MOVBstore", 14954 auxType: auxSymOff, 14955 argLen: 3, 14956 faultOnNilArg0: true, 14957 asm: mips.AMOVB, 14958 reg: regInfo{ 14959 inputs: []inputInfo{ 14960 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14961 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14962 }, 14963 }, 14964 }, 14965 { 14966 name: "MOVHstore", 14967 auxType: auxSymOff, 14968 argLen: 3, 14969 faultOnNilArg0: true, 14970 asm: mips.AMOVH, 14971 reg: regInfo{ 14972 inputs: []inputInfo{ 14973 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14974 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14975 }, 14976 }, 14977 }, 14978 { 14979 name: "MOVWstore", 14980 auxType: auxSymOff, 14981 argLen: 3, 14982 faultOnNilArg0: true, 14983 asm: mips.AMOVW, 14984 reg: regInfo{ 14985 inputs: []inputInfo{ 14986 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14987 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14988 }, 14989 }, 14990 }, 14991 { 14992 name: "MOVVstore", 14993 auxType: auxSymOff, 14994 argLen: 3, 14995 faultOnNilArg0: true, 14996 asm: mips.AMOVV, 14997 reg: regInfo{ 14998 inputs: []inputInfo{ 14999 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15000 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15001 }, 15002 }, 15003 }, 15004 { 15005 name: "MOVFstore", 15006 auxType: auxSymOff, 15007 argLen: 3, 15008 faultOnNilArg0: true, 15009 asm: mips.AMOVF, 15010 reg: regInfo{ 15011 inputs: []inputInfo{ 15012 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15013 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15014 }, 15015 }, 15016 }, 15017 { 15018 name: "MOVDstore", 15019 auxType: auxSymOff, 15020 argLen: 3, 15021 faultOnNilArg0: true, 15022 asm: mips.AMOVD, 15023 reg: regInfo{ 15024 inputs: []inputInfo{ 15025 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15026 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15027 }, 15028 }, 15029 }, 15030 { 15031 name: "MOVBstorezero", 15032 auxType: auxSymOff, 15033 argLen: 2, 15034 faultOnNilArg0: true, 15035 asm: mips.AMOVB, 15036 reg: regInfo{ 15037 inputs: []inputInfo{ 15038 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15039 }, 15040 }, 15041 }, 15042 { 15043 name: "MOVHstorezero", 15044 auxType: auxSymOff, 15045 argLen: 2, 15046 faultOnNilArg0: true, 15047 asm: mips.AMOVH, 15048 reg: regInfo{ 15049 inputs: []inputInfo{ 15050 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15051 }, 15052 }, 15053 }, 15054 { 15055 name: "MOVWstorezero", 15056 auxType: auxSymOff, 15057 argLen: 2, 15058 faultOnNilArg0: true, 15059 asm: mips.AMOVW, 15060 reg: regInfo{ 15061 inputs: []inputInfo{ 15062 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15063 }, 15064 }, 15065 }, 15066 { 15067 name: "MOVVstorezero", 15068 auxType: auxSymOff, 15069 argLen: 2, 15070 faultOnNilArg0: true, 15071 asm: mips.AMOVV, 15072 reg: regInfo{ 15073 inputs: []inputInfo{ 15074 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15075 }, 15076 }, 15077 }, 15078 { 15079 name: "MOVBreg", 15080 argLen: 1, 15081 asm: mips.AMOVB, 15082 reg: regInfo{ 15083 inputs: []inputInfo{ 15084 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15085 }, 15086 outputs: []outputInfo{ 15087 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15088 }, 15089 }, 15090 }, 15091 { 15092 name: "MOVBUreg", 15093 argLen: 1, 15094 asm: mips.AMOVBU, 15095 reg: regInfo{ 15096 inputs: []inputInfo{ 15097 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15098 }, 15099 outputs: []outputInfo{ 15100 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15101 }, 15102 }, 15103 }, 15104 { 15105 name: "MOVHreg", 15106 argLen: 1, 15107 asm: mips.AMOVH, 15108 reg: regInfo{ 15109 inputs: []inputInfo{ 15110 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15111 }, 15112 outputs: []outputInfo{ 15113 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15114 }, 15115 }, 15116 }, 15117 { 15118 name: "MOVHUreg", 15119 argLen: 1, 15120 asm: mips.AMOVHU, 15121 reg: regInfo{ 15122 inputs: []inputInfo{ 15123 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15124 }, 15125 outputs: []outputInfo{ 15126 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15127 }, 15128 }, 15129 }, 15130 { 15131 name: "MOVWreg", 15132 argLen: 1, 15133 asm: mips.AMOVW, 15134 reg: regInfo{ 15135 inputs: []inputInfo{ 15136 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15137 }, 15138 outputs: []outputInfo{ 15139 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15140 }, 15141 }, 15142 }, 15143 { 15144 name: "MOVWUreg", 15145 argLen: 1, 15146 asm: mips.AMOVWU, 15147 reg: regInfo{ 15148 inputs: []inputInfo{ 15149 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15150 }, 15151 outputs: []outputInfo{ 15152 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15153 }, 15154 }, 15155 }, 15156 { 15157 name: "MOVVreg", 15158 argLen: 1, 15159 asm: mips.AMOVV, 15160 reg: regInfo{ 15161 inputs: []inputInfo{ 15162 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15163 }, 15164 outputs: []outputInfo{ 15165 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15166 }, 15167 }, 15168 }, 15169 { 15170 name: "MOVVnop", 15171 argLen: 1, 15172 resultInArg0: true, 15173 reg: regInfo{ 15174 inputs: []inputInfo{ 15175 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15176 }, 15177 outputs: []outputInfo{ 15178 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15179 }, 15180 }, 15181 }, 15182 { 15183 name: "MOVWF", 15184 argLen: 1, 15185 asm: mips.AMOVWF, 15186 reg: regInfo{ 15187 inputs: []inputInfo{ 15188 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15189 }, 15190 outputs: []outputInfo{ 15191 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15192 }, 15193 }, 15194 }, 15195 { 15196 name: "MOVWD", 15197 argLen: 1, 15198 asm: mips.AMOVWD, 15199 reg: regInfo{ 15200 inputs: []inputInfo{ 15201 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15202 }, 15203 outputs: []outputInfo{ 15204 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15205 }, 15206 }, 15207 }, 15208 { 15209 name: "MOVVF", 15210 argLen: 1, 15211 asm: mips.AMOVVF, 15212 reg: regInfo{ 15213 inputs: []inputInfo{ 15214 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15215 }, 15216 outputs: []outputInfo{ 15217 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15218 }, 15219 }, 15220 }, 15221 { 15222 name: "MOVVD", 15223 argLen: 1, 15224 asm: mips.AMOVVD, 15225 reg: regInfo{ 15226 inputs: []inputInfo{ 15227 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15228 }, 15229 outputs: []outputInfo{ 15230 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15231 }, 15232 }, 15233 }, 15234 { 15235 name: "TRUNCFW", 15236 argLen: 1, 15237 asm: mips.ATRUNCFW, 15238 reg: regInfo{ 15239 inputs: []inputInfo{ 15240 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15241 }, 15242 outputs: []outputInfo{ 15243 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15244 }, 15245 }, 15246 }, 15247 { 15248 name: "TRUNCDW", 15249 argLen: 1, 15250 asm: mips.ATRUNCDW, 15251 reg: regInfo{ 15252 inputs: []inputInfo{ 15253 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15254 }, 15255 outputs: []outputInfo{ 15256 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15257 }, 15258 }, 15259 }, 15260 { 15261 name: "TRUNCFV", 15262 argLen: 1, 15263 asm: mips.ATRUNCFV, 15264 reg: regInfo{ 15265 inputs: []inputInfo{ 15266 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15267 }, 15268 outputs: []outputInfo{ 15269 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15270 }, 15271 }, 15272 }, 15273 { 15274 name: "TRUNCDV", 15275 argLen: 1, 15276 asm: mips.ATRUNCDV, 15277 reg: regInfo{ 15278 inputs: []inputInfo{ 15279 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15280 }, 15281 outputs: []outputInfo{ 15282 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15283 }, 15284 }, 15285 }, 15286 { 15287 name: "MOVFD", 15288 argLen: 1, 15289 asm: mips.AMOVFD, 15290 reg: regInfo{ 15291 inputs: []inputInfo{ 15292 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15293 }, 15294 outputs: []outputInfo{ 15295 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15296 }, 15297 }, 15298 }, 15299 { 15300 name: "MOVDF", 15301 argLen: 1, 15302 asm: mips.AMOVDF, 15303 reg: regInfo{ 15304 inputs: []inputInfo{ 15305 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15306 }, 15307 outputs: []outputInfo{ 15308 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15309 }, 15310 }, 15311 }, 15312 { 15313 name: "CALLstatic", 15314 auxType: auxSymOff, 15315 argLen: 1, 15316 clobberFlags: true, 15317 call: true, 15318 reg: regInfo{ 15319 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15320 }, 15321 }, 15322 { 15323 name: "CALLclosure", 15324 auxType: auxInt64, 15325 argLen: 3, 15326 clobberFlags: true, 15327 call: true, 15328 reg: regInfo{ 15329 inputs: []inputInfo{ 15330 {1, 4194304}, // R22 15331 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 15332 }, 15333 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15334 }, 15335 }, 15336 { 15337 name: "CALLdefer", 15338 auxType: auxInt64, 15339 argLen: 1, 15340 clobberFlags: true, 15341 call: true, 15342 reg: regInfo{ 15343 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15344 }, 15345 }, 15346 { 15347 name: "CALLgo", 15348 auxType: auxInt64, 15349 argLen: 1, 15350 clobberFlags: true, 15351 call: true, 15352 reg: regInfo{ 15353 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15354 }, 15355 }, 15356 { 15357 name: "CALLinter", 15358 auxType: auxInt64, 15359 argLen: 2, 15360 clobberFlags: true, 15361 call: true, 15362 reg: regInfo{ 15363 inputs: []inputInfo{ 15364 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15365 }, 15366 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15367 }, 15368 }, 15369 { 15370 name: "DUFFZERO", 15371 auxType: auxInt64, 15372 argLen: 2, 15373 faultOnNilArg0: true, 15374 reg: regInfo{ 15375 inputs: []inputInfo{ 15376 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15377 }, 15378 clobbers: 134217730, // R1 R31 15379 }, 15380 }, 15381 { 15382 name: "LoweredZero", 15383 auxType: auxInt64, 15384 argLen: 3, 15385 clobberFlags: true, 15386 faultOnNilArg0: true, 15387 reg: regInfo{ 15388 inputs: []inputInfo{ 15389 {0, 2}, // R1 15390 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15391 }, 15392 clobbers: 2, // R1 15393 }, 15394 }, 15395 { 15396 name: "LoweredMove", 15397 auxType: auxInt64, 15398 argLen: 4, 15399 clobberFlags: true, 15400 faultOnNilArg0: true, 15401 faultOnNilArg1: true, 15402 reg: regInfo{ 15403 inputs: []inputInfo{ 15404 {0, 4}, // R2 15405 {1, 2}, // R1 15406 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15407 }, 15408 clobbers: 6, // R1 R2 15409 }, 15410 }, 15411 { 15412 name: "LoweredNilCheck", 15413 argLen: 2, 15414 nilCheck: true, 15415 faultOnNilArg0: true, 15416 reg: regInfo{ 15417 inputs: []inputInfo{ 15418 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15419 }, 15420 }, 15421 }, 15422 { 15423 name: "FPFlagTrue", 15424 argLen: 1, 15425 reg: regInfo{ 15426 outputs: []outputInfo{ 15427 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15428 }, 15429 }, 15430 }, 15431 { 15432 name: "FPFlagFalse", 15433 argLen: 1, 15434 reg: regInfo{ 15435 outputs: []outputInfo{ 15436 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15437 }, 15438 }, 15439 }, 15440 { 15441 name: "LoweredGetClosurePtr", 15442 argLen: 0, 15443 reg: regInfo{ 15444 outputs: []outputInfo{ 15445 {0, 4194304}, // R22 15446 }, 15447 }, 15448 }, 15449 { 15450 name: "MOVVconvert", 15451 argLen: 2, 15452 asm: mips.AMOVV, 15453 reg: regInfo{ 15454 inputs: []inputInfo{ 15455 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15456 }, 15457 outputs: []outputInfo{ 15458 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15459 }, 15460 }, 15461 }, 15462 15463 { 15464 name: "ADD", 15465 argLen: 2, 15466 commutative: true, 15467 asm: ppc64.AADD, 15468 reg: regInfo{ 15469 inputs: []inputInfo{ 15470 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15471 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15472 }, 15473 outputs: []outputInfo{ 15474 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15475 }, 15476 }, 15477 }, 15478 { 15479 name: "ADDconst", 15480 auxType: auxSymOff, 15481 argLen: 1, 15482 asm: ppc64.AADD, 15483 reg: regInfo{ 15484 inputs: []inputInfo{ 15485 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15486 }, 15487 outputs: []outputInfo{ 15488 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15489 }, 15490 }, 15491 }, 15492 { 15493 name: "FADD", 15494 argLen: 2, 15495 commutative: true, 15496 asm: ppc64.AFADD, 15497 reg: regInfo{ 15498 inputs: []inputInfo{ 15499 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15500 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15501 }, 15502 outputs: []outputInfo{ 15503 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15504 }, 15505 }, 15506 }, 15507 { 15508 name: "FADDS", 15509 argLen: 2, 15510 commutative: true, 15511 asm: ppc64.AFADDS, 15512 reg: regInfo{ 15513 inputs: []inputInfo{ 15514 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15515 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15516 }, 15517 outputs: []outputInfo{ 15518 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15519 }, 15520 }, 15521 }, 15522 { 15523 name: "SUB", 15524 argLen: 2, 15525 asm: ppc64.ASUB, 15526 reg: regInfo{ 15527 inputs: []inputInfo{ 15528 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15529 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15530 }, 15531 outputs: []outputInfo{ 15532 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15533 }, 15534 }, 15535 }, 15536 { 15537 name: "FSUB", 15538 argLen: 2, 15539 asm: ppc64.AFSUB, 15540 reg: regInfo{ 15541 inputs: []inputInfo{ 15542 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15543 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15544 }, 15545 outputs: []outputInfo{ 15546 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15547 }, 15548 }, 15549 }, 15550 { 15551 name: "FSUBS", 15552 argLen: 2, 15553 asm: ppc64.AFSUBS, 15554 reg: regInfo{ 15555 inputs: []inputInfo{ 15556 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15557 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15558 }, 15559 outputs: []outputInfo{ 15560 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15561 }, 15562 }, 15563 }, 15564 { 15565 name: "MULLD", 15566 argLen: 2, 15567 commutative: true, 15568 asm: ppc64.AMULLD, 15569 reg: regInfo{ 15570 inputs: []inputInfo{ 15571 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15572 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15573 }, 15574 outputs: []outputInfo{ 15575 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15576 }, 15577 }, 15578 }, 15579 { 15580 name: "MULLW", 15581 argLen: 2, 15582 commutative: true, 15583 asm: ppc64.AMULLW, 15584 reg: regInfo{ 15585 inputs: []inputInfo{ 15586 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15587 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15588 }, 15589 outputs: []outputInfo{ 15590 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15591 }, 15592 }, 15593 }, 15594 { 15595 name: "MULHD", 15596 argLen: 2, 15597 commutative: true, 15598 asm: ppc64.AMULHD, 15599 reg: regInfo{ 15600 inputs: []inputInfo{ 15601 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15602 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15603 }, 15604 outputs: []outputInfo{ 15605 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15606 }, 15607 }, 15608 }, 15609 { 15610 name: "MULHW", 15611 argLen: 2, 15612 commutative: true, 15613 asm: ppc64.AMULHW, 15614 reg: regInfo{ 15615 inputs: []inputInfo{ 15616 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15617 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15618 }, 15619 outputs: []outputInfo{ 15620 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15621 }, 15622 }, 15623 }, 15624 { 15625 name: "MULHDU", 15626 argLen: 2, 15627 commutative: true, 15628 asm: ppc64.AMULHDU, 15629 reg: regInfo{ 15630 inputs: []inputInfo{ 15631 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15632 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15633 }, 15634 outputs: []outputInfo{ 15635 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15636 }, 15637 }, 15638 }, 15639 { 15640 name: "MULHWU", 15641 argLen: 2, 15642 commutative: true, 15643 asm: ppc64.AMULHWU, 15644 reg: regInfo{ 15645 inputs: []inputInfo{ 15646 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15647 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15648 }, 15649 outputs: []outputInfo{ 15650 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15651 }, 15652 }, 15653 }, 15654 { 15655 name: "FMUL", 15656 argLen: 2, 15657 commutative: true, 15658 asm: ppc64.AFMUL, 15659 reg: regInfo{ 15660 inputs: []inputInfo{ 15661 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15662 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15663 }, 15664 outputs: []outputInfo{ 15665 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15666 }, 15667 }, 15668 }, 15669 { 15670 name: "FMULS", 15671 argLen: 2, 15672 commutative: true, 15673 asm: ppc64.AFMULS, 15674 reg: regInfo{ 15675 inputs: []inputInfo{ 15676 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15677 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15678 }, 15679 outputs: []outputInfo{ 15680 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15681 }, 15682 }, 15683 }, 15684 { 15685 name: "SRAD", 15686 argLen: 2, 15687 asm: ppc64.ASRAD, 15688 reg: regInfo{ 15689 inputs: []inputInfo{ 15690 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15691 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15692 }, 15693 outputs: []outputInfo{ 15694 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15695 }, 15696 }, 15697 }, 15698 { 15699 name: "SRAW", 15700 argLen: 2, 15701 asm: ppc64.ASRAW, 15702 reg: regInfo{ 15703 inputs: []inputInfo{ 15704 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15705 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15706 }, 15707 outputs: []outputInfo{ 15708 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15709 }, 15710 }, 15711 }, 15712 { 15713 name: "SRD", 15714 argLen: 2, 15715 asm: ppc64.ASRD, 15716 reg: regInfo{ 15717 inputs: []inputInfo{ 15718 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15719 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15720 }, 15721 outputs: []outputInfo{ 15722 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15723 }, 15724 }, 15725 }, 15726 { 15727 name: "SRW", 15728 argLen: 2, 15729 asm: ppc64.ASRW, 15730 reg: regInfo{ 15731 inputs: []inputInfo{ 15732 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15733 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15734 }, 15735 outputs: []outputInfo{ 15736 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15737 }, 15738 }, 15739 }, 15740 { 15741 name: "SLD", 15742 argLen: 2, 15743 asm: ppc64.ASLD, 15744 reg: regInfo{ 15745 inputs: []inputInfo{ 15746 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15747 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15748 }, 15749 outputs: []outputInfo{ 15750 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15751 }, 15752 }, 15753 }, 15754 { 15755 name: "SLW", 15756 argLen: 2, 15757 asm: ppc64.ASLW, 15758 reg: regInfo{ 15759 inputs: []inputInfo{ 15760 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15761 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15762 }, 15763 outputs: []outputInfo{ 15764 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15765 }, 15766 }, 15767 }, 15768 { 15769 name: "ADDconstForCarry", 15770 auxType: auxInt16, 15771 argLen: 1, 15772 asm: ppc64.AADDC, 15773 reg: regInfo{ 15774 inputs: []inputInfo{ 15775 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15776 }, 15777 clobbers: 2147483648, // R31 15778 }, 15779 }, 15780 { 15781 name: "MaskIfNotCarry", 15782 argLen: 1, 15783 asm: ppc64.AADDME, 15784 reg: regInfo{ 15785 outputs: []outputInfo{ 15786 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15787 }, 15788 }, 15789 }, 15790 { 15791 name: "SRADconst", 15792 auxType: auxInt64, 15793 argLen: 1, 15794 asm: ppc64.ASRAD, 15795 reg: regInfo{ 15796 inputs: []inputInfo{ 15797 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15798 }, 15799 outputs: []outputInfo{ 15800 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15801 }, 15802 }, 15803 }, 15804 { 15805 name: "SRAWconst", 15806 auxType: auxInt64, 15807 argLen: 1, 15808 asm: ppc64.ASRAW, 15809 reg: regInfo{ 15810 inputs: []inputInfo{ 15811 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15812 }, 15813 outputs: []outputInfo{ 15814 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15815 }, 15816 }, 15817 }, 15818 { 15819 name: "SRDconst", 15820 auxType: auxInt64, 15821 argLen: 1, 15822 asm: ppc64.ASRD, 15823 reg: regInfo{ 15824 inputs: []inputInfo{ 15825 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15826 }, 15827 outputs: []outputInfo{ 15828 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15829 }, 15830 }, 15831 }, 15832 { 15833 name: "SRWconst", 15834 auxType: auxInt64, 15835 argLen: 1, 15836 asm: ppc64.ASRW, 15837 reg: regInfo{ 15838 inputs: []inputInfo{ 15839 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15840 }, 15841 outputs: []outputInfo{ 15842 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15843 }, 15844 }, 15845 }, 15846 { 15847 name: "SLDconst", 15848 auxType: auxInt64, 15849 argLen: 1, 15850 asm: ppc64.ASLD, 15851 reg: regInfo{ 15852 inputs: []inputInfo{ 15853 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15854 }, 15855 outputs: []outputInfo{ 15856 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15857 }, 15858 }, 15859 }, 15860 { 15861 name: "SLWconst", 15862 auxType: auxInt64, 15863 argLen: 1, 15864 asm: ppc64.ASLW, 15865 reg: regInfo{ 15866 inputs: []inputInfo{ 15867 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15868 }, 15869 outputs: []outputInfo{ 15870 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15871 }, 15872 }, 15873 }, 15874 { 15875 name: "FDIV", 15876 argLen: 2, 15877 asm: ppc64.AFDIV, 15878 reg: regInfo{ 15879 inputs: []inputInfo{ 15880 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15881 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15882 }, 15883 outputs: []outputInfo{ 15884 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15885 }, 15886 }, 15887 }, 15888 { 15889 name: "FDIVS", 15890 argLen: 2, 15891 asm: ppc64.AFDIVS, 15892 reg: regInfo{ 15893 inputs: []inputInfo{ 15894 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15895 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15896 }, 15897 outputs: []outputInfo{ 15898 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15899 }, 15900 }, 15901 }, 15902 { 15903 name: "DIVD", 15904 argLen: 2, 15905 asm: ppc64.ADIVD, 15906 reg: regInfo{ 15907 inputs: []inputInfo{ 15908 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15909 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15910 }, 15911 outputs: []outputInfo{ 15912 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15913 }, 15914 }, 15915 }, 15916 { 15917 name: "DIVW", 15918 argLen: 2, 15919 asm: ppc64.ADIVW, 15920 reg: regInfo{ 15921 inputs: []inputInfo{ 15922 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15923 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15924 }, 15925 outputs: []outputInfo{ 15926 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15927 }, 15928 }, 15929 }, 15930 { 15931 name: "DIVDU", 15932 argLen: 2, 15933 asm: ppc64.ADIVDU, 15934 reg: regInfo{ 15935 inputs: []inputInfo{ 15936 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15937 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15938 }, 15939 outputs: []outputInfo{ 15940 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15941 }, 15942 }, 15943 }, 15944 { 15945 name: "DIVWU", 15946 argLen: 2, 15947 asm: ppc64.ADIVWU, 15948 reg: regInfo{ 15949 inputs: []inputInfo{ 15950 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15951 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15952 }, 15953 outputs: []outputInfo{ 15954 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15955 }, 15956 }, 15957 }, 15958 { 15959 name: "FCTIDZ", 15960 argLen: 1, 15961 asm: ppc64.AFCTIDZ, 15962 reg: regInfo{ 15963 inputs: []inputInfo{ 15964 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15965 }, 15966 outputs: []outputInfo{ 15967 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15968 }, 15969 }, 15970 }, 15971 { 15972 name: "FCTIWZ", 15973 argLen: 1, 15974 asm: ppc64.AFCTIWZ, 15975 reg: regInfo{ 15976 inputs: []inputInfo{ 15977 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15978 }, 15979 outputs: []outputInfo{ 15980 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15981 }, 15982 }, 15983 }, 15984 { 15985 name: "FCFID", 15986 argLen: 1, 15987 asm: ppc64.AFCFID, 15988 reg: regInfo{ 15989 inputs: []inputInfo{ 15990 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15991 }, 15992 outputs: []outputInfo{ 15993 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15994 }, 15995 }, 15996 }, 15997 { 15998 name: "FRSP", 15999 argLen: 1, 16000 asm: ppc64.AFRSP, 16001 reg: regInfo{ 16002 inputs: []inputInfo{ 16003 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16004 }, 16005 outputs: []outputInfo{ 16006 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16007 }, 16008 }, 16009 }, 16010 { 16011 name: "Xf2i64", 16012 argLen: 1, 16013 usesScratch: true, 16014 reg: regInfo{ 16015 inputs: []inputInfo{ 16016 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16017 }, 16018 outputs: []outputInfo{ 16019 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16020 }, 16021 }, 16022 }, 16023 { 16024 name: "Xi2f64", 16025 argLen: 1, 16026 usesScratch: true, 16027 reg: regInfo{ 16028 inputs: []inputInfo{ 16029 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16030 }, 16031 outputs: []outputInfo{ 16032 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16033 }, 16034 }, 16035 }, 16036 { 16037 name: "AND", 16038 argLen: 2, 16039 commutative: true, 16040 asm: ppc64.AAND, 16041 reg: regInfo{ 16042 inputs: []inputInfo{ 16043 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16044 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16045 }, 16046 outputs: []outputInfo{ 16047 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16048 }, 16049 }, 16050 }, 16051 { 16052 name: "ANDN", 16053 argLen: 2, 16054 asm: ppc64.AANDN, 16055 reg: regInfo{ 16056 inputs: []inputInfo{ 16057 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16058 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16059 }, 16060 outputs: []outputInfo{ 16061 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16062 }, 16063 }, 16064 }, 16065 { 16066 name: "OR", 16067 argLen: 2, 16068 commutative: true, 16069 asm: ppc64.AOR, 16070 reg: regInfo{ 16071 inputs: []inputInfo{ 16072 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16073 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16074 }, 16075 outputs: []outputInfo{ 16076 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16077 }, 16078 }, 16079 }, 16080 { 16081 name: "ORN", 16082 argLen: 2, 16083 asm: ppc64.AORN, 16084 reg: regInfo{ 16085 inputs: []inputInfo{ 16086 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16087 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16088 }, 16089 outputs: []outputInfo{ 16090 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16091 }, 16092 }, 16093 }, 16094 { 16095 name: "NOR", 16096 argLen: 2, 16097 asm: ppc64.ANOR, 16098 reg: regInfo{ 16099 inputs: []inputInfo{ 16100 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16101 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16102 }, 16103 outputs: []outputInfo{ 16104 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16105 }, 16106 }, 16107 }, 16108 { 16109 name: "XOR", 16110 argLen: 2, 16111 commutative: true, 16112 asm: ppc64.AXOR, 16113 reg: regInfo{ 16114 inputs: []inputInfo{ 16115 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16116 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16117 }, 16118 outputs: []outputInfo{ 16119 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16120 }, 16121 }, 16122 }, 16123 { 16124 name: "EQV", 16125 argLen: 2, 16126 commutative: true, 16127 asm: ppc64.AEQV, 16128 reg: regInfo{ 16129 inputs: []inputInfo{ 16130 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16131 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16132 }, 16133 outputs: []outputInfo{ 16134 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16135 }, 16136 }, 16137 }, 16138 { 16139 name: "NEG", 16140 argLen: 1, 16141 asm: ppc64.ANEG, 16142 reg: regInfo{ 16143 inputs: []inputInfo{ 16144 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16145 }, 16146 outputs: []outputInfo{ 16147 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16148 }, 16149 }, 16150 }, 16151 { 16152 name: "FNEG", 16153 argLen: 1, 16154 asm: ppc64.AFNEG, 16155 reg: regInfo{ 16156 inputs: []inputInfo{ 16157 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16158 }, 16159 outputs: []outputInfo{ 16160 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16161 }, 16162 }, 16163 }, 16164 { 16165 name: "FSQRT", 16166 argLen: 1, 16167 asm: ppc64.AFSQRT, 16168 reg: regInfo{ 16169 inputs: []inputInfo{ 16170 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16171 }, 16172 outputs: []outputInfo{ 16173 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16174 }, 16175 }, 16176 }, 16177 { 16178 name: "FSQRTS", 16179 argLen: 1, 16180 asm: ppc64.AFSQRTS, 16181 reg: regInfo{ 16182 inputs: []inputInfo{ 16183 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16184 }, 16185 outputs: []outputInfo{ 16186 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16187 }, 16188 }, 16189 }, 16190 { 16191 name: "ORconst", 16192 auxType: auxInt64, 16193 argLen: 1, 16194 asm: ppc64.AOR, 16195 reg: regInfo{ 16196 inputs: []inputInfo{ 16197 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16198 }, 16199 outputs: []outputInfo{ 16200 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16201 }, 16202 }, 16203 }, 16204 { 16205 name: "XORconst", 16206 auxType: auxInt64, 16207 argLen: 1, 16208 asm: ppc64.AXOR, 16209 reg: regInfo{ 16210 inputs: []inputInfo{ 16211 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16212 }, 16213 outputs: []outputInfo{ 16214 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16215 }, 16216 }, 16217 }, 16218 { 16219 name: "ANDconst", 16220 auxType: auxInt64, 16221 argLen: 1, 16222 clobberFlags: true, 16223 asm: ppc64.AANDCC, 16224 reg: regInfo{ 16225 inputs: []inputInfo{ 16226 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16227 }, 16228 outputs: []outputInfo{ 16229 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16230 }, 16231 }, 16232 }, 16233 { 16234 name: "ANDCCconst", 16235 auxType: auxInt64, 16236 argLen: 1, 16237 asm: ppc64.AANDCC, 16238 reg: regInfo{ 16239 inputs: []inputInfo{ 16240 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16241 }, 16242 }, 16243 }, 16244 { 16245 name: "MOVBreg", 16246 argLen: 1, 16247 asm: ppc64.AMOVB, 16248 reg: regInfo{ 16249 inputs: []inputInfo{ 16250 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16251 }, 16252 outputs: []outputInfo{ 16253 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16254 }, 16255 }, 16256 }, 16257 { 16258 name: "MOVBZreg", 16259 argLen: 1, 16260 asm: ppc64.AMOVBZ, 16261 reg: regInfo{ 16262 inputs: []inputInfo{ 16263 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16264 }, 16265 outputs: []outputInfo{ 16266 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16267 }, 16268 }, 16269 }, 16270 { 16271 name: "MOVHreg", 16272 argLen: 1, 16273 asm: ppc64.AMOVH, 16274 reg: regInfo{ 16275 inputs: []inputInfo{ 16276 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16277 }, 16278 outputs: []outputInfo{ 16279 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16280 }, 16281 }, 16282 }, 16283 { 16284 name: "MOVHZreg", 16285 argLen: 1, 16286 asm: ppc64.AMOVHZ, 16287 reg: regInfo{ 16288 inputs: []inputInfo{ 16289 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16290 }, 16291 outputs: []outputInfo{ 16292 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16293 }, 16294 }, 16295 }, 16296 { 16297 name: "MOVWreg", 16298 argLen: 1, 16299 asm: ppc64.AMOVW, 16300 reg: regInfo{ 16301 inputs: []inputInfo{ 16302 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16303 }, 16304 outputs: []outputInfo{ 16305 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16306 }, 16307 }, 16308 }, 16309 { 16310 name: "MOVWZreg", 16311 argLen: 1, 16312 asm: ppc64.AMOVWZ, 16313 reg: regInfo{ 16314 inputs: []inputInfo{ 16315 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16316 }, 16317 outputs: []outputInfo{ 16318 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16319 }, 16320 }, 16321 }, 16322 { 16323 name: "MOVBZload", 16324 auxType: auxSymOff, 16325 argLen: 2, 16326 faultOnNilArg0: true, 16327 asm: ppc64.AMOVBZ, 16328 reg: regInfo{ 16329 inputs: []inputInfo{ 16330 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16331 }, 16332 outputs: []outputInfo{ 16333 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16334 }, 16335 }, 16336 }, 16337 { 16338 name: "MOVHload", 16339 auxType: auxSymOff, 16340 argLen: 2, 16341 faultOnNilArg0: true, 16342 asm: ppc64.AMOVH, 16343 reg: regInfo{ 16344 inputs: []inputInfo{ 16345 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16346 }, 16347 outputs: []outputInfo{ 16348 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16349 }, 16350 }, 16351 }, 16352 { 16353 name: "MOVHZload", 16354 auxType: auxSymOff, 16355 argLen: 2, 16356 faultOnNilArg0: true, 16357 asm: ppc64.AMOVHZ, 16358 reg: regInfo{ 16359 inputs: []inputInfo{ 16360 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16361 }, 16362 outputs: []outputInfo{ 16363 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16364 }, 16365 }, 16366 }, 16367 { 16368 name: "MOVWload", 16369 auxType: auxSymOff, 16370 argLen: 2, 16371 faultOnNilArg0: true, 16372 asm: ppc64.AMOVW, 16373 reg: regInfo{ 16374 inputs: []inputInfo{ 16375 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16376 }, 16377 outputs: []outputInfo{ 16378 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16379 }, 16380 }, 16381 }, 16382 { 16383 name: "MOVWZload", 16384 auxType: auxSymOff, 16385 argLen: 2, 16386 faultOnNilArg0: true, 16387 asm: ppc64.AMOVWZ, 16388 reg: regInfo{ 16389 inputs: []inputInfo{ 16390 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16391 }, 16392 outputs: []outputInfo{ 16393 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16394 }, 16395 }, 16396 }, 16397 { 16398 name: "MOVDload", 16399 auxType: auxSymOff, 16400 argLen: 2, 16401 faultOnNilArg0: true, 16402 asm: ppc64.AMOVD, 16403 reg: regInfo{ 16404 inputs: []inputInfo{ 16405 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16406 }, 16407 outputs: []outputInfo{ 16408 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16409 }, 16410 }, 16411 }, 16412 { 16413 name: "FMOVDload", 16414 auxType: auxSymOff, 16415 argLen: 2, 16416 faultOnNilArg0: true, 16417 asm: ppc64.AFMOVD, 16418 reg: regInfo{ 16419 inputs: []inputInfo{ 16420 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16421 }, 16422 outputs: []outputInfo{ 16423 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16424 }, 16425 }, 16426 }, 16427 { 16428 name: "FMOVSload", 16429 auxType: auxSymOff, 16430 argLen: 2, 16431 faultOnNilArg0: true, 16432 asm: ppc64.AFMOVS, 16433 reg: regInfo{ 16434 inputs: []inputInfo{ 16435 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16436 }, 16437 outputs: []outputInfo{ 16438 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16439 }, 16440 }, 16441 }, 16442 { 16443 name: "MOVBstore", 16444 auxType: auxSymOff, 16445 argLen: 3, 16446 faultOnNilArg0: true, 16447 asm: ppc64.AMOVB, 16448 reg: regInfo{ 16449 inputs: []inputInfo{ 16450 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16451 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16452 }, 16453 }, 16454 }, 16455 { 16456 name: "MOVHstore", 16457 auxType: auxSymOff, 16458 argLen: 3, 16459 faultOnNilArg0: true, 16460 asm: ppc64.AMOVH, 16461 reg: regInfo{ 16462 inputs: []inputInfo{ 16463 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16464 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16465 }, 16466 }, 16467 }, 16468 { 16469 name: "MOVWstore", 16470 auxType: auxSymOff, 16471 argLen: 3, 16472 faultOnNilArg0: true, 16473 asm: ppc64.AMOVW, 16474 reg: regInfo{ 16475 inputs: []inputInfo{ 16476 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16477 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16478 }, 16479 }, 16480 }, 16481 { 16482 name: "MOVDstore", 16483 auxType: auxSymOff, 16484 argLen: 3, 16485 faultOnNilArg0: true, 16486 asm: ppc64.AMOVD, 16487 reg: regInfo{ 16488 inputs: []inputInfo{ 16489 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16490 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16491 }, 16492 }, 16493 }, 16494 { 16495 name: "FMOVDstore", 16496 auxType: auxSymOff, 16497 argLen: 3, 16498 faultOnNilArg0: true, 16499 asm: ppc64.AFMOVD, 16500 reg: regInfo{ 16501 inputs: []inputInfo{ 16502 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16503 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16504 }, 16505 }, 16506 }, 16507 { 16508 name: "FMOVSstore", 16509 auxType: auxSymOff, 16510 argLen: 3, 16511 faultOnNilArg0: true, 16512 asm: ppc64.AFMOVS, 16513 reg: regInfo{ 16514 inputs: []inputInfo{ 16515 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16516 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16517 }, 16518 }, 16519 }, 16520 { 16521 name: "MOVBstorezero", 16522 auxType: auxSymOff, 16523 argLen: 2, 16524 faultOnNilArg0: true, 16525 asm: ppc64.AMOVB, 16526 reg: regInfo{ 16527 inputs: []inputInfo{ 16528 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16529 }, 16530 }, 16531 }, 16532 { 16533 name: "MOVHstorezero", 16534 auxType: auxSymOff, 16535 argLen: 2, 16536 faultOnNilArg0: true, 16537 asm: ppc64.AMOVH, 16538 reg: regInfo{ 16539 inputs: []inputInfo{ 16540 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16541 }, 16542 }, 16543 }, 16544 { 16545 name: "MOVWstorezero", 16546 auxType: auxSymOff, 16547 argLen: 2, 16548 faultOnNilArg0: true, 16549 asm: ppc64.AMOVW, 16550 reg: regInfo{ 16551 inputs: []inputInfo{ 16552 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16553 }, 16554 }, 16555 }, 16556 { 16557 name: "MOVDstorezero", 16558 auxType: auxSymOff, 16559 argLen: 2, 16560 faultOnNilArg0: true, 16561 asm: ppc64.AMOVD, 16562 reg: regInfo{ 16563 inputs: []inputInfo{ 16564 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16565 }, 16566 }, 16567 }, 16568 { 16569 name: "MOVDaddr", 16570 auxType: auxSymOff, 16571 argLen: 1, 16572 rematerializeable: true, 16573 asm: ppc64.AMOVD, 16574 reg: regInfo{ 16575 inputs: []inputInfo{ 16576 {0, 6}, // SP SB 16577 }, 16578 outputs: []outputInfo{ 16579 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16580 }, 16581 }, 16582 }, 16583 { 16584 name: "MOVDconst", 16585 auxType: auxInt64, 16586 argLen: 0, 16587 rematerializeable: true, 16588 asm: ppc64.AMOVD, 16589 reg: regInfo{ 16590 outputs: []outputInfo{ 16591 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16592 }, 16593 }, 16594 }, 16595 { 16596 name: "FMOVDconst", 16597 auxType: auxFloat64, 16598 argLen: 0, 16599 rematerializeable: true, 16600 asm: ppc64.AFMOVD, 16601 reg: regInfo{ 16602 outputs: []outputInfo{ 16603 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16604 }, 16605 }, 16606 }, 16607 { 16608 name: "FMOVSconst", 16609 auxType: auxFloat32, 16610 argLen: 0, 16611 rematerializeable: true, 16612 asm: ppc64.AFMOVS, 16613 reg: regInfo{ 16614 outputs: []outputInfo{ 16615 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16616 }, 16617 }, 16618 }, 16619 { 16620 name: "FCMPU", 16621 argLen: 2, 16622 asm: ppc64.AFCMPU, 16623 reg: regInfo{ 16624 inputs: []inputInfo{ 16625 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16626 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16627 }, 16628 }, 16629 }, 16630 { 16631 name: "CMP", 16632 argLen: 2, 16633 asm: ppc64.ACMP, 16634 reg: regInfo{ 16635 inputs: []inputInfo{ 16636 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16637 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16638 }, 16639 }, 16640 }, 16641 { 16642 name: "CMPU", 16643 argLen: 2, 16644 asm: ppc64.ACMPU, 16645 reg: regInfo{ 16646 inputs: []inputInfo{ 16647 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16648 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16649 }, 16650 }, 16651 }, 16652 { 16653 name: "CMPW", 16654 argLen: 2, 16655 asm: ppc64.ACMPW, 16656 reg: regInfo{ 16657 inputs: []inputInfo{ 16658 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16659 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16660 }, 16661 }, 16662 }, 16663 { 16664 name: "CMPWU", 16665 argLen: 2, 16666 asm: ppc64.ACMPWU, 16667 reg: regInfo{ 16668 inputs: []inputInfo{ 16669 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16670 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16671 }, 16672 }, 16673 }, 16674 { 16675 name: "CMPconst", 16676 auxType: auxInt64, 16677 argLen: 1, 16678 asm: ppc64.ACMP, 16679 reg: regInfo{ 16680 inputs: []inputInfo{ 16681 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16682 }, 16683 }, 16684 }, 16685 { 16686 name: "CMPUconst", 16687 auxType: auxInt64, 16688 argLen: 1, 16689 asm: ppc64.ACMPU, 16690 reg: regInfo{ 16691 inputs: []inputInfo{ 16692 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16693 }, 16694 }, 16695 }, 16696 { 16697 name: "CMPWconst", 16698 auxType: auxInt32, 16699 argLen: 1, 16700 asm: ppc64.ACMPW, 16701 reg: regInfo{ 16702 inputs: []inputInfo{ 16703 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16704 }, 16705 }, 16706 }, 16707 { 16708 name: "CMPWUconst", 16709 auxType: auxInt32, 16710 argLen: 1, 16711 asm: ppc64.ACMPWU, 16712 reg: regInfo{ 16713 inputs: []inputInfo{ 16714 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16715 }, 16716 }, 16717 }, 16718 { 16719 name: "Equal", 16720 argLen: 1, 16721 reg: regInfo{ 16722 outputs: []outputInfo{ 16723 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16724 }, 16725 }, 16726 }, 16727 { 16728 name: "NotEqual", 16729 argLen: 1, 16730 reg: regInfo{ 16731 outputs: []outputInfo{ 16732 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16733 }, 16734 }, 16735 }, 16736 { 16737 name: "LessThan", 16738 argLen: 1, 16739 reg: regInfo{ 16740 outputs: []outputInfo{ 16741 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16742 }, 16743 }, 16744 }, 16745 { 16746 name: "FLessThan", 16747 argLen: 1, 16748 reg: regInfo{ 16749 outputs: []outputInfo{ 16750 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16751 }, 16752 }, 16753 }, 16754 { 16755 name: "LessEqual", 16756 argLen: 1, 16757 reg: regInfo{ 16758 outputs: []outputInfo{ 16759 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16760 }, 16761 }, 16762 }, 16763 { 16764 name: "FLessEqual", 16765 argLen: 1, 16766 reg: regInfo{ 16767 outputs: []outputInfo{ 16768 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16769 }, 16770 }, 16771 }, 16772 { 16773 name: "GreaterThan", 16774 argLen: 1, 16775 reg: regInfo{ 16776 outputs: []outputInfo{ 16777 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16778 }, 16779 }, 16780 }, 16781 { 16782 name: "FGreaterThan", 16783 argLen: 1, 16784 reg: regInfo{ 16785 outputs: []outputInfo{ 16786 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16787 }, 16788 }, 16789 }, 16790 { 16791 name: "GreaterEqual", 16792 argLen: 1, 16793 reg: regInfo{ 16794 outputs: []outputInfo{ 16795 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16796 }, 16797 }, 16798 }, 16799 { 16800 name: "FGreaterEqual", 16801 argLen: 1, 16802 reg: regInfo{ 16803 outputs: []outputInfo{ 16804 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16805 }, 16806 }, 16807 }, 16808 { 16809 name: "LoweredGetClosurePtr", 16810 argLen: 0, 16811 reg: regInfo{ 16812 outputs: []outputInfo{ 16813 {0, 2048}, // R11 16814 }, 16815 }, 16816 }, 16817 { 16818 name: "LoweredNilCheck", 16819 argLen: 2, 16820 clobberFlags: true, 16821 nilCheck: true, 16822 faultOnNilArg0: true, 16823 reg: regInfo{ 16824 inputs: []inputInfo{ 16825 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16826 }, 16827 clobbers: 2147483648, // R31 16828 }, 16829 }, 16830 { 16831 name: "MOVDconvert", 16832 argLen: 2, 16833 asm: ppc64.AMOVD, 16834 reg: regInfo{ 16835 inputs: []inputInfo{ 16836 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16837 }, 16838 outputs: []outputInfo{ 16839 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16840 }, 16841 }, 16842 }, 16843 { 16844 name: "CALLstatic", 16845 auxType: auxSymOff, 16846 argLen: 1, 16847 clobberFlags: true, 16848 call: true, 16849 reg: regInfo{ 16850 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16851 }, 16852 }, 16853 { 16854 name: "CALLclosure", 16855 auxType: auxInt64, 16856 argLen: 3, 16857 clobberFlags: true, 16858 call: true, 16859 reg: regInfo{ 16860 inputs: []inputInfo{ 16861 {1, 2048}, // R11 16862 {0, 1073733626}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16863 }, 16864 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16865 }, 16866 }, 16867 { 16868 name: "CALLdefer", 16869 auxType: auxInt64, 16870 argLen: 1, 16871 clobberFlags: true, 16872 call: true, 16873 reg: regInfo{ 16874 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16875 }, 16876 }, 16877 { 16878 name: "CALLgo", 16879 auxType: auxInt64, 16880 argLen: 1, 16881 clobberFlags: true, 16882 call: true, 16883 reg: regInfo{ 16884 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16885 }, 16886 }, 16887 { 16888 name: "CALLinter", 16889 auxType: auxInt64, 16890 argLen: 2, 16891 clobberFlags: true, 16892 call: true, 16893 reg: regInfo{ 16894 inputs: []inputInfo{ 16895 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16896 }, 16897 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16898 }, 16899 }, 16900 { 16901 name: "LoweredZero", 16902 auxType: auxInt64, 16903 argLen: 3, 16904 clobberFlags: true, 16905 faultOnNilArg0: true, 16906 reg: regInfo{ 16907 inputs: []inputInfo{ 16908 {0, 8}, // R3 16909 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16910 }, 16911 clobbers: 8, // R3 16912 }, 16913 }, 16914 { 16915 name: "LoweredMove", 16916 auxType: auxInt64, 16917 argLen: 4, 16918 clobberFlags: true, 16919 faultOnNilArg0: true, 16920 faultOnNilArg1: true, 16921 reg: regInfo{ 16922 inputs: []inputInfo{ 16923 {0, 8}, // R3 16924 {1, 16}, // R4 16925 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16926 }, 16927 clobbers: 24, // R3 R4 16928 }, 16929 }, 16930 { 16931 name: "InvertFlags", 16932 argLen: 1, 16933 reg: regInfo{}, 16934 }, 16935 { 16936 name: "FlagEQ", 16937 argLen: 0, 16938 reg: regInfo{}, 16939 }, 16940 { 16941 name: "FlagLT", 16942 argLen: 0, 16943 reg: regInfo{}, 16944 }, 16945 { 16946 name: "FlagGT", 16947 argLen: 0, 16948 reg: regInfo{}, 16949 }, 16950 16951 { 16952 name: "FADDS", 16953 argLen: 2, 16954 commutative: true, 16955 resultInArg0: true, 16956 clobberFlags: true, 16957 asm: s390x.AFADDS, 16958 reg: regInfo{ 16959 inputs: []inputInfo{ 16960 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16961 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16962 }, 16963 outputs: []outputInfo{ 16964 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16965 }, 16966 }, 16967 }, 16968 { 16969 name: "FADD", 16970 argLen: 2, 16971 commutative: true, 16972 resultInArg0: true, 16973 clobberFlags: true, 16974 asm: s390x.AFADD, 16975 reg: regInfo{ 16976 inputs: []inputInfo{ 16977 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16978 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16979 }, 16980 outputs: []outputInfo{ 16981 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16982 }, 16983 }, 16984 }, 16985 { 16986 name: "FSUBS", 16987 argLen: 2, 16988 resultInArg0: true, 16989 clobberFlags: true, 16990 asm: s390x.AFSUBS, 16991 reg: regInfo{ 16992 inputs: []inputInfo{ 16993 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16994 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16995 }, 16996 outputs: []outputInfo{ 16997 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16998 }, 16999 }, 17000 }, 17001 { 17002 name: "FSUB", 17003 argLen: 2, 17004 resultInArg0: true, 17005 clobberFlags: true, 17006 asm: s390x.AFSUB, 17007 reg: regInfo{ 17008 inputs: []inputInfo{ 17009 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17010 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17011 }, 17012 outputs: []outputInfo{ 17013 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17014 }, 17015 }, 17016 }, 17017 { 17018 name: "FMULS", 17019 argLen: 2, 17020 commutative: true, 17021 resultInArg0: true, 17022 asm: s390x.AFMULS, 17023 reg: regInfo{ 17024 inputs: []inputInfo{ 17025 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17026 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17027 }, 17028 outputs: []outputInfo{ 17029 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17030 }, 17031 }, 17032 }, 17033 { 17034 name: "FMUL", 17035 argLen: 2, 17036 commutative: true, 17037 resultInArg0: true, 17038 asm: s390x.AFMUL, 17039 reg: regInfo{ 17040 inputs: []inputInfo{ 17041 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17042 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17043 }, 17044 outputs: []outputInfo{ 17045 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17046 }, 17047 }, 17048 }, 17049 { 17050 name: "FDIVS", 17051 argLen: 2, 17052 resultInArg0: true, 17053 asm: s390x.AFDIVS, 17054 reg: regInfo{ 17055 inputs: []inputInfo{ 17056 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17057 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17058 }, 17059 outputs: []outputInfo{ 17060 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17061 }, 17062 }, 17063 }, 17064 { 17065 name: "FDIV", 17066 argLen: 2, 17067 resultInArg0: true, 17068 asm: s390x.AFDIV, 17069 reg: regInfo{ 17070 inputs: []inputInfo{ 17071 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17072 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17073 }, 17074 outputs: []outputInfo{ 17075 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17076 }, 17077 }, 17078 }, 17079 { 17080 name: "FNEGS", 17081 argLen: 1, 17082 clobberFlags: true, 17083 asm: s390x.AFNEGS, 17084 reg: regInfo{ 17085 inputs: []inputInfo{ 17086 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17087 }, 17088 outputs: []outputInfo{ 17089 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17090 }, 17091 }, 17092 }, 17093 { 17094 name: "FNEG", 17095 argLen: 1, 17096 clobberFlags: true, 17097 asm: s390x.AFNEG, 17098 reg: regInfo{ 17099 inputs: []inputInfo{ 17100 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17101 }, 17102 outputs: []outputInfo{ 17103 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17104 }, 17105 }, 17106 }, 17107 { 17108 name: "FMOVSload", 17109 auxType: auxSymOff, 17110 argLen: 2, 17111 faultOnNilArg0: true, 17112 asm: s390x.AFMOVS, 17113 reg: regInfo{ 17114 inputs: []inputInfo{ 17115 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17116 }, 17117 outputs: []outputInfo{ 17118 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17119 }, 17120 }, 17121 }, 17122 { 17123 name: "FMOVDload", 17124 auxType: auxSymOff, 17125 argLen: 2, 17126 faultOnNilArg0: true, 17127 asm: s390x.AFMOVD, 17128 reg: regInfo{ 17129 inputs: []inputInfo{ 17130 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17131 }, 17132 outputs: []outputInfo{ 17133 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17134 }, 17135 }, 17136 }, 17137 { 17138 name: "FMOVSconst", 17139 auxType: auxFloat32, 17140 argLen: 0, 17141 rematerializeable: true, 17142 asm: s390x.AFMOVS, 17143 reg: regInfo{ 17144 outputs: []outputInfo{ 17145 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17146 }, 17147 }, 17148 }, 17149 { 17150 name: "FMOVDconst", 17151 auxType: auxFloat64, 17152 argLen: 0, 17153 rematerializeable: true, 17154 asm: s390x.AFMOVD, 17155 reg: regInfo{ 17156 outputs: []outputInfo{ 17157 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17158 }, 17159 }, 17160 }, 17161 { 17162 name: "FMOVSloadidx", 17163 auxType: auxSymOff, 17164 argLen: 3, 17165 asm: s390x.AFMOVS, 17166 reg: regInfo{ 17167 inputs: []inputInfo{ 17168 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17169 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17170 }, 17171 outputs: []outputInfo{ 17172 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17173 }, 17174 }, 17175 }, 17176 { 17177 name: "FMOVDloadidx", 17178 auxType: auxSymOff, 17179 argLen: 3, 17180 asm: s390x.AFMOVD, 17181 reg: regInfo{ 17182 inputs: []inputInfo{ 17183 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17184 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17185 }, 17186 outputs: []outputInfo{ 17187 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17188 }, 17189 }, 17190 }, 17191 { 17192 name: "FMOVSstore", 17193 auxType: auxSymOff, 17194 argLen: 3, 17195 faultOnNilArg0: true, 17196 asm: s390x.AFMOVS, 17197 reg: regInfo{ 17198 inputs: []inputInfo{ 17199 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17200 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17201 }, 17202 }, 17203 }, 17204 { 17205 name: "FMOVDstore", 17206 auxType: auxSymOff, 17207 argLen: 3, 17208 faultOnNilArg0: true, 17209 asm: s390x.AFMOVD, 17210 reg: regInfo{ 17211 inputs: []inputInfo{ 17212 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17213 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17214 }, 17215 }, 17216 }, 17217 { 17218 name: "FMOVSstoreidx", 17219 auxType: auxSymOff, 17220 argLen: 4, 17221 asm: s390x.AFMOVS, 17222 reg: regInfo{ 17223 inputs: []inputInfo{ 17224 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17225 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17226 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17227 }, 17228 }, 17229 }, 17230 { 17231 name: "FMOVDstoreidx", 17232 auxType: auxSymOff, 17233 argLen: 4, 17234 asm: s390x.AFMOVD, 17235 reg: regInfo{ 17236 inputs: []inputInfo{ 17237 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17238 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17239 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17240 }, 17241 }, 17242 }, 17243 { 17244 name: "ADD", 17245 argLen: 2, 17246 commutative: true, 17247 clobberFlags: true, 17248 asm: s390x.AADD, 17249 reg: regInfo{ 17250 inputs: []inputInfo{ 17251 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17252 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17253 }, 17254 outputs: []outputInfo{ 17255 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17256 }, 17257 }, 17258 }, 17259 { 17260 name: "ADDW", 17261 argLen: 2, 17262 commutative: true, 17263 clobberFlags: true, 17264 asm: s390x.AADDW, 17265 reg: regInfo{ 17266 inputs: []inputInfo{ 17267 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17268 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17269 }, 17270 outputs: []outputInfo{ 17271 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17272 }, 17273 }, 17274 }, 17275 { 17276 name: "ADDconst", 17277 auxType: auxInt64, 17278 argLen: 1, 17279 clobberFlags: true, 17280 asm: s390x.AADD, 17281 reg: regInfo{ 17282 inputs: []inputInfo{ 17283 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17284 }, 17285 outputs: []outputInfo{ 17286 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17287 }, 17288 }, 17289 }, 17290 { 17291 name: "ADDWconst", 17292 auxType: auxInt32, 17293 argLen: 1, 17294 clobberFlags: true, 17295 asm: s390x.AADDW, 17296 reg: regInfo{ 17297 inputs: []inputInfo{ 17298 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17299 }, 17300 outputs: []outputInfo{ 17301 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17302 }, 17303 }, 17304 }, 17305 { 17306 name: "ADDload", 17307 auxType: auxSymOff, 17308 argLen: 3, 17309 resultInArg0: true, 17310 clobberFlags: true, 17311 faultOnNilArg1: true, 17312 asm: s390x.AADD, 17313 reg: regInfo{ 17314 inputs: []inputInfo{ 17315 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17316 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17317 }, 17318 outputs: []outputInfo{ 17319 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17320 }, 17321 }, 17322 }, 17323 { 17324 name: "ADDWload", 17325 auxType: auxSymOff, 17326 argLen: 3, 17327 resultInArg0: true, 17328 clobberFlags: true, 17329 faultOnNilArg1: true, 17330 asm: s390x.AADDW, 17331 reg: regInfo{ 17332 inputs: []inputInfo{ 17333 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17334 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17335 }, 17336 outputs: []outputInfo{ 17337 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17338 }, 17339 }, 17340 }, 17341 { 17342 name: "SUB", 17343 argLen: 2, 17344 clobberFlags: true, 17345 asm: s390x.ASUB, 17346 reg: regInfo{ 17347 inputs: []inputInfo{ 17348 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17349 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17350 }, 17351 outputs: []outputInfo{ 17352 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17353 }, 17354 }, 17355 }, 17356 { 17357 name: "SUBW", 17358 argLen: 2, 17359 clobberFlags: true, 17360 asm: s390x.ASUBW, 17361 reg: regInfo{ 17362 inputs: []inputInfo{ 17363 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17364 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17365 }, 17366 outputs: []outputInfo{ 17367 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17368 }, 17369 }, 17370 }, 17371 { 17372 name: "SUBconst", 17373 auxType: auxInt64, 17374 argLen: 1, 17375 resultInArg0: true, 17376 clobberFlags: true, 17377 asm: s390x.ASUB, 17378 reg: regInfo{ 17379 inputs: []inputInfo{ 17380 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17381 }, 17382 outputs: []outputInfo{ 17383 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17384 }, 17385 }, 17386 }, 17387 { 17388 name: "SUBWconst", 17389 auxType: auxInt32, 17390 argLen: 1, 17391 resultInArg0: true, 17392 clobberFlags: true, 17393 asm: s390x.ASUBW, 17394 reg: regInfo{ 17395 inputs: []inputInfo{ 17396 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17397 }, 17398 outputs: []outputInfo{ 17399 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17400 }, 17401 }, 17402 }, 17403 { 17404 name: "SUBload", 17405 auxType: auxSymOff, 17406 argLen: 3, 17407 resultInArg0: true, 17408 clobberFlags: true, 17409 faultOnNilArg1: true, 17410 asm: s390x.ASUB, 17411 reg: regInfo{ 17412 inputs: []inputInfo{ 17413 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17414 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17415 }, 17416 outputs: []outputInfo{ 17417 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17418 }, 17419 }, 17420 }, 17421 { 17422 name: "SUBWload", 17423 auxType: auxSymOff, 17424 argLen: 3, 17425 resultInArg0: true, 17426 clobberFlags: true, 17427 faultOnNilArg1: true, 17428 asm: s390x.ASUBW, 17429 reg: regInfo{ 17430 inputs: []inputInfo{ 17431 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17432 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17433 }, 17434 outputs: []outputInfo{ 17435 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17436 }, 17437 }, 17438 }, 17439 { 17440 name: "MULLD", 17441 argLen: 2, 17442 commutative: true, 17443 resultInArg0: true, 17444 clobberFlags: true, 17445 asm: s390x.AMULLD, 17446 reg: regInfo{ 17447 inputs: []inputInfo{ 17448 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17449 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17450 }, 17451 outputs: []outputInfo{ 17452 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17453 }, 17454 }, 17455 }, 17456 { 17457 name: "MULLW", 17458 argLen: 2, 17459 commutative: true, 17460 resultInArg0: true, 17461 clobberFlags: true, 17462 asm: s390x.AMULLW, 17463 reg: regInfo{ 17464 inputs: []inputInfo{ 17465 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17466 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17467 }, 17468 outputs: []outputInfo{ 17469 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17470 }, 17471 }, 17472 }, 17473 { 17474 name: "MULLDconst", 17475 auxType: auxInt64, 17476 argLen: 1, 17477 resultInArg0: true, 17478 clobberFlags: true, 17479 asm: s390x.AMULLD, 17480 reg: regInfo{ 17481 inputs: []inputInfo{ 17482 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17483 }, 17484 outputs: []outputInfo{ 17485 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17486 }, 17487 }, 17488 }, 17489 { 17490 name: "MULLWconst", 17491 auxType: auxInt32, 17492 argLen: 1, 17493 resultInArg0: true, 17494 clobberFlags: true, 17495 asm: s390x.AMULLW, 17496 reg: regInfo{ 17497 inputs: []inputInfo{ 17498 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17499 }, 17500 outputs: []outputInfo{ 17501 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17502 }, 17503 }, 17504 }, 17505 { 17506 name: "MULLDload", 17507 auxType: auxSymOff, 17508 argLen: 3, 17509 resultInArg0: true, 17510 clobberFlags: true, 17511 faultOnNilArg1: true, 17512 asm: s390x.AMULLD, 17513 reg: regInfo{ 17514 inputs: []inputInfo{ 17515 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17516 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17517 }, 17518 outputs: []outputInfo{ 17519 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17520 }, 17521 }, 17522 }, 17523 { 17524 name: "MULLWload", 17525 auxType: auxSymOff, 17526 argLen: 3, 17527 resultInArg0: true, 17528 clobberFlags: true, 17529 faultOnNilArg1: true, 17530 asm: s390x.AMULLW, 17531 reg: regInfo{ 17532 inputs: []inputInfo{ 17533 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17534 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17535 }, 17536 outputs: []outputInfo{ 17537 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17538 }, 17539 }, 17540 }, 17541 { 17542 name: "MULHD", 17543 argLen: 2, 17544 resultInArg0: true, 17545 clobberFlags: true, 17546 asm: s390x.AMULHD, 17547 reg: regInfo{ 17548 inputs: []inputInfo{ 17549 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17550 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17551 }, 17552 outputs: []outputInfo{ 17553 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17554 }, 17555 }, 17556 }, 17557 { 17558 name: "MULHDU", 17559 argLen: 2, 17560 resultInArg0: true, 17561 clobberFlags: true, 17562 asm: s390x.AMULHDU, 17563 reg: regInfo{ 17564 inputs: []inputInfo{ 17565 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17566 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17567 }, 17568 outputs: []outputInfo{ 17569 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17570 }, 17571 }, 17572 }, 17573 { 17574 name: "DIVD", 17575 argLen: 2, 17576 resultInArg0: true, 17577 clobberFlags: true, 17578 asm: s390x.ADIVD, 17579 reg: regInfo{ 17580 inputs: []inputInfo{ 17581 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17582 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17583 }, 17584 outputs: []outputInfo{ 17585 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17586 }, 17587 }, 17588 }, 17589 { 17590 name: "DIVW", 17591 argLen: 2, 17592 resultInArg0: true, 17593 clobberFlags: true, 17594 asm: s390x.ADIVW, 17595 reg: regInfo{ 17596 inputs: []inputInfo{ 17597 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17598 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17599 }, 17600 outputs: []outputInfo{ 17601 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17602 }, 17603 }, 17604 }, 17605 { 17606 name: "DIVDU", 17607 argLen: 2, 17608 resultInArg0: true, 17609 clobberFlags: true, 17610 asm: s390x.ADIVDU, 17611 reg: regInfo{ 17612 inputs: []inputInfo{ 17613 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17614 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17615 }, 17616 outputs: []outputInfo{ 17617 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17618 }, 17619 }, 17620 }, 17621 { 17622 name: "DIVWU", 17623 argLen: 2, 17624 resultInArg0: true, 17625 clobberFlags: true, 17626 asm: s390x.ADIVWU, 17627 reg: regInfo{ 17628 inputs: []inputInfo{ 17629 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17630 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17631 }, 17632 outputs: []outputInfo{ 17633 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17634 }, 17635 }, 17636 }, 17637 { 17638 name: "MODD", 17639 argLen: 2, 17640 resultInArg0: true, 17641 clobberFlags: true, 17642 asm: s390x.AMODD, 17643 reg: regInfo{ 17644 inputs: []inputInfo{ 17645 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17646 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17647 }, 17648 outputs: []outputInfo{ 17649 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17650 }, 17651 }, 17652 }, 17653 { 17654 name: "MODW", 17655 argLen: 2, 17656 resultInArg0: true, 17657 clobberFlags: true, 17658 asm: s390x.AMODW, 17659 reg: regInfo{ 17660 inputs: []inputInfo{ 17661 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17662 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17663 }, 17664 outputs: []outputInfo{ 17665 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17666 }, 17667 }, 17668 }, 17669 { 17670 name: "MODDU", 17671 argLen: 2, 17672 resultInArg0: true, 17673 clobberFlags: true, 17674 asm: s390x.AMODDU, 17675 reg: regInfo{ 17676 inputs: []inputInfo{ 17677 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17678 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17679 }, 17680 outputs: []outputInfo{ 17681 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17682 }, 17683 }, 17684 }, 17685 { 17686 name: "MODWU", 17687 argLen: 2, 17688 resultInArg0: true, 17689 clobberFlags: true, 17690 asm: s390x.AMODWU, 17691 reg: regInfo{ 17692 inputs: []inputInfo{ 17693 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17694 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17695 }, 17696 outputs: []outputInfo{ 17697 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17698 }, 17699 }, 17700 }, 17701 { 17702 name: "AND", 17703 argLen: 2, 17704 commutative: true, 17705 clobberFlags: true, 17706 asm: s390x.AAND, 17707 reg: regInfo{ 17708 inputs: []inputInfo{ 17709 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17710 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17711 }, 17712 outputs: []outputInfo{ 17713 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17714 }, 17715 }, 17716 }, 17717 { 17718 name: "ANDW", 17719 argLen: 2, 17720 commutative: true, 17721 clobberFlags: true, 17722 asm: s390x.AANDW, 17723 reg: regInfo{ 17724 inputs: []inputInfo{ 17725 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17726 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17727 }, 17728 outputs: []outputInfo{ 17729 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17730 }, 17731 }, 17732 }, 17733 { 17734 name: "ANDconst", 17735 auxType: auxInt64, 17736 argLen: 1, 17737 resultInArg0: true, 17738 clobberFlags: true, 17739 asm: s390x.AAND, 17740 reg: regInfo{ 17741 inputs: []inputInfo{ 17742 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17743 }, 17744 outputs: []outputInfo{ 17745 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17746 }, 17747 }, 17748 }, 17749 { 17750 name: "ANDWconst", 17751 auxType: auxInt32, 17752 argLen: 1, 17753 resultInArg0: true, 17754 clobberFlags: true, 17755 asm: s390x.AANDW, 17756 reg: regInfo{ 17757 inputs: []inputInfo{ 17758 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17759 }, 17760 outputs: []outputInfo{ 17761 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17762 }, 17763 }, 17764 }, 17765 { 17766 name: "ANDload", 17767 auxType: auxSymOff, 17768 argLen: 3, 17769 resultInArg0: true, 17770 clobberFlags: true, 17771 faultOnNilArg1: true, 17772 asm: s390x.AAND, 17773 reg: regInfo{ 17774 inputs: []inputInfo{ 17775 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17776 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17777 }, 17778 outputs: []outputInfo{ 17779 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17780 }, 17781 }, 17782 }, 17783 { 17784 name: "ANDWload", 17785 auxType: auxSymOff, 17786 argLen: 3, 17787 resultInArg0: true, 17788 clobberFlags: true, 17789 faultOnNilArg1: true, 17790 asm: s390x.AANDW, 17791 reg: regInfo{ 17792 inputs: []inputInfo{ 17793 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17794 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17795 }, 17796 outputs: []outputInfo{ 17797 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17798 }, 17799 }, 17800 }, 17801 { 17802 name: "OR", 17803 argLen: 2, 17804 commutative: true, 17805 clobberFlags: true, 17806 asm: s390x.AOR, 17807 reg: regInfo{ 17808 inputs: []inputInfo{ 17809 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17810 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17811 }, 17812 outputs: []outputInfo{ 17813 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17814 }, 17815 }, 17816 }, 17817 { 17818 name: "ORW", 17819 argLen: 2, 17820 commutative: true, 17821 clobberFlags: true, 17822 asm: s390x.AORW, 17823 reg: regInfo{ 17824 inputs: []inputInfo{ 17825 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17826 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17827 }, 17828 outputs: []outputInfo{ 17829 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17830 }, 17831 }, 17832 }, 17833 { 17834 name: "ORconst", 17835 auxType: auxInt64, 17836 argLen: 1, 17837 resultInArg0: true, 17838 clobberFlags: true, 17839 asm: s390x.AOR, 17840 reg: regInfo{ 17841 inputs: []inputInfo{ 17842 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17843 }, 17844 outputs: []outputInfo{ 17845 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17846 }, 17847 }, 17848 }, 17849 { 17850 name: "ORWconst", 17851 auxType: auxInt32, 17852 argLen: 1, 17853 resultInArg0: true, 17854 clobberFlags: true, 17855 asm: s390x.AORW, 17856 reg: regInfo{ 17857 inputs: []inputInfo{ 17858 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17859 }, 17860 outputs: []outputInfo{ 17861 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17862 }, 17863 }, 17864 }, 17865 { 17866 name: "ORload", 17867 auxType: auxSymOff, 17868 argLen: 3, 17869 resultInArg0: true, 17870 clobberFlags: true, 17871 faultOnNilArg1: true, 17872 asm: s390x.AOR, 17873 reg: regInfo{ 17874 inputs: []inputInfo{ 17875 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17876 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17877 }, 17878 outputs: []outputInfo{ 17879 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17880 }, 17881 }, 17882 }, 17883 { 17884 name: "ORWload", 17885 auxType: auxSymOff, 17886 argLen: 3, 17887 resultInArg0: true, 17888 clobberFlags: true, 17889 faultOnNilArg1: true, 17890 asm: s390x.AORW, 17891 reg: regInfo{ 17892 inputs: []inputInfo{ 17893 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17894 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17895 }, 17896 outputs: []outputInfo{ 17897 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17898 }, 17899 }, 17900 }, 17901 { 17902 name: "XOR", 17903 argLen: 2, 17904 commutative: true, 17905 clobberFlags: true, 17906 asm: s390x.AXOR, 17907 reg: regInfo{ 17908 inputs: []inputInfo{ 17909 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17910 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17911 }, 17912 outputs: []outputInfo{ 17913 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17914 }, 17915 }, 17916 }, 17917 { 17918 name: "XORW", 17919 argLen: 2, 17920 commutative: true, 17921 clobberFlags: true, 17922 asm: s390x.AXORW, 17923 reg: regInfo{ 17924 inputs: []inputInfo{ 17925 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17926 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17927 }, 17928 outputs: []outputInfo{ 17929 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17930 }, 17931 }, 17932 }, 17933 { 17934 name: "XORconst", 17935 auxType: auxInt64, 17936 argLen: 1, 17937 resultInArg0: true, 17938 clobberFlags: true, 17939 asm: s390x.AXOR, 17940 reg: regInfo{ 17941 inputs: []inputInfo{ 17942 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17943 }, 17944 outputs: []outputInfo{ 17945 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17946 }, 17947 }, 17948 }, 17949 { 17950 name: "XORWconst", 17951 auxType: auxInt32, 17952 argLen: 1, 17953 resultInArg0: true, 17954 clobberFlags: true, 17955 asm: s390x.AXORW, 17956 reg: regInfo{ 17957 inputs: []inputInfo{ 17958 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17959 }, 17960 outputs: []outputInfo{ 17961 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17962 }, 17963 }, 17964 }, 17965 { 17966 name: "XORload", 17967 auxType: auxSymOff, 17968 argLen: 3, 17969 resultInArg0: true, 17970 clobberFlags: true, 17971 faultOnNilArg1: true, 17972 asm: s390x.AXOR, 17973 reg: regInfo{ 17974 inputs: []inputInfo{ 17975 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17976 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17977 }, 17978 outputs: []outputInfo{ 17979 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17980 }, 17981 }, 17982 }, 17983 { 17984 name: "XORWload", 17985 auxType: auxSymOff, 17986 argLen: 3, 17987 resultInArg0: true, 17988 clobberFlags: true, 17989 faultOnNilArg1: true, 17990 asm: s390x.AXORW, 17991 reg: regInfo{ 17992 inputs: []inputInfo{ 17993 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17994 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17995 }, 17996 outputs: []outputInfo{ 17997 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17998 }, 17999 }, 18000 }, 18001 { 18002 name: "CMP", 18003 argLen: 2, 18004 asm: s390x.ACMP, 18005 reg: regInfo{ 18006 inputs: []inputInfo{ 18007 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18008 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18009 }, 18010 }, 18011 }, 18012 { 18013 name: "CMPW", 18014 argLen: 2, 18015 asm: s390x.ACMPW, 18016 reg: regInfo{ 18017 inputs: []inputInfo{ 18018 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18019 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18020 }, 18021 }, 18022 }, 18023 { 18024 name: "CMPU", 18025 argLen: 2, 18026 asm: s390x.ACMPU, 18027 reg: regInfo{ 18028 inputs: []inputInfo{ 18029 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18030 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18031 }, 18032 }, 18033 }, 18034 { 18035 name: "CMPWU", 18036 argLen: 2, 18037 asm: s390x.ACMPWU, 18038 reg: regInfo{ 18039 inputs: []inputInfo{ 18040 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18041 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18042 }, 18043 }, 18044 }, 18045 { 18046 name: "CMPconst", 18047 auxType: auxInt64, 18048 argLen: 1, 18049 asm: s390x.ACMP, 18050 reg: regInfo{ 18051 inputs: []inputInfo{ 18052 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18053 }, 18054 }, 18055 }, 18056 { 18057 name: "CMPWconst", 18058 auxType: auxInt32, 18059 argLen: 1, 18060 asm: s390x.ACMPW, 18061 reg: regInfo{ 18062 inputs: []inputInfo{ 18063 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18064 }, 18065 }, 18066 }, 18067 { 18068 name: "CMPUconst", 18069 auxType: auxInt64, 18070 argLen: 1, 18071 asm: s390x.ACMPU, 18072 reg: regInfo{ 18073 inputs: []inputInfo{ 18074 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18075 }, 18076 }, 18077 }, 18078 { 18079 name: "CMPWUconst", 18080 auxType: auxInt32, 18081 argLen: 1, 18082 asm: s390x.ACMPWU, 18083 reg: regInfo{ 18084 inputs: []inputInfo{ 18085 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18086 }, 18087 }, 18088 }, 18089 { 18090 name: "FCMPS", 18091 argLen: 2, 18092 asm: s390x.ACEBR, 18093 reg: regInfo{ 18094 inputs: []inputInfo{ 18095 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18096 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18097 }, 18098 }, 18099 }, 18100 { 18101 name: "FCMP", 18102 argLen: 2, 18103 asm: s390x.AFCMPU, 18104 reg: regInfo{ 18105 inputs: []inputInfo{ 18106 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18107 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18108 }, 18109 }, 18110 }, 18111 { 18112 name: "SLD", 18113 argLen: 2, 18114 asm: s390x.ASLD, 18115 reg: regInfo{ 18116 inputs: []inputInfo{ 18117 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18118 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18119 }, 18120 outputs: []outputInfo{ 18121 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18122 }, 18123 }, 18124 }, 18125 { 18126 name: "SLW", 18127 argLen: 2, 18128 asm: s390x.ASLW, 18129 reg: regInfo{ 18130 inputs: []inputInfo{ 18131 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18132 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18133 }, 18134 outputs: []outputInfo{ 18135 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18136 }, 18137 }, 18138 }, 18139 { 18140 name: "SLDconst", 18141 auxType: auxInt64, 18142 argLen: 1, 18143 asm: s390x.ASLD, 18144 reg: regInfo{ 18145 inputs: []inputInfo{ 18146 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18147 }, 18148 outputs: []outputInfo{ 18149 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18150 }, 18151 }, 18152 }, 18153 { 18154 name: "SLWconst", 18155 auxType: auxInt32, 18156 argLen: 1, 18157 asm: s390x.ASLW, 18158 reg: regInfo{ 18159 inputs: []inputInfo{ 18160 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18161 }, 18162 outputs: []outputInfo{ 18163 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18164 }, 18165 }, 18166 }, 18167 { 18168 name: "SRD", 18169 argLen: 2, 18170 asm: s390x.ASRD, 18171 reg: regInfo{ 18172 inputs: []inputInfo{ 18173 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18174 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18175 }, 18176 outputs: []outputInfo{ 18177 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18178 }, 18179 }, 18180 }, 18181 { 18182 name: "SRW", 18183 argLen: 2, 18184 asm: s390x.ASRW, 18185 reg: regInfo{ 18186 inputs: []inputInfo{ 18187 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18188 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18189 }, 18190 outputs: []outputInfo{ 18191 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18192 }, 18193 }, 18194 }, 18195 { 18196 name: "SRDconst", 18197 auxType: auxInt64, 18198 argLen: 1, 18199 asm: s390x.ASRD, 18200 reg: regInfo{ 18201 inputs: []inputInfo{ 18202 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18203 }, 18204 outputs: []outputInfo{ 18205 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18206 }, 18207 }, 18208 }, 18209 { 18210 name: "SRWconst", 18211 auxType: auxInt32, 18212 argLen: 1, 18213 asm: s390x.ASRW, 18214 reg: regInfo{ 18215 inputs: []inputInfo{ 18216 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18217 }, 18218 outputs: []outputInfo{ 18219 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18220 }, 18221 }, 18222 }, 18223 { 18224 name: "SRAD", 18225 argLen: 2, 18226 clobberFlags: true, 18227 asm: s390x.ASRAD, 18228 reg: regInfo{ 18229 inputs: []inputInfo{ 18230 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18231 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18232 }, 18233 outputs: []outputInfo{ 18234 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18235 }, 18236 }, 18237 }, 18238 { 18239 name: "SRAW", 18240 argLen: 2, 18241 clobberFlags: true, 18242 asm: s390x.ASRAW, 18243 reg: regInfo{ 18244 inputs: []inputInfo{ 18245 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18246 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18247 }, 18248 outputs: []outputInfo{ 18249 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18250 }, 18251 }, 18252 }, 18253 { 18254 name: "SRADconst", 18255 auxType: auxInt64, 18256 argLen: 1, 18257 clobberFlags: true, 18258 asm: s390x.ASRAD, 18259 reg: regInfo{ 18260 inputs: []inputInfo{ 18261 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18262 }, 18263 outputs: []outputInfo{ 18264 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18265 }, 18266 }, 18267 }, 18268 { 18269 name: "SRAWconst", 18270 auxType: auxInt32, 18271 argLen: 1, 18272 clobberFlags: true, 18273 asm: s390x.ASRAW, 18274 reg: regInfo{ 18275 inputs: []inputInfo{ 18276 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18277 }, 18278 outputs: []outputInfo{ 18279 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18280 }, 18281 }, 18282 }, 18283 { 18284 name: "RLLGconst", 18285 auxType: auxInt64, 18286 argLen: 1, 18287 asm: s390x.ARLLG, 18288 reg: regInfo{ 18289 inputs: []inputInfo{ 18290 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18291 }, 18292 outputs: []outputInfo{ 18293 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18294 }, 18295 }, 18296 }, 18297 { 18298 name: "RLLconst", 18299 auxType: auxInt32, 18300 argLen: 1, 18301 asm: s390x.ARLL, 18302 reg: regInfo{ 18303 inputs: []inputInfo{ 18304 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18305 }, 18306 outputs: []outputInfo{ 18307 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18308 }, 18309 }, 18310 }, 18311 { 18312 name: "NEG", 18313 argLen: 1, 18314 clobberFlags: true, 18315 asm: s390x.ANEG, 18316 reg: regInfo{ 18317 inputs: []inputInfo{ 18318 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18319 }, 18320 outputs: []outputInfo{ 18321 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18322 }, 18323 }, 18324 }, 18325 { 18326 name: "NEGW", 18327 argLen: 1, 18328 clobberFlags: true, 18329 asm: s390x.ANEGW, 18330 reg: regInfo{ 18331 inputs: []inputInfo{ 18332 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18333 }, 18334 outputs: []outputInfo{ 18335 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18336 }, 18337 }, 18338 }, 18339 { 18340 name: "NOT", 18341 argLen: 1, 18342 resultInArg0: true, 18343 clobberFlags: true, 18344 reg: regInfo{ 18345 inputs: []inputInfo{ 18346 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18347 }, 18348 outputs: []outputInfo{ 18349 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18350 }, 18351 }, 18352 }, 18353 { 18354 name: "NOTW", 18355 argLen: 1, 18356 resultInArg0: true, 18357 clobberFlags: true, 18358 reg: regInfo{ 18359 inputs: []inputInfo{ 18360 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18361 }, 18362 outputs: []outputInfo{ 18363 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18364 }, 18365 }, 18366 }, 18367 { 18368 name: "FSQRT", 18369 argLen: 1, 18370 asm: s390x.AFSQRT, 18371 reg: regInfo{ 18372 inputs: []inputInfo{ 18373 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18374 }, 18375 outputs: []outputInfo{ 18376 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18377 }, 18378 }, 18379 }, 18380 { 18381 name: "SUBEcarrymask", 18382 argLen: 1, 18383 asm: s390x.ASUBE, 18384 reg: regInfo{ 18385 outputs: []outputInfo{ 18386 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18387 }, 18388 }, 18389 }, 18390 { 18391 name: "SUBEWcarrymask", 18392 argLen: 1, 18393 asm: s390x.ASUBE, 18394 reg: regInfo{ 18395 outputs: []outputInfo{ 18396 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18397 }, 18398 }, 18399 }, 18400 { 18401 name: "MOVDEQ", 18402 argLen: 3, 18403 resultInArg0: true, 18404 asm: s390x.AMOVDEQ, 18405 reg: regInfo{ 18406 inputs: []inputInfo{ 18407 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18408 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18409 }, 18410 outputs: []outputInfo{ 18411 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18412 }, 18413 }, 18414 }, 18415 { 18416 name: "MOVDNE", 18417 argLen: 3, 18418 resultInArg0: true, 18419 asm: s390x.AMOVDNE, 18420 reg: regInfo{ 18421 inputs: []inputInfo{ 18422 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18423 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18424 }, 18425 outputs: []outputInfo{ 18426 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18427 }, 18428 }, 18429 }, 18430 { 18431 name: "MOVDLT", 18432 argLen: 3, 18433 resultInArg0: true, 18434 asm: s390x.AMOVDLT, 18435 reg: regInfo{ 18436 inputs: []inputInfo{ 18437 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18438 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18439 }, 18440 outputs: []outputInfo{ 18441 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18442 }, 18443 }, 18444 }, 18445 { 18446 name: "MOVDLE", 18447 argLen: 3, 18448 resultInArg0: true, 18449 asm: s390x.AMOVDLE, 18450 reg: regInfo{ 18451 inputs: []inputInfo{ 18452 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18453 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18454 }, 18455 outputs: []outputInfo{ 18456 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18457 }, 18458 }, 18459 }, 18460 { 18461 name: "MOVDGT", 18462 argLen: 3, 18463 resultInArg0: true, 18464 asm: s390x.AMOVDGT, 18465 reg: regInfo{ 18466 inputs: []inputInfo{ 18467 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18468 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18469 }, 18470 outputs: []outputInfo{ 18471 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18472 }, 18473 }, 18474 }, 18475 { 18476 name: "MOVDGE", 18477 argLen: 3, 18478 resultInArg0: true, 18479 asm: s390x.AMOVDGE, 18480 reg: regInfo{ 18481 inputs: []inputInfo{ 18482 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18483 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18484 }, 18485 outputs: []outputInfo{ 18486 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18487 }, 18488 }, 18489 }, 18490 { 18491 name: "MOVDGTnoinv", 18492 argLen: 3, 18493 resultInArg0: true, 18494 asm: s390x.AMOVDGT, 18495 reg: regInfo{ 18496 inputs: []inputInfo{ 18497 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18498 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18499 }, 18500 outputs: []outputInfo{ 18501 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18502 }, 18503 }, 18504 }, 18505 { 18506 name: "MOVDGEnoinv", 18507 argLen: 3, 18508 resultInArg0: true, 18509 asm: s390x.AMOVDGE, 18510 reg: regInfo{ 18511 inputs: []inputInfo{ 18512 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18513 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18514 }, 18515 outputs: []outputInfo{ 18516 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18517 }, 18518 }, 18519 }, 18520 { 18521 name: "MOVBreg", 18522 argLen: 1, 18523 asm: s390x.AMOVB, 18524 reg: regInfo{ 18525 inputs: []inputInfo{ 18526 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18527 }, 18528 outputs: []outputInfo{ 18529 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18530 }, 18531 }, 18532 }, 18533 { 18534 name: "MOVBZreg", 18535 argLen: 1, 18536 asm: s390x.AMOVBZ, 18537 reg: regInfo{ 18538 inputs: []inputInfo{ 18539 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18540 }, 18541 outputs: []outputInfo{ 18542 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18543 }, 18544 }, 18545 }, 18546 { 18547 name: "MOVHreg", 18548 argLen: 1, 18549 asm: s390x.AMOVH, 18550 reg: regInfo{ 18551 inputs: []inputInfo{ 18552 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18553 }, 18554 outputs: []outputInfo{ 18555 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18556 }, 18557 }, 18558 }, 18559 { 18560 name: "MOVHZreg", 18561 argLen: 1, 18562 asm: s390x.AMOVHZ, 18563 reg: regInfo{ 18564 inputs: []inputInfo{ 18565 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18566 }, 18567 outputs: []outputInfo{ 18568 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18569 }, 18570 }, 18571 }, 18572 { 18573 name: "MOVWreg", 18574 argLen: 1, 18575 asm: s390x.AMOVW, 18576 reg: regInfo{ 18577 inputs: []inputInfo{ 18578 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18579 }, 18580 outputs: []outputInfo{ 18581 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18582 }, 18583 }, 18584 }, 18585 { 18586 name: "MOVWZreg", 18587 argLen: 1, 18588 asm: s390x.AMOVWZ, 18589 reg: regInfo{ 18590 inputs: []inputInfo{ 18591 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18592 }, 18593 outputs: []outputInfo{ 18594 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18595 }, 18596 }, 18597 }, 18598 { 18599 name: "MOVDreg", 18600 argLen: 1, 18601 asm: s390x.AMOVD, 18602 reg: regInfo{ 18603 inputs: []inputInfo{ 18604 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18605 }, 18606 outputs: []outputInfo{ 18607 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18608 }, 18609 }, 18610 }, 18611 { 18612 name: "MOVDnop", 18613 argLen: 1, 18614 resultInArg0: true, 18615 reg: regInfo{ 18616 inputs: []inputInfo{ 18617 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18618 }, 18619 outputs: []outputInfo{ 18620 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18621 }, 18622 }, 18623 }, 18624 { 18625 name: "MOVDconst", 18626 auxType: auxInt64, 18627 argLen: 0, 18628 rematerializeable: true, 18629 asm: s390x.AMOVD, 18630 reg: regInfo{ 18631 outputs: []outputInfo{ 18632 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18633 }, 18634 }, 18635 }, 18636 { 18637 name: "CFDBRA", 18638 argLen: 1, 18639 asm: s390x.ACFDBRA, 18640 reg: regInfo{ 18641 inputs: []inputInfo{ 18642 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18643 }, 18644 outputs: []outputInfo{ 18645 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18646 }, 18647 }, 18648 }, 18649 { 18650 name: "CGDBRA", 18651 argLen: 1, 18652 asm: s390x.ACGDBRA, 18653 reg: regInfo{ 18654 inputs: []inputInfo{ 18655 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18656 }, 18657 outputs: []outputInfo{ 18658 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18659 }, 18660 }, 18661 }, 18662 { 18663 name: "CFEBRA", 18664 argLen: 1, 18665 asm: s390x.ACFEBRA, 18666 reg: regInfo{ 18667 inputs: []inputInfo{ 18668 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18669 }, 18670 outputs: []outputInfo{ 18671 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18672 }, 18673 }, 18674 }, 18675 { 18676 name: "CGEBRA", 18677 argLen: 1, 18678 asm: s390x.ACGEBRA, 18679 reg: regInfo{ 18680 inputs: []inputInfo{ 18681 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18682 }, 18683 outputs: []outputInfo{ 18684 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18685 }, 18686 }, 18687 }, 18688 { 18689 name: "CEFBRA", 18690 argLen: 1, 18691 asm: s390x.ACEFBRA, 18692 reg: regInfo{ 18693 inputs: []inputInfo{ 18694 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18695 }, 18696 outputs: []outputInfo{ 18697 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18698 }, 18699 }, 18700 }, 18701 { 18702 name: "CDFBRA", 18703 argLen: 1, 18704 asm: s390x.ACDFBRA, 18705 reg: regInfo{ 18706 inputs: []inputInfo{ 18707 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18708 }, 18709 outputs: []outputInfo{ 18710 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18711 }, 18712 }, 18713 }, 18714 { 18715 name: "CEGBRA", 18716 argLen: 1, 18717 asm: s390x.ACEGBRA, 18718 reg: regInfo{ 18719 inputs: []inputInfo{ 18720 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18721 }, 18722 outputs: []outputInfo{ 18723 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18724 }, 18725 }, 18726 }, 18727 { 18728 name: "CDGBRA", 18729 argLen: 1, 18730 asm: s390x.ACDGBRA, 18731 reg: regInfo{ 18732 inputs: []inputInfo{ 18733 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18734 }, 18735 outputs: []outputInfo{ 18736 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18737 }, 18738 }, 18739 }, 18740 { 18741 name: "LEDBR", 18742 argLen: 1, 18743 asm: s390x.ALEDBR, 18744 reg: regInfo{ 18745 inputs: []inputInfo{ 18746 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18747 }, 18748 outputs: []outputInfo{ 18749 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18750 }, 18751 }, 18752 }, 18753 { 18754 name: "LDEBR", 18755 argLen: 1, 18756 asm: s390x.ALDEBR, 18757 reg: regInfo{ 18758 inputs: []inputInfo{ 18759 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18760 }, 18761 outputs: []outputInfo{ 18762 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18763 }, 18764 }, 18765 }, 18766 { 18767 name: "MOVDaddr", 18768 auxType: auxSymOff, 18769 argLen: 1, 18770 rematerializeable: true, 18771 clobberFlags: true, 18772 reg: regInfo{ 18773 inputs: []inputInfo{ 18774 {0, 4295000064}, // SP SB 18775 }, 18776 outputs: []outputInfo{ 18777 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18778 }, 18779 }, 18780 }, 18781 { 18782 name: "MOVDaddridx", 18783 auxType: auxSymOff, 18784 argLen: 2, 18785 clobberFlags: true, 18786 reg: regInfo{ 18787 inputs: []inputInfo{ 18788 {0, 4295000064}, // SP SB 18789 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18790 }, 18791 outputs: []outputInfo{ 18792 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18793 }, 18794 }, 18795 }, 18796 { 18797 name: "MOVBZload", 18798 auxType: auxSymOff, 18799 argLen: 2, 18800 clobberFlags: true, 18801 faultOnNilArg0: true, 18802 asm: s390x.AMOVBZ, 18803 reg: regInfo{ 18804 inputs: []inputInfo{ 18805 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18806 }, 18807 outputs: []outputInfo{ 18808 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18809 }, 18810 }, 18811 }, 18812 { 18813 name: "MOVBload", 18814 auxType: auxSymOff, 18815 argLen: 2, 18816 clobberFlags: true, 18817 faultOnNilArg0: true, 18818 asm: s390x.AMOVB, 18819 reg: regInfo{ 18820 inputs: []inputInfo{ 18821 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18822 }, 18823 outputs: []outputInfo{ 18824 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18825 }, 18826 }, 18827 }, 18828 { 18829 name: "MOVHZload", 18830 auxType: auxSymOff, 18831 argLen: 2, 18832 clobberFlags: true, 18833 faultOnNilArg0: true, 18834 asm: s390x.AMOVHZ, 18835 reg: regInfo{ 18836 inputs: []inputInfo{ 18837 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18838 }, 18839 outputs: []outputInfo{ 18840 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18841 }, 18842 }, 18843 }, 18844 { 18845 name: "MOVHload", 18846 auxType: auxSymOff, 18847 argLen: 2, 18848 clobberFlags: true, 18849 faultOnNilArg0: true, 18850 asm: s390x.AMOVH, 18851 reg: regInfo{ 18852 inputs: []inputInfo{ 18853 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18854 }, 18855 outputs: []outputInfo{ 18856 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18857 }, 18858 }, 18859 }, 18860 { 18861 name: "MOVWZload", 18862 auxType: auxSymOff, 18863 argLen: 2, 18864 clobberFlags: true, 18865 faultOnNilArg0: true, 18866 asm: s390x.AMOVWZ, 18867 reg: regInfo{ 18868 inputs: []inputInfo{ 18869 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18870 }, 18871 outputs: []outputInfo{ 18872 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18873 }, 18874 }, 18875 }, 18876 { 18877 name: "MOVWload", 18878 auxType: auxSymOff, 18879 argLen: 2, 18880 clobberFlags: true, 18881 faultOnNilArg0: true, 18882 asm: s390x.AMOVW, 18883 reg: regInfo{ 18884 inputs: []inputInfo{ 18885 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18886 }, 18887 outputs: []outputInfo{ 18888 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18889 }, 18890 }, 18891 }, 18892 { 18893 name: "MOVDload", 18894 auxType: auxSymOff, 18895 argLen: 2, 18896 clobberFlags: true, 18897 faultOnNilArg0: true, 18898 asm: s390x.AMOVD, 18899 reg: regInfo{ 18900 inputs: []inputInfo{ 18901 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18902 }, 18903 outputs: []outputInfo{ 18904 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18905 }, 18906 }, 18907 }, 18908 { 18909 name: "MOVWBR", 18910 argLen: 1, 18911 asm: s390x.AMOVWBR, 18912 reg: regInfo{ 18913 inputs: []inputInfo{ 18914 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18915 }, 18916 outputs: []outputInfo{ 18917 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18918 }, 18919 }, 18920 }, 18921 { 18922 name: "MOVDBR", 18923 argLen: 1, 18924 asm: s390x.AMOVDBR, 18925 reg: regInfo{ 18926 inputs: []inputInfo{ 18927 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18928 }, 18929 outputs: []outputInfo{ 18930 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18931 }, 18932 }, 18933 }, 18934 { 18935 name: "MOVHBRload", 18936 auxType: auxSymOff, 18937 argLen: 2, 18938 clobberFlags: true, 18939 faultOnNilArg0: true, 18940 asm: s390x.AMOVHBR, 18941 reg: regInfo{ 18942 inputs: []inputInfo{ 18943 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18944 }, 18945 outputs: []outputInfo{ 18946 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18947 }, 18948 }, 18949 }, 18950 { 18951 name: "MOVWBRload", 18952 auxType: auxSymOff, 18953 argLen: 2, 18954 clobberFlags: true, 18955 faultOnNilArg0: true, 18956 asm: s390x.AMOVWBR, 18957 reg: regInfo{ 18958 inputs: []inputInfo{ 18959 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18960 }, 18961 outputs: []outputInfo{ 18962 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18963 }, 18964 }, 18965 }, 18966 { 18967 name: "MOVDBRload", 18968 auxType: auxSymOff, 18969 argLen: 2, 18970 clobberFlags: true, 18971 faultOnNilArg0: true, 18972 asm: s390x.AMOVDBR, 18973 reg: regInfo{ 18974 inputs: []inputInfo{ 18975 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18976 }, 18977 outputs: []outputInfo{ 18978 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18979 }, 18980 }, 18981 }, 18982 { 18983 name: "MOVBstore", 18984 auxType: auxSymOff, 18985 argLen: 3, 18986 clobberFlags: true, 18987 faultOnNilArg0: true, 18988 asm: s390x.AMOVB, 18989 reg: regInfo{ 18990 inputs: []inputInfo{ 18991 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18992 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18993 }, 18994 }, 18995 }, 18996 { 18997 name: "MOVHstore", 18998 auxType: auxSymOff, 18999 argLen: 3, 19000 clobberFlags: true, 19001 faultOnNilArg0: true, 19002 asm: s390x.AMOVH, 19003 reg: regInfo{ 19004 inputs: []inputInfo{ 19005 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19006 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19007 }, 19008 }, 19009 }, 19010 { 19011 name: "MOVWstore", 19012 auxType: auxSymOff, 19013 argLen: 3, 19014 clobberFlags: true, 19015 faultOnNilArg0: true, 19016 asm: s390x.AMOVW, 19017 reg: regInfo{ 19018 inputs: []inputInfo{ 19019 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19020 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19021 }, 19022 }, 19023 }, 19024 { 19025 name: "MOVDstore", 19026 auxType: auxSymOff, 19027 argLen: 3, 19028 clobberFlags: true, 19029 faultOnNilArg0: true, 19030 asm: s390x.AMOVD, 19031 reg: regInfo{ 19032 inputs: []inputInfo{ 19033 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19034 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19035 }, 19036 }, 19037 }, 19038 { 19039 name: "MOVHBRstore", 19040 auxType: auxSymOff, 19041 argLen: 3, 19042 clobberFlags: true, 19043 faultOnNilArg0: true, 19044 asm: s390x.AMOVHBR, 19045 reg: regInfo{ 19046 inputs: []inputInfo{ 19047 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19048 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19049 }, 19050 }, 19051 }, 19052 { 19053 name: "MOVWBRstore", 19054 auxType: auxSymOff, 19055 argLen: 3, 19056 clobberFlags: true, 19057 faultOnNilArg0: true, 19058 asm: s390x.AMOVWBR, 19059 reg: regInfo{ 19060 inputs: []inputInfo{ 19061 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19062 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19063 }, 19064 }, 19065 }, 19066 { 19067 name: "MOVDBRstore", 19068 auxType: auxSymOff, 19069 argLen: 3, 19070 clobberFlags: true, 19071 faultOnNilArg0: true, 19072 asm: s390x.AMOVDBR, 19073 reg: regInfo{ 19074 inputs: []inputInfo{ 19075 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19076 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19077 }, 19078 }, 19079 }, 19080 { 19081 name: "MVC", 19082 auxType: auxSymValAndOff, 19083 argLen: 3, 19084 clobberFlags: true, 19085 faultOnNilArg0: true, 19086 faultOnNilArg1: true, 19087 asm: s390x.AMVC, 19088 reg: regInfo{ 19089 inputs: []inputInfo{ 19090 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19091 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19092 }, 19093 }, 19094 }, 19095 { 19096 name: "MOVBZloadidx", 19097 auxType: auxSymOff, 19098 argLen: 3, 19099 clobberFlags: true, 19100 asm: s390x.AMOVBZ, 19101 reg: regInfo{ 19102 inputs: []inputInfo{ 19103 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19104 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19105 }, 19106 outputs: []outputInfo{ 19107 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19108 }, 19109 }, 19110 }, 19111 { 19112 name: "MOVHZloadidx", 19113 auxType: auxSymOff, 19114 argLen: 3, 19115 clobberFlags: true, 19116 asm: s390x.AMOVHZ, 19117 reg: regInfo{ 19118 inputs: []inputInfo{ 19119 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19120 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19121 }, 19122 outputs: []outputInfo{ 19123 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19124 }, 19125 }, 19126 }, 19127 { 19128 name: "MOVWZloadidx", 19129 auxType: auxSymOff, 19130 argLen: 3, 19131 clobberFlags: true, 19132 asm: s390x.AMOVWZ, 19133 reg: regInfo{ 19134 inputs: []inputInfo{ 19135 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19136 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19137 }, 19138 outputs: []outputInfo{ 19139 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19140 }, 19141 }, 19142 }, 19143 { 19144 name: "MOVDloadidx", 19145 auxType: auxSymOff, 19146 argLen: 3, 19147 clobberFlags: true, 19148 asm: s390x.AMOVD, 19149 reg: regInfo{ 19150 inputs: []inputInfo{ 19151 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19152 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19153 }, 19154 outputs: []outputInfo{ 19155 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19156 }, 19157 }, 19158 }, 19159 { 19160 name: "MOVHBRloadidx", 19161 auxType: auxSymOff, 19162 argLen: 3, 19163 clobberFlags: true, 19164 asm: s390x.AMOVHBR, 19165 reg: regInfo{ 19166 inputs: []inputInfo{ 19167 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19168 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19169 }, 19170 outputs: []outputInfo{ 19171 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19172 }, 19173 }, 19174 }, 19175 { 19176 name: "MOVWBRloadidx", 19177 auxType: auxSymOff, 19178 argLen: 3, 19179 clobberFlags: true, 19180 asm: s390x.AMOVWBR, 19181 reg: regInfo{ 19182 inputs: []inputInfo{ 19183 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19184 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19185 }, 19186 outputs: []outputInfo{ 19187 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19188 }, 19189 }, 19190 }, 19191 { 19192 name: "MOVDBRloadidx", 19193 auxType: auxSymOff, 19194 argLen: 3, 19195 clobberFlags: true, 19196 asm: s390x.AMOVDBR, 19197 reg: regInfo{ 19198 inputs: []inputInfo{ 19199 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19200 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19201 }, 19202 outputs: []outputInfo{ 19203 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19204 }, 19205 }, 19206 }, 19207 { 19208 name: "MOVBstoreidx", 19209 auxType: auxSymOff, 19210 argLen: 4, 19211 clobberFlags: true, 19212 asm: s390x.AMOVB, 19213 reg: regInfo{ 19214 inputs: []inputInfo{ 19215 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19216 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19217 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19218 }, 19219 }, 19220 }, 19221 { 19222 name: "MOVHstoreidx", 19223 auxType: auxSymOff, 19224 argLen: 4, 19225 clobberFlags: true, 19226 asm: s390x.AMOVH, 19227 reg: regInfo{ 19228 inputs: []inputInfo{ 19229 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19230 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19231 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19232 }, 19233 }, 19234 }, 19235 { 19236 name: "MOVWstoreidx", 19237 auxType: auxSymOff, 19238 argLen: 4, 19239 clobberFlags: true, 19240 asm: s390x.AMOVW, 19241 reg: regInfo{ 19242 inputs: []inputInfo{ 19243 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19244 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19245 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19246 }, 19247 }, 19248 }, 19249 { 19250 name: "MOVDstoreidx", 19251 auxType: auxSymOff, 19252 argLen: 4, 19253 clobberFlags: true, 19254 asm: s390x.AMOVD, 19255 reg: regInfo{ 19256 inputs: []inputInfo{ 19257 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19258 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19259 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19260 }, 19261 }, 19262 }, 19263 { 19264 name: "MOVHBRstoreidx", 19265 auxType: auxSymOff, 19266 argLen: 4, 19267 clobberFlags: true, 19268 asm: s390x.AMOVHBR, 19269 reg: regInfo{ 19270 inputs: []inputInfo{ 19271 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19272 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19273 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19274 }, 19275 }, 19276 }, 19277 { 19278 name: "MOVWBRstoreidx", 19279 auxType: auxSymOff, 19280 argLen: 4, 19281 clobberFlags: true, 19282 asm: s390x.AMOVWBR, 19283 reg: regInfo{ 19284 inputs: []inputInfo{ 19285 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19286 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19287 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19288 }, 19289 }, 19290 }, 19291 { 19292 name: "MOVDBRstoreidx", 19293 auxType: auxSymOff, 19294 argLen: 4, 19295 clobberFlags: true, 19296 asm: s390x.AMOVDBR, 19297 reg: regInfo{ 19298 inputs: []inputInfo{ 19299 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19300 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19301 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19302 }, 19303 }, 19304 }, 19305 { 19306 name: "MOVBstoreconst", 19307 auxType: auxSymValAndOff, 19308 argLen: 2, 19309 clobberFlags: true, 19310 faultOnNilArg0: true, 19311 asm: s390x.AMOVB, 19312 reg: regInfo{ 19313 inputs: []inputInfo{ 19314 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19315 }, 19316 }, 19317 }, 19318 { 19319 name: "MOVHstoreconst", 19320 auxType: auxSymValAndOff, 19321 argLen: 2, 19322 clobberFlags: true, 19323 faultOnNilArg0: true, 19324 asm: s390x.AMOVH, 19325 reg: regInfo{ 19326 inputs: []inputInfo{ 19327 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19328 }, 19329 }, 19330 }, 19331 { 19332 name: "MOVWstoreconst", 19333 auxType: auxSymValAndOff, 19334 argLen: 2, 19335 clobberFlags: true, 19336 faultOnNilArg0: true, 19337 asm: s390x.AMOVW, 19338 reg: regInfo{ 19339 inputs: []inputInfo{ 19340 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19341 }, 19342 }, 19343 }, 19344 { 19345 name: "MOVDstoreconst", 19346 auxType: auxSymValAndOff, 19347 argLen: 2, 19348 clobberFlags: true, 19349 faultOnNilArg0: true, 19350 asm: s390x.AMOVD, 19351 reg: regInfo{ 19352 inputs: []inputInfo{ 19353 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19354 }, 19355 }, 19356 }, 19357 { 19358 name: "CLEAR", 19359 auxType: auxSymValAndOff, 19360 argLen: 2, 19361 clobberFlags: true, 19362 faultOnNilArg0: true, 19363 asm: s390x.ACLEAR, 19364 reg: regInfo{ 19365 inputs: []inputInfo{ 19366 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19367 }, 19368 }, 19369 }, 19370 { 19371 name: "CALLstatic", 19372 auxType: auxSymOff, 19373 argLen: 1, 19374 clobberFlags: true, 19375 call: true, 19376 reg: regInfo{ 19377 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19378 }, 19379 }, 19380 { 19381 name: "CALLclosure", 19382 auxType: auxInt64, 19383 argLen: 3, 19384 clobberFlags: true, 19385 call: true, 19386 reg: regInfo{ 19387 inputs: []inputInfo{ 19388 {1, 4096}, // R12 19389 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19390 }, 19391 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19392 }, 19393 }, 19394 { 19395 name: "CALLdefer", 19396 auxType: auxInt64, 19397 argLen: 1, 19398 clobberFlags: true, 19399 call: true, 19400 reg: regInfo{ 19401 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19402 }, 19403 }, 19404 { 19405 name: "CALLgo", 19406 auxType: auxInt64, 19407 argLen: 1, 19408 clobberFlags: true, 19409 call: true, 19410 reg: regInfo{ 19411 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19412 }, 19413 }, 19414 { 19415 name: "CALLinter", 19416 auxType: auxInt64, 19417 argLen: 2, 19418 clobberFlags: true, 19419 call: true, 19420 reg: regInfo{ 19421 inputs: []inputInfo{ 19422 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19423 }, 19424 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19425 }, 19426 }, 19427 { 19428 name: "InvertFlags", 19429 argLen: 1, 19430 reg: regInfo{}, 19431 }, 19432 { 19433 name: "LoweredGetG", 19434 argLen: 1, 19435 reg: regInfo{ 19436 outputs: []outputInfo{ 19437 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19438 }, 19439 }, 19440 }, 19441 { 19442 name: "LoweredGetClosurePtr", 19443 argLen: 0, 19444 reg: regInfo{ 19445 outputs: []outputInfo{ 19446 {0, 4096}, // R12 19447 }, 19448 }, 19449 }, 19450 { 19451 name: "LoweredNilCheck", 19452 argLen: 2, 19453 clobberFlags: true, 19454 nilCheck: true, 19455 faultOnNilArg0: true, 19456 reg: regInfo{ 19457 inputs: []inputInfo{ 19458 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19459 }, 19460 }, 19461 }, 19462 { 19463 name: "MOVDconvert", 19464 argLen: 2, 19465 asm: s390x.AMOVD, 19466 reg: regInfo{ 19467 inputs: []inputInfo{ 19468 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19469 }, 19470 outputs: []outputInfo{ 19471 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19472 }, 19473 }, 19474 }, 19475 { 19476 name: "FlagEQ", 19477 argLen: 0, 19478 reg: regInfo{}, 19479 }, 19480 { 19481 name: "FlagLT", 19482 argLen: 0, 19483 reg: regInfo{}, 19484 }, 19485 { 19486 name: "FlagGT", 19487 argLen: 0, 19488 reg: regInfo{}, 19489 }, 19490 { 19491 name: "MOVWZatomicload", 19492 auxType: auxSymOff, 19493 argLen: 2, 19494 faultOnNilArg0: true, 19495 asm: s390x.AMOVWZ, 19496 reg: regInfo{ 19497 inputs: []inputInfo{ 19498 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19499 }, 19500 outputs: []outputInfo{ 19501 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19502 }, 19503 }, 19504 }, 19505 { 19506 name: "MOVDatomicload", 19507 auxType: auxSymOff, 19508 argLen: 2, 19509 faultOnNilArg0: true, 19510 asm: s390x.AMOVD, 19511 reg: regInfo{ 19512 inputs: []inputInfo{ 19513 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19514 }, 19515 outputs: []outputInfo{ 19516 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19517 }, 19518 }, 19519 }, 19520 { 19521 name: "MOVWatomicstore", 19522 auxType: auxSymOff, 19523 argLen: 3, 19524 clobberFlags: true, 19525 faultOnNilArg0: true, 19526 asm: s390x.AMOVW, 19527 reg: regInfo{ 19528 inputs: []inputInfo{ 19529 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19530 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19531 }, 19532 }, 19533 }, 19534 { 19535 name: "MOVDatomicstore", 19536 auxType: auxSymOff, 19537 argLen: 3, 19538 clobberFlags: true, 19539 faultOnNilArg0: true, 19540 asm: s390x.AMOVD, 19541 reg: regInfo{ 19542 inputs: []inputInfo{ 19543 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19544 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19545 }, 19546 }, 19547 }, 19548 { 19549 name: "LAA", 19550 auxType: auxSymOff, 19551 argLen: 3, 19552 faultOnNilArg0: true, 19553 asm: s390x.ALAA, 19554 reg: regInfo{ 19555 inputs: []inputInfo{ 19556 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19557 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19558 }, 19559 outputs: []outputInfo{ 19560 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19561 }, 19562 }, 19563 }, 19564 { 19565 name: "LAAG", 19566 auxType: auxSymOff, 19567 argLen: 3, 19568 faultOnNilArg0: true, 19569 asm: s390x.ALAAG, 19570 reg: regInfo{ 19571 inputs: []inputInfo{ 19572 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19573 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19574 }, 19575 outputs: []outputInfo{ 19576 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19577 }, 19578 }, 19579 }, 19580 { 19581 name: "AddTupleFirst32", 19582 argLen: 2, 19583 reg: regInfo{}, 19584 }, 19585 { 19586 name: "AddTupleFirst64", 19587 argLen: 2, 19588 reg: regInfo{}, 19589 }, 19590 { 19591 name: "LoweredAtomicCas32", 19592 auxType: auxSymOff, 19593 argLen: 4, 19594 clobberFlags: true, 19595 faultOnNilArg0: true, 19596 asm: s390x.ACS, 19597 reg: regInfo{ 19598 inputs: []inputInfo{ 19599 {1, 1}, // R0 19600 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19601 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19602 }, 19603 clobbers: 1, // R0 19604 outputs: []outputInfo{ 19605 {1, 0}, 19606 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19607 }, 19608 }, 19609 }, 19610 { 19611 name: "LoweredAtomicCas64", 19612 auxType: auxSymOff, 19613 argLen: 4, 19614 clobberFlags: true, 19615 faultOnNilArg0: true, 19616 asm: s390x.ACSG, 19617 reg: regInfo{ 19618 inputs: []inputInfo{ 19619 {1, 1}, // R0 19620 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19621 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19622 }, 19623 clobbers: 1, // R0 19624 outputs: []outputInfo{ 19625 {1, 0}, 19626 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19627 }, 19628 }, 19629 }, 19630 { 19631 name: "LoweredAtomicExchange32", 19632 auxType: auxSymOff, 19633 argLen: 3, 19634 clobberFlags: true, 19635 faultOnNilArg0: true, 19636 asm: s390x.ACS, 19637 reg: regInfo{ 19638 inputs: []inputInfo{ 19639 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19640 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19641 }, 19642 outputs: []outputInfo{ 19643 {1, 0}, 19644 {0, 1}, // R0 19645 }, 19646 }, 19647 }, 19648 { 19649 name: "LoweredAtomicExchange64", 19650 auxType: auxSymOff, 19651 argLen: 3, 19652 clobberFlags: true, 19653 faultOnNilArg0: true, 19654 asm: s390x.ACSG, 19655 reg: regInfo{ 19656 inputs: []inputInfo{ 19657 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19658 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19659 }, 19660 outputs: []outputInfo{ 19661 {1, 0}, 19662 {0, 1}, // R0 19663 }, 19664 }, 19665 }, 19666 { 19667 name: "FLOGR", 19668 argLen: 1, 19669 clobberFlags: true, 19670 asm: s390x.AFLOGR, 19671 reg: regInfo{ 19672 inputs: []inputInfo{ 19673 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19674 }, 19675 clobbers: 2, // R1 19676 outputs: []outputInfo{ 19677 {0, 1}, // R0 19678 }, 19679 }, 19680 }, 19681 { 19682 name: "STMG2", 19683 auxType: auxSymOff, 19684 argLen: 4, 19685 faultOnNilArg0: true, 19686 asm: s390x.ASTMG, 19687 reg: regInfo{ 19688 inputs: []inputInfo{ 19689 {1, 2}, // R1 19690 {2, 4}, // R2 19691 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19692 }, 19693 }, 19694 }, 19695 { 19696 name: "STMG3", 19697 auxType: auxSymOff, 19698 argLen: 5, 19699 faultOnNilArg0: true, 19700 asm: s390x.ASTMG, 19701 reg: regInfo{ 19702 inputs: []inputInfo{ 19703 {1, 2}, // R1 19704 {2, 4}, // R2 19705 {3, 8}, // R3 19706 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19707 }, 19708 }, 19709 }, 19710 { 19711 name: "STMG4", 19712 auxType: auxSymOff, 19713 argLen: 6, 19714 faultOnNilArg0: true, 19715 asm: s390x.ASTMG, 19716 reg: regInfo{ 19717 inputs: []inputInfo{ 19718 {1, 2}, // R1 19719 {2, 4}, // R2 19720 {3, 8}, // R3 19721 {4, 16}, // R4 19722 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19723 }, 19724 }, 19725 }, 19726 { 19727 name: "STM2", 19728 auxType: auxSymOff, 19729 argLen: 4, 19730 faultOnNilArg0: true, 19731 asm: s390x.ASTMY, 19732 reg: regInfo{ 19733 inputs: []inputInfo{ 19734 {1, 2}, // R1 19735 {2, 4}, // R2 19736 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19737 }, 19738 }, 19739 }, 19740 { 19741 name: "STM3", 19742 auxType: auxSymOff, 19743 argLen: 5, 19744 faultOnNilArg0: true, 19745 asm: s390x.ASTMY, 19746 reg: regInfo{ 19747 inputs: []inputInfo{ 19748 {1, 2}, // R1 19749 {2, 4}, // R2 19750 {3, 8}, // R3 19751 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19752 }, 19753 }, 19754 }, 19755 { 19756 name: "STM4", 19757 auxType: auxSymOff, 19758 argLen: 6, 19759 faultOnNilArg0: true, 19760 asm: s390x.ASTMY, 19761 reg: regInfo{ 19762 inputs: []inputInfo{ 19763 {1, 2}, // R1 19764 {2, 4}, // R2 19765 {3, 8}, // R3 19766 {4, 16}, // R4 19767 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19768 }, 19769 }, 19770 }, 19771 { 19772 name: "LoweredMove", 19773 auxType: auxInt64, 19774 argLen: 4, 19775 clobberFlags: true, 19776 faultOnNilArg0: true, 19777 faultOnNilArg1: true, 19778 reg: regInfo{ 19779 inputs: []inputInfo{ 19780 {0, 2}, // R1 19781 {1, 4}, // R2 19782 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19783 }, 19784 clobbers: 6, // R1 R2 19785 }, 19786 }, 19787 { 19788 name: "LoweredZero", 19789 auxType: auxInt64, 19790 argLen: 3, 19791 clobberFlags: true, 19792 faultOnNilArg0: true, 19793 reg: regInfo{ 19794 inputs: []inputInfo{ 19795 {0, 2}, // R1 19796 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19797 }, 19798 clobbers: 2, // R1 19799 }, 19800 }, 19801 19802 { 19803 name: "Add8", 19804 argLen: 2, 19805 commutative: true, 19806 generic: true, 19807 }, 19808 { 19809 name: "Add16", 19810 argLen: 2, 19811 commutative: true, 19812 generic: true, 19813 }, 19814 { 19815 name: "Add32", 19816 argLen: 2, 19817 commutative: true, 19818 generic: true, 19819 }, 19820 { 19821 name: "Add64", 19822 argLen: 2, 19823 commutative: true, 19824 generic: true, 19825 }, 19826 { 19827 name: "AddPtr", 19828 argLen: 2, 19829 generic: true, 19830 }, 19831 { 19832 name: "Add32F", 19833 argLen: 2, 19834 generic: true, 19835 }, 19836 { 19837 name: "Add64F", 19838 argLen: 2, 19839 generic: true, 19840 }, 19841 { 19842 name: "Sub8", 19843 argLen: 2, 19844 generic: true, 19845 }, 19846 { 19847 name: "Sub16", 19848 argLen: 2, 19849 generic: true, 19850 }, 19851 { 19852 name: "Sub32", 19853 argLen: 2, 19854 generic: true, 19855 }, 19856 { 19857 name: "Sub64", 19858 argLen: 2, 19859 generic: true, 19860 }, 19861 { 19862 name: "SubPtr", 19863 argLen: 2, 19864 generic: true, 19865 }, 19866 { 19867 name: "Sub32F", 19868 argLen: 2, 19869 generic: true, 19870 }, 19871 { 19872 name: "Sub64F", 19873 argLen: 2, 19874 generic: true, 19875 }, 19876 { 19877 name: "Mul8", 19878 argLen: 2, 19879 commutative: true, 19880 generic: true, 19881 }, 19882 { 19883 name: "Mul16", 19884 argLen: 2, 19885 commutative: true, 19886 generic: true, 19887 }, 19888 { 19889 name: "Mul32", 19890 argLen: 2, 19891 commutative: true, 19892 generic: true, 19893 }, 19894 { 19895 name: "Mul64", 19896 argLen: 2, 19897 commutative: true, 19898 generic: true, 19899 }, 19900 { 19901 name: "Mul32F", 19902 argLen: 2, 19903 generic: true, 19904 }, 19905 { 19906 name: "Mul64F", 19907 argLen: 2, 19908 generic: true, 19909 }, 19910 { 19911 name: "Div32F", 19912 argLen: 2, 19913 generic: true, 19914 }, 19915 { 19916 name: "Div64F", 19917 argLen: 2, 19918 generic: true, 19919 }, 19920 { 19921 name: "Hmul8", 19922 argLen: 2, 19923 generic: true, 19924 }, 19925 { 19926 name: "Hmul8u", 19927 argLen: 2, 19928 generic: true, 19929 }, 19930 { 19931 name: "Hmul16", 19932 argLen: 2, 19933 generic: true, 19934 }, 19935 { 19936 name: "Hmul16u", 19937 argLen: 2, 19938 generic: true, 19939 }, 19940 { 19941 name: "Hmul32", 19942 argLen: 2, 19943 generic: true, 19944 }, 19945 { 19946 name: "Hmul32u", 19947 argLen: 2, 19948 generic: true, 19949 }, 19950 { 19951 name: "Hmul64", 19952 argLen: 2, 19953 generic: true, 19954 }, 19955 { 19956 name: "Hmul64u", 19957 argLen: 2, 19958 generic: true, 19959 }, 19960 { 19961 name: "Mul32uhilo", 19962 argLen: 2, 19963 generic: true, 19964 }, 19965 { 19966 name: "Mul64uhilo", 19967 argLen: 2, 19968 generic: true, 19969 }, 19970 { 19971 name: "Avg64u", 19972 argLen: 2, 19973 generic: true, 19974 }, 19975 { 19976 name: "Div8", 19977 argLen: 2, 19978 generic: true, 19979 }, 19980 { 19981 name: "Div8u", 19982 argLen: 2, 19983 generic: true, 19984 }, 19985 { 19986 name: "Div16", 19987 argLen: 2, 19988 generic: true, 19989 }, 19990 { 19991 name: "Div16u", 19992 argLen: 2, 19993 generic: true, 19994 }, 19995 { 19996 name: "Div32", 19997 argLen: 2, 19998 generic: true, 19999 }, 20000 { 20001 name: "Div32u", 20002 argLen: 2, 20003 generic: true, 20004 }, 20005 { 20006 name: "Div64", 20007 argLen: 2, 20008 generic: true, 20009 }, 20010 { 20011 name: "Div64u", 20012 argLen: 2, 20013 generic: true, 20014 }, 20015 { 20016 name: "Div128u", 20017 argLen: 3, 20018 generic: true, 20019 }, 20020 { 20021 name: "Mod8", 20022 argLen: 2, 20023 generic: true, 20024 }, 20025 { 20026 name: "Mod8u", 20027 argLen: 2, 20028 generic: true, 20029 }, 20030 { 20031 name: "Mod16", 20032 argLen: 2, 20033 generic: true, 20034 }, 20035 { 20036 name: "Mod16u", 20037 argLen: 2, 20038 generic: true, 20039 }, 20040 { 20041 name: "Mod32", 20042 argLen: 2, 20043 generic: true, 20044 }, 20045 { 20046 name: "Mod32u", 20047 argLen: 2, 20048 generic: true, 20049 }, 20050 { 20051 name: "Mod64", 20052 argLen: 2, 20053 generic: true, 20054 }, 20055 { 20056 name: "Mod64u", 20057 argLen: 2, 20058 generic: true, 20059 }, 20060 { 20061 name: "And8", 20062 argLen: 2, 20063 commutative: true, 20064 generic: true, 20065 }, 20066 { 20067 name: "And16", 20068 argLen: 2, 20069 commutative: true, 20070 generic: true, 20071 }, 20072 { 20073 name: "And32", 20074 argLen: 2, 20075 commutative: true, 20076 generic: true, 20077 }, 20078 { 20079 name: "And64", 20080 argLen: 2, 20081 commutative: true, 20082 generic: true, 20083 }, 20084 { 20085 name: "Or8", 20086 argLen: 2, 20087 commutative: true, 20088 generic: true, 20089 }, 20090 { 20091 name: "Or16", 20092 argLen: 2, 20093 commutative: true, 20094 generic: true, 20095 }, 20096 { 20097 name: "Or32", 20098 argLen: 2, 20099 commutative: true, 20100 generic: true, 20101 }, 20102 { 20103 name: "Or64", 20104 argLen: 2, 20105 commutative: true, 20106 generic: true, 20107 }, 20108 { 20109 name: "Xor8", 20110 argLen: 2, 20111 commutative: true, 20112 generic: true, 20113 }, 20114 { 20115 name: "Xor16", 20116 argLen: 2, 20117 commutative: true, 20118 generic: true, 20119 }, 20120 { 20121 name: "Xor32", 20122 argLen: 2, 20123 commutative: true, 20124 generic: true, 20125 }, 20126 { 20127 name: "Xor64", 20128 argLen: 2, 20129 commutative: true, 20130 generic: true, 20131 }, 20132 { 20133 name: "Lsh8x8", 20134 argLen: 2, 20135 generic: true, 20136 }, 20137 { 20138 name: "Lsh8x16", 20139 argLen: 2, 20140 generic: true, 20141 }, 20142 { 20143 name: "Lsh8x32", 20144 argLen: 2, 20145 generic: true, 20146 }, 20147 { 20148 name: "Lsh8x64", 20149 argLen: 2, 20150 generic: true, 20151 }, 20152 { 20153 name: "Lsh16x8", 20154 argLen: 2, 20155 generic: true, 20156 }, 20157 { 20158 name: "Lsh16x16", 20159 argLen: 2, 20160 generic: true, 20161 }, 20162 { 20163 name: "Lsh16x32", 20164 argLen: 2, 20165 generic: true, 20166 }, 20167 { 20168 name: "Lsh16x64", 20169 argLen: 2, 20170 generic: true, 20171 }, 20172 { 20173 name: "Lsh32x8", 20174 argLen: 2, 20175 generic: true, 20176 }, 20177 { 20178 name: "Lsh32x16", 20179 argLen: 2, 20180 generic: true, 20181 }, 20182 { 20183 name: "Lsh32x32", 20184 argLen: 2, 20185 generic: true, 20186 }, 20187 { 20188 name: "Lsh32x64", 20189 argLen: 2, 20190 generic: true, 20191 }, 20192 { 20193 name: "Lsh64x8", 20194 argLen: 2, 20195 generic: true, 20196 }, 20197 { 20198 name: "Lsh64x16", 20199 argLen: 2, 20200 generic: true, 20201 }, 20202 { 20203 name: "Lsh64x32", 20204 argLen: 2, 20205 generic: true, 20206 }, 20207 { 20208 name: "Lsh64x64", 20209 argLen: 2, 20210 generic: true, 20211 }, 20212 { 20213 name: "Rsh8x8", 20214 argLen: 2, 20215 generic: true, 20216 }, 20217 { 20218 name: "Rsh8x16", 20219 argLen: 2, 20220 generic: true, 20221 }, 20222 { 20223 name: "Rsh8x32", 20224 argLen: 2, 20225 generic: true, 20226 }, 20227 { 20228 name: "Rsh8x64", 20229 argLen: 2, 20230 generic: true, 20231 }, 20232 { 20233 name: "Rsh16x8", 20234 argLen: 2, 20235 generic: true, 20236 }, 20237 { 20238 name: "Rsh16x16", 20239 argLen: 2, 20240 generic: true, 20241 }, 20242 { 20243 name: "Rsh16x32", 20244 argLen: 2, 20245 generic: true, 20246 }, 20247 { 20248 name: "Rsh16x64", 20249 argLen: 2, 20250 generic: true, 20251 }, 20252 { 20253 name: "Rsh32x8", 20254 argLen: 2, 20255 generic: true, 20256 }, 20257 { 20258 name: "Rsh32x16", 20259 argLen: 2, 20260 generic: true, 20261 }, 20262 { 20263 name: "Rsh32x32", 20264 argLen: 2, 20265 generic: true, 20266 }, 20267 { 20268 name: "Rsh32x64", 20269 argLen: 2, 20270 generic: true, 20271 }, 20272 { 20273 name: "Rsh64x8", 20274 argLen: 2, 20275 generic: true, 20276 }, 20277 { 20278 name: "Rsh64x16", 20279 argLen: 2, 20280 generic: true, 20281 }, 20282 { 20283 name: "Rsh64x32", 20284 argLen: 2, 20285 generic: true, 20286 }, 20287 { 20288 name: "Rsh64x64", 20289 argLen: 2, 20290 generic: true, 20291 }, 20292 { 20293 name: "Rsh8Ux8", 20294 argLen: 2, 20295 generic: true, 20296 }, 20297 { 20298 name: "Rsh8Ux16", 20299 argLen: 2, 20300 generic: true, 20301 }, 20302 { 20303 name: "Rsh8Ux32", 20304 argLen: 2, 20305 generic: true, 20306 }, 20307 { 20308 name: "Rsh8Ux64", 20309 argLen: 2, 20310 generic: true, 20311 }, 20312 { 20313 name: "Rsh16Ux8", 20314 argLen: 2, 20315 generic: true, 20316 }, 20317 { 20318 name: "Rsh16Ux16", 20319 argLen: 2, 20320 generic: true, 20321 }, 20322 { 20323 name: "Rsh16Ux32", 20324 argLen: 2, 20325 generic: true, 20326 }, 20327 { 20328 name: "Rsh16Ux64", 20329 argLen: 2, 20330 generic: true, 20331 }, 20332 { 20333 name: "Rsh32Ux8", 20334 argLen: 2, 20335 generic: true, 20336 }, 20337 { 20338 name: "Rsh32Ux16", 20339 argLen: 2, 20340 generic: true, 20341 }, 20342 { 20343 name: "Rsh32Ux32", 20344 argLen: 2, 20345 generic: true, 20346 }, 20347 { 20348 name: "Rsh32Ux64", 20349 argLen: 2, 20350 generic: true, 20351 }, 20352 { 20353 name: "Rsh64Ux8", 20354 argLen: 2, 20355 generic: true, 20356 }, 20357 { 20358 name: "Rsh64Ux16", 20359 argLen: 2, 20360 generic: true, 20361 }, 20362 { 20363 name: "Rsh64Ux32", 20364 argLen: 2, 20365 generic: true, 20366 }, 20367 { 20368 name: "Rsh64Ux64", 20369 argLen: 2, 20370 generic: true, 20371 }, 20372 { 20373 name: "Eq8", 20374 argLen: 2, 20375 commutative: true, 20376 generic: true, 20377 }, 20378 { 20379 name: "Eq16", 20380 argLen: 2, 20381 commutative: true, 20382 generic: true, 20383 }, 20384 { 20385 name: "Eq32", 20386 argLen: 2, 20387 commutative: true, 20388 generic: true, 20389 }, 20390 { 20391 name: "Eq64", 20392 argLen: 2, 20393 commutative: true, 20394 generic: true, 20395 }, 20396 { 20397 name: "EqPtr", 20398 argLen: 2, 20399 commutative: true, 20400 generic: true, 20401 }, 20402 { 20403 name: "EqInter", 20404 argLen: 2, 20405 generic: true, 20406 }, 20407 { 20408 name: "EqSlice", 20409 argLen: 2, 20410 generic: true, 20411 }, 20412 { 20413 name: "Eq32F", 20414 argLen: 2, 20415 generic: true, 20416 }, 20417 { 20418 name: "Eq64F", 20419 argLen: 2, 20420 generic: true, 20421 }, 20422 { 20423 name: "Neq8", 20424 argLen: 2, 20425 commutative: true, 20426 generic: true, 20427 }, 20428 { 20429 name: "Neq16", 20430 argLen: 2, 20431 commutative: true, 20432 generic: true, 20433 }, 20434 { 20435 name: "Neq32", 20436 argLen: 2, 20437 commutative: true, 20438 generic: true, 20439 }, 20440 { 20441 name: "Neq64", 20442 argLen: 2, 20443 commutative: true, 20444 generic: true, 20445 }, 20446 { 20447 name: "NeqPtr", 20448 argLen: 2, 20449 commutative: true, 20450 generic: true, 20451 }, 20452 { 20453 name: "NeqInter", 20454 argLen: 2, 20455 generic: true, 20456 }, 20457 { 20458 name: "NeqSlice", 20459 argLen: 2, 20460 generic: true, 20461 }, 20462 { 20463 name: "Neq32F", 20464 argLen: 2, 20465 generic: true, 20466 }, 20467 { 20468 name: "Neq64F", 20469 argLen: 2, 20470 generic: true, 20471 }, 20472 { 20473 name: "Less8", 20474 argLen: 2, 20475 generic: true, 20476 }, 20477 { 20478 name: "Less8U", 20479 argLen: 2, 20480 generic: true, 20481 }, 20482 { 20483 name: "Less16", 20484 argLen: 2, 20485 generic: true, 20486 }, 20487 { 20488 name: "Less16U", 20489 argLen: 2, 20490 generic: true, 20491 }, 20492 { 20493 name: "Less32", 20494 argLen: 2, 20495 generic: true, 20496 }, 20497 { 20498 name: "Less32U", 20499 argLen: 2, 20500 generic: true, 20501 }, 20502 { 20503 name: "Less64", 20504 argLen: 2, 20505 generic: true, 20506 }, 20507 { 20508 name: "Less64U", 20509 argLen: 2, 20510 generic: true, 20511 }, 20512 { 20513 name: "Less32F", 20514 argLen: 2, 20515 generic: true, 20516 }, 20517 { 20518 name: "Less64F", 20519 argLen: 2, 20520 generic: true, 20521 }, 20522 { 20523 name: "Leq8", 20524 argLen: 2, 20525 generic: true, 20526 }, 20527 { 20528 name: "Leq8U", 20529 argLen: 2, 20530 generic: true, 20531 }, 20532 { 20533 name: "Leq16", 20534 argLen: 2, 20535 generic: true, 20536 }, 20537 { 20538 name: "Leq16U", 20539 argLen: 2, 20540 generic: true, 20541 }, 20542 { 20543 name: "Leq32", 20544 argLen: 2, 20545 generic: true, 20546 }, 20547 { 20548 name: "Leq32U", 20549 argLen: 2, 20550 generic: true, 20551 }, 20552 { 20553 name: "Leq64", 20554 argLen: 2, 20555 generic: true, 20556 }, 20557 { 20558 name: "Leq64U", 20559 argLen: 2, 20560 generic: true, 20561 }, 20562 { 20563 name: "Leq32F", 20564 argLen: 2, 20565 generic: true, 20566 }, 20567 { 20568 name: "Leq64F", 20569 argLen: 2, 20570 generic: true, 20571 }, 20572 { 20573 name: "Greater8", 20574 argLen: 2, 20575 generic: true, 20576 }, 20577 { 20578 name: "Greater8U", 20579 argLen: 2, 20580 generic: true, 20581 }, 20582 { 20583 name: "Greater16", 20584 argLen: 2, 20585 generic: true, 20586 }, 20587 { 20588 name: "Greater16U", 20589 argLen: 2, 20590 generic: true, 20591 }, 20592 { 20593 name: "Greater32", 20594 argLen: 2, 20595 generic: true, 20596 }, 20597 { 20598 name: "Greater32U", 20599 argLen: 2, 20600 generic: true, 20601 }, 20602 { 20603 name: "Greater64", 20604 argLen: 2, 20605 generic: true, 20606 }, 20607 { 20608 name: "Greater64U", 20609 argLen: 2, 20610 generic: true, 20611 }, 20612 { 20613 name: "Greater32F", 20614 argLen: 2, 20615 generic: true, 20616 }, 20617 { 20618 name: "Greater64F", 20619 argLen: 2, 20620 generic: true, 20621 }, 20622 { 20623 name: "Geq8", 20624 argLen: 2, 20625 generic: true, 20626 }, 20627 { 20628 name: "Geq8U", 20629 argLen: 2, 20630 generic: true, 20631 }, 20632 { 20633 name: "Geq16", 20634 argLen: 2, 20635 generic: true, 20636 }, 20637 { 20638 name: "Geq16U", 20639 argLen: 2, 20640 generic: true, 20641 }, 20642 { 20643 name: "Geq32", 20644 argLen: 2, 20645 generic: true, 20646 }, 20647 { 20648 name: "Geq32U", 20649 argLen: 2, 20650 generic: true, 20651 }, 20652 { 20653 name: "Geq64", 20654 argLen: 2, 20655 generic: true, 20656 }, 20657 { 20658 name: "Geq64U", 20659 argLen: 2, 20660 generic: true, 20661 }, 20662 { 20663 name: "Geq32F", 20664 argLen: 2, 20665 generic: true, 20666 }, 20667 { 20668 name: "Geq64F", 20669 argLen: 2, 20670 generic: true, 20671 }, 20672 { 20673 name: "AndB", 20674 argLen: 2, 20675 generic: true, 20676 }, 20677 { 20678 name: "OrB", 20679 argLen: 2, 20680 generic: true, 20681 }, 20682 { 20683 name: "EqB", 20684 argLen: 2, 20685 generic: true, 20686 }, 20687 { 20688 name: "NeqB", 20689 argLen: 2, 20690 generic: true, 20691 }, 20692 { 20693 name: "Not", 20694 argLen: 1, 20695 generic: true, 20696 }, 20697 { 20698 name: "Neg8", 20699 argLen: 1, 20700 generic: true, 20701 }, 20702 { 20703 name: "Neg16", 20704 argLen: 1, 20705 generic: true, 20706 }, 20707 { 20708 name: "Neg32", 20709 argLen: 1, 20710 generic: true, 20711 }, 20712 { 20713 name: "Neg64", 20714 argLen: 1, 20715 generic: true, 20716 }, 20717 { 20718 name: "Neg32F", 20719 argLen: 1, 20720 generic: true, 20721 }, 20722 { 20723 name: "Neg64F", 20724 argLen: 1, 20725 generic: true, 20726 }, 20727 { 20728 name: "Com8", 20729 argLen: 1, 20730 generic: true, 20731 }, 20732 { 20733 name: "Com16", 20734 argLen: 1, 20735 generic: true, 20736 }, 20737 { 20738 name: "Com32", 20739 argLen: 1, 20740 generic: true, 20741 }, 20742 { 20743 name: "Com64", 20744 argLen: 1, 20745 generic: true, 20746 }, 20747 { 20748 name: "Ctz32", 20749 argLen: 1, 20750 generic: true, 20751 }, 20752 { 20753 name: "Ctz64", 20754 argLen: 1, 20755 generic: true, 20756 }, 20757 { 20758 name: "Bswap32", 20759 argLen: 1, 20760 generic: true, 20761 }, 20762 { 20763 name: "Bswap64", 20764 argLen: 1, 20765 generic: true, 20766 }, 20767 { 20768 name: "Sqrt", 20769 argLen: 1, 20770 generic: true, 20771 }, 20772 { 20773 name: "Phi", 20774 argLen: -1, 20775 generic: true, 20776 }, 20777 { 20778 name: "Copy", 20779 argLen: 1, 20780 generic: true, 20781 }, 20782 { 20783 name: "Convert", 20784 argLen: 2, 20785 generic: true, 20786 }, 20787 { 20788 name: "ConstBool", 20789 auxType: auxBool, 20790 argLen: 0, 20791 generic: true, 20792 }, 20793 { 20794 name: "ConstString", 20795 auxType: auxString, 20796 argLen: 0, 20797 generic: true, 20798 }, 20799 { 20800 name: "ConstNil", 20801 argLen: 0, 20802 generic: true, 20803 }, 20804 { 20805 name: "Const8", 20806 auxType: auxInt8, 20807 argLen: 0, 20808 generic: true, 20809 }, 20810 { 20811 name: "Const16", 20812 auxType: auxInt16, 20813 argLen: 0, 20814 generic: true, 20815 }, 20816 { 20817 name: "Const32", 20818 auxType: auxInt32, 20819 argLen: 0, 20820 generic: true, 20821 }, 20822 { 20823 name: "Const64", 20824 auxType: auxInt64, 20825 argLen: 0, 20826 generic: true, 20827 }, 20828 { 20829 name: "Const32F", 20830 auxType: auxFloat32, 20831 argLen: 0, 20832 generic: true, 20833 }, 20834 { 20835 name: "Const64F", 20836 auxType: auxFloat64, 20837 argLen: 0, 20838 generic: true, 20839 }, 20840 { 20841 name: "ConstInterface", 20842 argLen: 0, 20843 generic: true, 20844 }, 20845 { 20846 name: "ConstSlice", 20847 argLen: 0, 20848 generic: true, 20849 }, 20850 { 20851 name: "InitMem", 20852 argLen: 0, 20853 generic: true, 20854 }, 20855 { 20856 name: "Arg", 20857 auxType: auxSymOff, 20858 argLen: 0, 20859 generic: true, 20860 }, 20861 { 20862 name: "Addr", 20863 auxType: auxSym, 20864 argLen: 1, 20865 generic: true, 20866 }, 20867 { 20868 name: "SP", 20869 argLen: 0, 20870 generic: true, 20871 }, 20872 { 20873 name: "SB", 20874 argLen: 0, 20875 generic: true, 20876 }, 20877 { 20878 name: "Func", 20879 auxType: auxSym, 20880 argLen: 0, 20881 generic: true, 20882 }, 20883 { 20884 name: "Load", 20885 argLen: 2, 20886 generic: true, 20887 }, 20888 { 20889 name: "Store", 20890 auxType: auxInt64, 20891 argLen: 3, 20892 generic: true, 20893 }, 20894 { 20895 name: "Move", 20896 auxType: auxSizeAndAlign, 20897 argLen: 3, 20898 generic: true, 20899 }, 20900 { 20901 name: "Zero", 20902 auxType: auxSizeAndAlign, 20903 argLen: 2, 20904 generic: true, 20905 }, 20906 { 20907 name: "StoreWB", 20908 auxType: auxInt64, 20909 argLen: 3, 20910 generic: true, 20911 }, 20912 { 20913 name: "MoveWB", 20914 auxType: auxSymSizeAndAlign, 20915 argLen: 3, 20916 generic: true, 20917 }, 20918 { 20919 name: "MoveWBVolatile", 20920 auxType: auxSymSizeAndAlign, 20921 argLen: 3, 20922 generic: true, 20923 }, 20924 { 20925 name: "ZeroWB", 20926 auxType: auxSymSizeAndAlign, 20927 argLen: 2, 20928 generic: true, 20929 }, 20930 { 20931 name: "ClosureCall", 20932 auxType: auxInt64, 20933 argLen: 3, 20934 call: true, 20935 generic: true, 20936 }, 20937 { 20938 name: "StaticCall", 20939 auxType: auxSymOff, 20940 argLen: 1, 20941 call: true, 20942 generic: true, 20943 }, 20944 { 20945 name: "DeferCall", 20946 auxType: auxInt64, 20947 argLen: 1, 20948 call: true, 20949 generic: true, 20950 }, 20951 { 20952 name: "GoCall", 20953 auxType: auxInt64, 20954 argLen: 1, 20955 call: true, 20956 generic: true, 20957 }, 20958 { 20959 name: "InterCall", 20960 auxType: auxInt64, 20961 argLen: 2, 20962 call: true, 20963 generic: true, 20964 }, 20965 { 20966 name: "SignExt8to16", 20967 argLen: 1, 20968 generic: true, 20969 }, 20970 { 20971 name: "SignExt8to32", 20972 argLen: 1, 20973 generic: true, 20974 }, 20975 { 20976 name: "SignExt8to64", 20977 argLen: 1, 20978 generic: true, 20979 }, 20980 { 20981 name: "SignExt16to32", 20982 argLen: 1, 20983 generic: true, 20984 }, 20985 { 20986 name: "SignExt16to64", 20987 argLen: 1, 20988 generic: true, 20989 }, 20990 { 20991 name: "SignExt32to64", 20992 argLen: 1, 20993 generic: true, 20994 }, 20995 { 20996 name: "ZeroExt8to16", 20997 argLen: 1, 20998 generic: true, 20999 }, 21000 { 21001 name: "ZeroExt8to32", 21002 argLen: 1, 21003 generic: true, 21004 }, 21005 { 21006 name: "ZeroExt8to64", 21007 argLen: 1, 21008 generic: true, 21009 }, 21010 { 21011 name: "ZeroExt16to32", 21012 argLen: 1, 21013 generic: true, 21014 }, 21015 { 21016 name: "ZeroExt16to64", 21017 argLen: 1, 21018 generic: true, 21019 }, 21020 { 21021 name: "ZeroExt32to64", 21022 argLen: 1, 21023 generic: true, 21024 }, 21025 { 21026 name: "Trunc16to8", 21027 argLen: 1, 21028 generic: true, 21029 }, 21030 { 21031 name: "Trunc32to8", 21032 argLen: 1, 21033 generic: true, 21034 }, 21035 { 21036 name: "Trunc32to16", 21037 argLen: 1, 21038 generic: true, 21039 }, 21040 { 21041 name: "Trunc64to8", 21042 argLen: 1, 21043 generic: true, 21044 }, 21045 { 21046 name: "Trunc64to16", 21047 argLen: 1, 21048 generic: true, 21049 }, 21050 { 21051 name: "Trunc64to32", 21052 argLen: 1, 21053 generic: true, 21054 }, 21055 { 21056 name: "Cvt32to32F", 21057 argLen: 1, 21058 generic: true, 21059 }, 21060 { 21061 name: "Cvt32to64F", 21062 argLen: 1, 21063 generic: true, 21064 }, 21065 { 21066 name: "Cvt64to32F", 21067 argLen: 1, 21068 generic: true, 21069 }, 21070 { 21071 name: "Cvt64to64F", 21072 argLen: 1, 21073 generic: true, 21074 }, 21075 { 21076 name: "Cvt32Fto32", 21077 argLen: 1, 21078 generic: true, 21079 }, 21080 { 21081 name: "Cvt32Fto64", 21082 argLen: 1, 21083 generic: true, 21084 }, 21085 { 21086 name: "Cvt64Fto32", 21087 argLen: 1, 21088 generic: true, 21089 }, 21090 { 21091 name: "Cvt64Fto64", 21092 argLen: 1, 21093 generic: true, 21094 }, 21095 { 21096 name: "Cvt32Fto64F", 21097 argLen: 1, 21098 generic: true, 21099 }, 21100 { 21101 name: "Cvt64Fto32F", 21102 argLen: 1, 21103 generic: true, 21104 }, 21105 { 21106 name: "IsNonNil", 21107 argLen: 1, 21108 generic: true, 21109 }, 21110 { 21111 name: "IsInBounds", 21112 argLen: 2, 21113 generic: true, 21114 }, 21115 { 21116 name: "IsSliceInBounds", 21117 argLen: 2, 21118 generic: true, 21119 }, 21120 { 21121 name: "NilCheck", 21122 argLen: 2, 21123 generic: true, 21124 }, 21125 { 21126 name: "GetG", 21127 argLen: 1, 21128 generic: true, 21129 }, 21130 { 21131 name: "GetClosurePtr", 21132 argLen: 0, 21133 generic: true, 21134 }, 21135 { 21136 name: "PtrIndex", 21137 argLen: 2, 21138 generic: true, 21139 }, 21140 { 21141 name: "OffPtr", 21142 auxType: auxInt64, 21143 argLen: 1, 21144 generic: true, 21145 }, 21146 { 21147 name: "SliceMake", 21148 argLen: 3, 21149 generic: true, 21150 }, 21151 { 21152 name: "SlicePtr", 21153 argLen: 1, 21154 generic: true, 21155 }, 21156 { 21157 name: "SliceLen", 21158 argLen: 1, 21159 generic: true, 21160 }, 21161 { 21162 name: "SliceCap", 21163 argLen: 1, 21164 generic: true, 21165 }, 21166 { 21167 name: "ComplexMake", 21168 argLen: 2, 21169 generic: true, 21170 }, 21171 { 21172 name: "ComplexReal", 21173 argLen: 1, 21174 generic: true, 21175 }, 21176 { 21177 name: "ComplexImag", 21178 argLen: 1, 21179 generic: true, 21180 }, 21181 { 21182 name: "StringMake", 21183 argLen: 2, 21184 generic: true, 21185 }, 21186 { 21187 name: "StringPtr", 21188 argLen: 1, 21189 generic: true, 21190 }, 21191 { 21192 name: "StringLen", 21193 argLen: 1, 21194 generic: true, 21195 }, 21196 { 21197 name: "IMake", 21198 argLen: 2, 21199 generic: true, 21200 }, 21201 { 21202 name: "ITab", 21203 argLen: 1, 21204 generic: true, 21205 }, 21206 { 21207 name: "IData", 21208 argLen: 1, 21209 generic: true, 21210 }, 21211 { 21212 name: "StructMake0", 21213 argLen: 0, 21214 generic: true, 21215 }, 21216 { 21217 name: "StructMake1", 21218 argLen: 1, 21219 generic: true, 21220 }, 21221 { 21222 name: "StructMake2", 21223 argLen: 2, 21224 generic: true, 21225 }, 21226 { 21227 name: "StructMake3", 21228 argLen: 3, 21229 generic: true, 21230 }, 21231 { 21232 name: "StructMake4", 21233 argLen: 4, 21234 generic: true, 21235 }, 21236 { 21237 name: "StructSelect", 21238 auxType: auxInt64, 21239 argLen: 1, 21240 generic: true, 21241 }, 21242 { 21243 name: "ArrayMake0", 21244 argLen: 0, 21245 generic: true, 21246 }, 21247 { 21248 name: "ArrayMake1", 21249 argLen: 1, 21250 generic: true, 21251 }, 21252 { 21253 name: "ArraySelect", 21254 auxType: auxInt64, 21255 argLen: 1, 21256 generic: true, 21257 }, 21258 { 21259 name: "StoreReg", 21260 argLen: 1, 21261 generic: true, 21262 }, 21263 { 21264 name: "LoadReg", 21265 argLen: 1, 21266 generic: true, 21267 }, 21268 { 21269 name: "FwdRef", 21270 auxType: auxSym, 21271 argLen: 0, 21272 generic: true, 21273 }, 21274 { 21275 name: "Unknown", 21276 argLen: 0, 21277 generic: true, 21278 }, 21279 { 21280 name: "VarDef", 21281 auxType: auxSym, 21282 argLen: 1, 21283 generic: true, 21284 }, 21285 { 21286 name: "VarKill", 21287 auxType: auxSym, 21288 argLen: 1, 21289 generic: true, 21290 }, 21291 { 21292 name: "VarLive", 21293 auxType: auxSym, 21294 argLen: 1, 21295 generic: true, 21296 }, 21297 { 21298 name: "KeepAlive", 21299 argLen: 2, 21300 generic: true, 21301 }, 21302 { 21303 name: "Int64Make", 21304 argLen: 2, 21305 generic: true, 21306 }, 21307 { 21308 name: "Int64Hi", 21309 argLen: 1, 21310 generic: true, 21311 }, 21312 { 21313 name: "Int64Lo", 21314 argLen: 1, 21315 generic: true, 21316 }, 21317 { 21318 name: "Add32carry", 21319 argLen: 2, 21320 commutative: true, 21321 generic: true, 21322 }, 21323 { 21324 name: "Add32withcarry", 21325 argLen: 3, 21326 commutative: true, 21327 generic: true, 21328 }, 21329 { 21330 name: "Sub32carry", 21331 argLen: 2, 21332 generic: true, 21333 }, 21334 { 21335 name: "Sub32withcarry", 21336 argLen: 3, 21337 generic: true, 21338 }, 21339 { 21340 name: "Signmask", 21341 argLen: 1, 21342 generic: true, 21343 }, 21344 { 21345 name: "Zeromask", 21346 argLen: 1, 21347 generic: true, 21348 }, 21349 { 21350 name: "Slicemask", 21351 argLen: 1, 21352 generic: true, 21353 }, 21354 { 21355 name: "Cvt32Uto32F", 21356 argLen: 1, 21357 generic: true, 21358 }, 21359 { 21360 name: "Cvt32Uto64F", 21361 argLen: 1, 21362 generic: true, 21363 }, 21364 { 21365 name: "Cvt32Fto32U", 21366 argLen: 1, 21367 generic: true, 21368 }, 21369 { 21370 name: "Cvt64Fto32U", 21371 argLen: 1, 21372 generic: true, 21373 }, 21374 { 21375 name: "Cvt64Uto32F", 21376 argLen: 1, 21377 generic: true, 21378 }, 21379 { 21380 name: "Cvt64Uto64F", 21381 argLen: 1, 21382 generic: true, 21383 }, 21384 { 21385 name: "Cvt32Fto64U", 21386 argLen: 1, 21387 generic: true, 21388 }, 21389 { 21390 name: "Cvt64Fto64U", 21391 argLen: 1, 21392 generic: true, 21393 }, 21394 { 21395 name: "Select0", 21396 argLen: 1, 21397 generic: true, 21398 }, 21399 { 21400 name: "Select1", 21401 argLen: 1, 21402 generic: true, 21403 }, 21404 { 21405 name: "AtomicLoad32", 21406 argLen: 2, 21407 generic: true, 21408 }, 21409 { 21410 name: "AtomicLoad64", 21411 argLen: 2, 21412 generic: true, 21413 }, 21414 { 21415 name: "AtomicLoadPtr", 21416 argLen: 2, 21417 generic: true, 21418 }, 21419 { 21420 name: "AtomicStore32", 21421 argLen: 3, 21422 generic: true, 21423 }, 21424 { 21425 name: "AtomicStore64", 21426 argLen: 3, 21427 generic: true, 21428 }, 21429 { 21430 name: "AtomicStorePtrNoWB", 21431 argLen: 3, 21432 generic: true, 21433 }, 21434 { 21435 name: "AtomicExchange32", 21436 argLen: 3, 21437 generic: true, 21438 }, 21439 { 21440 name: "AtomicExchange64", 21441 argLen: 3, 21442 generic: true, 21443 }, 21444 { 21445 name: "AtomicAdd32", 21446 argLen: 3, 21447 generic: true, 21448 }, 21449 { 21450 name: "AtomicAdd64", 21451 argLen: 3, 21452 generic: true, 21453 }, 21454 { 21455 name: "AtomicCompareAndSwap32", 21456 argLen: 4, 21457 generic: true, 21458 }, 21459 { 21460 name: "AtomicCompareAndSwap64", 21461 argLen: 4, 21462 generic: true, 21463 }, 21464 { 21465 name: "AtomicAnd8", 21466 argLen: 3, 21467 generic: true, 21468 }, 21469 { 21470 name: "AtomicOr8", 21471 argLen: 3, 21472 generic: true, 21473 }, 21474 } 21475 21476 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 21477 func (o Op) String() string { return opcodeTable[o].name } 21478 func (o Op) UsesScratch() bool { return opcodeTable[o].usesScratch } 21479 21480 var registers386 = [...]Register{ 21481 {0, x86.REG_AX, "AX"}, 21482 {1, x86.REG_CX, "CX"}, 21483 {2, x86.REG_DX, "DX"}, 21484 {3, x86.REG_BX, "BX"}, 21485 {4, x86.REGSP, "SP"}, 21486 {5, x86.REG_BP, "BP"}, 21487 {6, x86.REG_SI, "SI"}, 21488 {7, x86.REG_DI, "DI"}, 21489 {8, x86.REG_X0, "X0"}, 21490 {9, x86.REG_X1, "X1"}, 21491 {10, x86.REG_X2, "X2"}, 21492 {11, x86.REG_X3, "X3"}, 21493 {12, x86.REG_X4, "X4"}, 21494 {13, x86.REG_X5, "X5"}, 21495 {14, x86.REG_X6, "X6"}, 21496 {15, x86.REG_X7, "X7"}, 21497 {16, 0, "SB"}, 21498 } 21499 var gpRegMask386 = regMask(239) 21500 var fpRegMask386 = regMask(65280) 21501 var specialRegMask386 = regMask(0) 21502 var framepointerReg386 = int8(5) 21503 var linkReg386 = int8(-1) 21504 var registersAMD64 = [...]Register{ 21505 {0, x86.REG_AX, "AX"}, 21506 {1, x86.REG_CX, "CX"}, 21507 {2, x86.REG_DX, "DX"}, 21508 {3, x86.REG_BX, "BX"}, 21509 {4, x86.REGSP, "SP"}, 21510 {5, x86.REG_BP, "BP"}, 21511 {6, x86.REG_SI, "SI"}, 21512 {7, x86.REG_DI, "DI"}, 21513 {8, x86.REG_R8, "R8"}, 21514 {9, x86.REG_R9, "R9"}, 21515 {10, x86.REG_R10, "R10"}, 21516 {11, x86.REG_R11, "R11"}, 21517 {12, x86.REG_R12, "R12"}, 21518 {13, x86.REG_R13, "R13"}, 21519 {14, x86.REG_R14, "R14"}, 21520 {15, x86.REG_R15, "R15"}, 21521 {16, x86.REG_X0, "X0"}, 21522 {17, x86.REG_X1, "X1"}, 21523 {18, x86.REG_X2, "X2"}, 21524 {19, x86.REG_X3, "X3"}, 21525 {20, x86.REG_X4, "X4"}, 21526 {21, x86.REG_X5, "X5"}, 21527 {22, x86.REG_X6, "X6"}, 21528 {23, x86.REG_X7, "X7"}, 21529 {24, x86.REG_X8, "X8"}, 21530 {25, x86.REG_X9, "X9"}, 21531 {26, x86.REG_X10, "X10"}, 21532 {27, x86.REG_X11, "X11"}, 21533 {28, x86.REG_X12, "X12"}, 21534 {29, x86.REG_X13, "X13"}, 21535 {30, x86.REG_X14, "X14"}, 21536 {31, x86.REG_X15, "X15"}, 21537 {32, 0, "SB"}, 21538 } 21539 var gpRegMaskAMD64 = regMask(65519) 21540 var fpRegMaskAMD64 = regMask(4294901760) 21541 var specialRegMaskAMD64 = regMask(0) 21542 var framepointerRegAMD64 = int8(5) 21543 var linkRegAMD64 = int8(-1) 21544 var registersARM = [...]Register{ 21545 {0, arm.REG_R0, "R0"}, 21546 {1, arm.REG_R1, "R1"}, 21547 {2, arm.REG_R2, "R2"}, 21548 {3, arm.REG_R3, "R3"}, 21549 {4, arm.REG_R4, "R4"}, 21550 {5, arm.REG_R5, "R5"}, 21551 {6, arm.REG_R6, "R6"}, 21552 {7, arm.REG_R7, "R7"}, 21553 {8, arm.REG_R8, "R8"}, 21554 {9, arm.REG_R9, "R9"}, 21555 {10, arm.REGG, "g"}, 21556 {11, arm.REG_R11, "R11"}, 21557 {12, arm.REG_R12, "R12"}, 21558 {13, arm.REGSP, "SP"}, 21559 {14, arm.REG_R14, "R14"}, 21560 {15, arm.REG_R15, "R15"}, 21561 {16, arm.REG_F0, "F0"}, 21562 {17, arm.REG_F1, "F1"}, 21563 {18, arm.REG_F2, "F2"}, 21564 {19, arm.REG_F3, "F3"}, 21565 {20, arm.REG_F4, "F4"}, 21566 {21, arm.REG_F5, "F5"}, 21567 {22, arm.REG_F6, "F6"}, 21568 {23, arm.REG_F7, "F7"}, 21569 {24, arm.REG_F8, "F8"}, 21570 {25, arm.REG_F9, "F9"}, 21571 {26, arm.REG_F10, "F10"}, 21572 {27, arm.REG_F11, "F11"}, 21573 {28, arm.REG_F12, "F12"}, 21574 {29, arm.REG_F13, "F13"}, 21575 {30, arm.REG_F14, "F14"}, 21576 {31, arm.REG_F15, "F15"}, 21577 {32, 0, "SB"}, 21578 } 21579 var gpRegMaskARM = regMask(21503) 21580 var fpRegMaskARM = regMask(4294901760) 21581 var specialRegMaskARM = regMask(0) 21582 var framepointerRegARM = int8(-1) 21583 var linkRegARM = int8(14) 21584 var registersARM64 = [...]Register{ 21585 {0, arm64.REG_R0, "R0"}, 21586 {1, arm64.REG_R1, "R1"}, 21587 {2, arm64.REG_R2, "R2"}, 21588 {3, arm64.REG_R3, "R3"}, 21589 {4, arm64.REG_R4, "R4"}, 21590 {5, arm64.REG_R5, "R5"}, 21591 {6, arm64.REG_R6, "R6"}, 21592 {7, arm64.REG_R7, "R7"}, 21593 {8, arm64.REG_R8, "R8"}, 21594 {9, arm64.REG_R9, "R9"}, 21595 {10, arm64.REG_R10, "R10"}, 21596 {11, arm64.REG_R11, "R11"}, 21597 {12, arm64.REG_R12, "R12"}, 21598 {13, arm64.REG_R13, "R13"}, 21599 {14, arm64.REG_R14, "R14"}, 21600 {15, arm64.REG_R15, "R15"}, 21601 {16, arm64.REG_R16, "R16"}, 21602 {17, arm64.REG_R17, "R17"}, 21603 {18, arm64.REG_R18, "R18"}, 21604 {19, arm64.REG_R19, "R19"}, 21605 {20, arm64.REG_R20, "R20"}, 21606 {21, arm64.REG_R21, "R21"}, 21607 {22, arm64.REG_R22, "R22"}, 21608 {23, arm64.REG_R23, "R23"}, 21609 {24, arm64.REG_R24, "R24"}, 21610 {25, arm64.REG_R25, "R25"}, 21611 {26, arm64.REG_R26, "R26"}, 21612 {27, arm64.REGG, "g"}, 21613 {28, arm64.REG_R29, "R29"}, 21614 {29, arm64.REG_R30, "R30"}, 21615 {30, arm64.REGSP, "SP"}, 21616 {31, arm64.REG_F0, "F0"}, 21617 {32, arm64.REG_F1, "F1"}, 21618 {33, arm64.REG_F2, "F2"}, 21619 {34, arm64.REG_F3, "F3"}, 21620 {35, arm64.REG_F4, "F4"}, 21621 {36, arm64.REG_F5, "F5"}, 21622 {37, arm64.REG_F6, "F6"}, 21623 {38, arm64.REG_F7, "F7"}, 21624 {39, arm64.REG_F8, "F8"}, 21625 {40, arm64.REG_F9, "F9"}, 21626 {41, arm64.REG_F10, "F10"}, 21627 {42, arm64.REG_F11, "F11"}, 21628 {43, arm64.REG_F12, "F12"}, 21629 {44, arm64.REG_F13, "F13"}, 21630 {45, arm64.REG_F14, "F14"}, 21631 {46, arm64.REG_F15, "F15"}, 21632 {47, arm64.REG_F16, "F16"}, 21633 {48, arm64.REG_F17, "F17"}, 21634 {49, arm64.REG_F18, "F18"}, 21635 {50, arm64.REG_F19, "F19"}, 21636 {51, arm64.REG_F20, "F20"}, 21637 {52, arm64.REG_F21, "F21"}, 21638 {53, arm64.REG_F22, "F22"}, 21639 {54, arm64.REG_F23, "F23"}, 21640 {55, arm64.REG_F24, "F24"}, 21641 {56, arm64.REG_F25, "F25"}, 21642 {57, arm64.REG_F26, "F26"}, 21643 {58, arm64.REG_F27, "F27"}, 21644 {59, arm64.REG_F28, "F28"}, 21645 {60, arm64.REG_F29, "F29"}, 21646 {61, arm64.REG_F30, "F30"}, 21647 {62, arm64.REG_F31, "F31"}, 21648 {63, 0, "SB"}, 21649 } 21650 var gpRegMaskARM64 = regMask(670826495) 21651 var fpRegMaskARM64 = regMask(9223372034707292160) 21652 var specialRegMaskARM64 = regMask(0) 21653 var framepointerRegARM64 = int8(-1) 21654 var linkRegARM64 = int8(29) 21655 var registersMIPS = [...]Register{ 21656 {0, mips.REG_R0, "R0"}, 21657 {1, mips.REG_R1, "R1"}, 21658 {2, mips.REG_R2, "R2"}, 21659 {3, mips.REG_R3, "R3"}, 21660 {4, mips.REG_R4, "R4"}, 21661 {5, mips.REG_R5, "R5"}, 21662 {6, mips.REG_R6, "R6"}, 21663 {7, mips.REG_R7, "R7"}, 21664 {8, mips.REG_R8, "R8"}, 21665 {9, mips.REG_R9, "R9"}, 21666 {10, mips.REG_R10, "R10"}, 21667 {11, mips.REG_R11, "R11"}, 21668 {12, mips.REG_R12, "R12"}, 21669 {13, mips.REG_R13, "R13"}, 21670 {14, mips.REG_R14, "R14"}, 21671 {15, mips.REG_R15, "R15"}, 21672 {16, mips.REG_R16, "R16"}, 21673 {17, mips.REG_R17, "R17"}, 21674 {18, mips.REG_R18, "R18"}, 21675 {19, mips.REG_R19, "R19"}, 21676 {20, mips.REG_R20, "R20"}, 21677 {21, mips.REG_R21, "R21"}, 21678 {22, mips.REG_R22, "R22"}, 21679 {23, mips.REG_R24, "R24"}, 21680 {24, mips.REG_R25, "R25"}, 21681 {25, mips.REG_R28, "R28"}, 21682 {26, mips.REGSP, "SP"}, 21683 {27, mips.REGG, "g"}, 21684 {28, mips.REG_R31, "R31"}, 21685 {29, mips.REG_F0, "F0"}, 21686 {30, mips.REG_F2, "F2"}, 21687 {31, mips.REG_F4, "F4"}, 21688 {32, mips.REG_F6, "F6"}, 21689 {33, mips.REG_F8, "F8"}, 21690 {34, mips.REG_F10, "F10"}, 21691 {35, mips.REG_F12, "F12"}, 21692 {36, mips.REG_F14, "F14"}, 21693 {37, mips.REG_F16, "F16"}, 21694 {38, mips.REG_F18, "F18"}, 21695 {39, mips.REG_F20, "F20"}, 21696 {40, mips.REG_F22, "F22"}, 21697 {41, mips.REG_F24, "F24"}, 21698 {42, mips.REG_F26, "F26"}, 21699 {43, mips.REG_F28, "F28"}, 21700 {44, mips.REG_F30, "F30"}, 21701 {45, mips.REG_HI, "HI"}, 21702 {46, mips.REG_LO, "LO"}, 21703 {47, 0, "SB"}, 21704 } 21705 var gpRegMaskMIPS = regMask(335544318) 21706 var fpRegMaskMIPS = regMask(35183835217920) 21707 var specialRegMaskMIPS = regMask(105553116266496) 21708 var framepointerRegMIPS = int8(-1) 21709 var linkRegMIPS = int8(28) 21710 var registersMIPS64 = [...]Register{ 21711 {0, mips.REG_R0, "R0"}, 21712 {1, mips.REG_R1, "R1"}, 21713 {2, mips.REG_R2, "R2"}, 21714 {3, mips.REG_R3, "R3"}, 21715 {4, mips.REG_R4, "R4"}, 21716 {5, mips.REG_R5, "R5"}, 21717 {6, mips.REG_R6, "R6"}, 21718 {7, mips.REG_R7, "R7"}, 21719 {8, mips.REG_R8, "R8"}, 21720 {9, mips.REG_R9, "R9"}, 21721 {10, mips.REG_R10, "R10"}, 21722 {11, mips.REG_R11, "R11"}, 21723 {12, mips.REG_R12, "R12"}, 21724 {13, mips.REG_R13, "R13"}, 21725 {14, mips.REG_R14, "R14"}, 21726 {15, mips.REG_R15, "R15"}, 21727 {16, mips.REG_R16, "R16"}, 21728 {17, mips.REG_R17, "R17"}, 21729 {18, mips.REG_R18, "R18"}, 21730 {19, mips.REG_R19, "R19"}, 21731 {20, mips.REG_R20, "R20"}, 21732 {21, mips.REG_R21, "R21"}, 21733 {22, mips.REG_R22, "R22"}, 21734 {23, mips.REG_R24, "R24"}, 21735 {24, mips.REG_R25, "R25"}, 21736 {25, mips.REGSP, "SP"}, 21737 {26, mips.REGG, "g"}, 21738 {27, mips.REG_R31, "R31"}, 21739 {28, mips.REG_F0, "F0"}, 21740 {29, mips.REG_F1, "F1"}, 21741 {30, mips.REG_F2, "F2"}, 21742 {31, mips.REG_F3, "F3"}, 21743 {32, mips.REG_F4, "F4"}, 21744 {33, mips.REG_F5, "F5"}, 21745 {34, mips.REG_F6, "F6"}, 21746 {35, mips.REG_F7, "F7"}, 21747 {36, mips.REG_F8, "F8"}, 21748 {37, mips.REG_F9, "F9"}, 21749 {38, mips.REG_F10, "F10"}, 21750 {39, mips.REG_F11, "F11"}, 21751 {40, mips.REG_F12, "F12"}, 21752 {41, mips.REG_F13, "F13"}, 21753 {42, mips.REG_F14, "F14"}, 21754 {43, mips.REG_F15, "F15"}, 21755 {44, mips.REG_F16, "F16"}, 21756 {45, mips.REG_F17, "F17"}, 21757 {46, mips.REG_F18, "F18"}, 21758 {47, mips.REG_F19, "F19"}, 21759 {48, mips.REG_F20, "F20"}, 21760 {49, mips.REG_F21, "F21"}, 21761 {50, mips.REG_F22, "F22"}, 21762 {51, mips.REG_F23, "F23"}, 21763 {52, mips.REG_F24, "F24"}, 21764 {53, mips.REG_F25, "F25"}, 21765 {54, mips.REG_F26, "F26"}, 21766 {55, mips.REG_F27, "F27"}, 21767 {56, mips.REG_F28, "F28"}, 21768 {57, mips.REG_F29, "F29"}, 21769 {58, mips.REG_F30, "F30"}, 21770 {59, mips.REG_F31, "F31"}, 21771 {60, mips.REG_HI, "HI"}, 21772 {61, mips.REG_LO, "LO"}, 21773 {62, 0, "SB"}, 21774 } 21775 var gpRegMaskMIPS64 = regMask(167772158) 21776 var fpRegMaskMIPS64 = regMask(1152921504338411520) 21777 var specialRegMaskMIPS64 = regMask(3458764513820540928) 21778 var framepointerRegMIPS64 = int8(-1) 21779 var linkRegMIPS64 = int8(27) 21780 var registersPPC64 = [...]Register{ 21781 {0, ppc64.REG_R0, "R0"}, 21782 {1, ppc64.REGSP, "SP"}, 21783 {2, 0, "SB"}, 21784 {3, ppc64.REG_R3, "R3"}, 21785 {4, ppc64.REG_R4, "R4"}, 21786 {5, ppc64.REG_R5, "R5"}, 21787 {6, ppc64.REG_R6, "R6"}, 21788 {7, ppc64.REG_R7, "R7"}, 21789 {8, ppc64.REG_R8, "R8"}, 21790 {9, ppc64.REG_R9, "R9"}, 21791 {10, ppc64.REG_R10, "R10"}, 21792 {11, ppc64.REG_R11, "R11"}, 21793 {12, ppc64.REG_R12, "R12"}, 21794 {13, ppc64.REG_R13, "R13"}, 21795 {14, ppc64.REG_R14, "R14"}, 21796 {15, ppc64.REG_R15, "R15"}, 21797 {16, ppc64.REG_R16, "R16"}, 21798 {17, ppc64.REG_R17, "R17"}, 21799 {18, ppc64.REG_R18, "R18"}, 21800 {19, ppc64.REG_R19, "R19"}, 21801 {20, ppc64.REG_R20, "R20"}, 21802 {21, ppc64.REG_R21, "R21"}, 21803 {22, ppc64.REG_R22, "R22"}, 21804 {23, ppc64.REG_R23, "R23"}, 21805 {24, ppc64.REG_R24, "R24"}, 21806 {25, ppc64.REG_R25, "R25"}, 21807 {26, ppc64.REG_R26, "R26"}, 21808 {27, ppc64.REG_R27, "R27"}, 21809 {28, ppc64.REG_R28, "R28"}, 21810 {29, ppc64.REG_R29, "R29"}, 21811 {30, ppc64.REGG, "g"}, 21812 {31, ppc64.REG_R31, "R31"}, 21813 {32, ppc64.REG_F0, "F0"}, 21814 {33, ppc64.REG_F1, "F1"}, 21815 {34, ppc64.REG_F2, "F2"}, 21816 {35, ppc64.REG_F3, "F3"}, 21817 {36, ppc64.REG_F4, "F4"}, 21818 {37, ppc64.REG_F5, "F5"}, 21819 {38, ppc64.REG_F6, "F6"}, 21820 {39, ppc64.REG_F7, "F7"}, 21821 {40, ppc64.REG_F8, "F8"}, 21822 {41, ppc64.REG_F9, "F9"}, 21823 {42, ppc64.REG_F10, "F10"}, 21824 {43, ppc64.REG_F11, "F11"}, 21825 {44, ppc64.REG_F12, "F12"}, 21826 {45, ppc64.REG_F13, "F13"}, 21827 {46, ppc64.REG_F14, "F14"}, 21828 {47, ppc64.REG_F15, "F15"}, 21829 {48, ppc64.REG_F16, "F16"}, 21830 {49, ppc64.REG_F17, "F17"}, 21831 {50, ppc64.REG_F18, "F18"}, 21832 {51, ppc64.REG_F19, "F19"}, 21833 {52, ppc64.REG_F20, "F20"}, 21834 {53, ppc64.REG_F21, "F21"}, 21835 {54, ppc64.REG_F22, "F22"}, 21836 {55, ppc64.REG_F23, "F23"}, 21837 {56, ppc64.REG_F24, "F24"}, 21838 {57, ppc64.REG_F25, "F25"}, 21839 {58, ppc64.REG_F26, "F26"}, 21840 {59, ppc64.REG_F27, "F27"}, 21841 {60, ppc64.REG_F28, "F28"}, 21842 {61, ppc64.REG_F29, "F29"}, 21843 {62, ppc64.REG_F30, "F30"}, 21844 {63, ppc64.REG_F31, "F31"}, 21845 } 21846 var gpRegMaskPPC64 = regMask(1073733624) 21847 var fpRegMaskPPC64 = regMask(576460743713488896) 21848 var specialRegMaskPPC64 = regMask(0) 21849 var framepointerRegPPC64 = int8(1) 21850 var linkRegPPC64 = int8(-1) 21851 var registersS390X = [...]Register{ 21852 {0, s390x.REG_R0, "R0"}, 21853 {1, s390x.REG_R1, "R1"}, 21854 {2, s390x.REG_R2, "R2"}, 21855 {3, s390x.REG_R3, "R3"}, 21856 {4, s390x.REG_R4, "R4"}, 21857 {5, s390x.REG_R5, "R5"}, 21858 {6, s390x.REG_R6, "R6"}, 21859 {7, s390x.REG_R7, "R7"}, 21860 {8, s390x.REG_R8, "R8"}, 21861 {9, s390x.REG_R9, "R9"}, 21862 {10, s390x.REG_R10, "R10"}, 21863 {11, s390x.REG_R11, "R11"}, 21864 {12, s390x.REG_R12, "R12"}, 21865 {13, s390x.REGG, "g"}, 21866 {14, s390x.REG_R14, "R14"}, 21867 {15, s390x.REGSP, "SP"}, 21868 {16, s390x.REG_F0, "F0"}, 21869 {17, s390x.REG_F1, "F1"}, 21870 {18, s390x.REG_F2, "F2"}, 21871 {19, s390x.REG_F3, "F3"}, 21872 {20, s390x.REG_F4, "F4"}, 21873 {21, s390x.REG_F5, "F5"}, 21874 {22, s390x.REG_F6, "F6"}, 21875 {23, s390x.REG_F7, "F7"}, 21876 {24, s390x.REG_F8, "F8"}, 21877 {25, s390x.REG_F9, "F9"}, 21878 {26, s390x.REG_F10, "F10"}, 21879 {27, s390x.REG_F11, "F11"}, 21880 {28, s390x.REG_F12, "F12"}, 21881 {29, s390x.REG_F13, "F13"}, 21882 {30, s390x.REG_F14, "F14"}, 21883 {31, s390x.REG_F15, "F15"}, 21884 {32, 0, "SB"}, 21885 } 21886 var gpRegMaskS390X = regMask(21503) 21887 var fpRegMaskS390X = regMask(4294901760) 21888 var specialRegMaskS390X = regMask(0) 21889 var framepointerRegS390X = int8(-1) 21890 var linkRegS390X = int8(14)