github.com/rakyll/go@v0.0.0-20170216000551-64c02460d703/src/cmd/internal/obj/ppc64/asm9.go (about) 1 // cmd/9l/optab.c, cmd/9l/asmout.c from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package ppc64 31 32 import ( 33 "cmd/internal/obj" 34 "encoding/binary" 35 "fmt" 36 "log" 37 "sort" 38 ) 39 40 // Instruction layout. 41 42 const ( 43 funcAlign = 8 44 ) 45 46 const ( 47 r0iszero = 1 48 ) 49 50 type Optab struct { 51 as obj.As // Opcode 52 a1 uint8 53 a2 uint8 54 a3 uint8 55 a4 uint8 56 type_ int8 // cases in asmout below. E.g., 44 = st r,(ra+rb); 45 = ld (ra+rb), r 57 size int8 58 param int16 59 } 60 61 var optab = []Optab{ 62 {obj.ATEXT, C_LEXT, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 63 {obj.ATEXT, C_LEXT, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 64 {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 65 {obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 66 /* move register */ 67 {AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 4, 0}, 68 {AMOVB, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 69 {AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 70 {AMOVW, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 71 {AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 72 {AADD, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 73 {AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 74 {AADD, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 75 {AADD, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 76 {AADD, C_UCON, C_REG, C_NONE, C_REG, 20, 4, 0}, 77 {AADD, C_UCON, C_NONE, C_NONE, C_REG, 20, 4, 0}, 78 {AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 79 {AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 80 {AADDC, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 81 {AADDC, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 82 {AADDC, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 83 {AADDC, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 84 {AADDC, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 85 {AADDC, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 86 {AAND, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, no literal */ 87 {AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 88 {AANDCC, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 89 {AANDCC, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 90 {AANDCC, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 91 {AANDCC, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 92 {AANDCC, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 93 {AANDCC, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 94 {AANDCC, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 95 {AANDCC, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 96 {AMULLW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 97 {AMULLW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 98 {AMULLW, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 99 {AMULLW, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 100 {AMULLW, C_ANDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 101 {AMULLW, C_ANDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 102 {AMULLW, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 103 {AMULLW, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 104 {ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, 105 {ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 106 {ASUBC, C_REG, C_NONE, C_ADDCON, C_REG, 27, 4, 0}, 107 {ASUBC, C_REG, C_NONE, C_LCON, C_REG, 28, 12, 0}, 108 {AOR, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, literal not cc (or/xor) */ 109 {AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 110 {AOR, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 111 {AOR, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 112 {AOR, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 113 {AOR, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 114 {AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 115 {AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 116 {ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, /* op r1[,r2],r3 */ 117 {ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 118 {ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, /* op r2[,r1],r3 */ 119 {ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 120 {ASLW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 121 {ASLW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 122 {ASLD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 123 {ASLD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 124 {ASLD, C_SCON, C_REG, C_NONE, C_REG, 25, 4, 0}, 125 {ASLD, C_SCON, C_NONE, C_NONE, C_REG, 25, 4, 0}, 126 {ASLW, C_SCON, C_REG, C_NONE, C_REG, 57, 4, 0}, 127 {ASLW, C_SCON, C_NONE, C_NONE, C_REG, 57, 4, 0}, 128 {ASRAW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 129 {ASRAW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 130 {ASRAW, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 131 {ASRAW, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 132 {ASRAD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 133 {ASRAD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 134 {ASRAD, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 135 {ASRAD, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 136 {ARLWMI, C_SCON, C_REG, C_LCON, C_REG, 62, 4, 0}, 137 {ARLWMI, C_REG, C_REG, C_LCON, C_REG, 63, 4, 0}, 138 {ARLDMI, C_SCON, C_REG, C_LCON, C_REG, 30, 4, 0}, 139 {ARLDC, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 140 {ARLDCL, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 141 {ARLDCL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 142 {ARLDICL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 143 {ARLDICL, C_SCON, C_REG, C_LCON, C_REG, 14, 4, 0}, 144 {ARLDCL, C_REG, C_NONE, C_LCON, C_REG, 14, 4, 0}, 145 {AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 4, 0}, 146 {AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 4, 0}, 147 {AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 148 {AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 149 {AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 150 {AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 4, 0}, 151 {AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 4, 0}, 152 {AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 4, 0}, 153 154 /* store, short offset */ 155 {AMOVD, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 156 {AMOVW, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 157 {AMOVWZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 158 {AMOVBZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 159 {AMOVBZU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 160 {AMOVB, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 161 {AMOVBU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 162 {AMOVD, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 163 {AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 164 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 165 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 166 {AMOVB, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 167 {AMOVD, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 168 {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 169 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 170 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 171 {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 172 {AMOVD, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 173 {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 174 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 175 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 176 {AMOVBZU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 177 {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 178 {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 179 180 /* load, short offset */ 181 {AMOVD, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 182 {AMOVW, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 183 {AMOVWZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 184 {AMOVBZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 185 {AMOVBZU, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 186 {AMOVB, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 187 {AMOVBU, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 188 {AMOVD, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 189 {AMOVW, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 190 {AMOVWZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 191 {AMOVBZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 192 {AMOVB, C_SEXT, C_NONE, C_NONE, C_REG, 9, 8, REGSB}, 193 {AMOVD, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 194 {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 195 {AMOVWZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 196 {AMOVBZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 197 {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, 9, 8, REGSP}, 198 {AMOVD, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 199 {AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 200 {AMOVWZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 201 {AMOVBZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 202 {AMOVBZU, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 203 {AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 204 {AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 205 206 /* store, long offset */ 207 {AMOVD, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 208 {AMOVW, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 209 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 210 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 211 {AMOVB, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 212 {AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 213 {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 214 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 215 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 216 {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 217 {AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 218 {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 219 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 220 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 221 {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 222 {AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 223 {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 224 {AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 225 {AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 226 {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 227 228 /* load, long offset */ 229 {AMOVD, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 230 {AMOVW, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 231 {AMOVWZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 232 {AMOVBZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 233 {AMOVB, C_LEXT, C_NONE, C_NONE, C_REG, 37, 12, REGSB}, 234 {AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 235 {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 236 {AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 237 {AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 238 {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 37, 12, REGSP}, 239 {AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 240 {AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 241 {AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 242 {AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 243 {AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 37, 12, REGZERO}, 244 {AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 245 {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 246 {AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 247 {AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 248 {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 76, 12, 0}, 249 250 {AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 79, 4, 0}, 251 {AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 80, 8, 0}, 252 253 {AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 81, 8, 0}, 254 255 /* load constant */ 256 {AMOVD, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, 257 {AMOVD, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 258 {AMOVD, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 259 {AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 260 {AMOVD, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 261 {AMOVW, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 262 {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 263 {AMOVW, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 264 {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 265 {AMOVW, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 266 {AMOVWZ, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 267 {AMOVWZ, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 268 {AMOVWZ, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 269 {AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 270 {AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 271 272 /* load unsigned/long constants (TO DO: check) */ 273 {AMOVD, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 274 {AMOVD, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 275 {AMOVW, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 276 {AMOVW, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 277 {AMOVWZ, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 278 {AMOVWZ, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 279 {AMOVHBR, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 280 {AMOVHBR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 281 {AMOVHBR, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 282 {AMOVHBR, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 283 {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0}, 284 {ASYSCALL, C_REG, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 285 {ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 286 {ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 287 {ABEQ, C_CREG, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 288 {ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, 289 {ABR, C_NONE, C_NONE, C_NONE, C_LBRAPIC, 11, 8, 0}, 290 {ABC, C_SCON, C_REG, C_NONE, C_SBRA, 16, 4, 0}, 291 {ABC, C_SCON, C_REG, C_NONE, C_LBRA, 17, 4, 0}, 292 {ABR, C_NONE, C_NONE, C_NONE, C_LR, 18, 4, 0}, 293 {ABR, C_NONE, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 294 {ABR, C_REG, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 295 {ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 296 {ABC, C_NONE, C_REG, C_NONE, C_LR, 18, 4, 0}, 297 {ABC, C_NONE, C_REG, C_NONE, C_CTR, 18, 4, 0}, 298 {ABC, C_SCON, C_REG, C_NONE, C_LR, 18, 4, 0}, 299 {ABC, C_SCON, C_REG, C_NONE, C_CTR, 18, 4, 0}, 300 {ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 301 {AFMOVD, C_SEXT, C_NONE, C_NONE, C_FREG, 8, 4, REGSB}, 302 {AFMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, 8, 4, REGSP}, 303 {AFMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, 8, 4, REGZERO}, 304 {AFMOVD, C_LEXT, C_NONE, C_NONE, C_FREG, 36, 8, REGSB}, 305 {AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, 8, REGSP}, 306 {AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 8, REGZERO}, 307 {AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 8, 0}, 308 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 309 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 310 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 311 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 312 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 313 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 314 {AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 315 {AFMOVSX, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 316 {AFMOVSX, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 317 {AFMOVSX, C_FREG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 318 {AFMOVSX, C_FREG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 319 {AFMOVSZ, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 320 {AFMOVSZ, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 321 {ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 322 {AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 4, 0}, 323 {ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 324 {ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 325 {AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 326 {AEXTSB, C_REG, C_NONE, C_NONE, C_REG, 48, 4, 0}, 327 {AEXTSB, C_NONE, C_NONE, C_NONE, C_REG, 48, 4, 0}, 328 {AISEL, C_LCON, C_REG, C_REG, C_REG, 84, 4, 0}, 329 {AISEL, C_ZCON, C_REG, C_REG, C_REG, 84, 4, 0}, 330 {ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 331 {ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 4, 0}, 332 {AREM, C_REG, C_NONE, C_NONE, C_REG, 50, 12, 0}, 333 {AREM, C_REG, C_REG, C_NONE, C_REG, 50, 12, 0}, 334 {AREMU, C_REG, C_NONE, C_NONE, C_REG, 50, 16, 0}, 335 {AREMU, C_REG, C_REG, C_NONE, C_REG, 50, 16, 0}, 336 {AREMD, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 337 {AREMD, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 338 {AREMDU, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 339 {AREMDU, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 340 {AMTFSB0, C_SCON, C_NONE, C_NONE, C_NONE, 52, 4, 0}, 341 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_FREG, 53, 4, 0}, 342 {AMOVFL, C_FREG, C_NONE, C_NONE, C_FPSCR, 64, 4, 0}, 343 {AMOVFL, C_FREG, C_NONE, C_LCON, C_FPSCR, 64, 4, 0}, 344 {AMOVFL, C_LCON, C_NONE, C_NONE, C_FPSCR, 65, 4, 0}, 345 {AMOVD, C_MSR, C_NONE, C_NONE, C_REG, 54, 4, 0}, /* mfmsr */ 346 {AMOVD, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsrd */ 347 {AMOVWZ, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsr */ 348 349 /* Other ISA 2.05+ instructions */ 350 {APOPCNTD, C_REG, C_NONE, C_NONE, C_REG, 93, 4, 0}, /* population count, x-form */ 351 {ACMPB, C_REG, C_REG, C_NONE, C_REG, 92, 4, 0}, /* compare byte, x-form */ 352 {AFTDIV, C_FREG, C_FREG, C_NONE, C_SCON, 92, 4, 0}, /* floating test for sw divide, x-form */ 353 {AFTSQRT, C_FREG, C_NONE, C_NONE, C_SCON, 93, 4, 0}, /* floating test for sw square root, x-form */ 354 355 /* Vector instructions */ 356 357 /* Vector load */ 358 {ALV, C_SOREG, C_NONE, C_NONE, C_VREG, 45, 4, 0}, /* vector load, x-form */ 359 360 /* Vector store */ 361 {ASTV, C_VREG, C_NONE, C_NONE, C_SOREG, 44, 4, 0}, /* vector store, x-form */ 362 363 /* Vector logical */ 364 {AVAND, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector and, vx-form */ 365 {AVOR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector or, vx-form */ 366 367 /* Vector add */ 368 {AVADDUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned modulo, vx-form */ 369 {AVADDCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add & write carry unsigned, vx-form */ 370 {AVADDUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned saturate, vx-form */ 371 {AVADDSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add signed saturate, vx-form */ 372 {AVADDE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector add extended, va-form */ 373 374 /* Vector subtract */ 375 {AVSUBUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned modulo, vx-form */ 376 {AVSUBCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract & write carry unsigned, vx-form */ 377 {AVSUBUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned saturate, vx-form */ 378 {AVSUBSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract signed saturate, vx-form */ 379 {AVSUBE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector subtract extended, va-form */ 380 381 /* Vector multiply */ 382 {AVPMSUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector polynomial multiply & sum, vx-form */ 383 384 /* Vector rotate */ 385 {AVR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector rotate, vx-form */ 386 387 /* Vector shift */ 388 {AVS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift, vx-form */ 389 {AVSA, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift algebraic, vx-form */ 390 {AVSOI, C_ANDCON, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector shift by octet immediate, va-form */ 391 392 /* Vector count */ 393 {AVCLZ, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector count leading zeros, vx-form */ 394 {AVPOPCNT, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector population count, vx-form */ 395 396 /* Vector compare */ 397 {AVCMPEQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare equal, vc-form */ 398 {AVCMPGT, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare greater than, vc-form */ 399 400 /* Vector permute */ 401 {AVPERM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector permute, va-form */ 402 403 /* Vector select */ 404 {AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector select, va-form */ 405 406 /* Vector splat */ 407 {AVSPLT, C_SCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector splat, vx-form */ 408 {AVSPLT, C_ADDCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, 409 {AVSPLTI, C_SCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector splat immediate, vx-form */ 410 {AVSPLTI, C_ADDCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, 411 412 /* Vector AES */ 413 {AVCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES cipher, vx-form */ 414 {AVNCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES inverse cipher, vx-form */ 415 {AVSBOX, C_VREG, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector AES subbytes, vx-form */ 416 417 /* Vector SHA */ 418 {AVSHASIGMA, C_ANDCON, C_VREG, C_ANDCON, C_VREG, 82, 4, 0}, /* vector SHA sigma, vx-form */ 419 420 /* VSX vector load */ 421 {ALXV, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx vector load, xx1-form */ 422 423 /* VSX vector store */ 424 {ASTXV, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx vector store, xx1-form */ 425 426 /* VSX scalar load */ 427 {ALXS, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar load, xx1-form */ 428 429 /* VSX scalar store */ 430 {ASTXS, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar store, xx1-form */ 431 432 /* VSX scalar as integer load */ 433 {ALXSI, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar as integer load, xx1-form */ 434 435 /* VSX scalar store as integer */ 436 {ASTXSI, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar as integer store, xx1-form */ 437 438 /* VSX move from VSR */ 439 {AMFVSR, C_VSREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, /* vsx move from vsr, xx1-form */ 440 {AMFVSR, C_FREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 441 {AMFVSR, C_VREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 442 443 /* VSX move to VSR */ 444 {AMTVSR, C_REG, C_NONE, C_NONE, C_VSREG, 88, 4, 0}, /* vsx move to vsr, xx1-form */ 445 {AMTVSR, C_REG, C_NONE, C_NONE, C_FREG, 88, 4, 0}, 446 {AMTVSR, C_REG, C_NONE, C_NONE, C_VREG, 88, 4, 0}, 447 448 /* VSX logical */ 449 {AXXLAND, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx and, xx3-form */ 450 {AXXLOR, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx or, xx3-form */ 451 452 /* VSX select */ 453 {AXXSEL, C_VSREG, C_VSREG, C_VSREG, C_VSREG, 91, 4, 0}, /* vsx select, xx4-form */ 454 455 /* VSX merge */ 456 {AXXMRG, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx merge, xx3-form */ 457 458 /* VSX splat */ 459 {AXXSPLT, C_VSREG, C_NONE, C_SCON, C_VSREG, 89, 4, 0}, /* vsx splat, xx2-form */ 460 461 /* VSX permute */ 462 {AXXPERM, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx permute, xx3-form */ 463 464 /* VSX shift */ 465 {AXXSI, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx shift immediate, xx3-form */ 466 467 /* VSX scalar FP-FP conversion */ 468 {AXSCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-fp conversion, xx2-form */ 469 470 /* VSX vector FP-FP conversion */ 471 {AXVCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-fp conversion, xx2-form */ 472 473 /* VSX scalar FP-integer conversion */ 474 {AXSCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-integer conversion, xx2-form */ 475 476 /* VSX scalar integer-FP conversion */ 477 {AXSCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar integer-fp conversion, xx2-form */ 478 479 /* VSX vector FP-integer conversion */ 480 {AXVCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-integer conversion, xx2-form */ 481 482 /* VSX vector integer-FP conversion */ 483 {AXVCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector integer-fp conversion, xx2-form */ 484 485 /* 64-bit special registers */ 486 {AMOVD, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 487 {AMOVD, C_REG, C_NONE, C_NONE, C_LR, 66, 4, 0}, 488 {AMOVD, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 489 {AMOVD, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 490 {AMOVD, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 491 {AMOVD, C_LR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 492 {AMOVD, C_CTR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 493 {AMOVD, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 494 495 /* 32-bit special registers (gloss over sign-extension or not?) */ 496 {AMOVW, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 497 {AMOVW, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 498 {AMOVW, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 499 {AMOVW, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 500 {AMOVW, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 501 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 502 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 503 {AMOVWZ, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 504 {AMOVWZ, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 505 {AMOVWZ, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 506 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_CREG, 73, 4, 0}, 507 {AMOVFL, C_CREG, C_NONE, C_NONE, C_CREG, 67, 4, 0}, 508 {AMOVW, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 509 {AMOVWZ, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 510 {AMOVFL, C_REG, C_NONE, C_LCON, C_CREG, 69, 4, 0}, 511 {AMOVFL, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 512 {AMOVW, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 513 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 514 {ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 515 {ACMP, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 516 {ACMP, C_REG, C_NONE, C_NONE, C_ADDCON, 71, 4, 0}, 517 {ACMP, C_REG, C_REG, C_NONE, C_ADDCON, 71, 4, 0}, 518 {ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 519 {ACMPU, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 520 {ACMPU, C_REG, C_NONE, C_NONE, C_ANDCON, 71, 4, 0}, 521 {ACMPU, C_REG, C_REG, C_NONE, C_ANDCON, 71, 4, 0}, 522 {AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 4, 0}, 523 {AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 4, 0}, 524 {ATW, C_LCON, C_REG, C_NONE, C_REG, 60, 4, 0}, 525 {ATW, C_LCON, C_REG, C_NONE, C_ADDCON, 61, 4, 0}, 526 {ADCBF, C_ZOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0}, 527 {ADCBF, C_ZOREG, C_REG, C_NONE, C_NONE, 43, 4, 0}, 528 {AECOWX, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 529 {AECIWX, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 530 {AECOWX, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 531 {AECIWX, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 532 {AEIEIO, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 533 {ATLBIE, C_REG, C_NONE, C_NONE, C_NONE, 49, 4, 0}, 534 {ATLBIE, C_SCON, C_NONE, C_NONE, C_REG, 49, 4, 0}, 535 {ASLBMFEE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 536 {ASLBMTE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 537 {ASTSW, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 538 {ASTSW, C_REG, C_NONE, C_LCON, C_ZOREG, 41, 4, 0}, 539 {ALSW, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 540 {ALSW, C_ZOREG, C_NONE, C_LCON, C_REG, 42, 4, 0}, 541 {obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 4, 0}, 542 {obj.AUSEFIELD, C_ADDR, C_NONE, C_NONE, C_NONE, 0, 0, 0}, 543 {obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0, 0}, 544 {obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0, 0}, 545 {obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0}, 546 {obj.ADUFFZERO, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 547 {obj.ADUFFCOPY, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 548 549 {obj.AXXX, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0}, 550 } 551 552 var oprange [ALAST & obj.AMask][]Optab 553 554 var xcmp [C_NCLASS][C_NCLASS]bool 555 556 func span9(ctxt *obj.Link, cursym *obj.LSym) { 557 p := cursym.Text 558 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 559 return 560 } 561 ctxt.Cursym = cursym 562 ctxt.Autosize = int32(p.To.Offset) 563 564 if oprange[AANDN&obj.AMask] == nil { 565 buildop(ctxt) 566 } 567 568 c := int64(0) 569 p.Pc = c 570 571 var m int 572 var o *Optab 573 for p = p.Link; p != nil; p = p.Link { 574 ctxt.Curp = p 575 p.Pc = c 576 o = oplook(ctxt, p) 577 m = int(o.size) 578 if m == 0 { 579 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA && p.As != obj.AUSEFIELD { 580 ctxt.Diag("zero-width instruction\n%v", p) 581 } 582 continue 583 } 584 585 c += int64(m) 586 } 587 588 cursym.Size = c 589 590 /* 591 * if any procedure is large enough to 592 * generate a large SBRA branch, then 593 * generate extra passes putting branches 594 * around jmps to fix. this is rare. 595 */ 596 bflag := 1 597 598 var otxt int64 599 var q *obj.Prog 600 for bflag != 0 { 601 if ctxt.Debugvlog != 0 { 602 ctxt.Logf("%5.2f span1\n", obj.Cputime()) 603 } 604 bflag = 0 605 c = 0 606 for p = cursym.Text.Link; p != nil; p = p.Link { 607 p.Pc = c 608 o = oplook(ctxt, p) 609 610 // very large conditional branches 611 if (o.type_ == 16 || o.type_ == 17) && p.Pcond != nil { 612 otxt = p.Pcond.Pc - c 613 if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 { 614 q = ctxt.NewProg() 615 q.Link = p.Link 616 p.Link = q 617 q.As = ABR 618 q.To.Type = obj.TYPE_BRANCH 619 q.Pcond = p.Pcond 620 p.Pcond = q 621 q = ctxt.NewProg() 622 q.Link = p.Link 623 p.Link = q 624 q.As = ABR 625 q.To.Type = obj.TYPE_BRANCH 626 q.Pcond = q.Link.Link 627 628 //addnop(p->link); 629 //addnop(p); 630 bflag = 1 631 } 632 } 633 634 m = int(o.size) 635 if m == 0 { 636 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA && p.As != obj.AUSEFIELD { 637 ctxt.Diag("zero-width instruction\n%v", p) 638 } 639 continue 640 } 641 642 c += int64(m) 643 } 644 645 cursym.Size = c 646 } 647 648 c += -c & (funcAlign - 1) 649 cursym.Size = c 650 651 /* 652 * lay out the code, emitting code and data relocations. 653 */ 654 655 cursym.Grow(cursym.Size) 656 657 bp := cursym.P 658 var i int32 659 var out [6]uint32 660 for p := cursym.Text.Link; p != nil; p = p.Link { 661 ctxt.Pc = p.Pc 662 ctxt.Curp = p 663 o = oplook(ctxt, p) 664 if int(o.size) > 4*len(out) { 665 log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p) 666 } 667 asmout(ctxt, p, o, out[:]) 668 for i = 0; i < int32(o.size/4); i++ { 669 ctxt.Arch.ByteOrder.PutUint32(bp, out[i]) 670 bp = bp[4:] 671 } 672 } 673 } 674 675 func isint32(v int64) bool { 676 return int64(int32(v)) == v 677 } 678 679 func isuint32(v uint64) bool { 680 return uint64(uint32(v)) == v 681 } 682 683 func aclass(ctxt *obj.Link, a *obj.Addr) int { 684 switch a.Type { 685 case obj.TYPE_NONE: 686 return C_NONE 687 688 case obj.TYPE_REG: 689 if REG_R0 <= a.Reg && a.Reg <= REG_R31 { 690 return C_REG 691 } 692 if REG_F0 <= a.Reg && a.Reg <= REG_F31 { 693 return C_FREG 694 } 695 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 696 return C_VREG 697 } 698 if REG_VS0 <= a.Reg && a.Reg <= REG_VS63 { 699 return C_VSREG 700 } 701 if REG_CR0 <= a.Reg && a.Reg <= REG_CR7 || a.Reg == REG_CR { 702 return C_CREG 703 } 704 if REG_SPR0 <= a.Reg && a.Reg <= REG_SPR0+1023 { 705 switch a.Reg { 706 case REG_LR: 707 return C_LR 708 709 case REG_XER: 710 return C_XER 711 712 case REG_CTR: 713 return C_CTR 714 } 715 716 return C_SPR 717 } 718 719 if REG_DCR0 <= a.Reg && a.Reg <= REG_DCR0+1023 { 720 return C_SPR 721 } 722 if a.Reg == REG_FPSCR { 723 return C_FPSCR 724 } 725 if a.Reg == REG_MSR { 726 return C_MSR 727 } 728 return C_GOK 729 730 case obj.TYPE_MEM: 731 switch a.Name { 732 case obj.NAME_EXTERN, 733 obj.NAME_STATIC: 734 if a.Sym == nil { 735 break 736 } 737 ctxt.Instoffset = a.Offset 738 if a.Sym != nil { // use relocation 739 if a.Sym.Type == obj.STLSBSS { 740 if ctxt.Flag_shared { 741 return C_TLS_IE 742 } else { 743 return C_TLS_LE 744 } 745 } 746 return C_ADDR 747 } 748 return C_LEXT 749 750 case obj.NAME_GOTREF: 751 return C_GOTADDR 752 753 case obj.NAME_AUTO: 754 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset 755 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 756 return C_SAUTO 757 } 758 return C_LAUTO 759 760 case obj.NAME_PARAM: 761 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + ctxt.FixedFrameSize() 762 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 763 return C_SAUTO 764 } 765 return C_LAUTO 766 767 case obj.NAME_NONE: 768 ctxt.Instoffset = a.Offset 769 if ctxt.Instoffset == 0 { 770 return C_ZOREG 771 } 772 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 773 return C_SOREG 774 } 775 return C_LOREG 776 } 777 778 return C_GOK 779 780 case obj.TYPE_TEXTSIZE: 781 return C_TEXTSIZE 782 783 case obj.TYPE_CONST, 784 obj.TYPE_ADDR: 785 switch a.Name { 786 case obj.NAME_NONE: 787 ctxt.Instoffset = a.Offset 788 if a.Reg != 0 { 789 if -BIG <= ctxt.Instoffset && ctxt.Instoffset <= BIG { 790 return C_SACON 791 } 792 if isint32(ctxt.Instoffset) { 793 return C_LACON 794 } 795 return C_DACON 796 } 797 798 goto consize 799 800 case obj.NAME_EXTERN, 801 obj.NAME_STATIC: 802 s := a.Sym 803 if s == nil { 804 break 805 } 806 if s.Type == obj.SCONST { 807 ctxt.Instoffset = a.Offset 808 goto consize 809 } 810 811 ctxt.Instoffset = a.Offset 812 813 /* not sure why this barfs */ 814 return C_LCON 815 816 case obj.NAME_AUTO: 817 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset 818 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 819 return C_SACON 820 } 821 return C_LACON 822 823 case obj.NAME_PARAM: 824 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + ctxt.FixedFrameSize() 825 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 826 return C_SACON 827 } 828 return C_LACON 829 } 830 831 return C_GOK 832 833 consize: 834 if ctxt.Instoffset >= 0 { 835 if ctxt.Instoffset == 0 { 836 return C_ZCON 837 } 838 if ctxt.Instoffset <= 0x7fff { 839 return C_SCON 840 } 841 if ctxt.Instoffset <= 0xffff { 842 return C_ANDCON 843 } 844 if ctxt.Instoffset&0xffff == 0 && isuint32(uint64(ctxt.Instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 845 return C_UCON 846 } 847 if isint32(ctxt.Instoffset) || isuint32(uint64(ctxt.Instoffset)) { 848 return C_LCON 849 } 850 return C_DCON 851 } 852 853 if ctxt.Instoffset >= -0x8000 { 854 return C_ADDCON 855 } 856 if ctxt.Instoffset&0xffff == 0 && isint32(ctxt.Instoffset) { 857 return C_UCON 858 } 859 if isint32(ctxt.Instoffset) { 860 return C_LCON 861 } 862 return C_DCON 863 864 case obj.TYPE_BRANCH: 865 if a.Sym != nil && ctxt.Flag_dynlink { 866 return C_LBRAPIC 867 } 868 return C_SBRA 869 } 870 871 return C_GOK 872 } 873 874 func prasm(p *obj.Prog) { 875 fmt.Printf("%v\n", p) 876 } 877 878 func oplook(ctxt *obj.Link, p *obj.Prog) *Optab { 879 a1 := int(p.Optab) 880 if a1 != 0 { 881 return &optab[a1-1] 882 } 883 a1 = int(p.From.Class) 884 if a1 == 0 { 885 a1 = aclass(ctxt, &p.From) + 1 886 p.From.Class = int8(a1) 887 } 888 889 a1-- 890 a3 := C_NONE + 1 891 if p.From3 != nil { 892 a3 = int(p.From3.Class) 893 if a3 == 0 { 894 a3 = aclass(ctxt, p.From3) + 1 895 p.From3.Class = int8(a3) 896 } 897 } 898 899 a3-- 900 a4 := int(p.To.Class) 901 if a4 == 0 { 902 a4 = aclass(ctxt, &p.To) + 1 903 p.To.Class = int8(a4) 904 } 905 906 a4-- 907 a2 := C_NONE 908 if p.Reg != 0 { 909 if REG_R0 <= p.Reg && p.Reg <= REG_R31 { 910 a2 = C_REG 911 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 912 a2 = C_VREG 913 } else if REG_VS0 <= p.Reg && p.Reg <= REG_VS63 { 914 a2 = C_VSREG 915 } else if REG_F0 <= p.Reg && p.Reg <= REG_F31 { 916 a2 = C_FREG 917 } 918 } 919 920 //print("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4); 921 ops := oprange[p.As&obj.AMask] 922 c1 := &xcmp[a1] 923 c3 := &xcmp[a3] 924 c4 := &xcmp[a4] 925 for i := range ops { 926 op := &ops[i] 927 if int(op.a2) == a2 && c1[op.a1] && c3[op.a3] && c4[op.a4] { 928 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 929 return op 930 } 931 } 932 933 ctxt.Diag("illegal combination %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 934 prasm(p) 935 if ops == nil { 936 ops = optab 937 } 938 return &ops[0] 939 } 940 941 func cmp(a int, b int) bool { 942 if a == b { 943 return true 944 } 945 switch a { 946 case C_LCON: 947 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 948 return true 949 } 950 951 case C_ADDCON: 952 if b == C_ZCON || b == C_SCON { 953 return true 954 } 955 956 case C_ANDCON: 957 if b == C_ZCON || b == C_SCON { 958 return true 959 } 960 961 case C_SPR: 962 if b == C_LR || b == C_XER || b == C_CTR { 963 return true 964 } 965 966 case C_UCON: 967 if b == C_ZCON { 968 return true 969 } 970 971 case C_SCON: 972 if b == C_ZCON { 973 return true 974 } 975 976 case C_LACON: 977 if b == C_SACON { 978 return true 979 } 980 981 case C_LBRA: 982 if b == C_SBRA { 983 return true 984 } 985 986 case C_LEXT: 987 if b == C_SEXT { 988 return true 989 } 990 991 case C_LAUTO: 992 if b == C_SAUTO { 993 return true 994 } 995 996 case C_REG: 997 if b == C_ZCON { 998 return r0iszero != 0 /*TypeKind(100016)*/ 999 } 1000 1001 case C_LOREG: 1002 if b == C_ZOREG || b == C_SOREG { 1003 return true 1004 } 1005 1006 case C_SOREG: 1007 if b == C_ZOREG { 1008 return true 1009 } 1010 1011 case C_ANY: 1012 return true 1013 } 1014 1015 return false 1016 } 1017 1018 type ocmp []Optab 1019 1020 func (x ocmp) Len() int { 1021 return len(x) 1022 } 1023 1024 func (x ocmp) Swap(i, j int) { 1025 x[i], x[j] = x[j], x[i] 1026 } 1027 1028 func (x ocmp) Less(i, j int) bool { 1029 p1 := &x[i] 1030 p2 := &x[j] 1031 n := int(p1.as) - int(p2.as) 1032 if n != 0 { 1033 return n < 0 1034 } 1035 n = int(p1.a1) - int(p2.a1) 1036 if n != 0 { 1037 return n < 0 1038 } 1039 n = int(p1.a2) - int(p2.a2) 1040 if n != 0 { 1041 return n < 0 1042 } 1043 n = int(p1.a3) - int(p2.a3) 1044 if n != 0 { 1045 return n < 0 1046 } 1047 n = int(p1.a4) - int(p2.a4) 1048 if n != 0 { 1049 return n < 0 1050 } 1051 return false 1052 } 1053 func opset(a, b0 obj.As) { 1054 oprange[a&obj.AMask] = oprange[b0] 1055 } 1056 1057 func buildop(ctxt *obj.Link) { 1058 var n int 1059 1060 for i := 0; i < C_NCLASS; i++ { 1061 for n = 0; n < C_NCLASS; n++ { 1062 if cmp(n, i) { 1063 xcmp[i][n] = true 1064 } 1065 } 1066 } 1067 for n = 0; optab[n].as != obj.AXXX; n++ { 1068 } 1069 sort.Sort(ocmp(optab[:n])) 1070 for i := 0; i < n; i++ { 1071 r := optab[i].as 1072 r0 := r & obj.AMask 1073 start := i 1074 for optab[i].as == r { 1075 i++ 1076 } 1077 oprange[r0] = optab[start:i] 1078 i-- 1079 1080 switch r { 1081 default: 1082 ctxt.Diag("unknown op in build: %v", r) 1083 log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r) 1084 1085 case ADCBF: /* unary indexed: op (b+a); op (b) */ 1086 opset(ADCBI, r0) 1087 1088 opset(ADCBST, r0) 1089 opset(ADCBT, r0) 1090 opset(ADCBTST, r0) 1091 opset(ADCBZ, r0) 1092 opset(AICBI, r0) 1093 1094 case AECOWX: /* indexed store: op s,(b+a); op s,(b) */ 1095 opset(ASTWCCC, r0) 1096 opset(ASTBCCC, r0) 1097 1098 opset(ASTDCCC, r0) 1099 1100 case AREM: /* macro */ 1101 opset(AREMCC, r0) 1102 1103 opset(AREMV, r0) 1104 opset(AREMVCC, r0) 1105 1106 case AREMU: 1107 opset(AREMU, r0) 1108 opset(AREMUCC, r0) 1109 opset(AREMUV, r0) 1110 opset(AREMUVCC, r0) 1111 1112 case AREMD: 1113 opset(AREMDCC, r0) 1114 opset(AREMDV, r0) 1115 opset(AREMDVCC, r0) 1116 1117 case AREMDU: 1118 opset(AREMDU, r0) 1119 opset(AREMDUCC, r0) 1120 opset(AREMDUV, r0) 1121 opset(AREMDUVCC, r0) 1122 1123 case ADIVW: /* op Rb[,Ra],Rd */ 1124 opset(AMULHW, r0) 1125 1126 opset(AMULHWCC, r0) 1127 opset(AMULHWU, r0) 1128 opset(AMULHWUCC, r0) 1129 opset(AMULLWCC, r0) 1130 opset(AMULLWVCC, r0) 1131 opset(AMULLWV, r0) 1132 opset(ADIVWCC, r0) 1133 opset(ADIVWV, r0) 1134 opset(ADIVWVCC, r0) 1135 opset(ADIVWU, r0) 1136 opset(ADIVWUCC, r0) 1137 opset(ADIVWUV, r0) 1138 opset(ADIVWUVCC, r0) 1139 opset(AADDCC, r0) 1140 opset(AADDCV, r0) 1141 opset(AADDCVCC, r0) 1142 opset(AADDV, r0) 1143 opset(AADDVCC, r0) 1144 opset(AADDE, r0) 1145 opset(AADDECC, r0) 1146 opset(AADDEV, r0) 1147 opset(AADDEVCC, r0) 1148 opset(ACRAND, r0) 1149 opset(ACRANDN, r0) 1150 opset(ACREQV, r0) 1151 opset(ACRNAND, r0) 1152 opset(ACRNOR, r0) 1153 opset(ACROR, r0) 1154 opset(ACRORN, r0) 1155 opset(ACRXOR, r0) 1156 opset(AMULHD, r0) 1157 opset(AMULHDCC, r0) 1158 opset(AMULHDU, r0) 1159 opset(AMULHDUCC, r0) 1160 opset(AMULLD, r0) 1161 opset(AMULLDCC, r0) 1162 opset(AMULLDVCC, r0) 1163 opset(AMULLDV, r0) 1164 opset(ADIVD, r0) 1165 opset(ADIVDCC, r0) 1166 opset(ADIVDE, r0) 1167 opset(ADIVDEU, r0) 1168 opset(ADIVDECC, r0) 1169 opset(ADIVDEUCC, r0) 1170 opset(ADIVDVCC, r0) 1171 opset(ADIVDV, r0) 1172 opset(ADIVDU, r0) 1173 opset(ADIVDUCC, r0) 1174 opset(ADIVDUVCC, r0) 1175 opset(ADIVDUCC, r0) 1176 1177 case APOPCNTD: 1178 opset(APOPCNTW, r0) 1179 opset(APOPCNTB, r0) 1180 1181 case AMOVBZ: /* lbz, stz, rlwm(r/r), lhz, lha, stz, and x variants */ 1182 opset(AMOVH, r0) 1183 1184 opset(AMOVHZ, r0) 1185 1186 case AMOVBZU: /* lbz[x]u, stb[x]u, lhz[x]u, lha[x]u, sth[u]x, ld[x]u, std[u]x */ 1187 opset(AMOVHU, r0) 1188 1189 opset(AMOVHZU, r0) 1190 opset(AMOVWU, r0) 1191 opset(AMOVWZU, r0) 1192 opset(AMOVDU, r0) 1193 opset(AMOVMW, r0) 1194 1195 case ALV: /* lvebx, lvehx, lvewx, lvx, lvxl, lvsl, lvsr */ 1196 opset(ALVEBX, r0) 1197 opset(ALVEHX, r0) 1198 opset(ALVEWX, r0) 1199 opset(ALVX, r0) 1200 opset(ALVXL, r0) 1201 opset(ALVSL, r0) 1202 opset(ALVSR, r0) 1203 1204 case ASTV: /* stvebx, stvehx, stvewx, stvx, stvxl */ 1205 opset(ASTVEBX, r0) 1206 opset(ASTVEHX, r0) 1207 opset(ASTVEWX, r0) 1208 opset(ASTVX, r0) 1209 opset(ASTVXL, r0) 1210 1211 case AVAND: /* vand, vandc, vnand */ 1212 opset(AVAND, r0) 1213 opset(AVANDC, r0) 1214 opset(AVNAND, r0) 1215 1216 case AVOR: /* vor, vorc, vxor, vnor, veqv */ 1217 opset(AVOR, r0) 1218 opset(AVORC, r0) 1219 opset(AVXOR, r0) 1220 opset(AVNOR, r0) 1221 opset(AVEQV, r0) 1222 1223 case AVADDUM: /* vaddubm, vadduhm, vadduwm, vaddudm, vadduqm */ 1224 opset(AVADDUBM, r0) 1225 opset(AVADDUHM, r0) 1226 opset(AVADDUWM, r0) 1227 opset(AVADDUDM, r0) 1228 opset(AVADDUQM, r0) 1229 1230 case AVADDCU: /* vaddcuq, vaddcuw */ 1231 opset(AVADDCUQ, r0) 1232 opset(AVADDCUW, r0) 1233 1234 case AVADDUS: /* vaddubs, vadduhs, vadduws */ 1235 opset(AVADDUBS, r0) 1236 opset(AVADDUHS, r0) 1237 opset(AVADDUWS, r0) 1238 1239 case AVADDSS: /* vaddsbs, vaddshs, vaddsws */ 1240 opset(AVADDSBS, r0) 1241 opset(AVADDSHS, r0) 1242 opset(AVADDSWS, r0) 1243 1244 case AVADDE: /* vaddeuqm, vaddecuq */ 1245 opset(AVADDEUQM, r0) 1246 opset(AVADDECUQ, r0) 1247 1248 case AVSUBUM: /* vsububm, vsubuhm, vsubuwm, vsubudm, vsubuqm */ 1249 opset(AVSUBUBM, r0) 1250 opset(AVSUBUHM, r0) 1251 opset(AVSUBUWM, r0) 1252 opset(AVSUBUDM, r0) 1253 opset(AVSUBUQM, r0) 1254 1255 case AVSUBCU: /* vsubcuq, vsubcuw */ 1256 opset(AVSUBCUQ, r0) 1257 opset(AVSUBCUW, r0) 1258 1259 case AVSUBUS: /* vsububs, vsubuhs, vsubuws */ 1260 opset(AVSUBUBS, r0) 1261 opset(AVSUBUHS, r0) 1262 opset(AVSUBUWS, r0) 1263 1264 case AVSUBSS: /* vsubsbs, vsubshs, vsubsws */ 1265 opset(AVSUBSBS, r0) 1266 opset(AVSUBSHS, r0) 1267 opset(AVSUBSWS, r0) 1268 1269 case AVSUBE: /* vsubeuqm, vsubecuq */ 1270 opset(AVSUBEUQM, r0) 1271 opset(AVSUBECUQ, r0) 1272 1273 case AVPMSUM: /* vpmsumb, vpmsumh, vpmsumw, vpmsumd */ 1274 opset(AVPMSUMB, r0) 1275 opset(AVPMSUMH, r0) 1276 opset(AVPMSUMW, r0) 1277 opset(AVPMSUMD, r0) 1278 1279 case AVR: /* vrlb, vrlh, vrlw, vrld */ 1280 opset(AVRLB, r0) 1281 opset(AVRLH, r0) 1282 opset(AVRLW, r0) 1283 opset(AVRLD, r0) 1284 1285 case AVS: /* vs[l,r], vs[l,r]o, vs[l,r]b, vs[l,r]h, vs[l,r]w, vs[l,r]d */ 1286 opset(AVSLB, r0) 1287 opset(AVSLH, r0) 1288 opset(AVSLW, r0) 1289 opset(AVSL, r0) 1290 opset(AVSLO, r0) 1291 opset(AVSRB, r0) 1292 opset(AVSRH, r0) 1293 opset(AVSRW, r0) 1294 opset(AVSR, r0) 1295 opset(AVSRO, r0) 1296 opset(AVSLD, r0) 1297 opset(AVSRD, r0) 1298 1299 case AVSA: /* vsrab, vsrah, vsraw, vsrad */ 1300 opset(AVSRAB, r0) 1301 opset(AVSRAH, r0) 1302 opset(AVSRAW, r0) 1303 opset(AVSRAD, r0) 1304 1305 case AVSOI: /* vsldoi */ 1306 opset(AVSLDOI, r0) 1307 1308 case AVCLZ: /* vclzb, vclzh, vclzw, vclzd */ 1309 opset(AVCLZB, r0) 1310 opset(AVCLZH, r0) 1311 opset(AVCLZW, r0) 1312 opset(AVCLZD, r0) 1313 1314 case AVPOPCNT: /* vpopcntb, vpopcnth, vpopcntw, vpopcntd */ 1315 opset(AVPOPCNTB, r0) 1316 opset(AVPOPCNTH, r0) 1317 opset(AVPOPCNTW, r0) 1318 opset(AVPOPCNTD, r0) 1319 1320 case AVCMPEQ: /* vcmpequb[.], vcmpequh[.], vcmpequw[.], vcmpequd[.] */ 1321 opset(AVCMPEQUB, r0) 1322 opset(AVCMPEQUBCC, r0) 1323 opset(AVCMPEQUH, r0) 1324 opset(AVCMPEQUHCC, r0) 1325 opset(AVCMPEQUW, r0) 1326 opset(AVCMPEQUWCC, r0) 1327 opset(AVCMPEQUD, r0) 1328 opset(AVCMPEQUDCC, r0) 1329 1330 case AVCMPGT: /* vcmpgt[u,s]b[.], vcmpgt[u,s]h[.], vcmpgt[u,s]w[.], vcmpgt[u,s]d[.] */ 1331 opset(AVCMPGTUB, r0) 1332 opset(AVCMPGTUBCC, r0) 1333 opset(AVCMPGTUH, r0) 1334 opset(AVCMPGTUHCC, r0) 1335 opset(AVCMPGTUW, r0) 1336 opset(AVCMPGTUWCC, r0) 1337 opset(AVCMPGTUD, r0) 1338 opset(AVCMPGTUDCC, r0) 1339 opset(AVCMPGTSB, r0) 1340 opset(AVCMPGTSBCC, r0) 1341 opset(AVCMPGTSH, r0) 1342 opset(AVCMPGTSHCC, r0) 1343 opset(AVCMPGTSW, r0) 1344 opset(AVCMPGTSWCC, r0) 1345 opset(AVCMPGTSD, r0) 1346 opset(AVCMPGTSDCC, r0) 1347 1348 case AVPERM: /* vperm */ 1349 opset(AVPERM, r0) 1350 1351 case AVSEL: /* vsel */ 1352 opset(AVSEL, r0) 1353 1354 case AVSPLT: /* vspltb, vsplth, vspltw */ 1355 opset(AVSPLTB, r0) 1356 opset(AVSPLTH, r0) 1357 opset(AVSPLTW, r0) 1358 1359 case AVSPLTI: /* vspltisb, vspltish, vspltisw */ 1360 opset(AVSPLTISB, r0) 1361 opset(AVSPLTISH, r0) 1362 opset(AVSPLTISW, r0) 1363 1364 case AVCIPH: /* vcipher, vcipherlast */ 1365 opset(AVCIPHER, r0) 1366 opset(AVCIPHERLAST, r0) 1367 1368 case AVNCIPH: /* vncipher, vncipherlast */ 1369 opset(AVNCIPHER, r0) 1370 opset(AVNCIPHERLAST, r0) 1371 1372 case AVSBOX: /* vsbox */ 1373 opset(AVSBOX, r0) 1374 1375 case AVSHASIGMA: /* vshasigmaw, vshasigmad */ 1376 opset(AVSHASIGMAW, r0) 1377 opset(AVSHASIGMAD, r0) 1378 1379 case ALXV: /* lxvd2x, lxvdsx, lxvw4x */ 1380 opset(ALXVD2X, r0) 1381 opset(ALXVDSX, r0) 1382 opset(ALXVW4X, r0) 1383 1384 case ASTXV: /* stxvd2x, stxvdsx, stxvw4x */ 1385 opset(ASTXVD2X, r0) 1386 opset(ASTXVW4X, r0) 1387 1388 case ALXS: /* lxsdx */ 1389 opset(ALXSDX, r0) 1390 1391 case ASTXS: /* stxsdx */ 1392 opset(ASTXSDX, r0) 1393 1394 case ALXSI: /* lxsiwax, lxsiwzx */ 1395 opset(ALXSIWAX, r0) 1396 opset(ALXSIWZX, r0) 1397 1398 case ASTXSI: /* stxsiwx */ 1399 opset(ASTXSIWX, r0) 1400 1401 case AMFVSR: /* mfvsrd, mfvsrwz (and extended mnemonics) */ 1402 opset(AMFVSRD, r0) 1403 opset(AMFFPRD, r0) 1404 opset(AMFVRD, r0) 1405 opset(AMFVSRWZ, r0) 1406 1407 case AMTVSR: /* mtvsrd, mtvsrwa, mtvsrwz (and extended mnemonics) */ 1408 opset(AMTVSRD, r0) 1409 opset(AMTFPRD, r0) 1410 opset(AMTVRD, r0) 1411 opset(AMTVSRWA, r0) 1412 opset(AMTVSRWZ, r0) 1413 1414 case AXXLAND: /* xxland, xxlandc, xxleqv, xxlnand */ 1415 opset(AXXLANDQ, r0) 1416 opset(AXXLANDC, r0) 1417 opset(AXXLEQV, r0) 1418 opset(AXXLNAND, r0) 1419 1420 case AXXLOR: /* xxlorc, xxlnor, xxlor, xxlxor */ 1421 opset(AXXLORC, r0) 1422 opset(AXXLNOR, r0) 1423 opset(AXXLORQ, r0) 1424 opset(AXXLXOR, r0) 1425 1426 case AXXSEL: /* xxsel */ 1427 opset(AXXSEL, r0) 1428 1429 case AXXMRG: /* xxmrghw, xxmrglw */ 1430 opset(AXXMRGHW, r0) 1431 opset(AXXMRGLW, r0) 1432 1433 case AXXSPLT: /* xxspltw */ 1434 opset(AXXSPLTW, r0) 1435 1436 case AXXPERM: /* xxpermdi */ 1437 opset(AXXPERMDI, r0) 1438 1439 case AXXSI: /* xxsldwi */ 1440 opset(AXXSLDWI, r0) 1441 1442 case AXSCV: /* xscvdpsp, xscvspdp, xscvdpspn, xscvspdpn */ 1443 opset(AXSCVDPSP, r0) 1444 opset(AXSCVSPDP, r0) 1445 opset(AXSCVDPSPN, r0) 1446 opset(AXSCVSPDPN, r0) 1447 1448 case AXVCV: /* xvcvdpsp, xvcvspdp */ 1449 opset(AXVCVDPSP, r0) 1450 opset(AXVCVSPDP, r0) 1451 1452 case AXSCVX: /* xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws */ 1453 opset(AXSCVDPSXDS, r0) 1454 opset(AXSCVDPSXWS, r0) 1455 opset(AXSCVDPUXDS, r0) 1456 opset(AXSCVDPUXWS, r0) 1457 1458 case AXSCVXP: /* xscvsxddp, xscvuxddp, xscvsxdsp, xscvuxdsp */ 1459 opset(AXSCVSXDDP, r0) 1460 opset(AXSCVUXDDP, r0) 1461 opset(AXSCVSXDSP, r0) 1462 opset(AXSCVUXDSP, r0) 1463 1464 case AXVCVX: /* xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws, xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws */ 1465 opset(AXVCVDPSXDS, r0) 1466 opset(AXVCVDPSXWS, r0) 1467 opset(AXVCVDPUXDS, r0) 1468 opset(AXVCVDPUXWS, r0) 1469 opset(AXVCVSPSXDS, r0) 1470 opset(AXVCVSPSXWS, r0) 1471 opset(AXVCVSPUXDS, r0) 1472 opset(AXVCVSPUXWS, r0) 1473 1474 case AXVCVXP: /* xvcvsxddp, xvcvsxwdp, xvcvuxddp, xvcvuxwdp, xvcvsxdsp, xvcvsxwsp, xvcvuxdsp, xvcvuxwsp */ 1475 opset(AXVCVSXDDP, r0) 1476 opset(AXVCVSXWDP, r0) 1477 opset(AXVCVUXDDP, r0) 1478 opset(AXVCVUXWDP, r0) 1479 opset(AXVCVSXDSP, r0) 1480 opset(AXVCVSXWSP, r0) 1481 opset(AXVCVUXDSP, r0) 1482 opset(AXVCVUXWSP, r0) 1483 1484 case AAND: /* logical op Rb,Rs,Ra; no literal */ 1485 opset(AANDN, r0) 1486 1487 opset(AANDNCC, r0) 1488 opset(AEQV, r0) 1489 opset(AEQVCC, r0) 1490 opset(ANAND, r0) 1491 opset(ANANDCC, r0) 1492 opset(ANOR, r0) 1493 opset(ANORCC, r0) 1494 opset(AORCC, r0) 1495 opset(AORN, r0) 1496 opset(AORNCC, r0) 1497 opset(AXORCC, r0) 1498 1499 case AADDME: /* op Ra, Rd */ 1500 opset(AADDMECC, r0) 1501 1502 opset(AADDMEV, r0) 1503 opset(AADDMEVCC, r0) 1504 opset(AADDZE, r0) 1505 opset(AADDZECC, r0) 1506 opset(AADDZEV, r0) 1507 opset(AADDZEVCC, r0) 1508 opset(ASUBME, r0) 1509 opset(ASUBMECC, r0) 1510 opset(ASUBMEV, r0) 1511 opset(ASUBMEVCC, r0) 1512 opset(ASUBZE, r0) 1513 opset(ASUBZECC, r0) 1514 opset(ASUBZEV, r0) 1515 opset(ASUBZEVCC, r0) 1516 1517 case AADDC: 1518 opset(AADDCCC, r0) 1519 1520 case ABEQ: 1521 opset(ABGE, r0) 1522 opset(ABGT, r0) 1523 opset(ABLE, r0) 1524 opset(ABLT, r0) 1525 opset(ABNE, r0) 1526 opset(ABVC, r0) 1527 opset(ABVS, r0) 1528 1529 case ABR: 1530 opset(ABL, r0) 1531 1532 case ABC: 1533 opset(ABCL, r0) 1534 1535 case AEXTSB: /* op Rs, Ra */ 1536 opset(AEXTSBCC, r0) 1537 1538 opset(AEXTSH, r0) 1539 opset(AEXTSHCC, r0) 1540 opset(ACNTLZW, r0) 1541 opset(ACNTLZWCC, r0) 1542 opset(ACNTLZD, r0) 1543 opset(AEXTSW, r0) 1544 opset(AEXTSWCC, r0) 1545 opset(ACNTLZDCC, r0) 1546 1547 case AFABS: /* fop [s,]d */ 1548 opset(AFABSCC, r0) 1549 1550 opset(AFNABS, r0) 1551 opset(AFNABSCC, r0) 1552 opset(AFNEG, r0) 1553 opset(AFNEGCC, r0) 1554 opset(AFRSP, r0) 1555 opset(AFRSPCC, r0) 1556 opset(AFCTIW, r0) 1557 opset(AFCTIWCC, r0) 1558 opset(AFCTIWZ, r0) 1559 opset(AFCTIWZCC, r0) 1560 opset(AFCTID, r0) 1561 opset(AFCTIDCC, r0) 1562 opset(AFCTIDZ, r0) 1563 opset(AFCTIDZCC, r0) 1564 opset(AFCFID, r0) 1565 opset(AFCFIDCC, r0) 1566 opset(AFCFIDU, r0) 1567 opset(AFCFIDUCC, r0) 1568 opset(AFRES, r0) 1569 opset(AFRESCC, r0) 1570 opset(AFRIM, r0) 1571 opset(AFRIMCC, r0) 1572 opset(AFRIP, r0) 1573 opset(AFRIPCC, r0) 1574 opset(AFRIZ, r0) 1575 opset(AFRIZCC, r0) 1576 opset(AFRSQRTE, r0) 1577 opset(AFRSQRTECC, r0) 1578 opset(AFSQRT, r0) 1579 opset(AFSQRTCC, r0) 1580 opset(AFSQRTS, r0) 1581 opset(AFSQRTSCC, r0) 1582 1583 case AFADD: 1584 opset(AFADDS, r0) 1585 opset(AFADDCC, r0) 1586 opset(AFADDSCC, r0) 1587 opset(AFDIV, r0) 1588 opset(AFDIVS, r0) 1589 opset(AFDIVCC, r0) 1590 opset(AFDIVSCC, r0) 1591 opset(AFSUB, r0) 1592 opset(AFSUBS, r0) 1593 opset(AFSUBCC, r0) 1594 opset(AFSUBSCC, r0) 1595 1596 case AFMADD: 1597 opset(AFMADDCC, r0) 1598 opset(AFMADDS, r0) 1599 opset(AFMADDSCC, r0) 1600 opset(AFMSUB, r0) 1601 opset(AFMSUBCC, r0) 1602 opset(AFMSUBS, r0) 1603 opset(AFMSUBSCC, r0) 1604 opset(AFNMADD, r0) 1605 opset(AFNMADDCC, r0) 1606 opset(AFNMADDS, r0) 1607 opset(AFNMADDSCC, r0) 1608 opset(AFNMSUB, r0) 1609 opset(AFNMSUBCC, r0) 1610 opset(AFNMSUBS, r0) 1611 opset(AFNMSUBSCC, r0) 1612 opset(AFSEL, r0) 1613 opset(AFSELCC, r0) 1614 1615 case AFMUL: 1616 opset(AFMULS, r0) 1617 opset(AFMULCC, r0) 1618 opset(AFMULSCC, r0) 1619 1620 case AFCMPO: 1621 opset(AFCMPU, r0) 1622 1623 case AISEL: 1624 opset(AISEL, r0) 1625 1626 case AMTFSB0: 1627 opset(AMTFSB0CC, r0) 1628 opset(AMTFSB1, r0) 1629 opset(AMTFSB1CC, r0) 1630 1631 case ANEG: /* op [Ra,] Rd */ 1632 opset(ANEGCC, r0) 1633 1634 opset(ANEGV, r0) 1635 opset(ANEGVCC, r0) 1636 1637 case AOR: /* or/xor Rb,Rs,Ra; ori/xori $uimm,Rs,Ra; oris/xoris $uimm,Rs,Ra */ 1638 opset(AXOR, r0) 1639 1640 case ASLW: 1641 opset(ASLWCC, r0) 1642 opset(ASRW, r0) 1643 opset(ASRWCC, r0) 1644 1645 case ASLD: 1646 opset(ASLDCC, r0) 1647 opset(ASRD, r0) 1648 opset(ASRDCC, r0) 1649 1650 case ASRAW: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1651 opset(ASRAWCC, r0) 1652 1653 case ASRAD: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1654 opset(ASRADCC, r0) 1655 1656 case ASUB: /* SUB Ra,Rb,Rd => subf Rd,ra,rb */ 1657 opset(ASUB, r0) 1658 1659 opset(ASUBCC, r0) 1660 opset(ASUBV, r0) 1661 opset(ASUBVCC, r0) 1662 opset(ASUBCCC, r0) 1663 opset(ASUBCV, r0) 1664 opset(ASUBCVCC, r0) 1665 opset(ASUBE, r0) 1666 opset(ASUBECC, r0) 1667 opset(ASUBEV, r0) 1668 opset(ASUBEVCC, r0) 1669 1670 case ASYNC: 1671 opset(AISYNC, r0) 1672 opset(ALWSYNC, r0) 1673 opset(APTESYNC, r0) 1674 opset(ATLBSYNC, r0) 1675 1676 case ARLWMI: 1677 opset(ARLWMICC, r0) 1678 opset(ARLWNM, r0) 1679 opset(ARLWNMCC, r0) 1680 1681 case ARLDMI: 1682 opset(ARLDMICC, r0) 1683 opset(ARLDIMI, r0) 1684 opset(ARLDIMICC, r0) 1685 1686 case ARLDC: 1687 opset(ARLDCCC, r0) 1688 1689 case ARLDCL: 1690 opset(ARLDCR, r0) 1691 opset(ARLDCLCC, r0) 1692 opset(ARLDCRCC, r0) 1693 1694 case ARLDICL: 1695 opset(ARLDICLCC, r0) 1696 opset(ARLDICR, r0) 1697 opset(ARLDICRCC, r0) 1698 1699 case AFMOVD: 1700 opset(AFMOVDCC, r0) 1701 opset(AFMOVDU, r0) 1702 opset(AFMOVS, r0) 1703 opset(AFMOVSU, r0) 1704 1705 case AECIWX: 1706 opset(ALBAR, r0) 1707 opset(ALWAR, r0) 1708 opset(ALDAR, r0) 1709 1710 case ASYSCALL: /* just the op; flow of control */ 1711 opset(ARFI, r0) 1712 1713 opset(ARFCI, r0) 1714 opset(ARFID, r0) 1715 opset(AHRFID, r0) 1716 1717 case AMOVHBR: 1718 opset(AMOVWBR, r0) 1719 opset(AMOVDBR, r0) 1720 1721 case ASLBMFEE: 1722 opset(ASLBMFEV, r0) 1723 1724 case ATW: 1725 opset(ATD, r0) 1726 1727 case ATLBIE: 1728 opset(ASLBIE, r0) 1729 opset(ATLBIEL, r0) 1730 1731 case AEIEIO: 1732 opset(ASLBIA, r0) 1733 1734 case ACMP: 1735 opset(ACMPW, r0) 1736 1737 case ACMPU: 1738 opset(ACMPWU, r0) 1739 1740 case ACMPB: 1741 opset(ACMPB, r0) 1742 1743 case AFTDIV: 1744 opset(AFTDIV, r0) 1745 1746 case AFTSQRT: 1747 opset(AFTSQRT, r0) 1748 1749 case AADD, 1750 AANDCC, /* and. Rb,Rs,Ra; andi. $uimm,Rs,Ra; andis. $uimm,Rs,Ra */ 1751 AFMOVSX, 1752 AFMOVSZ, 1753 ALSW, 1754 AMOVW, 1755 /* load/store/move word with sign extension; special 32-bit move; move 32-bit literals */ 1756 AMOVWZ, /* load/store/move word with zero extension; move 32-bit literals */ 1757 AMOVD, /* load/store/move 64-bit values, including 32-bit literals with/without sign-extension */ 1758 AMOVB, /* macro: move byte with sign extension */ 1759 AMOVBU, /* macro: move byte with sign extension & update */ 1760 AMOVFL, 1761 AMULLW, 1762 /* op $s[,r2],r3; op r1[,r2],r3; no cc/v */ 1763 ASUBC, /* op r1,$s,r3; op r1[,r2],r3 */ 1764 ASTSW, 1765 ASLBMTE, 1766 AWORD, 1767 ADWORD, 1768 obj.ANOP, 1769 obj.ATEXT, 1770 obj.AUNDEF, 1771 obj.AUSEFIELD, 1772 obj.AFUNCDATA, 1773 obj.APCDATA, 1774 obj.ADUFFZERO, 1775 obj.ADUFFCOPY: 1776 break 1777 } 1778 } 1779 } 1780 1781 func OPVXX1(o uint32, xo uint32, oe uint32) uint32 { 1782 return o<<26 | xo<<1 | oe<<11 1783 } 1784 1785 func OPVXX2(o uint32, xo uint32, oe uint32) uint32 { 1786 return o<<26 | xo<<2 | oe<<11 1787 } 1788 1789 func OPVXX3(o uint32, xo uint32, oe uint32) uint32 { 1790 return o<<26 | xo<<3 | oe<<11 1791 } 1792 1793 func OPVXX4(o uint32, xo uint32, oe uint32) uint32 { 1794 return o<<26 | xo<<4 | oe<<11 1795 } 1796 1797 func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1798 return o<<26 | xo | oe<<11 | rc&1 1799 } 1800 1801 func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1802 return o<<26 | xo | oe<<11 | (rc&1)<<10 1803 } 1804 1805 func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1806 return o<<26 | xo<<1 | oe<<10 | rc&1 1807 } 1808 1809 func OPCC(o uint32, xo uint32, rc uint32) uint32 { 1810 return OPVCC(o, xo, 0, rc) 1811 } 1812 1813 func OP(o uint32, xo uint32) uint32 { 1814 return OPVCC(o, xo, 0, 0) 1815 } 1816 1817 /* the order is dest, a/s, b/imm for both arithmetic and logical operations */ 1818 func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 { 1819 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 1820 } 1821 1822 /* VX-form 2-register operands, r/none/r */ 1823 func AOP_RR(op uint32, d uint32, a uint32) uint32 { 1824 return op | (d&31)<<21 | (a&31)<<11 1825 } 1826 1827 /* VA-form 4-register operands */ 1828 func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1829 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6 1830 } 1831 1832 func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1833 return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF 1834 } 1835 1836 /* VX-form 2-register + UIM operands */ 1837 func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1838 return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11 1839 } 1840 1841 /* VX-form 2-register + ST + SIX operands */ 1842 func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 { 1843 return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11 1844 } 1845 1846 /* VA-form 3-register + SHB operands */ 1847 func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 { 1848 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6 1849 } 1850 1851 /* VX-form 1-register + SIM operands */ 1852 func AOP_IR(op uint32, d uint32, simm uint32) uint32 { 1853 return op | (d&31)<<21 | (simm&31)<<16 1854 } 1855 1856 /* XX1-form 3-register operands, 1 VSR operand */ 1857 func AOP_XX1(op uint32, d uint32, a uint32, b uint32) uint32 { 1858 /* For the XX-form encodings, we need the VSX register number to be exactly */ 1859 /* between 0-63, so we can properly set the rightmost bits. */ 1860 r := d - REG_VS0 1861 return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5 1862 } 1863 1864 /* XX2-form 3-register operands, 2 VSR operands */ 1865 func AOP_XX2(op uint32, d uint32, a uint32, b uint32) uint32 { 1866 xt := d - REG_VS0 1867 xb := b - REG_VS0 1868 return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5 1869 } 1870 1871 /* XX3-form 3 VSR operands */ 1872 func AOP_XX3(op uint32, d uint32, a uint32, b uint32) uint32 { 1873 xt := d - REG_VS0 1874 xa := a - REG_VS0 1875 xb := b - REG_VS0 1876 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1877 } 1878 1879 /* XX3-form 3 VSR operands + immediate */ 1880 func AOP_XX3I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1881 xt := d - REG_VS0 1882 xa := a - REG_VS0 1883 xb := b - REG_VS0 1884 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1885 } 1886 1887 /* XX4-form, 4 VSR operands */ 1888 func AOP_XX4(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1889 xt := d - REG_VS0 1890 xa := a - REG_VS0 1891 xb := b - REG_VS0 1892 xc := c - REG_VS0 1893 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1894 } 1895 1896 func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 { 1897 return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11 1898 } 1899 1900 func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 { 1901 return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF 1902 } 1903 1904 func OP_BR(op uint32, li uint32, aa uint32) uint32 { 1905 return op | li&0x03FFFFFC | aa<<1 1906 } 1907 1908 func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 { 1909 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1 1910 } 1911 1912 func OP_BCR(op uint32, bo uint32, bi uint32) uint32 { 1913 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 1914 } 1915 1916 func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 { 1917 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1 1918 } 1919 1920 func AOP_RLDIC(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 { 1921 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5 1922 } 1923 1924 func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 { 1925 return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6 1926 } 1927 1928 const ( 1929 /* each rhs is OPVCC(_, _, _, _) */ 1930 OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0 1931 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0 1932 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0 1933 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0 1934 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0 1935 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0 1936 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0 1937 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0 1938 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0 1939 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0 1940 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0 1941 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0 1942 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0 1943 OP_MFMSR = 31<<26 | 83<<1 | 0<<10 | 0 1944 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0 1945 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0 1946 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0 1947 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0 1948 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0 1949 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0 1950 OP_MTMSR = 31<<26 | 146<<1 | 0<<10 | 0 1951 OP_MTMSRD = 31<<26 | 178<<1 | 0<<10 | 0 1952 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0 1953 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0 1954 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0 1955 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0 1956 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0 1957 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0 1958 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0 1959 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0 1960 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0 1961 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0 1962 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0 1963 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0 1964 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0 1965 ) 1966 1967 func oclass(a *obj.Addr) int { 1968 return int(a.Class) - 1 1969 } 1970 1971 const ( 1972 D_FORM = iota 1973 DS_FORM 1974 ) 1975 1976 // opform returns the form (D_FORM or DS_FORM) of an instruction. Used to decide on 1977 // which relocation to use with a load or store and only supports the needed 1978 // instructions. 1979 func opform(ctxt *obj.Link, insn uint32) int { 1980 switch insn { 1981 default: 1982 ctxt.Diag("bad insn in loadform: %x", insn) 1983 case OPVCC(58, 0, 0, 0), // ld 1984 OPVCC(58, 0, 0, 0) | 1<<1, // lwa 1985 OPVCC(62, 0, 0, 0): // std 1986 return DS_FORM 1987 case OP_ADDI, // add 1988 OPVCC(32, 0, 0, 0), // lwz 1989 OPVCC(42, 0, 0, 0), // lha 1990 OPVCC(40, 0, 0, 0), // lhz 1991 OPVCC(34, 0, 0, 0), // lbz 1992 OPVCC(50, 0, 0, 0), // lfd 1993 OPVCC(48, 0, 0, 0), // lfs 1994 OPVCC(36, 0, 0, 0), // stw 1995 OPVCC(44, 0, 0, 0), // sth 1996 OPVCC(38, 0, 0, 0), // stb 1997 OPVCC(54, 0, 0, 0), // stfd 1998 OPVCC(52, 0, 0, 0): // stfs 1999 return D_FORM 2000 } 2001 return 0 2002 } 2003 2004 // Encode instructions and create relocation for accessing s+d according to the 2005 // instruction op with source or destination (as appropriate) register reg. 2006 func symbolAccess(ctxt *obj.Link, s *obj.LSym, d int64, reg int16, op uint32) (o1, o2 uint32) { 2007 var base uint32 2008 form := opform(ctxt, op) 2009 if ctxt.Flag_shared { 2010 base = REG_R2 2011 } else { 2012 base = REG_R0 2013 } 2014 o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0) 2015 o2 = AOP_IRR(op, uint32(reg), REGTMP, 0) 2016 rel := obj.Addrel(ctxt.Cursym) 2017 rel.Off = int32(ctxt.Pc) 2018 rel.Siz = 8 2019 rel.Sym = s 2020 rel.Add = d 2021 if ctxt.Flag_shared { 2022 switch form { 2023 case D_FORM: 2024 rel.Type = obj.R_ADDRPOWER_TOCREL 2025 case DS_FORM: 2026 rel.Type = obj.R_ADDRPOWER_TOCREL_DS 2027 } 2028 2029 } else { 2030 switch form { 2031 case D_FORM: 2032 rel.Type = obj.R_ADDRPOWER 2033 case DS_FORM: 2034 rel.Type = obj.R_ADDRPOWER_DS 2035 } 2036 } 2037 return 2038 } 2039 2040 /* 2041 * 32-bit masks 2042 */ 2043 func getmask(m []byte, v uint32) bool { 2044 m[1] = 0 2045 m[0] = m[1] 2046 if v != ^uint32(0) && v&(1<<31) != 0 && v&1 != 0 { /* MB > ME */ 2047 if getmask(m, ^v) { 2048 i := int(m[0]) 2049 m[0] = m[1] + 1 2050 m[1] = byte(i - 1) 2051 return true 2052 } 2053 2054 return false 2055 } 2056 2057 for i := 0; i < 32; i++ { 2058 if v&(1<<uint(31-i)) != 0 { 2059 m[0] = byte(i) 2060 for { 2061 m[1] = byte(i) 2062 i++ 2063 if i >= 32 || v&(1<<uint(31-i)) == 0 { 2064 break 2065 } 2066 } 2067 2068 for ; i < 32; i++ { 2069 if v&(1<<uint(31-i)) != 0 { 2070 return false 2071 } 2072 } 2073 return true 2074 } 2075 } 2076 2077 return false 2078 } 2079 2080 func maskgen(ctxt *obj.Link, p *obj.Prog, m []byte, v uint32) { 2081 if !getmask(m, v) { 2082 ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2083 } 2084 } 2085 2086 /* 2087 * 64-bit masks (rldic etc) 2088 */ 2089 func getmask64(m []byte, v uint64) bool { 2090 m[1] = 0 2091 m[0] = m[1] 2092 for i := 0; i < 64; i++ { 2093 if v&(uint64(1)<<uint(63-i)) != 0 { 2094 m[0] = byte(i) 2095 for { 2096 m[1] = byte(i) 2097 i++ 2098 if i >= 64 || v&(uint64(1)<<uint(63-i)) == 0 { 2099 break 2100 } 2101 } 2102 2103 for ; i < 64; i++ { 2104 if v&(uint64(1)<<uint(63-i)) != 0 { 2105 return false 2106 } 2107 } 2108 return true 2109 } 2110 } 2111 2112 return false 2113 } 2114 2115 func maskgen64(ctxt *obj.Link, p *obj.Prog, m []byte, v uint64) { 2116 if !getmask64(m, v) { 2117 ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2118 } 2119 } 2120 2121 func loadu32(r int, d int64) uint32 { 2122 v := int32(d >> 16) 2123 if isuint32(uint64(d)) { 2124 return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v)) 2125 } 2126 return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v)) 2127 } 2128 2129 func high16adjusted(d int32) uint16 { 2130 if d&0x8000 != 0 { 2131 return uint16((d >> 16) + 1) 2132 } 2133 return uint16(d >> 16) 2134 } 2135 2136 func asmout(ctxt *obj.Link, p *obj.Prog, o *Optab, out []uint32) { 2137 o1 := uint32(0) 2138 o2 := uint32(0) 2139 o3 := uint32(0) 2140 o4 := uint32(0) 2141 o5 := uint32(0) 2142 2143 //print("%v => case %d\n", p, o->type); 2144 switch o.type_ { 2145 default: 2146 ctxt.Diag("unknown type %d", o.type_) 2147 prasm(p) 2148 2149 case 0: /* pseudo ops */ 2150 break 2151 2152 case 1: /* mov r1,r2 ==> OR Rs,Rs,Ra */ 2153 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2154 v := regoff(ctxt, &p.From) 2155 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2156 //nerrors--; 2157 ctxt.Diag("literal operation on R0\n%v", p) 2158 } 2159 2160 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2161 break 2162 } 2163 2164 o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg)) 2165 2166 case 2: /* int/cr/fp op Rb,[Ra],Rd */ 2167 r := int(p.Reg) 2168 2169 if r == 0 { 2170 r = int(p.To.Reg) 2171 } 2172 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2173 2174 case 3: /* mov $soreg/addcon/ucon, r ==> addis/addi $i,reg',r */ 2175 d := vregoff(ctxt, &p.From) 2176 2177 v := int32(d) 2178 r := int(p.From.Reg) 2179 if r == 0 { 2180 r = int(o.param) 2181 } 2182 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 && (r != 0 || v != 0) { 2183 ctxt.Diag("literal operation on R0\n%v", p) 2184 } 2185 a := OP_ADDI 2186 if o.a1 == C_UCON { 2187 if d&0xffff != 0 { 2188 log.Fatalf("invalid handling of %v", p) 2189 } 2190 v >>= 16 2191 if r == REGZERO && isuint32(uint64(d)) { 2192 o1 = LOP_IRR(OP_ORIS, uint32(p.To.Reg), REGZERO, uint32(v)) 2193 break 2194 } 2195 2196 a = OP_ADDIS 2197 } else { 2198 if int64(int16(d)) != d { 2199 log.Fatalf("invalid handling of %v", p) 2200 } 2201 } 2202 2203 o1 = AOP_IRR(uint32(a), uint32(p.To.Reg), uint32(r), uint32(v)) 2204 2205 case 4: /* add/mul $scon,[r1],r2 */ 2206 v := regoff(ctxt, &p.From) 2207 2208 r := int(p.Reg) 2209 if r == 0 { 2210 r = int(p.To.Reg) 2211 } 2212 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 { 2213 ctxt.Diag("literal operation on R0\n%v", p) 2214 } 2215 if int32(int16(v)) != v { 2216 log.Fatalf("mishandled instruction %v", p) 2217 } 2218 o1 = AOP_IRR(opirr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2219 2220 case 5: /* syscall */ 2221 o1 = oprrr(ctxt, p.As) 2222 2223 case 6: /* logical op Rb,[Rs,]Ra; no literal */ 2224 r := int(p.Reg) 2225 2226 if r == 0 { 2227 r = int(p.To.Reg) 2228 } 2229 o1 = LOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2230 2231 case 7: /* mov r, soreg ==> stw o(r) */ 2232 r := int(p.To.Reg) 2233 2234 if r == 0 { 2235 r = int(o.param) 2236 } 2237 v := regoff(ctxt, &p.To) 2238 if p.To.Type == obj.TYPE_MEM && p.To.Index != 0 { 2239 if v != 0 { 2240 ctxt.Diag("illegal indexed instruction\n%v", p) 2241 } 2242 if ctxt.Flag_shared && r == REG_R13 { 2243 rel := obj.Addrel(ctxt.Cursym) 2244 rel.Off = int32(ctxt.Pc) 2245 rel.Siz = 4 2246 // This (and the matching part in the load case 2247 // below) are the only places in the ppc64 toolchain 2248 // that knows the name of the tls variable. Possibly 2249 // we could add some assembly syntax so that the name 2250 // of the variable does not have to be assumed. 2251 rel.Sym = obj.Linklookup(ctxt, "runtime.tls_g", 0) 2252 rel.Type = obj.R_POWER_TLS 2253 } 2254 o1 = AOP_RRR(opstorex(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r)) 2255 } else { 2256 if int32(int16(v)) != v { 2257 log.Fatalf("mishandled instruction %v", p) 2258 } 2259 o1 = AOP_IRR(opstore(ctxt, p.As), uint32(p.From.Reg), uint32(r), uint32(v)) 2260 } 2261 2262 case 8: /* mov soreg, r ==> lbz/lhz/lwz o(r) */ 2263 r := int(p.From.Reg) 2264 2265 if r == 0 { 2266 r = int(o.param) 2267 } 2268 v := regoff(ctxt, &p.From) 2269 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2270 if v != 0 { 2271 ctxt.Diag("illegal indexed instruction\n%v", p) 2272 } 2273 if ctxt.Flag_shared && r == REG_R13 { 2274 rel := obj.Addrel(ctxt.Cursym) 2275 rel.Off = int32(ctxt.Pc) 2276 rel.Siz = 4 2277 rel.Sym = obj.Linklookup(ctxt, "runtime.tls_g", 0) 2278 rel.Type = obj.R_POWER_TLS 2279 } 2280 o1 = AOP_RRR(oploadx(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2281 } else { 2282 if int32(int16(v)) != v { 2283 log.Fatalf("mishandled instruction %v", p) 2284 } 2285 o1 = AOP_IRR(opload(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2286 } 2287 2288 case 9: /* movb soreg, r ==> lbz o(r),r2; extsb r2,r2 */ 2289 r := int(p.From.Reg) 2290 2291 if r == 0 { 2292 r = int(o.param) 2293 } 2294 v := regoff(ctxt, &p.From) 2295 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2296 if v != 0 { 2297 ctxt.Diag("illegal indexed instruction\n%v", p) 2298 } 2299 o1 = AOP_RRR(oploadx(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2300 } else { 2301 o1 = AOP_IRR(opload(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2302 } 2303 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2304 2305 case 10: /* sub Ra,[Rb],Rd => subf Rd,Ra,Rb */ 2306 r := int(p.Reg) 2307 2308 if r == 0 { 2309 r = int(p.To.Reg) 2310 } 2311 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r)) 2312 2313 case 11: /* br/bl lbra */ 2314 v := int32(0) 2315 2316 if p.Pcond != nil { 2317 v = int32(p.Pcond.Pc - p.Pc) 2318 if v&03 != 0 { 2319 ctxt.Diag("odd branch target address\n%v", p) 2320 v &^= 03 2321 } 2322 2323 if v < -(1<<25) || v >= 1<<24 { 2324 ctxt.Diag("branch too far\n%v", p) 2325 } 2326 } 2327 2328 o1 = OP_BR(opirr(ctxt, p.As), uint32(v), 0) 2329 if p.To.Sym != nil { 2330 rel := obj.Addrel(ctxt.Cursym) 2331 rel.Off = int32(ctxt.Pc) 2332 rel.Siz = 4 2333 rel.Sym = p.To.Sym 2334 v += int32(p.To.Offset) 2335 if v&03 != 0 { 2336 ctxt.Diag("odd branch target address\n%v", p) 2337 v &^= 03 2338 } 2339 2340 rel.Add = int64(v) 2341 rel.Type = obj.R_CALLPOWER 2342 } 2343 o2 = 0x60000000 // nop, sometimes overwritten by ld r2, 24(r1) when dynamic linking 2344 2345 case 12: /* movb r,r (extsb); movw r,r (extsw) */ 2346 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2347 v := regoff(ctxt, &p.From) 2348 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2349 ctxt.Diag("literal operation on R0\n%v", p) 2350 } 2351 2352 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2353 break 2354 } 2355 2356 if p.As == AMOVW { 2357 o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2358 } else { 2359 o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2360 } 2361 2362 case 13: /* mov[bhw]z r,r; uses rlwinm not andi. to avoid changing CC */ 2363 if p.As == AMOVBZ { 2364 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31) 2365 } else if p.As == AMOVH { 2366 o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2367 } else if p.As == AMOVHZ { 2368 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31) 2369 } else if p.As == AMOVWZ { 2370 o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5 /* MB=32 */ 2371 } else { 2372 ctxt.Diag("internal: bad mov[bhw]z\n%v", p) 2373 } 2374 2375 case 14: /* rldc[lr] Rb,Rs,$mask,Ra -- left, right give different masks */ 2376 r := int(p.Reg) 2377 2378 if r == 0 { 2379 r = int(p.To.Reg) 2380 } 2381 d := vregoff(ctxt, p.From3) 2382 var a int 2383 switch p.As { 2384 2385 // These opcodes expect a mask operand that has to be converted into the 2386 // appropriate operand. The way these were defined, not all valid masks are possible. 2387 // Left here for compatibility in case they were used or generated. 2388 case ARLDCL, ARLDCLCC: 2389 var mask [2]uint8 2390 maskgen64(ctxt, p, mask[:], uint64(d)) 2391 2392 a = int(mask[0]) /* MB */ 2393 if mask[1] != 63 { 2394 ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p) 2395 } 2396 o1 = LOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2397 o1 |= (uint32(a) & 31) << 6 2398 if a&0x20 != 0 { 2399 o1 |= 1 << 5 /* mb[5] is top bit */ 2400 } 2401 2402 case ARLDCR, ARLDCRCC: 2403 var mask [2]uint8 2404 maskgen64(ctxt, p, mask[:], uint64(d)) 2405 2406 a = int(mask[1]) /* ME */ 2407 if mask[0] != 0 { 2408 ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p) 2409 } 2410 o1 = LOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2411 o1 |= (uint32(a) & 31) << 6 2412 if a&0x20 != 0 { 2413 o1 |= 1 << 5 /* mb[5] is top bit */ 2414 } 2415 2416 // These opcodes use a shift count like the ppc64 asm, no mask conversion done 2417 case ARLDICR, ARLDICRCC: 2418 me := int(d) 2419 sh := regoff(ctxt, &p.From) 2420 o1 = AOP_RLDIC(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(me)) 2421 2422 case ARLDICL, ARLDICLCC: 2423 mb := int(d) 2424 sh := regoff(ctxt, &p.From) 2425 o1 = AOP_RLDIC(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(mb)) 2426 2427 default: 2428 ctxt.Diag("unexpected op in rldc case\n%v", p) 2429 a = 0 2430 } 2431 2432 case 17, /* bc bo,bi,lbra (same for now) */ 2433 16: /* bc bo,bi,sbra */ 2434 a := 0 2435 2436 r := int(p.Reg) 2437 2438 if p.From.Type == obj.TYPE_CONST { 2439 a = int(regoff(ctxt, &p.From)) 2440 } else if p.From.Type == obj.TYPE_REG { 2441 if r != 0 { 2442 ctxt.Diag("unexpected register setting for branch with CR: %d\n", r) 2443 } 2444 // BI values for the CR 2445 switch p.From.Reg { 2446 case REG_CR0: 2447 r = BI_CR0 2448 case REG_CR1: 2449 r = BI_CR1 2450 case REG_CR2: 2451 r = BI_CR2 2452 case REG_CR3: 2453 r = BI_CR3 2454 case REG_CR4: 2455 r = BI_CR4 2456 case REG_CR5: 2457 r = BI_CR5 2458 case REG_CR6: 2459 r = BI_CR6 2460 case REG_CR7: 2461 r = BI_CR7 2462 default: 2463 ctxt.Diag("unrecognized register: expecting CR\n") 2464 } 2465 } 2466 v := int32(0) 2467 if p.Pcond != nil { 2468 v = int32(p.Pcond.Pc - p.Pc) 2469 } 2470 if v&03 != 0 { 2471 ctxt.Diag("odd branch target address\n%v", p) 2472 v &^= 03 2473 } 2474 2475 if v < -(1<<16) || v >= 1<<15 { 2476 ctxt.Diag("branch too far\n%v", p) 2477 } 2478 o1 = OP_BC(opirr(ctxt, p.As), uint32(a), uint32(r), uint32(v), 0) 2479 2480 case 15: /* br/bl (r) => mov r,lr; br/bl (lr) */ 2481 var v int32 2482 if p.As == ABC || p.As == ABCL { 2483 v = regoff(ctxt, &p.To) & 31 2484 } else { 2485 v = 20 /* unconditional */ 2486 } 2487 o1 = AOP_RRR(OP_MTSPR, uint32(p.To.Reg), 0, 0) | (REG_LR&0x1f)<<16 | ((REG_LR>>5)&0x1f)<<11 2488 o2 = OPVCC(19, 16, 0, 0) 2489 if p.As == ABL || p.As == ABCL { 2490 o2 |= 1 2491 } 2492 o2 = OP_BCR(o2, uint32(v), uint32(p.To.Index)) 2493 2494 case 18: /* br/bl (lr/ctr); bc/bcl bo,bi,(lr/ctr) */ 2495 var v int32 2496 if p.As == ABC || p.As == ABCL { 2497 v = regoff(ctxt, &p.From) & 31 2498 } else { 2499 v = 20 /* unconditional */ 2500 } 2501 r := int(p.Reg) 2502 if r == 0 { 2503 r = 0 2504 } 2505 switch oclass(&p.To) { 2506 case C_CTR: 2507 o1 = OPVCC(19, 528, 0, 0) 2508 2509 case C_LR: 2510 o1 = OPVCC(19, 16, 0, 0) 2511 2512 default: 2513 ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p) 2514 v = 0 2515 } 2516 2517 if p.As == ABL || p.As == ABCL { 2518 o1 |= 1 2519 } 2520 o1 = OP_BCR(o1, uint32(v), uint32(r)) 2521 2522 case 19: /* mov $lcon,r ==> cau+or */ 2523 d := vregoff(ctxt, &p.From) 2524 2525 if p.From.Sym == nil { 2526 o1 = loadu32(int(p.To.Reg), d) 2527 o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d))) 2528 } else { 2529 o1, o2 = symbolAccess(ctxt, p.From.Sym, d, p.To.Reg, OP_ADDI) 2530 } 2531 2532 //if(dlm) reloc(&p->from, p->pc, 0); 2533 2534 case 20: /* add $ucon,,r */ 2535 v := regoff(ctxt, &p.From) 2536 2537 r := int(p.Reg) 2538 if r == 0 { 2539 r = int(p.To.Reg) 2540 } 2541 if p.As == AADD && (r0iszero == 0 /*TypeKind(100016)*/ && p.Reg == 0 || r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0) { 2542 ctxt.Diag("literal operation on R0\n%v", p) 2543 } 2544 o1 = AOP_IRR(opirr(ctxt, -p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) 2545 2546 case 22: /* add $lcon,r1,r2 ==> cau+or+add */ /* could do add/sub more efficiently */ 2547 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2548 ctxt.Diag("can't synthesize large constant\n%v", p) 2549 } 2550 d := vregoff(ctxt, &p.From) 2551 o1 = loadu32(REGTMP, d) 2552 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2553 r := int(p.Reg) 2554 if r == 0 { 2555 r = int(p.To.Reg) 2556 } 2557 o3 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2558 if p.From.Sym != nil { 2559 ctxt.Diag("%v is not supported", p) 2560 } 2561 2562 //if(dlm) reloc(&p->from, p->pc, 0); 2563 2564 case 23: /* and $lcon,r1,r2 ==> cau+or+and */ /* masks could be done using rlnm etc. */ 2565 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2566 ctxt.Diag("can't synthesize large constant\n%v", p) 2567 } 2568 d := vregoff(ctxt, &p.From) 2569 o1 = loadu32(REGTMP, d) 2570 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2571 r := int(p.Reg) 2572 if r == 0 { 2573 r = int(p.To.Reg) 2574 } 2575 o3 = LOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2576 if p.From.Sym != nil { 2577 ctxt.Diag("%v is not supported", p) 2578 } 2579 2580 //if(dlm) reloc(&p->from, p->pc, 0); 2581 2582 /*24*/ 2583 case 25: 2584 /* sld[.] $sh,rS,rA -> rldicr[.] $sh,rS,mask(0,63-sh),rA; srd[.] -> rldicl */ 2585 v := regoff(ctxt, &p.From) 2586 2587 if v < 0 { 2588 v = 0 2589 } else if v > 63 { 2590 v = 63 2591 } 2592 r := int(p.Reg) 2593 if r == 0 { 2594 r = int(p.To.Reg) 2595 } 2596 var a int 2597 switch p.As { 2598 case ASLD, ASLDCC: 2599 a = int(63 - v) 2600 o1 = OP_RLDICR 2601 2602 case ASRD, ASRDCC: 2603 a = int(v) 2604 v = 64 - v 2605 o1 = OP_RLDICL 2606 2607 default: 2608 ctxt.Diag("unexpected op in sldi case\n%v", p) 2609 a = 0 2610 o1 = 0 2611 } 2612 2613 o1 = AOP_RRR(o1, uint32(r), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2614 o1 |= (uint32(a) & 31) << 6 2615 if v&0x20 != 0 { 2616 o1 |= 1 << 1 2617 } 2618 if a&0x20 != 0 { 2619 o1 |= 1 << 5 /* mb[5] is top bit */ 2620 } 2621 if p.As == ASLDCC || p.As == ASRDCC { 2622 o1 |= 1 /* Rc */ 2623 } 2624 2625 case 26: /* mov $lsext/auto/oreg,,r2 ==> addis+addi */ 2626 if p.To.Reg == REGTMP { 2627 ctxt.Diag("can't synthesize large constant\n%v", p) 2628 } 2629 v := regoff(ctxt, &p.From) 2630 r := int(p.From.Reg) 2631 if r == 0 { 2632 r = int(o.param) 2633 } 2634 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2635 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGTMP, uint32(v)) 2636 2637 case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */ 2638 v := regoff(ctxt, p.From3) 2639 2640 r := int(p.From.Reg) 2641 o1 = AOP_IRR(opirr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2642 2643 case 28: /* subc r1,$lcon,r2 ==> cau+or+subfc */ 2644 if p.To.Reg == REGTMP || p.From.Reg == REGTMP { 2645 ctxt.Diag("can't synthesize large constant\n%v", p) 2646 } 2647 v := regoff(ctxt, p.From3) 2648 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16) 2649 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(v)) 2650 o3 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP) 2651 if p.From.Sym != nil { 2652 ctxt.Diag("%v is not supported", p) 2653 } 2654 2655 //if(dlm) reloc(&p->from3, p->pc, 0); 2656 2657 case 29: /* rldic[lr]? $sh,s,$mask,a -- left, right, plain give different masks */ 2658 v := regoff(ctxt, &p.From) 2659 2660 d := vregoff(ctxt, p.From3) 2661 var mask [2]uint8 2662 maskgen64(ctxt, p, mask[:], uint64(d)) 2663 var a int 2664 switch p.As { 2665 case ARLDC, ARLDCCC: 2666 a = int(mask[0]) /* MB */ 2667 if int32(mask[1]) != (63 - v) { 2668 ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2669 } 2670 2671 case ARLDCL, ARLDCLCC: 2672 a = int(mask[0]) /* MB */ 2673 if mask[1] != 63 { 2674 ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2675 } 2676 2677 case ARLDCR, ARLDCRCC: 2678 a = int(mask[1]) /* ME */ 2679 if mask[0] != 0 { 2680 ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2681 } 2682 2683 default: 2684 ctxt.Diag("unexpected op in rldic case\n%v", p) 2685 a = 0 2686 } 2687 2688 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2689 o1 |= (uint32(a) & 31) << 6 2690 if v&0x20 != 0 { 2691 o1 |= 1 << 1 2692 } 2693 if a&0x20 != 0 { 2694 o1 |= 1 << 5 /* mb[5] is top bit */ 2695 } 2696 2697 case 30: /* rldimi $sh,s,$mask,a */ 2698 v := regoff(ctxt, &p.From) 2699 2700 d := vregoff(ctxt, p.From3) 2701 2702 // Original opcodes had mask operands which had to be converted to a shift count as expected by 2703 // the ppc64 asm. 2704 switch p.As { 2705 case ARLDMI, ARLDMICC: 2706 var mask [2]uint8 2707 maskgen64(ctxt, p, mask[:], uint64(d)) 2708 if int32(mask[1]) != (63 - v) { 2709 ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2710 } 2711 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2712 o1 |= (uint32(mask[0]) & 31) << 6 2713 if v&0x20 != 0 { 2714 o1 |= 1 << 1 2715 } 2716 if mask[0]&0x20 != 0 { 2717 o1 |= 1 << 5 /* mb[5] is top bit */ 2718 } 2719 2720 // Opcodes with shift count operands. 2721 case ARLDIMI, ARLDIMICC: 2722 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2723 o1 |= (uint32(d) & 31) << 6 2724 if v&0x20 != 0 { 2725 o1 |= 1 << 1 2726 } 2727 } 2728 2729 case 31: /* dword */ 2730 d := vregoff(ctxt, &p.From) 2731 2732 if ctxt.Arch.ByteOrder == binary.BigEndian { 2733 o1 = uint32(d >> 32) 2734 o2 = uint32(d) 2735 } else { 2736 o1 = uint32(d) 2737 o2 = uint32(d >> 32) 2738 } 2739 2740 if p.From.Sym != nil { 2741 rel := obj.Addrel(ctxt.Cursym) 2742 rel.Off = int32(ctxt.Pc) 2743 rel.Siz = 8 2744 rel.Sym = p.From.Sym 2745 rel.Add = p.From.Offset 2746 rel.Type = obj.R_ADDR 2747 o2 = 0 2748 o1 = o2 2749 } 2750 2751 case 32: /* fmul frc,fra,frd */ 2752 r := int(p.Reg) 2753 2754 if r == 0 { 2755 r = int(p.To.Reg) 2756 } 2757 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6 2758 2759 case 33: /* fabs [frb,]frd; fmr. frb,frd */ 2760 r := int(p.From.Reg) 2761 2762 if oclass(&p.From) == C_NONE { 2763 r = int(p.To.Reg) 2764 } 2765 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), 0, uint32(r)) 2766 2767 case 34: /* FMADDx fra,frb,frc,frd (d=a*b+c); FSELx a<0? (d=b): (d=c) */ 2768 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.From3.Reg)&31)<<6 2769 2770 case 35: /* mov r,lext/lauto/loreg ==> cau $(v>>16),sb,r'; store o(r') */ 2771 v := regoff(ctxt, &p.To) 2772 2773 r := int(p.To.Reg) 2774 if r == 0 { 2775 r = int(o.param) 2776 } 2777 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2778 o2 = AOP_IRR(opstore(ctxt, p.As), uint32(p.From.Reg), REGTMP, uint32(v)) 2779 2780 case 36: /* mov bz/h/hz lext/lauto/lreg,r ==> lbz/lha/lhz etc */ 2781 v := regoff(ctxt, &p.From) 2782 2783 r := int(p.From.Reg) 2784 if r == 0 { 2785 r = int(o.param) 2786 } 2787 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2788 o2 = AOP_IRR(opload(ctxt, p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2789 2790 case 37: /* movb lext/lauto/lreg,r ==> lbz o(reg),r; extsb r */ 2791 v := regoff(ctxt, &p.From) 2792 2793 r := int(p.From.Reg) 2794 if r == 0 { 2795 r = int(o.param) 2796 } 2797 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2798 o2 = AOP_IRR(opload(ctxt, p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2799 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2800 2801 case 40: /* word */ 2802 o1 = uint32(regoff(ctxt, &p.From)) 2803 2804 case 41: /* stswi */ 2805 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(regoff(ctxt, p.From3))&0x7F)<<11 2806 2807 case 42: /* lswi */ 2808 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(regoff(ctxt, p.From3))&0x7F)<<11 2809 2810 case 43: /* unary indexed source: dcbf (b); dcbf (a+b) */ 2811 o1 = AOP_RRR(oprrr(ctxt, p.As), 0, uint32(p.From.Index), uint32(p.From.Reg)) 2812 2813 case 44: /* indexed store */ 2814 o1 = AOP_RRR(opstorex(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 2815 2816 case 45: /* indexed load */ 2817 o1 = AOP_RRR(oploadx(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 2818 2819 case 46: /* plain op */ 2820 o1 = oprrr(ctxt, p.As) 2821 2822 case 47: /* op Ra, Rd; also op [Ra,] Rd */ 2823 r := int(p.From.Reg) 2824 2825 if r == 0 { 2826 r = int(p.To.Reg) 2827 } 2828 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), 0) 2829 2830 case 48: /* op Rs, Ra */ 2831 r := int(p.From.Reg) 2832 2833 if r == 0 { 2834 r = int(p.To.Reg) 2835 } 2836 o1 = LOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), 0) 2837 2838 case 49: /* op Rb; op $n, Rb */ 2839 if p.From.Type != obj.TYPE_REG { /* tlbie $L, rB */ 2840 v := regoff(ctxt, &p.From) & 1 2841 o1 = AOP_RRR(oprrr(ctxt, p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21 2842 } else { 2843 o1 = AOP_RRR(oprrr(ctxt, p.As), 0, 0, uint32(p.From.Reg)) 2844 } 2845 2846 case 50: /* rem[u] r1[,r2],r3 */ 2847 r := int(p.Reg) 2848 2849 if r == 0 { 2850 r = int(p.To.Reg) 2851 } 2852 v := oprrr(ctxt, p.As) 2853 t := v & (1<<10 | 1) /* OE|Rc */ 2854 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2855 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg)) 2856 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2857 if p.As == AREMU { 2858 o4 = o3 2859 2860 /* Clear top 32 bits */ 2861 o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5 2862 } 2863 2864 case 51: /* remd[u] r1[,r2],r3 */ 2865 r := int(p.Reg) 2866 2867 if r == 0 { 2868 r = int(p.To.Reg) 2869 } 2870 v := oprrr(ctxt, p.As) 2871 t := v & (1<<10 | 1) /* OE|Rc */ 2872 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2873 o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg)) 2874 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2875 2876 case 52: /* mtfsbNx cr(n) */ 2877 v := regoff(ctxt, &p.From) & 31 2878 2879 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(v), 0, 0) 2880 2881 case 53: /* mffsX ,fr1 */ 2882 o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0) 2883 2884 case 54: /* mov msr,r1; mov r1, msr*/ 2885 if oclass(&p.From) == C_REG { 2886 if p.As == AMOVD { 2887 o1 = AOP_RRR(OP_MTMSRD, uint32(p.From.Reg), 0, 0) 2888 } else { 2889 o1 = AOP_RRR(OP_MTMSR, uint32(p.From.Reg), 0, 0) 2890 } 2891 } else { 2892 o1 = AOP_RRR(OP_MFMSR, uint32(p.To.Reg), 0, 0) 2893 } 2894 2895 case 55: /* op Rb, Rd */ 2896 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg)) 2897 2898 case 56: /* sra $sh,[s,]a; srd $sh,[s,]a */ 2899 v := regoff(ctxt, &p.From) 2900 2901 r := int(p.Reg) 2902 if r == 0 { 2903 r = int(p.To.Reg) 2904 } 2905 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31) 2906 if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) { 2907 o1 |= 1 << 1 /* mb[5] */ 2908 } 2909 2910 case 57: /* slw $sh,[s,]a -> rlwinm ... */ 2911 v := regoff(ctxt, &p.From) 2912 2913 r := int(p.Reg) 2914 if r == 0 { 2915 r = int(p.To.Reg) 2916 } 2917 2918 /* 2919 * Let user (gs) shoot himself in the foot. 2920 * qc has already complained. 2921 * 2922 if(v < 0 || v > 31) 2923 ctxt->diag("illegal shift %ld\n%v", v, p); 2924 */ 2925 if v < 0 { 2926 v = 0 2927 } else if v > 32 { 2928 v = 32 2929 } 2930 var mask [2]uint8 2931 if p.As == ASRW || p.As == ASRWCC { /* shift right */ 2932 mask[0] = uint8(v) 2933 mask[1] = 31 2934 v = 32 - v 2935 } else { 2936 mask[0] = 0 2937 mask[1] = uint8(31 - v) 2938 } 2939 2940 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1])) 2941 if p.As == ASLWCC || p.As == ASRWCC { 2942 o1 |= 1 /* Rc */ 2943 } 2944 2945 case 58: /* logical $andcon,[s],a */ 2946 v := regoff(ctxt, &p.From) 2947 2948 r := int(p.Reg) 2949 if r == 0 { 2950 r = int(p.To.Reg) 2951 } 2952 o1 = LOP_IRR(opirr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2953 2954 case 59: /* or/and $ucon,,r */ 2955 v := regoff(ctxt, &p.From) 2956 2957 r := int(p.Reg) 2958 if r == 0 { 2959 r = int(p.To.Reg) 2960 } 2961 o1 = LOP_IRR(opirr(ctxt, -p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) /* oris, xoris, andis */ 2962 2963 case 60: /* tw to,a,b */ 2964 r := int(regoff(ctxt, &p.From) & 31) 2965 2966 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg)) 2967 2968 case 61: /* tw to,a,$simm */ 2969 r := int(regoff(ctxt, &p.From) & 31) 2970 2971 v := regoff(ctxt, &p.To) 2972 o1 = AOP_IRR(opirr(ctxt, p.As), uint32(r), uint32(p.Reg), uint32(v)) 2973 2974 case 62: /* rlwmi $sh,s,$mask,a */ 2975 v := regoff(ctxt, &p.From) 2976 2977 var mask [2]uint8 2978 maskgen(ctxt, p, mask[:], uint32(regoff(ctxt, p.From3))) 2979 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v)) 2980 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 2981 2982 case 63: /* rlwmi b,s,$mask,a */ 2983 var mask [2]uint8 2984 maskgen(ctxt, p, mask[:], uint32(regoff(ctxt, p.From3))) 2985 2986 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(p.From.Reg)) 2987 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 2988 2989 case 64: /* mtfsf fr[, $m] {,fpcsr} */ 2990 var v int32 2991 if p.From3Type() != obj.TYPE_NONE { 2992 v = regoff(ctxt, p.From3) & 255 2993 } else { 2994 v = 255 2995 } 2996 o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11 2997 2998 case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */ 2999 if p.To.Reg == 0 { 3000 ctxt.Diag("must specify FPSCR(n)\n%v", p) 3001 } 3002 o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(regoff(ctxt, &p.From))&31)<<12 3003 3004 case 66: /* mov spr,r1; mov r1,spr, also dcr */ 3005 var r int 3006 var v int32 3007 if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 { 3008 r = int(p.From.Reg) 3009 v = int32(p.To.Reg) 3010 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3011 o1 = OPVCC(31, 451, 0, 0) /* mtdcr */ 3012 } else { 3013 o1 = OPVCC(31, 467, 0, 0) /* mtspr */ 3014 } 3015 } else { 3016 r = int(p.To.Reg) 3017 v = int32(p.From.Reg) 3018 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3019 o1 = OPVCC(31, 323, 0, 0) /* mfdcr */ 3020 } else { 3021 o1 = OPVCC(31, 339, 0, 0) /* mfspr */ 3022 } 3023 } 3024 3025 o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11 3026 3027 case 67: /* mcrf crfD,crfS */ 3028 if p.From.Type != obj.TYPE_REG || p.From.Reg < REG_CR0 || REG_CR7 < p.From.Reg || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3029 ctxt.Diag("illegal CR field number\n%v", p) 3030 } 3031 o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0) 3032 3033 case 68: /* mfcr rD; mfocrf CRM,rD */ 3034 if p.From.Type == obj.TYPE_REG && REG_CR0 <= p.From.Reg && p.From.Reg <= REG_CR7 { 3035 v := int32(1 << uint(7-(p.To.Reg&7))) /* CR(n) */ 3036 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) | 1<<20 | uint32(v)<<12 /* new form, mfocrf */ 3037 } else { 3038 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) /* old form, whole register */ 3039 } 3040 3041 case 69: /* mtcrf CRM,rS */ 3042 var v int32 3043 if p.From3Type() != obj.TYPE_NONE { 3044 if p.To.Reg != 0 { 3045 ctxt.Diag("can't use both mask and CR(n)\n%v", p) 3046 } 3047 v = regoff(ctxt, p.From3) & 0xff 3048 } else { 3049 if p.To.Reg == 0 { 3050 v = 0xff /* CR */ 3051 } else { 3052 v = 1 << uint(7-(p.To.Reg&7)) /* CR(n) */ 3053 } 3054 } 3055 3056 o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12 3057 3058 case 70: /* [f]cmp r,r,cr*/ 3059 var r int 3060 if p.Reg == 0 { 3061 r = 0 3062 } else { 3063 r = (int(p.Reg) & 7) << 2 3064 } 3065 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(r), uint32(p.From.Reg), uint32(p.To.Reg)) 3066 3067 case 71: /* cmp[l] r,i,cr*/ 3068 var r int 3069 if p.Reg == 0 { 3070 r = 0 3071 } else { 3072 r = (int(p.Reg) & 7) << 2 3073 } 3074 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(r), uint32(p.From.Reg), 0) | uint32(regoff(ctxt, &p.To))&0xffff 3075 3076 case 72: /* slbmte (Rb+Rs -> slb[Rb]) -> Rs, Rb */ 3077 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg)) 3078 3079 case 73: /* mcrfs crfD,crfS */ 3080 if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3081 ctxt.Diag("illegal FPSCR/CR field number\n%v", p) 3082 } 3083 o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0) 3084 3085 case 77: /* syscall $scon, syscall Rx */ 3086 if p.From.Type == obj.TYPE_CONST { 3087 if p.From.Offset > BIG || p.From.Offset < -BIG { 3088 ctxt.Diag("illegal syscall, sysnum too large: %v", p) 3089 } 3090 o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset)) 3091 } else if p.From.Type == obj.TYPE_REG { 3092 o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg)) 3093 } else { 3094 ctxt.Diag("illegal syscall: %v", p) 3095 o1 = 0x7fe00008 // trap always 3096 } 3097 3098 o2 = oprrr(ctxt, p.As) 3099 o3 = AOP_RRR(oprrr(ctxt, AXOR), REGZERO, REGZERO, REGZERO) // XOR R0, R0 3100 3101 case 78: /* undef */ 3102 o1 = 0 /* "An instruction consisting entirely of binary 0s is guaranteed 3103 always to be an illegal instruction." */ 3104 3105 /* relocation operations */ 3106 case 74: 3107 v := vregoff(ctxt, &p.To) 3108 o1, o2 = symbolAccess(ctxt, p.To.Sym, v, p.From.Reg, opstore(ctxt, p.As)) 3109 3110 //if(dlm) reloc(&p->to, p->pc, 1); 3111 3112 case 75: 3113 v := vregoff(ctxt, &p.From) 3114 o1, o2 = symbolAccess(ctxt, p.From.Sym, v, p.To.Reg, opload(ctxt, p.As)) 3115 3116 //if(dlm) reloc(&p->from, p->pc, 1); 3117 3118 case 76: 3119 v := vregoff(ctxt, &p.From) 3120 o1, o2 = symbolAccess(ctxt, p.From.Sym, v, p.To.Reg, opload(ctxt, p.As)) 3121 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 3122 3123 //if(dlm) reloc(&p->from, p->pc, 1); 3124 3125 case 79: 3126 if p.From.Offset != 0 { 3127 ctxt.Diag("invalid offset against tls var %v", p) 3128 } 3129 o1 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGZERO, 0) 3130 rel := obj.Addrel(ctxt.Cursym) 3131 rel.Off = int32(ctxt.Pc) 3132 rel.Siz = 4 3133 rel.Sym = p.From.Sym 3134 rel.Type = obj.R_POWER_TLS_LE 3135 3136 case 80: 3137 if p.From.Offset != 0 { 3138 ctxt.Diag("invalid offset against tls var %v", p) 3139 } 3140 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3141 o2 = AOP_IRR(opload(ctxt, AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3142 rel := obj.Addrel(ctxt.Cursym) 3143 rel.Off = int32(ctxt.Pc) 3144 rel.Siz = 8 3145 rel.Sym = p.From.Sym 3146 rel.Type = obj.R_POWER_TLS_IE 3147 3148 case 81: 3149 v := vregoff(ctxt, &p.To) 3150 if v != 0 { 3151 ctxt.Diag("invalid offset against GOT slot %v", p) 3152 } 3153 3154 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3155 o2 = AOP_IRR(opload(ctxt, AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3156 rel := obj.Addrel(ctxt.Cursym) 3157 rel.Off = int32(ctxt.Pc) 3158 rel.Siz = 8 3159 rel.Sym = p.From.Sym 3160 rel.Type = obj.R_ADDRPOWER_GOT 3161 case 82: /* vector instructions, VX-form and VC-form */ 3162 if p.From.Type == obj.TYPE_REG { 3163 /* reg reg none OR reg reg reg */ 3164 /* 3-register operand order: VRA, VRB, VRT */ 3165 /* 2-register operand order: VRA, VRT */ 3166 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3167 } else if p.From3Type() == obj.TYPE_CONST { 3168 /* imm imm reg reg */ 3169 /* operand order: SIX, VRA, ST, VRT */ 3170 six := int(regoff(ctxt, &p.From)) 3171 st := int(regoff(ctxt, p.From3)) 3172 o1 = AOP_IIRR(opiirr(ctxt, p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six)) 3173 } else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 { 3174 /* imm reg reg */ 3175 /* operand order: UIM, VRB, VRT */ 3176 uim := int(regoff(ctxt, &p.From)) 3177 o1 = AOP_VIRR(opirr(ctxt, p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim)) 3178 } else { 3179 /* imm reg */ 3180 /* operand order: SIM, VRT */ 3181 sim := int(regoff(ctxt, &p.From)) 3182 o1 = AOP_IR(opirr(ctxt, p.As), uint32(p.To.Reg), uint32(sim)) 3183 } 3184 3185 case 83: /* vector instructions, VA-form */ 3186 if p.From.Type == obj.TYPE_REG { 3187 /* reg reg reg reg */ 3188 /* 4-register operand order: VRA, VRB, VRC, VRT */ 3189 o1 = AOP_RRRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.From3.Reg)) 3190 } else if p.From.Type == obj.TYPE_CONST { 3191 /* imm reg reg reg */ 3192 /* operand order: SHB, VRA, VRB, VRT */ 3193 shb := int(regoff(ctxt, &p.From)) 3194 o1 = AOP_IRRR(opirrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), uint32(shb)) 3195 } 3196 3197 case 84: // ISEL BC,RA,RB,RT -> isel rt,ra,rb,bc 3198 bc := vregoff(ctxt, &p.From) 3199 3200 // rt = To.Reg, ra = p.Reg, rb = p.From3.Reg 3201 o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), uint32(bc)) 3202 3203 case 85: /* vector instructions, VX-form */ 3204 /* reg none reg */ 3205 /* 2-register operand order: VRB, VRT */ 3206 o1 = AOP_RR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg)) 3207 3208 case 86: /* VSX indexed store, XX1-form */ 3209 /* reg reg reg */ 3210 /* 3-register operand order: XT, (RB)(RA*1) */ 3211 o1 = AOP_XX1(opstorex(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 3212 3213 case 87: /* VSX indexed load, XX1-form */ 3214 /* reg reg reg */ 3215 /* 3-register operand order: (RB)(RA*1), XT */ 3216 o1 = AOP_XX1(oploadx(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 3217 3218 case 88: /* VSX instructions, XX1-form */ 3219 /* reg reg none OR reg reg reg */ 3220 /* 3-register operand order: RA, RB, XT */ 3221 /* 2-register operand order: XS, RA or RA, XT */ 3222 xt := int32(p.To.Reg) 3223 xs := int32(p.From.Reg) 3224 /* We need to treat the special case of extended mnemonics that may have a FREG/VREG as an argument */ 3225 if REG_V0 <= xt && xt <= REG_V31 { 3226 /* Convert V0-V31 to VS32-VS63 */ 3227 xt = xt + 64 3228 o1 = AOP_XX1(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3229 } else if REG_F0 <= xt && xt <= REG_F31 { 3230 /* Convert F0-F31 to VS0-VS31 */ 3231 xt = xt + 64 3232 o1 = AOP_XX1(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3233 } else if REG_VS0 <= xt && xt <= REG_VS63 { 3234 o1 = AOP_XX1(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3235 } else if REG_V0 <= xs && xs <= REG_V31 { 3236 /* Likewise for XS */ 3237 xs = xs + 64 3238 o1 = AOP_XX1(oprrr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3239 } else if REG_F0 <= xs && xs <= REG_F31 { 3240 xs = xs + 64 3241 o1 = AOP_XX1(oprrr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3242 } else if REG_VS0 <= xs && xs <= REG_VS63 { 3243 o1 = AOP_XX1(oprrr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3244 } 3245 3246 case 89: /* VSX instructions, XX2-form */ 3247 /* reg none reg OR reg imm reg */ 3248 /* 2-register operand order: XB, XT or XB, UIM, XT*/ 3249 uim := int(regoff(ctxt, p.From3)) 3250 o1 = AOP_XX2(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg)) 3251 3252 case 90: /* VSX instructions, XX3-form */ 3253 if p.From3Type() == obj.TYPE_NONE { 3254 /* reg reg reg */ 3255 /* 3-register operand order: XA, XB, XT */ 3256 o1 = AOP_XX3(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3257 } else if p.From3Type() == obj.TYPE_CONST { 3258 /* reg reg reg imm */ 3259 /* operand order: XA, XB, DM, XT */ 3260 dm := int(regoff(ctxt, p.From3)) 3261 o1 = AOP_XX3I(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm)) 3262 } 3263 3264 case 91: /* VSX instructions, XX4-form */ 3265 /* reg reg reg reg */ 3266 /* 3-register operand order: XA, XB, XC, XT */ 3267 o1 = AOP_XX4(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.From3.Reg)) 3268 3269 case 92: /* X-form instructions, 3-operands */ 3270 if p.To.Type == obj.TYPE_CONST { 3271 /* imm reg reg */ 3272 /* operand order: FRA, FRB, BF */ 3273 bf := int(regoff(ctxt, &p.To)) << 2 3274 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg)) 3275 } else if p.To.Type == obj.TYPE_REG { 3276 /* reg reg reg */ 3277 /* operand order: RS, RB, RA */ 3278 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3279 } 3280 3281 case 93: /* X-form instructions, 2-operands */ 3282 if p.To.Type == obj.TYPE_CONST { 3283 /* imm reg */ 3284 /* operand order: FRB, BF */ 3285 bf := int(regoff(ctxt, &p.To)) << 2 3286 o1 = AOP_RR(opirr(ctxt, p.As), uint32(bf), uint32(p.From.Reg)) 3287 } else if p.Reg == 0 { 3288 /* popcnt* r,r, X-form */ 3289 /* operand order: RS, RA */ 3290 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3291 } 3292 3293 } 3294 3295 out[0] = o1 3296 out[1] = o2 3297 out[2] = o3 3298 out[3] = o4 3299 out[4] = o5 3300 return 3301 } 3302 3303 func vregoff(ctxt *obj.Link, a *obj.Addr) int64 { 3304 ctxt.Instoffset = 0 3305 if a != nil { 3306 aclass(ctxt, a) 3307 } 3308 return ctxt.Instoffset 3309 } 3310 3311 func regoff(ctxt *obj.Link, a *obj.Addr) int32 { 3312 return int32(vregoff(ctxt, a)) 3313 } 3314 3315 func oprrr(ctxt *obj.Link, a obj.As) uint32 { 3316 switch a { 3317 case AADD: 3318 return OPVCC(31, 266, 0, 0) 3319 case AADDCC: 3320 return OPVCC(31, 266, 0, 1) 3321 case AADDV: 3322 return OPVCC(31, 266, 1, 0) 3323 case AADDVCC: 3324 return OPVCC(31, 266, 1, 1) 3325 case AADDC: 3326 return OPVCC(31, 10, 0, 0) 3327 case AADDCCC: 3328 return OPVCC(31, 10, 0, 1) 3329 case AADDCV: 3330 return OPVCC(31, 10, 1, 0) 3331 case AADDCVCC: 3332 return OPVCC(31, 10, 1, 1) 3333 case AADDE: 3334 return OPVCC(31, 138, 0, 0) 3335 case AADDECC: 3336 return OPVCC(31, 138, 0, 1) 3337 case AADDEV: 3338 return OPVCC(31, 138, 1, 0) 3339 case AADDEVCC: 3340 return OPVCC(31, 138, 1, 1) 3341 case AADDME: 3342 return OPVCC(31, 234, 0, 0) 3343 case AADDMECC: 3344 return OPVCC(31, 234, 0, 1) 3345 case AADDMEV: 3346 return OPVCC(31, 234, 1, 0) 3347 case AADDMEVCC: 3348 return OPVCC(31, 234, 1, 1) 3349 case AADDZE: 3350 return OPVCC(31, 202, 0, 0) 3351 case AADDZECC: 3352 return OPVCC(31, 202, 0, 1) 3353 case AADDZEV: 3354 return OPVCC(31, 202, 1, 0) 3355 case AADDZEVCC: 3356 return OPVCC(31, 202, 1, 1) 3357 3358 case AAND: 3359 return OPVCC(31, 28, 0, 0) 3360 case AANDCC: 3361 return OPVCC(31, 28, 0, 1) 3362 case AANDN: 3363 return OPVCC(31, 60, 0, 0) 3364 case AANDNCC: 3365 return OPVCC(31, 60, 0, 1) 3366 3367 case ACMP: 3368 return OPVCC(31, 0, 0, 0) | 1<<21 /* L=1 */ 3369 case ACMPU: 3370 return OPVCC(31, 32, 0, 0) | 1<<21 3371 case ACMPW: 3372 return OPVCC(31, 0, 0, 0) /* L=0 */ 3373 case ACMPWU: 3374 return OPVCC(31, 32, 0, 0) 3375 case ACMPB: 3376 return OPVCC(31, 508, 0, 0) /* cmpb - v2.05 */ 3377 3378 case ACNTLZW: 3379 return OPVCC(31, 26, 0, 0) 3380 case ACNTLZWCC: 3381 return OPVCC(31, 26, 0, 1) 3382 case ACNTLZD: 3383 return OPVCC(31, 58, 0, 0) 3384 case ACNTLZDCC: 3385 return OPVCC(31, 58, 0, 1) 3386 3387 case ACRAND: 3388 return OPVCC(19, 257, 0, 0) 3389 case ACRANDN: 3390 return OPVCC(19, 129, 0, 0) 3391 case ACREQV: 3392 return OPVCC(19, 289, 0, 0) 3393 case ACRNAND: 3394 return OPVCC(19, 225, 0, 0) 3395 case ACRNOR: 3396 return OPVCC(19, 33, 0, 0) 3397 case ACROR: 3398 return OPVCC(19, 449, 0, 0) 3399 case ACRORN: 3400 return OPVCC(19, 417, 0, 0) 3401 case ACRXOR: 3402 return OPVCC(19, 193, 0, 0) 3403 3404 case ADCBF: 3405 return OPVCC(31, 86, 0, 0) 3406 case ADCBI: 3407 return OPVCC(31, 470, 0, 0) 3408 case ADCBST: 3409 return OPVCC(31, 54, 0, 0) 3410 case ADCBT: 3411 return OPVCC(31, 278, 0, 0) 3412 case ADCBTST: 3413 return OPVCC(31, 246, 0, 0) 3414 case ADCBZ: 3415 return OPVCC(31, 1014, 0, 0) 3416 3417 case AREM, ADIVW: 3418 return OPVCC(31, 491, 0, 0) 3419 3420 case AREMCC, ADIVWCC: 3421 return OPVCC(31, 491, 0, 1) 3422 3423 case AREMV, ADIVWV: 3424 return OPVCC(31, 491, 1, 0) 3425 3426 case AREMVCC, ADIVWVCC: 3427 return OPVCC(31, 491, 1, 1) 3428 3429 case AREMU, ADIVWU: 3430 return OPVCC(31, 459, 0, 0) 3431 3432 case AREMUCC, ADIVWUCC: 3433 return OPVCC(31, 459, 0, 1) 3434 3435 case AREMUV, ADIVWUV: 3436 return OPVCC(31, 459, 1, 0) 3437 3438 case AREMUVCC, ADIVWUVCC: 3439 return OPVCC(31, 459, 1, 1) 3440 3441 case AREMD, ADIVD: 3442 return OPVCC(31, 489, 0, 0) 3443 3444 case AREMDCC, ADIVDCC: 3445 return OPVCC(31, 489, 0, 1) 3446 3447 case ADIVDE: 3448 return OPVCC(31, 425, 0, 0) 3449 3450 case ADIVDECC: 3451 return OPVCC(31, 425, 0, 1) 3452 3453 case ADIVDEU: 3454 return OPVCC(31, 393, 0, 0) 3455 3456 case ADIVDEUCC: 3457 return OPVCC(31, 393, 0, 1) 3458 3459 case AREMDV, ADIVDV: 3460 return OPVCC(31, 489, 1, 0) 3461 3462 case AREMDVCC, ADIVDVCC: 3463 return OPVCC(31, 489, 1, 1) 3464 3465 case AREMDU, ADIVDU: 3466 return OPVCC(31, 457, 0, 0) 3467 3468 case AREMDUCC, ADIVDUCC: 3469 return OPVCC(31, 457, 0, 1) 3470 3471 case AREMDUV, ADIVDUV: 3472 return OPVCC(31, 457, 1, 0) 3473 3474 case AREMDUVCC, ADIVDUVCC: 3475 return OPVCC(31, 457, 1, 1) 3476 3477 case AEIEIO: 3478 return OPVCC(31, 854, 0, 0) 3479 3480 case AEQV: 3481 return OPVCC(31, 284, 0, 0) 3482 case AEQVCC: 3483 return OPVCC(31, 284, 0, 1) 3484 3485 case AEXTSB: 3486 return OPVCC(31, 954, 0, 0) 3487 case AEXTSBCC: 3488 return OPVCC(31, 954, 0, 1) 3489 case AEXTSH: 3490 return OPVCC(31, 922, 0, 0) 3491 case AEXTSHCC: 3492 return OPVCC(31, 922, 0, 1) 3493 case AEXTSW: 3494 return OPVCC(31, 986, 0, 0) 3495 case AEXTSWCC: 3496 return OPVCC(31, 986, 0, 1) 3497 3498 case AFABS: 3499 return OPVCC(63, 264, 0, 0) 3500 case AFABSCC: 3501 return OPVCC(63, 264, 0, 1) 3502 case AFADD: 3503 return OPVCC(63, 21, 0, 0) 3504 case AFADDCC: 3505 return OPVCC(63, 21, 0, 1) 3506 case AFADDS: 3507 return OPVCC(59, 21, 0, 0) 3508 case AFADDSCC: 3509 return OPVCC(59, 21, 0, 1) 3510 case AFCMPO: 3511 return OPVCC(63, 32, 0, 0) 3512 case AFCMPU: 3513 return OPVCC(63, 0, 0, 0) 3514 case AFCFID: 3515 return OPVCC(63, 846, 0, 0) 3516 case AFCFIDCC: 3517 return OPVCC(63, 846, 0, 1) 3518 case AFCFIDU: 3519 return OPVCC(63, 974, 0, 0) 3520 case AFCFIDUCC: 3521 return OPVCC(63, 974, 0, 1) 3522 case AFCTIW: 3523 return OPVCC(63, 14, 0, 0) 3524 case AFCTIWCC: 3525 return OPVCC(63, 14, 0, 1) 3526 case AFCTIWZ: 3527 return OPVCC(63, 15, 0, 0) 3528 case AFCTIWZCC: 3529 return OPVCC(63, 15, 0, 1) 3530 case AFCTID: 3531 return OPVCC(63, 814, 0, 0) 3532 case AFCTIDCC: 3533 return OPVCC(63, 814, 0, 1) 3534 case AFCTIDZ: 3535 return OPVCC(63, 815, 0, 0) 3536 case AFCTIDZCC: 3537 return OPVCC(63, 815, 0, 1) 3538 case AFDIV: 3539 return OPVCC(63, 18, 0, 0) 3540 case AFDIVCC: 3541 return OPVCC(63, 18, 0, 1) 3542 case AFDIVS: 3543 return OPVCC(59, 18, 0, 0) 3544 case AFDIVSCC: 3545 return OPVCC(59, 18, 0, 1) 3546 case AFMADD: 3547 return OPVCC(63, 29, 0, 0) 3548 case AFMADDCC: 3549 return OPVCC(63, 29, 0, 1) 3550 case AFMADDS: 3551 return OPVCC(59, 29, 0, 0) 3552 case AFMADDSCC: 3553 return OPVCC(59, 29, 0, 1) 3554 3555 case AFMOVS, AFMOVD: 3556 return OPVCC(63, 72, 0, 0) /* load */ 3557 case AFMOVDCC: 3558 return OPVCC(63, 72, 0, 1) 3559 case AFMSUB: 3560 return OPVCC(63, 28, 0, 0) 3561 case AFMSUBCC: 3562 return OPVCC(63, 28, 0, 1) 3563 case AFMSUBS: 3564 return OPVCC(59, 28, 0, 0) 3565 case AFMSUBSCC: 3566 return OPVCC(59, 28, 0, 1) 3567 case AFMUL: 3568 return OPVCC(63, 25, 0, 0) 3569 case AFMULCC: 3570 return OPVCC(63, 25, 0, 1) 3571 case AFMULS: 3572 return OPVCC(59, 25, 0, 0) 3573 case AFMULSCC: 3574 return OPVCC(59, 25, 0, 1) 3575 case AFNABS: 3576 return OPVCC(63, 136, 0, 0) 3577 case AFNABSCC: 3578 return OPVCC(63, 136, 0, 1) 3579 case AFNEG: 3580 return OPVCC(63, 40, 0, 0) 3581 case AFNEGCC: 3582 return OPVCC(63, 40, 0, 1) 3583 case AFNMADD: 3584 return OPVCC(63, 31, 0, 0) 3585 case AFNMADDCC: 3586 return OPVCC(63, 31, 0, 1) 3587 case AFNMADDS: 3588 return OPVCC(59, 31, 0, 0) 3589 case AFNMADDSCC: 3590 return OPVCC(59, 31, 0, 1) 3591 case AFNMSUB: 3592 return OPVCC(63, 30, 0, 0) 3593 case AFNMSUBCC: 3594 return OPVCC(63, 30, 0, 1) 3595 case AFNMSUBS: 3596 return OPVCC(59, 30, 0, 0) 3597 case AFNMSUBSCC: 3598 return OPVCC(59, 30, 0, 1) 3599 case AFRES: 3600 return OPVCC(59, 24, 0, 0) 3601 case AFRESCC: 3602 return OPVCC(59, 24, 0, 1) 3603 case AFRIM: 3604 return OPVCC(63, 488, 0, 0) 3605 case AFRIMCC: 3606 return OPVCC(63, 488, 0, 1) 3607 case AFRIP: 3608 return OPVCC(63, 456, 0, 0) 3609 case AFRIPCC: 3610 return OPVCC(63, 456, 0, 1) 3611 case AFRIZ: 3612 return OPVCC(63, 424, 0, 0) 3613 case AFRIZCC: 3614 return OPVCC(63, 424, 0, 1) 3615 case AFRSP: 3616 return OPVCC(63, 12, 0, 0) 3617 case AFRSPCC: 3618 return OPVCC(63, 12, 0, 1) 3619 case AFRSQRTE: 3620 return OPVCC(63, 26, 0, 0) 3621 case AFRSQRTECC: 3622 return OPVCC(63, 26, 0, 1) 3623 case AFSEL: 3624 return OPVCC(63, 23, 0, 0) 3625 case AFSELCC: 3626 return OPVCC(63, 23, 0, 1) 3627 case AFSQRT: 3628 return OPVCC(63, 22, 0, 0) 3629 case AFSQRTCC: 3630 return OPVCC(63, 22, 0, 1) 3631 case AFSQRTS: 3632 return OPVCC(59, 22, 0, 0) 3633 case AFSQRTSCC: 3634 return OPVCC(59, 22, 0, 1) 3635 case AFSUB: 3636 return OPVCC(63, 20, 0, 0) 3637 case AFSUBCC: 3638 return OPVCC(63, 20, 0, 1) 3639 case AFSUBS: 3640 return OPVCC(59, 20, 0, 0) 3641 case AFSUBSCC: 3642 return OPVCC(59, 20, 0, 1) 3643 3644 case AICBI: 3645 return OPVCC(31, 982, 0, 0) 3646 case AISYNC: 3647 return OPVCC(19, 150, 0, 0) 3648 3649 case AMTFSB0: 3650 return OPVCC(63, 70, 0, 0) 3651 case AMTFSB0CC: 3652 return OPVCC(63, 70, 0, 1) 3653 case AMTFSB1: 3654 return OPVCC(63, 38, 0, 0) 3655 case AMTFSB1CC: 3656 return OPVCC(63, 38, 0, 1) 3657 3658 case AMULHW: 3659 return OPVCC(31, 75, 0, 0) 3660 case AMULHWCC: 3661 return OPVCC(31, 75, 0, 1) 3662 case AMULHWU: 3663 return OPVCC(31, 11, 0, 0) 3664 case AMULHWUCC: 3665 return OPVCC(31, 11, 0, 1) 3666 case AMULLW: 3667 return OPVCC(31, 235, 0, 0) 3668 case AMULLWCC: 3669 return OPVCC(31, 235, 0, 1) 3670 case AMULLWV: 3671 return OPVCC(31, 235, 1, 0) 3672 case AMULLWVCC: 3673 return OPVCC(31, 235, 1, 1) 3674 3675 case AMULHD: 3676 return OPVCC(31, 73, 0, 0) 3677 case AMULHDCC: 3678 return OPVCC(31, 73, 0, 1) 3679 case AMULHDU: 3680 return OPVCC(31, 9, 0, 0) 3681 case AMULHDUCC: 3682 return OPVCC(31, 9, 0, 1) 3683 case AMULLD: 3684 return OPVCC(31, 233, 0, 0) 3685 case AMULLDCC: 3686 return OPVCC(31, 233, 0, 1) 3687 case AMULLDV: 3688 return OPVCC(31, 233, 1, 0) 3689 case AMULLDVCC: 3690 return OPVCC(31, 233, 1, 1) 3691 3692 case ANAND: 3693 return OPVCC(31, 476, 0, 0) 3694 case ANANDCC: 3695 return OPVCC(31, 476, 0, 1) 3696 case ANEG: 3697 return OPVCC(31, 104, 0, 0) 3698 case ANEGCC: 3699 return OPVCC(31, 104, 0, 1) 3700 case ANEGV: 3701 return OPVCC(31, 104, 1, 0) 3702 case ANEGVCC: 3703 return OPVCC(31, 104, 1, 1) 3704 case ANOR: 3705 return OPVCC(31, 124, 0, 0) 3706 case ANORCC: 3707 return OPVCC(31, 124, 0, 1) 3708 case AOR: 3709 return OPVCC(31, 444, 0, 0) 3710 case AORCC: 3711 return OPVCC(31, 444, 0, 1) 3712 case AORN: 3713 return OPVCC(31, 412, 0, 0) 3714 case AORNCC: 3715 return OPVCC(31, 412, 0, 1) 3716 3717 case APOPCNTD: 3718 return OPVCC(31, 506, 0, 0) /* popcntd - v2.06 */ 3719 case APOPCNTW: 3720 return OPVCC(31, 378, 0, 0) /* popcntw - v2.06 */ 3721 case APOPCNTB: 3722 return OPVCC(31, 122, 0, 0) /* popcntb - v2.02 */ 3723 3724 case ARFI: 3725 return OPVCC(19, 50, 0, 0) 3726 case ARFCI: 3727 return OPVCC(19, 51, 0, 0) 3728 case ARFID: 3729 return OPVCC(19, 18, 0, 0) 3730 case AHRFID: 3731 return OPVCC(19, 274, 0, 0) 3732 3733 case ARLWMI: 3734 return OPVCC(20, 0, 0, 0) 3735 case ARLWMICC: 3736 return OPVCC(20, 0, 0, 1) 3737 case ARLWNM: 3738 return OPVCC(23, 0, 0, 0) 3739 case ARLWNMCC: 3740 return OPVCC(23, 0, 0, 1) 3741 3742 case ARLDCL: 3743 return OPVCC(30, 8, 0, 0) 3744 case ARLDCR: 3745 return OPVCC(30, 9, 0, 0) 3746 3747 case ARLDICL: 3748 return OPVCC(30, 0, 0, 0) 3749 case ARLDICLCC: 3750 return OPVCC(30, 0, 0, 1) 3751 case ARLDICR: 3752 return OPVCC(30, 0, 0, 0) | 2<<1 // rldicr 3753 case ARLDICRCC: 3754 return OPVCC(30, 0, 0, 1) | 2<<1 // rldicr. 3755 3756 case ASYSCALL: 3757 return OPVCC(17, 1, 0, 0) 3758 3759 case ASLW: 3760 return OPVCC(31, 24, 0, 0) 3761 case ASLWCC: 3762 return OPVCC(31, 24, 0, 1) 3763 case ASLD: 3764 return OPVCC(31, 27, 0, 0) 3765 case ASLDCC: 3766 return OPVCC(31, 27, 0, 1) 3767 3768 case ASRAW: 3769 return OPVCC(31, 792, 0, 0) 3770 case ASRAWCC: 3771 return OPVCC(31, 792, 0, 1) 3772 case ASRAD: 3773 return OPVCC(31, 794, 0, 0) 3774 case ASRADCC: 3775 return OPVCC(31, 794, 0, 1) 3776 3777 case ASRW: 3778 return OPVCC(31, 536, 0, 0) 3779 case ASRWCC: 3780 return OPVCC(31, 536, 0, 1) 3781 case ASRD: 3782 return OPVCC(31, 539, 0, 0) 3783 case ASRDCC: 3784 return OPVCC(31, 539, 0, 1) 3785 3786 case ASUB: 3787 return OPVCC(31, 40, 0, 0) 3788 case ASUBCC: 3789 return OPVCC(31, 40, 0, 1) 3790 case ASUBV: 3791 return OPVCC(31, 40, 1, 0) 3792 case ASUBVCC: 3793 return OPVCC(31, 40, 1, 1) 3794 case ASUBC: 3795 return OPVCC(31, 8, 0, 0) 3796 case ASUBCCC: 3797 return OPVCC(31, 8, 0, 1) 3798 case ASUBCV: 3799 return OPVCC(31, 8, 1, 0) 3800 case ASUBCVCC: 3801 return OPVCC(31, 8, 1, 1) 3802 case ASUBE: 3803 return OPVCC(31, 136, 0, 0) 3804 case ASUBECC: 3805 return OPVCC(31, 136, 0, 1) 3806 case ASUBEV: 3807 return OPVCC(31, 136, 1, 0) 3808 case ASUBEVCC: 3809 return OPVCC(31, 136, 1, 1) 3810 case ASUBME: 3811 return OPVCC(31, 232, 0, 0) 3812 case ASUBMECC: 3813 return OPVCC(31, 232, 0, 1) 3814 case ASUBMEV: 3815 return OPVCC(31, 232, 1, 0) 3816 case ASUBMEVCC: 3817 return OPVCC(31, 232, 1, 1) 3818 case ASUBZE: 3819 return OPVCC(31, 200, 0, 0) 3820 case ASUBZECC: 3821 return OPVCC(31, 200, 0, 1) 3822 case ASUBZEV: 3823 return OPVCC(31, 200, 1, 0) 3824 case ASUBZEVCC: 3825 return OPVCC(31, 200, 1, 1) 3826 3827 case ASYNC: 3828 return OPVCC(31, 598, 0, 0) 3829 case ALWSYNC: 3830 return OPVCC(31, 598, 0, 0) | 1<<21 3831 3832 case APTESYNC: 3833 return OPVCC(31, 598, 0, 0) | 2<<21 3834 3835 case ATLBIE: 3836 return OPVCC(31, 306, 0, 0) 3837 case ATLBIEL: 3838 return OPVCC(31, 274, 0, 0) 3839 case ATLBSYNC: 3840 return OPVCC(31, 566, 0, 0) 3841 case ASLBIA: 3842 return OPVCC(31, 498, 0, 0) 3843 case ASLBIE: 3844 return OPVCC(31, 434, 0, 0) 3845 case ASLBMFEE: 3846 return OPVCC(31, 915, 0, 0) 3847 case ASLBMFEV: 3848 return OPVCC(31, 851, 0, 0) 3849 case ASLBMTE: 3850 return OPVCC(31, 402, 0, 0) 3851 3852 case ATW: 3853 return OPVCC(31, 4, 0, 0) 3854 case ATD: 3855 return OPVCC(31, 68, 0, 0) 3856 3857 /* Vector (VMX/Altivec) instructions */ 3858 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 3859 /* are enabled starting at POWER6 (ISA 2.05). */ 3860 case AVAND: 3861 return OPVX(4, 1028, 0, 0) /* vand - v2.03 */ 3862 case AVANDC: 3863 return OPVX(4, 1092, 0, 0) /* vandc - v2.03 */ 3864 case AVNAND: 3865 return OPVX(4, 1412, 0, 0) /* vnand - v2.07 */ 3866 3867 case AVOR: 3868 return OPVX(4, 1156, 0, 0) /* vor - v2.03 */ 3869 case AVORC: 3870 return OPVX(4, 1348, 0, 0) /* vorc - v2.07 */ 3871 case AVNOR: 3872 return OPVX(4, 1284, 0, 0) /* vnor - v2.03 */ 3873 case AVXOR: 3874 return OPVX(4, 1220, 0, 0) /* vxor - v2.03 */ 3875 case AVEQV: 3876 return OPVX(4, 1668, 0, 0) /* veqv - v2.07 */ 3877 3878 case AVADDUBM: 3879 return OPVX(4, 0, 0, 0) /* vaddubm - v2.03 */ 3880 case AVADDUHM: 3881 return OPVX(4, 64, 0, 0) /* vadduhm - v2.03 */ 3882 case AVADDUWM: 3883 return OPVX(4, 128, 0, 0) /* vadduwm - v2.03 */ 3884 case AVADDUDM: 3885 return OPVX(4, 192, 0, 0) /* vaddudm - v2.07 */ 3886 case AVADDUQM: 3887 return OPVX(4, 256, 0, 0) /* vadduqm - v2.07 */ 3888 3889 case AVADDCUQ: 3890 return OPVX(4, 320, 0, 0) /* vaddcuq - v2.07 */ 3891 case AVADDCUW: 3892 return OPVX(4, 384, 0, 0) /* vaddcuw - v2.03 */ 3893 3894 case AVADDUBS: 3895 return OPVX(4, 512, 0, 0) /* vaddubs - v2.03 */ 3896 case AVADDUHS: 3897 return OPVX(4, 576, 0, 0) /* vadduhs - v2.03 */ 3898 case AVADDUWS: 3899 return OPVX(4, 640, 0, 0) /* vadduws - v2.03 */ 3900 3901 case AVADDSBS: 3902 return OPVX(4, 768, 0, 0) /* vaddsbs - v2.03 */ 3903 case AVADDSHS: 3904 return OPVX(4, 832, 0, 0) /* vaddshs - v2.03 */ 3905 case AVADDSWS: 3906 return OPVX(4, 896, 0, 0) /* vaddsws - v2.03 */ 3907 3908 case AVADDEUQM: 3909 return OPVX(4, 60, 0, 0) /* vaddeuqm - v2.07 */ 3910 case AVADDECUQ: 3911 return OPVX(4, 61, 0, 0) /* vaddecuq - v2.07 */ 3912 3913 case AVPMSUMB: 3914 return OPVX(4, 1032, 0, 0) /* vpmsumb - v2.07 */ 3915 case AVPMSUMH: 3916 return OPVX(4, 1096, 0, 0) /* vpmsumh - v2.07 */ 3917 case AVPMSUMW: 3918 return OPVX(4, 1160, 0, 0) /* vpmsumw - v2.07 */ 3919 case AVPMSUMD: 3920 return OPVX(4, 1224, 0, 0) /* vpmsumd - v2.07 */ 3921 3922 case AVSUBUBM: 3923 return OPVX(4, 1024, 0, 0) /* vsububm - v2.03 */ 3924 case AVSUBUHM: 3925 return OPVX(4, 1088, 0, 0) /* vsubuhm - v2.03 */ 3926 case AVSUBUWM: 3927 return OPVX(4, 1152, 0, 0) /* vsubuwm - v2.03 */ 3928 case AVSUBUDM: 3929 return OPVX(4, 1216, 0, 0) /* vsubudm - v2.07 */ 3930 case AVSUBUQM: 3931 return OPVX(4, 1280, 0, 0) /* vsubuqm - v2.07 */ 3932 3933 case AVSUBCUQ: 3934 return OPVX(4, 1344, 0, 0) /* vsubcuq - v2.07 */ 3935 case AVSUBCUW: 3936 return OPVX(4, 1408, 0, 0) /* vsubcuw - v2.03 */ 3937 3938 case AVSUBUBS: 3939 return OPVX(4, 1536, 0, 0) /* vsububs - v2.03 */ 3940 case AVSUBUHS: 3941 return OPVX(4, 1600, 0, 0) /* vsubuhs - v2.03 */ 3942 case AVSUBUWS: 3943 return OPVX(4, 1664, 0, 0) /* vsubuws - v2.03 */ 3944 3945 case AVSUBSBS: 3946 return OPVX(4, 1792, 0, 0) /* vsubsbs - v2.03 */ 3947 case AVSUBSHS: 3948 return OPVX(4, 1856, 0, 0) /* vsubshs - v2.03 */ 3949 case AVSUBSWS: 3950 return OPVX(4, 1920, 0, 0) /* vsubsws - v2.03 */ 3951 3952 case AVSUBEUQM: 3953 return OPVX(4, 62, 0, 0) /* vsubeuqm - v2.07 */ 3954 case AVSUBECUQ: 3955 return OPVX(4, 63, 0, 0) /* vsubecuq - v2.07 */ 3956 3957 case AVRLB: 3958 return OPVX(4, 4, 0, 0) /* vrlb - v2.03 */ 3959 case AVRLH: 3960 return OPVX(4, 68, 0, 0) /* vrlh - v2.03 */ 3961 case AVRLW: 3962 return OPVX(4, 132, 0, 0) /* vrlw - v2.03 */ 3963 case AVRLD: 3964 return OPVX(4, 196, 0, 0) /* vrld - v2.07 */ 3965 3966 case AVSLB: 3967 return OPVX(4, 260, 0, 0) /* vslh - v2.03 */ 3968 case AVSLH: 3969 return OPVX(4, 324, 0, 0) /* vslh - v2.03 */ 3970 case AVSLW: 3971 return OPVX(4, 388, 0, 0) /* vslw - v2.03 */ 3972 case AVSL: 3973 return OPVX(4, 452, 0, 0) /* vsl - v2.03 */ 3974 case AVSLO: 3975 return OPVX(4, 1036, 0, 0) /* vsl - v2.03 */ 3976 case AVSRB: 3977 return OPVX(4, 516, 0, 0) /* vsrb - v2.03 */ 3978 case AVSRH: 3979 return OPVX(4, 580, 0, 0) /* vsrh - v2.03 */ 3980 case AVSRW: 3981 return OPVX(4, 644, 0, 0) /* vsrw - v2.03 */ 3982 case AVSR: 3983 return OPVX(4, 708, 0, 0) /* vsr - v2.03 */ 3984 case AVSRO: 3985 return OPVX(4, 1100, 0, 0) /* vsro - v2.03 */ 3986 case AVSLD: 3987 return OPVX(4, 1476, 0, 0) /* vsld - v2.07 */ 3988 case AVSRD: 3989 return OPVX(4, 1732, 0, 0) /* vsrd - v2.07 */ 3990 3991 case AVSRAB: 3992 return OPVX(4, 772, 0, 0) /* vsrab - v2.03 */ 3993 case AVSRAH: 3994 return OPVX(4, 836, 0, 0) /* vsrah - v2.03 */ 3995 case AVSRAW: 3996 return OPVX(4, 900, 0, 0) /* vsraw - v2.03 */ 3997 case AVSRAD: 3998 return OPVX(4, 964, 0, 0) /* vsrad - v2.07 */ 3999 4000 case AVCLZB: 4001 return OPVX(4, 1794, 0, 0) /* vclzb - v2.07 */ 4002 case AVCLZH: 4003 return OPVX(4, 1858, 0, 0) /* vclzh - v2.07 */ 4004 case AVCLZW: 4005 return OPVX(4, 1922, 0, 0) /* vclzw - v2.07 */ 4006 case AVCLZD: 4007 return OPVX(4, 1986, 0, 0) /* vclzd - v2.07 */ 4008 4009 case AVPOPCNTB: 4010 return OPVX(4, 1795, 0, 0) /* vpopcntb - v2.07 */ 4011 case AVPOPCNTH: 4012 return OPVX(4, 1859, 0, 0) /* vpopcnth - v2.07 */ 4013 case AVPOPCNTW: 4014 return OPVX(4, 1923, 0, 0) /* vpopcntw - v2.07 */ 4015 case AVPOPCNTD: 4016 return OPVX(4, 1987, 0, 0) /* vpopcntd - v2.07 */ 4017 4018 case AVCMPEQUB: 4019 return OPVC(4, 6, 0, 0) /* vcmpequb - v2.03 */ 4020 case AVCMPEQUBCC: 4021 return OPVC(4, 6, 0, 1) /* vcmpequb. - v2.03 */ 4022 case AVCMPEQUH: 4023 return OPVC(4, 70, 0, 0) /* vcmpequh - v2.03 */ 4024 case AVCMPEQUHCC: 4025 return OPVC(4, 70, 0, 1) /* vcmpequh. - v2.03 */ 4026 case AVCMPEQUW: 4027 return OPVC(4, 134, 0, 0) /* vcmpequw - v2.03 */ 4028 case AVCMPEQUWCC: 4029 return OPVC(4, 134, 0, 1) /* vcmpequw. - v2.03 */ 4030 case AVCMPEQUD: 4031 return OPVC(4, 199, 0, 0) /* vcmpequd - v2.07 */ 4032 case AVCMPEQUDCC: 4033 return OPVC(4, 199, 0, 1) /* vcmpequd. - v2.07 */ 4034 4035 case AVCMPGTUB: 4036 return OPVC(4, 518, 0, 0) /* vcmpgtub - v2.03 */ 4037 case AVCMPGTUBCC: 4038 return OPVC(4, 518, 0, 1) /* vcmpgtub. - v2.03 */ 4039 case AVCMPGTUH: 4040 return OPVC(4, 582, 0, 0) /* vcmpgtuh - v2.03 */ 4041 case AVCMPGTUHCC: 4042 return OPVC(4, 582, 0, 1) /* vcmpgtuh. - v2.03 */ 4043 case AVCMPGTUW: 4044 return OPVC(4, 646, 0, 0) /* vcmpgtuw - v2.03 */ 4045 case AVCMPGTUWCC: 4046 return OPVC(4, 646, 0, 1) /* vcmpgtuw. - v2.03 */ 4047 case AVCMPGTUD: 4048 return OPVC(4, 711, 0, 0) /* vcmpgtud - v2.07 */ 4049 case AVCMPGTUDCC: 4050 return OPVC(4, 711, 0, 1) /* vcmpgtud. v2.07 */ 4051 case AVCMPGTSB: 4052 return OPVC(4, 774, 0, 0) /* vcmpgtsb - v2.03 */ 4053 case AVCMPGTSBCC: 4054 return OPVC(4, 774, 0, 1) /* vcmpgtsb. - v2.03 */ 4055 case AVCMPGTSH: 4056 return OPVC(4, 838, 0, 0) /* vcmpgtsh - v2.03 */ 4057 case AVCMPGTSHCC: 4058 return OPVC(4, 838, 0, 1) /* vcmpgtsh. - v2.03 */ 4059 case AVCMPGTSW: 4060 return OPVC(4, 902, 0, 0) /* vcmpgtsw - v2.03 */ 4061 case AVCMPGTSWCC: 4062 return OPVC(4, 902, 0, 1) /* vcmpgtsw. - v2.03 */ 4063 case AVCMPGTSD: 4064 return OPVC(4, 967, 0, 0) /* vcmpgtsd - v2.07 */ 4065 case AVCMPGTSDCC: 4066 return OPVC(4, 967, 0, 1) /* vcmpgtsd. - v2.07 */ 4067 4068 case AVPERM: 4069 return OPVX(4, 43, 0, 0) /* vperm - v2.03 */ 4070 4071 case AVSEL: 4072 return OPVX(4, 42, 0, 0) /* vsel - v2.03 */ 4073 4074 case AVCIPHER: 4075 return OPVX(4, 1288, 0, 0) /* vcipher - v2.07 */ 4076 case AVCIPHERLAST: 4077 return OPVX(4, 1289, 0, 0) /* vcipherlast - v2.07 */ 4078 case AVNCIPHER: 4079 return OPVX(4, 1352, 0, 0) /* vncipher - v2.07 */ 4080 case AVNCIPHERLAST: 4081 return OPVX(4, 1353, 0, 0) /* vncipherlast - v2.07 */ 4082 case AVSBOX: 4083 return OPVX(4, 1480, 0, 0) /* vsbox - v2.07 */ 4084 /* End of vector instructions */ 4085 4086 /* Vector scalar (VSX) instructions */ 4087 /* ISA 2.06 enables these for POWER7. */ 4088 case AMFVSRD, AMFVRD, AMFFPRD: 4089 return OPVXX1(31, 51, 0) /* mfvsrd - v2.07 */ 4090 case AMFVSRWZ: 4091 return OPVXX1(31, 115, 0) /* mfvsrwz - v2.07 */ 4092 4093 case AMTVSRD, AMTFPRD, AMTVRD: 4094 return OPVXX1(31, 179, 0) /* mtvsrd - v2.07 */ 4095 case AMTVSRWA: 4096 return OPVXX1(31, 211, 0) /* mtvsrwa - v2.07 */ 4097 case AMTVSRWZ: 4098 return OPVXX1(31, 243, 0) /* mtvsrwz - v2.07 */ 4099 4100 case AXXLANDQ: 4101 return OPVXX3(60, 130, 0) /* xxland - v2.06 */ 4102 case AXXLANDC: 4103 return OPVXX3(60, 138, 0) /* xxlandc - v2.06 */ 4104 case AXXLEQV: 4105 return OPVXX3(60, 186, 0) /* xxleqv - v2.07 */ 4106 case AXXLNAND: 4107 return OPVXX3(60, 178, 0) /* xxlnand - v2.07 */ 4108 4109 case AXXLORC: 4110 return OPVXX3(60, 170, 0) /* xxlorc - v2.07 */ 4111 case AXXLNOR: 4112 return OPVXX3(60, 162, 0) /* xxlnor - v2.06 */ 4113 case AXXLORQ: 4114 return OPVXX3(60, 146, 0) /* xxlor - v2.06 */ 4115 case AXXLXOR: 4116 return OPVXX3(60, 154, 0) /* xxlxor - v2.06 */ 4117 4118 case AXXSEL: 4119 return OPVXX4(60, 3, 0) /* xxsel - v2.06 */ 4120 4121 case AXXMRGHW: 4122 return OPVXX3(60, 18, 0) /* xxmrghw - v2.06 */ 4123 case AXXMRGLW: 4124 return OPVXX3(60, 50, 0) /* xxmrglw - v2.06 */ 4125 4126 case AXXSPLTW: 4127 return OPVXX2(60, 164, 0) /* xxspltw - v2.06 */ 4128 4129 case AXXPERMDI: 4130 return OPVXX3(60, 10, 0) /* xxpermdi - v2.06 */ 4131 4132 case AXXSLDWI: 4133 return OPVXX3(60, 2, 0) /* xxsldwi - v2.06 */ 4134 4135 case AXSCVDPSP: 4136 return OPVXX2(60, 265, 0) /* xscvdpsp - v2.06 */ 4137 case AXSCVSPDP: 4138 return OPVXX2(60, 329, 0) /* xscvspdp - v2.06 */ 4139 case AXSCVDPSPN: 4140 return OPVXX2(60, 267, 0) /* xscvdpspn - v2.07 */ 4141 case AXSCVSPDPN: 4142 return OPVXX2(60, 331, 0) /* xscvspdpn - v2.07 */ 4143 4144 case AXVCVDPSP: 4145 return OPVXX2(60, 393, 0) /* xvcvdpsp - v2.06 */ 4146 case AXVCVSPDP: 4147 return OPVXX2(60, 457, 0) /* xvcvspdp - v2.06 */ 4148 4149 case AXSCVDPSXDS: 4150 return OPVXX2(60, 344, 0) /* xscvdpsxds - v2.06 */ 4151 case AXSCVDPSXWS: 4152 return OPVXX2(60, 88, 0) /* xscvdpsxws - v2.06 */ 4153 case AXSCVDPUXDS: 4154 return OPVXX2(60, 328, 0) /* xscvdpuxds - v2.06 */ 4155 case AXSCVDPUXWS: 4156 return OPVXX2(60, 72, 0) /* xscvdpuxws - v2.06 */ 4157 4158 case AXSCVSXDDP: 4159 return OPVXX2(60, 376, 0) /* xscvsxddp - v2.06 */ 4160 case AXSCVUXDDP: 4161 return OPVXX2(60, 360, 0) /* xscvuxddp - v2.06 */ 4162 case AXSCVSXDSP: 4163 return OPVXX2(60, 312, 0) /* xscvsxdsp - v2.06 */ 4164 case AXSCVUXDSP: 4165 return OPVXX2(60, 296, 0) /* xscvuxdsp - v2.06 */ 4166 4167 case AXVCVDPSXDS: 4168 return OPVXX2(60, 472, 0) /* xvcvdpsxds - v2.06 */ 4169 case AXVCVDPSXWS: 4170 return OPVXX2(60, 216, 0) /* xvcvdpsxws - v2.06 */ 4171 case AXVCVDPUXDS: 4172 return OPVXX2(60, 456, 0) /* xvcvdpuxds - v2.06 */ 4173 case AXVCVDPUXWS: 4174 return OPVXX2(60, 200, 0) /* xvcvdpuxws - v2.06 */ 4175 case AXVCVSPSXDS: 4176 return OPVXX2(60, 408, 0) /* xvcvspsxds - v2.07 */ 4177 case AXVCVSPSXWS: 4178 return OPVXX2(60, 152, 0) /* xvcvspsxws - v2.07 */ 4179 case AXVCVSPUXDS: 4180 return OPVXX2(60, 392, 0) /* xvcvspuxds - v2.07 */ 4181 case AXVCVSPUXWS: 4182 return OPVXX2(60, 136, 0) /* xvcvspuxws - v2.07 */ 4183 4184 case AXVCVSXDDP: 4185 return OPVXX2(60, 504, 0) /* xvcvsxddp - v2.06 */ 4186 case AXVCVSXWDP: 4187 return OPVXX2(60, 248, 0) /* xvcvsxwdp - v2.06 */ 4188 case AXVCVUXDDP: 4189 return OPVXX2(60, 488, 0) /* xvcvuxddp - v2.06 */ 4190 case AXVCVUXWDP: 4191 return OPVXX2(60, 232, 0) /* xvcvuxwdp - v2.06 */ 4192 case AXVCVSXDSP: 4193 return OPVXX2(60, 440, 0) /* xvcvsxdsp - v2.06 */ 4194 case AXVCVSXWSP: 4195 return OPVXX2(60, 184, 0) /* xvcvsxwsp - v2.06 */ 4196 case AXVCVUXDSP: 4197 return OPVXX2(60, 424, 0) /* xvcvuxdsp - v2.06 */ 4198 case AXVCVUXWSP: 4199 return OPVXX2(60, 168, 0) /* xvcvuxwsp - v2.06 */ 4200 /* End of VSX instructions */ 4201 4202 case AXOR: 4203 return OPVCC(31, 316, 0, 0) 4204 case AXORCC: 4205 return OPVCC(31, 316, 0, 1) 4206 } 4207 4208 ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a) 4209 return 0 4210 } 4211 4212 func opirrr(ctxt *obj.Link, a obj.As) uint32 { 4213 switch a { 4214 /* Vector (VMX/Altivec) instructions */ 4215 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4216 /* are enabled starting at POWER6 (ISA 2.05). */ 4217 case AVSLDOI: 4218 return OPVX(4, 44, 0, 0) /* vsldoi - v2.03 */ 4219 } 4220 4221 ctxt.Diag("bad i/r/r/r opcode %v", a) 4222 return 0 4223 } 4224 4225 func opiirr(ctxt *obj.Link, a obj.As) uint32 { 4226 switch a { 4227 /* Vector (VMX/Altivec) instructions */ 4228 /* ISA 2.07 enables these for POWER8 and beyond. */ 4229 case AVSHASIGMAW: 4230 return OPVX(4, 1666, 0, 0) /* vshasigmaw - v2.07 */ 4231 case AVSHASIGMAD: 4232 return OPVX(4, 1730, 0, 0) /* vshasigmad - v2.07 */ 4233 } 4234 4235 ctxt.Diag("bad i/i/r/r opcode %v", a) 4236 return 0 4237 } 4238 4239 func opirr(ctxt *obj.Link, a obj.As) uint32 { 4240 switch a { 4241 case AADD: 4242 return OPVCC(14, 0, 0, 0) 4243 case AADDC: 4244 return OPVCC(12, 0, 0, 0) 4245 case AADDCCC: 4246 return OPVCC(13, 0, 0, 0) 4247 case -AADD: 4248 return OPVCC(15, 0, 0, 0) /* ADDIS/CAU */ 4249 4250 case AANDCC: 4251 return OPVCC(28, 0, 0, 0) 4252 case -AANDCC: 4253 return OPVCC(29, 0, 0, 0) /* ANDIS./ANDIU. */ 4254 4255 case ABR: 4256 return OPVCC(18, 0, 0, 0) 4257 case ABL: 4258 return OPVCC(18, 0, 0, 0) | 1 4259 case obj.ADUFFZERO: 4260 return OPVCC(18, 0, 0, 0) | 1 4261 case obj.ADUFFCOPY: 4262 return OPVCC(18, 0, 0, 0) | 1 4263 case ABC: 4264 return OPVCC(16, 0, 0, 0) 4265 case ABCL: 4266 return OPVCC(16, 0, 0, 0) | 1 4267 4268 case ABEQ: 4269 return AOP_RRR(16<<26, 12, 2, 0) 4270 case ABGE: 4271 return AOP_RRR(16<<26, 4, 0, 0) 4272 case ABGT: 4273 return AOP_RRR(16<<26, 12, 1, 0) 4274 case ABLE: 4275 return AOP_RRR(16<<26, 4, 1, 0) 4276 case ABLT: 4277 return AOP_RRR(16<<26, 12, 0, 0) 4278 case ABNE: 4279 return AOP_RRR(16<<26, 4, 2, 0) 4280 case ABVC: 4281 return AOP_RRR(16<<26, 4, 3, 0) // apparently unordered-clear 4282 case ABVS: 4283 return AOP_RRR(16<<26, 12, 3, 0) // apparently unordered-set 4284 4285 case ACMP: 4286 return OPVCC(11, 0, 0, 0) | 1<<21 /* L=1 */ 4287 case ACMPU: 4288 return OPVCC(10, 0, 0, 0) | 1<<21 4289 case ACMPW: 4290 return OPVCC(11, 0, 0, 0) /* L=0 */ 4291 case ACMPWU: 4292 return OPVCC(10, 0, 0, 0) 4293 case ALSW: 4294 return OPVCC(31, 597, 0, 0) 4295 4296 case AMULLW: 4297 return OPVCC(7, 0, 0, 0) 4298 4299 case AOR: 4300 return OPVCC(24, 0, 0, 0) 4301 case -AOR: 4302 return OPVCC(25, 0, 0, 0) /* ORIS/ORIU */ 4303 4304 case ARLWMI: 4305 return OPVCC(20, 0, 0, 0) /* rlwimi */ 4306 case ARLWMICC: 4307 return OPVCC(20, 0, 0, 1) 4308 case ARLDMI: 4309 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4310 case ARLDMICC: 4311 return OPVCC(30, 0, 0, 1) | 3<<2 4312 case ARLDIMI: 4313 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4314 case ARLDIMICC: 4315 return OPVCC(30, 0, 0, 1) | 3<<2 4316 case ARLWNM: 4317 return OPVCC(21, 0, 0, 0) /* rlwinm */ 4318 case ARLWNMCC: 4319 return OPVCC(21, 0, 0, 1) 4320 4321 case ARLDCL: 4322 return OPVCC(30, 0, 0, 0) /* rldicl */ 4323 case ARLDCLCC: 4324 return OPVCC(30, 0, 0, 1) 4325 case ARLDCR: 4326 return OPVCC(30, 1, 0, 0) /* rldicr */ 4327 case ARLDCRCC: 4328 return OPVCC(30, 1, 0, 1) 4329 case ARLDC: 4330 return OPVCC(30, 0, 0, 0) | 2<<2 4331 case ARLDCCC: 4332 return OPVCC(30, 0, 0, 1) | 2<<2 4333 4334 case ASRAW: 4335 return OPVCC(31, 824, 0, 0) 4336 case ASRAWCC: 4337 return OPVCC(31, 824, 0, 1) 4338 case ASRAD: 4339 return OPVCC(31, (413 << 1), 0, 0) 4340 case ASRADCC: 4341 return OPVCC(31, (413 << 1), 0, 1) 4342 4343 case ASTSW: 4344 return OPVCC(31, 725, 0, 0) 4345 4346 case ASUBC: 4347 return OPVCC(8, 0, 0, 0) 4348 4349 case ATW: 4350 return OPVCC(3, 0, 0, 0) 4351 case ATD: 4352 return OPVCC(2, 0, 0, 0) 4353 4354 /* Vector (VMX/Altivec) instructions */ 4355 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4356 /* are enabled starting at POWER6 (ISA 2.05). */ 4357 case AVSPLTB: 4358 return OPVX(4, 524, 0, 0) /* vspltb - v2.03 */ 4359 case AVSPLTH: 4360 return OPVX(4, 588, 0, 0) /* vsplth - v2.03 */ 4361 case AVSPLTW: 4362 return OPVX(4, 652, 0, 0) /* vspltw - v2.03 */ 4363 4364 case AVSPLTISB: 4365 return OPVX(4, 780, 0, 0) /* vspltisb - v2.03 */ 4366 case AVSPLTISH: 4367 return OPVX(4, 844, 0, 0) /* vspltish - v2.03 */ 4368 case AVSPLTISW: 4369 return OPVX(4, 908, 0, 0) /* vspltisw - v2.03 */ 4370 /* End of vector instructions */ 4371 4372 case AFTDIV: 4373 return OPVCC(63, 128, 0, 0) /* ftdiv - v2.06 */ 4374 case AFTSQRT: 4375 return OPVCC(63, 160, 0, 0) /* ftsqrt - v2.06 */ 4376 4377 case AXOR: 4378 return OPVCC(26, 0, 0, 0) /* XORIL */ 4379 case -AXOR: 4380 return OPVCC(27, 0, 0, 0) /* XORIU */ 4381 } 4382 4383 ctxt.Diag("bad opcode i/r or i/r/r %v", a) 4384 return 0 4385 } 4386 4387 /* 4388 * load o(a),d 4389 */ 4390 func opload(ctxt *obj.Link, a obj.As) uint32 { 4391 switch a { 4392 case AMOVD: 4393 return OPVCC(58, 0, 0, 0) /* ld */ 4394 case AMOVDU: 4395 return OPVCC(58, 0, 0, 1) /* ldu */ 4396 case AMOVWZ: 4397 return OPVCC(32, 0, 0, 0) /* lwz */ 4398 case AMOVWZU: 4399 return OPVCC(33, 0, 0, 0) /* lwzu */ 4400 case AMOVW: 4401 return OPVCC(58, 0, 0, 0) | 1<<1 /* lwa */ 4402 4403 /* no AMOVWU */ 4404 case AMOVB, AMOVBZ: 4405 return OPVCC(34, 0, 0, 0) 4406 /* load */ 4407 4408 case AMOVBU, AMOVBZU: 4409 return OPVCC(35, 0, 0, 0) 4410 case AFMOVD: 4411 return OPVCC(50, 0, 0, 0) 4412 case AFMOVDU: 4413 return OPVCC(51, 0, 0, 0) 4414 case AFMOVS: 4415 return OPVCC(48, 0, 0, 0) 4416 case AFMOVSU: 4417 return OPVCC(49, 0, 0, 0) 4418 case AMOVH: 4419 return OPVCC(42, 0, 0, 0) 4420 case AMOVHU: 4421 return OPVCC(43, 0, 0, 0) 4422 case AMOVHZ: 4423 return OPVCC(40, 0, 0, 0) 4424 case AMOVHZU: 4425 return OPVCC(41, 0, 0, 0) 4426 case AMOVMW: 4427 return OPVCC(46, 0, 0, 0) /* lmw */ 4428 } 4429 4430 ctxt.Diag("bad load opcode %v", a) 4431 return 0 4432 } 4433 4434 /* 4435 * indexed load a(b),d 4436 */ 4437 func oploadx(ctxt *obj.Link, a obj.As) uint32 { 4438 switch a { 4439 case AMOVWZ: 4440 return OPVCC(31, 23, 0, 0) /* lwzx */ 4441 case AMOVWZU: 4442 return OPVCC(31, 55, 0, 0) /* lwzux */ 4443 case AMOVW: 4444 return OPVCC(31, 341, 0, 0) /* lwax */ 4445 case AMOVWU: 4446 return OPVCC(31, 373, 0, 0) /* lwaux */ 4447 4448 case AMOVB, AMOVBZ: 4449 return OPVCC(31, 87, 0, 0) /* lbzx */ 4450 4451 case AMOVBU, AMOVBZU: 4452 return OPVCC(31, 119, 0, 0) /* lbzux */ 4453 case AFMOVD: 4454 return OPVCC(31, 599, 0, 0) /* lfdx */ 4455 case AFMOVDU: 4456 return OPVCC(31, 631, 0, 0) /* lfdux */ 4457 case AFMOVS: 4458 return OPVCC(31, 535, 0, 0) /* lfsx */ 4459 case AFMOVSU: 4460 return OPVCC(31, 567, 0, 0) /* lfsux */ 4461 case AFMOVSX: 4462 return OPVCC(31, 855, 0, 0) /* lfiwax - power6, isa 2.05 */ 4463 case AFMOVSZ: 4464 return OPVCC(31, 887, 0, 0) /* lfiwzx - power7, isa 2.06 */ 4465 case AMOVH: 4466 return OPVCC(31, 343, 0, 0) /* lhax */ 4467 case AMOVHU: 4468 return OPVCC(31, 375, 0, 0) /* lhaux */ 4469 case AMOVHBR: 4470 return OPVCC(31, 790, 0, 0) /* lhbrx */ 4471 case AMOVWBR: 4472 return OPVCC(31, 534, 0, 0) /* lwbrx */ 4473 case AMOVDBR: 4474 return OPVCC(31, 532, 0, 0) /* ldbrx */ 4475 case AMOVHZ: 4476 return OPVCC(31, 279, 0, 0) /* lhzx */ 4477 case AMOVHZU: 4478 return OPVCC(31, 311, 0, 0) /* lhzux */ 4479 case AECIWX: 4480 return OPVCC(31, 310, 0, 0) /* eciwx */ 4481 case ALBAR: 4482 return OPVCC(31, 52, 0, 0) /* lbarx */ 4483 case ALWAR: 4484 return OPVCC(31, 20, 0, 0) /* lwarx */ 4485 case ALDAR: 4486 return OPVCC(31, 84, 0, 0) 4487 case ALSW: 4488 return OPVCC(31, 533, 0, 0) /* lswx */ 4489 case AMOVD: 4490 return OPVCC(31, 21, 0, 0) /* ldx */ 4491 case AMOVDU: 4492 return OPVCC(31, 53, 0, 0) /* ldux */ 4493 4494 /* Vector (VMX/Altivec) instructions */ 4495 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4496 /* are enabled starting at POWER6 (ISA 2.05). */ 4497 case ALVEBX: 4498 return OPVCC(31, 7, 0, 0) /* lvebx - v2.03 */ 4499 case ALVEHX: 4500 return OPVCC(31, 39, 0, 0) /* lvehx - v2.03 */ 4501 case ALVEWX: 4502 return OPVCC(31, 71, 0, 0) /* lvewx - v2.03 */ 4503 case ALVX: 4504 return OPVCC(31, 103, 0, 0) /* lvx - v2.03 */ 4505 case ALVXL: 4506 return OPVCC(31, 359, 0, 0) /* lvxl - v2.03 */ 4507 case ALVSL: 4508 return OPVCC(31, 6, 0, 0) /* lvsl - v2.03 */ 4509 case ALVSR: 4510 return OPVCC(31, 38, 0, 0) /* lvsr - v2.03 */ 4511 /* End of vector instructions */ 4512 4513 /* Vector scalar (VSX) instructions */ 4514 /* ISA 2.06 enables these for POWER7. */ 4515 case ALXVD2X: 4516 return OPVXX1(31, 844, 0) /* lxvd2x - v2.06 */ 4517 case ALXVDSX: 4518 return OPVXX1(31, 332, 0) /* lxvdsx - v2.06 */ 4519 case ALXVW4X: 4520 return OPVXX1(31, 780, 0) /* lxvw4x - v2.06 */ 4521 4522 case ALXSDX: 4523 return OPVXX1(31, 588, 0) /* lxsdx - v2.06 */ 4524 4525 case ALXSIWAX: 4526 return OPVXX1(31, 76, 0) /* lxsiwax - v2.07 */ 4527 case ALXSIWZX: 4528 return OPVXX1(31, 12, 0) /* lxsiwzx - v2.07 */ 4529 /* End of vector scalar instructions */ 4530 4531 } 4532 4533 ctxt.Diag("bad loadx opcode %v", a) 4534 return 0 4535 } 4536 4537 /* 4538 * store s,o(d) 4539 */ 4540 func opstore(ctxt *obj.Link, a obj.As) uint32 { 4541 switch a { 4542 case AMOVB, AMOVBZ: 4543 return OPVCC(38, 0, 0, 0) /* stb */ 4544 4545 case AMOVBU, AMOVBZU: 4546 return OPVCC(39, 0, 0, 0) /* stbu */ 4547 case AFMOVD: 4548 return OPVCC(54, 0, 0, 0) /* stfd */ 4549 case AFMOVDU: 4550 return OPVCC(55, 0, 0, 0) /* stfdu */ 4551 case AFMOVS: 4552 return OPVCC(52, 0, 0, 0) /* stfs */ 4553 case AFMOVSU: 4554 return OPVCC(53, 0, 0, 0) /* stfsu */ 4555 4556 case AMOVHZ, AMOVH: 4557 return OPVCC(44, 0, 0, 0) /* sth */ 4558 4559 case AMOVHZU, AMOVHU: 4560 return OPVCC(45, 0, 0, 0) /* sthu */ 4561 case AMOVMW: 4562 return OPVCC(47, 0, 0, 0) /* stmw */ 4563 case ASTSW: 4564 return OPVCC(31, 725, 0, 0) /* stswi */ 4565 4566 case AMOVWZ, AMOVW: 4567 return OPVCC(36, 0, 0, 0) /* stw */ 4568 4569 case AMOVWZU, AMOVWU: 4570 return OPVCC(37, 0, 0, 0) /* stwu */ 4571 case AMOVD: 4572 return OPVCC(62, 0, 0, 0) /* std */ 4573 case AMOVDU: 4574 return OPVCC(62, 0, 0, 1) /* stdu */ 4575 } 4576 4577 ctxt.Diag("unknown store opcode %v", a) 4578 return 0 4579 } 4580 4581 /* 4582 * indexed store s,a(b) 4583 */ 4584 func opstorex(ctxt *obj.Link, a obj.As) uint32 { 4585 switch a { 4586 case AMOVB, AMOVBZ: 4587 return OPVCC(31, 215, 0, 0) /* stbx */ 4588 4589 case AMOVBU, AMOVBZU: 4590 return OPVCC(31, 247, 0, 0) /* stbux */ 4591 case AFMOVD: 4592 return OPVCC(31, 727, 0, 0) /* stfdx */ 4593 case AFMOVDU: 4594 return OPVCC(31, 759, 0, 0) /* stfdux */ 4595 case AFMOVS: 4596 return OPVCC(31, 663, 0, 0) /* stfsx */ 4597 case AFMOVSU: 4598 return OPVCC(31, 695, 0, 0) /* stfsux */ 4599 case AFMOVSX: 4600 return OPVCC(31, 983, 0, 0) /* stfiwx */ 4601 4602 case AMOVHZ, AMOVH: 4603 return OPVCC(31, 407, 0, 0) /* sthx */ 4604 case AMOVHBR: 4605 return OPVCC(31, 918, 0, 0) /* sthbrx */ 4606 4607 case AMOVHZU, AMOVHU: 4608 return OPVCC(31, 439, 0, 0) /* sthux */ 4609 4610 case AMOVWZ, AMOVW: 4611 return OPVCC(31, 151, 0, 0) /* stwx */ 4612 4613 case AMOVWZU, AMOVWU: 4614 return OPVCC(31, 183, 0, 0) /* stwux */ 4615 case ASTSW: 4616 return OPVCC(31, 661, 0, 0) /* stswx */ 4617 case AMOVWBR: 4618 return OPVCC(31, 662, 0, 0) /* stwbrx */ 4619 case ASTBCCC: 4620 return OPVCC(31, 694, 0, 1) /* stbcx. */ 4621 case ASTWCCC: 4622 return OPVCC(31, 150, 0, 1) /* stwcx. */ 4623 case ASTDCCC: 4624 return OPVCC(31, 214, 0, 1) /* stwdx. */ 4625 case AECOWX: 4626 return OPVCC(31, 438, 0, 0) /* ecowx */ 4627 case AMOVD: 4628 return OPVCC(31, 149, 0, 0) /* stdx */ 4629 case AMOVDU: 4630 return OPVCC(31, 181, 0, 0) /* stdux */ 4631 4632 /* Vector (VMX/Altivec) instructions */ 4633 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4634 /* are enabled starting at POWER6 (ISA 2.05). */ 4635 case ASTVEBX: 4636 return OPVCC(31, 135, 0, 0) /* stvebx - v2.03 */ 4637 case ASTVEHX: 4638 return OPVCC(31, 167, 0, 0) /* stvehx - v2.03 */ 4639 case ASTVEWX: 4640 return OPVCC(31, 199, 0, 0) /* stvewx - v2.03 */ 4641 case ASTVX: 4642 return OPVCC(31, 231, 0, 0) /* stvx - v2.03 */ 4643 case ASTVXL: 4644 return OPVCC(31, 487, 0, 0) /* stvxl - v2.03 */ 4645 /* End of vector instructions */ 4646 4647 /* Vector scalar (VSX) instructions */ 4648 /* ISA 2.06 enables these for POWER7. */ 4649 case ASTXVD2X: 4650 return OPVXX1(31, 972, 0) /* stxvd2x - v2.06 */ 4651 case ASTXVW4X: 4652 return OPVXX1(31, 908, 0) /* stxvw4x - v2.06 */ 4653 4654 case ASTXSDX: 4655 return OPVXX1(31, 716, 0) /* stxsdx - v2.06 */ 4656 4657 case ASTXSIWX: 4658 return OPVXX1(31, 140, 0) /* stxsiwx - v2.07 */ 4659 /* End of vector scalar instructions */ 4660 4661 } 4662 4663 ctxt.Diag("unknown storex opcode %v", a) 4664 return 0 4665 }