github.com/rakyll/go@v0.0.0-20170216000551-64c02460d703/src/cmd/internal/obj/s390x/asmz.go (about) 1 // Based on cmd/internal/obj/ppc64/asm9.go. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package s390x 31 32 import ( 33 "cmd/internal/obj" 34 "log" 35 "math" 36 "sort" 37 ) 38 39 // instruction layout. 40 const ( 41 funcAlign = 16 42 ) 43 44 type Optab struct { 45 as obj.As // opcode 46 a1 uint8 // From 47 a2 uint8 // Reg 48 a3 uint8 // From3 49 a4 uint8 // To 50 type_ int8 51 param int16 // REGSP for auto variables 52 } 53 54 var optab = []Optab{ 55 // instruction, From, Reg, From3, To, type, param 56 Optab{obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0}, 57 Optab{obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0}, 58 59 // move register 60 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 61 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 62 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 63 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 64 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 65 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 1, 0}, 66 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 67 68 // load constant 69 Optab{AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 70 Optab{AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 71 Optab{AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 72 Optab{AMOVD, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 73 Optab{AMOVW, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 74 Optab{AMOVWZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 75 Optab{AMOVB, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 76 Optab{AMOVBZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 77 78 // store constant 79 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 80 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 81 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 82 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 83 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 84 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 85 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 86 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 87 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 88 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 89 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 90 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 91 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 92 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 93 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 94 95 // store 96 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 97 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 98 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 99 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 100 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 101 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 102 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 103 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 104 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 105 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 106 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 107 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 108 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 109 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 110 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 111 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 112 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 113 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 114 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 115 116 // load 117 Optab{AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 118 Optab{AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 119 Optab{AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 120 Optab{AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 121 Optab{AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 122 Optab{AMOVDBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 123 Optab{AMOVHBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 124 Optab{AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 125 Optab{AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 126 Optab{AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 127 Optab{AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 128 Optab{AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 129 Optab{AMOVDBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 130 Optab{AMOVHBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 131 Optab{AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 132 Optab{AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 133 Optab{AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 134 Optab{AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 135 Optab{AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 136 137 // interlocked load and op 138 Optab{ALAAG, C_REG, C_REG, C_NONE, C_LOREG, 99, 0}, 139 140 // integer arithmetic 141 Optab{AADD, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 142 Optab{AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 143 Optab{AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 0}, 144 Optab{AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 0}, 145 Optab{AADD, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 146 Optab{AADD, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 147 Optab{ASUB, C_LCON, C_REG, C_NONE, C_REG, 21, 0}, 148 Optab{ASUB, C_LCON, C_NONE, C_NONE, C_REG, 21, 0}, 149 Optab{ASUB, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 150 Optab{ASUB, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 151 Optab{AMULHD, C_REG, C_NONE, C_NONE, C_REG, 4, 0}, 152 Optab{AMULHD, C_REG, C_REG, C_NONE, C_REG, 4, 0}, 153 Optab{ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 154 Optab{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 155 Optab{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 0}, 156 Optab{ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 0}, 157 Optab{ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 0}, 158 Optab{ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 0}, 159 160 // integer logical 161 Optab{AAND, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 162 Optab{AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 163 Optab{AAND, C_LCON, C_NONE, C_NONE, C_REG, 23, 0}, 164 Optab{AAND, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 165 Optab{AAND, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 166 Optab{AANDW, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 167 Optab{AANDW, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 168 Optab{AANDW, C_LCON, C_NONE, C_NONE, C_REG, 24, 0}, 169 Optab{AANDW, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 170 Optab{AANDW, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 171 Optab{ASLD, C_REG, C_NONE, C_NONE, C_REG, 7, 0}, 172 Optab{ASLD, C_REG, C_REG, C_NONE, C_REG, 7, 0}, 173 Optab{ASLD, C_SCON, C_REG, C_NONE, C_REG, 7, 0}, 174 Optab{ASLD, C_SCON, C_NONE, C_NONE, C_REG, 7, 0}, 175 176 // compare and swap 177 Optab{ACSG, C_REG, C_REG, C_NONE, C_SOREG, 79, 0}, 178 179 // floating point 180 Optab{AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 181 Optab{AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 0}, 182 Optab{AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 0}, 183 Optab{AFMADD, C_FREG, C_FREG, C_NONE, C_FREG, 34, 0}, 184 Optab{AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 185 Optab{AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, REGSP}, 186 Optab{AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 0}, 187 Optab{AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 0}, 188 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 189 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 0}, 190 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 0}, 191 Optab{AFMOVD, C_ZCON, C_NONE, C_NONE, C_FREG, 67, 0}, 192 Optab{ACEFBRA, C_REG, C_NONE, C_NONE, C_FREG, 82, 0}, 193 Optab{ACFEBRA, C_FREG, C_NONE, C_NONE, C_REG, 83, 0}, 194 Optab{AFIEBR, C_SCON, C_FREG, C_NONE, C_FREG, 48, 0}, 195 196 // load symbol address (plus offset) 197 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_REG, 19, 0}, 198 Optab{AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 93, 0}, 199 Optab{AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 94, 0}, 200 Optab{AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 95, 0}, 201 202 // system call 203 Optab{ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 0}, 204 Optab{ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 0}, 205 206 // branch 207 Optab{ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 0}, 208 Optab{ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 0}, 209 Optab{ABC, C_SCON, C_REG, C_NONE, C_LBRA, 16, 0}, 210 Optab{ABR, C_NONE, C_NONE, C_NONE, C_REG, 18, 0}, 211 Optab{ABR, C_REG, C_NONE, C_NONE, C_REG, 18, 0}, 212 Optab{ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 213 Optab{ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 214 Optab{ACMPBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 215 Optab{ACMPBEQ, C_REG, C_NONE, C_ADDCON, C_SBRA, 90, 0}, 216 Optab{ACMPBEQ, C_REG, C_NONE, C_SCON, C_SBRA, 90, 0}, 217 Optab{ACMPUBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 218 Optab{ACMPUBEQ, C_REG, C_NONE, C_ANDCON, C_SBRA, 90, 0}, 219 220 // move on condition 221 Optab{AMOVDEQ, C_REG, C_NONE, C_NONE, C_REG, 17, 0}, 222 223 // find leftmost one 224 Optab{AFLOGR, C_REG, C_NONE, C_NONE, C_REG, 8, 0}, 225 226 // compare 227 Optab{ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 228 Optab{ACMP, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 229 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 230 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 231 Optab{AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 0}, 232 Optab{AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 0}, 233 234 // 32-bit access registers 235 Optab{AMOVW, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 236 Optab{AMOVWZ, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 237 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 238 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 239 240 // macros 241 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LOREG, 96, 0}, 242 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LAUTO, 96, REGSP}, 243 244 // load/store multiple 245 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LOREG, 97, 0}, 246 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LAUTO, 97, REGSP}, 247 Optab{ALMG, C_LOREG, C_REG, C_NONE, C_REG, 98, 0}, 248 Optab{ALMG, C_LAUTO, C_REG, C_NONE, C_REG, 98, REGSP}, 249 250 // bytes 251 Optab{ABYTE, C_SCON, C_NONE, C_NONE, C_NONE, 40, 0}, 252 Optab{AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 0}, 253 Optab{ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 0}, 254 Optab{ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 0}, 255 256 // fast synchronization 257 Optab{ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 81, 0}, 258 259 // store clock 260 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SAUTO, 88, REGSP}, 261 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SOREG, 88, 0}, 262 263 // storage and storage 264 Optab{AMVC, C_LOREG, C_NONE, C_SCON, C_LOREG, 84, 0}, 265 Optab{AMVC, C_LOREG, C_NONE, C_SCON, C_LAUTO, 84, REGSP}, 266 Optab{AMVC, C_LAUTO, C_NONE, C_SCON, C_LAUTO, 84, REGSP}, 267 268 // address 269 Optab{ALARL, C_LCON, C_NONE, C_NONE, C_REG, 85, 0}, 270 Optab{ALARL, C_SYMADDR, C_NONE, C_NONE, C_REG, 85, 0}, 271 Optab{ALA, C_SOREG, C_NONE, C_NONE, C_REG, 86, 0}, 272 Optab{ALA, C_SAUTO, C_NONE, C_NONE, C_REG, 86, REGSP}, 273 Optab{AEXRL, C_SYMADDR, C_NONE, C_NONE, C_REG, 87, 0}, 274 275 // misc 276 Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 0}, 277 Optab{obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0}, 278 Optab{obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0}, 279 Optab{obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0}, 280 Optab{obj.ANOP, C_SAUTO, C_NONE, C_NONE, C_NONE, 0, 0}, 281 282 // vector instructions 283 284 // VRX store 285 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SOREG, 100, 0}, 286 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SAUTO, 100, REGSP}, 287 Optab{AVSTEG, C_VREG, C_NONE, C_SCON, C_SOREG, 100, 0}, 288 Optab{AVSTEG, C_VREG, C_NONE, C_SCON, C_SAUTO, 100, REGSP}, 289 290 // VRX load 291 Optab{AVL, C_SOREG, C_NONE, C_NONE, C_VREG, 101, 0}, 292 Optab{AVL, C_SAUTO, C_NONE, C_NONE, C_VREG, 101, REGSP}, 293 Optab{AVLEG, C_SOREG, C_NONE, C_SCON, C_VREG, 101, 0}, 294 Optab{AVLEG, C_SAUTO, C_NONE, C_SCON, C_VREG, 101, REGSP}, 295 296 // VRV scatter 297 Optab{AVSCEG, C_VREG, C_NONE, C_SCON, C_SOREG, 102, 0}, 298 Optab{AVSCEG, C_VREG, C_NONE, C_SCON, C_SAUTO, 102, REGSP}, 299 300 // VRV gather 301 Optab{AVGEG, C_SOREG, C_NONE, C_SCON, C_VREG, 103, 0}, 302 Optab{AVGEG, C_SAUTO, C_NONE, C_SCON, C_VREG, 103, REGSP}, 303 304 // VRS element shift/rotate and load gr to/from vr element 305 Optab{AVESLG, C_SCON, C_VREG, C_NONE, C_VREG, 104, 0}, 306 Optab{AVESLG, C_REG, C_VREG, C_NONE, C_VREG, 104, 0}, 307 Optab{AVESLG, C_SCON, C_NONE, C_NONE, C_VREG, 104, 0}, 308 Optab{AVESLG, C_REG, C_NONE, C_NONE, C_VREG, 104, 0}, 309 Optab{AVLGVG, C_SCON, C_VREG, C_NONE, C_REG, 104, 0}, 310 Optab{AVLGVG, C_REG, C_VREG, C_NONE, C_REG, 104, 0}, 311 Optab{AVLVGG, C_SCON, C_REG, C_NONE, C_VREG, 104, 0}, 312 Optab{AVLVGG, C_REG, C_REG, C_NONE, C_VREG, 104, 0}, 313 314 // VRS store multiple 315 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SOREG, 105, 0}, 316 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SAUTO, 105, REGSP}, 317 318 // VRS load multiple 319 Optab{AVLM, C_SOREG, C_VREG, C_NONE, C_VREG, 106, 0}, 320 Optab{AVLM, C_SAUTO, C_VREG, C_NONE, C_VREG, 106, REGSP}, 321 322 // VRS store with length 323 Optab{AVSTL, C_VREG, C_NONE, C_REG, C_SOREG, 107, 0}, 324 Optab{AVSTL, C_VREG, C_NONE, C_REG, C_SAUTO, 107, REGSP}, 325 326 // VRS load with length 327 Optab{AVLL, C_SOREG, C_NONE, C_REG, C_VREG, 108, 0}, 328 Optab{AVLL, C_SAUTO, C_NONE, C_REG, C_VREG, 108, REGSP}, 329 330 // VRI-a 331 Optab{AVGBM, C_ANDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 332 Optab{AVZERO, C_NONE, C_NONE, C_NONE, C_VREG, 109, 0}, 333 Optab{AVREPIG, C_ADDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 334 Optab{AVREPIG, C_SCON, C_NONE, C_NONE, C_VREG, 109, 0}, 335 Optab{AVLEIG, C_ADDCON, C_NONE, C_SCON, C_VREG, 109, 0}, 336 Optab{AVLEIG, C_SCON, C_NONE, C_SCON, C_VREG, 109, 0}, 337 338 // VRI-b generate mask 339 Optab{AVGMG, C_SCON, C_NONE, C_SCON, C_VREG, 110, 0}, 340 341 // VRI-c replicate 342 Optab{AVREPG, C_UCON, C_VREG, C_NONE, C_VREG, 111, 0}, 343 344 // VRI-d element rotate and insert under mask and 345 // shift left double by byte 346 Optab{AVERIMG, C_VREG, C_VREG, C_SCON, C_VREG, 112, 0}, 347 Optab{AVSLDB, C_VREG, C_VREG, C_SCON, C_VREG, 112, 0}, 348 349 // VRI-d fp test data class immediate 350 Optab{AVFTCIDB, C_SCON, C_VREG, C_NONE, C_VREG, 113, 0}, 351 352 // VRR-a load reg 353 Optab{AVLR, C_VREG, C_NONE, C_NONE, C_VREG, 114, 0}, 354 355 // VRR-a compare 356 Optab{AVECG, C_VREG, C_NONE, C_NONE, C_VREG, 115, 0}, 357 358 // VRR-b 359 Optab{AVCEQG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 360 Optab{AVFAEF, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 361 Optab{AVPKSG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 362 363 // VRR-c 364 Optab{AVAQ, C_VREG, C_VREG, C_NONE, C_VREG, 118, 0}, 365 Optab{AVAQ, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 366 Optab{AVNOT, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 367 Optab{AVPDI, C_VREG, C_VREG, C_SCON, C_VREG, 123, 0}, 368 369 // VRR-c shifts 370 Optab{AVERLLVG, C_VREG, C_VREG, C_NONE, C_VREG, 119, 0}, 371 Optab{AVERLLVG, C_VREG, C_NONE, C_NONE, C_VREG, 119, 0}, 372 373 // VRR-d 374 // 2 3 1 4 375 Optab{AVACQ, C_VREG, C_VREG, C_VREG, C_VREG, 120, 0}, 376 377 // VRR-e 378 Optab{AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 121, 0}, 379 380 // VRR-f 381 Optab{AVLVGP, C_REG, C_REG, C_NONE, C_VREG, 122, 0}, 382 } 383 384 var oprange [ALAST & obj.AMask][]Optab 385 386 var xcmp [C_NCLASS][C_NCLASS]bool 387 388 func spanz(ctxt *obj.Link, cursym *obj.LSym) { 389 p := cursym.Text 390 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 391 return 392 } 393 ctxt.Cursym = cursym 394 ctxt.Autosize = int32(p.To.Offset) 395 396 if oprange[AORW&obj.AMask] == nil { 397 buildop(ctxt) 398 } 399 400 buffer := make([]byte, 0) 401 changed := true 402 loop := 0 403 for changed { 404 if loop > 10 { 405 ctxt.Diag("stuck in spanz loop") 406 break 407 } 408 changed = false 409 buffer = buffer[:0] 410 ctxt.Cursym.R = make([]obj.Reloc, 0) 411 for p := cursym.Text; p != nil; p = p.Link { 412 pc := int64(len(buffer)) 413 if pc != p.Pc { 414 changed = true 415 } 416 p.Pc = pc 417 ctxt.Pc = p.Pc 418 ctxt.Curp = p 419 asmout(ctxt, &buffer) 420 if pc == int64(len(buffer)) { 421 switch p.As { 422 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT: 423 // ok 424 default: 425 ctxt.Diag("zero-width instruction\n%v", p) 426 } 427 } 428 } 429 loop++ 430 } 431 432 cursym.Size = int64(len(buffer)) 433 if cursym.Size%funcAlign != 0 { 434 cursym.Size += funcAlign - (cursym.Size % funcAlign) 435 } 436 cursym.Grow(cursym.Size) 437 copy(cursym.P, buffer) 438 } 439 440 func isint32(v int64) bool { 441 return int64(int32(v)) == v 442 } 443 444 func isuint32(v uint64) bool { 445 return uint64(uint32(v)) == v 446 } 447 448 func aclass(ctxt *obj.Link, a *obj.Addr) int { 449 switch a.Type { 450 case obj.TYPE_NONE: 451 return C_NONE 452 453 case obj.TYPE_REG: 454 if REG_R0 <= a.Reg && a.Reg <= REG_R15 { 455 return C_REG 456 } 457 if REG_F0 <= a.Reg && a.Reg <= REG_F15 { 458 return C_FREG 459 } 460 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 { 461 return C_AREG 462 } 463 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 464 return C_VREG 465 } 466 return C_GOK 467 468 case obj.TYPE_MEM: 469 switch a.Name { 470 case obj.NAME_EXTERN, 471 obj.NAME_STATIC: 472 if a.Sym == nil { 473 // must have a symbol 474 break 475 } 476 ctxt.Instoffset = a.Offset 477 if a.Sym.Type == obj.STLSBSS { 478 if ctxt.Flag_shared { 479 return C_TLS_IE // initial exec model 480 } 481 return C_TLS_LE // local exec model 482 } 483 return C_ADDR 484 485 case obj.NAME_GOTREF: 486 return C_GOTADDR 487 488 case obj.NAME_AUTO: 489 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset 490 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 491 return C_SAUTO 492 } 493 return C_LAUTO 494 495 case obj.NAME_PARAM: 496 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + ctxt.FixedFrameSize() 497 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 498 return C_SAUTO 499 } 500 return C_LAUTO 501 502 case obj.NAME_NONE: 503 ctxt.Instoffset = a.Offset 504 if ctxt.Instoffset == 0 { 505 return C_ZOREG 506 } 507 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 508 return C_SOREG 509 } 510 return C_LOREG 511 } 512 513 return C_GOK 514 515 case obj.TYPE_TEXTSIZE: 516 return C_TEXTSIZE 517 518 case obj.TYPE_FCONST: 519 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 { 520 return C_ZCON 521 } 522 ctxt.Diag("cannot handle the floating point constant %v", a.Val) 523 524 case obj.TYPE_CONST, 525 obj.TYPE_ADDR: 526 switch a.Name { 527 case obj.NAME_NONE: 528 ctxt.Instoffset = a.Offset 529 if a.Reg != 0 { 530 if -BIG <= ctxt.Instoffset && ctxt.Instoffset <= BIG { 531 return C_SACON 532 } 533 if isint32(ctxt.Instoffset) { 534 return C_LACON 535 } 536 return C_DACON 537 } 538 goto consize 539 540 case obj.NAME_EXTERN, 541 obj.NAME_STATIC: 542 s := a.Sym 543 if s == nil { 544 break 545 } 546 ctxt.Instoffset = a.Offset 547 if s.Type == obj.SCONST { 548 goto consize 549 } 550 551 return C_SYMADDR 552 553 case obj.NAME_AUTO: 554 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset 555 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 556 return C_SACON 557 } 558 return C_LACON 559 560 case obj.NAME_PARAM: 561 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + ctxt.FixedFrameSize() 562 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 563 return C_SACON 564 } 565 return C_LACON 566 } 567 568 return C_GOK 569 570 consize: 571 if ctxt.Instoffset == 0 { 572 return C_ZCON 573 } 574 if ctxt.Instoffset >= 0 { 575 if ctxt.Instoffset <= 0x7fff { 576 return C_SCON 577 } 578 if ctxt.Instoffset <= 0xffff { 579 return C_ANDCON 580 } 581 if ctxt.Instoffset&0xffff == 0 && isuint32(uint64(ctxt.Instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 582 return C_UCON 583 } 584 if isint32(ctxt.Instoffset) || isuint32(uint64(ctxt.Instoffset)) { 585 return C_LCON 586 } 587 return C_DCON 588 } 589 590 if ctxt.Instoffset >= -0x8000 { 591 return C_ADDCON 592 } 593 if ctxt.Instoffset&0xffff == 0 && isint32(ctxt.Instoffset) { 594 return C_UCON 595 } 596 if isint32(ctxt.Instoffset) { 597 return C_LCON 598 } 599 return C_DCON 600 601 case obj.TYPE_BRANCH: 602 return C_SBRA 603 } 604 605 return C_GOK 606 } 607 608 func oplook(ctxt *obj.Link, p *obj.Prog) *Optab { 609 a1 := int(p.Optab) 610 if a1 != 0 { 611 return &optab[a1-1] 612 } 613 a1 = int(p.From.Class) 614 if a1 == 0 { 615 a1 = aclass(ctxt, &p.From) + 1 616 p.From.Class = int8(a1) 617 } 618 619 a1-- 620 a3 := C_NONE + 1 621 if p.From3 != nil { 622 a3 = int(p.From3.Class) 623 if a3 == 0 { 624 a3 = aclass(ctxt, p.From3) + 1 625 p.From3.Class = int8(a3) 626 } 627 } 628 629 a3-- 630 a4 := int(p.To.Class) 631 if a4 == 0 { 632 a4 = aclass(ctxt, &p.To) + 1 633 p.To.Class = int8(a4) 634 } 635 636 a4-- 637 a2 := C_NONE 638 if p.Reg != 0 { 639 if REG_R0 <= p.Reg && p.Reg <= REG_R15 { 640 a2 = C_REG 641 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 642 a2 = C_VREG 643 } else if REG_F0 <= p.Reg && p.Reg <= REG_F15 { 644 a2 = C_FREG 645 } else if REG_AR0 <= p.Reg && p.Reg <= REG_AR15 { 646 a2 = C_AREG 647 } 648 } 649 650 ops := oprange[p.As&obj.AMask] 651 c1 := &xcmp[a1] 652 c2 := &xcmp[a2] 653 c3 := &xcmp[a3] 654 c4 := &xcmp[a4] 655 for i := range ops { 656 op := &ops[i] 657 if (int(op.a2) == a2 || c2[op.a2]) && c4[op.a4] && c1[op.a1] && c3[op.a3] { 658 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 659 return op 660 } 661 } 662 663 // cannot find a case; abort 664 ctxt.Diag("illegal combination %v %v %v %v %v\n", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 665 ctxt.Diag("prog: %v\n", p) 666 return nil 667 } 668 669 func cmp(a int, b int) bool { 670 if a == b { 671 return true 672 } 673 switch a { 674 case C_DCON: 675 if b == C_LCON { 676 return true 677 } 678 fallthrough 679 case C_LCON: 680 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 681 return true 682 } 683 684 case C_ADDCON: 685 if b == C_ZCON || b == C_SCON { 686 return true 687 } 688 689 case C_ANDCON: 690 if b == C_ZCON || b == C_SCON { 691 return true 692 } 693 694 case C_UCON: 695 if b == C_ZCON || b == C_SCON { 696 return true 697 } 698 699 case C_SCON: 700 if b == C_ZCON { 701 return true 702 } 703 704 case C_LACON: 705 if b == C_SACON { 706 return true 707 } 708 709 case C_LBRA: 710 if b == C_SBRA { 711 return true 712 } 713 714 case C_LAUTO: 715 if b == C_SAUTO { 716 return true 717 } 718 719 case C_LOREG: 720 if b == C_ZOREG || b == C_SOREG { 721 return true 722 } 723 724 case C_SOREG: 725 if b == C_ZOREG { 726 return true 727 } 728 729 case C_ANY: 730 return true 731 } 732 733 return false 734 } 735 736 type ocmp []Optab 737 738 func (x ocmp) Len() int { 739 return len(x) 740 } 741 742 func (x ocmp) Swap(i, j int) { 743 x[i], x[j] = x[j], x[i] 744 } 745 746 func (x ocmp) Less(i, j int) bool { 747 p1 := &x[i] 748 p2 := &x[j] 749 n := int(p1.as) - int(p2.as) 750 if n != 0 { 751 return n < 0 752 } 753 n = int(p1.a1) - int(p2.a1) 754 if n != 0 { 755 return n < 0 756 } 757 n = int(p1.a2) - int(p2.a2) 758 if n != 0 { 759 return n < 0 760 } 761 n = int(p1.a3) - int(p2.a3) 762 if n != 0 { 763 return n < 0 764 } 765 n = int(p1.a4) - int(p2.a4) 766 if n != 0 { 767 return n < 0 768 } 769 return false 770 } 771 func opset(a, b obj.As) { 772 oprange[a&obj.AMask] = oprange[b&obj.AMask] 773 } 774 775 func buildop(ctxt *obj.Link) { 776 for i := 0; i < C_NCLASS; i++ { 777 for n := 0; n < C_NCLASS; n++ { 778 if cmp(n, i) { 779 xcmp[i][n] = true 780 } 781 } 782 } 783 sort.Sort(ocmp(optab)) 784 for i := 0; i < len(optab); i++ { 785 r := optab[i].as 786 start := i 787 for ; i+1 < len(optab); i++ { 788 if optab[i+1].as != r { 789 break 790 } 791 } 792 oprange[r&obj.AMask] = optab[start : i+1] 793 794 // opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array. 795 // oprange[] is used by oplook() to find the Optab entry that applies to a given Prog. 796 switch r { 797 case AADD: 798 opset(AADDC, r) 799 opset(AADDW, r) 800 opset(AMULLD, r) 801 opset(AMULLW, r) 802 case ADIVW: 803 opset(AADDE, r) 804 opset(ADIVD, r) 805 opset(ADIVDU, r) 806 opset(ADIVWU, r) 807 opset(AMODD, r) 808 opset(AMODDU, r) 809 opset(AMODW, r) 810 opset(AMODWU, r) 811 case AMULHD: 812 opset(AMULHDU, r) 813 case AMOVBZ: 814 opset(AMOVH, r) 815 opset(AMOVHZ, r) 816 case ALA: 817 opset(ALAY, r) 818 case AMVC: 819 opset(ACLC, r) 820 opset(AXC, r) 821 opset(AOC, r) 822 opset(ANC, r) 823 case ASTCK: 824 opset(ASTCKC, r) 825 opset(ASTCKE, r) 826 opset(ASTCKF, r) 827 case ALAAG: 828 opset(ALAA, r) 829 opset(ALAAL, r) 830 opset(ALAALG, r) 831 opset(ALAN, r) 832 opset(ALANG, r) 833 opset(ALAX, r) 834 opset(ALAXG, r) 835 opset(ALAO, r) 836 opset(ALAOG, r) 837 case ASTMG: 838 opset(ASTMY, r) 839 case ALMG: 840 opset(ALMY, r) 841 case ABEQ: 842 opset(ABGE, r) 843 opset(ABGT, r) 844 opset(ABLE, r) 845 opset(ABLT, r) 846 opset(ABNE, r) 847 opset(ABVC, r) 848 opset(ABVS, r) 849 opset(ABLEU, r) 850 opset(ABLTU, r) 851 case ABR: 852 opset(ABL, r) 853 case ABC: 854 opset(ABCL, r) 855 case AFABS: 856 opset(AFNABS, r) 857 opset(AFNEG, r) 858 opset(AFNEGS, r) 859 opset(ALEDBR, r) 860 opset(ALDEBR, r) 861 opset(AFSQRT, r) 862 opset(AFSQRTS, r) 863 case AFADD: 864 opset(AFADDS, r) 865 opset(AFDIV, r) 866 opset(AFDIVS, r) 867 opset(AFSUB, r) 868 opset(AFSUBS, r) 869 case AFMADD: 870 opset(AFMADDS, r) 871 opset(AFMSUB, r) 872 opset(AFMSUBS, r) 873 case AFMUL: 874 opset(AFMULS, r) 875 case AFCMPO: 876 opset(AFCMPU, r) 877 opset(ACEBR, r) 878 case AAND: 879 opset(AOR, r) 880 opset(AXOR, r) 881 case AANDW: 882 opset(AORW, r) 883 opset(AXORW, r) 884 case ASLD: 885 opset(ASRD, r) 886 opset(ASLW, r) 887 opset(ASRW, r) 888 opset(ASRAD, r) 889 opset(ASRAW, r) 890 opset(ARLL, r) 891 opset(ARLLG, r) 892 case ACSG: 893 opset(ACS, r) 894 case ASUB: 895 opset(ASUBC, r) 896 opset(ASUBE, r) 897 opset(ASUBW, r) 898 case ANEG: 899 opset(ANEGW, r) 900 case AFMOVD: 901 opset(AFMOVS, r) 902 case AMOVDBR: 903 opset(AMOVWBR, r) 904 case ACMP: 905 opset(ACMPW, r) 906 case ACMPU: 907 opset(ACMPWU, r) 908 case ACEFBRA: 909 opset(ACDFBRA, r) 910 opset(ACEGBRA, r) 911 opset(ACDGBRA, r) 912 opset(ACELFBR, r) 913 opset(ACDLFBR, r) 914 opset(ACELGBR, r) 915 opset(ACDLGBR, r) 916 case ACFEBRA: 917 opset(ACFDBRA, r) 918 opset(ACGEBRA, r) 919 opset(ACGDBRA, r) 920 opset(ACLFEBR, r) 921 opset(ACLFDBR, r) 922 opset(ACLGEBR, r) 923 opset(ACLGDBR, r) 924 case AFIEBR: 925 opset(AFIDBR, r) 926 case ACMPBEQ: 927 opset(ACMPBGE, r) 928 opset(ACMPBGT, r) 929 opset(ACMPBLE, r) 930 opset(ACMPBLT, r) 931 opset(ACMPBNE, r) 932 case ACMPUBEQ: 933 opset(ACMPUBGE, r) 934 opset(ACMPUBGT, r) 935 opset(ACMPUBLE, r) 936 opset(ACMPUBLT, r) 937 opset(ACMPUBNE, r) 938 case AMOVDEQ: 939 opset(AMOVDGE, r) 940 opset(AMOVDGT, r) 941 opset(AMOVDLE, r) 942 opset(AMOVDLT, r) 943 opset(AMOVDNE, r) 944 case AVL: 945 opset(AVLLEZB, r) 946 opset(AVLLEZH, r) 947 opset(AVLLEZF, r) 948 opset(AVLLEZG, r) 949 opset(AVLREPB, r) 950 opset(AVLREPH, r) 951 opset(AVLREPF, r) 952 opset(AVLREPG, r) 953 case AVLEG: 954 opset(AVLBB, r) 955 opset(AVLEB, r) 956 opset(AVLEH, r) 957 opset(AVLEF, r) 958 opset(AVLEG, r) 959 opset(AVLREP, r) 960 case AVSTEG: 961 opset(AVSTEB, r) 962 opset(AVSTEH, r) 963 opset(AVSTEF, r) 964 case AVSCEG: 965 opset(AVSCEF, r) 966 case AVGEG: 967 opset(AVGEF, r) 968 case AVESLG: 969 opset(AVESLB, r) 970 opset(AVESLH, r) 971 opset(AVESLF, r) 972 opset(AVERLLB, r) 973 opset(AVERLLH, r) 974 opset(AVERLLF, r) 975 opset(AVERLLG, r) 976 opset(AVESRAB, r) 977 opset(AVESRAH, r) 978 opset(AVESRAF, r) 979 opset(AVESRAG, r) 980 opset(AVESRLB, r) 981 opset(AVESRLH, r) 982 opset(AVESRLF, r) 983 opset(AVESRLG, r) 984 case AVLGVG: 985 opset(AVLGVB, r) 986 opset(AVLGVH, r) 987 opset(AVLGVF, r) 988 case AVLVGG: 989 opset(AVLVGB, r) 990 opset(AVLVGH, r) 991 opset(AVLVGF, r) 992 case AVZERO: 993 opset(AVONE, r) 994 case AVREPIG: 995 opset(AVREPIB, r) 996 opset(AVREPIH, r) 997 opset(AVREPIF, r) 998 case AVLEIG: 999 opset(AVLEIB, r) 1000 opset(AVLEIH, r) 1001 opset(AVLEIF, r) 1002 case AVGMG: 1003 opset(AVGMB, r) 1004 opset(AVGMH, r) 1005 opset(AVGMF, r) 1006 case AVREPG: 1007 opset(AVREPB, r) 1008 opset(AVREPH, r) 1009 opset(AVREPF, r) 1010 case AVERIMG: 1011 opset(AVERIMB, r) 1012 opset(AVERIMH, r) 1013 opset(AVERIMF, r) 1014 case AVFTCIDB: 1015 opset(AWFTCIDB, r) 1016 case AVLR: 1017 opset(AVUPHB, r) 1018 opset(AVUPHH, r) 1019 opset(AVUPHF, r) 1020 opset(AVUPLHB, r) 1021 opset(AVUPLHH, r) 1022 opset(AVUPLHF, r) 1023 opset(AVUPLB, r) 1024 opset(AVUPLHW, r) 1025 opset(AVUPLF, r) 1026 opset(AVUPLLB, r) 1027 opset(AVUPLLH, r) 1028 opset(AVUPLLF, r) 1029 opset(AVCLZB, r) 1030 opset(AVCLZH, r) 1031 opset(AVCLZF, r) 1032 opset(AVCLZG, r) 1033 opset(AVCTZB, r) 1034 opset(AVCTZH, r) 1035 opset(AVCTZF, r) 1036 opset(AVCTZG, r) 1037 opset(AVLDEB, r) 1038 opset(AWLDEB, r) 1039 opset(AVFLCDB, r) 1040 opset(AWFLCDB, r) 1041 opset(AVFLNDB, r) 1042 opset(AWFLNDB, r) 1043 opset(AVFLPDB, r) 1044 opset(AWFLPDB, r) 1045 opset(AVFSQDB, r) 1046 opset(AWFSQDB, r) 1047 opset(AVISTRB, r) 1048 opset(AVISTRH, r) 1049 opset(AVISTRF, r) 1050 opset(AVISTRBS, r) 1051 opset(AVISTRHS, r) 1052 opset(AVISTRFS, r) 1053 opset(AVLCB, r) 1054 opset(AVLCH, r) 1055 opset(AVLCF, r) 1056 opset(AVLCG, r) 1057 opset(AVLPB, r) 1058 opset(AVLPH, r) 1059 opset(AVLPF, r) 1060 opset(AVLPG, r) 1061 opset(AVPOPCT, r) 1062 opset(AVSEGB, r) 1063 opset(AVSEGH, r) 1064 opset(AVSEGF, r) 1065 case AVECG: 1066 opset(AVECB, r) 1067 opset(AVECH, r) 1068 opset(AVECF, r) 1069 opset(AVECLB, r) 1070 opset(AVECLH, r) 1071 opset(AVECLF, r) 1072 opset(AVECLG, r) 1073 opset(AWFCDB, r) 1074 opset(AWFKDB, r) 1075 case AVCEQG: 1076 opset(AVCEQB, r) 1077 opset(AVCEQH, r) 1078 opset(AVCEQF, r) 1079 opset(AVCEQBS, r) 1080 opset(AVCEQHS, r) 1081 opset(AVCEQFS, r) 1082 opset(AVCEQGS, r) 1083 opset(AVCHB, r) 1084 opset(AVCHH, r) 1085 opset(AVCHF, r) 1086 opset(AVCHG, r) 1087 opset(AVCHBS, r) 1088 opset(AVCHHS, r) 1089 opset(AVCHFS, r) 1090 opset(AVCHGS, r) 1091 opset(AVCHLB, r) 1092 opset(AVCHLH, r) 1093 opset(AVCHLF, r) 1094 opset(AVCHLG, r) 1095 opset(AVCHLBS, r) 1096 opset(AVCHLHS, r) 1097 opset(AVCHLFS, r) 1098 opset(AVCHLGS, r) 1099 case AVFAEF: 1100 opset(AVFAEB, r) 1101 opset(AVFAEH, r) 1102 opset(AVFAEBS, r) 1103 opset(AVFAEHS, r) 1104 opset(AVFAEFS, r) 1105 opset(AVFAEZB, r) 1106 opset(AVFAEZH, r) 1107 opset(AVFAEZF, r) 1108 opset(AVFAEZBS, r) 1109 opset(AVFAEZHS, r) 1110 opset(AVFAEZFS, r) 1111 opset(AVFEEB, r) 1112 opset(AVFEEH, r) 1113 opset(AVFEEF, r) 1114 opset(AVFEEBS, r) 1115 opset(AVFEEHS, r) 1116 opset(AVFEEFS, r) 1117 opset(AVFEEZB, r) 1118 opset(AVFEEZH, r) 1119 opset(AVFEEZF, r) 1120 opset(AVFEEZBS, r) 1121 opset(AVFEEZHS, r) 1122 opset(AVFEEZFS, r) 1123 opset(AVFENEB, r) 1124 opset(AVFENEH, r) 1125 opset(AVFENEF, r) 1126 opset(AVFENEBS, r) 1127 opset(AVFENEHS, r) 1128 opset(AVFENEFS, r) 1129 opset(AVFENEZB, r) 1130 opset(AVFENEZH, r) 1131 opset(AVFENEZF, r) 1132 opset(AVFENEZBS, r) 1133 opset(AVFENEZHS, r) 1134 opset(AVFENEZFS, r) 1135 case AVPKSG: 1136 opset(AVPKSH, r) 1137 opset(AVPKSF, r) 1138 opset(AVPKSHS, r) 1139 opset(AVPKSFS, r) 1140 opset(AVPKSGS, r) 1141 opset(AVPKLSH, r) 1142 opset(AVPKLSF, r) 1143 opset(AVPKLSG, r) 1144 opset(AVPKLSHS, r) 1145 opset(AVPKLSFS, r) 1146 opset(AVPKLSGS, r) 1147 case AVAQ: 1148 opset(AVAB, r) 1149 opset(AVAH, r) 1150 opset(AVAF, r) 1151 opset(AVAG, r) 1152 opset(AVACCB, r) 1153 opset(AVACCH, r) 1154 opset(AVACCF, r) 1155 opset(AVACCG, r) 1156 opset(AVACCQ, r) 1157 opset(AVN, r) 1158 opset(AVNC, r) 1159 opset(AVAVGB, r) 1160 opset(AVAVGH, r) 1161 opset(AVAVGF, r) 1162 opset(AVAVGG, r) 1163 opset(AVAVGLB, r) 1164 opset(AVAVGLH, r) 1165 opset(AVAVGLF, r) 1166 opset(AVAVGLG, r) 1167 opset(AVCKSM, r) 1168 opset(AVX, r) 1169 opset(AVFADB, r) 1170 opset(AWFADB, r) 1171 opset(AVFCEDB, r) 1172 opset(AVFCEDBS, r) 1173 opset(AWFCEDB, r) 1174 opset(AWFCEDBS, r) 1175 opset(AVFCHDB, r) 1176 opset(AVFCHDBS, r) 1177 opset(AWFCHDB, r) 1178 opset(AWFCHDBS, r) 1179 opset(AVFCHEDB, r) 1180 opset(AVFCHEDBS, r) 1181 opset(AWFCHEDB, r) 1182 opset(AWFCHEDBS, r) 1183 opset(AVFMDB, r) 1184 opset(AWFMDB, r) 1185 opset(AVGFMB, r) 1186 opset(AVGFMH, r) 1187 opset(AVGFMF, r) 1188 opset(AVGFMG, r) 1189 opset(AVMXB, r) 1190 opset(AVMXH, r) 1191 opset(AVMXF, r) 1192 opset(AVMXG, r) 1193 opset(AVMXLB, r) 1194 opset(AVMXLH, r) 1195 opset(AVMXLF, r) 1196 opset(AVMXLG, r) 1197 opset(AVMNB, r) 1198 opset(AVMNH, r) 1199 opset(AVMNF, r) 1200 opset(AVMNG, r) 1201 opset(AVMNLB, r) 1202 opset(AVMNLH, r) 1203 opset(AVMNLF, r) 1204 opset(AVMNLG, r) 1205 opset(AVMRHB, r) 1206 opset(AVMRHH, r) 1207 opset(AVMRHF, r) 1208 opset(AVMRHG, r) 1209 opset(AVMRLB, r) 1210 opset(AVMRLH, r) 1211 opset(AVMRLF, r) 1212 opset(AVMRLG, r) 1213 opset(AVMEB, r) 1214 opset(AVMEH, r) 1215 opset(AVMEF, r) 1216 opset(AVMLEB, r) 1217 opset(AVMLEH, r) 1218 opset(AVMLEF, r) 1219 opset(AVMOB, r) 1220 opset(AVMOH, r) 1221 opset(AVMOF, r) 1222 opset(AVMLOB, r) 1223 opset(AVMLOH, r) 1224 opset(AVMLOF, r) 1225 opset(AVMHB, r) 1226 opset(AVMHH, r) 1227 opset(AVMHF, r) 1228 opset(AVMLHB, r) 1229 opset(AVMLHH, r) 1230 opset(AVMLHF, r) 1231 opset(AVMLH, r) 1232 opset(AVMLHW, r) 1233 opset(AVMLF, r) 1234 opset(AVNO, r) 1235 opset(AVO, r) 1236 opset(AVPKH, r) 1237 opset(AVPKF, r) 1238 opset(AVPKG, r) 1239 opset(AVSUMGH, r) 1240 opset(AVSUMGF, r) 1241 opset(AVSUMQF, r) 1242 opset(AVSUMQG, r) 1243 opset(AVSUMB, r) 1244 opset(AVSUMH, r) 1245 case AVERLLVG: 1246 opset(AVERLLVB, r) 1247 opset(AVERLLVH, r) 1248 opset(AVERLLVF, r) 1249 opset(AVESLVB, r) 1250 opset(AVESLVH, r) 1251 opset(AVESLVF, r) 1252 opset(AVESLVG, r) 1253 opset(AVESRAVB, r) 1254 opset(AVESRAVH, r) 1255 opset(AVESRAVF, r) 1256 opset(AVESRAVG, r) 1257 opset(AVESRLVB, r) 1258 opset(AVESRLVH, r) 1259 opset(AVESRLVF, r) 1260 opset(AVESRLVG, r) 1261 opset(AVFDDB, r) 1262 opset(AWFDDB, r) 1263 opset(AVFSDB, r) 1264 opset(AWFSDB, r) 1265 opset(AVSL, r) 1266 opset(AVSLB, r) 1267 opset(AVSRA, r) 1268 opset(AVSRAB, r) 1269 opset(AVSRL, r) 1270 opset(AVSRLB, r) 1271 opset(AVSF, r) 1272 opset(AVSG, r) 1273 opset(AVSQ, r) 1274 opset(AVSCBIB, r) 1275 opset(AVSCBIH, r) 1276 opset(AVSCBIF, r) 1277 opset(AVSCBIG, r) 1278 opset(AVSCBIQ, r) 1279 case AVACQ: 1280 opset(AVACCCQ, r) 1281 opset(AVGFMAB, r) 1282 opset(AVGFMAH, r) 1283 opset(AVGFMAF, r) 1284 opset(AVGFMAG, r) 1285 opset(AVMALB, r) 1286 opset(AVMALHW, r) 1287 opset(AVMALF, r) 1288 opset(AVMAHB, r) 1289 opset(AVMAHH, r) 1290 opset(AVMAHF, r) 1291 opset(AVMALHB, r) 1292 opset(AVMALHH, r) 1293 opset(AVMALHF, r) 1294 opset(AVMAEB, r) 1295 opset(AVMAEH, r) 1296 opset(AVMAEF, r) 1297 opset(AVMALEB, r) 1298 opset(AVMALEH, r) 1299 opset(AVMALEF, r) 1300 opset(AVMAOB, r) 1301 opset(AVMAOH, r) 1302 opset(AVMAOF, r) 1303 opset(AVMALOB, r) 1304 opset(AVMALOH, r) 1305 opset(AVMALOF, r) 1306 opset(AVSTRCB, r) 1307 opset(AVSTRCH, r) 1308 opset(AVSTRCF, r) 1309 opset(AVSTRCBS, r) 1310 opset(AVSTRCHS, r) 1311 opset(AVSTRCFS, r) 1312 opset(AVSTRCZB, r) 1313 opset(AVSTRCZH, r) 1314 opset(AVSTRCZF, r) 1315 opset(AVSTRCZBS, r) 1316 opset(AVSTRCZHS, r) 1317 opset(AVSTRCZFS, r) 1318 opset(AVSBCBIQ, r) 1319 opset(AVSBIQ, r) 1320 case AVSEL: 1321 opset(AVFMADB, r) 1322 opset(AWFMADB, r) 1323 opset(AVFMSDB, r) 1324 opset(AWFMSDB, r) 1325 opset(AVPERM, r) 1326 } 1327 } 1328 } 1329 1330 const ( 1331 op_A uint32 = 0x5A00 // FORMAT_RX1 ADD (32) 1332 op_AD uint32 = 0x6A00 // FORMAT_RX1 ADD NORMALIZED (long HFP) 1333 op_ADB uint32 = 0xED1A // FORMAT_RXE ADD (long BFP) 1334 op_ADBR uint32 = 0xB31A // FORMAT_RRE ADD (long BFP) 1335 op_ADR uint32 = 0x2A00 // FORMAT_RR ADD NORMALIZED (long HFP) 1336 op_ADTR uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1337 op_ADTRA uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1338 op_AE uint32 = 0x7A00 // FORMAT_RX1 ADD NORMALIZED (short HFP) 1339 op_AEB uint32 = 0xED0A // FORMAT_RXE ADD (short BFP) 1340 op_AEBR uint32 = 0xB30A // FORMAT_RRE ADD (short BFP) 1341 op_AER uint32 = 0x3A00 // FORMAT_RR ADD NORMALIZED (short HFP) 1342 op_AFI uint32 = 0xC209 // FORMAT_RIL1 ADD IMMEDIATE (32) 1343 op_AG uint32 = 0xE308 // FORMAT_RXY1 ADD (64) 1344 op_AGF uint32 = 0xE318 // FORMAT_RXY1 ADD (64<-32) 1345 op_AGFI uint32 = 0xC208 // FORMAT_RIL1 ADD IMMEDIATE (64<-32) 1346 op_AGFR uint32 = 0xB918 // FORMAT_RRE ADD (64<-32) 1347 op_AGHI uint32 = 0xA70B // FORMAT_RI1 ADD HALFWORD IMMEDIATE (64) 1348 op_AGHIK uint32 = 0xECD9 // FORMAT_RIE4 ADD IMMEDIATE (64<-16) 1349 op_AGR uint32 = 0xB908 // FORMAT_RRE ADD (64) 1350 op_AGRK uint32 = 0xB9E8 // FORMAT_RRF1 ADD (64) 1351 op_AGSI uint32 = 0xEB7A // FORMAT_SIY ADD IMMEDIATE (64<-8) 1352 op_AH uint32 = 0x4A00 // FORMAT_RX1 ADD HALFWORD 1353 op_AHHHR uint32 = 0xB9C8 // FORMAT_RRF1 ADD HIGH (32) 1354 op_AHHLR uint32 = 0xB9D8 // FORMAT_RRF1 ADD HIGH (32) 1355 op_AHI uint32 = 0xA70A // FORMAT_RI1 ADD HALFWORD IMMEDIATE (32) 1356 op_AHIK uint32 = 0xECD8 // FORMAT_RIE4 ADD IMMEDIATE (32<-16) 1357 op_AHY uint32 = 0xE37A // FORMAT_RXY1 ADD HALFWORD 1358 op_AIH uint32 = 0xCC08 // FORMAT_RIL1 ADD IMMEDIATE HIGH (32) 1359 op_AL uint32 = 0x5E00 // FORMAT_RX1 ADD LOGICAL (32) 1360 op_ALC uint32 = 0xE398 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (32) 1361 op_ALCG uint32 = 0xE388 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (64) 1362 op_ALCGR uint32 = 0xB988 // FORMAT_RRE ADD LOGICAL WITH CARRY (64) 1363 op_ALCR uint32 = 0xB998 // FORMAT_RRE ADD LOGICAL WITH CARRY (32) 1364 op_ALFI uint32 = 0xC20B // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (32) 1365 op_ALG uint32 = 0xE30A // FORMAT_RXY1 ADD LOGICAL (64) 1366 op_ALGF uint32 = 0xE31A // FORMAT_RXY1 ADD LOGICAL (64<-32) 1367 op_ALGFI uint32 = 0xC20A // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (64<-32) 1368 op_ALGFR uint32 = 0xB91A // FORMAT_RRE ADD LOGICAL (64<-32) 1369 op_ALGHSIK uint32 = 0xECDB // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16) 1370 op_ALGR uint32 = 0xB90A // FORMAT_RRE ADD LOGICAL (64) 1371 op_ALGRK uint32 = 0xB9EA // FORMAT_RRF1 ADD LOGICAL (64) 1372 op_ALGSI uint32 = 0xEB7E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8) 1373 op_ALHHHR uint32 = 0xB9CA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1374 op_ALHHLR uint32 = 0xB9DA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1375 op_ALHSIK uint32 = 0xECDA // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16) 1376 op_ALR uint32 = 0x1E00 // FORMAT_RR ADD LOGICAL (32) 1377 op_ALRK uint32 = 0xB9FA // FORMAT_RRF1 ADD LOGICAL (32) 1378 op_ALSI uint32 = 0xEB6E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8) 1379 op_ALSIH uint32 = 0xCC0A // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1380 op_ALSIHN uint32 = 0xCC0B // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1381 op_ALY uint32 = 0xE35E // FORMAT_RXY1 ADD LOGICAL (32) 1382 op_AP uint32 = 0xFA00 // FORMAT_SS2 ADD DECIMAL 1383 op_AR uint32 = 0x1A00 // FORMAT_RR ADD (32) 1384 op_ARK uint32 = 0xB9F8 // FORMAT_RRF1 ADD (32) 1385 op_ASI uint32 = 0xEB6A // FORMAT_SIY ADD IMMEDIATE (32<-8) 1386 op_AU uint32 = 0x7E00 // FORMAT_RX1 ADD UNNORMALIZED (short HFP) 1387 op_AUR uint32 = 0x3E00 // FORMAT_RR ADD UNNORMALIZED (short HFP) 1388 op_AW uint32 = 0x6E00 // FORMAT_RX1 ADD UNNORMALIZED (long HFP) 1389 op_AWR uint32 = 0x2E00 // FORMAT_RR ADD UNNORMALIZED (long HFP) 1390 op_AXBR uint32 = 0xB34A // FORMAT_RRE ADD (extended BFP) 1391 op_AXR uint32 = 0x3600 // FORMAT_RR ADD NORMALIZED (extended HFP) 1392 op_AXTR uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1393 op_AXTRA uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1394 op_AY uint32 = 0xE35A // FORMAT_RXY1 ADD (32) 1395 op_BAKR uint32 = 0xB240 // FORMAT_RRE BRANCH AND STACK 1396 op_BAL uint32 = 0x4500 // FORMAT_RX1 BRANCH AND LINK 1397 op_BALR uint32 = 0x0500 // FORMAT_RR BRANCH AND LINK 1398 op_BAS uint32 = 0x4D00 // FORMAT_RX1 BRANCH AND SAVE 1399 op_BASR uint32 = 0x0D00 // FORMAT_RR BRANCH AND SAVE 1400 op_BASSM uint32 = 0x0C00 // FORMAT_RR BRANCH AND SAVE AND SET MODE 1401 op_BC uint32 = 0x4700 // FORMAT_RX2 BRANCH ON CONDITION 1402 op_BCR uint32 = 0x0700 // FORMAT_RR BRANCH ON CONDITION 1403 op_BCT uint32 = 0x4600 // FORMAT_RX1 BRANCH ON COUNT (32) 1404 op_BCTG uint32 = 0xE346 // FORMAT_RXY1 BRANCH ON COUNT (64) 1405 op_BCTGR uint32 = 0xB946 // FORMAT_RRE BRANCH ON COUNT (64) 1406 op_BCTR uint32 = 0x0600 // FORMAT_RR BRANCH ON COUNT (32) 1407 op_BPP uint32 = 0xC700 // FORMAT_SMI BRANCH PREDICTION PRELOAD 1408 op_BPRP uint32 = 0xC500 // FORMAT_MII BRANCH PREDICTION RELATIVE PRELOAD 1409 op_BRAS uint32 = 0xA705 // FORMAT_RI2 BRANCH RELATIVE AND SAVE 1410 op_BRASL uint32 = 0xC005 // FORMAT_RIL2 BRANCH RELATIVE AND SAVE LONG 1411 op_BRC uint32 = 0xA704 // FORMAT_RI3 BRANCH RELATIVE ON CONDITION 1412 op_BRCL uint32 = 0xC004 // FORMAT_RIL3 BRANCH RELATIVE ON CONDITION LONG 1413 op_BRCT uint32 = 0xA706 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (32) 1414 op_BRCTG uint32 = 0xA707 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (64) 1415 op_BRCTH uint32 = 0xCC06 // FORMAT_RIL2 BRANCH RELATIVE ON COUNT HIGH (32) 1416 op_BRXH uint32 = 0x8400 // FORMAT_RSI BRANCH RELATIVE ON INDEX HIGH (32) 1417 op_BRXHG uint32 = 0xEC44 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX HIGH (64) 1418 op_BRXLE uint32 = 0x8500 // FORMAT_RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32) 1419 op_BRXLG uint32 = 0xEC45 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX LOW OR EQ. (64) 1420 op_BSA uint32 = 0xB25A // FORMAT_RRE BRANCH AND SET AUTHORITY 1421 op_BSG uint32 = 0xB258 // FORMAT_RRE BRANCH IN SUBSPACE GROUP 1422 op_BSM uint32 = 0x0B00 // FORMAT_RR BRANCH AND SET MODE 1423 op_BXH uint32 = 0x8600 // FORMAT_RS1 BRANCH ON INDEX HIGH (32) 1424 op_BXHG uint32 = 0xEB44 // FORMAT_RSY1 BRANCH ON INDEX HIGH (64) 1425 op_BXLE uint32 = 0x8700 // FORMAT_RS1 BRANCH ON INDEX LOW OR EQUAL (32) 1426 op_BXLEG uint32 = 0xEB45 // FORMAT_RSY1 BRANCH ON INDEX LOW OR EQUAL (64) 1427 op_C uint32 = 0x5900 // FORMAT_RX1 COMPARE (32) 1428 op_CD uint32 = 0x6900 // FORMAT_RX1 COMPARE (long HFP) 1429 op_CDB uint32 = 0xED19 // FORMAT_RXE COMPARE (long BFP) 1430 op_CDBR uint32 = 0xB319 // FORMAT_RRE COMPARE (long BFP) 1431 op_CDFBR uint32 = 0xB395 // FORMAT_RRE CONVERT FROM FIXED (32 to long BFP) 1432 op_CDFBRA uint32 = 0xB395 // FORMAT_RRF5 CONVERT FROM FIXED (32 to long BFP) 1433 op_CDFR uint32 = 0xB3B5 // FORMAT_RRE CONVERT FROM FIXED (32 to long HFP) 1434 op_CDFTR uint32 = 0xB951 // FORMAT_RRE CONVERT FROM FIXED (32 to long DFP) 1435 op_CDGBR uint32 = 0xB3A5 // FORMAT_RRE CONVERT FROM FIXED (64 to long BFP) 1436 op_CDGBRA uint32 = 0xB3A5 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long BFP) 1437 op_CDGR uint32 = 0xB3C5 // FORMAT_RRE CONVERT FROM FIXED (64 to long HFP) 1438 op_CDGTR uint32 = 0xB3F1 // FORMAT_RRE CONVERT FROM FIXED (64 to long DFP) 1439 op_CDGTRA uint32 = 0xB3F1 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long DFP) 1440 op_CDLFBR uint32 = 0xB391 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long BFP) 1441 op_CDLFTR uint32 = 0xB953 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long DFP) 1442 op_CDLGBR uint32 = 0xB3A1 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long BFP) 1443 op_CDLGTR uint32 = 0xB952 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long DFP) 1444 op_CDR uint32 = 0x2900 // FORMAT_RR COMPARE (long HFP) 1445 op_CDS uint32 = 0xBB00 // FORMAT_RS1 COMPARE DOUBLE AND SWAP (32) 1446 op_CDSG uint32 = 0xEB3E // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (64) 1447 op_CDSTR uint32 = 0xB3F3 // FORMAT_RRE CONVERT FROM SIGNED PACKED (64 to long DFP) 1448 op_CDSY uint32 = 0xEB31 // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (32) 1449 op_CDTR uint32 = 0xB3E4 // FORMAT_RRE COMPARE (long DFP) 1450 op_CDUTR uint32 = 0xB3F2 // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP) 1451 op_CDZT uint32 = 0xEDAA // FORMAT_RSL CONVERT FROM ZONED (to long DFP) 1452 op_CE uint32 = 0x7900 // FORMAT_RX1 COMPARE (short HFP) 1453 op_CEB uint32 = 0xED09 // FORMAT_RXE COMPARE (short BFP) 1454 op_CEBR uint32 = 0xB309 // FORMAT_RRE COMPARE (short BFP) 1455 op_CEDTR uint32 = 0xB3F4 // FORMAT_RRE COMPARE BIASED EXPONENT (long DFP) 1456 op_CEFBR uint32 = 0xB394 // FORMAT_RRE CONVERT FROM FIXED (32 to short BFP) 1457 op_CEFBRA uint32 = 0xB394 // FORMAT_RRF5 CONVERT FROM FIXED (32 to short BFP) 1458 op_CEFR uint32 = 0xB3B4 // FORMAT_RRE CONVERT FROM FIXED (32 to short HFP) 1459 op_CEGBR uint32 = 0xB3A4 // FORMAT_RRE CONVERT FROM FIXED (64 to short BFP) 1460 op_CEGBRA uint32 = 0xB3A4 // FORMAT_RRF5 CONVERT FROM FIXED (64 to short BFP) 1461 op_CEGR uint32 = 0xB3C4 // FORMAT_RRE CONVERT FROM FIXED (64 to short HFP) 1462 op_CELFBR uint32 = 0xB390 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to short BFP) 1463 op_CELGBR uint32 = 0xB3A0 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to short BFP) 1464 op_CER uint32 = 0x3900 // FORMAT_RR COMPARE (short HFP) 1465 op_CEXTR uint32 = 0xB3FC // FORMAT_RRE COMPARE BIASED EXPONENT (extended DFP) 1466 op_CFC uint32 = 0xB21A // FORMAT_S COMPARE AND FORM CODEWORD 1467 op_CFDBR uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1468 op_CFDBRA uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1469 op_CFDR uint32 = 0xB3B9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 32) 1470 op_CFDTR uint32 = 0xB941 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 32) 1471 op_CFEBR uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1472 op_CFEBRA uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1473 op_CFER uint32 = 0xB3B8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 32) 1474 op_CFI uint32 = 0xC20D // FORMAT_RIL1 COMPARE IMMEDIATE (32) 1475 op_CFXBR uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1476 op_CFXBRA uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1477 op_CFXR uint32 = 0xB3BA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 32) 1478 op_CFXTR uint32 = 0xB949 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 32) 1479 op_CG uint32 = 0xE320 // FORMAT_RXY1 COMPARE (64) 1480 op_CGDBR uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1481 op_CGDBRA uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1482 op_CGDR uint32 = 0xB3C9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 64) 1483 op_CGDTR uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1484 op_CGDTRA uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1485 op_CGEBR uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1486 op_CGEBRA uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1487 op_CGER uint32 = 0xB3C8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 64) 1488 op_CGF uint32 = 0xE330 // FORMAT_RXY1 COMPARE (64<-32) 1489 op_CGFI uint32 = 0xC20C // FORMAT_RIL1 COMPARE IMMEDIATE (64<-32) 1490 op_CGFR uint32 = 0xB930 // FORMAT_RRE COMPARE (64<-32) 1491 op_CGFRL uint32 = 0xC60C // FORMAT_RIL2 COMPARE RELATIVE LONG (64<-32) 1492 op_CGH uint32 = 0xE334 // FORMAT_RXY1 COMPARE HALFWORD (64<-16) 1493 op_CGHI uint32 = 0xA70F // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (64<-16) 1494 op_CGHRL uint32 = 0xC604 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (64<-16) 1495 op_CGHSI uint32 = 0xE558 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (64<-16) 1496 op_CGIB uint32 = 0xECFC // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (64<-8) 1497 op_CGIJ uint32 = 0xEC7C // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8) 1498 op_CGIT uint32 = 0xEC70 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (64<-16) 1499 op_CGR uint32 = 0xB920 // FORMAT_RRE COMPARE (64) 1500 op_CGRB uint32 = 0xECE4 // FORMAT_RRS COMPARE AND BRANCH (64) 1501 op_CGRJ uint32 = 0xEC64 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (64) 1502 op_CGRL uint32 = 0xC608 // FORMAT_RIL2 COMPARE RELATIVE LONG (64) 1503 op_CGRT uint32 = 0xB960 // FORMAT_RRF3 COMPARE AND TRAP (64) 1504 op_CGXBR uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1505 op_CGXBRA uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1506 op_CGXR uint32 = 0xB3CA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 64) 1507 op_CGXTR uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1508 op_CGXTRA uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1509 op_CH uint32 = 0x4900 // FORMAT_RX1 COMPARE HALFWORD (32<-16) 1510 op_CHF uint32 = 0xE3CD // FORMAT_RXY1 COMPARE HIGH (32) 1511 op_CHHR uint32 = 0xB9CD // FORMAT_RRE COMPARE HIGH (32) 1512 op_CHHSI uint32 = 0xE554 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (16) 1513 op_CHI uint32 = 0xA70E // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (32<-16) 1514 op_CHLR uint32 = 0xB9DD // FORMAT_RRE COMPARE HIGH (32) 1515 op_CHRL uint32 = 0xC605 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (32<-16) 1516 op_CHSI uint32 = 0xE55C // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (32<-16) 1517 op_CHY uint32 = 0xE379 // FORMAT_RXY1 COMPARE HALFWORD (32<-16) 1518 op_CIB uint32 = 0xECFE // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (32<-8) 1519 op_CIH uint32 = 0xCC0D // FORMAT_RIL1 COMPARE IMMEDIATE HIGH (32) 1520 op_CIJ uint32 = 0xEC7E // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8) 1521 op_CIT uint32 = 0xEC72 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (32<-16) 1522 op_CKSM uint32 = 0xB241 // FORMAT_RRE CHECKSUM 1523 op_CL uint32 = 0x5500 // FORMAT_RX1 COMPARE LOGICAL (32) 1524 op_CLC uint32 = 0xD500 // FORMAT_SS1 COMPARE LOGICAL (character) 1525 op_CLCL uint32 = 0x0F00 // FORMAT_RR COMPARE LOGICAL LONG 1526 op_CLCLE uint32 = 0xA900 // FORMAT_RS1 COMPARE LOGICAL LONG EXTENDED 1527 op_CLCLU uint32 = 0xEB8F // FORMAT_RSY1 COMPARE LOGICAL LONG UNICODE 1528 op_CLFDBR uint32 = 0xB39D // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 32) 1529 op_CLFDTR uint32 = 0xB943 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 32) 1530 op_CLFEBR uint32 = 0xB39C // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 32) 1531 op_CLFHSI uint32 = 0xE55D // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (32<-16) 1532 op_CLFI uint32 = 0xC20F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (32) 1533 op_CLFIT uint32 = 0xEC73 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16) 1534 op_CLFXBR uint32 = 0xB39E // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 32) 1535 op_CLFXTR uint32 = 0xB94B // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 32) 1536 op_CLG uint32 = 0xE321 // FORMAT_RXY1 COMPARE LOGICAL (64) 1537 op_CLGDBR uint32 = 0xB3AD // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 64) 1538 op_CLGDTR uint32 = 0xB942 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 64) 1539 op_CLGEBR uint32 = 0xB3AC // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 64) 1540 op_CLGF uint32 = 0xE331 // FORMAT_RXY1 COMPARE LOGICAL (64<-32) 1541 op_CLGFI uint32 = 0xC20E // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (64<-32) 1542 op_CLGFR uint32 = 0xB931 // FORMAT_RRE COMPARE LOGICAL (64<-32) 1543 op_CLGFRL uint32 = 0xC60E // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-32) 1544 op_CLGHRL uint32 = 0xC606 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-16) 1545 op_CLGHSI uint32 = 0xE559 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (64<-16) 1546 op_CLGIB uint32 = 0xECFD // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8) 1547 op_CLGIJ uint32 = 0xEC7D // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (64<-8) 1548 op_CLGIT uint32 = 0xEC71 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16) 1549 op_CLGR uint32 = 0xB921 // FORMAT_RRE COMPARE LOGICAL (64) 1550 op_CLGRB uint32 = 0xECE5 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (64) 1551 op_CLGRJ uint32 = 0xEC65 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (64) 1552 op_CLGRL uint32 = 0xC60A // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64) 1553 op_CLGRT uint32 = 0xB961 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (64) 1554 op_CLGT uint32 = 0xEB2B // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (64) 1555 op_CLGXBR uint32 = 0xB3AE // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 64) 1556 op_CLGXTR uint32 = 0xB94A // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 64) 1557 op_CLHF uint32 = 0xE3CF // FORMAT_RXY1 COMPARE LOGICAL HIGH (32) 1558 op_CLHHR uint32 = 0xB9CF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1559 op_CLHHSI uint32 = 0xE555 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (16) 1560 op_CLHLR uint32 = 0xB9DF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1561 op_CLHRL uint32 = 0xC607 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32<-16) 1562 op_CLI uint32 = 0x9500 // FORMAT_SI COMPARE LOGICAL (immediate) 1563 op_CLIB uint32 = 0xECFF // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8) 1564 op_CLIH uint32 = 0xCC0F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE HIGH (32) 1565 op_CLIJ uint32 = 0xEC7F // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (32<-8) 1566 op_CLIY uint32 = 0xEB55 // FORMAT_SIY COMPARE LOGICAL (immediate) 1567 op_CLM uint32 = 0xBD00 // FORMAT_RS2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1568 op_CLMH uint32 = 0xEB20 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (high) 1569 op_CLMY uint32 = 0xEB21 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1570 op_CLR uint32 = 0x1500 // FORMAT_RR COMPARE LOGICAL (32) 1571 op_CLRB uint32 = 0xECF7 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (32) 1572 op_CLRJ uint32 = 0xEC77 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (32) 1573 op_CLRL uint32 = 0xC60F // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32) 1574 op_CLRT uint32 = 0xB973 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (32) 1575 op_CLST uint32 = 0xB25D // FORMAT_RRE COMPARE LOGICAL STRING 1576 op_CLT uint32 = 0xEB23 // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (32) 1577 op_CLY uint32 = 0xE355 // FORMAT_RXY1 COMPARE LOGICAL (32) 1578 op_CMPSC uint32 = 0xB263 // FORMAT_RRE COMPRESSION CALL 1579 op_CP uint32 = 0xF900 // FORMAT_SS2 COMPARE DECIMAL 1580 op_CPSDR uint32 = 0xB372 // FORMAT_RRF2 COPY SIGN (long) 1581 op_CPYA uint32 = 0xB24D // FORMAT_RRE COPY ACCESS 1582 op_CR uint32 = 0x1900 // FORMAT_RR COMPARE (32) 1583 op_CRB uint32 = 0xECF6 // FORMAT_RRS COMPARE AND BRANCH (32) 1584 op_CRDTE uint32 = 0xB98F // FORMAT_RRF2 COMPARE AND REPLACE DAT TABLE ENTRY 1585 op_CRJ uint32 = 0xEC76 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (32) 1586 op_CRL uint32 = 0xC60D // FORMAT_RIL2 COMPARE RELATIVE LONG (32) 1587 op_CRT uint32 = 0xB972 // FORMAT_RRF3 COMPARE AND TRAP (32) 1588 op_CS uint32 = 0xBA00 // FORMAT_RS1 COMPARE AND SWAP (32) 1589 op_CSCH uint32 = 0xB230 // FORMAT_S CLEAR SUBCHANNEL 1590 op_CSDTR uint32 = 0xB3E3 // FORMAT_RRF4 CONVERT TO SIGNED PACKED (long DFP to 64) 1591 op_CSG uint32 = 0xEB30 // FORMAT_RSY1 COMPARE AND SWAP (64) 1592 op_CSP uint32 = 0xB250 // FORMAT_RRE COMPARE AND SWAP AND PURGE 1593 op_CSPG uint32 = 0xB98A // FORMAT_RRE COMPARE AND SWAP AND PURGE 1594 op_CSST uint32 = 0xC802 // FORMAT_SSF COMPARE AND SWAP AND STORE 1595 op_CSXTR uint32 = 0xB3EB // FORMAT_RRF4 CONVERT TO SIGNED PACKED (extended DFP to 128) 1596 op_CSY uint32 = 0xEB14 // FORMAT_RSY1 COMPARE AND SWAP (32) 1597 op_CU12 uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-16 1598 op_CU14 uint32 = 0xB9B0 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-32 1599 op_CU21 uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-8 1600 op_CU24 uint32 = 0xB9B1 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-32 1601 op_CU41 uint32 = 0xB9B2 // FORMAT_RRE CONVERT UTF-32 TO UTF-8 1602 op_CU42 uint32 = 0xB9B3 // FORMAT_RRE CONVERT UTF-32 TO UTF-16 1603 op_CUDTR uint32 = 0xB3E2 // FORMAT_RRE CONVERT TO UNSIGNED PACKED (long DFP to 64) 1604 op_CUSE uint32 = 0xB257 // FORMAT_RRE COMPARE UNTIL SUBSTRING EQUAL 1605 op_CUTFU uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UNICODE 1606 op_CUUTF uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UNICODE TO UTF-8 1607 op_CUXTR uint32 = 0xB3EA // FORMAT_RRE CONVERT TO UNSIGNED PACKED (extended DFP to 128) 1608 op_CVB uint32 = 0x4F00 // FORMAT_RX1 CONVERT TO BINARY (32) 1609 op_CVBG uint32 = 0xE30E // FORMAT_RXY1 CONVERT TO BINARY (64) 1610 op_CVBY uint32 = 0xE306 // FORMAT_RXY1 CONVERT TO BINARY (32) 1611 op_CVD uint32 = 0x4E00 // FORMAT_RX1 CONVERT TO DECIMAL (32) 1612 op_CVDG uint32 = 0xE32E // FORMAT_RXY1 CONVERT TO DECIMAL (64) 1613 op_CVDY uint32 = 0xE326 // FORMAT_RXY1 CONVERT TO DECIMAL (32) 1614 op_CXBR uint32 = 0xB349 // FORMAT_RRE COMPARE (extended BFP) 1615 op_CXFBR uint32 = 0xB396 // FORMAT_RRE CONVERT FROM FIXED (32 to extended BFP) 1616 op_CXFBRA uint32 = 0xB396 // FORMAT_RRF5 CONVERT FROM FIXED (32 to extended BFP) 1617 op_CXFR uint32 = 0xB3B6 // FORMAT_RRE CONVERT FROM FIXED (32 to extended HFP) 1618 op_CXFTR uint32 = 0xB959 // FORMAT_RRE CONVERT FROM FIXED (32 to extended DFP) 1619 op_CXGBR uint32 = 0xB3A6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended BFP) 1620 op_CXGBRA uint32 = 0xB3A6 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended BFP) 1621 op_CXGR uint32 = 0xB3C6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended HFP) 1622 op_CXGTR uint32 = 0xB3F9 // FORMAT_RRE CONVERT FROM FIXED (64 to extended DFP) 1623 op_CXGTRA uint32 = 0xB3F9 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended DFP) 1624 op_CXLFBR uint32 = 0xB392 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended BFP) 1625 op_CXLFTR uint32 = 0xB95B // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended DFP) 1626 op_CXLGBR uint32 = 0xB3A2 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended BFP) 1627 op_CXLGTR uint32 = 0xB95A // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended DFP) 1628 op_CXR uint32 = 0xB369 // FORMAT_RRE COMPARE (extended HFP) 1629 op_CXSTR uint32 = 0xB3FB // FORMAT_RRE CONVERT FROM SIGNED PACKED (128 to extended DFP) 1630 op_CXTR uint32 = 0xB3EC // FORMAT_RRE COMPARE (extended DFP) 1631 op_CXUTR uint32 = 0xB3FA // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) 1632 op_CXZT uint32 = 0xEDAB // FORMAT_RSL CONVERT FROM ZONED (to extended DFP) 1633 op_CY uint32 = 0xE359 // FORMAT_RXY1 COMPARE (32) 1634 op_CZDT uint32 = 0xEDA8 // FORMAT_RSL CONVERT TO ZONED (from long DFP) 1635 op_CZXT uint32 = 0xEDA9 // FORMAT_RSL CONVERT TO ZONED (from extended DFP) 1636 op_D uint32 = 0x5D00 // FORMAT_RX1 DIVIDE (32<-64) 1637 op_DD uint32 = 0x6D00 // FORMAT_RX1 DIVIDE (long HFP) 1638 op_DDB uint32 = 0xED1D // FORMAT_RXE DIVIDE (long BFP) 1639 op_DDBR uint32 = 0xB31D // FORMAT_RRE DIVIDE (long BFP) 1640 op_DDR uint32 = 0x2D00 // FORMAT_RR DIVIDE (long HFP) 1641 op_DDTR uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1642 op_DDTRA uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1643 op_DE uint32 = 0x7D00 // FORMAT_RX1 DIVIDE (short HFP) 1644 op_DEB uint32 = 0xED0D // FORMAT_RXE DIVIDE (short BFP) 1645 op_DEBR uint32 = 0xB30D // FORMAT_RRE DIVIDE (short BFP) 1646 op_DER uint32 = 0x3D00 // FORMAT_RR DIVIDE (short HFP) 1647 op_DIDBR uint32 = 0xB35B // FORMAT_RRF2 DIVIDE TO INTEGER (long BFP) 1648 op_DIEBR uint32 = 0xB353 // FORMAT_RRF2 DIVIDE TO INTEGER (short BFP) 1649 op_DL uint32 = 0xE397 // FORMAT_RXY1 DIVIDE LOGICAL (32<-64) 1650 op_DLG uint32 = 0xE387 // FORMAT_RXY1 DIVIDE LOGICAL (64<-128) 1651 op_DLGR uint32 = 0xB987 // FORMAT_RRE DIVIDE LOGICAL (64<-128) 1652 op_DLR uint32 = 0xB997 // FORMAT_RRE DIVIDE LOGICAL (32<-64) 1653 op_DP uint32 = 0xFD00 // FORMAT_SS2 DIVIDE DECIMAL 1654 op_DR uint32 = 0x1D00 // FORMAT_RR DIVIDE (32<-64) 1655 op_DSG uint32 = 0xE30D // FORMAT_RXY1 DIVIDE SINGLE (64) 1656 op_DSGF uint32 = 0xE31D // FORMAT_RXY1 DIVIDE SINGLE (64<-32) 1657 op_DSGFR uint32 = 0xB91D // FORMAT_RRE DIVIDE SINGLE (64<-32) 1658 op_DSGR uint32 = 0xB90D // FORMAT_RRE DIVIDE SINGLE (64) 1659 op_DXBR uint32 = 0xB34D // FORMAT_RRE DIVIDE (extended BFP) 1660 op_DXR uint32 = 0xB22D // FORMAT_RRE DIVIDE (extended HFP) 1661 op_DXTR uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1662 op_DXTRA uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1663 op_EAR uint32 = 0xB24F // FORMAT_RRE EXTRACT ACCESS 1664 op_ECAG uint32 = 0xEB4C // FORMAT_RSY1 EXTRACT CACHE ATTRIBUTE 1665 op_ECTG uint32 = 0xC801 // FORMAT_SSF EXTRACT CPU TIME 1666 op_ED uint32 = 0xDE00 // FORMAT_SS1 EDIT 1667 op_EDMK uint32 = 0xDF00 // FORMAT_SS1 EDIT AND MARK 1668 op_EEDTR uint32 = 0xB3E5 // FORMAT_RRE EXTRACT BIASED EXPONENT (long DFP to 64) 1669 op_EEXTR uint32 = 0xB3ED // FORMAT_RRE EXTRACT BIASED EXPONENT (extended DFP to 64) 1670 op_EFPC uint32 = 0xB38C // FORMAT_RRE EXTRACT FPC 1671 op_EPAIR uint32 = 0xB99A // FORMAT_RRE EXTRACT PRIMARY ASN AND INSTANCE 1672 op_EPAR uint32 = 0xB226 // FORMAT_RRE EXTRACT PRIMARY ASN 1673 op_EPSW uint32 = 0xB98D // FORMAT_RRE EXTRACT PSW 1674 op_EREG uint32 = 0xB249 // FORMAT_RRE EXTRACT STACKED REGISTERS (32) 1675 op_EREGG uint32 = 0xB90E // FORMAT_RRE EXTRACT STACKED REGISTERS (64) 1676 op_ESAIR uint32 = 0xB99B // FORMAT_RRE EXTRACT SECONDARY ASN AND INSTANCE 1677 op_ESAR uint32 = 0xB227 // FORMAT_RRE EXTRACT SECONDARY ASN 1678 op_ESDTR uint32 = 0xB3E7 // FORMAT_RRE EXTRACT SIGNIFICANCE (long DFP) 1679 op_ESEA uint32 = 0xB99D // FORMAT_RRE EXTRACT AND SET EXTENDED AUTHORITY 1680 op_ESTA uint32 = 0xB24A // FORMAT_RRE EXTRACT STACKED STATE 1681 op_ESXTR uint32 = 0xB3EF // FORMAT_RRE EXTRACT SIGNIFICANCE (extended DFP) 1682 op_ETND uint32 = 0xB2EC // FORMAT_RRE EXTRACT TRANSACTION NESTING DEPTH 1683 op_EX uint32 = 0x4400 // FORMAT_RX1 EXECUTE 1684 op_EXRL uint32 = 0xC600 // FORMAT_RIL2 EXECUTE RELATIVE LONG 1685 op_FIDBR uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1686 op_FIDBRA uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1687 op_FIDR uint32 = 0xB37F // FORMAT_RRE LOAD FP INTEGER (long HFP) 1688 op_FIDTR uint32 = 0xB3D7 // FORMAT_RRF5 LOAD FP INTEGER (long DFP) 1689 op_FIEBR uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1690 op_FIEBRA uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1691 op_FIER uint32 = 0xB377 // FORMAT_RRE LOAD FP INTEGER (short HFP) 1692 op_FIXBR uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1693 op_FIXBRA uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1694 op_FIXR uint32 = 0xB367 // FORMAT_RRE LOAD FP INTEGER (extended HFP) 1695 op_FIXTR uint32 = 0xB3DF // FORMAT_RRF5 LOAD FP INTEGER (extended DFP) 1696 op_FLOGR uint32 = 0xB983 // FORMAT_RRE FIND LEFTMOST ONE 1697 op_HDR uint32 = 0x2400 // FORMAT_RR HALVE (long HFP) 1698 op_HER uint32 = 0x3400 // FORMAT_RR HALVE (short HFP) 1699 op_HSCH uint32 = 0xB231 // FORMAT_S HALT SUBCHANNEL 1700 op_IAC uint32 = 0xB224 // FORMAT_RRE INSERT ADDRESS SPACE CONTROL 1701 op_IC uint32 = 0x4300 // FORMAT_RX1 INSERT CHARACTER 1702 op_ICM uint32 = 0xBF00 // FORMAT_RS2 INSERT CHARACTERS UNDER MASK (low) 1703 op_ICMH uint32 = 0xEB80 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (high) 1704 op_ICMY uint32 = 0xEB81 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (low) 1705 op_ICY uint32 = 0xE373 // FORMAT_RXY1 INSERT CHARACTER 1706 op_IDTE uint32 = 0xB98E // FORMAT_RRF2 INVALIDATE DAT TABLE ENTRY 1707 op_IEDTR uint32 = 0xB3F6 // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to long DFP) 1708 op_IEXTR uint32 = 0xB3FE // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to extended DFP) 1709 op_IIHF uint32 = 0xC008 // FORMAT_RIL1 INSERT IMMEDIATE (high) 1710 op_IIHH uint32 = 0xA500 // FORMAT_RI1 INSERT IMMEDIATE (high high) 1711 op_IIHL uint32 = 0xA501 // FORMAT_RI1 INSERT IMMEDIATE (high low) 1712 op_IILF uint32 = 0xC009 // FORMAT_RIL1 INSERT IMMEDIATE (low) 1713 op_IILH uint32 = 0xA502 // FORMAT_RI1 INSERT IMMEDIATE (low high) 1714 op_IILL uint32 = 0xA503 // FORMAT_RI1 INSERT IMMEDIATE (low low) 1715 op_IPK uint32 = 0xB20B // FORMAT_S INSERT PSW KEY 1716 op_IPM uint32 = 0xB222 // FORMAT_RRE INSERT PROGRAM MASK 1717 op_IPTE uint32 = 0xB221 // FORMAT_RRF1 INVALIDATE PAGE TABLE ENTRY 1718 op_ISKE uint32 = 0xB229 // FORMAT_RRE INSERT STORAGE KEY EXTENDED 1719 op_IVSK uint32 = 0xB223 // FORMAT_RRE INSERT VIRTUAL STORAGE KEY 1720 op_KDB uint32 = 0xED18 // FORMAT_RXE COMPARE AND SIGNAL (long BFP) 1721 op_KDBR uint32 = 0xB318 // FORMAT_RRE COMPARE AND SIGNAL (long BFP) 1722 op_KDTR uint32 = 0xB3E0 // FORMAT_RRE COMPARE AND SIGNAL (long DFP) 1723 op_KEB uint32 = 0xED08 // FORMAT_RXE COMPARE AND SIGNAL (short BFP) 1724 op_KEBR uint32 = 0xB308 // FORMAT_RRE COMPARE AND SIGNAL (short BFP) 1725 op_KIMD uint32 = 0xB93E // FORMAT_RRE COMPUTE INTERMEDIATE MESSAGE DIGEST 1726 op_KLMD uint32 = 0xB93F // FORMAT_RRE COMPUTE LAST MESSAGE DIGEST 1727 op_KM uint32 = 0xB92E // FORMAT_RRE CIPHER MESSAGE 1728 op_KMAC uint32 = 0xB91E // FORMAT_RRE COMPUTE MESSAGE AUTHENTICATION CODE 1729 op_KMC uint32 = 0xB92F // FORMAT_RRE CIPHER MESSAGE WITH CHAINING 1730 op_KMCTR uint32 = 0xB92D // FORMAT_RRF2 CIPHER MESSAGE WITH COUNTER 1731 op_KMF uint32 = 0xB92A // FORMAT_RRE CIPHER MESSAGE WITH CFB 1732 op_KMO uint32 = 0xB92B // FORMAT_RRE CIPHER MESSAGE WITH OFB 1733 op_KXBR uint32 = 0xB348 // FORMAT_RRE COMPARE AND SIGNAL (extended BFP) 1734 op_KXTR uint32 = 0xB3E8 // FORMAT_RRE COMPARE AND SIGNAL (extended DFP) 1735 op_L uint32 = 0x5800 // FORMAT_RX1 LOAD (32) 1736 op_LA uint32 = 0x4100 // FORMAT_RX1 LOAD ADDRESS 1737 op_LAA uint32 = 0xEBF8 // FORMAT_RSY1 LOAD AND ADD (32) 1738 op_LAAG uint32 = 0xEBE8 // FORMAT_RSY1 LOAD AND ADD (64) 1739 op_LAAL uint32 = 0xEBFA // FORMAT_RSY1 LOAD AND ADD LOGICAL (32) 1740 op_LAALG uint32 = 0xEBEA // FORMAT_RSY1 LOAD AND ADD LOGICAL (64) 1741 op_LAE uint32 = 0x5100 // FORMAT_RX1 LOAD ADDRESS EXTENDED 1742 op_LAEY uint32 = 0xE375 // FORMAT_RXY1 LOAD ADDRESS EXTENDED 1743 op_LAM uint32 = 0x9A00 // FORMAT_RS1 LOAD ACCESS MULTIPLE 1744 op_LAMY uint32 = 0xEB9A // FORMAT_RSY1 LOAD ACCESS MULTIPLE 1745 op_LAN uint32 = 0xEBF4 // FORMAT_RSY1 LOAD AND AND (32) 1746 op_LANG uint32 = 0xEBE4 // FORMAT_RSY1 LOAD AND AND (64) 1747 op_LAO uint32 = 0xEBF6 // FORMAT_RSY1 LOAD AND OR (32) 1748 op_LAOG uint32 = 0xEBE6 // FORMAT_RSY1 LOAD AND OR (64) 1749 op_LARL uint32 = 0xC000 // FORMAT_RIL2 LOAD ADDRESS RELATIVE LONG 1750 op_LASP uint32 = 0xE500 // FORMAT_SSE LOAD ADDRESS SPACE PARAMETERS 1751 op_LAT uint32 = 0xE39F // FORMAT_RXY1 LOAD AND TRAP (32L<-32) 1752 op_LAX uint32 = 0xEBF7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (32) 1753 op_LAXG uint32 = 0xEBE7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (64) 1754 op_LAY uint32 = 0xE371 // FORMAT_RXY1 LOAD ADDRESS 1755 op_LB uint32 = 0xE376 // FORMAT_RXY1 LOAD BYTE (32) 1756 op_LBH uint32 = 0xE3C0 // FORMAT_RXY1 LOAD BYTE HIGH (32<-8) 1757 op_LBR uint32 = 0xB926 // FORMAT_RRE LOAD BYTE (32) 1758 op_LCDBR uint32 = 0xB313 // FORMAT_RRE LOAD COMPLEMENT (long BFP) 1759 op_LCDFR uint32 = 0xB373 // FORMAT_RRE LOAD COMPLEMENT (long) 1760 op_LCDR uint32 = 0x2300 // FORMAT_RR LOAD COMPLEMENT (long HFP) 1761 op_LCEBR uint32 = 0xB303 // FORMAT_RRE LOAD COMPLEMENT (short BFP) 1762 op_LCER uint32 = 0x3300 // FORMAT_RR LOAD COMPLEMENT (short HFP) 1763 op_LCGFR uint32 = 0xB913 // FORMAT_RRE LOAD COMPLEMENT (64<-32) 1764 op_LCGR uint32 = 0xB903 // FORMAT_RRE LOAD COMPLEMENT (64) 1765 op_LCR uint32 = 0x1300 // FORMAT_RR LOAD COMPLEMENT (32) 1766 op_LCTL uint32 = 0xB700 // FORMAT_RS1 LOAD CONTROL (32) 1767 op_LCTLG uint32 = 0xEB2F // FORMAT_RSY1 LOAD CONTROL (64) 1768 op_LCXBR uint32 = 0xB343 // FORMAT_RRE LOAD COMPLEMENT (extended BFP) 1769 op_LCXR uint32 = 0xB363 // FORMAT_RRE LOAD COMPLEMENT (extended HFP) 1770 op_LD uint32 = 0x6800 // FORMAT_RX1 LOAD (long) 1771 op_LDE uint32 = 0xED24 // FORMAT_RXE LOAD LENGTHENED (short to long HFP) 1772 op_LDEB uint32 = 0xED04 // FORMAT_RXE LOAD LENGTHENED (short to long BFP) 1773 op_LDEBR uint32 = 0xB304 // FORMAT_RRE LOAD LENGTHENED (short to long BFP) 1774 op_LDER uint32 = 0xB324 // FORMAT_RRE LOAD LENGTHENED (short to long HFP) 1775 op_LDETR uint32 = 0xB3D4 // FORMAT_RRF4 LOAD LENGTHENED (short to long DFP) 1776 op_LDGR uint32 = 0xB3C1 // FORMAT_RRE LOAD FPR FROM GR (64 to long) 1777 op_LDR uint32 = 0x2800 // FORMAT_RR LOAD (long) 1778 op_LDXBR uint32 = 0xB345 // FORMAT_RRE LOAD ROUNDED (extended to long BFP) 1779 op_LDXBRA uint32 = 0xB345 // FORMAT_RRF5 LOAD ROUNDED (extended to long BFP) 1780 op_LDXR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1781 op_LDXTR uint32 = 0xB3DD // FORMAT_RRF5 LOAD ROUNDED (extended to long DFP) 1782 op_LDY uint32 = 0xED65 // FORMAT_RXY1 LOAD (long) 1783 op_LE uint32 = 0x7800 // FORMAT_RX1 LOAD (short) 1784 op_LEDBR uint32 = 0xB344 // FORMAT_RRE LOAD ROUNDED (long to short BFP) 1785 op_LEDBRA uint32 = 0xB344 // FORMAT_RRF5 LOAD ROUNDED (long to short BFP) 1786 op_LEDR uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1787 op_LEDTR uint32 = 0xB3D5 // FORMAT_RRF5 LOAD ROUNDED (long to short DFP) 1788 op_LER uint32 = 0x3800 // FORMAT_RR LOAD (short) 1789 op_LEXBR uint32 = 0xB346 // FORMAT_RRE LOAD ROUNDED (extended to short BFP) 1790 op_LEXBRA uint32 = 0xB346 // FORMAT_RRF5 LOAD ROUNDED (extended to short BFP) 1791 op_LEXR uint32 = 0xB366 // FORMAT_RRE LOAD ROUNDED (extended to short HFP) 1792 op_LEY uint32 = 0xED64 // FORMAT_RXY1 LOAD (short) 1793 op_LFAS uint32 = 0xB2BD // FORMAT_S LOAD FPC AND SIGNAL 1794 op_LFH uint32 = 0xE3CA // FORMAT_RXY1 LOAD HIGH (32) 1795 op_LFHAT uint32 = 0xE3C8 // FORMAT_RXY1 LOAD HIGH AND TRAP (32H<-32) 1796 op_LFPC uint32 = 0xB29D // FORMAT_S LOAD FPC 1797 op_LG uint32 = 0xE304 // FORMAT_RXY1 LOAD (64) 1798 op_LGAT uint32 = 0xE385 // FORMAT_RXY1 LOAD AND TRAP (64) 1799 op_LGB uint32 = 0xE377 // FORMAT_RXY1 LOAD BYTE (64) 1800 op_LGBR uint32 = 0xB906 // FORMAT_RRE LOAD BYTE (64) 1801 op_LGDR uint32 = 0xB3CD // FORMAT_RRE LOAD GR FROM FPR (long to 64) 1802 op_LGF uint32 = 0xE314 // FORMAT_RXY1 LOAD (64<-32) 1803 op_LGFI uint32 = 0xC001 // FORMAT_RIL1 LOAD IMMEDIATE (64<-32) 1804 op_LGFR uint32 = 0xB914 // FORMAT_RRE LOAD (64<-32) 1805 op_LGFRL uint32 = 0xC40C // FORMAT_RIL2 LOAD RELATIVE LONG (64<-32) 1806 op_LGH uint32 = 0xE315 // FORMAT_RXY1 LOAD HALFWORD (64) 1807 op_LGHI uint32 = 0xA709 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (64) 1808 op_LGHR uint32 = 0xB907 // FORMAT_RRE LOAD HALFWORD (64) 1809 op_LGHRL uint32 = 0xC404 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (64<-16) 1810 op_LGR uint32 = 0xB904 // FORMAT_RRE LOAD (64) 1811 op_LGRL uint32 = 0xC408 // FORMAT_RIL2 LOAD RELATIVE LONG (64) 1812 op_LH uint32 = 0x4800 // FORMAT_RX1 LOAD HALFWORD (32) 1813 op_LHH uint32 = 0xE3C4 // FORMAT_RXY1 LOAD HALFWORD HIGH (32<-16) 1814 op_LHI uint32 = 0xA708 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (32) 1815 op_LHR uint32 = 0xB927 // FORMAT_RRE LOAD HALFWORD (32) 1816 op_LHRL uint32 = 0xC405 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (32<-16) 1817 op_LHY uint32 = 0xE378 // FORMAT_RXY1 LOAD HALFWORD (32) 1818 op_LLC uint32 = 0xE394 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (32) 1819 op_LLCH uint32 = 0xE3C2 // FORMAT_RXY1 LOAD LOGICAL CHARACTER HIGH (32<-8) 1820 op_LLCR uint32 = 0xB994 // FORMAT_RRE LOAD LOGICAL CHARACTER (32) 1821 op_LLGC uint32 = 0xE390 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (64) 1822 op_LLGCR uint32 = 0xB984 // FORMAT_RRE LOAD LOGICAL CHARACTER (64) 1823 op_LLGF uint32 = 0xE316 // FORMAT_RXY1 LOAD LOGICAL (64<-32) 1824 op_LLGFAT uint32 = 0xE39D // FORMAT_RXY1 LOAD LOGICAL AND TRAP (64<-32) 1825 op_LLGFR uint32 = 0xB916 // FORMAT_RRE LOAD LOGICAL (64<-32) 1826 op_LLGFRL uint32 = 0xC40E // FORMAT_RIL2 LOAD LOGICAL RELATIVE LONG (64<-32) 1827 op_LLGH uint32 = 0xE391 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (64) 1828 op_LLGHR uint32 = 0xB985 // FORMAT_RRE LOAD LOGICAL HALFWORD (64) 1829 op_LLGHRL uint32 = 0xC406 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16) 1830 op_LLGT uint32 = 0xE317 // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS 1831 op_LLGTAT uint32 = 0xE39C // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31) 1832 op_LLGTR uint32 = 0xB917 // FORMAT_RRE LOAD LOGICAL THIRTY ONE BITS 1833 op_LLH uint32 = 0xE395 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (32) 1834 op_LLHH uint32 = 0xE3C6 // FORMAT_RXY1 LOAD LOGICAL HALFWORD HIGH (32<-16) 1835 op_LLHR uint32 = 0xB995 // FORMAT_RRE LOAD LOGICAL HALFWORD (32) 1836 op_LLHRL uint32 = 0xC402 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16) 1837 op_LLIHF uint32 = 0xC00E // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (high) 1838 op_LLIHH uint32 = 0xA50C // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high high) 1839 op_LLIHL uint32 = 0xA50D // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high low) 1840 op_LLILF uint32 = 0xC00F // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (low) 1841 op_LLILH uint32 = 0xA50E // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low high) 1842 op_LLILL uint32 = 0xA50F // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low low) 1843 op_LM uint32 = 0x9800 // FORMAT_RS1 LOAD MULTIPLE (32) 1844 op_LMD uint32 = 0xEF00 // FORMAT_SS5 LOAD MULTIPLE DISJOINT 1845 op_LMG uint32 = 0xEB04 // FORMAT_RSY1 LOAD MULTIPLE (64) 1846 op_LMH uint32 = 0xEB96 // FORMAT_RSY1 LOAD MULTIPLE HIGH 1847 op_LMY uint32 = 0xEB98 // FORMAT_RSY1 LOAD MULTIPLE (32) 1848 op_LNDBR uint32 = 0xB311 // FORMAT_RRE LOAD NEGATIVE (long BFP) 1849 op_LNDFR uint32 = 0xB371 // FORMAT_RRE LOAD NEGATIVE (long) 1850 op_LNDR uint32 = 0x2100 // FORMAT_RR LOAD NEGATIVE (long HFP) 1851 op_LNEBR uint32 = 0xB301 // FORMAT_RRE LOAD NEGATIVE (short BFP) 1852 op_LNER uint32 = 0x3100 // FORMAT_RR LOAD NEGATIVE (short HFP) 1853 op_LNGFR uint32 = 0xB911 // FORMAT_RRE LOAD NEGATIVE (64<-32) 1854 op_LNGR uint32 = 0xB901 // FORMAT_RRE LOAD NEGATIVE (64) 1855 op_LNR uint32 = 0x1100 // FORMAT_RR LOAD NEGATIVE (32) 1856 op_LNXBR uint32 = 0xB341 // FORMAT_RRE LOAD NEGATIVE (extended BFP) 1857 op_LNXR uint32 = 0xB361 // FORMAT_RRE LOAD NEGATIVE (extended HFP) 1858 op_LOC uint32 = 0xEBF2 // FORMAT_RSY2 LOAD ON CONDITION (32) 1859 op_LOCG uint32 = 0xEBE2 // FORMAT_RSY2 LOAD ON CONDITION (64) 1860 op_LOCGR uint32 = 0xB9E2 // FORMAT_RRF3 LOAD ON CONDITION (64) 1861 op_LOCR uint32 = 0xB9F2 // FORMAT_RRF3 LOAD ON CONDITION (32) 1862 op_LPD uint32 = 0xC804 // FORMAT_SSF LOAD PAIR DISJOINT (32) 1863 op_LPDBR uint32 = 0xB310 // FORMAT_RRE LOAD POSITIVE (long BFP) 1864 op_LPDFR uint32 = 0xB370 // FORMAT_RRE LOAD POSITIVE (long) 1865 op_LPDG uint32 = 0xC805 // FORMAT_SSF LOAD PAIR DISJOINT (64) 1866 op_LPDR uint32 = 0x2000 // FORMAT_RR LOAD POSITIVE (long HFP) 1867 op_LPEBR uint32 = 0xB300 // FORMAT_RRE LOAD POSITIVE (short BFP) 1868 op_LPER uint32 = 0x3000 // FORMAT_RR LOAD POSITIVE (short HFP) 1869 op_LPGFR uint32 = 0xB910 // FORMAT_RRE LOAD POSITIVE (64<-32) 1870 op_LPGR uint32 = 0xB900 // FORMAT_RRE LOAD POSITIVE (64) 1871 op_LPQ uint32 = 0xE38F // FORMAT_RXY1 LOAD PAIR FROM QUADWORD 1872 op_LPR uint32 = 0x1000 // FORMAT_RR LOAD POSITIVE (32) 1873 op_LPSW uint32 = 0x8200 // FORMAT_S LOAD PSW 1874 op_LPSWE uint32 = 0xB2B2 // FORMAT_S LOAD PSW EXTENDED 1875 op_LPTEA uint32 = 0xB9AA // FORMAT_RRF2 LOAD PAGE TABLE ENTRY ADDRESS 1876 op_LPXBR uint32 = 0xB340 // FORMAT_RRE LOAD POSITIVE (extended BFP) 1877 op_LPXR uint32 = 0xB360 // FORMAT_RRE LOAD POSITIVE (extended HFP) 1878 op_LR uint32 = 0x1800 // FORMAT_RR LOAD (32) 1879 op_LRA uint32 = 0xB100 // FORMAT_RX1 LOAD REAL ADDRESS (32) 1880 op_LRAG uint32 = 0xE303 // FORMAT_RXY1 LOAD REAL ADDRESS (64) 1881 op_LRAY uint32 = 0xE313 // FORMAT_RXY1 LOAD REAL ADDRESS (32) 1882 op_LRDR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1883 op_LRER uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1884 op_LRL uint32 = 0xC40D // FORMAT_RIL2 LOAD RELATIVE LONG (32) 1885 op_LRV uint32 = 0xE31E // FORMAT_RXY1 LOAD REVERSED (32) 1886 op_LRVG uint32 = 0xE30F // FORMAT_RXY1 LOAD REVERSED (64) 1887 op_LRVGR uint32 = 0xB90F // FORMAT_RRE LOAD REVERSED (64) 1888 op_LRVH uint32 = 0xE31F // FORMAT_RXY1 LOAD REVERSED (16) 1889 op_LRVR uint32 = 0xB91F // FORMAT_RRE LOAD REVERSED (32) 1890 op_LT uint32 = 0xE312 // FORMAT_RXY1 LOAD AND TEST (32) 1891 op_LTDBR uint32 = 0xB312 // FORMAT_RRE LOAD AND TEST (long BFP) 1892 op_LTDR uint32 = 0x2200 // FORMAT_RR LOAD AND TEST (long HFP) 1893 op_LTDTR uint32 = 0xB3D6 // FORMAT_RRE LOAD AND TEST (long DFP) 1894 op_LTEBR uint32 = 0xB302 // FORMAT_RRE LOAD AND TEST (short BFP) 1895 op_LTER uint32 = 0x3200 // FORMAT_RR LOAD AND TEST (short HFP) 1896 op_LTG uint32 = 0xE302 // FORMAT_RXY1 LOAD AND TEST (64) 1897 op_LTGF uint32 = 0xE332 // FORMAT_RXY1 LOAD AND TEST (64<-32) 1898 op_LTGFR uint32 = 0xB912 // FORMAT_RRE LOAD AND TEST (64<-32) 1899 op_LTGR uint32 = 0xB902 // FORMAT_RRE LOAD AND TEST (64) 1900 op_LTR uint32 = 0x1200 // FORMAT_RR LOAD AND TEST (32) 1901 op_LTXBR uint32 = 0xB342 // FORMAT_RRE LOAD AND TEST (extended BFP) 1902 op_LTXR uint32 = 0xB362 // FORMAT_RRE LOAD AND TEST (extended HFP) 1903 op_LTXTR uint32 = 0xB3DE // FORMAT_RRE LOAD AND TEST (extended DFP) 1904 op_LURA uint32 = 0xB24B // FORMAT_RRE LOAD USING REAL ADDRESS (32) 1905 op_LURAG uint32 = 0xB905 // FORMAT_RRE LOAD USING REAL ADDRESS (64) 1906 op_LXD uint32 = 0xED25 // FORMAT_RXE LOAD LENGTHENED (long to extended HFP) 1907 op_LXDB uint32 = 0xED05 // FORMAT_RXE LOAD LENGTHENED (long to extended BFP) 1908 op_LXDBR uint32 = 0xB305 // FORMAT_RRE LOAD LENGTHENED (long to extended BFP) 1909 op_LXDR uint32 = 0xB325 // FORMAT_RRE LOAD LENGTHENED (long to extended HFP) 1910 op_LXDTR uint32 = 0xB3DC // FORMAT_RRF4 LOAD LENGTHENED (long to extended DFP) 1911 op_LXE uint32 = 0xED26 // FORMAT_RXE LOAD LENGTHENED (short to extended HFP) 1912 op_LXEB uint32 = 0xED06 // FORMAT_RXE LOAD LENGTHENED (short to extended BFP) 1913 op_LXEBR uint32 = 0xB306 // FORMAT_RRE LOAD LENGTHENED (short to extended BFP) 1914 op_LXER uint32 = 0xB326 // FORMAT_RRE LOAD LENGTHENED (short to extended HFP) 1915 op_LXR uint32 = 0xB365 // FORMAT_RRE LOAD (extended) 1916 op_LY uint32 = 0xE358 // FORMAT_RXY1 LOAD (32) 1917 op_LZDR uint32 = 0xB375 // FORMAT_RRE LOAD ZERO (long) 1918 op_LZER uint32 = 0xB374 // FORMAT_RRE LOAD ZERO (short) 1919 op_LZXR uint32 = 0xB376 // FORMAT_RRE LOAD ZERO (extended) 1920 op_M uint32 = 0x5C00 // FORMAT_RX1 MULTIPLY (64<-32) 1921 op_MAD uint32 = 0xED3E // FORMAT_RXF MULTIPLY AND ADD (long HFP) 1922 op_MADB uint32 = 0xED1E // FORMAT_RXF MULTIPLY AND ADD (long BFP) 1923 op_MADBR uint32 = 0xB31E // FORMAT_RRD MULTIPLY AND ADD (long BFP) 1924 op_MADR uint32 = 0xB33E // FORMAT_RRD MULTIPLY AND ADD (long HFP) 1925 op_MAE uint32 = 0xED2E // FORMAT_RXF MULTIPLY AND ADD (short HFP) 1926 op_MAEB uint32 = 0xED0E // FORMAT_RXF MULTIPLY AND ADD (short BFP) 1927 op_MAEBR uint32 = 0xB30E // FORMAT_RRD MULTIPLY AND ADD (short BFP) 1928 op_MAER uint32 = 0xB32E // FORMAT_RRD MULTIPLY AND ADD (short HFP) 1929 op_MAY uint32 = 0xED3A // FORMAT_RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1930 op_MAYH uint32 = 0xED3C // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1931 op_MAYHR uint32 = 0xB33C // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1932 op_MAYL uint32 = 0xED38 // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1933 op_MAYLR uint32 = 0xB338 // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1934 op_MAYR uint32 = 0xB33A // FORMAT_RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1935 op_MC uint32 = 0xAF00 // FORMAT_SI MONITOR CALL 1936 op_MD uint32 = 0x6C00 // FORMAT_RX1 MULTIPLY (long HFP) 1937 op_MDB uint32 = 0xED1C // FORMAT_RXE MULTIPLY (long BFP) 1938 op_MDBR uint32 = 0xB31C // FORMAT_RRE MULTIPLY (long BFP) 1939 op_MDE uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1940 op_MDEB uint32 = 0xED0C // FORMAT_RXE MULTIPLY (short to long BFP) 1941 op_MDEBR uint32 = 0xB30C // FORMAT_RRE MULTIPLY (short to long BFP) 1942 op_MDER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1943 op_MDR uint32 = 0x2C00 // FORMAT_RR MULTIPLY (long HFP) 1944 op_MDTR uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1945 op_MDTRA uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1946 op_ME uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1947 op_MEE uint32 = 0xED37 // FORMAT_RXE MULTIPLY (short HFP) 1948 op_MEEB uint32 = 0xED17 // FORMAT_RXE MULTIPLY (short BFP) 1949 op_MEEBR uint32 = 0xB317 // FORMAT_RRE MULTIPLY (short BFP) 1950 op_MEER uint32 = 0xB337 // FORMAT_RRE MULTIPLY (short HFP) 1951 op_MER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1952 op_MFY uint32 = 0xE35C // FORMAT_RXY1 MULTIPLY (64<-32) 1953 op_MGHI uint32 = 0xA70D // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (64) 1954 op_MH uint32 = 0x4C00 // FORMAT_RX1 MULTIPLY HALFWORD (32) 1955 op_MHI uint32 = 0xA70C // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (32) 1956 op_MHY uint32 = 0xE37C // FORMAT_RXY1 MULTIPLY HALFWORD (32) 1957 op_ML uint32 = 0xE396 // FORMAT_RXY1 MULTIPLY LOGICAL (64<-32) 1958 op_MLG uint32 = 0xE386 // FORMAT_RXY1 MULTIPLY LOGICAL (128<-64) 1959 op_MLGR uint32 = 0xB986 // FORMAT_RRE MULTIPLY LOGICAL (128<-64) 1960 op_MLR uint32 = 0xB996 // FORMAT_RRE MULTIPLY LOGICAL (64<-32) 1961 op_MP uint32 = 0xFC00 // FORMAT_SS2 MULTIPLY DECIMAL 1962 op_MR uint32 = 0x1C00 // FORMAT_RR MULTIPLY (64<-32) 1963 op_MS uint32 = 0x7100 // FORMAT_RX1 MULTIPLY SINGLE (32) 1964 op_MSCH uint32 = 0xB232 // FORMAT_S MODIFY SUBCHANNEL 1965 op_MSD uint32 = 0xED3F // FORMAT_RXF MULTIPLY AND SUBTRACT (long HFP) 1966 op_MSDB uint32 = 0xED1F // FORMAT_RXF MULTIPLY AND SUBTRACT (long BFP) 1967 op_MSDBR uint32 = 0xB31F // FORMAT_RRD MULTIPLY AND SUBTRACT (long BFP) 1968 op_MSDR uint32 = 0xB33F // FORMAT_RRD MULTIPLY AND SUBTRACT (long HFP) 1969 op_MSE uint32 = 0xED2F // FORMAT_RXF MULTIPLY AND SUBTRACT (short HFP) 1970 op_MSEB uint32 = 0xED0F // FORMAT_RXF MULTIPLY AND SUBTRACT (short BFP) 1971 op_MSEBR uint32 = 0xB30F // FORMAT_RRD MULTIPLY AND SUBTRACT (short BFP) 1972 op_MSER uint32 = 0xB32F // FORMAT_RRD MULTIPLY AND SUBTRACT (short HFP) 1973 op_MSFI uint32 = 0xC201 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (32) 1974 op_MSG uint32 = 0xE30C // FORMAT_RXY1 MULTIPLY SINGLE (64) 1975 op_MSGF uint32 = 0xE31C // FORMAT_RXY1 MULTIPLY SINGLE (64<-32) 1976 op_MSGFI uint32 = 0xC200 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (64<-32) 1977 op_MSGFR uint32 = 0xB91C // FORMAT_RRE MULTIPLY SINGLE (64<-32) 1978 op_MSGR uint32 = 0xB90C // FORMAT_RRE MULTIPLY SINGLE (64) 1979 op_MSR uint32 = 0xB252 // FORMAT_RRE MULTIPLY SINGLE (32) 1980 op_MSTA uint32 = 0xB247 // FORMAT_RRE MODIFY STACKED STATE 1981 op_MSY uint32 = 0xE351 // FORMAT_RXY1 MULTIPLY SINGLE (32) 1982 op_MVC uint32 = 0xD200 // FORMAT_SS1 MOVE (character) 1983 op_MVCDK uint32 = 0xE50F // FORMAT_SSE MOVE WITH DESTINATION KEY 1984 op_MVCIN uint32 = 0xE800 // FORMAT_SS1 MOVE INVERSE 1985 op_MVCK uint32 = 0xD900 // FORMAT_SS4 MOVE WITH KEY 1986 op_MVCL uint32 = 0x0E00 // FORMAT_RR MOVE LONG 1987 op_MVCLE uint32 = 0xA800 // FORMAT_RS1 MOVE LONG EXTENDED 1988 op_MVCLU uint32 = 0xEB8E // FORMAT_RSY1 MOVE LONG UNICODE 1989 op_MVCOS uint32 = 0xC800 // FORMAT_SSF MOVE WITH OPTIONAL SPECIFICATIONS 1990 op_MVCP uint32 = 0xDA00 // FORMAT_SS4 MOVE TO PRIMARY 1991 op_MVCS uint32 = 0xDB00 // FORMAT_SS4 MOVE TO SECONDARY 1992 op_MVCSK uint32 = 0xE50E // FORMAT_SSE MOVE WITH SOURCE KEY 1993 op_MVGHI uint32 = 0xE548 // FORMAT_SIL MOVE (64<-16) 1994 op_MVHHI uint32 = 0xE544 // FORMAT_SIL MOVE (16<-16) 1995 op_MVHI uint32 = 0xE54C // FORMAT_SIL MOVE (32<-16) 1996 op_MVI uint32 = 0x9200 // FORMAT_SI MOVE (immediate) 1997 op_MVIY uint32 = 0xEB52 // FORMAT_SIY MOVE (immediate) 1998 op_MVN uint32 = 0xD100 // FORMAT_SS1 MOVE NUMERICS 1999 op_MVO uint32 = 0xF100 // FORMAT_SS2 MOVE WITH OFFSET 2000 op_MVPG uint32 = 0xB254 // FORMAT_RRE MOVE PAGE 2001 op_MVST uint32 = 0xB255 // FORMAT_RRE MOVE STRING 2002 op_MVZ uint32 = 0xD300 // FORMAT_SS1 MOVE ZONES 2003 op_MXBR uint32 = 0xB34C // FORMAT_RRE MULTIPLY (extended BFP) 2004 op_MXD uint32 = 0x6700 // FORMAT_RX1 MULTIPLY (long to extended HFP) 2005 op_MXDB uint32 = 0xED07 // FORMAT_RXE MULTIPLY (long to extended BFP) 2006 op_MXDBR uint32 = 0xB307 // FORMAT_RRE MULTIPLY (long to extended BFP) 2007 op_MXDR uint32 = 0x2700 // FORMAT_RR MULTIPLY (long to extended HFP) 2008 op_MXR uint32 = 0x2600 // FORMAT_RR MULTIPLY (extended HFP) 2009 op_MXTR uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2010 op_MXTRA uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2011 op_MY uint32 = 0xED3B // FORMAT_RXF MULTIPLY UNNORMALIZED (long to ext. HFP) 2012 op_MYH uint32 = 0xED3D // FORMAT_RXF MULTIPLY UNNORM. (long to ext. high HFP) 2013 op_MYHR uint32 = 0xB33D // FORMAT_RRD MULTIPLY UNNORM. (long to ext. high HFP) 2014 op_MYL uint32 = 0xED39 // FORMAT_RXF MULTIPLY UNNORM. (long to ext. low HFP) 2015 op_MYLR uint32 = 0xB339 // FORMAT_RRD MULTIPLY UNNORM. (long to ext. low HFP) 2016 op_MYR uint32 = 0xB33B // FORMAT_RRD MULTIPLY UNNORMALIZED (long to ext. HFP) 2017 op_N uint32 = 0x5400 // FORMAT_RX1 AND (32) 2018 op_NC uint32 = 0xD400 // FORMAT_SS1 AND (character) 2019 op_NG uint32 = 0xE380 // FORMAT_RXY1 AND (64) 2020 op_NGR uint32 = 0xB980 // FORMAT_RRE AND (64) 2021 op_NGRK uint32 = 0xB9E4 // FORMAT_RRF1 AND (64) 2022 op_NI uint32 = 0x9400 // FORMAT_SI AND (immediate) 2023 op_NIAI uint32 = 0xB2FA // FORMAT_IE NEXT INSTRUCTION ACCESS INTENT 2024 op_NIHF uint32 = 0xC00A // FORMAT_RIL1 AND IMMEDIATE (high) 2025 op_NIHH uint32 = 0xA504 // FORMAT_RI1 AND IMMEDIATE (high high) 2026 op_NIHL uint32 = 0xA505 // FORMAT_RI1 AND IMMEDIATE (high low) 2027 op_NILF uint32 = 0xC00B // FORMAT_RIL1 AND IMMEDIATE (low) 2028 op_NILH uint32 = 0xA506 // FORMAT_RI1 AND IMMEDIATE (low high) 2029 op_NILL uint32 = 0xA507 // FORMAT_RI1 AND IMMEDIATE (low low) 2030 op_NIY uint32 = 0xEB54 // FORMAT_SIY AND (immediate) 2031 op_NR uint32 = 0x1400 // FORMAT_RR AND (32) 2032 op_NRK uint32 = 0xB9F4 // FORMAT_RRF1 AND (32) 2033 op_NTSTG uint32 = 0xE325 // FORMAT_RXY1 NONTRANSACTIONAL STORE 2034 op_NY uint32 = 0xE354 // FORMAT_RXY1 AND (32) 2035 op_O uint32 = 0x5600 // FORMAT_RX1 OR (32) 2036 op_OC uint32 = 0xD600 // FORMAT_SS1 OR (character) 2037 op_OG uint32 = 0xE381 // FORMAT_RXY1 OR (64) 2038 op_OGR uint32 = 0xB981 // FORMAT_RRE OR (64) 2039 op_OGRK uint32 = 0xB9E6 // FORMAT_RRF1 OR (64) 2040 op_OI uint32 = 0x9600 // FORMAT_SI OR (immediate) 2041 op_OIHF uint32 = 0xC00C // FORMAT_RIL1 OR IMMEDIATE (high) 2042 op_OIHH uint32 = 0xA508 // FORMAT_RI1 OR IMMEDIATE (high high) 2043 op_OIHL uint32 = 0xA509 // FORMAT_RI1 OR IMMEDIATE (high low) 2044 op_OILF uint32 = 0xC00D // FORMAT_RIL1 OR IMMEDIATE (low) 2045 op_OILH uint32 = 0xA50A // FORMAT_RI1 OR IMMEDIATE (low high) 2046 op_OILL uint32 = 0xA50B // FORMAT_RI1 OR IMMEDIATE (low low) 2047 op_OIY uint32 = 0xEB56 // FORMAT_SIY OR (immediate) 2048 op_OR uint32 = 0x1600 // FORMAT_RR OR (32) 2049 op_ORK uint32 = 0xB9F6 // FORMAT_RRF1 OR (32) 2050 op_OY uint32 = 0xE356 // FORMAT_RXY1 OR (32) 2051 op_PACK uint32 = 0xF200 // FORMAT_SS2 PACK 2052 op_PALB uint32 = 0xB248 // FORMAT_RRE PURGE ALB 2053 op_PC uint32 = 0xB218 // FORMAT_S PROGRAM CALL 2054 op_PCC uint32 = 0xB92C // FORMAT_RRE PERFORM CRYPTOGRAPHIC COMPUTATION 2055 op_PCKMO uint32 = 0xB928 // FORMAT_RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS 2056 op_PFD uint32 = 0xE336 // FORMAT_RXY2 PREFETCH DATA 2057 op_PFDRL uint32 = 0xC602 // FORMAT_RIL3 PREFETCH DATA RELATIVE LONG 2058 op_PFMF uint32 = 0xB9AF // FORMAT_RRE PERFORM FRAME MANAGEMENT FUNCTION 2059 op_PFPO uint32 = 0x010A // FORMAT_E PERFORM FLOATING-POINT OPERATION 2060 op_PGIN uint32 = 0xB22E // FORMAT_RRE PAGE IN 2061 op_PGOUT uint32 = 0xB22F // FORMAT_RRE PAGE OUT 2062 op_PKA uint32 = 0xE900 // FORMAT_SS6 PACK ASCII 2063 op_PKU uint32 = 0xE100 // FORMAT_SS6 PACK UNICODE 2064 op_PLO uint32 = 0xEE00 // FORMAT_SS5 PERFORM LOCKED OPERATION 2065 op_POPCNT uint32 = 0xB9E1 // FORMAT_RRE POPULATION COUNT 2066 op_PPA uint32 = 0xB2E8 // FORMAT_RRF3 PERFORM PROCESSOR ASSIST 2067 op_PR uint32 = 0x0101 // FORMAT_E PROGRAM RETURN 2068 op_PT uint32 = 0xB228 // FORMAT_RRE PROGRAM TRANSFER 2069 op_PTF uint32 = 0xB9A2 // FORMAT_RRE PERFORM TOPOLOGY FUNCTION 2070 op_PTFF uint32 = 0x0104 // FORMAT_E PERFORM TIMING FACILITY FUNCTION 2071 op_PTI uint32 = 0xB99E // FORMAT_RRE PROGRAM TRANSFER WITH INSTANCE 2072 op_PTLB uint32 = 0xB20D // FORMAT_S PURGE TLB 2073 op_QADTR uint32 = 0xB3F5 // FORMAT_RRF2 QUANTIZE (long DFP) 2074 op_QAXTR uint32 = 0xB3FD // FORMAT_RRF2 QUANTIZE (extended DFP) 2075 op_RCHP uint32 = 0xB23B // FORMAT_S RESET CHANNEL PATH 2076 op_RISBG uint32 = 0xEC55 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2077 op_RISBGN uint32 = 0xEC59 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2078 op_RISBHG uint32 = 0xEC5D // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS HIGH 2079 op_RISBLG uint32 = 0xEC51 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS LOW 2080 op_RLL uint32 = 0xEB1D // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (32) 2081 op_RLLG uint32 = 0xEB1C // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (64) 2082 op_RNSBG uint32 = 0xEC54 // FORMAT_RIE6 ROTATE THEN AND SELECTED BITS 2083 op_ROSBG uint32 = 0xEC56 // FORMAT_RIE6 ROTATE THEN OR SELECTED BITS 2084 op_RP uint32 = 0xB277 // FORMAT_S RESUME PROGRAM 2085 op_RRBE uint32 = 0xB22A // FORMAT_RRE RESET REFERENCE BIT EXTENDED 2086 op_RRBM uint32 = 0xB9AE // FORMAT_RRE RESET REFERENCE BITS MULTIPLE 2087 op_RRDTR uint32 = 0xB3F7 // FORMAT_RRF2 REROUND (long DFP) 2088 op_RRXTR uint32 = 0xB3FF // FORMAT_RRF2 REROUND (extended DFP) 2089 op_RSCH uint32 = 0xB238 // FORMAT_S RESUME SUBCHANNEL 2090 op_RXSBG uint32 = 0xEC57 // FORMAT_RIE6 ROTATE THEN EXCLUSIVE OR SELECTED BITS 2091 op_S uint32 = 0x5B00 // FORMAT_RX1 SUBTRACT (32) 2092 op_SAC uint32 = 0xB219 // FORMAT_S SET ADDRESS SPACE CONTROL 2093 op_SACF uint32 = 0xB279 // FORMAT_S SET ADDRESS SPACE CONTROL FAST 2094 op_SAL uint32 = 0xB237 // FORMAT_S SET ADDRESS LIMIT 2095 op_SAM24 uint32 = 0x010C // FORMAT_E SET ADDRESSING MODE (24) 2096 op_SAM31 uint32 = 0x010D // FORMAT_E SET ADDRESSING MODE (31) 2097 op_SAM64 uint32 = 0x010E // FORMAT_E SET ADDRESSING MODE (64) 2098 op_SAR uint32 = 0xB24E // FORMAT_RRE SET ACCESS 2099 op_SCHM uint32 = 0xB23C // FORMAT_S SET CHANNEL MONITOR 2100 op_SCK uint32 = 0xB204 // FORMAT_S SET CLOCK 2101 op_SCKC uint32 = 0xB206 // FORMAT_S SET CLOCK COMPARATOR 2102 op_SCKPF uint32 = 0x0107 // FORMAT_E SET CLOCK PROGRAMMABLE FIELD 2103 op_SD uint32 = 0x6B00 // FORMAT_RX1 SUBTRACT NORMALIZED (long HFP) 2104 op_SDB uint32 = 0xED1B // FORMAT_RXE SUBTRACT (long BFP) 2105 op_SDBR uint32 = 0xB31B // FORMAT_RRE SUBTRACT (long BFP) 2106 op_SDR uint32 = 0x2B00 // FORMAT_RR SUBTRACT NORMALIZED (long HFP) 2107 op_SDTR uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2108 op_SDTRA uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2109 op_SE uint32 = 0x7B00 // FORMAT_RX1 SUBTRACT NORMALIZED (short HFP) 2110 op_SEB uint32 = 0xED0B // FORMAT_RXE SUBTRACT (short BFP) 2111 op_SEBR uint32 = 0xB30B // FORMAT_RRE SUBTRACT (short BFP) 2112 op_SER uint32 = 0x3B00 // FORMAT_RR SUBTRACT NORMALIZED (short HFP) 2113 op_SFASR uint32 = 0xB385 // FORMAT_RRE SET FPC AND SIGNAL 2114 op_SFPC uint32 = 0xB384 // FORMAT_RRE SET FPC 2115 op_SG uint32 = 0xE309 // FORMAT_RXY1 SUBTRACT (64) 2116 op_SGF uint32 = 0xE319 // FORMAT_RXY1 SUBTRACT (64<-32) 2117 op_SGFR uint32 = 0xB919 // FORMAT_RRE SUBTRACT (64<-32) 2118 op_SGR uint32 = 0xB909 // FORMAT_RRE SUBTRACT (64) 2119 op_SGRK uint32 = 0xB9E9 // FORMAT_RRF1 SUBTRACT (64) 2120 op_SH uint32 = 0x4B00 // FORMAT_RX1 SUBTRACT HALFWORD 2121 op_SHHHR uint32 = 0xB9C9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2122 op_SHHLR uint32 = 0xB9D9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2123 op_SHY uint32 = 0xE37B // FORMAT_RXY1 SUBTRACT HALFWORD 2124 op_SIGP uint32 = 0xAE00 // FORMAT_RS1 SIGNAL PROCESSOR 2125 op_SL uint32 = 0x5F00 // FORMAT_RX1 SUBTRACT LOGICAL (32) 2126 op_SLA uint32 = 0x8B00 // FORMAT_RS1 SHIFT LEFT SINGLE (32) 2127 op_SLAG uint32 = 0xEB0B // FORMAT_RSY1 SHIFT LEFT SINGLE (64) 2128 op_SLAK uint32 = 0xEBDD // FORMAT_RSY1 SHIFT LEFT SINGLE (32) 2129 op_SLB uint32 = 0xE399 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (32) 2130 op_SLBG uint32 = 0xE389 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (64) 2131 op_SLBGR uint32 = 0xB989 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (64) 2132 op_SLBR uint32 = 0xB999 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (32) 2133 op_SLDA uint32 = 0x8F00 // FORMAT_RS1 SHIFT LEFT DOUBLE 2134 op_SLDL uint32 = 0x8D00 // FORMAT_RS1 SHIFT LEFT DOUBLE LOGICAL 2135 op_SLDT uint32 = 0xED40 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (long DFP) 2136 op_SLFI uint32 = 0xC205 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (32) 2137 op_SLG uint32 = 0xE30B // FORMAT_RXY1 SUBTRACT LOGICAL (64) 2138 op_SLGF uint32 = 0xE31B // FORMAT_RXY1 SUBTRACT LOGICAL (64<-32) 2139 op_SLGFI uint32 = 0xC204 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (64<-32) 2140 op_SLGFR uint32 = 0xB91B // FORMAT_RRE SUBTRACT LOGICAL (64<-32) 2141 op_SLGR uint32 = 0xB90B // FORMAT_RRE SUBTRACT LOGICAL (64) 2142 op_SLGRK uint32 = 0xB9EB // FORMAT_RRF1 SUBTRACT LOGICAL (64) 2143 op_SLHHHR uint32 = 0xB9CB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2144 op_SLHHLR uint32 = 0xB9DB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2145 op_SLL uint32 = 0x8900 // FORMAT_RS1 SHIFT LEFT SINGLE LOGICAL (32) 2146 op_SLLG uint32 = 0xEB0D // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (64) 2147 op_SLLK uint32 = 0xEBDF // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (32) 2148 op_SLR uint32 = 0x1F00 // FORMAT_RR SUBTRACT LOGICAL (32) 2149 op_SLRK uint32 = 0xB9FB // FORMAT_RRF1 SUBTRACT LOGICAL (32) 2150 op_SLXT uint32 = 0xED48 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (extended DFP) 2151 op_SLY uint32 = 0xE35F // FORMAT_RXY1 SUBTRACT LOGICAL (32) 2152 op_SP uint32 = 0xFB00 // FORMAT_SS2 SUBTRACT DECIMAL 2153 op_SPKA uint32 = 0xB20A // FORMAT_S SET PSW KEY FROM ADDRESS 2154 op_SPM uint32 = 0x0400 // FORMAT_RR SET PROGRAM MASK 2155 op_SPT uint32 = 0xB208 // FORMAT_S SET CPU TIMER 2156 op_SPX uint32 = 0xB210 // FORMAT_S SET PREFIX 2157 op_SQD uint32 = 0xED35 // FORMAT_RXE SQUARE ROOT (long HFP) 2158 op_SQDB uint32 = 0xED15 // FORMAT_RXE SQUARE ROOT (long BFP) 2159 op_SQDBR uint32 = 0xB315 // FORMAT_RRE SQUARE ROOT (long BFP) 2160 op_SQDR uint32 = 0xB244 // FORMAT_RRE SQUARE ROOT (long HFP) 2161 op_SQE uint32 = 0xED34 // FORMAT_RXE SQUARE ROOT (short HFP) 2162 op_SQEB uint32 = 0xED14 // FORMAT_RXE SQUARE ROOT (short BFP) 2163 op_SQEBR uint32 = 0xB314 // FORMAT_RRE SQUARE ROOT (short BFP) 2164 op_SQER uint32 = 0xB245 // FORMAT_RRE SQUARE ROOT (short HFP) 2165 op_SQXBR uint32 = 0xB316 // FORMAT_RRE SQUARE ROOT (extended BFP) 2166 op_SQXR uint32 = 0xB336 // FORMAT_RRE SQUARE ROOT (extended HFP) 2167 op_SR uint32 = 0x1B00 // FORMAT_RR SUBTRACT (32) 2168 op_SRA uint32 = 0x8A00 // FORMAT_RS1 SHIFT RIGHT SINGLE (32) 2169 op_SRAG uint32 = 0xEB0A // FORMAT_RSY1 SHIFT RIGHT SINGLE (64) 2170 op_SRAK uint32 = 0xEBDC // FORMAT_RSY1 SHIFT RIGHT SINGLE (32) 2171 op_SRDA uint32 = 0x8E00 // FORMAT_RS1 SHIFT RIGHT DOUBLE 2172 op_SRDL uint32 = 0x8C00 // FORMAT_RS1 SHIFT RIGHT DOUBLE LOGICAL 2173 op_SRDT uint32 = 0xED41 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (long DFP) 2174 op_SRK uint32 = 0xB9F9 // FORMAT_RRF1 SUBTRACT (32) 2175 op_SRL uint32 = 0x8800 // FORMAT_RS1 SHIFT RIGHT SINGLE LOGICAL (32) 2176 op_SRLG uint32 = 0xEB0C // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (64) 2177 op_SRLK uint32 = 0xEBDE // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (32) 2178 op_SRNM uint32 = 0xB299 // FORMAT_S SET BFP ROUNDING MODE (2 bit) 2179 op_SRNMB uint32 = 0xB2B8 // FORMAT_S SET BFP ROUNDING MODE (3 bit) 2180 op_SRNMT uint32 = 0xB2B9 // FORMAT_S SET DFP ROUNDING MODE 2181 op_SRP uint32 = 0xF000 // FORMAT_SS3 SHIFT AND ROUND DECIMAL 2182 op_SRST uint32 = 0xB25E // FORMAT_RRE SEARCH STRING 2183 op_SRSTU uint32 = 0xB9BE // FORMAT_RRE SEARCH STRING UNICODE 2184 op_SRXT uint32 = 0xED49 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (extended DFP) 2185 op_SSAIR uint32 = 0xB99F // FORMAT_RRE SET SECONDARY ASN WITH INSTANCE 2186 op_SSAR uint32 = 0xB225 // FORMAT_RRE SET SECONDARY ASN 2187 op_SSCH uint32 = 0xB233 // FORMAT_S START SUBCHANNEL 2188 op_SSKE uint32 = 0xB22B // FORMAT_RRF3 SET STORAGE KEY EXTENDED 2189 op_SSM uint32 = 0x8000 // FORMAT_S SET SYSTEM MASK 2190 op_ST uint32 = 0x5000 // FORMAT_RX1 STORE (32) 2191 op_STAM uint32 = 0x9B00 // FORMAT_RS1 STORE ACCESS MULTIPLE 2192 op_STAMY uint32 = 0xEB9B // FORMAT_RSY1 STORE ACCESS MULTIPLE 2193 op_STAP uint32 = 0xB212 // FORMAT_S STORE CPU ADDRESS 2194 op_STC uint32 = 0x4200 // FORMAT_RX1 STORE CHARACTER 2195 op_STCH uint32 = 0xE3C3 // FORMAT_RXY1 STORE CHARACTER HIGH (8) 2196 op_STCK uint32 = 0xB205 // FORMAT_S STORE CLOCK 2197 op_STCKC uint32 = 0xB207 // FORMAT_S STORE CLOCK COMPARATOR 2198 op_STCKE uint32 = 0xB278 // FORMAT_S STORE CLOCK EXTENDED 2199 op_STCKF uint32 = 0xB27C // FORMAT_S STORE CLOCK FAST 2200 op_STCM uint32 = 0xBE00 // FORMAT_RS2 STORE CHARACTERS UNDER MASK (low) 2201 op_STCMH uint32 = 0xEB2C // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (high) 2202 op_STCMY uint32 = 0xEB2D // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (low) 2203 op_STCPS uint32 = 0xB23A // FORMAT_S STORE CHANNEL PATH STATUS 2204 op_STCRW uint32 = 0xB239 // FORMAT_S STORE CHANNEL REPORT WORD 2205 op_STCTG uint32 = 0xEB25 // FORMAT_RSY1 STORE CONTROL (64) 2206 op_STCTL uint32 = 0xB600 // FORMAT_RS1 STORE CONTROL (32) 2207 op_STCY uint32 = 0xE372 // FORMAT_RXY1 STORE CHARACTER 2208 op_STD uint32 = 0x6000 // FORMAT_RX1 STORE (long) 2209 op_STDY uint32 = 0xED67 // FORMAT_RXY1 STORE (long) 2210 op_STE uint32 = 0x7000 // FORMAT_RX1 STORE (short) 2211 op_STEY uint32 = 0xED66 // FORMAT_RXY1 STORE (short) 2212 op_STFH uint32 = 0xE3CB // FORMAT_RXY1 STORE HIGH (32) 2213 op_STFL uint32 = 0xB2B1 // FORMAT_S STORE FACILITY LIST 2214 op_STFLE uint32 = 0xB2B0 // FORMAT_S STORE FACILITY LIST EXTENDED 2215 op_STFPC uint32 = 0xB29C // FORMAT_S STORE FPC 2216 op_STG uint32 = 0xE324 // FORMAT_RXY1 STORE (64) 2217 op_STGRL uint32 = 0xC40B // FORMAT_RIL2 STORE RELATIVE LONG (64) 2218 op_STH uint32 = 0x4000 // FORMAT_RX1 STORE HALFWORD 2219 op_STHH uint32 = 0xE3C7 // FORMAT_RXY1 STORE HALFWORD HIGH (16) 2220 op_STHRL uint32 = 0xC407 // FORMAT_RIL2 STORE HALFWORD RELATIVE LONG 2221 op_STHY uint32 = 0xE370 // FORMAT_RXY1 STORE HALFWORD 2222 op_STIDP uint32 = 0xB202 // FORMAT_S STORE CPU ID 2223 op_STM uint32 = 0x9000 // FORMAT_RS1 STORE MULTIPLE (32) 2224 op_STMG uint32 = 0xEB24 // FORMAT_RSY1 STORE MULTIPLE (64) 2225 op_STMH uint32 = 0xEB26 // FORMAT_RSY1 STORE MULTIPLE HIGH 2226 op_STMY uint32 = 0xEB90 // FORMAT_RSY1 STORE MULTIPLE (32) 2227 op_STNSM uint32 = 0xAC00 // FORMAT_SI STORE THEN AND SYSTEM MASK 2228 op_STOC uint32 = 0xEBF3 // FORMAT_RSY2 STORE ON CONDITION (32) 2229 op_STOCG uint32 = 0xEBE3 // FORMAT_RSY2 STORE ON CONDITION (64) 2230 op_STOSM uint32 = 0xAD00 // FORMAT_SI STORE THEN OR SYSTEM MASK 2231 op_STPQ uint32 = 0xE38E // FORMAT_RXY1 STORE PAIR TO QUADWORD 2232 op_STPT uint32 = 0xB209 // FORMAT_S STORE CPU TIMER 2233 op_STPX uint32 = 0xB211 // FORMAT_S STORE PREFIX 2234 op_STRAG uint32 = 0xE502 // FORMAT_SSE STORE REAL ADDRESS 2235 op_STRL uint32 = 0xC40F // FORMAT_RIL2 STORE RELATIVE LONG (32) 2236 op_STRV uint32 = 0xE33E // FORMAT_RXY1 STORE REVERSED (32) 2237 op_STRVG uint32 = 0xE32F // FORMAT_RXY1 STORE REVERSED (64) 2238 op_STRVH uint32 = 0xE33F // FORMAT_RXY1 STORE REVERSED (16) 2239 op_STSCH uint32 = 0xB234 // FORMAT_S STORE SUBCHANNEL 2240 op_STSI uint32 = 0xB27D // FORMAT_S STORE SYSTEM INFORMATION 2241 op_STURA uint32 = 0xB246 // FORMAT_RRE STORE USING REAL ADDRESS (32) 2242 op_STURG uint32 = 0xB925 // FORMAT_RRE STORE USING REAL ADDRESS (64) 2243 op_STY uint32 = 0xE350 // FORMAT_RXY1 STORE (32) 2244 op_SU uint32 = 0x7F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (short HFP) 2245 op_SUR uint32 = 0x3F00 // FORMAT_RR SUBTRACT UNNORMALIZED (short HFP) 2246 op_SVC uint32 = 0x0A00 // FORMAT_I SUPERVISOR CALL 2247 op_SW uint32 = 0x6F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (long HFP) 2248 op_SWR uint32 = 0x2F00 // FORMAT_RR SUBTRACT UNNORMALIZED (long HFP) 2249 op_SXBR uint32 = 0xB34B // FORMAT_RRE SUBTRACT (extended BFP) 2250 op_SXR uint32 = 0x3700 // FORMAT_RR SUBTRACT NORMALIZED (extended HFP) 2251 op_SXTR uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2252 op_SXTRA uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2253 op_SY uint32 = 0xE35B // FORMAT_RXY1 SUBTRACT (32) 2254 op_TABORT uint32 = 0xB2FC // FORMAT_S TRANSACTION ABORT 2255 op_TAM uint32 = 0x010B // FORMAT_E TEST ADDRESSING MODE 2256 op_TAR uint32 = 0xB24C // FORMAT_RRE TEST ACCESS 2257 op_TB uint32 = 0xB22C // FORMAT_RRE TEST BLOCK 2258 op_TBDR uint32 = 0xB351 // FORMAT_RRF5 CONVERT HFP TO BFP (long) 2259 op_TBEDR uint32 = 0xB350 // FORMAT_RRF5 CONVERT HFP TO BFP (long to short) 2260 op_TBEGIN uint32 = 0xE560 // FORMAT_SIL TRANSACTION BEGIN 2261 op_TBEGINC uint32 = 0xE561 // FORMAT_SIL TRANSACTION BEGIN 2262 op_TCDB uint32 = 0xED11 // FORMAT_RXE TEST DATA CLASS (long BFP) 2263 op_TCEB uint32 = 0xED10 // FORMAT_RXE TEST DATA CLASS (short BFP) 2264 op_TCXB uint32 = 0xED12 // FORMAT_RXE TEST DATA CLASS (extended BFP) 2265 op_TDCDT uint32 = 0xED54 // FORMAT_RXE TEST DATA CLASS (long DFP) 2266 op_TDCET uint32 = 0xED50 // FORMAT_RXE TEST DATA CLASS (short DFP) 2267 op_TDCXT uint32 = 0xED58 // FORMAT_RXE TEST DATA CLASS (extended DFP) 2268 op_TDGDT uint32 = 0xED55 // FORMAT_RXE TEST DATA GROUP (long DFP) 2269 op_TDGET uint32 = 0xED51 // FORMAT_RXE TEST DATA GROUP (short DFP) 2270 op_TDGXT uint32 = 0xED59 // FORMAT_RXE TEST DATA GROUP (extended DFP) 2271 op_TEND uint32 = 0xB2F8 // FORMAT_S TRANSACTION END 2272 op_THDER uint32 = 0xB358 // FORMAT_RRE CONVERT BFP TO HFP (short to long) 2273 op_THDR uint32 = 0xB359 // FORMAT_RRE CONVERT BFP TO HFP (long) 2274 op_TM uint32 = 0x9100 // FORMAT_SI TEST UNDER MASK 2275 op_TMH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK HIGH 2276 op_TMHH uint32 = 0xA702 // FORMAT_RI1 TEST UNDER MASK (high high) 2277 op_TMHL uint32 = 0xA703 // FORMAT_RI1 TEST UNDER MASK (high low) 2278 op_TML uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK LOW 2279 op_TMLH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK (low high) 2280 op_TMLL uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK (low low) 2281 op_TMY uint32 = 0xEB51 // FORMAT_SIY TEST UNDER MASK 2282 op_TP uint32 = 0xEBC0 // FORMAT_RSL TEST DECIMAL 2283 op_TPI uint32 = 0xB236 // FORMAT_S TEST PENDING INTERRUPTION 2284 op_TPROT uint32 = 0xE501 // FORMAT_SSE TEST PROTECTION 2285 op_TR uint32 = 0xDC00 // FORMAT_SS1 TRANSLATE 2286 op_TRACE uint32 = 0x9900 // FORMAT_RS1 TRACE (32) 2287 op_TRACG uint32 = 0xEB0F // FORMAT_RSY1 TRACE (64) 2288 op_TRAP2 uint32 = 0x01FF // FORMAT_E TRAP 2289 op_TRAP4 uint32 = 0xB2FF // FORMAT_S TRAP 2290 op_TRE uint32 = 0xB2A5 // FORMAT_RRE TRANSLATE EXTENDED 2291 op_TROO uint32 = 0xB993 // FORMAT_RRF3 TRANSLATE ONE TO ONE 2292 op_TROT uint32 = 0xB992 // FORMAT_RRF3 TRANSLATE ONE TO TWO 2293 op_TRT uint32 = 0xDD00 // FORMAT_SS1 TRANSLATE AND TEST 2294 op_TRTE uint32 = 0xB9BF // FORMAT_RRF3 TRANSLATE AND TEST EXTENDED 2295 op_TRTO uint32 = 0xB991 // FORMAT_RRF3 TRANSLATE TWO TO ONE 2296 op_TRTR uint32 = 0xD000 // FORMAT_SS1 TRANSLATE AND TEST REVERSE 2297 op_TRTRE uint32 = 0xB9BD // FORMAT_RRF3 TRANSLATE AND TEST REVERSE EXTENDED 2298 op_TRTT uint32 = 0xB990 // FORMAT_RRF3 TRANSLATE TWO TO TWO 2299 op_TS uint32 = 0x9300 // FORMAT_S TEST AND SET 2300 op_TSCH uint32 = 0xB235 // FORMAT_S TEST SUBCHANNEL 2301 op_UNPK uint32 = 0xF300 // FORMAT_SS2 UNPACK 2302 op_UNPKA uint32 = 0xEA00 // FORMAT_SS1 UNPACK ASCII 2303 op_UNPKU uint32 = 0xE200 // FORMAT_SS1 UNPACK UNICODE 2304 op_UPT uint32 = 0x0102 // FORMAT_E UPDATE TREE 2305 op_X uint32 = 0x5700 // FORMAT_RX1 EXCLUSIVE OR (32) 2306 op_XC uint32 = 0xD700 // FORMAT_SS1 EXCLUSIVE OR (character) 2307 op_XG uint32 = 0xE382 // FORMAT_RXY1 EXCLUSIVE OR (64) 2308 op_XGR uint32 = 0xB982 // FORMAT_RRE EXCLUSIVE OR (64) 2309 op_XGRK uint32 = 0xB9E7 // FORMAT_RRF1 EXCLUSIVE OR (64) 2310 op_XI uint32 = 0x9700 // FORMAT_SI EXCLUSIVE OR (immediate) 2311 op_XIHF uint32 = 0xC006 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (high) 2312 op_XILF uint32 = 0xC007 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (low) 2313 op_XIY uint32 = 0xEB57 // FORMAT_SIY EXCLUSIVE OR (immediate) 2314 op_XR uint32 = 0x1700 // FORMAT_RR EXCLUSIVE OR (32) 2315 op_XRK uint32 = 0xB9F7 // FORMAT_RRF1 EXCLUSIVE OR (32) 2316 op_XSCH uint32 = 0xB276 // FORMAT_S CANCEL SUBCHANNEL 2317 op_XY uint32 = 0xE357 // FORMAT_RXY1 EXCLUSIVE OR (32) 2318 op_ZAP uint32 = 0xF800 // FORMAT_SS2 ZERO AND ADD 2319 2320 // added in z13 2321 op_CXPT uint32 = 0xEDAF // RSL-b CONVERT FROM PACKED (to extended DFP) 2322 op_CDPT uint32 = 0xEDAE // RSL-b CONVERT FROM PACKED (to long DFP) 2323 op_CPXT uint32 = 0xEDAD // RSL-b CONVERT TO PACKED (from extended DFP) 2324 op_CPDT uint32 = 0xEDAC // RSL-b CONVERT TO PACKED (from long DFP) 2325 op_LZRF uint32 = 0xE33B // RXY-a LOAD AND ZERO RIGHTMOST BYTE (32) 2326 op_LZRG uint32 = 0xE32A // RXY-a LOAD AND ZERO RIGHTMOST BYTE (64) 2327 op_LCCB uint32 = 0xE727 // RXE LOAD COUNT TO BLOCK BOUNDARY 2328 op_LOCHHI uint32 = 0xEC4E // RIE-g LOAD HALFWORD HIGH IMMEDIATE ON CONDITION (32←16) 2329 op_LOCHI uint32 = 0xEC42 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (32←16) 2330 op_LOCGHI uint32 = 0xEC46 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (64←16) 2331 op_LOCFH uint32 = 0xEBE0 // RSY-b LOAD HIGH ON CONDITION (32) 2332 op_LOCFHR uint32 = 0xB9E0 // RRF-c LOAD HIGH ON CONDITION (32) 2333 op_LLZRGF uint32 = 0xE33A // RXY-a LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64←32) 2334 op_STOCFH uint32 = 0xEBE1 // RSY-b STORE HIGH ON CONDITION 2335 op_VA uint32 = 0xE7F3 // VRR-c VECTOR ADD 2336 op_VACC uint32 = 0xE7F1 // VRR-c VECTOR ADD COMPUTE CARRY 2337 op_VAC uint32 = 0xE7BB // VRR-d VECTOR ADD WITH CARRY 2338 op_VACCC uint32 = 0xE7B9 // VRR-d VECTOR ADD WITH CARRY COMPUTE CARRY 2339 op_VN uint32 = 0xE768 // VRR-c VECTOR AND 2340 op_VNC uint32 = 0xE769 // VRR-c VECTOR AND WITH COMPLEMENT 2341 op_VAVG uint32 = 0xE7F2 // VRR-c VECTOR AVERAGE 2342 op_VAVGL uint32 = 0xE7F0 // VRR-c VECTOR AVERAGE LOGICAL 2343 op_VCKSM uint32 = 0xE766 // VRR-c VECTOR CHECKSUM 2344 op_VCEQ uint32 = 0xE7F8 // VRR-b VECTOR COMPARE EQUAL 2345 op_VCH uint32 = 0xE7FB // VRR-b VECTOR COMPARE HIGH 2346 op_VCHL uint32 = 0xE7F9 // VRR-b VECTOR COMPARE HIGH LOGICAL 2347 op_VCLZ uint32 = 0xE753 // VRR-a VECTOR COUNT LEADING ZEROS 2348 op_VCTZ uint32 = 0xE752 // VRR-a VECTOR COUNT TRAILING ZEROS 2349 op_VEC uint32 = 0xE7DB // VRR-a VECTOR ELEMENT COMPARE 2350 op_VECL uint32 = 0xE7D9 // VRR-a VECTOR ELEMENT COMPARE LOGICAL 2351 op_VERIM uint32 = 0xE772 // VRI-d VECTOR ELEMENT ROTATE AND INSERT UNDER MASK 2352 op_VERLL uint32 = 0xE733 // VRS-a VECTOR ELEMENT ROTATE LEFT LOGICAL 2353 op_VERLLV uint32 = 0xE773 // VRR-c VECTOR ELEMENT ROTATE LEFT LOGICAL 2354 op_VESLV uint32 = 0xE770 // VRR-c VECTOR ELEMENT SHIFT LEFT 2355 op_VESL uint32 = 0xE730 // VRS-a VECTOR ELEMENT SHIFT LEFT 2356 op_VESRA uint32 = 0xE73A // VRS-a VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2357 op_VESRAV uint32 = 0xE77A // VRR-c VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2358 op_VESRL uint32 = 0xE738 // VRS-a VECTOR ELEMENT SHIFT RIGHT LOGICAL 2359 op_VESRLV uint32 = 0xE778 // VRR-c VECTOR ELEMENT SHIFT RIGHT LOGICAL 2360 op_VX uint32 = 0xE76D // VRR-c VECTOR EXCLUSIVE OR 2361 op_VFAE uint32 = 0xE782 // VRR-b VECTOR FIND ANY ELEMENT EQUAL 2362 op_VFEE uint32 = 0xE780 // VRR-b VECTOR FIND ELEMENT EQUAL 2363 op_VFENE uint32 = 0xE781 // VRR-b VECTOR FIND ELEMENT NOT EQUAL 2364 op_VFA uint32 = 0xE7E3 // VRR-c VECTOR FP ADD 2365 op_WFK uint32 = 0xE7CA // VRR-a VECTOR FP COMPARE AND SIGNAL SCALAR 2366 op_VFCE uint32 = 0xE7E8 // VRR-c VECTOR FP COMPARE EQUAL 2367 op_VFCH uint32 = 0xE7EB // VRR-c VECTOR FP COMPARE HIGH 2368 op_VFCHE uint32 = 0xE7EA // VRR-c VECTOR FP COMPARE HIGH OR EQUAL 2369 op_WFC uint32 = 0xE7CB // VRR-a VECTOR FP COMPARE SCALAR 2370 op_VCDG uint32 = 0xE7C3 // VRR-a VECTOR FP CONVERT FROM FIXED 64-BIT 2371 op_VCDLG uint32 = 0xE7C1 // VRR-a VECTOR FP CONVERT FROM LOGICAL 64-BIT 2372 op_VCGD uint32 = 0xE7C2 // VRR-a VECTOR FP CONVERT TO FIXED 64-BIT 2373 op_VCLGD uint32 = 0xE7C0 // VRR-a VECTOR FP CONVERT TO LOGICAL 64-BIT 2374 op_VFD uint32 = 0xE7E5 // VRR-c VECTOR FP DIVIDE 2375 op_VLDE uint32 = 0xE7C4 // VRR-a VECTOR FP LOAD LENGTHENED 2376 op_VLED uint32 = 0xE7C5 // VRR-a VECTOR FP LOAD ROUNDED 2377 op_VFM uint32 = 0xE7E7 // VRR-c VECTOR FP MULTIPLY 2378 op_VFMA uint32 = 0xE78F // VRR-e VECTOR FP MULTIPLY AND ADD 2379 op_VFMS uint32 = 0xE78E // VRR-e VECTOR FP MULTIPLY AND SUBTRACT 2380 op_VFPSO uint32 = 0xE7CC // VRR-a VECTOR FP PERFORM SIGN OPERATION 2381 op_VFSQ uint32 = 0xE7CE // VRR-a VECTOR FP SQUARE ROOT 2382 op_VFS uint32 = 0xE7E2 // VRR-c VECTOR FP SUBTRACT 2383 op_VFTCI uint32 = 0xE74A // VRI-e VECTOR FP TEST DATA CLASS IMMEDIATE 2384 op_VGFM uint32 = 0xE7B4 // VRR-c VECTOR GALOIS FIELD MULTIPLY SUM 2385 op_VGFMA uint32 = 0xE7BC // VRR-d VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE 2386 op_VGEF uint32 = 0xE713 // VRV VECTOR GATHER ELEMENT (32) 2387 op_VGEG uint32 = 0xE712 // VRV VECTOR GATHER ELEMENT (64) 2388 op_VGBM uint32 = 0xE744 // VRI-a VECTOR GENERATE BYTE MASK 2389 op_VGM uint32 = 0xE746 // VRI-b VECTOR GENERATE MASK 2390 op_VISTR uint32 = 0xE75C // VRR-a VECTOR ISOLATE STRING 2391 op_VL uint32 = 0xE706 // VRX VECTOR LOAD 2392 op_VLR uint32 = 0xE756 // VRR-a VECTOR LOAD 2393 op_VLREP uint32 = 0xE705 // VRX VECTOR LOAD AND REPLICATE 2394 op_VLC uint32 = 0xE7DE // VRR-a VECTOR LOAD COMPLEMENT 2395 op_VLEH uint32 = 0xE701 // VRX VECTOR LOAD ELEMENT (16) 2396 op_VLEF uint32 = 0xE703 // VRX VECTOR LOAD ELEMENT (32) 2397 op_VLEG uint32 = 0xE702 // VRX VECTOR LOAD ELEMENT (64) 2398 op_VLEB uint32 = 0xE700 // VRX VECTOR LOAD ELEMENT (8) 2399 op_VLEIH uint32 = 0xE741 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (16) 2400 op_VLEIF uint32 = 0xE743 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (32) 2401 op_VLEIG uint32 = 0xE742 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (64) 2402 op_VLEIB uint32 = 0xE740 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (8) 2403 op_VFI uint32 = 0xE7C7 // VRR-a VECTOR LOAD FP INTEGER 2404 op_VLGV uint32 = 0xE721 // VRS-c VECTOR LOAD GR FROM VR ELEMENT 2405 op_VLLEZ uint32 = 0xE704 // VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO 2406 op_VLM uint32 = 0xE736 // VRS-a VECTOR LOAD MULTIPLE 2407 op_VLP uint32 = 0xE7DF // VRR-a VECTOR LOAD POSITIVE 2408 op_VLBB uint32 = 0xE707 // VRX VECTOR LOAD TO BLOCK BOUNDARY 2409 op_VLVG uint32 = 0xE722 // VRS-b VECTOR LOAD VR ELEMENT FROM GR 2410 op_VLVGP uint32 = 0xE762 // VRR-f VECTOR LOAD VR FROM GRS DISJOINT 2411 op_VLL uint32 = 0xE737 // VRS-b VECTOR LOAD WITH LENGTH 2412 op_VMX uint32 = 0xE7FF // VRR-c VECTOR MAXIMUM 2413 op_VMXL uint32 = 0xE7FD // VRR-c VECTOR MAXIMUM LOGICAL 2414 op_VMRH uint32 = 0xE761 // VRR-c VECTOR MERGE HIGH 2415 op_VMRL uint32 = 0xE760 // VRR-c VECTOR MERGE LOW 2416 op_VMN uint32 = 0xE7FE // VRR-c VECTOR MINIMUM 2417 op_VMNL uint32 = 0xE7FC // VRR-c VECTOR MINIMUM LOGICAL 2418 op_VMAE uint32 = 0xE7AE // VRR-d VECTOR MULTIPLY AND ADD EVEN 2419 op_VMAH uint32 = 0xE7AB // VRR-d VECTOR MULTIPLY AND ADD HIGH 2420 op_VMALE uint32 = 0xE7AC // VRR-d VECTOR MULTIPLY AND ADD LOGICAL EVEN 2421 op_VMALH uint32 = 0xE7A9 // VRR-d VECTOR MULTIPLY AND ADD LOGICAL HIGH 2422 op_VMALO uint32 = 0xE7AD // VRR-d VECTOR MULTIPLY AND ADD LOGICAL ODD 2423 op_VMAL uint32 = 0xE7AA // VRR-d VECTOR MULTIPLY AND ADD LOW 2424 op_VMAO uint32 = 0xE7AF // VRR-d VECTOR MULTIPLY AND ADD ODD 2425 op_VME uint32 = 0xE7A6 // VRR-c VECTOR MULTIPLY EVEN 2426 op_VMH uint32 = 0xE7A3 // VRR-c VECTOR MULTIPLY HIGH 2427 op_VMLE uint32 = 0xE7A4 // VRR-c VECTOR MULTIPLY EVEN LOGICAL 2428 op_VMLH uint32 = 0xE7A1 // VRR-c VECTOR MULTIPLY HIGH LOGICAL 2429 op_VMLO uint32 = 0xE7A5 // VRR-c VECTOR MULTIPLY ODD LOGICAL 2430 op_VML uint32 = 0xE7A2 // VRR-c VECTOR MULTIPLY LOW 2431 op_VMO uint32 = 0xE7A7 // VRR-c VECTOR MULTIPLY ODD 2432 op_VNO uint32 = 0xE76B // VRR-c VECTOR NOR 2433 op_VO uint32 = 0xE76A // VRR-c VECTOR OR 2434 op_VPK uint32 = 0xE794 // VRR-c VECTOR PACK 2435 op_VPKLS uint32 = 0xE795 // VRR-b VECTOR PACK LOGICAL SATURATE 2436 op_VPKS uint32 = 0xE797 // VRR-b VECTOR PACK SATURATE 2437 op_VPERM uint32 = 0xE78C // VRR-e VECTOR PERMUTE 2438 op_VPDI uint32 = 0xE784 // VRR-c VECTOR PERMUTE DOUBLEWORD IMMEDIATE 2439 op_VPOPCT uint32 = 0xE750 // VRR-a VECTOR POPULATION COUNT 2440 op_VREP uint32 = 0xE74D // VRI-c VECTOR REPLICATE 2441 op_VREPI uint32 = 0xE745 // VRI-a VECTOR REPLICATE IMMEDIATE 2442 op_VSCEF uint32 = 0xE71B // VRV VECTOR SCATTER ELEMENT (32) 2443 op_VSCEG uint32 = 0xE71A // VRV VECTOR SCATTER ELEMENT (64) 2444 op_VSEL uint32 = 0xE78D // VRR-e VECTOR SELECT 2445 op_VSL uint32 = 0xE774 // VRR-c VECTOR SHIFT LEFT 2446 op_VSLB uint32 = 0xE775 // VRR-c VECTOR SHIFT LEFT BY BYTE 2447 op_VSLDB uint32 = 0xE777 // VRI-d VECTOR SHIFT LEFT DOUBLE BY BYTE 2448 op_VSRA uint32 = 0xE77E // VRR-c VECTOR SHIFT RIGHT ARITHMETIC 2449 op_VSRAB uint32 = 0xE77F // VRR-c VECTOR SHIFT RIGHT ARITHMETIC BY BYTE 2450 op_VSRL uint32 = 0xE77C // VRR-c VECTOR SHIFT RIGHT LOGICAL 2451 op_VSRLB uint32 = 0xE77D // VRR-c VECTOR SHIFT RIGHT LOGICAL BY BYTE 2452 op_VSEG uint32 = 0xE75F // VRR-a VECTOR SIGN EXTEND TO DOUBLEWORD 2453 op_VST uint32 = 0xE70E // VRX VECTOR STORE 2454 op_VSTEH uint32 = 0xE709 // VRX VECTOR STORE ELEMENT (16) 2455 op_VSTEF uint32 = 0xE70B // VRX VECTOR STORE ELEMENT (32) 2456 op_VSTEG uint32 = 0xE70A // VRX VECTOR STORE ELEMENT (64) 2457 op_VSTEB uint32 = 0xE708 // VRX VECTOR STORE ELEMENT (8) 2458 op_VSTM uint32 = 0xE73E // VRS-a VECTOR STORE MULTIPLE 2459 op_VSTL uint32 = 0xE73F // VRS-b VECTOR STORE WITH LENGTH 2460 op_VSTRC uint32 = 0xE78A // VRR-d VECTOR STRING RANGE COMPARE 2461 op_VS uint32 = 0xE7F7 // VRR-c VECTOR SUBTRACT 2462 op_VSCBI uint32 = 0xE7F5 // VRR-c VECTOR SUBTRACT COMPUTE BORROW INDICATION 2463 op_VSBCBI uint32 = 0xE7BD // VRR-d VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION 2464 op_VSBI uint32 = 0xE7BF // VRR-d VECTOR SUBTRACT WITH BORROW INDICATION 2465 op_VSUMG uint32 = 0xE765 // VRR-c VECTOR SUM ACROSS DOUBLEWORD 2466 op_VSUMQ uint32 = 0xE767 // VRR-c VECTOR SUM ACROSS QUADWORD 2467 op_VSUM uint32 = 0xE764 // VRR-c VECTOR SUM ACROSS WORD 2468 op_VTM uint32 = 0xE7D8 // VRR-a VECTOR TEST UNDER MASK 2469 op_VUPH uint32 = 0xE7D7 // VRR-a VECTOR UNPACK HIGH 2470 op_VUPLH uint32 = 0xE7D5 // VRR-a VECTOR UNPACK LOGICAL HIGH 2471 op_VUPLL uint32 = 0xE7D4 // VRR-a VECTOR UNPACK LOGICAL LOW 2472 op_VUPL uint32 = 0xE7D6 // VRR-a VECTOR UNPACK LOW 2473 ) 2474 2475 func oclass(a *obj.Addr) int { 2476 return int(a.Class) - 1 2477 } 2478 2479 // Add a relocation for the immediate in a RIL style instruction. 2480 // The addend will be adjusted as required. 2481 func addrilreloc(ctxt *obj.Link, sym *obj.LSym, add int64) *obj.Reloc { 2482 if sym == nil { 2483 ctxt.Diag("require symbol to apply relocation") 2484 } 2485 offset := int64(2) // relocation offset from start of instruction 2486 rel := obj.Addrel(ctxt.Cursym) 2487 rel.Off = int32(ctxt.Pc + offset) 2488 rel.Siz = 4 2489 rel.Sym = sym 2490 rel.Add = add + offset + int64(rel.Siz) 2491 rel.Type = obj.R_PCRELDBL 2492 return rel 2493 } 2494 2495 func addrilrelocoffset(ctxt *obj.Link, sym *obj.LSym, add, offset int64) *obj.Reloc { 2496 if sym == nil { 2497 ctxt.Diag("require symbol to apply relocation") 2498 } 2499 offset += int64(2) // relocation offset from start of instruction 2500 rel := obj.Addrel(ctxt.Cursym) 2501 rel.Off = int32(ctxt.Pc + offset) 2502 rel.Siz = 4 2503 rel.Sym = sym 2504 rel.Add = add + offset + int64(rel.Siz) 2505 rel.Type = obj.R_PCRELDBL 2506 return rel 2507 } 2508 2509 // Add a CALL relocation for the immediate in a RIL style instruction. 2510 // The addend will be adjusted as required. 2511 func addcallreloc(ctxt *obj.Link, sym *obj.LSym, add int64) *obj.Reloc { 2512 if sym == nil { 2513 ctxt.Diag("require symbol to apply relocation") 2514 } 2515 offset := int64(2) // relocation offset from start of instruction 2516 rel := obj.Addrel(ctxt.Cursym) 2517 rel.Off = int32(ctxt.Pc + offset) 2518 rel.Siz = 4 2519 rel.Sym = sym 2520 rel.Add = add + offset + int64(rel.Siz) 2521 rel.Type = obj.R_CALL 2522 return rel 2523 } 2524 2525 func branchMask(ctxt *obj.Link, p *obj.Prog) uint32 { 2526 switch p.As { 2527 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ: 2528 return 0x8 2529 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE: 2530 return 0xA 2531 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT: 2532 return 0x2 2533 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE: 2534 return 0xC 2535 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT: 2536 return 0x4 2537 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE: 2538 return 0x7 2539 case ABLEU: // LE or unordered 2540 return 0xD 2541 case ABLTU: // LT or unordered 2542 return 0x5 2543 case ABVC: 2544 return 0x0 // needs extra instruction 2545 case ABVS: 2546 return 0x1 // unordered 2547 } 2548 ctxt.Diag("unknown conditional branch %v", p.As) 2549 return 0xF 2550 } 2551 2552 func asmout(ctxt *obj.Link, asm *[]byte) { 2553 p := ctxt.Curp 2554 o := oplook(ctxt, p) 2555 ctxt.Printp = p 2556 2557 switch o.type_ { 2558 default: 2559 ctxt.Diag("unknown type %d", o.type_) 2560 2561 case 0: // PSEUDO OPS 2562 break 2563 2564 case 1: // mov reg reg 2565 switch p.As { 2566 default: 2567 ctxt.Diag("unhandled operation: %v", p.As) 2568 case AMOVD: 2569 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2570 // sign extend 2571 case AMOVW: 2572 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2573 case AMOVH: 2574 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2575 case AMOVB: 2576 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2577 // zero extend 2578 case AMOVWZ: 2579 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2580 case AMOVHZ: 2581 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2582 case AMOVBZ: 2583 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2584 // reverse bytes 2585 case AMOVDBR: 2586 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2587 case AMOVWBR: 2588 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2589 // floating point 2590 case AFMOVD, AFMOVS: 2591 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2592 } 2593 2594 case 2: // arithmetic op reg [reg] reg 2595 r := p.Reg 2596 if r == 0 { 2597 r = p.To.Reg 2598 } 2599 2600 var opcode uint32 2601 2602 switch p.As { 2603 default: 2604 ctxt.Diag("invalid opcode") 2605 case AADD: 2606 opcode = op_AGRK 2607 case AADDC: 2608 opcode = op_ALGRK 2609 case AADDE: 2610 opcode = op_ALCGR 2611 case AADDW: 2612 opcode = op_ARK 2613 case AMULLW: 2614 opcode = op_MSGFR 2615 case AMULLD: 2616 opcode = op_MSGR 2617 case ADIVW, AMODW: 2618 opcode = op_DSGFR 2619 case ADIVWU, AMODWU: 2620 opcode = op_DLR 2621 case ADIVD, AMODD: 2622 opcode = op_DSGR 2623 case ADIVDU, AMODDU: 2624 opcode = op_DLGR 2625 } 2626 2627 switch p.As { 2628 default: 2629 2630 case AADD, AADDC, AADDW: 2631 if p.As == AADDW && r == p.To.Reg { 2632 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2633 } else { 2634 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2635 } 2636 2637 case AADDE, AMULLW, AMULLD: 2638 if r == p.To.Reg { 2639 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2640 } else if p.From.Reg == p.To.Reg { 2641 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2642 } else { 2643 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2644 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2645 } 2646 2647 case ADIVW, ADIVWU, ADIVD, ADIVDU: 2648 if p.As == ADIVWU || p.As == ADIVDU { 2649 zRI(op_LGHI, REGTMP, 0, asm) 2650 } 2651 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2652 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2653 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm) 2654 2655 case AMODW, AMODWU, AMODD, AMODDU: 2656 if p.As == AMODWU || p.As == AMODDU { 2657 zRI(op_LGHI, REGTMP, 0, asm) 2658 } 2659 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2660 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2661 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2662 2663 } 2664 2665 case 3: // mov $constant reg 2666 v := vregoff(ctxt, &p.From) 2667 switch p.As { 2668 case AMOVBZ: 2669 v = int64(uint8(v)) 2670 case AMOVHZ: 2671 v = int64(uint16(v)) 2672 case AMOVWZ: 2673 v = int64(uint32(v)) 2674 case AMOVB: 2675 v = int64(int8(v)) 2676 case AMOVH: 2677 v = int64(int16(v)) 2678 case AMOVW: 2679 v = int64(int32(v)) 2680 } 2681 if int64(int16(v)) == v { 2682 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm) 2683 } else if v&0xffff0000 == v { 2684 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm) 2685 } else if v&0xffff00000000 == v { 2686 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm) 2687 } else if uint64(v)&0xffff000000000000 == uint64(v) { 2688 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm) 2689 } else if int64(int32(v)) == v { 2690 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm) 2691 } else if int64(uint32(v)) == v { 2692 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2693 } else if uint64(v)&0xffffffff00000000 == uint64(v) { 2694 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2695 } else { 2696 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2697 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2698 } 2699 2700 case 4: // multiply high (a*b)>>64 2701 r := p.Reg 2702 if r == 0 { 2703 r = p.To.Reg 2704 } 2705 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2706 zRRE(op_MLGR, REGTMP, uint32(p.From.Reg), asm) 2707 switch p.As { 2708 case AMULHDU: 2709 // Unsigned: move result into correct register. 2710 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2711 case AMULHD: 2712 // Signed: need to convert result. 2713 // See Hacker's Delight 8-3. 2714 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm) 2715 zRRE(op_NGR, REGTMP2, uint32(r), asm) 2716 zRRE(op_SGR, REGTMP, REGTMP2, asm) 2717 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm) 2718 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm) 2719 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), REGTMP, asm) 2720 } 2721 2722 case 5: // syscall 2723 zI(op_SVC, 0, asm) 2724 2725 case 6: // logical op reg [reg] reg 2726 var oprr, oprre, oprrf uint32 2727 switch p.As { 2728 case AAND: 2729 oprre = op_NGR 2730 oprrf = op_NGRK 2731 case AANDW: 2732 oprr = op_NR 2733 oprrf = op_NRK 2734 case AOR: 2735 oprre = op_OGR 2736 oprrf = op_OGRK 2737 case AORW: 2738 oprr = op_OR 2739 oprrf = op_ORK 2740 case AXOR: 2741 oprre = op_XGR 2742 oprrf = op_XGRK 2743 case AXORW: 2744 oprr = op_XR 2745 oprrf = op_XRK 2746 } 2747 if p.Reg == 0 { 2748 if oprr != 0 { 2749 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2750 } else { 2751 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2752 } 2753 } else { 2754 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2755 } 2756 2757 case 7: // shift/rotate reg [reg] reg 2758 d2 := vregoff(ctxt, &p.From) 2759 b2 := p.From.Reg 2760 r3 := p.Reg 2761 if r3 == 0 { 2762 r3 = p.To.Reg 2763 } 2764 r1 := p.To.Reg 2765 var opcode uint32 2766 switch p.As { 2767 default: 2768 case ASLD: 2769 opcode = op_SLLG 2770 case ASRD: 2771 opcode = op_SRLG 2772 case ASLW: 2773 opcode = op_SLLK 2774 case ASRW: 2775 opcode = op_SRLK 2776 case ARLL: 2777 opcode = op_RLL 2778 case ARLLG: 2779 opcode = op_RLLG 2780 case ASRAW: 2781 opcode = op_SRAK 2782 case ASRAD: 2783 opcode = op_SRAG 2784 } 2785 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm) 2786 2787 case 8: // find leftmost one 2788 if p.To.Reg&1 != 0 { 2789 ctxt.Diag("target must be an even-numbered register") 2790 } 2791 // FLOGR also writes a mask to p.To.Reg+1. 2792 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2793 2794 case 10: // subtract reg [reg] reg 2795 r := int(p.Reg) 2796 2797 switch p.As { 2798 default: 2799 case ASUB: 2800 if r == 0 { 2801 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2802 } else { 2803 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2804 } 2805 case ASUBC: 2806 if r == 0 { 2807 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2808 } else { 2809 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2810 } 2811 case ASUBE: 2812 if r == 0 { 2813 r = int(p.To.Reg) 2814 } 2815 if r == int(p.To.Reg) { 2816 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2817 } else if p.From.Reg == p.To.Reg { 2818 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 2819 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2820 zRRE(op_SLBGR, uint32(p.To.Reg), REGTMP, asm) 2821 } else { 2822 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2823 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2824 } 2825 case ASUBW: 2826 if r == 0 { 2827 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2828 } else { 2829 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2830 } 2831 } 2832 2833 case 11: // br/bl 2834 v := int32(0) 2835 2836 if p.Pcond != nil { 2837 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2838 } 2839 2840 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v { 2841 zRI(op_BRC, 0xF, uint32(v), asm) 2842 } else { 2843 if p.As == ABL { 2844 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm) 2845 } else { 2846 zRIL(_c, op_BRCL, 0xF, uint32(v), asm) 2847 } 2848 if p.To.Sym != nil { 2849 addcallreloc(ctxt, p.To.Sym, p.To.Offset) 2850 } 2851 } 2852 2853 case 12: 2854 r1 := p.To.Reg 2855 d2 := vregoff(ctxt, &p.From) 2856 b2 := p.From.Reg 2857 if b2 == 0 { 2858 b2 = o.param 2859 } 2860 x2 := p.From.Index 2861 if -DISP20/2 > d2 || d2 >= DISP20/2 { 2862 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 2863 if x2 != 0 { 2864 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 2865 } 2866 x2 = REGTMP 2867 d2 = 0 2868 } 2869 var opx, opxy uint32 2870 switch p.As { 2871 case AADD: 2872 opxy = op_AG 2873 case AADDC: 2874 opxy = op_ALG 2875 case AADDW: 2876 opx = op_A 2877 opxy = op_AY 2878 case AMULLW: 2879 opx = op_MS 2880 opxy = op_MSY 2881 case AMULLD: 2882 opxy = op_MSG 2883 case ASUB: 2884 opxy = op_SG 2885 case ASUBC: 2886 opxy = op_SLG 2887 case ASUBE: 2888 opxy = op_SLBG 2889 case ASUBW: 2890 opx = op_S 2891 opxy = op_SY 2892 case AAND: 2893 opxy = op_NG 2894 case AANDW: 2895 opx = op_N 2896 opxy = op_NY 2897 case AOR: 2898 opxy = op_OG 2899 case AORW: 2900 opx = op_O 2901 opxy = op_OY 2902 case AXOR: 2903 opxy = op_XG 2904 case AXORW: 2905 opx = op_X 2906 opxy = op_XY 2907 } 2908 if opx != 0 && 0 <= d2 && d2 < DISP12 { 2909 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 2910 } else { 2911 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 2912 } 2913 2914 case 15: // br/bl (reg) 2915 r := p.To.Reg 2916 if p.As == ABCL || p.As == ABL { 2917 zRR(op_BASR, uint32(REG_LR), uint32(r), asm) 2918 } else { 2919 zRR(op_BCR, 0xF, uint32(r), asm) 2920 } 2921 2922 case 16: // conditional branch 2923 v := int32(0) 2924 if p.Pcond != nil { 2925 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2926 } 2927 mask := branchMask(ctxt, p) 2928 if p.To.Sym == nil && int32(int16(v)) == v { 2929 zRI(op_BRC, mask, uint32(v), asm) 2930 } else { 2931 zRIL(_c, op_BRCL, mask, uint32(v), asm) 2932 } 2933 if p.To.Sym != nil { 2934 addrilreloc(ctxt, p.To.Sym, p.To.Offset) 2935 } 2936 2937 case 17: // move on condition 2938 m3 := branchMask(ctxt, p) 2939 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2940 2941 case 18: // br/bl reg 2942 if p.As == ABL { 2943 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm) 2944 } else { 2945 zRR(op_BCR, 0xF, uint32(p.To.Reg), asm) 2946 } 2947 2948 case 19: // mov $sym+n(SB) reg 2949 d := vregoff(ctxt, &p.From) 2950 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm) 2951 if d&1 != 0 { 2952 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm) 2953 d -= 1 2954 } 2955 addrilreloc(ctxt, p.From.Sym, d) 2956 2957 case 21: // subtract $constant [reg] reg 2958 v := vregoff(ctxt, &p.From) 2959 r := p.Reg 2960 if r == 0 { 2961 r = p.To.Reg 2962 } 2963 switch p.As { 2964 case ASUB: 2965 zRIL(_a, op_LGFI, uint32(REGTMP), uint32(v), asm) 2966 zRRF(op_SLGRK, uint32(REGTMP), 0, uint32(p.To.Reg), uint32(r), asm) 2967 case ASUBC: 2968 if r != p.To.Reg { 2969 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2970 } 2971 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm) 2972 case ASUBW: 2973 if r != p.To.Reg { 2974 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 2975 } 2976 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm) 2977 } 2978 2979 case 22: // add/multiply $constant [reg] reg 2980 v := vregoff(ctxt, &p.From) 2981 r := p.Reg 2982 if r == 0 { 2983 r = p.To.Reg 2984 } 2985 var opri, opril, oprie uint32 2986 switch p.As { 2987 case AADD: 2988 opri = op_AGHI 2989 opril = op_AGFI 2990 oprie = op_AGHIK 2991 case AADDC: 2992 opril = op_ALGFI 2993 oprie = op_ALGHSIK 2994 case AADDW: 2995 opri = op_AHI 2996 opril = op_AFI 2997 oprie = op_AHIK 2998 case AMULLW: 2999 opri = op_MHI 3000 opril = op_MSFI 3001 case AMULLD: 3002 opri = op_MGHI 3003 opril = op_MSGFI 3004 } 3005 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) { 3006 switch p.As { 3007 case AADD, AADDC, AMULLD: 3008 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3009 case AADDW, AMULLW: 3010 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3011 } 3012 r = p.To.Reg 3013 } 3014 if r == p.To.Reg { 3015 if opri != 0 && int64(int16(v)) == v { 3016 zRI(opri, uint32(p.To.Reg), uint32(v), asm) 3017 } else { 3018 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm) 3019 } 3020 } else { 3021 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm) 3022 } 3023 3024 case 23: // 64-bit logical op $constant reg 3025 // TODO(mundaym): merge with case 24. 3026 v := vregoff(ctxt, &p.From) 3027 switch p.As { 3028 default: 3029 ctxt.Diag("%v is not supported", p) 3030 case AAND: 3031 if v >= 0 { // needs zero extend 3032 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3033 zRRE(op_NGR, uint32(p.To.Reg), REGTMP, asm) 3034 } else if int64(int16(v)) == v { 3035 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3036 } else { // r.To.Reg & 0xffffffff00000000 & uint32(v) 3037 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3038 } 3039 case AOR: 3040 if int64(uint32(v)) != v { // needs sign extend 3041 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3042 zRRE(op_OGR, uint32(p.To.Reg), REGTMP, asm) 3043 } else if int64(uint16(v)) == v { 3044 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3045 } else { 3046 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3047 } 3048 case AXOR: 3049 if int64(uint32(v)) != v { // needs sign extend 3050 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3051 zRRE(op_XGR, uint32(p.To.Reg), REGTMP, asm) 3052 } else { 3053 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3054 } 3055 } 3056 3057 case 24: // 32-bit logical op $constant reg 3058 v := vregoff(ctxt, &p.From) 3059 switch p.As { 3060 case AANDW: 3061 if uint32(v&0xffff0000) == 0xffff0000 { 3062 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3063 } else if uint32(v&0x0000ffff) == 0x0000ffff { 3064 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3065 } else { 3066 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3067 } 3068 case AORW: 3069 if uint32(v&0xffff0000) == 0 { 3070 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3071 } else if uint32(v&0x0000ffff) == 0 { 3072 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3073 } else { 3074 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3075 } 3076 case AXORW: 3077 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3078 } 3079 3080 case 26: // MOVD $offset(base)(index), reg 3081 v := regoff(ctxt, &p.From) 3082 r := p.From.Reg 3083 if r == 0 { 3084 r = o.param 3085 } 3086 i := p.From.Index 3087 if v >= 0 && v < DISP12 { 3088 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3089 } else if v >= -DISP20/2 && v < DISP20/2 { 3090 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3091 } else { 3092 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3093 zRX(op_LA, uint32(p.To.Reg), uint32(r), REGTMP, uint32(i), asm) 3094 } 3095 3096 case 31: // dword 3097 wd := uint64(vregoff(ctxt, &p.From)) 3098 *asm = append(*asm, 3099 uint8(wd>>56), 3100 uint8(wd>>48), 3101 uint8(wd>>40), 3102 uint8(wd>>32), 3103 uint8(wd>>24), 3104 uint8(wd>>16), 3105 uint8(wd>>8), 3106 uint8(wd)) 3107 3108 case 32: // float op freg freg 3109 var opcode uint32 3110 switch p.As { 3111 default: 3112 ctxt.Diag("invalid opcode") 3113 case AFADD: 3114 opcode = op_ADBR 3115 case AFADDS: 3116 opcode = op_AEBR 3117 case AFDIV: 3118 opcode = op_DDBR 3119 case AFDIVS: 3120 opcode = op_DEBR 3121 case AFMUL: 3122 opcode = op_MDBR 3123 case AFMULS: 3124 opcode = op_MEEBR 3125 case AFSUB: 3126 opcode = op_SDBR 3127 case AFSUBS: 3128 opcode = op_SEBR 3129 } 3130 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3131 3132 case 33: // float op [freg] freg 3133 r := p.From.Reg 3134 if oclass(&p.From) == C_NONE { 3135 r = p.To.Reg 3136 } 3137 var opcode uint32 3138 switch p.As { 3139 default: 3140 case AFABS: 3141 opcode = op_LPDBR 3142 case AFNABS: 3143 opcode = op_LNDBR 3144 case AFNEG: 3145 opcode = op_LCDFR 3146 case AFNEGS: 3147 opcode = op_LCEBR 3148 case ALEDBR: 3149 opcode = op_LEDBR 3150 case ALDEBR: 3151 opcode = op_LDEBR 3152 case AFSQRT: 3153 opcode = op_SQDBR 3154 case AFSQRTS: 3155 opcode = op_SQEBR 3156 } 3157 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3158 3159 case 34: // float multiply-add freg freg freg 3160 var opcode uint32 3161 switch p.As { 3162 default: 3163 ctxt.Diag("invalid opcode") 3164 case AFMADD: 3165 opcode = op_MADBR 3166 case AFMADDS: 3167 opcode = op_MAEBR 3168 case AFMSUB: 3169 opcode = op_MSDBR 3170 case AFMSUBS: 3171 opcode = op_MSEBR 3172 } 3173 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 3174 3175 case 35: // mov reg mem (no relocation) 3176 d2 := regoff(ctxt, &p.To) 3177 b2 := p.To.Reg 3178 if b2 == 0 { 3179 b2 = o.param 3180 } 3181 x2 := p.To.Index 3182 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3183 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3184 if x2 != 0 { 3185 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3186 } 3187 x2 = REGTMP 3188 d2 = 0 3189 } 3190 zRXY(zopstore(ctxt, p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3191 3192 case 36: // mov mem reg (no relocation) 3193 d2 := regoff(ctxt, &p.From) 3194 b2 := p.From.Reg 3195 if b2 == 0 { 3196 b2 = o.param 3197 } 3198 x2 := p.From.Index 3199 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3200 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3201 if x2 != 0 { 3202 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3203 } 3204 x2 = REGTMP 3205 d2 = 0 3206 } 3207 zRXY(zopload(ctxt, p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3208 3209 case 40: // word/byte 3210 wd := uint32(regoff(ctxt, &p.From)) 3211 if p.As == AWORD { //WORD 3212 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd)) 3213 } else { //BYTE 3214 *asm = append(*asm, uint8(wd)) 3215 } 3216 3217 case 47: // negate [reg] reg 3218 r := p.From.Reg 3219 if r == 0 { 3220 r = p.To.Reg 3221 } 3222 switch p.As { 3223 case ANEG: 3224 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm) 3225 case ANEGW: 3226 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm) 3227 } 3228 3229 case 48: // floating-point round to integer 3230 m3 := vregoff(ctxt, &p.From) 3231 if 0 > m3 || m3 > 7 { 3232 ctxt.Diag("mask (%v) must be in the range [0, 7]", m3) 3233 } 3234 var opcode uint32 3235 switch p.As { 3236 case AFIEBR: 3237 opcode = op_FIEBR 3238 case AFIDBR: 3239 opcode = op_FIDBR 3240 } 3241 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3242 3243 case 67: // fmov $0 freg 3244 var opcode uint32 3245 switch p.As { 3246 case AFMOVS: 3247 opcode = op_LZER 3248 case AFMOVD: 3249 opcode = op_LZDR 3250 } 3251 zRRE(opcode, uint32(p.To.Reg), 0, asm) 3252 3253 case 68: // movw areg reg 3254 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm) 3255 3256 case 69: // movw reg areg 3257 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm) 3258 3259 case 70: // cmp reg reg 3260 if p.As == ACMPW || p.As == ACMPWU { 3261 zRR(zoprr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3262 } else { 3263 zRRE(zoprre(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3264 } 3265 3266 case 71: // cmp reg $constant 3267 v := vregoff(ctxt, &p.To) 3268 switch p.As { 3269 case ACMP, ACMPW: 3270 if int64(int32(v)) != v { 3271 ctxt.Diag("%v overflows an int32", v) 3272 } 3273 case ACMPU, ACMPWU: 3274 if int64(uint32(v)) != v { 3275 ctxt.Diag("%v overflows a uint32", v) 3276 } 3277 } 3278 if p.As == ACMP && int64(int16(v)) == v { 3279 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm) 3280 } else if p.As == ACMPW && int64(int16(v)) == v { 3281 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm) 3282 } else { 3283 zRIL(_a, zopril(ctxt, p.As), uint32(p.From.Reg), uint32(v), asm) 3284 } 3285 3286 case 72: // mov $constant mem 3287 v := regoff(ctxt, &p.From) 3288 d := regoff(ctxt, &p.To) 3289 r := p.To.Reg 3290 x := p.To.Index 3291 if r == 0 { 3292 r = o.param 3293 } 3294 if int32(int16(v)) == v && x == 0 { 3295 if d < 0 || d >= DISP12 { 3296 if r == REGTMP || r == REGTMP2 { 3297 zRIL(_a, op_AGFI, uint32(r), uint32(d), asm) 3298 } else { 3299 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm) 3300 zRRE(op_AGR, REGTMP, uint32(r), asm) 3301 r = REGTMP 3302 } 3303 d = 0 3304 } 3305 var opcode uint32 3306 switch p.As { 3307 case AMOVD: 3308 opcode = op_MVGHI 3309 case AMOVW, AMOVWZ: 3310 opcode = op_MVHI 3311 case AMOVH, AMOVHZ: 3312 opcode = op_MVHHI 3313 case AMOVB, AMOVBZ: 3314 opcode = op_MVI 3315 } 3316 if opcode == op_MVI { 3317 zSI(opcode, uint32(v), uint32(r), uint32(d), asm) 3318 } else { 3319 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm) 3320 } 3321 } else { 3322 zRIL(_a, op_LGFI, REGTMP2, uint32(v), asm) 3323 if d < -DISP20/2 || d >= DISP20/2 { 3324 if r == REGTMP { 3325 zRIL(_a, op_AGFI, REGTMP, uint32(d), asm) 3326 } else { 3327 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm) 3328 if x != 0 { 3329 zRRE(op_AGR, REGTMP, uint32(x), asm) 3330 } 3331 x = REGTMP 3332 } 3333 d = 0 3334 } 3335 zRXY(zopstore(ctxt, p.As), REGTMP2, uint32(x), uint32(r), uint32(d), asm) 3336 } 3337 3338 case 73: // mov $constant addr (including relocation) 3339 v := regoff(ctxt, &p.From) 3340 d := regoff(ctxt, &p.To) 3341 a := uint32(0) 3342 if d&1 != 0 { 3343 d -= 1 3344 a = 1 3345 } 3346 zRIL(_b, op_LARL, REGTMP, uint32(d), asm) 3347 addrilreloc(ctxt, p.To.Sym, int64(d)) 3348 if int32(int16(v)) == v { 3349 var opcode uint32 3350 switch p.As { 3351 case AMOVD: 3352 opcode = op_MVGHI 3353 case AMOVW, AMOVWZ: 3354 opcode = op_MVHI 3355 case AMOVH, AMOVHZ: 3356 opcode = op_MVHHI 3357 case AMOVB, AMOVBZ: 3358 opcode = op_MVI 3359 } 3360 if opcode == op_MVI { 3361 zSI(opcode, uint32(v), REGTMP, a, asm) 3362 } else { 3363 zSIL(opcode, REGTMP, a, uint32(v), asm) 3364 } 3365 } else { 3366 zRIL(_a, op_LGFI, REGTMP2, uint32(v), asm) 3367 zRXY(zopstore(ctxt, p.As), REGTMP2, 0, REGTMP, a, asm) 3368 } 3369 3370 case 74: // mov reg addr (including relocation) 3371 i2 := regoff(ctxt, &p.To) 3372 switch p.As { 3373 case AMOVD: 3374 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm) 3375 case AMOVW, AMOVWZ: // The zero extension doesn't affect store instructions 3376 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm) 3377 case AMOVH, AMOVHZ: // The zero extension doesn't affect store instructions 3378 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm) 3379 case AMOVB, AMOVBZ: // The zero extension doesn't affect store instructions 3380 zRIL(_b, op_LARL, REGTMP, 0, asm) 3381 adj := uint32(0) // adjustment needed for odd addresses 3382 if i2&1 != 0 { 3383 i2 -= 1 3384 adj = 1 3385 } 3386 zRX(op_STC, uint32(p.From.Reg), 0, REGTMP, adj, asm) 3387 case AFMOVD: 3388 zRIL(_b, op_LARL, REGTMP, 0, asm) 3389 zRX(op_STD, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3390 case AFMOVS: 3391 zRIL(_b, op_LARL, REGTMP, 0, asm) 3392 zRX(op_STE, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3393 } 3394 addrilreloc(ctxt, p.To.Sym, int64(i2)) 3395 3396 case 75: // mov addr reg (including relocation) 3397 i2 := regoff(ctxt, &p.From) 3398 switch p.As { 3399 case AMOVD: 3400 if i2&1 != 0 { 3401 zRIL(_b, op_LARL, REGTMP, 0, asm) 3402 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 1, asm) 3403 i2 -= 1 3404 } else { 3405 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3406 } 3407 case AMOVW: 3408 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm) 3409 case AMOVWZ: 3410 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm) 3411 case AMOVH: 3412 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm) 3413 case AMOVHZ: 3414 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm) 3415 case AMOVB, AMOVBZ: 3416 zRIL(_b, op_LARL, REGTMP, 0, asm) 3417 adj := uint32(0) // adjustment needed for odd addresses 3418 if i2&1 != 0 { 3419 i2 -= 1 3420 adj = 1 3421 } 3422 switch p.As { 3423 case AMOVB: 3424 zRXY(op_LGB, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3425 case AMOVBZ: 3426 zRXY(op_LLGC, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3427 } 3428 case AFMOVD: 3429 zRIL(_a, op_LARL, REGTMP, 0, asm) 3430 zRX(op_LD, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3431 case AFMOVS: 3432 zRIL(_a, op_LARL, REGTMP, 0, asm) 3433 zRX(op_LE, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3434 } 3435 addrilreloc(ctxt, p.From.Sym, int64(i2)) 3436 3437 case 77: // syscall $constant 3438 if p.From.Offset > 255 || p.From.Offset < 1 { 3439 ctxt.Diag("illegal system call; system call number out of range: %v", p) 3440 zE(op_TRAP2, asm) // trap always 3441 } else { 3442 zI(op_SVC, uint32(p.From.Offset), asm) 3443 } 3444 3445 case 78: // undef 3446 // "An instruction consisting entirely of binary 0s is guaranteed 3447 // always to be an illegal instruction." 3448 *asm = append(*asm, 0, 0, 0, 0) 3449 3450 case 79: // compare and swap reg reg reg 3451 v := regoff(ctxt, &p.To) 3452 if v < 0 { 3453 v = 0 3454 } 3455 if p.As == ACS { 3456 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3457 } else if p.As == ACSG { 3458 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3459 } 3460 3461 case 81: // sync 3462 zRR(op_BCR, 0xE, 0, asm) 3463 3464 case 82: // fixed to float conversion 3465 var opcode uint32 3466 switch p.As { 3467 default: 3468 log.Fatalf("unexpected opcode %v", p.As) 3469 case ACEFBRA: 3470 opcode = op_CEFBRA 3471 case ACDFBRA: 3472 opcode = op_CDFBRA 3473 case ACEGBRA: 3474 opcode = op_CEGBRA 3475 case ACDGBRA: 3476 opcode = op_CDGBRA 3477 case ACELFBR: 3478 opcode = op_CELFBR 3479 case ACDLFBR: 3480 opcode = op_CDLFBR 3481 case ACELGBR: 3482 opcode = op_CELGBR 3483 case ACDLGBR: 3484 opcode = op_CDLGBR 3485 } 3486 // set immediate operand M3 to 0 to use the default BFP rounding mode 3487 // (usually round to nearest, ties to even) 3488 // TODO(mundaym): should this be fixed at round to nearest, ties to even? 3489 // M4 is reserved and must be 0 3490 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3491 3492 case 83: // float to fixed conversion 3493 var opcode uint32 3494 switch p.As { 3495 default: 3496 log.Fatalf("unexpected opcode %v", p.As) 3497 case ACFEBRA: 3498 opcode = op_CFEBRA 3499 case ACFDBRA: 3500 opcode = op_CFDBRA 3501 case ACGEBRA: 3502 opcode = op_CGEBRA 3503 case ACGDBRA: 3504 opcode = op_CGDBRA 3505 case ACLFEBR: 3506 opcode = op_CLFEBR 3507 case ACLFDBR: 3508 opcode = op_CLFDBR 3509 case ACLGEBR: 3510 opcode = op_CLGEBR 3511 case ACLGDBR: 3512 opcode = op_CLGDBR 3513 } 3514 // set immediate operand M3 to 5 for rounding toward zero (required by Go spec) 3515 // M4 is reserved and must be 0 3516 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3517 3518 case 84: // storage-and-storage operations $length mem mem (length in From3) 3519 l := regoff(ctxt, p.From3) 3520 if l < 1 || l > 256 { 3521 ctxt.Diag("number of bytes (%v) not in range [1,256]", l) 3522 } 3523 if p.From.Index != 0 || p.To.Index != 0 { 3524 ctxt.Diag("cannot use index reg") 3525 } 3526 b1 := p.To.Reg 3527 b2 := p.From.Reg 3528 if b1 == 0 { 3529 b1 = o.param 3530 } 3531 if b2 == 0 { 3532 b2 = o.param 3533 } 3534 d1 := regoff(ctxt, &p.To) 3535 d2 := regoff(ctxt, &p.From) 3536 if d1 < 0 || d1 >= DISP12 { 3537 if b2 == REGTMP { 3538 ctxt.Diag("REGTMP conflict") 3539 } 3540 if b1 != REGTMP { 3541 zRRE(op_LGR, REGTMP, uint32(b1), asm) 3542 } 3543 zRIL(_a, op_AGFI, REGTMP, uint32(d1), asm) 3544 if d1 == d2 && b1 == b2 { 3545 d2 = 0 3546 b2 = REGTMP 3547 } 3548 d1 = 0 3549 b1 = REGTMP 3550 } 3551 if d2 < 0 || d2 >= DISP12 { 3552 if b1 == REGTMP2 { 3553 ctxt.Diag("REGTMP2 conflict") 3554 } 3555 if b2 != REGTMP2 { 3556 zRRE(op_LGR, REGTMP2, uint32(b2), asm) 3557 } 3558 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm) 3559 d2 = 0 3560 b2 = REGTMP2 3561 } 3562 var opcode uint32 3563 switch p.As { 3564 default: 3565 ctxt.Diag("unexpected opcode %v", p.As) 3566 case AMVC: 3567 opcode = op_MVC 3568 case ACLC: 3569 opcode = op_CLC 3570 // swap operand order for CLC so that it matches CMP 3571 b1, b2 = b2, b1 3572 d1, d2 = d2, d1 3573 case AXC: 3574 opcode = op_XC 3575 case AOC: 3576 opcode = op_OC 3577 case ANC: 3578 opcode = op_NC 3579 } 3580 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm) 3581 3582 case 85: // load address relative long 3583 v := regoff(ctxt, &p.From) 3584 if p.From.Sym == nil { 3585 if (v & 1) != 0 { 3586 ctxt.Diag("cannot use LARL with odd offset: %v", v) 3587 } 3588 } else { 3589 addrilreloc(ctxt, p.From.Sym, int64(v)) 3590 v = 0 3591 } 3592 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm) 3593 3594 case 86: // load address 3595 d := vregoff(ctxt, &p.From) 3596 x := p.From.Index 3597 b := p.From.Reg 3598 if b == 0 { 3599 b = o.param 3600 } 3601 switch p.As { 3602 case ALA: 3603 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3604 case ALAY: 3605 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3606 } 3607 3608 case 87: // execute relative long 3609 v := vregoff(ctxt, &p.From) 3610 if p.From.Sym == nil { 3611 if v&1 != 0 { 3612 ctxt.Diag("cannot use EXRL with odd offset: %v", v) 3613 } 3614 } else { 3615 addrilreloc(ctxt, p.From.Sym, v) 3616 v = 0 3617 } 3618 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm) 3619 3620 case 88: // store clock 3621 var opcode uint32 3622 switch p.As { 3623 case ASTCK: 3624 opcode = op_STCK 3625 case ASTCKC: 3626 opcode = op_STCKC 3627 case ASTCKE: 3628 opcode = op_STCKE 3629 case ASTCKF: 3630 opcode = op_STCKF 3631 } 3632 v := vregoff(ctxt, &p.To) 3633 r := int(p.To.Reg) 3634 if r == 0 { 3635 r = int(o.param) 3636 } 3637 zS(opcode, uint32(r), uint32(v), asm) 3638 3639 case 89: // compare and branch reg reg 3640 var v int32 3641 if p.Pcond != nil { 3642 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3643 } 3644 var opcode, opcode2 uint32 3645 switch p.As { 3646 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3647 opcode = op_CGRJ 3648 opcode2 = op_CGR 3649 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3650 opcode = op_CLGRJ 3651 opcode2 = op_CLGR 3652 } 3653 mask := branchMask(ctxt, p) 3654 if int32(int16(v)) != v { 3655 zRRE(opcode2, uint32(p.From.Reg), uint32(p.Reg), asm) 3656 zRIL(_c, op_BRCL, mask, uint32(v-sizeRRE/2), asm) 3657 } else { 3658 zRIE(_b, opcode, uint32(p.From.Reg), uint32(p.Reg), uint32(v), 0, 0, mask, 0, asm) 3659 } 3660 3661 case 90: // compare and branch reg $constant 3662 var v int32 3663 if p.Pcond != nil { 3664 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3665 } 3666 var opcode, opcode2 uint32 3667 switch p.As { 3668 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3669 opcode = op_CGIJ 3670 opcode2 = op_CGFI 3671 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3672 opcode = op_CLGIJ 3673 opcode2 = op_CLGFI 3674 } 3675 mask := branchMask(ctxt, p) 3676 if int32(int16(v)) != v { 3677 zRIL(_a, opcode2, uint32(p.From.Reg), uint32(regoff(ctxt, p.From3)), asm) 3678 zRIL(_c, op_BRCL, mask, uint32(v-sizeRIL/2), asm) 3679 } else { 3680 zRIE(_c, opcode, uint32(p.From.Reg), mask, uint32(v), 0, 0, 0, uint32(regoff(ctxt, p.From3)), asm) 3681 } 3682 3683 case 93: // GOT lookup 3684 v := vregoff(ctxt, &p.To) 3685 if v != 0 { 3686 ctxt.Diag("invalid offset against GOT slot %v", p) 3687 } 3688 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3689 rel := obj.Addrel(ctxt.Cursym) 3690 rel.Off = int32(ctxt.Pc + 2) 3691 rel.Siz = 4 3692 rel.Sym = p.From.Sym 3693 rel.Type = obj.R_GOTPCREL 3694 rel.Add = 2 + int64(rel.Siz) 3695 3696 case 94: // TLS local exec model 3697 zRIL(_b, op_LARL, REGTMP, (sizeRIL+sizeRXY+sizeRI)>>1, asm) 3698 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3699 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm) 3700 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0) 3701 rel := obj.Addrel(ctxt.Cursym) 3702 rel.Off = int32(ctxt.Pc + sizeRIL + sizeRXY + sizeRI) 3703 rel.Siz = 8 3704 rel.Sym = p.From.Sym 3705 rel.Type = obj.R_TLS_LE 3706 rel.Add = 0 3707 3708 case 95: // TLS initial exec model 3709 // Assembly | Relocation symbol | Done Here? 3710 // -------------------------------------------------------------- 3711 // ear %r11, %a0 | | 3712 // sllg %r11, %r11, 32 | | 3713 // ear %r11, %a1 | | 3714 // larl %r10, <var>@indntpoff | R_390_TLS_IEENT | Y 3715 // lg %r10, 0(%r10) | R_390_TLS_LOAD (tag) | Y 3716 // la %r10, 0(%r10, %r11) | | 3717 // -------------------------------------------------------------- 3718 3719 // R_390_TLS_IEENT 3720 zRIL(_b, op_LARL, REGTMP, 0, asm) 3721 ieent := obj.Addrel(ctxt.Cursym) 3722 ieent.Off = int32(ctxt.Pc + 2) 3723 ieent.Siz = 4 3724 ieent.Sym = p.From.Sym 3725 ieent.Type = obj.R_TLS_IE 3726 ieent.Add = 2 + int64(ieent.Siz) 3727 3728 // R_390_TLS_LOAD 3729 zRXY(op_LGF, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3730 // TODO(mundaym): add R_390_TLS_LOAD relocation here 3731 // not strictly required but might allow the linker to optimize 3732 3733 case 96: // clear macro 3734 length := vregoff(ctxt, &p.From) 3735 offset := vregoff(ctxt, &p.To) 3736 reg := p.To.Reg 3737 if reg == 0 { 3738 reg = o.param 3739 } 3740 if length <= 0 { 3741 ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length) 3742 } 3743 for length > 0 { 3744 if offset < 0 || offset >= DISP12 { 3745 if offset >= -DISP20/2 && offset < DISP20/2 { 3746 zRXY(op_LAY, REGTMP, uint32(reg), 0, uint32(offset), asm) 3747 } else { 3748 if reg != REGTMP { 3749 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3750 } 3751 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3752 } 3753 reg = REGTMP 3754 offset = 0 3755 } 3756 size := length 3757 if size > 256 { 3758 size = 256 3759 } 3760 3761 switch size { 3762 case 1: 3763 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm) 3764 case 2: 3765 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm) 3766 case 4: 3767 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm) 3768 case 8: 3769 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm) 3770 default: 3771 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm) 3772 } 3773 3774 length -= size 3775 offset += size 3776 } 3777 3778 case 97: // store multiple 3779 rstart := p.From.Reg 3780 rend := p.Reg 3781 offset := regoff(ctxt, &p.To) 3782 reg := p.To.Reg 3783 if reg == 0 { 3784 reg = o.param 3785 } 3786 if offset < -DISP20/2 || offset >= DISP20/2 { 3787 if reg != REGTMP { 3788 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3789 } 3790 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3791 reg = REGTMP 3792 offset = 0 3793 } 3794 switch p.As { 3795 case ASTMY: 3796 if offset >= 0 && offset < DISP12 { 3797 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3798 } else { 3799 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3800 } 3801 case ASTMG: 3802 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3803 } 3804 3805 case 98: // load multiple 3806 rstart := p.Reg 3807 rend := p.To.Reg 3808 offset := regoff(ctxt, &p.From) 3809 reg := p.From.Reg 3810 if reg == 0 { 3811 reg = o.param 3812 } 3813 if offset < -DISP20/2 || offset >= DISP20/2 { 3814 if reg != REGTMP { 3815 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3816 } 3817 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3818 reg = REGTMP 3819 offset = 0 3820 } 3821 switch p.As { 3822 case ALMY: 3823 if offset >= 0 && offset < DISP12 { 3824 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3825 } else { 3826 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3827 } 3828 case ALMG: 3829 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3830 } 3831 3832 case 99: // interlocked load and op 3833 if p.To.Index != 0 { 3834 ctxt.Diag("cannot use indexed address") 3835 } 3836 offset := regoff(ctxt, &p.To) 3837 if offset < -DISP20/2 || offset >= DISP20/2 { 3838 ctxt.Diag("%v does not fit into 20-bit signed integer", offset) 3839 } 3840 var opcode uint32 3841 switch p.As { 3842 case ALAA: 3843 opcode = op_LAA 3844 case ALAAG: 3845 opcode = op_LAAG 3846 case ALAAL: 3847 opcode = op_LAAL 3848 case ALAALG: 3849 opcode = op_LAALG 3850 case ALAN: 3851 opcode = op_LAN 3852 case ALANG: 3853 opcode = op_LANG 3854 case ALAX: 3855 opcode = op_LAX 3856 case ALAXG: 3857 opcode = op_LAXG 3858 case ALAO: 3859 opcode = op_LAO 3860 case ALAOG: 3861 opcode = op_LAOG 3862 } 3863 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm) 3864 3865 case 100: // VRX STORE 3866 op, m3, _ := vop(p.As) 3867 if p.From3 != nil { 3868 m3 = uint32(vregoff(ctxt, p.From3)) 3869 } 3870 b2 := p.To.Reg 3871 if b2 == 0 { 3872 b2 = o.param 3873 } 3874 d2 := uint32(vregoff(ctxt, &p.To)) 3875 zVRX(op, uint32(p.From.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3876 3877 case 101: // VRX LOAD 3878 op, m3, _ := vop(p.As) 3879 if p.From3 != nil { 3880 m3 = uint32(vregoff(ctxt, p.From3)) 3881 } 3882 b2 := p.From.Reg 3883 if b2 == 0 { 3884 b2 = o.param 3885 } 3886 d2 := uint32(vregoff(ctxt, &p.From)) 3887 zVRX(op, uint32(p.To.Reg), uint32(p.From.Index), uint32(b2), d2, m3, asm) 3888 3889 case 102: // VRV SCATTER 3890 op, m3, _ := vop(p.As) 3891 if p.From3 != nil { 3892 m3 = uint32(vregoff(ctxt, p.From3)) 3893 } 3894 b2 := p.To.Reg 3895 if b2 == 0 { 3896 b2 = o.param 3897 } 3898 d2 := uint32(vregoff(ctxt, &p.To)) 3899 zVRV(op, uint32(p.From.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3900 3901 case 103: // VRV GATHER 3902 op, m3, _ := vop(p.As) 3903 if p.From3 != nil { 3904 m3 = uint32(vregoff(ctxt, p.From3)) 3905 } 3906 b2 := p.From.Reg 3907 if b2 == 0 { 3908 b2 = o.param 3909 } 3910 d2 := uint32(vregoff(ctxt, &p.From)) 3911 zVRV(op, uint32(p.To.Reg), uint32(p.From.Index), uint32(b2), d2, m3, asm) 3912 3913 case 104: // VRS SHIFT/ROTATE and LOAD GR FROM VR ELEMENT 3914 op, m4, _ := vop(p.As) 3915 fr := p.Reg 3916 if fr == 0 { 3917 fr = p.To.Reg 3918 } 3919 bits := uint32(vregoff(ctxt, &p.From)) 3920 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm) 3921 3922 case 105: // VRS STORE MULTIPLE 3923 op, _, _ := vop(p.As) 3924 offset := uint32(vregoff(ctxt, &p.To)) 3925 reg := p.To.Reg 3926 if reg == 0 { 3927 reg = o.param 3928 } 3929 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm) 3930 3931 case 106: // VRS LOAD MULTIPLE 3932 op, _, _ := vop(p.As) 3933 offset := uint32(vregoff(ctxt, &p.From)) 3934 reg := p.From.Reg 3935 if reg == 0 { 3936 reg = o.param 3937 } 3938 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm) 3939 3940 case 107: // VRS STORE WITH LENGTH 3941 op, _, _ := vop(p.As) 3942 offset := uint32(vregoff(ctxt, &p.To)) 3943 reg := p.To.Reg 3944 if reg == 0 { 3945 reg = o.param 3946 } 3947 zVRS(op, uint32(p.From.Reg), uint32(p.From3.Reg), uint32(reg), offset, 0, asm) 3948 3949 case 108: // VRS LOAD WITH LENGTH 3950 op, _, _ := vop(p.As) 3951 offset := uint32(vregoff(ctxt, &p.From)) 3952 reg := p.From.Reg 3953 if reg == 0 { 3954 reg = o.param 3955 } 3956 zVRS(op, uint32(p.To.Reg), uint32(p.From3.Reg), uint32(reg), offset, 0, asm) 3957 3958 case 109: // VRI-a 3959 op, m3, _ := vop(p.As) 3960 i2 := uint32(vregoff(ctxt, &p.From)) 3961 switch p.As { 3962 case AVZERO: 3963 i2 = 0 3964 case AVONE: 3965 i2 = 0xffff 3966 } 3967 if p.From3 != nil { 3968 m3 = uint32(vregoff(ctxt, p.From3)) 3969 } 3970 zVRIa(op, uint32(p.To.Reg), i2, m3, asm) 3971 3972 case 110: 3973 op, m4, _ := vop(p.As) 3974 i2 := uint32(vregoff(ctxt, p.From3)) 3975 i3 := uint32(vregoff(ctxt, &p.From)) 3976 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm) 3977 3978 case 111: 3979 op, m4, _ := vop(p.As) 3980 i2 := uint32(vregoff(ctxt, &p.From)) 3981 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm) 3982 3983 case 112: 3984 op, m5, _ := vop(p.As) 3985 i4 := uint32(vregoff(ctxt, p.From3)) 3986 zVRId(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), i4, m5, asm) 3987 3988 case 113: 3989 op, m4, _ := vop(p.As) 3990 m5 := singleElementMask(p.As) 3991 i3 := uint32(vregoff(ctxt, &p.From)) 3992 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm) 3993 3994 case 114: // VRR-a 3995 op, m3, m5 := vop(p.As) 3996 m4 := singleElementMask(p.As) 3997 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm) 3998 3999 case 115: // VRR-a COMPARE 4000 op, m3, m5 := vop(p.As) 4001 m4 := singleElementMask(p.As) 4002 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm) 4003 4004 case 116: // VRR-a 4005 4006 case 117: // VRR-b 4007 op, m4, m5 := vop(p.As) 4008 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm) 4009 4010 case 118: // VRR-c 4011 op, m4, m6 := vop(p.As) 4012 m5 := singleElementMask(p.As) 4013 v3 := p.Reg 4014 if v3 == 0 { 4015 v3 = p.To.Reg 4016 } 4017 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm) 4018 4019 case 119: // VRR-c SHIFT/ROTATE/DIVIDE/SUB (rhs value on the left, like SLD, DIV etc.) 4020 op, m4, m6 := vop(p.As) 4021 m5 := singleElementMask(p.As) 4022 v2 := p.Reg 4023 if v2 == 0 { 4024 v2 = p.To.Reg 4025 } 4026 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm) 4027 4028 case 120: // VRR-d 4029 op, m6, _ := vop(p.As) 4030 m5 := singleElementMask(p.As) 4031 v1 := uint32(p.To.Reg) 4032 v2 := uint32(p.From3.Reg) 4033 v3 := uint32(p.From.Reg) 4034 v4 := uint32(p.Reg) 4035 zVRRd(op, v1, v2, v3, m6, m5, v4, asm) 4036 4037 case 121: // VRR-e 4038 op, m6, _ := vop(p.As) 4039 m5 := singleElementMask(p.As) 4040 v1 := uint32(p.To.Reg) 4041 v2 := uint32(p.From3.Reg) 4042 v3 := uint32(p.From.Reg) 4043 v4 := uint32(p.Reg) 4044 zVRRe(op, v1, v2, v3, m6, m5, v4, asm) 4045 4046 case 122: // VRR-f LOAD VRS FROM GRS DISJOINT 4047 op, _, _ := vop(p.As) 4048 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 4049 4050 case 123: // VPDI $m4, V2, V3, V1 4051 op, _, _ := vop(p.As) 4052 m4 := regoff(ctxt, p.From3) 4053 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), 0, 0, uint32(m4), asm) 4054 } 4055 } 4056 4057 func vregoff(ctxt *obj.Link, a *obj.Addr) int64 { 4058 ctxt.Instoffset = 0 4059 if a != nil { 4060 aclass(ctxt, a) 4061 } 4062 return ctxt.Instoffset 4063 } 4064 4065 func regoff(ctxt *obj.Link, a *obj.Addr) int32 { 4066 return int32(vregoff(ctxt, a)) 4067 } 4068 4069 // zopload returns the RXY op for the given load 4070 func zopload(ctxt *obj.Link, a obj.As) uint32 { 4071 switch a { 4072 // fixed point load 4073 case AMOVD: 4074 return op_LG 4075 case AMOVW: 4076 return op_LGF 4077 case AMOVWZ: 4078 return op_LLGF 4079 case AMOVH: 4080 return op_LGH 4081 case AMOVHZ: 4082 return op_LLGH 4083 case AMOVB: 4084 return op_LGB 4085 case AMOVBZ: 4086 return op_LLGC 4087 4088 // floating point load 4089 case AFMOVD: 4090 return op_LDY 4091 case AFMOVS: 4092 return op_LEY 4093 4094 // byte reversed load 4095 case AMOVDBR: 4096 return op_LRVG 4097 case AMOVWBR: 4098 return op_LRV 4099 case AMOVHBR: 4100 return op_LRVH 4101 } 4102 4103 ctxt.Diag("unknown store opcode %v", a) 4104 return 0 4105 } 4106 4107 // zopstore returns the RXY op for the given store 4108 func zopstore(ctxt *obj.Link, a obj.As) uint32 { 4109 switch a { 4110 // fixed point store 4111 case AMOVD: 4112 return op_STG 4113 case AMOVW, AMOVWZ: 4114 return op_STY 4115 case AMOVH, AMOVHZ: 4116 return op_STHY 4117 case AMOVB, AMOVBZ: 4118 return op_STCY 4119 4120 // floating point store 4121 case AFMOVD: 4122 return op_STDY 4123 case AFMOVS: 4124 return op_STEY 4125 4126 // byte reversed store 4127 case AMOVDBR: 4128 return op_STRVG 4129 case AMOVWBR: 4130 return op_STRV 4131 case AMOVHBR: 4132 return op_STRVH 4133 } 4134 4135 ctxt.Diag("unknown store opcode %v", a) 4136 return 0 4137 } 4138 4139 // zoprre returns the RRE op for the given a 4140 func zoprre(ctxt *obj.Link, a obj.As) uint32 { 4141 switch a { 4142 case ACMP: 4143 return op_CGR 4144 case ACMPU: 4145 return op_CLGR 4146 case AFCMPO: //ordered 4147 return op_KDBR 4148 case AFCMPU: //unordered 4149 return op_CDBR 4150 case ACEBR: 4151 return op_CEBR 4152 } 4153 ctxt.Diag("unknown rre opcode %v", a) 4154 return 0 4155 } 4156 4157 // zoprr returns the RR op for the given a 4158 func zoprr(ctxt *obj.Link, a obj.As) uint32 { 4159 switch a { 4160 case ACMPW: 4161 return op_CR 4162 case ACMPWU: 4163 return op_CLR 4164 } 4165 ctxt.Diag("unknown rr opcode %v", a) 4166 return 0 4167 } 4168 4169 // zopril returns the RIL op for the given a 4170 func zopril(ctxt *obj.Link, a obj.As) uint32 { 4171 switch a { 4172 case ACMP: 4173 return op_CGFI 4174 case ACMPU: 4175 return op_CLGFI 4176 case ACMPW: 4177 return op_CFI 4178 case ACMPWU: 4179 return op_CLFI 4180 } 4181 ctxt.Diag("unknown ril opcode %v", a) 4182 return 0 4183 } 4184 4185 // z instructions sizes 4186 const ( 4187 sizeE = 2 4188 sizeI = 2 4189 sizeIE = 4 4190 sizeMII = 6 4191 sizeRI = 4 4192 sizeRI1 = 4 4193 sizeRI2 = 4 4194 sizeRI3 = 4 4195 sizeRIE = 6 4196 sizeRIE1 = 6 4197 sizeRIE2 = 6 4198 sizeRIE3 = 6 4199 sizeRIE4 = 6 4200 sizeRIE5 = 6 4201 sizeRIE6 = 6 4202 sizeRIL = 6 4203 sizeRIL1 = 6 4204 sizeRIL2 = 6 4205 sizeRIL3 = 6 4206 sizeRIS = 6 4207 sizeRR = 2 4208 sizeRRD = 4 4209 sizeRRE = 4 4210 sizeRRF = 4 4211 sizeRRF1 = 4 4212 sizeRRF2 = 4 4213 sizeRRF3 = 4 4214 sizeRRF4 = 4 4215 sizeRRF5 = 4 4216 sizeRRR = 2 4217 sizeRRS = 6 4218 sizeRS = 4 4219 sizeRS1 = 4 4220 sizeRS2 = 4 4221 sizeRSI = 4 4222 sizeRSL = 6 4223 sizeRSY = 6 4224 sizeRSY1 = 6 4225 sizeRSY2 = 6 4226 sizeRX = 4 4227 sizeRX1 = 4 4228 sizeRX2 = 4 4229 sizeRXE = 6 4230 sizeRXF = 6 4231 sizeRXY = 6 4232 sizeRXY1 = 6 4233 sizeRXY2 = 6 4234 sizeS = 4 4235 sizeSI = 4 4236 sizeSIL = 6 4237 sizeSIY = 6 4238 sizeSMI = 6 4239 sizeSS = 6 4240 sizeSS1 = 6 4241 sizeSS2 = 6 4242 sizeSS3 = 6 4243 sizeSS4 = 6 4244 sizeSS5 = 6 4245 sizeSS6 = 6 4246 sizeSSE = 6 4247 sizeSSF = 6 4248 ) 4249 4250 // instruction format variations 4251 type form int 4252 4253 const ( 4254 _a form = iota 4255 _b 4256 _c 4257 _d 4258 _e 4259 _f 4260 ) 4261 4262 func zE(op uint32, asm *[]byte) { 4263 *asm = append(*asm, uint8(op>>8), uint8(op)) 4264 } 4265 4266 func zI(op, i1 uint32, asm *[]byte) { 4267 *asm = append(*asm, uint8(op>>8), uint8(i1)) 4268 } 4269 4270 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) { 4271 *asm = append(*asm, 4272 uint8(op>>8), 4273 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F), 4274 uint8(ri2), 4275 uint8(ri3>>16), 4276 uint8(ri3>>8), 4277 uint8(ri3)) 4278 } 4279 4280 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4281 *asm = append(*asm, 4282 uint8(op>>8), 4283 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4284 uint8(i2_ri2>>8), 4285 uint8(i2_ri2)) 4286 } 4287 4288 // Expected argument values for the instruction formats. 4289 // 4290 // Format a1 a2 a3 a4 a5 a6 a7 4291 // ------------------------------------ 4292 // a r1, 0, i2, 0, 0, m3, 0 4293 // b r1, r2, ri4, 0, 0, m3, 0 4294 // c r1, m3, ri4, 0, 0, 0, i2 4295 // d r1, r3, i2, 0, 0, 0, 0 4296 // e r1, r3, ri2, 0, 0, 0, 0 4297 // f r1, r2, 0, i3, i4, 0, i5 4298 // g r1, m3, i2, 0, 0, 0, 0 4299 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) { 4300 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F)) 4301 4302 switch f { 4303 default: 4304 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2)) 4305 case _f: 4306 *asm = append(*asm, uint8(i3), uint8(i4)) 4307 } 4308 4309 switch f { 4310 case _a, _b: 4311 *asm = append(*asm, uint8(m3)<<4) 4312 default: 4313 *asm = append(*asm, uint8(i2_i5)) 4314 } 4315 4316 *asm = append(*asm, uint8(op)) 4317 } 4318 4319 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4320 if f == _a || f == _b { 4321 r1_m1 = r1_m1 - obj.RBaseS390X // this is a register base 4322 } 4323 *asm = append(*asm, 4324 uint8(op>>8), 4325 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4326 uint8(i2_ri2>>24), 4327 uint8(i2_ri2>>16), 4328 uint8(i2_ri2>>8), 4329 uint8(i2_ri2)) 4330 } 4331 4332 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) { 4333 *asm = append(*asm, 4334 uint8(op>>8), 4335 (uint8(r1)<<4)|uint8(m3&0x0F), 4336 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F), 4337 uint8(d4), 4338 uint8(i2), 4339 uint8(op)) 4340 } 4341 4342 func zRR(op, r1, r2 uint32, asm *[]byte) { 4343 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F)) 4344 } 4345 4346 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) { 4347 *asm = append(*asm, 4348 uint8(op>>8), 4349 uint8(op), 4350 uint8(r1)<<4, 4351 (uint8(r3)<<4)|uint8(r2&0x0F)) 4352 } 4353 4354 func zRRE(op, r1, r2 uint32, asm *[]byte) { 4355 *asm = append(*asm, 4356 uint8(op>>8), 4357 uint8(op), 4358 0, 4359 (uint8(r1)<<4)|uint8(r2&0x0F)) 4360 } 4361 4362 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) { 4363 *asm = append(*asm, 4364 uint8(op>>8), 4365 uint8(op), 4366 (uint8(r3_m3)<<4)|uint8(m4&0x0F), 4367 (uint8(r1)<<4)|uint8(r2&0x0F)) 4368 } 4369 4370 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) { 4371 *asm = append(*asm, 4372 uint8(op>>8), 4373 (uint8(r1)<<4)|uint8(r2&0x0F), 4374 (uint8(b4)<<4)|uint8((d4>>8)&0x0F), 4375 uint8(d4), 4376 uint8(m3)<<4, 4377 uint8(op)) 4378 } 4379 4380 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4381 *asm = append(*asm, 4382 uint8(op>>8), 4383 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4384 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4385 uint8(d2)) 4386 } 4387 4388 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) { 4389 *asm = append(*asm, 4390 uint8(op>>8), 4391 (uint8(r1)<<4)|uint8(r3&0x0F), 4392 uint8(ri2>>8), 4393 uint8(ri2)) 4394 } 4395 4396 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) { 4397 *asm = append(*asm, 4398 uint8(op>>8), 4399 uint8(l1), 4400 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4401 uint8(d2), 4402 uint8(op)) 4403 } 4404 4405 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4406 dl2 := uint16(d2) & 0x0FFF 4407 *asm = append(*asm, 4408 uint8(op>>8), 4409 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4410 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4411 uint8(dl2), 4412 uint8(d2>>12), 4413 uint8(op)) 4414 } 4415 4416 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4417 *asm = append(*asm, 4418 uint8(op>>8), 4419 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4420 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4421 uint8(d2)) 4422 } 4423 4424 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) { 4425 *asm = append(*asm, 4426 uint8(op>>8), 4427 (uint8(r1)<<4)|uint8(x2&0x0F), 4428 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4429 uint8(d2), 4430 uint8(m3)<<4, 4431 uint8(op)) 4432 } 4433 4434 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) { 4435 *asm = append(*asm, 4436 uint8(op>>8), 4437 (uint8(r3)<<4)|uint8(x2&0x0F), 4438 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4439 uint8(d2), 4440 uint8(m1)<<4, 4441 uint8(op)) 4442 } 4443 4444 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4445 dl2 := uint16(d2) & 0x0FFF 4446 *asm = append(*asm, 4447 uint8(op>>8), 4448 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4449 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4450 uint8(dl2), 4451 uint8(d2>>12), 4452 uint8(op)) 4453 } 4454 4455 func zS(op, b2, d2 uint32, asm *[]byte) { 4456 *asm = append(*asm, 4457 uint8(op>>8), 4458 uint8(op), 4459 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4460 uint8(d2)) 4461 } 4462 4463 func zSI(op, i2, b1, d1 uint32, asm *[]byte) { 4464 *asm = append(*asm, 4465 uint8(op>>8), 4466 uint8(i2), 4467 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4468 uint8(d1)) 4469 } 4470 4471 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) { 4472 *asm = append(*asm, 4473 uint8(op>>8), 4474 uint8(op), 4475 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4476 uint8(d1), 4477 uint8(i2>>8), 4478 uint8(i2)) 4479 } 4480 4481 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) { 4482 dl1 := uint16(d1) & 0x0FFF 4483 *asm = append(*asm, 4484 uint8(op>>8), 4485 uint8(i2), 4486 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F), 4487 uint8(dl1), 4488 uint8(d1>>12), 4489 uint8(op)) 4490 } 4491 4492 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) { 4493 *asm = append(*asm, 4494 uint8(op>>8), 4495 uint8(m1)<<4, 4496 (uint8(b3)<<4)|uint8((d3>>8)&0x0F), 4497 uint8(d3), 4498 uint8(ri2>>8), 4499 uint8(ri2)) 4500 } 4501 4502 // Expected argument values for the instruction formats. 4503 // 4504 // Format a1 a2 a3 a4 a5 a6 4505 // ------------------------------- 4506 // a l1, 0, b1, d1, b2, d2 4507 // b l1, l2, b1, d1, b2, d2 4508 // c l1, i3, b1, d1, b2, d2 4509 // d r1, r3, b1, d1, b2, d2 4510 // e r1, r3, b2, d2, b4, d4 4511 // f 0, l2, b1, d1, b2, d2 4512 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) { 4513 *asm = append(*asm, uint8(op>>8)) 4514 4515 switch f { 4516 case _a: 4517 *asm = append(*asm, uint8(l1_r1)) 4518 case _b, _c, _d, _e: 4519 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F)) 4520 case _f: 4521 *asm = append(*asm, uint8(l2_i3_r3)) 4522 } 4523 4524 *asm = append(*asm, 4525 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F), 4526 uint8(d1_d2), 4527 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F), 4528 uint8(d2_d4)) 4529 } 4530 4531 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) { 4532 *asm = append(*asm, 4533 uint8(op>>8), 4534 uint8(op), 4535 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4536 uint8(d1), 4537 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4538 uint8(d2)) 4539 } 4540 4541 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) { 4542 *asm = append(*asm, 4543 uint8(op>>8), 4544 (uint8(r3)<<4)|(uint8(op)&0x0F), 4545 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4546 uint8(d1), 4547 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4548 uint8(d2)) 4549 } 4550 4551 func rxb(va, vb, vc, vd uint32) uint8 { 4552 mask := uint8(0) 4553 if va >= REG_V16 && va <= REG_V31 { 4554 mask |= 0x8 4555 } 4556 if vb >= REG_V16 && vb <= REG_V31 { 4557 mask |= 0x4 4558 } 4559 if vc >= REG_V16 && vc <= REG_V31 { 4560 mask |= 0x2 4561 } 4562 if vd >= REG_V16 && vd <= REG_V31 { 4563 mask |= 0x1 4564 } 4565 return mask 4566 } 4567 4568 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) { 4569 *asm = append(*asm, 4570 uint8(op>>8), 4571 (uint8(v1)<<4)|(uint8(x2)&0xf), 4572 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4573 uint8(d2), 4574 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4575 uint8(op)) 4576 } 4577 4578 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) { 4579 *asm = append(*asm, 4580 uint8(op>>8), 4581 (uint8(v1)<<4)|(uint8(v2)&0xf), 4582 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4583 uint8(d2), 4584 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4585 uint8(op)) 4586 } 4587 4588 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) { 4589 *asm = append(*asm, 4590 uint8(op>>8), 4591 (uint8(v1)<<4)|(uint8(v3_r3)&0xf), 4592 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4593 uint8(d2), 4594 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0), 4595 uint8(op)) 4596 } 4597 4598 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) { 4599 *asm = append(*asm, 4600 uint8(op>>8), 4601 (uint8(v1)<<4)|(uint8(v2)&0xf), 4602 0, 4603 (uint8(m5)<<4)|(uint8(m4)&0xf), 4604 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4605 uint8(op)) 4606 } 4607 4608 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) { 4609 *asm = append(*asm, 4610 uint8(op>>8), 4611 (uint8(v1)<<4)|(uint8(v2)&0xf), 4612 uint8(v3)<<4, 4613 uint8(m5)<<4, 4614 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4615 uint8(op)) 4616 } 4617 4618 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) { 4619 *asm = append(*asm, 4620 uint8(op>>8), 4621 (uint8(v1)<<4)|(uint8(v2)&0xf), 4622 uint8(v3)<<4, 4623 (uint8(m6)<<4)|(uint8(m5)&0xf), 4624 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4625 uint8(op)) 4626 } 4627 4628 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) { 4629 *asm = append(*asm, 4630 uint8(op>>8), 4631 (uint8(v1)<<4)|(uint8(v2)&0xf), 4632 (uint8(v3)<<4)|(uint8(m5)&0xf), 4633 uint8(m6)<<4, 4634 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4635 uint8(op)) 4636 } 4637 4638 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) { 4639 *asm = append(*asm, 4640 uint8(op>>8), 4641 (uint8(v1)<<4)|(uint8(v2)&0xf), 4642 (uint8(v3)<<4)|(uint8(m6)&0xf), 4643 uint8(m5), 4644 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4645 uint8(op)) 4646 } 4647 4648 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) { 4649 *asm = append(*asm, 4650 uint8(op>>8), 4651 (uint8(v1)<<4)|(uint8(r2)&0xf), 4652 uint8(r3)<<4, 4653 0, 4654 rxb(v1, 0, 0, 0), 4655 uint8(op)) 4656 } 4657 4658 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) { 4659 *asm = append(*asm, 4660 uint8(op>>8), 4661 uint8(v1)<<4, 4662 uint8(i2>>8), 4663 uint8(i2), 4664 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4665 uint8(op)) 4666 } 4667 4668 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) { 4669 *asm = append(*asm, 4670 uint8(op>>8), 4671 uint8(v1)<<4, 4672 uint8(i2), 4673 uint8(i3), 4674 (uint8(m4)<<4)|rxb(v1, 0, 0, 0), 4675 uint8(op)) 4676 } 4677 4678 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) { 4679 *asm = append(*asm, 4680 uint8(op>>8), 4681 (uint8(v1)<<4)|(uint8(v3)&0xf), 4682 uint8(i2>>8), 4683 uint8(i2), 4684 (uint8(m4)<<4)|rxb(v1, v3, 0, 0), 4685 uint8(op)) 4686 } 4687 4688 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) { 4689 *asm = append(*asm, 4690 uint8(op>>8), 4691 (uint8(v1)<<4)|(uint8(v2)&0xf), 4692 uint8(v3)<<4, 4693 uint8(i4), 4694 (uint8(m5)<<4)|rxb(v1, v2, v3, 0), 4695 uint8(op)) 4696 } 4697 4698 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) { 4699 *asm = append(*asm, 4700 uint8(op>>8), 4701 (uint8(v1)<<4)|(uint8(v2)&0xf), 4702 uint8(i3>>4), 4703 (uint8(i3)<<4)|(uint8(m5)&0xf), 4704 (uint8(m4)<<4)|rxb(v1, v2, 0, 0), 4705 uint8(op)) 4706 }