github.com/riscv/riscv-go@v0.0.0-20200123204226-124ebd6fcc8e/src/cmd/compile/internal/ssa/opGen.go (about) 1 // autogenerated: do not edit! 2 // generated from gen/*Ops.go 3 4 package ssa 5 6 import ( 7 "cmd/internal/obj" 8 "cmd/internal/obj/arm" 9 "cmd/internal/obj/arm64" 10 "cmd/internal/obj/mips" 11 "cmd/internal/obj/ppc64" 12 "cmd/internal/obj/riscv" 13 "cmd/internal/obj/s390x" 14 "cmd/internal/obj/x86" 15 ) 16 17 const ( 18 BlockInvalid BlockKind = iota 19 20 Block386EQ 21 Block386NE 22 Block386LT 23 Block386LE 24 Block386GT 25 Block386GE 26 Block386ULT 27 Block386ULE 28 Block386UGT 29 Block386UGE 30 Block386EQF 31 Block386NEF 32 Block386ORD 33 Block386NAN 34 35 BlockAMD64EQ 36 BlockAMD64NE 37 BlockAMD64LT 38 BlockAMD64LE 39 BlockAMD64GT 40 BlockAMD64GE 41 BlockAMD64ULT 42 BlockAMD64ULE 43 BlockAMD64UGT 44 BlockAMD64UGE 45 BlockAMD64EQF 46 BlockAMD64NEF 47 BlockAMD64ORD 48 BlockAMD64NAN 49 50 BlockARMEQ 51 BlockARMNE 52 BlockARMLT 53 BlockARMLE 54 BlockARMGT 55 BlockARMGE 56 BlockARMULT 57 BlockARMULE 58 BlockARMUGT 59 BlockARMUGE 60 61 BlockARM64EQ 62 BlockARM64NE 63 BlockARM64LT 64 BlockARM64LE 65 BlockARM64GT 66 BlockARM64GE 67 BlockARM64ULT 68 BlockARM64ULE 69 BlockARM64UGT 70 BlockARM64UGE 71 BlockARM64Z 72 BlockARM64NZ 73 BlockARM64ZW 74 BlockARM64NZW 75 76 BlockMIPSEQ 77 BlockMIPSNE 78 BlockMIPSLTZ 79 BlockMIPSLEZ 80 BlockMIPSGTZ 81 BlockMIPSGEZ 82 BlockMIPSFPT 83 BlockMIPSFPF 84 85 BlockMIPS64EQ 86 BlockMIPS64NE 87 BlockMIPS64LTZ 88 BlockMIPS64LEZ 89 BlockMIPS64GTZ 90 BlockMIPS64GEZ 91 BlockMIPS64FPT 92 BlockMIPS64FPF 93 94 BlockPPC64EQ 95 BlockPPC64NE 96 BlockPPC64LT 97 BlockPPC64LE 98 BlockPPC64GT 99 BlockPPC64GE 100 BlockPPC64FLT 101 BlockPPC64FLE 102 BlockPPC64FGT 103 BlockPPC64FGE 104 105 BlockRISCVBNE 106 107 BlockS390XEQ 108 BlockS390XNE 109 BlockS390XLT 110 BlockS390XLE 111 BlockS390XGT 112 BlockS390XGE 113 BlockS390XGTF 114 BlockS390XGEF 115 116 BlockPlain 117 BlockIf 118 BlockDefer 119 BlockRet 120 BlockRetJmp 121 BlockExit 122 BlockFirst 123 ) 124 125 var blockString = [...]string{ 126 BlockInvalid: "BlockInvalid", 127 128 Block386EQ: "EQ", 129 Block386NE: "NE", 130 Block386LT: "LT", 131 Block386LE: "LE", 132 Block386GT: "GT", 133 Block386GE: "GE", 134 Block386ULT: "ULT", 135 Block386ULE: "ULE", 136 Block386UGT: "UGT", 137 Block386UGE: "UGE", 138 Block386EQF: "EQF", 139 Block386NEF: "NEF", 140 Block386ORD: "ORD", 141 Block386NAN: "NAN", 142 143 BlockAMD64EQ: "EQ", 144 BlockAMD64NE: "NE", 145 BlockAMD64LT: "LT", 146 BlockAMD64LE: "LE", 147 BlockAMD64GT: "GT", 148 BlockAMD64GE: "GE", 149 BlockAMD64ULT: "ULT", 150 BlockAMD64ULE: "ULE", 151 BlockAMD64UGT: "UGT", 152 BlockAMD64UGE: "UGE", 153 BlockAMD64EQF: "EQF", 154 BlockAMD64NEF: "NEF", 155 BlockAMD64ORD: "ORD", 156 BlockAMD64NAN: "NAN", 157 158 BlockARMEQ: "EQ", 159 BlockARMNE: "NE", 160 BlockARMLT: "LT", 161 BlockARMLE: "LE", 162 BlockARMGT: "GT", 163 BlockARMGE: "GE", 164 BlockARMULT: "ULT", 165 BlockARMULE: "ULE", 166 BlockARMUGT: "UGT", 167 BlockARMUGE: "UGE", 168 169 BlockARM64EQ: "EQ", 170 BlockARM64NE: "NE", 171 BlockARM64LT: "LT", 172 BlockARM64LE: "LE", 173 BlockARM64GT: "GT", 174 BlockARM64GE: "GE", 175 BlockARM64ULT: "ULT", 176 BlockARM64ULE: "ULE", 177 BlockARM64UGT: "UGT", 178 BlockARM64UGE: "UGE", 179 BlockARM64Z: "Z", 180 BlockARM64NZ: "NZ", 181 BlockARM64ZW: "ZW", 182 BlockARM64NZW: "NZW", 183 184 BlockMIPSEQ: "EQ", 185 BlockMIPSNE: "NE", 186 BlockMIPSLTZ: "LTZ", 187 BlockMIPSLEZ: "LEZ", 188 BlockMIPSGTZ: "GTZ", 189 BlockMIPSGEZ: "GEZ", 190 BlockMIPSFPT: "FPT", 191 BlockMIPSFPF: "FPF", 192 193 BlockMIPS64EQ: "EQ", 194 BlockMIPS64NE: "NE", 195 BlockMIPS64LTZ: "LTZ", 196 BlockMIPS64LEZ: "LEZ", 197 BlockMIPS64GTZ: "GTZ", 198 BlockMIPS64GEZ: "GEZ", 199 BlockMIPS64FPT: "FPT", 200 BlockMIPS64FPF: "FPF", 201 202 BlockPPC64EQ: "EQ", 203 BlockPPC64NE: "NE", 204 BlockPPC64LT: "LT", 205 BlockPPC64LE: "LE", 206 BlockPPC64GT: "GT", 207 BlockPPC64GE: "GE", 208 BlockPPC64FLT: "FLT", 209 BlockPPC64FLE: "FLE", 210 BlockPPC64FGT: "FGT", 211 BlockPPC64FGE: "FGE", 212 213 BlockRISCVBNE: "BNE", 214 215 BlockS390XEQ: "EQ", 216 BlockS390XNE: "NE", 217 BlockS390XLT: "LT", 218 BlockS390XLE: "LE", 219 BlockS390XGT: "GT", 220 BlockS390XGE: "GE", 221 BlockS390XGTF: "GTF", 222 BlockS390XGEF: "GEF", 223 224 BlockPlain: "Plain", 225 BlockIf: "If", 226 BlockDefer: "Defer", 227 BlockRet: "Ret", 228 BlockRetJmp: "RetJmp", 229 BlockExit: "Exit", 230 BlockFirst: "First", 231 } 232 233 func (k BlockKind) String() string { return blockString[k] } 234 235 const ( 236 OpInvalid Op = iota 237 238 Op386ADDSS 239 Op386ADDSD 240 Op386SUBSS 241 Op386SUBSD 242 Op386MULSS 243 Op386MULSD 244 Op386DIVSS 245 Op386DIVSD 246 Op386MOVSSload 247 Op386MOVSDload 248 Op386MOVSSconst 249 Op386MOVSDconst 250 Op386MOVSSloadidx1 251 Op386MOVSSloadidx4 252 Op386MOVSDloadidx1 253 Op386MOVSDloadidx8 254 Op386MOVSSstore 255 Op386MOVSDstore 256 Op386MOVSSstoreidx1 257 Op386MOVSSstoreidx4 258 Op386MOVSDstoreidx1 259 Op386MOVSDstoreidx8 260 Op386ADDL 261 Op386ADDLconst 262 Op386ADDLcarry 263 Op386ADDLconstcarry 264 Op386ADCL 265 Op386ADCLconst 266 Op386SUBL 267 Op386SUBLconst 268 Op386SUBLcarry 269 Op386SUBLconstcarry 270 Op386SBBL 271 Op386SBBLconst 272 Op386MULL 273 Op386MULLconst 274 Op386HMULL 275 Op386HMULLU 276 Op386HMULW 277 Op386HMULB 278 Op386HMULWU 279 Op386HMULBU 280 Op386MULLQU 281 Op386DIVL 282 Op386DIVW 283 Op386DIVLU 284 Op386DIVWU 285 Op386MODL 286 Op386MODW 287 Op386MODLU 288 Op386MODWU 289 Op386ANDL 290 Op386ANDLconst 291 Op386ORL 292 Op386ORLconst 293 Op386XORL 294 Op386XORLconst 295 Op386CMPL 296 Op386CMPW 297 Op386CMPB 298 Op386CMPLconst 299 Op386CMPWconst 300 Op386CMPBconst 301 Op386UCOMISS 302 Op386UCOMISD 303 Op386TESTL 304 Op386TESTW 305 Op386TESTB 306 Op386TESTLconst 307 Op386TESTWconst 308 Op386TESTBconst 309 Op386SHLL 310 Op386SHLLconst 311 Op386SHRL 312 Op386SHRW 313 Op386SHRB 314 Op386SHRLconst 315 Op386SHRWconst 316 Op386SHRBconst 317 Op386SARL 318 Op386SARW 319 Op386SARB 320 Op386SARLconst 321 Op386SARWconst 322 Op386SARBconst 323 Op386ROLLconst 324 Op386ROLWconst 325 Op386ROLBconst 326 Op386NEGL 327 Op386NOTL 328 Op386BSFL 329 Op386BSFW 330 Op386BSRL 331 Op386BSRW 332 Op386BSWAPL 333 Op386SQRTSD 334 Op386SBBLcarrymask 335 Op386SETEQ 336 Op386SETNE 337 Op386SETL 338 Op386SETLE 339 Op386SETG 340 Op386SETGE 341 Op386SETB 342 Op386SETBE 343 Op386SETA 344 Op386SETAE 345 Op386SETEQF 346 Op386SETNEF 347 Op386SETORD 348 Op386SETNAN 349 Op386SETGF 350 Op386SETGEF 351 Op386MOVBLSX 352 Op386MOVBLZX 353 Op386MOVWLSX 354 Op386MOVWLZX 355 Op386MOVLconst 356 Op386CVTTSD2SL 357 Op386CVTTSS2SL 358 Op386CVTSL2SS 359 Op386CVTSL2SD 360 Op386CVTSD2SS 361 Op386CVTSS2SD 362 Op386PXOR 363 Op386LEAL 364 Op386LEAL1 365 Op386LEAL2 366 Op386LEAL4 367 Op386LEAL8 368 Op386MOVBload 369 Op386MOVBLSXload 370 Op386MOVWload 371 Op386MOVWLSXload 372 Op386MOVLload 373 Op386MOVBstore 374 Op386MOVWstore 375 Op386MOVLstore 376 Op386MOVBloadidx1 377 Op386MOVWloadidx1 378 Op386MOVWloadidx2 379 Op386MOVLloadidx1 380 Op386MOVLloadidx4 381 Op386MOVBstoreidx1 382 Op386MOVWstoreidx1 383 Op386MOVWstoreidx2 384 Op386MOVLstoreidx1 385 Op386MOVLstoreidx4 386 Op386MOVBstoreconst 387 Op386MOVWstoreconst 388 Op386MOVLstoreconst 389 Op386MOVBstoreconstidx1 390 Op386MOVWstoreconstidx1 391 Op386MOVWstoreconstidx2 392 Op386MOVLstoreconstidx1 393 Op386MOVLstoreconstidx4 394 Op386DUFFZERO 395 Op386REPSTOSL 396 Op386CALLstatic 397 Op386CALLclosure 398 Op386CALLdefer 399 Op386CALLgo 400 Op386CALLinter 401 Op386DUFFCOPY 402 Op386REPMOVSL 403 Op386InvertFlags 404 Op386LoweredGetG 405 Op386LoweredGetClosurePtr 406 Op386LoweredNilCheck 407 Op386MOVLconvert 408 Op386FlagEQ 409 Op386FlagLT_ULT 410 Op386FlagLT_UGT 411 Op386FlagGT_UGT 412 Op386FlagGT_ULT 413 Op386FCHS 414 Op386MOVSSconst1 415 Op386MOVSDconst1 416 Op386MOVSSconst2 417 Op386MOVSDconst2 418 419 OpAMD64ADDSS 420 OpAMD64ADDSD 421 OpAMD64SUBSS 422 OpAMD64SUBSD 423 OpAMD64MULSS 424 OpAMD64MULSD 425 OpAMD64DIVSS 426 OpAMD64DIVSD 427 OpAMD64MOVSSload 428 OpAMD64MOVSDload 429 OpAMD64MOVSSconst 430 OpAMD64MOVSDconst 431 OpAMD64MOVSSloadidx1 432 OpAMD64MOVSSloadidx4 433 OpAMD64MOVSDloadidx1 434 OpAMD64MOVSDloadidx8 435 OpAMD64MOVSSstore 436 OpAMD64MOVSDstore 437 OpAMD64MOVSSstoreidx1 438 OpAMD64MOVSSstoreidx4 439 OpAMD64MOVSDstoreidx1 440 OpAMD64MOVSDstoreidx8 441 OpAMD64ADDQ 442 OpAMD64ADDL 443 OpAMD64ADDQconst 444 OpAMD64ADDLconst 445 OpAMD64SUBQ 446 OpAMD64SUBL 447 OpAMD64SUBQconst 448 OpAMD64SUBLconst 449 OpAMD64MULQ 450 OpAMD64MULL 451 OpAMD64MULQconst 452 OpAMD64MULLconst 453 OpAMD64HMULQ 454 OpAMD64HMULL 455 OpAMD64HMULW 456 OpAMD64HMULB 457 OpAMD64HMULQU 458 OpAMD64HMULLU 459 OpAMD64HMULWU 460 OpAMD64HMULBU 461 OpAMD64AVGQU 462 OpAMD64DIVQ 463 OpAMD64DIVL 464 OpAMD64DIVW 465 OpAMD64DIVQU 466 OpAMD64DIVLU 467 OpAMD64DIVWU 468 OpAMD64MULQU2 469 OpAMD64DIVQU2 470 OpAMD64ANDQ 471 OpAMD64ANDL 472 OpAMD64ANDQconst 473 OpAMD64ANDLconst 474 OpAMD64ORQ 475 OpAMD64ORL 476 OpAMD64ORQconst 477 OpAMD64ORLconst 478 OpAMD64XORQ 479 OpAMD64XORL 480 OpAMD64XORQconst 481 OpAMD64XORLconst 482 OpAMD64CMPQ 483 OpAMD64CMPL 484 OpAMD64CMPW 485 OpAMD64CMPB 486 OpAMD64CMPQconst 487 OpAMD64CMPLconst 488 OpAMD64CMPWconst 489 OpAMD64CMPBconst 490 OpAMD64UCOMISS 491 OpAMD64UCOMISD 492 OpAMD64TESTQ 493 OpAMD64TESTL 494 OpAMD64TESTW 495 OpAMD64TESTB 496 OpAMD64TESTQconst 497 OpAMD64TESTLconst 498 OpAMD64TESTWconst 499 OpAMD64TESTBconst 500 OpAMD64SHLQ 501 OpAMD64SHLL 502 OpAMD64SHLQconst 503 OpAMD64SHLLconst 504 OpAMD64SHRQ 505 OpAMD64SHRL 506 OpAMD64SHRW 507 OpAMD64SHRB 508 OpAMD64SHRQconst 509 OpAMD64SHRLconst 510 OpAMD64SHRWconst 511 OpAMD64SHRBconst 512 OpAMD64SARQ 513 OpAMD64SARL 514 OpAMD64SARW 515 OpAMD64SARB 516 OpAMD64SARQconst 517 OpAMD64SARLconst 518 OpAMD64SARWconst 519 OpAMD64SARBconst 520 OpAMD64ROLQconst 521 OpAMD64ROLLconst 522 OpAMD64ROLWconst 523 OpAMD64ROLBconst 524 OpAMD64NEGQ 525 OpAMD64NEGL 526 OpAMD64NOTQ 527 OpAMD64NOTL 528 OpAMD64BSFQ 529 OpAMD64BSFL 530 OpAMD64CMOVQEQ 531 OpAMD64CMOVLEQ 532 OpAMD64BSWAPQ 533 OpAMD64BSWAPL 534 OpAMD64SQRTSD 535 OpAMD64SBBQcarrymask 536 OpAMD64SBBLcarrymask 537 OpAMD64SETEQ 538 OpAMD64SETNE 539 OpAMD64SETL 540 OpAMD64SETLE 541 OpAMD64SETG 542 OpAMD64SETGE 543 OpAMD64SETB 544 OpAMD64SETBE 545 OpAMD64SETA 546 OpAMD64SETAE 547 OpAMD64SETEQF 548 OpAMD64SETNEF 549 OpAMD64SETORD 550 OpAMD64SETNAN 551 OpAMD64SETGF 552 OpAMD64SETGEF 553 OpAMD64MOVBQSX 554 OpAMD64MOVBQZX 555 OpAMD64MOVWQSX 556 OpAMD64MOVWQZX 557 OpAMD64MOVLQSX 558 OpAMD64MOVLQZX 559 OpAMD64MOVLconst 560 OpAMD64MOVQconst 561 OpAMD64CVTTSD2SL 562 OpAMD64CVTTSD2SQ 563 OpAMD64CVTTSS2SL 564 OpAMD64CVTTSS2SQ 565 OpAMD64CVTSL2SS 566 OpAMD64CVTSL2SD 567 OpAMD64CVTSQ2SS 568 OpAMD64CVTSQ2SD 569 OpAMD64CVTSD2SS 570 OpAMD64CVTSS2SD 571 OpAMD64PXOR 572 OpAMD64LEAQ 573 OpAMD64LEAQ1 574 OpAMD64LEAQ2 575 OpAMD64LEAQ4 576 OpAMD64LEAQ8 577 OpAMD64LEAL 578 OpAMD64MOVBload 579 OpAMD64MOVBQSXload 580 OpAMD64MOVWload 581 OpAMD64MOVWQSXload 582 OpAMD64MOVLload 583 OpAMD64MOVLQSXload 584 OpAMD64MOVQload 585 OpAMD64MOVBstore 586 OpAMD64MOVWstore 587 OpAMD64MOVLstore 588 OpAMD64MOVQstore 589 OpAMD64MOVOload 590 OpAMD64MOVOstore 591 OpAMD64MOVBloadidx1 592 OpAMD64MOVWloadidx1 593 OpAMD64MOVWloadidx2 594 OpAMD64MOVLloadidx1 595 OpAMD64MOVLloadidx4 596 OpAMD64MOVQloadidx1 597 OpAMD64MOVQloadidx8 598 OpAMD64MOVBstoreidx1 599 OpAMD64MOVWstoreidx1 600 OpAMD64MOVWstoreidx2 601 OpAMD64MOVLstoreidx1 602 OpAMD64MOVLstoreidx4 603 OpAMD64MOVQstoreidx1 604 OpAMD64MOVQstoreidx8 605 OpAMD64MOVBstoreconst 606 OpAMD64MOVWstoreconst 607 OpAMD64MOVLstoreconst 608 OpAMD64MOVQstoreconst 609 OpAMD64MOVBstoreconstidx1 610 OpAMD64MOVWstoreconstidx1 611 OpAMD64MOVWstoreconstidx2 612 OpAMD64MOVLstoreconstidx1 613 OpAMD64MOVLstoreconstidx4 614 OpAMD64MOVQstoreconstidx1 615 OpAMD64MOVQstoreconstidx8 616 OpAMD64DUFFZERO 617 OpAMD64MOVOconst 618 OpAMD64REPSTOSQ 619 OpAMD64CALLstatic 620 OpAMD64CALLclosure 621 OpAMD64CALLdefer 622 OpAMD64CALLgo 623 OpAMD64CALLinter 624 OpAMD64DUFFCOPY 625 OpAMD64REPMOVSQ 626 OpAMD64InvertFlags 627 OpAMD64LoweredGetG 628 OpAMD64LoweredGetClosurePtr 629 OpAMD64LoweredNilCheck 630 OpAMD64MOVQconvert 631 OpAMD64MOVLconvert 632 OpAMD64FlagEQ 633 OpAMD64FlagLT_ULT 634 OpAMD64FlagLT_UGT 635 OpAMD64FlagGT_UGT 636 OpAMD64FlagGT_ULT 637 OpAMD64MOVLatomicload 638 OpAMD64MOVQatomicload 639 OpAMD64XCHGL 640 OpAMD64XCHGQ 641 OpAMD64XADDLlock 642 OpAMD64XADDQlock 643 OpAMD64AddTupleFirst32 644 OpAMD64AddTupleFirst64 645 OpAMD64CMPXCHGLlock 646 OpAMD64CMPXCHGQlock 647 OpAMD64ANDBlock 648 OpAMD64ORBlock 649 650 OpARMADD 651 OpARMADDconst 652 OpARMSUB 653 OpARMSUBconst 654 OpARMRSB 655 OpARMRSBconst 656 OpARMMUL 657 OpARMHMUL 658 OpARMHMULU 659 OpARMUDIVrtcall 660 OpARMADDS 661 OpARMADDSconst 662 OpARMADC 663 OpARMADCconst 664 OpARMSUBS 665 OpARMSUBSconst 666 OpARMRSBSconst 667 OpARMSBC 668 OpARMSBCconst 669 OpARMRSCconst 670 OpARMMULLU 671 OpARMMULA 672 OpARMADDF 673 OpARMADDD 674 OpARMSUBF 675 OpARMSUBD 676 OpARMMULF 677 OpARMMULD 678 OpARMDIVF 679 OpARMDIVD 680 OpARMAND 681 OpARMANDconst 682 OpARMOR 683 OpARMORconst 684 OpARMXOR 685 OpARMXORconst 686 OpARMBIC 687 OpARMBICconst 688 OpARMMVN 689 OpARMNEGF 690 OpARMNEGD 691 OpARMSQRTD 692 OpARMCLZ 693 OpARMSLL 694 OpARMSLLconst 695 OpARMSRL 696 OpARMSRLconst 697 OpARMSRA 698 OpARMSRAconst 699 OpARMSRRconst 700 OpARMADDshiftLL 701 OpARMADDshiftRL 702 OpARMADDshiftRA 703 OpARMSUBshiftLL 704 OpARMSUBshiftRL 705 OpARMSUBshiftRA 706 OpARMRSBshiftLL 707 OpARMRSBshiftRL 708 OpARMRSBshiftRA 709 OpARMANDshiftLL 710 OpARMANDshiftRL 711 OpARMANDshiftRA 712 OpARMORshiftLL 713 OpARMORshiftRL 714 OpARMORshiftRA 715 OpARMXORshiftLL 716 OpARMXORshiftRL 717 OpARMXORshiftRA 718 OpARMXORshiftRR 719 OpARMBICshiftLL 720 OpARMBICshiftRL 721 OpARMBICshiftRA 722 OpARMMVNshiftLL 723 OpARMMVNshiftRL 724 OpARMMVNshiftRA 725 OpARMADCshiftLL 726 OpARMADCshiftRL 727 OpARMADCshiftRA 728 OpARMSBCshiftLL 729 OpARMSBCshiftRL 730 OpARMSBCshiftRA 731 OpARMRSCshiftLL 732 OpARMRSCshiftRL 733 OpARMRSCshiftRA 734 OpARMADDSshiftLL 735 OpARMADDSshiftRL 736 OpARMADDSshiftRA 737 OpARMSUBSshiftLL 738 OpARMSUBSshiftRL 739 OpARMSUBSshiftRA 740 OpARMRSBSshiftLL 741 OpARMRSBSshiftRL 742 OpARMRSBSshiftRA 743 OpARMADDshiftLLreg 744 OpARMADDshiftRLreg 745 OpARMADDshiftRAreg 746 OpARMSUBshiftLLreg 747 OpARMSUBshiftRLreg 748 OpARMSUBshiftRAreg 749 OpARMRSBshiftLLreg 750 OpARMRSBshiftRLreg 751 OpARMRSBshiftRAreg 752 OpARMANDshiftLLreg 753 OpARMANDshiftRLreg 754 OpARMANDshiftRAreg 755 OpARMORshiftLLreg 756 OpARMORshiftRLreg 757 OpARMORshiftRAreg 758 OpARMXORshiftLLreg 759 OpARMXORshiftRLreg 760 OpARMXORshiftRAreg 761 OpARMBICshiftLLreg 762 OpARMBICshiftRLreg 763 OpARMBICshiftRAreg 764 OpARMMVNshiftLLreg 765 OpARMMVNshiftRLreg 766 OpARMMVNshiftRAreg 767 OpARMADCshiftLLreg 768 OpARMADCshiftRLreg 769 OpARMADCshiftRAreg 770 OpARMSBCshiftLLreg 771 OpARMSBCshiftRLreg 772 OpARMSBCshiftRAreg 773 OpARMRSCshiftLLreg 774 OpARMRSCshiftRLreg 775 OpARMRSCshiftRAreg 776 OpARMADDSshiftLLreg 777 OpARMADDSshiftRLreg 778 OpARMADDSshiftRAreg 779 OpARMSUBSshiftLLreg 780 OpARMSUBSshiftRLreg 781 OpARMSUBSshiftRAreg 782 OpARMRSBSshiftLLreg 783 OpARMRSBSshiftRLreg 784 OpARMRSBSshiftRAreg 785 OpARMCMP 786 OpARMCMPconst 787 OpARMCMN 788 OpARMCMNconst 789 OpARMTST 790 OpARMTSTconst 791 OpARMTEQ 792 OpARMTEQconst 793 OpARMCMPF 794 OpARMCMPD 795 OpARMCMPshiftLL 796 OpARMCMPshiftRL 797 OpARMCMPshiftRA 798 OpARMCMPshiftLLreg 799 OpARMCMPshiftRLreg 800 OpARMCMPshiftRAreg 801 OpARMCMPF0 802 OpARMCMPD0 803 OpARMMOVWconst 804 OpARMMOVFconst 805 OpARMMOVDconst 806 OpARMMOVWaddr 807 OpARMMOVBload 808 OpARMMOVBUload 809 OpARMMOVHload 810 OpARMMOVHUload 811 OpARMMOVWload 812 OpARMMOVFload 813 OpARMMOVDload 814 OpARMMOVBstore 815 OpARMMOVHstore 816 OpARMMOVWstore 817 OpARMMOVFstore 818 OpARMMOVDstore 819 OpARMMOVWloadidx 820 OpARMMOVWloadshiftLL 821 OpARMMOVWloadshiftRL 822 OpARMMOVWloadshiftRA 823 OpARMMOVWstoreidx 824 OpARMMOVWstoreshiftLL 825 OpARMMOVWstoreshiftRL 826 OpARMMOVWstoreshiftRA 827 OpARMMOVBreg 828 OpARMMOVBUreg 829 OpARMMOVHreg 830 OpARMMOVHUreg 831 OpARMMOVWreg 832 OpARMMOVWnop 833 OpARMMOVWF 834 OpARMMOVWD 835 OpARMMOVWUF 836 OpARMMOVWUD 837 OpARMMOVFW 838 OpARMMOVDW 839 OpARMMOVFWU 840 OpARMMOVDWU 841 OpARMMOVFD 842 OpARMMOVDF 843 OpARMCMOVWHSconst 844 OpARMCMOVWLSconst 845 OpARMSRAcond 846 OpARMCALLstatic 847 OpARMCALLclosure 848 OpARMCALLdefer 849 OpARMCALLgo 850 OpARMCALLinter 851 OpARMLoweredNilCheck 852 OpARMEqual 853 OpARMNotEqual 854 OpARMLessThan 855 OpARMLessEqual 856 OpARMGreaterThan 857 OpARMGreaterEqual 858 OpARMLessThanU 859 OpARMLessEqualU 860 OpARMGreaterThanU 861 OpARMGreaterEqualU 862 OpARMDUFFZERO 863 OpARMDUFFCOPY 864 OpARMLoweredZero 865 OpARMLoweredMove 866 OpARMLoweredGetClosurePtr 867 OpARMMOVWconvert 868 OpARMFlagEQ 869 OpARMFlagLT_ULT 870 OpARMFlagLT_UGT 871 OpARMFlagGT_UGT 872 OpARMFlagGT_ULT 873 OpARMInvertFlags 874 875 OpARM64ADD 876 OpARM64ADDconst 877 OpARM64SUB 878 OpARM64SUBconst 879 OpARM64MUL 880 OpARM64MULW 881 OpARM64MULH 882 OpARM64UMULH 883 OpARM64MULL 884 OpARM64UMULL 885 OpARM64DIV 886 OpARM64UDIV 887 OpARM64DIVW 888 OpARM64UDIVW 889 OpARM64MOD 890 OpARM64UMOD 891 OpARM64MODW 892 OpARM64UMODW 893 OpARM64FADDS 894 OpARM64FADDD 895 OpARM64FSUBS 896 OpARM64FSUBD 897 OpARM64FMULS 898 OpARM64FMULD 899 OpARM64FDIVS 900 OpARM64FDIVD 901 OpARM64AND 902 OpARM64ANDconst 903 OpARM64OR 904 OpARM64ORconst 905 OpARM64XOR 906 OpARM64XORconst 907 OpARM64BIC 908 OpARM64BICconst 909 OpARM64MVN 910 OpARM64NEG 911 OpARM64FNEGS 912 OpARM64FNEGD 913 OpARM64FSQRTD 914 OpARM64REV 915 OpARM64REVW 916 OpARM64REV16W 917 OpARM64RBIT 918 OpARM64RBITW 919 OpARM64CLZ 920 OpARM64CLZW 921 OpARM64SLL 922 OpARM64SLLconst 923 OpARM64SRL 924 OpARM64SRLconst 925 OpARM64SRA 926 OpARM64SRAconst 927 OpARM64RORconst 928 OpARM64RORWconst 929 OpARM64CMP 930 OpARM64CMPconst 931 OpARM64CMPW 932 OpARM64CMPWconst 933 OpARM64CMN 934 OpARM64CMNconst 935 OpARM64CMNW 936 OpARM64CMNWconst 937 OpARM64FCMPS 938 OpARM64FCMPD 939 OpARM64ADDshiftLL 940 OpARM64ADDshiftRL 941 OpARM64ADDshiftRA 942 OpARM64SUBshiftLL 943 OpARM64SUBshiftRL 944 OpARM64SUBshiftRA 945 OpARM64ANDshiftLL 946 OpARM64ANDshiftRL 947 OpARM64ANDshiftRA 948 OpARM64ORshiftLL 949 OpARM64ORshiftRL 950 OpARM64ORshiftRA 951 OpARM64XORshiftLL 952 OpARM64XORshiftRL 953 OpARM64XORshiftRA 954 OpARM64BICshiftLL 955 OpARM64BICshiftRL 956 OpARM64BICshiftRA 957 OpARM64CMPshiftLL 958 OpARM64CMPshiftRL 959 OpARM64CMPshiftRA 960 OpARM64MOVDconst 961 OpARM64FMOVSconst 962 OpARM64FMOVDconst 963 OpARM64MOVDaddr 964 OpARM64MOVBload 965 OpARM64MOVBUload 966 OpARM64MOVHload 967 OpARM64MOVHUload 968 OpARM64MOVWload 969 OpARM64MOVWUload 970 OpARM64MOVDload 971 OpARM64FMOVSload 972 OpARM64FMOVDload 973 OpARM64MOVBstore 974 OpARM64MOVHstore 975 OpARM64MOVWstore 976 OpARM64MOVDstore 977 OpARM64FMOVSstore 978 OpARM64FMOVDstore 979 OpARM64MOVBstorezero 980 OpARM64MOVHstorezero 981 OpARM64MOVWstorezero 982 OpARM64MOVDstorezero 983 OpARM64MOVBreg 984 OpARM64MOVBUreg 985 OpARM64MOVHreg 986 OpARM64MOVHUreg 987 OpARM64MOVWreg 988 OpARM64MOVWUreg 989 OpARM64MOVDreg 990 OpARM64MOVDnop 991 OpARM64SCVTFWS 992 OpARM64SCVTFWD 993 OpARM64UCVTFWS 994 OpARM64UCVTFWD 995 OpARM64SCVTFS 996 OpARM64SCVTFD 997 OpARM64UCVTFS 998 OpARM64UCVTFD 999 OpARM64FCVTZSSW 1000 OpARM64FCVTZSDW 1001 OpARM64FCVTZUSW 1002 OpARM64FCVTZUDW 1003 OpARM64FCVTZSS 1004 OpARM64FCVTZSD 1005 OpARM64FCVTZUS 1006 OpARM64FCVTZUD 1007 OpARM64FCVTSD 1008 OpARM64FCVTDS 1009 OpARM64CSELULT 1010 OpARM64CSELULT0 1011 OpARM64CALLstatic 1012 OpARM64CALLclosure 1013 OpARM64CALLdefer 1014 OpARM64CALLgo 1015 OpARM64CALLinter 1016 OpARM64LoweredNilCheck 1017 OpARM64Equal 1018 OpARM64NotEqual 1019 OpARM64LessThan 1020 OpARM64LessEqual 1021 OpARM64GreaterThan 1022 OpARM64GreaterEqual 1023 OpARM64LessThanU 1024 OpARM64LessEqualU 1025 OpARM64GreaterThanU 1026 OpARM64GreaterEqualU 1027 OpARM64DUFFZERO 1028 OpARM64LoweredZero 1029 OpARM64DUFFCOPY 1030 OpARM64LoweredMove 1031 OpARM64LoweredGetClosurePtr 1032 OpARM64MOVDconvert 1033 OpARM64FlagEQ 1034 OpARM64FlagLT_ULT 1035 OpARM64FlagLT_UGT 1036 OpARM64FlagGT_UGT 1037 OpARM64FlagGT_ULT 1038 OpARM64InvertFlags 1039 OpARM64LDAR 1040 OpARM64LDARW 1041 OpARM64STLR 1042 OpARM64STLRW 1043 OpARM64LoweredAtomicExchange64 1044 OpARM64LoweredAtomicExchange32 1045 OpARM64LoweredAtomicAdd64 1046 OpARM64LoweredAtomicAdd32 1047 OpARM64LoweredAtomicCas64 1048 OpARM64LoweredAtomicCas32 1049 OpARM64LoweredAtomicAnd8 1050 OpARM64LoweredAtomicOr8 1051 1052 OpMIPSADD 1053 OpMIPSADDconst 1054 OpMIPSSUB 1055 OpMIPSSUBconst 1056 OpMIPSMUL 1057 OpMIPSMULT 1058 OpMIPSMULTU 1059 OpMIPSDIV 1060 OpMIPSDIVU 1061 OpMIPSADDF 1062 OpMIPSADDD 1063 OpMIPSSUBF 1064 OpMIPSSUBD 1065 OpMIPSMULF 1066 OpMIPSMULD 1067 OpMIPSDIVF 1068 OpMIPSDIVD 1069 OpMIPSAND 1070 OpMIPSANDconst 1071 OpMIPSOR 1072 OpMIPSORconst 1073 OpMIPSXOR 1074 OpMIPSXORconst 1075 OpMIPSNOR 1076 OpMIPSNORconst 1077 OpMIPSNEG 1078 OpMIPSNEGF 1079 OpMIPSNEGD 1080 OpMIPSSQRTD 1081 OpMIPSSLL 1082 OpMIPSSLLconst 1083 OpMIPSSRL 1084 OpMIPSSRLconst 1085 OpMIPSSRA 1086 OpMIPSSRAconst 1087 OpMIPSCLZ 1088 OpMIPSSGT 1089 OpMIPSSGTconst 1090 OpMIPSSGTzero 1091 OpMIPSSGTU 1092 OpMIPSSGTUconst 1093 OpMIPSSGTUzero 1094 OpMIPSCMPEQF 1095 OpMIPSCMPEQD 1096 OpMIPSCMPGEF 1097 OpMIPSCMPGED 1098 OpMIPSCMPGTF 1099 OpMIPSCMPGTD 1100 OpMIPSMOVWconst 1101 OpMIPSMOVFconst 1102 OpMIPSMOVDconst 1103 OpMIPSMOVWaddr 1104 OpMIPSMOVBload 1105 OpMIPSMOVBUload 1106 OpMIPSMOVHload 1107 OpMIPSMOVHUload 1108 OpMIPSMOVWload 1109 OpMIPSMOVFload 1110 OpMIPSMOVDload 1111 OpMIPSMOVBstore 1112 OpMIPSMOVHstore 1113 OpMIPSMOVWstore 1114 OpMIPSMOVFstore 1115 OpMIPSMOVDstore 1116 OpMIPSMOVBstorezero 1117 OpMIPSMOVHstorezero 1118 OpMIPSMOVWstorezero 1119 OpMIPSMOVBreg 1120 OpMIPSMOVBUreg 1121 OpMIPSMOVHreg 1122 OpMIPSMOVHUreg 1123 OpMIPSMOVWreg 1124 OpMIPSMOVWnop 1125 OpMIPSCMOVZ 1126 OpMIPSCMOVZzero 1127 OpMIPSMOVWF 1128 OpMIPSMOVWD 1129 OpMIPSTRUNCFW 1130 OpMIPSTRUNCDW 1131 OpMIPSMOVFD 1132 OpMIPSMOVDF 1133 OpMIPSCALLstatic 1134 OpMIPSCALLclosure 1135 OpMIPSCALLdefer 1136 OpMIPSCALLgo 1137 OpMIPSCALLinter 1138 OpMIPSLoweredAtomicLoad 1139 OpMIPSLoweredAtomicStore 1140 OpMIPSLoweredAtomicStorezero 1141 OpMIPSLoweredAtomicExchange 1142 OpMIPSLoweredAtomicAdd 1143 OpMIPSLoweredAtomicAddconst 1144 OpMIPSLoweredAtomicCas 1145 OpMIPSLoweredAtomicAnd 1146 OpMIPSLoweredAtomicOr 1147 OpMIPSLoweredZero 1148 OpMIPSLoweredMove 1149 OpMIPSLoweredNilCheck 1150 OpMIPSFPFlagTrue 1151 OpMIPSFPFlagFalse 1152 OpMIPSLoweredGetClosurePtr 1153 OpMIPSMOVWconvert 1154 1155 OpMIPS64ADDV 1156 OpMIPS64ADDVconst 1157 OpMIPS64SUBV 1158 OpMIPS64SUBVconst 1159 OpMIPS64MULV 1160 OpMIPS64MULVU 1161 OpMIPS64DIVV 1162 OpMIPS64DIVVU 1163 OpMIPS64ADDF 1164 OpMIPS64ADDD 1165 OpMIPS64SUBF 1166 OpMIPS64SUBD 1167 OpMIPS64MULF 1168 OpMIPS64MULD 1169 OpMIPS64DIVF 1170 OpMIPS64DIVD 1171 OpMIPS64AND 1172 OpMIPS64ANDconst 1173 OpMIPS64OR 1174 OpMIPS64ORconst 1175 OpMIPS64XOR 1176 OpMIPS64XORconst 1177 OpMIPS64NOR 1178 OpMIPS64NORconst 1179 OpMIPS64NEGV 1180 OpMIPS64NEGF 1181 OpMIPS64NEGD 1182 OpMIPS64SLLV 1183 OpMIPS64SLLVconst 1184 OpMIPS64SRLV 1185 OpMIPS64SRLVconst 1186 OpMIPS64SRAV 1187 OpMIPS64SRAVconst 1188 OpMIPS64SGT 1189 OpMIPS64SGTconst 1190 OpMIPS64SGTU 1191 OpMIPS64SGTUconst 1192 OpMIPS64CMPEQF 1193 OpMIPS64CMPEQD 1194 OpMIPS64CMPGEF 1195 OpMIPS64CMPGED 1196 OpMIPS64CMPGTF 1197 OpMIPS64CMPGTD 1198 OpMIPS64MOVVconst 1199 OpMIPS64MOVFconst 1200 OpMIPS64MOVDconst 1201 OpMIPS64MOVVaddr 1202 OpMIPS64MOVBload 1203 OpMIPS64MOVBUload 1204 OpMIPS64MOVHload 1205 OpMIPS64MOVHUload 1206 OpMIPS64MOVWload 1207 OpMIPS64MOVWUload 1208 OpMIPS64MOVVload 1209 OpMIPS64MOVFload 1210 OpMIPS64MOVDload 1211 OpMIPS64MOVBstore 1212 OpMIPS64MOVHstore 1213 OpMIPS64MOVWstore 1214 OpMIPS64MOVVstore 1215 OpMIPS64MOVFstore 1216 OpMIPS64MOVDstore 1217 OpMIPS64MOVBstorezero 1218 OpMIPS64MOVHstorezero 1219 OpMIPS64MOVWstorezero 1220 OpMIPS64MOVVstorezero 1221 OpMIPS64MOVBreg 1222 OpMIPS64MOVBUreg 1223 OpMIPS64MOVHreg 1224 OpMIPS64MOVHUreg 1225 OpMIPS64MOVWreg 1226 OpMIPS64MOVWUreg 1227 OpMIPS64MOVVreg 1228 OpMIPS64MOVVnop 1229 OpMIPS64MOVWF 1230 OpMIPS64MOVWD 1231 OpMIPS64MOVVF 1232 OpMIPS64MOVVD 1233 OpMIPS64TRUNCFW 1234 OpMIPS64TRUNCDW 1235 OpMIPS64TRUNCFV 1236 OpMIPS64TRUNCDV 1237 OpMIPS64MOVFD 1238 OpMIPS64MOVDF 1239 OpMIPS64CALLstatic 1240 OpMIPS64CALLclosure 1241 OpMIPS64CALLdefer 1242 OpMIPS64CALLgo 1243 OpMIPS64CALLinter 1244 OpMIPS64DUFFZERO 1245 OpMIPS64LoweredZero 1246 OpMIPS64LoweredMove 1247 OpMIPS64LoweredNilCheck 1248 OpMIPS64FPFlagTrue 1249 OpMIPS64FPFlagFalse 1250 OpMIPS64LoweredGetClosurePtr 1251 OpMIPS64MOVVconvert 1252 1253 OpPPC64ADD 1254 OpPPC64ADDconst 1255 OpPPC64FADD 1256 OpPPC64FADDS 1257 OpPPC64SUB 1258 OpPPC64FSUB 1259 OpPPC64FSUBS 1260 OpPPC64MULLD 1261 OpPPC64MULLW 1262 OpPPC64MULHD 1263 OpPPC64MULHW 1264 OpPPC64MULHDU 1265 OpPPC64MULHWU 1266 OpPPC64FMUL 1267 OpPPC64FMULS 1268 OpPPC64SRAD 1269 OpPPC64SRAW 1270 OpPPC64SRD 1271 OpPPC64SRW 1272 OpPPC64SLD 1273 OpPPC64SLW 1274 OpPPC64ADDconstForCarry 1275 OpPPC64MaskIfNotCarry 1276 OpPPC64SRADconst 1277 OpPPC64SRAWconst 1278 OpPPC64SRDconst 1279 OpPPC64SRWconst 1280 OpPPC64SLDconst 1281 OpPPC64SLWconst 1282 OpPPC64FDIV 1283 OpPPC64FDIVS 1284 OpPPC64DIVD 1285 OpPPC64DIVW 1286 OpPPC64DIVDU 1287 OpPPC64DIVWU 1288 OpPPC64FCTIDZ 1289 OpPPC64FCTIWZ 1290 OpPPC64FCFID 1291 OpPPC64FRSP 1292 OpPPC64Xf2i64 1293 OpPPC64Xi2f64 1294 OpPPC64AND 1295 OpPPC64ANDN 1296 OpPPC64OR 1297 OpPPC64ORN 1298 OpPPC64XOR 1299 OpPPC64EQV 1300 OpPPC64NEG 1301 OpPPC64FNEG 1302 OpPPC64FSQRT 1303 OpPPC64FSQRTS 1304 OpPPC64ORconst 1305 OpPPC64XORconst 1306 OpPPC64ANDconst 1307 OpPPC64ANDCCconst 1308 OpPPC64MOVBreg 1309 OpPPC64MOVBZreg 1310 OpPPC64MOVHreg 1311 OpPPC64MOVHZreg 1312 OpPPC64MOVWreg 1313 OpPPC64MOVWZreg 1314 OpPPC64MOVBZload 1315 OpPPC64MOVHload 1316 OpPPC64MOVHZload 1317 OpPPC64MOVWload 1318 OpPPC64MOVWZload 1319 OpPPC64MOVDload 1320 OpPPC64FMOVDload 1321 OpPPC64FMOVSload 1322 OpPPC64MOVBstore 1323 OpPPC64MOVHstore 1324 OpPPC64MOVWstore 1325 OpPPC64MOVDstore 1326 OpPPC64FMOVDstore 1327 OpPPC64FMOVSstore 1328 OpPPC64MOVBstorezero 1329 OpPPC64MOVHstorezero 1330 OpPPC64MOVWstorezero 1331 OpPPC64MOVDstorezero 1332 OpPPC64MOVDaddr 1333 OpPPC64MOVDconst 1334 OpPPC64FMOVDconst 1335 OpPPC64FMOVSconst 1336 OpPPC64FCMPU 1337 OpPPC64CMP 1338 OpPPC64CMPU 1339 OpPPC64CMPW 1340 OpPPC64CMPWU 1341 OpPPC64CMPconst 1342 OpPPC64CMPUconst 1343 OpPPC64CMPWconst 1344 OpPPC64CMPWUconst 1345 OpPPC64Equal 1346 OpPPC64NotEqual 1347 OpPPC64LessThan 1348 OpPPC64FLessThan 1349 OpPPC64LessEqual 1350 OpPPC64FLessEqual 1351 OpPPC64GreaterThan 1352 OpPPC64FGreaterThan 1353 OpPPC64GreaterEqual 1354 OpPPC64FGreaterEqual 1355 OpPPC64LoweredGetClosurePtr 1356 OpPPC64LoweredNilCheck 1357 OpPPC64MOVDconvert 1358 OpPPC64CALLstatic 1359 OpPPC64CALLclosure 1360 OpPPC64CALLdefer 1361 OpPPC64CALLgo 1362 OpPPC64CALLinter 1363 OpPPC64LoweredZero 1364 OpPPC64LoweredMove 1365 OpPPC64InvertFlags 1366 OpPPC64FlagEQ 1367 OpPPC64FlagLT 1368 OpPPC64FlagGT 1369 1370 OpRISCVADD 1371 OpRISCVADDI 1372 OpRISCVSUB 1373 OpRISCVMUL 1374 OpRISCVMULW 1375 OpRISCVMULH 1376 OpRISCVMULHU 1377 OpRISCVDIV 1378 OpRISCVDIVU 1379 OpRISCVDIVW 1380 OpRISCVDIVUW 1381 OpRISCVREM 1382 OpRISCVREMU 1383 OpRISCVREMW 1384 OpRISCVREMUW 1385 OpRISCVMOVaddr 1386 OpRISCVMOVBconst 1387 OpRISCVMOVHconst 1388 OpRISCVMOVWconst 1389 OpRISCVMOVDconst 1390 OpRISCVMOVSconst 1391 OpRISCVMOVBload 1392 OpRISCVMOVHload 1393 OpRISCVMOVWload 1394 OpRISCVMOVDload 1395 OpRISCVMOVBUload 1396 OpRISCVMOVHUload 1397 OpRISCVMOVWUload 1398 OpRISCVMOVBstore 1399 OpRISCVMOVHstore 1400 OpRISCVMOVWstore 1401 OpRISCVMOVDstore 1402 OpRISCVSLL 1403 OpRISCVSRA 1404 OpRISCVSRL 1405 OpRISCVSLLI 1406 OpRISCVSRAI 1407 OpRISCVSRLI 1408 OpRISCVXOR 1409 OpRISCVXORI 1410 OpRISCVOR 1411 OpRISCVORI 1412 OpRISCVAND 1413 OpRISCVANDI 1414 OpRISCVSEQZ 1415 OpRISCVSNEZ 1416 OpRISCVSLT 1417 OpRISCVSLTI 1418 OpRISCVSLTU 1419 OpRISCVSLTIU 1420 OpRISCVMOVconvert 1421 OpRISCVCALLstatic 1422 OpRISCVCALLclosure 1423 OpRISCVCALLdefer 1424 OpRISCVCALLgo 1425 OpRISCVCALLinter 1426 OpRISCVLoweredZero 1427 OpRISCVLoweredMove 1428 OpRISCVLoweredNilCheck 1429 OpRISCVLoweredGetClosurePtr 1430 OpRISCVFADDS 1431 OpRISCVFSUBS 1432 OpRISCVFMULS 1433 OpRISCVFDIVS 1434 OpRISCVFSQRTS 1435 OpRISCVFNEGS 1436 OpRISCVFMVSX 1437 OpRISCVFCVTSW 1438 OpRISCVFCVTSL 1439 OpRISCVFCVTWS 1440 OpRISCVFCVTLS 1441 OpRISCVFMOVWload 1442 OpRISCVFMOVWstore 1443 OpRISCVFEQS 1444 OpRISCVFNES 1445 OpRISCVFLTS 1446 OpRISCVFLES 1447 OpRISCVFADDD 1448 OpRISCVFSUBD 1449 OpRISCVFMULD 1450 OpRISCVFDIVD 1451 OpRISCVFSQRTD 1452 OpRISCVFNEGD 1453 OpRISCVFMVDX 1454 OpRISCVFCVTDW 1455 OpRISCVFCVTDL 1456 OpRISCVFCVTWD 1457 OpRISCVFCVTLD 1458 OpRISCVFCVTDS 1459 OpRISCVFCVTSD 1460 OpRISCVFMOVDload 1461 OpRISCVFMOVDstore 1462 OpRISCVFEQD 1463 OpRISCVFNED 1464 OpRISCVFLTD 1465 OpRISCVFLED 1466 1467 OpS390XFADDS 1468 OpS390XFADD 1469 OpS390XFSUBS 1470 OpS390XFSUB 1471 OpS390XFMULS 1472 OpS390XFMUL 1473 OpS390XFDIVS 1474 OpS390XFDIV 1475 OpS390XFNEGS 1476 OpS390XFNEG 1477 OpS390XFMOVSload 1478 OpS390XFMOVDload 1479 OpS390XFMOVSconst 1480 OpS390XFMOVDconst 1481 OpS390XFMOVSloadidx 1482 OpS390XFMOVDloadidx 1483 OpS390XFMOVSstore 1484 OpS390XFMOVDstore 1485 OpS390XFMOVSstoreidx 1486 OpS390XFMOVDstoreidx 1487 OpS390XADD 1488 OpS390XADDW 1489 OpS390XADDconst 1490 OpS390XADDWconst 1491 OpS390XADDload 1492 OpS390XADDWload 1493 OpS390XSUB 1494 OpS390XSUBW 1495 OpS390XSUBconst 1496 OpS390XSUBWconst 1497 OpS390XSUBload 1498 OpS390XSUBWload 1499 OpS390XMULLD 1500 OpS390XMULLW 1501 OpS390XMULLDconst 1502 OpS390XMULLWconst 1503 OpS390XMULLDload 1504 OpS390XMULLWload 1505 OpS390XMULHD 1506 OpS390XMULHDU 1507 OpS390XDIVD 1508 OpS390XDIVW 1509 OpS390XDIVDU 1510 OpS390XDIVWU 1511 OpS390XMODD 1512 OpS390XMODW 1513 OpS390XMODDU 1514 OpS390XMODWU 1515 OpS390XAND 1516 OpS390XANDW 1517 OpS390XANDconst 1518 OpS390XANDWconst 1519 OpS390XANDload 1520 OpS390XANDWload 1521 OpS390XOR 1522 OpS390XORW 1523 OpS390XORconst 1524 OpS390XORWconst 1525 OpS390XORload 1526 OpS390XORWload 1527 OpS390XXOR 1528 OpS390XXORW 1529 OpS390XXORconst 1530 OpS390XXORWconst 1531 OpS390XXORload 1532 OpS390XXORWload 1533 OpS390XCMP 1534 OpS390XCMPW 1535 OpS390XCMPU 1536 OpS390XCMPWU 1537 OpS390XCMPconst 1538 OpS390XCMPWconst 1539 OpS390XCMPUconst 1540 OpS390XCMPWUconst 1541 OpS390XFCMPS 1542 OpS390XFCMP 1543 OpS390XSLD 1544 OpS390XSLW 1545 OpS390XSLDconst 1546 OpS390XSLWconst 1547 OpS390XSRD 1548 OpS390XSRW 1549 OpS390XSRDconst 1550 OpS390XSRWconst 1551 OpS390XSRAD 1552 OpS390XSRAW 1553 OpS390XSRADconst 1554 OpS390XSRAWconst 1555 OpS390XRLLGconst 1556 OpS390XRLLconst 1557 OpS390XNEG 1558 OpS390XNEGW 1559 OpS390XNOT 1560 OpS390XNOTW 1561 OpS390XFSQRT 1562 OpS390XSUBEcarrymask 1563 OpS390XSUBEWcarrymask 1564 OpS390XMOVDEQ 1565 OpS390XMOVDNE 1566 OpS390XMOVDLT 1567 OpS390XMOVDLE 1568 OpS390XMOVDGT 1569 OpS390XMOVDGE 1570 OpS390XMOVDGTnoinv 1571 OpS390XMOVDGEnoinv 1572 OpS390XMOVBreg 1573 OpS390XMOVBZreg 1574 OpS390XMOVHreg 1575 OpS390XMOVHZreg 1576 OpS390XMOVWreg 1577 OpS390XMOVWZreg 1578 OpS390XMOVDreg 1579 OpS390XMOVDnop 1580 OpS390XMOVDconst 1581 OpS390XCFDBRA 1582 OpS390XCGDBRA 1583 OpS390XCFEBRA 1584 OpS390XCGEBRA 1585 OpS390XCEFBRA 1586 OpS390XCDFBRA 1587 OpS390XCEGBRA 1588 OpS390XCDGBRA 1589 OpS390XLEDBR 1590 OpS390XLDEBR 1591 OpS390XMOVDaddr 1592 OpS390XMOVDaddridx 1593 OpS390XMOVBZload 1594 OpS390XMOVBload 1595 OpS390XMOVHZload 1596 OpS390XMOVHload 1597 OpS390XMOVWZload 1598 OpS390XMOVWload 1599 OpS390XMOVDload 1600 OpS390XMOVWBR 1601 OpS390XMOVDBR 1602 OpS390XMOVHBRload 1603 OpS390XMOVWBRload 1604 OpS390XMOVDBRload 1605 OpS390XMOVBstore 1606 OpS390XMOVHstore 1607 OpS390XMOVWstore 1608 OpS390XMOVDstore 1609 OpS390XMOVHBRstore 1610 OpS390XMOVWBRstore 1611 OpS390XMOVDBRstore 1612 OpS390XMVC 1613 OpS390XMOVBZloadidx 1614 OpS390XMOVHZloadidx 1615 OpS390XMOVWZloadidx 1616 OpS390XMOVDloadidx 1617 OpS390XMOVHBRloadidx 1618 OpS390XMOVWBRloadidx 1619 OpS390XMOVDBRloadidx 1620 OpS390XMOVBstoreidx 1621 OpS390XMOVHstoreidx 1622 OpS390XMOVWstoreidx 1623 OpS390XMOVDstoreidx 1624 OpS390XMOVHBRstoreidx 1625 OpS390XMOVWBRstoreidx 1626 OpS390XMOVDBRstoreidx 1627 OpS390XMOVBstoreconst 1628 OpS390XMOVHstoreconst 1629 OpS390XMOVWstoreconst 1630 OpS390XMOVDstoreconst 1631 OpS390XCLEAR 1632 OpS390XCALLstatic 1633 OpS390XCALLclosure 1634 OpS390XCALLdefer 1635 OpS390XCALLgo 1636 OpS390XCALLinter 1637 OpS390XInvertFlags 1638 OpS390XLoweredGetG 1639 OpS390XLoweredGetClosurePtr 1640 OpS390XLoweredNilCheck 1641 OpS390XMOVDconvert 1642 OpS390XFlagEQ 1643 OpS390XFlagLT 1644 OpS390XFlagGT 1645 OpS390XMOVWZatomicload 1646 OpS390XMOVDatomicload 1647 OpS390XMOVWatomicstore 1648 OpS390XMOVDatomicstore 1649 OpS390XLAA 1650 OpS390XLAAG 1651 OpS390XAddTupleFirst32 1652 OpS390XAddTupleFirst64 1653 OpS390XLoweredAtomicCas32 1654 OpS390XLoweredAtomicCas64 1655 OpS390XLoweredAtomicExchange32 1656 OpS390XLoweredAtomicExchange64 1657 OpS390XFLOGR 1658 OpS390XSTMG2 1659 OpS390XSTMG3 1660 OpS390XSTMG4 1661 OpS390XSTM2 1662 OpS390XSTM3 1663 OpS390XSTM4 1664 OpS390XLoweredMove 1665 OpS390XLoweredZero 1666 1667 OpAdd8 1668 OpAdd16 1669 OpAdd32 1670 OpAdd64 1671 OpAddPtr 1672 OpAdd32F 1673 OpAdd64F 1674 OpSub8 1675 OpSub16 1676 OpSub32 1677 OpSub64 1678 OpSubPtr 1679 OpSub32F 1680 OpSub64F 1681 OpMul8 1682 OpMul16 1683 OpMul32 1684 OpMul64 1685 OpMul32F 1686 OpMul64F 1687 OpDiv32F 1688 OpDiv64F 1689 OpHmul8 1690 OpHmul8u 1691 OpHmul16 1692 OpHmul16u 1693 OpHmul32 1694 OpHmul32u 1695 OpHmul64 1696 OpHmul64u 1697 OpMul32uhilo 1698 OpMul64uhilo 1699 OpAvg64u 1700 OpDiv8 1701 OpDiv8u 1702 OpDiv16 1703 OpDiv16u 1704 OpDiv32 1705 OpDiv32u 1706 OpDiv64 1707 OpDiv64u 1708 OpDiv128u 1709 OpMod8 1710 OpMod8u 1711 OpMod16 1712 OpMod16u 1713 OpMod32 1714 OpMod32u 1715 OpMod64 1716 OpMod64u 1717 OpAnd8 1718 OpAnd16 1719 OpAnd32 1720 OpAnd64 1721 OpOr8 1722 OpOr16 1723 OpOr32 1724 OpOr64 1725 OpXor8 1726 OpXor16 1727 OpXor32 1728 OpXor64 1729 OpLsh8x8 1730 OpLsh8x16 1731 OpLsh8x32 1732 OpLsh8x64 1733 OpLsh16x8 1734 OpLsh16x16 1735 OpLsh16x32 1736 OpLsh16x64 1737 OpLsh32x8 1738 OpLsh32x16 1739 OpLsh32x32 1740 OpLsh32x64 1741 OpLsh64x8 1742 OpLsh64x16 1743 OpLsh64x32 1744 OpLsh64x64 1745 OpRsh8x8 1746 OpRsh8x16 1747 OpRsh8x32 1748 OpRsh8x64 1749 OpRsh16x8 1750 OpRsh16x16 1751 OpRsh16x32 1752 OpRsh16x64 1753 OpRsh32x8 1754 OpRsh32x16 1755 OpRsh32x32 1756 OpRsh32x64 1757 OpRsh64x8 1758 OpRsh64x16 1759 OpRsh64x32 1760 OpRsh64x64 1761 OpRsh8Ux8 1762 OpRsh8Ux16 1763 OpRsh8Ux32 1764 OpRsh8Ux64 1765 OpRsh16Ux8 1766 OpRsh16Ux16 1767 OpRsh16Ux32 1768 OpRsh16Ux64 1769 OpRsh32Ux8 1770 OpRsh32Ux16 1771 OpRsh32Ux32 1772 OpRsh32Ux64 1773 OpRsh64Ux8 1774 OpRsh64Ux16 1775 OpRsh64Ux32 1776 OpRsh64Ux64 1777 OpEq8 1778 OpEq16 1779 OpEq32 1780 OpEq64 1781 OpEqPtr 1782 OpEqInter 1783 OpEqSlice 1784 OpEq32F 1785 OpEq64F 1786 OpNeq8 1787 OpNeq16 1788 OpNeq32 1789 OpNeq64 1790 OpNeqPtr 1791 OpNeqInter 1792 OpNeqSlice 1793 OpNeq32F 1794 OpNeq64F 1795 OpLess8 1796 OpLess8U 1797 OpLess16 1798 OpLess16U 1799 OpLess32 1800 OpLess32U 1801 OpLess64 1802 OpLess64U 1803 OpLess32F 1804 OpLess64F 1805 OpLeq8 1806 OpLeq8U 1807 OpLeq16 1808 OpLeq16U 1809 OpLeq32 1810 OpLeq32U 1811 OpLeq64 1812 OpLeq64U 1813 OpLeq32F 1814 OpLeq64F 1815 OpGreater8 1816 OpGreater8U 1817 OpGreater16 1818 OpGreater16U 1819 OpGreater32 1820 OpGreater32U 1821 OpGreater64 1822 OpGreater64U 1823 OpGreater32F 1824 OpGreater64F 1825 OpGeq8 1826 OpGeq8U 1827 OpGeq16 1828 OpGeq16U 1829 OpGeq32 1830 OpGeq32U 1831 OpGeq64 1832 OpGeq64U 1833 OpGeq32F 1834 OpGeq64F 1835 OpAndB 1836 OpOrB 1837 OpEqB 1838 OpNeqB 1839 OpNot 1840 OpNeg8 1841 OpNeg16 1842 OpNeg32 1843 OpNeg64 1844 OpNeg32F 1845 OpNeg64F 1846 OpCom8 1847 OpCom16 1848 OpCom32 1849 OpCom64 1850 OpCtz32 1851 OpCtz64 1852 OpBswap32 1853 OpBswap64 1854 OpSqrt 1855 OpPhi 1856 OpCopy 1857 OpConvert 1858 OpConstBool 1859 OpConstString 1860 OpConstNil 1861 OpConst8 1862 OpConst16 1863 OpConst32 1864 OpConst64 1865 OpConst32F 1866 OpConst64F 1867 OpConstInterface 1868 OpConstSlice 1869 OpInitMem 1870 OpArg 1871 OpAddr 1872 OpSP 1873 OpSB 1874 OpFunc 1875 OpLoad 1876 OpStore 1877 OpMove 1878 OpZero 1879 OpStoreWB 1880 OpMoveWB 1881 OpMoveWBVolatile 1882 OpZeroWB 1883 OpClosureCall 1884 OpStaticCall 1885 OpDeferCall 1886 OpGoCall 1887 OpInterCall 1888 OpSignExt8to16 1889 OpSignExt8to32 1890 OpSignExt8to64 1891 OpSignExt16to32 1892 OpSignExt16to64 1893 OpSignExt32to64 1894 OpZeroExt8to16 1895 OpZeroExt8to32 1896 OpZeroExt8to64 1897 OpZeroExt16to32 1898 OpZeroExt16to64 1899 OpZeroExt32to64 1900 OpTrunc16to8 1901 OpTrunc32to8 1902 OpTrunc32to16 1903 OpTrunc64to8 1904 OpTrunc64to16 1905 OpTrunc64to32 1906 OpCvt32to32F 1907 OpCvt32to64F 1908 OpCvt64to32F 1909 OpCvt64to64F 1910 OpCvt32Fto32 1911 OpCvt32Fto64 1912 OpCvt64Fto32 1913 OpCvt64Fto64 1914 OpCvt32Fto64F 1915 OpCvt64Fto32F 1916 OpIsNonNil 1917 OpIsInBounds 1918 OpIsSliceInBounds 1919 OpNilCheck 1920 OpGetG 1921 OpGetClosurePtr 1922 OpPtrIndex 1923 OpOffPtr 1924 OpSliceMake 1925 OpSlicePtr 1926 OpSliceLen 1927 OpSliceCap 1928 OpComplexMake 1929 OpComplexReal 1930 OpComplexImag 1931 OpStringMake 1932 OpStringPtr 1933 OpStringLen 1934 OpIMake 1935 OpITab 1936 OpIData 1937 OpStructMake0 1938 OpStructMake1 1939 OpStructMake2 1940 OpStructMake3 1941 OpStructMake4 1942 OpStructSelect 1943 OpArrayMake0 1944 OpArrayMake1 1945 OpArraySelect 1946 OpStoreReg 1947 OpLoadReg 1948 OpFwdRef 1949 OpUnknown 1950 OpVarDef 1951 OpVarKill 1952 OpVarLive 1953 OpKeepAlive 1954 OpInt64Make 1955 OpInt64Hi 1956 OpInt64Lo 1957 OpAdd32carry 1958 OpAdd32withcarry 1959 OpSub32carry 1960 OpSub32withcarry 1961 OpSignmask 1962 OpZeromask 1963 OpSlicemask 1964 OpCvt32Uto32F 1965 OpCvt32Uto64F 1966 OpCvt32Fto32U 1967 OpCvt64Fto32U 1968 OpCvt64Uto32F 1969 OpCvt64Uto64F 1970 OpCvt32Fto64U 1971 OpCvt64Fto64U 1972 OpSelect0 1973 OpSelect1 1974 OpAtomicLoad32 1975 OpAtomicLoad64 1976 OpAtomicLoadPtr 1977 OpAtomicStore32 1978 OpAtomicStore64 1979 OpAtomicStorePtrNoWB 1980 OpAtomicExchange32 1981 OpAtomicExchange64 1982 OpAtomicAdd32 1983 OpAtomicAdd64 1984 OpAtomicCompareAndSwap32 1985 OpAtomicCompareAndSwap64 1986 OpAtomicAnd8 1987 OpAtomicOr8 1988 ) 1989 1990 var opcodeTable = [...]opInfo{ 1991 {name: "OpInvalid"}, 1992 1993 { 1994 name: "ADDSS", 1995 argLen: 2, 1996 commutative: true, 1997 resultInArg0: true, 1998 usesScratch: true, 1999 asm: x86.AADDSS, 2000 reg: regInfo{ 2001 inputs: []inputInfo{ 2002 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2003 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2004 }, 2005 outputs: []outputInfo{ 2006 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2007 }, 2008 }, 2009 }, 2010 { 2011 name: "ADDSD", 2012 argLen: 2, 2013 commutative: true, 2014 resultInArg0: true, 2015 asm: x86.AADDSD, 2016 reg: regInfo{ 2017 inputs: []inputInfo{ 2018 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2019 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2020 }, 2021 outputs: []outputInfo{ 2022 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2023 }, 2024 }, 2025 }, 2026 { 2027 name: "SUBSS", 2028 argLen: 2, 2029 resultInArg0: true, 2030 usesScratch: true, 2031 asm: x86.ASUBSS, 2032 reg: regInfo{ 2033 inputs: []inputInfo{ 2034 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2035 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2036 }, 2037 outputs: []outputInfo{ 2038 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2039 }, 2040 }, 2041 }, 2042 { 2043 name: "SUBSD", 2044 argLen: 2, 2045 resultInArg0: true, 2046 asm: x86.ASUBSD, 2047 reg: regInfo{ 2048 inputs: []inputInfo{ 2049 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2050 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2051 }, 2052 outputs: []outputInfo{ 2053 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2054 }, 2055 }, 2056 }, 2057 { 2058 name: "MULSS", 2059 argLen: 2, 2060 commutative: true, 2061 resultInArg0: true, 2062 usesScratch: true, 2063 asm: x86.AMULSS, 2064 reg: regInfo{ 2065 inputs: []inputInfo{ 2066 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2067 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2068 }, 2069 outputs: []outputInfo{ 2070 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2071 }, 2072 }, 2073 }, 2074 { 2075 name: "MULSD", 2076 argLen: 2, 2077 commutative: true, 2078 resultInArg0: true, 2079 asm: x86.AMULSD, 2080 reg: regInfo{ 2081 inputs: []inputInfo{ 2082 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2083 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2084 }, 2085 outputs: []outputInfo{ 2086 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2087 }, 2088 }, 2089 }, 2090 { 2091 name: "DIVSS", 2092 argLen: 2, 2093 resultInArg0: true, 2094 usesScratch: true, 2095 asm: x86.ADIVSS, 2096 reg: regInfo{ 2097 inputs: []inputInfo{ 2098 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2099 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2100 }, 2101 outputs: []outputInfo{ 2102 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2103 }, 2104 }, 2105 }, 2106 { 2107 name: "DIVSD", 2108 argLen: 2, 2109 resultInArg0: true, 2110 asm: x86.ADIVSD, 2111 reg: regInfo{ 2112 inputs: []inputInfo{ 2113 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2114 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2115 }, 2116 outputs: []outputInfo{ 2117 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2118 }, 2119 }, 2120 }, 2121 { 2122 name: "MOVSSload", 2123 auxType: auxSymOff, 2124 argLen: 2, 2125 faultOnNilArg0: true, 2126 asm: x86.AMOVSS, 2127 reg: regInfo{ 2128 inputs: []inputInfo{ 2129 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2130 }, 2131 outputs: []outputInfo{ 2132 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2133 }, 2134 }, 2135 }, 2136 { 2137 name: "MOVSDload", 2138 auxType: auxSymOff, 2139 argLen: 2, 2140 faultOnNilArg0: true, 2141 asm: x86.AMOVSD, 2142 reg: regInfo{ 2143 inputs: []inputInfo{ 2144 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2145 }, 2146 outputs: []outputInfo{ 2147 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2148 }, 2149 }, 2150 }, 2151 { 2152 name: "MOVSSconst", 2153 auxType: auxFloat32, 2154 argLen: 0, 2155 rematerializeable: true, 2156 asm: x86.AMOVSS, 2157 reg: regInfo{ 2158 outputs: []outputInfo{ 2159 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2160 }, 2161 }, 2162 }, 2163 { 2164 name: "MOVSDconst", 2165 auxType: auxFloat64, 2166 argLen: 0, 2167 rematerializeable: true, 2168 asm: x86.AMOVSD, 2169 reg: regInfo{ 2170 outputs: []outputInfo{ 2171 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2172 }, 2173 }, 2174 }, 2175 { 2176 name: "MOVSSloadidx1", 2177 auxType: auxSymOff, 2178 argLen: 3, 2179 asm: x86.AMOVSS, 2180 reg: regInfo{ 2181 inputs: []inputInfo{ 2182 {1, 255}, // AX CX DX BX SP BP SI DI 2183 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2184 }, 2185 outputs: []outputInfo{ 2186 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2187 }, 2188 }, 2189 }, 2190 { 2191 name: "MOVSSloadidx4", 2192 auxType: auxSymOff, 2193 argLen: 3, 2194 asm: x86.AMOVSS, 2195 reg: regInfo{ 2196 inputs: []inputInfo{ 2197 {1, 255}, // AX CX DX BX SP BP SI DI 2198 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2199 }, 2200 outputs: []outputInfo{ 2201 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2202 }, 2203 }, 2204 }, 2205 { 2206 name: "MOVSDloadidx1", 2207 auxType: auxSymOff, 2208 argLen: 3, 2209 asm: x86.AMOVSD, 2210 reg: regInfo{ 2211 inputs: []inputInfo{ 2212 {1, 255}, // AX CX DX BX SP BP SI DI 2213 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2214 }, 2215 outputs: []outputInfo{ 2216 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2217 }, 2218 }, 2219 }, 2220 { 2221 name: "MOVSDloadidx8", 2222 auxType: auxSymOff, 2223 argLen: 3, 2224 asm: x86.AMOVSD, 2225 reg: regInfo{ 2226 inputs: []inputInfo{ 2227 {1, 255}, // AX CX DX BX SP BP SI DI 2228 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2229 }, 2230 outputs: []outputInfo{ 2231 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2232 }, 2233 }, 2234 }, 2235 { 2236 name: "MOVSSstore", 2237 auxType: auxSymOff, 2238 argLen: 3, 2239 faultOnNilArg0: true, 2240 asm: x86.AMOVSS, 2241 reg: regInfo{ 2242 inputs: []inputInfo{ 2243 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2244 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2245 }, 2246 }, 2247 }, 2248 { 2249 name: "MOVSDstore", 2250 auxType: auxSymOff, 2251 argLen: 3, 2252 faultOnNilArg0: true, 2253 asm: x86.AMOVSD, 2254 reg: regInfo{ 2255 inputs: []inputInfo{ 2256 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2257 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2258 }, 2259 }, 2260 }, 2261 { 2262 name: "MOVSSstoreidx1", 2263 auxType: auxSymOff, 2264 argLen: 4, 2265 asm: x86.AMOVSS, 2266 reg: regInfo{ 2267 inputs: []inputInfo{ 2268 {1, 255}, // AX CX DX BX SP BP SI DI 2269 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2270 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2271 }, 2272 }, 2273 }, 2274 { 2275 name: "MOVSSstoreidx4", 2276 auxType: auxSymOff, 2277 argLen: 4, 2278 asm: x86.AMOVSS, 2279 reg: regInfo{ 2280 inputs: []inputInfo{ 2281 {1, 255}, // AX CX DX BX SP BP SI DI 2282 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2283 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2284 }, 2285 }, 2286 }, 2287 { 2288 name: "MOVSDstoreidx1", 2289 auxType: auxSymOff, 2290 argLen: 4, 2291 asm: x86.AMOVSD, 2292 reg: regInfo{ 2293 inputs: []inputInfo{ 2294 {1, 255}, // AX CX DX BX SP BP SI DI 2295 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2296 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2297 }, 2298 }, 2299 }, 2300 { 2301 name: "MOVSDstoreidx8", 2302 auxType: auxSymOff, 2303 argLen: 4, 2304 asm: x86.AMOVSD, 2305 reg: regInfo{ 2306 inputs: []inputInfo{ 2307 {1, 255}, // AX CX DX BX SP BP SI DI 2308 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2309 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2310 }, 2311 }, 2312 }, 2313 { 2314 name: "ADDL", 2315 argLen: 2, 2316 commutative: true, 2317 clobberFlags: true, 2318 asm: x86.AADDL, 2319 reg: regInfo{ 2320 inputs: []inputInfo{ 2321 {1, 239}, // AX CX DX BX BP SI DI 2322 {0, 255}, // AX CX DX BX SP BP SI DI 2323 }, 2324 outputs: []outputInfo{ 2325 {0, 239}, // AX CX DX BX BP SI DI 2326 }, 2327 }, 2328 }, 2329 { 2330 name: "ADDLconst", 2331 auxType: auxInt32, 2332 argLen: 1, 2333 clobberFlags: true, 2334 asm: x86.AADDL, 2335 reg: regInfo{ 2336 inputs: []inputInfo{ 2337 {0, 255}, // AX CX DX BX SP BP SI DI 2338 }, 2339 outputs: []outputInfo{ 2340 {0, 239}, // AX CX DX BX BP SI DI 2341 }, 2342 }, 2343 }, 2344 { 2345 name: "ADDLcarry", 2346 argLen: 2, 2347 commutative: true, 2348 resultInArg0: true, 2349 asm: x86.AADDL, 2350 reg: regInfo{ 2351 inputs: []inputInfo{ 2352 {0, 239}, // AX CX DX BX BP SI DI 2353 {1, 239}, // AX CX DX BX BP SI DI 2354 }, 2355 outputs: []outputInfo{ 2356 {1, 0}, 2357 {0, 239}, // AX CX DX BX BP SI DI 2358 }, 2359 }, 2360 }, 2361 { 2362 name: "ADDLconstcarry", 2363 auxType: auxInt32, 2364 argLen: 1, 2365 resultInArg0: true, 2366 asm: x86.AADDL, 2367 reg: regInfo{ 2368 inputs: []inputInfo{ 2369 {0, 239}, // AX CX DX BX BP SI DI 2370 }, 2371 outputs: []outputInfo{ 2372 {1, 0}, 2373 {0, 239}, // AX CX DX BX BP SI DI 2374 }, 2375 }, 2376 }, 2377 { 2378 name: "ADCL", 2379 argLen: 3, 2380 commutative: true, 2381 resultInArg0: true, 2382 clobberFlags: true, 2383 asm: x86.AADCL, 2384 reg: regInfo{ 2385 inputs: []inputInfo{ 2386 {0, 239}, // AX CX DX BX BP SI DI 2387 {1, 239}, // AX CX DX BX BP SI DI 2388 }, 2389 outputs: []outputInfo{ 2390 {0, 239}, // AX CX DX BX BP SI DI 2391 }, 2392 }, 2393 }, 2394 { 2395 name: "ADCLconst", 2396 auxType: auxInt32, 2397 argLen: 2, 2398 resultInArg0: true, 2399 clobberFlags: true, 2400 asm: x86.AADCL, 2401 reg: regInfo{ 2402 inputs: []inputInfo{ 2403 {0, 239}, // AX CX DX BX BP SI DI 2404 }, 2405 outputs: []outputInfo{ 2406 {0, 239}, // AX CX DX BX BP SI DI 2407 }, 2408 }, 2409 }, 2410 { 2411 name: "SUBL", 2412 argLen: 2, 2413 resultInArg0: true, 2414 clobberFlags: true, 2415 asm: x86.ASUBL, 2416 reg: regInfo{ 2417 inputs: []inputInfo{ 2418 {0, 239}, // AX CX DX BX BP SI DI 2419 {1, 239}, // AX CX DX BX BP SI DI 2420 }, 2421 outputs: []outputInfo{ 2422 {0, 239}, // AX CX DX BX BP SI DI 2423 }, 2424 }, 2425 }, 2426 { 2427 name: "SUBLconst", 2428 auxType: auxInt32, 2429 argLen: 1, 2430 resultInArg0: true, 2431 clobberFlags: true, 2432 asm: x86.ASUBL, 2433 reg: regInfo{ 2434 inputs: []inputInfo{ 2435 {0, 239}, // AX CX DX BX BP SI DI 2436 }, 2437 outputs: []outputInfo{ 2438 {0, 239}, // AX CX DX BX BP SI DI 2439 }, 2440 }, 2441 }, 2442 { 2443 name: "SUBLcarry", 2444 argLen: 2, 2445 resultInArg0: true, 2446 asm: x86.ASUBL, 2447 reg: regInfo{ 2448 inputs: []inputInfo{ 2449 {0, 239}, // AX CX DX BX BP SI DI 2450 {1, 239}, // AX CX DX BX BP SI DI 2451 }, 2452 outputs: []outputInfo{ 2453 {1, 0}, 2454 {0, 239}, // AX CX DX BX BP SI DI 2455 }, 2456 }, 2457 }, 2458 { 2459 name: "SUBLconstcarry", 2460 auxType: auxInt32, 2461 argLen: 1, 2462 resultInArg0: true, 2463 asm: x86.ASUBL, 2464 reg: regInfo{ 2465 inputs: []inputInfo{ 2466 {0, 239}, // AX CX DX BX BP SI DI 2467 }, 2468 outputs: []outputInfo{ 2469 {1, 0}, 2470 {0, 239}, // AX CX DX BX BP SI DI 2471 }, 2472 }, 2473 }, 2474 { 2475 name: "SBBL", 2476 argLen: 3, 2477 resultInArg0: true, 2478 clobberFlags: true, 2479 asm: x86.ASBBL, 2480 reg: regInfo{ 2481 inputs: []inputInfo{ 2482 {0, 239}, // AX CX DX BX BP SI DI 2483 {1, 239}, // AX CX DX BX BP SI DI 2484 }, 2485 outputs: []outputInfo{ 2486 {0, 239}, // AX CX DX BX BP SI DI 2487 }, 2488 }, 2489 }, 2490 { 2491 name: "SBBLconst", 2492 auxType: auxInt32, 2493 argLen: 2, 2494 resultInArg0: true, 2495 clobberFlags: true, 2496 asm: x86.ASBBL, 2497 reg: regInfo{ 2498 inputs: []inputInfo{ 2499 {0, 239}, // AX CX DX BX BP SI DI 2500 }, 2501 outputs: []outputInfo{ 2502 {0, 239}, // AX CX DX BX BP SI DI 2503 }, 2504 }, 2505 }, 2506 { 2507 name: "MULL", 2508 argLen: 2, 2509 commutative: true, 2510 resultInArg0: true, 2511 clobberFlags: true, 2512 asm: x86.AIMULL, 2513 reg: regInfo{ 2514 inputs: []inputInfo{ 2515 {0, 239}, // AX CX DX BX BP SI DI 2516 {1, 239}, // AX CX DX BX BP SI DI 2517 }, 2518 outputs: []outputInfo{ 2519 {0, 239}, // AX CX DX BX BP SI DI 2520 }, 2521 }, 2522 }, 2523 { 2524 name: "MULLconst", 2525 auxType: auxInt32, 2526 argLen: 1, 2527 resultInArg0: true, 2528 clobberFlags: true, 2529 asm: x86.AIMULL, 2530 reg: regInfo{ 2531 inputs: []inputInfo{ 2532 {0, 239}, // AX CX DX BX BP SI DI 2533 }, 2534 outputs: []outputInfo{ 2535 {0, 239}, // AX CX DX BX BP SI DI 2536 }, 2537 }, 2538 }, 2539 { 2540 name: "HMULL", 2541 argLen: 2, 2542 clobberFlags: true, 2543 asm: x86.AIMULL, 2544 reg: regInfo{ 2545 inputs: []inputInfo{ 2546 {0, 1}, // AX 2547 {1, 255}, // AX CX DX BX SP BP SI DI 2548 }, 2549 clobbers: 1, // AX 2550 outputs: []outputInfo{ 2551 {0, 4}, // DX 2552 }, 2553 }, 2554 }, 2555 { 2556 name: "HMULLU", 2557 argLen: 2, 2558 clobberFlags: true, 2559 asm: x86.AMULL, 2560 reg: regInfo{ 2561 inputs: []inputInfo{ 2562 {0, 1}, // AX 2563 {1, 255}, // AX CX DX BX SP BP SI DI 2564 }, 2565 clobbers: 1, // AX 2566 outputs: []outputInfo{ 2567 {0, 4}, // DX 2568 }, 2569 }, 2570 }, 2571 { 2572 name: "HMULW", 2573 argLen: 2, 2574 clobberFlags: true, 2575 asm: x86.AIMULW, 2576 reg: regInfo{ 2577 inputs: []inputInfo{ 2578 {0, 1}, // AX 2579 {1, 255}, // AX CX DX BX SP BP SI DI 2580 }, 2581 clobbers: 1, // AX 2582 outputs: []outputInfo{ 2583 {0, 4}, // DX 2584 }, 2585 }, 2586 }, 2587 { 2588 name: "HMULB", 2589 argLen: 2, 2590 clobberFlags: true, 2591 asm: x86.AIMULB, 2592 reg: regInfo{ 2593 inputs: []inputInfo{ 2594 {0, 1}, // AX 2595 {1, 255}, // AX CX DX BX SP BP SI DI 2596 }, 2597 clobbers: 1, // AX 2598 outputs: []outputInfo{ 2599 {0, 4}, // DX 2600 }, 2601 }, 2602 }, 2603 { 2604 name: "HMULWU", 2605 argLen: 2, 2606 clobberFlags: true, 2607 asm: x86.AMULW, 2608 reg: regInfo{ 2609 inputs: []inputInfo{ 2610 {0, 1}, // AX 2611 {1, 255}, // AX CX DX BX SP BP SI DI 2612 }, 2613 clobbers: 1, // AX 2614 outputs: []outputInfo{ 2615 {0, 4}, // DX 2616 }, 2617 }, 2618 }, 2619 { 2620 name: "HMULBU", 2621 argLen: 2, 2622 clobberFlags: true, 2623 asm: x86.AMULB, 2624 reg: regInfo{ 2625 inputs: []inputInfo{ 2626 {0, 1}, // AX 2627 {1, 255}, // AX CX DX BX SP BP SI DI 2628 }, 2629 clobbers: 1, // AX 2630 outputs: []outputInfo{ 2631 {0, 4}, // DX 2632 }, 2633 }, 2634 }, 2635 { 2636 name: "MULLQU", 2637 argLen: 2, 2638 clobberFlags: true, 2639 asm: x86.AMULL, 2640 reg: regInfo{ 2641 inputs: []inputInfo{ 2642 {0, 1}, // AX 2643 {1, 255}, // AX CX DX BX SP BP SI DI 2644 }, 2645 outputs: []outputInfo{ 2646 {0, 4}, // DX 2647 {1, 1}, // AX 2648 }, 2649 }, 2650 }, 2651 { 2652 name: "DIVL", 2653 argLen: 2, 2654 clobberFlags: true, 2655 asm: x86.AIDIVL, 2656 reg: regInfo{ 2657 inputs: []inputInfo{ 2658 {0, 1}, // AX 2659 {1, 251}, // AX CX BX SP BP SI DI 2660 }, 2661 clobbers: 4, // DX 2662 outputs: []outputInfo{ 2663 {0, 1}, // AX 2664 }, 2665 }, 2666 }, 2667 { 2668 name: "DIVW", 2669 argLen: 2, 2670 clobberFlags: true, 2671 asm: x86.AIDIVW, 2672 reg: regInfo{ 2673 inputs: []inputInfo{ 2674 {0, 1}, // AX 2675 {1, 251}, // AX CX BX SP BP SI DI 2676 }, 2677 clobbers: 4, // DX 2678 outputs: []outputInfo{ 2679 {0, 1}, // AX 2680 }, 2681 }, 2682 }, 2683 { 2684 name: "DIVLU", 2685 argLen: 2, 2686 clobberFlags: true, 2687 asm: x86.ADIVL, 2688 reg: regInfo{ 2689 inputs: []inputInfo{ 2690 {0, 1}, // AX 2691 {1, 251}, // AX CX BX SP BP SI DI 2692 }, 2693 clobbers: 4, // DX 2694 outputs: []outputInfo{ 2695 {0, 1}, // AX 2696 }, 2697 }, 2698 }, 2699 { 2700 name: "DIVWU", 2701 argLen: 2, 2702 clobberFlags: true, 2703 asm: x86.ADIVW, 2704 reg: regInfo{ 2705 inputs: []inputInfo{ 2706 {0, 1}, // AX 2707 {1, 251}, // AX CX BX SP BP SI DI 2708 }, 2709 clobbers: 4, // DX 2710 outputs: []outputInfo{ 2711 {0, 1}, // AX 2712 }, 2713 }, 2714 }, 2715 { 2716 name: "MODL", 2717 argLen: 2, 2718 clobberFlags: true, 2719 asm: x86.AIDIVL, 2720 reg: regInfo{ 2721 inputs: []inputInfo{ 2722 {0, 1}, // AX 2723 {1, 251}, // AX CX BX SP BP SI DI 2724 }, 2725 clobbers: 1, // AX 2726 outputs: []outputInfo{ 2727 {0, 4}, // DX 2728 }, 2729 }, 2730 }, 2731 { 2732 name: "MODW", 2733 argLen: 2, 2734 clobberFlags: true, 2735 asm: x86.AIDIVW, 2736 reg: regInfo{ 2737 inputs: []inputInfo{ 2738 {0, 1}, // AX 2739 {1, 251}, // AX CX BX SP BP SI DI 2740 }, 2741 clobbers: 1, // AX 2742 outputs: []outputInfo{ 2743 {0, 4}, // DX 2744 }, 2745 }, 2746 }, 2747 { 2748 name: "MODLU", 2749 argLen: 2, 2750 clobberFlags: true, 2751 asm: x86.ADIVL, 2752 reg: regInfo{ 2753 inputs: []inputInfo{ 2754 {0, 1}, // AX 2755 {1, 251}, // AX CX BX SP BP SI DI 2756 }, 2757 clobbers: 1, // AX 2758 outputs: []outputInfo{ 2759 {0, 4}, // DX 2760 }, 2761 }, 2762 }, 2763 { 2764 name: "MODWU", 2765 argLen: 2, 2766 clobberFlags: true, 2767 asm: x86.ADIVW, 2768 reg: regInfo{ 2769 inputs: []inputInfo{ 2770 {0, 1}, // AX 2771 {1, 251}, // AX CX BX SP BP SI DI 2772 }, 2773 clobbers: 1, // AX 2774 outputs: []outputInfo{ 2775 {0, 4}, // DX 2776 }, 2777 }, 2778 }, 2779 { 2780 name: "ANDL", 2781 argLen: 2, 2782 commutative: true, 2783 resultInArg0: true, 2784 clobberFlags: true, 2785 asm: x86.AANDL, 2786 reg: regInfo{ 2787 inputs: []inputInfo{ 2788 {0, 239}, // AX CX DX BX BP SI DI 2789 {1, 239}, // AX CX DX BX BP SI DI 2790 }, 2791 outputs: []outputInfo{ 2792 {0, 239}, // AX CX DX BX BP SI DI 2793 }, 2794 }, 2795 }, 2796 { 2797 name: "ANDLconst", 2798 auxType: auxInt32, 2799 argLen: 1, 2800 resultInArg0: true, 2801 clobberFlags: true, 2802 asm: x86.AANDL, 2803 reg: regInfo{ 2804 inputs: []inputInfo{ 2805 {0, 239}, // AX CX DX BX BP SI DI 2806 }, 2807 outputs: []outputInfo{ 2808 {0, 239}, // AX CX DX BX BP SI DI 2809 }, 2810 }, 2811 }, 2812 { 2813 name: "ORL", 2814 argLen: 2, 2815 commutative: true, 2816 resultInArg0: true, 2817 clobberFlags: true, 2818 asm: x86.AORL, 2819 reg: regInfo{ 2820 inputs: []inputInfo{ 2821 {0, 239}, // AX CX DX BX BP SI DI 2822 {1, 239}, // AX CX DX BX BP SI DI 2823 }, 2824 outputs: []outputInfo{ 2825 {0, 239}, // AX CX DX BX BP SI DI 2826 }, 2827 }, 2828 }, 2829 { 2830 name: "ORLconst", 2831 auxType: auxInt32, 2832 argLen: 1, 2833 resultInArg0: true, 2834 clobberFlags: true, 2835 asm: x86.AORL, 2836 reg: regInfo{ 2837 inputs: []inputInfo{ 2838 {0, 239}, // AX CX DX BX BP SI DI 2839 }, 2840 outputs: []outputInfo{ 2841 {0, 239}, // AX CX DX BX BP SI DI 2842 }, 2843 }, 2844 }, 2845 { 2846 name: "XORL", 2847 argLen: 2, 2848 commutative: true, 2849 resultInArg0: true, 2850 clobberFlags: true, 2851 asm: x86.AXORL, 2852 reg: regInfo{ 2853 inputs: []inputInfo{ 2854 {0, 239}, // AX CX DX BX BP SI DI 2855 {1, 239}, // AX CX DX BX BP SI DI 2856 }, 2857 outputs: []outputInfo{ 2858 {0, 239}, // AX CX DX BX BP SI DI 2859 }, 2860 }, 2861 }, 2862 { 2863 name: "XORLconst", 2864 auxType: auxInt32, 2865 argLen: 1, 2866 resultInArg0: true, 2867 clobberFlags: true, 2868 asm: x86.AXORL, 2869 reg: regInfo{ 2870 inputs: []inputInfo{ 2871 {0, 239}, // AX CX DX BX BP SI DI 2872 }, 2873 outputs: []outputInfo{ 2874 {0, 239}, // AX CX DX BX BP SI DI 2875 }, 2876 }, 2877 }, 2878 { 2879 name: "CMPL", 2880 argLen: 2, 2881 asm: x86.ACMPL, 2882 reg: regInfo{ 2883 inputs: []inputInfo{ 2884 {0, 255}, // AX CX DX BX SP BP SI DI 2885 {1, 255}, // AX CX DX BX SP BP SI DI 2886 }, 2887 }, 2888 }, 2889 { 2890 name: "CMPW", 2891 argLen: 2, 2892 asm: x86.ACMPW, 2893 reg: regInfo{ 2894 inputs: []inputInfo{ 2895 {0, 255}, // AX CX DX BX SP BP SI DI 2896 {1, 255}, // AX CX DX BX SP BP SI DI 2897 }, 2898 }, 2899 }, 2900 { 2901 name: "CMPB", 2902 argLen: 2, 2903 asm: x86.ACMPB, 2904 reg: regInfo{ 2905 inputs: []inputInfo{ 2906 {0, 255}, // AX CX DX BX SP BP SI DI 2907 {1, 255}, // AX CX DX BX SP BP SI DI 2908 }, 2909 }, 2910 }, 2911 { 2912 name: "CMPLconst", 2913 auxType: auxInt32, 2914 argLen: 1, 2915 asm: x86.ACMPL, 2916 reg: regInfo{ 2917 inputs: []inputInfo{ 2918 {0, 255}, // AX CX DX BX SP BP SI DI 2919 }, 2920 }, 2921 }, 2922 { 2923 name: "CMPWconst", 2924 auxType: auxInt16, 2925 argLen: 1, 2926 asm: x86.ACMPW, 2927 reg: regInfo{ 2928 inputs: []inputInfo{ 2929 {0, 255}, // AX CX DX BX SP BP SI DI 2930 }, 2931 }, 2932 }, 2933 { 2934 name: "CMPBconst", 2935 auxType: auxInt8, 2936 argLen: 1, 2937 asm: x86.ACMPB, 2938 reg: regInfo{ 2939 inputs: []inputInfo{ 2940 {0, 255}, // AX CX DX BX SP BP SI DI 2941 }, 2942 }, 2943 }, 2944 { 2945 name: "UCOMISS", 2946 argLen: 2, 2947 usesScratch: true, 2948 asm: x86.AUCOMISS, 2949 reg: regInfo{ 2950 inputs: []inputInfo{ 2951 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2952 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2953 }, 2954 }, 2955 }, 2956 { 2957 name: "UCOMISD", 2958 argLen: 2, 2959 usesScratch: true, 2960 asm: x86.AUCOMISD, 2961 reg: regInfo{ 2962 inputs: []inputInfo{ 2963 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2964 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2965 }, 2966 }, 2967 }, 2968 { 2969 name: "TESTL", 2970 argLen: 2, 2971 asm: x86.ATESTL, 2972 reg: regInfo{ 2973 inputs: []inputInfo{ 2974 {0, 255}, // AX CX DX BX SP BP SI DI 2975 {1, 255}, // AX CX DX BX SP BP SI DI 2976 }, 2977 }, 2978 }, 2979 { 2980 name: "TESTW", 2981 argLen: 2, 2982 asm: x86.ATESTW, 2983 reg: regInfo{ 2984 inputs: []inputInfo{ 2985 {0, 255}, // AX CX DX BX SP BP SI DI 2986 {1, 255}, // AX CX DX BX SP BP SI DI 2987 }, 2988 }, 2989 }, 2990 { 2991 name: "TESTB", 2992 argLen: 2, 2993 asm: x86.ATESTB, 2994 reg: regInfo{ 2995 inputs: []inputInfo{ 2996 {0, 255}, // AX CX DX BX SP BP SI DI 2997 {1, 255}, // AX CX DX BX SP BP SI DI 2998 }, 2999 }, 3000 }, 3001 { 3002 name: "TESTLconst", 3003 auxType: auxInt32, 3004 argLen: 1, 3005 asm: x86.ATESTL, 3006 reg: regInfo{ 3007 inputs: []inputInfo{ 3008 {0, 255}, // AX CX DX BX SP BP SI DI 3009 }, 3010 }, 3011 }, 3012 { 3013 name: "TESTWconst", 3014 auxType: auxInt16, 3015 argLen: 1, 3016 asm: x86.ATESTW, 3017 reg: regInfo{ 3018 inputs: []inputInfo{ 3019 {0, 255}, // AX CX DX BX SP BP SI DI 3020 }, 3021 }, 3022 }, 3023 { 3024 name: "TESTBconst", 3025 auxType: auxInt8, 3026 argLen: 1, 3027 asm: x86.ATESTB, 3028 reg: regInfo{ 3029 inputs: []inputInfo{ 3030 {0, 255}, // AX CX DX BX SP BP SI DI 3031 }, 3032 }, 3033 }, 3034 { 3035 name: "SHLL", 3036 argLen: 2, 3037 resultInArg0: true, 3038 clobberFlags: true, 3039 asm: x86.ASHLL, 3040 reg: regInfo{ 3041 inputs: []inputInfo{ 3042 {1, 2}, // CX 3043 {0, 239}, // AX CX DX BX BP SI DI 3044 }, 3045 outputs: []outputInfo{ 3046 {0, 239}, // AX CX DX BX BP SI DI 3047 }, 3048 }, 3049 }, 3050 { 3051 name: "SHLLconst", 3052 auxType: auxInt32, 3053 argLen: 1, 3054 resultInArg0: true, 3055 clobberFlags: true, 3056 asm: x86.ASHLL, 3057 reg: regInfo{ 3058 inputs: []inputInfo{ 3059 {0, 239}, // AX CX DX BX BP SI DI 3060 }, 3061 outputs: []outputInfo{ 3062 {0, 239}, // AX CX DX BX BP SI DI 3063 }, 3064 }, 3065 }, 3066 { 3067 name: "SHRL", 3068 argLen: 2, 3069 resultInArg0: true, 3070 clobberFlags: true, 3071 asm: x86.ASHRL, 3072 reg: regInfo{ 3073 inputs: []inputInfo{ 3074 {1, 2}, // CX 3075 {0, 239}, // AX CX DX BX BP SI DI 3076 }, 3077 outputs: []outputInfo{ 3078 {0, 239}, // AX CX DX BX BP SI DI 3079 }, 3080 }, 3081 }, 3082 { 3083 name: "SHRW", 3084 argLen: 2, 3085 resultInArg0: true, 3086 clobberFlags: true, 3087 asm: x86.ASHRW, 3088 reg: regInfo{ 3089 inputs: []inputInfo{ 3090 {1, 2}, // CX 3091 {0, 239}, // AX CX DX BX BP SI DI 3092 }, 3093 outputs: []outputInfo{ 3094 {0, 239}, // AX CX DX BX BP SI DI 3095 }, 3096 }, 3097 }, 3098 { 3099 name: "SHRB", 3100 argLen: 2, 3101 resultInArg0: true, 3102 clobberFlags: true, 3103 asm: x86.ASHRB, 3104 reg: regInfo{ 3105 inputs: []inputInfo{ 3106 {1, 2}, // CX 3107 {0, 239}, // AX CX DX BX BP SI DI 3108 }, 3109 outputs: []outputInfo{ 3110 {0, 239}, // AX CX DX BX BP SI DI 3111 }, 3112 }, 3113 }, 3114 { 3115 name: "SHRLconst", 3116 auxType: auxInt32, 3117 argLen: 1, 3118 resultInArg0: true, 3119 clobberFlags: true, 3120 asm: x86.ASHRL, 3121 reg: regInfo{ 3122 inputs: []inputInfo{ 3123 {0, 239}, // AX CX DX BX BP SI DI 3124 }, 3125 outputs: []outputInfo{ 3126 {0, 239}, // AX CX DX BX BP SI DI 3127 }, 3128 }, 3129 }, 3130 { 3131 name: "SHRWconst", 3132 auxType: auxInt16, 3133 argLen: 1, 3134 resultInArg0: true, 3135 clobberFlags: true, 3136 asm: x86.ASHRW, 3137 reg: regInfo{ 3138 inputs: []inputInfo{ 3139 {0, 239}, // AX CX DX BX BP SI DI 3140 }, 3141 outputs: []outputInfo{ 3142 {0, 239}, // AX CX DX BX BP SI DI 3143 }, 3144 }, 3145 }, 3146 { 3147 name: "SHRBconst", 3148 auxType: auxInt8, 3149 argLen: 1, 3150 resultInArg0: true, 3151 clobberFlags: true, 3152 asm: x86.ASHRB, 3153 reg: regInfo{ 3154 inputs: []inputInfo{ 3155 {0, 239}, // AX CX DX BX BP SI DI 3156 }, 3157 outputs: []outputInfo{ 3158 {0, 239}, // AX CX DX BX BP SI DI 3159 }, 3160 }, 3161 }, 3162 { 3163 name: "SARL", 3164 argLen: 2, 3165 resultInArg0: true, 3166 clobberFlags: true, 3167 asm: x86.ASARL, 3168 reg: regInfo{ 3169 inputs: []inputInfo{ 3170 {1, 2}, // CX 3171 {0, 239}, // AX CX DX BX BP SI DI 3172 }, 3173 outputs: []outputInfo{ 3174 {0, 239}, // AX CX DX BX BP SI DI 3175 }, 3176 }, 3177 }, 3178 { 3179 name: "SARW", 3180 argLen: 2, 3181 resultInArg0: true, 3182 clobberFlags: true, 3183 asm: x86.ASARW, 3184 reg: regInfo{ 3185 inputs: []inputInfo{ 3186 {1, 2}, // CX 3187 {0, 239}, // AX CX DX BX BP SI DI 3188 }, 3189 outputs: []outputInfo{ 3190 {0, 239}, // AX CX DX BX BP SI DI 3191 }, 3192 }, 3193 }, 3194 { 3195 name: "SARB", 3196 argLen: 2, 3197 resultInArg0: true, 3198 clobberFlags: true, 3199 asm: x86.ASARB, 3200 reg: regInfo{ 3201 inputs: []inputInfo{ 3202 {1, 2}, // CX 3203 {0, 239}, // AX CX DX BX BP SI DI 3204 }, 3205 outputs: []outputInfo{ 3206 {0, 239}, // AX CX DX BX BP SI DI 3207 }, 3208 }, 3209 }, 3210 { 3211 name: "SARLconst", 3212 auxType: auxInt32, 3213 argLen: 1, 3214 resultInArg0: true, 3215 clobberFlags: true, 3216 asm: x86.ASARL, 3217 reg: regInfo{ 3218 inputs: []inputInfo{ 3219 {0, 239}, // AX CX DX BX BP SI DI 3220 }, 3221 outputs: []outputInfo{ 3222 {0, 239}, // AX CX DX BX BP SI DI 3223 }, 3224 }, 3225 }, 3226 { 3227 name: "SARWconst", 3228 auxType: auxInt16, 3229 argLen: 1, 3230 resultInArg0: true, 3231 clobberFlags: true, 3232 asm: x86.ASARW, 3233 reg: regInfo{ 3234 inputs: []inputInfo{ 3235 {0, 239}, // AX CX DX BX BP SI DI 3236 }, 3237 outputs: []outputInfo{ 3238 {0, 239}, // AX CX DX BX BP SI DI 3239 }, 3240 }, 3241 }, 3242 { 3243 name: "SARBconst", 3244 auxType: auxInt8, 3245 argLen: 1, 3246 resultInArg0: true, 3247 clobberFlags: true, 3248 asm: x86.ASARB, 3249 reg: regInfo{ 3250 inputs: []inputInfo{ 3251 {0, 239}, // AX CX DX BX BP SI DI 3252 }, 3253 outputs: []outputInfo{ 3254 {0, 239}, // AX CX DX BX BP SI DI 3255 }, 3256 }, 3257 }, 3258 { 3259 name: "ROLLconst", 3260 auxType: auxInt32, 3261 argLen: 1, 3262 resultInArg0: true, 3263 clobberFlags: true, 3264 asm: x86.AROLL, 3265 reg: regInfo{ 3266 inputs: []inputInfo{ 3267 {0, 239}, // AX CX DX BX BP SI DI 3268 }, 3269 outputs: []outputInfo{ 3270 {0, 239}, // AX CX DX BX BP SI DI 3271 }, 3272 }, 3273 }, 3274 { 3275 name: "ROLWconst", 3276 auxType: auxInt16, 3277 argLen: 1, 3278 resultInArg0: true, 3279 clobberFlags: true, 3280 asm: x86.AROLW, 3281 reg: regInfo{ 3282 inputs: []inputInfo{ 3283 {0, 239}, // AX CX DX BX BP SI DI 3284 }, 3285 outputs: []outputInfo{ 3286 {0, 239}, // AX CX DX BX BP SI DI 3287 }, 3288 }, 3289 }, 3290 { 3291 name: "ROLBconst", 3292 auxType: auxInt8, 3293 argLen: 1, 3294 resultInArg0: true, 3295 clobberFlags: true, 3296 asm: x86.AROLB, 3297 reg: regInfo{ 3298 inputs: []inputInfo{ 3299 {0, 239}, // AX CX DX BX BP SI DI 3300 }, 3301 outputs: []outputInfo{ 3302 {0, 239}, // AX CX DX BX BP SI DI 3303 }, 3304 }, 3305 }, 3306 { 3307 name: "NEGL", 3308 argLen: 1, 3309 resultInArg0: true, 3310 clobberFlags: true, 3311 asm: x86.ANEGL, 3312 reg: regInfo{ 3313 inputs: []inputInfo{ 3314 {0, 239}, // AX CX DX BX BP SI DI 3315 }, 3316 outputs: []outputInfo{ 3317 {0, 239}, // AX CX DX BX BP SI DI 3318 }, 3319 }, 3320 }, 3321 { 3322 name: "NOTL", 3323 argLen: 1, 3324 resultInArg0: true, 3325 clobberFlags: true, 3326 asm: x86.ANOTL, 3327 reg: regInfo{ 3328 inputs: []inputInfo{ 3329 {0, 239}, // AX CX DX BX BP SI DI 3330 }, 3331 outputs: []outputInfo{ 3332 {0, 239}, // AX CX DX BX BP SI DI 3333 }, 3334 }, 3335 }, 3336 { 3337 name: "BSFL", 3338 argLen: 1, 3339 clobberFlags: true, 3340 asm: x86.ABSFL, 3341 reg: regInfo{ 3342 inputs: []inputInfo{ 3343 {0, 239}, // AX CX DX BX BP SI DI 3344 }, 3345 outputs: []outputInfo{ 3346 {0, 239}, // AX CX DX BX BP SI DI 3347 }, 3348 }, 3349 }, 3350 { 3351 name: "BSFW", 3352 argLen: 1, 3353 clobberFlags: true, 3354 asm: x86.ABSFW, 3355 reg: regInfo{ 3356 inputs: []inputInfo{ 3357 {0, 239}, // AX CX DX BX BP SI DI 3358 }, 3359 outputs: []outputInfo{ 3360 {0, 239}, // AX CX DX BX BP SI DI 3361 }, 3362 }, 3363 }, 3364 { 3365 name: "BSRL", 3366 argLen: 1, 3367 clobberFlags: true, 3368 asm: x86.ABSRL, 3369 reg: regInfo{ 3370 inputs: []inputInfo{ 3371 {0, 239}, // AX CX DX BX BP SI DI 3372 }, 3373 outputs: []outputInfo{ 3374 {0, 239}, // AX CX DX BX BP SI DI 3375 }, 3376 }, 3377 }, 3378 { 3379 name: "BSRW", 3380 argLen: 1, 3381 clobberFlags: true, 3382 asm: x86.ABSRW, 3383 reg: regInfo{ 3384 inputs: []inputInfo{ 3385 {0, 239}, // AX CX DX BX BP SI DI 3386 }, 3387 outputs: []outputInfo{ 3388 {0, 239}, // AX CX DX BX BP SI DI 3389 }, 3390 }, 3391 }, 3392 { 3393 name: "BSWAPL", 3394 argLen: 1, 3395 resultInArg0: true, 3396 clobberFlags: true, 3397 asm: x86.ABSWAPL, 3398 reg: regInfo{ 3399 inputs: []inputInfo{ 3400 {0, 239}, // AX CX DX BX BP SI DI 3401 }, 3402 outputs: []outputInfo{ 3403 {0, 239}, // AX CX DX BX BP SI DI 3404 }, 3405 }, 3406 }, 3407 { 3408 name: "SQRTSD", 3409 argLen: 1, 3410 asm: x86.ASQRTSD, 3411 reg: regInfo{ 3412 inputs: []inputInfo{ 3413 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3414 }, 3415 outputs: []outputInfo{ 3416 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3417 }, 3418 }, 3419 }, 3420 { 3421 name: "SBBLcarrymask", 3422 argLen: 1, 3423 asm: x86.ASBBL, 3424 reg: regInfo{ 3425 outputs: []outputInfo{ 3426 {0, 239}, // AX CX DX BX BP SI DI 3427 }, 3428 }, 3429 }, 3430 { 3431 name: "SETEQ", 3432 argLen: 1, 3433 asm: x86.ASETEQ, 3434 reg: regInfo{ 3435 outputs: []outputInfo{ 3436 {0, 239}, // AX CX DX BX BP SI DI 3437 }, 3438 }, 3439 }, 3440 { 3441 name: "SETNE", 3442 argLen: 1, 3443 asm: x86.ASETNE, 3444 reg: regInfo{ 3445 outputs: []outputInfo{ 3446 {0, 239}, // AX CX DX BX BP SI DI 3447 }, 3448 }, 3449 }, 3450 { 3451 name: "SETL", 3452 argLen: 1, 3453 asm: x86.ASETLT, 3454 reg: regInfo{ 3455 outputs: []outputInfo{ 3456 {0, 239}, // AX CX DX BX BP SI DI 3457 }, 3458 }, 3459 }, 3460 { 3461 name: "SETLE", 3462 argLen: 1, 3463 asm: x86.ASETLE, 3464 reg: regInfo{ 3465 outputs: []outputInfo{ 3466 {0, 239}, // AX CX DX BX BP SI DI 3467 }, 3468 }, 3469 }, 3470 { 3471 name: "SETG", 3472 argLen: 1, 3473 asm: x86.ASETGT, 3474 reg: regInfo{ 3475 outputs: []outputInfo{ 3476 {0, 239}, // AX CX DX BX BP SI DI 3477 }, 3478 }, 3479 }, 3480 { 3481 name: "SETGE", 3482 argLen: 1, 3483 asm: x86.ASETGE, 3484 reg: regInfo{ 3485 outputs: []outputInfo{ 3486 {0, 239}, // AX CX DX BX BP SI DI 3487 }, 3488 }, 3489 }, 3490 { 3491 name: "SETB", 3492 argLen: 1, 3493 asm: x86.ASETCS, 3494 reg: regInfo{ 3495 outputs: []outputInfo{ 3496 {0, 239}, // AX CX DX BX BP SI DI 3497 }, 3498 }, 3499 }, 3500 { 3501 name: "SETBE", 3502 argLen: 1, 3503 asm: x86.ASETLS, 3504 reg: regInfo{ 3505 outputs: []outputInfo{ 3506 {0, 239}, // AX CX DX BX BP SI DI 3507 }, 3508 }, 3509 }, 3510 { 3511 name: "SETA", 3512 argLen: 1, 3513 asm: x86.ASETHI, 3514 reg: regInfo{ 3515 outputs: []outputInfo{ 3516 {0, 239}, // AX CX DX BX BP SI DI 3517 }, 3518 }, 3519 }, 3520 { 3521 name: "SETAE", 3522 argLen: 1, 3523 asm: x86.ASETCC, 3524 reg: regInfo{ 3525 outputs: []outputInfo{ 3526 {0, 239}, // AX CX DX BX BP SI DI 3527 }, 3528 }, 3529 }, 3530 { 3531 name: "SETEQF", 3532 argLen: 1, 3533 clobberFlags: true, 3534 asm: x86.ASETEQ, 3535 reg: regInfo{ 3536 clobbers: 1, // AX 3537 outputs: []outputInfo{ 3538 {0, 238}, // CX DX BX BP SI DI 3539 }, 3540 }, 3541 }, 3542 { 3543 name: "SETNEF", 3544 argLen: 1, 3545 clobberFlags: true, 3546 asm: x86.ASETNE, 3547 reg: regInfo{ 3548 clobbers: 1, // AX 3549 outputs: []outputInfo{ 3550 {0, 238}, // CX DX BX BP SI DI 3551 }, 3552 }, 3553 }, 3554 { 3555 name: "SETORD", 3556 argLen: 1, 3557 asm: x86.ASETPC, 3558 reg: regInfo{ 3559 outputs: []outputInfo{ 3560 {0, 239}, // AX CX DX BX BP SI DI 3561 }, 3562 }, 3563 }, 3564 { 3565 name: "SETNAN", 3566 argLen: 1, 3567 asm: x86.ASETPS, 3568 reg: regInfo{ 3569 outputs: []outputInfo{ 3570 {0, 239}, // AX CX DX BX BP SI DI 3571 }, 3572 }, 3573 }, 3574 { 3575 name: "SETGF", 3576 argLen: 1, 3577 asm: x86.ASETHI, 3578 reg: regInfo{ 3579 outputs: []outputInfo{ 3580 {0, 239}, // AX CX DX BX BP SI DI 3581 }, 3582 }, 3583 }, 3584 { 3585 name: "SETGEF", 3586 argLen: 1, 3587 asm: x86.ASETCC, 3588 reg: regInfo{ 3589 outputs: []outputInfo{ 3590 {0, 239}, // AX CX DX BX BP SI DI 3591 }, 3592 }, 3593 }, 3594 { 3595 name: "MOVBLSX", 3596 argLen: 1, 3597 asm: x86.AMOVBLSX, 3598 reg: regInfo{ 3599 inputs: []inputInfo{ 3600 {0, 239}, // AX CX DX BX BP SI DI 3601 }, 3602 outputs: []outputInfo{ 3603 {0, 239}, // AX CX DX BX BP SI DI 3604 }, 3605 }, 3606 }, 3607 { 3608 name: "MOVBLZX", 3609 argLen: 1, 3610 asm: x86.AMOVBLZX, 3611 reg: regInfo{ 3612 inputs: []inputInfo{ 3613 {0, 239}, // AX CX DX BX BP SI DI 3614 }, 3615 outputs: []outputInfo{ 3616 {0, 239}, // AX CX DX BX BP SI DI 3617 }, 3618 }, 3619 }, 3620 { 3621 name: "MOVWLSX", 3622 argLen: 1, 3623 asm: x86.AMOVWLSX, 3624 reg: regInfo{ 3625 inputs: []inputInfo{ 3626 {0, 239}, // AX CX DX BX BP SI DI 3627 }, 3628 outputs: []outputInfo{ 3629 {0, 239}, // AX CX DX BX BP SI DI 3630 }, 3631 }, 3632 }, 3633 { 3634 name: "MOVWLZX", 3635 argLen: 1, 3636 asm: x86.AMOVWLZX, 3637 reg: regInfo{ 3638 inputs: []inputInfo{ 3639 {0, 239}, // AX CX DX BX BP SI DI 3640 }, 3641 outputs: []outputInfo{ 3642 {0, 239}, // AX CX DX BX BP SI DI 3643 }, 3644 }, 3645 }, 3646 { 3647 name: "MOVLconst", 3648 auxType: auxInt32, 3649 argLen: 0, 3650 rematerializeable: true, 3651 asm: x86.AMOVL, 3652 reg: regInfo{ 3653 outputs: []outputInfo{ 3654 {0, 239}, // AX CX DX BX BP SI DI 3655 }, 3656 }, 3657 }, 3658 { 3659 name: "CVTTSD2SL", 3660 argLen: 1, 3661 usesScratch: true, 3662 asm: x86.ACVTTSD2SL, 3663 reg: regInfo{ 3664 inputs: []inputInfo{ 3665 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3666 }, 3667 outputs: []outputInfo{ 3668 {0, 239}, // AX CX DX BX BP SI DI 3669 }, 3670 }, 3671 }, 3672 { 3673 name: "CVTTSS2SL", 3674 argLen: 1, 3675 usesScratch: true, 3676 asm: x86.ACVTTSS2SL, 3677 reg: regInfo{ 3678 inputs: []inputInfo{ 3679 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3680 }, 3681 outputs: []outputInfo{ 3682 {0, 239}, // AX CX DX BX BP SI DI 3683 }, 3684 }, 3685 }, 3686 { 3687 name: "CVTSL2SS", 3688 argLen: 1, 3689 usesScratch: true, 3690 asm: x86.ACVTSL2SS, 3691 reg: regInfo{ 3692 inputs: []inputInfo{ 3693 {0, 239}, // AX CX DX BX BP SI DI 3694 }, 3695 outputs: []outputInfo{ 3696 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3697 }, 3698 }, 3699 }, 3700 { 3701 name: "CVTSL2SD", 3702 argLen: 1, 3703 usesScratch: true, 3704 asm: x86.ACVTSL2SD, 3705 reg: regInfo{ 3706 inputs: []inputInfo{ 3707 {0, 239}, // AX CX DX BX BP SI DI 3708 }, 3709 outputs: []outputInfo{ 3710 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3711 }, 3712 }, 3713 }, 3714 { 3715 name: "CVTSD2SS", 3716 argLen: 1, 3717 usesScratch: true, 3718 asm: x86.ACVTSD2SS, 3719 reg: regInfo{ 3720 inputs: []inputInfo{ 3721 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3722 }, 3723 outputs: []outputInfo{ 3724 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3725 }, 3726 }, 3727 }, 3728 { 3729 name: "CVTSS2SD", 3730 argLen: 1, 3731 asm: x86.ACVTSS2SD, 3732 reg: regInfo{ 3733 inputs: []inputInfo{ 3734 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3735 }, 3736 outputs: []outputInfo{ 3737 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3738 }, 3739 }, 3740 }, 3741 { 3742 name: "PXOR", 3743 argLen: 2, 3744 commutative: true, 3745 resultInArg0: true, 3746 asm: x86.APXOR, 3747 reg: regInfo{ 3748 inputs: []inputInfo{ 3749 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3750 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3751 }, 3752 outputs: []outputInfo{ 3753 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3754 }, 3755 }, 3756 }, 3757 { 3758 name: "LEAL", 3759 auxType: auxSymOff, 3760 argLen: 1, 3761 rematerializeable: true, 3762 reg: regInfo{ 3763 inputs: []inputInfo{ 3764 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3765 }, 3766 outputs: []outputInfo{ 3767 {0, 239}, // AX CX DX BX BP SI DI 3768 }, 3769 }, 3770 }, 3771 { 3772 name: "LEAL1", 3773 auxType: auxSymOff, 3774 argLen: 2, 3775 reg: regInfo{ 3776 inputs: []inputInfo{ 3777 {1, 255}, // AX CX DX BX SP BP SI DI 3778 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3779 }, 3780 outputs: []outputInfo{ 3781 {0, 239}, // AX CX DX BX BP SI DI 3782 }, 3783 }, 3784 }, 3785 { 3786 name: "LEAL2", 3787 auxType: auxSymOff, 3788 argLen: 2, 3789 reg: regInfo{ 3790 inputs: []inputInfo{ 3791 {1, 255}, // AX CX DX BX SP BP SI DI 3792 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3793 }, 3794 outputs: []outputInfo{ 3795 {0, 239}, // AX CX DX BX BP SI DI 3796 }, 3797 }, 3798 }, 3799 { 3800 name: "LEAL4", 3801 auxType: auxSymOff, 3802 argLen: 2, 3803 reg: regInfo{ 3804 inputs: []inputInfo{ 3805 {1, 255}, // AX CX DX BX SP BP SI DI 3806 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3807 }, 3808 outputs: []outputInfo{ 3809 {0, 239}, // AX CX DX BX BP SI DI 3810 }, 3811 }, 3812 }, 3813 { 3814 name: "LEAL8", 3815 auxType: auxSymOff, 3816 argLen: 2, 3817 reg: regInfo{ 3818 inputs: []inputInfo{ 3819 {1, 255}, // AX CX DX BX SP BP SI DI 3820 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3821 }, 3822 outputs: []outputInfo{ 3823 {0, 239}, // AX CX DX BX BP SI DI 3824 }, 3825 }, 3826 }, 3827 { 3828 name: "MOVBload", 3829 auxType: auxSymOff, 3830 argLen: 2, 3831 faultOnNilArg0: true, 3832 asm: x86.AMOVBLZX, 3833 reg: regInfo{ 3834 inputs: []inputInfo{ 3835 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3836 }, 3837 outputs: []outputInfo{ 3838 {0, 239}, // AX CX DX BX BP SI DI 3839 }, 3840 }, 3841 }, 3842 { 3843 name: "MOVBLSXload", 3844 auxType: auxSymOff, 3845 argLen: 2, 3846 faultOnNilArg0: true, 3847 asm: x86.AMOVBLSX, 3848 reg: regInfo{ 3849 inputs: []inputInfo{ 3850 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3851 }, 3852 outputs: []outputInfo{ 3853 {0, 239}, // AX CX DX BX BP SI DI 3854 }, 3855 }, 3856 }, 3857 { 3858 name: "MOVWload", 3859 auxType: auxSymOff, 3860 argLen: 2, 3861 faultOnNilArg0: true, 3862 asm: x86.AMOVWLZX, 3863 reg: regInfo{ 3864 inputs: []inputInfo{ 3865 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3866 }, 3867 outputs: []outputInfo{ 3868 {0, 239}, // AX CX DX BX BP SI DI 3869 }, 3870 }, 3871 }, 3872 { 3873 name: "MOVWLSXload", 3874 auxType: auxSymOff, 3875 argLen: 2, 3876 faultOnNilArg0: true, 3877 asm: x86.AMOVWLSX, 3878 reg: regInfo{ 3879 inputs: []inputInfo{ 3880 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3881 }, 3882 outputs: []outputInfo{ 3883 {0, 239}, // AX CX DX BX BP SI DI 3884 }, 3885 }, 3886 }, 3887 { 3888 name: "MOVLload", 3889 auxType: auxSymOff, 3890 argLen: 2, 3891 faultOnNilArg0: true, 3892 asm: x86.AMOVL, 3893 reg: regInfo{ 3894 inputs: []inputInfo{ 3895 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3896 }, 3897 outputs: []outputInfo{ 3898 {0, 239}, // AX CX DX BX BP SI DI 3899 }, 3900 }, 3901 }, 3902 { 3903 name: "MOVBstore", 3904 auxType: auxSymOff, 3905 argLen: 3, 3906 faultOnNilArg0: true, 3907 asm: x86.AMOVB, 3908 reg: regInfo{ 3909 inputs: []inputInfo{ 3910 {1, 255}, // AX CX DX BX SP BP SI DI 3911 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3912 }, 3913 }, 3914 }, 3915 { 3916 name: "MOVWstore", 3917 auxType: auxSymOff, 3918 argLen: 3, 3919 faultOnNilArg0: true, 3920 asm: x86.AMOVW, 3921 reg: regInfo{ 3922 inputs: []inputInfo{ 3923 {1, 255}, // AX CX DX BX SP BP SI DI 3924 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3925 }, 3926 }, 3927 }, 3928 { 3929 name: "MOVLstore", 3930 auxType: auxSymOff, 3931 argLen: 3, 3932 faultOnNilArg0: true, 3933 asm: x86.AMOVL, 3934 reg: regInfo{ 3935 inputs: []inputInfo{ 3936 {1, 255}, // AX CX DX BX SP BP SI DI 3937 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3938 }, 3939 }, 3940 }, 3941 { 3942 name: "MOVBloadidx1", 3943 auxType: auxSymOff, 3944 argLen: 3, 3945 asm: x86.AMOVBLZX, 3946 reg: regInfo{ 3947 inputs: []inputInfo{ 3948 {1, 255}, // AX CX DX BX SP BP SI DI 3949 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3950 }, 3951 outputs: []outputInfo{ 3952 {0, 239}, // AX CX DX BX BP SI DI 3953 }, 3954 }, 3955 }, 3956 { 3957 name: "MOVWloadidx1", 3958 auxType: auxSymOff, 3959 argLen: 3, 3960 asm: x86.AMOVWLZX, 3961 reg: regInfo{ 3962 inputs: []inputInfo{ 3963 {1, 255}, // AX CX DX BX SP BP SI DI 3964 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3965 }, 3966 outputs: []outputInfo{ 3967 {0, 239}, // AX CX DX BX BP SI DI 3968 }, 3969 }, 3970 }, 3971 { 3972 name: "MOVWloadidx2", 3973 auxType: auxSymOff, 3974 argLen: 3, 3975 asm: x86.AMOVWLZX, 3976 reg: regInfo{ 3977 inputs: []inputInfo{ 3978 {1, 255}, // AX CX DX BX SP BP SI DI 3979 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3980 }, 3981 outputs: []outputInfo{ 3982 {0, 239}, // AX CX DX BX BP SI DI 3983 }, 3984 }, 3985 }, 3986 { 3987 name: "MOVLloadidx1", 3988 auxType: auxSymOff, 3989 argLen: 3, 3990 asm: x86.AMOVL, 3991 reg: regInfo{ 3992 inputs: []inputInfo{ 3993 {1, 255}, // AX CX DX BX SP BP SI DI 3994 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3995 }, 3996 outputs: []outputInfo{ 3997 {0, 239}, // AX CX DX BX BP SI DI 3998 }, 3999 }, 4000 }, 4001 { 4002 name: "MOVLloadidx4", 4003 auxType: auxSymOff, 4004 argLen: 3, 4005 asm: x86.AMOVL, 4006 reg: regInfo{ 4007 inputs: []inputInfo{ 4008 {1, 255}, // AX CX DX BX SP BP SI DI 4009 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4010 }, 4011 outputs: []outputInfo{ 4012 {0, 239}, // AX CX DX BX BP SI DI 4013 }, 4014 }, 4015 }, 4016 { 4017 name: "MOVBstoreidx1", 4018 auxType: auxSymOff, 4019 argLen: 4, 4020 asm: x86.AMOVB, 4021 reg: regInfo{ 4022 inputs: []inputInfo{ 4023 {1, 255}, // AX CX DX BX SP BP SI DI 4024 {2, 255}, // AX CX DX BX SP BP SI DI 4025 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4026 }, 4027 }, 4028 }, 4029 { 4030 name: "MOVWstoreidx1", 4031 auxType: auxSymOff, 4032 argLen: 4, 4033 asm: x86.AMOVW, 4034 reg: regInfo{ 4035 inputs: []inputInfo{ 4036 {1, 255}, // AX CX DX BX SP BP SI DI 4037 {2, 255}, // AX CX DX BX SP BP SI DI 4038 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4039 }, 4040 }, 4041 }, 4042 { 4043 name: "MOVWstoreidx2", 4044 auxType: auxSymOff, 4045 argLen: 4, 4046 asm: x86.AMOVW, 4047 reg: regInfo{ 4048 inputs: []inputInfo{ 4049 {1, 255}, // AX CX DX BX SP BP SI DI 4050 {2, 255}, // AX CX DX BX SP BP SI DI 4051 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4052 }, 4053 }, 4054 }, 4055 { 4056 name: "MOVLstoreidx1", 4057 auxType: auxSymOff, 4058 argLen: 4, 4059 asm: x86.AMOVL, 4060 reg: regInfo{ 4061 inputs: []inputInfo{ 4062 {1, 255}, // AX CX DX BX SP BP SI DI 4063 {2, 255}, // AX CX DX BX SP BP SI DI 4064 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4065 }, 4066 }, 4067 }, 4068 { 4069 name: "MOVLstoreidx4", 4070 auxType: auxSymOff, 4071 argLen: 4, 4072 asm: x86.AMOVL, 4073 reg: regInfo{ 4074 inputs: []inputInfo{ 4075 {1, 255}, // AX CX DX BX SP BP SI DI 4076 {2, 255}, // AX CX DX BX SP BP SI DI 4077 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4078 }, 4079 }, 4080 }, 4081 { 4082 name: "MOVBstoreconst", 4083 auxType: auxSymValAndOff, 4084 argLen: 2, 4085 faultOnNilArg0: true, 4086 asm: x86.AMOVB, 4087 reg: regInfo{ 4088 inputs: []inputInfo{ 4089 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4090 }, 4091 }, 4092 }, 4093 { 4094 name: "MOVWstoreconst", 4095 auxType: auxSymValAndOff, 4096 argLen: 2, 4097 faultOnNilArg0: true, 4098 asm: x86.AMOVW, 4099 reg: regInfo{ 4100 inputs: []inputInfo{ 4101 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4102 }, 4103 }, 4104 }, 4105 { 4106 name: "MOVLstoreconst", 4107 auxType: auxSymValAndOff, 4108 argLen: 2, 4109 faultOnNilArg0: true, 4110 asm: x86.AMOVL, 4111 reg: regInfo{ 4112 inputs: []inputInfo{ 4113 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4114 }, 4115 }, 4116 }, 4117 { 4118 name: "MOVBstoreconstidx1", 4119 auxType: auxSymValAndOff, 4120 argLen: 3, 4121 asm: x86.AMOVB, 4122 reg: regInfo{ 4123 inputs: []inputInfo{ 4124 {1, 255}, // AX CX DX BX SP BP SI DI 4125 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4126 }, 4127 }, 4128 }, 4129 { 4130 name: "MOVWstoreconstidx1", 4131 auxType: auxSymValAndOff, 4132 argLen: 3, 4133 asm: x86.AMOVW, 4134 reg: regInfo{ 4135 inputs: []inputInfo{ 4136 {1, 255}, // AX CX DX BX SP BP SI DI 4137 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4138 }, 4139 }, 4140 }, 4141 { 4142 name: "MOVWstoreconstidx2", 4143 auxType: auxSymValAndOff, 4144 argLen: 3, 4145 asm: x86.AMOVW, 4146 reg: regInfo{ 4147 inputs: []inputInfo{ 4148 {1, 255}, // AX CX DX BX SP BP SI DI 4149 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4150 }, 4151 }, 4152 }, 4153 { 4154 name: "MOVLstoreconstidx1", 4155 auxType: auxSymValAndOff, 4156 argLen: 3, 4157 asm: x86.AMOVL, 4158 reg: regInfo{ 4159 inputs: []inputInfo{ 4160 {1, 255}, // AX CX DX BX SP BP SI DI 4161 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4162 }, 4163 }, 4164 }, 4165 { 4166 name: "MOVLstoreconstidx4", 4167 auxType: auxSymValAndOff, 4168 argLen: 3, 4169 asm: x86.AMOVL, 4170 reg: regInfo{ 4171 inputs: []inputInfo{ 4172 {1, 255}, // AX CX DX BX SP BP SI DI 4173 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4174 }, 4175 }, 4176 }, 4177 { 4178 name: "DUFFZERO", 4179 auxType: auxInt64, 4180 argLen: 3, 4181 faultOnNilArg0: true, 4182 reg: regInfo{ 4183 inputs: []inputInfo{ 4184 {0, 128}, // DI 4185 {1, 1}, // AX 4186 }, 4187 clobbers: 130, // CX DI 4188 }, 4189 }, 4190 { 4191 name: "REPSTOSL", 4192 argLen: 4, 4193 faultOnNilArg0: true, 4194 reg: regInfo{ 4195 inputs: []inputInfo{ 4196 {0, 128}, // DI 4197 {1, 2}, // CX 4198 {2, 1}, // AX 4199 }, 4200 clobbers: 130, // CX DI 4201 }, 4202 }, 4203 { 4204 name: "CALLstatic", 4205 auxType: auxSymOff, 4206 argLen: 1, 4207 clobberFlags: true, 4208 call: true, 4209 reg: regInfo{ 4210 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4211 }, 4212 }, 4213 { 4214 name: "CALLclosure", 4215 auxType: auxInt64, 4216 argLen: 3, 4217 clobberFlags: true, 4218 call: true, 4219 reg: regInfo{ 4220 inputs: []inputInfo{ 4221 {1, 4}, // DX 4222 {0, 255}, // AX CX DX BX SP BP SI DI 4223 }, 4224 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4225 }, 4226 }, 4227 { 4228 name: "CALLdefer", 4229 auxType: auxInt64, 4230 argLen: 1, 4231 clobberFlags: true, 4232 call: true, 4233 reg: regInfo{ 4234 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4235 }, 4236 }, 4237 { 4238 name: "CALLgo", 4239 auxType: auxInt64, 4240 argLen: 1, 4241 clobberFlags: true, 4242 call: true, 4243 reg: regInfo{ 4244 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4245 }, 4246 }, 4247 { 4248 name: "CALLinter", 4249 auxType: auxInt64, 4250 argLen: 2, 4251 clobberFlags: true, 4252 call: true, 4253 reg: regInfo{ 4254 inputs: []inputInfo{ 4255 {0, 239}, // AX CX DX BX BP SI DI 4256 }, 4257 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4258 }, 4259 }, 4260 { 4261 name: "DUFFCOPY", 4262 auxType: auxInt64, 4263 argLen: 3, 4264 clobberFlags: true, 4265 faultOnNilArg0: true, 4266 faultOnNilArg1: true, 4267 reg: regInfo{ 4268 inputs: []inputInfo{ 4269 {0, 128}, // DI 4270 {1, 64}, // SI 4271 }, 4272 clobbers: 194, // CX SI DI 4273 }, 4274 }, 4275 { 4276 name: "REPMOVSL", 4277 argLen: 4, 4278 faultOnNilArg0: true, 4279 faultOnNilArg1: true, 4280 reg: regInfo{ 4281 inputs: []inputInfo{ 4282 {0, 128}, // DI 4283 {1, 64}, // SI 4284 {2, 2}, // CX 4285 }, 4286 clobbers: 194, // CX SI DI 4287 }, 4288 }, 4289 { 4290 name: "InvertFlags", 4291 argLen: 1, 4292 reg: regInfo{}, 4293 }, 4294 { 4295 name: "LoweredGetG", 4296 argLen: 1, 4297 reg: regInfo{ 4298 outputs: []outputInfo{ 4299 {0, 239}, // AX CX DX BX BP SI DI 4300 }, 4301 }, 4302 }, 4303 { 4304 name: "LoweredGetClosurePtr", 4305 argLen: 0, 4306 reg: regInfo{ 4307 outputs: []outputInfo{ 4308 {0, 4}, // DX 4309 }, 4310 }, 4311 }, 4312 { 4313 name: "LoweredNilCheck", 4314 argLen: 2, 4315 clobberFlags: true, 4316 nilCheck: true, 4317 faultOnNilArg0: true, 4318 reg: regInfo{ 4319 inputs: []inputInfo{ 4320 {0, 255}, // AX CX DX BX SP BP SI DI 4321 }, 4322 }, 4323 }, 4324 { 4325 name: "MOVLconvert", 4326 argLen: 2, 4327 asm: x86.AMOVL, 4328 reg: regInfo{ 4329 inputs: []inputInfo{ 4330 {0, 239}, // AX CX DX BX BP SI DI 4331 }, 4332 outputs: []outputInfo{ 4333 {0, 239}, // AX CX DX BX BP SI DI 4334 }, 4335 }, 4336 }, 4337 { 4338 name: "FlagEQ", 4339 argLen: 0, 4340 reg: regInfo{}, 4341 }, 4342 { 4343 name: "FlagLT_ULT", 4344 argLen: 0, 4345 reg: regInfo{}, 4346 }, 4347 { 4348 name: "FlagLT_UGT", 4349 argLen: 0, 4350 reg: regInfo{}, 4351 }, 4352 { 4353 name: "FlagGT_UGT", 4354 argLen: 0, 4355 reg: regInfo{}, 4356 }, 4357 { 4358 name: "FlagGT_ULT", 4359 argLen: 0, 4360 reg: regInfo{}, 4361 }, 4362 { 4363 name: "FCHS", 4364 argLen: 1, 4365 reg: regInfo{ 4366 inputs: []inputInfo{ 4367 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4368 }, 4369 outputs: []outputInfo{ 4370 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4371 }, 4372 }, 4373 }, 4374 { 4375 name: "MOVSSconst1", 4376 auxType: auxFloat32, 4377 argLen: 0, 4378 reg: regInfo{ 4379 outputs: []outputInfo{ 4380 {0, 239}, // AX CX DX BX BP SI DI 4381 }, 4382 }, 4383 }, 4384 { 4385 name: "MOVSDconst1", 4386 auxType: auxFloat64, 4387 argLen: 0, 4388 reg: regInfo{ 4389 outputs: []outputInfo{ 4390 {0, 239}, // AX CX DX BX BP SI DI 4391 }, 4392 }, 4393 }, 4394 { 4395 name: "MOVSSconst2", 4396 argLen: 1, 4397 asm: x86.AMOVSS, 4398 reg: regInfo{ 4399 inputs: []inputInfo{ 4400 {0, 239}, // AX CX DX BX BP SI DI 4401 }, 4402 outputs: []outputInfo{ 4403 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4404 }, 4405 }, 4406 }, 4407 { 4408 name: "MOVSDconst2", 4409 argLen: 1, 4410 asm: x86.AMOVSD, 4411 reg: regInfo{ 4412 inputs: []inputInfo{ 4413 {0, 239}, // AX CX DX BX BP SI DI 4414 }, 4415 outputs: []outputInfo{ 4416 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4417 }, 4418 }, 4419 }, 4420 4421 { 4422 name: "ADDSS", 4423 argLen: 2, 4424 commutative: true, 4425 resultInArg0: true, 4426 asm: x86.AADDSS, 4427 reg: regInfo{ 4428 inputs: []inputInfo{ 4429 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4430 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4431 }, 4432 outputs: []outputInfo{ 4433 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4434 }, 4435 }, 4436 }, 4437 { 4438 name: "ADDSD", 4439 argLen: 2, 4440 commutative: true, 4441 resultInArg0: true, 4442 asm: x86.AADDSD, 4443 reg: regInfo{ 4444 inputs: []inputInfo{ 4445 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4446 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4447 }, 4448 outputs: []outputInfo{ 4449 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4450 }, 4451 }, 4452 }, 4453 { 4454 name: "SUBSS", 4455 argLen: 2, 4456 resultInArg0: true, 4457 asm: x86.ASUBSS, 4458 reg: regInfo{ 4459 inputs: []inputInfo{ 4460 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4461 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4462 }, 4463 outputs: []outputInfo{ 4464 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4465 }, 4466 }, 4467 }, 4468 { 4469 name: "SUBSD", 4470 argLen: 2, 4471 resultInArg0: true, 4472 asm: x86.ASUBSD, 4473 reg: regInfo{ 4474 inputs: []inputInfo{ 4475 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4476 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4477 }, 4478 outputs: []outputInfo{ 4479 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4480 }, 4481 }, 4482 }, 4483 { 4484 name: "MULSS", 4485 argLen: 2, 4486 commutative: true, 4487 resultInArg0: true, 4488 asm: x86.AMULSS, 4489 reg: regInfo{ 4490 inputs: []inputInfo{ 4491 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4492 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4493 }, 4494 outputs: []outputInfo{ 4495 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4496 }, 4497 }, 4498 }, 4499 { 4500 name: "MULSD", 4501 argLen: 2, 4502 commutative: true, 4503 resultInArg0: true, 4504 asm: x86.AMULSD, 4505 reg: regInfo{ 4506 inputs: []inputInfo{ 4507 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4508 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4509 }, 4510 outputs: []outputInfo{ 4511 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4512 }, 4513 }, 4514 }, 4515 { 4516 name: "DIVSS", 4517 argLen: 2, 4518 resultInArg0: true, 4519 asm: x86.ADIVSS, 4520 reg: regInfo{ 4521 inputs: []inputInfo{ 4522 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4523 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4524 }, 4525 outputs: []outputInfo{ 4526 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4527 }, 4528 }, 4529 }, 4530 { 4531 name: "DIVSD", 4532 argLen: 2, 4533 resultInArg0: true, 4534 asm: x86.ADIVSD, 4535 reg: regInfo{ 4536 inputs: []inputInfo{ 4537 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4538 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4539 }, 4540 outputs: []outputInfo{ 4541 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4542 }, 4543 }, 4544 }, 4545 { 4546 name: "MOVSSload", 4547 auxType: auxSymOff, 4548 argLen: 2, 4549 faultOnNilArg0: true, 4550 asm: x86.AMOVSS, 4551 reg: regInfo{ 4552 inputs: []inputInfo{ 4553 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4554 }, 4555 outputs: []outputInfo{ 4556 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4557 }, 4558 }, 4559 }, 4560 { 4561 name: "MOVSDload", 4562 auxType: auxSymOff, 4563 argLen: 2, 4564 faultOnNilArg0: true, 4565 asm: x86.AMOVSD, 4566 reg: regInfo{ 4567 inputs: []inputInfo{ 4568 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4569 }, 4570 outputs: []outputInfo{ 4571 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4572 }, 4573 }, 4574 }, 4575 { 4576 name: "MOVSSconst", 4577 auxType: auxFloat32, 4578 argLen: 0, 4579 rematerializeable: true, 4580 asm: x86.AMOVSS, 4581 reg: regInfo{ 4582 outputs: []outputInfo{ 4583 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4584 }, 4585 }, 4586 }, 4587 { 4588 name: "MOVSDconst", 4589 auxType: auxFloat64, 4590 argLen: 0, 4591 rematerializeable: true, 4592 asm: x86.AMOVSD, 4593 reg: regInfo{ 4594 outputs: []outputInfo{ 4595 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4596 }, 4597 }, 4598 }, 4599 { 4600 name: "MOVSSloadidx1", 4601 auxType: auxSymOff, 4602 argLen: 3, 4603 asm: x86.AMOVSS, 4604 reg: regInfo{ 4605 inputs: []inputInfo{ 4606 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4607 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4608 }, 4609 outputs: []outputInfo{ 4610 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4611 }, 4612 }, 4613 }, 4614 { 4615 name: "MOVSSloadidx4", 4616 auxType: auxSymOff, 4617 argLen: 3, 4618 asm: x86.AMOVSS, 4619 reg: regInfo{ 4620 inputs: []inputInfo{ 4621 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4622 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4623 }, 4624 outputs: []outputInfo{ 4625 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4626 }, 4627 }, 4628 }, 4629 { 4630 name: "MOVSDloadidx1", 4631 auxType: auxSymOff, 4632 argLen: 3, 4633 asm: x86.AMOVSD, 4634 reg: regInfo{ 4635 inputs: []inputInfo{ 4636 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4637 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4638 }, 4639 outputs: []outputInfo{ 4640 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4641 }, 4642 }, 4643 }, 4644 { 4645 name: "MOVSDloadidx8", 4646 auxType: auxSymOff, 4647 argLen: 3, 4648 asm: x86.AMOVSD, 4649 reg: regInfo{ 4650 inputs: []inputInfo{ 4651 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4652 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4653 }, 4654 outputs: []outputInfo{ 4655 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4656 }, 4657 }, 4658 }, 4659 { 4660 name: "MOVSSstore", 4661 auxType: auxSymOff, 4662 argLen: 3, 4663 faultOnNilArg0: true, 4664 asm: x86.AMOVSS, 4665 reg: regInfo{ 4666 inputs: []inputInfo{ 4667 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4668 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4669 }, 4670 }, 4671 }, 4672 { 4673 name: "MOVSDstore", 4674 auxType: auxSymOff, 4675 argLen: 3, 4676 faultOnNilArg0: true, 4677 asm: x86.AMOVSD, 4678 reg: regInfo{ 4679 inputs: []inputInfo{ 4680 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4681 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4682 }, 4683 }, 4684 }, 4685 { 4686 name: "MOVSSstoreidx1", 4687 auxType: auxSymOff, 4688 argLen: 4, 4689 asm: x86.AMOVSS, 4690 reg: regInfo{ 4691 inputs: []inputInfo{ 4692 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4693 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4694 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4695 }, 4696 }, 4697 }, 4698 { 4699 name: "MOVSSstoreidx4", 4700 auxType: auxSymOff, 4701 argLen: 4, 4702 asm: x86.AMOVSS, 4703 reg: regInfo{ 4704 inputs: []inputInfo{ 4705 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4706 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4707 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4708 }, 4709 }, 4710 }, 4711 { 4712 name: "MOVSDstoreidx1", 4713 auxType: auxSymOff, 4714 argLen: 4, 4715 asm: x86.AMOVSD, 4716 reg: regInfo{ 4717 inputs: []inputInfo{ 4718 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4719 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4720 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4721 }, 4722 }, 4723 }, 4724 { 4725 name: "MOVSDstoreidx8", 4726 auxType: auxSymOff, 4727 argLen: 4, 4728 asm: x86.AMOVSD, 4729 reg: regInfo{ 4730 inputs: []inputInfo{ 4731 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4732 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4733 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4734 }, 4735 }, 4736 }, 4737 { 4738 name: "ADDQ", 4739 argLen: 2, 4740 commutative: true, 4741 clobberFlags: true, 4742 asm: x86.AADDQ, 4743 reg: regInfo{ 4744 inputs: []inputInfo{ 4745 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4746 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4747 }, 4748 outputs: []outputInfo{ 4749 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4750 }, 4751 }, 4752 }, 4753 { 4754 name: "ADDL", 4755 argLen: 2, 4756 commutative: true, 4757 clobberFlags: true, 4758 asm: x86.AADDL, 4759 reg: regInfo{ 4760 inputs: []inputInfo{ 4761 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4762 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4763 }, 4764 outputs: []outputInfo{ 4765 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4766 }, 4767 }, 4768 }, 4769 { 4770 name: "ADDQconst", 4771 auxType: auxInt64, 4772 argLen: 1, 4773 clobberFlags: true, 4774 asm: x86.AADDQ, 4775 reg: regInfo{ 4776 inputs: []inputInfo{ 4777 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4778 }, 4779 outputs: []outputInfo{ 4780 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4781 }, 4782 }, 4783 }, 4784 { 4785 name: "ADDLconst", 4786 auxType: auxInt32, 4787 argLen: 1, 4788 clobberFlags: true, 4789 asm: x86.AADDL, 4790 reg: regInfo{ 4791 inputs: []inputInfo{ 4792 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4793 }, 4794 outputs: []outputInfo{ 4795 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4796 }, 4797 }, 4798 }, 4799 { 4800 name: "SUBQ", 4801 argLen: 2, 4802 resultInArg0: true, 4803 clobberFlags: true, 4804 asm: x86.ASUBQ, 4805 reg: regInfo{ 4806 inputs: []inputInfo{ 4807 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4808 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4809 }, 4810 outputs: []outputInfo{ 4811 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4812 }, 4813 }, 4814 }, 4815 { 4816 name: "SUBL", 4817 argLen: 2, 4818 resultInArg0: true, 4819 clobberFlags: true, 4820 asm: x86.ASUBL, 4821 reg: regInfo{ 4822 inputs: []inputInfo{ 4823 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4824 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4825 }, 4826 outputs: []outputInfo{ 4827 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4828 }, 4829 }, 4830 }, 4831 { 4832 name: "SUBQconst", 4833 auxType: auxInt64, 4834 argLen: 1, 4835 resultInArg0: true, 4836 clobberFlags: true, 4837 asm: x86.ASUBQ, 4838 reg: regInfo{ 4839 inputs: []inputInfo{ 4840 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4841 }, 4842 outputs: []outputInfo{ 4843 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4844 }, 4845 }, 4846 }, 4847 { 4848 name: "SUBLconst", 4849 auxType: auxInt32, 4850 argLen: 1, 4851 resultInArg0: true, 4852 clobberFlags: true, 4853 asm: x86.ASUBL, 4854 reg: regInfo{ 4855 inputs: []inputInfo{ 4856 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4857 }, 4858 outputs: []outputInfo{ 4859 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4860 }, 4861 }, 4862 }, 4863 { 4864 name: "MULQ", 4865 argLen: 2, 4866 commutative: true, 4867 resultInArg0: true, 4868 clobberFlags: true, 4869 asm: x86.AIMULQ, 4870 reg: regInfo{ 4871 inputs: []inputInfo{ 4872 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4873 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4874 }, 4875 outputs: []outputInfo{ 4876 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4877 }, 4878 }, 4879 }, 4880 { 4881 name: "MULL", 4882 argLen: 2, 4883 commutative: true, 4884 resultInArg0: true, 4885 clobberFlags: true, 4886 asm: x86.AIMULL, 4887 reg: regInfo{ 4888 inputs: []inputInfo{ 4889 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4890 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4891 }, 4892 outputs: []outputInfo{ 4893 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4894 }, 4895 }, 4896 }, 4897 { 4898 name: "MULQconst", 4899 auxType: auxInt64, 4900 argLen: 1, 4901 resultInArg0: true, 4902 clobberFlags: true, 4903 asm: x86.AIMULQ, 4904 reg: regInfo{ 4905 inputs: []inputInfo{ 4906 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4907 }, 4908 outputs: []outputInfo{ 4909 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4910 }, 4911 }, 4912 }, 4913 { 4914 name: "MULLconst", 4915 auxType: auxInt32, 4916 argLen: 1, 4917 resultInArg0: true, 4918 clobberFlags: true, 4919 asm: x86.AIMULL, 4920 reg: regInfo{ 4921 inputs: []inputInfo{ 4922 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4923 }, 4924 outputs: []outputInfo{ 4925 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4926 }, 4927 }, 4928 }, 4929 { 4930 name: "HMULQ", 4931 argLen: 2, 4932 clobberFlags: true, 4933 asm: x86.AIMULQ, 4934 reg: regInfo{ 4935 inputs: []inputInfo{ 4936 {0, 1}, // AX 4937 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4938 }, 4939 clobbers: 1, // AX 4940 outputs: []outputInfo{ 4941 {0, 4}, // DX 4942 }, 4943 }, 4944 }, 4945 { 4946 name: "HMULL", 4947 argLen: 2, 4948 clobberFlags: true, 4949 asm: x86.AIMULL, 4950 reg: regInfo{ 4951 inputs: []inputInfo{ 4952 {0, 1}, // AX 4953 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4954 }, 4955 clobbers: 1, // AX 4956 outputs: []outputInfo{ 4957 {0, 4}, // DX 4958 }, 4959 }, 4960 }, 4961 { 4962 name: "HMULW", 4963 argLen: 2, 4964 clobberFlags: true, 4965 asm: x86.AIMULW, 4966 reg: regInfo{ 4967 inputs: []inputInfo{ 4968 {0, 1}, // AX 4969 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4970 }, 4971 clobbers: 1, // AX 4972 outputs: []outputInfo{ 4973 {0, 4}, // DX 4974 }, 4975 }, 4976 }, 4977 { 4978 name: "HMULB", 4979 argLen: 2, 4980 clobberFlags: true, 4981 asm: x86.AIMULB, 4982 reg: regInfo{ 4983 inputs: []inputInfo{ 4984 {0, 1}, // AX 4985 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4986 }, 4987 clobbers: 1, // AX 4988 outputs: []outputInfo{ 4989 {0, 4}, // DX 4990 }, 4991 }, 4992 }, 4993 { 4994 name: "HMULQU", 4995 argLen: 2, 4996 clobberFlags: true, 4997 asm: x86.AMULQ, 4998 reg: regInfo{ 4999 inputs: []inputInfo{ 5000 {0, 1}, // AX 5001 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5002 }, 5003 clobbers: 1, // AX 5004 outputs: []outputInfo{ 5005 {0, 4}, // DX 5006 }, 5007 }, 5008 }, 5009 { 5010 name: "HMULLU", 5011 argLen: 2, 5012 clobberFlags: true, 5013 asm: x86.AMULL, 5014 reg: regInfo{ 5015 inputs: []inputInfo{ 5016 {0, 1}, // AX 5017 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5018 }, 5019 clobbers: 1, // AX 5020 outputs: []outputInfo{ 5021 {0, 4}, // DX 5022 }, 5023 }, 5024 }, 5025 { 5026 name: "HMULWU", 5027 argLen: 2, 5028 clobberFlags: true, 5029 asm: x86.AMULW, 5030 reg: regInfo{ 5031 inputs: []inputInfo{ 5032 {0, 1}, // AX 5033 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5034 }, 5035 clobbers: 1, // AX 5036 outputs: []outputInfo{ 5037 {0, 4}, // DX 5038 }, 5039 }, 5040 }, 5041 { 5042 name: "HMULBU", 5043 argLen: 2, 5044 clobberFlags: true, 5045 asm: x86.AMULB, 5046 reg: regInfo{ 5047 inputs: []inputInfo{ 5048 {0, 1}, // AX 5049 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5050 }, 5051 clobbers: 1, // AX 5052 outputs: []outputInfo{ 5053 {0, 4}, // DX 5054 }, 5055 }, 5056 }, 5057 { 5058 name: "AVGQU", 5059 argLen: 2, 5060 commutative: true, 5061 resultInArg0: true, 5062 clobberFlags: true, 5063 reg: regInfo{ 5064 inputs: []inputInfo{ 5065 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5066 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5067 }, 5068 outputs: []outputInfo{ 5069 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5070 }, 5071 }, 5072 }, 5073 { 5074 name: "DIVQ", 5075 argLen: 2, 5076 clobberFlags: true, 5077 asm: x86.AIDIVQ, 5078 reg: regInfo{ 5079 inputs: []inputInfo{ 5080 {0, 1}, // AX 5081 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5082 }, 5083 outputs: []outputInfo{ 5084 {0, 1}, // AX 5085 {1, 4}, // DX 5086 }, 5087 }, 5088 }, 5089 { 5090 name: "DIVL", 5091 argLen: 2, 5092 clobberFlags: true, 5093 asm: x86.AIDIVL, 5094 reg: regInfo{ 5095 inputs: []inputInfo{ 5096 {0, 1}, // AX 5097 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5098 }, 5099 outputs: []outputInfo{ 5100 {0, 1}, // AX 5101 {1, 4}, // DX 5102 }, 5103 }, 5104 }, 5105 { 5106 name: "DIVW", 5107 argLen: 2, 5108 clobberFlags: true, 5109 asm: x86.AIDIVW, 5110 reg: regInfo{ 5111 inputs: []inputInfo{ 5112 {0, 1}, // AX 5113 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5114 }, 5115 outputs: []outputInfo{ 5116 {0, 1}, // AX 5117 {1, 4}, // DX 5118 }, 5119 }, 5120 }, 5121 { 5122 name: "DIVQU", 5123 argLen: 2, 5124 clobberFlags: true, 5125 asm: x86.ADIVQ, 5126 reg: regInfo{ 5127 inputs: []inputInfo{ 5128 {0, 1}, // AX 5129 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5130 }, 5131 outputs: []outputInfo{ 5132 {0, 1}, // AX 5133 {1, 4}, // DX 5134 }, 5135 }, 5136 }, 5137 { 5138 name: "DIVLU", 5139 argLen: 2, 5140 clobberFlags: true, 5141 asm: x86.ADIVL, 5142 reg: regInfo{ 5143 inputs: []inputInfo{ 5144 {0, 1}, // AX 5145 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5146 }, 5147 outputs: []outputInfo{ 5148 {0, 1}, // AX 5149 {1, 4}, // DX 5150 }, 5151 }, 5152 }, 5153 { 5154 name: "DIVWU", 5155 argLen: 2, 5156 clobberFlags: true, 5157 asm: x86.ADIVW, 5158 reg: regInfo{ 5159 inputs: []inputInfo{ 5160 {0, 1}, // AX 5161 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5162 }, 5163 outputs: []outputInfo{ 5164 {0, 1}, // AX 5165 {1, 4}, // DX 5166 }, 5167 }, 5168 }, 5169 { 5170 name: "MULQU2", 5171 argLen: 2, 5172 clobberFlags: true, 5173 asm: x86.AMULQ, 5174 reg: regInfo{ 5175 inputs: []inputInfo{ 5176 {0, 1}, // AX 5177 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5178 }, 5179 outputs: []outputInfo{ 5180 {0, 4}, // DX 5181 {1, 1}, // AX 5182 }, 5183 }, 5184 }, 5185 { 5186 name: "DIVQU2", 5187 argLen: 3, 5188 clobberFlags: true, 5189 asm: x86.ADIVQ, 5190 reg: regInfo{ 5191 inputs: []inputInfo{ 5192 {0, 4}, // DX 5193 {1, 1}, // AX 5194 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5195 }, 5196 outputs: []outputInfo{ 5197 {0, 1}, // AX 5198 {1, 4}, // DX 5199 }, 5200 }, 5201 }, 5202 { 5203 name: "ANDQ", 5204 argLen: 2, 5205 commutative: true, 5206 resultInArg0: true, 5207 clobberFlags: true, 5208 asm: x86.AANDQ, 5209 reg: regInfo{ 5210 inputs: []inputInfo{ 5211 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5212 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5213 }, 5214 outputs: []outputInfo{ 5215 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5216 }, 5217 }, 5218 }, 5219 { 5220 name: "ANDL", 5221 argLen: 2, 5222 commutative: true, 5223 resultInArg0: true, 5224 clobberFlags: true, 5225 asm: x86.AANDL, 5226 reg: regInfo{ 5227 inputs: []inputInfo{ 5228 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5229 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5230 }, 5231 outputs: []outputInfo{ 5232 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5233 }, 5234 }, 5235 }, 5236 { 5237 name: "ANDQconst", 5238 auxType: auxInt64, 5239 argLen: 1, 5240 resultInArg0: true, 5241 clobberFlags: true, 5242 asm: x86.AANDQ, 5243 reg: regInfo{ 5244 inputs: []inputInfo{ 5245 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5246 }, 5247 outputs: []outputInfo{ 5248 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5249 }, 5250 }, 5251 }, 5252 { 5253 name: "ANDLconst", 5254 auxType: auxInt32, 5255 argLen: 1, 5256 resultInArg0: true, 5257 clobberFlags: true, 5258 asm: x86.AANDL, 5259 reg: regInfo{ 5260 inputs: []inputInfo{ 5261 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5262 }, 5263 outputs: []outputInfo{ 5264 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5265 }, 5266 }, 5267 }, 5268 { 5269 name: "ORQ", 5270 argLen: 2, 5271 commutative: true, 5272 resultInArg0: true, 5273 clobberFlags: true, 5274 asm: x86.AORQ, 5275 reg: regInfo{ 5276 inputs: []inputInfo{ 5277 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5278 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5279 }, 5280 outputs: []outputInfo{ 5281 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5282 }, 5283 }, 5284 }, 5285 { 5286 name: "ORL", 5287 argLen: 2, 5288 commutative: true, 5289 resultInArg0: true, 5290 clobberFlags: true, 5291 asm: x86.AORL, 5292 reg: regInfo{ 5293 inputs: []inputInfo{ 5294 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5295 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5296 }, 5297 outputs: []outputInfo{ 5298 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5299 }, 5300 }, 5301 }, 5302 { 5303 name: "ORQconst", 5304 auxType: auxInt64, 5305 argLen: 1, 5306 resultInArg0: true, 5307 clobberFlags: true, 5308 asm: x86.AORQ, 5309 reg: regInfo{ 5310 inputs: []inputInfo{ 5311 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5312 }, 5313 outputs: []outputInfo{ 5314 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5315 }, 5316 }, 5317 }, 5318 { 5319 name: "ORLconst", 5320 auxType: auxInt32, 5321 argLen: 1, 5322 resultInArg0: true, 5323 clobberFlags: true, 5324 asm: x86.AORL, 5325 reg: regInfo{ 5326 inputs: []inputInfo{ 5327 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5328 }, 5329 outputs: []outputInfo{ 5330 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5331 }, 5332 }, 5333 }, 5334 { 5335 name: "XORQ", 5336 argLen: 2, 5337 commutative: true, 5338 resultInArg0: true, 5339 clobberFlags: true, 5340 asm: x86.AXORQ, 5341 reg: regInfo{ 5342 inputs: []inputInfo{ 5343 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5344 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5345 }, 5346 outputs: []outputInfo{ 5347 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5348 }, 5349 }, 5350 }, 5351 { 5352 name: "XORL", 5353 argLen: 2, 5354 commutative: true, 5355 resultInArg0: true, 5356 clobberFlags: true, 5357 asm: x86.AXORL, 5358 reg: regInfo{ 5359 inputs: []inputInfo{ 5360 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5361 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5362 }, 5363 outputs: []outputInfo{ 5364 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5365 }, 5366 }, 5367 }, 5368 { 5369 name: "XORQconst", 5370 auxType: auxInt64, 5371 argLen: 1, 5372 resultInArg0: true, 5373 clobberFlags: true, 5374 asm: x86.AXORQ, 5375 reg: regInfo{ 5376 inputs: []inputInfo{ 5377 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5378 }, 5379 outputs: []outputInfo{ 5380 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5381 }, 5382 }, 5383 }, 5384 { 5385 name: "XORLconst", 5386 auxType: auxInt32, 5387 argLen: 1, 5388 resultInArg0: true, 5389 clobberFlags: true, 5390 asm: x86.AXORL, 5391 reg: regInfo{ 5392 inputs: []inputInfo{ 5393 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5394 }, 5395 outputs: []outputInfo{ 5396 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5397 }, 5398 }, 5399 }, 5400 { 5401 name: "CMPQ", 5402 argLen: 2, 5403 asm: x86.ACMPQ, 5404 reg: regInfo{ 5405 inputs: []inputInfo{ 5406 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5407 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5408 }, 5409 }, 5410 }, 5411 { 5412 name: "CMPL", 5413 argLen: 2, 5414 asm: x86.ACMPL, 5415 reg: regInfo{ 5416 inputs: []inputInfo{ 5417 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5418 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5419 }, 5420 }, 5421 }, 5422 { 5423 name: "CMPW", 5424 argLen: 2, 5425 asm: x86.ACMPW, 5426 reg: regInfo{ 5427 inputs: []inputInfo{ 5428 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5429 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5430 }, 5431 }, 5432 }, 5433 { 5434 name: "CMPB", 5435 argLen: 2, 5436 asm: x86.ACMPB, 5437 reg: regInfo{ 5438 inputs: []inputInfo{ 5439 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5440 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5441 }, 5442 }, 5443 }, 5444 { 5445 name: "CMPQconst", 5446 auxType: auxInt64, 5447 argLen: 1, 5448 asm: x86.ACMPQ, 5449 reg: regInfo{ 5450 inputs: []inputInfo{ 5451 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5452 }, 5453 }, 5454 }, 5455 { 5456 name: "CMPLconst", 5457 auxType: auxInt32, 5458 argLen: 1, 5459 asm: x86.ACMPL, 5460 reg: regInfo{ 5461 inputs: []inputInfo{ 5462 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5463 }, 5464 }, 5465 }, 5466 { 5467 name: "CMPWconst", 5468 auxType: auxInt16, 5469 argLen: 1, 5470 asm: x86.ACMPW, 5471 reg: regInfo{ 5472 inputs: []inputInfo{ 5473 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5474 }, 5475 }, 5476 }, 5477 { 5478 name: "CMPBconst", 5479 auxType: auxInt8, 5480 argLen: 1, 5481 asm: x86.ACMPB, 5482 reg: regInfo{ 5483 inputs: []inputInfo{ 5484 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5485 }, 5486 }, 5487 }, 5488 { 5489 name: "UCOMISS", 5490 argLen: 2, 5491 asm: x86.AUCOMISS, 5492 reg: regInfo{ 5493 inputs: []inputInfo{ 5494 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5495 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5496 }, 5497 }, 5498 }, 5499 { 5500 name: "UCOMISD", 5501 argLen: 2, 5502 asm: x86.AUCOMISD, 5503 reg: regInfo{ 5504 inputs: []inputInfo{ 5505 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5506 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5507 }, 5508 }, 5509 }, 5510 { 5511 name: "TESTQ", 5512 argLen: 2, 5513 asm: x86.ATESTQ, 5514 reg: regInfo{ 5515 inputs: []inputInfo{ 5516 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5517 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5518 }, 5519 }, 5520 }, 5521 { 5522 name: "TESTL", 5523 argLen: 2, 5524 asm: x86.ATESTL, 5525 reg: regInfo{ 5526 inputs: []inputInfo{ 5527 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5528 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5529 }, 5530 }, 5531 }, 5532 { 5533 name: "TESTW", 5534 argLen: 2, 5535 asm: x86.ATESTW, 5536 reg: regInfo{ 5537 inputs: []inputInfo{ 5538 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5539 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5540 }, 5541 }, 5542 }, 5543 { 5544 name: "TESTB", 5545 argLen: 2, 5546 asm: x86.ATESTB, 5547 reg: regInfo{ 5548 inputs: []inputInfo{ 5549 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5550 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5551 }, 5552 }, 5553 }, 5554 { 5555 name: "TESTQconst", 5556 auxType: auxInt64, 5557 argLen: 1, 5558 asm: x86.ATESTQ, 5559 reg: regInfo{ 5560 inputs: []inputInfo{ 5561 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5562 }, 5563 }, 5564 }, 5565 { 5566 name: "TESTLconst", 5567 auxType: auxInt32, 5568 argLen: 1, 5569 asm: x86.ATESTL, 5570 reg: regInfo{ 5571 inputs: []inputInfo{ 5572 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5573 }, 5574 }, 5575 }, 5576 { 5577 name: "TESTWconst", 5578 auxType: auxInt16, 5579 argLen: 1, 5580 asm: x86.ATESTW, 5581 reg: regInfo{ 5582 inputs: []inputInfo{ 5583 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5584 }, 5585 }, 5586 }, 5587 { 5588 name: "TESTBconst", 5589 auxType: auxInt8, 5590 argLen: 1, 5591 asm: x86.ATESTB, 5592 reg: regInfo{ 5593 inputs: []inputInfo{ 5594 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5595 }, 5596 }, 5597 }, 5598 { 5599 name: "SHLQ", 5600 argLen: 2, 5601 resultInArg0: true, 5602 clobberFlags: true, 5603 asm: x86.ASHLQ, 5604 reg: regInfo{ 5605 inputs: []inputInfo{ 5606 {1, 2}, // CX 5607 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5608 }, 5609 outputs: []outputInfo{ 5610 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5611 }, 5612 }, 5613 }, 5614 { 5615 name: "SHLL", 5616 argLen: 2, 5617 resultInArg0: true, 5618 clobberFlags: true, 5619 asm: x86.ASHLL, 5620 reg: regInfo{ 5621 inputs: []inputInfo{ 5622 {1, 2}, // CX 5623 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5624 }, 5625 outputs: []outputInfo{ 5626 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5627 }, 5628 }, 5629 }, 5630 { 5631 name: "SHLQconst", 5632 auxType: auxInt64, 5633 argLen: 1, 5634 resultInArg0: true, 5635 clobberFlags: true, 5636 asm: x86.ASHLQ, 5637 reg: regInfo{ 5638 inputs: []inputInfo{ 5639 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5640 }, 5641 outputs: []outputInfo{ 5642 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5643 }, 5644 }, 5645 }, 5646 { 5647 name: "SHLLconst", 5648 auxType: auxInt32, 5649 argLen: 1, 5650 resultInArg0: true, 5651 clobberFlags: true, 5652 asm: x86.ASHLL, 5653 reg: regInfo{ 5654 inputs: []inputInfo{ 5655 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5656 }, 5657 outputs: []outputInfo{ 5658 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5659 }, 5660 }, 5661 }, 5662 { 5663 name: "SHRQ", 5664 argLen: 2, 5665 resultInArg0: true, 5666 clobberFlags: true, 5667 asm: x86.ASHRQ, 5668 reg: regInfo{ 5669 inputs: []inputInfo{ 5670 {1, 2}, // CX 5671 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5672 }, 5673 outputs: []outputInfo{ 5674 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5675 }, 5676 }, 5677 }, 5678 { 5679 name: "SHRL", 5680 argLen: 2, 5681 resultInArg0: true, 5682 clobberFlags: true, 5683 asm: x86.ASHRL, 5684 reg: regInfo{ 5685 inputs: []inputInfo{ 5686 {1, 2}, // CX 5687 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5688 }, 5689 outputs: []outputInfo{ 5690 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5691 }, 5692 }, 5693 }, 5694 { 5695 name: "SHRW", 5696 argLen: 2, 5697 resultInArg0: true, 5698 clobberFlags: true, 5699 asm: x86.ASHRW, 5700 reg: regInfo{ 5701 inputs: []inputInfo{ 5702 {1, 2}, // CX 5703 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5704 }, 5705 outputs: []outputInfo{ 5706 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5707 }, 5708 }, 5709 }, 5710 { 5711 name: "SHRB", 5712 argLen: 2, 5713 resultInArg0: true, 5714 clobberFlags: true, 5715 asm: x86.ASHRB, 5716 reg: regInfo{ 5717 inputs: []inputInfo{ 5718 {1, 2}, // CX 5719 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5720 }, 5721 outputs: []outputInfo{ 5722 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5723 }, 5724 }, 5725 }, 5726 { 5727 name: "SHRQconst", 5728 auxType: auxInt64, 5729 argLen: 1, 5730 resultInArg0: true, 5731 clobberFlags: true, 5732 asm: x86.ASHRQ, 5733 reg: regInfo{ 5734 inputs: []inputInfo{ 5735 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5736 }, 5737 outputs: []outputInfo{ 5738 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5739 }, 5740 }, 5741 }, 5742 { 5743 name: "SHRLconst", 5744 auxType: auxInt32, 5745 argLen: 1, 5746 resultInArg0: true, 5747 clobberFlags: true, 5748 asm: x86.ASHRL, 5749 reg: regInfo{ 5750 inputs: []inputInfo{ 5751 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5752 }, 5753 outputs: []outputInfo{ 5754 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5755 }, 5756 }, 5757 }, 5758 { 5759 name: "SHRWconst", 5760 auxType: auxInt16, 5761 argLen: 1, 5762 resultInArg0: true, 5763 clobberFlags: true, 5764 asm: x86.ASHRW, 5765 reg: regInfo{ 5766 inputs: []inputInfo{ 5767 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5768 }, 5769 outputs: []outputInfo{ 5770 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5771 }, 5772 }, 5773 }, 5774 { 5775 name: "SHRBconst", 5776 auxType: auxInt8, 5777 argLen: 1, 5778 resultInArg0: true, 5779 clobberFlags: true, 5780 asm: x86.ASHRB, 5781 reg: regInfo{ 5782 inputs: []inputInfo{ 5783 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5784 }, 5785 outputs: []outputInfo{ 5786 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5787 }, 5788 }, 5789 }, 5790 { 5791 name: "SARQ", 5792 argLen: 2, 5793 resultInArg0: true, 5794 clobberFlags: true, 5795 asm: x86.ASARQ, 5796 reg: regInfo{ 5797 inputs: []inputInfo{ 5798 {1, 2}, // CX 5799 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5800 }, 5801 outputs: []outputInfo{ 5802 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5803 }, 5804 }, 5805 }, 5806 { 5807 name: "SARL", 5808 argLen: 2, 5809 resultInArg0: true, 5810 clobberFlags: true, 5811 asm: x86.ASARL, 5812 reg: regInfo{ 5813 inputs: []inputInfo{ 5814 {1, 2}, // CX 5815 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5816 }, 5817 outputs: []outputInfo{ 5818 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5819 }, 5820 }, 5821 }, 5822 { 5823 name: "SARW", 5824 argLen: 2, 5825 resultInArg0: true, 5826 clobberFlags: true, 5827 asm: x86.ASARW, 5828 reg: regInfo{ 5829 inputs: []inputInfo{ 5830 {1, 2}, // CX 5831 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5832 }, 5833 outputs: []outputInfo{ 5834 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5835 }, 5836 }, 5837 }, 5838 { 5839 name: "SARB", 5840 argLen: 2, 5841 resultInArg0: true, 5842 clobberFlags: true, 5843 asm: x86.ASARB, 5844 reg: regInfo{ 5845 inputs: []inputInfo{ 5846 {1, 2}, // CX 5847 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5848 }, 5849 outputs: []outputInfo{ 5850 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5851 }, 5852 }, 5853 }, 5854 { 5855 name: "SARQconst", 5856 auxType: auxInt64, 5857 argLen: 1, 5858 resultInArg0: true, 5859 clobberFlags: true, 5860 asm: x86.ASARQ, 5861 reg: regInfo{ 5862 inputs: []inputInfo{ 5863 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5864 }, 5865 outputs: []outputInfo{ 5866 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5867 }, 5868 }, 5869 }, 5870 { 5871 name: "SARLconst", 5872 auxType: auxInt32, 5873 argLen: 1, 5874 resultInArg0: true, 5875 clobberFlags: true, 5876 asm: x86.ASARL, 5877 reg: regInfo{ 5878 inputs: []inputInfo{ 5879 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5880 }, 5881 outputs: []outputInfo{ 5882 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5883 }, 5884 }, 5885 }, 5886 { 5887 name: "SARWconst", 5888 auxType: auxInt16, 5889 argLen: 1, 5890 resultInArg0: true, 5891 clobberFlags: true, 5892 asm: x86.ASARW, 5893 reg: regInfo{ 5894 inputs: []inputInfo{ 5895 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5896 }, 5897 outputs: []outputInfo{ 5898 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5899 }, 5900 }, 5901 }, 5902 { 5903 name: "SARBconst", 5904 auxType: auxInt8, 5905 argLen: 1, 5906 resultInArg0: true, 5907 clobberFlags: true, 5908 asm: x86.ASARB, 5909 reg: regInfo{ 5910 inputs: []inputInfo{ 5911 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5912 }, 5913 outputs: []outputInfo{ 5914 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5915 }, 5916 }, 5917 }, 5918 { 5919 name: "ROLQconst", 5920 auxType: auxInt64, 5921 argLen: 1, 5922 resultInArg0: true, 5923 clobberFlags: true, 5924 asm: x86.AROLQ, 5925 reg: regInfo{ 5926 inputs: []inputInfo{ 5927 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5928 }, 5929 outputs: []outputInfo{ 5930 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5931 }, 5932 }, 5933 }, 5934 { 5935 name: "ROLLconst", 5936 auxType: auxInt32, 5937 argLen: 1, 5938 resultInArg0: true, 5939 clobberFlags: true, 5940 asm: x86.AROLL, 5941 reg: regInfo{ 5942 inputs: []inputInfo{ 5943 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5944 }, 5945 outputs: []outputInfo{ 5946 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5947 }, 5948 }, 5949 }, 5950 { 5951 name: "ROLWconst", 5952 auxType: auxInt16, 5953 argLen: 1, 5954 resultInArg0: true, 5955 clobberFlags: true, 5956 asm: x86.AROLW, 5957 reg: regInfo{ 5958 inputs: []inputInfo{ 5959 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5960 }, 5961 outputs: []outputInfo{ 5962 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5963 }, 5964 }, 5965 }, 5966 { 5967 name: "ROLBconst", 5968 auxType: auxInt8, 5969 argLen: 1, 5970 resultInArg0: true, 5971 clobberFlags: true, 5972 asm: x86.AROLB, 5973 reg: regInfo{ 5974 inputs: []inputInfo{ 5975 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5976 }, 5977 outputs: []outputInfo{ 5978 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5979 }, 5980 }, 5981 }, 5982 { 5983 name: "NEGQ", 5984 argLen: 1, 5985 resultInArg0: true, 5986 clobberFlags: true, 5987 asm: x86.ANEGQ, 5988 reg: regInfo{ 5989 inputs: []inputInfo{ 5990 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5991 }, 5992 outputs: []outputInfo{ 5993 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5994 }, 5995 }, 5996 }, 5997 { 5998 name: "NEGL", 5999 argLen: 1, 6000 resultInArg0: true, 6001 clobberFlags: true, 6002 asm: x86.ANEGL, 6003 reg: regInfo{ 6004 inputs: []inputInfo{ 6005 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6006 }, 6007 outputs: []outputInfo{ 6008 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6009 }, 6010 }, 6011 }, 6012 { 6013 name: "NOTQ", 6014 argLen: 1, 6015 resultInArg0: true, 6016 clobberFlags: true, 6017 asm: x86.ANOTQ, 6018 reg: regInfo{ 6019 inputs: []inputInfo{ 6020 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6021 }, 6022 outputs: []outputInfo{ 6023 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6024 }, 6025 }, 6026 }, 6027 { 6028 name: "NOTL", 6029 argLen: 1, 6030 resultInArg0: true, 6031 clobberFlags: true, 6032 asm: x86.ANOTL, 6033 reg: regInfo{ 6034 inputs: []inputInfo{ 6035 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6036 }, 6037 outputs: []outputInfo{ 6038 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6039 }, 6040 }, 6041 }, 6042 { 6043 name: "BSFQ", 6044 argLen: 1, 6045 asm: x86.ABSFQ, 6046 reg: regInfo{ 6047 inputs: []inputInfo{ 6048 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6049 }, 6050 outputs: []outputInfo{ 6051 {1, 0}, 6052 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6053 }, 6054 }, 6055 }, 6056 { 6057 name: "BSFL", 6058 argLen: 1, 6059 asm: x86.ABSFL, 6060 reg: regInfo{ 6061 inputs: []inputInfo{ 6062 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6063 }, 6064 outputs: []outputInfo{ 6065 {1, 0}, 6066 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6067 }, 6068 }, 6069 }, 6070 { 6071 name: "CMOVQEQ", 6072 argLen: 3, 6073 resultInArg0: true, 6074 asm: x86.ACMOVQEQ, 6075 reg: regInfo{ 6076 inputs: []inputInfo{ 6077 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6078 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6079 }, 6080 outputs: []outputInfo{ 6081 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6082 }, 6083 }, 6084 }, 6085 { 6086 name: "CMOVLEQ", 6087 argLen: 3, 6088 resultInArg0: true, 6089 asm: x86.ACMOVLEQ, 6090 reg: regInfo{ 6091 inputs: []inputInfo{ 6092 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6093 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6094 }, 6095 outputs: []outputInfo{ 6096 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6097 }, 6098 }, 6099 }, 6100 { 6101 name: "BSWAPQ", 6102 argLen: 1, 6103 resultInArg0: true, 6104 clobberFlags: true, 6105 asm: x86.ABSWAPQ, 6106 reg: regInfo{ 6107 inputs: []inputInfo{ 6108 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6109 }, 6110 outputs: []outputInfo{ 6111 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6112 }, 6113 }, 6114 }, 6115 { 6116 name: "BSWAPL", 6117 argLen: 1, 6118 resultInArg0: true, 6119 clobberFlags: true, 6120 asm: x86.ABSWAPL, 6121 reg: regInfo{ 6122 inputs: []inputInfo{ 6123 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6124 }, 6125 outputs: []outputInfo{ 6126 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6127 }, 6128 }, 6129 }, 6130 { 6131 name: "SQRTSD", 6132 argLen: 1, 6133 asm: x86.ASQRTSD, 6134 reg: regInfo{ 6135 inputs: []inputInfo{ 6136 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6137 }, 6138 outputs: []outputInfo{ 6139 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6140 }, 6141 }, 6142 }, 6143 { 6144 name: "SBBQcarrymask", 6145 argLen: 1, 6146 asm: x86.ASBBQ, 6147 reg: regInfo{ 6148 outputs: []outputInfo{ 6149 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6150 }, 6151 }, 6152 }, 6153 { 6154 name: "SBBLcarrymask", 6155 argLen: 1, 6156 asm: x86.ASBBL, 6157 reg: regInfo{ 6158 outputs: []outputInfo{ 6159 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6160 }, 6161 }, 6162 }, 6163 { 6164 name: "SETEQ", 6165 argLen: 1, 6166 asm: x86.ASETEQ, 6167 reg: regInfo{ 6168 outputs: []outputInfo{ 6169 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6170 }, 6171 }, 6172 }, 6173 { 6174 name: "SETNE", 6175 argLen: 1, 6176 asm: x86.ASETNE, 6177 reg: regInfo{ 6178 outputs: []outputInfo{ 6179 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6180 }, 6181 }, 6182 }, 6183 { 6184 name: "SETL", 6185 argLen: 1, 6186 asm: x86.ASETLT, 6187 reg: regInfo{ 6188 outputs: []outputInfo{ 6189 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6190 }, 6191 }, 6192 }, 6193 { 6194 name: "SETLE", 6195 argLen: 1, 6196 asm: x86.ASETLE, 6197 reg: regInfo{ 6198 outputs: []outputInfo{ 6199 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6200 }, 6201 }, 6202 }, 6203 { 6204 name: "SETG", 6205 argLen: 1, 6206 asm: x86.ASETGT, 6207 reg: regInfo{ 6208 outputs: []outputInfo{ 6209 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6210 }, 6211 }, 6212 }, 6213 { 6214 name: "SETGE", 6215 argLen: 1, 6216 asm: x86.ASETGE, 6217 reg: regInfo{ 6218 outputs: []outputInfo{ 6219 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6220 }, 6221 }, 6222 }, 6223 { 6224 name: "SETB", 6225 argLen: 1, 6226 asm: x86.ASETCS, 6227 reg: regInfo{ 6228 outputs: []outputInfo{ 6229 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6230 }, 6231 }, 6232 }, 6233 { 6234 name: "SETBE", 6235 argLen: 1, 6236 asm: x86.ASETLS, 6237 reg: regInfo{ 6238 outputs: []outputInfo{ 6239 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6240 }, 6241 }, 6242 }, 6243 { 6244 name: "SETA", 6245 argLen: 1, 6246 asm: x86.ASETHI, 6247 reg: regInfo{ 6248 outputs: []outputInfo{ 6249 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6250 }, 6251 }, 6252 }, 6253 { 6254 name: "SETAE", 6255 argLen: 1, 6256 asm: x86.ASETCC, 6257 reg: regInfo{ 6258 outputs: []outputInfo{ 6259 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6260 }, 6261 }, 6262 }, 6263 { 6264 name: "SETEQF", 6265 argLen: 1, 6266 clobberFlags: true, 6267 asm: x86.ASETEQ, 6268 reg: regInfo{ 6269 clobbers: 1, // AX 6270 outputs: []outputInfo{ 6271 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6272 }, 6273 }, 6274 }, 6275 { 6276 name: "SETNEF", 6277 argLen: 1, 6278 clobberFlags: true, 6279 asm: x86.ASETNE, 6280 reg: regInfo{ 6281 clobbers: 1, // AX 6282 outputs: []outputInfo{ 6283 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6284 }, 6285 }, 6286 }, 6287 { 6288 name: "SETORD", 6289 argLen: 1, 6290 asm: x86.ASETPC, 6291 reg: regInfo{ 6292 outputs: []outputInfo{ 6293 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6294 }, 6295 }, 6296 }, 6297 { 6298 name: "SETNAN", 6299 argLen: 1, 6300 asm: x86.ASETPS, 6301 reg: regInfo{ 6302 outputs: []outputInfo{ 6303 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6304 }, 6305 }, 6306 }, 6307 { 6308 name: "SETGF", 6309 argLen: 1, 6310 asm: x86.ASETHI, 6311 reg: regInfo{ 6312 outputs: []outputInfo{ 6313 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6314 }, 6315 }, 6316 }, 6317 { 6318 name: "SETGEF", 6319 argLen: 1, 6320 asm: x86.ASETCC, 6321 reg: regInfo{ 6322 outputs: []outputInfo{ 6323 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6324 }, 6325 }, 6326 }, 6327 { 6328 name: "MOVBQSX", 6329 argLen: 1, 6330 asm: x86.AMOVBQSX, 6331 reg: regInfo{ 6332 inputs: []inputInfo{ 6333 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6334 }, 6335 outputs: []outputInfo{ 6336 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6337 }, 6338 }, 6339 }, 6340 { 6341 name: "MOVBQZX", 6342 argLen: 1, 6343 asm: x86.AMOVBLZX, 6344 reg: regInfo{ 6345 inputs: []inputInfo{ 6346 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6347 }, 6348 outputs: []outputInfo{ 6349 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6350 }, 6351 }, 6352 }, 6353 { 6354 name: "MOVWQSX", 6355 argLen: 1, 6356 asm: x86.AMOVWQSX, 6357 reg: regInfo{ 6358 inputs: []inputInfo{ 6359 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6360 }, 6361 outputs: []outputInfo{ 6362 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6363 }, 6364 }, 6365 }, 6366 { 6367 name: "MOVWQZX", 6368 argLen: 1, 6369 asm: x86.AMOVWLZX, 6370 reg: regInfo{ 6371 inputs: []inputInfo{ 6372 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6373 }, 6374 outputs: []outputInfo{ 6375 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6376 }, 6377 }, 6378 }, 6379 { 6380 name: "MOVLQSX", 6381 argLen: 1, 6382 asm: x86.AMOVLQSX, 6383 reg: regInfo{ 6384 inputs: []inputInfo{ 6385 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6386 }, 6387 outputs: []outputInfo{ 6388 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6389 }, 6390 }, 6391 }, 6392 { 6393 name: "MOVLQZX", 6394 argLen: 1, 6395 asm: x86.AMOVL, 6396 reg: regInfo{ 6397 inputs: []inputInfo{ 6398 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6399 }, 6400 outputs: []outputInfo{ 6401 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6402 }, 6403 }, 6404 }, 6405 { 6406 name: "MOVLconst", 6407 auxType: auxInt32, 6408 argLen: 0, 6409 rematerializeable: true, 6410 asm: x86.AMOVL, 6411 reg: regInfo{ 6412 outputs: []outputInfo{ 6413 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6414 }, 6415 }, 6416 }, 6417 { 6418 name: "MOVQconst", 6419 auxType: auxInt64, 6420 argLen: 0, 6421 rematerializeable: true, 6422 asm: x86.AMOVQ, 6423 reg: regInfo{ 6424 outputs: []outputInfo{ 6425 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6426 }, 6427 }, 6428 }, 6429 { 6430 name: "CVTTSD2SL", 6431 argLen: 1, 6432 asm: x86.ACVTTSD2SL, 6433 reg: regInfo{ 6434 inputs: []inputInfo{ 6435 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6436 }, 6437 outputs: []outputInfo{ 6438 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6439 }, 6440 }, 6441 }, 6442 { 6443 name: "CVTTSD2SQ", 6444 argLen: 1, 6445 asm: x86.ACVTTSD2SQ, 6446 reg: regInfo{ 6447 inputs: []inputInfo{ 6448 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6449 }, 6450 outputs: []outputInfo{ 6451 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6452 }, 6453 }, 6454 }, 6455 { 6456 name: "CVTTSS2SL", 6457 argLen: 1, 6458 asm: x86.ACVTTSS2SL, 6459 reg: regInfo{ 6460 inputs: []inputInfo{ 6461 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6462 }, 6463 outputs: []outputInfo{ 6464 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6465 }, 6466 }, 6467 }, 6468 { 6469 name: "CVTTSS2SQ", 6470 argLen: 1, 6471 asm: x86.ACVTTSS2SQ, 6472 reg: regInfo{ 6473 inputs: []inputInfo{ 6474 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6475 }, 6476 outputs: []outputInfo{ 6477 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6478 }, 6479 }, 6480 }, 6481 { 6482 name: "CVTSL2SS", 6483 argLen: 1, 6484 asm: x86.ACVTSL2SS, 6485 reg: regInfo{ 6486 inputs: []inputInfo{ 6487 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6488 }, 6489 outputs: []outputInfo{ 6490 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6491 }, 6492 }, 6493 }, 6494 { 6495 name: "CVTSL2SD", 6496 argLen: 1, 6497 asm: x86.ACVTSL2SD, 6498 reg: regInfo{ 6499 inputs: []inputInfo{ 6500 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6501 }, 6502 outputs: []outputInfo{ 6503 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6504 }, 6505 }, 6506 }, 6507 { 6508 name: "CVTSQ2SS", 6509 argLen: 1, 6510 asm: x86.ACVTSQ2SS, 6511 reg: regInfo{ 6512 inputs: []inputInfo{ 6513 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6514 }, 6515 outputs: []outputInfo{ 6516 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6517 }, 6518 }, 6519 }, 6520 { 6521 name: "CVTSQ2SD", 6522 argLen: 1, 6523 asm: x86.ACVTSQ2SD, 6524 reg: regInfo{ 6525 inputs: []inputInfo{ 6526 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6527 }, 6528 outputs: []outputInfo{ 6529 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6530 }, 6531 }, 6532 }, 6533 { 6534 name: "CVTSD2SS", 6535 argLen: 1, 6536 asm: x86.ACVTSD2SS, 6537 reg: regInfo{ 6538 inputs: []inputInfo{ 6539 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6540 }, 6541 outputs: []outputInfo{ 6542 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6543 }, 6544 }, 6545 }, 6546 { 6547 name: "CVTSS2SD", 6548 argLen: 1, 6549 asm: x86.ACVTSS2SD, 6550 reg: regInfo{ 6551 inputs: []inputInfo{ 6552 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6553 }, 6554 outputs: []outputInfo{ 6555 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6556 }, 6557 }, 6558 }, 6559 { 6560 name: "PXOR", 6561 argLen: 2, 6562 commutative: true, 6563 resultInArg0: true, 6564 asm: x86.APXOR, 6565 reg: regInfo{ 6566 inputs: []inputInfo{ 6567 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6568 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6569 }, 6570 outputs: []outputInfo{ 6571 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6572 }, 6573 }, 6574 }, 6575 { 6576 name: "LEAQ", 6577 auxType: auxSymOff, 6578 argLen: 1, 6579 rematerializeable: true, 6580 asm: x86.ALEAQ, 6581 reg: regInfo{ 6582 inputs: []inputInfo{ 6583 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6584 }, 6585 outputs: []outputInfo{ 6586 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6587 }, 6588 }, 6589 }, 6590 { 6591 name: "LEAQ1", 6592 auxType: auxSymOff, 6593 argLen: 2, 6594 reg: regInfo{ 6595 inputs: []inputInfo{ 6596 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6597 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6598 }, 6599 outputs: []outputInfo{ 6600 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6601 }, 6602 }, 6603 }, 6604 { 6605 name: "LEAQ2", 6606 auxType: auxSymOff, 6607 argLen: 2, 6608 reg: regInfo{ 6609 inputs: []inputInfo{ 6610 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6611 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6612 }, 6613 outputs: []outputInfo{ 6614 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6615 }, 6616 }, 6617 }, 6618 { 6619 name: "LEAQ4", 6620 auxType: auxSymOff, 6621 argLen: 2, 6622 reg: regInfo{ 6623 inputs: []inputInfo{ 6624 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6625 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6626 }, 6627 outputs: []outputInfo{ 6628 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6629 }, 6630 }, 6631 }, 6632 { 6633 name: "LEAQ8", 6634 auxType: auxSymOff, 6635 argLen: 2, 6636 reg: regInfo{ 6637 inputs: []inputInfo{ 6638 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6639 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6640 }, 6641 outputs: []outputInfo{ 6642 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6643 }, 6644 }, 6645 }, 6646 { 6647 name: "LEAL", 6648 auxType: auxSymOff, 6649 argLen: 1, 6650 rematerializeable: true, 6651 asm: x86.ALEAL, 6652 reg: regInfo{ 6653 inputs: []inputInfo{ 6654 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6655 }, 6656 outputs: []outputInfo{ 6657 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6658 }, 6659 }, 6660 }, 6661 { 6662 name: "MOVBload", 6663 auxType: auxSymOff, 6664 argLen: 2, 6665 faultOnNilArg0: true, 6666 asm: x86.AMOVBLZX, 6667 reg: regInfo{ 6668 inputs: []inputInfo{ 6669 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6670 }, 6671 outputs: []outputInfo{ 6672 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6673 }, 6674 }, 6675 }, 6676 { 6677 name: "MOVBQSXload", 6678 auxType: auxSymOff, 6679 argLen: 2, 6680 faultOnNilArg0: true, 6681 asm: x86.AMOVBQSX, 6682 reg: regInfo{ 6683 inputs: []inputInfo{ 6684 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6685 }, 6686 outputs: []outputInfo{ 6687 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6688 }, 6689 }, 6690 }, 6691 { 6692 name: "MOVWload", 6693 auxType: auxSymOff, 6694 argLen: 2, 6695 faultOnNilArg0: true, 6696 asm: x86.AMOVWLZX, 6697 reg: regInfo{ 6698 inputs: []inputInfo{ 6699 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6700 }, 6701 outputs: []outputInfo{ 6702 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6703 }, 6704 }, 6705 }, 6706 { 6707 name: "MOVWQSXload", 6708 auxType: auxSymOff, 6709 argLen: 2, 6710 faultOnNilArg0: true, 6711 asm: x86.AMOVWQSX, 6712 reg: regInfo{ 6713 inputs: []inputInfo{ 6714 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6715 }, 6716 outputs: []outputInfo{ 6717 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6718 }, 6719 }, 6720 }, 6721 { 6722 name: "MOVLload", 6723 auxType: auxSymOff, 6724 argLen: 2, 6725 faultOnNilArg0: true, 6726 asm: x86.AMOVL, 6727 reg: regInfo{ 6728 inputs: []inputInfo{ 6729 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6730 }, 6731 outputs: []outputInfo{ 6732 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6733 }, 6734 }, 6735 }, 6736 { 6737 name: "MOVLQSXload", 6738 auxType: auxSymOff, 6739 argLen: 2, 6740 faultOnNilArg0: true, 6741 asm: x86.AMOVLQSX, 6742 reg: regInfo{ 6743 inputs: []inputInfo{ 6744 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6745 }, 6746 outputs: []outputInfo{ 6747 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6748 }, 6749 }, 6750 }, 6751 { 6752 name: "MOVQload", 6753 auxType: auxSymOff, 6754 argLen: 2, 6755 faultOnNilArg0: true, 6756 asm: x86.AMOVQ, 6757 reg: regInfo{ 6758 inputs: []inputInfo{ 6759 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6760 }, 6761 outputs: []outputInfo{ 6762 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6763 }, 6764 }, 6765 }, 6766 { 6767 name: "MOVBstore", 6768 auxType: auxSymOff, 6769 argLen: 3, 6770 faultOnNilArg0: true, 6771 asm: x86.AMOVB, 6772 reg: regInfo{ 6773 inputs: []inputInfo{ 6774 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6775 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6776 }, 6777 }, 6778 }, 6779 { 6780 name: "MOVWstore", 6781 auxType: auxSymOff, 6782 argLen: 3, 6783 faultOnNilArg0: true, 6784 asm: x86.AMOVW, 6785 reg: regInfo{ 6786 inputs: []inputInfo{ 6787 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6788 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6789 }, 6790 }, 6791 }, 6792 { 6793 name: "MOVLstore", 6794 auxType: auxSymOff, 6795 argLen: 3, 6796 faultOnNilArg0: true, 6797 asm: x86.AMOVL, 6798 reg: regInfo{ 6799 inputs: []inputInfo{ 6800 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6801 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6802 }, 6803 }, 6804 }, 6805 { 6806 name: "MOVQstore", 6807 auxType: auxSymOff, 6808 argLen: 3, 6809 faultOnNilArg0: true, 6810 asm: x86.AMOVQ, 6811 reg: regInfo{ 6812 inputs: []inputInfo{ 6813 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6814 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6815 }, 6816 }, 6817 }, 6818 { 6819 name: "MOVOload", 6820 auxType: auxSymOff, 6821 argLen: 2, 6822 faultOnNilArg0: true, 6823 asm: x86.AMOVUPS, 6824 reg: regInfo{ 6825 inputs: []inputInfo{ 6826 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6827 }, 6828 outputs: []outputInfo{ 6829 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6830 }, 6831 }, 6832 }, 6833 { 6834 name: "MOVOstore", 6835 auxType: auxSymOff, 6836 argLen: 3, 6837 faultOnNilArg0: true, 6838 asm: x86.AMOVUPS, 6839 reg: regInfo{ 6840 inputs: []inputInfo{ 6841 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6842 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6843 }, 6844 }, 6845 }, 6846 { 6847 name: "MOVBloadidx1", 6848 auxType: auxSymOff, 6849 argLen: 3, 6850 asm: x86.AMOVBLZX, 6851 reg: regInfo{ 6852 inputs: []inputInfo{ 6853 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6854 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6855 }, 6856 outputs: []outputInfo{ 6857 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6858 }, 6859 }, 6860 }, 6861 { 6862 name: "MOVWloadidx1", 6863 auxType: auxSymOff, 6864 argLen: 3, 6865 asm: x86.AMOVWLZX, 6866 reg: regInfo{ 6867 inputs: []inputInfo{ 6868 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6869 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6870 }, 6871 outputs: []outputInfo{ 6872 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6873 }, 6874 }, 6875 }, 6876 { 6877 name: "MOVWloadidx2", 6878 auxType: auxSymOff, 6879 argLen: 3, 6880 asm: x86.AMOVWLZX, 6881 reg: regInfo{ 6882 inputs: []inputInfo{ 6883 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6884 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6885 }, 6886 outputs: []outputInfo{ 6887 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6888 }, 6889 }, 6890 }, 6891 { 6892 name: "MOVLloadidx1", 6893 auxType: auxSymOff, 6894 argLen: 3, 6895 asm: x86.AMOVL, 6896 reg: regInfo{ 6897 inputs: []inputInfo{ 6898 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6899 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6900 }, 6901 outputs: []outputInfo{ 6902 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6903 }, 6904 }, 6905 }, 6906 { 6907 name: "MOVLloadidx4", 6908 auxType: auxSymOff, 6909 argLen: 3, 6910 asm: x86.AMOVL, 6911 reg: regInfo{ 6912 inputs: []inputInfo{ 6913 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6914 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6915 }, 6916 outputs: []outputInfo{ 6917 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6918 }, 6919 }, 6920 }, 6921 { 6922 name: "MOVQloadidx1", 6923 auxType: auxSymOff, 6924 argLen: 3, 6925 asm: x86.AMOVQ, 6926 reg: regInfo{ 6927 inputs: []inputInfo{ 6928 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6929 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6930 }, 6931 outputs: []outputInfo{ 6932 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6933 }, 6934 }, 6935 }, 6936 { 6937 name: "MOVQloadidx8", 6938 auxType: auxSymOff, 6939 argLen: 3, 6940 asm: x86.AMOVQ, 6941 reg: regInfo{ 6942 inputs: []inputInfo{ 6943 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6944 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6945 }, 6946 outputs: []outputInfo{ 6947 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6948 }, 6949 }, 6950 }, 6951 { 6952 name: "MOVBstoreidx1", 6953 auxType: auxSymOff, 6954 argLen: 4, 6955 asm: x86.AMOVB, 6956 reg: regInfo{ 6957 inputs: []inputInfo{ 6958 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6959 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6960 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6961 }, 6962 }, 6963 }, 6964 { 6965 name: "MOVWstoreidx1", 6966 auxType: auxSymOff, 6967 argLen: 4, 6968 asm: x86.AMOVW, 6969 reg: regInfo{ 6970 inputs: []inputInfo{ 6971 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6972 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6973 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6974 }, 6975 }, 6976 }, 6977 { 6978 name: "MOVWstoreidx2", 6979 auxType: auxSymOff, 6980 argLen: 4, 6981 asm: x86.AMOVW, 6982 reg: regInfo{ 6983 inputs: []inputInfo{ 6984 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6985 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6986 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6987 }, 6988 }, 6989 }, 6990 { 6991 name: "MOVLstoreidx1", 6992 auxType: auxSymOff, 6993 argLen: 4, 6994 asm: x86.AMOVL, 6995 reg: regInfo{ 6996 inputs: []inputInfo{ 6997 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6998 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6999 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7000 }, 7001 }, 7002 }, 7003 { 7004 name: "MOVLstoreidx4", 7005 auxType: auxSymOff, 7006 argLen: 4, 7007 asm: x86.AMOVL, 7008 reg: regInfo{ 7009 inputs: []inputInfo{ 7010 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7011 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7012 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7013 }, 7014 }, 7015 }, 7016 { 7017 name: "MOVQstoreidx1", 7018 auxType: auxSymOff, 7019 argLen: 4, 7020 asm: x86.AMOVQ, 7021 reg: regInfo{ 7022 inputs: []inputInfo{ 7023 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7024 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7025 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7026 }, 7027 }, 7028 }, 7029 { 7030 name: "MOVQstoreidx8", 7031 auxType: auxSymOff, 7032 argLen: 4, 7033 asm: x86.AMOVQ, 7034 reg: regInfo{ 7035 inputs: []inputInfo{ 7036 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7037 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7038 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7039 }, 7040 }, 7041 }, 7042 { 7043 name: "MOVBstoreconst", 7044 auxType: auxSymValAndOff, 7045 argLen: 2, 7046 faultOnNilArg0: true, 7047 asm: x86.AMOVB, 7048 reg: regInfo{ 7049 inputs: []inputInfo{ 7050 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7051 }, 7052 }, 7053 }, 7054 { 7055 name: "MOVWstoreconst", 7056 auxType: auxSymValAndOff, 7057 argLen: 2, 7058 faultOnNilArg0: true, 7059 asm: x86.AMOVW, 7060 reg: regInfo{ 7061 inputs: []inputInfo{ 7062 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7063 }, 7064 }, 7065 }, 7066 { 7067 name: "MOVLstoreconst", 7068 auxType: auxSymValAndOff, 7069 argLen: 2, 7070 faultOnNilArg0: true, 7071 asm: x86.AMOVL, 7072 reg: regInfo{ 7073 inputs: []inputInfo{ 7074 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7075 }, 7076 }, 7077 }, 7078 { 7079 name: "MOVQstoreconst", 7080 auxType: auxSymValAndOff, 7081 argLen: 2, 7082 faultOnNilArg0: true, 7083 asm: x86.AMOVQ, 7084 reg: regInfo{ 7085 inputs: []inputInfo{ 7086 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7087 }, 7088 }, 7089 }, 7090 { 7091 name: "MOVBstoreconstidx1", 7092 auxType: auxSymValAndOff, 7093 argLen: 3, 7094 asm: x86.AMOVB, 7095 reg: regInfo{ 7096 inputs: []inputInfo{ 7097 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7098 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7099 }, 7100 }, 7101 }, 7102 { 7103 name: "MOVWstoreconstidx1", 7104 auxType: auxSymValAndOff, 7105 argLen: 3, 7106 asm: x86.AMOVW, 7107 reg: regInfo{ 7108 inputs: []inputInfo{ 7109 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7110 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7111 }, 7112 }, 7113 }, 7114 { 7115 name: "MOVWstoreconstidx2", 7116 auxType: auxSymValAndOff, 7117 argLen: 3, 7118 asm: x86.AMOVW, 7119 reg: regInfo{ 7120 inputs: []inputInfo{ 7121 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7122 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7123 }, 7124 }, 7125 }, 7126 { 7127 name: "MOVLstoreconstidx1", 7128 auxType: auxSymValAndOff, 7129 argLen: 3, 7130 asm: x86.AMOVL, 7131 reg: regInfo{ 7132 inputs: []inputInfo{ 7133 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7134 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7135 }, 7136 }, 7137 }, 7138 { 7139 name: "MOVLstoreconstidx4", 7140 auxType: auxSymValAndOff, 7141 argLen: 3, 7142 asm: x86.AMOVL, 7143 reg: regInfo{ 7144 inputs: []inputInfo{ 7145 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7146 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7147 }, 7148 }, 7149 }, 7150 { 7151 name: "MOVQstoreconstidx1", 7152 auxType: auxSymValAndOff, 7153 argLen: 3, 7154 asm: x86.AMOVQ, 7155 reg: regInfo{ 7156 inputs: []inputInfo{ 7157 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7158 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7159 }, 7160 }, 7161 }, 7162 { 7163 name: "MOVQstoreconstidx8", 7164 auxType: auxSymValAndOff, 7165 argLen: 3, 7166 asm: x86.AMOVQ, 7167 reg: regInfo{ 7168 inputs: []inputInfo{ 7169 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7170 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7171 }, 7172 }, 7173 }, 7174 { 7175 name: "DUFFZERO", 7176 auxType: auxInt64, 7177 argLen: 3, 7178 clobberFlags: true, 7179 faultOnNilArg0: true, 7180 reg: regInfo{ 7181 inputs: []inputInfo{ 7182 {0, 128}, // DI 7183 {1, 65536}, // X0 7184 }, 7185 clobbers: 128, // DI 7186 }, 7187 }, 7188 { 7189 name: "MOVOconst", 7190 auxType: auxInt128, 7191 argLen: 0, 7192 rematerializeable: true, 7193 reg: regInfo{ 7194 outputs: []outputInfo{ 7195 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7196 }, 7197 }, 7198 }, 7199 { 7200 name: "REPSTOSQ", 7201 argLen: 4, 7202 faultOnNilArg0: true, 7203 reg: regInfo{ 7204 inputs: []inputInfo{ 7205 {0, 128}, // DI 7206 {1, 2}, // CX 7207 {2, 1}, // AX 7208 }, 7209 clobbers: 130, // CX DI 7210 }, 7211 }, 7212 { 7213 name: "CALLstatic", 7214 auxType: auxSymOff, 7215 argLen: 1, 7216 clobberFlags: true, 7217 call: true, 7218 reg: regInfo{ 7219 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7220 }, 7221 }, 7222 { 7223 name: "CALLclosure", 7224 auxType: auxInt64, 7225 argLen: 3, 7226 clobberFlags: true, 7227 call: true, 7228 reg: regInfo{ 7229 inputs: []inputInfo{ 7230 {1, 4}, // DX 7231 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7232 }, 7233 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7234 }, 7235 }, 7236 { 7237 name: "CALLdefer", 7238 auxType: auxInt64, 7239 argLen: 1, 7240 clobberFlags: true, 7241 call: true, 7242 reg: regInfo{ 7243 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7244 }, 7245 }, 7246 { 7247 name: "CALLgo", 7248 auxType: auxInt64, 7249 argLen: 1, 7250 clobberFlags: true, 7251 call: true, 7252 reg: regInfo{ 7253 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7254 }, 7255 }, 7256 { 7257 name: "CALLinter", 7258 auxType: auxInt64, 7259 argLen: 2, 7260 clobberFlags: true, 7261 call: true, 7262 reg: regInfo{ 7263 inputs: []inputInfo{ 7264 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7265 }, 7266 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7267 }, 7268 }, 7269 { 7270 name: "DUFFCOPY", 7271 auxType: auxInt64, 7272 argLen: 3, 7273 clobberFlags: true, 7274 faultOnNilArg0: true, 7275 faultOnNilArg1: true, 7276 reg: regInfo{ 7277 inputs: []inputInfo{ 7278 {0, 128}, // DI 7279 {1, 64}, // SI 7280 }, 7281 clobbers: 65728, // SI DI X0 7282 }, 7283 }, 7284 { 7285 name: "REPMOVSQ", 7286 argLen: 4, 7287 faultOnNilArg0: true, 7288 faultOnNilArg1: true, 7289 reg: regInfo{ 7290 inputs: []inputInfo{ 7291 {0, 128}, // DI 7292 {1, 64}, // SI 7293 {2, 2}, // CX 7294 }, 7295 clobbers: 194, // CX SI DI 7296 }, 7297 }, 7298 { 7299 name: "InvertFlags", 7300 argLen: 1, 7301 reg: regInfo{}, 7302 }, 7303 { 7304 name: "LoweredGetG", 7305 argLen: 1, 7306 reg: regInfo{ 7307 outputs: []outputInfo{ 7308 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7309 }, 7310 }, 7311 }, 7312 { 7313 name: "LoweredGetClosurePtr", 7314 argLen: 0, 7315 reg: regInfo{ 7316 outputs: []outputInfo{ 7317 {0, 4}, // DX 7318 }, 7319 }, 7320 }, 7321 { 7322 name: "LoweredNilCheck", 7323 argLen: 2, 7324 clobberFlags: true, 7325 nilCheck: true, 7326 faultOnNilArg0: true, 7327 reg: regInfo{ 7328 inputs: []inputInfo{ 7329 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7330 }, 7331 }, 7332 }, 7333 { 7334 name: "MOVQconvert", 7335 argLen: 2, 7336 asm: x86.AMOVQ, 7337 reg: regInfo{ 7338 inputs: []inputInfo{ 7339 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7340 }, 7341 outputs: []outputInfo{ 7342 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7343 }, 7344 }, 7345 }, 7346 { 7347 name: "MOVLconvert", 7348 argLen: 2, 7349 asm: x86.AMOVL, 7350 reg: regInfo{ 7351 inputs: []inputInfo{ 7352 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7353 }, 7354 outputs: []outputInfo{ 7355 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7356 }, 7357 }, 7358 }, 7359 { 7360 name: "FlagEQ", 7361 argLen: 0, 7362 reg: regInfo{}, 7363 }, 7364 { 7365 name: "FlagLT_ULT", 7366 argLen: 0, 7367 reg: regInfo{}, 7368 }, 7369 { 7370 name: "FlagLT_UGT", 7371 argLen: 0, 7372 reg: regInfo{}, 7373 }, 7374 { 7375 name: "FlagGT_UGT", 7376 argLen: 0, 7377 reg: regInfo{}, 7378 }, 7379 { 7380 name: "FlagGT_ULT", 7381 argLen: 0, 7382 reg: regInfo{}, 7383 }, 7384 { 7385 name: "MOVLatomicload", 7386 auxType: auxSymOff, 7387 argLen: 2, 7388 faultOnNilArg0: true, 7389 asm: x86.AMOVL, 7390 reg: regInfo{ 7391 inputs: []inputInfo{ 7392 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7393 }, 7394 outputs: []outputInfo{ 7395 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7396 }, 7397 }, 7398 }, 7399 { 7400 name: "MOVQatomicload", 7401 auxType: auxSymOff, 7402 argLen: 2, 7403 faultOnNilArg0: true, 7404 asm: x86.AMOVQ, 7405 reg: regInfo{ 7406 inputs: []inputInfo{ 7407 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7408 }, 7409 outputs: []outputInfo{ 7410 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7411 }, 7412 }, 7413 }, 7414 { 7415 name: "XCHGL", 7416 auxType: auxSymOff, 7417 argLen: 3, 7418 resultInArg0: true, 7419 faultOnNilArg1: true, 7420 asm: x86.AXCHGL, 7421 reg: regInfo{ 7422 inputs: []inputInfo{ 7423 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7424 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7425 }, 7426 outputs: []outputInfo{ 7427 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7428 }, 7429 }, 7430 }, 7431 { 7432 name: "XCHGQ", 7433 auxType: auxSymOff, 7434 argLen: 3, 7435 resultInArg0: true, 7436 faultOnNilArg1: true, 7437 asm: x86.AXCHGQ, 7438 reg: regInfo{ 7439 inputs: []inputInfo{ 7440 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7441 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7442 }, 7443 outputs: []outputInfo{ 7444 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7445 }, 7446 }, 7447 }, 7448 { 7449 name: "XADDLlock", 7450 auxType: auxSymOff, 7451 argLen: 3, 7452 resultInArg0: true, 7453 clobberFlags: true, 7454 faultOnNilArg1: true, 7455 asm: x86.AXADDL, 7456 reg: regInfo{ 7457 inputs: []inputInfo{ 7458 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7459 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7460 }, 7461 outputs: []outputInfo{ 7462 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7463 }, 7464 }, 7465 }, 7466 { 7467 name: "XADDQlock", 7468 auxType: auxSymOff, 7469 argLen: 3, 7470 resultInArg0: true, 7471 clobberFlags: true, 7472 faultOnNilArg1: true, 7473 asm: x86.AXADDQ, 7474 reg: regInfo{ 7475 inputs: []inputInfo{ 7476 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7477 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7478 }, 7479 outputs: []outputInfo{ 7480 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7481 }, 7482 }, 7483 }, 7484 { 7485 name: "AddTupleFirst32", 7486 argLen: 2, 7487 reg: regInfo{}, 7488 }, 7489 { 7490 name: "AddTupleFirst64", 7491 argLen: 2, 7492 reg: regInfo{}, 7493 }, 7494 { 7495 name: "CMPXCHGLlock", 7496 auxType: auxSymOff, 7497 argLen: 4, 7498 clobberFlags: true, 7499 faultOnNilArg0: true, 7500 asm: x86.ACMPXCHGL, 7501 reg: regInfo{ 7502 inputs: []inputInfo{ 7503 {1, 1}, // AX 7504 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7505 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7506 }, 7507 clobbers: 1, // AX 7508 outputs: []outputInfo{ 7509 {1, 0}, 7510 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7511 }, 7512 }, 7513 }, 7514 { 7515 name: "CMPXCHGQlock", 7516 auxType: auxSymOff, 7517 argLen: 4, 7518 clobberFlags: true, 7519 faultOnNilArg0: true, 7520 asm: x86.ACMPXCHGQ, 7521 reg: regInfo{ 7522 inputs: []inputInfo{ 7523 {1, 1}, // AX 7524 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7525 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7526 }, 7527 clobbers: 1, // AX 7528 outputs: []outputInfo{ 7529 {1, 0}, 7530 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7531 }, 7532 }, 7533 }, 7534 { 7535 name: "ANDBlock", 7536 auxType: auxSymOff, 7537 argLen: 3, 7538 clobberFlags: true, 7539 faultOnNilArg0: true, 7540 asm: x86.AANDB, 7541 reg: regInfo{ 7542 inputs: []inputInfo{ 7543 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7544 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7545 }, 7546 }, 7547 }, 7548 { 7549 name: "ORBlock", 7550 auxType: auxSymOff, 7551 argLen: 3, 7552 clobberFlags: true, 7553 faultOnNilArg0: true, 7554 asm: x86.AORB, 7555 reg: regInfo{ 7556 inputs: []inputInfo{ 7557 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7558 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7559 }, 7560 }, 7561 }, 7562 7563 { 7564 name: "ADD", 7565 argLen: 2, 7566 commutative: true, 7567 asm: arm.AADD, 7568 reg: regInfo{ 7569 inputs: []inputInfo{ 7570 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7571 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7572 }, 7573 outputs: []outputInfo{ 7574 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7575 }, 7576 }, 7577 }, 7578 { 7579 name: "ADDconst", 7580 auxType: auxInt32, 7581 argLen: 1, 7582 asm: arm.AADD, 7583 reg: regInfo{ 7584 inputs: []inputInfo{ 7585 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 7586 }, 7587 outputs: []outputInfo{ 7588 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7589 }, 7590 }, 7591 }, 7592 { 7593 name: "SUB", 7594 argLen: 2, 7595 asm: arm.ASUB, 7596 reg: regInfo{ 7597 inputs: []inputInfo{ 7598 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7599 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7600 }, 7601 outputs: []outputInfo{ 7602 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7603 }, 7604 }, 7605 }, 7606 { 7607 name: "SUBconst", 7608 auxType: auxInt32, 7609 argLen: 1, 7610 asm: arm.ASUB, 7611 reg: regInfo{ 7612 inputs: []inputInfo{ 7613 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7614 }, 7615 outputs: []outputInfo{ 7616 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7617 }, 7618 }, 7619 }, 7620 { 7621 name: "RSB", 7622 argLen: 2, 7623 asm: arm.ARSB, 7624 reg: regInfo{ 7625 inputs: []inputInfo{ 7626 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7627 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7628 }, 7629 outputs: []outputInfo{ 7630 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7631 }, 7632 }, 7633 }, 7634 { 7635 name: "RSBconst", 7636 auxType: auxInt32, 7637 argLen: 1, 7638 asm: arm.ARSB, 7639 reg: regInfo{ 7640 inputs: []inputInfo{ 7641 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7642 }, 7643 outputs: []outputInfo{ 7644 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7645 }, 7646 }, 7647 }, 7648 { 7649 name: "MUL", 7650 argLen: 2, 7651 commutative: true, 7652 asm: arm.AMUL, 7653 reg: regInfo{ 7654 inputs: []inputInfo{ 7655 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7656 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7657 }, 7658 outputs: []outputInfo{ 7659 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7660 }, 7661 }, 7662 }, 7663 { 7664 name: "HMUL", 7665 argLen: 2, 7666 commutative: true, 7667 asm: arm.AMULL, 7668 reg: regInfo{ 7669 inputs: []inputInfo{ 7670 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7671 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7672 }, 7673 outputs: []outputInfo{ 7674 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7675 }, 7676 }, 7677 }, 7678 { 7679 name: "HMULU", 7680 argLen: 2, 7681 commutative: true, 7682 asm: arm.AMULLU, 7683 reg: regInfo{ 7684 inputs: []inputInfo{ 7685 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7686 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7687 }, 7688 outputs: []outputInfo{ 7689 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7690 }, 7691 }, 7692 }, 7693 { 7694 name: "UDIVrtcall", 7695 argLen: 2, 7696 clobberFlags: true, 7697 reg: regInfo{ 7698 inputs: []inputInfo{ 7699 {0, 2}, // R1 7700 {1, 1}, // R0 7701 }, 7702 clobbers: 16396, // R2 R3 R14 7703 outputs: []outputInfo{ 7704 {0, 1}, // R0 7705 {1, 2}, // R1 7706 }, 7707 }, 7708 }, 7709 { 7710 name: "ADDS", 7711 argLen: 2, 7712 commutative: true, 7713 asm: arm.AADD, 7714 reg: regInfo{ 7715 inputs: []inputInfo{ 7716 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7717 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7718 }, 7719 outputs: []outputInfo{ 7720 {1, 0}, 7721 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7722 }, 7723 }, 7724 }, 7725 { 7726 name: "ADDSconst", 7727 auxType: auxInt32, 7728 argLen: 1, 7729 asm: arm.AADD, 7730 reg: regInfo{ 7731 inputs: []inputInfo{ 7732 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7733 }, 7734 outputs: []outputInfo{ 7735 {1, 0}, 7736 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7737 }, 7738 }, 7739 }, 7740 { 7741 name: "ADC", 7742 argLen: 3, 7743 commutative: true, 7744 asm: arm.AADC, 7745 reg: regInfo{ 7746 inputs: []inputInfo{ 7747 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7748 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7749 }, 7750 outputs: []outputInfo{ 7751 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7752 }, 7753 }, 7754 }, 7755 { 7756 name: "ADCconst", 7757 auxType: auxInt32, 7758 argLen: 2, 7759 asm: arm.AADC, 7760 reg: regInfo{ 7761 inputs: []inputInfo{ 7762 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7763 }, 7764 outputs: []outputInfo{ 7765 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7766 }, 7767 }, 7768 }, 7769 { 7770 name: "SUBS", 7771 argLen: 2, 7772 asm: arm.ASUB, 7773 reg: regInfo{ 7774 inputs: []inputInfo{ 7775 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7776 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7777 }, 7778 outputs: []outputInfo{ 7779 {1, 0}, 7780 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7781 }, 7782 }, 7783 }, 7784 { 7785 name: "SUBSconst", 7786 auxType: auxInt32, 7787 argLen: 1, 7788 asm: arm.ASUB, 7789 reg: regInfo{ 7790 inputs: []inputInfo{ 7791 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7792 }, 7793 outputs: []outputInfo{ 7794 {1, 0}, 7795 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7796 }, 7797 }, 7798 }, 7799 { 7800 name: "RSBSconst", 7801 auxType: auxInt32, 7802 argLen: 1, 7803 asm: arm.ARSB, 7804 reg: regInfo{ 7805 inputs: []inputInfo{ 7806 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7807 }, 7808 outputs: []outputInfo{ 7809 {1, 0}, 7810 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7811 }, 7812 }, 7813 }, 7814 { 7815 name: "SBC", 7816 argLen: 3, 7817 asm: arm.ASBC, 7818 reg: regInfo{ 7819 inputs: []inputInfo{ 7820 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7821 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7822 }, 7823 outputs: []outputInfo{ 7824 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7825 }, 7826 }, 7827 }, 7828 { 7829 name: "SBCconst", 7830 auxType: auxInt32, 7831 argLen: 2, 7832 asm: arm.ASBC, 7833 reg: regInfo{ 7834 inputs: []inputInfo{ 7835 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7836 }, 7837 outputs: []outputInfo{ 7838 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7839 }, 7840 }, 7841 }, 7842 { 7843 name: "RSCconst", 7844 auxType: auxInt32, 7845 argLen: 2, 7846 asm: arm.ARSC, 7847 reg: regInfo{ 7848 inputs: []inputInfo{ 7849 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7850 }, 7851 outputs: []outputInfo{ 7852 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7853 }, 7854 }, 7855 }, 7856 { 7857 name: "MULLU", 7858 argLen: 2, 7859 commutative: true, 7860 asm: arm.AMULLU, 7861 reg: regInfo{ 7862 inputs: []inputInfo{ 7863 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7864 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7865 }, 7866 outputs: []outputInfo{ 7867 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7868 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7869 }, 7870 }, 7871 }, 7872 { 7873 name: "MULA", 7874 argLen: 3, 7875 asm: arm.AMULA, 7876 reg: regInfo{ 7877 inputs: []inputInfo{ 7878 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7879 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7880 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7881 }, 7882 outputs: []outputInfo{ 7883 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7884 }, 7885 }, 7886 }, 7887 { 7888 name: "ADDF", 7889 argLen: 2, 7890 commutative: true, 7891 asm: arm.AADDF, 7892 reg: regInfo{ 7893 inputs: []inputInfo{ 7894 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7895 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7896 }, 7897 outputs: []outputInfo{ 7898 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7899 }, 7900 }, 7901 }, 7902 { 7903 name: "ADDD", 7904 argLen: 2, 7905 commutative: true, 7906 asm: arm.AADDD, 7907 reg: regInfo{ 7908 inputs: []inputInfo{ 7909 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7910 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7911 }, 7912 outputs: []outputInfo{ 7913 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7914 }, 7915 }, 7916 }, 7917 { 7918 name: "SUBF", 7919 argLen: 2, 7920 asm: arm.ASUBF, 7921 reg: regInfo{ 7922 inputs: []inputInfo{ 7923 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7924 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7925 }, 7926 outputs: []outputInfo{ 7927 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7928 }, 7929 }, 7930 }, 7931 { 7932 name: "SUBD", 7933 argLen: 2, 7934 asm: arm.ASUBD, 7935 reg: regInfo{ 7936 inputs: []inputInfo{ 7937 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7938 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7939 }, 7940 outputs: []outputInfo{ 7941 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7942 }, 7943 }, 7944 }, 7945 { 7946 name: "MULF", 7947 argLen: 2, 7948 commutative: true, 7949 asm: arm.AMULF, 7950 reg: regInfo{ 7951 inputs: []inputInfo{ 7952 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7953 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7954 }, 7955 outputs: []outputInfo{ 7956 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7957 }, 7958 }, 7959 }, 7960 { 7961 name: "MULD", 7962 argLen: 2, 7963 commutative: true, 7964 asm: arm.AMULD, 7965 reg: regInfo{ 7966 inputs: []inputInfo{ 7967 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7968 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7969 }, 7970 outputs: []outputInfo{ 7971 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7972 }, 7973 }, 7974 }, 7975 { 7976 name: "DIVF", 7977 argLen: 2, 7978 asm: arm.ADIVF, 7979 reg: regInfo{ 7980 inputs: []inputInfo{ 7981 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7982 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7983 }, 7984 outputs: []outputInfo{ 7985 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7986 }, 7987 }, 7988 }, 7989 { 7990 name: "DIVD", 7991 argLen: 2, 7992 asm: arm.ADIVD, 7993 reg: regInfo{ 7994 inputs: []inputInfo{ 7995 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7996 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7997 }, 7998 outputs: []outputInfo{ 7999 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8000 }, 8001 }, 8002 }, 8003 { 8004 name: "AND", 8005 argLen: 2, 8006 commutative: true, 8007 asm: arm.AAND, 8008 reg: regInfo{ 8009 inputs: []inputInfo{ 8010 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8011 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8012 }, 8013 outputs: []outputInfo{ 8014 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8015 }, 8016 }, 8017 }, 8018 { 8019 name: "ANDconst", 8020 auxType: auxInt32, 8021 argLen: 1, 8022 asm: arm.AAND, 8023 reg: regInfo{ 8024 inputs: []inputInfo{ 8025 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8026 }, 8027 outputs: []outputInfo{ 8028 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8029 }, 8030 }, 8031 }, 8032 { 8033 name: "OR", 8034 argLen: 2, 8035 commutative: true, 8036 asm: arm.AORR, 8037 reg: regInfo{ 8038 inputs: []inputInfo{ 8039 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8040 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8041 }, 8042 outputs: []outputInfo{ 8043 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8044 }, 8045 }, 8046 }, 8047 { 8048 name: "ORconst", 8049 auxType: auxInt32, 8050 argLen: 1, 8051 asm: arm.AORR, 8052 reg: regInfo{ 8053 inputs: []inputInfo{ 8054 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8055 }, 8056 outputs: []outputInfo{ 8057 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8058 }, 8059 }, 8060 }, 8061 { 8062 name: "XOR", 8063 argLen: 2, 8064 commutative: true, 8065 asm: arm.AEOR, 8066 reg: regInfo{ 8067 inputs: []inputInfo{ 8068 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8069 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8070 }, 8071 outputs: []outputInfo{ 8072 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8073 }, 8074 }, 8075 }, 8076 { 8077 name: "XORconst", 8078 auxType: auxInt32, 8079 argLen: 1, 8080 asm: arm.AEOR, 8081 reg: regInfo{ 8082 inputs: []inputInfo{ 8083 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8084 }, 8085 outputs: []outputInfo{ 8086 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8087 }, 8088 }, 8089 }, 8090 { 8091 name: "BIC", 8092 argLen: 2, 8093 asm: arm.ABIC, 8094 reg: regInfo{ 8095 inputs: []inputInfo{ 8096 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8097 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8098 }, 8099 outputs: []outputInfo{ 8100 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8101 }, 8102 }, 8103 }, 8104 { 8105 name: "BICconst", 8106 auxType: auxInt32, 8107 argLen: 1, 8108 asm: arm.ABIC, 8109 reg: regInfo{ 8110 inputs: []inputInfo{ 8111 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8112 }, 8113 outputs: []outputInfo{ 8114 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8115 }, 8116 }, 8117 }, 8118 { 8119 name: "MVN", 8120 argLen: 1, 8121 asm: arm.AMVN, 8122 reg: regInfo{ 8123 inputs: []inputInfo{ 8124 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8125 }, 8126 outputs: []outputInfo{ 8127 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8128 }, 8129 }, 8130 }, 8131 { 8132 name: "NEGF", 8133 argLen: 1, 8134 asm: arm.ANEGF, 8135 reg: regInfo{ 8136 inputs: []inputInfo{ 8137 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8138 }, 8139 outputs: []outputInfo{ 8140 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8141 }, 8142 }, 8143 }, 8144 { 8145 name: "NEGD", 8146 argLen: 1, 8147 asm: arm.ANEGD, 8148 reg: regInfo{ 8149 inputs: []inputInfo{ 8150 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8151 }, 8152 outputs: []outputInfo{ 8153 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8154 }, 8155 }, 8156 }, 8157 { 8158 name: "SQRTD", 8159 argLen: 1, 8160 asm: arm.ASQRTD, 8161 reg: regInfo{ 8162 inputs: []inputInfo{ 8163 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8164 }, 8165 outputs: []outputInfo{ 8166 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8167 }, 8168 }, 8169 }, 8170 { 8171 name: "CLZ", 8172 argLen: 1, 8173 asm: arm.ACLZ, 8174 reg: regInfo{ 8175 inputs: []inputInfo{ 8176 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8177 }, 8178 outputs: []outputInfo{ 8179 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8180 }, 8181 }, 8182 }, 8183 { 8184 name: "SLL", 8185 argLen: 2, 8186 asm: arm.ASLL, 8187 reg: regInfo{ 8188 inputs: []inputInfo{ 8189 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8190 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8191 }, 8192 outputs: []outputInfo{ 8193 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8194 }, 8195 }, 8196 }, 8197 { 8198 name: "SLLconst", 8199 auxType: auxInt32, 8200 argLen: 1, 8201 asm: arm.ASLL, 8202 reg: regInfo{ 8203 inputs: []inputInfo{ 8204 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8205 }, 8206 outputs: []outputInfo{ 8207 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8208 }, 8209 }, 8210 }, 8211 { 8212 name: "SRL", 8213 argLen: 2, 8214 asm: arm.ASRL, 8215 reg: regInfo{ 8216 inputs: []inputInfo{ 8217 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8218 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8219 }, 8220 outputs: []outputInfo{ 8221 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8222 }, 8223 }, 8224 }, 8225 { 8226 name: "SRLconst", 8227 auxType: auxInt32, 8228 argLen: 1, 8229 asm: arm.ASRL, 8230 reg: regInfo{ 8231 inputs: []inputInfo{ 8232 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8233 }, 8234 outputs: []outputInfo{ 8235 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8236 }, 8237 }, 8238 }, 8239 { 8240 name: "SRA", 8241 argLen: 2, 8242 asm: arm.ASRA, 8243 reg: regInfo{ 8244 inputs: []inputInfo{ 8245 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8246 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8247 }, 8248 outputs: []outputInfo{ 8249 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8250 }, 8251 }, 8252 }, 8253 { 8254 name: "SRAconst", 8255 auxType: auxInt32, 8256 argLen: 1, 8257 asm: arm.ASRA, 8258 reg: regInfo{ 8259 inputs: []inputInfo{ 8260 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8261 }, 8262 outputs: []outputInfo{ 8263 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8264 }, 8265 }, 8266 }, 8267 { 8268 name: "SRRconst", 8269 auxType: auxInt32, 8270 argLen: 1, 8271 reg: regInfo{ 8272 inputs: []inputInfo{ 8273 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8274 }, 8275 outputs: []outputInfo{ 8276 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8277 }, 8278 }, 8279 }, 8280 { 8281 name: "ADDshiftLL", 8282 auxType: auxInt32, 8283 argLen: 2, 8284 asm: arm.AADD, 8285 reg: regInfo{ 8286 inputs: []inputInfo{ 8287 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8288 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8289 }, 8290 outputs: []outputInfo{ 8291 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8292 }, 8293 }, 8294 }, 8295 { 8296 name: "ADDshiftRL", 8297 auxType: auxInt32, 8298 argLen: 2, 8299 asm: arm.AADD, 8300 reg: regInfo{ 8301 inputs: []inputInfo{ 8302 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8303 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8304 }, 8305 outputs: []outputInfo{ 8306 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8307 }, 8308 }, 8309 }, 8310 { 8311 name: "ADDshiftRA", 8312 auxType: auxInt32, 8313 argLen: 2, 8314 asm: arm.AADD, 8315 reg: regInfo{ 8316 inputs: []inputInfo{ 8317 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8318 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8319 }, 8320 outputs: []outputInfo{ 8321 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8322 }, 8323 }, 8324 }, 8325 { 8326 name: "SUBshiftLL", 8327 auxType: auxInt32, 8328 argLen: 2, 8329 asm: arm.ASUB, 8330 reg: regInfo{ 8331 inputs: []inputInfo{ 8332 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8333 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8334 }, 8335 outputs: []outputInfo{ 8336 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8337 }, 8338 }, 8339 }, 8340 { 8341 name: "SUBshiftRL", 8342 auxType: auxInt32, 8343 argLen: 2, 8344 asm: arm.ASUB, 8345 reg: regInfo{ 8346 inputs: []inputInfo{ 8347 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8348 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8349 }, 8350 outputs: []outputInfo{ 8351 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8352 }, 8353 }, 8354 }, 8355 { 8356 name: "SUBshiftRA", 8357 auxType: auxInt32, 8358 argLen: 2, 8359 asm: arm.ASUB, 8360 reg: regInfo{ 8361 inputs: []inputInfo{ 8362 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8363 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8364 }, 8365 outputs: []outputInfo{ 8366 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8367 }, 8368 }, 8369 }, 8370 { 8371 name: "RSBshiftLL", 8372 auxType: auxInt32, 8373 argLen: 2, 8374 asm: arm.ARSB, 8375 reg: regInfo{ 8376 inputs: []inputInfo{ 8377 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8378 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8379 }, 8380 outputs: []outputInfo{ 8381 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8382 }, 8383 }, 8384 }, 8385 { 8386 name: "RSBshiftRL", 8387 auxType: auxInt32, 8388 argLen: 2, 8389 asm: arm.ARSB, 8390 reg: regInfo{ 8391 inputs: []inputInfo{ 8392 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8393 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8394 }, 8395 outputs: []outputInfo{ 8396 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8397 }, 8398 }, 8399 }, 8400 { 8401 name: "RSBshiftRA", 8402 auxType: auxInt32, 8403 argLen: 2, 8404 asm: arm.ARSB, 8405 reg: regInfo{ 8406 inputs: []inputInfo{ 8407 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8408 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8409 }, 8410 outputs: []outputInfo{ 8411 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8412 }, 8413 }, 8414 }, 8415 { 8416 name: "ANDshiftLL", 8417 auxType: auxInt32, 8418 argLen: 2, 8419 asm: arm.AAND, 8420 reg: regInfo{ 8421 inputs: []inputInfo{ 8422 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8423 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8424 }, 8425 outputs: []outputInfo{ 8426 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8427 }, 8428 }, 8429 }, 8430 { 8431 name: "ANDshiftRL", 8432 auxType: auxInt32, 8433 argLen: 2, 8434 asm: arm.AAND, 8435 reg: regInfo{ 8436 inputs: []inputInfo{ 8437 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8438 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8439 }, 8440 outputs: []outputInfo{ 8441 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8442 }, 8443 }, 8444 }, 8445 { 8446 name: "ANDshiftRA", 8447 auxType: auxInt32, 8448 argLen: 2, 8449 asm: arm.AAND, 8450 reg: regInfo{ 8451 inputs: []inputInfo{ 8452 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8453 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8454 }, 8455 outputs: []outputInfo{ 8456 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8457 }, 8458 }, 8459 }, 8460 { 8461 name: "ORshiftLL", 8462 auxType: auxInt32, 8463 argLen: 2, 8464 asm: arm.AORR, 8465 reg: regInfo{ 8466 inputs: []inputInfo{ 8467 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8468 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8469 }, 8470 outputs: []outputInfo{ 8471 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8472 }, 8473 }, 8474 }, 8475 { 8476 name: "ORshiftRL", 8477 auxType: auxInt32, 8478 argLen: 2, 8479 asm: arm.AORR, 8480 reg: regInfo{ 8481 inputs: []inputInfo{ 8482 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8483 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8484 }, 8485 outputs: []outputInfo{ 8486 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8487 }, 8488 }, 8489 }, 8490 { 8491 name: "ORshiftRA", 8492 auxType: auxInt32, 8493 argLen: 2, 8494 asm: arm.AORR, 8495 reg: regInfo{ 8496 inputs: []inputInfo{ 8497 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8498 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8499 }, 8500 outputs: []outputInfo{ 8501 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8502 }, 8503 }, 8504 }, 8505 { 8506 name: "XORshiftLL", 8507 auxType: auxInt32, 8508 argLen: 2, 8509 asm: arm.AEOR, 8510 reg: regInfo{ 8511 inputs: []inputInfo{ 8512 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8513 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8514 }, 8515 outputs: []outputInfo{ 8516 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8517 }, 8518 }, 8519 }, 8520 { 8521 name: "XORshiftRL", 8522 auxType: auxInt32, 8523 argLen: 2, 8524 asm: arm.AEOR, 8525 reg: regInfo{ 8526 inputs: []inputInfo{ 8527 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8528 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8529 }, 8530 outputs: []outputInfo{ 8531 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8532 }, 8533 }, 8534 }, 8535 { 8536 name: "XORshiftRA", 8537 auxType: auxInt32, 8538 argLen: 2, 8539 asm: arm.AEOR, 8540 reg: regInfo{ 8541 inputs: []inputInfo{ 8542 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8543 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8544 }, 8545 outputs: []outputInfo{ 8546 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8547 }, 8548 }, 8549 }, 8550 { 8551 name: "XORshiftRR", 8552 auxType: auxInt32, 8553 argLen: 2, 8554 asm: arm.AEOR, 8555 reg: regInfo{ 8556 inputs: []inputInfo{ 8557 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8558 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8559 }, 8560 outputs: []outputInfo{ 8561 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8562 }, 8563 }, 8564 }, 8565 { 8566 name: "BICshiftLL", 8567 auxType: auxInt32, 8568 argLen: 2, 8569 asm: arm.ABIC, 8570 reg: regInfo{ 8571 inputs: []inputInfo{ 8572 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8573 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8574 }, 8575 outputs: []outputInfo{ 8576 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8577 }, 8578 }, 8579 }, 8580 { 8581 name: "BICshiftRL", 8582 auxType: auxInt32, 8583 argLen: 2, 8584 asm: arm.ABIC, 8585 reg: regInfo{ 8586 inputs: []inputInfo{ 8587 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8588 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8589 }, 8590 outputs: []outputInfo{ 8591 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8592 }, 8593 }, 8594 }, 8595 { 8596 name: "BICshiftRA", 8597 auxType: auxInt32, 8598 argLen: 2, 8599 asm: arm.ABIC, 8600 reg: regInfo{ 8601 inputs: []inputInfo{ 8602 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8603 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8604 }, 8605 outputs: []outputInfo{ 8606 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8607 }, 8608 }, 8609 }, 8610 { 8611 name: "MVNshiftLL", 8612 auxType: auxInt32, 8613 argLen: 1, 8614 asm: arm.AMVN, 8615 reg: regInfo{ 8616 inputs: []inputInfo{ 8617 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8618 }, 8619 outputs: []outputInfo{ 8620 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8621 }, 8622 }, 8623 }, 8624 { 8625 name: "MVNshiftRL", 8626 auxType: auxInt32, 8627 argLen: 1, 8628 asm: arm.AMVN, 8629 reg: regInfo{ 8630 inputs: []inputInfo{ 8631 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8632 }, 8633 outputs: []outputInfo{ 8634 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8635 }, 8636 }, 8637 }, 8638 { 8639 name: "MVNshiftRA", 8640 auxType: auxInt32, 8641 argLen: 1, 8642 asm: arm.AMVN, 8643 reg: regInfo{ 8644 inputs: []inputInfo{ 8645 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8646 }, 8647 outputs: []outputInfo{ 8648 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8649 }, 8650 }, 8651 }, 8652 { 8653 name: "ADCshiftLL", 8654 auxType: auxInt32, 8655 argLen: 3, 8656 asm: arm.AADC, 8657 reg: regInfo{ 8658 inputs: []inputInfo{ 8659 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8660 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8661 }, 8662 outputs: []outputInfo{ 8663 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8664 }, 8665 }, 8666 }, 8667 { 8668 name: "ADCshiftRL", 8669 auxType: auxInt32, 8670 argLen: 3, 8671 asm: arm.AADC, 8672 reg: regInfo{ 8673 inputs: []inputInfo{ 8674 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8675 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8676 }, 8677 outputs: []outputInfo{ 8678 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8679 }, 8680 }, 8681 }, 8682 { 8683 name: "ADCshiftRA", 8684 auxType: auxInt32, 8685 argLen: 3, 8686 asm: arm.AADC, 8687 reg: regInfo{ 8688 inputs: []inputInfo{ 8689 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8690 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8691 }, 8692 outputs: []outputInfo{ 8693 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8694 }, 8695 }, 8696 }, 8697 { 8698 name: "SBCshiftLL", 8699 auxType: auxInt32, 8700 argLen: 3, 8701 asm: arm.ASBC, 8702 reg: regInfo{ 8703 inputs: []inputInfo{ 8704 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8705 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8706 }, 8707 outputs: []outputInfo{ 8708 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8709 }, 8710 }, 8711 }, 8712 { 8713 name: "SBCshiftRL", 8714 auxType: auxInt32, 8715 argLen: 3, 8716 asm: arm.ASBC, 8717 reg: regInfo{ 8718 inputs: []inputInfo{ 8719 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8720 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8721 }, 8722 outputs: []outputInfo{ 8723 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8724 }, 8725 }, 8726 }, 8727 { 8728 name: "SBCshiftRA", 8729 auxType: auxInt32, 8730 argLen: 3, 8731 asm: arm.ASBC, 8732 reg: regInfo{ 8733 inputs: []inputInfo{ 8734 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8735 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8736 }, 8737 outputs: []outputInfo{ 8738 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8739 }, 8740 }, 8741 }, 8742 { 8743 name: "RSCshiftLL", 8744 auxType: auxInt32, 8745 argLen: 3, 8746 asm: arm.ARSC, 8747 reg: regInfo{ 8748 inputs: []inputInfo{ 8749 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8750 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8751 }, 8752 outputs: []outputInfo{ 8753 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8754 }, 8755 }, 8756 }, 8757 { 8758 name: "RSCshiftRL", 8759 auxType: auxInt32, 8760 argLen: 3, 8761 asm: arm.ARSC, 8762 reg: regInfo{ 8763 inputs: []inputInfo{ 8764 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8765 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8766 }, 8767 outputs: []outputInfo{ 8768 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8769 }, 8770 }, 8771 }, 8772 { 8773 name: "RSCshiftRA", 8774 auxType: auxInt32, 8775 argLen: 3, 8776 asm: arm.ARSC, 8777 reg: regInfo{ 8778 inputs: []inputInfo{ 8779 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8780 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8781 }, 8782 outputs: []outputInfo{ 8783 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8784 }, 8785 }, 8786 }, 8787 { 8788 name: "ADDSshiftLL", 8789 auxType: auxInt32, 8790 argLen: 2, 8791 asm: arm.AADD, 8792 reg: regInfo{ 8793 inputs: []inputInfo{ 8794 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8795 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8796 }, 8797 outputs: []outputInfo{ 8798 {1, 0}, 8799 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8800 }, 8801 }, 8802 }, 8803 { 8804 name: "ADDSshiftRL", 8805 auxType: auxInt32, 8806 argLen: 2, 8807 asm: arm.AADD, 8808 reg: regInfo{ 8809 inputs: []inputInfo{ 8810 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8811 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8812 }, 8813 outputs: []outputInfo{ 8814 {1, 0}, 8815 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8816 }, 8817 }, 8818 }, 8819 { 8820 name: "ADDSshiftRA", 8821 auxType: auxInt32, 8822 argLen: 2, 8823 asm: arm.AADD, 8824 reg: regInfo{ 8825 inputs: []inputInfo{ 8826 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8827 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8828 }, 8829 outputs: []outputInfo{ 8830 {1, 0}, 8831 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8832 }, 8833 }, 8834 }, 8835 { 8836 name: "SUBSshiftLL", 8837 auxType: auxInt32, 8838 argLen: 2, 8839 asm: arm.ASUB, 8840 reg: regInfo{ 8841 inputs: []inputInfo{ 8842 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8843 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8844 }, 8845 outputs: []outputInfo{ 8846 {1, 0}, 8847 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8848 }, 8849 }, 8850 }, 8851 { 8852 name: "SUBSshiftRL", 8853 auxType: auxInt32, 8854 argLen: 2, 8855 asm: arm.ASUB, 8856 reg: regInfo{ 8857 inputs: []inputInfo{ 8858 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8859 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8860 }, 8861 outputs: []outputInfo{ 8862 {1, 0}, 8863 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8864 }, 8865 }, 8866 }, 8867 { 8868 name: "SUBSshiftRA", 8869 auxType: auxInt32, 8870 argLen: 2, 8871 asm: arm.ASUB, 8872 reg: regInfo{ 8873 inputs: []inputInfo{ 8874 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8875 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8876 }, 8877 outputs: []outputInfo{ 8878 {1, 0}, 8879 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8880 }, 8881 }, 8882 }, 8883 { 8884 name: "RSBSshiftLL", 8885 auxType: auxInt32, 8886 argLen: 2, 8887 asm: arm.ARSB, 8888 reg: regInfo{ 8889 inputs: []inputInfo{ 8890 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8891 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8892 }, 8893 outputs: []outputInfo{ 8894 {1, 0}, 8895 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8896 }, 8897 }, 8898 }, 8899 { 8900 name: "RSBSshiftRL", 8901 auxType: auxInt32, 8902 argLen: 2, 8903 asm: arm.ARSB, 8904 reg: regInfo{ 8905 inputs: []inputInfo{ 8906 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8907 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8908 }, 8909 outputs: []outputInfo{ 8910 {1, 0}, 8911 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8912 }, 8913 }, 8914 }, 8915 { 8916 name: "RSBSshiftRA", 8917 auxType: auxInt32, 8918 argLen: 2, 8919 asm: arm.ARSB, 8920 reg: regInfo{ 8921 inputs: []inputInfo{ 8922 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8923 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8924 }, 8925 outputs: []outputInfo{ 8926 {1, 0}, 8927 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8928 }, 8929 }, 8930 }, 8931 { 8932 name: "ADDshiftLLreg", 8933 argLen: 3, 8934 asm: arm.AADD, 8935 reg: regInfo{ 8936 inputs: []inputInfo{ 8937 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8938 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8939 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8940 }, 8941 outputs: []outputInfo{ 8942 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8943 }, 8944 }, 8945 }, 8946 { 8947 name: "ADDshiftRLreg", 8948 argLen: 3, 8949 asm: arm.AADD, 8950 reg: regInfo{ 8951 inputs: []inputInfo{ 8952 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8953 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8954 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8955 }, 8956 outputs: []outputInfo{ 8957 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8958 }, 8959 }, 8960 }, 8961 { 8962 name: "ADDshiftRAreg", 8963 argLen: 3, 8964 asm: arm.AADD, 8965 reg: regInfo{ 8966 inputs: []inputInfo{ 8967 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8968 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8969 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8970 }, 8971 outputs: []outputInfo{ 8972 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8973 }, 8974 }, 8975 }, 8976 { 8977 name: "SUBshiftLLreg", 8978 argLen: 3, 8979 asm: arm.ASUB, 8980 reg: regInfo{ 8981 inputs: []inputInfo{ 8982 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8983 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8984 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8985 }, 8986 outputs: []outputInfo{ 8987 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8988 }, 8989 }, 8990 }, 8991 { 8992 name: "SUBshiftRLreg", 8993 argLen: 3, 8994 asm: arm.ASUB, 8995 reg: regInfo{ 8996 inputs: []inputInfo{ 8997 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8998 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8999 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9000 }, 9001 outputs: []outputInfo{ 9002 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9003 }, 9004 }, 9005 }, 9006 { 9007 name: "SUBshiftRAreg", 9008 argLen: 3, 9009 asm: arm.ASUB, 9010 reg: regInfo{ 9011 inputs: []inputInfo{ 9012 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9013 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9014 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9015 }, 9016 outputs: []outputInfo{ 9017 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9018 }, 9019 }, 9020 }, 9021 { 9022 name: "RSBshiftLLreg", 9023 argLen: 3, 9024 asm: arm.ARSB, 9025 reg: regInfo{ 9026 inputs: []inputInfo{ 9027 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9028 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9029 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9030 }, 9031 outputs: []outputInfo{ 9032 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9033 }, 9034 }, 9035 }, 9036 { 9037 name: "RSBshiftRLreg", 9038 argLen: 3, 9039 asm: arm.ARSB, 9040 reg: regInfo{ 9041 inputs: []inputInfo{ 9042 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9043 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9044 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9045 }, 9046 outputs: []outputInfo{ 9047 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9048 }, 9049 }, 9050 }, 9051 { 9052 name: "RSBshiftRAreg", 9053 argLen: 3, 9054 asm: arm.ARSB, 9055 reg: regInfo{ 9056 inputs: []inputInfo{ 9057 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9058 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9059 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9060 }, 9061 outputs: []outputInfo{ 9062 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9063 }, 9064 }, 9065 }, 9066 { 9067 name: "ANDshiftLLreg", 9068 argLen: 3, 9069 asm: arm.AAND, 9070 reg: regInfo{ 9071 inputs: []inputInfo{ 9072 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9073 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9074 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9075 }, 9076 outputs: []outputInfo{ 9077 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9078 }, 9079 }, 9080 }, 9081 { 9082 name: "ANDshiftRLreg", 9083 argLen: 3, 9084 asm: arm.AAND, 9085 reg: regInfo{ 9086 inputs: []inputInfo{ 9087 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9088 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9089 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9090 }, 9091 outputs: []outputInfo{ 9092 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9093 }, 9094 }, 9095 }, 9096 { 9097 name: "ANDshiftRAreg", 9098 argLen: 3, 9099 asm: arm.AAND, 9100 reg: regInfo{ 9101 inputs: []inputInfo{ 9102 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9103 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9104 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9105 }, 9106 outputs: []outputInfo{ 9107 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9108 }, 9109 }, 9110 }, 9111 { 9112 name: "ORshiftLLreg", 9113 argLen: 3, 9114 asm: arm.AORR, 9115 reg: regInfo{ 9116 inputs: []inputInfo{ 9117 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9118 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9119 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9120 }, 9121 outputs: []outputInfo{ 9122 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9123 }, 9124 }, 9125 }, 9126 { 9127 name: "ORshiftRLreg", 9128 argLen: 3, 9129 asm: arm.AORR, 9130 reg: regInfo{ 9131 inputs: []inputInfo{ 9132 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9133 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9134 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9135 }, 9136 outputs: []outputInfo{ 9137 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9138 }, 9139 }, 9140 }, 9141 { 9142 name: "ORshiftRAreg", 9143 argLen: 3, 9144 asm: arm.AORR, 9145 reg: regInfo{ 9146 inputs: []inputInfo{ 9147 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9148 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9149 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9150 }, 9151 outputs: []outputInfo{ 9152 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9153 }, 9154 }, 9155 }, 9156 { 9157 name: "XORshiftLLreg", 9158 argLen: 3, 9159 asm: arm.AEOR, 9160 reg: regInfo{ 9161 inputs: []inputInfo{ 9162 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9163 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9164 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9165 }, 9166 outputs: []outputInfo{ 9167 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9168 }, 9169 }, 9170 }, 9171 { 9172 name: "XORshiftRLreg", 9173 argLen: 3, 9174 asm: arm.AEOR, 9175 reg: regInfo{ 9176 inputs: []inputInfo{ 9177 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9178 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9179 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9180 }, 9181 outputs: []outputInfo{ 9182 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9183 }, 9184 }, 9185 }, 9186 { 9187 name: "XORshiftRAreg", 9188 argLen: 3, 9189 asm: arm.AEOR, 9190 reg: regInfo{ 9191 inputs: []inputInfo{ 9192 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9193 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9194 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9195 }, 9196 outputs: []outputInfo{ 9197 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9198 }, 9199 }, 9200 }, 9201 { 9202 name: "BICshiftLLreg", 9203 argLen: 3, 9204 asm: arm.ABIC, 9205 reg: regInfo{ 9206 inputs: []inputInfo{ 9207 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9208 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9209 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9210 }, 9211 outputs: []outputInfo{ 9212 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9213 }, 9214 }, 9215 }, 9216 { 9217 name: "BICshiftRLreg", 9218 argLen: 3, 9219 asm: arm.ABIC, 9220 reg: regInfo{ 9221 inputs: []inputInfo{ 9222 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9223 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9224 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9225 }, 9226 outputs: []outputInfo{ 9227 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9228 }, 9229 }, 9230 }, 9231 { 9232 name: "BICshiftRAreg", 9233 argLen: 3, 9234 asm: arm.ABIC, 9235 reg: regInfo{ 9236 inputs: []inputInfo{ 9237 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9238 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9239 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9240 }, 9241 outputs: []outputInfo{ 9242 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9243 }, 9244 }, 9245 }, 9246 { 9247 name: "MVNshiftLLreg", 9248 argLen: 2, 9249 asm: arm.AMVN, 9250 reg: regInfo{ 9251 inputs: []inputInfo{ 9252 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9253 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9254 }, 9255 outputs: []outputInfo{ 9256 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9257 }, 9258 }, 9259 }, 9260 { 9261 name: "MVNshiftRLreg", 9262 argLen: 2, 9263 asm: arm.AMVN, 9264 reg: regInfo{ 9265 inputs: []inputInfo{ 9266 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9267 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9268 }, 9269 outputs: []outputInfo{ 9270 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9271 }, 9272 }, 9273 }, 9274 { 9275 name: "MVNshiftRAreg", 9276 argLen: 2, 9277 asm: arm.AMVN, 9278 reg: regInfo{ 9279 inputs: []inputInfo{ 9280 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9281 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9282 }, 9283 outputs: []outputInfo{ 9284 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9285 }, 9286 }, 9287 }, 9288 { 9289 name: "ADCshiftLLreg", 9290 argLen: 4, 9291 asm: arm.AADC, 9292 reg: regInfo{ 9293 inputs: []inputInfo{ 9294 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9295 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9296 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9297 }, 9298 outputs: []outputInfo{ 9299 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9300 }, 9301 }, 9302 }, 9303 { 9304 name: "ADCshiftRLreg", 9305 argLen: 4, 9306 asm: arm.AADC, 9307 reg: regInfo{ 9308 inputs: []inputInfo{ 9309 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9310 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9311 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9312 }, 9313 outputs: []outputInfo{ 9314 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9315 }, 9316 }, 9317 }, 9318 { 9319 name: "ADCshiftRAreg", 9320 argLen: 4, 9321 asm: arm.AADC, 9322 reg: regInfo{ 9323 inputs: []inputInfo{ 9324 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9325 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9326 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9327 }, 9328 outputs: []outputInfo{ 9329 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9330 }, 9331 }, 9332 }, 9333 { 9334 name: "SBCshiftLLreg", 9335 argLen: 4, 9336 asm: arm.ASBC, 9337 reg: regInfo{ 9338 inputs: []inputInfo{ 9339 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9340 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9341 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9342 }, 9343 outputs: []outputInfo{ 9344 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9345 }, 9346 }, 9347 }, 9348 { 9349 name: "SBCshiftRLreg", 9350 argLen: 4, 9351 asm: arm.ASBC, 9352 reg: regInfo{ 9353 inputs: []inputInfo{ 9354 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9355 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9356 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9357 }, 9358 outputs: []outputInfo{ 9359 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9360 }, 9361 }, 9362 }, 9363 { 9364 name: "SBCshiftRAreg", 9365 argLen: 4, 9366 asm: arm.ASBC, 9367 reg: regInfo{ 9368 inputs: []inputInfo{ 9369 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9370 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9371 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9372 }, 9373 outputs: []outputInfo{ 9374 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9375 }, 9376 }, 9377 }, 9378 { 9379 name: "RSCshiftLLreg", 9380 argLen: 4, 9381 asm: arm.ARSC, 9382 reg: regInfo{ 9383 inputs: []inputInfo{ 9384 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9385 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9386 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9387 }, 9388 outputs: []outputInfo{ 9389 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9390 }, 9391 }, 9392 }, 9393 { 9394 name: "RSCshiftRLreg", 9395 argLen: 4, 9396 asm: arm.ARSC, 9397 reg: regInfo{ 9398 inputs: []inputInfo{ 9399 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9400 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9401 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9402 }, 9403 outputs: []outputInfo{ 9404 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9405 }, 9406 }, 9407 }, 9408 { 9409 name: "RSCshiftRAreg", 9410 argLen: 4, 9411 asm: arm.ARSC, 9412 reg: regInfo{ 9413 inputs: []inputInfo{ 9414 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9415 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9416 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9417 }, 9418 outputs: []outputInfo{ 9419 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9420 }, 9421 }, 9422 }, 9423 { 9424 name: "ADDSshiftLLreg", 9425 argLen: 3, 9426 asm: arm.AADD, 9427 reg: regInfo{ 9428 inputs: []inputInfo{ 9429 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9430 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9431 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9432 }, 9433 outputs: []outputInfo{ 9434 {1, 0}, 9435 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9436 }, 9437 }, 9438 }, 9439 { 9440 name: "ADDSshiftRLreg", 9441 argLen: 3, 9442 asm: arm.AADD, 9443 reg: regInfo{ 9444 inputs: []inputInfo{ 9445 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9446 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9447 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9448 }, 9449 outputs: []outputInfo{ 9450 {1, 0}, 9451 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9452 }, 9453 }, 9454 }, 9455 { 9456 name: "ADDSshiftRAreg", 9457 argLen: 3, 9458 asm: arm.AADD, 9459 reg: regInfo{ 9460 inputs: []inputInfo{ 9461 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9462 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9463 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9464 }, 9465 outputs: []outputInfo{ 9466 {1, 0}, 9467 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9468 }, 9469 }, 9470 }, 9471 { 9472 name: "SUBSshiftLLreg", 9473 argLen: 3, 9474 asm: arm.ASUB, 9475 reg: regInfo{ 9476 inputs: []inputInfo{ 9477 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9478 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9479 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9480 }, 9481 outputs: []outputInfo{ 9482 {1, 0}, 9483 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9484 }, 9485 }, 9486 }, 9487 { 9488 name: "SUBSshiftRLreg", 9489 argLen: 3, 9490 asm: arm.ASUB, 9491 reg: regInfo{ 9492 inputs: []inputInfo{ 9493 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9494 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9495 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9496 }, 9497 outputs: []outputInfo{ 9498 {1, 0}, 9499 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9500 }, 9501 }, 9502 }, 9503 { 9504 name: "SUBSshiftRAreg", 9505 argLen: 3, 9506 asm: arm.ASUB, 9507 reg: regInfo{ 9508 inputs: []inputInfo{ 9509 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9510 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9511 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9512 }, 9513 outputs: []outputInfo{ 9514 {1, 0}, 9515 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9516 }, 9517 }, 9518 }, 9519 { 9520 name: "RSBSshiftLLreg", 9521 argLen: 3, 9522 asm: arm.ARSB, 9523 reg: regInfo{ 9524 inputs: []inputInfo{ 9525 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9526 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9527 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9528 }, 9529 outputs: []outputInfo{ 9530 {1, 0}, 9531 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9532 }, 9533 }, 9534 }, 9535 { 9536 name: "RSBSshiftRLreg", 9537 argLen: 3, 9538 asm: arm.ARSB, 9539 reg: regInfo{ 9540 inputs: []inputInfo{ 9541 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9542 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9543 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9544 }, 9545 outputs: []outputInfo{ 9546 {1, 0}, 9547 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9548 }, 9549 }, 9550 }, 9551 { 9552 name: "RSBSshiftRAreg", 9553 argLen: 3, 9554 asm: arm.ARSB, 9555 reg: regInfo{ 9556 inputs: []inputInfo{ 9557 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9558 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9559 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9560 }, 9561 outputs: []outputInfo{ 9562 {1, 0}, 9563 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9564 }, 9565 }, 9566 }, 9567 { 9568 name: "CMP", 9569 argLen: 2, 9570 asm: arm.ACMP, 9571 reg: regInfo{ 9572 inputs: []inputInfo{ 9573 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9574 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9575 }, 9576 }, 9577 }, 9578 { 9579 name: "CMPconst", 9580 auxType: auxInt32, 9581 argLen: 1, 9582 asm: arm.ACMP, 9583 reg: regInfo{ 9584 inputs: []inputInfo{ 9585 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9586 }, 9587 }, 9588 }, 9589 { 9590 name: "CMN", 9591 argLen: 2, 9592 asm: arm.ACMN, 9593 reg: regInfo{ 9594 inputs: []inputInfo{ 9595 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9596 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9597 }, 9598 }, 9599 }, 9600 { 9601 name: "CMNconst", 9602 auxType: auxInt32, 9603 argLen: 1, 9604 asm: arm.ACMN, 9605 reg: regInfo{ 9606 inputs: []inputInfo{ 9607 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9608 }, 9609 }, 9610 }, 9611 { 9612 name: "TST", 9613 argLen: 2, 9614 commutative: true, 9615 asm: arm.ATST, 9616 reg: regInfo{ 9617 inputs: []inputInfo{ 9618 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9619 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9620 }, 9621 }, 9622 }, 9623 { 9624 name: "TSTconst", 9625 auxType: auxInt32, 9626 argLen: 1, 9627 asm: arm.ATST, 9628 reg: regInfo{ 9629 inputs: []inputInfo{ 9630 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9631 }, 9632 }, 9633 }, 9634 { 9635 name: "TEQ", 9636 argLen: 2, 9637 commutative: true, 9638 asm: arm.ATEQ, 9639 reg: regInfo{ 9640 inputs: []inputInfo{ 9641 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9642 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9643 }, 9644 }, 9645 }, 9646 { 9647 name: "TEQconst", 9648 auxType: auxInt32, 9649 argLen: 1, 9650 asm: arm.ATEQ, 9651 reg: regInfo{ 9652 inputs: []inputInfo{ 9653 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9654 }, 9655 }, 9656 }, 9657 { 9658 name: "CMPF", 9659 argLen: 2, 9660 asm: arm.ACMPF, 9661 reg: regInfo{ 9662 inputs: []inputInfo{ 9663 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9664 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9665 }, 9666 }, 9667 }, 9668 { 9669 name: "CMPD", 9670 argLen: 2, 9671 asm: arm.ACMPD, 9672 reg: regInfo{ 9673 inputs: []inputInfo{ 9674 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9675 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9676 }, 9677 }, 9678 }, 9679 { 9680 name: "CMPshiftLL", 9681 auxType: auxInt32, 9682 argLen: 2, 9683 asm: arm.ACMP, 9684 reg: regInfo{ 9685 inputs: []inputInfo{ 9686 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9687 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9688 }, 9689 }, 9690 }, 9691 { 9692 name: "CMPshiftRL", 9693 auxType: auxInt32, 9694 argLen: 2, 9695 asm: arm.ACMP, 9696 reg: regInfo{ 9697 inputs: []inputInfo{ 9698 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9699 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9700 }, 9701 }, 9702 }, 9703 { 9704 name: "CMPshiftRA", 9705 auxType: auxInt32, 9706 argLen: 2, 9707 asm: arm.ACMP, 9708 reg: regInfo{ 9709 inputs: []inputInfo{ 9710 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9711 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9712 }, 9713 }, 9714 }, 9715 { 9716 name: "CMPshiftLLreg", 9717 argLen: 3, 9718 asm: arm.ACMP, 9719 reg: regInfo{ 9720 inputs: []inputInfo{ 9721 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9722 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9723 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9724 }, 9725 }, 9726 }, 9727 { 9728 name: "CMPshiftRLreg", 9729 argLen: 3, 9730 asm: arm.ACMP, 9731 reg: regInfo{ 9732 inputs: []inputInfo{ 9733 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9734 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9735 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9736 }, 9737 }, 9738 }, 9739 { 9740 name: "CMPshiftRAreg", 9741 argLen: 3, 9742 asm: arm.ACMP, 9743 reg: regInfo{ 9744 inputs: []inputInfo{ 9745 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9746 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9747 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9748 }, 9749 }, 9750 }, 9751 { 9752 name: "CMPF0", 9753 argLen: 1, 9754 asm: arm.ACMPF, 9755 reg: regInfo{ 9756 inputs: []inputInfo{ 9757 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9758 }, 9759 }, 9760 }, 9761 { 9762 name: "CMPD0", 9763 argLen: 1, 9764 asm: arm.ACMPD, 9765 reg: regInfo{ 9766 inputs: []inputInfo{ 9767 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9768 }, 9769 }, 9770 }, 9771 { 9772 name: "MOVWconst", 9773 auxType: auxInt32, 9774 argLen: 0, 9775 rematerializeable: true, 9776 asm: arm.AMOVW, 9777 reg: regInfo{ 9778 outputs: []outputInfo{ 9779 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9780 }, 9781 }, 9782 }, 9783 { 9784 name: "MOVFconst", 9785 auxType: auxFloat64, 9786 argLen: 0, 9787 rematerializeable: true, 9788 asm: arm.AMOVF, 9789 reg: regInfo{ 9790 outputs: []outputInfo{ 9791 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9792 }, 9793 }, 9794 }, 9795 { 9796 name: "MOVDconst", 9797 auxType: auxFloat64, 9798 argLen: 0, 9799 rematerializeable: true, 9800 asm: arm.AMOVD, 9801 reg: regInfo{ 9802 outputs: []outputInfo{ 9803 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9804 }, 9805 }, 9806 }, 9807 { 9808 name: "MOVWaddr", 9809 auxType: auxSymOff, 9810 argLen: 1, 9811 rematerializeable: true, 9812 asm: arm.AMOVW, 9813 reg: regInfo{ 9814 inputs: []inputInfo{ 9815 {0, 4294975488}, // SP SB 9816 }, 9817 outputs: []outputInfo{ 9818 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9819 }, 9820 }, 9821 }, 9822 { 9823 name: "MOVBload", 9824 auxType: auxSymOff, 9825 argLen: 2, 9826 faultOnNilArg0: true, 9827 asm: arm.AMOVB, 9828 reg: regInfo{ 9829 inputs: []inputInfo{ 9830 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9831 }, 9832 outputs: []outputInfo{ 9833 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9834 }, 9835 }, 9836 }, 9837 { 9838 name: "MOVBUload", 9839 auxType: auxSymOff, 9840 argLen: 2, 9841 faultOnNilArg0: true, 9842 asm: arm.AMOVBU, 9843 reg: regInfo{ 9844 inputs: []inputInfo{ 9845 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9846 }, 9847 outputs: []outputInfo{ 9848 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9849 }, 9850 }, 9851 }, 9852 { 9853 name: "MOVHload", 9854 auxType: auxSymOff, 9855 argLen: 2, 9856 faultOnNilArg0: true, 9857 asm: arm.AMOVH, 9858 reg: regInfo{ 9859 inputs: []inputInfo{ 9860 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9861 }, 9862 outputs: []outputInfo{ 9863 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9864 }, 9865 }, 9866 }, 9867 { 9868 name: "MOVHUload", 9869 auxType: auxSymOff, 9870 argLen: 2, 9871 faultOnNilArg0: true, 9872 asm: arm.AMOVHU, 9873 reg: regInfo{ 9874 inputs: []inputInfo{ 9875 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9876 }, 9877 outputs: []outputInfo{ 9878 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9879 }, 9880 }, 9881 }, 9882 { 9883 name: "MOVWload", 9884 auxType: auxSymOff, 9885 argLen: 2, 9886 faultOnNilArg0: true, 9887 asm: arm.AMOVW, 9888 reg: regInfo{ 9889 inputs: []inputInfo{ 9890 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9891 }, 9892 outputs: []outputInfo{ 9893 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9894 }, 9895 }, 9896 }, 9897 { 9898 name: "MOVFload", 9899 auxType: auxSymOff, 9900 argLen: 2, 9901 faultOnNilArg0: true, 9902 asm: arm.AMOVF, 9903 reg: regInfo{ 9904 inputs: []inputInfo{ 9905 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9906 }, 9907 outputs: []outputInfo{ 9908 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9909 }, 9910 }, 9911 }, 9912 { 9913 name: "MOVDload", 9914 auxType: auxSymOff, 9915 argLen: 2, 9916 faultOnNilArg0: true, 9917 asm: arm.AMOVD, 9918 reg: regInfo{ 9919 inputs: []inputInfo{ 9920 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9921 }, 9922 outputs: []outputInfo{ 9923 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9924 }, 9925 }, 9926 }, 9927 { 9928 name: "MOVBstore", 9929 auxType: auxSymOff, 9930 argLen: 3, 9931 faultOnNilArg0: true, 9932 asm: arm.AMOVB, 9933 reg: regInfo{ 9934 inputs: []inputInfo{ 9935 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9936 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9937 }, 9938 }, 9939 }, 9940 { 9941 name: "MOVHstore", 9942 auxType: auxSymOff, 9943 argLen: 3, 9944 faultOnNilArg0: true, 9945 asm: arm.AMOVH, 9946 reg: regInfo{ 9947 inputs: []inputInfo{ 9948 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9949 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9950 }, 9951 }, 9952 }, 9953 { 9954 name: "MOVWstore", 9955 auxType: auxSymOff, 9956 argLen: 3, 9957 faultOnNilArg0: true, 9958 asm: arm.AMOVW, 9959 reg: regInfo{ 9960 inputs: []inputInfo{ 9961 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9962 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9963 }, 9964 }, 9965 }, 9966 { 9967 name: "MOVFstore", 9968 auxType: auxSymOff, 9969 argLen: 3, 9970 faultOnNilArg0: true, 9971 asm: arm.AMOVF, 9972 reg: regInfo{ 9973 inputs: []inputInfo{ 9974 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9975 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9976 }, 9977 }, 9978 }, 9979 { 9980 name: "MOVDstore", 9981 auxType: auxSymOff, 9982 argLen: 3, 9983 faultOnNilArg0: true, 9984 asm: arm.AMOVD, 9985 reg: regInfo{ 9986 inputs: []inputInfo{ 9987 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9988 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9989 }, 9990 }, 9991 }, 9992 { 9993 name: "MOVWloadidx", 9994 argLen: 3, 9995 asm: arm.AMOVW, 9996 reg: regInfo{ 9997 inputs: []inputInfo{ 9998 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9999 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10000 }, 10001 outputs: []outputInfo{ 10002 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10003 }, 10004 }, 10005 }, 10006 { 10007 name: "MOVWloadshiftLL", 10008 auxType: auxInt32, 10009 argLen: 3, 10010 asm: arm.AMOVW, 10011 reg: regInfo{ 10012 inputs: []inputInfo{ 10013 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10014 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10015 }, 10016 outputs: []outputInfo{ 10017 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10018 }, 10019 }, 10020 }, 10021 { 10022 name: "MOVWloadshiftRL", 10023 auxType: auxInt32, 10024 argLen: 3, 10025 asm: arm.AMOVW, 10026 reg: regInfo{ 10027 inputs: []inputInfo{ 10028 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10029 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10030 }, 10031 outputs: []outputInfo{ 10032 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10033 }, 10034 }, 10035 }, 10036 { 10037 name: "MOVWloadshiftRA", 10038 auxType: auxInt32, 10039 argLen: 3, 10040 asm: arm.AMOVW, 10041 reg: regInfo{ 10042 inputs: []inputInfo{ 10043 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10044 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10045 }, 10046 outputs: []outputInfo{ 10047 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10048 }, 10049 }, 10050 }, 10051 { 10052 name: "MOVWstoreidx", 10053 argLen: 4, 10054 asm: arm.AMOVW, 10055 reg: regInfo{ 10056 inputs: []inputInfo{ 10057 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10058 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10059 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10060 }, 10061 }, 10062 }, 10063 { 10064 name: "MOVWstoreshiftLL", 10065 auxType: auxInt32, 10066 argLen: 4, 10067 asm: arm.AMOVW, 10068 reg: regInfo{ 10069 inputs: []inputInfo{ 10070 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10071 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10072 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10073 }, 10074 }, 10075 }, 10076 { 10077 name: "MOVWstoreshiftRL", 10078 auxType: auxInt32, 10079 argLen: 4, 10080 asm: arm.AMOVW, 10081 reg: regInfo{ 10082 inputs: []inputInfo{ 10083 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10084 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10085 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10086 }, 10087 }, 10088 }, 10089 { 10090 name: "MOVWstoreshiftRA", 10091 auxType: auxInt32, 10092 argLen: 4, 10093 asm: arm.AMOVW, 10094 reg: regInfo{ 10095 inputs: []inputInfo{ 10096 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10097 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10098 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10099 }, 10100 }, 10101 }, 10102 { 10103 name: "MOVBreg", 10104 argLen: 1, 10105 asm: arm.AMOVBS, 10106 reg: regInfo{ 10107 inputs: []inputInfo{ 10108 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10109 }, 10110 outputs: []outputInfo{ 10111 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10112 }, 10113 }, 10114 }, 10115 { 10116 name: "MOVBUreg", 10117 argLen: 1, 10118 asm: arm.AMOVBU, 10119 reg: regInfo{ 10120 inputs: []inputInfo{ 10121 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10122 }, 10123 outputs: []outputInfo{ 10124 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10125 }, 10126 }, 10127 }, 10128 { 10129 name: "MOVHreg", 10130 argLen: 1, 10131 asm: arm.AMOVHS, 10132 reg: regInfo{ 10133 inputs: []inputInfo{ 10134 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10135 }, 10136 outputs: []outputInfo{ 10137 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10138 }, 10139 }, 10140 }, 10141 { 10142 name: "MOVHUreg", 10143 argLen: 1, 10144 asm: arm.AMOVHU, 10145 reg: regInfo{ 10146 inputs: []inputInfo{ 10147 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10148 }, 10149 outputs: []outputInfo{ 10150 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10151 }, 10152 }, 10153 }, 10154 { 10155 name: "MOVWreg", 10156 argLen: 1, 10157 asm: arm.AMOVW, 10158 reg: regInfo{ 10159 inputs: []inputInfo{ 10160 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10161 }, 10162 outputs: []outputInfo{ 10163 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10164 }, 10165 }, 10166 }, 10167 { 10168 name: "MOVWnop", 10169 argLen: 1, 10170 resultInArg0: true, 10171 reg: regInfo{ 10172 inputs: []inputInfo{ 10173 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10174 }, 10175 outputs: []outputInfo{ 10176 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10177 }, 10178 }, 10179 }, 10180 { 10181 name: "MOVWF", 10182 argLen: 1, 10183 asm: arm.AMOVWF, 10184 reg: regInfo{ 10185 inputs: []inputInfo{ 10186 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10187 }, 10188 outputs: []outputInfo{ 10189 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10190 }, 10191 }, 10192 }, 10193 { 10194 name: "MOVWD", 10195 argLen: 1, 10196 asm: arm.AMOVWD, 10197 reg: regInfo{ 10198 inputs: []inputInfo{ 10199 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10200 }, 10201 outputs: []outputInfo{ 10202 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10203 }, 10204 }, 10205 }, 10206 { 10207 name: "MOVWUF", 10208 argLen: 1, 10209 asm: arm.AMOVWF, 10210 reg: regInfo{ 10211 inputs: []inputInfo{ 10212 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10213 }, 10214 outputs: []outputInfo{ 10215 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10216 }, 10217 }, 10218 }, 10219 { 10220 name: "MOVWUD", 10221 argLen: 1, 10222 asm: arm.AMOVWD, 10223 reg: regInfo{ 10224 inputs: []inputInfo{ 10225 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10226 }, 10227 outputs: []outputInfo{ 10228 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10229 }, 10230 }, 10231 }, 10232 { 10233 name: "MOVFW", 10234 argLen: 1, 10235 asm: arm.AMOVFW, 10236 reg: regInfo{ 10237 inputs: []inputInfo{ 10238 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10239 }, 10240 outputs: []outputInfo{ 10241 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10242 }, 10243 }, 10244 }, 10245 { 10246 name: "MOVDW", 10247 argLen: 1, 10248 asm: arm.AMOVDW, 10249 reg: regInfo{ 10250 inputs: []inputInfo{ 10251 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10252 }, 10253 outputs: []outputInfo{ 10254 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10255 }, 10256 }, 10257 }, 10258 { 10259 name: "MOVFWU", 10260 argLen: 1, 10261 asm: arm.AMOVFW, 10262 reg: regInfo{ 10263 inputs: []inputInfo{ 10264 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10265 }, 10266 outputs: []outputInfo{ 10267 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10268 }, 10269 }, 10270 }, 10271 { 10272 name: "MOVDWU", 10273 argLen: 1, 10274 asm: arm.AMOVDW, 10275 reg: regInfo{ 10276 inputs: []inputInfo{ 10277 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10278 }, 10279 outputs: []outputInfo{ 10280 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10281 }, 10282 }, 10283 }, 10284 { 10285 name: "MOVFD", 10286 argLen: 1, 10287 asm: arm.AMOVFD, 10288 reg: regInfo{ 10289 inputs: []inputInfo{ 10290 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10291 }, 10292 outputs: []outputInfo{ 10293 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10294 }, 10295 }, 10296 }, 10297 { 10298 name: "MOVDF", 10299 argLen: 1, 10300 asm: arm.AMOVDF, 10301 reg: regInfo{ 10302 inputs: []inputInfo{ 10303 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10304 }, 10305 outputs: []outputInfo{ 10306 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10307 }, 10308 }, 10309 }, 10310 { 10311 name: "CMOVWHSconst", 10312 auxType: auxInt32, 10313 argLen: 2, 10314 resultInArg0: true, 10315 asm: arm.AMOVW, 10316 reg: regInfo{ 10317 inputs: []inputInfo{ 10318 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10319 }, 10320 outputs: []outputInfo{ 10321 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10322 }, 10323 }, 10324 }, 10325 { 10326 name: "CMOVWLSconst", 10327 auxType: auxInt32, 10328 argLen: 2, 10329 resultInArg0: true, 10330 asm: arm.AMOVW, 10331 reg: regInfo{ 10332 inputs: []inputInfo{ 10333 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10334 }, 10335 outputs: []outputInfo{ 10336 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10337 }, 10338 }, 10339 }, 10340 { 10341 name: "SRAcond", 10342 argLen: 3, 10343 asm: arm.ASRA, 10344 reg: regInfo{ 10345 inputs: []inputInfo{ 10346 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10347 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10348 }, 10349 outputs: []outputInfo{ 10350 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10351 }, 10352 }, 10353 }, 10354 { 10355 name: "CALLstatic", 10356 auxType: auxSymOff, 10357 argLen: 1, 10358 clobberFlags: true, 10359 call: true, 10360 reg: regInfo{ 10361 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10362 }, 10363 }, 10364 { 10365 name: "CALLclosure", 10366 auxType: auxInt64, 10367 argLen: 3, 10368 clobberFlags: true, 10369 call: true, 10370 reg: regInfo{ 10371 inputs: []inputInfo{ 10372 {1, 128}, // R7 10373 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 10374 }, 10375 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10376 }, 10377 }, 10378 { 10379 name: "CALLdefer", 10380 auxType: auxInt64, 10381 argLen: 1, 10382 clobberFlags: true, 10383 call: true, 10384 reg: regInfo{ 10385 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10386 }, 10387 }, 10388 { 10389 name: "CALLgo", 10390 auxType: auxInt64, 10391 argLen: 1, 10392 clobberFlags: true, 10393 call: true, 10394 reg: regInfo{ 10395 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10396 }, 10397 }, 10398 { 10399 name: "CALLinter", 10400 auxType: auxInt64, 10401 argLen: 2, 10402 clobberFlags: true, 10403 call: true, 10404 reg: regInfo{ 10405 inputs: []inputInfo{ 10406 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10407 }, 10408 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10409 }, 10410 }, 10411 { 10412 name: "LoweredNilCheck", 10413 argLen: 2, 10414 nilCheck: true, 10415 faultOnNilArg0: true, 10416 reg: regInfo{ 10417 inputs: []inputInfo{ 10418 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10419 }, 10420 }, 10421 }, 10422 { 10423 name: "Equal", 10424 argLen: 1, 10425 reg: regInfo{ 10426 outputs: []outputInfo{ 10427 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10428 }, 10429 }, 10430 }, 10431 { 10432 name: "NotEqual", 10433 argLen: 1, 10434 reg: regInfo{ 10435 outputs: []outputInfo{ 10436 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10437 }, 10438 }, 10439 }, 10440 { 10441 name: "LessThan", 10442 argLen: 1, 10443 reg: regInfo{ 10444 outputs: []outputInfo{ 10445 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10446 }, 10447 }, 10448 }, 10449 { 10450 name: "LessEqual", 10451 argLen: 1, 10452 reg: regInfo{ 10453 outputs: []outputInfo{ 10454 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10455 }, 10456 }, 10457 }, 10458 { 10459 name: "GreaterThan", 10460 argLen: 1, 10461 reg: regInfo{ 10462 outputs: []outputInfo{ 10463 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10464 }, 10465 }, 10466 }, 10467 { 10468 name: "GreaterEqual", 10469 argLen: 1, 10470 reg: regInfo{ 10471 outputs: []outputInfo{ 10472 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10473 }, 10474 }, 10475 }, 10476 { 10477 name: "LessThanU", 10478 argLen: 1, 10479 reg: regInfo{ 10480 outputs: []outputInfo{ 10481 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10482 }, 10483 }, 10484 }, 10485 { 10486 name: "LessEqualU", 10487 argLen: 1, 10488 reg: regInfo{ 10489 outputs: []outputInfo{ 10490 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10491 }, 10492 }, 10493 }, 10494 { 10495 name: "GreaterThanU", 10496 argLen: 1, 10497 reg: regInfo{ 10498 outputs: []outputInfo{ 10499 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10500 }, 10501 }, 10502 }, 10503 { 10504 name: "GreaterEqualU", 10505 argLen: 1, 10506 reg: regInfo{ 10507 outputs: []outputInfo{ 10508 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10509 }, 10510 }, 10511 }, 10512 { 10513 name: "DUFFZERO", 10514 auxType: auxInt64, 10515 argLen: 3, 10516 faultOnNilArg0: true, 10517 reg: regInfo{ 10518 inputs: []inputInfo{ 10519 {0, 2}, // R1 10520 {1, 1}, // R0 10521 }, 10522 clobbers: 16386, // R1 R14 10523 }, 10524 }, 10525 { 10526 name: "DUFFCOPY", 10527 auxType: auxInt64, 10528 argLen: 3, 10529 faultOnNilArg0: true, 10530 faultOnNilArg1: true, 10531 reg: regInfo{ 10532 inputs: []inputInfo{ 10533 {0, 4}, // R2 10534 {1, 2}, // R1 10535 }, 10536 clobbers: 16391, // R0 R1 R2 R14 10537 }, 10538 }, 10539 { 10540 name: "LoweredZero", 10541 auxType: auxInt64, 10542 argLen: 4, 10543 clobberFlags: true, 10544 faultOnNilArg0: true, 10545 reg: regInfo{ 10546 inputs: []inputInfo{ 10547 {0, 2}, // R1 10548 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10549 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10550 }, 10551 clobbers: 2, // R1 10552 }, 10553 }, 10554 { 10555 name: "LoweredMove", 10556 auxType: auxInt64, 10557 argLen: 4, 10558 clobberFlags: true, 10559 faultOnNilArg0: true, 10560 faultOnNilArg1: true, 10561 reg: regInfo{ 10562 inputs: []inputInfo{ 10563 {0, 4}, // R2 10564 {1, 2}, // R1 10565 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10566 }, 10567 clobbers: 6, // R1 R2 10568 }, 10569 }, 10570 { 10571 name: "LoweredGetClosurePtr", 10572 argLen: 0, 10573 reg: regInfo{ 10574 outputs: []outputInfo{ 10575 {0, 128}, // R7 10576 }, 10577 }, 10578 }, 10579 { 10580 name: "MOVWconvert", 10581 argLen: 2, 10582 asm: arm.AMOVW, 10583 reg: regInfo{ 10584 inputs: []inputInfo{ 10585 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10586 }, 10587 outputs: []outputInfo{ 10588 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10589 }, 10590 }, 10591 }, 10592 { 10593 name: "FlagEQ", 10594 argLen: 0, 10595 reg: regInfo{}, 10596 }, 10597 { 10598 name: "FlagLT_ULT", 10599 argLen: 0, 10600 reg: regInfo{}, 10601 }, 10602 { 10603 name: "FlagLT_UGT", 10604 argLen: 0, 10605 reg: regInfo{}, 10606 }, 10607 { 10608 name: "FlagGT_UGT", 10609 argLen: 0, 10610 reg: regInfo{}, 10611 }, 10612 { 10613 name: "FlagGT_ULT", 10614 argLen: 0, 10615 reg: regInfo{}, 10616 }, 10617 { 10618 name: "InvertFlags", 10619 argLen: 1, 10620 reg: regInfo{}, 10621 }, 10622 10623 { 10624 name: "ADD", 10625 argLen: 2, 10626 commutative: true, 10627 asm: arm64.AADD, 10628 reg: regInfo{ 10629 inputs: []inputInfo{ 10630 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10631 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10632 }, 10633 outputs: []outputInfo{ 10634 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10635 }, 10636 }, 10637 }, 10638 { 10639 name: "ADDconst", 10640 auxType: auxInt64, 10641 argLen: 1, 10642 asm: arm64.AADD, 10643 reg: regInfo{ 10644 inputs: []inputInfo{ 10645 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 10646 }, 10647 outputs: []outputInfo{ 10648 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10649 }, 10650 }, 10651 }, 10652 { 10653 name: "SUB", 10654 argLen: 2, 10655 asm: arm64.ASUB, 10656 reg: regInfo{ 10657 inputs: []inputInfo{ 10658 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10659 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10660 }, 10661 outputs: []outputInfo{ 10662 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10663 }, 10664 }, 10665 }, 10666 { 10667 name: "SUBconst", 10668 auxType: auxInt64, 10669 argLen: 1, 10670 asm: arm64.ASUB, 10671 reg: regInfo{ 10672 inputs: []inputInfo{ 10673 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10674 }, 10675 outputs: []outputInfo{ 10676 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10677 }, 10678 }, 10679 }, 10680 { 10681 name: "MUL", 10682 argLen: 2, 10683 commutative: true, 10684 asm: arm64.AMUL, 10685 reg: regInfo{ 10686 inputs: []inputInfo{ 10687 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10688 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10689 }, 10690 outputs: []outputInfo{ 10691 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10692 }, 10693 }, 10694 }, 10695 { 10696 name: "MULW", 10697 argLen: 2, 10698 commutative: true, 10699 asm: arm64.AMULW, 10700 reg: regInfo{ 10701 inputs: []inputInfo{ 10702 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10703 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10704 }, 10705 outputs: []outputInfo{ 10706 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10707 }, 10708 }, 10709 }, 10710 { 10711 name: "MULH", 10712 argLen: 2, 10713 commutative: true, 10714 asm: arm64.ASMULH, 10715 reg: regInfo{ 10716 inputs: []inputInfo{ 10717 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10718 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10719 }, 10720 outputs: []outputInfo{ 10721 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10722 }, 10723 }, 10724 }, 10725 { 10726 name: "UMULH", 10727 argLen: 2, 10728 commutative: true, 10729 asm: arm64.AUMULH, 10730 reg: regInfo{ 10731 inputs: []inputInfo{ 10732 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10733 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10734 }, 10735 outputs: []outputInfo{ 10736 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10737 }, 10738 }, 10739 }, 10740 { 10741 name: "MULL", 10742 argLen: 2, 10743 commutative: true, 10744 asm: arm64.ASMULL, 10745 reg: regInfo{ 10746 inputs: []inputInfo{ 10747 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10748 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10749 }, 10750 outputs: []outputInfo{ 10751 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10752 }, 10753 }, 10754 }, 10755 { 10756 name: "UMULL", 10757 argLen: 2, 10758 commutative: true, 10759 asm: arm64.AUMULL, 10760 reg: regInfo{ 10761 inputs: []inputInfo{ 10762 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10763 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10764 }, 10765 outputs: []outputInfo{ 10766 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10767 }, 10768 }, 10769 }, 10770 { 10771 name: "DIV", 10772 argLen: 2, 10773 asm: arm64.ASDIV, 10774 reg: regInfo{ 10775 inputs: []inputInfo{ 10776 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10777 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10778 }, 10779 outputs: []outputInfo{ 10780 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10781 }, 10782 }, 10783 }, 10784 { 10785 name: "UDIV", 10786 argLen: 2, 10787 asm: arm64.AUDIV, 10788 reg: regInfo{ 10789 inputs: []inputInfo{ 10790 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10791 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10792 }, 10793 outputs: []outputInfo{ 10794 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10795 }, 10796 }, 10797 }, 10798 { 10799 name: "DIVW", 10800 argLen: 2, 10801 asm: arm64.ASDIVW, 10802 reg: regInfo{ 10803 inputs: []inputInfo{ 10804 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10805 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10806 }, 10807 outputs: []outputInfo{ 10808 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10809 }, 10810 }, 10811 }, 10812 { 10813 name: "UDIVW", 10814 argLen: 2, 10815 asm: arm64.AUDIVW, 10816 reg: regInfo{ 10817 inputs: []inputInfo{ 10818 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10819 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10820 }, 10821 outputs: []outputInfo{ 10822 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10823 }, 10824 }, 10825 }, 10826 { 10827 name: "MOD", 10828 argLen: 2, 10829 asm: arm64.AREM, 10830 reg: regInfo{ 10831 inputs: []inputInfo{ 10832 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10833 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10834 }, 10835 outputs: []outputInfo{ 10836 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10837 }, 10838 }, 10839 }, 10840 { 10841 name: "UMOD", 10842 argLen: 2, 10843 asm: arm64.AUREM, 10844 reg: regInfo{ 10845 inputs: []inputInfo{ 10846 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10847 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10848 }, 10849 outputs: []outputInfo{ 10850 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10851 }, 10852 }, 10853 }, 10854 { 10855 name: "MODW", 10856 argLen: 2, 10857 asm: arm64.AREMW, 10858 reg: regInfo{ 10859 inputs: []inputInfo{ 10860 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10861 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10862 }, 10863 outputs: []outputInfo{ 10864 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10865 }, 10866 }, 10867 }, 10868 { 10869 name: "UMODW", 10870 argLen: 2, 10871 asm: arm64.AUREMW, 10872 reg: regInfo{ 10873 inputs: []inputInfo{ 10874 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10875 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10876 }, 10877 outputs: []outputInfo{ 10878 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10879 }, 10880 }, 10881 }, 10882 { 10883 name: "FADDS", 10884 argLen: 2, 10885 commutative: true, 10886 asm: arm64.AFADDS, 10887 reg: regInfo{ 10888 inputs: []inputInfo{ 10889 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10890 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10891 }, 10892 outputs: []outputInfo{ 10893 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10894 }, 10895 }, 10896 }, 10897 { 10898 name: "FADDD", 10899 argLen: 2, 10900 commutative: true, 10901 asm: arm64.AFADDD, 10902 reg: regInfo{ 10903 inputs: []inputInfo{ 10904 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10905 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10906 }, 10907 outputs: []outputInfo{ 10908 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10909 }, 10910 }, 10911 }, 10912 { 10913 name: "FSUBS", 10914 argLen: 2, 10915 asm: arm64.AFSUBS, 10916 reg: regInfo{ 10917 inputs: []inputInfo{ 10918 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10919 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10920 }, 10921 outputs: []outputInfo{ 10922 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10923 }, 10924 }, 10925 }, 10926 { 10927 name: "FSUBD", 10928 argLen: 2, 10929 asm: arm64.AFSUBD, 10930 reg: regInfo{ 10931 inputs: []inputInfo{ 10932 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10933 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10934 }, 10935 outputs: []outputInfo{ 10936 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10937 }, 10938 }, 10939 }, 10940 { 10941 name: "FMULS", 10942 argLen: 2, 10943 commutative: true, 10944 asm: arm64.AFMULS, 10945 reg: regInfo{ 10946 inputs: []inputInfo{ 10947 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10948 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10949 }, 10950 outputs: []outputInfo{ 10951 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10952 }, 10953 }, 10954 }, 10955 { 10956 name: "FMULD", 10957 argLen: 2, 10958 commutative: true, 10959 asm: arm64.AFMULD, 10960 reg: regInfo{ 10961 inputs: []inputInfo{ 10962 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10963 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10964 }, 10965 outputs: []outputInfo{ 10966 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10967 }, 10968 }, 10969 }, 10970 { 10971 name: "FDIVS", 10972 argLen: 2, 10973 asm: arm64.AFDIVS, 10974 reg: regInfo{ 10975 inputs: []inputInfo{ 10976 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10977 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10978 }, 10979 outputs: []outputInfo{ 10980 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10981 }, 10982 }, 10983 }, 10984 { 10985 name: "FDIVD", 10986 argLen: 2, 10987 asm: arm64.AFDIVD, 10988 reg: regInfo{ 10989 inputs: []inputInfo{ 10990 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10991 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10992 }, 10993 outputs: []outputInfo{ 10994 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10995 }, 10996 }, 10997 }, 10998 { 10999 name: "AND", 11000 argLen: 2, 11001 commutative: true, 11002 asm: arm64.AAND, 11003 reg: regInfo{ 11004 inputs: []inputInfo{ 11005 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11006 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11007 }, 11008 outputs: []outputInfo{ 11009 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11010 }, 11011 }, 11012 }, 11013 { 11014 name: "ANDconst", 11015 auxType: auxInt64, 11016 argLen: 1, 11017 asm: arm64.AAND, 11018 reg: regInfo{ 11019 inputs: []inputInfo{ 11020 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11021 }, 11022 outputs: []outputInfo{ 11023 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11024 }, 11025 }, 11026 }, 11027 { 11028 name: "OR", 11029 argLen: 2, 11030 commutative: true, 11031 asm: arm64.AORR, 11032 reg: regInfo{ 11033 inputs: []inputInfo{ 11034 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11035 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11036 }, 11037 outputs: []outputInfo{ 11038 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11039 }, 11040 }, 11041 }, 11042 { 11043 name: "ORconst", 11044 auxType: auxInt64, 11045 argLen: 1, 11046 asm: arm64.AORR, 11047 reg: regInfo{ 11048 inputs: []inputInfo{ 11049 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11050 }, 11051 outputs: []outputInfo{ 11052 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11053 }, 11054 }, 11055 }, 11056 { 11057 name: "XOR", 11058 argLen: 2, 11059 commutative: true, 11060 asm: arm64.AEOR, 11061 reg: regInfo{ 11062 inputs: []inputInfo{ 11063 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11064 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11065 }, 11066 outputs: []outputInfo{ 11067 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11068 }, 11069 }, 11070 }, 11071 { 11072 name: "XORconst", 11073 auxType: auxInt64, 11074 argLen: 1, 11075 asm: arm64.AEOR, 11076 reg: regInfo{ 11077 inputs: []inputInfo{ 11078 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11079 }, 11080 outputs: []outputInfo{ 11081 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11082 }, 11083 }, 11084 }, 11085 { 11086 name: "BIC", 11087 argLen: 2, 11088 asm: arm64.ABIC, 11089 reg: regInfo{ 11090 inputs: []inputInfo{ 11091 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11092 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11093 }, 11094 outputs: []outputInfo{ 11095 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11096 }, 11097 }, 11098 }, 11099 { 11100 name: "BICconst", 11101 auxType: auxInt64, 11102 argLen: 1, 11103 asm: arm64.ABIC, 11104 reg: regInfo{ 11105 inputs: []inputInfo{ 11106 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11107 }, 11108 outputs: []outputInfo{ 11109 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11110 }, 11111 }, 11112 }, 11113 { 11114 name: "MVN", 11115 argLen: 1, 11116 asm: arm64.AMVN, 11117 reg: regInfo{ 11118 inputs: []inputInfo{ 11119 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11120 }, 11121 outputs: []outputInfo{ 11122 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11123 }, 11124 }, 11125 }, 11126 { 11127 name: "NEG", 11128 argLen: 1, 11129 asm: arm64.ANEG, 11130 reg: regInfo{ 11131 inputs: []inputInfo{ 11132 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11133 }, 11134 outputs: []outputInfo{ 11135 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11136 }, 11137 }, 11138 }, 11139 { 11140 name: "FNEGS", 11141 argLen: 1, 11142 asm: arm64.AFNEGS, 11143 reg: regInfo{ 11144 inputs: []inputInfo{ 11145 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11146 }, 11147 outputs: []outputInfo{ 11148 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11149 }, 11150 }, 11151 }, 11152 { 11153 name: "FNEGD", 11154 argLen: 1, 11155 asm: arm64.AFNEGD, 11156 reg: regInfo{ 11157 inputs: []inputInfo{ 11158 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11159 }, 11160 outputs: []outputInfo{ 11161 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11162 }, 11163 }, 11164 }, 11165 { 11166 name: "FSQRTD", 11167 argLen: 1, 11168 asm: arm64.AFSQRTD, 11169 reg: regInfo{ 11170 inputs: []inputInfo{ 11171 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11172 }, 11173 outputs: []outputInfo{ 11174 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11175 }, 11176 }, 11177 }, 11178 { 11179 name: "REV", 11180 argLen: 1, 11181 asm: arm64.AREV, 11182 reg: regInfo{ 11183 inputs: []inputInfo{ 11184 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11185 }, 11186 outputs: []outputInfo{ 11187 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11188 }, 11189 }, 11190 }, 11191 { 11192 name: "REVW", 11193 argLen: 1, 11194 asm: arm64.AREVW, 11195 reg: regInfo{ 11196 inputs: []inputInfo{ 11197 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11198 }, 11199 outputs: []outputInfo{ 11200 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11201 }, 11202 }, 11203 }, 11204 { 11205 name: "REV16W", 11206 argLen: 1, 11207 asm: arm64.AREV16W, 11208 reg: regInfo{ 11209 inputs: []inputInfo{ 11210 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11211 }, 11212 outputs: []outputInfo{ 11213 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11214 }, 11215 }, 11216 }, 11217 { 11218 name: "RBIT", 11219 argLen: 1, 11220 asm: arm64.ARBIT, 11221 reg: regInfo{ 11222 inputs: []inputInfo{ 11223 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11224 }, 11225 outputs: []outputInfo{ 11226 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11227 }, 11228 }, 11229 }, 11230 { 11231 name: "RBITW", 11232 argLen: 1, 11233 asm: arm64.ARBITW, 11234 reg: regInfo{ 11235 inputs: []inputInfo{ 11236 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11237 }, 11238 outputs: []outputInfo{ 11239 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11240 }, 11241 }, 11242 }, 11243 { 11244 name: "CLZ", 11245 argLen: 1, 11246 asm: arm64.ACLZ, 11247 reg: regInfo{ 11248 inputs: []inputInfo{ 11249 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11250 }, 11251 outputs: []outputInfo{ 11252 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11253 }, 11254 }, 11255 }, 11256 { 11257 name: "CLZW", 11258 argLen: 1, 11259 asm: arm64.ACLZW, 11260 reg: regInfo{ 11261 inputs: []inputInfo{ 11262 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11263 }, 11264 outputs: []outputInfo{ 11265 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11266 }, 11267 }, 11268 }, 11269 { 11270 name: "SLL", 11271 argLen: 2, 11272 asm: arm64.ALSL, 11273 reg: regInfo{ 11274 inputs: []inputInfo{ 11275 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11276 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11277 }, 11278 outputs: []outputInfo{ 11279 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11280 }, 11281 }, 11282 }, 11283 { 11284 name: "SLLconst", 11285 auxType: auxInt64, 11286 argLen: 1, 11287 asm: arm64.ALSL, 11288 reg: regInfo{ 11289 inputs: []inputInfo{ 11290 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11291 }, 11292 outputs: []outputInfo{ 11293 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11294 }, 11295 }, 11296 }, 11297 { 11298 name: "SRL", 11299 argLen: 2, 11300 asm: arm64.ALSR, 11301 reg: regInfo{ 11302 inputs: []inputInfo{ 11303 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11304 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11305 }, 11306 outputs: []outputInfo{ 11307 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11308 }, 11309 }, 11310 }, 11311 { 11312 name: "SRLconst", 11313 auxType: auxInt64, 11314 argLen: 1, 11315 asm: arm64.ALSR, 11316 reg: regInfo{ 11317 inputs: []inputInfo{ 11318 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11319 }, 11320 outputs: []outputInfo{ 11321 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11322 }, 11323 }, 11324 }, 11325 { 11326 name: "SRA", 11327 argLen: 2, 11328 asm: arm64.AASR, 11329 reg: regInfo{ 11330 inputs: []inputInfo{ 11331 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11332 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11333 }, 11334 outputs: []outputInfo{ 11335 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11336 }, 11337 }, 11338 }, 11339 { 11340 name: "SRAconst", 11341 auxType: auxInt64, 11342 argLen: 1, 11343 asm: arm64.AASR, 11344 reg: regInfo{ 11345 inputs: []inputInfo{ 11346 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11347 }, 11348 outputs: []outputInfo{ 11349 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11350 }, 11351 }, 11352 }, 11353 { 11354 name: "RORconst", 11355 auxType: auxInt64, 11356 argLen: 1, 11357 asm: arm64.AROR, 11358 reg: regInfo{ 11359 inputs: []inputInfo{ 11360 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11361 }, 11362 outputs: []outputInfo{ 11363 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11364 }, 11365 }, 11366 }, 11367 { 11368 name: "RORWconst", 11369 auxType: auxInt64, 11370 argLen: 1, 11371 asm: arm64.ARORW, 11372 reg: regInfo{ 11373 inputs: []inputInfo{ 11374 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11375 }, 11376 outputs: []outputInfo{ 11377 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11378 }, 11379 }, 11380 }, 11381 { 11382 name: "CMP", 11383 argLen: 2, 11384 asm: arm64.ACMP, 11385 reg: regInfo{ 11386 inputs: []inputInfo{ 11387 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11388 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11389 }, 11390 }, 11391 }, 11392 { 11393 name: "CMPconst", 11394 auxType: auxInt64, 11395 argLen: 1, 11396 asm: arm64.ACMP, 11397 reg: regInfo{ 11398 inputs: []inputInfo{ 11399 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11400 }, 11401 }, 11402 }, 11403 { 11404 name: "CMPW", 11405 argLen: 2, 11406 asm: arm64.ACMPW, 11407 reg: regInfo{ 11408 inputs: []inputInfo{ 11409 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11410 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11411 }, 11412 }, 11413 }, 11414 { 11415 name: "CMPWconst", 11416 auxType: auxInt32, 11417 argLen: 1, 11418 asm: arm64.ACMPW, 11419 reg: regInfo{ 11420 inputs: []inputInfo{ 11421 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11422 }, 11423 }, 11424 }, 11425 { 11426 name: "CMN", 11427 argLen: 2, 11428 asm: arm64.ACMN, 11429 reg: regInfo{ 11430 inputs: []inputInfo{ 11431 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11432 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11433 }, 11434 }, 11435 }, 11436 { 11437 name: "CMNconst", 11438 auxType: auxInt64, 11439 argLen: 1, 11440 asm: arm64.ACMN, 11441 reg: regInfo{ 11442 inputs: []inputInfo{ 11443 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11444 }, 11445 }, 11446 }, 11447 { 11448 name: "CMNW", 11449 argLen: 2, 11450 asm: arm64.ACMNW, 11451 reg: regInfo{ 11452 inputs: []inputInfo{ 11453 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11454 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11455 }, 11456 }, 11457 }, 11458 { 11459 name: "CMNWconst", 11460 auxType: auxInt32, 11461 argLen: 1, 11462 asm: arm64.ACMNW, 11463 reg: regInfo{ 11464 inputs: []inputInfo{ 11465 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11466 }, 11467 }, 11468 }, 11469 { 11470 name: "FCMPS", 11471 argLen: 2, 11472 asm: arm64.AFCMPS, 11473 reg: regInfo{ 11474 inputs: []inputInfo{ 11475 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11476 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11477 }, 11478 }, 11479 }, 11480 { 11481 name: "FCMPD", 11482 argLen: 2, 11483 asm: arm64.AFCMPD, 11484 reg: regInfo{ 11485 inputs: []inputInfo{ 11486 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11487 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11488 }, 11489 }, 11490 }, 11491 { 11492 name: "ADDshiftLL", 11493 auxType: auxInt64, 11494 argLen: 2, 11495 asm: arm64.AADD, 11496 reg: regInfo{ 11497 inputs: []inputInfo{ 11498 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11499 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11500 }, 11501 outputs: []outputInfo{ 11502 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11503 }, 11504 }, 11505 }, 11506 { 11507 name: "ADDshiftRL", 11508 auxType: auxInt64, 11509 argLen: 2, 11510 asm: arm64.AADD, 11511 reg: regInfo{ 11512 inputs: []inputInfo{ 11513 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11514 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11515 }, 11516 outputs: []outputInfo{ 11517 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11518 }, 11519 }, 11520 }, 11521 { 11522 name: "ADDshiftRA", 11523 auxType: auxInt64, 11524 argLen: 2, 11525 asm: arm64.AADD, 11526 reg: regInfo{ 11527 inputs: []inputInfo{ 11528 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11529 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11530 }, 11531 outputs: []outputInfo{ 11532 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11533 }, 11534 }, 11535 }, 11536 { 11537 name: "SUBshiftLL", 11538 auxType: auxInt64, 11539 argLen: 2, 11540 asm: arm64.ASUB, 11541 reg: regInfo{ 11542 inputs: []inputInfo{ 11543 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11544 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11545 }, 11546 outputs: []outputInfo{ 11547 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11548 }, 11549 }, 11550 }, 11551 { 11552 name: "SUBshiftRL", 11553 auxType: auxInt64, 11554 argLen: 2, 11555 asm: arm64.ASUB, 11556 reg: regInfo{ 11557 inputs: []inputInfo{ 11558 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11559 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11560 }, 11561 outputs: []outputInfo{ 11562 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11563 }, 11564 }, 11565 }, 11566 { 11567 name: "SUBshiftRA", 11568 auxType: auxInt64, 11569 argLen: 2, 11570 asm: arm64.ASUB, 11571 reg: regInfo{ 11572 inputs: []inputInfo{ 11573 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11574 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11575 }, 11576 outputs: []outputInfo{ 11577 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11578 }, 11579 }, 11580 }, 11581 { 11582 name: "ANDshiftLL", 11583 auxType: auxInt64, 11584 argLen: 2, 11585 asm: arm64.AAND, 11586 reg: regInfo{ 11587 inputs: []inputInfo{ 11588 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11589 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11590 }, 11591 outputs: []outputInfo{ 11592 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11593 }, 11594 }, 11595 }, 11596 { 11597 name: "ANDshiftRL", 11598 auxType: auxInt64, 11599 argLen: 2, 11600 asm: arm64.AAND, 11601 reg: regInfo{ 11602 inputs: []inputInfo{ 11603 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11604 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11605 }, 11606 outputs: []outputInfo{ 11607 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11608 }, 11609 }, 11610 }, 11611 { 11612 name: "ANDshiftRA", 11613 auxType: auxInt64, 11614 argLen: 2, 11615 asm: arm64.AAND, 11616 reg: regInfo{ 11617 inputs: []inputInfo{ 11618 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11619 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11620 }, 11621 outputs: []outputInfo{ 11622 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11623 }, 11624 }, 11625 }, 11626 { 11627 name: "ORshiftLL", 11628 auxType: auxInt64, 11629 argLen: 2, 11630 asm: arm64.AORR, 11631 reg: regInfo{ 11632 inputs: []inputInfo{ 11633 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11634 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11635 }, 11636 outputs: []outputInfo{ 11637 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11638 }, 11639 }, 11640 }, 11641 { 11642 name: "ORshiftRL", 11643 auxType: auxInt64, 11644 argLen: 2, 11645 asm: arm64.AORR, 11646 reg: regInfo{ 11647 inputs: []inputInfo{ 11648 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11649 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11650 }, 11651 outputs: []outputInfo{ 11652 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11653 }, 11654 }, 11655 }, 11656 { 11657 name: "ORshiftRA", 11658 auxType: auxInt64, 11659 argLen: 2, 11660 asm: arm64.AORR, 11661 reg: regInfo{ 11662 inputs: []inputInfo{ 11663 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11664 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11665 }, 11666 outputs: []outputInfo{ 11667 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11668 }, 11669 }, 11670 }, 11671 { 11672 name: "XORshiftLL", 11673 auxType: auxInt64, 11674 argLen: 2, 11675 asm: arm64.AEOR, 11676 reg: regInfo{ 11677 inputs: []inputInfo{ 11678 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11679 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11680 }, 11681 outputs: []outputInfo{ 11682 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11683 }, 11684 }, 11685 }, 11686 { 11687 name: "XORshiftRL", 11688 auxType: auxInt64, 11689 argLen: 2, 11690 asm: arm64.AEOR, 11691 reg: regInfo{ 11692 inputs: []inputInfo{ 11693 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11694 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11695 }, 11696 outputs: []outputInfo{ 11697 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11698 }, 11699 }, 11700 }, 11701 { 11702 name: "XORshiftRA", 11703 auxType: auxInt64, 11704 argLen: 2, 11705 asm: arm64.AEOR, 11706 reg: regInfo{ 11707 inputs: []inputInfo{ 11708 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11709 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11710 }, 11711 outputs: []outputInfo{ 11712 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11713 }, 11714 }, 11715 }, 11716 { 11717 name: "BICshiftLL", 11718 auxType: auxInt64, 11719 argLen: 2, 11720 asm: arm64.ABIC, 11721 reg: regInfo{ 11722 inputs: []inputInfo{ 11723 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11724 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11725 }, 11726 outputs: []outputInfo{ 11727 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11728 }, 11729 }, 11730 }, 11731 { 11732 name: "BICshiftRL", 11733 auxType: auxInt64, 11734 argLen: 2, 11735 asm: arm64.ABIC, 11736 reg: regInfo{ 11737 inputs: []inputInfo{ 11738 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11739 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11740 }, 11741 outputs: []outputInfo{ 11742 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11743 }, 11744 }, 11745 }, 11746 { 11747 name: "BICshiftRA", 11748 auxType: auxInt64, 11749 argLen: 2, 11750 asm: arm64.ABIC, 11751 reg: regInfo{ 11752 inputs: []inputInfo{ 11753 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11754 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11755 }, 11756 outputs: []outputInfo{ 11757 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11758 }, 11759 }, 11760 }, 11761 { 11762 name: "CMPshiftLL", 11763 auxType: auxInt64, 11764 argLen: 2, 11765 asm: arm64.ACMP, 11766 reg: regInfo{ 11767 inputs: []inputInfo{ 11768 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11769 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11770 }, 11771 }, 11772 }, 11773 { 11774 name: "CMPshiftRL", 11775 auxType: auxInt64, 11776 argLen: 2, 11777 asm: arm64.ACMP, 11778 reg: regInfo{ 11779 inputs: []inputInfo{ 11780 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11781 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11782 }, 11783 }, 11784 }, 11785 { 11786 name: "CMPshiftRA", 11787 auxType: auxInt64, 11788 argLen: 2, 11789 asm: arm64.ACMP, 11790 reg: regInfo{ 11791 inputs: []inputInfo{ 11792 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11793 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11794 }, 11795 }, 11796 }, 11797 { 11798 name: "MOVDconst", 11799 auxType: auxInt64, 11800 argLen: 0, 11801 rematerializeable: true, 11802 asm: arm64.AMOVD, 11803 reg: regInfo{ 11804 outputs: []outputInfo{ 11805 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11806 }, 11807 }, 11808 }, 11809 { 11810 name: "FMOVSconst", 11811 auxType: auxFloat64, 11812 argLen: 0, 11813 rematerializeable: true, 11814 asm: arm64.AFMOVS, 11815 reg: regInfo{ 11816 outputs: []outputInfo{ 11817 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11818 }, 11819 }, 11820 }, 11821 { 11822 name: "FMOVDconst", 11823 auxType: auxFloat64, 11824 argLen: 0, 11825 rematerializeable: true, 11826 asm: arm64.AFMOVD, 11827 reg: regInfo{ 11828 outputs: []outputInfo{ 11829 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11830 }, 11831 }, 11832 }, 11833 { 11834 name: "MOVDaddr", 11835 auxType: auxSymOff, 11836 argLen: 1, 11837 rematerializeable: true, 11838 asm: arm64.AMOVD, 11839 reg: regInfo{ 11840 inputs: []inputInfo{ 11841 {0, 9223372037928517632}, // SP SB 11842 }, 11843 outputs: []outputInfo{ 11844 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11845 }, 11846 }, 11847 }, 11848 { 11849 name: "MOVBload", 11850 auxType: auxSymOff, 11851 argLen: 2, 11852 faultOnNilArg0: true, 11853 asm: arm64.AMOVB, 11854 reg: regInfo{ 11855 inputs: []inputInfo{ 11856 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11857 }, 11858 outputs: []outputInfo{ 11859 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11860 }, 11861 }, 11862 }, 11863 { 11864 name: "MOVBUload", 11865 auxType: auxSymOff, 11866 argLen: 2, 11867 faultOnNilArg0: true, 11868 asm: arm64.AMOVBU, 11869 reg: regInfo{ 11870 inputs: []inputInfo{ 11871 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11872 }, 11873 outputs: []outputInfo{ 11874 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11875 }, 11876 }, 11877 }, 11878 { 11879 name: "MOVHload", 11880 auxType: auxSymOff, 11881 argLen: 2, 11882 faultOnNilArg0: true, 11883 asm: arm64.AMOVH, 11884 reg: regInfo{ 11885 inputs: []inputInfo{ 11886 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11887 }, 11888 outputs: []outputInfo{ 11889 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11890 }, 11891 }, 11892 }, 11893 { 11894 name: "MOVHUload", 11895 auxType: auxSymOff, 11896 argLen: 2, 11897 faultOnNilArg0: true, 11898 asm: arm64.AMOVHU, 11899 reg: regInfo{ 11900 inputs: []inputInfo{ 11901 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11902 }, 11903 outputs: []outputInfo{ 11904 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11905 }, 11906 }, 11907 }, 11908 { 11909 name: "MOVWload", 11910 auxType: auxSymOff, 11911 argLen: 2, 11912 faultOnNilArg0: true, 11913 asm: arm64.AMOVW, 11914 reg: regInfo{ 11915 inputs: []inputInfo{ 11916 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11917 }, 11918 outputs: []outputInfo{ 11919 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11920 }, 11921 }, 11922 }, 11923 { 11924 name: "MOVWUload", 11925 auxType: auxSymOff, 11926 argLen: 2, 11927 faultOnNilArg0: true, 11928 asm: arm64.AMOVWU, 11929 reg: regInfo{ 11930 inputs: []inputInfo{ 11931 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11932 }, 11933 outputs: []outputInfo{ 11934 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11935 }, 11936 }, 11937 }, 11938 { 11939 name: "MOVDload", 11940 auxType: auxSymOff, 11941 argLen: 2, 11942 faultOnNilArg0: true, 11943 asm: arm64.AMOVD, 11944 reg: regInfo{ 11945 inputs: []inputInfo{ 11946 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11947 }, 11948 outputs: []outputInfo{ 11949 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11950 }, 11951 }, 11952 }, 11953 { 11954 name: "FMOVSload", 11955 auxType: auxSymOff, 11956 argLen: 2, 11957 faultOnNilArg0: true, 11958 asm: arm64.AFMOVS, 11959 reg: regInfo{ 11960 inputs: []inputInfo{ 11961 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11962 }, 11963 outputs: []outputInfo{ 11964 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11965 }, 11966 }, 11967 }, 11968 { 11969 name: "FMOVDload", 11970 auxType: auxSymOff, 11971 argLen: 2, 11972 faultOnNilArg0: true, 11973 asm: arm64.AFMOVD, 11974 reg: regInfo{ 11975 inputs: []inputInfo{ 11976 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11977 }, 11978 outputs: []outputInfo{ 11979 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11980 }, 11981 }, 11982 }, 11983 { 11984 name: "MOVBstore", 11985 auxType: auxSymOff, 11986 argLen: 3, 11987 faultOnNilArg0: true, 11988 asm: arm64.AMOVB, 11989 reg: regInfo{ 11990 inputs: []inputInfo{ 11991 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11992 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11993 }, 11994 }, 11995 }, 11996 { 11997 name: "MOVHstore", 11998 auxType: auxSymOff, 11999 argLen: 3, 12000 faultOnNilArg0: true, 12001 asm: arm64.AMOVH, 12002 reg: regInfo{ 12003 inputs: []inputInfo{ 12004 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12005 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12006 }, 12007 }, 12008 }, 12009 { 12010 name: "MOVWstore", 12011 auxType: auxSymOff, 12012 argLen: 3, 12013 faultOnNilArg0: true, 12014 asm: arm64.AMOVW, 12015 reg: regInfo{ 12016 inputs: []inputInfo{ 12017 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12018 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12019 }, 12020 }, 12021 }, 12022 { 12023 name: "MOVDstore", 12024 auxType: auxSymOff, 12025 argLen: 3, 12026 faultOnNilArg0: true, 12027 asm: arm64.AMOVD, 12028 reg: regInfo{ 12029 inputs: []inputInfo{ 12030 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12031 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12032 }, 12033 }, 12034 }, 12035 { 12036 name: "FMOVSstore", 12037 auxType: auxSymOff, 12038 argLen: 3, 12039 faultOnNilArg0: true, 12040 asm: arm64.AFMOVS, 12041 reg: regInfo{ 12042 inputs: []inputInfo{ 12043 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12044 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12045 }, 12046 }, 12047 }, 12048 { 12049 name: "FMOVDstore", 12050 auxType: auxSymOff, 12051 argLen: 3, 12052 faultOnNilArg0: true, 12053 asm: arm64.AFMOVD, 12054 reg: regInfo{ 12055 inputs: []inputInfo{ 12056 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12057 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12058 }, 12059 }, 12060 }, 12061 { 12062 name: "MOVBstorezero", 12063 auxType: auxSymOff, 12064 argLen: 2, 12065 faultOnNilArg0: true, 12066 asm: arm64.AMOVB, 12067 reg: regInfo{ 12068 inputs: []inputInfo{ 12069 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12070 }, 12071 }, 12072 }, 12073 { 12074 name: "MOVHstorezero", 12075 auxType: auxSymOff, 12076 argLen: 2, 12077 faultOnNilArg0: true, 12078 asm: arm64.AMOVH, 12079 reg: regInfo{ 12080 inputs: []inputInfo{ 12081 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12082 }, 12083 }, 12084 }, 12085 { 12086 name: "MOVWstorezero", 12087 auxType: auxSymOff, 12088 argLen: 2, 12089 faultOnNilArg0: true, 12090 asm: arm64.AMOVW, 12091 reg: regInfo{ 12092 inputs: []inputInfo{ 12093 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12094 }, 12095 }, 12096 }, 12097 { 12098 name: "MOVDstorezero", 12099 auxType: auxSymOff, 12100 argLen: 2, 12101 faultOnNilArg0: true, 12102 asm: arm64.AMOVD, 12103 reg: regInfo{ 12104 inputs: []inputInfo{ 12105 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12106 }, 12107 }, 12108 }, 12109 { 12110 name: "MOVBreg", 12111 argLen: 1, 12112 asm: arm64.AMOVB, 12113 reg: regInfo{ 12114 inputs: []inputInfo{ 12115 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12116 }, 12117 outputs: []outputInfo{ 12118 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12119 }, 12120 }, 12121 }, 12122 { 12123 name: "MOVBUreg", 12124 argLen: 1, 12125 asm: arm64.AMOVBU, 12126 reg: regInfo{ 12127 inputs: []inputInfo{ 12128 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12129 }, 12130 outputs: []outputInfo{ 12131 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12132 }, 12133 }, 12134 }, 12135 { 12136 name: "MOVHreg", 12137 argLen: 1, 12138 asm: arm64.AMOVH, 12139 reg: regInfo{ 12140 inputs: []inputInfo{ 12141 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12142 }, 12143 outputs: []outputInfo{ 12144 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12145 }, 12146 }, 12147 }, 12148 { 12149 name: "MOVHUreg", 12150 argLen: 1, 12151 asm: arm64.AMOVHU, 12152 reg: regInfo{ 12153 inputs: []inputInfo{ 12154 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12155 }, 12156 outputs: []outputInfo{ 12157 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12158 }, 12159 }, 12160 }, 12161 { 12162 name: "MOVWreg", 12163 argLen: 1, 12164 asm: arm64.AMOVW, 12165 reg: regInfo{ 12166 inputs: []inputInfo{ 12167 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12168 }, 12169 outputs: []outputInfo{ 12170 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12171 }, 12172 }, 12173 }, 12174 { 12175 name: "MOVWUreg", 12176 argLen: 1, 12177 asm: arm64.AMOVWU, 12178 reg: regInfo{ 12179 inputs: []inputInfo{ 12180 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12181 }, 12182 outputs: []outputInfo{ 12183 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12184 }, 12185 }, 12186 }, 12187 { 12188 name: "MOVDreg", 12189 argLen: 1, 12190 asm: arm64.AMOVD, 12191 reg: regInfo{ 12192 inputs: []inputInfo{ 12193 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12194 }, 12195 outputs: []outputInfo{ 12196 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12197 }, 12198 }, 12199 }, 12200 { 12201 name: "MOVDnop", 12202 argLen: 1, 12203 resultInArg0: true, 12204 reg: regInfo{ 12205 inputs: []inputInfo{ 12206 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12207 }, 12208 outputs: []outputInfo{ 12209 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12210 }, 12211 }, 12212 }, 12213 { 12214 name: "SCVTFWS", 12215 argLen: 1, 12216 asm: arm64.ASCVTFWS, 12217 reg: regInfo{ 12218 inputs: []inputInfo{ 12219 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12220 }, 12221 outputs: []outputInfo{ 12222 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12223 }, 12224 }, 12225 }, 12226 { 12227 name: "SCVTFWD", 12228 argLen: 1, 12229 asm: arm64.ASCVTFWD, 12230 reg: regInfo{ 12231 inputs: []inputInfo{ 12232 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12233 }, 12234 outputs: []outputInfo{ 12235 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12236 }, 12237 }, 12238 }, 12239 { 12240 name: "UCVTFWS", 12241 argLen: 1, 12242 asm: arm64.AUCVTFWS, 12243 reg: regInfo{ 12244 inputs: []inputInfo{ 12245 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12246 }, 12247 outputs: []outputInfo{ 12248 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12249 }, 12250 }, 12251 }, 12252 { 12253 name: "UCVTFWD", 12254 argLen: 1, 12255 asm: arm64.AUCVTFWD, 12256 reg: regInfo{ 12257 inputs: []inputInfo{ 12258 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12259 }, 12260 outputs: []outputInfo{ 12261 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12262 }, 12263 }, 12264 }, 12265 { 12266 name: "SCVTFS", 12267 argLen: 1, 12268 asm: arm64.ASCVTFS, 12269 reg: regInfo{ 12270 inputs: []inputInfo{ 12271 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12272 }, 12273 outputs: []outputInfo{ 12274 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12275 }, 12276 }, 12277 }, 12278 { 12279 name: "SCVTFD", 12280 argLen: 1, 12281 asm: arm64.ASCVTFD, 12282 reg: regInfo{ 12283 inputs: []inputInfo{ 12284 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12285 }, 12286 outputs: []outputInfo{ 12287 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12288 }, 12289 }, 12290 }, 12291 { 12292 name: "UCVTFS", 12293 argLen: 1, 12294 asm: arm64.AUCVTFS, 12295 reg: regInfo{ 12296 inputs: []inputInfo{ 12297 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12298 }, 12299 outputs: []outputInfo{ 12300 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12301 }, 12302 }, 12303 }, 12304 { 12305 name: "UCVTFD", 12306 argLen: 1, 12307 asm: arm64.AUCVTFD, 12308 reg: regInfo{ 12309 inputs: []inputInfo{ 12310 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12311 }, 12312 outputs: []outputInfo{ 12313 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12314 }, 12315 }, 12316 }, 12317 { 12318 name: "FCVTZSSW", 12319 argLen: 1, 12320 asm: arm64.AFCVTZSSW, 12321 reg: regInfo{ 12322 inputs: []inputInfo{ 12323 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12324 }, 12325 outputs: []outputInfo{ 12326 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12327 }, 12328 }, 12329 }, 12330 { 12331 name: "FCVTZSDW", 12332 argLen: 1, 12333 asm: arm64.AFCVTZSDW, 12334 reg: regInfo{ 12335 inputs: []inputInfo{ 12336 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12337 }, 12338 outputs: []outputInfo{ 12339 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12340 }, 12341 }, 12342 }, 12343 { 12344 name: "FCVTZUSW", 12345 argLen: 1, 12346 asm: arm64.AFCVTZUSW, 12347 reg: regInfo{ 12348 inputs: []inputInfo{ 12349 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12350 }, 12351 outputs: []outputInfo{ 12352 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12353 }, 12354 }, 12355 }, 12356 { 12357 name: "FCVTZUDW", 12358 argLen: 1, 12359 asm: arm64.AFCVTZUDW, 12360 reg: regInfo{ 12361 inputs: []inputInfo{ 12362 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12363 }, 12364 outputs: []outputInfo{ 12365 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12366 }, 12367 }, 12368 }, 12369 { 12370 name: "FCVTZSS", 12371 argLen: 1, 12372 asm: arm64.AFCVTZSS, 12373 reg: regInfo{ 12374 inputs: []inputInfo{ 12375 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12376 }, 12377 outputs: []outputInfo{ 12378 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12379 }, 12380 }, 12381 }, 12382 { 12383 name: "FCVTZSD", 12384 argLen: 1, 12385 asm: arm64.AFCVTZSD, 12386 reg: regInfo{ 12387 inputs: []inputInfo{ 12388 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12389 }, 12390 outputs: []outputInfo{ 12391 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12392 }, 12393 }, 12394 }, 12395 { 12396 name: "FCVTZUS", 12397 argLen: 1, 12398 asm: arm64.AFCVTZUS, 12399 reg: regInfo{ 12400 inputs: []inputInfo{ 12401 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12402 }, 12403 outputs: []outputInfo{ 12404 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12405 }, 12406 }, 12407 }, 12408 { 12409 name: "FCVTZUD", 12410 argLen: 1, 12411 asm: arm64.AFCVTZUD, 12412 reg: regInfo{ 12413 inputs: []inputInfo{ 12414 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12415 }, 12416 outputs: []outputInfo{ 12417 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12418 }, 12419 }, 12420 }, 12421 { 12422 name: "FCVTSD", 12423 argLen: 1, 12424 asm: arm64.AFCVTSD, 12425 reg: regInfo{ 12426 inputs: []inputInfo{ 12427 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12428 }, 12429 outputs: []outputInfo{ 12430 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12431 }, 12432 }, 12433 }, 12434 { 12435 name: "FCVTDS", 12436 argLen: 1, 12437 asm: arm64.AFCVTDS, 12438 reg: regInfo{ 12439 inputs: []inputInfo{ 12440 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12441 }, 12442 outputs: []outputInfo{ 12443 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12444 }, 12445 }, 12446 }, 12447 { 12448 name: "CSELULT", 12449 argLen: 3, 12450 asm: arm64.ACSEL, 12451 reg: regInfo{ 12452 inputs: []inputInfo{ 12453 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12454 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12455 }, 12456 outputs: []outputInfo{ 12457 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12458 }, 12459 }, 12460 }, 12461 { 12462 name: "CSELULT0", 12463 argLen: 2, 12464 asm: arm64.ACSEL, 12465 reg: regInfo{ 12466 inputs: []inputInfo{ 12467 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12468 }, 12469 outputs: []outputInfo{ 12470 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12471 }, 12472 }, 12473 }, 12474 { 12475 name: "CALLstatic", 12476 auxType: auxSymOff, 12477 argLen: 1, 12478 clobberFlags: true, 12479 call: true, 12480 reg: regInfo{ 12481 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12482 }, 12483 }, 12484 { 12485 name: "CALLclosure", 12486 auxType: auxInt64, 12487 argLen: 3, 12488 clobberFlags: true, 12489 call: true, 12490 reg: regInfo{ 12491 inputs: []inputInfo{ 12492 {1, 67108864}, // R26 12493 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 12494 }, 12495 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12496 }, 12497 }, 12498 { 12499 name: "CALLdefer", 12500 auxType: auxInt64, 12501 argLen: 1, 12502 clobberFlags: true, 12503 call: true, 12504 reg: regInfo{ 12505 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12506 }, 12507 }, 12508 { 12509 name: "CALLgo", 12510 auxType: auxInt64, 12511 argLen: 1, 12512 clobberFlags: true, 12513 call: true, 12514 reg: regInfo{ 12515 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12516 }, 12517 }, 12518 { 12519 name: "CALLinter", 12520 auxType: auxInt64, 12521 argLen: 2, 12522 clobberFlags: true, 12523 call: true, 12524 reg: regInfo{ 12525 inputs: []inputInfo{ 12526 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12527 }, 12528 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12529 }, 12530 }, 12531 { 12532 name: "LoweredNilCheck", 12533 argLen: 2, 12534 nilCheck: true, 12535 faultOnNilArg0: true, 12536 reg: regInfo{ 12537 inputs: []inputInfo{ 12538 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12539 }, 12540 }, 12541 }, 12542 { 12543 name: "Equal", 12544 argLen: 1, 12545 reg: regInfo{ 12546 outputs: []outputInfo{ 12547 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12548 }, 12549 }, 12550 }, 12551 { 12552 name: "NotEqual", 12553 argLen: 1, 12554 reg: regInfo{ 12555 outputs: []outputInfo{ 12556 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12557 }, 12558 }, 12559 }, 12560 { 12561 name: "LessThan", 12562 argLen: 1, 12563 reg: regInfo{ 12564 outputs: []outputInfo{ 12565 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12566 }, 12567 }, 12568 }, 12569 { 12570 name: "LessEqual", 12571 argLen: 1, 12572 reg: regInfo{ 12573 outputs: []outputInfo{ 12574 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12575 }, 12576 }, 12577 }, 12578 { 12579 name: "GreaterThan", 12580 argLen: 1, 12581 reg: regInfo{ 12582 outputs: []outputInfo{ 12583 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12584 }, 12585 }, 12586 }, 12587 { 12588 name: "GreaterEqual", 12589 argLen: 1, 12590 reg: regInfo{ 12591 outputs: []outputInfo{ 12592 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12593 }, 12594 }, 12595 }, 12596 { 12597 name: "LessThanU", 12598 argLen: 1, 12599 reg: regInfo{ 12600 outputs: []outputInfo{ 12601 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12602 }, 12603 }, 12604 }, 12605 { 12606 name: "LessEqualU", 12607 argLen: 1, 12608 reg: regInfo{ 12609 outputs: []outputInfo{ 12610 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12611 }, 12612 }, 12613 }, 12614 { 12615 name: "GreaterThanU", 12616 argLen: 1, 12617 reg: regInfo{ 12618 outputs: []outputInfo{ 12619 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12620 }, 12621 }, 12622 }, 12623 { 12624 name: "GreaterEqualU", 12625 argLen: 1, 12626 reg: regInfo{ 12627 outputs: []outputInfo{ 12628 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12629 }, 12630 }, 12631 }, 12632 { 12633 name: "DUFFZERO", 12634 auxType: auxInt64, 12635 argLen: 2, 12636 faultOnNilArg0: true, 12637 reg: regInfo{ 12638 inputs: []inputInfo{ 12639 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12640 }, 12641 clobbers: 536936448, // R16 R30 12642 }, 12643 }, 12644 { 12645 name: "LoweredZero", 12646 argLen: 3, 12647 clobberFlags: true, 12648 faultOnNilArg0: true, 12649 reg: regInfo{ 12650 inputs: []inputInfo{ 12651 {0, 65536}, // R16 12652 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12653 }, 12654 clobbers: 65536, // R16 12655 }, 12656 }, 12657 { 12658 name: "DUFFCOPY", 12659 auxType: auxInt64, 12660 argLen: 3, 12661 faultOnNilArg0: true, 12662 faultOnNilArg1: true, 12663 reg: regInfo{ 12664 inputs: []inputInfo{ 12665 {0, 131072}, // R17 12666 {1, 65536}, // R16 12667 }, 12668 clobbers: 537067520, // R16 R17 R30 12669 }, 12670 }, 12671 { 12672 name: "LoweredMove", 12673 argLen: 4, 12674 clobberFlags: true, 12675 faultOnNilArg0: true, 12676 faultOnNilArg1: true, 12677 reg: regInfo{ 12678 inputs: []inputInfo{ 12679 {0, 131072}, // R17 12680 {1, 65536}, // R16 12681 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12682 }, 12683 clobbers: 196608, // R16 R17 12684 }, 12685 }, 12686 { 12687 name: "LoweredGetClosurePtr", 12688 argLen: 0, 12689 reg: regInfo{ 12690 outputs: []outputInfo{ 12691 {0, 67108864}, // R26 12692 }, 12693 }, 12694 }, 12695 { 12696 name: "MOVDconvert", 12697 argLen: 2, 12698 asm: arm64.AMOVD, 12699 reg: regInfo{ 12700 inputs: []inputInfo{ 12701 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12702 }, 12703 outputs: []outputInfo{ 12704 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12705 }, 12706 }, 12707 }, 12708 { 12709 name: "FlagEQ", 12710 argLen: 0, 12711 reg: regInfo{}, 12712 }, 12713 { 12714 name: "FlagLT_ULT", 12715 argLen: 0, 12716 reg: regInfo{}, 12717 }, 12718 { 12719 name: "FlagLT_UGT", 12720 argLen: 0, 12721 reg: regInfo{}, 12722 }, 12723 { 12724 name: "FlagGT_UGT", 12725 argLen: 0, 12726 reg: regInfo{}, 12727 }, 12728 { 12729 name: "FlagGT_ULT", 12730 argLen: 0, 12731 reg: regInfo{}, 12732 }, 12733 { 12734 name: "InvertFlags", 12735 argLen: 1, 12736 reg: regInfo{}, 12737 }, 12738 { 12739 name: "LDAR", 12740 argLen: 2, 12741 faultOnNilArg0: true, 12742 asm: arm64.ALDAR, 12743 reg: regInfo{ 12744 inputs: []inputInfo{ 12745 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12746 }, 12747 outputs: []outputInfo{ 12748 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12749 }, 12750 }, 12751 }, 12752 { 12753 name: "LDARW", 12754 argLen: 2, 12755 faultOnNilArg0: true, 12756 asm: arm64.ALDARW, 12757 reg: regInfo{ 12758 inputs: []inputInfo{ 12759 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12760 }, 12761 outputs: []outputInfo{ 12762 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12763 }, 12764 }, 12765 }, 12766 { 12767 name: "STLR", 12768 argLen: 3, 12769 faultOnNilArg0: true, 12770 asm: arm64.ASTLR, 12771 reg: regInfo{ 12772 inputs: []inputInfo{ 12773 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12774 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12775 }, 12776 }, 12777 }, 12778 { 12779 name: "STLRW", 12780 argLen: 3, 12781 faultOnNilArg0: true, 12782 asm: arm64.ASTLRW, 12783 reg: regInfo{ 12784 inputs: []inputInfo{ 12785 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12786 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12787 }, 12788 }, 12789 }, 12790 { 12791 name: "LoweredAtomicExchange64", 12792 argLen: 3, 12793 resultNotInArgs: true, 12794 faultOnNilArg0: true, 12795 reg: regInfo{ 12796 inputs: []inputInfo{ 12797 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12798 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12799 }, 12800 outputs: []outputInfo{ 12801 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12802 }, 12803 }, 12804 }, 12805 { 12806 name: "LoweredAtomicExchange32", 12807 argLen: 3, 12808 resultNotInArgs: true, 12809 faultOnNilArg0: true, 12810 reg: regInfo{ 12811 inputs: []inputInfo{ 12812 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12813 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12814 }, 12815 outputs: []outputInfo{ 12816 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12817 }, 12818 }, 12819 }, 12820 { 12821 name: "LoweredAtomicAdd64", 12822 argLen: 3, 12823 resultNotInArgs: true, 12824 faultOnNilArg0: true, 12825 reg: regInfo{ 12826 inputs: []inputInfo{ 12827 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12828 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12829 }, 12830 outputs: []outputInfo{ 12831 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12832 }, 12833 }, 12834 }, 12835 { 12836 name: "LoweredAtomicAdd32", 12837 argLen: 3, 12838 resultNotInArgs: true, 12839 faultOnNilArg0: true, 12840 reg: regInfo{ 12841 inputs: []inputInfo{ 12842 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12843 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12844 }, 12845 outputs: []outputInfo{ 12846 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12847 }, 12848 }, 12849 }, 12850 { 12851 name: "LoweredAtomicCas64", 12852 argLen: 4, 12853 resultNotInArgs: true, 12854 clobberFlags: true, 12855 faultOnNilArg0: true, 12856 reg: regInfo{ 12857 inputs: []inputInfo{ 12858 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12859 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12860 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12861 }, 12862 outputs: []outputInfo{ 12863 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12864 }, 12865 }, 12866 }, 12867 { 12868 name: "LoweredAtomicCas32", 12869 argLen: 4, 12870 resultNotInArgs: true, 12871 clobberFlags: true, 12872 faultOnNilArg0: true, 12873 reg: regInfo{ 12874 inputs: []inputInfo{ 12875 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12876 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12877 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12878 }, 12879 outputs: []outputInfo{ 12880 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12881 }, 12882 }, 12883 }, 12884 { 12885 name: "LoweredAtomicAnd8", 12886 argLen: 3, 12887 faultOnNilArg0: true, 12888 asm: arm64.AAND, 12889 reg: regInfo{ 12890 inputs: []inputInfo{ 12891 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12892 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12893 }, 12894 }, 12895 }, 12896 { 12897 name: "LoweredAtomicOr8", 12898 argLen: 3, 12899 faultOnNilArg0: true, 12900 asm: arm64.AORR, 12901 reg: regInfo{ 12902 inputs: []inputInfo{ 12903 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12904 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12905 }, 12906 }, 12907 }, 12908 12909 { 12910 name: "ADD", 12911 argLen: 2, 12912 commutative: true, 12913 asm: mips.AADDU, 12914 reg: regInfo{ 12915 inputs: []inputInfo{ 12916 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12917 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12918 }, 12919 outputs: []outputInfo{ 12920 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12921 }, 12922 }, 12923 }, 12924 { 12925 name: "ADDconst", 12926 auxType: auxInt32, 12927 argLen: 1, 12928 asm: mips.AADDU, 12929 reg: regInfo{ 12930 inputs: []inputInfo{ 12931 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 12932 }, 12933 outputs: []outputInfo{ 12934 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12935 }, 12936 }, 12937 }, 12938 { 12939 name: "SUB", 12940 argLen: 2, 12941 asm: mips.ASUBU, 12942 reg: regInfo{ 12943 inputs: []inputInfo{ 12944 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12945 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12946 }, 12947 outputs: []outputInfo{ 12948 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12949 }, 12950 }, 12951 }, 12952 { 12953 name: "SUBconst", 12954 auxType: auxInt32, 12955 argLen: 1, 12956 asm: mips.ASUBU, 12957 reg: regInfo{ 12958 inputs: []inputInfo{ 12959 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12960 }, 12961 outputs: []outputInfo{ 12962 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12963 }, 12964 }, 12965 }, 12966 { 12967 name: "MUL", 12968 argLen: 2, 12969 commutative: true, 12970 asm: mips.AMUL, 12971 reg: regInfo{ 12972 inputs: []inputInfo{ 12973 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12974 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12975 }, 12976 clobbers: 105553116266496, // HI LO 12977 outputs: []outputInfo{ 12978 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12979 }, 12980 }, 12981 }, 12982 { 12983 name: "MULT", 12984 argLen: 2, 12985 commutative: true, 12986 asm: mips.AMUL, 12987 reg: regInfo{ 12988 inputs: []inputInfo{ 12989 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12990 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12991 }, 12992 outputs: []outputInfo{ 12993 {0, 35184372088832}, // HI 12994 {1, 70368744177664}, // LO 12995 }, 12996 }, 12997 }, 12998 { 12999 name: "MULTU", 13000 argLen: 2, 13001 commutative: true, 13002 asm: mips.AMULU, 13003 reg: regInfo{ 13004 inputs: []inputInfo{ 13005 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13006 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13007 }, 13008 outputs: []outputInfo{ 13009 {0, 35184372088832}, // HI 13010 {1, 70368744177664}, // LO 13011 }, 13012 }, 13013 }, 13014 { 13015 name: "DIV", 13016 argLen: 2, 13017 asm: mips.ADIV, 13018 reg: regInfo{ 13019 inputs: []inputInfo{ 13020 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13021 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13022 }, 13023 outputs: []outputInfo{ 13024 {0, 35184372088832}, // HI 13025 {1, 70368744177664}, // LO 13026 }, 13027 }, 13028 }, 13029 { 13030 name: "DIVU", 13031 argLen: 2, 13032 asm: mips.ADIVU, 13033 reg: regInfo{ 13034 inputs: []inputInfo{ 13035 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13036 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13037 }, 13038 outputs: []outputInfo{ 13039 {0, 35184372088832}, // HI 13040 {1, 70368744177664}, // LO 13041 }, 13042 }, 13043 }, 13044 { 13045 name: "ADDF", 13046 argLen: 2, 13047 commutative: true, 13048 asm: mips.AADDF, 13049 reg: regInfo{ 13050 inputs: []inputInfo{ 13051 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13052 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13053 }, 13054 outputs: []outputInfo{ 13055 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13056 }, 13057 }, 13058 }, 13059 { 13060 name: "ADDD", 13061 argLen: 2, 13062 commutative: true, 13063 asm: mips.AADDD, 13064 reg: regInfo{ 13065 inputs: []inputInfo{ 13066 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13067 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13068 }, 13069 outputs: []outputInfo{ 13070 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13071 }, 13072 }, 13073 }, 13074 { 13075 name: "SUBF", 13076 argLen: 2, 13077 asm: mips.ASUBF, 13078 reg: regInfo{ 13079 inputs: []inputInfo{ 13080 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13081 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13082 }, 13083 outputs: []outputInfo{ 13084 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13085 }, 13086 }, 13087 }, 13088 { 13089 name: "SUBD", 13090 argLen: 2, 13091 asm: mips.ASUBD, 13092 reg: regInfo{ 13093 inputs: []inputInfo{ 13094 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13095 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13096 }, 13097 outputs: []outputInfo{ 13098 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13099 }, 13100 }, 13101 }, 13102 { 13103 name: "MULF", 13104 argLen: 2, 13105 commutative: true, 13106 asm: mips.AMULF, 13107 reg: regInfo{ 13108 inputs: []inputInfo{ 13109 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13110 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13111 }, 13112 outputs: []outputInfo{ 13113 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13114 }, 13115 }, 13116 }, 13117 { 13118 name: "MULD", 13119 argLen: 2, 13120 commutative: true, 13121 asm: mips.AMULD, 13122 reg: regInfo{ 13123 inputs: []inputInfo{ 13124 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13125 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13126 }, 13127 outputs: []outputInfo{ 13128 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13129 }, 13130 }, 13131 }, 13132 { 13133 name: "DIVF", 13134 argLen: 2, 13135 asm: mips.ADIVF, 13136 reg: regInfo{ 13137 inputs: []inputInfo{ 13138 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13139 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13140 }, 13141 outputs: []outputInfo{ 13142 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13143 }, 13144 }, 13145 }, 13146 { 13147 name: "DIVD", 13148 argLen: 2, 13149 asm: mips.ADIVD, 13150 reg: regInfo{ 13151 inputs: []inputInfo{ 13152 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13153 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13154 }, 13155 outputs: []outputInfo{ 13156 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13157 }, 13158 }, 13159 }, 13160 { 13161 name: "AND", 13162 argLen: 2, 13163 commutative: true, 13164 asm: mips.AAND, 13165 reg: regInfo{ 13166 inputs: []inputInfo{ 13167 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13168 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13169 }, 13170 outputs: []outputInfo{ 13171 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13172 }, 13173 }, 13174 }, 13175 { 13176 name: "ANDconst", 13177 auxType: auxInt32, 13178 argLen: 1, 13179 asm: mips.AAND, 13180 reg: regInfo{ 13181 inputs: []inputInfo{ 13182 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13183 }, 13184 outputs: []outputInfo{ 13185 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13186 }, 13187 }, 13188 }, 13189 { 13190 name: "OR", 13191 argLen: 2, 13192 commutative: true, 13193 asm: mips.AOR, 13194 reg: regInfo{ 13195 inputs: []inputInfo{ 13196 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13197 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13198 }, 13199 outputs: []outputInfo{ 13200 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13201 }, 13202 }, 13203 }, 13204 { 13205 name: "ORconst", 13206 auxType: auxInt32, 13207 argLen: 1, 13208 asm: mips.AOR, 13209 reg: regInfo{ 13210 inputs: []inputInfo{ 13211 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13212 }, 13213 outputs: []outputInfo{ 13214 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13215 }, 13216 }, 13217 }, 13218 { 13219 name: "XOR", 13220 argLen: 2, 13221 commutative: true, 13222 asm: mips.AXOR, 13223 reg: regInfo{ 13224 inputs: []inputInfo{ 13225 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13226 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13227 }, 13228 outputs: []outputInfo{ 13229 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13230 }, 13231 }, 13232 }, 13233 { 13234 name: "XORconst", 13235 auxType: auxInt32, 13236 argLen: 1, 13237 asm: mips.AXOR, 13238 reg: regInfo{ 13239 inputs: []inputInfo{ 13240 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13241 }, 13242 outputs: []outputInfo{ 13243 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13244 }, 13245 }, 13246 }, 13247 { 13248 name: "NOR", 13249 argLen: 2, 13250 commutative: true, 13251 asm: mips.ANOR, 13252 reg: regInfo{ 13253 inputs: []inputInfo{ 13254 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13255 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13256 }, 13257 outputs: []outputInfo{ 13258 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13259 }, 13260 }, 13261 }, 13262 { 13263 name: "NORconst", 13264 auxType: auxInt32, 13265 argLen: 1, 13266 asm: mips.ANOR, 13267 reg: regInfo{ 13268 inputs: []inputInfo{ 13269 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13270 }, 13271 outputs: []outputInfo{ 13272 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13273 }, 13274 }, 13275 }, 13276 { 13277 name: "NEG", 13278 argLen: 1, 13279 reg: regInfo{ 13280 inputs: []inputInfo{ 13281 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13282 }, 13283 outputs: []outputInfo{ 13284 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13285 }, 13286 }, 13287 }, 13288 { 13289 name: "NEGF", 13290 argLen: 1, 13291 asm: mips.ANEGF, 13292 reg: regInfo{ 13293 inputs: []inputInfo{ 13294 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13295 }, 13296 outputs: []outputInfo{ 13297 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13298 }, 13299 }, 13300 }, 13301 { 13302 name: "NEGD", 13303 argLen: 1, 13304 asm: mips.ANEGD, 13305 reg: regInfo{ 13306 inputs: []inputInfo{ 13307 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13308 }, 13309 outputs: []outputInfo{ 13310 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13311 }, 13312 }, 13313 }, 13314 { 13315 name: "SQRTD", 13316 argLen: 1, 13317 asm: mips.ASQRTD, 13318 reg: regInfo{ 13319 inputs: []inputInfo{ 13320 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13321 }, 13322 outputs: []outputInfo{ 13323 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13324 }, 13325 }, 13326 }, 13327 { 13328 name: "SLL", 13329 argLen: 2, 13330 asm: mips.ASLL, 13331 reg: regInfo{ 13332 inputs: []inputInfo{ 13333 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13334 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13335 }, 13336 outputs: []outputInfo{ 13337 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13338 }, 13339 }, 13340 }, 13341 { 13342 name: "SLLconst", 13343 auxType: auxInt32, 13344 argLen: 1, 13345 asm: mips.ASLL, 13346 reg: regInfo{ 13347 inputs: []inputInfo{ 13348 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13349 }, 13350 outputs: []outputInfo{ 13351 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13352 }, 13353 }, 13354 }, 13355 { 13356 name: "SRL", 13357 argLen: 2, 13358 asm: mips.ASRL, 13359 reg: regInfo{ 13360 inputs: []inputInfo{ 13361 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13362 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13363 }, 13364 outputs: []outputInfo{ 13365 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13366 }, 13367 }, 13368 }, 13369 { 13370 name: "SRLconst", 13371 auxType: auxInt32, 13372 argLen: 1, 13373 asm: mips.ASRL, 13374 reg: regInfo{ 13375 inputs: []inputInfo{ 13376 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13377 }, 13378 outputs: []outputInfo{ 13379 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13380 }, 13381 }, 13382 }, 13383 { 13384 name: "SRA", 13385 argLen: 2, 13386 asm: mips.ASRA, 13387 reg: regInfo{ 13388 inputs: []inputInfo{ 13389 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13390 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13391 }, 13392 outputs: []outputInfo{ 13393 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13394 }, 13395 }, 13396 }, 13397 { 13398 name: "SRAconst", 13399 auxType: auxInt32, 13400 argLen: 1, 13401 asm: mips.ASRA, 13402 reg: regInfo{ 13403 inputs: []inputInfo{ 13404 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13405 }, 13406 outputs: []outputInfo{ 13407 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13408 }, 13409 }, 13410 }, 13411 { 13412 name: "CLZ", 13413 argLen: 1, 13414 asm: mips.ACLZ, 13415 reg: regInfo{ 13416 inputs: []inputInfo{ 13417 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13418 }, 13419 outputs: []outputInfo{ 13420 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13421 }, 13422 }, 13423 }, 13424 { 13425 name: "SGT", 13426 argLen: 2, 13427 asm: mips.ASGT, 13428 reg: regInfo{ 13429 inputs: []inputInfo{ 13430 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13431 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13432 }, 13433 outputs: []outputInfo{ 13434 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13435 }, 13436 }, 13437 }, 13438 { 13439 name: "SGTconst", 13440 auxType: auxInt32, 13441 argLen: 1, 13442 asm: mips.ASGT, 13443 reg: regInfo{ 13444 inputs: []inputInfo{ 13445 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13446 }, 13447 outputs: []outputInfo{ 13448 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13449 }, 13450 }, 13451 }, 13452 { 13453 name: "SGTzero", 13454 argLen: 1, 13455 asm: mips.ASGT, 13456 reg: regInfo{ 13457 inputs: []inputInfo{ 13458 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13459 }, 13460 outputs: []outputInfo{ 13461 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13462 }, 13463 }, 13464 }, 13465 { 13466 name: "SGTU", 13467 argLen: 2, 13468 asm: mips.ASGTU, 13469 reg: regInfo{ 13470 inputs: []inputInfo{ 13471 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13472 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13473 }, 13474 outputs: []outputInfo{ 13475 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13476 }, 13477 }, 13478 }, 13479 { 13480 name: "SGTUconst", 13481 auxType: auxInt32, 13482 argLen: 1, 13483 asm: mips.ASGTU, 13484 reg: regInfo{ 13485 inputs: []inputInfo{ 13486 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13487 }, 13488 outputs: []outputInfo{ 13489 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13490 }, 13491 }, 13492 }, 13493 { 13494 name: "SGTUzero", 13495 argLen: 1, 13496 asm: mips.ASGTU, 13497 reg: regInfo{ 13498 inputs: []inputInfo{ 13499 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13500 }, 13501 outputs: []outputInfo{ 13502 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13503 }, 13504 }, 13505 }, 13506 { 13507 name: "CMPEQF", 13508 argLen: 2, 13509 asm: mips.ACMPEQF, 13510 reg: regInfo{ 13511 inputs: []inputInfo{ 13512 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13513 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13514 }, 13515 }, 13516 }, 13517 { 13518 name: "CMPEQD", 13519 argLen: 2, 13520 asm: mips.ACMPEQD, 13521 reg: regInfo{ 13522 inputs: []inputInfo{ 13523 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13524 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13525 }, 13526 }, 13527 }, 13528 { 13529 name: "CMPGEF", 13530 argLen: 2, 13531 asm: mips.ACMPGEF, 13532 reg: regInfo{ 13533 inputs: []inputInfo{ 13534 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13535 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13536 }, 13537 }, 13538 }, 13539 { 13540 name: "CMPGED", 13541 argLen: 2, 13542 asm: mips.ACMPGED, 13543 reg: regInfo{ 13544 inputs: []inputInfo{ 13545 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13546 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13547 }, 13548 }, 13549 }, 13550 { 13551 name: "CMPGTF", 13552 argLen: 2, 13553 asm: mips.ACMPGTF, 13554 reg: regInfo{ 13555 inputs: []inputInfo{ 13556 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13557 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13558 }, 13559 }, 13560 }, 13561 { 13562 name: "CMPGTD", 13563 argLen: 2, 13564 asm: mips.ACMPGTD, 13565 reg: regInfo{ 13566 inputs: []inputInfo{ 13567 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13568 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13569 }, 13570 }, 13571 }, 13572 { 13573 name: "MOVWconst", 13574 auxType: auxInt32, 13575 argLen: 0, 13576 rematerializeable: true, 13577 asm: mips.AMOVW, 13578 reg: regInfo{ 13579 outputs: []outputInfo{ 13580 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13581 }, 13582 }, 13583 }, 13584 { 13585 name: "MOVFconst", 13586 auxType: auxFloat32, 13587 argLen: 0, 13588 rematerializeable: true, 13589 asm: mips.AMOVF, 13590 reg: regInfo{ 13591 outputs: []outputInfo{ 13592 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13593 }, 13594 }, 13595 }, 13596 { 13597 name: "MOVDconst", 13598 auxType: auxFloat64, 13599 argLen: 0, 13600 rematerializeable: true, 13601 asm: mips.AMOVD, 13602 reg: regInfo{ 13603 outputs: []outputInfo{ 13604 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13605 }, 13606 }, 13607 }, 13608 { 13609 name: "MOVWaddr", 13610 auxType: auxSymOff, 13611 argLen: 1, 13612 rematerializeable: true, 13613 asm: mips.AMOVW, 13614 reg: regInfo{ 13615 inputs: []inputInfo{ 13616 {0, 140737555464192}, // SP SB 13617 }, 13618 outputs: []outputInfo{ 13619 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13620 }, 13621 }, 13622 }, 13623 { 13624 name: "MOVBload", 13625 auxType: auxSymOff, 13626 argLen: 2, 13627 faultOnNilArg0: true, 13628 asm: mips.AMOVB, 13629 reg: regInfo{ 13630 inputs: []inputInfo{ 13631 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13632 }, 13633 outputs: []outputInfo{ 13634 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13635 }, 13636 }, 13637 }, 13638 { 13639 name: "MOVBUload", 13640 auxType: auxSymOff, 13641 argLen: 2, 13642 faultOnNilArg0: true, 13643 asm: mips.AMOVBU, 13644 reg: regInfo{ 13645 inputs: []inputInfo{ 13646 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13647 }, 13648 outputs: []outputInfo{ 13649 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13650 }, 13651 }, 13652 }, 13653 { 13654 name: "MOVHload", 13655 auxType: auxSymOff, 13656 argLen: 2, 13657 faultOnNilArg0: true, 13658 asm: mips.AMOVH, 13659 reg: regInfo{ 13660 inputs: []inputInfo{ 13661 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13662 }, 13663 outputs: []outputInfo{ 13664 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13665 }, 13666 }, 13667 }, 13668 { 13669 name: "MOVHUload", 13670 auxType: auxSymOff, 13671 argLen: 2, 13672 faultOnNilArg0: true, 13673 asm: mips.AMOVHU, 13674 reg: regInfo{ 13675 inputs: []inputInfo{ 13676 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13677 }, 13678 outputs: []outputInfo{ 13679 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13680 }, 13681 }, 13682 }, 13683 { 13684 name: "MOVWload", 13685 auxType: auxSymOff, 13686 argLen: 2, 13687 faultOnNilArg0: true, 13688 asm: mips.AMOVW, 13689 reg: regInfo{ 13690 inputs: []inputInfo{ 13691 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13692 }, 13693 outputs: []outputInfo{ 13694 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13695 }, 13696 }, 13697 }, 13698 { 13699 name: "MOVFload", 13700 auxType: auxSymOff, 13701 argLen: 2, 13702 faultOnNilArg0: true, 13703 asm: mips.AMOVF, 13704 reg: regInfo{ 13705 inputs: []inputInfo{ 13706 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13707 }, 13708 outputs: []outputInfo{ 13709 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13710 }, 13711 }, 13712 }, 13713 { 13714 name: "MOVDload", 13715 auxType: auxSymOff, 13716 argLen: 2, 13717 faultOnNilArg0: true, 13718 asm: mips.AMOVD, 13719 reg: regInfo{ 13720 inputs: []inputInfo{ 13721 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13722 }, 13723 outputs: []outputInfo{ 13724 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13725 }, 13726 }, 13727 }, 13728 { 13729 name: "MOVBstore", 13730 auxType: auxSymOff, 13731 argLen: 3, 13732 faultOnNilArg0: true, 13733 asm: mips.AMOVB, 13734 reg: regInfo{ 13735 inputs: []inputInfo{ 13736 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13737 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13738 }, 13739 }, 13740 }, 13741 { 13742 name: "MOVHstore", 13743 auxType: auxSymOff, 13744 argLen: 3, 13745 faultOnNilArg0: true, 13746 asm: mips.AMOVH, 13747 reg: regInfo{ 13748 inputs: []inputInfo{ 13749 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13750 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13751 }, 13752 }, 13753 }, 13754 { 13755 name: "MOVWstore", 13756 auxType: auxSymOff, 13757 argLen: 3, 13758 faultOnNilArg0: true, 13759 asm: mips.AMOVW, 13760 reg: regInfo{ 13761 inputs: []inputInfo{ 13762 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13763 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13764 }, 13765 }, 13766 }, 13767 { 13768 name: "MOVFstore", 13769 auxType: auxSymOff, 13770 argLen: 3, 13771 faultOnNilArg0: true, 13772 asm: mips.AMOVF, 13773 reg: regInfo{ 13774 inputs: []inputInfo{ 13775 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13776 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13777 }, 13778 }, 13779 }, 13780 { 13781 name: "MOVDstore", 13782 auxType: auxSymOff, 13783 argLen: 3, 13784 faultOnNilArg0: true, 13785 asm: mips.AMOVD, 13786 reg: regInfo{ 13787 inputs: []inputInfo{ 13788 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13789 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13790 }, 13791 }, 13792 }, 13793 { 13794 name: "MOVBstorezero", 13795 auxType: auxSymOff, 13796 argLen: 2, 13797 faultOnNilArg0: true, 13798 asm: mips.AMOVB, 13799 reg: regInfo{ 13800 inputs: []inputInfo{ 13801 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13802 }, 13803 }, 13804 }, 13805 { 13806 name: "MOVHstorezero", 13807 auxType: auxSymOff, 13808 argLen: 2, 13809 faultOnNilArg0: true, 13810 asm: mips.AMOVH, 13811 reg: regInfo{ 13812 inputs: []inputInfo{ 13813 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13814 }, 13815 }, 13816 }, 13817 { 13818 name: "MOVWstorezero", 13819 auxType: auxSymOff, 13820 argLen: 2, 13821 faultOnNilArg0: true, 13822 asm: mips.AMOVW, 13823 reg: regInfo{ 13824 inputs: []inputInfo{ 13825 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13826 }, 13827 }, 13828 }, 13829 { 13830 name: "MOVBreg", 13831 argLen: 1, 13832 asm: mips.AMOVB, 13833 reg: regInfo{ 13834 inputs: []inputInfo{ 13835 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13836 }, 13837 outputs: []outputInfo{ 13838 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13839 }, 13840 }, 13841 }, 13842 { 13843 name: "MOVBUreg", 13844 argLen: 1, 13845 asm: mips.AMOVBU, 13846 reg: regInfo{ 13847 inputs: []inputInfo{ 13848 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13849 }, 13850 outputs: []outputInfo{ 13851 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13852 }, 13853 }, 13854 }, 13855 { 13856 name: "MOVHreg", 13857 argLen: 1, 13858 asm: mips.AMOVH, 13859 reg: regInfo{ 13860 inputs: []inputInfo{ 13861 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13862 }, 13863 outputs: []outputInfo{ 13864 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13865 }, 13866 }, 13867 }, 13868 { 13869 name: "MOVHUreg", 13870 argLen: 1, 13871 asm: mips.AMOVHU, 13872 reg: regInfo{ 13873 inputs: []inputInfo{ 13874 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13875 }, 13876 outputs: []outputInfo{ 13877 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13878 }, 13879 }, 13880 }, 13881 { 13882 name: "MOVWreg", 13883 argLen: 1, 13884 asm: mips.AMOVW, 13885 reg: regInfo{ 13886 inputs: []inputInfo{ 13887 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13888 }, 13889 outputs: []outputInfo{ 13890 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13891 }, 13892 }, 13893 }, 13894 { 13895 name: "MOVWnop", 13896 argLen: 1, 13897 resultInArg0: true, 13898 reg: regInfo{ 13899 inputs: []inputInfo{ 13900 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13901 }, 13902 outputs: []outputInfo{ 13903 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13904 }, 13905 }, 13906 }, 13907 { 13908 name: "CMOVZ", 13909 argLen: 3, 13910 resultInArg0: true, 13911 asm: mips.ACMOVZ, 13912 reg: regInfo{ 13913 inputs: []inputInfo{ 13914 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13915 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13916 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13917 }, 13918 outputs: []outputInfo{ 13919 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13920 }, 13921 }, 13922 }, 13923 { 13924 name: "CMOVZzero", 13925 argLen: 2, 13926 resultInArg0: true, 13927 asm: mips.ACMOVZ, 13928 reg: regInfo{ 13929 inputs: []inputInfo{ 13930 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13931 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13932 }, 13933 outputs: []outputInfo{ 13934 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13935 }, 13936 }, 13937 }, 13938 { 13939 name: "MOVWF", 13940 argLen: 1, 13941 asm: mips.AMOVWF, 13942 reg: regInfo{ 13943 inputs: []inputInfo{ 13944 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13945 }, 13946 outputs: []outputInfo{ 13947 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13948 }, 13949 }, 13950 }, 13951 { 13952 name: "MOVWD", 13953 argLen: 1, 13954 asm: mips.AMOVWD, 13955 reg: regInfo{ 13956 inputs: []inputInfo{ 13957 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13958 }, 13959 outputs: []outputInfo{ 13960 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13961 }, 13962 }, 13963 }, 13964 { 13965 name: "TRUNCFW", 13966 argLen: 1, 13967 asm: mips.ATRUNCFW, 13968 reg: regInfo{ 13969 inputs: []inputInfo{ 13970 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13971 }, 13972 outputs: []outputInfo{ 13973 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13974 }, 13975 }, 13976 }, 13977 { 13978 name: "TRUNCDW", 13979 argLen: 1, 13980 asm: mips.ATRUNCDW, 13981 reg: regInfo{ 13982 inputs: []inputInfo{ 13983 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13984 }, 13985 outputs: []outputInfo{ 13986 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13987 }, 13988 }, 13989 }, 13990 { 13991 name: "MOVFD", 13992 argLen: 1, 13993 asm: mips.AMOVFD, 13994 reg: regInfo{ 13995 inputs: []inputInfo{ 13996 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13997 }, 13998 outputs: []outputInfo{ 13999 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14000 }, 14001 }, 14002 }, 14003 { 14004 name: "MOVDF", 14005 argLen: 1, 14006 asm: mips.AMOVDF, 14007 reg: regInfo{ 14008 inputs: []inputInfo{ 14009 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14010 }, 14011 outputs: []outputInfo{ 14012 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14013 }, 14014 }, 14015 }, 14016 { 14017 name: "CALLstatic", 14018 auxType: auxSymOff, 14019 argLen: 1, 14020 clobberFlags: true, 14021 call: true, 14022 reg: regInfo{ 14023 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14024 }, 14025 }, 14026 { 14027 name: "CALLclosure", 14028 auxType: auxInt32, 14029 argLen: 3, 14030 clobberFlags: true, 14031 call: true, 14032 reg: regInfo{ 14033 inputs: []inputInfo{ 14034 {1, 4194304}, // R22 14035 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 14036 }, 14037 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14038 }, 14039 }, 14040 { 14041 name: "CALLdefer", 14042 auxType: auxInt32, 14043 argLen: 1, 14044 clobberFlags: true, 14045 call: true, 14046 reg: regInfo{ 14047 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14048 }, 14049 }, 14050 { 14051 name: "CALLgo", 14052 auxType: auxInt32, 14053 argLen: 1, 14054 clobberFlags: true, 14055 call: true, 14056 reg: regInfo{ 14057 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14058 }, 14059 }, 14060 { 14061 name: "CALLinter", 14062 auxType: auxInt32, 14063 argLen: 2, 14064 clobberFlags: true, 14065 call: true, 14066 reg: regInfo{ 14067 inputs: []inputInfo{ 14068 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14069 }, 14070 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14071 }, 14072 }, 14073 { 14074 name: "LoweredAtomicLoad", 14075 argLen: 2, 14076 faultOnNilArg0: true, 14077 reg: regInfo{ 14078 inputs: []inputInfo{ 14079 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14080 }, 14081 outputs: []outputInfo{ 14082 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14083 }, 14084 }, 14085 }, 14086 { 14087 name: "LoweredAtomicStore", 14088 argLen: 3, 14089 faultOnNilArg0: true, 14090 reg: regInfo{ 14091 inputs: []inputInfo{ 14092 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14093 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14094 }, 14095 }, 14096 }, 14097 { 14098 name: "LoweredAtomicStorezero", 14099 argLen: 2, 14100 faultOnNilArg0: true, 14101 reg: regInfo{ 14102 inputs: []inputInfo{ 14103 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14104 }, 14105 }, 14106 }, 14107 { 14108 name: "LoweredAtomicExchange", 14109 argLen: 3, 14110 resultNotInArgs: true, 14111 faultOnNilArg0: true, 14112 reg: regInfo{ 14113 inputs: []inputInfo{ 14114 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14115 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14116 }, 14117 outputs: []outputInfo{ 14118 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14119 }, 14120 }, 14121 }, 14122 { 14123 name: "LoweredAtomicAdd", 14124 argLen: 3, 14125 resultNotInArgs: true, 14126 faultOnNilArg0: true, 14127 reg: regInfo{ 14128 inputs: []inputInfo{ 14129 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14130 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14131 }, 14132 outputs: []outputInfo{ 14133 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14134 }, 14135 }, 14136 }, 14137 { 14138 name: "LoweredAtomicAddconst", 14139 auxType: auxInt32, 14140 argLen: 2, 14141 resultNotInArgs: true, 14142 faultOnNilArg0: true, 14143 reg: regInfo{ 14144 inputs: []inputInfo{ 14145 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14146 }, 14147 outputs: []outputInfo{ 14148 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14149 }, 14150 }, 14151 }, 14152 { 14153 name: "LoweredAtomicCas", 14154 argLen: 4, 14155 resultNotInArgs: true, 14156 faultOnNilArg0: true, 14157 reg: regInfo{ 14158 inputs: []inputInfo{ 14159 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14160 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14161 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14162 }, 14163 outputs: []outputInfo{ 14164 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14165 }, 14166 }, 14167 }, 14168 { 14169 name: "LoweredAtomicAnd", 14170 argLen: 3, 14171 faultOnNilArg0: true, 14172 asm: mips.AAND, 14173 reg: regInfo{ 14174 inputs: []inputInfo{ 14175 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14176 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14177 }, 14178 }, 14179 }, 14180 { 14181 name: "LoweredAtomicOr", 14182 argLen: 3, 14183 faultOnNilArg0: true, 14184 asm: mips.AOR, 14185 reg: regInfo{ 14186 inputs: []inputInfo{ 14187 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14188 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14189 }, 14190 }, 14191 }, 14192 { 14193 name: "LoweredZero", 14194 auxType: auxInt32, 14195 argLen: 3, 14196 faultOnNilArg0: true, 14197 reg: regInfo{ 14198 inputs: []inputInfo{ 14199 {0, 2}, // R1 14200 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14201 }, 14202 clobbers: 2, // R1 14203 }, 14204 }, 14205 { 14206 name: "LoweredMove", 14207 auxType: auxInt32, 14208 argLen: 4, 14209 faultOnNilArg0: true, 14210 faultOnNilArg1: true, 14211 reg: regInfo{ 14212 inputs: []inputInfo{ 14213 {0, 4}, // R2 14214 {1, 2}, // R1 14215 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14216 }, 14217 clobbers: 6, // R1 R2 14218 }, 14219 }, 14220 { 14221 name: "LoweredNilCheck", 14222 argLen: 2, 14223 nilCheck: true, 14224 faultOnNilArg0: true, 14225 reg: regInfo{ 14226 inputs: []inputInfo{ 14227 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14228 }, 14229 }, 14230 }, 14231 { 14232 name: "FPFlagTrue", 14233 argLen: 1, 14234 reg: regInfo{ 14235 outputs: []outputInfo{ 14236 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14237 }, 14238 }, 14239 }, 14240 { 14241 name: "FPFlagFalse", 14242 argLen: 1, 14243 reg: regInfo{ 14244 outputs: []outputInfo{ 14245 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14246 }, 14247 }, 14248 }, 14249 { 14250 name: "LoweredGetClosurePtr", 14251 argLen: 0, 14252 reg: regInfo{ 14253 outputs: []outputInfo{ 14254 {0, 4194304}, // R22 14255 }, 14256 }, 14257 }, 14258 { 14259 name: "MOVWconvert", 14260 argLen: 2, 14261 asm: mips.AMOVW, 14262 reg: regInfo{ 14263 inputs: []inputInfo{ 14264 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14265 }, 14266 outputs: []outputInfo{ 14267 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14268 }, 14269 }, 14270 }, 14271 14272 { 14273 name: "ADDV", 14274 argLen: 2, 14275 commutative: true, 14276 asm: mips.AADDVU, 14277 reg: regInfo{ 14278 inputs: []inputInfo{ 14279 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14280 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14281 }, 14282 outputs: []outputInfo{ 14283 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14284 }, 14285 }, 14286 }, 14287 { 14288 name: "ADDVconst", 14289 auxType: auxInt64, 14290 argLen: 1, 14291 asm: mips.AADDVU, 14292 reg: regInfo{ 14293 inputs: []inputInfo{ 14294 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 14295 }, 14296 outputs: []outputInfo{ 14297 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14298 }, 14299 }, 14300 }, 14301 { 14302 name: "SUBV", 14303 argLen: 2, 14304 asm: mips.ASUBVU, 14305 reg: regInfo{ 14306 inputs: []inputInfo{ 14307 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14308 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14309 }, 14310 outputs: []outputInfo{ 14311 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14312 }, 14313 }, 14314 }, 14315 { 14316 name: "SUBVconst", 14317 auxType: auxInt64, 14318 argLen: 1, 14319 asm: mips.ASUBVU, 14320 reg: regInfo{ 14321 inputs: []inputInfo{ 14322 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14323 }, 14324 outputs: []outputInfo{ 14325 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14326 }, 14327 }, 14328 }, 14329 { 14330 name: "MULV", 14331 argLen: 2, 14332 commutative: true, 14333 asm: mips.AMULV, 14334 reg: regInfo{ 14335 inputs: []inputInfo{ 14336 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14337 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14338 }, 14339 outputs: []outputInfo{ 14340 {0, 1152921504606846976}, // HI 14341 {1, 2305843009213693952}, // LO 14342 }, 14343 }, 14344 }, 14345 { 14346 name: "MULVU", 14347 argLen: 2, 14348 commutative: true, 14349 asm: mips.AMULVU, 14350 reg: regInfo{ 14351 inputs: []inputInfo{ 14352 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14353 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14354 }, 14355 outputs: []outputInfo{ 14356 {0, 1152921504606846976}, // HI 14357 {1, 2305843009213693952}, // LO 14358 }, 14359 }, 14360 }, 14361 { 14362 name: "DIVV", 14363 argLen: 2, 14364 asm: mips.ADIVV, 14365 reg: regInfo{ 14366 inputs: []inputInfo{ 14367 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14368 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14369 }, 14370 outputs: []outputInfo{ 14371 {0, 1152921504606846976}, // HI 14372 {1, 2305843009213693952}, // LO 14373 }, 14374 }, 14375 }, 14376 { 14377 name: "DIVVU", 14378 argLen: 2, 14379 asm: mips.ADIVVU, 14380 reg: regInfo{ 14381 inputs: []inputInfo{ 14382 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14383 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14384 }, 14385 outputs: []outputInfo{ 14386 {0, 1152921504606846976}, // HI 14387 {1, 2305843009213693952}, // LO 14388 }, 14389 }, 14390 }, 14391 { 14392 name: "ADDF", 14393 argLen: 2, 14394 commutative: true, 14395 asm: mips.AADDF, 14396 reg: regInfo{ 14397 inputs: []inputInfo{ 14398 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14399 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14400 }, 14401 outputs: []outputInfo{ 14402 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14403 }, 14404 }, 14405 }, 14406 { 14407 name: "ADDD", 14408 argLen: 2, 14409 commutative: true, 14410 asm: mips.AADDD, 14411 reg: regInfo{ 14412 inputs: []inputInfo{ 14413 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14414 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14415 }, 14416 outputs: []outputInfo{ 14417 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14418 }, 14419 }, 14420 }, 14421 { 14422 name: "SUBF", 14423 argLen: 2, 14424 asm: mips.ASUBF, 14425 reg: regInfo{ 14426 inputs: []inputInfo{ 14427 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14428 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14429 }, 14430 outputs: []outputInfo{ 14431 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14432 }, 14433 }, 14434 }, 14435 { 14436 name: "SUBD", 14437 argLen: 2, 14438 asm: mips.ASUBD, 14439 reg: regInfo{ 14440 inputs: []inputInfo{ 14441 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14442 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14443 }, 14444 outputs: []outputInfo{ 14445 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14446 }, 14447 }, 14448 }, 14449 { 14450 name: "MULF", 14451 argLen: 2, 14452 commutative: true, 14453 asm: mips.AMULF, 14454 reg: regInfo{ 14455 inputs: []inputInfo{ 14456 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14457 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14458 }, 14459 outputs: []outputInfo{ 14460 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14461 }, 14462 }, 14463 }, 14464 { 14465 name: "MULD", 14466 argLen: 2, 14467 commutative: true, 14468 asm: mips.AMULD, 14469 reg: regInfo{ 14470 inputs: []inputInfo{ 14471 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14472 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14473 }, 14474 outputs: []outputInfo{ 14475 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14476 }, 14477 }, 14478 }, 14479 { 14480 name: "DIVF", 14481 argLen: 2, 14482 asm: mips.ADIVF, 14483 reg: regInfo{ 14484 inputs: []inputInfo{ 14485 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14486 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14487 }, 14488 outputs: []outputInfo{ 14489 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14490 }, 14491 }, 14492 }, 14493 { 14494 name: "DIVD", 14495 argLen: 2, 14496 asm: mips.ADIVD, 14497 reg: regInfo{ 14498 inputs: []inputInfo{ 14499 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14500 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14501 }, 14502 outputs: []outputInfo{ 14503 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14504 }, 14505 }, 14506 }, 14507 { 14508 name: "AND", 14509 argLen: 2, 14510 commutative: true, 14511 asm: mips.AAND, 14512 reg: regInfo{ 14513 inputs: []inputInfo{ 14514 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14515 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14516 }, 14517 outputs: []outputInfo{ 14518 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14519 }, 14520 }, 14521 }, 14522 { 14523 name: "ANDconst", 14524 auxType: auxInt64, 14525 argLen: 1, 14526 asm: mips.AAND, 14527 reg: regInfo{ 14528 inputs: []inputInfo{ 14529 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14530 }, 14531 outputs: []outputInfo{ 14532 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14533 }, 14534 }, 14535 }, 14536 { 14537 name: "OR", 14538 argLen: 2, 14539 commutative: true, 14540 asm: mips.AOR, 14541 reg: regInfo{ 14542 inputs: []inputInfo{ 14543 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14544 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14545 }, 14546 outputs: []outputInfo{ 14547 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14548 }, 14549 }, 14550 }, 14551 { 14552 name: "ORconst", 14553 auxType: auxInt64, 14554 argLen: 1, 14555 asm: mips.AOR, 14556 reg: regInfo{ 14557 inputs: []inputInfo{ 14558 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14559 }, 14560 outputs: []outputInfo{ 14561 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14562 }, 14563 }, 14564 }, 14565 { 14566 name: "XOR", 14567 argLen: 2, 14568 commutative: true, 14569 asm: mips.AXOR, 14570 reg: regInfo{ 14571 inputs: []inputInfo{ 14572 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14573 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14574 }, 14575 outputs: []outputInfo{ 14576 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14577 }, 14578 }, 14579 }, 14580 { 14581 name: "XORconst", 14582 auxType: auxInt64, 14583 argLen: 1, 14584 asm: mips.AXOR, 14585 reg: regInfo{ 14586 inputs: []inputInfo{ 14587 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14588 }, 14589 outputs: []outputInfo{ 14590 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14591 }, 14592 }, 14593 }, 14594 { 14595 name: "NOR", 14596 argLen: 2, 14597 commutative: true, 14598 asm: mips.ANOR, 14599 reg: regInfo{ 14600 inputs: []inputInfo{ 14601 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14602 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14603 }, 14604 outputs: []outputInfo{ 14605 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14606 }, 14607 }, 14608 }, 14609 { 14610 name: "NORconst", 14611 auxType: auxInt64, 14612 argLen: 1, 14613 asm: mips.ANOR, 14614 reg: regInfo{ 14615 inputs: []inputInfo{ 14616 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14617 }, 14618 outputs: []outputInfo{ 14619 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14620 }, 14621 }, 14622 }, 14623 { 14624 name: "NEGV", 14625 argLen: 1, 14626 reg: regInfo{ 14627 inputs: []inputInfo{ 14628 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14629 }, 14630 outputs: []outputInfo{ 14631 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14632 }, 14633 }, 14634 }, 14635 { 14636 name: "NEGF", 14637 argLen: 1, 14638 asm: mips.ANEGF, 14639 reg: regInfo{ 14640 inputs: []inputInfo{ 14641 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14642 }, 14643 outputs: []outputInfo{ 14644 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14645 }, 14646 }, 14647 }, 14648 { 14649 name: "NEGD", 14650 argLen: 1, 14651 asm: mips.ANEGD, 14652 reg: regInfo{ 14653 inputs: []inputInfo{ 14654 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14655 }, 14656 outputs: []outputInfo{ 14657 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14658 }, 14659 }, 14660 }, 14661 { 14662 name: "SLLV", 14663 argLen: 2, 14664 asm: mips.ASLLV, 14665 reg: regInfo{ 14666 inputs: []inputInfo{ 14667 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14668 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14669 }, 14670 outputs: []outputInfo{ 14671 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14672 }, 14673 }, 14674 }, 14675 { 14676 name: "SLLVconst", 14677 auxType: auxInt64, 14678 argLen: 1, 14679 asm: mips.ASLLV, 14680 reg: regInfo{ 14681 inputs: []inputInfo{ 14682 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14683 }, 14684 outputs: []outputInfo{ 14685 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14686 }, 14687 }, 14688 }, 14689 { 14690 name: "SRLV", 14691 argLen: 2, 14692 asm: mips.ASRLV, 14693 reg: regInfo{ 14694 inputs: []inputInfo{ 14695 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14696 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14697 }, 14698 outputs: []outputInfo{ 14699 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14700 }, 14701 }, 14702 }, 14703 { 14704 name: "SRLVconst", 14705 auxType: auxInt64, 14706 argLen: 1, 14707 asm: mips.ASRLV, 14708 reg: regInfo{ 14709 inputs: []inputInfo{ 14710 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14711 }, 14712 outputs: []outputInfo{ 14713 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14714 }, 14715 }, 14716 }, 14717 { 14718 name: "SRAV", 14719 argLen: 2, 14720 asm: mips.ASRAV, 14721 reg: regInfo{ 14722 inputs: []inputInfo{ 14723 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14724 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14725 }, 14726 outputs: []outputInfo{ 14727 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14728 }, 14729 }, 14730 }, 14731 { 14732 name: "SRAVconst", 14733 auxType: auxInt64, 14734 argLen: 1, 14735 asm: mips.ASRAV, 14736 reg: regInfo{ 14737 inputs: []inputInfo{ 14738 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14739 }, 14740 outputs: []outputInfo{ 14741 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14742 }, 14743 }, 14744 }, 14745 { 14746 name: "SGT", 14747 argLen: 2, 14748 asm: mips.ASGT, 14749 reg: regInfo{ 14750 inputs: []inputInfo{ 14751 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14752 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14753 }, 14754 outputs: []outputInfo{ 14755 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14756 }, 14757 }, 14758 }, 14759 { 14760 name: "SGTconst", 14761 auxType: auxInt64, 14762 argLen: 1, 14763 asm: mips.ASGT, 14764 reg: regInfo{ 14765 inputs: []inputInfo{ 14766 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14767 }, 14768 outputs: []outputInfo{ 14769 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14770 }, 14771 }, 14772 }, 14773 { 14774 name: "SGTU", 14775 argLen: 2, 14776 asm: mips.ASGTU, 14777 reg: regInfo{ 14778 inputs: []inputInfo{ 14779 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14780 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14781 }, 14782 outputs: []outputInfo{ 14783 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14784 }, 14785 }, 14786 }, 14787 { 14788 name: "SGTUconst", 14789 auxType: auxInt64, 14790 argLen: 1, 14791 asm: mips.ASGTU, 14792 reg: regInfo{ 14793 inputs: []inputInfo{ 14794 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14795 }, 14796 outputs: []outputInfo{ 14797 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14798 }, 14799 }, 14800 }, 14801 { 14802 name: "CMPEQF", 14803 argLen: 2, 14804 asm: mips.ACMPEQF, 14805 reg: regInfo{ 14806 inputs: []inputInfo{ 14807 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14808 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14809 }, 14810 }, 14811 }, 14812 { 14813 name: "CMPEQD", 14814 argLen: 2, 14815 asm: mips.ACMPEQD, 14816 reg: regInfo{ 14817 inputs: []inputInfo{ 14818 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14819 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14820 }, 14821 }, 14822 }, 14823 { 14824 name: "CMPGEF", 14825 argLen: 2, 14826 asm: mips.ACMPGEF, 14827 reg: regInfo{ 14828 inputs: []inputInfo{ 14829 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14830 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14831 }, 14832 }, 14833 }, 14834 { 14835 name: "CMPGED", 14836 argLen: 2, 14837 asm: mips.ACMPGED, 14838 reg: regInfo{ 14839 inputs: []inputInfo{ 14840 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14841 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14842 }, 14843 }, 14844 }, 14845 { 14846 name: "CMPGTF", 14847 argLen: 2, 14848 asm: mips.ACMPGTF, 14849 reg: regInfo{ 14850 inputs: []inputInfo{ 14851 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14852 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14853 }, 14854 }, 14855 }, 14856 { 14857 name: "CMPGTD", 14858 argLen: 2, 14859 asm: mips.ACMPGTD, 14860 reg: regInfo{ 14861 inputs: []inputInfo{ 14862 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14863 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14864 }, 14865 }, 14866 }, 14867 { 14868 name: "MOVVconst", 14869 auxType: auxInt64, 14870 argLen: 0, 14871 rematerializeable: true, 14872 asm: mips.AMOVV, 14873 reg: regInfo{ 14874 outputs: []outputInfo{ 14875 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14876 }, 14877 }, 14878 }, 14879 { 14880 name: "MOVFconst", 14881 auxType: auxFloat64, 14882 argLen: 0, 14883 rematerializeable: true, 14884 asm: mips.AMOVF, 14885 reg: regInfo{ 14886 outputs: []outputInfo{ 14887 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14888 }, 14889 }, 14890 }, 14891 { 14892 name: "MOVDconst", 14893 auxType: auxFloat64, 14894 argLen: 0, 14895 rematerializeable: true, 14896 asm: mips.AMOVD, 14897 reg: regInfo{ 14898 outputs: []outputInfo{ 14899 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14900 }, 14901 }, 14902 }, 14903 { 14904 name: "MOVVaddr", 14905 auxType: auxSymOff, 14906 argLen: 1, 14907 rematerializeable: true, 14908 asm: mips.AMOVV, 14909 reg: regInfo{ 14910 inputs: []inputInfo{ 14911 {0, 4611686018460942336}, // SP SB 14912 }, 14913 outputs: []outputInfo{ 14914 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14915 }, 14916 }, 14917 }, 14918 { 14919 name: "MOVBload", 14920 auxType: auxSymOff, 14921 argLen: 2, 14922 faultOnNilArg0: true, 14923 asm: mips.AMOVB, 14924 reg: regInfo{ 14925 inputs: []inputInfo{ 14926 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14927 }, 14928 outputs: []outputInfo{ 14929 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14930 }, 14931 }, 14932 }, 14933 { 14934 name: "MOVBUload", 14935 auxType: auxSymOff, 14936 argLen: 2, 14937 faultOnNilArg0: true, 14938 asm: mips.AMOVBU, 14939 reg: regInfo{ 14940 inputs: []inputInfo{ 14941 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14942 }, 14943 outputs: []outputInfo{ 14944 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14945 }, 14946 }, 14947 }, 14948 { 14949 name: "MOVHload", 14950 auxType: auxSymOff, 14951 argLen: 2, 14952 faultOnNilArg0: true, 14953 asm: mips.AMOVH, 14954 reg: regInfo{ 14955 inputs: []inputInfo{ 14956 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14957 }, 14958 outputs: []outputInfo{ 14959 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14960 }, 14961 }, 14962 }, 14963 { 14964 name: "MOVHUload", 14965 auxType: auxSymOff, 14966 argLen: 2, 14967 faultOnNilArg0: true, 14968 asm: mips.AMOVHU, 14969 reg: regInfo{ 14970 inputs: []inputInfo{ 14971 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14972 }, 14973 outputs: []outputInfo{ 14974 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14975 }, 14976 }, 14977 }, 14978 { 14979 name: "MOVWload", 14980 auxType: auxSymOff, 14981 argLen: 2, 14982 faultOnNilArg0: true, 14983 asm: mips.AMOVW, 14984 reg: regInfo{ 14985 inputs: []inputInfo{ 14986 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14987 }, 14988 outputs: []outputInfo{ 14989 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14990 }, 14991 }, 14992 }, 14993 { 14994 name: "MOVWUload", 14995 auxType: auxSymOff, 14996 argLen: 2, 14997 faultOnNilArg0: true, 14998 asm: mips.AMOVWU, 14999 reg: regInfo{ 15000 inputs: []inputInfo{ 15001 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15002 }, 15003 outputs: []outputInfo{ 15004 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15005 }, 15006 }, 15007 }, 15008 { 15009 name: "MOVVload", 15010 auxType: auxSymOff, 15011 argLen: 2, 15012 faultOnNilArg0: true, 15013 asm: mips.AMOVV, 15014 reg: regInfo{ 15015 inputs: []inputInfo{ 15016 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15017 }, 15018 outputs: []outputInfo{ 15019 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15020 }, 15021 }, 15022 }, 15023 { 15024 name: "MOVFload", 15025 auxType: auxSymOff, 15026 argLen: 2, 15027 faultOnNilArg0: true, 15028 asm: mips.AMOVF, 15029 reg: regInfo{ 15030 inputs: []inputInfo{ 15031 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15032 }, 15033 outputs: []outputInfo{ 15034 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15035 }, 15036 }, 15037 }, 15038 { 15039 name: "MOVDload", 15040 auxType: auxSymOff, 15041 argLen: 2, 15042 faultOnNilArg0: true, 15043 asm: mips.AMOVD, 15044 reg: regInfo{ 15045 inputs: []inputInfo{ 15046 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15047 }, 15048 outputs: []outputInfo{ 15049 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15050 }, 15051 }, 15052 }, 15053 { 15054 name: "MOVBstore", 15055 auxType: auxSymOff, 15056 argLen: 3, 15057 faultOnNilArg0: true, 15058 asm: mips.AMOVB, 15059 reg: regInfo{ 15060 inputs: []inputInfo{ 15061 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15062 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15063 }, 15064 }, 15065 }, 15066 { 15067 name: "MOVHstore", 15068 auxType: auxSymOff, 15069 argLen: 3, 15070 faultOnNilArg0: true, 15071 asm: mips.AMOVH, 15072 reg: regInfo{ 15073 inputs: []inputInfo{ 15074 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15075 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15076 }, 15077 }, 15078 }, 15079 { 15080 name: "MOVWstore", 15081 auxType: auxSymOff, 15082 argLen: 3, 15083 faultOnNilArg0: true, 15084 asm: mips.AMOVW, 15085 reg: regInfo{ 15086 inputs: []inputInfo{ 15087 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15088 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15089 }, 15090 }, 15091 }, 15092 { 15093 name: "MOVVstore", 15094 auxType: auxSymOff, 15095 argLen: 3, 15096 faultOnNilArg0: true, 15097 asm: mips.AMOVV, 15098 reg: regInfo{ 15099 inputs: []inputInfo{ 15100 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15101 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15102 }, 15103 }, 15104 }, 15105 { 15106 name: "MOVFstore", 15107 auxType: auxSymOff, 15108 argLen: 3, 15109 faultOnNilArg0: true, 15110 asm: mips.AMOVF, 15111 reg: regInfo{ 15112 inputs: []inputInfo{ 15113 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15114 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15115 }, 15116 }, 15117 }, 15118 { 15119 name: "MOVDstore", 15120 auxType: auxSymOff, 15121 argLen: 3, 15122 faultOnNilArg0: true, 15123 asm: mips.AMOVD, 15124 reg: regInfo{ 15125 inputs: []inputInfo{ 15126 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15127 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15128 }, 15129 }, 15130 }, 15131 { 15132 name: "MOVBstorezero", 15133 auxType: auxSymOff, 15134 argLen: 2, 15135 faultOnNilArg0: true, 15136 asm: mips.AMOVB, 15137 reg: regInfo{ 15138 inputs: []inputInfo{ 15139 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15140 }, 15141 }, 15142 }, 15143 { 15144 name: "MOVHstorezero", 15145 auxType: auxSymOff, 15146 argLen: 2, 15147 faultOnNilArg0: true, 15148 asm: mips.AMOVH, 15149 reg: regInfo{ 15150 inputs: []inputInfo{ 15151 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15152 }, 15153 }, 15154 }, 15155 { 15156 name: "MOVWstorezero", 15157 auxType: auxSymOff, 15158 argLen: 2, 15159 faultOnNilArg0: true, 15160 asm: mips.AMOVW, 15161 reg: regInfo{ 15162 inputs: []inputInfo{ 15163 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15164 }, 15165 }, 15166 }, 15167 { 15168 name: "MOVVstorezero", 15169 auxType: auxSymOff, 15170 argLen: 2, 15171 faultOnNilArg0: true, 15172 asm: mips.AMOVV, 15173 reg: regInfo{ 15174 inputs: []inputInfo{ 15175 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15176 }, 15177 }, 15178 }, 15179 { 15180 name: "MOVBreg", 15181 argLen: 1, 15182 asm: mips.AMOVB, 15183 reg: regInfo{ 15184 inputs: []inputInfo{ 15185 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15186 }, 15187 outputs: []outputInfo{ 15188 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15189 }, 15190 }, 15191 }, 15192 { 15193 name: "MOVBUreg", 15194 argLen: 1, 15195 asm: mips.AMOVBU, 15196 reg: regInfo{ 15197 inputs: []inputInfo{ 15198 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15199 }, 15200 outputs: []outputInfo{ 15201 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15202 }, 15203 }, 15204 }, 15205 { 15206 name: "MOVHreg", 15207 argLen: 1, 15208 asm: mips.AMOVH, 15209 reg: regInfo{ 15210 inputs: []inputInfo{ 15211 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15212 }, 15213 outputs: []outputInfo{ 15214 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15215 }, 15216 }, 15217 }, 15218 { 15219 name: "MOVHUreg", 15220 argLen: 1, 15221 asm: mips.AMOVHU, 15222 reg: regInfo{ 15223 inputs: []inputInfo{ 15224 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15225 }, 15226 outputs: []outputInfo{ 15227 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15228 }, 15229 }, 15230 }, 15231 { 15232 name: "MOVWreg", 15233 argLen: 1, 15234 asm: mips.AMOVW, 15235 reg: regInfo{ 15236 inputs: []inputInfo{ 15237 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15238 }, 15239 outputs: []outputInfo{ 15240 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15241 }, 15242 }, 15243 }, 15244 { 15245 name: "MOVWUreg", 15246 argLen: 1, 15247 asm: mips.AMOVWU, 15248 reg: regInfo{ 15249 inputs: []inputInfo{ 15250 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15251 }, 15252 outputs: []outputInfo{ 15253 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15254 }, 15255 }, 15256 }, 15257 { 15258 name: "MOVVreg", 15259 argLen: 1, 15260 asm: mips.AMOVV, 15261 reg: regInfo{ 15262 inputs: []inputInfo{ 15263 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15264 }, 15265 outputs: []outputInfo{ 15266 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15267 }, 15268 }, 15269 }, 15270 { 15271 name: "MOVVnop", 15272 argLen: 1, 15273 resultInArg0: true, 15274 reg: regInfo{ 15275 inputs: []inputInfo{ 15276 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15277 }, 15278 outputs: []outputInfo{ 15279 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15280 }, 15281 }, 15282 }, 15283 { 15284 name: "MOVWF", 15285 argLen: 1, 15286 asm: mips.AMOVWF, 15287 reg: regInfo{ 15288 inputs: []inputInfo{ 15289 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15290 }, 15291 outputs: []outputInfo{ 15292 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15293 }, 15294 }, 15295 }, 15296 { 15297 name: "MOVWD", 15298 argLen: 1, 15299 asm: mips.AMOVWD, 15300 reg: regInfo{ 15301 inputs: []inputInfo{ 15302 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15303 }, 15304 outputs: []outputInfo{ 15305 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15306 }, 15307 }, 15308 }, 15309 { 15310 name: "MOVVF", 15311 argLen: 1, 15312 asm: mips.AMOVVF, 15313 reg: regInfo{ 15314 inputs: []inputInfo{ 15315 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15316 }, 15317 outputs: []outputInfo{ 15318 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15319 }, 15320 }, 15321 }, 15322 { 15323 name: "MOVVD", 15324 argLen: 1, 15325 asm: mips.AMOVVD, 15326 reg: regInfo{ 15327 inputs: []inputInfo{ 15328 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15329 }, 15330 outputs: []outputInfo{ 15331 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15332 }, 15333 }, 15334 }, 15335 { 15336 name: "TRUNCFW", 15337 argLen: 1, 15338 asm: mips.ATRUNCFW, 15339 reg: regInfo{ 15340 inputs: []inputInfo{ 15341 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15342 }, 15343 outputs: []outputInfo{ 15344 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15345 }, 15346 }, 15347 }, 15348 { 15349 name: "TRUNCDW", 15350 argLen: 1, 15351 asm: mips.ATRUNCDW, 15352 reg: regInfo{ 15353 inputs: []inputInfo{ 15354 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15355 }, 15356 outputs: []outputInfo{ 15357 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15358 }, 15359 }, 15360 }, 15361 { 15362 name: "TRUNCFV", 15363 argLen: 1, 15364 asm: mips.ATRUNCFV, 15365 reg: regInfo{ 15366 inputs: []inputInfo{ 15367 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15368 }, 15369 outputs: []outputInfo{ 15370 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15371 }, 15372 }, 15373 }, 15374 { 15375 name: "TRUNCDV", 15376 argLen: 1, 15377 asm: mips.ATRUNCDV, 15378 reg: regInfo{ 15379 inputs: []inputInfo{ 15380 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15381 }, 15382 outputs: []outputInfo{ 15383 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15384 }, 15385 }, 15386 }, 15387 { 15388 name: "MOVFD", 15389 argLen: 1, 15390 asm: mips.AMOVFD, 15391 reg: regInfo{ 15392 inputs: []inputInfo{ 15393 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15394 }, 15395 outputs: []outputInfo{ 15396 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15397 }, 15398 }, 15399 }, 15400 { 15401 name: "MOVDF", 15402 argLen: 1, 15403 asm: mips.AMOVDF, 15404 reg: regInfo{ 15405 inputs: []inputInfo{ 15406 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15407 }, 15408 outputs: []outputInfo{ 15409 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15410 }, 15411 }, 15412 }, 15413 { 15414 name: "CALLstatic", 15415 auxType: auxSymOff, 15416 argLen: 1, 15417 clobberFlags: true, 15418 call: true, 15419 reg: regInfo{ 15420 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15421 }, 15422 }, 15423 { 15424 name: "CALLclosure", 15425 auxType: auxInt64, 15426 argLen: 3, 15427 clobberFlags: true, 15428 call: true, 15429 reg: regInfo{ 15430 inputs: []inputInfo{ 15431 {1, 4194304}, // R22 15432 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 15433 }, 15434 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15435 }, 15436 }, 15437 { 15438 name: "CALLdefer", 15439 auxType: auxInt64, 15440 argLen: 1, 15441 clobberFlags: true, 15442 call: true, 15443 reg: regInfo{ 15444 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15445 }, 15446 }, 15447 { 15448 name: "CALLgo", 15449 auxType: auxInt64, 15450 argLen: 1, 15451 clobberFlags: true, 15452 call: true, 15453 reg: regInfo{ 15454 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15455 }, 15456 }, 15457 { 15458 name: "CALLinter", 15459 auxType: auxInt64, 15460 argLen: 2, 15461 clobberFlags: true, 15462 call: true, 15463 reg: regInfo{ 15464 inputs: []inputInfo{ 15465 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15466 }, 15467 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15468 }, 15469 }, 15470 { 15471 name: "DUFFZERO", 15472 auxType: auxInt64, 15473 argLen: 2, 15474 faultOnNilArg0: true, 15475 reg: regInfo{ 15476 inputs: []inputInfo{ 15477 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15478 }, 15479 clobbers: 134217730, // R1 R31 15480 }, 15481 }, 15482 { 15483 name: "LoweredZero", 15484 auxType: auxInt64, 15485 argLen: 3, 15486 clobberFlags: true, 15487 faultOnNilArg0: true, 15488 reg: regInfo{ 15489 inputs: []inputInfo{ 15490 {0, 2}, // R1 15491 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15492 }, 15493 clobbers: 2, // R1 15494 }, 15495 }, 15496 { 15497 name: "LoweredMove", 15498 auxType: auxInt64, 15499 argLen: 4, 15500 clobberFlags: true, 15501 faultOnNilArg0: true, 15502 faultOnNilArg1: true, 15503 reg: regInfo{ 15504 inputs: []inputInfo{ 15505 {0, 4}, // R2 15506 {1, 2}, // R1 15507 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15508 }, 15509 clobbers: 6, // R1 R2 15510 }, 15511 }, 15512 { 15513 name: "LoweredNilCheck", 15514 argLen: 2, 15515 nilCheck: true, 15516 faultOnNilArg0: true, 15517 reg: regInfo{ 15518 inputs: []inputInfo{ 15519 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15520 }, 15521 }, 15522 }, 15523 { 15524 name: "FPFlagTrue", 15525 argLen: 1, 15526 reg: regInfo{ 15527 outputs: []outputInfo{ 15528 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15529 }, 15530 }, 15531 }, 15532 { 15533 name: "FPFlagFalse", 15534 argLen: 1, 15535 reg: regInfo{ 15536 outputs: []outputInfo{ 15537 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15538 }, 15539 }, 15540 }, 15541 { 15542 name: "LoweredGetClosurePtr", 15543 argLen: 0, 15544 reg: regInfo{ 15545 outputs: []outputInfo{ 15546 {0, 4194304}, // R22 15547 }, 15548 }, 15549 }, 15550 { 15551 name: "MOVVconvert", 15552 argLen: 2, 15553 asm: mips.AMOVV, 15554 reg: regInfo{ 15555 inputs: []inputInfo{ 15556 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15557 }, 15558 outputs: []outputInfo{ 15559 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15560 }, 15561 }, 15562 }, 15563 15564 { 15565 name: "ADD", 15566 argLen: 2, 15567 commutative: true, 15568 asm: ppc64.AADD, 15569 reg: regInfo{ 15570 inputs: []inputInfo{ 15571 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15572 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15573 }, 15574 outputs: []outputInfo{ 15575 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15576 }, 15577 }, 15578 }, 15579 { 15580 name: "ADDconst", 15581 auxType: auxSymOff, 15582 argLen: 1, 15583 asm: ppc64.AADD, 15584 reg: regInfo{ 15585 inputs: []inputInfo{ 15586 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15587 }, 15588 outputs: []outputInfo{ 15589 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15590 }, 15591 }, 15592 }, 15593 { 15594 name: "FADD", 15595 argLen: 2, 15596 commutative: true, 15597 asm: ppc64.AFADD, 15598 reg: regInfo{ 15599 inputs: []inputInfo{ 15600 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15601 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15602 }, 15603 outputs: []outputInfo{ 15604 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15605 }, 15606 }, 15607 }, 15608 { 15609 name: "FADDS", 15610 argLen: 2, 15611 commutative: true, 15612 asm: ppc64.AFADDS, 15613 reg: regInfo{ 15614 inputs: []inputInfo{ 15615 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15616 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15617 }, 15618 outputs: []outputInfo{ 15619 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15620 }, 15621 }, 15622 }, 15623 { 15624 name: "SUB", 15625 argLen: 2, 15626 asm: ppc64.ASUB, 15627 reg: regInfo{ 15628 inputs: []inputInfo{ 15629 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15630 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15631 }, 15632 outputs: []outputInfo{ 15633 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15634 }, 15635 }, 15636 }, 15637 { 15638 name: "FSUB", 15639 argLen: 2, 15640 asm: ppc64.AFSUB, 15641 reg: regInfo{ 15642 inputs: []inputInfo{ 15643 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15644 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15645 }, 15646 outputs: []outputInfo{ 15647 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15648 }, 15649 }, 15650 }, 15651 { 15652 name: "FSUBS", 15653 argLen: 2, 15654 asm: ppc64.AFSUBS, 15655 reg: regInfo{ 15656 inputs: []inputInfo{ 15657 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15658 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15659 }, 15660 outputs: []outputInfo{ 15661 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15662 }, 15663 }, 15664 }, 15665 { 15666 name: "MULLD", 15667 argLen: 2, 15668 commutative: true, 15669 asm: ppc64.AMULLD, 15670 reg: regInfo{ 15671 inputs: []inputInfo{ 15672 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15673 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15674 }, 15675 outputs: []outputInfo{ 15676 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15677 }, 15678 }, 15679 }, 15680 { 15681 name: "MULLW", 15682 argLen: 2, 15683 commutative: true, 15684 asm: ppc64.AMULLW, 15685 reg: regInfo{ 15686 inputs: []inputInfo{ 15687 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15688 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15689 }, 15690 outputs: []outputInfo{ 15691 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15692 }, 15693 }, 15694 }, 15695 { 15696 name: "MULHD", 15697 argLen: 2, 15698 commutative: true, 15699 asm: ppc64.AMULHD, 15700 reg: regInfo{ 15701 inputs: []inputInfo{ 15702 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15703 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15704 }, 15705 outputs: []outputInfo{ 15706 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15707 }, 15708 }, 15709 }, 15710 { 15711 name: "MULHW", 15712 argLen: 2, 15713 commutative: true, 15714 asm: ppc64.AMULHW, 15715 reg: regInfo{ 15716 inputs: []inputInfo{ 15717 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15718 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15719 }, 15720 outputs: []outputInfo{ 15721 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15722 }, 15723 }, 15724 }, 15725 { 15726 name: "MULHDU", 15727 argLen: 2, 15728 commutative: true, 15729 asm: ppc64.AMULHDU, 15730 reg: regInfo{ 15731 inputs: []inputInfo{ 15732 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15733 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15734 }, 15735 outputs: []outputInfo{ 15736 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15737 }, 15738 }, 15739 }, 15740 { 15741 name: "MULHWU", 15742 argLen: 2, 15743 commutative: true, 15744 asm: ppc64.AMULHWU, 15745 reg: regInfo{ 15746 inputs: []inputInfo{ 15747 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15748 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15749 }, 15750 outputs: []outputInfo{ 15751 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15752 }, 15753 }, 15754 }, 15755 { 15756 name: "FMUL", 15757 argLen: 2, 15758 commutative: true, 15759 asm: ppc64.AFMUL, 15760 reg: regInfo{ 15761 inputs: []inputInfo{ 15762 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15763 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15764 }, 15765 outputs: []outputInfo{ 15766 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15767 }, 15768 }, 15769 }, 15770 { 15771 name: "FMULS", 15772 argLen: 2, 15773 commutative: true, 15774 asm: ppc64.AFMULS, 15775 reg: regInfo{ 15776 inputs: []inputInfo{ 15777 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15778 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15779 }, 15780 outputs: []outputInfo{ 15781 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15782 }, 15783 }, 15784 }, 15785 { 15786 name: "SRAD", 15787 argLen: 2, 15788 asm: ppc64.ASRAD, 15789 reg: regInfo{ 15790 inputs: []inputInfo{ 15791 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15792 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15793 }, 15794 outputs: []outputInfo{ 15795 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15796 }, 15797 }, 15798 }, 15799 { 15800 name: "SRAW", 15801 argLen: 2, 15802 asm: ppc64.ASRAW, 15803 reg: regInfo{ 15804 inputs: []inputInfo{ 15805 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15806 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15807 }, 15808 outputs: []outputInfo{ 15809 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15810 }, 15811 }, 15812 }, 15813 { 15814 name: "SRD", 15815 argLen: 2, 15816 asm: ppc64.ASRD, 15817 reg: regInfo{ 15818 inputs: []inputInfo{ 15819 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15820 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15821 }, 15822 outputs: []outputInfo{ 15823 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15824 }, 15825 }, 15826 }, 15827 { 15828 name: "SRW", 15829 argLen: 2, 15830 asm: ppc64.ASRW, 15831 reg: regInfo{ 15832 inputs: []inputInfo{ 15833 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15834 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15835 }, 15836 outputs: []outputInfo{ 15837 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15838 }, 15839 }, 15840 }, 15841 { 15842 name: "SLD", 15843 argLen: 2, 15844 asm: ppc64.ASLD, 15845 reg: regInfo{ 15846 inputs: []inputInfo{ 15847 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15848 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15849 }, 15850 outputs: []outputInfo{ 15851 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15852 }, 15853 }, 15854 }, 15855 { 15856 name: "SLW", 15857 argLen: 2, 15858 asm: ppc64.ASLW, 15859 reg: regInfo{ 15860 inputs: []inputInfo{ 15861 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15862 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15863 }, 15864 outputs: []outputInfo{ 15865 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15866 }, 15867 }, 15868 }, 15869 { 15870 name: "ADDconstForCarry", 15871 auxType: auxInt16, 15872 argLen: 1, 15873 asm: ppc64.AADDC, 15874 reg: regInfo{ 15875 inputs: []inputInfo{ 15876 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15877 }, 15878 clobbers: 2147483648, // R31 15879 }, 15880 }, 15881 { 15882 name: "MaskIfNotCarry", 15883 argLen: 1, 15884 asm: ppc64.AADDME, 15885 reg: regInfo{ 15886 outputs: []outputInfo{ 15887 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15888 }, 15889 }, 15890 }, 15891 { 15892 name: "SRADconst", 15893 auxType: auxInt64, 15894 argLen: 1, 15895 asm: ppc64.ASRAD, 15896 reg: regInfo{ 15897 inputs: []inputInfo{ 15898 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15899 }, 15900 outputs: []outputInfo{ 15901 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15902 }, 15903 }, 15904 }, 15905 { 15906 name: "SRAWconst", 15907 auxType: auxInt64, 15908 argLen: 1, 15909 asm: ppc64.ASRAW, 15910 reg: regInfo{ 15911 inputs: []inputInfo{ 15912 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15913 }, 15914 outputs: []outputInfo{ 15915 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15916 }, 15917 }, 15918 }, 15919 { 15920 name: "SRDconst", 15921 auxType: auxInt64, 15922 argLen: 1, 15923 asm: ppc64.ASRD, 15924 reg: regInfo{ 15925 inputs: []inputInfo{ 15926 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15927 }, 15928 outputs: []outputInfo{ 15929 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15930 }, 15931 }, 15932 }, 15933 { 15934 name: "SRWconst", 15935 auxType: auxInt64, 15936 argLen: 1, 15937 asm: ppc64.ASRW, 15938 reg: regInfo{ 15939 inputs: []inputInfo{ 15940 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15941 }, 15942 outputs: []outputInfo{ 15943 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15944 }, 15945 }, 15946 }, 15947 { 15948 name: "SLDconst", 15949 auxType: auxInt64, 15950 argLen: 1, 15951 asm: ppc64.ASLD, 15952 reg: regInfo{ 15953 inputs: []inputInfo{ 15954 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15955 }, 15956 outputs: []outputInfo{ 15957 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15958 }, 15959 }, 15960 }, 15961 { 15962 name: "SLWconst", 15963 auxType: auxInt64, 15964 argLen: 1, 15965 asm: ppc64.ASLW, 15966 reg: regInfo{ 15967 inputs: []inputInfo{ 15968 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15969 }, 15970 outputs: []outputInfo{ 15971 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15972 }, 15973 }, 15974 }, 15975 { 15976 name: "FDIV", 15977 argLen: 2, 15978 asm: ppc64.AFDIV, 15979 reg: regInfo{ 15980 inputs: []inputInfo{ 15981 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15982 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15983 }, 15984 outputs: []outputInfo{ 15985 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15986 }, 15987 }, 15988 }, 15989 { 15990 name: "FDIVS", 15991 argLen: 2, 15992 asm: ppc64.AFDIVS, 15993 reg: regInfo{ 15994 inputs: []inputInfo{ 15995 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15996 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15997 }, 15998 outputs: []outputInfo{ 15999 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16000 }, 16001 }, 16002 }, 16003 { 16004 name: "DIVD", 16005 argLen: 2, 16006 asm: ppc64.ADIVD, 16007 reg: regInfo{ 16008 inputs: []inputInfo{ 16009 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16010 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16011 }, 16012 outputs: []outputInfo{ 16013 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16014 }, 16015 }, 16016 }, 16017 { 16018 name: "DIVW", 16019 argLen: 2, 16020 asm: ppc64.ADIVW, 16021 reg: regInfo{ 16022 inputs: []inputInfo{ 16023 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16024 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16025 }, 16026 outputs: []outputInfo{ 16027 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16028 }, 16029 }, 16030 }, 16031 { 16032 name: "DIVDU", 16033 argLen: 2, 16034 asm: ppc64.ADIVDU, 16035 reg: regInfo{ 16036 inputs: []inputInfo{ 16037 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16038 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16039 }, 16040 outputs: []outputInfo{ 16041 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16042 }, 16043 }, 16044 }, 16045 { 16046 name: "DIVWU", 16047 argLen: 2, 16048 asm: ppc64.ADIVWU, 16049 reg: regInfo{ 16050 inputs: []inputInfo{ 16051 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16052 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16053 }, 16054 outputs: []outputInfo{ 16055 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16056 }, 16057 }, 16058 }, 16059 { 16060 name: "FCTIDZ", 16061 argLen: 1, 16062 asm: ppc64.AFCTIDZ, 16063 reg: regInfo{ 16064 inputs: []inputInfo{ 16065 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16066 }, 16067 outputs: []outputInfo{ 16068 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16069 }, 16070 }, 16071 }, 16072 { 16073 name: "FCTIWZ", 16074 argLen: 1, 16075 asm: ppc64.AFCTIWZ, 16076 reg: regInfo{ 16077 inputs: []inputInfo{ 16078 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16079 }, 16080 outputs: []outputInfo{ 16081 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16082 }, 16083 }, 16084 }, 16085 { 16086 name: "FCFID", 16087 argLen: 1, 16088 asm: ppc64.AFCFID, 16089 reg: regInfo{ 16090 inputs: []inputInfo{ 16091 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16092 }, 16093 outputs: []outputInfo{ 16094 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16095 }, 16096 }, 16097 }, 16098 { 16099 name: "FRSP", 16100 argLen: 1, 16101 asm: ppc64.AFRSP, 16102 reg: regInfo{ 16103 inputs: []inputInfo{ 16104 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16105 }, 16106 outputs: []outputInfo{ 16107 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16108 }, 16109 }, 16110 }, 16111 { 16112 name: "Xf2i64", 16113 argLen: 1, 16114 usesScratch: true, 16115 reg: regInfo{ 16116 inputs: []inputInfo{ 16117 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16118 }, 16119 outputs: []outputInfo{ 16120 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16121 }, 16122 }, 16123 }, 16124 { 16125 name: "Xi2f64", 16126 argLen: 1, 16127 usesScratch: true, 16128 reg: regInfo{ 16129 inputs: []inputInfo{ 16130 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16131 }, 16132 outputs: []outputInfo{ 16133 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16134 }, 16135 }, 16136 }, 16137 { 16138 name: "AND", 16139 argLen: 2, 16140 commutative: true, 16141 asm: ppc64.AAND, 16142 reg: regInfo{ 16143 inputs: []inputInfo{ 16144 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16145 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16146 }, 16147 outputs: []outputInfo{ 16148 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16149 }, 16150 }, 16151 }, 16152 { 16153 name: "ANDN", 16154 argLen: 2, 16155 asm: ppc64.AANDN, 16156 reg: regInfo{ 16157 inputs: []inputInfo{ 16158 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16159 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16160 }, 16161 outputs: []outputInfo{ 16162 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16163 }, 16164 }, 16165 }, 16166 { 16167 name: "OR", 16168 argLen: 2, 16169 commutative: true, 16170 asm: ppc64.AOR, 16171 reg: regInfo{ 16172 inputs: []inputInfo{ 16173 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16174 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16175 }, 16176 outputs: []outputInfo{ 16177 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16178 }, 16179 }, 16180 }, 16181 { 16182 name: "ORN", 16183 argLen: 2, 16184 asm: ppc64.AORN, 16185 reg: regInfo{ 16186 inputs: []inputInfo{ 16187 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16188 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16189 }, 16190 outputs: []outputInfo{ 16191 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16192 }, 16193 }, 16194 }, 16195 { 16196 name: "XOR", 16197 argLen: 2, 16198 commutative: true, 16199 asm: ppc64.AXOR, 16200 reg: regInfo{ 16201 inputs: []inputInfo{ 16202 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16203 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16204 }, 16205 outputs: []outputInfo{ 16206 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16207 }, 16208 }, 16209 }, 16210 { 16211 name: "EQV", 16212 argLen: 2, 16213 commutative: true, 16214 asm: ppc64.AEQV, 16215 reg: regInfo{ 16216 inputs: []inputInfo{ 16217 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16218 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16219 }, 16220 outputs: []outputInfo{ 16221 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16222 }, 16223 }, 16224 }, 16225 { 16226 name: "NEG", 16227 argLen: 1, 16228 asm: ppc64.ANEG, 16229 reg: regInfo{ 16230 inputs: []inputInfo{ 16231 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16232 }, 16233 outputs: []outputInfo{ 16234 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16235 }, 16236 }, 16237 }, 16238 { 16239 name: "FNEG", 16240 argLen: 1, 16241 asm: ppc64.AFNEG, 16242 reg: regInfo{ 16243 inputs: []inputInfo{ 16244 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16245 }, 16246 outputs: []outputInfo{ 16247 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16248 }, 16249 }, 16250 }, 16251 { 16252 name: "FSQRT", 16253 argLen: 1, 16254 asm: ppc64.AFSQRT, 16255 reg: regInfo{ 16256 inputs: []inputInfo{ 16257 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16258 }, 16259 outputs: []outputInfo{ 16260 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16261 }, 16262 }, 16263 }, 16264 { 16265 name: "FSQRTS", 16266 argLen: 1, 16267 asm: ppc64.AFSQRTS, 16268 reg: regInfo{ 16269 inputs: []inputInfo{ 16270 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16271 }, 16272 outputs: []outputInfo{ 16273 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16274 }, 16275 }, 16276 }, 16277 { 16278 name: "ORconst", 16279 auxType: auxInt64, 16280 argLen: 1, 16281 asm: ppc64.AOR, 16282 reg: regInfo{ 16283 inputs: []inputInfo{ 16284 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16285 }, 16286 outputs: []outputInfo{ 16287 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16288 }, 16289 }, 16290 }, 16291 { 16292 name: "XORconst", 16293 auxType: auxInt64, 16294 argLen: 1, 16295 asm: ppc64.AXOR, 16296 reg: regInfo{ 16297 inputs: []inputInfo{ 16298 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16299 }, 16300 outputs: []outputInfo{ 16301 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16302 }, 16303 }, 16304 }, 16305 { 16306 name: "ANDconst", 16307 auxType: auxInt64, 16308 argLen: 1, 16309 clobberFlags: true, 16310 asm: ppc64.AANDCC, 16311 reg: regInfo{ 16312 inputs: []inputInfo{ 16313 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16314 }, 16315 outputs: []outputInfo{ 16316 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16317 }, 16318 }, 16319 }, 16320 { 16321 name: "ANDCCconst", 16322 auxType: auxInt64, 16323 argLen: 1, 16324 asm: ppc64.AANDCC, 16325 reg: regInfo{ 16326 inputs: []inputInfo{ 16327 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16328 }, 16329 }, 16330 }, 16331 { 16332 name: "MOVBreg", 16333 argLen: 1, 16334 asm: ppc64.AMOVB, 16335 reg: regInfo{ 16336 inputs: []inputInfo{ 16337 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16338 }, 16339 outputs: []outputInfo{ 16340 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16341 }, 16342 }, 16343 }, 16344 { 16345 name: "MOVBZreg", 16346 argLen: 1, 16347 asm: ppc64.AMOVBZ, 16348 reg: regInfo{ 16349 inputs: []inputInfo{ 16350 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16351 }, 16352 outputs: []outputInfo{ 16353 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16354 }, 16355 }, 16356 }, 16357 { 16358 name: "MOVHreg", 16359 argLen: 1, 16360 asm: ppc64.AMOVH, 16361 reg: regInfo{ 16362 inputs: []inputInfo{ 16363 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16364 }, 16365 outputs: []outputInfo{ 16366 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16367 }, 16368 }, 16369 }, 16370 { 16371 name: "MOVHZreg", 16372 argLen: 1, 16373 asm: ppc64.AMOVHZ, 16374 reg: regInfo{ 16375 inputs: []inputInfo{ 16376 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16377 }, 16378 outputs: []outputInfo{ 16379 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16380 }, 16381 }, 16382 }, 16383 { 16384 name: "MOVWreg", 16385 argLen: 1, 16386 asm: ppc64.AMOVW, 16387 reg: regInfo{ 16388 inputs: []inputInfo{ 16389 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16390 }, 16391 outputs: []outputInfo{ 16392 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16393 }, 16394 }, 16395 }, 16396 { 16397 name: "MOVWZreg", 16398 argLen: 1, 16399 asm: ppc64.AMOVWZ, 16400 reg: regInfo{ 16401 inputs: []inputInfo{ 16402 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16403 }, 16404 outputs: []outputInfo{ 16405 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16406 }, 16407 }, 16408 }, 16409 { 16410 name: "MOVBZload", 16411 auxType: auxSymOff, 16412 argLen: 2, 16413 faultOnNilArg0: true, 16414 asm: ppc64.AMOVBZ, 16415 reg: regInfo{ 16416 inputs: []inputInfo{ 16417 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16418 }, 16419 outputs: []outputInfo{ 16420 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16421 }, 16422 }, 16423 }, 16424 { 16425 name: "MOVHload", 16426 auxType: auxSymOff, 16427 argLen: 2, 16428 faultOnNilArg0: true, 16429 asm: ppc64.AMOVH, 16430 reg: regInfo{ 16431 inputs: []inputInfo{ 16432 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16433 }, 16434 outputs: []outputInfo{ 16435 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16436 }, 16437 }, 16438 }, 16439 { 16440 name: "MOVHZload", 16441 auxType: auxSymOff, 16442 argLen: 2, 16443 faultOnNilArg0: true, 16444 asm: ppc64.AMOVHZ, 16445 reg: regInfo{ 16446 inputs: []inputInfo{ 16447 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16448 }, 16449 outputs: []outputInfo{ 16450 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16451 }, 16452 }, 16453 }, 16454 { 16455 name: "MOVWload", 16456 auxType: auxSymOff, 16457 argLen: 2, 16458 faultOnNilArg0: true, 16459 asm: ppc64.AMOVW, 16460 reg: regInfo{ 16461 inputs: []inputInfo{ 16462 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16463 }, 16464 outputs: []outputInfo{ 16465 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16466 }, 16467 }, 16468 }, 16469 { 16470 name: "MOVWZload", 16471 auxType: auxSymOff, 16472 argLen: 2, 16473 faultOnNilArg0: true, 16474 asm: ppc64.AMOVWZ, 16475 reg: regInfo{ 16476 inputs: []inputInfo{ 16477 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16478 }, 16479 outputs: []outputInfo{ 16480 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16481 }, 16482 }, 16483 }, 16484 { 16485 name: "MOVDload", 16486 auxType: auxSymOff, 16487 argLen: 2, 16488 faultOnNilArg0: true, 16489 asm: ppc64.AMOVD, 16490 reg: regInfo{ 16491 inputs: []inputInfo{ 16492 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16493 }, 16494 outputs: []outputInfo{ 16495 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16496 }, 16497 }, 16498 }, 16499 { 16500 name: "FMOVDload", 16501 auxType: auxSymOff, 16502 argLen: 2, 16503 faultOnNilArg0: true, 16504 asm: ppc64.AFMOVD, 16505 reg: regInfo{ 16506 inputs: []inputInfo{ 16507 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16508 }, 16509 outputs: []outputInfo{ 16510 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16511 }, 16512 }, 16513 }, 16514 { 16515 name: "FMOVSload", 16516 auxType: auxSymOff, 16517 argLen: 2, 16518 faultOnNilArg0: true, 16519 asm: ppc64.AFMOVS, 16520 reg: regInfo{ 16521 inputs: []inputInfo{ 16522 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16523 }, 16524 outputs: []outputInfo{ 16525 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16526 }, 16527 }, 16528 }, 16529 { 16530 name: "MOVBstore", 16531 auxType: auxSymOff, 16532 argLen: 3, 16533 faultOnNilArg0: true, 16534 asm: ppc64.AMOVB, 16535 reg: regInfo{ 16536 inputs: []inputInfo{ 16537 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16538 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16539 }, 16540 }, 16541 }, 16542 { 16543 name: "MOVHstore", 16544 auxType: auxSymOff, 16545 argLen: 3, 16546 faultOnNilArg0: true, 16547 asm: ppc64.AMOVH, 16548 reg: regInfo{ 16549 inputs: []inputInfo{ 16550 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16551 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16552 }, 16553 }, 16554 }, 16555 { 16556 name: "MOVWstore", 16557 auxType: auxSymOff, 16558 argLen: 3, 16559 faultOnNilArg0: true, 16560 asm: ppc64.AMOVW, 16561 reg: regInfo{ 16562 inputs: []inputInfo{ 16563 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16564 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16565 }, 16566 }, 16567 }, 16568 { 16569 name: "MOVDstore", 16570 auxType: auxSymOff, 16571 argLen: 3, 16572 faultOnNilArg0: true, 16573 asm: ppc64.AMOVD, 16574 reg: regInfo{ 16575 inputs: []inputInfo{ 16576 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16577 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16578 }, 16579 }, 16580 }, 16581 { 16582 name: "FMOVDstore", 16583 auxType: auxSymOff, 16584 argLen: 3, 16585 faultOnNilArg0: true, 16586 asm: ppc64.AFMOVD, 16587 reg: regInfo{ 16588 inputs: []inputInfo{ 16589 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16590 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16591 }, 16592 }, 16593 }, 16594 { 16595 name: "FMOVSstore", 16596 auxType: auxSymOff, 16597 argLen: 3, 16598 faultOnNilArg0: true, 16599 asm: ppc64.AFMOVS, 16600 reg: regInfo{ 16601 inputs: []inputInfo{ 16602 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16603 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16604 }, 16605 }, 16606 }, 16607 { 16608 name: "MOVBstorezero", 16609 auxType: auxSymOff, 16610 argLen: 2, 16611 faultOnNilArg0: true, 16612 asm: ppc64.AMOVB, 16613 reg: regInfo{ 16614 inputs: []inputInfo{ 16615 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16616 }, 16617 }, 16618 }, 16619 { 16620 name: "MOVHstorezero", 16621 auxType: auxSymOff, 16622 argLen: 2, 16623 faultOnNilArg0: true, 16624 asm: ppc64.AMOVH, 16625 reg: regInfo{ 16626 inputs: []inputInfo{ 16627 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16628 }, 16629 }, 16630 }, 16631 { 16632 name: "MOVWstorezero", 16633 auxType: auxSymOff, 16634 argLen: 2, 16635 faultOnNilArg0: true, 16636 asm: ppc64.AMOVW, 16637 reg: regInfo{ 16638 inputs: []inputInfo{ 16639 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16640 }, 16641 }, 16642 }, 16643 { 16644 name: "MOVDstorezero", 16645 auxType: auxSymOff, 16646 argLen: 2, 16647 faultOnNilArg0: true, 16648 asm: ppc64.AMOVD, 16649 reg: regInfo{ 16650 inputs: []inputInfo{ 16651 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16652 }, 16653 }, 16654 }, 16655 { 16656 name: "MOVDaddr", 16657 auxType: auxSymOff, 16658 argLen: 1, 16659 rematerializeable: true, 16660 asm: ppc64.AMOVD, 16661 reg: regInfo{ 16662 inputs: []inputInfo{ 16663 {0, 6}, // SP SB 16664 }, 16665 outputs: []outputInfo{ 16666 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16667 }, 16668 }, 16669 }, 16670 { 16671 name: "MOVDconst", 16672 auxType: auxInt64, 16673 argLen: 0, 16674 rematerializeable: true, 16675 asm: ppc64.AMOVD, 16676 reg: regInfo{ 16677 outputs: []outputInfo{ 16678 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16679 }, 16680 }, 16681 }, 16682 { 16683 name: "FMOVDconst", 16684 auxType: auxFloat64, 16685 argLen: 0, 16686 rematerializeable: true, 16687 asm: ppc64.AFMOVD, 16688 reg: regInfo{ 16689 outputs: []outputInfo{ 16690 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16691 }, 16692 }, 16693 }, 16694 { 16695 name: "FMOVSconst", 16696 auxType: auxFloat32, 16697 argLen: 0, 16698 rematerializeable: true, 16699 asm: ppc64.AFMOVS, 16700 reg: regInfo{ 16701 outputs: []outputInfo{ 16702 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16703 }, 16704 }, 16705 }, 16706 { 16707 name: "FCMPU", 16708 argLen: 2, 16709 asm: ppc64.AFCMPU, 16710 reg: regInfo{ 16711 inputs: []inputInfo{ 16712 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16713 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16714 }, 16715 }, 16716 }, 16717 { 16718 name: "CMP", 16719 argLen: 2, 16720 asm: ppc64.ACMP, 16721 reg: regInfo{ 16722 inputs: []inputInfo{ 16723 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16724 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16725 }, 16726 }, 16727 }, 16728 { 16729 name: "CMPU", 16730 argLen: 2, 16731 asm: ppc64.ACMPU, 16732 reg: regInfo{ 16733 inputs: []inputInfo{ 16734 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16735 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16736 }, 16737 }, 16738 }, 16739 { 16740 name: "CMPW", 16741 argLen: 2, 16742 asm: ppc64.ACMPW, 16743 reg: regInfo{ 16744 inputs: []inputInfo{ 16745 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16746 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16747 }, 16748 }, 16749 }, 16750 { 16751 name: "CMPWU", 16752 argLen: 2, 16753 asm: ppc64.ACMPWU, 16754 reg: regInfo{ 16755 inputs: []inputInfo{ 16756 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16757 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16758 }, 16759 }, 16760 }, 16761 { 16762 name: "CMPconst", 16763 auxType: auxInt64, 16764 argLen: 1, 16765 asm: ppc64.ACMP, 16766 reg: regInfo{ 16767 inputs: []inputInfo{ 16768 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16769 }, 16770 }, 16771 }, 16772 { 16773 name: "CMPUconst", 16774 auxType: auxInt64, 16775 argLen: 1, 16776 asm: ppc64.ACMPU, 16777 reg: regInfo{ 16778 inputs: []inputInfo{ 16779 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16780 }, 16781 }, 16782 }, 16783 { 16784 name: "CMPWconst", 16785 auxType: auxInt32, 16786 argLen: 1, 16787 asm: ppc64.ACMPW, 16788 reg: regInfo{ 16789 inputs: []inputInfo{ 16790 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16791 }, 16792 }, 16793 }, 16794 { 16795 name: "CMPWUconst", 16796 auxType: auxInt32, 16797 argLen: 1, 16798 asm: ppc64.ACMPWU, 16799 reg: regInfo{ 16800 inputs: []inputInfo{ 16801 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16802 }, 16803 }, 16804 }, 16805 { 16806 name: "Equal", 16807 argLen: 1, 16808 reg: regInfo{ 16809 outputs: []outputInfo{ 16810 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16811 }, 16812 }, 16813 }, 16814 { 16815 name: "NotEqual", 16816 argLen: 1, 16817 reg: regInfo{ 16818 outputs: []outputInfo{ 16819 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16820 }, 16821 }, 16822 }, 16823 { 16824 name: "LessThan", 16825 argLen: 1, 16826 reg: regInfo{ 16827 outputs: []outputInfo{ 16828 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16829 }, 16830 }, 16831 }, 16832 { 16833 name: "FLessThan", 16834 argLen: 1, 16835 reg: regInfo{ 16836 outputs: []outputInfo{ 16837 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16838 }, 16839 }, 16840 }, 16841 { 16842 name: "LessEqual", 16843 argLen: 1, 16844 reg: regInfo{ 16845 outputs: []outputInfo{ 16846 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16847 }, 16848 }, 16849 }, 16850 { 16851 name: "FLessEqual", 16852 argLen: 1, 16853 reg: regInfo{ 16854 outputs: []outputInfo{ 16855 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16856 }, 16857 }, 16858 }, 16859 { 16860 name: "GreaterThan", 16861 argLen: 1, 16862 reg: regInfo{ 16863 outputs: []outputInfo{ 16864 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16865 }, 16866 }, 16867 }, 16868 { 16869 name: "FGreaterThan", 16870 argLen: 1, 16871 reg: regInfo{ 16872 outputs: []outputInfo{ 16873 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16874 }, 16875 }, 16876 }, 16877 { 16878 name: "GreaterEqual", 16879 argLen: 1, 16880 reg: regInfo{ 16881 outputs: []outputInfo{ 16882 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16883 }, 16884 }, 16885 }, 16886 { 16887 name: "FGreaterEqual", 16888 argLen: 1, 16889 reg: regInfo{ 16890 outputs: []outputInfo{ 16891 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16892 }, 16893 }, 16894 }, 16895 { 16896 name: "LoweredGetClosurePtr", 16897 argLen: 0, 16898 reg: regInfo{ 16899 outputs: []outputInfo{ 16900 {0, 2048}, // R11 16901 }, 16902 }, 16903 }, 16904 { 16905 name: "LoweredNilCheck", 16906 argLen: 2, 16907 clobberFlags: true, 16908 nilCheck: true, 16909 faultOnNilArg0: true, 16910 reg: regInfo{ 16911 inputs: []inputInfo{ 16912 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16913 }, 16914 clobbers: 2147483648, // R31 16915 }, 16916 }, 16917 { 16918 name: "MOVDconvert", 16919 argLen: 2, 16920 asm: ppc64.AMOVD, 16921 reg: regInfo{ 16922 inputs: []inputInfo{ 16923 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16924 }, 16925 outputs: []outputInfo{ 16926 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16927 }, 16928 }, 16929 }, 16930 { 16931 name: "CALLstatic", 16932 auxType: auxSymOff, 16933 argLen: 1, 16934 clobberFlags: true, 16935 call: true, 16936 reg: regInfo{ 16937 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16938 }, 16939 }, 16940 { 16941 name: "CALLclosure", 16942 auxType: auxInt64, 16943 argLen: 3, 16944 clobberFlags: true, 16945 call: true, 16946 reg: regInfo{ 16947 inputs: []inputInfo{ 16948 {1, 2048}, // R11 16949 {0, 1073733626}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16950 }, 16951 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16952 }, 16953 }, 16954 { 16955 name: "CALLdefer", 16956 auxType: auxInt64, 16957 argLen: 1, 16958 clobberFlags: true, 16959 call: true, 16960 reg: regInfo{ 16961 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16962 }, 16963 }, 16964 { 16965 name: "CALLgo", 16966 auxType: auxInt64, 16967 argLen: 1, 16968 clobberFlags: true, 16969 call: true, 16970 reg: regInfo{ 16971 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16972 }, 16973 }, 16974 { 16975 name: "CALLinter", 16976 auxType: auxInt64, 16977 argLen: 2, 16978 clobberFlags: true, 16979 call: true, 16980 reg: regInfo{ 16981 inputs: []inputInfo{ 16982 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16983 }, 16984 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16985 }, 16986 }, 16987 { 16988 name: "LoweredZero", 16989 auxType: auxInt64, 16990 argLen: 3, 16991 clobberFlags: true, 16992 faultOnNilArg0: true, 16993 reg: regInfo{ 16994 inputs: []inputInfo{ 16995 {0, 8}, // R3 16996 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16997 }, 16998 clobbers: 8, // R3 16999 }, 17000 }, 17001 { 17002 name: "LoweredMove", 17003 auxType: auxInt64, 17004 argLen: 4, 17005 clobberFlags: true, 17006 faultOnNilArg0: true, 17007 faultOnNilArg1: true, 17008 reg: regInfo{ 17009 inputs: []inputInfo{ 17010 {0, 8}, // R3 17011 {1, 16}, // R4 17012 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17013 }, 17014 clobbers: 24, // R3 R4 17015 }, 17016 }, 17017 { 17018 name: "InvertFlags", 17019 argLen: 1, 17020 reg: regInfo{}, 17021 }, 17022 { 17023 name: "FlagEQ", 17024 argLen: 0, 17025 reg: regInfo{}, 17026 }, 17027 { 17028 name: "FlagLT", 17029 argLen: 0, 17030 reg: regInfo{}, 17031 }, 17032 { 17033 name: "FlagGT", 17034 argLen: 0, 17035 reg: regInfo{}, 17036 }, 17037 17038 { 17039 name: "ADD", 17040 argLen: 2, 17041 commutative: true, 17042 asm: riscv.AADD, 17043 reg: regInfo{ 17044 inputs: []inputInfo{ 17045 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17046 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17047 }, 17048 outputs: []outputInfo{ 17049 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17050 }, 17051 }, 17052 }, 17053 { 17054 name: "ADDI", 17055 auxType: auxInt64, 17056 argLen: 1, 17057 asm: riscv.AADDI, 17058 reg: regInfo{ 17059 inputs: []inputInfo{ 17060 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 17061 }, 17062 outputs: []outputInfo{ 17063 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17064 }, 17065 }, 17066 }, 17067 { 17068 name: "SUB", 17069 argLen: 2, 17070 asm: riscv.ASUB, 17071 reg: regInfo{ 17072 inputs: []inputInfo{ 17073 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17074 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17075 }, 17076 outputs: []outputInfo{ 17077 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17078 }, 17079 }, 17080 }, 17081 { 17082 name: "MUL", 17083 argLen: 2, 17084 commutative: true, 17085 asm: riscv.AMUL, 17086 reg: regInfo{ 17087 inputs: []inputInfo{ 17088 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17089 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17090 }, 17091 outputs: []outputInfo{ 17092 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17093 }, 17094 }, 17095 }, 17096 { 17097 name: "MULW", 17098 argLen: 2, 17099 commutative: true, 17100 asm: riscv.AMULW, 17101 reg: regInfo{ 17102 inputs: []inputInfo{ 17103 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17104 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17105 }, 17106 outputs: []outputInfo{ 17107 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17108 }, 17109 }, 17110 }, 17111 { 17112 name: "MULH", 17113 argLen: 2, 17114 commutative: true, 17115 asm: riscv.AMULH, 17116 reg: regInfo{ 17117 inputs: []inputInfo{ 17118 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17119 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17120 }, 17121 outputs: []outputInfo{ 17122 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17123 }, 17124 }, 17125 }, 17126 { 17127 name: "MULHU", 17128 argLen: 2, 17129 commutative: true, 17130 asm: riscv.AMULHU, 17131 reg: regInfo{ 17132 inputs: []inputInfo{ 17133 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17134 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17135 }, 17136 outputs: []outputInfo{ 17137 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17138 }, 17139 }, 17140 }, 17141 { 17142 name: "DIV", 17143 argLen: 2, 17144 asm: riscv.ADIV, 17145 reg: regInfo{ 17146 inputs: []inputInfo{ 17147 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17148 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17149 }, 17150 outputs: []outputInfo{ 17151 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17152 }, 17153 }, 17154 }, 17155 { 17156 name: "DIVU", 17157 argLen: 2, 17158 asm: riscv.ADIVU, 17159 reg: regInfo{ 17160 inputs: []inputInfo{ 17161 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17162 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17163 }, 17164 outputs: []outputInfo{ 17165 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17166 }, 17167 }, 17168 }, 17169 { 17170 name: "DIVW", 17171 argLen: 2, 17172 asm: riscv.ADIVW, 17173 reg: regInfo{ 17174 inputs: []inputInfo{ 17175 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17176 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17177 }, 17178 outputs: []outputInfo{ 17179 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17180 }, 17181 }, 17182 }, 17183 { 17184 name: "DIVUW", 17185 argLen: 2, 17186 asm: riscv.ADIVUW, 17187 reg: regInfo{ 17188 inputs: []inputInfo{ 17189 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17190 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17191 }, 17192 outputs: []outputInfo{ 17193 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17194 }, 17195 }, 17196 }, 17197 { 17198 name: "REM", 17199 argLen: 2, 17200 asm: riscv.AREM, 17201 reg: regInfo{ 17202 inputs: []inputInfo{ 17203 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17204 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17205 }, 17206 outputs: []outputInfo{ 17207 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17208 }, 17209 }, 17210 }, 17211 { 17212 name: "REMU", 17213 argLen: 2, 17214 asm: riscv.AREMU, 17215 reg: regInfo{ 17216 inputs: []inputInfo{ 17217 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17218 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17219 }, 17220 outputs: []outputInfo{ 17221 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17222 }, 17223 }, 17224 }, 17225 { 17226 name: "REMW", 17227 argLen: 2, 17228 asm: riscv.AREMW, 17229 reg: regInfo{ 17230 inputs: []inputInfo{ 17231 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17232 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17233 }, 17234 outputs: []outputInfo{ 17235 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17236 }, 17237 }, 17238 }, 17239 { 17240 name: "REMUW", 17241 argLen: 2, 17242 asm: riscv.AREMUW, 17243 reg: regInfo{ 17244 inputs: []inputInfo{ 17245 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17246 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17247 }, 17248 outputs: []outputInfo{ 17249 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17250 }, 17251 }, 17252 }, 17253 { 17254 name: "MOVaddr", 17255 auxType: auxSymOff, 17256 argLen: 1, 17257 rematerializeable: true, 17258 asm: riscv.AMOV, 17259 reg: regInfo{ 17260 inputs: []inputInfo{ 17261 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 17262 }, 17263 outputs: []outputInfo{ 17264 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17265 }, 17266 }, 17267 }, 17268 { 17269 name: "MOVBconst", 17270 auxType: auxInt8, 17271 argLen: 0, 17272 rematerializeable: true, 17273 asm: riscv.AMOV, 17274 reg: regInfo{ 17275 outputs: []outputInfo{ 17276 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17277 }, 17278 }, 17279 }, 17280 { 17281 name: "MOVHconst", 17282 auxType: auxInt16, 17283 argLen: 0, 17284 rematerializeable: true, 17285 asm: riscv.AMOV, 17286 reg: regInfo{ 17287 outputs: []outputInfo{ 17288 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17289 }, 17290 }, 17291 }, 17292 { 17293 name: "MOVWconst", 17294 auxType: auxInt32, 17295 argLen: 0, 17296 rematerializeable: true, 17297 asm: riscv.AMOV, 17298 reg: regInfo{ 17299 outputs: []outputInfo{ 17300 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17301 }, 17302 }, 17303 }, 17304 { 17305 name: "MOVDconst", 17306 auxType: auxInt64, 17307 argLen: 0, 17308 rematerializeable: true, 17309 asm: riscv.AMOV, 17310 reg: regInfo{ 17311 outputs: []outputInfo{ 17312 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17313 }, 17314 }, 17315 }, 17316 { 17317 name: "MOVSconst", 17318 auxType: auxInt32, 17319 argLen: 0, 17320 rematerializeable: true, 17321 asm: riscv.AMOV, 17322 reg: regInfo{ 17323 outputs: []outputInfo{ 17324 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17325 }, 17326 }, 17327 }, 17328 { 17329 name: "MOVBload", 17330 auxType: auxSymOff, 17331 argLen: 2, 17332 faultOnNilArg0: true, 17333 asm: riscv.AMOVB, 17334 reg: regInfo{ 17335 inputs: []inputInfo{ 17336 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 17337 }, 17338 outputs: []outputInfo{ 17339 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17340 }, 17341 }, 17342 }, 17343 { 17344 name: "MOVHload", 17345 auxType: auxSymOff, 17346 argLen: 2, 17347 faultOnNilArg0: true, 17348 asm: riscv.AMOVH, 17349 reg: regInfo{ 17350 inputs: []inputInfo{ 17351 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 17352 }, 17353 outputs: []outputInfo{ 17354 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17355 }, 17356 }, 17357 }, 17358 { 17359 name: "MOVWload", 17360 auxType: auxSymOff, 17361 argLen: 2, 17362 faultOnNilArg0: true, 17363 asm: riscv.AMOVW, 17364 reg: regInfo{ 17365 inputs: []inputInfo{ 17366 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 17367 }, 17368 outputs: []outputInfo{ 17369 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17370 }, 17371 }, 17372 }, 17373 { 17374 name: "MOVDload", 17375 auxType: auxSymOff, 17376 argLen: 2, 17377 faultOnNilArg0: true, 17378 asm: riscv.AMOV, 17379 reg: regInfo{ 17380 inputs: []inputInfo{ 17381 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 17382 }, 17383 outputs: []outputInfo{ 17384 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17385 }, 17386 }, 17387 }, 17388 { 17389 name: "MOVBUload", 17390 auxType: auxSymOff, 17391 argLen: 2, 17392 faultOnNilArg0: true, 17393 asm: riscv.AMOVBU, 17394 reg: regInfo{ 17395 inputs: []inputInfo{ 17396 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 17397 }, 17398 outputs: []outputInfo{ 17399 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17400 }, 17401 }, 17402 }, 17403 { 17404 name: "MOVHUload", 17405 auxType: auxSymOff, 17406 argLen: 2, 17407 faultOnNilArg0: true, 17408 asm: riscv.AMOVHU, 17409 reg: regInfo{ 17410 inputs: []inputInfo{ 17411 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 17412 }, 17413 outputs: []outputInfo{ 17414 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17415 }, 17416 }, 17417 }, 17418 { 17419 name: "MOVWUload", 17420 auxType: auxSymOff, 17421 argLen: 2, 17422 faultOnNilArg0: true, 17423 asm: riscv.AMOVWU, 17424 reg: regInfo{ 17425 inputs: []inputInfo{ 17426 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 17427 }, 17428 outputs: []outputInfo{ 17429 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17430 }, 17431 }, 17432 }, 17433 { 17434 name: "MOVBstore", 17435 auxType: auxSymOff, 17436 argLen: 3, 17437 faultOnNilArg0: true, 17438 asm: riscv.AMOVB, 17439 reg: regInfo{ 17440 inputs: []inputInfo{ 17441 {1, 1073741814}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17442 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 17443 }, 17444 }, 17445 }, 17446 { 17447 name: "MOVHstore", 17448 auxType: auxSymOff, 17449 argLen: 3, 17450 faultOnNilArg0: true, 17451 asm: riscv.AMOVH, 17452 reg: regInfo{ 17453 inputs: []inputInfo{ 17454 {1, 1073741814}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17455 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 17456 }, 17457 }, 17458 }, 17459 { 17460 name: "MOVWstore", 17461 auxType: auxSymOff, 17462 argLen: 3, 17463 faultOnNilArg0: true, 17464 asm: riscv.AMOVW, 17465 reg: regInfo{ 17466 inputs: []inputInfo{ 17467 {1, 1073741814}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17468 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 17469 }, 17470 }, 17471 }, 17472 { 17473 name: "MOVDstore", 17474 auxType: auxSymOff, 17475 argLen: 3, 17476 faultOnNilArg0: true, 17477 asm: riscv.AMOV, 17478 reg: regInfo{ 17479 inputs: []inputInfo{ 17480 {1, 1073741814}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17481 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 17482 }, 17483 }, 17484 }, 17485 { 17486 name: "SLL", 17487 argLen: 2, 17488 asm: riscv.ASLL, 17489 reg: regInfo{ 17490 inputs: []inputInfo{ 17491 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17492 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17493 }, 17494 outputs: []outputInfo{ 17495 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17496 }, 17497 }, 17498 }, 17499 { 17500 name: "SRA", 17501 argLen: 2, 17502 asm: riscv.ASRA, 17503 reg: regInfo{ 17504 inputs: []inputInfo{ 17505 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17506 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17507 }, 17508 outputs: []outputInfo{ 17509 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17510 }, 17511 }, 17512 }, 17513 { 17514 name: "SRL", 17515 argLen: 2, 17516 asm: riscv.ASRL, 17517 reg: regInfo{ 17518 inputs: []inputInfo{ 17519 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17520 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17521 }, 17522 outputs: []outputInfo{ 17523 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17524 }, 17525 }, 17526 }, 17527 { 17528 name: "SLLI", 17529 auxType: auxInt64, 17530 argLen: 1, 17531 asm: riscv.ASLLI, 17532 reg: regInfo{ 17533 inputs: []inputInfo{ 17534 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17535 }, 17536 outputs: []outputInfo{ 17537 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17538 }, 17539 }, 17540 }, 17541 { 17542 name: "SRAI", 17543 auxType: auxInt64, 17544 argLen: 1, 17545 asm: riscv.ASRAI, 17546 reg: regInfo{ 17547 inputs: []inputInfo{ 17548 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17549 }, 17550 outputs: []outputInfo{ 17551 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17552 }, 17553 }, 17554 }, 17555 { 17556 name: "SRLI", 17557 auxType: auxInt64, 17558 argLen: 1, 17559 asm: riscv.ASRLI, 17560 reg: regInfo{ 17561 inputs: []inputInfo{ 17562 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17563 }, 17564 outputs: []outputInfo{ 17565 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17566 }, 17567 }, 17568 }, 17569 { 17570 name: "XOR", 17571 argLen: 2, 17572 commutative: true, 17573 asm: riscv.AXOR, 17574 reg: regInfo{ 17575 inputs: []inputInfo{ 17576 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17577 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17578 }, 17579 outputs: []outputInfo{ 17580 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17581 }, 17582 }, 17583 }, 17584 { 17585 name: "XORI", 17586 auxType: auxInt64, 17587 argLen: 1, 17588 asm: riscv.AXORI, 17589 reg: regInfo{ 17590 inputs: []inputInfo{ 17591 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17592 }, 17593 outputs: []outputInfo{ 17594 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17595 }, 17596 }, 17597 }, 17598 { 17599 name: "OR", 17600 argLen: 2, 17601 commutative: true, 17602 asm: riscv.AOR, 17603 reg: regInfo{ 17604 inputs: []inputInfo{ 17605 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17606 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17607 }, 17608 outputs: []outputInfo{ 17609 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17610 }, 17611 }, 17612 }, 17613 { 17614 name: "ORI", 17615 auxType: auxInt64, 17616 argLen: 1, 17617 asm: riscv.AORI, 17618 reg: regInfo{ 17619 inputs: []inputInfo{ 17620 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17621 }, 17622 outputs: []outputInfo{ 17623 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17624 }, 17625 }, 17626 }, 17627 { 17628 name: "AND", 17629 argLen: 2, 17630 commutative: true, 17631 asm: riscv.AAND, 17632 reg: regInfo{ 17633 inputs: []inputInfo{ 17634 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17635 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17636 }, 17637 outputs: []outputInfo{ 17638 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17639 }, 17640 }, 17641 }, 17642 { 17643 name: "ANDI", 17644 auxType: auxInt64, 17645 argLen: 1, 17646 asm: riscv.AANDI, 17647 reg: regInfo{ 17648 inputs: []inputInfo{ 17649 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17650 }, 17651 outputs: []outputInfo{ 17652 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17653 }, 17654 }, 17655 }, 17656 { 17657 name: "SEQZ", 17658 argLen: 1, 17659 asm: riscv.ASEQZ, 17660 reg: regInfo{ 17661 inputs: []inputInfo{ 17662 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17663 }, 17664 outputs: []outputInfo{ 17665 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17666 }, 17667 }, 17668 }, 17669 { 17670 name: "SNEZ", 17671 argLen: 1, 17672 asm: riscv.ASNEZ, 17673 reg: regInfo{ 17674 inputs: []inputInfo{ 17675 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17676 }, 17677 outputs: []outputInfo{ 17678 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17679 }, 17680 }, 17681 }, 17682 { 17683 name: "SLT", 17684 argLen: 2, 17685 asm: riscv.ASLT, 17686 reg: regInfo{ 17687 inputs: []inputInfo{ 17688 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17689 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17690 }, 17691 outputs: []outputInfo{ 17692 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17693 }, 17694 }, 17695 }, 17696 { 17697 name: "SLTI", 17698 auxType: auxInt64, 17699 argLen: 1, 17700 asm: riscv.ASLTI, 17701 reg: regInfo{ 17702 inputs: []inputInfo{ 17703 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17704 }, 17705 outputs: []outputInfo{ 17706 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17707 }, 17708 }, 17709 }, 17710 { 17711 name: "SLTU", 17712 argLen: 2, 17713 asm: riscv.ASLTU, 17714 reg: regInfo{ 17715 inputs: []inputInfo{ 17716 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17717 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17718 }, 17719 outputs: []outputInfo{ 17720 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17721 }, 17722 }, 17723 }, 17724 { 17725 name: "SLTIU", 17726 auxType: auxInt64, 17727 argLen: 1, 17728 asm: riscv.ASLTIU, 17729 reg: regInfo{ 17730 inputs: []inputInfo{ 17731 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17732 }, 17733 outputs: []outputInfo{ 17734 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17735 }, 17736 }, 17737 }, 17738 { 17739 name: "MOVconvert", 17740 argLen: 2, 17741 asm: riscv.AMOV, 17742 reg: regInfo{ 17743 inputs: []inputInfo{ 17744 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17745 }, 17746 outputs: []outputInfo{ 17747 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17748 }, 17749 }, 17750 }, 17751 { 17752 name: "CALLstatic", 17753 auxType: auxSymOff, 17754 argLen: 1, 17755 call: true, 17756 reg: regInfo{ 17757 clobbers: 9223372035781033980, // GP g T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17758 }, 17759 }, 17760 { 17761 name: "CALLclosure", 17762 auxType: auxInt64, 17763 argLen: 3, 17764 call: true, 17765 reg: regInfo{ 17766 inputs: []inputInfo{ 17767 {1, 524288}, // CTXT 17768 {0, 1073741814}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17769 }, 17770 clobbers: 9223372035781033980, // GP g T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17771 }, 17772 }, 17773 { 17774 name: "CALLdefer", 17775 auxType: auxInt64, 17776 argLen: 1, 17777 call: true, 17778 reg: regInfo{ 17779 clobbers: 9223372035781033980, // GP g T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17780 }, 17781 }, 17782 { 17783 name: "CALLgo", 17784 auxType: auxInt64, 17785 argLen: 1, 17786 call: true, 17787 reg: regInfo{ 17788 clobbers: 9223372035781033980, // GP g T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17789 }, 17790 }, 17791 { 17792 name: "CALLinter", 17793 auxType: auxInt64, 17794 argLen: 2, 17795 call: true, 17796 reg: regInfo{ 17797 inputs: []inputInfo{ 17798 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17799 }, 17800 clobbers: 9223372035781033980, // GP g T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17801 }, 17802 }, 17803 { 17804 name: "LoweredZero", 17805 auxType: auxInt64, 17806 argLen: 3, 17807 faultOnNilArg0: true, 17808 reg: regInfo{ 17809 inputs: []inputInfo{ 17810 {0, 16}, // T0 17811 {1, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17812 }, 17813 clobbers: 16, // T0 17814 }, 17815 }, 17816 { 17817 name: "LoweredMove", 17818 auxType: auxInt64, 17819 argLen: 4, 17820 faultOnNilArg0: true, 17821 faultOnNilArg1: true, 17822 reg: regInfo{ 17823 inputs: []inputInfo{ 17824 {0, 16}, // T0 17825 {1, 32}, // T1 17826 {2, 1073741748}, // GP T0 T1 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17827 }, 17828 clobbers: 112, // T0 T1 T2 17829 }, 17830 }, 17831 { 17832 name: "LoweredNilCheck", 17833 argLen: 2, 17834 nilCheck: true, 17835 faultOnNilArg0: true, 17836 reg: regInfo{ 17837 inputs: []inputInfo{ 17838 {0, 1073741814}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17839 }, 17840 }, 17841 }, 17842 { 17843 name: "LoweredGetClosurePtr", 17844 argLen: 0, 17845 reg: regInfo{ 17846 outputs: []outputInfo{ 17847 {0, 524288}, // CTXT 17848 }, 17849 }, 17850 }, 17851 { 17852 name: "FADDS", 17853 argLen: 2, 17854 commutative: true, 17855 asm: riscv.AFADDS, 17856 reg: regInfo{ 17857 inputs: []inputInfo{ 17858 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17859 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17860 }, 17861 outputs: []outputInfo{ 17862 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17863 }, 17864 }, 17865 }, 17866 { 17867 name: "FSUBS", 17868 argLen: 2, 17869 asm: riscv.AFSUBS, 17870 reg: regInfo{ 17871 inputs: []inputInfo{ 17872 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17873 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17874 }, 17875 outputs: []outputInfo{ 17876 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17877 }, 17878 }, 17879 }, 17880 { 17881 name: "FMULS", 17882 argLen: 2, 17883 commutative: true, 17884 asm: riscv.AFMULS, 17885 reg: regInfo{ 17886 inputs: []inputInfo{ 17887 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17888 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17889 }, 17890 outputs: []outputInfo{ 17891 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17892 }, 17893 }, 17894 }, 17895 { 17896 name: "FDIVS", 17897 argLen: 2, 17898 asm: riscv.AFDIVS, 17899 reg: regInfo{ 17900 inputs: []inputInfo{ 17901 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17902 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17903 }, 17904 outputs: []outputInfo{ 17905 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17906 }, 17907 }, 17908 }, 17909 { 17910 name: "FSQRTS", 17911 argLen: 1, 17912 asm: riscv.AFSQRTS, 17913 reg: regInfo{ 17914 inputs: []inputInfo{ 17915 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17916 }, 17917 outputs: []outputInfo{ 17918 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17919 }, 17920 }, 17921 }, 17922 { 17923 name: "FNEGS", 17924 argLen: 1, 17925 asm: riscv.AFNEGS, 17926 reg: regInfo{ 17927 inputs: []inputInfo{ 17928 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17929 }, 17930 outputs: []outputInfo{ 17931 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17932 }, 17933 }, 17934 }, 17935 { 17936 name: "FMVSX", 17937 argLen: 1, 17938 asm: riscv.AFMVSX, 17939 reg: regInfo{ 17940 inputs: []inputInfo{ 17941 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17942 }, 17943 outputs: []outputInfo{ 17944 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17945 }, 17946 }, 17947 }, 17948 { 17949 name: "FCVTSW", 17950 argLen: 1, 17951 asm: riscv.AFCVTSW, 17952 reg: regInfo{ 17953 inputs: []inputInfo{ 17954 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17955 }, 17956 outputs: []outputInfo{ 17957 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17958 }, 17959 }, 17960 }, 17961 { 17962 name: "FCVTSL", 17963 argLen: 1, 17964 asm: riscv.AFCVTSL, 17965 reg: regInfo{ 17966 inputs: []inputInfo{ 17967 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17968 }, 17969 outputs: []outputInfo{ 17970 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17971 }, 17972 }, 17973 }, 17974 { 17975 name: "FCVTWS", 17976 argLen: 1, 17977 asm: riscv.AFCVTWS, 17978 reg: regInfo{ 17979 inputs: []inputInfo{ 17980 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17981 }, 17982 outputs: []outputInfo{ 17983 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17984 }, 17985 }, 17986 }, 17987 { 17988 name: "FCVTLS", 17989 argLen: 1, 17990 asm: riscv.AFCVTLS, 17991 reg: regInfo{ 17992 inputs: []inputInfo{ 17993 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 17994 }, 17995 outputs: []outputInfo{ 17996 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 17997 }, 17998 }, 17999 }, 18000 { 18001 name: "FMOVWload", 18002 auxType: auxSymOff, 18003 argLen: 2, 18004 faultOnNilArg0: true, 18005 asm: riscv.AMOVF, 18006 reg: regInfo{ 18007 inputs: []inputInfo{ 18008 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 18009 }, 18010 outputs: []outputInfo{ 18011 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18012 }, 18013 }, 18014 }, 18015 { 18016 name: "FMOVWstore", 18017 auxType: auxSymOff, 18018 argLen: 3, 18019 faultOnNilArg0: true, 18020 asm: riscv.AMOVF, 18021 reg: regInfo{ 18022 inputs: []inputInfo{ 18023 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 18024 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18025 }, 18026 }, 18027 }, 18028 { 18029 name: "FEQS", 18030 argLen: 2, 18031 commutative: true, 18032 asm: riscv.AFEQS, 18033 reg: regInfo{ 18034 inputs: []inputInfo{ 18035 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18036 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18037 }, 18038 outputs: []outputInfo{ 18039 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 18040 }, 18041 }, 18042 }, 18043 { 18044 name: "FNES", 18045 argLen: 2, 18046 commutative: true, 18047 asm: riscv.AFNES, 18048 reg: regInfo{ 18049 inputs: []inputInfo{ 18050 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18051 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18052 }, 18053 outputs: []outputInfo{ 18054 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 18055 }, 18056 }, 18057 }, 18058 { 18059 name: "FLTS", 18060 argLen: 2, 18061 asm: riscv.AFLTS, 18062 reg: regInfo{ 18063 inputs: []inputInfo{ 18064 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18065 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18066 }, 18067 outputs: []outputInfo{ 18068 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 18069 }, 18070 }, 18071 }, 18072 { 18073 name: "FLES", 18074 argLen: 2, 18075 asm: riscv.AFLES, 18076 reg: regInfo{ 18077 inputs: []inputInfo{ 18078 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18079 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18080 }, 18081 outputs: []outputInfo{ 18082 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 18083 }, 18084 }, 18085 }, 18086 { 18087 name: "FADDD", 18088 argLen: 2, 18089 commutative: true, 18090 asm: riscv.AFADDD, 18091 reg: regInfo{ 18092 inputs: []inputInfo{ 18093 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18094 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18095 }, 18096 outputs: []outputInfo{ 18097 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18098 }, 18099 }, 18100 }, 18101 { 18102 name: "FSUBD", 18103 argLen: 2, 18104 asm: riscv.AFSUBD, 18105 reg: regInfo{ 18106 inputs: []inputInfo{ 18107 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18108 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18109 }, 18110 outputs: []outputInfo{ 18111 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18112 }, 18113 }, 18114 }, 18115 { 18116 name: "FMULD", 18117 argLen: 2, 18118 commutative: true, 18119 asm: riscv.AFMULD, 18120 reg: regInfo{ 18121 inputs: []inputInfo{ 18122 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18123 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18124 }, 18125 outputs: []outputInfo{ 18126 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18127 }, 18128 }, 18129 }, 18130 { 18131 name: "FDIVD", 18132 argLen: 2, 18133 asm: riscv.AFDIVD, 18134 reg: regInfo{ 18135 inputs: []inputInfo{ 18136 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18137 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18138 }, 18139 outputs: []outputInfo{ 18140 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18141 }, 18142 }, 18143 }, 18144 { 18145 name: "FSQRTD", 18146 argLen: 1, 18147 asm: riscv.AFSQRTD, 18148 reg: regInfo{ 18149 inputs: []inputInfo{ 18150 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18151 }, 18152 outputs: []outputInfo{ 18153 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18154 }, 18155 }, 18156 }, 18157 { 18158 name: "FNEGD", 18159 argLen: 1, 18160 asm: riscv.AFNEGD, 18161 reg: regInfo{ 18162 inputs: []inputInfo{ 18163 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18164 }, 18165 outputs: []outputInfo{ 18166 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18167 }, 18168 }, 18169 }, 18170 { 18171 name: "FMVDX", 18172 argLen: 1, 18173 asm: riscv.AFMVDX, 18174 reg: regInfo{ 18175 inputs: []inputInfo{ 18176 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 18177 }, 18178 outputs: []outputInfo{ 18179 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18180 }, 18181 }, 18182 }, 18183 { 18184 name: "FCVTDW", 18185 argLen: 1, 18186 asm: riscv.AFCVTDW, 18187 reg: regInfo{ 18188 inputs: []inputInfo{ 18189 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 18190 }, 18191 outputs: []outputInfo{ 18192 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18193 }, 18194 }, 18195 }, 18196 { 18197 name: "FCVTDL", 18198 argLen: 1, 18199 asm: riscv.AFCVTDL, 18200 reg: regInfo{ 18201 inputs: []inputInfo{ 18202 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 18203 }, 18204 outputs: []outputInfo{ 18205 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18206 }, 18207 }, 18208 }, 18209 { 18210 name: "FCVTWD", 18211 argLen: 1, 18212 asm: riscv.AFCVTWD, 18213 reg: regInfo{ 18214 inputs: []inputInfo{ 18215 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18216 }, 18217 outputs: []outputInfo{ 18218 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 18219 }, 18220 }, 18221 }, 18222 { 18223 name: "FCVTLD", 18224 argLen: 1, 18225 asm: riscv.AFCVTLD, 18226 reg: regInfo{ 18227 inputs: []inputInfo{ 18228 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18229 }, 18230 outputs: []outputInfo{ 18231 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 18232 }, 18233 }, 18234 }, 18235 { 18236 name: "FCVTDS", 18237 argLen: 1, 18238 asm: riscv.AFCVTDS, 18239 reg: regInfo{ 18240 inputs: []inputInfo{ 18241 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18242 }, 18243 outputs: []outputInfo{ 18244 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18245 }, 18246 }, 18247 }, 18248 { 18249 name: "FCVTSD", 18250 argLen: 1, 18251 asm: riscv.AFCVTSD, 18252 reg: regInfo{ 18253 inputs: []inputInfo{ 18254 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18255 }, 18256 outputs: []outputInfo{ 18257 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18258 }, 18259 }, 18260 }, 18261 { 18262 name: "FMOVDload", 18263 auxType: auxSymOff, 18264 argLen: 2, 18265 faultOnNilArg0: true, 18266 asm: riscv.AMOVD, 18267 reg: regInfo{ 18268 inputs: []inputInfo{ 18269 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 18270 }, 18271 outputs: []outputInfo{ 18272 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18273 }, 18274 }, 18275 }, 18276 { 18277 name: "FMOVDstore", 18278 auxType: auxSymOff, 18279 argLen: 3, 18280 faultOnNilArg0: true, 18281 asm: riscv.AMOVD, 18282 reg: regInfo{ 18283 inputs: []inputInfo{ 18284 {0, 9223372037928517622}, // SP GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 SB 18285 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18286 }, 18287 }, 18288 }, 18289 { 18290 name: "FEQD", 18291 argLen: 2, 18292 commutative: true, 18293 asm: riscv.AFEQD, 18294 reg: regInfo{ 18295 inputs: []inputInfo{ 18296 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18297 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18298 }, 18299 outputs: []outputInfo{ 18300 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 18301 }, 18302 }, 18303 }, 18304 { 18305 name: "FNED", 18306 argLen: 2, 18307 commutative: true, 18308 asm: riscv.AFNED, 18309 reg: regInfo{ 18310 inputs: []inputInfo{ 18311 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18312 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18313 }, 18314 outputs: []outputInfo{ 18315 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 18316 }, 18317 }, 18318 }, 18319 { 18320 name: "FLTD", 18321 argLen: 2, 18322 asm: riscv.AFLTD, 18323 reg: regInfo{ 18324 inputs: []inputInfo{ 18325 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18326 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18327 }, 18328 outputs: []outputInfo{ 18329 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 18330 }, 18331 }, 18332 }, 18333 { 18334 name: "FLED", 18335 argLen: 2, 18336 asm: riscv.AFLED, 18337 reg: regInfo{ 18338 inputs: []inputInfo{ 18339 {0, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18340 {1, 9223372034707292160}, // FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FS0 FS1 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FT8 FT9 FT10 FT11 18341 }, 18342 outputs: []outputInfo{ 18343 {0, 1073741812}, // GP T0 T1 T2 S0 S1 A0 A1 A2 A3 A4 A5 A6 A7 S2 S3 CTXT S5 S6 S7 S8 S9 S10 S11 T3 T4 T5 18344 }, 18345 }, 18346 }, 18347 18348 { 18349 name: "FADDS", 18350 argLen: 2, 18351 commutative: true, 18352 resultInArg0: true, 18353 clobberFlags: true, 18354 asm: s390x.AFADDS, 18355 reg: regInfo{ 18356 inputs: []inputInfo{ 18357 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18358 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18359 }, 18360 outputs: []outputInfo{ 18361 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18362 }, 18363 }, 18364 }, 18365 { 18366 name: "FADD", 18367 argLen: 2, 18368 commutative: true, 18369 resultInArg0: true, 18370 clobberFlags: true, 18371 asm: s390x.AFADD, 18372 reg: regInfo{ 18373 inputs: []inputInfo{ 18374 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18375 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18376 }, 18377 outputs: []outputInfo{ 18378 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18379 }, 18380 }, 18381 }, 18382 { 18383 name: "FSUBS", 18384 argLen: 2, 18385 resultInArg0: true, 18386 clobberFlags: true, 18387 asm: s390x.AFSUBS, 18388 reg: regInfo{ 18389 inputs: []inputInfo{ 18390 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18391 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18392 }, 18393 outputs: []outputInfo{ 18394 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18395 }, 18396 }, 18397 }, 18398 { 18399 name: "FSUB", 18400 argLen: 2, 18401 resultInArg0: true, 18402 clobberFlags: true, 18403 asm: s390x.AFSUB, 18404 reg: regInfo{ 18405 inputs: []inputInfo{ 18406 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18407 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18408 }, 18409 outputs: []outputInfo{ 18410 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18411 }, 18412 }, 18413 }, 18414 { 18415 name: "FMULS", 18416 argLen: 2, 18417 commutative: true, 18418 resultInArg0: true, 18419 asm: s390x.AFMULS, 18420 reg: regInfo{ 18421 inputs: []inputInfo{ 18422 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18423 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18424 }, 18425 outputs: []outputInfo{ 18426 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18427 }, 18428 }, 18429 }, 18430 { 18431 name: "FMUL", 18432 argLen: 2, 18433 commutative: true, 18434 resultInArg0: true, 18435 asm: s390x.AFMUL, 18436 reg: regInfo{ 18437 inputs: []inputInfo{ 18438 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18439 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18440 }, 18441 outputs: []outputInfo{ 18442 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18443 }, 18444 }, 18445 }, 18446 { 18447 name: "FDIVS", 18448 argLen: 2, 18449 resultInArg0: true, 18450 asm: s390x.AFDIVS, 18451 reg: regInfo{ 18452 inputs: []inputInfo{ 18453 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18454 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18455 }, 18456 outputs: []outputInfo{ 18457 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18458 }, 18459 }, 18460 }, 18461 { 18462 name: "FDIV", 18463 argLen: 2, 18464 resultInArg0: true, 18465 asm: s390x.AFDIV, 18466 reg: regInfo{ 18467 inputs: []inputInfo{ 18468 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18469 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18470 }, 18471 outputs: []outputInfo{ 18472 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18473 }, 18474 }, 18475 }, 18476 { 18477 name: "FNEGS", 18478 argLen: 1, 18479 clobberFlags: true, 18480 asm: s390x.AFNEGS, 18481 reg: regInfo{ 18482 inputs: []inputInfo{ 18483 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18484 }, 18485 outputs: []outputInfo{ 18486 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18487 }, 18488 }, 18489 }, 18490 { 18491 name: "FNEG", 18492 argLen: 1, 18493 clobberFlags: true, 18494 asm: s390x.AFNEG, 18495 reg: regInfo{ 18496 inputs: []inputInfo{ 18497 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18498 }, 18499 outputs: []outputInfo{ 18500 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18501 }, 18502 }, 18503 }, 18504 { 18505 name: "FMOVSload", 18506 auxType: auxSymOff, 18507 argLen: 2, 18508 faultOnNilArg0: true, 18509 asm: s390x.AFMOVS, 18510 reg: regInfo{ 18511 inputs: []inputInfo{ 18512 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18513 }, 18514 outputs: []outputInfo{ 18515 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18516 }, 18517 }, 18518 }, 18519 { 18520 name: "FMOVDload", 18521 auxType: auxSymOff, 18522 argLen: 2, 18523 faultOnNilArg0: true, 18524 asm: s390x.AFMOVD, 18525 reg: regInfo{ 18526 inputs: []inputInfo{ 18527 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18528 }, 18529 outputs: []outputInfo{ 18530 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18531 }, 18532 }, 18533 }, 18534 { 18535 name: "FMOVSconst", 18536 auxType: auxFloat32, 18537 argLen: 0, 18538 rematerializeable: true, 18539 asm: s390x.AFMOVS, 18540 reg: regInfo{ 18541 outputs: []outputInfo{ 18542 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18543 }, 18544 }, 18545 }, 18546 { 18547 name: "FMOVDconst", 18548 auxType: auxFloat64, 18549 argLen: 0, 18550 rematerializeable: true, 18551 asm: s390x.AFMOVD, 18552 reg: regInfo{ 18553 outputs: []outputInfo{ 18554 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18555 }, 18556 }, 18557 }, 18558 { 18559 name: "FMOVSloadidx", 18560 auxType: auxSymOff, 18561 argLen: 3, 18562 asm: s390x.AFMOVS, 18563 reg: regInfo{ 18564 inputs: []inputInfo{ 18565 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18566 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18567 }, 18568 outputs: []outputInfo{ 18569 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18570 }, 18571 }, 18572 }, 18573 { 18574 name: "FMOVDloadidx", 18575 auxType: auxSymOff, 18576 argLen: 3, 18577 asm: s390x.AFMOVD, 18578 reg: regInfo{ 18579 inputs: []inputInfo{ 18580 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18581 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18582 }, 18583 outputs: []outputInfo{ 18584 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18585 }, 18586 }, 18587 }, 18588 { 18589 name: "FMOVSstore", 18590 auxType: auxSymOff, 18591 argLen: 3, 18592 faultOnNilArg0: true, 18593 asm: s390x.AFMOVS, 18594 reg: regInfo{ 18595 inputs: []inputInfo{ 18596 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18597 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18598 }, 18599 }, 18600 }, 18601 { 18602 name: "FMOVDstore", 18603 auxType: auxSymOff, 18604 argLen: 3, 18605 faultOnNilArg0: true, 18606 asm: s390x.AFMOVD, 18607 reg: regInfo{ 18608 inputs: []inputInfo{ 18609 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18610 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18611 }, 18612 }, 18613 }, 18614 { 18615 name: "FMOVSstoreidx", 18616 auxType: auxSymOff, 18617 argLen: 4, 18618 asm: s390x.AFMOVS, 18619 reg: regInfo{ 18620 inputs: []inputInfo{ 18621 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18622 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18623 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18624 }, 18625 }, 18626 }, 18627 { 18628 name: "FMOVDstoreidx", 18629 auxType: auxSymOff, 18630 argLen: 4, 18631 asm: s390x.AFMOVD, 18632 reg: regInfo{ 18633 inputs: []inputInfo{ 18634 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18635 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18636 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18637 }, 18638 }, 18639 }, 18640 { 18641 name: "ADD", 18642 argLen: 2, 18643 commutative: true, 18644 clobberFlags: true, 18645 asm: s390x.AADD, 18646 reg: regInfo{ 18647 inputs: []inputInfo{ 18648 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18649 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18650 }, 18651 outputs: []outputInfo{ 18652 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18653 }, 18654 }, 18655 }, 18656 { 18657 name: "ADDW", 18658 argLen: 2, 18659 commutative: true, 18660 clobberFlags: true, 18661 asm: s390x.AADDW, 18662 reg: regInfo{ 18663 inputs: []inputInfo{ 18664 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18665 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18666 }, 18667 outputs: []outputInfo{ 18668 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18669 }, 18670 }, 18671 }, 18672 { 18673 name: "ADDconst", 18674 auxType: auxInt64, 18675 argLen: 1, 18676 clobberFlags: true, 18677 asm: s390x.AADD, 18678 reg: regInfo{ 18679 inputs: []inputInfo{ 18680 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18681 }, 18682 outputs: []outputInfo{ 18683 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18684 }, 18685 }, 18686 }, 18687 { 18688 name: "ADDWconst", 18689 auxType: auxInt32, 18690 argLen: 1, 18691 clobberFlags: true, 18692 asm: s390x.AADDW, 18693 reg: regInfo{ 18694 inputs: []inputInfo{ 18695 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18696 }, 18697 outputs: []outputInfo{ 18698 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18699 }, 18700 }, 18701 }, 18702 { 18703 name: "ADDload", 18704 auxType: auxSymOff, 18705 argLen: 3, 18706 resultInArg0: true, 18707 clobberFlags: true, 18708 faultOnNilArg1: true, 18709 asm: s390x.AADD, 18710 reg: regInfo{ 18711 inputs: []inputInfo{ 18712 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18713 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18714 }, 18715 outputs: []outputInfo{ 18716 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18717 }, 18718 }, 18719 }, 18720 { 18721 name: "ADDWload", 18722 auxType: auxSymOff, 18723 argLen: 3, 18724 resultInArg0: true, 18725 clobberFlags: true, 18726 faultOnNilArg1: true, 18727 asm: s390x.AADDW, 18728 reg: regInfo{ 18729 inputs: []inputInfo{ 18730 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18731 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18732 }, 18733 outputs: []outputInfo{ 18734 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18735 }, 18736 }, 18737 }, 18738 { 18739 name: "SUB", 18740 argLen: 2, 18741 clobberFlags: true, 18742 asm: s390x.ASUB, 18743 reg: regInfo{ 18744 inputs: []inputInfo{ 18745 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18746 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18747 }, 18748 outputs: []outputInfo{ 18749 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18750 }, 18751 }, 18752 }, 18753 { 18754 name: "SUBW", 18755 argLen: 2, 18756 clobberFlags: true, 18757 asm: s390x.ASUBW, 18758 reg: regInfo{ 18759 inputs: []inputInfo{ 18760 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18761 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18762 }, 18763 outputs: []outputInfo{ 18764 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18765 }, 18766 }, 18767 }, 18768 { 18769 name: "SUBconst", 18770 auxType: auxInt64, 18771 argLen: 1, 18772 resultInArg0: true, 18773 clobberFlags: true, 18774 asm: s390x.ASUB, 18775 reg: regInfo{ 18776 inputs: []inputInfo{ 18777 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18778 }, 18779 outputs: []outputInfo{ 18780 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18781 }, 18782 }, 18783 }, 18784 { 18785 name: "SUBWconst", 18786 auxType: auxInt32, 18787 argLen: 1, 18788 resultInArg0: true, 18789 clobberFlags: true, 18790 asm: s390x.ASUBW, 18791 reg: regInfo{ 18792 inputs: []inputInfo{ 18793 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18794 }, 18795 outputs: []outputInfo{ 18796 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18797 }, 18798 }, 18799 }, 18800 { 18801 name: "SUBload", 18802 auxType: auxSymOff, 18803 argLen: 3, 18804 resultInArg0: true, 18805 clobberFlags: true, 18806 faultOnNilArg1: true, 18807 asm: s390x.ASUB, 18808 reg: regInfo{ 18809 inputs: []inputInfo{ 18810 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18811 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18812 }, 18813 outputs: []outputInfo{ 18814 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18815 }, 18816 }, 18817 }, 18818 { 18819 name: "SUBWload", 18820 auxType: auxSymOff, 18821 argLen: 3, 18822 resultInArg0: true, 18823 clobberFlags: true, 18824 faultOnNilArg1: true, 18825 asm: s390x.ASUBW, 18826 reg: regInfo{ 18827 inputs: []inputInfo{ 18828 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18829 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18830 }, 18831 outputs: []outputInfo{ 18832 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18833 }, 18834 }, 18835 }, 18836 { 18837 name: "MULLD", 18838 argLen: 2, 18839 commutative: true, 18840 resultInArg0: true, 18841 clobberFlags: true, 18842 asm: s390x.AMULLD, 18843 reg: regInfo{ 18844 inputs: []inputInfo{ 18845 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18846 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18847 }, 18848 outputs: []outputInfo{ 18849 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18850 }, 18851 }, 18852 }, 18853 { 18854 name: "MULLW", 18855 argLen: 2, 18856 commutative: true, 18857 resultInArg0: true, 18858 clobberFlags: true, 18859 asm: s390x.AMULLW, 18860 reg: regInfo{ 18861 inputs: []inputInfo{ 18862 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18863 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18864 }, 18865 outputs: []outputInfo{ 18866 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18867 }, 18868 }, 18869 }, 18870 { 18871 name: "MULLDconst", 18872 auxType: auxInt64, 18873 argLen: 1, 18874 resultInArg0: true, 18875 clobberFlags: true, 18876 asm: s390x.AMULLD, 18877 reg: regInfo{ 18878 inputs: []inputInfo{ 18879 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18880 }, 18881 outputs: []outputInfo{ 18882 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18883 }, 18884 }, 18885 }, 18886 { 18887 name: "MULLWconst", 18888 auxType: auxInt32, 18889 argLen: 1, 18890 resultInArg0: true, 18891 clobberFlags: true, 18892 asm: s390x.AMULLW, 18893 reg: regInfo{ 18894 inputs: []inputInfo{ 18895 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18896 }, 18897 outputs: []outputInfo{ 18898 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18899 }, 18900 }, 18901 }, 18902 { 18903 name: "MULLDload", 18904 auxType: auxSymOff, 18905 argLen: 3, 18906 resultInArg0: true, 18907 clobberFlags: true, 18908 faultOnNilArg1: true, 18909 asm: s390x.AMULLD, 18910 reg: regInfo{ 18911 inputs: []inputInfo{ 18912 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18913 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18914 }, 18915 outputs: []outputInfo{ 18916 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18917 }, 18918 }, 18919 }, 18920 { 18921 name: "MULLWload", 18922 auxType: auxSymOff, 18923 argLen: 3, 18924 resultInArg0: true, 18925 clobberFlags: true, 18926 faultOnNilArg1: true, 18927 asm: s390x.AMULLW, 18928 reg: regInfo{ 18929 inputs: []inputInfo{ 18930 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18931 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18932 }, 18933 outputs: []outputInfo{ 18934 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18935 }, 18936 }, 18937 }, 18938 { 18939 name: "MULHD", 18940 argLen: 2, 18941 resultInArg0: true, 18942 clobberFlags: true, 18943 asm: s390x.AMULHD, 18944 reg: regInfo{ 18945 inputs: []inputInfo{ 18946 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18947 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18948 }, 18949 outputs: []outputInfo{ 18950 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18951 }, 18952 }, 18953 }, 18954 { 18955 name: "MULHDU", 18956 argLen: 2, 18957 resultInArg0: true, 18958 clobberFlags: true, 18959 asm: s390x.AMULHDU, 18960 reg: regInfo{ 18961 inputs: []inputInfo{ 18962 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18963 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18964 }, 18965 outputs: []outputInfo{ 18966 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18967 }, 18968 }, 18969 }, 18970 { 18971 name: "DIVD", 18972 argLen: 2, 18973 resultInArg0: true, 18974 clobberFlags: true, 18975 asm: s390x.ADIVD, 18976 reg: regInfo{ 18977 inputs: []inputInfo{ 18978 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18979 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18980 }, 18981 outputs: []outputInfo{ 18982 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18983 }, 18984 }, 18985 }, 18986 { 18987 name: "DIVW", 18988 argLen: 2, 18989 resultInArg0: true, 18990 clobberFlags: true, 18991 asm: s390x.ADIVW, 18992 reg: regInfo{ 18993 inputs: []inputInfo{ 18994 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18995 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18996 }, 18997 outputs: []outputInfo{ 18998 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18999 }, 19000 }, 19001 }, 19002 { 19003 name: "DIVDU", 19004 argLen: 2, 19005 resultInArg0: true, 19006 clobberFlags: true, 19007 asm: s390x.ADIVDU, 19008 reg: regInfo{ 19009 inputs: []inputInfo{ 19010 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19011 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19012 }, 19013 outputs: []outputInfo{ 19014 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19015 }, 19016 }, 19017 }, 19018 { 19019 name: "DIVWU", 19020 argLen: 2, 19021 resultInArg0: true, 19022 clobberFlags: true, 19023 asm: s390x.ADIVWU, 19024 reg: regInfo{ 19025 inputs: []inputInfo{ 19026 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19027 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19028 }, 19029 outputs: []outputInfo{ 19030 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19031 }, 19032 }, 19033 }, 19034 { 19035 name: "MODD", 19036 argLen: 2, 19037 resultInArg0: true, 19038 clobberFlags: true, 19039 asm: s390x.AMODD, 19040 reg: regInfo{ 19041 inputs: []inputInfo{ 19042 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19043 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19044 }, 19045 outputs: []outputInfo{ 19046 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19047 }, 19048 }, 19049 }, 19050 { 19051 name: "MODW", 19052 argLen: 2, 19053 resultInArg0: true, 19054 clobberFlags: true, 19055 asm: s390x.AMODW, 19056 reg: regInfo{ 19057 inputs: []inputInfo{ 19058 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19059 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19060 }, 19061 outputs: []outputInfo{ 19062 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19063 }, 19064 }, 19065 }, 19066 { 19067 name: "MODDU", 19068 argLen: 2, 19069 resultInArg0: true, 19070 clobberFlags: true, 19071 asm: s390x.AMODDU, 19072 reg: regInfo{ 19073 inputs: []inputInfo{ 19074 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19075 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19076 }, 19077 outputs: []outputInfo{ 19078 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19079 }, 19080 }, 19081 }, 19082 { 19083 name: "MODWU", 19084 argLen: 2, 19085 resultInArg0: true, 19086 clobberFlags: true, 19087 asm: s390x.AMODWU, 19088 reg: regInfo{ 19089 inputs: []inputInfo{ 19090 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19091 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19092 }, 19093 outputs: []outputInfo{ 19094 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19095 }, 19096 }, 19097 }, 19098 { 19099 name: "AND", 19100 argLen: 2, 19101 commutative: true, 19102 clobberFlags: true, 19103 asm: s390x.AAND, 19104 reg: regInfo{ 19105 inputs: []inputInfo{ 19106 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19107 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19108 }, 19109 outputs: []outputInfo{ 19110 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19111 }, 19112 }, 19113 }, 19114 { 19115 name: "ANDW", 19116 argLen: 2, 19117 commutative: true, 19118 clobberFlags: true, 19119 asm: s390x.AANDW, 19120 reg: regInfo{ 19121 inputs: []inputInfo{ 19122 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19123 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19124 }, 19125 outputs: []outputInfo{ 19126 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19127 }, 19128 }, 19129 }, 19130 { 19131 name: "ANDconst", 19132 auxType: auxInt64, 19133 argLen: 1, 19134 resultInArg0: true, 19135 clobberFlags: true, 19136 asm: s390x.AAND, 19137 reg: regInfo{ 19138 inputs: []inputInfo{ 19139 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19140 }, 19141 outputs: []outputInfo{ 19142 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19143 }, 19144 }, 19145 }, 19146 { 19147 name: "ANDWconst", 19148 auxType: auxInt32, 19149 argLen: 1, 19150 resultInArg0: true, 19151 clobberFlags: true, 19152 asm: s390x.AANDW, 19153 reg: regInfo{ 19154 inputs: []inputInfo{ 19155 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19156 }, 19157 outputs: []outputInfo{ 19158 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19159 }, 19160 }, 19161 }, 19162 { 19163 name: "ANDload", 19164 auxType: auxSymOff, 19165 argLen: 3, 19166 resultInArg0: true, 19167 clobberFlags: true, 19168 faultOnNilArg1: true, 19169 asm: s390x.AAND, 19170 reg: regInfo{ 19171 inputs: []inputInfo{ 19172 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19173 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19174 }, 19175 outputs: []outputInfo{ 19176 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19177 }, 19178 }, 19179 }, 19180 { 19181 name: "ANDWload", 19182 auxType: auxSymOff, 19183 argLen: 3, 19184 resultInArg0: true, 19185 clobberFlags: true, 19186 faultOnNilArg1: true, 19187 asm: s390x.AANDW, 19188 reg: regInfo{ 19189 inputs: []inputInfo{ 19190 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19191 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19192 }, 19193 outputs: []outputInfo{ 19194 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19195 }, 19196 }, 19197 }, 19198 { 19199 name: "OR", 19200 argLen: 2, 19201 commutative: true, 19202 clobberFlags: true, 19203 asm: s390x.AOR, 19204 reg: regInfo{ 19205 inputs: []inputInfo{ 19206 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19207 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19208 }, 19209 outputs: []outputInfo{ 19210 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19211 }, 19212 }, 19213 }, 19214 { 19215 name: "ORW", 19216 argLen: 2, 19217 commutative: true, 19218 clobberFlags: true, 19219 asm: s390x.AORW, 19220 reg: regInfo{ 19221 inputs: []inputInfo{ 19222 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19223 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19224 }, 19225 outputs: []outputInfo{ 19226 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19227 }, 19228 }, 19229 }, 19230 { 19231 name: "ORconst", 19232 auxType: auxInt64, 19233 argLen: 1, 19234 resultInArg0: true, 19235 clobberFlags: true, 19236 asm: s390x.AOR, 19237 reg: regInfo{ 19238 inputs: []inputInfo{ 19239 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19240 }, 19241 outputs: []outputInfo{ 19242 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19243 }, 19244 }, 19245 }, 19246 { 19247 name: "ORWconst", 19248 auxType: auxInt32, 19249 argLen: 1, 19250 resultInArg0: true, 19251 clobberFlags: true, 19252 asm: s390x.AORW, 19253 reg: regInfo{ 19254 inputs: []inputInfo{ 19255 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19256 }, 19257 outputs: []outputInfo{ 19258 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19259 }, 19260 }, 19261 }, 19262 { 19263 name: "ORload", 19264 auxType: auxSymOff, 19265 argLen: 3, 19266 resultInArg0: true, 19267 clobberFlags: true, 19268 faultOnNilArg1: true, 19269 asm: s390x.AOR, 19270 reg: regInfo{ 19271 inputs: []inputInfo{ 19272 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19273 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19274 }, 19275 outputs: []outputInfo{ 19276 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19277 }, 19278 }, 19279 }, 19280 { 19281 name: "ORWload", 19282 auxType: auxSymOff, 19283 argLen: 3, 19284 resultInArg0: true, 19285 clobberFlags: true, 19286 faultOnNilArg1: true, 19287 asm: s390x.AORW, 19288 reg: regInfo{ 19289 inputs: []inputInfo{ 19290 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19291 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19292 }, 19293 outputs: []outputInfo{ 19294 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19295 }, 19296 }, 19297 }, 19298 { 19299 name: "XOR", 19300 argLen: 2, 19301 commutative: true, 19302 clobberFlags: true, 19303 asm: s390x.AXOR, 19304 reg: regInfo{ 19305 inputs: []inputInfo{ 19306 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19307 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19308 }, 19309 outputs: []outputInfo{ 19310 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19311 }, 19312 }, 19313 }, 19314 { 19315 name: "XORW", 19316 argLen: 2, 19317 commutative: true, 19318 clobberFlags: true, 19319 asm: s390x.AXORW, 19320 reg: regInfo{ 19321 inputs: []inputInfo{ 19322 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19323 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19324 }, 19325 outputs: []outputInfo{ 19326 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19327 }, 19328 }, 19329 }, 19330 { 19331 name: "XORconst", 19332 auxType: auxInt64, 19333 argLen: 1, 19334 resultInArg0: true, 19335 clobberFlags: true, 19336 asm: s390x.AXOR, 19337 reg: regInfo{ 19338 inputs: []inputInfo{ 19339 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19340 }, 19341 outputs: []outputInfo{ 19342 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19343 }, 19344 }, 19345 }, 19346 { 19347 name: "XORWconst", 19348 auxType: auxInt32, 19349 argLen: 1, 19350 resultInArg0: true, 19351 clobberFlags: true, 19352 asm: s390x.AXORW, 19353 reg: regInfo{ 19354 inputs: []inputInfo{ 19355 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19356 }, 19357 outputs: []outputInfo{ 19358 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19359 }, 19360 }, 19361 }, 19362 { 19363 name: "XORload", 19364 auxType: auxSymOff, 19365 argLen: 3, 19366 resultInArg0: true, 19367 clobberFlags: true, 19368 faultOnNilArg1: true, 19369 asm: s390x.AXOR, 19370 reg: regInfo{ 19371 inputs: []inputInfo{ 19372 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19373 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19374 }, 19375 outputs: []outputInfo{ 19376 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19377 }, 19378 }, 19379 }, 19380 { 19381 name: "XORWload", 19382 auxType: auxSymOff, 19383 argLen: 3, 19384 resultInArg0: true, 19385 clobberFlags: true, 19386 faultOnNilArg1: true, 19387 asm: s390x.AXORW, 19388 reg: regInfo{ 19389 inputs: []inputInfo{ 19390 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19391 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19392 }, 19393 outputs: []outputInfo{ 19394 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19395 }, 19396 }, 19397 }, 19398 { 19399 name: "CMP", 19400 argLen: 2, 19401 asm: s390x.ACMP, 19402 reg: regInfo{ 19403 inputs: []inputInfo{ 19404 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19405 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19406 }, 19407 }, 19408 }, 19409 { 19410 name: "CMPW", 19411 argLen: 2, 19412 asm: s390x.ACMPW, 19413 reg: regInfo{ 19414 inputs: []inputInfo{ 19415 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19416 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19417 }, 19418 }, 19419 }, 19420 { 19421 name: "CMPU", 19422 argLen: 2, 19423 asm: s390x.ACMPU, 19424 reg: regInfo{ 19425 inputs: []inputInfo{ 19426 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19427 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19428 }, 19429 }, 19430 }, 19431 { 19432 name: "CMPWU", 19433 argLen: 2, 19434 asm: s390x.ACMPWU, 19435 reg: regInfo{ 19436 inputs: []inputInfo{ 19437 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19438 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19439 }, 19440 }, 19441 }, 19442 { 19443 name: "CMPconst", 19444 auxType: auxInt64, 19445 argLen: 1, 19446 asm: s390x.ACMP, 19447 reg: regInfo{ 19448 inputs: []inputInfo{ 19449 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19450 }, 19451 }, 19452 }, 19453 { 19454 name: "CMPWconst", 19455 auxType: auxInt32, 19456 argLen: 1, 19457 asm: s390x.ACMPW, 19458 reg: regInfo{ 19459 inputs: []inputInfo{ 19460 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19461 }, 19462 }, 19463 }, 19464 { 19465 name: "CMPUconst", 19466 auxType: auxInt64, 19467 argLen: 1, 19468 asm: s390x.ACMPU, 19469 reg: regInfo{ 19470 inputs: []inputInfo{ 19471 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19472 }, 19473 }, 19474 }, 19475 { 19476 name: "CMPWUconst", 19477 auxType: auxInt32, 19478 argLen: 1, 19479 asm: s390x.ACMPWU, 19480 reg: regInfo{ 19481 inputs: []inputInfo{ 19482 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19483 }, 19484 }, 19485 }, 19486 { 19487 name: "FCMPS", 19488 argLen: 2, 19489 asm: s390x.ACEBR, 19490 reg: regInfo{ 19491 inputs: []inputInfo{ 19492 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19493 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19494 }, 19495 }, 19496 }, 19497 { 19498 name: "FCMP", 19499 argLen: 2, 19500 asm: s390x.AFCMPU, 19501 reg: regInfo{ 19502 inputs: []inputInfo{ 19503 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19504 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19505 }, 19506 }, 19507 }, 19508 { 19509 name: "SLD", 19510 argLen: 2, 19511 asm: s390x.ASLD, 19512 reg: regInfo{ 19513 inputs: []inputInfo{ 19514 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19515 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19516 }, 19517 outputs: []outputInfo{ 19518 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19519 }, 19520 }, 19521 }, 19522 { 19523 name: "SLW", 19524 argLen: 2, 19525 asm: s390x.ASLW, 19526 reg: regInfo{ 19527 inputs: []inputInfo{ 19528 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19529 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19530 }, 19531 outputs: []outputInfo{ 19532 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19533 }, 19534 }, 19535 }, 19536 { 19537 name: "SLDconst", 19538 auxType: auxInt64, 19539 argLen: 1, 19540 asm: s390x.ASLD, 19541 reg: regInfo{ 19542 inputs: []inputInfo{ 19543 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19544 }, 19545 outputs: []outputInfo{ 19546 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19547 }, 19548 }, 19549 }, 19550 { 19551 name: "SLWconst", 19552 auxType: auxInt32, 19553 argLen: 1, 19554 asm: s390x.ASLW, 19555 reg: regInfo{ 19556 inputs: []inputInfo{ 19557 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19558 }, 19559 outputs: []outputInfo{ 19560 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19561 }, 19562 }, 19563 }, 19564 { 19565 name: "SRD", 19566 argLen: 2, 19567 asm: s390x.ASRD, 19568 reg: regInfo{ 19569 inputs: []inputInfo{ 19570 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19571 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19572 }, 19573 outputs: []outputInfo{ 19574 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19575 }, 19576 }, 19577 }, 19578 { 19579 name: "SRW", 19580 argLen: 2, 19581 asm: s390x.ASRW, 19582 reg: regInfo{ 19583 inputs: []inputInfo{ 19584 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19585 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19586 }, 19587 outputs: []outputInfo{ 19588 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19589 }, 19590 }, 19591 }, 19592 { 19593 name: "SRDconst", 19594 auxType: auxInt64, 19595 argLen: 1, 19596 asm: s390x.ASRD, 19597 reg: regInfo{ 19598 inputs: []inputInfo{ 19599 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19600 }, 19601 outputs: []outputInfo{ 19602 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19603 }, 19604 }, 19605 }, 19606 { 19607 name: "SRWconst", 19608 auxType: auxInt32, 19609 argLen: 1, 19610 asm: s390x.ASRW, 19611 reg: regInfo{ 19612 inputs: []inputInfo{ 19613 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19614 }, 19615 outputs: []outputInfo{ 19616 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19617 }, 19618 }, 19619 }, 19620 { 19621 name: "SRAD", 19622 argLen: 2, 19623 clobberFlags: true, 19624 asm: s390x.ASRAD, 19625 reg: regInfo{ 19626 inputs: []inputInfo{ 19627 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19628 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19629 }, 19630 outputs: []outputInfo{ 19631 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19632 }, 19633 }, 19634 }, 19635 { 19636 name: "SRAW", 19637 argLen: 2, 19638 clobberFlags: true, 19639 asm: s390x.ASRAW, 19640 reg: regInfo{ 19641 inputs: []inputInfo{ 19642 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19643 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19644 }, 19645 outputs: []outputInfo{ 19646 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19647 }, 19648 }, 19649 }, 19650 { 19651 name: "SRADconst", 19652 auxType: auxInt64, 19653 argLen: 1, 19654 clobberFlags: true, 19655 asm: s390x.ASRAD, 19656 reg: regInfo{ 19657 inputs: []inputInfo{ 19658 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19659 }, 19660 outputs: []outputInfo{ 19661 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19662 }, 19663 }, 19664 }, 19665 { 19666 name: "SRAWconst", 19667 auxType: auxInt32, 19668 argLen: 1, 19669 clobberFlags: true, 19670 asm: s390x.ASRAW, 19671 reg: regInfo{ 19672 inputs: []inputInfo{ 19673 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19674 }, 19675 outputs: []outputInfo{ 19676 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19677 }, 19678 }, 19679 }, 19680 { 19681 name: "RLLGconst", 19682 auxType: auxInt64, 19683 argLen: 1, 19684 asm: s390x.ARLLG, 19685 reg: regInfo{ 19686 inputs: []inputInfo{ 19687 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19688 }, 19689 outputs: []outputInfo{ 19690 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19691 }, 19692 }, 19693 }, 19694 { 19695 name: "RLLconst", 19696 auxType: auxInt32, 19697 argLen: 1, 19698 asm: s390x.ARLL, 19699 reg: regInfo{ 19700 inputs: []inputInfo{ 19701 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19702 }, 19703 outputs: []outputInfo{ 19704 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19705 }, 19706 }, 19707 }, 19708 { 19709 name: "NEG", 19710 argLen: 1, 19711 clobberFlags: true, 19712 asm: s390x.ANEG, 19713 reg: regInfo{ 19714 inputs: []inputInfo{ 19715 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19716 }, 19717 outputs: []outputInfo{ 19718 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19719 }, 19720 }, 19721 }, 19722 { 19723 name: "NEGW", 19724 argLen: 1, 19725 clobberFlags: true, 19726 asm: s390x.ANEGW, 19727 reg: regInfo{ 19728 inputs: []inputInfo{ 19729 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19730 }, 19731 outputs: []outputInfo{ 19732 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19733 }, 19734 }, 19735 }, 19736 { 19737 name: "NOT", 19738 argLen: 1, 19739 resultInArg0: true, 19740 clobberFlags: true, 19741 reg: regInfo{ 19742 inputs: []inputInfo{ 19743 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19744 }, 19745 outputs: []outputInfo{ 19746 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19747 }, 19748 }, 19749 }, 19750 { 19751 name: "NOTW", 19752 argLen: 1, 19753 resultInArg0: true, 19754 clobberFlags: true, 19755 reg: regInfo{ 19756 inputs: []inputInfo{ 19757 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19758 }, 19759 outputs: []outputInfo{ 19760 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19761 }, 19762 }, 19763 }, 19764 { 19765 name: "FSQRT", 19766 argLen: 1, 19767 asm: s390x.AFSQRT, 19768 reg: regInfo{ 19769 inputs: []inputInfo{ 19770 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19771 }, 19772 outputs: []outputInfo{ 19773 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19774 }, 19775 }, 19776 }, 19777 { 19778 name: "SUBEcarrymask", 19779 argLen: 1, 19780 asm: s390x.ASUBE, 19781 reg: regInfo{ 19782 outputs: []outputInfo{ 19783 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19784 }, 19785 }, 19786 }, 19787 { 19788 name: "SUBEWcarrymask", 19789 argLen: 1, 19790 asm: s390x.ASUBE, 19791 reg: regInfo{ 19792 outputs: []outputInfo{ 19793 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19794 }, 19795 }, 19796 }, 19797 { 19798 name: "MOVDEQ", 19799 argLen: 3, 19800 resultInArg0: true, 19801 asm: s390x.AMOVDEQ, 19802 reg: regInfo{ 19803 inputs: []inputInfo{ 19804 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19805 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19806 }, 19807 outputs: []outputInfo{ 19808 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19809 }, 19810 }, 19811 }, 19812 { 19813 name: "MOVDNE", 19814 argLen: 3, 19815 resultInArg0: true, 19816 asm: s390x.AMOVDNE, 19817 reg: regInfo{ 19818 inputs: []inputInfo{ 19819 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19820 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19821 }, 19822 outputs: []outputInfo{ 19823 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19824 }, 19825 }, 19826 }, 19827 { 19828 name: "MOVDLT", 19829 argLen: 3, 19830 resultInArg0: true, 19831 asm: s390x.AMOVDLT, 19832 reg: regInfo{ 19833 inputs: []inputInfo{ 19834 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19835 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19836 }, 19837 outputs: []outputInfo{ 19838 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19839 }, 19840 }, 19841 }, 19842 { 19843 name: "MOVDLE", 19844 argLen: 3, 19845 resultInArg0: true, 19846 asm: s390x.AMOVDLE, 19847 reg: regInfo{ 19848 inputs: []inputInfo{ 19849 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19850 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19851 }, 19852 outputs: []outputInfo{ 19853 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19854 }, 19855 }, 19856 }, 19857 { 19858 name: "MOVDGT", 19859 argLen: 3, 19860 resultInArg0: true, 19861 asm: s390x.AMOVDGT, 19862 reg: regInfo{ 19863 inputs: []inputInfo{ 19864 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19865 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19866 }, 19867 outputs: []outputInfo{ 19868 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19869 }, 19870 }, 19871 }, 19872 { 19873 name: "MOVDGE", 19874 argLen: 3, 19875 resultInArg0: true, 19876 asm: s390x.AMOVDGE, 19877 reg: regInfo{ 19878 inputs: []inputInfo{ 19879 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19880 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19881 }, 19882 outputs: []outputInfo{ 19883 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19884 }, 19885 }, 19886 }, 19887 { 19888 name: "MOVDGTnoinv", 19889 argLen: 3, 19890 resultInArg0: true, 19891 asm: s390x.AMOVDGT, 19892 reg: regInfo{ 19893 inputs: []inputInfo{ 19894 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19895 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19896 }, 19897 outputs: []outputInfo{ 19898 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19899 }, 19900 }, 19901 }, 19902 { 19903 name: "MOVDGEnoinv", 19904 argLen: 3, 19905 resultInArg0: true, 19906 asm: s390x.AMOVDGE, 19907 reg: regInfo{ 19908 inputs: []inputInfo{ 19909 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19910 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19911 }, 19912 outputs: []outputInfo{ 19913 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19914 }, 19915 }, 19916 }, 19917 { 19918 name: "MOVBreg", 19919 argLen: 1, 19920 asm: s390x.AMOVB, 19921 reg: regInfo{ 19922 inputs: []inputInfo{ 19923 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19924 }, 19925 outputs: []outputInfo{ 19926 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19927 }, 19928 }, 19929 }, 19930 { 19931 name: "MOVBZreg", 19932 argLen: 1, 19933 asm: s390x.AMOVBZ, 19934 reg: regInfo{ 19935 inputs: []inputInfo{ 19936 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19937 }, 19938 outputs: []outputInfo{ 19939 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19940 }, 19941 }, 19942 }, 19943 { 19944 name: "MOVHreg", 19945 argLen: 1, 19946 asm: s390x.AMOVH, 19947 reg: regInfo{ 19948 inputs: []inputInfo{ 19949 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19950 }, 19951 outputs: []outputInfo{ 19952 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19953 }, 19954 }, 19955 }, 19956 { 19957 name: "MOVHZreg", 19958 argLen: 1, 19959 asm: s390x.AMOVHZ, 19960 reg: regInfo{ 19961 inputs: []inputInfo{ 19962 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19963 }, 19964 outputs: []outputInfo{ 19965 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19966 }, 19967 }, 19968 }, 19969 { 19970 name: "MOVWreg", 19971 argLen: 1, 19972 asm: s390x.AMOVW, 19973 reg: regInfo{ 19974 inputs: []inputInfo{ 19975 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19976 }, 19977 outputs: []outputInfo{ 19978 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19979 }, 19980 }, 19981 }, 19982 { 19983 name: "MOVWZreg", 19984 argLen: 1, 19985 asm: s390x.AMOVWZ, 19986 reg: regInfo{ 19987 inputs: []inputInfo{ 19988 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19989 }, 19990 outputs: []outputInfo{ 19991 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19992 }, 19993 }, 19994 }, 19995 { 19996 name: "MOVDreg", 19997 argLen: 1, 19998 asm: s390x.AMOVD, 19999 reg: regInfo{ 20000 inputs: []inputInfo{ 20001 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20002 }, 20003 outputs: []outputInfo{ 20004 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20005 }, 20006 }, 20007 }, 20008 { 20009 name: "MOVDnop", 20010 argLen: 1, 20011 resultInArg0: true, 20012 reg: regInfo{ 20013 inputs: []inputInfo{ 20014 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20015 }, 20016 outputs: []outputInfo{ 20017 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20018 }, 20019 }, 20020 }, 20021 { 20022 name: "MOVDconst", 20023 auxType: auxInt64, 20024 argLen: 0, 20025 rematerializeable: true, 20026 asm: s390x.AMOVD, 20027 reg: regInfo{ 20028 outputs: []outputInfo{ 20029 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20030 }, 20031 }, 20032 }, 20033 { 20034 name: "CFDBRA", 20035 argLen: 1, 20036 asm: s390x.ACFDBRA, 20037 reg: regInfo{ 20038 inputs: []inputInfo{ 20039 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20040 }, 20041 outputs: []outputInfo{ 20042 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20043 }, 20044 }, 20045 }, 20046 { 20047 name: "CGDBRA", 20048 argLen: 1, 20049 asm: s390x.ACGDBRA, 20050 reg: regInfo{ 20051 inputs: []inputInfo{ 20052 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20053 }, 20054 outputs: []outputInfo{ 20055 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20056 }, 20057 }, 20058 }, 20059 { 20060 name: "CFEBRA", 20061 argLen: 1, 20062 asm: s390x.ACFEBRA, 20063 reg: regInfo{ 20064 inputs: []inputInfo{ 20065 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20066 }, 20067 outputs: []outputInfo{ 20068 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20069 }, 20070 }, 20071 }, 20072 { 20073 name: "CGEBRA", 20074 argLen: 1, 20075 asm: s390x.ACGEBRA, 20076 reg: regInfo{ 20077 inputs: []inputInfo{ 20078 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20079 }, 20080 outputs: []outputInfo{ 20081 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20082 }, 20083 }, 20084 }, 20085 { 20086 name: "CEFBRA", 20087 argLen: 1, 20088 asm: s390x.ACEFBRA, 20089 reg: regInfo{ 20090 inputs: []inputInfo{ 20091 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20092 }, 20093 outputs: []outputInfo{ 20094 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20095 }, 20096 }, 20097 }, 20098 { 20099 name: "CDFBRA", 20100 argLen: 1, 20101 asm: s390x.ACDFBRA, 20102 reg: regInfo{ 20103 inputs: []inputInfo{ 20104 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20105 }, 20106 outputs: []outputInfo{ 20107 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20108 }, 20109 }, 20110 }, 20111 { 20112 name: "CEGBRA", 20113 argLen: 1, 20114 asm: s390x.ACEGBRA, 20115 reg: regInfo{ 20116 inputs: []inputInfo{ 20117 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20118 }, 20119 outputs: []outputInfo{ 20120 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20121 }, 20122 }, 20123 }, 20124 { 20125 name: "CDGBRA", 20126 argLen: 1, 20127 asm: s390x.ACDGBRA, 20128 reg: regInfo{ 20129 inputs: []inputInfo{ 20130 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20131 }, 20132 outputs: []outputInfo{ 20133 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20134 }, 20135 }, 20136 }, 20137 { 20138 name: "LEDBR", 20139 argLen: 1, 20140 asm: s390x.ALEDBR, 20141 reg: regInfo{ 20142 inputs: []inputInfo{ 20143 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20144 }, 20145 outputs: []outputInfo{ 20146 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20147 }, 20148 }, 20149 }, 20150 { 20151 name: "LDEBR", 20152 argLen: 1, 20153 asm: s390x.ALDEBR, 20154 reg: regInfo{ 20155 inputs: []inputInfo{ 20156 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20157 }, 20158 outputs: []outputInfo{ 20159 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20160 }, 20161 }, 20162 }, 20163 { 20164 name: "MOVDaddr", 20165 auxType: auxSymOff, 20166 argLen: 1, 20167 rematerializeable: true, 20168 clobberFlags: true, 20169 reg: regInfo{ 20170 inputs: []inputInfo{ 20171 {0, 4295000064}, // SP SB 20172 }, 20173 outputs: []outputInfo{ 20174 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20175 }, 20176 }, 20177 }, 20178 { 20179 name: "MOVDaddridx", 20180 auxType: auxSymOff, 20181 argLen: 2, 20182 clobberFlags: true, 20183 reg: regInfo{ 20184 inputs: []inputInfo{ 20185 {0, 4295000064}, // SP SB 20186 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20187 }, 20188 outputs: []outputInfo{ 20189 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20190 }, 20191 }, 20192 }, 20193 { 20194 name: "MOVBZload", 20195 auxType: auxSymOff, 20196 argLen: 2, 20197 clobberFlags: true, 20198 faultOnNilArg0: true, 20199 asm: s390x.AMOVBZ, 20200 reg: regInfo{ 20201 inputs: []inputInfo{ 20202 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20203 }, 20204 outputs: []outputInfo{ 20205 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20206 }, 20207 }, 20208 }, 20209 { 20210 name: "MOVBload", 20211 auxType: auxSymOff, 20212 argLen: 2, 20213 clobberFlags: true, 20214 faultOnNilArg0: true, 20215 asm: s390x.AMOVB, 20216 reg: regInfo{ 20217 inputs: []inputInfo{ 20218 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20219 }, 20220 outputs: []outputInfo{ 20221 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20222 }, 20223 }, 20224 }, 20225 { 20226 name: "MOVHZload", 20227 auxType: auxSymOff, 20228 argLen: 2, 20229 clobberFlags: true, 20230 faultOnNilArg0: true, 20231 asm: s390x.AMOVHZ, 20232 reg: regInfo{ 20233 inputs: []inputInfo{ 20234 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20235 }, 20236 outputs: []outputInfo{ 20237 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20238 }, 20239 }, 20240 }, 20241 { 20242 name: "MOVHload", 20243 auxType: auxSymOff, 20244 argLen: 2, 20245 clobberFlags: true, 20246 faultOnNilArg0: true, 20247 asm: s390x.AMOVH, 20248 reg: regInfo{ 20249 inputs: []inputInfo{ 20250 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20251 }, 20252 outputs: []outputInfo{ 20253 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20254 }, 20255 }, 20256 }, 20257 { 20258 name: "MOVWZload", 20259 auxType: auxSymOff, 20260 argLen: 2, 20261 clobberFlags: true, 20262 faultOnNilArg0: true, 20263 asm: s390x.AMOVWZ, 20264 reg: regInfo{ 20265 inputs: []inputInfo{ 20266 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20267 }, 20268 outputs: []outputInfo{ 20269 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20270 }, 20271 }, 20272 }, 20273 { 20274 name: "MOVWload", 20275 auxType: auxSymOff, 20276 argLen: 2, 20277 clobberFlags: true, 20278 faultOnNilArg0: true, 20279 asm: s390x.AMOVW, 20280 reg: regInfo{ 20281 inputs: []inputInfo{ 20282 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20283 }, 20284 outputs: []outputInfo{ 20285 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20286 }, 20287 }, 20288 }, 20289 { 20290 name: "MOVDload", 20291 auxType: auxSymOff, 20292 argLen: 2, 20293 clobberFlags: true, 20294 faultOnNilArg0: true, 20295 asm: s390x.AMOVD, 20296 reg: regInfo{ 20297 inputs: []inputInfo{ 20298 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20299 }, 20300 outputs: []outputInfo{ 20301 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20302 }, 20303 }, 20304 }, 20305 { 20306 name: "MOVWBR", 20307 argLen: 1, 20308 asm: s390x.AMOVWBR, 20309 reg: regInfo{ 20310 inputs: []inputInfo{ 20311 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20312 }, 20313 outputs: []outputInfo{ 20314 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20315 }, 20316 }, 20317 }, 20318 { 20319 name: "MOVDBR", 20320 argLen: 1, 20321 asm: s390x.AMOVDBR, 20322 reg: regInfo{ 20323 inputs: []inputInfo{ 20324 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20325 }, 20326 outputs: []outputInfo{ 20327 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20328 }, 20329 }, 20330 }, 20331 { 20332 name: "MOVHBRload", 20333 auxType: auxSymOff, 20334 argLen: 2, 20335 clobberFlags: true, 20336 faultOnNilArg0: true, 20337 asm: s390x.AMOVHBR, 20338 reg: regInfo{ 20339 inputs: []inputInfo{ 20340 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20341 }, 20342 outputs: []outputInfo{ 20343 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20344 }, 20345 }, 20346 }, 20347 { 20348 name: "MOVWBRload", 20349 auxType: auxSymOff, 20350 argLen: 2, 20351 clobberFlags: true, 20352 faultOnNilArg0: true, 20353 asm: s390x.AMOVWBR, 20354 reg: regInfo{ 20355 inputs: []inputInfo{ 20356 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20357 }, 20358 outputs: []outputInfo{ 20359 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20360 }, 20361 }, 20362 }, 20363 { 20364 name: "MOVDBRload", 20365 auxType: auxSymOff, 20366 argLen: 2, 20367 clobberFlags: true, 20368 faultOnNilArg0: true, 20369 asm: s390x.AMOVDBR, 20370 reg: regInfo{ 20371 inputs: []inputInfo{ 20372 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20373 }, 20374 outputs: []outputInfo{ 20375 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20376 }, 20377 }, 20378 }, 20379 { 20380 name: "MOVBstore", 20381 auxType: auxSymOff, 20382 argLen: 3, 20383 clobberFlags: true, 20384 faultOnNilArg0: true, 20385 asm: s390x.AMOVB, 20386 reg: regInfo{ 20387 inputs: []inputInfo{ 20388 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20389 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20390 }, 20391 }, 20392 }, 20393 { 20394 name: "MOVHstore", 20395 auxType: auxSymOff, 20396 argLen: 3, 20397 clobberFlags: true, 20398 faultOnNilArg0: true, 20399 asm: s390x.AMOVH, 20400 reg: regInfo{ 20401 inputs: []inputInfo{ 20402 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20403 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20404 }, 20405 }, 20406 }, 20407 { 20408 name: "MOVWstore", 20409 auxType: auxSymOff, 20410 argLen: 3, 20411 clobberFlags: true, 20412 faultOnNilArg0: true, 20413 asm: s390x.AMOVW, 20414 reg: regInfo{ 20415 inputs: []inputInfo{ 20416 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20417 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20418 }, 20419 }, 20420 }, 20421 { 20422 name: "MOVDstore", 20423 auxType: auxSymOff, 20424 argLen: 3, 20425 clobberFlags: true, 20426 faultOnNilArg0: true, 20427 asm: s390x.AMOVD, 20428 reg: regInfo{ 20429 inputs: []inputInfo{ 20430 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20431 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20432 }, 20433 }, 20434 }, 20435 { 20436 name: "MOVHBRstore", 20437 auxType: auxSymOff, 20438 argLen: 3, 20439 clobberFlags: true, 20440 faultOnNilArg0: true, 20441 asm: s390x.AMOVHBR, 20442 reg: regInfo{ 20443 inputs: []inputInfo{ 20444 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20445 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20446 }, 20447 }, 20448 }, 20449 { 20450 name: "MOVWBRstore", 20451 auxType: auxSymOff, 20452 argLen: 3, 20453 clobberFlags: true, 20454 faultOnNilArg0: true, 20455 asm: s390x.AMOVWBR, 20456 reg: regInfo{ 20457 inputs: []inputInfo{ 20458 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20459 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20460 }, 20461 }, 20462 }, 20463 { 20464 name: "MOVDBRstore", 20465 auxType: auxSymOff, 20466 argLen: 3, 20467 clobberFlags: true, 20468 faultOnNilArg0: true, 20469 asm: s390x.AMOVDBR, 20470 reg: regInfo{ 20471 inputs: []inputInfo{ 20472 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20473 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20474 }, 20475 }, 20476 }, 20477 { 20478 name: "MVC", 20479 auxType: auxSymValAndOff, 20480 argLen: 3, 20481 clobberFlags: true, 20482 faultOnNilArg0: true, 20483 faultOnNilArg1: true, 20484 asm: s390x.AMVC, 20485 reg: regInfo{ 20486 inputs: []inputInfo{ 20487 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20488 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20489 }, 20490 }, 20491 }, 20492 { 20493 name: "MOVBZloadidx", 20494 auxType: auxSymOff, 20495 argLen: 3, 20496 clobberFlags: true, 20497 asm: s390x.AMOVBZ, 20498 reg: regInfo{ 20499 inputs: []inputInfo{ 20500 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20501 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20502 }, 20503 outputs: []outputInfo{ 20504 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20505 }, 20506 }, 20507 }, 20508 { 20509 name: "MOVHZloadidx", 20510 auxType: auxSymOff, 20511 argLen: 3, 20512 clobberFlags: true, 20513 asm: s390x.AMOVHZ, 20514 reg: regInfo{ 20515 inputs: []inputInfo{ 20516 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20517 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20518 }, 20519 outputs: []outputInfo{ 20520 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20521 }, 20522 }, 20523 }, 20524 { 20525 name: "MOVWZloadidx", 20526 auxType: auxSymOff, 20527 argLen: 3, 20528 clobberFlags: true, 20529 asm: s390x.AMOVWZ, 20530 reg: regInfo{ 20531 inputs: []inputInfo{ 20532 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20533 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20534 }, 20535 outputs: []outputInfo{ 20536 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20537 }, 20538 }, 20539 }, 20540 { 20541 name: "MOVDloadidx", 20542 auxType: auxSymOff, 20543 argLen: 3, 20544 clobberFlags: true, 20545 asm: s390x.AMOVD, 20546 reg: regInfo{ 20547 inputs: []inputInfo{ 20548 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20549 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20550 }, 20551 outputs: []outputInfo{ 20552 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20553 }, 20554 }, 20555 }, 20556 { 20557 name: "MOVHBRloadidx", 20558 auxType: auxSymOff, 20559 argLen: 3, 20560 clobberFlags: true, 20561 asm: s390x.AMOVHBR, 20562 reg: regInfo{ 20563 inputs: []inputInfo{ 20564 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20565 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20566 }, 20567 outputs: []outputInfo{ 20568 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20569 }, 20570 }, 20571 }, 20572 { 20573 name: "MOVWBRloadidx", 20574 auxType: auxSymOff, 20575 argLen: 3, 20576 clobberFlags: true, 20577 asm: s390x.AMOVWBR, 20578 reg: regInfo{ 20579 inputs: []inputInfo{ 20580 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20581 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20582 }, 20583 outputs: []outputInfo{ 20584 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20585 }, 20586 }, 20587 }, 20588 { 20589 name: "MOVDBRloadidx", 20590 auxType: auxSymOff, 20591 argLen: 3, 20592 clobberFlags: true, 20593 asm: s390x.AMOVDBR, 20594 reg: regInfo{ 20595 inputs: []inputInfo{ 20596 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20597 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20598 }, 20599 outputs: []outputInfo{ 20600 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20601 }, 20602 }, 20603 }, 20604 { 20605 name: "MOVBstoreidx", 20606 auxType: auxSymOff, 20607 argLen: 4, 20608 clobberFlags: true, 20609 asm: s390x.AMOVB, 20610 reg: regInfo{ 20611 inputs: []inputInfo{ 20612 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20613 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20614 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20615 }, 20616 }, 20617 }, 20618 { 20619 name: "MOVHstoreidx", 20620 auxType: auxSymOff, 20621 argLen: 4, 20622 clobberFlags: true, 20623 asm: s390x.AMOVH, 20624 reg: regInfo{ 20625 inputs: []inputInfo{ 20626 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20627 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20628 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20629 }, 20630 }, 20631 }, 20632 { 20633 name: "MOVWstoreidx", 20634 auxType: auxSymOff, 20635 argLen: 4, 20636 clobberFlags: true, 20637 asm: s390x.AMOVW, 20638 reg: regInfo{ 20639 inputs: []inputInfo{ 20640 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20641 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20642 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20643 }, 20644 }, 20645 }, 20646 { 20647 name: "MOVDstoreidx", 20648 auxType: auxSymOff, 20649 argLen: 4, 20650 clobberFlags: true, 20651 asm: s390x.AMOVD, 20652 reg: regInfo{ 20653 inputs: []inputInfo{ 20654 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20655 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20656 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20657 }, 20658 }, 20659 }, 20660 { 20661 name: "MOVHBRstoreidx", 20662 auxType: auxSymOff, 20663 argLen: 4, 20664 clobberFlags: true, 20665 asm: s390x.AMOVHBR, 20666 reg: regInfo{ 20667 inputs: []inputInfo{ 20668 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20669 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20670 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20671 }, 20672 }, 20673 }, 20674 { 20675 name: "MOVWBRstoreidx", 20676 auxType: auxSymOff, 20677 argLen: 4, 20678 clobberFlags: true, 20679 asm: s390x.AMOVWBR, 20680 reg: regInfo{ 20681 inputs: []inputInfo{ 20682 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20683 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20684 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20685 }, 20686 }, 20687 }, 20688 { 20689 name: "MOVDBRstoreidx", 20690 auxType: auxSymOff, 20691 argLen: 4, 20692 clobberFlags: true, 20693 asm: s390x.AMOVDBR, 20694 reg: regInfo{ 20695 inputs: []inputInfo{ 20696 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20697 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20698 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20699 }, 20700 }, 20701 }, 20702 { 20703 name: "MOVBstoreconst", 20704 auxType: auxSymValAndOff, 20705 argLen: 2, 20706 clobberFlags: true, 20707 faultOnNilArg0: true, 20708 asm: s390x.AMOVB, 20709 reg: regInfo{ 20710 inputs: []inputInfo{ 20711 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20712 }, 20713 }, 20714 }, 20715 { 20716 name: "MOVHstoreconst", 20717 auxType: auxSymValAndOff, 20718 argLen: 2, 20719 clobberFlags: true, 20720 faultOnNilArg0: true, 20721 asm: s390x.AMOVH, 20722 reg: regInfo{ 20723 inputs: []inputInfo{ 20724 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20725 }, 20726 }, 20727 }, 20728 { 20729 name: "MOVWstoreconst", 20730 auxType: auxSymValAndOff, 20731 argLen: 2, 20732 clobberFlags: true, 20733 faultOnNilArg0: true, 20734 asm: s390x.AMOVW, 20735 reg: regInfo{ 20736 inputs: []inputInfo{ 20737 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20738 }, 20739 }, 20740 }, 20741 { 20742 name: "MOVDstoreconst", 20743 auxType: auxSymValAndOff, 20744 argLen: 2, 20745 clobberFlags: true, 20746 faultOnNilArg0: true, 20747 asm: s390x.AMOVD, 20748 reg: regInfo{ 20749 inputs: []inputInfo{ 20750 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20751 }, 20752 }, 20753 }, 20754 { 20755 name: "CLEAR", 20756 auxType: auxSymValAndOff, 20757 argLen: 2, 20758 clobberFlags: true, 20759 faultOnNilArg0: true, 20760 asm: s390x.ACLEAR, 20761 reg: regInfo{ 20762 inputs: []inputInfo{ 20763 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20764 }, 20765 }, 20766 }, 20767 { 20768 name: "CALLstatic", 20769 auxType: auxSymOff, 20770 argLen: 1, 20771 clobberFlags: true, 20772 call: true, 20773 reg: regInfo{ 20774 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20775 }, 20776 }, 20777 { 20778 name: "CALLclosure", 20779 auxType: auxInt64, 20780 argLen: 3, 20781 clobberFlags: true, 20782 call: true, 20783 reg: regInfo{ 20784 inputs: []inputInfo{ 20785 {1, 4096}, // R12 20786 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20787 }, 20788 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20789 }, 20790 }, 20791 { 20792 name: "CALLdefer", 20793 auxType: auxInt64, 20794 argLen: 1, 20795 clobberFlags: true, 20796 call: true, 20797 reg: regInfo{ 20798 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20799 }, 20800 }, 20801 { 20802 name: "CALLgo", 20803 auxType: auxInt64, 20804 argLen: 1, 20805 clobberFlags: true, 20806 call: true, 20807 reg: regInfo{ 20808 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20809 }, 20810 }, 20811 { 20812 name: "CALLinter", 20813 auxType: auxInt64, 20814 argLen: 2, 20815 clobberFlags: true, 20816 call: true, 20817 reg: regInfo{ 20818 inputs: []inputInfo{ 20819 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20820 }, 20821 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20822 }, 20823 }, 20824 { 20825 name: "InvertFlags", 20826 argLen: 1, 20827 reg: regInfo{}, 20828 }, 20829 { 20830 name: "LoweredGetG", 20831 argLen: 1, 20832 reg: regInfo{ 20833 outputs: []outputInfo{ 20834 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20835 }, 20836 }, 20837 }, 20838 { 20839 name: "LoweredGetClosurePtr", 20840 argLen: 0, 20841 reg: regInfo{ 20842 outputs: []outputInfo{ 20843 {0, 4096}, // R12 20844 }, 20845 }, 20846 }, 20847 { 20848 name: "LoweredNilCheck", 20849 argLen: 2, 20850 clobberFlags: true, 20851 nilCheck: true, 20852 faultOnNilArg0: true, 20853 reg: regInfo{ 20854 inputs: []inputInfo{ 20855 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20856 }, 20857 }, 20858 }, 20859 { 20860 name: "MOVDconvert", 20861 argLen: 2, 20862 asm: s390x.AMOVD, 20863 reg: regInfo{ 20864 inputs: []inputInfo{ 20865 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20866 }, 20867 outputs: []outputInfo{ 20868 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20869 }, 20870 }, 20871 }, 20872 { 20873 name: "FlagEQ", 20874 argLen: 0, 20875 reg: regInfo{}, 20876 }, 20877 { 20878 name: "FlagLT", 20879 argLen: 0, 20880 reg: regInfo{}, 20881 }, 20882 { 20883 name: "FlagGT", 20884 argLen: 0, 20885 reg: regInfo{}, 20886 }, 20887 { 20888 name: "MOVWZatomicload", 20889 auxType: auxSymOff, 20890 argLen: 2, 20891 faultOnNilArg0: true, 20892 asm: s390x.AMOVWZ, 20893 reg: regInfo{ 20894 inputs: []inputInfo{ 20895 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20896 }, 20897 outputs: []outputInfo{ 20898 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20899 }, 20900 }, 20901 }, 20902 { 20903 name: "MOVDatomicload", 20904 auxType: auxSymOff, 20905 argLen: 2, 20906 faultOnNilArg0: true, 20907 asm: s390x.AMOVD, 20908 reg: regInfo{ 20909 inputs: []inputInfo{ 20910 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20911 }, 20912 outputs: []outputInfo{ 20913 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20914 }, 20915 }, 20916 }, 20917 { 20918 name: "MOVWatomicstore", 20919 auxType: auxSymOff, 20920 argLen: 3, 20921 clobberFlags: true, 20922 faultOnNilArg0: true, 20923 asm: s390x.AMOVW, 20924 reg: regInfo{ 20925 inputs: []inputInfo{ 20926 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20927 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20928 }, 20929 }, 20930 }, 20931 { 20932 name: "MOVDatomicstore", 20933 auxType: auxSymOff, 20934 argLen: 3, 20935 clobberFlags: true, 20936 faultOnNilArg0: true, 20937 asm: s390x.AMOVD, 20938 reg: regInfo{ 20939 inputs: []inputInfo{ 20940 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20941 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20942 }, 20943 }, 20944 }, 20945 { 20946 name: "LAA", 20947 auxType: auxSymOff, 20948 argLen: 3, 20949 faultOnNilArg0: true, 20950 asm: s390x.ALAA, 20951 reg: regInfo{ 20952 inputs: []inputInfo{ 20953 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20954 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20955 }, 20956 outputs: []outputInfo{ 20957 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20958 }, 20959 }, 20960 }, 20961 { 20962 name: "LAAG", 20963 auxType: auxSymOff, 20964 argLen: 3, 20965 faultOnNilArg0: true, 20966 asm: s390x.ALAAG, 20967 reg: regInfo{ 20968 inputs: []inputInfo{ 20969 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20970 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20971 }, 20972 outputs: []outputInfo{ 20973 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20974 }, 20975 }, 20976 }, 20977 { 20978 name: "AddTupleFirst32", 20979 argLen: 2, 20980 reg: regInfo{}, 20981 }, 20982 { 20983 name: "AddTupleFirst64", 20984 argLen: 2, 20985 reg: regInfo{}, 20986 }, 20987 { 20988 name: "LoweredAtomicCas32", 20989 auxType: auxSymOff, 20990 argLen: 4, 20991 clobberFlags: true, 20992 faultOnNilArg0: true, 20993 asm: s390x.ACS, 20994 reg: regInfo{ 20995 inputs: []inputInfo{ 20996 {1, 1}, // R0 20997 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20998 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20999 }, 21000 clobbers: 1, // R0 21001 outputs: []outputInfo{ 21002 {1, 0}, 21003 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21004 }, 21005 }, 21006 }, 21007 { 21008 name: "LoweredAtomicCas64", 21009 auxType: auxSymOff, 21010 argLen: 4, 21011 clobberFlags: true, 21012 faultOnNilArg0: true, 21013 asm: s390x.ACSG, 21014 reg: regInfo{ 21015 inputs: []inputInfo{ 21016 {1, 1}, // R0 21017 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21018 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21019 }, 21020 clobbers: 1, // R0 21021 outputs: []outputInfo{ 21022 {1, 0}, 21023 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21024 }, 21025 }, 21026 }, 21027 { 21028 name: "LoweredAtomicExchange32", 21029 auxType: auxSymOff, 21030 argLen: 3, 21031 clobberFlags: true, 21032 faultOnNilArg0: true, 21033 asm: s390x.ACS, 21034 reg: regInfo{ 21035 inputs: []inputInfo{ 21036 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21037 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21038 }, 21039 outputs: []outputInfo{ 21040 {1, 0}, 21041 {0, 1}, // R0 21042 }, 21043 }, 21044 }, 21045 { 21046 name: "LoweredAtomicExchange64", 21047 auxType: auxSymOff, 21048 argLen: 3, 21049 clobberFlags: true, 21050 faultOnNilArg0: true, 21051 asm: s390x.ACSG, 21052 reg: regInfo{ 21053 inputs: []inputInfo{ 21054 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21055 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21056 }, 21057 outputs: []outputInfo{ 21058 {1, 0}, 21059 {0, 1}, // R0 21060 }, 21061 }, 21062 }, 21063 { 21064 name: "FLOGR", 21065 argLen: 1, 21066 clobberFlags: true, 21067 asm: s390x.AFLOGR, 21068 reg: regInfo{ 21069 inputs: []inputInfo{ 21070 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21071 }, 21072 clobbers: 2, // R1 21073 outputs: []outputInfo{ 21074 {0, 1}, // R0 21075 }, 21076 }, 21077 }, 21078 { 21079 name: "STMG2", 21080 auxType: auxSymOff, 21081 argLen: 4, 21082 faultOnNilArg0: true, 21083 asm: s390x.ASTMG, 21084 reg: regInfo{ 21085 inputs: []inputInfo{ 21086 {1, 2}, // R1 21087 {2, 4}, // R2 21088 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21089 }, 21090 }, 21091 }, 21092 { 21093 name: "STMG3", 21094 auxType: auxSymOff, 21095 argLen: 5, 21096 faultOnNilArg0: true, 21097 asm: s390x.ASTMG, 21098 reg: regInfo{ 21099 inputs: []inputInfo{ 21100 {1, 2}, // R1 21101 {2, 4}, // R2 21102 {3, 8}, // R3 21103 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21104 }, 21105 }, 21106 }, 21107 { 21108 name: "STMG4", 21109 auxType: auxSymOff, 21110 argLen: 6, 21111 faultOnNilArg0: true, 21112 asm: s390x.ASTMG, 21113 reg: regInfo{ 21114 inputs: []inputInfo{ 21115 {1, 2}, // R1 21116 {2, 4}, // R2 21117 {3, 8}, // R3 21118 {4, 16}, // R4 21119 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21120 }, 21121 }, 21122 }, 21123 { 21124 name: "STM2", 21125 auxType: auxSymOff, 21126 argLen: 4, 21127 faultOnNilArg0: true, 21128 asm: s390x.ASTMY, 21129 reg: regInfo{ 21130 inputs: []inputInfo{ 21131 {1, 2}, // R1 21132 {2, 4}, // R2 21133 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21134 }, 21135 }, 21136 }, 21137 { 21138 name: "STM3", 21139 auxType: auxSymOff, 21140 argLen: 5, 21141 faultOnNilArg0: true, 21142 asm: s390x.ASTMY, 21143 reg: regInfo{ 21144 inputs: []inputInfo{ 21145 {1, 2}, // R1 21146 {2, 4}, // R2 21147 {3, 8}, // R3 21148 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21149 }, 21150 }, 21151 }, 21152 { 21153 name: "STM4", 21154 auxType: auxSymOff, 21155 argLen: 6, 21156 faultOnNilArg0: true, 21157 asm: s390x.ASTMY, 21158 reg: regInfo{ 21159 inputs: []inputInfo{ 21160 {1, 2}, // R1 21161 {2, 4}, // R2 21162 {3, 8}, // R3 21163 {4, 16}, // R4 21164 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21165 }, 21166 }, 21167 }, 21168 { 21169 name: "LoweredMove", 21170 auxType: auxInt64, 21171 argLen: 4, 21172 clobberFlags: true, 21173 faultOnNilArg0: true, 21174 faultOnNilArg1: true, 21175 reg: regInfo{ 21176 inputs: []inputInfo{ 21177 {0, 2}, // R1 21178 {1, 4}, // R2 21179 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21180 }, 21181 clobbers: 6, // R1 R2 21182 }, 21183 }, 21184 { 21185 name: "LoweredZero", 21186 auxType: auxInt64, 21187 argLen: 3, 21188 clobberFlags: true, 21189 faultOnNilArg0: true, 21190 reg: regInfo{ 21191 inputs: []inputInfo{ 21192 {0, 2}, // R1 21193 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21194 }, 21195 clobbers: 2, // R1 21196 }, 21197 }, 21198 21199 { 21200 name: "Add8", 21201 argLen: 2, 21202 commutative: true, 21203 generic: true, 21204 }, 21205 { 21206 name: "Add16", 21207 argLen: 2, 21208 commutative: true, 21209 generic: true, 21210 }, 21211 { 21212 name: "Add32", 21213 argLen: 2, 21214 commutative: true, 21215 generic: true, 21216 }, 21217 { 21218 name: "Add64", 21219 argLen: 2, 21220 commutative: true, 21221 generic: true, 21222 }, 21223 { 21224 name: "AddPtr", 21225 argLen: 2, 21226 generic: true, 21227 }, 21228 { 21229 name: "Add32F", 21230 argLen: 2, 21231 generic: true, 21232 }, 21233 { 21234 name: "Add64F", 21235 argLen: 2, 21236 generic: true, 21237 }, 21238 { 21239 name: "Sub8", 21240 argLen: 2, 21241 generic: true, 21242 }, 21243 { 21244 name: "Sub16", 21245 argLen: 2, 21246 generic: true, 21247 }, 21248 { 21249 name: "Sub32", 21250 argLen: 2, 21251 generic: true, 21252 }, 21253 { 21254 name: "Sub64", 21255 argLen: 2, 21256 generic: true, 21257 }, 21258 { 21259 name: "SubPtr", 21260 argLen: 2, 21261 generic: true, 21262 }, 21263 { 21264 name: "Sub32F", 21265 argLen: 2, 21266 generic: true, 21267 }, 21268 { 21269 name: "Sub64F", 21270 argLen: 2, 21271 generic: true, 21272 }, 21273 { 21274 name: "Mul8", 21275 argLen: 2, 21276 commutative: true, 21277 generic: true, 21278 }, 21279 { 21280 name: "Mul16", 21281 argLen: 2, 21282 commutative: true, 21283 generic: true, 21284 }, 21285 { 21286 name: "Mul32", 21287 argLen: 2, 21288 commutative: true, 21289 generic: true, 21290 }, 21291 { 21292 name: "Mul64", 21293 argLen: 2, 21294 commutative: true, 21295 generic: true, 21296 }, 21297 { 21298 name: "Mul32F", 21299 argLen: 2, 21300 generic: true, 21301 }, 21302 { 21303 name: "Mul64F", 21304 argLen: 2, 21305 generic: true, 21306 }, 21307 { 21308 name: "Div32F", 21309 argLen: 2, 21310 generic: true, 21311 }, 21312 { 21313 name: "Div64F", 21314 argLen: 2, 21315 generic: true, 21316 }, 21317 { 21318 name: "Hmul8", 21319 argLen: 2, 21320 generic: true, 21321 }, 21322 { 21323 name: "Hmul8u", 21324 argLen: 2, 21325 generic: true, 21326 }, 21327 { 21328 name: "Hmul16", 21329 argLen: 2, 21330 generic: true, 21331 }, 21332 { 21333 name: "Hmul16u", 21334 argLen: 2, 21335 generic: true, 21336 }, 21337 { 21338 name: "Hmul32", 21339 argLen: 2, 21340 generic: true, 21341 }, 21342 { 21343 name: "Hmul32u", 21344 argLen: 2, 21345 generic: true, 21346 }, 21347 { 21348 name: "Hmul64", 21349 argLen: 2, 21350 generic: true, 21351 }, 21352 { 21353 name: "Hmul64u", 21354 argLen: 2, 21355 generic: true, 21356 }, 21357 { 21358 name: "Mul32uhilo", 21359 argLen: 2, 21360 generic: true, 21361 }, 21362 { 21363 name: "Mul64uhilo", 21364 argLen: 2, 21365 generic: true, 21366 }, 21367 { 21368 name: "Avg64u", 21369 argLen: 2, 21370 generic: true, 21371 }, 21372 { 21373 name: "Div8", 21374 argLen: 2, 21375 generic: true, 21376 }, 21377 { 21378 name: "Div8u", 21379 argLen: 2, 21380 generic: true, 21381 }, 21382 { 21383 name: "Div16", 21384 argLen: 2, 21385 generic: true, 21386 }, 21387 { 21388 name: "Div16u", 21389 argLen: 2, 21390 generic: true, 21391 }, 21392 { 21393 name: "Div32", 21394 argLen: 2, 21395 generic: true, 21396 }, 21397 { 21398 name: "Div32u", 21399 argLen: 2, 21400 generic: true, 21401 }, 21402 { 21403 name: "Div64", 21404 argLen: 2, 21405 generic: true, 21406 }, 21407 { 21408 name: "Div64u", 21409 argLen: 2, 21410 generic: true, 21411 }, 21412 { 21413 name: "Div128u", 21414 argLen: 3, 21415 generic: true, 21416 }, 21417 { 21418 name: "Mod8", 21419 argLen: 2, 21420 generic: true, 21421 }, 21422 { 21423 name: "Mod8u", 21424 argLen: 2, 21425 generic: true, 21426 }, 21427 { 21428 name: "Mod16", 21429 argLen: 2, 21430 generic: true, 21431 }, 21432 { 21433 name: "Mod16u", 21434 argLen: 2, 21435 generic: true, 21436 }, 21437 { 21438 name: "Mod32", 21439 argLen: 2, 21440 generic: true, 21441 }, 21442 { 21443 name: "Mod32u", 21444 argLen: 2, 21445 generic: true, 21446 }, 21447 { 21448 name: "Mod64", 21449 argLen: 2, 21450 generic: true, 21451 }, 21452 { 21453 name: "Mod64u", 21454 argLen: 2, 21455 generic: true, 21456 }, 21457 { 21458 name: "And8", 21459 argLen: 2, 21460 commutative: true, 21461 generic: true, 21462 }, 21463 { 21464 name: "And16", 21465 argLen: 2, 21466 commutative: true, 21467 generic: true, 21468 }, 21469 { 21470 name: "And32", 21471 argLen: 2, 21472 commutative: true, 21473 generic: true, 21474 }, 21475 { 21476 name: "And64", 21477 argLen: 2, 21478 commutative: true, 21479 generic: true, 21480 }, 21481 { 21482 name: "Or8", 21483 argLen: 2, 21484 commutative: true, 21485 generic: true, 21486 }, 21487 { 21488 name: "Or16", 21489 argLen: 2, 21490 commutative: true, 21491 generic: true, 21492 }, 21493 { 21494 name: "Or32", 21495 argLen: 2, 21496 commutative: true, 21497 generic: true, 21498 }, 21499 { 21500 name: "Or64", 21501 argLen: 2, 21502 commutative: true, 21503 generic: true, 21504 }, 21505 { 21506 name: "Xor8", 21507 argLen: 2, 21508 commutative: true, 21509 generic: true, 21510 }, 21511 { 21512 name: "Xor16", 21513 argLen: 2, 21514 commutative: true, 21515 generic: true, 21516 }, 21517 { 21518 name: "Xor32", 21519 argLen: 2, 21520 commutative: true, 21521 generic: true, 21522 }, 21523 { 21524 name: "Xor64", 21525 argLen: 2, 21526 commutative: true, 21527 generic: true, 21528 }, 21529 { 21530 name: "Lsh8x8", 21531 argLen: 2, 21532 generic: true, 21533 }, 21534 { 21535 name: "Lsh8x16", 21536 argLen: 2, 21537 generic: true, 21538 }, 21539 { 21540 name: "Lsh8x32", 21541 argLen: 2, 21542 generic: true, 21543 }, 21544 { 21545 name: "Lsh8x64", 21546 argLen: 2, 21547 generic: true, 21548 }, 21549 { 21550 name: "Lsh16x8", 21551 argLen: 2, 21552 generic: true, 21553 }, 21554 { 21555 name: "Lsh16x16", 21556 argLen: 2, 21557 generic: true, 21558 }, 21559 { 21560 name: "Lsh16x32", 21561 argLen: 2, 21562 generic: true, 21563 }, 21564 { 21565 name: "Lsh16x64", 21566 argLen: 2, 21567 generic: true, 21568 }, 21569 { 21570 name: "Lsh32x8", 21571 argLen: 2, 21572 generic: true, 21573 }, 21574 { 21575 name: "Lsh32x16", 21576 argLen: 2, 21577 generic: true, 21578 }, 21579 { 21580 name: "Lsh32x32", 21581 argLen: 2, 21582 generic: true, 21583 }, 21584 { 21585 name: "Lsh32x64", 21586 argLen: 2, 21587 generic: true, 21588 }, 21589 { 21590 name: "Lsh64x8", 21591 argLen: 2, 21592 generic: true, 21593 }, 21594 { 21595 name: "Lsh64x16", 21596 argLen: 2, 21597 generic: true, 21598 }, 21599 { 21600 name: "Lsh64x32", 21601 argLen: 2, 21602 generic: true, 21603 }, 21604 { 21605 name: "Lsh64x64", 21606 argLen: 2, 21607 generic: true, 21608 }, 21609 { 21610 name: "Rsh8x8", 21611 argLen: 2, 21612 generic: true, 21613 }, 21614 { 21615 name: "Rsh8x16", 21616 argLen: 2, 21617 generic: true, 21618 }, 21619 { 21620 name: "Rsh8x32", 21621 argLen: 2, 21622 generic: true, 21623 }, 21624 { 21625 name: "Rsh8x64", 21626 argLen: 2, 21627 generic: true, 21628 }, 21629 { 21630 name: "Rsh16x8", 21631 argLen: 2, 21632 generic: true, 21633 }, 21634 { 21635 name: "Rsh16x16", 21636 argLen: 2, 21637 generic: true, 21638 }, 21639 { 21640 name: "Rsh16x32", 21641 argLen: 2, 21642 generic: true, 21643 }, 21644 { 21645 name: "Rsh16x64", 21646 argLen: 2, 21647 generic: true, 21648 }, 21649 { 21650 name: "Rsh32x8", 21651 argLen: 2, 21652 generic: true, 21653 }, 21654 { 21655 name: "Rsh32x16", 21656 argLen: 2, 21657 generic: true, 21658 }, 21659 { 21660 name: "Rsh32x32", 21661 argLen: 2, 21662 generic: true, 21663 }, 21664 { 21665 name: "Rsh32x64", 21666 argLen: 2, 21667 generic: true, 21668 }, 21669 { 21670 name: "Rsh64x8", 21671 argLen: 2, 21672 generic: true, 21673 }, 21674 { 21675 name: "Rsh64x16", 21676 argLen: 2, 21677 generic: true, 21678 }, 21679 { 21680 name: "Rsh64x32", 21681 argLen: 2, 21682 generic: true, 21683 }, 21684 { 21685 name: "Rsh64x64", 21686 argLen: 2, 21687 generic: true, 21688 }, 21689 { 21690 name: "Rsh8Ux8", 21691 argLen: 2, 21692 generic: true, 21693 }, 21694 { 21695 name: "Rsh8Ux16", 21696 argLen: 2, 21697 generic: true, 21698 }, 21699 { 21700 name: "Rsh8Ux32", 21701 argLen: 2, 21702 generic: true, 21703 }, 21704 { 21705 name: "Rsh8Ux64", 21706 argLen: 2, 21707 generic: true, 21708 }, 21709 { 21710 name: "Rsh16Ux8", 21711 argLen: 2, 21712 generic: true, 21713 }, 21714 { 21715 name: "Rsh16Ux16", 21716 argLen: 2, 21717 generic: true, 21718 }, 21719 { 21720 name: "Rsh16Ux32", 21721 argLen: 2, 21722 generic: true, 21723 }, 21724 { 21725 name: "Rsh16Ux64", 21726 argLen: 2, 21727 generic: true, 21728 }, 21729 { 21730 name: "Rsh32Ux8", 21731 argLen: 2, 21732 generic: true, 21733 }, 21734 { 21735 name: "Rsh32Ux16", 21736 argLen: 2, 21737 generic: true, 21738 }, 21739 { 21740 name: "Rsh32Ux32", 21741 argLen: 2, 21742 generic: true, 21743 }, 21744 { 21745 name: "Rsh32Ux64", 21746 argLen: 2, 21747 generic: true, 21748 }, 21749 { 21750 name: "Rsh64Ux8", 21751 argLen: 2, 21752 generic: true, 21753 }, 21754 { 21755 name: "Rsh64Ux16", 21756 argLen: 2, 21757 generic: true, 21758 }, 21759 { 21760 name: "Rsh64Ux32", 21761 argLen: 2, 21762 generic: true, 21763 }, 21764 { 21765 name: "Rsh64Ux64", 21766 argLen: 2, 21767 generic: true, 21768 }, 21769 { 21770 name: "Eq8", 21771 argLen: 2, 21772 commutative: true, 21773 generic: true, 21774 }, 21775 { 21776 name: "Eq16", 21777 argLen: 2, 21778 commutative: true, 21779 generic: true, 21780 }, 21781 { 21782 name: "Eq32", 21783 argLen: 2, 21784 commutative: true, 21785 generic: true, 21786 }, 21787 { 21788 name: "Eq64", 21789 argLen: 2, 21790 commutative: true, 21791 generic: true, 21792 }, 21793 { 21794 name: "EqPtr", 21795 argLen: 2, 21796 commutative: true, 21797 generic: true, 21798 }, 21799 { 21800 name: "EqInter", 21801 argLen: 2, 21802 generic: true, 21803 }, 21804 { 21805 name: "EqSlice", 21806 argLen: 2, 21807 generic: true, 21808 }, 21809 { 21810 name: "Eq32F", 21811 argLen: 2, 21812 generic: true, 21813 }, 21814 { 21815 name: "Eq64F", 21816 argLen: 2, 21817 generic: true, 21818 }, 21819 { 21820 name: "Neq8", 21821 argLen: 2, 21822 commutative: true, 21823 generic: true, 21824 }, 21825 { 21826 name: "Neq16", 21827 argLen: 2, 21828 commutative: true, 21829 generic: true, 21830 }, 21831 { 21832 name: "Neq32", 21833 argLen: 2, 21834 commutative: true, 21835 generic: true, 21836 }, 21837 { 21838 name: "Neq64", 21839 argLen: 2, 21840 commutative: true, 21841 generic: true, 21842 }, 21843 { 21844 name: "NeqPtr", 21845 argLen: 2, 21846 commutative: true, 21847 generic: true, 21848 }, 21849 { 21850 name: "NeqInter", 21851 argLen: 2, 21852 generic: true, 21853 }, 21854 { 21855 name: "NeqSlice", 21856 argLen: 2, 21857 generic: true, 21858 }, 21859 { 21860 name: "Neq32F", 21861 argLen: 2, 21862 generic: true, 21863 }, 21864 { 21865 name: "Neq64F", 21866 argLen: 2, 21867 generic: true, 21868 }, 21869 { 21870 name: "Less8", 21871 argLen: 2, 21872 generic: true, 21873 }, 21874 { 21875 name: "Less8U", 21876 argLen: 2, 21877 generic: true, 21878 }, 21879 { 21880 name: "Less16", 21881 argLen: 2, 21882 generic: true, 21883 }, 21884 { 21885 name: "Less16U", 21886 argLen: 2, 21887 generic: true, 21888 }, 21889 { 21890 name: "Less32", 21891 argLen: 2, 21892 generic: true, 21893 }, 21894 { 21895 name: "Less32U", 21896 argLen: 2, 21897 generic: true, 21898 }, 21899 { 21900 name: "Less64", 21901 argLen: 2, 21902 generic: true, 21903 }, 21904 { 21905 name: "Less64U", 21906 argLen: 2, 21907 generic: true, 21908 }, 21909 { 21910 name: "Less32F", 21911 argLen: 2, 21912 generic: true, 21913 }, 21914 { 21915 name: "Less64F", 21916 argLen: 2, 21917 generic: true, 21918 }, 21919 { 21920 name: "Leq8", 21921 argLen: 2, 21922 generic: true, 21923 }, 21924 { 21925 name: "Leq8U", 21926 argLen: 2, 21927 generic: true, 21928 }, 21929 { 21930 name: "Leq16", 21931 argLen: 2, 21932 generic: true, 21933 }, 21934 { 21935 name: "Leq16U", 21936 argLen: 2, 21937 generic: true, 21938 }, 21939 { 21940 name: "Leq32", 21941 argLen: 2, 21942 generic: true, 21943 }, 21944 { 21945 name: "Leq32U", 21946 argLen: 2, 21947 generic: true, 21948 }, 21949 { 21950 name: "Leq64", 21951 argLen: 2, 21952 generic: true, 21953 }, 21954 { 21955 name: "Leq64U", 21956 argLen: 2, 21957 generic: true, 21958 }, 21959 { 21960 name: "Leq32F", 21961 argLen: 2, 21962 generic: true, 21963 }, 21964 { 21965 name: "Leq64F", 21966 argLen: 2, 21967 generic: true, 21968 }, 21969 { 21970 name: "Greater8", 21971 argLen: 2, 21972 generic: true, 21973 }, 21974 { 21975 name: "Greater8U", 21976 argLen: 2, 21977 generic: true, 21978 }, 21979 { 21980 name: "Greater16", 21981 argLen: 2, 21982 generic: true, 21983 }, 21984 { 21985 name: "Greater16U", 21986 argLen: 2, 21987 generic: true, 21988 }, 21989 { 21990 name: "Greater32", 21991 argLen: 2, 21992 generic: true, 21993 }, 21994 { 21995 name: "Greater32U", 21996 argLen: 2, 21997 generic: true, 21998 }, 21999 { 22000 name: "Greater64", 22001 argLen: 2, 22002 generic: true, 22003 }, 22004 { 22005 name: "Greater64U", 22006 argLen: 2, 22007 generic: true, 22008 }, 22009 { 22010 name: "Greater32F", 22011 argLen: 2, 22012 generic: true, 22013 }, 22014 { 22015 name: "Greater64F", 22016 argLen: 2, 22017 generic: true, 22018 }, 22019 { 22020 name: "Geq8", 22021 argLen: 2, 22022 generic: true, 22023 }, 22024 { 22025 name: "Geq8U", 22026 argLen: 2, 22027 generic: true, 22028 }, 22029 { 22030 name: "Geq16", 22031 argLen: 2, 22032 generic: true, 22033 }, 22034 { 22035 name: "Geq16U", 22036 argLen: 2, 22037 generic: true, 22038 }, 22039 { 22040 name: "Geq32", 22041 argLen: 2, 22042 generic: true, 22043 }, 22044 { 22045 name: "Geq32U", 22046 argLen: 2, 22047 generic: true, 22048 }, 22049 { 22050 name: "Geq64", 22051 argLen: 2, 22052 generic: true, 22053 }, 22054 { 22055 name: "Geq64U", 22056 argLen: 2, 22057 generic: true, 22058 }, 22059 { 22060 name: "Geq32F", 22061 argLen: 2, 22062 generic: true, 22063 }, 22064 { 22065 name: "Geq64F", 22066 argLen: 2, 22067 generic: true, 22068 }, 22069 { 22070 name: "AndB", 22071 argLen: 2, 22072 generic: true, 22073 }, 22074 { 22075 name: "OrB", 22076 argLen: 2, 22077 generic: true, 22078 }, 22079 { 22080 name: "EqB", 22081 argLen: 2, 22082 generic: true, 22083 }, 22084 { 22085 name: "NeqB", 22086 argLen: 2, 22087 generic: true, 22088 }, 22089 { 22090 name: "Not", 22091 argLen: 1, 22092 generic: true, 22093 }, 22094 { 22095 name: "Neg8", 22096 argLen: 1, 22097 generic: true, 22098 }, 22099 { 22100 name: "Neg16", 22101 argLen: 1, 22102 generic: true, 22103 }, 22104 { 22105 name: "Neg32", 22106 argLen: 1, 22107 generic: true, 22108 }, 22109 { 22110 name: "Neg64", 22111 argLen: 1, 22112 generic: true, 22113 }, 22114 { 22115 name: "Neg32F", 22116 argLen: 1, 22117 generic: true, 22118 }, 22119 { 22120 name: "Neg64F", 22121 argLen: 1, 22122 generic: true, 22123 }, 22124 { 22125 name: "Com8", 22126 argLen: 1, 22127 generic: true, 22128 }, 22129 { 22130 name: "Com16", 22131 argLen: 1, 22132 generic: true, 22133 }, 22134 { 22135 name: "Com32", 22136 argLen: 1, 22137 generic: true, 22138 }, 22139 { 22140 name: "Com64", 22141 argLen: 1, 22142 generic: true, 22143 }, 22144 { 22145 name: "Ctz32", 22146 argLen: 1, 22147 generic: true, 22148 }, 22149 { 22150 name: "Ctz64", 22151 argLen: 1, 22152 generic: true, 22153 }, 22154 { 22155 name: "Bswap32", 22156 argLen: 1, 22157 generic: true, 22158 }, 22159 { 22160 name: "Bswap64", 22161 argLen: 1, 22162 generic: true, 22163 }, 22164 { 22165 name: "Sqrt", 22166 argLen: 1, 22167 generic: true, 22168 }, 22169 { 22170 name: "Phi", 22171 argLen: -1, 22172 generic: true, 22173 }, 22174 { 22175 name: "Copy", 22176 argLen: 1, 22177 generic: true, 22178 }, 22179 { 22180 name: "Convert", 22181 argLen: 2, 22182 generic: true, 22183 }, 22184 { 22185 name: "ConstBool", 22186 auxType: auxBool, 22187 argLen: 0, 22188 generic: true, 22189 }, 22190 { 22191 name: "ConstString", 22192 auxType: auxString, 22193 argLen: 0, 22194 generic: true, 22195 }, 22196 { 22197 name: "ConstNil", 22198 argLen: 0, 22199 generic: true, 22200 }, 22201 { 22202 name: "Const8", 22203 auxType: auxInt8, 22204 argLen: 0, 22205 generic: true, 22206 }, 22207 { 22208 name: "Const16", 22209 auxType: auxInt16, 22210 argLen: 0, 22211 generic: true, 22212 }, 22213 { 22214 name: "Const32", 22215 auxType: auxInt32, 22216 argLen: 0, 22217 generic: true, 22218 }, 22219 { 22220 name: "Const64", 22221 auxType: auxInt64, 22222 argLen: 0, 22223 generic: true, 22224 }, 22225 { 22226 name: "Const32F", 22227 auxType: auxFloat32, 22228 argLen: 0, 22229 generic: true, 22230 }, 22231 { 22232 name: "Const64F", 22233 auxType: auxFloat64, 22234 argLen: 0, 22235 generic: true, 22236 }, 22237 { 22238 name: "ConstInterface", 22239 argLen: 0, 22240 generic: true, 22241 }, 22242 { 22243 name: "ConstSlice", 22244 argLen: 0, 22245 generic: true, 22246 }, 22247 { 22248 name: "InitMem", 22249 argLen: 0, 22250 generic: true, 22251 }, 22252 { 22253 name: "Arg", 22254 auxType: auxSymOff, 22255 argLen: 0, 22256 generic: true, 22257 }, 22258 { 22259 name: "Addr", 22260 auxType: auxSym, 22261 argLen: 1, 22262 generic: true, 22263 }, 22264 { 22265 name: "SP", 22266 argLen: 0, 22267 generic: true, 22268 }, 22269 { 22270 name: "SB", 22271 argLen: 0, 22272 generic: true, 22273 }, 22274 { 22275 name: "Func", 22276 auxType: auxSym, 22277 argLen: 0, 22278 generic: true, 22279 }, 22280 { 22281 name: "Load", 22282 argLen: 2, 22283 generic: true, 22284 }, 22285 { 22286 name: "Store", 22287 auxType: auxInt64, 22288 argLen: 3, 22289 generic: true, 22290 }, 22291 { 22292 name: "Move", 22293 auxType: auxSizeAndAlign, 22294 argLen: 3, 22295 generic: true, 22296 }, 22297 { 22298 name: "Zero", 22299 auxType: auxSizeAndAlign, 22300 argLen: 2, 22301 generic: true, 22302 }, 22303 { 22304 name: "StoreWB", 22305 auxType: auxInt64, 22306 argLen: 3, 22307 generic: true, 22308 }, 22309 { 22310 name: "MoveWB", 22311 auxType: auxSymSizeAndAlign, 22312 argLen: 3, 22313 generic: true, 22314 }, 22315 { 22316 name: "MoveWBVolatile", 22317 auxType: auxSymSizeAndAlign, 22318 argLen: 3, 22319 generic: true, 22320 }, 22321 { 22322 name: "ZeroWB", 22323 auxType: auxSymSizeAndAlign, 22324 argLen: 2, 22325 generic: true, 22326 }, 22327 { 22328 name: "ClosureCall", 22329 auxType: auxInt64, 22330 argLen: 3, 22331 call: true, 22332 generic: true, 22333 }, 22334 { 22335 name: "StaticCall", 22336 auxType: auxSymOff, 22337 argLen: 1, 22338 call: true, 22339 generic: true, 22340 }, 22341 { 22342 name: "DeferCall", 22343 auxType: auxInt64, 22344 argLen: 1, 22345 call: true, 22346 generic: true, 22347 }, 22348 { 22349 name: "GoCall", 22350 auxType: auxInt64, 22351 argLen: 1, 22352 call: true, 22353 generic: true, 22354 }, 22355 { 22356 name: "InterCall", 22357 auxType: auxInt64, 22358 argLen: 2, 22359 call: true, 22360 generic: true, 22361 }, 22362 { 22363 name: "SignExt8to16", 22364 argLen: 1, 22365 generic: true, 22366 }, 22367 { 22368 name: "SignExt8to32", 22369 argLen: 1, 22370 generic: true, 22371 }, 22372 { 22373 name: "SignExt8to64", 22374 argLen: 1, 22375 generic: true, 22376 }, 22377 { 22378 name: "SignExt16to32", 22379 argLen: 1, 22380 generic: true, 22381 }, 22382 { 22383 name: "SignExt16to64", 22384 argLen: 1, 22385 generic: true, 22386 }, 22387 { 22388 name: "SignExt32to64", 22389 argLen: 1, 22390 generic: true, 22391 }, 22392 { 22393 name: "ZeroExt8to16", 22394 argLen: 1, 22395 generic: true, 22396 }, 22397 { 22398 name: "ZeroExt8to32", 22399 argLen: 1, 22400 generic: true, 22401 }, 22402 { 22403 name: "ZeroExt8to64", 22404 argLen: 1, 22405 generic: true, 22406 }, 22407 { 22408 name: "ZeroExt16to32", 22409 argLen: 1, 22410 generic: true, 22411 }, 22412 { 22413 name: "ZeroExt16to64", 22414 argLen: 1, 22415 generic: true, 22416 }, 22417 { 22418 name: "ZeroExt32to64", 22419 argLen: 1, 22420 generic: true, 22421 }, 22422 { 22423 name: "Trunc16to8", 22424 argLen: 1, 22425 generic: true, 22426 }, 22427 { 22428 name: "Trunc32to8", 22429 argLen: 1, 22430 generic: true, 22431 }, 22432 { 22433 name: "Trunc32to16", 22434 argLen: 1, 22435 generic: true, 22436 }, 22437 { 22438 name: "Trunc64to8", 22439 argLen: 1, 22440 generic: true, 22441 }, 22442 { 22443 name: "Trunc64to16", 22444 argLen: 1, 22445 generic: true, 22446 }, 22447 { 22448 name: "Trunc64to32", 22449 argLen: 1, 22450 generic: true, 22451 }, 22452 { 22453 name: "Cvt32to32F", 22454 argLen: 1, 22455 generic: true, 22456 }, 22457 { 22458 name: "Cvt32to64F", 22459 argLen: 1, 22460 generic: true, 22461 }, 22462 { 22463 name: "Cvt64to32F", 22464 argLen: 1, 22465 generic: true, 22466 }, 22467 { 22468 name: "Cvt64to64F", 22469 argLen: 1, 22470 generic: true, 22471 }, 22472 { 22473 name: "Cvt32Fto32", 22474 argLen: 1, 22475 generic: true, 22476 }, 22477 { 22478 name: "Cvt32Fto64", 22479 argLen: 1, 22480 generic: true, 22481 }, 22482 { 22483 name: "Cvt64Fto32", 22484 argLen: 1, 22485 generic: true, 22486 }, 22487 { 22488 name: "Cvt64Fto64", 22489 argLen: 1, 22490 generic: true, 22491 }, 22492 { 22493 name: "Cvt32Fto64F", 22494 argLen: 1, 22495 generic: true, 22496 }, 22497 { 22498 name: "Cvt64Fto32F", 22499 argLen: 1, 22500 generic: true, 22501 }, 22502 { 22503 name: "IsNonNil", 22504 argLen: 1, 22505 generic: true, 22506 }, 22507 { 22508 name: "IsInBounds", 22509 argLen: 2, 22510 generic: true, 22511 }, 22512 { 22513 name: "IsSliceInBounds", 22514 argLen: 2, 22515 generic: true, 22516 }, 22517 { 22518 name: "NilCheck", 22519 argLen: 2, 22520 generic: true, 22521 }, 22522 { 22523 name: "GetG", 22524 argLen: 1, 22525 generic: true, 22526 }, 22527 { 22528 name: "GetClosurePtr", 22529 argLen: 0, 22530 generic: true, 22531 }, 22532 { 22533 name: "PtrIndex", 22534 argLen: 2, 22535 generic: true, 22536 }, 22537 { 22538 name: "OffPtr", 22539 auxType: auxInt64, 22540 argLen: 1, 22541 generic: true, 22542 }, 22543 { 22544 name: "SliceMake", 22545 argLen: 3, 22546 generic: true, 22547 }, 22548 { 22549 name: "SlicePtr", 22550 argLen: 1, 22551 generic: true, 22552 }, 22553 { 22554 name: "SliceLen", 22555 argLen: 1, 22556 generic: true, 22557 }, 22558 { 22559 name: "SliceCap", 22560 argLen: 1, 22561 generic: true, 22562 }, 22563 { 22564 name: "ComplexMake", 22565 argLen: 2, 22566 generic: true, 22567 }, 22568 { 22569 name: "ComplexReal", 22570 argLen: 1, 22571 generic: true, 22572 }, 22573 { 22574 name: "ComplexImag", 22575 argLen: 1, 22576 generic: true, 22577 }, 22578 { 22579 name: "StringMake", 22580 argLen: 2, 22581 generic: true, 22582 }, 22583 { 22584 name: "StringPtr", 22585 argLen: 1, 22586 generic: true, 22587 }, 22588 { 22589 name: "StringLen", 22590 argLen: 1, 22591 generic: true, 22592 }, 22593 { 22594 name: "IMake", 22595 argLen: 2, 22596 generic: true, 22597 }, 22598 { 22599 name: "ITab", 22600 argLen: 1, 22601 generic: true, 22602 }, 22603 { 22604 name: "IData", 22605 argLen: 1, 22606 generic: true, 22607 }, 22608 { 22609 name: "StructMake0", 22610 argLen: 0, 22611 generic: true, 22612 }, 22613 { 22614 name: "StructMake1", 22615 argLen: 1, 22616 generic: true, 22617 }, 22618 { 22619 name: "StructMake2", 22620 argLen: 2, 22621 generic: true, 22622 }, 22623 { 22624 name: "StructMake3", 22625 argLen: 3, 22626 generic: true, 22627 }, 22628 { 22629 name: "StructMake4", 22630 argLen: 4, 22631 generic: true, 22632 }, 22633 { 22634 name: "StructSelect", 22635 auxType: auxInt64, 22636 argLen: 1, 22637 generic: true, 22638 }, 22639 { 22640 name: "ArrayMake0", 22641 argLen: 0, 22642 generic: true, 22643 }, 22644 { 22645 name: "ArrayMake1", 22646 argLen: 1, 22647 generic: true, 22648 }, 22649 { 22650 name: "ArraySelect", 22651 auxType: auxInt64, 22652 argLen: 1, 22653 generic: true, 22654 }, 22655 { 22656 name: "StoreReg", 22657 argLen: 1, 22658 generic: true, 22659 }, 22660 { 22661 name: "LoadReg", 22662 argLen: 1, 22663 generic: true, 22664 }, 22665 { 22666 name: "FwdRef", 22667 auxType: auxSym, 22668 argLen: 0, 22669 generic: true, 22670 }, 22671 { 22672 name: "Unknown", 22673 argLen: 0, 22674 generic: true, 22675 }, 22676 { 22677 name: "VarDef", 22678 auxType: auxSym, 22679 argLen: 1, 22680 generic: true, 22681 }, 22682 { 22683 name: "VarKill", 22684 auxType: auxSym, 22685 argLen: 1, 22686 generic: true, 22687 }, 22688 { 22689 name: "VarLive", 22690 auxType: auxSym, 22691 argLen: 1, 22692 generic: true, 22693 }, 22694 { 22695 name: "KeepAlive", 22696 argLen: 2, 22697 generic: true, 22698 }, 22699 { 22700 name: "Int64Make", 22701 argLen: 2, 22702 generic: true, 22703 }, 22704 { 22705 name: "Int64Hi", 22706 argLen: 1, 22707 generic: true, 22708 }, 22709 { 22710 name: "Int64Lo", 22711 argLen: 1, 22712 generic: true, 22713 }, 22714 { 22715 name: "Add32carry", 22716 argLen: 2, 22717 commutative: true, 22718 generic: true, 22719 }, 22720 { 22721 name: "Add32withcarry", 22722 argLen: 3, 22723 commutative: true, 22724 generic: true, 22725 }, 22726 { 22727 name: "Sub32carry", 22728 argLen: 2, 22729 generic: true, 22730 }, 22731 { 22732 name: "Sub32withcarry", 22733 argLen: 3, 22734 generic: true, 22735 }, 22736 { 22737 name: "Signmask", 22738 argLen: 1, 22739 generic: true, 22740 }, 22741 { 22742 name: "Zeromask", 22743 argLen: 1, 22744 generic: true, 22745 }, 22746 { 22747 name: "Slicemask", 22748 argLen: 1, 22749 generic: true, 22750 }, 22751 { 22752 name: "Cvt32Uto32F", 22753 argLen: 1, 22754 generic: true, 22755 }, 22756 { 22757 name: "Cvt32Uto64F", 22758 argLen: 1, 22759 generic: true, 22760 }, 22761 { 22762 name: "Cvt32Fto32U", 22763 argLen: 1, 22764 generic: true, 22765 }, 22766 { 22767 name: "Cvt64Fto32U", 22768 argLen: 1, 22769 generic: true, 22770 }, 22771 { 22772 name: "Cvt64Uto32F", 22773 argLen: 1, 22774 generic: true, 22775 }, 22776 { 22777 name: "Cvt64Uto64F", 22778 argLen: 1, 22779 generic: true, 22780 }, 22781 { 22782 name: "Cvt32Fto64U", 22783 argLen: 1, 22784 generic: true, 22785 }, 22786 { 22787 name: "Cvt64Fto64U", 22788 argLen: 1, 22789 generic: true, 22790 }, 22791 { 22792 name: "Select0", 22793 argLen: 1, 22794 generic: true, 22795 }, 22796 { 22797 name: "Select1", 22798 argLen: 1, 22799 generic: true, 22800 }, 22801 { 22802 name: "AtomicLoad32", 22803 argLen: 2, 22804 generic: true, 22805 }, 22806 { 22807 name: "AtomicLoad64", 22808 argLen: 2, 22809 generic: true, 22810 }, 22811 { 22812 name: "AtomicLoadPtr", 22813 argLen: 2, 22814 generic: true, 22815 }, 22816 { 22817 name: "AtomicStore32", 22818 argLen: 3, 22819 generic: true, 22820 }, 22821 { 22822 name: "AtomicStore64", 22823 argLen: 3, 22824 generic: true, 22825 }, 22826 { 22827 name: "AtomicStorePtrNoWB", 22828 argLen: 3, 22829 generic: true, 22830 }, 22831 { 22832 name: "AtomicExchange32", 22833 argLen: 3, 22834 generic: true, 22835 }, 22836 { 22837 name: "AtomicExchange64", 22838 argLen: 3, 22839 generic: true, 22840 }, 22841 { 22842 name: "AtomicAdd32", 22843 argLen: 3, 22844 generic: true, 22845 }, 22846 { 22847 name: "AtomicAdd64", 22848 argLen: 3, 22849 generic: true, 22850 }, 22851 { 22852 name: "AtomicCompareAndSwap32", 22853 argLen: 4, 22854 generic: true, 22855 }, 22856 { 22857 name: "AtomicCompareAndSwap64", 22858 argLen: 4, 22859 generic: true, 22860 }, 22861 { 22862 name: "AtomicAnd8", 22863 argLen: 3, 22864 generic: true, 22865 }, 22866 { 22867 name: "AtomicOr8", 22868 argLen: 3, 22869 generic: true, 22870 }, 22871 } 22872 22873 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 22874 func (o Op) String() string { return opcodeTable[o].name } 22875 func (o Op) UsesScratch() bool { return opcodeTable[o].usesScratch } 22876 22877 var registers386 = [...]Register{ 22878 {0, x86.REG_AX, "AX"}, 22879 {1, x86.REG_CX, "CX"}, 22880 {2, x86.REG_DX, "DX"}, 22881 {3, x86.REG_BX, "BX"}, 22882 {4, x86.REGSP, "SP"}, 22883 {5, x86.REG_BP, "BP"}, 22884 {6, x86.REG_SI, "SI"}, 22885 {7, x86.REG_DI, "DI"}, 22886 {8, x86.REG_X0, "X0"}, 22887 {9, x86.REG_X1, "X1"}, 22888 {10, x86.REG_X2, "X2"}, 22889 {11, x86.REG_X3, "X3"}, 22890 {12, x86.REG_X4, "X4"}, 22891 {13, x86.REG_X5, "X5"}, 22892 {14, x86.REG_X6, "X6"}, 22893 {15, x86.REG_X7, "X7"}, 22894 {16, 0, "SB"}, 22895 } 22896 var gpRegMask386 = regMask(239) 22897 var fpRegMask386 = regMask(65280) 22898 var specialRegMask386 = regMask(0) 22899 var framepointerReg386 = int8(5) 22900 var linkReg386 = int8(-1) 22901 var registersAMD64 = [...]Register{ 22902 {0, x86.REG_AX, "AX"}, 22903 {1, x86.REG_CX, "CX"}, 22904 {2, x86.REG_DX, "DX"}, 22905 {3, x86.REG_BX, "BX"}, 22906 {4, x86.REGSP, "SP"}, 22907 {5, x86.REG_BP, "BP"}, 22908 {6, x86.REG_SI, "SI"}, 22909 {7, x86.REG_DI, "DI"}, 22910 {8, x86.REG_R8, "R8"}, 22911 {9, x86.REG_R9, "R9"}, 22912 {10, x86.REG_R10, "R10"}, 22913 {11, x86.REG_R11, "R11"}, 22914 {12, x86.REG_R12, "R12"}, 22915 {13, x86.REG_R13, "R13"}, 22916 {14, x86.REG_R14, "R14"}, 22917 {15, x86.REG_R15, "R15"}, 22918 {16, x86.REG_X0, "X0"}, 22919 {17, x86.REG_X1, "X1"}, 22920 {18, x86.REG_X2, "X2"}, 22921 {19, x86.REG_X3, "X3"}, 22922 {20, x86.REG_X4, "X4"}, 22923 {21, x86.REG_X5, "X5"}, 22924 {22, x86.REG_X6, "X6"}, 22925 {23, x86.REG_X7, "X7"}, 22926 {24, x86.REG_X8, "X8"}, 22927 {25, x86.REG_X9, "X9"}, 22928 {26, x86.REG_X10, "X10"}, 22929 {27, x86.REG_X11, "X11"}, 22930 {28, x86.REG_X12, "X12"}, 22931 {29, x86.REG_X13, "X13"}, 22932 {30, x86.REG_X14, "X14"}, 22933 {31, x86.REG_X15, "X15"}, 22934 {32, 0, "SB"}, 22935 } 22936 var gpRegMaskAMD64 = regMask(65519) 22937 var fpRegMaskAMD64 = regMask(4294901760) 22938 var specialRegMaskAMD64 = regMask(0) 22939 var framepointerRegAMD64 = int8(5) 22940 var linkRegAMD64 = int8(-1) 22941 var registersARM = [...]Register{ 22942 {0, arm.REG_R0, "R0"}, 22943 {1, arm.REG_R1, "R1"}, 22944 {2, arm.REG_R2, "R2"}, 22945 {3, arm.REG_R3, "R3"}, 22946 {4, arm.REG_R4, "R4"}, 22947 {5, arm.REG_R5, "R5"}, 22948 {6, arm.REG_R6, "R6"}, 22949 {7, arm.REG_R7, "R7"}, 22950 {8, arm.REG_R8, "R8"}, 22951 {9, arm.REG_R9, "R9"}, 22952 {10, arm.REGG, "g"}, 22953 {11, arm.REG_R11, "R11"}, 22954 {12, arm.REG_R12, "R12"}, 22955 {13, arm.REGSP, "SP"}, 22956 {14, arm.REG_R14, "R14"}, 22957 {15, arm.REG_R15, "R15"}, 22958 {16, arm.REG_F0, "F0"}, 22959 {17, arm.REG_F1, "F1"}, 22960 {18, arm.REG_F2, "F2"}, 22961 {19, arm.REG_F3, "F3"}, 22962 {20, arm.REG_F4, "F4"}, 22963 {21, arm.REG_F5, "F5"}, 22964 {22, arm.REG_F6, "F6"}, 22965 {23, arm.REG_F7, "F7"}, 22966 {24, arm.REG_F8, "F8"}, 22967 {25, arm.REG_F9, "F9"}, 22968 {26, arm.REG_F10, "F10"}, 22969 {27, arm.REG_F11, "F11"}, 22970 {28, arm.REG_F12, "F12"}, 22971 {29, arm.REG_F13, "F13"}, 22972 {30, arm.REG_F14, "F14"}, 22973 {31, arm.REG_F15, "F15"}, 22974 {32, 0, "SB"}, 22975 } 22976 var gpRegMaskARM = regMask(21503) 22977 var fpRegMaskARM = regMask(4294901760) 22978 var specialRegMaskARM = regMask(0) 22979 var framepointerRegARM = int8(-1) 22980 var linkRegARM = int8(14) 22981 var registersARM64 = [...]Register{ 22982 {0, arm64.REG_R0, "R0"}, 22983 {1, arm64.REG_R1, "R1"}, 22984 {2, arm64.REG_R2, "R2"}, 22985 {3, arm64.REG_R3, "R3"}, 22986 {4, arm64.REG_R4, "R4"}, 22987 {5, arm64.REG_R5, "R5"}, 22988 {6, arm64.REG_R6, "R6"}, 22989 {7, arm64.REG_R7, "R7"}, 22990 {8, arm64.REG_R8, "R8"}, 22991 {9, arm64.REG_R9, "R9"}, 22992 {10, arm64.REG_R10, "R10"}, 22993 {11, arm64.REG_R11, "R11"}, 22994 {12, arm64.REG_R12, "R12"}, 22995 {13, arm64.REG_R13, "R13"}, 22996 {14, arm64.REG_R14, "R14"}, 22997 {15, arm64.REG_R15, "R15"}, 22998 {16, arm64.REG_R16, "R16"}, 22999 {17, arm64.REG_R17, "R17"}, 23000 {18, arm64.REG_R18, "R18"}, 23001 {19, arm64.REG_R19, "R19"}, 23002 {20, arm64.REG_R20, "R20"}, 23003 {21, arm64.REG_R21, "R21"}, 23004 {22, arm64.REG_R22, "R22"}, 23005 {23, arm64.REG_R23, "R23"}, 23006 {24, arm64.REG_R24, "R24"}, 23007 {25, arm64.REG_R25, "R25"}, 23008 {26, arm64.REG_R26, "R26"}, 23009 {27, arm64.REGG, "g"}, 23010 {28, arm64.REG_R29, "R29"}, 23011 {29, arm64.REG_R30, "R30"}, 23012 {30, arm64.REGSP, "SP"}, 23013 {31, arm64.REG_F0, "F0"}, 23014 {32, arm64.REG_F1, "F1"}, 23015 {33, arm64.REG_F2, "F2"}, 23016 {34, arm64.REG_F3, "F3"}, 23017 {35, arm64.REG_F4, "F4"}, 23018 {36, arm64.REG_F5, "F5"}, 23019 {37, arm64.REG_F6, "F6"}, 23020 {38, arm64.REG_F7, "F7"}, 23021 {39, arm64.REG_F8, "F8"}, 23022 {40, arm64.REG_F9, "F9"}, 23023 {41, arm64.REG_F10, "F10"}, 23024 {42, arm64.REG_F11, "F11"}, 23025 {43, arm64.REG_F12, "F12"}, 23026 {44, arm64.REG_F13, "F13"}, 23027 {45, arm64.REG_F14, "F14"}, 23028 {46, arm64.REG_F15, "F15"}, 23029 {47, arm64.REG_F16, "F16"}, 23030 {48, arm64.REG_F17, "F17"}, 23031 {49, arm64.REG_F18, "F18"}, 23032 {50, arm64.REG_F19, "F19"}, 23033 {51, arm64.REG_F20, "F20"}, 23034 {52, arm64.REG_F21, "F21"}, 23035 {53, arm64.REG_F22, "F22"}, 23036 {54, arm64.REG_F23, "F23"}, 23037 {55, arm64.REG_F24, "F24"}, 23038 {56, arm64.REG_F25, "F25"}, 23039 {57, arm64.REG_F26, "F26"}, 23040 {58, arm64.REG_F27, "F27"}, 23041 {59, arm64.REG_F28, "F28"}, 23042 {60, arm64.REG_F29, "F29"}, 23043 {61, arm64.REG_F30, "F30"}, 23044 {62, arm64.REG_F31, "F31"}, 23045 {63, 0, "SB"}, 23046 } 23047 var gpRegMaskARM64 = regMask(670826495) 23048 var fpRegMaskARM64 = regMask(9223372034707292160) 23049 var specialRegMaskARM64 = regMask(0) 23050 var framepointerRegARM64 = int8(-1) 23051 var linkRegARM64 = int8(29) 23052 var registersMIPS = [...]Register{ 23053 {0, mips.REG_R0, "R0"}, 23054 {1, mips.REG_R1, "R1"}, 23055 {2, mips.REG_R2, "R2"}, 23056 {3, mips.REG_R3, "R3"}, 23057 {4, mips.REG_R4, "R4"}, 23058 {5, mips.REG_R5, "R5"}, 23059 {6, mips.REG_R6, "R6"}, 23060 {7, mips.REG_R7, "R7"}, 23061 {8, mips.REG_R8, "R8"}, 23062 {9, mips.REG_R9, "R9"}, 23063 {10, mips.REG_R10, "R10"}, 23064 {11, mips.REG_R11, "R11"}, 23065 {12, mips.REG_R12, "R12"}, 23066 {13, mips.REG_R13, "R13"}, 23067 {14, mips.REG_R14, "R14"}, 23068 {15, mips.REG_R15, "R15"}, 23069 {16, mips.REG_R16, "R16"}, 23070 {17, mips.REG_R17, "R17"}, 23071 {18, mips.REG_R18, "R18"}, 23072 {19, mips.REG_R19, "R19"}, 23073 {20, mips.REG_R20, "R20"}, 23074 {21, mips.REG_R21, "R21"}, 23075 {22, mips.REG_R22, "R22"}, 23076 {23, mips.REG_R24, "R24"}, 23077 {24, mips.REG_R25, "R25"}, 23078 {25, mips.REG_R28, "R28"}, 23079 {26, mips.REGSP, "SP"}, 23080 {27, mips.REGG, "g"}, 23081 {28, mips.REG_R31, "R31"}, 23082 {29, mips.REG_F0, "F0"}, 23083 {30, mips.REG_F2, "F2"}, 23084 {31, mips.REG_F4, "F4"}, 23085 {32, mips.REG_F6, "F6"}, 23086 {33, mips.REG_F8, "F8"}, 23087 {34, mips.REG_F10, "F10"}, 23088 {35, mips.REG_F12, "F12"}, 23089 {36, mips.REG_F14, "F14"}, 23090 {37, mips.REG_F16, "F16"}, 23091 {38, mips.REG_F18, "F18"}, 23092 {39, mips.REG_F20, "F20"}, 23093 {40, mips.REG_F22, "F22"}, 23094 {41, mips.REG_F24, "F24"}, 23095 {42, mips.REG_F26, "F26"}, 23096 {43, mips.REG_F28, "F28"}, 23097 {44, mips.REG_F30, "F30"}, 23098 {45, mips.REG_HI, "HI"}, 23099 {46, mips.REG_LO, "LO"}, 23100 {47, 0, "SB"}, 23101 } 23102 var gpRegMaskMIPS = regMask(335544318) 23103 var fpRegMaskMIPS = regMask(35183835217920) 23104 var specialRegMaskMIPS = regMask(105553116266496) 23105 var framepointerRegMIPS = int8(-1) 23106 var linkRegMIPS = int8(28) 23107 var registersMIPS64 = [...]Register{ 23108 {0, mips.REG_R0, "R0"}, 23109 {1, mips.REG_R1, "R1"}, 23110 {2, mips.REG_R2, "R2"}, 23111 {3, mips.REG_R3, "R3"}, 23112 {4, mips.REG_R4, "R4"}, 23113 {5, mips.REG_R5, "R5"}, 23114 {6, mips.REG_R6, "R6"}, 23115 {7, mips.REG_R7, "R7"}, 23116 {8, mips.REG_R8, "R8"}, 23117 {9, mips.REG_R9, "R9"}, 23118 {10, mips.REG_R10, "R10"}, 23119 {11, mips.REG_R11, "R11"}, 23120 {12, mips.REG_R12, "R12"}, 23121 {13, mips.REG_R13, "R13"}, 23122 {14, mips.REG_R14, "R14"}, 23123 {15, mips.REG_R15, "R15"}, 23124 {16, mips.REG_R16, "R16"}, 23125 {17, mips.REG_R17, "R17"}, 23126 {18, mips.REG_R18, "R18"}, 23127 {19, mips.REG_R19, "R19"}, 23128 {20, mips.REG_R20, "R20"}, 23129 {21, mips.REG_R21, "R21"}, 23130 {22, mips.REG_R22, "R22"}, 23131 {23, mips.REG_R24, "R24"}, 23132 {24, mips.REG_R25, "R25"}, 23133 {25, mips.REGSP, "SP"}, 23134 {26, mips.REGG, "g"}, 23135 {27, mips.REG_R31, "R31"}, 23136 {28, mips.REG_F0, "F0"}, 23137 {29, mips.REG_F1, "F1"}, 23138 {30, mips.REG_F2, "F2"}, 23139 {31, mips.REG_F3, "F3"}, 23140 {32, mips.REG_F4, "F4"}, 23141 {33, mips.REG_F5, "F5"}, 23142 {34, mips.REG_F6, "F6"}, 23143 {35, mips.REG_F7, "F7"}, 23144 {36, mips.REG_F8, "F8"}, 23145 {37, mips.REG_F9, "F9"}, 23146 {38, mips.REG_F10, "F10"}, 23147 {39, mips.REG_F11, "F11"}, 23148 {40, mips.REG_F12, "F12"}, 23149 {41, mips.REG_F13, "F13"}, 23150 {42, mips.REG_F14, "F14"}, 23151 {43, mips.REG_F15, "F15"}, 23152 {44, mips.REG_F16, "F16"}, 23153 {45, mips.REG_F17, "F17"}, 23154 {46, mips.REG_F18, "F18"}, 23155 {47, mips.REG_F19, "F19"}, 23156 {48, mips.REG_F20, "F20"}, 23157 {49, mips.REG_F21, "F21"}, 23158 {50, mips.REG_F22, "F22"}, 23159 {51, mips.REG_F23, "F23"}, 23160 {52, mips.REG_F24, "F24"}, 23161 {53, mips.REG_F25, "F25"}, 23162 {54, mips.REG_F26, "F26"}, 23163 {55, mips.REG_F27, "F27"}, 23164 {56, mips.REG_F28, "F28"}, 23165 {57, mips.REG_F29, "F29"}, 23166 {58, mips.REG_F30, "F30"}, 23167 {59, mips.REG_F31, "F31"}, 23168 {60, mips.REG_HI, "HI"}, 23169 {61, mips.REG_LO, "LO"}, 23170 {62, 0, "SB"}, 23171 } 23172 var gpRegMaskMIPS64 = regMask(167772158) 23173 var fpRegMaskMIPS64 = regMask(1152921504338411520) 23174 var specialRegMaskMIPS64 = regMask(3458764513820540928) 23175 var framepointerRegMIPS64 = int8(-1) 23176 var linkRegMIPS64 = int8(27) 23177 var registersPPC64 = [...]Register{ 23178 {0, ppc64.REG_R0, "R0"}, 23179 {1, ppc64.REGSP, "SP"}, 23180 {2, 0, "SB"}, 23181 {3, ppc64.REG_R3, "R3"}, 23182 {4, ppc64.REG_R4, "R4"}, 23183 {5, ppc64.REG_R5, "R5"}, 23184 {6, ppc64.REG_R6, "R6"}, 23185 {7, ppc64.REG_R7, "R7"}, 23186 {8, ppc64.REG_R8, "R8"}, 23187 {9, ppc64.REG_R9, "R9"}, 23188 {10, ppc64.REG_R10, "R10"}, 23189 {11, ppc64.REG_R11, "R11"}, 23190 {12, ppc64.REG_R12, "R12"}, 23191 {13, ppc64.REG_R13, "R13"}, 23192 {14, ppc64.REG_R14, "R14"}, 23193 {15, ppc64.REG_R15, "R15"}, 23194 {16, ppc64.REG_R16, "R16"}, 23195 {17, ppc64.REG_R17, "R17"}, 23196 {18, ppc64.REG_R18, "R18"}, 23197 {19, ppc64.REG_R19, "R19"}, 23198 {20, ppc64.REG_R20, "R20"}, 23199 {21, ppc64.REG_R21, "R21"}, 23200 {22, ppc64.REG_R22, "R22"}, 23201 {23, ppc64.REG_R23, "R23"}, 23202 {24, ppc64.REG_R24, "R24"}, 23203 {25, ppc64.REG_R25, "R25"}, 23204 {26, ppc64.REG_R26, "R26"}, 23205 {27, ppc64.REG_R27, "R27"}, 23206 {28, ppc64.REG_R28, "R28"}, 23207 {29, ppc64.REG_R29, "R29"}, 23208 {30, ppc64.REGG, "g"}, 23209 {31, ppc64.REG_R31, "R31"}, 23210 {32, ppc64.REG_F0, "F0"}, 23211 {33, ppc64.REG_F1, "F1"}, 23212 {34, ppc64.REG_F2, "F2"}, 23213 {35, ppc64.REG_F3, "F3"}, 23214 {36, ppc64.REG_F4, "F4"}, 23215 {37, ppc64.REG_F5, "F5"}, 23216 {38, ppc64.REG_F6, "F6"}, 23217 {39, ppc64.REG_F7, "F7"}, 23218 {40, ppc64.REG_F8, "F8"}, 23219 {41, ppc64.REG_F9, "F9"}, 23220 {42, ppc64.REG_F10, "F10"}, 23221 {43, ppc64.REG_F11, "F11"}, 23222 {44, ppc64.REG_F12, "F12"}, 23223 {45, ppc64.REG_F13, "F13"}, 23224 {46, ppc64.REG_F14, "F14"}, 23225 {47, ppc64.REG_F15, "F15"}, 23226 {48, ppc64.REG_F16, "F16"}, 23227 {49, ppc64.REG_F17, "F17"}, 23228 {50, ppc64.REG_F18, "F18"}, 23229 {51, ppc64.REG_F19, "F19"}, 23230 {52, ppc64.REG_F20, "F20"}, 23231 {53, ppc64.REG_F21, "F21"}, 23232 {54, ppc64.REG_F22, "F22"}, 23233 {55, ppc64.REG_F23, "F23"}, 23234 {56, ppc64.REG_F24, "F24"}, 23235 {57, ppc64.REG_F25, "F25"}, 23236 {58, ppc64.REG_F26, "F26"}, 23237 {59, ppc64.REG_F27, "F27"}, 23238 {60, ppc64.REG_F28, "F28"}, 23239 {61, ppc64.REG_F29, "F29"}, 23240 {62, ppc64.REG_F30, "F30"}, 23241 {63, ppc64.REG_F31, "F31"}, 23242 } 23243 var gpRegMaskPPC64 = regMask(1073733624) 23244 var fpRegMaskPPC64 = regMask(576460743713488896) 23245 var specialRegMaskPPC64 = regMask(0) 23246 var framepointerRegPPC64 = int8(1) 23247 var linkRegPPC64 = int8(-1) 23248 var registersRISCV = [...]Register{ 23249 {0, riscv.REG_ZERO, "ZERO"}, 23250 {1, riscv.REGSP, "SP"}, 23251 {2, riscv.REG_GP, "GP"}, 23252 {3, riscv.REGG, "g"}, 23253 {4, riscv.REG_T0, "T0"}, 23254 {5, riscv.REG_T1, "T1"}, 23255 {6, riscv.REG_T2, "T2"}, 23256 {7, riscv.REG_S0, "S0"}, 23257 {8, riscv.REG_S1, "S1"}, 23258 {9, riscv.REG_A0, "A0"}, 23259 {10, riscv.REG_A1, "A1"}, 23260 {11, riscv.REG_A2, "A2"}, 23261 {12, riscv.REG_A3, "A3"}, 23262 {13, riscv.REG_A4, "A4"}, 23263 {14, riscv.REG_A5, "A5"}, 23264 {15, riscv.REG_A6, "A6"}, 23265 {16, riscv.REG_A7, "A7"}, 23266 {17, riscv.REG_S2, "S2"}, 23267 {18, riscv.REG_S3, "S3"}, 23268 {19, riscv.REG_CTXT, "CTXT"}, 23269 {20, riscv.REG_S5, "S5"}, 23270 {21, riscv.REG_S6, "S6"}, 23271 {22, riscv.REG_S7, "S7"}, 23272 {23, riscv.REG_S8, "S8"}, 23273 {24, riscv.REG_S9, "S9"}, 23274 {25, riscv.REG_S10, "S10"}, 23275 {26, riscv.REG_S11, "S11"}, 23276 {27, riscv.REG_T3, "T3"}, 23277 {28, riscv.REG_T4, "T4"}, 23278 {29, riscv.REG_T5, "T5"}, 23279 {30, riscv.REG_TMP, "TMP"}, 23280 {31, riscv.REG_FT0, "FT0"}, 23281 {32, riscv.REG_FT1, "FT1"}, 23282 {33, riscv.REG_FT2, "FT2"}, 23283 {34, riscv.REG_FT3, "FT3"}, 23284 {35, riscv.REG_FT4, "FT4"}, 23285 {36, riscv.REG_FT5, "FT5"}, 23286 {37, riscv.REG_FT6, "FT6"}, 23287 {38, riscv.REG_FT7, "FT7"}, 23288 {39, riscv.REG_FS0, "FS0"}, 23289 {40, riscv.REG_FS1, "FS1"}, 23290 {41, riscv.REG_FA0, "FA0"}, 23291 {42, riscv.REG_FA1, "FA1"}, 23292 {43, riscv.REG_FA2, "FA2"}, 23293 {44, riscv.REG_FA3, "FA3"}, 23294 {45, riscv.REG_FA4, "FA4"}, 23295 {46, riscv.REG_FA5, "FA5"}, 23296 {47, riscv.REG_FA6, "FA6"}, 23297 {48, riscv.REG_FA7, "FA7"}, 23298 {49, riscv.REG_FS2, "FS2"}, 23299 {50, riscv.REG_FS3, "FS3"}, 23300 {51, riscv.REG_FS4, "FS4"}, 23301 {52, riscv.REG_FS5, "FS5"}, 23302 {53, riscv.REG_FS6, "FS6"}, 23303 {54, riscv.REG_FS7, "FS7"}, 23304 {55, riscv.REG_FS8, "FS8"}, 23305 {56, riscv.REG_FS9, "FS9"}, 23306 {57, riscv.REG_FS10, "FS10"}, 23307 {58, riscv.REG_FS11, "FS11"}, 23308 {59, riscv.REG_FT8, "FT8"}, 23309 {60, riscv.REG_FT9, "FT9"}, 23310 {61, riscv.REG_FT10, "FT10"}, 23311 {62, riscv.REG_FT11, "FT11"}, 23312 {63, 0, "SB"}, 23313 } 23314 var gpRegMaskRISCV = regMask(1073741812) 23315 var fpRegMaskRISCV = regMask(9223372034707292160) 23316 var specialRegMaskRISCV = regMask(0) 23317 var framepointerRegRISCV = int8(-1) 23318 var linkRegRISCV = int8(0) 23319 var registersS390X = [...]Register{ 23320 {0, s390x.REG_R0, "R0"}, 23321 {1, s390x.REG_R1, "R1"}, 23322 {2, s390x.REG_R2, "R2"}, 23323 {3, s390x.REG_R3, "R3"}, 23324 {4, s390x.REG_R4, "R4"}, 23325 {5, s390x.REG_R5, "R5"}, 23326 {6, s390x.REG_R6, "R6"}, 23327 {7, s390x.REG_R7, "R7"}, 23328 {8, s390x.REG_R8, "R8"}, 23329 {9, s390x.REG_R9, "R9"}, 23330 {10, s390x.REG_R10, "R10"}, 23331 {11, s390x.REG_R11, "R11"}, 23332 {12, s390x.REG_R12, "R12"}, 23333 {13, s390x.REGG, "g"}, 23334 {14, s390x.REG_R14, "R14"}, 23335 {15, s390x.REGSP, "SP"}, 23336 {16, s390x.REG_F0, "F0"}, 23337 {17, s390x.REG_F1, "F1"}, 23338 {18, s390x.REG_F2, "F2"}, 23339 {19, s390x.REG_F3, "F3"}, 23340 {20, s390x.REG_F4, "F4"}, 23341 {21, s390x.REG_F5, "F5"}, 23342 {22, s390x.REG_F6, "F6"}, 23343 {23, s390x.REG_F7, "F7"}, 23344 {24, s390x.REG_F8, "F8"}, 23345 {25, s390x.REG_F9, "F9"}, 23346 {26, s390x.REG_F10, "F10"}, 23347 {27, s390x.REG_F11, "F11"}, 23348 {28, s390x.REG_F12, "F12"}, 23349 {29, s390x.REG_F13, "F13"}, 23350 {30, s390x.REG_F14, "F14"}, 23351 {31, s390x.REG_F15, "F15"}, 23352 {32, 0, "SB"}, 23353 } 23354 var gpRegMaskS390X = regMask(21503) 23355 var fpRegMaskS390X = regMask(4294901760) 23356 var specialRegMaskS390X = regMask(0) 23357 var framepointerRegS390X = int8(-1) 23358 var linkRegS390X = int8(14)