github.com/rohankumardubey/syslog-redirector-golang@v0.0.0-20140320174030-4859f03d829a/src/cmd/5g/prog.c (about)

     1  // Copyright 2013 The Go Authors.  All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  #include <u.h>
     6  #include <libc.h>
     7  #include "gg.h"
     8  #include "opt.h"
     9  
    10  enum
    11  {
    12  	RightRdwr = RightRead | RightWrite,
    13  };
    14  
    15  // This table gives the basic information about instruction
    16  // generated by the compiler and processed in the optimizer.
    17  // See opt.h for bit definitions.
    18  //
    19  // Instructions not generated need not be listed.
    20  // As an exception to that rule, we typically write down all the
    21  // size variants of an operation even if we just use a subset.
    22  //
    23  // The table is formatted for 8-space tabs.
    24  static ProgInfo progtable[ALAST] = {
    25  	[ATYPE]=	{Pseudo | Skip},
    26  	[ATEXT]=	{Pseudo},
    27  	[AFUNCDATA]=	{Pseudo},
    28  	[APCDATA]=	{Pseudo},
    29  	[AUNDEF]=	{OK},
    30  	[AUSEFIELD]=	{OK},
    31  	[ACHECKNIL]=	{LeftRead},
    32  
    33  	// NOP is an internal no-op that also stands
    34  	// for USED and SET annotations, not the Intel opcode.
    35  	[ANOP]=		{LeftRead | RightWrite},
    36  	
    37  	// Integer.
    38  	[AADC]=		{SizeL | LeftRead | RegRead | RightWrite},
    39  	[AADD]=		{SizeL | LeftRead | RegRead | RightWrite},
    40  	[AAND]=		{SizeL | LeftRead | RegRead | RightWrite},
    41  	[ABIC]=		{SizeL | LeftRead | RegRead | RightWrite},
    42  	[ACMN]=		{SizeL | LeftRead | RightRead},
    43  	[ACMP]=		{SizeL | LeftRead | RightRead},
    44  	[ADIVU]=	{SizeL | LeftRead | RegRead | RightWrite},
    45  	[ADIV]=		{SizeL | LeftRead | RegRead | RightWrite},
    46  	[AEOR]=		{SizeL | LeftRead | RegRead | RightWrite},
    47  	[AMODU]=	{SizeL | LeftRead | RegRead | RightWrite},
    48  	[AMOD]=		{SizeL | LeftRead | RegRead | RightWrite},
    49  	[AMULALU]=	{SizeL | LeftRead | RegRead | RightRdwr},
    50  	[AMULAL]=	{SizeL | LeftRead | RegRead | RightRdwr},
    51  	[AMULA]=	{SizeL | LeftRead | RegRead | RightRdwr},
    52  	[AMULU]=	{SizeL | LeftRead | RegRead | RightWrite},
    53  	[AMUL]=		{SizeL | LeftRead | RegRead | RightWrite},
    54  	[AMULL]=	{SizeL | LeftRead | RegRead | RightWrite},
    55  	[AMULLU]=	{SizeL | LeftRead | RegRead | RightWrite},
    56  	[AMVN]=		{SizeL | LeftRead | RightWrite},
    57  	[AORR]=		{SizeL | LeftRead | RegRead | RightWrite},
    58  	[ARSB]=		{SizeL | LeftRead | RegRead | RightWrite},
    59  	[ARSC]=		{SizeL | LeftRead | RegRead | RightWrite},
    60  	[ASBC]=		{SizeL | LeftRead | RegRead | RightWrite},
    61  	[ASLL]=		{SizeL | LeftRead | RegRead | RightWrite},
    62  	[ASRA]=		{SizeL | LeftRead | RegRead | RightWrite},
    63  	[ASRL]=		{SizeL | LeftRead | RegRead | RightWrite},
    64  	[ASUB]=		{SizeL | LeftRead | RegRead | RightWrite},
    65  	[ATEQ]=		{SizeL | LeftRead | RightRead},
    66  	[ATST]=		{SizeL | LeftRead | RightRead},
    67  
    68  	// Floating point.
    69  	[AADDD]=	{SizeD | LeftRead | RightRdwr},
    70  	[AADDF]=	{SizeF | LeftRead | RightRdwr},
    71  	[ACMPD]=	{SizeD | LeftRead | RightRead},
    72  	[ACMPF]=	{SizeF | LeftRead | RightRead},
    73  	[ADIVD]=	{SizeD | LeftRead | RightRdwr},
    74  	[ADIVF]=	{SizeF | LeftRead | RightRdwr},
    75  	[AMULD]=	{SizeD | LeftRead | RightRdwr},
    76  	[AMULF]=	{SizeF | LeftRead | RightRdwr},
    77  	[ASUBD]=	{SizeD | LeftRead | RightRdwr},
    78  	[ASUBF]=	{SizeF | LeftRead | RightRdwr},
    79  
    80  	// Conversions.
    81  	[AMOVWD]=		{SizeD | LeftRead | RightWrite | Conv},
    82  	[AMOVWF]=		{SizeF | LeftRead | RightWrite | Conv},
    83  	[AMOVDF]=		{SizeF | LeftRead | RightWrite | Conv},
    84  	[AMOVDW]=		{SizeL | LeftRead | RightWrite | Conv},
    85  	[AMOVFD]=		{SizeD | LeftRead | RightWrite | Conv},
    86  	[AMOVFW]=		{SizeL | LeftRead | RightWrite | Conv},
    87  
    88  	// Moves.
    89  	[AMOVB]=		{SizeB | LeftRead | RightWrite | Move},
    90  	[AMOVD]=		{SizeD | LeftRead | RightWrite | Move},
    91  	[AMOVF]=		{SizeF | LeftRead | RightWrite | Move},
    92  	[AMOVH]=		{SizeW | LeftRead | RightWrite | Move},
    93  	[AMOVW]=		{SizeL | LeftRead | RightWrite | Move},
    94  
    95  	// These should be split into the two different conversions instead
    96  	// of overloading the one.
    97  	[AMOVBS]=		{SizeB | LeftRead | RightWrite | Conv},
    98  	[AMOVBU]=		{SizeB | LeftRead | RightWrite | Conv},
    99  	[AMOVHS]=		{SizeW | LeftRead | RightWrite | Conv},
   100  	[AMOVHU]=		{SizeW | LeftRead | RightWrite | Conv},
   101  	
   102  	// Jumps.
   103  	[AB]=		{Jump | Break},
   104  	[ABL]=		{Call},
   105  	[ABEQ]=		{Cjmp},
   106  	[ABNE]=		{Cjmp},
   107  	[ABCS]=		{Cjmp},
   108  	[ABHS]=		{Cjmp},
   109  	[ABCC]=		{Cjmp},
   110  	[ABLO]=		{Cjmp},
   111  	[ABMI]=		{Cjmp},
   112  	[ABPL]=		{Cjmp},
   113  	[ABVS]=		{Cjmp},
   114  	[ABVC]=		{Cjmp},
   115  	[ABHI]=		{Cjmp},
   116  	[ABLS]=		{Cjmp},
   117  	[ABGE]=		{Cjmp},
   118  	[ABLT]=		{Cjmp},
   119  	[ABGT]=		{Cjmp},
   120  	[ABLE]=		{Cjmp},
   121  	[ARET]=		{Break},
   122  };
   123  
   124  void
   125  proginfo(ProgInfo *info, Prog *p)
   126  {
   127  	*info = progtable[p->as];
   128  	if(info->flags == 0)
   129  		fatal("unknown instruction %P", p);
   130  
   131  	if(p->from.type == D_CONST && p->from.sym != nil && (info->flags & LeftRead)) {
   132  		info->flags &= ~LeftRead;
   133  		info->flags |= LeftAddr;
   134  	}
   135  
   136  	if((info->flags & RegRead) && p->reg == NREG) {
   137  		info->flags &= ~RegRead;
   138  		info->flags |= CanRegRead | RightRead;
   139  	}
   140  	
   141  	if(((p->scond & C_SCOND) != C_SCOND_NONE) && (info->flags & RightWrite))
   142  		info->flags |= RightRead;
   143  }