github.com/sagernet/gvisor@v0.0.0-20240428053021-e691de28565f/pkg/abi/nvgpu/ctrl.go (about) 1 // Copyright 2023 The gVisor Authors. 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 package nvgpu 16 17 // From src/nvidia/interface/deprecated/rmapi_deprecated.h: 18 const ( 19 RM_GSS_LEGACY_MASK = 0x00008000 20 ) 21 22 // From src/nvidia/inc/kernel/rmapi/param_copy.h: 23 const ( 24 // RMAPI_PARAM_COPY_MAX_PARAMS_SIZE is the size limit imposed while copying 25 // "embedded pointers" in rmapi parameter structs. 26 // See src/nvidia/src/kernel/rmapi/param_copy.c:rmapiParamsAcquire(). 27 RMAPI_PARAM_COPY_MAX_PARAMS_SIZE = 1 * 1024 * 1024 28 ) 29 30 // From src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h: 31 32 // +marshal 33 type NVXXXX_CTRL_XXX_INFO struct { 34 Index uint32 35 Data uint32 36 } 37 38 // From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h: 39 const ( 40 NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE = 0xd01 41 NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY = 0xd04 42 ) 43 44 // From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h: 45 const ( 46 NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS = 0x201 47 NV0000_CTRL_CMD_GPU_GET_ID_INFO = 0x202 48 NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 = 0x205 49 NV0000_CTRL_CMD_GPU_GET_PROBED_IDS = 0x214 50 NV0000_CTRL_CMD_GPU_ATTACH_IDS = 0x215 51 NV0000_CTRL_CMD_GPU_DETACH_IDS = 0x216 52 NV0000_CTRL_CMD_GPU_GET_PCI_INFO = 0x21b 53 NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE = 0x279 54 NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE = 0x27b 55 NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID = 0x289 56 NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID = 0x290 57 ) 58 59 // From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h: 60 const ( 61 NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO = 0xa04 62 ) 63 64 // From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h: 65 const ( 66 NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION = 0x101 67 NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS = 0x127 68 NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 = 0x12b 69 NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS = 0x136 70 NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX = 0x13a 71 NV0000_CTRL_CMD_SYSTEM_GET_FEATURES = 0x1f0 72 ) 73 74 // +marshal 75 type NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS struct { 76 SizeOfStrings uint32 77 Pad [4]byte 78 PDriverVersionBuffer P64 79 PVersionBuffer P64 80 PTitleBuffer P64 81 ChangelistNumber uint32 82 OfficialChangelistNumber uint32 83 } 84 85 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h: 86 const ( 87 NV0080_CTRL_CMD_FB_GET_CAPS_V2 = 0x801307 88 ) 89 90 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h: 91 const ( 92 NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST = 0x80170d 93 ) 94 95 // +marshal 96 type NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS struct { 97 NumChannels uint32 98 Pad [4]byte 99 PChannelHandleList P64 100 PChannelList P64 101 } 102 103 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h: 104 const ( 105 NV0080_CTRL_CMD_GPU_GET_CLASSLIST = 0x800201 106 NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES = 0x800280 107 NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE = 0x800288 108 NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE = 0x800289 109 NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 = 0x800292 110 ) 111 112 // +marshal 113 type NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS struct { 114 NumClasses uint32 115 Pad [4]byte 116 ClassList P64 117 } 118 119 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h: 120 121 // +marshal 122 type NV0080_CTRL_GR_ROUTE_INFO struct { 123 Flags uint32 124 Pad [4]byte 125 Route uint64 126 } 127 128 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h: 129 const ( 130 NV0080_CTRL_CMD_HOST_GET_CAPS_V2 = 0x801402 131 ) 132 133 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h: 134 const ( 135 NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL = 0x801909 136 ) 137 138 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h: 139 const ( 140 NV2080_CTRL_CMD_BUS_GET_PCI_INFO = 0x20801801 141 NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO = 0x20801803 142 NV2080_CTRL_CMD_BUS_GET_INFO_V2 = 0x20801823 143 NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS = 0x2080182a 144 NV2080_CTRL_CMD_BUS_GET_C2C_INFO = 0x2080182b 145 ) 146 147 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h: 148 const ( 149 NV2080_CTRL_CMD_CE_GET_ALL_CAPS = 0x20802a0a 150 ) 151 152 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h: 153 const ( 154 NV2080_CTRL_CMD_FB_GET_INFO_V2 = 0x20801303 155 ) 156 157 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h: 158 const ( 159 NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS = 0x2080110b 160 161 NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES = 64 162 ) 163 164 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h: 165 const ( 166 NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE = 0x20803125 167 ) 168 169 // +marshal 170 type NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS struct { 171 BDisable uint8 172 Pad1 [3]byte 173 NumChannels uint32 174 BOnlyDisableScheduling uint8 175 BRewindGpPut uint8 176 Pad2 [6]byte 177 PRunlistPreemptEvent P64 178 HClientList [NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]Handle 179 HChannelList [NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]Handle 180 } 181 182 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h: 183 const ( 184 NV2080_CTRL_CMD_GPU_GET_INFO_V2 = 0x20800102 185 NV2080_CTRL_CMD_GPU_GET_NAME_STRING = 0x20800110 186 NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING = 0x20800111 187 NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO = 0x20800119 188 NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS = 0x2080012f 189 NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES = 0x20800131 190 NV2080_CTRL_CMD_GPU_ACQUIRE_COMPUTE_MODE_RESERVATION = 0x20800145 // undocumented; paramSize == 0 191 NV2080_CTRL_CMD_GPU_RELEASE_COMPUTE_MODE_RESERVATION = 0x20800146 // undocumented; paramSize == 0 192 NV2080_CTRL_CMD_GPU_GET_GID_INFO = 0x2080014a 193 NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 = 0x20800170 194 NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS = 0x2080018b 195 NV2080_CTRL_CMD_GPU_GET_PIDS = 0x2080018d 196 NV2080_CTRL_CMD_GPU_GET_PID_INFO = 0x2080018e 197 NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG = 0x20800195 198 NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO = 0x208001a3 199 ) 200 201 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h: 202 const ( 203 NV2080_CTRL_CMD_GR_GET_INFO = 0x20801201 204 NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE = 0x20801210 205 NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE = 0x20801218 206 NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER = 0x2080121b 207 NV2080_CTRL_CMD_GR_GET_CAPS_V2 = 0x20801227 208 NV2080_CTRL_CMD_GR_GET_GPC_MASK = 0x2080122a 209 NV2080_CTRL_CMD_GR_GET_TPC_MASK = 0x2080122b 210 NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER = 0x20801230 211 ) 212 213 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h: 214 const ( 215 NV2080_CTRL_CMD_GSP_GET_FEATURES = 0x20803601 216 ) 217 218 // +marshal 219 type NV2080_CTRL_GR_GET_INFO_PARAMS struct { 220 GRInfoListSize uint32 // in elements 221 Pad [4]byte 222 GRInfoList P64 223 GRRouteInfo NV0080_CTRL_GR_ROUTE_INFO 224 } 225 226 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h: 227 const ( 228 NV2080_CTRL_CMD_MC_GET_ARCH_INFO = 0x20801701 229 NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS = 0x20801702 230 ) 231 232 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h: 233 const ( 234 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS = 0x20803001 235 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS = 0x20803002 236 ) 237 238 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h: 239 const ( 240 NV2080_CTRL_CMD_PERF_BOOST = 0x2080200a 241 ) 242 243 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h: 244 const ( 245 NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO = 0x20802209 246 NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS = 0x2080220c 247 NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG = 0x20802210 248 ) 249 250 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h: 251 const ( 252 NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO = 0x20800406 253 ) 254 255 // From src/common/sdk/nvidia/inc/ctrl/ctrl503c.h: 256 const ( 257 NV503C_CTRL_CMD_REGISTER_VA_SPACE = 0x503c0102 258 NV503C_CTRL_CMD_REGISTER_VIDMEM = 0x503c0104 259 NV503C_CTRL_CMD_UNREGISTER_VIDMEM = 0x503c0105 260 ) 261 262 // From src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h: 263 const ( 264 NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK = 0x83de0309 265 NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES = 0x83de030c 266 NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES = 0x83de0310 267 ) 268 269 // From src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h: 270 const ( 271 NVC36F_CTRL_GET_CLASS_ENGINEID = 0xc36f0101 272 NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN = 0xc36f0108 273 ) 274 275 // From src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h: 276 const ( 277 NVC56F_CTRL_CMD_GET_KMB = 0xc56f010b 278 ) 279 280 // From src/common/sdk/nvidia/inc/ctrl/ctrl906f.h: 281 const ( 282 NV906F_CTRL_CMD_RESET_CHANNEL = 0x906f0102 283 ) 284 285 // From src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h: 286 const ( 287 NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK = 0x90e60102 288 ) 289 290 // From src/common/sdk/nvidia/inc/ctrl/ctrla06c.h: 291 const ( 292 NVA06C_CTRL_CMD_GPFIFO_SCHEDULE = 0xa06c0101 293 NVA06C_CTRL_CMD_SET_TIMESLICE = 0xa06c0103 294 NVA06C_CTRL_CMD_PREEMPT = 0xa06c0105 295 ) 296 297 // From src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h: 298 const ( 299 NVA06F_CTRL_CMD_GPFIFO_SCHEDULE = 0xa06f0103 300 ) 301 302 // From src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h: 303 const ( 304 NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES = 0xcb330101 305 NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE = 0xcb330104 306 NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS = 0xcb33010b 307 )