github.com/sagernet/gvisor@v0.0.0-20240428053021-e691de28565f/pkg/abi/nvgpu/nvgpu.go (about)

     1  // Copyright 2023 The gVisor Authors.
     2  //
     3  // Licensed under the Apache License, Version 2.0 (the "License");
     4  // you may not use this file except in compliance with the License.
     5  // You may obtain a copy of the License at
     6  //
     7  //     http://www.apache.org/licenses/LICENSE-2.0
     8  //
     9  // Unless required by applicable law or agreed to in writing, software
    10  // distributed under the License is distributed on an "AS IS" BASIS,
    11  // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    12  // See the License for the specific language governing permissions and
    13  // limitations under the License.
    14  
    15  // Package nvgpu tracks the ABI of the Nvidia GPU Linux kernel driver:
    16  // https://github.com/NVIDIA/open-gpu-kernel-modules
    17  package nvgpu
    18  
    19  import (
    20  	"fmt"
    21  )
    22  
    23  // Device numbers.
    24  const (
    25  	NV_MAJOR_DEVICE_NUMBER          = 195 // from kernel-open/common/inc/nv.h
    26  	NV_CONTROL_DEVICE_MINOR         = 255 // from kernel-open/common/inc/nv-linux.h
    27  	NVIDIA_UVM_PRIMARY_MINOR_NUMBER = 0   // from kernel-open/nvidia-uvm/uvm_common.h
    28  )
    29  
    30  // Handle is NvHandle, from src/common/sdk/nvidia/inc/nvtypes.h.
    31  //
    32  // +marshal
    33  type Handle struct {
    34  	Val uint32
    35  }
    36  
    37  // String implements fmt.Stringer.String.
    38  func (h Handle) String() string {
    39  	return fmt.Sprintf("%#x", h.Val)
    40  }
    41  
    42  // P64 is NvP64, from src/common/sdk/nvidia/inc/nvtypes.h.
    43  //
    44  // +marshal
    45  type P64 uint64
    46  
    47  // From src/common/sdk/nvidia/inc/nvlimits.h:
    48  const (
    49  	NV_MAX_DEVICES    = 32
    50  	NV_MAX_SUBDEVICES = 8
    51  )
    52  
    53  // From src/common/sdk/nvidia/inc/alloc/alloc_channel.h.
    54  const (
    55  	CC_CHAN_ALLOC_IV_SIZE_DWORD    = 3
    56  	CC_CHAN_ALLOC_NONCE_SIZE_DWORD = 8
    57  )
    58  
    59  // RS_ACCESS_MASK is RS_ACCESS_MASK, from
    60  // src/common/sdk/nvidia/inc/rs_access.h.
    61  //
    62  // +marshal
    63  type RS_ACCESS_MASK struct {
    64  	Limbs [SDK_RS_ACCESS_MAX_LIMBS]uint32 // RsAccessLimb
    65  }
    66  
    67  const SDK_RS_ACCESS_MAX_LIMBS = 1
    68  
    69  // RS_SHARE_POLICY is RS_SHARE_POLICY, from
    70  // src/common/sdk/nvidia/inc/rs_access.h.
    71  //
    72  // +marshal
    73  type RS_SHARE_POLICY struct {
    74  	Target     uint32
    75  	AccessMask RS_ACCESS_MASK
    76  	Type       uint16
    77  	Action     uint8
    78  	Pad        [1]byte
    79  }
    80  
    81  // NvUUID is defined in src/common/inc/nvCpuUuid.h.
    82  //
    83  // +marshal
    84  type NvUUID [16]uint8