github.com/sagernet/gvisor@v0.0.0-20240428053021-e691de28565f/pkg/abi/nvgpu/uvm.go (about) 1 // Copyright 2023 The gVisor Authors. 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 package nvgpu 16 17 // HasRMCtrlFD is a type constraint for UVM parameter structs containing a 18 // RMCtrlFD field. This is necessary because, as of this writing (Go 1.20), 19 // there is no way to enable field access using a Go type constraint. 20 type HasRMCtrlFD interface { 21 GetRMCtrlFD() int32 22 SetRMCtrlFD(int32) 23 } 24 25 // UVM ioctl commands. 26 const ( 27 // From kernel-open/nvidia-uvm/uvm_linux_ioctl.h: 28 UVM_INITIALIZE = 0x30000001 29 UVM_DEINITIALIZE = 0x30000002 30 31 // From kernel-open/nvidia-uvm/uvm_ioctl.h: 32 UVM_CREATE_RANGE_GROUP = 23 33 UVM_DESTROY_RANGE_GROUP = 24 34 UVM_REGISTER_GPU_VASPACE = 25 35 UVM_UNREGISTER_GPU_VASPACE = 26 36 UVM_REGISTER_CHANNEL = 27 37 UVM_UNREGISTER_CHANNEL = 28 38 UVM_MAP_EXTERNAL_ALLOCATION = 33 39 UVM_FREE = 34 40 UVM_REGISTER_GPU = 37 41 UVM_UNREGISTER_GPU = 38 42 UVM_PAGEABLE_MEM_ACCESS = 39 43 UVM_SET_PREFERRED_LOCATION = 42 44 UVM_DISABLE_READ_DUPLICATION = 45 45 UVM_MAP_DYNAMIC_PARALLELISM_REGION = 65 46 UVM_ALLOC_SEMAPHORE_POOL = 68 47 UVM_VALIDATE_VA_RANGE = 72 48 UVM_CREATE_EXTERNAL_RANGE = 73 49 UVM_MM_INITIALIZE = 75 50 ) 51 52 // +marshal 53 type UVM_INITIALIZE_PARAMS struct { 54 Flags uint64 55 RMStatus uint32 56 Pad0 [4]byte 57 } 58 59 // UVM_INITIALIZE_PARAMS flags, from kernel-open/nvidia-uvm/uvm_types.h. 60 const ( 61 UVM_INIT_FLAGS_MULTI_PROCESS_SHARING_MODE = 0x2 62 ) 63 64 // +marshal 65 type UVM_CREATE_RANGE_GROUP_PARAMS struct { 66 RangeGroupID uint64 67 RMStatus uint32 68 Pad0 [4]byte 69 } 70 71 // +marshal 72 type UVM_DESTROY_RANGE_GROUP_PARAMS struct { 73 RangeGroupID uint64 74 RMStatus uint32 75 Pad0 [4]byte 76 } 77 78 // +marshal 79 type UVM_REGISTER_GPU_VASPACE_PARAMS struct { 80 GPUUUID NvUUID 81 RMCtrlFD int32 82 HClient Handle 83 HVASpace Handle 84 RMStatus uint32 85 } 86 87 func (p *UVM_REGISTER_GPU_VASPACE_PARAMS) GetRMCtrlFD() int32 { 88 return p.RMCtrlFD 89 } 90 91 func (p *UVM_REGISTER_GPU_VASPACE_PARAMS) SetRMCtrlFD(fd int32) { 92 p.RMCtrlFD = fd 93 } 94 95 // +marshal 96 type UVM_UNREGISTER_GPU_VASPACE_PARAMS struct { 97 GPUUUID NvUUID 98 RMStatus uint32 99 } 100 101 // +marshal 102 type UVM_REGISTER_CHANNEL_PARAMS struct { 103 GPUUUID NvUUID 104 RMCtrlFD int32 105 HClient Handle 106 HChannel Handle 107 Pad [4]byte 108 Base uint64 109 Length uint64 110 RMStatus uint32 111 Pad0 [4]byte 112 } 113 114 func (p *UVM_REGISTER_CHANNEL_PARAMS) GetRMCtrlFD() int32 { 115 return p.RMCtrlFD 116 } 117 118 func (p *UVM_REGISTER_CHANNEL_PARAMS) SetRMCtrlFD(fd int32) { 119 p.RMCtrlFD = fd 120 } 121 122 // +marshal 123 type UVM_UNREGISTER_CHANNEL_PARAMS struct { 124 GPUUUID NvUUID 125 HClient Handle 126 HChannel Handle 127 RMStatus uint32 128 } 129 130 // +marshal 131 type UVM_MAP_EXTERNAL_ALLOCATION_PARAMS struct { 132 Base uint64 133 Length uint64 134 Offset uint64 135 PerGPUAttributes [UVM_MAX_GPUS]UvmGpuMappingAttributes 136 GPUAttributesCount uint64 137 RMCtrlFD int32 138 HClient Handle 139 HMemory Handle 140 RMStatus uint32 141 } 142 143 func (p *UVM_MAP_EXTERNAL_ALLOCATION_PARAMS) GetRMCtrlFD() int32 { 144 return p.RMCtrlFD 145 } 146 147 func (p *UVM_MAP_EXTERNAL_ALLOCATION_PARAMS) SetRMCtrlFD(fd int32) { 148 p.RMCtrlFD = fd 149 } 150 151 // +marshal 152 type UVM_MAP_EXTERNAL_ALLOCATION_PARAMS_V550 struct { 153 Base uint64 154 Length uint64 155 Offset uint64 156 PerGPUAttributes [UVM_MAX_GPUS_V2]UvmGpuMappingAttributes 157 GPUAttributesCount uint64 158 RMCtrlFD int32 159 HClient Handle 160 HMemory Handle 161 RMStatus uint32 162 } 163 164 func (p *UVM_MAP_EXTERNAL_ALLOCATION_PARAMS_V550) GetRMCtrlFD() int32 { 165 return p.RMCtrlFD 166 } 167 168 func (p *UVM_MAP_EXTERNAL_ALLOCATION_PARAMS_V550) SetRMCtrlFD(fd int32) { 169 p.RMCtrlFD = fd 170 } 171 172 // +marshal 173 type UVM_FREE_PARAMS struct { 174 Base uint64 175 Length uint64 176 RMStatus uint32 177 Pad0 [4]byte 178 } 179 180 // +marshal 181 type UVM_REGISTER_GPU_PARAMS struct { 182 GPUUUID NvUUID 183 NumaEnabled uint8 184 Pad [3]byte 185 NumaNodeID int32 186 RMCtrlFD int32 187 HClient Handle 188 HSMCPartRef Handle 189 RMStatus uint32 190 } 191 192 func (p *UVM_REGISTER_GPU_PARAMS) GetRMCtrlFD() int32 { 193 return p.RMCtrlFD 194 } 195 196 func (p *UVM_REGISTER_GPU_PARAMS) SetRMCtrlFD(fd int32) { 197 p.RMCtrlFD = fd 198 } 199 200 // +marshal 201 type UVM_UNREGISTER_GPU_PARAMS struct { 202 GPUUUID NvUUID 203 RMStatus uint32 204 } 205 206 // +marshal 207 type UVM_PAGEABLE_MEM_ACCESS_PARAMS struct { 208 PageableMemAccess uint8 209 Pad [3]byte 210 RMStatus uint32 211 } 212 213 // +marshal 214 type UVM_SET_PREFERRED_LOCATION_PARAMS struct { 215 RequestedBase uint64 216 Length uint64 217 PreferredLocation NvUUID 218 RMStatus uint32 219 Pad0 [4]byte 220 } 221 222 // +marshal 223 type UVM_SET_PREFERRED_LOCATION_PARAMS_V550 struct { 224 RequestedBase uint64 225 Length uint64 226 PreferredLocation NvUUID 227 PreferredCPUNumaNode int32 228 RMStatus uint32 229 } 230 231 // +marshal 232 type UVM_DISABLE_READ_DUPLICATION_PARAMS struct { 233 RequestedBase uint64 234 Length uint64 235 RMStatus uint32 236 Pad0 [4]byte 237 } 238 239 // +marshal 240 type UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS struct { 241 Base uint64 242 Length uint64 243 GPUUUID NvUUID 244 RMStatus uint32 245 Pad0 [4]byte 246 } 247 248 // +marshal 249 type UVM_ALLOC_SEMAPHORE_POOL_PARAMS struct { 250 Base uint64 251 Length uint64 252 PerGPUAttributes [UVM_MAX_GPUS]UvmGpuMappingAttributes 253 GPUAttributesCount uint64 254 RMStatus uint32 255 Pad0 [4]byte 256 } 257 258 // +marshal 259 type UVM_ALLOC_SEMAPHORE_POOL_PARAMS_V550 struct { 260 Base uint64 261 Length uint64 262 PerGPUAttributes [UVM_MAX_GPUS_V2]UvmGpuMappingAttributes 263 GPUAttributesCount uint64 264 RMStatus uint32 265 Pad0 [4]byte 266 } 267 268 // +marshal 269 type UVM_VALIDATE_VA_RANGE_PARAMS struct { 270 Base uint64 271 Length uint64 272 RMStatus uint32 273 Pad0 [4]byte 274 } 275 276 // +marshal 277 type UVM_CREATE_EXTERNAL_RANGE_PARAMS struct { 278 Base uint64 279 Length uint64 280 RMStatus uint32 281 Pad0 [4]byte 282 } 283 284 // +marshal 285 type UVM_MM_INITIALIZE_PARAMS struct { 286 UvmFD int32 287 Status uint32 288 } 289 290 // From kernel-open/nvidia-uvm/uvm_types.h: 291 292 const ( 293 UVM_MAX_GPUS = NV_MAX_DEVICES 294 UVM_MAX_GPUS_V2 = NV_MAX_DEVICES * NV_MAX_SUBDEVICES 295 ) 296 297 // +marshal 298 type UvmGpuMappingAttributes struct { 299 GPUUUID NvUUID 300 GPUMappingType uint32 301 GPUCachingType uint32 302 GPUFormatType uint32 303 GPUElementBits uint32 304 GPUCompressionType uint32 305 }