github.com/sanprasirt/go@v0.0.0-20170607001320-a027466e4b6d/src/cmd/internal/obj/s390x/asmz.go (about) 1 // Based on cmd/internal/obj/ppc64/asm9.go. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package s390x 31 32 import ( 33 "cmd/internal/obj" 34 "cmd/internal/objabi" 35 "log" 36 "math" 37 "sort" 38 ) 39 40 // ctxtz holds state while assembling a single function. 41 // Each function gets a fresh ctxtz. 42 // This allows for multiple functions to be safely concurrently assembled. 43 type ctxtz struct { 44 ctxt *obj.Link 45 newprog obj.ProgAlloc 46 cursym *obj.LSym 47 autosize int32 48 instoffset int64 49 pc int64 50 } 51 52 // instruction layout. 53 const ( 54 funcAlign = 16 55 ) 56 57 type Optab struct { 58 as obj.As // opcode 59 a1 uint8 // From 60 a2 uint8 // Reg 61 a3 uint8 // From3 62 a4 uint8 // To 63 type_ int8 64 param int16 // REGSP for auto variables 65 } 66 67 var optab = []Optab{ 68 // instruction, From, Reg, From3, To, type, param 69 Optab{obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0}, 70 Optab{obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0}, 71 72 // move register 73 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 74 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 75 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 76 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 77 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 78 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 1, 0}, 79 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 80 81 // load constant 82 Optab{AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 83 Optab{AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 84 Optab{AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 85 Optab{AMOVD, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 86 Optab{AMOVW, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 87 Optab{AMOVWZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 88 Optab{AMOVB, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 89 Optab{AMOVBZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 90 91 // store constant 92 Optab{AMOVD, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 93 Optab{AMOVD, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 94 Optab{AMOVW, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 95 Optab{AMOVW, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 96 Optab{AMOVWZ, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 97 Optab{AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 98 Optab{AMOVB, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 99 Optab{AMOVB, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 100 Optab{AMOVBZ, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 101 Optab{AMOVBZ, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 102 Optab{AMOVD, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 103 Optab{AMOVD, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 104 Optab{AMOVW, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 105 Optab{AMOVW, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 106 Optab{AMOVWZ, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 107 Optab{AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 108 Optab{AMOVB, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 109 Optab{AMOVB, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 110 Optab{AMOVBZ, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 111 Optab{AMOVBZ, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 112 113 // store 114 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 115 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 116 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 117 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 118 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 119 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 120 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 121 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 122 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 123 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 124 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 125 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 126 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 127 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 128 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 129 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 130 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 131 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 132 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 133 134 // load 135 Optab{AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 136 Optab{AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 137 Optab{AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 138 Optab{AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 139 Optab{AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 140 Optab{AMOVDBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 141 Optab{AMOVHBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 142 Optab{AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 143 Optab{AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 144 Optab{AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 145 Optab{AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 146 Optab{AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 147 Optab{AMOVDBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 148 Optab{AMOVHBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 149 Optab{AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 150 Optab{AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 151 Optab{AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 152 Optab{AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 153 Optab{AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 154 155 // interlocked load and op 156 Optab{ALAAG, C_REG, C_REG, C_NONE, C_LOREG, 99, 0}, 157 158 // integer arithmetic 159 Optab{AADD, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 160 Optab{AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 161 Optab{AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 0}, 162 Optab{AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 0}, 163 Optab{AADD, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 164 Optab{AADD, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 165 Optab{ASUB, C_LCON, C_REG, C_NONE, C_REG, 21, 0}, 166 Optab{ASUB, C_LCON, C_NONE, C_NONE, C_REG, 21, 0}, 167 Optab{ASUB, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 168 Optab{ASUB, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 169 Optab{AMULHD, C_REG, C_NONE, C_NONE, C_REG, 4, 0}, 170 Optab{AMULHD, C_REG, C_REG, C_NONE, C_REG, 4, 0}, 171 Optab{ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 172 Optab{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 173 Optab{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 0}, 174 Optab{ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 0}, 175 Optab{ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 0}, 176 Optab{ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 0}, 177 178 // integer logical 179 Optab{AAND, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 180 Optab{AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 181 Optab{AAND, C_LCON, C_NONE, C_NONE, C_REG, 23, 0}, 182 Optab{AAND, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 183 Optab{AAND, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 184 Optab{AANDW, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 185 Optab{AANDW, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 186 Optab{AANDW, C_LCON, C_NONE, C_NONE, C_REG, 24, 0}, 187 Optab{AANDW, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 188 Optab{AANDW, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 189 Optab{ASLD, C_REG, C_NONE, C_NONE, C_REG, 7, 0}, 190 Optab{ASLD, C_REG, C_REG, C_NONE, C_REG, 7, 0}, 191 Optab{ASLD, C_SCON, C_REG, C_NONE, C_REG, 7, 0}, 192 Optab{ASLD, C_SCON, C_NONE, C_NONE, C_REG, 7, 0}, 193 194 // compare and swap 195 Optab{ACSG, C_REG, C_REG, C_NONE, C_SOREG, 79, 0}, 196 197 // floating point 198 Optab{AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 199 Optab{AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 0}, 200 Optab{AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 0}, 201 Optab{AFMADD, C_FREG, C_FREG, C_NONE, C_FREG, 34, 0}, 202 Optab{AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 203 Optab{AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, REGSP}, 204 Optab{AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 0}, 205 Optab{AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 0}, 206 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 207 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 0}, 208 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 0}, 209 Optab{AFMOVD, C_ZCON, C_NONE, C_NONE, C_FREG, 67, 0}, 210 Optab{ALDGR, C_REG, C_NONE, C_NONE, C_FREG, 81, 0}, 211 Optab{ALGDR, C_FREG, C_NONE, C_NONE, C_REG, 81, 0}, 212 Optab{ACEFBRA, C_REG, C_NONE, C_NONE, C_FREG, 82, 0}, 213 Optab{ACFEBRA, C_FREG, C_NONE, C_NONE, C_REG, 83, 0}, 214 Optab{AFIEBR, C_SCON, C_FREG, C_NONE, C_FREG, 48, 0}, 215 216 // load symbol address (plus offset) 217 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_REG, 19, 0}, 218 Optab{AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 93, 0}, 219 Optab{AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 94, 0}, 220 Optab{AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 95, 0}, 221 222 // system call 223 Optab{ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 0}, 224 Optab{ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 0}, 225 226 // branch 227 Optab{ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 0}, 228 Optab{ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 0}, 229 Optab{ABC, C_SCON, C_REG, C_NONE, C_LBRA, 16, 0}, 230 Optab{ABR, C_NONE, C_NONE, C_NONE, C_REG, 18, 0}, 231 Optab{ABR, C_REG, C_NONE, C_NONE, C_REG, 18, 0}, 232 Optab{ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 233 Optab{ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 234 Optab{ACMPBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 235 Optab{ACMPBEQ, C_REG, C_NONE, C_ADDCON, C_SBRA, 90, 0}, 236 Optab{ACMPBEQ, C_REG, C_NONE, C_SCON, C_SBRA, 90, 0}, 237 Optab{ACMPUBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 238 Optab{ACMPUBEQ, C_REG, C_NONE, C_ANDCON, C_SBRA, 90, 0}, 239 240 // move on condition 241 Optab{AMOVDEQ, C_REG, C_NONE, C_NONE, C_REG, 17, 0}, 242 243 // find leftmost one 244 Optab{AFLOGR, C_REG, C_NONE, C_NONE, C_REG, 8, 0}, 245 246 // compare 247 Optab{ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 248 Optab{ACMP, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 249 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 250 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 251 Optab{AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 0}, 252 Optab{AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 0}, 253 254 // 32-bit access registers 255 Optab{AMOVW, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 256 Optab{AMOVWZ, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 257 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 258 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 259 260 // macros 261 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LOREG, 96, 0}, 262 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LAUTO, 96, REGSP}, 263 264 // load/store multiple 265 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LOREG, 97, 0}, 266 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LAUTO, 97, REGSP}, 267 Optab{ALMG, C_LOREG, C_REG, C_NONE, C_REG, 98, 0}, 268 Optab{ALMG, C_LAUTO, C_REG, C_NONE, C_REG, 98, REGSP}, 269 270 // bytes 271 Optab{ABYTE, C_SCON, C_NONE, C_NONE, C_NONE, 40, 0}, 272 Optab{AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 0}, 273 Optab{ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 0}, 274 Optab{ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 0}, 275 276 // fast synchronization 277 Optab{ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 80, 0}, 278 279 // store clock 280 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SAUTO, 88, REGSP}, 281 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SOREG, 88, 0}, 282 283 // storage and storage 284 Optab{AMVC, C_SCON, C_NONE, C_LOREG, C_LOREG, 84, 0}, 285 Optab{AMVC, C_SCON, C_NONE, C_LOREG, C_LAUTO, 84, REGSP}, 286 Optab{AMVC, C_SCON, C_NONE, C_LAUTO, C_LAUTO, 84, REGSP}, 287 288 // address 289 Optab{ALARL, C_LCON, C_NONE, C_NONE, C_REG, 85, 0}, 290 Optab{ALARL, C_SYMADDR, C_NONE, C_NONE, C_REG, 85, 0}, 291 Optab{ALA, C_SOREG, C_NONE, C_NONE, C_REG, 86, 0}, 292 Optab{ALA, C_SAUTO, C_NONE, C_NONE, C_REG, 86, REGSP}, 293 Optab{AEXRL, C_SYMADDR, C_NONE, C_NONE, C_REG, 87, 0}, 294 295 // misc 296 Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 0}, 297 Optab{obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0}, 298 Optab{obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0}, 299 Optab{obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0}, 300 Optab{obj.ANOP, C_SAUTO, C_NONE, C_NONE, C_NONE, 0, 0}, 301 302 // vector instructions 303 304 // VRX store 305 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SOREG, 100, 0}, 306 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SAUTO, 100, REGSP}, 307 Optab{AVSTEG, C_SCON, C_VREG, C_NONE, C_SOREG, 100, 0}, 308 Optab{AVSTEG, C_SCON, C_VREG, C_NONE, C_SAUTO, 100, REGSP}, 309 310 // VRX load 311 Optab{AVL, C_SOREG, C_NONE, C_NONE, C_VREG, 101, 0}, 312 Optab{AVL, C_SAUTO, C_NONE, C_NONE, C_VREG, 101, REGSP}, 313 Optab{AVLEG, C_SCON, C_NONE, C_SOREG, C_VREG, 101, 0}, 314 Optab{AVLEG, C_SCON, C_NONE, C_SAUTO, C_VREG, 101, REGSP}, 315 316 // VRV scatter 317 Optab{AVSCEG, C_SCON, C_VREG, C_NONE, C_SOREG, 102, 0}, 318 Optab{AVSCEG, C_SCON, C_VREG, C_NONE, C_SAUTO, 102, REGSP}, 319 320 // VRV gather 321 Optab{AVGEG, C_SCON, C_NONE, C_SOREG, C_VREG, 103, 0}, 322 Optab{AVGEG, C_SCON, C_NONE, C_SAUTO, C_VREG, 103, REGSP}, 323 324 // VRS element shift/rotate and load gr to/from vr element 325 Optab{AVESLG, C_SCON, C_VREG, C_NONE, C_VREG, 104, 0}, 326 Optab{AVESLG, C_REG, C_VREG, C_NONE, C_VREG, 104, 0}, 327 Optab{AVESLG, C_SCON, C_NONE, C_NONE, C_VREG, 104, 0}, 328 Optab{AVESLG, C_REG, C_NONE, C_NONE, C_VREG, 104, 0}, 329 Optab{AVLGVG, C_SCON, C_VREG, C_NONE, C_REG, 104, 0}, 330 Optab{AVLGVG, C_REG, C_VREG, C_NONE, C_REG, 104, 0}, 331 Optab{AVLVGG, C_SCON, C_REG, C_NONE, C_VREG, 104, 0}, 332 Optab{AVLVGG, C_REG, C_REG, C_NONE, C_VREG, 104, 0}, 333 334 // VRS store multiple 335 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SOREG, 105, 0}, 336 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SAUTO, 105, REGSP}, 337 338 // VRS load multiple 339 Optab{AVLM, C_SOREG, C_VREG, C_NONE, C_VREG, 106, 0}, 340 Optab{AVLM, C_SAUTO, C_VREG, C_NONE, C_VREG, 106, REGSP}, 341 342 // VRS store with length 343 Optab{AVSTL, C_REG, C_VREG, C_NONE, C_SOREG, 107, 0}, 344 Optab{AVSTL, C_REG, C_VREG, C_NONE, C_SAUTO, 107, REGSP}, 345 346 // VRS load with length 347 Optab{AVLL, C_REG, C_NONE, C_SOREG, C_VREG, 108, 0}, 348 Optab{AVLL, C_REG, C_NONE, C_SAUTO, C_VREG, 108, REGSP}, 349 350 // VRI-a 351 Optab{AVGBM, C_ANDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 352 Optab{AVZERO, C_NONE, C_NONE, C_NONE, C_VREG, 109, 0}, 353 Optab{AVREPIG, C_ADDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 354 Optab{AVREPIG, C_SCON, C_NONE, C_NONE, C_VREG, 109, 0}, 355 Optab{AVLEIG, C_SCON, C_NONE, C_ADDCON, C_VREG, 109, 0}, 356 Optab{AVLEIG, C_SCON, C_NONE, C_SCON, C_VREG, 109, 0}, 357 358 // VRI-b generate mask 359 Optab{AVGMG, C_SCON, C_NONE, C_SCON, C_VREG, 110, 0}, 360 361 // VRI-c replicate 362 Optab{AVREPG, C_UCON, C_VREG, C_NONE, C_VREG, 111, 0}, 363 364 // VRI-d element rotate and insert under mask and 365 // shift left double by byte 366 Optab{AVERIMG, C_SCON, C_VREG, C_VREG, C_VREG, 112, 0}, 367 Optab{AVSLDB, C_SCON, C_VREG, C_VREG, C_VREG, 112, 0}, 368 369 // VRI-d fp test data class immediate 370 Optab{AVFTCIDB, C_SCON, C_VREG, C_NONE, C_VREG, 113, 0}, 371 372 // VRR-a load reg 373 Optab{AVLR, C_VREG, C_NONE, C_NONE, C_VREG, 114, 0}, 374 375 // VRR-a compare 376 Optab{AVECG, C_VREG, C_NONE, C_NONE, C_VREG, 115, 0}, 377 378 // VRR-b 379 Optab{AVCEQG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 380 Optab{AVFAEF, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 381 Optab{AVPKSG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 382 383 // VRR-c 384 Optab{AVAQ, C_VREG, C_VREG, C_NONE, C_VREG, 118, 0}, 385 Optab{AVAQ, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 386 Optab{AVNOT, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 387 Optab{AVPDI, C_SCON, C_VREG, C_VREG, C_VREG, 123, 0}, 388 389 // VRR-c shifts 390 Optab{AVERLLVG, C_VREG, C_VREG, C_NONE, C_VREG, 119, 0}, 391 Optab{AVERLLVG, C_VREG, C_NONE, C_NONE, C_VREG, 119, 0}, 392 393 // VRR-d 394 // 2 3 1 4 395 Optab{AVACQ, C_VREG, C_VREG, C_VREG, C_VREG, 120, 0}, 396 397 // VRR-e 398 Optab{AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 121, 0}, 399 400 // VRR-f 401 Optab{AVLVGP, C_REG, C_REG, C_NONE, C_VREG, 122, 0}, 402 } 403 404 var oprange [ALAST & obj.AMask][]Optab 405 406 var xcmp [C_NCLASS][C_NCLASS]bool 407 408 func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 409 p := cursym.Func.Text 410 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 411 return 412 } 413 414 if oprange[AORW&obj.AMask] == nil { 415 ctxt.Diag("s390x ops not initialized, call s390x.buildop first") 416 } 417 418 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 419 420 buffer := make([]byte, 0) 421 changed := true 422 loop := 0 423 for changed { 424 if loop > 10 { 425 c.ctxt.Diag("stuck in spanz loop") 426 break 427 } 428 changed = false 429 buffer = buffer[:0] 430 c.cursym.R = make([]obj.Reloc, 0) 431 for p := c.cursym.Func.Text; p != nil; p = p.Link { 432 pc := int64(len(buffer)) 433 if pc != p.Pc { 434 changed = true 435 } 436 p.Pc = pc 437 c.pc = p.Pc 438 c.asmout(p, &buffer) 439 if pc == int64(len(buffer)) { 440 switch p.As { 441 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT: 442 // ok 443 default: 444 c.ctxt.Diag("zero-width instruction\n%v", p) 445 } 446 } 447 } 448 loop++ 449 } 450 451 c.cursym.Size = int64(len(buffer)) 452 if c.cursym.Size%funcAlign != 0 { 453 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign) 454 } 455 c.cursym.Grow(c.cursym.Size) 456 copy(c.cursym.P, buffer) 457 } 458 459 func isint32(v int64) bool { 460 return int64(int32(v)) == v 461 } 462 463 func isuint32(v uint64) bool { 464 return uint64(uint32(v)) == v 465 } 466 467 func (c *ctxtz) aclass(a *obj.Addr) int { 468 switch a.Type { 469 case obj.TYPE_NONE: 470 return C_NONE 471 472 case obj.TYPE_REG: 473 if REG_R0 <= a.Reg && a.Reg <= REG_R15 { 474 return C_REG 475 } 476 if REG_F0 <= a.Reg && a.Reg <= REG_F15 { 477 return C_FREG 478 } 479 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 { 480 return C_AREG 481 } 482 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 483 return C_VREG 484 } 485 return C_GOK 486 487 case obj.TYPE_MEM: 488 switch a.Name { 489 case obj.NAME_EXTERN, 490 obj.NAME_STATIC: 491 if a.Sym == nil { 492 // must have a symbol 493 break 494 } 495 c.instoffset = a.Offset 496 if a.Sym.Type == objabi.STLSBSS { 497 if c.ctxt.Flag_shared { 498 return C_TLS_IE // initial exec model 499 } 500 return C_TLS_LE // local exec model 501 } 502 return C_ADDR 503 504 case obj.NAME_GOTREF: 505 return C_GOTADDR 506 507 case obj.NAME_AUTO: 508 c.instoffset = int64(c.autosize) + a.Offset 509 if c.instoffset >= -BIG && c.instoffset < BIG { 510 return C_SAUTO 511 } 512 return C_LAUTO 513 514 case obj.NAME_PARAM: 515 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 516 if c.instoffset >= -BIG && c.instoffset < BIG { 517 return C_SAUTO 518 } 519 return C_LAUTO 520 521 case obj.NAME_NONE: 522 c.instoffset = a.Offset 523 if c.instoffset == 0 { 524 return C_ZOREG 525 } 526 if c.instoffset >= -BIG && c.instoffset < BIG { 527 return C_SOREG 528 } 529 return C_LOREG 530 } 531 532 return C_GOK 533 534 case obj.TYPE_TEXTSIZE: 535 return C_TEXTSIZE 536 537 case obj.TYPE_FCONST: 538 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 { 539 return C_ZCON 540 } 541 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val) 542 543 case obj.TYPE_CONST, 544 obj.TYPE_ADDR: 545 switch a.Name { 546 case obj.NAME_NONE: 547 c.instoffset = a.Offset 548 if a.Reg != 0 { 549 if -BIG <= c.instoffset && c.instoffset <= BIG { 550 return C_SACON 551 } 552 if isint32(c.instoffset) { 553 return C_LACON 554 } 555 return C_DACON 556 } 557 goto consize 558 559 case obj.NAME_EXTERN, 560 obj.NAME_STATIC: 561 s := a.Sym 562 if s == nil { 563 break 564 } 565 c.instoffset = a.Offset 566 567 return C_SYMADDR 568 569 case obj.NAME_AUTO: 570 c.instoffset = int64(c.autosize) + a.Offset 571 if c.instoffset >= -BIG && c.instoffset < BIG { 572 return C_SACON 573 } 574 return C_LACON 575 576 case obj.NAME_PARAM: 577 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 578 if c.instoffset >= -BIG && c.instoffset < BIG { 579 return C_SACON 580 } 581 return C_LACON 582 } 583 584 return C_GOK 585 586 consize: 587 if c.instoffset == 0 { 588 return C_ZCON 589 } 590 if c.instoffset >= 0 { 591 if c.instoffset <= 0x7fff { 592 return C_SCON 593 } 594 if c.instoffset <= 0xffff { 595 return C_ANDCON 596 } 597 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 598 return C_UCON 599 } 600 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 601 return C_LCON 602 } 603 return C_DCON 604 } 605 606 if c.instoffset >= -0x8000 { 607 return C_ADDCON 608 } 609 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 610 return C_UCON 611 } 612 if isint32(c.instoffset) { 613 return C_LCON 614 } 615 return C_DCON 616 617 case obj.TYPE_BRANCH: 618 return C_SBRA 619 } 620 621 return C_GOK 622 } 623 624 func (c *ctxtz) oplook(p *obj.Prog) *Optab { 625 a1 := int(p.Optab) 626 if a1 != 0 { 627 return &optab[a1-1] 628 } 629 a1 = int(p.From.Class) 630 if a1 == 0 { 631 a1 = c.aclass(&p.From) + 1 632 p.From.Class = int8(a1) 633 } 634 635 a1-- 636 a3 := C_NONE + 1 637 if p.From3 != nil { 638 a3 = int(p.From3.Class) 639 if a3 == 0 { 640 a3 = c.aclass(p.From3) + 1 641 p.From3.Class = int8(a3) 642 } 643 } 644 645 a3-- 646 a4 := int(p.To.Class) 647 if a4 == 0 { 648 a4 = c.aclass(&p.To) + 1 649 p.To.Class = int8(a4) 650 } 651 652 a4-- 653 a2 := C_NONE 654 if p.Reg != 0 { 655 if REG_R0 <= p.Reg && p.Reg <= REG_R15 { 656 a2 = C_REG 657 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 658 a2 = C_VREG 659 } else if REG_F0 <= p.Reg && p.Reg <= REG_F15 { 660 a2 = C_FREG 661 } else if REG_AR0 <= p.Reg && p.Reg <= REG_AR15 { 662 a2 = C_AREG 663 } 664 } 665 666 ops := oprange[p.As&obj.AMask] 667 c1 := &xcmp[a1] 668 c2 := &xcmp[a2] 669 c3 := &xcmp[a3] 670 c4 := &xcmp[a4] 671 for i := range ops { 672 op := &ops[i] 673 if (int(op.a2) == a2 || c2[op.a2]) && c4[op.a4] && c1[op.a1] && c3[op.a3] { 674 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 675 return op 676 } 677 } 678 679 // cannot find a case; abort 680 c.ctxt.Diag("illegal combination %v %v %v %v %v\n", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 681 c.ctxt.Diag("prog: %v\n", p) 682 return nil 683 } 684 685 func cmp(a int, b int) bool { 686 if a == b { 687 return true 688 } 689 switch a { 690 case C_DCON: 691 if b == C_LCON { 692 return true 693 } 694 fallthrough 695 case C_LCON: 696 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 697 return true 698 } 699 700 case C_ADDCON: 701 if b == C_ZCON || b == C_SCON { 702 return true 703 } 704 705 case C_ANDCON: 706 if b == C_ZCON || b == C_SCON { 707 return true 708 } 709 710 case C_UCON: 711 if b == C_ZCON || b == C_SCON { 712 return true 713 } 714 715 case C_SCON: 716 if b == C_ZCON { 717 return true 718 } 719 720 case C_LACON: 721 if b == C_SACON { 722 return true 723 } 724 725 case C_LBRA: 726 if b == C_SBRA { 727 return true 728 } 729 730 case C_LAUTO: 731 if b == C_SAUTO { 732 return true 733 } 734 735 case C_LOREG: 736 if b == C_ZOREG || b == C_SOREG { 737 return true 738 } 739 740 case C_SOREG: 741 if b == C_ZOREG { 742 return true 743 } 744 745 case C_ANY: 746 return true 747 } 748 749 return false 750 } 751 752 type ocmp []Optab 753 754 func (x ocmp) Len() int { 755 return len(x) 756 } 757 758 func (x ocmp) Swap(i, j int) { 759 x[i], x[j] = x[j], x[i] 760 } 761 762 func (x ocmp) Less(i, j int) bool { 763 p1 := &x[i] 764 p2 := &x[j] 765 n := int(p1.as) - int(p2.as) 766 if n != 0 { 767 return n < 0 768 } 769 n = int(p1.a1) - int(p2.a1) 770 if n != 0 { 771 return n < 0 772 } 773 n = int(p1.a2) - int(p2.a2) 774 if n != 0 { 775 return n < 0 776 } 777 n = int(p1.a3) - int(p2.a3) 778 if n != 0 { 779 return n < 0 780 } 781 n = int(p1.a4) - int(p2.a4) 782 if n != 0 { 783 return n < 0 784 } 785 return false 786 } 787 func opset(a, b obj.As) { 788 oprange[a&obj.AMask] = oprange[b&obj.AMask] 789 } 790 791 func buildop(ctxt *obj.Link) { 792 if oprange[AORW&obj.AMask] != nil { 793 // Already initialized; stop now. 794 // This happens in the cmd/asm tests, 795 // each of which re-initializes the arch. 796 return 797 } 798 799 for i := 0; i < C_NCLASS; i++ { 800 for n := 0; n < C_NCLASS; n++ { 801 if cmp(n, i) { 802 xcmp[i][n] = true 803 } 804 } 805 } 806 sort.Sort(ocmp(optab)) 807 for i := 0; i < len(optab); i++ { 808 r := optab[i].as 809 start := i 810 for ; i+1 < len(optab); i++ { 811 if optab[i+1].as != r { 812 break 813 } 814 } 815 oprange[r&obj.AMask] = optab[start : i+1] 816 817 // opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array. 818 // oprange[] is used by oplook() to find the Optab entry that applies to a given Prog. 819 switch r { 820 case AADD: 821 opset(AADDC, r) 822 opset(AADDW, r) 823 opset(AMULLD, r) 824 opset(AMULLW, r) 825 case ADIVW: 826 opset(AADDE, r) 827 opset(ADIVD, r) 828 opset(ADIVDU, r) 829 opset(ADIVWU, r) 830 opset(AMODD, r) 831 opset(AMODDU, r) 832 opset(AMODW, r) 833 opset(AMODWU, r) 834 case AMULHD: 835 opset(AMULHDU, r) 836 case AMOVBZ: 837 opset(AMOVH, r) 838 opset(AMOVHZ, r) 839 case ALA: 840 opset(ALAY, r) 841 case AMVC: 842 opset(ACLC, r) 843 opset(AXC, r) 844 opset(AOC, r) 845 opset(ANC, r) 846 case ASTCK: 847 opset(ASTCKC, r) 848 opset(ASTCKE, r) 849 opset(ASTCKF, r) 850 case ALAAG: 851 opset(ALAA, r) 852 opset(ALAAL, r) 853 opset(ALAALG, r) 854 opset(ALAN, r) 855 opset(ALANG, r) 856 opset(ALAX, r) 857 opset(ALAXG, r) 858 opset(ALAO, r) 859 opset(ALAOG, r) 860 case ASTMG: 861 opset(ASTMY, r) 862 case ALMG: 863 opset(ALMY, r) 864 case ABEQ: 865 opset(ABGE, r) 866 opset(ABGT, r) 867 opset(ABLE, r) 868 opset(ABLT, r) 869 opset(ABNE, r) 870 opset(ABVC, r) 871 opset(ABVS, r) 872 opset(ABLEU, r) 873 opset(ABLTU, r) 874 case ABR: 875 opset(ABL, r) 876 case ABC: 877 opset(ABCL, r) 878 case AFABS: 879 opset(AFNABS, r) 880 opset(AFNEG, r) 881 opset(AFNEGS, r) 882 opset(ALEDBR, r) 883 opset(ALDEBR, r) 884 opset(AFSQRT, r) 885 opset(AFSQRTS, r) 886 case AFADD: 887 opset(AFADDS, r) 888 opset(AFDIV, r) 889 opset(AFDIVS, r) 890 opset(AFSUB, r) 891 opset(AFSUBS, r) 892 case AFMADD: 893 opset(AFMADDS, r) 894 opset(AFMSUB, r) 895 opset(AFMSUBS, r) 896 case AFMUL: 897 opset(AFMULS, r) 898 case AFCMPO: 899 opset(AFCMPU, r) 900 opset(ACEBR, r) 901 case AAND: 902 opset(AOR, r) 903 opset(AXOR, r) 904 case AANDW: 905 opset(AORW, r) 906 opset(AXORW, r) 907 case ASLD: 908 opset(ASRD, r) 909 opset(ASLW, r) 910 opset(ASRW, r) 911 opset(ASRAD, r) 912 opset(ASRAW, r) 913 opset(ARLL, r) 914 opset(ARLLG, r) 915 case ACSG: 916 opset(ACS, r) 917 case ASUB: 918 opset(ASUBC, r) 919 opset(ASUBE, r) 920 opset(ASUBW, r) 921 case ANEG: 922 opset(ANEGW, r) 923 case AFMOVD: 924 opset(AFMOVS, r) 925 case AMOVDBR: 926 opset(AMOVWBR, r) 927 case ACMP: 928 opset(ACMPW, r) 929 case ACMPU: 930 opset(ACMPWU, r) 931 case ACEFBRA: 932 opset(ACDFBRA, r) 933 opset(ACEGBRA, r) 934 opset(ACDGBRA, r) 935 opset(ACELFBR, r) 936 opset(ACDLFBR, r) 937 opset(ACELGBR, r) 938 opset(ACDLGBR, r) 939 case ACFEBRA: 940 opset(ACFDBRA, r) 941 opset(ACGEBRA, r) 942 opset(ACGDBRA, r) 943 opset(ACLFEBR, r) 944 opset(ACLFDBR, r) 945 opset(ACLGEBR, r) 946 opset(ACLGDBR, r) 947 case AFIEBR: 948 opset(AFIDBR, r) 949 case ACMPBEQ: 950 opset(ACMPBGE, r) 951 opset(ACMPBGT, r) 952 opset(ACMPBLE, r) 953 opset(ACMPBLT, r) 954 opset(ACMPBNE, r) 955 case ACMPUBEQ: 956 opset(ACMPUBGE, r) 957 opset(ACMPUBGT, r) 958 opset(ACMPUBLE, r) 959 opset(ACMPUBLT, r) 960 opset(ACMPUBNE, r) 961 case AMOVDEQ: 962 opset(AMOVDGE, r) 963 opset(AMOVDGT, r) 964 opset(AMOVDLE, r) 965 opset(AMOVDLT, r) 966 opset(AMOVDNE, r) 967 case AVL: 968 opset(AVLLEZB, r) 969 opset(AVLLEZH, r) 970 opset(AVLLEZF, r) 971 opset(AVLLEZG, r) 972 opset(AVLREPB, r) 973 opset(AVLREPH, r) 974 opset(AVLREPF, r) 975 opset(AVLREPG, r) 976 case AVLEG: 977 opset(AVLBB, r) 978 opset(AVLEB, r) 979 opset(AVLEH, r) 980 opset(AVLEF, r) 981 opset(AVLEG, r) 982 opset(AVLREP, r) 983 case AVSTEG: 984 opset(AVSTEB, r) 985 opset(AVSTEH, r) 986 opset(AVSTEF, r) 987 case AVSCEG: 988 opset(AVSCEF, r) 989 case AVGEG: 990 opset(AVGEF, r) 991 case AVESLG: 992 opset(AVESLB, r) 993 opset(AVESLH, r) 994 opset(AVESLF, r) 995 opset(AVERLLB, r) 996 opset(AVERLLH, r) 997 opset(AVERLLF, r) 998 opset(AVERLLG, r) 999 opset(AVESRAB, r) 1000 opset(AVESRAH, r) 1001 opset(AVESRAF, r) 1002 opset(AVESRAG, r) 1003 opset(AVESRLB, r) 1004 opset(AVESRLH, r) 1005 opset(AVESRLF, r) 1006 opset(AVESRLG, r) 1007 case AVLGVG: 1008 opset(AVLGVB, r) 1009 opset(AVLGVH, r) 1010 opset(AVLGVF, r) 1011 case AVLVGG: 1012 opset(AVLVGB, r) 1013 opset(AVLVGH, r) 1014 opset(AVLVGF, r) 1015 case AVZERO: 1016 opset(AVONE, r) 1017 case AVREPIG: 1018 opset(AVREPIB, r) 1019 opset(AVREPIH, r) 1020 opset(AVREPIF, r) 1021 case AVLEIG: 1022 opset(AVLEIB, r) 1023 opset(AVLEIH, r) 1024 opset(AVLEIF, r) 1025 case AVGMG: 1026 opset(AVGMB, r) 1027 opset(AVGMH, r) 1028 opset(AVGMF, r) 1029 case AVREPG: 1030 opset(AVREPB, r) 1031 opset(AVREPH, r) 1032 opset(AVREPF, r) 1033 case AVERIMG: 1034 opset(AVERIMB, r) 1035 opset(AVERIMH, r) 1036 opset(AVERIMF, r) 1037 case AVFTCIDB: 1038 opset(AWFTCIDB, r) 1039 case AVLR: 1040 opset(AVUPHB, r) 1041 opset(AVUPHH, r) 1042 opset(AVUPHF, r) 1043 opset(AVUPLHB, r) 1044 opset(AVUPLHH, r) 1045 opset(AVUPLHF, r) 1046 opset(AVUPLB, r) 1047 opset(AVUPLHW, r) 1048 opset(AVUPLF, r) 1049 opset(AVUPLLB, r) 1050 opset(AVUPLLH, r) 1051 opset(AVUPLLF, r) 1052 opset(AVCLZB, r) 1053 opset(AVCLZH, r) 1054 opset(AVCLZF, r) 1055 opset(AVCLZG, r) 1056 opset(AVCTZB, r) 1057 opset(AVCTZH, r) 1058 opset(AVCTZF, r) 1059 opset(AVCTZG, r) 1060 opset(AVLDEB, r) 1061 opset(AWLDEB, r) 1062 opset(AVFLCDB, r) 1063 opset(AWFLCDB, r) 1064 opset(AVFLNDB, r) 1065 opset(AWFLNDB, r) 1066 opset(AVFLPDB, r) 1067 opset(AWFLPDB, r) 1068 opset(AVFSQDB, r) 1069 opset(AWFSQDB, r) 1070 opset(AVISTRB, r) 1071 opset(AVISTRH, r) 1072 opset(AVISTRF, r) 1073 opset(AVISTRBS, r) 1074 opset(AVISTRHS, r) 1075 opset(AVISTRFS, r) 1076 opset(AVLCB, r) 1077 opset(AVLCH, r) 1078 opset(AVLCF, r) 1079 opset(AVLCG, r) 1080 opset(AVLPB, r) 1081 opset(AVLPH, r) 1082 opset(AVLPF, r) 1083 opset(AVLPG, r) 1084 opset(AVPOPCT, r) 1085 opset(AVSEGB, r) 1086 opset(AVSEGH, r) 1087 opset(AVSEGF, r) 1088 case AVECG: 1089 opset(AVECB, r) 1090 opset(AVECH, r) 1091 opset(AVECF, r) 1092 opset(AVECLB, r) 1093 opset(AVECLH, r) 1094 opset(AVECLF, r) 1095 opset(AVECLG, r) 1096 opset(AWFCDB, r) 1097 opset(AWFKDB, r) 1098 case AVCEQG: 1099 opset(AVCEQB, r) 1100 opset(AVCEQH, r) 1101 opset(AVCEQF, r) 1102 opset(AVCEQBS, r) 1103 opset(AVCEQHS, r) 1104 opset(AVCEQFS, r) 1105 opset(AVCEQGS, r) 1106 opset(AVCHB, r) 1107 opset(AVCHH, r) 1108 opset(AVCHF, r) 1109 opset(AVCHG, r) 1110 opset(AVCHBS, r) 1111 opset(AVCHHS, r) 1112 opset(AVCHFS, r) 1113 opset(AVCHGS, r) 1114 opset(AVCHLB, r) 1115 opset(AVCHLH, r) 1116 opset(AVCHLF, r) 1117 opset(AVCHLG, r) 1118 opset(AVCHLBS, r) 1119 opset(AVCHLHS, r) 1120 opset(AVCHLFS, r) 1121 opset(AVCHLGS, r) 1122 case AVFAEF: 1123 opset(AVFAEB, r) 1124 opset(AVFAEH, r) 1125 opset(AVFAEBS, r) 1126 opset(AVFAEHS, r) 1127 opset(AVFAEFS, r) 1128 opset(AVFAEZB, r) 1129 opset(AVFAEZH, r) 1130 opset(AVFAEZF, r) 1131 opset(AVFAEZBS, r) 1132 opset(AVFAEZHS, r) 1133 opset(AVFAEZFS, r) 1134 opset(AVFEEB, r) 1135 opset(AVFEEH, r) 1136 opset(AVFEEF, r) 1137 opset(AVFEEBS, r) 1138 opset(AVFEEHS, r) 1139 opset(AVFEEFS, r) 1140 opset(AVFEEZB, r) 1141 opset(AVFEEZH, r) 1142 opset(AVFEEZF, r) 1143 opset(AVFEEZBS, r) 1144 opset(AVFEEZHS, r) 1145 opset(AVFEEZFS, r) 1146 opset(AVFENEB, r) 1147 opset(AVFENEH, r) 1148 opset(AVFENEF, r) 1149 opset(AVFENEBS, r) 1150 opset(AVFENEHS, r) 1151 opset(AVFENEFS, r) 1152 opset(AVFENEZB, r) 1153 opset(AVFENEZH, r) 1154 opset(AVFENEZF, r) 1155 opset(AVFENEZBS, r) 1156 opset(AVFENEZHS, r) 1157 opset(AVFENEZFS, r) 1158 case AVPKSG: 1159 opset(AVPKSH, r) 1160 opset(AVPKSF, r) 1161 opset(AVPKSHS, r) 1162 opset(AVPKSFS, r) 1163 opset(AVPKSGS, r) 1164 opset(AVPKLSH, r) 1165 opset(AVPKLSF, r) 1166 opset(AVPKLSG, r) 1167 opset(AVPKLSHS, r) 1168 opset(AVPKLSFS, r) 1169 opset(AVPKLSGS, r) 1170 case AVAQ: 1171 opset(AVAB, r) 1172 opset(AVAH, r) 1173 opset(AVAF, r) 1174 opset(AVAG, r) 1175 opset(AVACCB, r) 1176 opset(AVACCH, r) 1177 opset(AVACCF, r) 1178 opset(AVACCG, r) 1179 opset(AVACCQ, r) 1180 opset(AVN, r) 1181 opset(AVNC, r) 1182 opset(AVAVGB, r) 1183 opset(AVAVGH, r) 1184 opset(AVAVGF, r) 1185 opset(AVAVGG, r) 1186 opset(AVAVGLB, r) 1187 opset(AVAVGLH, r) 1188 opset(AVAVGLF, r) 1189 opset(AVAVGLG, r) 1190 opset(AVCKSM, r) 1191 opset(AVX, r) 1192 opset(AVFADB, r) 1193 opset(AWFADB, r) 1194 opset(AVFCEDB, r) 1195 opset(AVFCEDBS, r) 1196 opset(AWFCEDB, r) 1197 opset(AWFCEDBS, r) 1198 opset(AVFCHDB, r) 1199 opset(AVFCHDBS, r) 1200 opset(AWFCHDB, r) 1201 opset(AWFCHDBS, r) 1202 opset(AVFCHEDB, r) 1203 opset(AVFCHEDBS, r) 1204 opset(AWFCHEDB, r) 1205 opset(AWFCHEDBS, r) 1206 opset(AVFMDB, r) 1207 opset(AWFMDB, r) 1208 opset(AVGFMB, r) 1209 opset(AVGFMH, r) 1210 opset(AVGFMF, r) 1211 opset(AVGFMG, r) 1212 opset(AVMXB, r) 1213 opset(AVMXH, r) 1214 opset(AVMXF, r) 1215 opset(AVMXG, r) 1216 opset(AVMXLB, r) 1217 opset(AVMXLH, r) 1218 opset(AVMXLF, r) 1219 opset(AVMXLG, r) 1220 opset(AVMNB, r) 1221 opset(AVMNH, r) 1222 opset(AVMNF, r) 1223 opset(AVMNG, r) 1224 opset(AVMNLB, r) 1225 opset(AVMNLH, r) 1226 opset(AVMNLF, r) 1227 opset(AVMNLG, r) 1228 opset(AVMRHB, r) 1229 opset(AVMRHH, r) 1230 opset(AVMRHF, r) 1231 opset(AVMRHG, r) 1232 opset(AVMRLB, r) 1233 opset(AVMRLH, r) 1234 opset(AVMRLF, r) 1235 opset(AVMRLG, r) 1236 opset(AVMEB, r) 1237 opset(AVMEH, r) 1238 opset(AVMEF, r) 1239 opset(AVMLEB, r) 1240 opset(AVMLEH, r) 1241 opset(AVMLEF, r) 1242 opset(AVMOB, r) 1243 opset(AVMOH, r) 1244 opset(AVMOF, r) 1245 opset(AVMLOB, r) 1246 opset(AVMLOH, r) 1247 opset(AVMLOF, r) 1248 opset(AVMHB, r) 1249 opset(AVMHH, r) 1250 opset(AVMHF, r) 1251 opset(AVMLHB, r) 1252 opset(AVMLHH, r) 1253 opset(AVMLHF, r) 1254 opset(AVMLH, r) 1255 opset(AVMLHW, r) 1256 opset(AVMLF, r) 1257 opset(AVNO, r) 1258 opset(AVO, r) 1259 opset(AVPKH, r) 1260 opset(AVPKF, r) 1261 opset(AVPKG, r) 1262 opset(AVSUMGH, r) 1263 opset(AVSUMGF, r) 1264 opset(AVSUMQF, r) 1265 opset(AVSUMQG, r) 1266 opset(AVSUMB, r) 1267 opset(AVSUMH, r) 1268 case AVERLLVG: 1269 opset(AVERLLVB, r) 1270 opset(AVERLLVH, r) 1271 opset(AVERLLVF, r) 1272 opset(AVESLVB, r) 1273 opset(AVESLVH, r) 1274 opset(AVESLVF, r) 1275 opset(AVESLVG, r) 1276 opset(AVESRAVB, r) 1277 opset(AVESRAVH, r) 1278 opset(AVESRAVF, r) 1279 opset(AVESRAVG, r) 1280 opset(AVESRLVB, r) 1281 opset(AVESRLVH, r) 1282 opset(AVESRLVF, r) 1283 opset(AVESRLVG, r) 1284 opset(AVFDDB, r) 1285 opset(AWFDDB, r) 1286 opset(AVFSDB, r) 1287 opset(AWFSDB, r) 1288 opset(AVSL, r) 1289 opset(AVSLB, r) 1290 opset(AVSRA, r) 1291 opset(AVSRAB, r) 1292 opset(AVSRL, r) 1293 opset(AVSRLB, r) 1294 opset(AVSF, r) 1295 opset(AVSG, r) 1296 opset(AVSQ, r) 1297 opset(AVSCBIB, r) 1298 opset(AVSCBIH, r) 1299 opset(AVSCBIF, r) 1300 opset(AVSCBIG, r) 1301 opset(AVSCBIQ, r) 1302 case AVACQ: 1303 opset(AVACCCQ, r) 1304 opset(AVGFMAB, r) 1305 opset(AVGFMAH, r) 1306 opset(AVGFMAF, r) 1307 opset(AVGFMAG, r) 1308 opset(AVMALB, r) 1309 opset(AVMALHW, r) 1310 opset(AVMALF, r) 1311 opset(AVMAHB, r) 1312 opset(AVMAHH, r) 1313 opset(AVMAHF, r) 1314 opset(AVMALHB, r) 1315 opset(AVMALHH, r) 1316 opset(AVMALHF, r) 1317 opset(AVMAEB, r) 1318 opset(AVMAEH, r) 1319 opset(AVMAEF, r) 1320 opset(AVMALEB, r) 1321 opset(AVMALEH, r) 1322 opset(AVMALEF, r) 1323 opset(AVMAOB, r) 1324 opset(AVMAOH, r) 1325 opset(AVMAOF, r) 1326 opset(AVMALOB, r) 1327 opset(AVMALOH, r) 1328 opset(AVMALOF, r) 1329 opset(AVSTRCB, r) 1330 opset(AVSTRCH, r) 1331 opset(AVSTRCF, r) 1332 opset(AVSTRCBS, r) 1333 opset(AVSTRCHS, r) 1334 opset(AVSTRCFS, r) 1335 opset(AVSTRCZB, r) 1336 opset(AVSTRCZH, r) 1337 opset(AVSTRCZF, r) 1338 opset(AVSTRCZBS, r) 1339 opset(AVSTRCZHS, r) 1340 opset(AVSTRCZFS, r) 1341 opset(AVSBCBIQ, r) 1342 opset(AVSBIQ, r) 1343 case AVSEL: 1344 opset(AVFMADB, r) 1345 opset(AWFMADB, r) 1346 opset(AVFMSDB, r) 1347 opset(AWFMSDB, r) 1348 opset(AVPERM, r) 1349 } 1350 } 1351 } 1352 1353 const ( 1354 op_A uint32 = 0x5A00 // FORMAT_RX1 ADD (32) 1355 op_AD uint32 = 0x6A00 // FORMAT_RX1 ADD NORMALIZED (long HFP) 1356 op_ADB uint32 = 0xED1A // FORMAT_RXE ADD (long BFP) 1357 op_ADBR uint32 = 0xB31A // FORMAT_RRE ADD (long BFP) 1358 op_ADR uint32 = 0x2A00 // FORMAT_RR ADD NORMALIZED (long HFP) 1359 op_ADTR uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1360 op_ADTRA uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1361 op_AE uint32 = 0x7A00 // FORMAT_RX1 ADD NORMALIZED (short HFP) 1362 op_AEB uint32 = 0xED0A // FORMAT_RXE ADD (short BFP) 1363 op_AEBR uint32 = 0xB30A // FORMAT_RRE ADD (short BFP) 1364 op_AER uint32 = 0x3A00 // FORMAT_RR ADD NORMALIZED (short HFP) 1365 op_AFI uint32 = 0xC209 // FORMAT_RIL1 ADD IMMEDIATE (32) 1366 op_AG uint32 = 0xE308 // FORMAT_RXY1 ADD (64) 1367 op_AGF uint32 = 0xE318 // FORMAT_RXY1 ADD (64<-32) 1368 op_AGFI uint32 = 0xC208 // FORMAT_RIL1 ADD IMMEDIATE (64<-32) 1369 op_AGFR uint32 = 0xB918 // FORMAT_RRE ADD (64<-32) 1370 op_AGHI uint32 = 0xA70B // FORMAT_RI1 ADD HALFWORD IMMEDIATE (64) 1371 op_AGHIK uint32 = 0xECD9 // FORMAT_RIE4 ADD IMMEDIATE (64<-16) 1372 op_AGR uint32 = 0xB908 // FORMAT_RRE ADD (64) 1373 op_AGRK uint32 = 0xB9E8 // FORMAT_RRF1 ADD (64) 1374 op_AGSI uint32 = 0xEB7A // FORMAT_SIY ADD IMMEDIATE (64<-8) 1375 op_AH uint32 = 0x4A00 // FORMAT_RX1 ADD HALFWORD 1376 op_AHHHR uint32 = 0xB9C8 // FORMAT_RRF1 ADD HIGH (32) 1377 op_AHHLR uint32 = 0xB9D8 // FORMAT_RRF1 ADD HIGH (32) 1378 op_AHI uint32 = 0xA70A // FORMAT_RI1 ADD HALFWORD IMMEDIATE (32) 1379 op_AHIK uint32 = 0xECD8 // FORMAT_RIE4 ADD IMMEDIATE (32<-16) 1380 op_AHY uint32 = 0xE37A // FORMAT_RXY1 ADD HALFWORD 1381 op_AIH uint32 = 0xCC08 // FORMAT_RIL1 ADD IMMEDIATE HIGH (32) 1382 op_AL uint32 = 0x5E00 // FORMAT_RX1 ADD LOGICAL (32) 1383 op_ALC uint32 = 0xE398 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (32) 1384 op_ALCG uint32 = 0xE388 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (64) 1385 op_ALCGR uint32 = 0xB988 // FORMAT_RRE ADD LOGICAL WITH CARRY (64) 1386 op_ALCR uint32 = 0xB998 // FORMAT_RRE ADD LOGICAL WITH CARRY (32) 1387 op_ALFI uint32 = 0xC20B // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (32) 1388 op_ALG uint32 = 0xE30A // FORMAT_RXY1 ADD LOGICAL (64) 1389 op_ALGF uint32 = 0xE31A // FORMAT_RXY1 ADD LOGICAL (64<-32) 1390 op_ALGFI uint32 = 0xC20A // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (64<-32) 1391 op_ALGFR uint32 = 0xB91A // FORMAT_RRE ADD LOGICAL (64<-32) 1392 op_ALGHSIK uint32 = 0xECDB // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16) 1393 op_ALGR uint32 = 0xB90A // FORMAT_RRE ADD LOGICAL (64) 1394 op_ALGRK uint32 = 0xB9EA // FORMAT_RRF1 ADD LOGICAL (64) 1395 op_ALGSI uint32 = 0xEB7E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8) 1396 op_ALHHHR uint32 = 0xB9CA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1397 op_ALHHLR uint32 = 0xB9DA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1398 op_ALHSIK uint32 = 0xECDA // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16) 1399 op_ALR uint32 = 0x1E00 // FORMAT_RR ADD LOGICAL (32) 1400 op_ALRK uint32 = 0xB9FA // FORMAT_RRF1 ADD LOGICAL (32) 1401 op_ALSI uint32 = 0xEB6E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8) 1402 op_ALSIH uint32 = 0xCC0A // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1403 op_ALSIHN uint32 = 0xCC0B // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1404 op_ALY uint32 = 0xE35E // FORMAT_RXY1 ADD LOGICAL (32) 1405 op_AP uint32 = 0xFA00 // FORMAT_SS2 ADD DECIMAL 1406 op_AR uint32 = 0x1A00 // FORMAT_RR ADD (32) 1407 op_ARK uint32 = 0xB9F8 // FORMAT_RRF1 ADD (32) 1408 op_ASI uint32 = 0xEB6A // FORMAT_SIY ADD IMMEDIATE (32<-8) 1409 op_AU uint32 = 0x7E00 // FORMAT_RX1 ADD UNNORMALIZED (short HFP) 1410 op_AUR uint32 = 0x3E00 // FORMAT_RR ADD UNNORMALIZED (short HFP) 1411 op_AW uint32 = 0x6E00 // FORMAT_RX1 ADD UNNORMALIZED (long HFP) 1412 op_AWR uint32 = 0x2E00 // FORMAT_RR ADD UNNORMALIZED (long HFP) 1413 op_AXBR uint32 = 0xB34A // FORMAT_RRE ADD (extended BFP) 1414 op_AXR uint32 = 0x3600 // FORMAT_RR ADD NORMALIZED (extended HFP) 1415 op_AXTR uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1416 op_AXTRA uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1417 op_AY uint32 = 0xE35A // FORMAT_RXY1 ADD (32) 1418 op_BAKR uint32 = 0xB240 // FORMAT_RRE BRANCH AND STACK 1419 op_BAL uint32 = 0x4500 // FORMAT_RX1 BRANCH AND LINK 1420 op_BALR uint32 = 0x0500 // FORMAT_RR BRANCH AND LINK 1421 op_BAS uint32 = 0x4D00 // FORMAT_RX1 BRANCH AND SAVE 1422 op_BASR uint32 = 0x0D00 // FORMAT_RR BRANCH AND SAVE 1423 op_BASSM uint32 = 0x0C00 // FORMAT_RR BRANCH AND SAVE AND SET MODE 1424 op_BC uint32 = 0x4700 // FORMAT_RX2 BRANCH ON CONDITION 1425 op_BCR uint32 = 0x0700 // FORMAT_RR BRANCH ON CONDITION 1426 op_BCT uint32 = 0x4600 // FORMAT_RX1 BRANCH ON COUNT (32) 1427 op_BCTG uint32 = 0xE346 // FORMAT_RXY1 BRANCH ON COUNT (64) 1428 op_BCTGR uint32 = 0xB946 // FORMAT_RRE BRANCH ON COUNT (64) 1429 op_BCTR uint32 = 0x0600 // FORMAT_RR BRANCH ON COUNT (32) 1430 op_BPP uint32 = 0xC700 // FORMAT_SMI BRANCH PREDICTION PRELOAD 1431 op_BPRP uint32 = 0xC500 // FORMAT_MII BRANCH PREDICTION RELATIVE PRELOAD 1432 op_BRAS uint32 = 0xA705 // FORMAT_RI2 BRANCH RELATIVE AND SAVE 1433 op_BRASL uint32 = 0xC005 // FORMAT_RIL2 BRANCH RELATIVE AND SAVE LONG 1434 op_BRC uint32 = 0xA704 // FORMAT_RI3 BRANCH RELATIVE ON CONDITION 1435 op_BRCL uint32 = 0xC004 // FORMAT_RIL3 BRANCH RELATIVE ON CONDITION LONG 1436 op_BRCT uint32 = 0xA706 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (32) 1437 op_BRCTG uint32 = 0xA707 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (64) 1438 op_BRCTH uint32 = 0xCC06 // FORMAT_RIL2 BRANCH RELATIVE ON COUNT HIGH (32) 1439 op_BRXH uint32 = 0x8400 // FORMAT_RSI BRANCH RELATIVE ON INDEX HIGH (32) 1440 op_BRXHG uint32 = 0xEC44 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX HIGH (64) 1441 op_BRXLE uint32 = 0x8500 // FORMAT_RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32) 1442 op_BRXLG uint32 = 0xEC45 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX LOW OR EQ. (64) 1443 op_BSA uint32 = 0xB25A // FORMAT_RRE BRANCH AND SET AUTHORITY 1444 op_BSG uint32 = 0xB258 // FORMAT_RRE BRANCH IN SUBSPACE GROUP 1445 op_BSM uint32 = 0x0B00 // FORMAT_RR BRANCH AND SET MODE 1446 op_BXH uint32 = 0x8600 // FORMAT_RS1 BRANCH ON INDEX HIGH (32) 1447 op_BXHG uint32 = 0xEB44 // FORMAT_RSY1 BRANCH ON INDEX HIGH (64) 1448 op_BXLE uint32 = 0x8700 // FORMAT_RS1 BRANCH ON INDEX LOW OR EQUAL (32) 1449 op_BXLEG uint32 = 0xEB45 // FORMAT_RSY1 BRANCH ON INDEX LOW OR EQUAL (64) 1450 op_C uint32 = 0x5900 // FORMAT_RX1 COMPARE (32) 1451 op_CD uint32 = 0x6900 // FORMAT_RX1 COMPARE (long HFP) 1452 op_CDB uint32 = 0xED19 // FORMAT_RXE COMPARE (long BFP) 1453 op_CDBR uint32 = 0xB319 // FORMAT_RRE COMPARE (long BFP) 1454 op_CDFBR uint32 = 0xB395 // FORMAT_RRE CONVERT FROM FIXED (32 to long BFP) 1455 op_CDFBRA uint32 = 0xB395 // FORMAT_RRF5 CONVERT FROM FIXED (32 to long BFP) 1456 op_CDFR uint32 = 0xB3B5 // FORMAT_RRE CONVERT FROM FIXED (32 to long HFP) 1457 op_CDFTR uint32 = 0xB951 // FORMAT_RRE CONVERT FROM FIXED (32 to long DFP) 1458 op_CDGBR uint32 = 0xB3A5 // FORMAT_RRE CONVERT FROM FIXED (64 to long BFP) 1459 op_CDGBRA uint32 = 0xB3A5 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long BFP) 1460 op_CDGR uint32 = 0xB3C5 // FORMAT_RRE CONVERT FROM FIXED (64 to long HFP) 1461 op_CDGTR uint32 = 0xB3F1 // FORMAT_RRE CONVERT FROM FIXED (64 to long DFP) 1462 op_CDGTRA uint32 = 0xB3F1 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long DFP) 1463 op_CDLFBR uint32 = 0xB391 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long BFP) 1464 op_CDLFTR uint32 = 0xB953 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long DFP) 1465 op_CDLGBR uint32 = 0xB3A1 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long BFP) 1466 op_CDLGTR uint32 = 0xB952 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long DFP) 1467 op_CDR uint32 = 0x2900 // FORMAT_RR COMPARE (long HFP) 1468 op_CDS uint32 = 0xBB00 // FORMAT_RS1 COMPARE DOUBLE AND SWAP (32) 1469 op_CDSG uint32 = 0xEB3E // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (64) 1470 op_CDSTR uint32 = 0xB3F3 // FORMAT_RRE CONVERT FROM SIGNED PACKED (64 to long DFP) 1471 op_CDSY uint32 = 0xEB31 // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (32) 1472 op_CDTR uint32 = 0xB3E4 // FORMAT_RRE COMPARE (long DFP) 1473 op_CDUTR uint32 = 0xB3F2 // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP) 1474 op_CDZT uint32 = 0xEDAA // FORMAT_RSL CONVERT FROM ZONED (to long DFP) 1475 op_CE uint32 = 0x7900 // FORMAT_RX1 COMPARE (short HFP) 1476 op_CEB uint32 = 0xED09 // FORMAT_RXE COMPARE (short BFP) 1477 op_CEBR uint32 = 0xB309 // FORMAT_RRE COMPARE (short BFP) 1478 op_CEDTR uint32 = 0xB3F4 // FORMAT_RRE COMPARE BIASED EXPONENT (long DFP) 1479 op_CEFBR uint32 = 0xB394 // FORMAT_RRE CONVERT FROM FIXED (32 to short BFP) 1480 op_CEFBRA uint32 = 0xB394 // FORMAT_RRF5 CONVERT FROM FIXED (32 to short BFP) 1481 op_CEFR uint32 = 0xB3B4 // FORMAT_RRE CONVERT FROM FIXED (32 to short HFP) 1482 op_CEGBR uint32 = 0xB3A4 // FORMAT_RRE CONVERT FROM FIXED (64 to short BFP) 1483 op_CEGBRA uint32 = 0xB3A4 // FORMAT_RRF5 CONVERT FROM FIXED (64 to short BFP) 1484 op_CEGR uint32 = 0xB3C4 // FORMAT_RRE CONVERT FROM FIXED (64 to short HFP) 1485 op_CELFBR uint32 = 0xB390 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to short BFP) 1486 op_CELGBR uint32 = 0xB3A0 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to short BFP) 1487 op_CER uint32 = 0x3900 // FORMAT_RR COMPARE (short HFP) 1488 op_CEXTR uint32 = 0xB3FC // FORMAT_RRE COMPARE BIASED EXPONENT (extended DFP) 1489 op_CFC uint32 = 0xB21A // FORMAT_S COMPARE AND FORM CODEWORD 1490 op_CFDBR uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1491 op_CFDBRA uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1492 op_CFDR uint32 = 0xB3B9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 32) 1493 op_CFDTR uint32 = 0xB941 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 32) 1494 op_CFEBR uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1495 op_CFEBRA uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1496 op_CFER uint32 = 0xB3B8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 32) 1497 op_CFI uint32 = 0xC20D // FORMAT_RIL1 COMPARE IMMEDIATE (32) 1498 op_CFXBR uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1499 op_CFXBRA uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1500 op_CFXR uint32 = 0xB3BA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 32) 1501 op_CFXTR uint32 = 0xB949 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 32) 1502 op_CG uint32 = 0xE320 // FORMAT_RXY1 COMPARE (64) 1503 op_CGDBR uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1504 op_CGDBRA uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1505 op_CGDR uint32 = 0xB3C9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 64) 1506 op_CGDTR uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1507 op_CGDTRA uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1508 op_CGEBR uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1509 op_CGEBRA uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1510 op_CGER uint32 = 0xB3C8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 64) 1511 op_CGF uint32 = 0xE330 // FORMAT_RXY1 COMPARE (64<-32) 1512 op_CGFI uint32 = 0xC20C // FORMAT_RIL1 COMPARE IMMEDIATE (64<-32) 1513 op_CGFR uint32 = 0xB930 // FORMAT_RRE COMPARE (64<-32) 1514 op_CGFRL uint32 = 0xC60C // FORMAT_RIL2 COMPARE RELATIVE LONG (64<-32) 1515 op_CGH uint32 = 0xE334 // FORMAT_RXY1 COMPARE HALFWORD (64<-16) 1516 op_CGHI uint32 = 0xA70F // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (64<-16) 1517 op_CGHRL uint32 = 0xC604 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (64<-16) 1518 op_CGHSI uint32 = 0xE558 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (64<-16) 1519 op_CGIB uint32 = 0xECFC // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (64<-8) 1520 op_CGIJ uint32 = 0xEC7C // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8) 1521 op_CGIT uint32 = 0xEC70 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (64<-16) 1522 op_CGR uint32 = 0xB920 // FORMAT_RRE COMPARE (64) 1523 op_CGRB uint32 = 0xECE4 // FORMAT_RRS COMPARE AND BRANCH (64) 1524 op_CGRJ uint32 = 0xEC64 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (64) 1525 op_CGRL uint32 = 0xC608 // FORMAT_RIL2 COMPARE RELATIVE LONG (64) 1526 op_CGRT uint32 = 0xB960 // FORMAT_RRF3 COMPARE AND TRAP (64) 1527 op_CGXBR uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1528 op_CGXBRA uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1529 op_CGXR uint32 = 0xB3CA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 64) 1530 op_CGXTR uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1531 op_CGXTRA uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1532 op_CH uint32 = 0x4900 // FORMAT_RX1 COMPARE HALFWORD (32<-16) 1533 op_CHF uint32 = 0xE3CD // FORMAT_RXY1 COMPARE HIGH (32) 1534 op_CHHR uint32 = 0xB9CD // FORMAT_RRE COMPARE HIGH (32) 1535 op_CHHSI uint32 = 0xE554 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (16) 1536 op_CHI uint32 = 0xA70E // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (32<-16) 1537 op_CHLR uint32 = 0xB9DD // FORMAT_RRE COMPARE HIGH (32) 1538 op_CHRL uint32 = 0xC605 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (32<-16) 1539 op_CHSI uint32 = 0xE55C // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (32<-16) 1540 op_CHY uint32 = 0xE379 // FORMAT_RXY1 COMPARE HALFWORD (32<-16) 1541 op_CIB uint32 = 0xECFE // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (32<-8) 1542 op_CIH uint32 = 0xCC0D // FORMAT_RIL1 COMPARE IMMEDIATE HIGH (32) 1543 op_CIJ uint32 = 0xEC7E // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8) 1544 op_CIT uint32 = 0xEC72 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (32<-16) 1545 op_CKSM uint32 = 0xB241 // FORMAT_RRE CHECKSUM 1546 op_CL uint32 = 0x5500 // FORMAT_RX1 COMPARE LOGICAL (32) 1547 op_CLC uint32 = 0xD500 // FORMAT_SS1 COMPARE LOGICAL (character) 1548 op_CLCL uint32 = 0x0F00 // FORMAT_RR COMPARE LOGICAL LONG 1549 op_CLCLE uint32 = 0xA900 // FORMAT_RS1 COMPARE LOGICAL LONG EXTENDED 1550 op_CLCLU uint32 = 0xEB8F // FORMAT_RSY1 COMPARE LOGICAL LONG UNICODE 1551 op_CLFDBR uint32 = 0xB39D // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 32) 1552 op_CLFDTR uint32 = 0xB943 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 32) 1553 op_CLFEBR uint32 = 0xB39C // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 32) 1554 op_CLFHSI uint32 = 0xE55D // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (32<-16) 1555 op_CLFI uint32 = 0xC20F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (32) 1556 op_CLFIT uint32 = 0xEC73 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16) 1557 op_CLFXBR uint32 = 0xB39E // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 32) 1558 op_CLFXTR uint32 = 0xB94B // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 32) 1559 op_CLG uint32 = 0xE321 // FORMAT_RXY1 COMPARE LOGICAL (64) 1560 op_CLGDBR uint32 = 0xB3AD // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 64) 1561 op_CLGDTR uint32 = 0xB942 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 64) 1562 op_CLGEBR uint32 = 0xB3AC // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 64) 1563 op_CLGF uint32 = 0xE331 // FORMAT_RXY1 COMPARE LOGICAL (64<-32) 1564 op_CLGFI uint32 = 0xC20E // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (64<-32) 1565 op_CLGFR uint32 = 0xB931 // FORMAT_RRE COMPARE LOGICAL (64<-32) 1566 op_CLGFRL uint32 = 0xC60E // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-32) 1567 op_CLGHRL uint32 = 0xC606 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-16) 1568 op_CLGHSI uint32 = 0xE559 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (64<-16) 1569 op_CLGIB uint32 = 0xECFD // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8) 1570 op_CLGIJ uint32 = 0xEC7D // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (64<-8) 1571 op_CLGIT uint32 = 0xEC71 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16) 1572 op_CLGR uint32 = 0xB921 // FORMAT_RRE COMPARE LOGICAL (64) 1573 op_CLGRB uint32 = 0xECE5 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (64) 1574 op_CLGRJ uint32 = 0xEC65 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (64) 1575 op_CLGRL uint32 = 0xC60A // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64) 1576 op_CLGRT uint32 = 0xB961 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (64) 1577 op_CLGT uint32 = 0xEB2B // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (64) 1578 op_CLGXBR uint32 = 0xB3AE // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 64) 1579 op_CLGXTR uint32 = 0xB94A // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 64) 1580 op_CLHF uint32 = 0xE3CF // FORMAT_RXY1 COMPARE LOGICAL HIGH (32) 1581 op_CLHHR uint32 = 0xB9CF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1582 op_CLHHSI uint32 = 0xE555 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (16) 1583 op_CLHLR uint32 = 0xB9DF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1584 op_CLHRL uint32 = 0xC607 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32<-16) 1585 op_CLI uint32 = 0x9500 // FORMAT_SI COMPARE LOGICAL (immediate) 1586 op_CLIB uint32 = 0xECFF // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8) 1587 op_CLIH uint32 = 0xCC0F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE HIGH (32) 1588 op_CLIJ uint32 = 0xEC7F // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (32<-8) 1589 op_CLIY uint32 = 0xEB55 // FORMAT_SIY COMPARE LOGICAL (immediate) 1590 op_CLM uint32 = 0xBD00 // FORMAT_RS2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1591 op_CLMH uint32 = 0xEB20 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (high) 1592 op_CLMY uint32 = 0xEB21 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1593 op_CLR uint32 = 0x1500 // FORMAT_RR COMPARE LOGICAL (32) 1594 op_CLRB uint32 = 0xECF7 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (32) 1595 op_CLRJ uint32 = 0xEC77 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (32) 1596 op_CLRL uint32 = 0xC60F // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32) 1597 op_CLRT uint32 = 0xB973 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (32) 1598 op_CLST uint32 = 0xB25D // FORMAT_RRE COMPARE LOGICAL STRING 1599 op_CLT uint32 = 0xEB23 // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (32) 1600 op_CLY uint32 = 0xE355 // FORMAT_RXY1 COMPARE LOGICAL (32) 1601 op_CMPSC uint32 = 0xB263 // FORMAT_RRE COMPRESSION CALL 1602 op_CP uint32 = 0xF900 // FORMAT_SS2 COMPARE DECIMAL 1603 op_CPSDR uint32 = 0xB372 // FORMAT_RRF2 COPY SIGN (long) 1604 op_CPYA uint32 = 0xB24D // FORMAT_RRE COPY ACCESS 1605 op_CR uint32 = 0x1900 // FORMAT_RR COMPARE (32) 1606 op_CRB uint32 = 0xECF6 // FORMAT_RRS COMPARE AND BRANCH (32) 1607 op_CRDTE uint32 = 0xB98F // FORMAT_RRF2 COMPARE AND REPLACE DAT TABLE ENTRY 1608 op_CRJ uint32 = 0xEC76 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (32) 1609 op_CRL uint32 = 0xC60D // FORMAT_RIL2 COMPARE RELATIVE LONG (32) 1610 op_CRT uint32 = 0xB972 // FORMAT_RRF3 COMPARE AND TRAP (32) 1611 op_CS uint32 = 0xBA00 // FORMAT_RS1 COMPARE AND SWAP (32) 1612 op_CSCH uint32 = 0xB230 // FORMAT_S CLEAR SUBCHANNEL 1613 op_CSDTR uint32 = 0xB3E3 // FORMAT_RRF4 CONVERT TO SIGNED PACKED (long DFP to 64) 1614 op_CSG uint32 = 0xEB30 // FORMAT_RSY1 COMPARE AND SWAP (64) 1615 op_CSP uint32 = 0xB250 // FORMAT_RRE COMPARE AND SWAP AND PURGE 1616 op_CSPG uint32 = 0xB98A // FORMAT_RRE COMPARE AND SWAP AND PURGE 1617 op_CSST uint32 = 0xC802 // FORMAT_SSF COMPARE AND SWAP AND STORE 1618 op_CSXTR uint32 = 0xB3EB // FORMAT_RRF4 CONVERT TO SIGNED PACKED (extended DFP to 128) 1619 op_CSY uint32 = 0xEB14 // FORMAT_RSY1 COMPARE AND SWAP (32) 1620 op_CU12 uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-16 1621 op_CU14 uint32 = 0xB9B0 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-32 1622 op_CU21 uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-8 1623 op_CU24 uint32 = 0xB9B1 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-32 1624 op_CU41 uint32 = 0xB9B2 // FORMAT_RRE CONVERT UTF-32 TO UTF-8 1625 op_CU42 uint32 = 0xB9B3 // FORMAT_RRE CONVERT UTF-32 TO UTF-16 1626 op_CUDTR uint32 = 0xB3E2 // FORMAT_RRE CONVERT TO UNSIGNED PACKED (long DFP to 64) 1627 op_CUSE uint32 = 0xB257 // FORMAT_RRE COMPARE UNTIL SUBSTRING EQUAL 1628 op_CUTFU uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UNICODE 1629 op_CUUTF uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UNICODE TO UTF-8 1630 op_CUXTR uint32 = 0xB3EA // FORMAT_RRE CONVERT TO UNSIGNED PACKED (extended DFP to 128) 1631 op_CVB uint32 = 0x4F00 // FORMAT_RX1 CONVERT TO BINARY (32) 1632 op_CVBG uint32 = 0xE30E // FORMAT_RXY1 CONVERT TO BINARY (64) 1633 op_CVBY uint32 = 0xE306 // FORMAT_RXY1 CONVERT TO BINARY (32) 1634 op_CVD uint32 = 0x4E00 // FORMAT_RX1 CONVERT TO DECIMAL (32) 1635 op_CVDG uint32 = 0xE32E // FORMAT_RXY1 CONVERT TO DECIMAL (64) 1636 op_CVDY uint32 = 0xE326 // FORMAT_RXY1 CONVERT TO DECIMAL (32) 1637 op_CXBR uint32 = 0xB349 // FORMAT_RRE COMPARE (extended BFP) 1638 op_CXFBR uint32 = 0xB396 // FORMAT_RRE CONVERT FROM FIXED (32 to extended BFP) 1639 op_CXFBRA uint32 = 0xB396 // FORMAT_RRF5 CONVERT FROM FIXED (32 to extended BFP) 1640 op_CXFR uint32 = 0xB3B6 // FORMAT_RRE CONVERT FROM FIXED (32 to extended HFP) 1641 op_CXFTR uint32 = 0xB959 // FORMAT_RRE CONVERT FROM FIXED (32 to extended DFP) 1642 op_CXGBR uint32 = 0xB3A6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended BFP) 1643 op_CXGBRA uint32 = 0xB3A6 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended BFP) 1644 op_CXGR uint32 = 0xB3C6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended HFP) 1645 op_CXGTR uint32 = 0xB3F9 // FORMAT_RRE CONVERT FROM FIXED (64 to extended DFP) 1646 op_CXGTRA uint32 = 0xB3F9 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended DFP) 1647 op_CXLFBR uint32 = 0xB392 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended BFP) 1648 op_CXLFTR uint32 = 0xB95B // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended DFP) 1649 op_CXLGBR uint32 = 0xB3A2 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended BFP) 1650 op_CXLGTR uint32 = 0xB95A // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended DFP) 1651 op_CXR uint32 = 0xB369 // FORMAT_RRE COMPARE (extended HFP) 1652 op_CXSTR uint32 = 0xB3FB // FORMAT_RRE CONVERT FROM SIGNED PACKED (128 to extended DFP) 1653 op_CXTR uint32 = 0xB3EC // FORMAT_RRE COMPARE (extended DFP) 1654 op_CXUTR uint32 = 0xB3FA // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) 1655 op_CXZT uint32 = 0xEDAB // FORMAT_RSL CONVERT FROM ZONED (to extended DFP) 1656 op_CY uint32 = 0xE359 // FORMAT_RXY1 COMPARE (32) 1657 op_CZDT uint32 = 0xEDA8 // FORMAT_RSL CONVERT TO ZONED (from long DFP) 1658 op_CZXT uint32 = 0xEDA9 // FORMAT_RSL CONVERT TO ZONED (from extended DFP) 1659 op_D uint32 = 0x5D00 // FORMAT_RX1 DIVIDE (32<-64) 1660 op_DD uint32 = 0x6D00 // FORMAT_RX1 DIVIDE (long HFP) 1661 op_DDB uint32 = 0xED1D // FORMAT_RXE DIVIDE (long BFP) 1662 op_DDBR uint32 = 0xB31D // FORMAT_RRE DIVIDE (long BFP) 1663 op_DDR uint32 = 0x2D00 // FORMAT_RR DIVIDE (long HFP) 1664 op_DDTR uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1665 op_DDTRA uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1666 op_DE uint32 = 0x7D00 // FORMAT_RX1 DIVIDE (short HFP) 1667 op_DEB uint32 = 0xED0D // FORMAT_RXE DIVIDE (short BFP) 1668 op_DEBR uint32 = 0xB30D // FORMAT_RRE DIVIDE (short BFP) 1669 op_DER uint32 = 0x3D00 // FORMAT_RR DIVIDE (short HFP) 1670 op_DIDBR uint32 = 0xB35B // FORMAT_RRF2 DIVIDE TO INTEGER (long BFP) 1671 op_DIEBR uint32 = 0xB353 // FORMAT_RRF2 DIVIDE TO INTEGER (short BFP) 1672 op_DL uint32 = 0xE397 // FORMAT_RXY1 DIVIDE LOGICAL (32<-64) 1673 op_DLG uint32 = 0xE387 // FORMAT_RXY1 DIVIDE LOGICAL (64<-128) 1674 op_DLGR uint32 = 0xB987 // FORMAT_RRE DIVIDE LOGICAL (64<-128) 1675 op_DLR uint32 = 0xB997 // FORMAT_RRE DIVIDE LOGICAL (32<-64) 1676 op_DP uint32 = 0xFD00 // FORMAT_SS2 DIVIDE DECIMAL 1677 op_DR uint32 = 0x1D00 // FORMAT_RR DIVIDE (32<-64) 1678 op_DSG uint32 = 0xE30D // FORMAT_RXY1 DIVIDE SINGLE (64) 1679 op_DSGF uint32 = 0xE31D // FORMAT_RXY1 DIVIDE SINGLE (64<-32) 1680 op_DSGFR uint32 = 0xB91D // FORMAT_RRE DIVIDE SINGLE (64<-32) 1681 op_DSGR uint32 = 0xB90D // FORMAT_RRE DIVIDE SINGLE (64) 1682 op_DXBR uint32 = 0xB34D // FORMAT_RRE DIVIDE (extended BFP) 1683 op_DXR uint32 = 0xB22D // FORMAT_RRE DIVIDE (extended HFP) 1684 op_DXTR uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1685 op_DXTRA uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1686 op_EAR uint32 = 0xB24F // FORMAT_RRE EXTRACT ACCESS 1687 op_ECAG uint32 = 0xEB4C // FORMAT_RSY1 EXTRACT CACHE ATTRIBUTE 1688 op_ECTG uint32 = 0xC801 // FORMAT_SSF EXTRACT CPU TIME 1689 op_ED uint32 = 0xDE00 // FORMAT_SS1 EDIT 1690 op_EDMK uint32 = 0xDF00 // FORMAT_SS1 EDIT AND MARK 1691 op_EEDTR uint32 = 0xB3E5 // FORMAT_RRE EXTRACT BIASED EXPONENT (long DFP to 64) 1692 op_EEXTR uint32 = 0xB3ED // FORMAT_RRE EXTRACT BIASED EXPONENT (extended DFP to 64) 1693 op_EFPC uint32 = 0xB38C // FORMAT_RRE EXTRACT FPC 1694 op_EPAIR uint32 = 0xB99A // FORMAT_RRE EXTRACT PRIMARY ASN AND INSTANCE 1695 op_EPAR uint32 = 0xB226 // FORMAT_RRE EXTRACT PRIMARY ASN 1696 op_EPSW uint32 = 0xB98D // FORMAT_RRE EXTRACT PSW 1697 op_EREG uint32 = 0xB249 // FORMAT_RRE EXTRACT STACKED REGISTERS (32) 1698 op_EREGG uint32 = 0xB90E // FORMAT_RRE EXTRACT STACKED REGISTERS (64) 1699 op_ESAIR uint32 = 0xB99B // FORMAT_RRE EXTRACT SECONDARY ASN AND INSTANCE 1700 op_ESAR uint32 = 0xB227 // FORMAT_RRE EXTRACT SECONDARY ASN 1701 op_ESDTR uint32 = 0xB3E7 // FORMAT_RRE EXTRACT SIGNIFICANCE (long DFP) 1702 op_ESEA uint32 = 0xB99D // FORMAT_RRE EXTRACT AND SET EXTENDED AUTHORITY 1703 op_ESTA uint32 = 0xB24A // FORMAT_RRE EXTRACT STACKED STATE 1704 op_ESXTR uint32 = 0xB3EF // FORMAT_RRE EXTRACT SIGNIFICANCE (extended DFP) 1705 op_ETND uint32 = 0xB2EC // FORMAT_RRE EXTRACT TRANSACTION NESTING DEPTH 1706 op_EX uint32 = 0x4400 // FORMAT_RX1 EXECUTE 1707 op_EXRL uint32 = 0xC600 // FORMAT_RIL2 EXECUTE RELATIVE LONG 1708 op_FIDBR uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1709 op_FIDBRA uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1710 op_FIDR uint32 = 0xB37F // FORMAT_RRE LOAD FP INTEGER (long HFP) 1711 op_FIDTR uint32 = 0xB3D7 // FORMAT_RRF5 LOAD FP INTEGER (long DFP) 1712 op_FIEBR uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1713 op_FIEBRA uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1714 op_FIER uint32 = 0xB377 // FORMAT_RRE LOAD FP INTEGER (short HFP) 1715 op_FIXBR uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1716 op_FIXBRA uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1717 op_FIXR uint32 = 0xB367 // FORMAT_RRE LOAD FP INTEGER (extended HFP) 1718 op_FIXTR uint32 = 0xB3DF // FORMAT_RRF5 LOAD FP INTEGER (extended DFP) 1719 op_FLOGR uint32 = 0xB983 // FORMAT_RRE FIND LEFTMOST ONE 1720 op_HDR uint32 = 0x2400 // FORMAT_RR HALVE (long HFP) 1721 op_HER uint32 = 0x3400 // FORMAT_RR HALVE (short HFP) 1722 op_HSCH uint32 = 0xB231 // FORMAT_S HALT SUBCHANNEL 1723 op_IAC uint32 = 0xB224 // FORMAT_RRE INSERT ADDRESS SPACE CONTROL 1724 op_IC uint32 = 0x4300 // FORMAT_RX1 INSERT CHARACTER 1725 op_ICM uint32 = 0xBF00 // FORMAT_RS2 INSERT CHARACTERS UNDER MASK (low) 1726 op_ICMH uint32 = 0xEB80 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (high) 1727 op_ICMY uint32 = 0xEB81 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (low) 1728 op_ICY uint32 = 0xE373 // FORMAT_RXY1 INSERT CHARACTER 1729 op_IDTE uint32 = 0xB98E // FORMAT_RRF2 INVALIDATE DAT TABLE ENTRY 1730 op_IEDTR uint32 = 0xB3F6 // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to long DFP) 1731 op_IEXTR uint32 = 0xB3FE // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to extended DFP) 1732 op_IIHF uint32 = 0xC008 // FORMAT_RIL1 INSERT IMMEDIATE (high) 1733 op_IIHH uint32 = 0xA500 // FORMAT_RI1 INSERT IMMEDIATE (high high) 1734 op_IIHL uint32 = 0xA501 // FORMAT_RI1 INSERT IMMEDIATE (high low) 1735 op_IILF uint32 = 0xC009 // FORMAT_RIL1 INSERT IMMEDIATE (low) 1736 op_IILH uint32 = 0xA502 // FORMAT_RI1 INSERT IMMEDIATE (low high) 1737 op_IILL uint32 = 0xA503 // FORMAT_RI1 INSERT IMMEDIATE (low low) 1738 op_IPK uint32 = 0xB20B // FORMAT_S INSERT PSW KEY 1739 op_IPM uint32 = 0xB222 // FORMAT_RRE INSERT PROGRAM MASK 1740 op_IPTE uint32 = 0xB221 // FORMAT_RRF1 INVALIDATE PAGE TABLE ENTRY 1741 op_ISKE uint32 = 0xB229 // FORMAT_RRE INSERT STORAGE KEY EXTENDED 1742 op_IVSK uint32 = 0xB223 // FORMAT_RRE INSERT VIRTUAL STORAGE KEY 1743 op_KDB uint32 = 0xED18 // FORMAT_RXE COMPARE AND SIGNAL (long BFP) 1744 op_KDBR uint32 = 0xB318 // FORMAT_RRE COMPARE AND SIGNAL (long BFP) 1745 op_KDTR uint32 = 0xB3E0 // FORMAT_RRE COMPARE AND SIGNAL (long DFP) 1746 op_KEB uint32 = 0xED08 // FORMAT_RXE COMPARE AND SIGNAL (short BFP) 1747 op_KEBR uint32 = 0xB308 // FORMAT_RRE COMPARE AND SIGNAL (short BFP) 1748 op_KIMD uint32 = 0xB93E // FORMAT_RRE COMPUTE INTERMEDIATE MESSAGE DIGEST 1749 op_KLMD uint32 = 0xB93F // FORMAT_RRE COMPUTE LAST MESSAGE DIGEST 1750 op_KM uint32 = 0xB92E // FORMAT_RRE CIPHER MESSAGE 1751 op_KMAC uint32 = 0xB91E // FORMAT_RRE COMPUTE MESSAGE AUTHENTICATION CODE 1752 op_KMC uint32 = 0xB92F // FORMAT_RRE CIPHER MESSAGE WITH CHAINING 1753 op_KMCTR uint32 = 0xB92D // FORMAT_RRF2 CIPHER MESSAGE WITH COUNTER 1754 op_KMF uint32 = 0xB92A // FORMAT_RRE CIPHER MESSAGE WITH CFB 1755 op_KMO uint32 = 0xB92B // FORMAT_RRE CIPHER MESSAGE WITH OFB 1756 op_KXBR uint32 = 0xB348 // FORMAT_RRE COMPARE AND SIGNAL (extended BFP) 1757 op_KXTR uint32 = 0xB3E8 // FORMAT_RRE COMPARE AND SIGNAL (extended DFP) 1758 op_L uint32 = 0x5800 // FORMAT_RX1 LOAD (32) 1759 op_LA uint32 = 0x4100 // FORMAT_RX1 LOAD ADDRESS 1760 op_LAA uint32 = 0xEBF8 // FORMAT_RSY1 LOAD AND ADD (32) 1761 op_LAAG uint32 = 0xEBE8 // FORMAT_RSY1 LOAD AND ADD (64) 1762 op_LAAL uint32 = 0xEBFA // FORMAT_RSY1 LOAD AND ADD LOGICAL (32) 1763 op_LAALG uint32 = 0xEBEA // FORMAT_RSY1 LOAD AND ADD LOGICAL (64) 1764 op_LAE uint32 = 0x5100 // FORMAT_RX1 LOAD ADDRESS EXTENDED 1765 op_LAEY uint32 = 0xE375 // FORMAT_RXY1 LOAD ADDRESS EXTENDED 1766 op_LAM uint32 = 0x9A00 // FORMAT_RS1 LOAD ACCESS MULTIPLE 1767 op_LAMY uint32 = 0xEB9A // FORMAT_RSY1 LOAD ACCESS MULTIPLE 1768 op_LAN uint32 = 0xEBF4 // FORMAT_RSY1 LOAD AND AND (32) 1769 op_LANG uint32 = 0xEBE4 // FORMAT_RSY1 LOAD AND AND (64) 1770 op_LAO uint32 = 0xEBF6 // FORMAT_RSY1 LOAD AND OR (32) 1771 op_LAOG uint32 = 0xEBE6 // FORMAT_RSY1 LOAD AND OR (64) 1772 op_LARL uint32 = 0xC000 // FORMAT_RIL2 LOAD ADDRESS RELATIVE LONG 1773 op_LASP uint32 = 0xE500 // FORMAT_SSE LOAD ADDRESS SPACE PARAMETERS 1774 op_LAT uint32 = 0xE39F // FORMAT_RXY1 LOAD AND TRAP (32L<-32) 1775 op_LAX uint32 = 0xEBF7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (32) 1776 op_LAXG uint32 = 0xEBE7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (64) 1777 op_LAY uint32 = 0xE371 // FORMAT_RXY1 LOAD ADDRESS 1778 op_LB uint32 = 0xE376 // FORMAT_RXY1 LOAD BYTE (32) 1779 op_LBH uint32 = 0xE3C0 // FORMAT_RXY1 LOAD BYTE HIGH (32<-8) 1780 op_LBR uint32 = 0xB926 // FORMAT_RRE LOAD BYTE (32) 1781 op_LCDBR uint32 = 0xB313 // FORMAT_RRE LOAD COMPLEMENT (long BFP) 1782 op_LCDFR uint32 = 0xB373 // FORMAT_RRE LOAD COMPLEMENT (long) 1783 op_LCDR uint32 = 0x2300 // FORMAT_RR LOAD COMPLEMENT (long HFP) 1784 op_LCEBR uint32 = 0xB303 // FORMAT_RRE LOAD COMPLEMENT (short BFP) 1785 op_LCER uint32 = 0x3300 // FORMAT_RR LOAD COMPLEMENT (short HFP) 1786 op_LCGFR uint32 = 0xB913 // FORMAT_RRE LOAD COMPLEMENT (64<-32) 1787 op_LCGR uint32 = 0xB903 // FORMAT_RRE LOAD COMPLEMENT (64) 1788 op_LCR uint32 = 0x1300 // FORMAT_RR LOAD COMPLEMENT (32) 1789 op_LCTL uint32 = 0xB700 // FORMAT_RS1 LOAD CONTROL (32) 1790 op_LCTLG uint32 = 0xEB2F // FORMAT_RSY1 LOAD CONTROL (64) 1791 op_LCXBR uint32 = 0xB343 // FORMAT_RRE LOAD COMPLEMENT (extended BFP) 1792 op_LCXR uint32 = 0xB363 // FORMAT_RRE LOAD COMPLEMENT (extended HFP) 1793 op_LD uint32 = 0x6800 // FORMAT_RX1 LOAD (long) 1794 op_LDE uint32 = 0xED24 // FORMAT_RXE LOAD LENGTHENED (short to long HFP) 1795 op_LDEB uint32 = 0xED04 // FORMAT_RXE LOAD LENGTHENED (short to long BFP) 1796 op_LDEBR uint32 = 0xB304 // FORMAT_RRE LOAD LENGTHENED (short to long BFP) 1797 op_LDER uint32 = 0xB324 // FORMAT_RRE LOAD LENGTHENED (short to long HFP) 1798 op_LDETR uint32 = 0xB3D4 // FORMAT_RRF4 LOAD LENGTHENED (short to long DFP) 1799 op_LDGR uint32 = 0xB3C1 // FORMAT_RRE LOAD FPR FROM GR (64 to long) 1800 op_LDR uint32 = 0x2800 // FORMAT_RR LOAD (long) 1801 op_LDXBR uint32 = 0xB345 // FORMAT_RRE LOAD ROUNDED (extended to long BFP) 1802 op_LDXBRA uint32 = 0xB345 // FORMAT_RRF5 LOAD ROUNDED (extended to long BFP) 1803 op_LDXR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1804 op_LDXTR uint32 = 0xB3DD // FORMAT_RRF5 LOAD ROUNDED (extended to long DFP) 1805 op_LDY uint32 = 0xED65 // FORMAT_RXY1 LOAD (long) 1806 op_LE uint32 = 0x7800 // FORMAT_RX1 LOAD (short) 1807 op_LEDBR uint32 = 0xB344 // FORMAT_RRE LOAD ROUNDED (long to short BFP) 1808 op_LEDBRA uint32 = 0xB344 // FORMAT_RRF5 LOAD ROUNDED (long to short BFP) 1809 op_LEDR uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1810 op_LEDTR uint32 = 0xB3D5 // FORMAT_RRF5 LOAD ROUNDED (long to short DFP) 1811 op_LER uint32 = 0x3800 // FORMAT_RR LOAD (short) 1812 op_LEXBR uint32 = 0xB346 // FORMAT_RRE LOAD ROUNDED (extended to short BFP) 1813 op_LEXBRA uint32 = 0xB346 // FORMAT_RRF5 LOAD ROUNDED (extended to short BFP) 1814 op_LEXR uint32 = 0xB366 // FORMAT_RRE LOAD ROUNDED (extended to short HFP) 1815 op_LEY uint32 = 0xED64 // FORMAT_RXY1 LOAD (short) 1816 op_LFAS uint32 = 0xB2BD // FORMAT_S LOAD FPC AND SIGNAL 1817 op_LFH uint32 = 0xE3CA // FORMAT_RXY1 LOAD HIGH (32) 1818 op_LFHAT uint32 = 0xE3C8 // FORMAT_RXY1 LOAD HIGH AND TRAP (32H<-32) 1819 op_LFPC uint32 = 0xB29D // FORMAT_S LOAD FPC 1820 op_LG uint32 = 0xE304 // FORMAT_RXY1 LOAD (64) 1821 op_LGAT uint32 = 0xE385 // FORMAT_RXY1 LOAD AND TRAP (64) 1822 op_LGB uint32 = 0xE377 // FORMAT_RXY1 LOAD BYTE (64) 1823 op_LGBR uint32 = 0xB906 // FORMAT_RRE LOAD BYTE (64) 1824 op_LGDR uint32 = 0xB3CD // FORMAT_RRE LOAD GR FROM FPR (long to 64) 1825 op_LGF uint32 = 0xE314 // FORMAT_RXY1 LOAD (64<-32) 1826 op_LGFI uint32 = 0xC001 // FORMAT_RIL1 LOAD IMMEDIATE (64<-32) 1827 op_LGFR uint32 = 0xB914 // FORMAT_RRE LOAD (64<-32) 1828 op_LGFRL uint32 = 0xC40C // FORMAT_RIL2 LOAD RELATIVE LONG (64<-32) 1829 op_LGH uint32 = 0xE315 // FORMAT_RXY1 LOAD HALFWORD (64) 1830 op_LGHI uint32 = 0xA709 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (64) 1831 op_LGHR uint32 = 0xB907 // FORMAT_RRE LOAD HALFWORD (64) 1832 op_LGHRL uint32 = 0xC404 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (64<-16) 1833 op_LGR uint32 = 0xB904 // FORMAT_RRE LOAD (64) 1834 op_LGRL uint32 = 0xC408 // FORMAT_RIL2 LOAD RELATIVE LONG (64) 1835 op_LH uint32 = 0x4800 // FORMAT_RX1 LOAD HALFWORD (32) 1836 op_LHH uint32 = 0xE3C4 // FORMAT_RXY1 LOAD HALFWORD HIGH (32<-16) 1837 op_LHI uint32 = 0xA708 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (32) 1838 op_LHR uint32 = 0xB927 // FORMAT_RRE LOAD HALFWORD (32) 1839 op_LHRL uint32 = 0xC405 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (32<-16) 1840 op_LHY uint32 = 0xE378 // FORMAT_RXY1 LOAD HALFWORD (32) 1841 op_LLC uint32 = 0xE394 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (32) 1842 op_LLCH uint32 = 0xE3C2 // FORMAT_RXY1 LOAD LOGICAL CHARACTER HIGH (32<-8) 1843 op_LLCR uint32 = 0xB994 // FORMAT_RRE LOAD LOGICAL CHARACTER (32) 1844 op_LLGC uint32 = 0xE390 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (64) 1845 op_LLGCR uint32 = 0xB984 // FORMAT_RRE LOAD LOGICAL CHARACTER (64) 1846 op_LLGF uint32 = 0xE316 // FORMAT_RXY1 LOAD LOGICAL (64<-32) 1847 op_LLGFAT uint32 = 0xE39D // FORMAT_RXY1 LOAD LOGICAL AND TRAP (64<-32) 1848 op_LLGFR uint32 = 0xB916 // FORMAT_RRE LOAD LOGICAL (64<-32) 1849 op_LLGFRL uint32 = 0xC40E // FORMAT_RIL2 LOAD LOGICAL RELATIVE LONG (64<-32) 1850 op_LLGH uint32 = 0xE391 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (64) 1851 op_LLGHR uint32 = 0xB985 // FORMAT_RRE LOAD LOGICAL HALFWORD (64) 1852 op_LLGHRL uint32 = 0xC406 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16) 1853 op_LLGT uint32 = 0xE317 // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS 1854 op_LLGTAT uint32 = 0xE39C // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31) 1855 op_LLGTR uint32 = 0xB917 // FORMAT_RRE LOAD LOGICAL THIRTY ONE BITS 1856 op_LLH uint32 = 0xE395 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (32) 1857 op_LLHH uint32 = 0xE3C6 // FORMAT_RXY1 LOAD LOGICAL HALFWORD HIGH (32<-16) 1858 op_LLHR uint32 = 0xB995 // FORMAT_RRE LOAD LOGICAL HALFWORD (32) 1859 op_LLHRL uint32 = 0xC402 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16) 1860 op_LLIHF uint32 = 0xC00E // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (high) 1861 op_LLIHH uint32 = 0xA50C // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high high) 1862 op_LLIHL uint32 = 0xA50D // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high low) 1863 op_LLILF uint32 = 0xC00F // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (low) 1864 op_LLILH uint32 = 0xA50E // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low high) 1865 op_LLILL uint32 = 0xA50F // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low low) 1866 op_LM uint32 = 0x9800 // FORMAT_RS1 LOAD MULTIPLE (32) 1867 op_LMD uint32 = 0xEF00 // FORMAT_SS5 LOAD MULTIPLE DISJOINT 1868 op_LMG uint32 = 0xEB04 // FORMAT_RSY1 LOAD MULTIPLE (64) 1869 op_LMH uint32 = 0xEB96 // FORMAT_RSY1 LOAD MULTIPLE HIGH 1870 op_LMY uint32 = 0xEB98 // FORMAT_RSY1 LOAD MULTIPLE (32) 1871 op_LNDBR uint32 = 0xB311 // FORMAT_RRE LOAD NEGATIVE (long BFP) 1872 op_LNDFR uint32 = 0xB371 // FORMAT_RRE LOAD NEGATIVE (long) 1873 op_LNDR uint32 = 0x2100 // FORMAT_RR LOAD NEGATIVE (long HFP) 1874 op_LNEBR uint32 = 0xB301 // FORMAT_RRE LOAD NEGATIVE (short BFP) 1875 op_LNER uint32 = 0x3100 // FORMAT_RR LOAD NEGATIVE (short HFP) 1876 op_LNGFR uint32 = 0xB911 // FORMAT_RRE LOAD NEGATIVE (64<-32) 1877 op_LNGR uint32 = 0xB901 // FORMAT_RRE LOAD NEGATIVE (64) 1878 op_LNR uint32 = 0x1100 // FORMAT_RR LOAD NEGATIVE (32) 1879 op_LNXBR uint32 = 0xB341 // FORMAT_RRE LOAD NEGATIVE (extended BFP) 1880 op_LNXR uint32 = 0xB361 // FORMAT_RRE LOAD NEGATIVE (extended HFP) 1881 op_LOC uint32 = 0xEBF2 // FORMAT_RSY2 LOAD ON CONDITION (32) 1882 op_LOCG uint32 = 0xEBE2 // FORMAT_RSY2 LOAD ON CONDITION (64) 1883 op_LOCGR uint32 = 0xB9E2 // FORMAT_RRF3 LOAD ON CONDITION (64) 1884 op_LOCR uint32 = 0xB9F2 // FORMAT_RRF3 LOAD ON CONDITION (32) 1885 op_LPD uint32 = 0xC804 // FORMAT_SSF LOAD PAIR DISJOINT (32) 1886 op_LPDBR uint32 = 0xB310 // FORMAT_RRE LOAD POSITIVE (long BFP) 1887 op_LPDFR uint32 = 0xB370 // FORMAT_RRE LOAD POSITIVE (long) 1888 op_LPDG uint32 = 0xC805 // FORMAT_SSF LOAD PAIR DISJOINT (64) 1889 op_LPDR uint32 = 0x2000 // FORMAT_RR LOAD POSITIVE (long HFP) 1890 op_LPEBR uint32 = 0xB300 // FORMAT_RRE LOAD POSITIVE (short BFP) 1891 op_LPER uint32 = 0x3000 // FORMAT_RR LOAD POSITIVE (short HFP) 1892 op_LPGFR uint32 = 0xB910 // FORMAT_RRE LOAD POSITIVE (64<-32) 1893 op_LPGR uint32 = 0xB900 // FORMAT_RRE LOAD POSITIVE (64) 1894 op_LPQ uint32 = 0xE38F // FORMAT_RXY1 LOAD PAIR FROM QUADWORD 1895 op_LPR uint32 = 0x1000 // FORMAT_RR LOAD POSITIVE (32) 1896 op_LPSW uint32 = 0x8200 // FORMAT_S LOAD PSW 1897 op_LPSWE uint32 = 0xB2B2 // FORMAT_S LOAD PSW EXTENDED 1898 op_LPTEA uint32 = 0xB9AA // FORMAT_RRF2 LOAD PAGE TABLE ENTRY ADDRESS 1899 op_LPXBR uint32 = 0xB340 // FORMAT_RRE LOAD POSITIVE (extended BFP) 1900 op_LPXR uint32 = 0xB360 // FORMAT_RRE LOAD POSITIVE (extended HFP) 1901 op_LR uint32 = 0x1800 // FORMAT_RR LOAD (32) 1902 op_LRA uint32 = 0xB100 // FORMAT_RX1 LOAD REAL ADDRESS (32) 1903 op_LRAG uint32 = 0xE303 // FORMAT_RXY1 LOAD REAL ADDRESS (64) 1904 op_LRAY uint32 = 0xE313 // FORMAT_RXY1 LOAD REAL ADDRESS (32) 1905 op_LRDR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1906 op_LRER uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1907 op_LRL uint32 = 0xC40D // FORMAT_RIL2 LOAD RELATIVE LONG (32) 1908 op_LRV uint32 = 0xE31E // FORMAT_RXY1 LOAD REVERSED (32) 1909 op_LRVG uint32 = 0xE30F // FORMAT_RXY1 LOAD REVERSED (64) 1910 op_LRVGR uint32 = 0xB90F // FORMAT_RRE LOAD REVERSED (64) 1911 op_LRVH uint32 = 0xE31F // FORMAT_RXY1 LOAD REVERSED (16) 1912 op_LRVR uint32 = 0xB91F // FORMAT_RRE LOAD REVERSED (32) 1913 op_LT uint32 = 0xE312 // FORMAT_RXY1 LOAD AND TEST (32) 1914 op_LTDBR uint32 = 0xB312 // FORMAT_RRE LOAD AND TEST (long BFP) 1915 op_LTDR uint32 = 0x2200 // FORMAT_RR LOAD AND TEST (long HFP) 1916 op_LTDTR uint32 = 0xB3D6 // FORMAT_RRE LOAD AND TEST (long DFP) 1917 op_LTEBR uint32 = 0xB302 // FORMAT_RRE LOAD AND TEST (short BFP) 1918 op_LTER uint32 = 0x3200 // FORMAT_RR LOAD AND TEST (short HFP) 1919 op_LTG uint32 = 0xE302 // FORMAT_RXY1 LOAD AND TEST (64) 1920 op_LTGF uint32 = 0xE332 // FORMAT_RXY1 LOAD AND TEST (64<-32) 1921 op_LTGFR uint32 = 0xB912 // FORMAT_RRE LOAD AND TEST (64<-32) 1922 op_LTGR uint32 = 0xB902 // FORMAT_RRE LOAD AND TEST (64) 1923 op_LTR uint32 = 0x1200 // FORMAT_RR LOAD AND TEST (32) 1924 op_LTXBR uint32 = 0xB342 // FORMAT_RRE LOAD AND TEST (extended BFP) 1925 op_LTXR uint32 = 0xB362 // FORMAT_RRE LOAD AND TEST (extended HFP) 1926 op_LTXTR uint32 = 0xB3DE // FORMAT_RRE LOAD AND TEST (extended DFP) 1927 op_LURA uint32 = 0xB24B // FORMAT_RRE LOAD USING REAL ADDRESS (32) 1928 op_LURAG uint32 = 0xB905 // FORMAT_RRE LOAD USING REAL ADDRESS (64) 1929 op_LXD uint32 = 0xED25 // FORMAT_RXE LOAD LENGTHENED (long to extended HFP) 1930 op_LXDB uint32 = 0xED05 // FORMAT_RXE LOAD LENGTHENED (long to extended BFP) 1931 op_LXDBR uint32 = 0xB305 // FORMAT_RRE LOAD LENGTHENED (long to extended BFP) 1932 op_LXDR uint32 = 0xB325 // FORMAT_RRE LOAD LENGTHENED (long to extended HFP) 1933 op_LXDTR uint32 = 0xB3DC // FORMAT_RRF4 LOAD LENGTHENED (long to extended DFP) 1934 op_LXE uint32 = 0xED26 // FORMAT_RXE LOAD LENGTHENED (short to extended HFP) 1935 op_LXEB uint32 = 0xED06 // FORMAT_RXE LOAD LENGTHENED (short to extended BFP) 1936 op_LXEBR uint32 = 0xB306 // FORMAT_RRE LOAD LENGTHENED (short to extended BFP) 1937 op_LXER uint32 = 0xB326 // FORMAT_RRE LOAD LENGTHENED (short to extended HFP) 1938 op_LXR uint32 = 0xB365 // FORMAT_RRE LOAD (extended) 1939 op_LY uint32 = 0xE358 // FORMAT_RXY1 LOAD (32) 1940 op_LZDR uint32 = 0xB375 // FORMAT_RRE LOAD ZERO (long) 1941 op_LZER uint32 = 0xB374 // FORMAT_RRE LOAD ZERO (short) 1942 op_LZXR uint32 = 0xB376 // FORMAT_RRE LOAD ZERO (extended) 1943 op_M uint32 = 0x5C00 // FORMAT_RX1 MULTIPLY (64<-32) 1944 op_MAD uint32 = 0xED3E // FORMAT_RXF MULTIPLY AND ADD (long HFP) 1945 op_MADB uint32 = 0xED1E // FORMAT_RXF MULTIPLY AND ADD (long BFP) 1946 op_MADBR uint32 = 0xB31E // FORMAT_RRD MULTIPLY AND ADD (long BFP) 1947 op_MADR uint32 = 0xB33E // FORMAT_RRD MULTIPLY AND ADD (long HFP) 1948 op_MAE uint32 = 0xED2E // FORMAT_RXF MULTIPLY AND ADD (short HFP) 1949 op_MAEB uint32 = 0xED0E // FORMAT_RXF MULTIPLY AND ADD (short BFP) 1950 op_MAEBR uint32 = 0xB30E // FORMAT_RRD MULTIPLY AND ADD (short BFP) 1951 op_MAER uint32 = 0xB32E // FORMAT_RRD MULTIPLY AND ADD (short HFP) 1952 op_MAY uint32 = 0xED3A // FORMAT_RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1953 op_MAYH uint32 = 0xED3C // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1954 op_MAYHR uint32 = 0xB33C // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1955 op_MAYL uint32 = 0xED38 // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1956 op_MAYLR uint32 = 0xB338 // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1957 op_MAYR uint32 = 0xB33A // FORMAT_RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1958 op_MC uint32 = 0xAF00 // FORMAT_SI MONITOR CALL 1959 op_MD uint32 = 0x6C00 // FORMAT_RX1 MULTIPLY (long HFP) 1960 op_MDB uint32 = 0xED1C // FORMAT_RXE MULTIPLY (long BFP) 1961 op_MDBR uint32 = 0xB31C // FORMAT_RRE MULTIPLY (long BFP) 1962 op_MDE uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1963 op_MDEB uint32 = 0xED0C // FORMAT_RXE MULTIPLY (short to long BFP) 1964 op_MDEBR uint32 = 0xB30C // FORMAT_RRE MULTIPLY (short to long BFP) 1965 op_MDER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1966 op_MDR uint32 = 0x2C00 // FORMAT_RR MULTIPLY (long HFP) 1967 op_MDTR uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1968 op_MDTRA uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1969 op_ME uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1970 op_MEE uint32 = 0xED37 // FORMAT_RXE MULTIPLY (short HFP) 1971 op_MEEB uint32 = 0xED17 // FORMAT_RXE MULTIPLY (short BFP) 1972 op_MEEBR uint32 = 0xB317 // FORMAT_RRE MULTIPLY (short BFP) 1973 op_MEER uint32 = 0xB337 // FORMAT_RRE MULTIPLY (short HFP) 1974 op_MER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1975 op_MFY uint32 = 0xE35C // FORMAT_RXY1 MULTIPLY (64<-32) 1976 op_MGHI uint32 = 0xA70D // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (64) 1977 op_MH uint32 = 0x4C00 // FORMAT_RX1 MULTIPLY HALFWORD (32) 1978 op_MHI uint32 = 0xA70C // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (32) 1979 op_MHY uint32 = 0xE37C // FORMAT_RXY1 MULTIPLY HALFWORD (32) 1980 op_ML uint32 = 0xE396 // FORMAT_RXY1 MULTIPLY LOGICAL (64<-32) 1981 op_MLG uint32 = 0xE386 // FORMAT_RXY1 MULTIPLY LOGICAL (128<-64) 1982 op_MLGR uint32 = 0xB986 // FORMAT_RRE MULTIPLY LOGICAL (128<-64) 1983 op_MLR uint32 = 0xB996 // FORMAT_RRE MULTIPLY LOGICAL (64<-32) 1984 op_MP uint32 = 0xFC00 // FORMAT_SS2 MULTIPLY DECIMAL 1985 op_MR uint32 = 0x1C00 // FORMAT_RR MULTIPLY (64<-32) 1986 op_MS uint32 = 0x7100 // FORMAT_RX1 MULTIPLY SINGLE (32) 1987 op_MSCH uint32 = 0xB232 // FORMAT_S MODIFY SUBCHANNEL 1988 op_MSD uint32 = 0xED3F // FORMAT_RXF MULTIPLY AND SUBTRACT (long HFP) 1989 op_MSDB uint32 = 0xED1F // FORMAT_RXF MULTIPLY AND SUBTRACT (long BFP) 1990 op_MSDBR uint32 = 0xB31F // FORMAT_RRD MULTIPLY AND SUBTRACT (long BFP) 1991 op_MSDR uint32 = 0xB33F // FORMAT_RRD MULTIPLY AND SUBTRACT (long HFP) 1992 op_MSE uint32 = 0xED2F // FORMAT_RXF MULTIPLY AND SUBTRACT (short HFP) 1993 op_MSEB uint32 = 0xED0F // FORMAT_RXF MULTIPLY AND SUBTRACT (short BFP) 1994 op_MSEBR uint32 = 0xB30F // FORMAT_RRD MULTIPLY AND SUBTRACT (short BFP) 1995 op_MSER uint32 = 0xB32F // FORMAT_RRD MULTIPLY AND SUBTRACT (short HFP) 1996 op_MSFI uint32 = 0xC201 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (32) 1997 op_MSG uint32 = 0xE30C // FORMAT_RXY1 MULTIPLY SINGLE (64) 1998 op_MSGF uint32 = 0xE31C // FORMAT_RXY1 MULTIPLY SINGLE (64<-32) 1999 op_MSGFI uint32 = 0xC200 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (64<-32) 2000 op_MSGFR uint32 = 0xB91C // FORMAT_RRE MULTIPLY SINGLE (64<-32) 2001 op_MSGR uint32 = 0xB90C // FORMAT_RRE MULTIPLY SINGLE (64) 2002 op_MSR uint32 = 0xB252 // FORMAT_RRE MULTIPLY SINGLE (32) 2003 op_MSTA uint32 = 0xB247 // FORMAT_RRE MODIFY STACKED STATE 2004 op_MSY uint32 = 0xE351 // FORMAT_RXY1 MULTIPLY SINGLE (32) 2005 op_MVC uint32 = 0xD200 // FORMAT_SS1 MOVE (character) 2006 op_MVCDK uint32 = 0xE50F // FORMAT_SSE MOVE WITH DESTINATION KEY 2007 op_MVCIN uint32 = 0xE800 // FORMAT_SS1 MOVE INVERSE 2008 op_MVCK uint32 = 0xD900 // FORMAT_SS4 MOVE WITH KEY 2009 op_MVCL uint32 = 0x0E00 // FORMAT_RR MOVE LONG 2010 op_MVCLE uint32 = 0xA800 // FORMAT_RS1 MOVE LONG EXTENDED 2011 op_MVCLU uint32 = 0xEB8E // FORMAT_RSY1 MOVE LONG UNICODE 2012 op_MVCOS uint32 = 0xC800 // FORMAT_SSF MOVE WITH OPTIONAL SPECIFICATIONS 2013 op_MVCP uint32 = 0xDA00 // FORMAT_SS4 MOVE TO PRIMARY 2014 op_MVCS uint32 = 0xDB00 // FORMAT_SS4 MOVE TO SECONDARY 2015 op_MVCSK uint32 = 0xE50E // FORMAT_SSE MOVE WITH SOURCE KEY 2016 op_MVGHI uint32 = 0xE548 // FORMAT_SIL MOVE (64<-16) 2017 op_MVHHI uint32 = 0xE544 // FORMAT_SIL MOVE (16<-16) 2018 op_MVHI uint32 = 0xE54C // FORMAT_SIL MOVE (32<-16) 2019 op_MVI uint32 = 0x9200 // FORMAT_SI MOVE (immediate) 2020 op_MVIY uint32 = 0xEB52 // FORMAT_SIY MOVE (immediate) 2021 op_MVN uint32 = 0xD100 // FORMAT_SS1 MOVE NUMERICS 2022 op_MVO uint32 = 0xF100 // FORMAT_SS2 MOVE WITH OFFSET 2023 op_MVPG uint32 = 0xB254 // FORMAT_RRE MOVE PAGE 2024 op_MVST uint32 = 0xB255 // FORMAT_RRE MOVE STRING 2025 op_MVZ uint32 = 0xD300 // FORMAT_SS1 MOVE ZONES 2026 op_MXBR uint32 = 0xB34C // FORMAT_RRE MULTIPLY (extended BFP) 2027 op_MXD uint32 = 0x6700 // FORMAT_RX1 MULTIPLY (long to extended HFP) 2028 op_MXDB uint32 = 0xED07 // FORMAT_RXE MULTIPLY (long to extended BFP) 2029 op_MXDBR uint32 = 0xB307 // FORMAT_RRE MULTIPLY (long to extended BFP) 2030 op_MXDR uint32 = 0x2700 // FORMAT_RR MULTIPLY (long to extended HFP) 2031 op_MXR uint32 = 0x2600 // FORMAT_RR MULTIPLY (extended HFP) 2032 op_MXTR uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2033 op_MXTRA uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2034 op_MY uint32 = 0xED3B // FORMAT_RXF MULTIPLY UNNORMALIZED (long to ext. HFP) 2035 op_MYH uint32 = 0xED3D // FORMAT_RXF MULTIPLY UNNORM. (long to ext. high HFP) 2036 op_MYHR uint32 = 0xB33D // FORMAT_RRD MULTIPLY UNNORM. (long to ext. high HFP) 2037 op_MYL uint32 = 0xED39 // FORMAT_RXF MULTIPLY UNNORM. (long to ext. low HFP) 2038 op_MYLR uint32 = 0xB339 // FORMAT_RRD MULTIPLY UNNORM. (long to ext. low HFP) 2039 op_MYR uint32 = 0xB33B // FORMAT_RRD MULTIPLY UNNORMALIZED (long to ext. HFP) 2040 op_N uint32 = 0x5400 // FORMAT_RX1 AND (32) 2041 op_NC uint32 = 0xD400 // FORMAT_SS1 AND (character) 2042 op_NG uint32 = 0xE380 // FORMAT_RXY1 AND (64) 2043 op_NGR uint32 = 0xB980 // FORMAT_RRE AND (64) 2044 op_NGRK uint32 = 0xB9E4 // FORMAT_RRF1 AND (64) 2045 op_NI uint32 = 0x9400 // FORMAT_SI AND (immediate) 2046 op_NIAI uint32 = 0xB2FA // FORMAT_IE NEXT INSTRUCTION ACCESS INTENT 2047 op_NIHF uint32 = 0xC00A // FORMAT_RIL1 AND IMMEDIATE (high) 2048 op_NIHH uint32 = 0xA504 // FORMAT_RI1 AND IMMEDIATE (high high) 2049 op_NIHL uint32 = 0xA505 // FORMAT_RI1 AND IMMEDIATE (high low) 2050 op_NILF uint32 = 0xC00B // FORMAT_RIL1 AND IMMEDIATE (low) 2051 op_NILH uint32 = 0xA506 // FORMAT_RI1 AND IMMEDIATE (low high) 2052 op_NILL uint32 = 0xA507 // FORMAT_RI1 AND IMMEDIATE (low low) 2053 op_NIY uint32 = 0xEB54 // FORMAT_SIY AND (immediate) 2054 op_NR uint32 = 0x1400 // FORMAT_RR AND (32) 2055 op_NRK uint32 = 0xB9F4 // FORMAT_RRF1 AND (32) 2056 op_NTSTG uint32 = 0xE325 // FORMAT_RXY1 NONTRANSACTIONAL STORE 2057 op_NY uint32 = 0xE354 // FORMAT_RXY1 AND (32) 2058 op_O uint32 = 0x5600 // FORMAT_RX1 OR (32) 2059 op_OC uint32 = 0xD600 // FORMAT_SS1 OR (character) 2060 op_OG uint32 = 0xE381 // FORMAT_RXY1 OR (64) 2061 op_OGR uint32 = 0xB981 // FORMAT_RRE OR (64) 2062 op_OGRK uint32 = 0xB9E6 // FORMAT_RRF1 OR (64) 2063 op_OI uint32 = 0x9600 // FORMAT_SI OR (immediate) 2064 op_OIHF uint32 = 0xC00C // FORMAT_RIL1 OR IMMEDIATE (high) 2065 op_OIHH uint32 = 0xA508 // FORMAT_RI1 OR IMMEDIATE (high high) 2066 op_OIHL uint32 = 0xA509 // FORMAT_RI1 OR IMMEDIATE (high low) 2067 op_OILF uint32 = 0xC00D // FORMAT_RIL1 OR IMMEDIATE (low) 2068 op_OILH uint32 = 0xA50A // FORMAT_RI1 OR IMMEDIATE (low high) 2069 op_OILL uint32 = 0xA50B // FORMAT_RI1 OR IMMEDIATE (low low) 2070 op_OIY uint32 = 0xEB56 // FORMAT_SIY OR (immediate) 2071 op_OR uint32 = 0x1600 // FORMAT_RR OR (32) 2072 op_ORK uint32 = 0xB9F6 // FORMAT_RRF1 OR (32) 2073 op_OY uint32 = 0xE356 // FORMAT_RXY1 OR (32) 2074 op_PACK uint32 = 0xF200 // FORMAT_SS2 PACK 2075 op_PALB uint32 = 0xB248 // FORMAT_RRE PURGE ALB 2076 op_PC uint32 = 0xB218 // FORMAT_S PROGRAM CALL 2077 op_PCC uint32 = 0xB92C // FORMAT_RRE PERFORM CRYPTOGRAPHIC COMPUTATION 2078 op_PCKMO uint32 = 0xB928 // FORMAT_RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS 2079 op_PFD uint32 = 0xE336 // FORMAT_RXY2 PREFETCH DATA 2080 op_PFDRL uint32 = 0xC602 // FORMAT_RIL3 PREFETCH DATA RELATIVE LONG 2081 op_PFMF uint32 = 0xB9AF // FORMAT_RRE PERFORM FRAME MANAGEMENT FUNCTION 2082 op_PFPO uint32 = 0x010A // FORMAT_E PERFORM FLOATING-POINT OPERATION 2083 op_PGIN uint32 = 0xB22E // FORMAT_RRE PAGE IN 2084 op_PGOUT uint32 = 0xB22F // FORMAT_RRE PAGE OUT 2085 op_PKA uint32 = 0xE900 // FORMAT_SS6 PACK ASCII 2086 op_PKU uint32 = 0xE100 // FORMAT_SS6 PACK UNICODE 2087 op_PLO uint32 = 0xEE00 // FORMAT_SS5 PERFORM LOCKED OPERATION 2088 op_POPCNT uint32 = 0xB9E1 // FORMAT_RRE POPULATION COUNT 2089 op_PPA uint32 = 0xB2E8 // FORMAT_RRF3 PERFORM PROCESSOR ASSIST 2090 op_PR uint32 = 0x0101 // FORMAT_E PROGRAM RETURN 2091 op_PT uint32 = 0xB228 // FORMAT_RRE PROGRAM TRANSFER 2092 op_PTF uint32 = 0xB9A2 // FORMAT_RRE PERFORM TOPOLOGY FUNCTION 2093 op_PTFF uint32 = 0x0104 // FORMAT_E PERFORM TIMING FACILITY FUNCTION 2094 op_PTI uint32 = 0xB99E // FORMAT_RRE PROGRAM TRANSFER WITH INSTANCE 2095 op_PTLB uint32 = 0xB20D // FORMAT_S PURGE TLB 2096 op_QADTR uint32 = 0xB3F5 // FORMAT_RRF2 QUANTIZE (long DFP) 2097 op_QAXTR uint32 = 0xB3FD // FORMAT_RRF2 QUANTIZE (extended DFP) 2098 op_RCHP uint32 = 0xB23B // FORMAT_S RESET CHANNEL PATH 2099 op_RISBG uint32 = 0xEC55 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2100 op_RISBGN uint32 = 0xEC59 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2101 op_RISBHG uint32 = 0xEC5D // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS HIGH 2102 op_RISBLG uint32 = 0xEC51 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS LOW 2103 op_RLL uint32 = 0xEB1D // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (32) 2104 op_RLLG uint32 = 0xEB1C // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (64) 2105 op_RNSBG uint32 = 0xEC54 // FORMAT_RIE6 ROTATE THEN AND SELECTED BITS 2106 op_ROSBG uint32 = 0xEC56 // FORMAT_RIE6 ROTATE THEN OR SELECTED BITS 2107 op_RP uint32 = 0xB277 // FORMAT_S RESUME PROGRAM 2108 op_RRBE uint32 = 0xB22A // FORMAT_RRE RESET REFERENCE BIT EXTENDED 2109 op_RRBM uint32 = 0xB9AE // FORMAT_RRE RESET REFERENCE BITS MULTIPLE 2110 op_RRDTR uint32 = 0xB3F7 // FORMAT_RRF2 REROUND (long DFP) 2111 op_RRXTR uint32 = 0xB3FF // FORMAT_RRF2 REROUND (extended DFP) 2112 op_RSCH uint32 = 0xB238 // FORMAT_S RESUME SUBCHANNEL 2113 op_RXSBG uint32 = 0xEC57 // FORMAT_RIE6 ROTATE THEN EXCLUSIVE OR SELECTED BITS 2114 op_S uint32 = 0x5B00 // FORMAT_RX1 SUBTRACT (32) 2115 op_SAC uint32 = 0xB219 // FORMAT_S SET ADDRESS SPACE CONTROL 2116 op_SACF uint32 = 0xB279 // FORMAT_S SET ADDRESS SPACE CONTROL FAST 2117 op_SAL uint32 = 0xB237 // FORMAT_S SET ADDRESS LIMIT 2118 op_SAM24 uint32 = 0x010C // FORMAT_E SET ADDRESSING MODE (24) 2119 op_SAM31 uint32 = 0x010D // FORMAT_E SET ADDRESSING MODE (31) 2120 op_SAM64 uint32 = 0x010E // FORMAT_E SET ADDRESSING MODE (64) 2121 op_SAR uint32 = 0xB24E // FORMAT_RRE SET ACCESS 2122 op_SCHM uint32 = 0xB23C // FORMAT_S SET CHANNEL MONITOR 2123 op_SCK uint32 = 0xB204 // FORMAT_S SET CLOCK 2124 op_SCKC uint32 = 0xB206 // FORMAT_S SET CLOCK COMPARATOR 2125 op_SCKPF uint32 = 0x0107 // FORMAT_E SET CLOCK PROGRAMMABLE FIELD 2126 op_SD uint32 = 0x6B00 // FORMAT_RX1 SUBTRACT NORMALIZED (long HFP) 2127 op_SDB uint32 = 0xED1B // FORMAT_RXE SUBTRACT (long BFP) 2128 op_SDBR uint32 = 0xB31B // FORMAT_RRE SUBTRACT (long BFP) 2129 op_SDR uint32 = 0x2B00 // FORMAT_RR SUBTRACT NORMALIZED (long HFP) 2130 op_SDTR uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2131 op_SDTRA uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2132 op_SE uint32 = 0x7B00 // FORMAT_RX1 SUBTRACT NORMALIZED (short HFP) 2133 op_SEB uint32 = 0xED0B // FORMAT_RXE SUBTRACT (short BFP) 2134 op_SEBR uint32 = 0xB30B // FORMAT_RRE SUBTRACT (short BFP) 2135 op_SER uint32 = 0x3B00 // FORMAT_RR SUBTRACT NORMALIZED (short HFP) 2136 op_SFASR uint32 = 0xB385 // FORMAT_RRE SET FPC AND SIGNAL 2137 op_SFPC uint32 = 0xB384 // FORMAT_RRE SET FPC 2138 op_SG uint32 = 0xE309 // FORMAT_RXY1 SUBTRACT (64) 2139 op_SGF uint32 = 0xE319 // FORMAT_RXY1 SUBTRACT (64<-32) 2140 op_SGFR uint32 = 0xB919 // FORMAT_RRE SUBTRACT (64<-32) 2141 op_SGR uint32 = 0xB909 // FORMAT_RRE SUBTRACT (64) 2142 op_SGRK uint32 = 0xB9E9 // FORMAT_RRF1 SUBTRACT (64) 2143 op_SH uint32 = 0x4B00 // FORMAT_RX1 SUBTRACT HALFWORD 2144 op_SHHHR uint32 = 0xB9C9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2145 op_SHHLR uint32 = 0xB9D9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2146 op_SHY uint32 = 0xE37B // FORMAT_RXY1 SUBTRACT HALFWORD 2147 op_SIGP uint32 = 0xAE00 // FORMAT_RS1 SIGNAL PROCESSOR 2148 op_SL uint32 = 0x5F00 // FORMAT_RX1 SUBTRACT LOGICAL (32) 2149 op_SLA uint32 = 0x8B00 // FORMAT_RS1 SHIFT LEFT SINGLE (32) 2150 op_SLAG uint32 = 0xEB0B // FORMAT_RSY1 SHIFT LEFT SINGLE (64) 2151 op_SLAK uint32 = 0xEBDD // FORMAT_RSY1 SHIFT LEFT SINGLE (32) 2152 op_SLB uint32 = 0xE399 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (32) 2153 op_SLBG uint32 = 0xE389 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (64) 2154 op_SLBGR uint32 = 0xB989 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (64) 2155 op_SLBR uint32 = 0xB999 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (32) 2156 op_SLDA uint32 = 0x8F00 // FORMAT_RS1 SHIFT LEFT DOUBLE 2157 op_SLDL uint32 = 0x8D00 // FORMAT_RS1 SHIFT LEFT DOUBLE LOGICAL 2158 op_SLDT uint32 = 0xED40 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (long DFP) 2159 op_SLFI uint32 = 0xC205 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (32) 2160 op_SLG uint32 = 0xE30B // FORMAT_RXY1 SUBTRACT LOGICAL (64) 2161 op_SLGF uint32 = 0xE31B // FORMAT_RXY1 SUBTRACT LOGICAL (64<-32) 2162 op_SLGFI uint32 = 0xC204 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (64<-32) 2163 op_SLGFR uint32 = 0xB91B // FORMAT_RRE SUBTRACT LOGICAL (64<-32) 2164 op_SLGR uint32 = 0xB90B // FORMAT_RRE SUBTRACT LOGICAL (64) 2165 op_SLGRK uint32 = 0xB9EB // FORMAT_RRF1 SUBTRACT LOGICAL (64) 2166 op_SLHHHR uint32 = 0xB9CB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2167 op_SLHHLR uint32 = 0xB9DB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2168 op_SLL uint32 = 0x8900 // FORMAT_RS1 SHIFT LEFT SINGLE LOGICAL (32) 2169 op_SLLG uint32 = 0xEB0D // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (64) 2170 op_SLLK uint32 = 0xEBDF // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (32) 2171 op_SLR uint32 = 0x1F00 // FORMAT_RR SUBTRACT LOGICAL (32) 2172 op_SLRK uint32 = 0xB9FB // FORMAT_RRF1 SUBTRACT LOGICAL (32) 2173 op_SLXT uint32 = 0xED48 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (extended DFP) 2174 op_SLY uint32 = 0xE35F // FORMAT_RXY1 SUBTRACT LOGICAL (32) 2175 op_SP uint32 = 0xFB00 // FORMAT_SS2 SUBTRACT DECIMAL 2176 op_SPKA uint32 = 0xB20A // FORMAT_S SET PSW KEY FROM ADDRESS 2177 op_SPM uint32 = 0x0400 // FORMAT_RR SET PROGRAM MASK 2178 op_SPT uint32 = 0xB208 // FORMAT_S SET CPU TIMER 2179 op_SPX uint32 = 0xB210 // FORMAT_S SET PREFIX 2180 op_SQD uint32 = 0xED35 // FORMAT_RXE SQUARE ROOT (long HFP) 2181 op_SQDB uint32 = 0xED15 // FORMAT_RXE SQUARE ROOT (long BFP) 2182 op_SQDBR uint32 = 0xB315 // FORMAT_RRE SQUARE ROOT (long BFP) 2183 op_SQDR uint32 = 0xB244 // FORMAT_RRE SQUARE ROOT (long HFP) 2184 op_SQE uint32 = 0xED34 // FORMAT_RXE SQUARE ROOT (short HFP) 2185 op_SQEB uint32 = 0xED14 // FORMAT_RXE SQUARE ROOT (short BFP) 2186 op_SQEBR uint32 = 0xB314 // FORMAT_RRE SQUARE ROOT (short BFP) 2187 op_SQER uint32 = 0xB245 // FORMAT_RRE SQUARE ROOT (short HFP) 2188 op_SQXBR uint32 = 0xB316 // FORMAT_RRE SQUARE ROOT (extended BFP) 2189 op_SQXR uint32 = 0xB336 // FORMAT_RRE SQUARE ROOT (extended HFP) 2190 op_SR uint32 = 0x1B00 // FORMAT_RR SUBTRACT (32) 2191 op_SRA uint32 = 0x8A00 // FORMAT_RS1 SHIFT RIGHT SINGLE (32) 2192 op_SRAG uint32 = 0xEB0A // FORMAT_RSY1 SHIFT RIGHT SINGLE (64) 2193 op_SRAK uint32 = 0xEBDC // FORMAT_RSY1 SHIFT RIGHT SINGLE (32) 2194 op_SRDA uint32 = 0x8E00 // FORMAT_RS1 SHIFT RIGHT DOUBLE 2195 op_SRDL uint32 = 0x8C00 // FORMAT_RS1 SHIFT RIGHT DOUBLE LOGICAL 2196 op_SRDT uint32 = 0xED41 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (long DFP) 2197 op_SRK uint32 = 0xB9F9 // FORMAT_RRF1 SUBTRACT (32) 2198 op_SRL uint32 = 0x8800 // FORMAT_RS1 SHIFT RIGHT SINGLE LOGICAL (32) 2199 op_SRLG uint32 = 0xEB0C // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (64) 2200 op_SRLK uint32 = 0xEBDE // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (32) 2201 op_SRNM uint32 = 0xB299 // FORMAT_S SET BFP ROUNDING MODE (2 bit) 2202 op_SRNMB uint32 = 0xB2B8 // FORMAT_S SET BFP ROUNDING MODE (3 bit) 2203 op_SRNMT uint32 = 0xB2B9 // FORMAT_S SET DFP ROUNDING MODE 2204 op_SRP uint32 = 0xF000 // FORMAT_SS3 SHIFT AND ROUND DECIMAL 2205 op_SRST uint32 = 0xB25E // FORMAT_RRE SEARCH STRING 2206 op_SRSTU uint32 = 0xB9BE // FORMAT_RRE SEARCH STRING UNICODE 2207 op_SRXT uint32 = 0xED49 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (extended DFP) 2208 op_SSAIR uint32 = 0xB99F // FORMAT_RRE SET SECONDARY ASN WITH INSTANCE 2209 op_SSAR uint32 = 0xB225 // FORMAT_RRE SET SECONDARY ASN 2210 op_SSCH uint32 = 0xB233 // FORMAT_S START SUBCHANNEL 2211 op_SSKE uint32 = 0xB22B // FORMAT_RRF3 SET STORAGE KEY EXTENDED 2212 op_SSM uint32 = 0x8000 // FORMAT_S SET SYSTEM MASK 2213 op_ST uint32 = 0x5000 // FORMAT_RX1 STORE (32) 2214 op_STAM uint32 = 0x9B00 // FORMAT_RS1 STORE ACCESS MULTIPLE 2215 op_STAMY uint32 = 0xEB9B // FORMAT_RSY1 STORE ACCESS MULTIPLE 2216 op_STAP uint32 = 0xB212 // FORMAT_S STORE CPU ADDRESS 2217 op_STC uint32 = 0x4200 // FORMAT_RX1 STORE CHARACTER 2218 op_STCH uint32 = 0xE3C3 // FORMAT_RXY1 STORE CHARACTER HIGH (8) 2219 op_STCK uint32 = 0xB205 // FORMAT_S STORE CLOCK 2220 op_STCKC uint32 = 0xB207 // FORMAT_S STORE CLOCK COMPARATOR 2221 op_STCKE uint32 = 0xB278 // FORMAT_S STORE CLOCK EXTENDED 2222 op_STCKF uint32 = 0xB27C // FORMAT_S STORE CLOCK FAST 2223 op_STCM uint32 = 0xBE00 // FORMAT_RS2 STORE CHARACTERS UNDER MASK (low) 2224 op_STCMH uint32 = 0xEB2C // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (high) 2225 op_STCMY uint32 = 0xEB2D // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (low) 2226 op_STCPS uint32 = 0xB23A // FORMAT_S STORE CHANNEL PATH STATUS 2227 op_STCRW uint32 = 0xB239 // FORMAT_S STORE CHANNEL REPORT WORD 2228 op_STCTG uint32 = 0xEB25 // FORMAT_RSY1 STORE CONTROL (64) 2229 op_STCTL uint32 = 0xB600 // FORMAT_RS1 STORE CONTROL (32) 2230 op_STCY uint32 = 0xE372 // FORMAT_RXY1 STORE CHARACTER 2231 op_STD uint32 = 0x6000 // FORMAT_RX1 STORE (long) 2232 op_STDY uint32 = 0xED67 // FORMAT_RXY1 STORE (long) 2233 op_STE uint32 = 0x7000 // FORMAT_RX1 STORE (short) 2234 op_STEY uint32 = 0xED66 // FORMAT_RXY1 STORE (short) 2235 op_STFH uint32 = 0xE3CB // FORMAT_RXY1 STORE HIGH (32) 2236 op_STFL uint32 = 0xB2B1 // FORMAT_S STORE FACILITY LIST 2237 op_STFLE uint32 = 0xB2B0 // FORMAT_S STORE FACILITY LIST EXTENDED 2238 op_STFPC uint32 = 0xB29C // FORMAT_S STORE FPC 2239 op_STG uint32 = 0xE324 // FORMAT_RXY1 STORE (64) 2240 op_STGRL uint32 = 0xC40B // FORMAT_RIL2 STORE RELATIVE LONG (64) 2241 op_STH uint32 = 0x4000 // FORMAT_RX1 STORE HALFWORD 2242 op_STHH uint32 = 0xE3C7 // FORMAT_RXY1 STORE HALFWORD HIGH (16) 2243 op_STHRL uint32 = 0xC407 // FORMAT_RIL2 STORE HALFWORD RELATIVE LONG 2244 op_STHY uint32 = 0xE370 // FORMAT_RXY1 STORE HALFWORD 2245 op_STIDP uint32 = 0xB202 // FORMAT_S STORE CPU ID 2246 op_STM uint32 = 0x9000 // FORMAT_RS1 STORE MULTIPLE (32) 2247 op_STMG uint32 = 0xEB24 // FORMAT_RSY1 STORE MULTIPLE (64) 2248 op_STMH uint32 = 0xEB26 // FORMAT_RSY1 STORE MULTIPLE HIGH 2249 op_STMY uint32 = 0xEB90 // FORMAT_RSY1 STORE MULTIPLE (32) 2250 op_STNSM uint32 = 0xAC00 // FORMAT_SI STORE THEN AND SYSTEM MASK 2251 op_STOC uint32 = 0xEBF3 // FORMAT_RSY2 STORE ON CONDITION (32) 2252 op_STOCG uint32 = 0xEBE3 // FORMAT_RSY2 STORE ON CONDITION (64) 2253 op_STOSM uint32 = 0xAD00 // FORMAT_SI STORE THEN OR SYSTEM MASK 2254 op_STPQ uint32 = 0xE38E // FORMAT_RXY1 STORE PAIR TO QUADWORD 2255 op_STPT uint32 = 0xB209 // FORMAT_S STORE CPU TIMER 2256 op_STPX uint32 = 0xB211 // FORMAT_S STORE PREFIX 2257 op_STRAG uint32 = 0xE502 // FORMAT_SSE STORE REAL ADDRESS 2258 op_STRL uint32 = 0xC40F // FORMAT_RIL2 STORE RELATIVE LONG (32) 2259 op_STRV uint32 = 0xE33E // FORMAT_RXY1 STORE REVERSED (32) 2260 op_STRVG uint32 = 0xE32F // FORMAT_RXY1 STORE REVERSED (64) 2261 op_STRVH uint32 = 0xE33F // FORMAT_RXY1 STORE REVERSED (16) 2262 op_STSCH uint32 = 0xB234 // FORMAT_S STORE SUBCHANNEL 2263 op_STSI uint32 = 0xB27D // FORMAT_S STORE SYSTEM INFORMATION 2264 op_STURA uint32 = 0xB246 // FORMAT_RRE STORE USING REAL ADDRESS (32) 2265 op_STURG uint32 = 0xB925 // FORMAT_RRE STORE USING REAL ADDRESS (64) 2266 op_STY uint32 = 0xE350 // FORMAT_RXY1 STORE (32) 2267 op_SU uint32 = 0x7F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (short HFP) 2268 op_SUR uint32 = 0x3F00 // FORMAT_RR SUBTRACT UNNORMALIZED (short HFP) 2269 op_SVC uint32 = 0x0A00 // FORMAT_I SUPERVISOR CALL 2270 op_SW uint32 = 0x6F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (long HFP) 2271 op_SWR uint32 = 0x2F00 // FORMAT_RR SUBTRACT UNNORMALIZED (long HFP) 2272 op_SXBR uint32 = 0xB34B // FORMAT_RRE SUBTRACT (extended BFP) 2273 op_SXR uint32 = 0x3700 // FORMAT_RR SUBTRACT NORMALIZED (extended HFP) 2274 op_SXTR uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2275 op_SXTRA uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2276 op_SY uint32 = 0xE35B // FORMAT_RXY1 SUBTRACT (32) 2277 op_TABORT uint32 = 0xB2FC // FORMAT_S TRANSACTION ABORT 2278 op_TAM uint32 = 0x010B // FORMAT_E TEST ADDRESSING MODE 2279 op_TAR uint32 = 0xB24C // FORMAT_RRE TEST ACCESS 2280 op_TB uint32 = 0xB22C // FORMAT_RRE TEST BLOCK 2281 op_TBDR uint32 = 0xB351 // FORMAT_RRF5 CONVERT HFP TO BFP (long) 2282 op_TBEDR uint32 = 0xB350 // FORMAT_RRF5 CONVERT HFP TO BFP (long to short) 2283 op_TBEGIN uint32 = 0xE560 // FORMAT_SIL TRANSACTION BEGIN 2284 op_TBEGINC uint32 = 0xE561 // FORMAT_SIL TRANSACTION BEGIN 2285 op_TCDB uint32 = 0xED11 // FORMAT_RXE TEST DATA CLASS (long BFP) 2286 op_TCEB uint32 = 0xED10 // FORMAT_RXE TEST DATA CLASS (short BFP) 2287 op_TCXB uint32 = 0xED12 // FORMAT_RXE TEST DATA CLASS (extended BFP) 2288 op_TDCDT uint32 = 0xED54 // FORMAT_RXE TEST DATA CLASS (long DFP) 2289 op_TDCET uint32 = 0xED50 // FORMAT_RXE TEST DATA CLASS (short DFP) 2290 op_TDCXT uint32 = 0xED58 // FORMAT_RXE TEST DATA CLASS (extended DFP) 2291 op_TDGDT uint32 = 0xED55 // FORMAT_RXE TEST DATA GROUP (long DFP) 2292 op_TDGET uint32 = 0xED51 // FORMAT_RXE TEST DATA GROUP (short DFP) 2293 op_TDGXT uint32 = 0xED59 // FORMAT_RXE TEST DATA GROUP (extended DFP) 2294 op_TEND uint32 = 0xB2F8 // FORMAT_S TRANSACTION END 2295 op_THDER uint32 = 0xB358 // FORMAT_RRE CONVERT BFP TO HFP (short to long) 2296 op_THDR uint32 = 0xB359 // FORMAT_RRE CONVERT BFP TO HFP (long) 2297 op_TM uint32 = 0x9100 // FORMAT_SI TEST UNDER MASK 2298 op_TMH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK HIGH 2299 op_TMHH uint32 = 0xA702 // FORMAT_RI1 TEST UNDER MASK (high high) 2300 op_TMHL uint32 = 0xA703 // FORMAT_RI1 TEST UNDER MASK (high low) 2301 op_TML uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK LOW 2302 op_TMLH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK (low high) 2303 op_TMLL uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK (low low) 2304 op_TMY uint32 = 0xEB51 // FORMAT_SIY TEST UNDER MASK 2305 op_TP uint32 = 0xEBC0 // FORMAT_RSL TEST DECIMAL 2306 op_TPI uint32 = 0xB236 // FORMAT_S TEST PENDING INTERRUPTION 2307 op_TPROT uint32 = 0xE501 // FORMAT_SSE TEST PROTECTION 2308 op_TR uint32 = 0xDC00 // FORMAT_SS1 TRANSLATE 2309 op_TRACE uint32 = 0x9900 // FORMAT_RS1 TRACE (32) 2310 op_TRACG uint32 = 0xEB0F // FORMAT_RSY1 TRACE (64) 2311 op_TRAP2 uint32 = 0x01FF // FORMAT_E TRAP 2312 op_TRAP4 uint32 = 0xB2FF // FORMAT_S TRAP 2313 op_TRE uint32 = 0xB2A5 // FORMAT_RRE TRANSLATE EXTENDED 2314 op_TROO uint32 = 0xB993 // FORMAT_RRF3 TRANSLATE ONE TO ONE 2315 op_TROT uint32 = 0xB992 // FORMAT_RRF3 TRANSLATE ONE TO TWO 2316 op_TRT uint32 = 0xDD00 // FORMAT_SS1 TRANSLATE AND TEST 2317 op_TRTE uint32 = 0xB9BF // FORMAT_RRF3 TRANSLATE AND TEST EXTENDED 2318 op_TRTO uint32 = 0xB991 // FORMAT_RRF3 TRANSLATE TWO TO ONE 2319 op_TRTR uint32 = 0xD000 // FORMAT_SS1 TRANSLATE AND TEST REVERSE 2320 op_TRTRE uint32 = 0xB9BD // FORMAT_RRF3 TRANSLATE AND TEST REVERSE EXTENDED 2321 op_TRTT uint32 = 0xB990 // FORMAT_RRF3 TRANSLATE TWO TO TWO 2322 op_TS uint32 = 0x9300 // FORMAT_S TEST AND SET 2323 op_TSCH uint32 = 0xB235 // FORMAT_S TEST SUBCHANNEL 2324 op_UNPK uint32 = 0xF300 // FORMAT_SS2 UNPACK 2325 op_UNPKA uint32 = 0xEA00 // FORMAT_SS1 UNPACK ASCII 2326 op_UNPKU uint32 = 0xE200 // FORMAT_SS1 UNPACK UNICODE 2327 op_UPT uint32 = 0x0102 // FORMAT_E UPDATE TREE 2328 op_X uint32 = 0x5700 // FORMAT_RX1 EXCLUSIVE OR (32) 2329 op_XC uint32 = 0xD700 // FORMAT_SS1 EXCLUSIVE OR (character) 2330 op_XG uint32 = 0xE382 // FORMAT_RXY1 EXCLUSIVE OR (64) 2331 op_XGR uint32 = 0xB982 // FORMAT_RRE EXCLUSIVE OR (64) 2332 op_XGRK uint32 = 0xB9E7 // FORMAT_RRF1 EXCLUSIVE OR (64) 2333 op_XI uint32 = 0x9700 // FORMAT_SI EXCLUSIVE OR (immediate) 2334 op_XIHF uint32 = 0xC006 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (high) 2335 op_XILF uint32 = 0xC007 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (low) 2336 op_XIY uint32 = 0xEB57 // FORMAT_SIY EXCLUSIVE OR (immediate) 2337 op_XR uint32 = 0x1700 // FORMAT_RR EXCLUSIVE OR (32) 2338 op_XRK uint32 = 0xB9F7 // FORMAT_RRF1 EXCLUSIVE OR (32) 2339 op_XSCH uint32 = 0xB276 // FORMAT_S CANCEL SUBCHANNEL 2340 op_XY uint32 = 0xE357 // FORMAT_RXY1 EXCLUSIVE OR (32) 2341 op_ZAP uint32 = 0xF800 // FORMAT_SS2 ZERO AND ADD 2342 2343 // added in z13 2344 op_CXPT uint32 = 0xEDAF // RSL-b CONVERT FROM PACKED (to extended DFP) 2345 op_CDPT uint32 = 0xEDAE // RSL-b CONVERT FROM PACKED (to long DFP) 2346 op_CPXT uint32 = 0xEDAD // RSL-b CONVERT TO PACKED (from extended DFP) 2347 op_CPDT uint32 = 0xEDAC // RSL-b CONVERT TO PACKED (from long DFP) 2348 op_LZRF uint32 = 0xE33B // RXY-a LOAD AND ZERO RIGHTMOST BYTE (32) 2349 op_LZRG uint32 = 0xE32A // RXY-a LOAD AND ZERO RIGHTMOST BYTE (64) 2350 op_LCCB uint32 = 0xE727 // RXE LOAD COUNT TO BLOCK BOUNDARY 2351 op_LOCHHI uint32 = 0xEC4E // RIE-g LOAD HALFWORD HIGH IMMEDIATE ON CONDITION (32←16) 2352 op_LOCHI uint32 = 0xEC42 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (32←16) 2353 op_LOCGHI uint32 = 0xEC46 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (64←16) 2354 op_LOCFH uint32 = 0xEBE0 // RSY-b LOAD HIGH ON CONDITION (32) 2355 op_LOCFHR uint32 = 0xB9E0 // RRF-c LOAD HIGH ON CONDITION (32) 2356 op_LLZRGF uint32 = 0xE33A // RXY-a LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64←32) 2357 op_STOCFH uint32 = 0xEBE1 // RSY-b STORE HIGH ON CONDITION 2358 op_VA uint32 = 0xE7F3 // VRR-c VECTOR ADD 2359 op_VACC uint32 = 0xE7F1 // VRR-c VECTOR ADD COMPUTE CARRY 2360 op_VAC uint32 = 0xE7BB // VRR-d VECTOR ADD WITH CARRY 2361 op_VACCC uint32 = 0xE7B9 // VRR-d VECTOR ADD WITH CARRY COMPUTE CARRY 2362 op_VN uint32 = 0xE768 // VRR-c VECTOR AND 2363 op_VNC uint32 = 0xE769 // VRR-c VECTOR AND WITH COMPLEMENT 2364 op_VAVG uint32 = 0xE7F2 // VRR-c VECTOR AVERAGE 2365 op_VAVGL uint32 = 0xE7F0 // VRR-c VECTOR AVERAGE LOGICAL 2366 op_VCKSM uint32 = 0xE766 // VRR-c VECTOR CHECKSUM 2367 op_VCEQ uint32 = 0xE7F8 // VRR-b VECTOR COMPARE EQUAL 2368 op_VCH uint32 = 0xE7FB // VRR-b VECTOR COMPARE HIGH 2369 op_VCHL uint32 = 0xE7F9 // VRR-b VECTOR COMPARE HIGH LOGICAL 2370 op_VCLZ uint32 = 0xE753 // VRR-a VECTOR COUNT LEADING ZEROS 2371 op_VCTZ uint32 = 0xE752 // VRR-a VECTOR COUNT TRAILING ZEROS 2372 op_VEC uint32 = 0xE7DB // VRR-a VECTOR ELEMENT COMPARE 2373 op_VECL uint32 = 0xE7D9 // VRR-a VECTOR ELEMENT COMPARE LOGICAL 2374 op_VERIM uint32 = 0xE772 // VRI-d VECTOR ELEMENT ROTATE AND INSERT UNDER MASK 2375 op_VERLL uint32 = 0xE733 // VRS-a VECTOR ELEMENT ROTATE LEFT LOGICAL 2376 op_VERLLV uint32 = 0xE773 // VRR-c VECTOR ELEMENT ROTATE LEFT LOGICAL 2377 op_VESLV uint32 = 0xE770 // VRR-c VECTOR ELEMENT SHIFT LEFT 2378 op_VESL uint32 = 0xE730 // VRS-a VECTOR ELEMENT SHIFT LEFT 2379 op_VESRA uint32 = 0xE73A // VRS-a VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2380 op_VESRAV uint32 = 0xE77A // VRR-c VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2381 op_VESRL uint32 = 0xE738 // VRS-a VECTOR ELEMENT SHIFT RIGHT LOGICAL 2382 op_VESRLV uint32 = 0xE778 // VRR-c VECTOR ELEMENT SHIFT RIGHT LOGICAL 2383 op_VX uint32 = 0xE76D // VRR-c VECTOR EXCLUSIVE OR 2384 op_VFAE uint32 = 0xE782 // VRR-b VECTOR FIND ANY ELEMENT EQUAL 2385 op_VFEE uint32 = 0xE780 // VRR-b VECTOR FIND ELEMENT EQUAL 2386 op_VFENE uint32 = 0xE781 // VRR-b VECTOR FIND ELEMENT NOT EQUAL 2387 op_VFA uint32 = 0xE7E3 // VRR-c VECTOR FP ADD 2388 op_WFK uint32 = 0xE7CA // VRR-a VECTOR FP COMPARE AND SIGNAL SCALAR 2389 op_VFCE uint32 = 0xE7E8 // VRR-c VECTOR FP COMPARE EQUAL 2390 op_VFCH uint32 = 0xE7EB // VRR-c VECTOR FP COMPARE HIGH 2391 op_VFCHE uint32 = 0xE7EA // VRR-c VECTOR FP COMPARE HIGH OR EQUAL 2392 op_WFC uint32 = 0xE7CB // VRR-a VECTOR FP COMPARE SCALAR 2393 op_VCDG uint32 = 0xE7C3 // VRR-a VECTOR FP CONVERT FROM FIXED 64-BIT 2394 op_VCDLG uint32 = 0xE7C1 // VRR-a VECTOR FP CONVERT FROM LOGICAL 64-BIT 2395 op_VCGD uint32 = 0xE7C2 // VRR-a VECTOR FP CONVERT TO FIXED 64-BIT 2396 op_VCLGD uint32 = 0xE7C0 // VRR-a VECTOR FP CONVERT TO LOGICAL 64-BIT 2397 op_VFD uint32 = 0xE7E5 // VRR-c VECTOR FP DIVIDE 2398 op_VLDE uint32 = 0xE7C4 // VRR-a VECTOR FP LOAD LENGTHENED 2399 op_VLED uint32 = 0xE7C5 // VRR-a VECTOR FP LOAD ROUNDED 2400 op_VFM uint32 = 0xE7E7 // VRR-c VECTOR FP MULTIPLY 2401 op_VFMA uint32 = 0xE78F // VRR-e VECTOR FP MULTIPLY AND ADD 2402 op_VFMS uint32 = 0xE78E // VRR-e VECTOR FP MULTIPLY AND SUBTRACT 2403 op_VFPSO uint32 = 0xE7CC // VRR-a VECTOR FP PERFORM SIGN OPERATION 2404 op_VFSQ uint32 = 0xE7CE // VRR-a VECTOR FP SQUARE ROOT 2405 op_VFS uint32 = 0xE7E2 // VRR-c VECTOR FP SUBTRACT 2406 op_VFTCI uint32 = 0xE74A // VRI-e VECTOR FP TEST DATA CLASS IMMEDIATE 2407 op_VGFM uint32 = 0xE7B4 // VRR-c VECTOR GALOIS FIELD MULTIPLY SUM 2408 op_VGFMA uint32 = 0xE7BC // VRR-d VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE 2409 op_VGEF uint32 = 0xE713 // VRV VECTOR GATHER ELEMENT (32) 2410 op_VGEG uint32 = 0xE712 // VRV VECTOR GATHER ELEMENT (64) 2411 op_VGBM uint32 = 0xE744 // VRI-a VECTOR GENERATE BYTE MASK 2412 op_VGM uint32 = 0xE746 // VRI-b VECTOR GENERATE MASK 2413 op_VISTR uint32 = 0xE75C // VRR-a VECTOR ISOLATE STRING 2414 op_VL uint32 = 0xE706 // VRX VECTOR LOAD 2415 op_VLR uint32 = 0xE756 // VRR-a VECTOR LOAD 2416 op_VLREP uint32 = 0xE705 // VRX VECTOR LOAD AND REPLICATE 2417 op_VLC uint32 = 0xE7DE // VRR-a VECTOR LOAD COMPLEMENT 2418 op_VLEH uint32 = 0xE701 // VRX VECTOR LOAD ELEMENT (16) 2419 op_VLEF uint32 = 0xE703 // VRX VECTOR LOAD ELEMENT (32) 2420 op_VLEG uint32 = 0xE702 // VRX VECTOR LOAD ELEMENT (64) 2421 op_VLEB uint32 = 0xE700 // VRX VECTOR LOAD ELEMENT (8) 2422 op_VLEIH uint32 = 0xE741 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (16) 2423 op_VLEIF uint32 = 0xE743 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (32) 2424 op_VLEIG uint32 = 0xE742 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (64) 2425 op_VLEIB uint32 = 0xE740 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (8) 2426 op_VFI uint32 = 0xE7C7 // VRR-a VECTOR LOAD FP INTEGER 2427 op_VLGV uint32 = 0xE721 // VRS-c VECTOR LOAD GR FROM VR ELEMENT 2428 op_VLLEZ uint32 = 0xE704 // VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO 2429 op_VLM uint32 = 0xE736 // VRS-a VECTOR LOAD MULTIPLE 2430 op_VLP uint32 = 0xE7DF // VRR-a VECTOR LOAD POSITIVE 2431 op_VLBB uint32 = 0xE707 // VRX VECTOR LOAD TO BLOCK BOUNDARY 2432 op_VLVG uint32 = 0xE722 // VRS-b VECTOR LOAD VR ELEMENT FROM GR 2433 op_VLVGP uint32 = 0xE762 // VRR-f VECTOR LOAD VR FROM GRS DISJOINT 2434 op_VLL uint32 = 0xE737 // VRS-b VECTOR LOAD WITH LENGTH 2435 op_VMX uint32 = 0xE7FF // VRR-c VECTOR MAXIMUM 2436 op_VMXL uint32 = 0xE7FD // VRR-c VECTOR MAXIMUM LOGICAL 2437 op_VMRH uint32 = 0xE761 // VRR-c VECTOR MERGE HIGH 2438 op_VMRL uint32 = 0xE760 // VRR-c VECTOR MERGE LOW 2439 op_VMN uint32 = 0xE7FE // VRR-c VECTOR MINIMUM 2440 op_VMNL uint32 = 0xE7FC // VRR-c VECTOR MINIMUM LOGICAL 2441 op_VMAE uint32 = 0xE7AE // VRR-d VECTOR MULTIPLY AND ADD EVEN 2442 op_VMAH uint32 = 0xE7AB // VRR-d VECTOR MULTIPLY AND ADD HIGH 2443 op_VMALE uint32 = 0xE7AC // VRR-d VECTOR MULTIPLY AND ADD LOGICAL EVEN 2444 op_VMALH uint32 = 0xE7A9 // VRR-d VECTOR MULTIPLY AND ADD LOGICAL HIGH 2445 op_VMALO uint32 = 0xE7AD // VRR-d VECTOR MULTIPLY AND ADD LOGICAL ODD 2446 op_VMAL uint32 = 0xE7AA // VRR-d VECTOR MULTIPLY AND ADD LOW 2447 op_VMAO uint32 = 0xE7AF // VRR-d VECTOR MULTIPLY AND ADD ODD 2448 op_VME uint32 = 0xE7A6 // VRR-c VECTOR MULTIPLY EVEN 2449 op_VMH uint32 = 0xE7A3 // VRR-c VECTOR MULTIPLY HIGH 2450 op_VMLE uint32 = 0xE7A4 // VRR-c VECTOR MULTIPLY EVEN LOGICAL 2451 op_VMLH uint32 = 0xE7A1 // VRR-c VECTOR MULTIPLY HIGH LOGICAL 2452 op_VMLO uint32 = 0xE7A5 // VRR-c VECTOR MULTIPLY ODD LOGICAL 2453 op_VML uint32 = 0xE7A2 // VRR-c VECTOR MULTIPLY LOW 2454 op_VMO uint32 = 0xE7A7 // VRR-c VECTOR MULTIPLY ODD 2455 op_VNO uint32 = 0xE76B // VRR-c VECTOR NOR 2456 op_VO uint32 = 0xE76A // VRR-c VECTOR OR 2457 op_VPK uint32 = 0xE794 // VRR-c VECTOR PACK 2458 op_VPKLS uint32 = 0xE795 // VRR-b VECTOR PACK LOGICAL SATURATE 2459 op_VPKS uint32 = 0xE797 // VRR-b VECTOR PACK SATURATE 2460 op_VPERM uint32 = 0xE78C // VRR-e VECTOR PERMUTE 2461 op_VPDI uint32 = 0xE784 // VRR-c VECTOR PERMUTE DOUBLEWORD IMMEDIATE 2462 op_VPOPCT uint32 = 0xE750 // VRR-a VECTOR POPULATION COUNT 2463 op_VREP uint32 = 0xE74D // VRI-c VECTOR REPLICATE 2464 op_VREPI uint32 = 0xE745 // VRI-a VECTOR REPLICATE IMMEDIATE 2465 op_VSCEF uint32 = 0xE71B // VRV VECTOR SCATTER ELEMENT (32) 2466 op_VSCEG uint32 = 0xE71A // VRV VECTOR SCATTER ELEMENT (64) 2467 op_VSEL uint32 = 0xE78D // VRR-e VECTOR SELECT 2468 op_VSL uint32 = 0xE774 // VRR-c VECTOR SHIFT LEFT 2469 op_VSLB uint32 = 0xE775 // VRR-c VECTOR SHIFT LEFT BY BYTE 2470 op_VSLDB uint32 = 0xE777 // VRI-d VECTOR SHIFT LEFT DOUBLE BY BYTE 2471 op_VSRA uint32 = 0xE77E // VRR-c VECTOR SHIFT RIGHT ARITHMETIC 2472 op_VSRAB uint32 = 0xE77F // VRR-c VECTOR SHIFT RIGHT ARITHMETIC BY BYTE 2473 op_VSRL uint32 = 0xE77C // VRR-c VECTOR SHIFT RIGHT LOGICAL 2474 op_VSRLB uint32 = 0xE77D // VRR-c VECTOR SHIFT RIGHT LOGICAL BY BYTE 2475 op_VSEG uint32 = 0xE75F // VRR-a VECTOR SIGN EXTEND TO DOUBLEWORD 2476 op_VST uint32 = 0xE70E // VRX VECTOR STORE 2477 op_VSTEH uint32 = 0xE709 // VRX VECTOR STORE ELEMENT (16) 2478 op_VSTEF uint32 = 0xE70B // VRX VECTOR STORE ELEMENT (32) 2479 op_VSTEG uint32 = 0xE70A // VRX VECTOR STORE ELEMENT (64) 2480 op_VSTEB uint32 = 0xE708 // VRX VECTOR STORE ELEMENT (8) 2481 op_VSTM uint32 = 0xE73E // VRS-a VECTOR STORE MULTIPLE 2482 op_VSTL uint32 = 0xE73F // VRS-b VECTOR STORE WITH LENGTH 2483 op_VSTRC uint32 = 0xE78A // VRR-d VECTOR STRING RANGE COMPARE 2484 op_VS uint32 = 0xE7F7 // VRR-c VECTOR SUBTRACT 2485 op_VSCBI uint32 = 0xE7F5 // VRR-c VECTOR SUBTRACT COMPUTE BORROW INDICATION 2486 op_VSBCBI uint32 = 0xE7BD // VRR-d VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION 2487 op_VSBI uint32 = 0xE7BF // VRR-d VECTOR SUBTRACT WITH BORROW INDICATION 2488 op_VSUMG uint32 = 0xE765 // VRR-c VECTOR SUM ACROSS DOUBLEWORD 2489 op_VSUMQ uint32 = 0xE767 // VRR-c VECTOR SUM ACROSS QUADWORD 2490 op_VSUM uint32 = 0xE764 // VRR-c VECTOR SUM ACROSS WORD 2491 op_VTM uint32 = 0xE7D8 // VRR-a VECTOR TEST UNDER MASK 2492 op_VUPH uint32 = 0xE7D7 // VRR-a VECTOR UNPACK HIGH 2493 op_VUPLH uint32 = 0xE7D5 // VRR-a VECTOR UNPACK LOGICAL HIGH 2494 op_VUPLL uint32 = 0xE7D4 // VRR-a VECTOR UNPACK LOGICAL LOW 2495 op_VUPL uint32 = 0xE7D6 // VRR-a VECTOR UNPACK LOW 2496 ) 2497 2498 func oclass(a *obj.Addr) int { 2499 return int(a.Class) - 1 2500 } 2501 2502 // Add a relocation for the immediate in a RIL style instruction. 2503 // The addend will be adjusted as required. 2504 func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) *obj.Reloc { 2505 if sym == nil { 2506 c.ctxt.Diag("require symbol to apply relocation") 2507 } 2508 offset := int64(2) // relocation offset from start of instruction 2509 rel := obj.Addrel(c.cursym) 2510 rel.Off = int32(c.pc + offset) 2511 rel.Siz = 4 2512 rel.Sym = sym 2513 rel.Add = add + offset + int64(rel.Siz) 2514 rel.Type = objabi.R_PCRELDBL 2515 return rel 2516 } 2517 2518 func (c *ctxtz) addrilrelocoffset(sym *obj.LSym, add, offset int64) *obj.Reloc { 2519 if sym == nil { 2520 c.ctxt.Diag("require symbol to apply relocation") 2521 } 2522 offset += int64(2) // relocation offset from start of instruction 2523 rel := obj.Addrel(c.cursym) 2524 rel.Off = int32(c.pc + offset) 2525 rel.Siz = 4 2526 rel.Sym = sym 2527 rel.Add = add + offset + int64(rel.Siz) 2528 rel.Type = objabi.R_PCRELDBL 2529 return rel 2530 } 2531 2532 // Add a CALL relocation for the immediate in a RIL style instruction. 2533 // The addend will be adjusted as required. 2534 func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) *obj.Reloc { 2535 if sym == nil { 2536 c.ctxt.Diag("require symbol to apply relocation") 2537 } 2538 offset := int64(2) // relocation offset from start of instruction 2539 rel := obj.Addrel(c.cursym) 2540 rel.Off = int32(c.pc + offset) 2541 rel.Siz = 4 2542 rel.Sym = sym 2543 rel.Add = add + offset + int64(rel.Siz) 2544 rel.Type = objabi.R_CALL 2545 return rel 2546 } 2547 2548 func (c *ctxtz) branchMask(p *obj.Prog) uint32 { 2549 switch p.As { 2550 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ: 2551 return 0x8 2552 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE: 2553 return 0xA 2554 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT: 2555 return 0x2 2556 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE: 2557 return 0xC 2558 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT: 2559 return 0x4 2560 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE: 2561 return 0x7 2562 case ABLEU: // LE or unordered 2563 return 0xD 2564 case ABLTU: // LT or unordered 2565 return 0x5 2566 case ABVC: 2567 return 0x0 // needs extra instruction 2568 case ABVS: 2569 return 0x1 // unordered 2570 } 2571 c.ctxt.Diag("unknown conditional branch %v", p.As) 2572 return 0xF 2573 } 2574 2575 func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) { 2576 o := c.oplook(p) 2577 2578 switch o.type_ { 2579 default: 2580 c.ctxt.Diag("unknown type %d", o.type_) 2581 2582 case 0: // PSEUDO OPS 2583 break 2584 2585 case 1: // mov reg reg 2586 switch p.As { 2587 default: 2588 c.ctxt.Diag("unhandled operation: %v", p.As) 2589 case AMOVD: 2590 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2591 // sign extend 2592 case AMOVW: 2593 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2594 case AMOVH: 2595 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2596 case AMOVB: 2597 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2598 // zero extend 2599 case AMOVWZ: 2600 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2601 case AMOVHZ: 2602 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2603 case AMOVBZ: 2604 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2605 // reverse bytes 2606 case AMOVDBR: 2607 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2608 case AMOVWBR: 2609 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2610 // floating point 2611 case AFMOVD, AFMOVS: 2612 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2613 } 2614 2615 case 2: // arithmetic op reg [reg] reg 2616 r := p.Reg 2617 if r == 0 { 2618 r = p.To.Reg 2619 } 2620 2621 var opcode uint32 2622 2623 switch p.As { 2624 default: 2625 c.ctxt.Diag("invalid opcode") 2626 case AADD: 2627 opcode = op_AGRK 2628 case AADDC: 2629 opcode = op_ALGRK 2630 case AADDE: 2631 opcode = op_ALCGR 2632 case AADDW: 2633 opcode = op_ARK 2634 case AMULLW: 2635 opcode = op_MSGFR 2636 case AMULLD: 2637 opcode = op_MSGR 2638 case ADIVW, AMODW: 2639 opcode = op_DSGFR 2640 case ADIVWU, AMODWU: 2641 opcode = op_DLR 2642 case ADIVD, AMODD: 2643 opcode = op_DSGR 2644 case ADIVDU, AMODDU: 2645 opcode = op_DLGR 2646 } 2647 2648 switch p.As { 2649 default: 2650 2651 case AADD, AADDC, AADDW: 2652 if p.As == AADDW && r == p.To.Reg { 2653 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2654 } else { 2655 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2656 } 2657 2658 case AADDE, AMULLW, AMULLD: 2659 if r == p.To.Reg { 2660 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2661 } else if p.From.Reg == p.To.Reg { 2662 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2663 } else { 2664 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2665 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2666 } 2667 2668 case ADIVW, ADIVWU, ADIVD, ADIVDU: 2669 if p.As == ADIVWU || p.As == ADIVDU { 2670 zRI(op_LGHI, REGTMP, 0, asm) 2671 } 2672 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2673 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2674 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm) 2675 2676 case AMODW, AMODWU, AMODD, AMODDU: 2677 if p.As == AMODWU || p.As == AMODDU { 2678 zRI(op_LGHI, REGTMP, 0, asm) 2679 } 2680 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2681 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2682 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2683 2684 } 2685 2686 case 3: // mov $constant reg 2687 v := c.vregoff(&p.From) 2688 switch p.As { 2689 case AMOVBZ: 2690 v = int64(uint8(v)) 2691 case AMOVHZ: 2692 v = int64(uint16(v)) 2693 case AMOVWZ: 2694 v = int64(uint32(v)) 2695 case AMOVB: 2696 v = int64(int8(v)) 2697 case AMOVH: 2698 v = int64(int16(v)) 2699 case AMOVW: 2700 v = int64(int32(v)) 2701 } 2702 if int64(int16(v)) == v { 2703 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm) 2704 } else if v&0xffff0000 == v { 2705 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm) 2706 } else if v&0xffff00000000 == v { 2707 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm) 2708 } else if uint64(v)&0xffff000000000000 == uint64(v) { 2709 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm) 2710 } else if int64(int32(v)) == v { 2711 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm) 2712 } else if int64(uint32(v)) == v { 2713 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2714 } else if uint64(v)&0xffffffff00000000 == uint64(v) { 2715 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2716 } else { 2717 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2718 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2719 } 2720 2721 case 4: // multiply high (a*b)>>64 2722 r := p.Reg 2723 if r == 0 { 2724 r = p.To.Reg 2725 } 2726 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2727 zRRE(op_MLGR, REGTMP, uint32(p.From.Reg), asm) 2728 switch p.As { 2729 case AMULHDU: 2730 // Unsigned: move result into correct register. 2731 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2732 case AMULHD: 2733 // Signed: need to convert result. 2734 // See Hacker's Delight 8-3. 2735 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm) 2736 zRRE(op_NGR, REGTMP2, uint32(r), asm) 2737 zRRE(op_SGR, REGTMP, REGTMP2, asm) 2738 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm) 2739 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm) 2740 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), REGTMP, asm) 2741 } 2742 2743 case 5: // syscall 2744 zI(op_SVC, 0, asm) 2745 2746 case 6: // logical op reg [reg] reg 2747 var oprr, oprre, oprrf uint32 2748 switch p.As { 2749 case AAND: 2750 oprre = op_NGR 2751 oprrf = op_NGRK 2752 case AANDW: 2753 oprr = op_NR 2754 oprrf = op_NRK 2755 case AOR: 2756 oprre = op_OGR 2757 oprrf = op_OGRK 2758 case AORW: 2759 oprr = op_OR 2760 oprrf = op_ORK 2761 case AXOR: 2762 oprre = op_XGR 2763 oprrf = op_XGRK 2764 case AXORW: 2765 oprr = op_XR 2766 oprrf = op_XRK 2767 } 2768 if p.Reg == 0 { 2769 if oprr != 0 { 2770 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2771 } else { 2772 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2773 } 2774 } else { 2775 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2776 } 2777 2778 case 7: // shift/rotate reg [reg] reg 2779 d2 := c.vregoff(&p.From) 2780 b2 := p.From.Reg 2781 r3 := p.Reg 2782 if r3 == 0 { 2783 r3 = p.To.Reg 2784 } 2785 r1 := p.To.Reg 2786 var opcode uint32 2787 switch p.As { 2788 default: 2789 case ASLD: 2790 opcode = op_SLLG 2791 case ASRD: 2792 opcode = op_SRLG 2793 case ASLW: 2794 opcode = op_SLLK 2795 case ASRW: 2796 opcode = op_SRLK 2797 case ARLL: 2798 opcode = op_RLL 2799 case ARLLG: 2800 opcode = op_RLLG 2801 case ASRAW: 2802 opcode = op_SRAK 2803 case ASRAD: 2804 opcode = op_SRAG 2805 } 2806 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm) 2807 2808 case 8: // find leftmost one 2809 if p.To.Reg&1 != 0 { 2810 c.ctxt.Diag("target must be an even-numbered register") 2811 } 2812 // FLOGR also writes a mask to p.To.Reg+1. 2813 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2814 2815 case 10: // subtract reg [reg] reg 2816 r := int(p.Reg) 2817 2818 switch p.As { 2819 default: 2820 case ASUB: 2821 if r == 0 { 2822 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2823 } else { 2824 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2825 } 2826 case ASUBC: 2827 if r == 0 { 2828 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2829 } else { 2830 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2831 } 2832 case ASUBE: 2833 if r == 0 { 2834 r = int(p.To.Reg) 2835 } 2836 if r == int(p.To.Reg) { 2837 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2838 } else if p.From.Reg == p.To.Reg { 2839 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 2840 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2841 zRRE(op_SLBGR, uint32(p.To.Reg), REGTMP, asm) 2842 } else { 2843 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2844 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2845 } 2846 case ASUBW: 2847 if r == 0 { 2848 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2849 } else { 2850 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2851 } 2852 } 2853 2854 case 11: // br/bl 2855 v := int32(0) 2856 2857 if p.Pcond != nil { 2858 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2859 } 2860 2861 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v { 2862 zRI(op_BRC, 0xF, uint32(v), asm) 2863 } else { 2864 if p.As == ABL { 2865 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm) 2866 } else { 2867 zRIL(_c, op_BRCL, 0xF, uint32(v), asm) 2868 } 2869 if p.To.Sym != nil { 2870 c.addcallreloc(p.To.Sym, p.To.Offset) 2871 } 2872 } 2873 2874 case 12: 2875 r1 := p.To.Reg 2876 d2 := c.vregoff(&p.From) 2877 b2 := p.From.Reg 2878 if b2 == 0 { 2879 b2 = o.param 2880 } 2881 x2 := p.From.Index 2882 if -DISP20/2 > d2 || d2 >= DISP20/2 { 2883 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 2884 if x2 != 0 { 2885 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 2886 } 2887 x2 = REGTMP 2888 d2 = 0 2889 } 2890 var opx, opxy uint32 2891 switch p.As { 2892 case AADD: 2893 opxy = op_AG 2894 case AADDC: 2895 opxy = op_ALG 2896 case AADDW: 2897 opx = op_A 2898 opxy = op_AY 2899 case AMULLW: 2900 opx = op_MS 2901 opxy = op_MSY 2902 case AMULLD: 2903 opxy = op_MSG 2904 case ASUB: 2905 opxy = op_SG 2906 case ASUBC: 2907 opxy = op_SLG 2908 case ASUBE: 2909 opxy = op_SLBG 2910 case ASUBW: 2911 opx = op_S 2912 opxy = op_SY 2913 case AAND: 2914 opxy = op_NG 2915 case AANDW: 2916 opx = op_N 2917 opxy = op_NY 2918 case AOR: 2919 opxy = op_OG 2920 case AORW: 2921 opx = op_O 2922 opxy = op_OY 2923 case AXOR: 2924 opxy = op_XG 2925 case AXORW: 2926 opx = op_X 2927 opxy = op_XY 2928 } 2929 if opx != 0 && 0 <= d2 && d2 < DISP12 { 2930 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 2931 } else { 2932 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 2933 } 2934 2935 case 15: // br/bl (reg) 2936 r := p.To.Reg 2937 if p.As == ABCL || p.As == ABL { 2938 zRR(op_BASR, uint32(REG_LR), uint32(r), asm) 2939 } else { 2940 zRR(op_BCR, 0xF, uint32(r), asm) 2941 } 2942 2943 case 16: // conditional branch 2944 v := int32(0) 2945 if p.Pcond != nil { 2946 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2947 } 2948 mask := c.branchMask(p) 2949 if p.To.Sym == nil && int32(int16(v)) == v { 2950 zRI(op_BRC, mask, uint32(v), asm) 2951 } else { 2952 zRIL(_c, op_BRCL, mask, uint32(v), asm) 2953 } 2954 if p.To.Sym != nil { 2955 c.addrilreloc(p.To.Sym, p.To.Offset) 2956 } 2957 2958 case 17: // move on condition 2959 m3 := c.branchMask(p) 2960 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2961 2962 case 18: // br/bl reg 2963 if p.As == ABL { 2964 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm) 2965 } else { 2966 zRR(op_BCR, 0xF, uint32(p.To.Reg), asm) 2967 } 2968 2969 case 19: // mov $sym+n(SB) reg 2970 d := c.vregoff(&p.From) 2971 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm) 2972 if d&1 != 0 { 2973 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm) 2974 d -= 1 2975 } 2976 c.addrilreloc(p.From.Sym, d) 2977 2978 case 21: // subtract $constant [reg] reg 2979 v := c.vregoff(&p.From) 2980 r := p.Reg 2981 if r == 0 { 2982 r = p.To.Reg 2983 } 2984 switch p.As { 2985 case ASUB: 2986 zRIL(_a, op_LGFI, uint32(REGTMP), uint32(v), asm) 2987 zRRF(op_SLGRK, uint32(REGTMP), 0, uint32(p.To.Reg), uint32(r), asm) 2988 case ASUBC: 2989 if r != p.To.Reg { 2990 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2991 } 2992 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm) 2993 case ASUBW: 2994 if r != p.To.Reg { 2995 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 2996 } 2997 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm) 2998 } 2999 3000 case 22: // add/multiply $constant [reg] reg 3001 v := c.vregoff(&p.From) 3002 r := p.Reg 3003 if r == 0 { 3004 r = p.To.Reg 3005 } 3006 var opri, opril, oprie uint32 3007 switch p.As { 3008 case AADD: 3009 opri = op_AGHI 3010 opril = op_AGFI 3011 oprie = op_AGHIK 3012 case AADDC: 3013 opril = op_ALGFI 3014 oprie = op_ALGHSIK 3015 case AADDW: 3016 opri = op_AHI 3017 opril = op_AFI 3018 oprie = op_AHIK 3019 case AMULLW: 3020 opri = op_MHI 3021 opril = op_MSFI 3022 case AMULLD: 3023 opri = op_MGHI 3024 opril = op_MSGFI 3025 } 3026 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) { 3027 switch p.As { 3028 case AADD, AADDC, AMULLD: 3029 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3030 case AADDW, AMULLW: 3031 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3032 } 3033 r = p.To.Reg 3034 } 3035 if r == p.To.Reg { 3036 if opri != 0 && int64(int16(v)) == v { 3037 zRI(opri, uint32(p.To.Reg), uint32(v), asm) 3038 } else { 3039 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm) 3040 } 3041 } else { 3042 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm) 3043 } 3044 3045 case 23: // 64-bit logical op $constant reg 3046 // TODO(mundaym): merge with case 24. 3047 v := c.vregoff(&p.From) 3048 switch p.As { 3049 default: 3050 c.ctxt.Diag("%v is not supported", p) 3051 case AAND: 3052 if v >= 0 { // needs zero extend 3053 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3054 zRRE(op_NGR, uint32(p.To.Reg), REGTMP, asm) 3055 } else if int64(int16(v)) == v { 3056 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3057 } else { // r.To.Reg & 0xffffffff00000000 & uint32(v) 3058 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3059 } 3060 case AOR: 3061 if int64(uint32(v)) != v { // needs sign extend 3062 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3063 zRRE(op_OGR, uint32(p.To.Reg), REGTMP, asm) 3064 } else if int64(uint16(v)) == v { 3065 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3066 } else { 3067 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3068 } 3069 case AXOR: 3070 if int64(uint32(v)) != v { // needs sign extend 3071 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3072 zRRE(op_XGR, uint32(p.To.Reg), REGTMP, asm) 3073 } else { 3074 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3075 } 3076 } 3077 3078 case 24: // 32-bit logical op $constant reg 3079 v := c.vregoff(&p.From) 3080 switch p.As { 3081 case AANDW: 3082 if uint32(v&0xffff0000) == 0xffff0000 { 3083 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3084 } else if uint32(v&0x0000ffff) == 0x0000ffff { 3085 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3086 } else { 3087 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3088 } 3089 case AORW: 3090 if uint32(v&0xffff0000) == 0 { 3091 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3092 } else if uint32(v&0x0000ffff) == 0 { 3093 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3094 } else { 3095 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3096 } 3097 case AXORW: 3098 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3099 } 3100 3101 case 26: // MOVD $offset(base)(index), reg 3102 v := c.regoff(&p.From) 3103 r := p.From.Reg 3104 if r == 0 { 3105 r = o.param 3106 } 3107 i := p.From.Index 3108 if v >= 0 && v < DISP12 { 3109 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3110 } else if v >= -DISP20/2 && v < DISP20/2 { 3111 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3112 } else { 3113 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3114 zRX(op_LA, uint32(p.To.Reg), uint32(r), REGTMP, uint32(i), asm) 3115 } 3116 3117 case 31: // dword 3118 wd := uint64(c.vregoff(&p.From)) 3119 *asm = append(*asm, 3120 uint8(wd>>56), 3121 uint8(wd>>48), 3122 uint8(wd>>40), 3123 uint8(wd>>32), 3124 uint8(wd>>24), 3125 uint8(wd>>16), 3126 uint8(wd>>8), 3127 uint8(wd)) 3128 3129 case 32: // float op freg freg 3130 var opcode uint32 3131 switch p.As { 3132 default: 3133 c.ctxt.Diag("invalid opcode") 3134 case AFADD: 3135 opcode = op_ADBR 3136 case AFADDS: 3137 opcode = op_AEBR 3138 case AFDIV: 3139 opcode = op_DDBR 3140 case AFDIVS: 3141 opcode = op_DEBR 3142 case AFMUL: 3143 opcode = op_MDBR 3144 case AFMULS: 3145 opcode = op_MEEBR 3146 case AFSUB: 3147 opcode = op_SDBR 3148 case AFSUBS: 3149 opcode = op_SEBR 3150 } 3151 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3152 3153 case 33: // float op [freg] freg 3154 r := p.From.Reg 3155 if oclass(&p.From) == C_NONE { 3156 r = p.To.Reg 3157 } 3158 var opcode uint32 3159 switch p.As { 3160 default: 3161 case AFABS: 3162 opcode = op_LPDBR 3163 case AFNABS: 3164 opcode = op_LNDBR 3165 case AFNEG: 3166 opcode = op_LCDFR 3167 case AFNEGS: 3168 opcode = op_LCEBR 3169 case ALEDBR: 3170 opcode = op_LEDBR 3171 case ALDEBR: 3172 opcode = op_LDEBR 3173 case AFSQRT: 3174 opcode = op_SQDBR 3175 case AFSQRTS: 3176 opcode = op_SQEBR 3177 } 3178 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3179 3180 case 34: // float multiply-add freg freg freg 3181 var opcode uint32 3182 switch p.As { 3183 default: 3184 c.ctxt.Diag("invalid opcode") 3185 case AFMADD: 3186 opcode = op_MADBR 3187 case AFMADDS: 3188 opcode = op_MAEBR 3189 case AFMSUB: 3190 opcode = op_MSDBR 3191 case AFMSUBS: 3192 opcode = op_MSEBR 3193 } 3194 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 3195 3196 case 35: // mov reg mem (no relocation) 3197 d2 := c.regoff(&p.To) 3198 b2 := p.To.Reg 3199 if b2 == 0 { 3200 b2 = o.param 3201 } 3202 x2 := p.To.Index 3203 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3204 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3205 if x2 != 0 { 3206 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3207 } 3208 x2 = REGTMP 3209 d2 = 0 3210 } 3211 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3212 3213 case 36: // mov mem reg (no relocation) 3214 d2 := c.regoff(&p.From) 3215 b2 := p.From.Reg 3216 if b2 == 0 { 3217 b2 = o.param 3218 } 3219 x2 := p.From.Index 3220 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3221 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3222 if x2 != 0 { 3223 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3224 } 3225 x2 = REGTMP 3226 d2 = 0 3227 } 3228 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3229 3230 case 40: // word/byte 3231 wd := uint32(c.regoff(&p.From)) 3232 if p.As == AWORD { //WORD 3233 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd)) 3234 } else { //BYTE 3235 *asm = append(*asm, uint8(wd)) 3236 } 3237 3238 case 47: // negate [reg] reg 3239 r := p.From.Reg 3240 if r == 0 { 3241 r = p.To.Reg 3242 } 3243 switch p.As { 3244 case ANEG: 3245 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm) 3246 case ANEGW: 3247 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm) 3248 } 3249 3250 case 48: // floating-point round to integer 3251 m3 := c.vregoff(&p.From) 3252 if 0 > m3 || m3 > 7 { 3253 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3) 3254 } 3255 var opcode uint32 3256 switch p.As { 3257 case AFIEBR: 3258 opcode = op_FIEBR 3259 case AFIDBR: 3260 opcode = op_FIDBR 3261 } 3262 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3263 3264 case 67: // fmov $0 freg 3265 var opcode uint32 3266 switch p.As { 3267 case AFMOVS: 3268 opcode = op_LZER 3269 case AFMOVD: 3270 opcode = op_LZDR 3271 } 3272 zRRE(opcode, uint32(p.To.Reg), 0, asm) 3273 3274 case 68: // movw areg reg 3275 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm) 3276 3277 case 69: // movw reg areg 3278 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm) 3279 3280 case 70: // cmp reg reg 3281 if p.As == ACMPW || p.As == ACMPWU { 3282 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3283 } else { 3284 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3285 } 3286 3287 case 71: // cmp reg $constant 3288 v := c.vregoff(&p.To) 3289 switch p.As { 3290 case ACMP, ACMPW: 3291 if int64(int32(v)) != v { 3292 c.ctxt.Diag("%v overflows an int32", v) 3293 } 3294 case ACMPU, ACMPWU: 3295 if int64(uint32(v)) != v { 3296 c.ctxt.Diag("%v overflows a uint32", v) 3297 } 3298 } 3299 if p.As == ACMP && int64(int16(v)) == v { 3300 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm) 3301 } else if p.As == ACMPW && int64(int16(v)) == v { 3302 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm) 3303 } else { 3304 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm) 3305 } 3306 3307 case 72: // mov $constant mem 3308 v := c.regoff(&p.From) 3309 d := c.regoff(&p.To) 3310 r := p.To.Reg 3311 if p.To.Index != 0 { 3312 c.ctxt.Diag("cannot use index register") 3313 } 3314 if r == 0 { 3315 r = o.param 3316 } 3317 var opcode uint32 3318 switch p.As { 3319 case AMOVD: 3320 opcode = op_MVGHI 3321 case AMOVW, AMOVWZ: 3322 opcode = op_MVHI 3323 case AMOVH, AMOVHZ: 3324 opcode = op_MVHHI 3325 case AMOVB, AMOVBZ: 3326 opcode = op_MVI 3327 } 3328 if d < 0 || d >= DISP12 { 3329 if r == REGTMP { 3330 c.ctxt.Diag("displacement must be in range [0, 4096) to use %v", r) 3331 } 3332 if d >= -DISP20/2 && d < DISP20/2 { 3333 if opcode == op_MVI { 3334 opcode = op_MVIY 3335 } else { 3336 zRXY(op_LAY, uint32(REGTMP), 0, uint32(r), uint32(d), asm) 3337 r = REGTMP 3338 d = 0 3339 } 3340 } else { 3341 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm) 3342 zRX(op_LA, REGTMP, REGTMP, uint32(r), 0, asm) 3343 r = REGTMP 3344 d = 0 3345 } 3346 } 3347 switch opcode { 3348 case op_MVI: 3349 zSI(opcode, uint32(v), uint32(r), uint32(d), asm) 3350 case op_MVIY: 3351 zSIY(opcode, uint32(v), uint32(r), uint32(d), asm) 3352 default: 3353 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm) 3354 } 3355 3356 case 74: // mov reg addr (including relocation) 3357 i2 := c.regoff(&p.To) 3358 switch p.As { 3359 case AMOVD: 3360 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm) 3361 case AMOVW, AMOVWZ: // The zero extension doesn't affect store instructions 3362 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm) 3363 case AMOVH, AMOVHZ: // The zero extension doesn't affect store instructions 3364 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm) 3365 case AMOVB, AMOVBZ: // The zero extension doesn't affect store instructions 3366 zRIL(_b, op_LARL, REGTMP, 0, asm) 3367 adj := uint32(0) // adjustment needed for odd addresses 3368 if i2&1 != 0 { 3369 i2 -= 1 3370 adj = 1 3371 } 3372 zRX(op_STC, uint32(p.From.Reg), 0, REGTMP, adj, asm) 3373 case AFMOVD: 3374 zRIL(_b, op_LARL, REGTMP, 0, asm) 3375 zRX(op_STD, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3376 case AFMOVS: 3377 zRIL(_b, op_LARL, REGTMP, 0, asm) 3378 zRX(op_STE, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3379 } 3380 c.addrilreloc(p.To.Sym, int64(i2)) 3381 3382 case 75: // mov addr reg (including relocation) 3383 i2 := c.regoff(&p.From) 3384 switch p.As { 3385 case AMOVD: 3386 if i2&1 != 0 { 3387 zRIL(_b, op_LARL, REGTMP, 0, asm) 3388 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 1, asm) 3389 i2 -= 1 3390 } else { 3391 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3392 } 3393 case AMOVW: 3394 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm) 3395 case AMOVWZ: 3396 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm) 3397 case AMOVH: 3398 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm) 3399 case AMOVHZ: 3400 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm) 3401 case AMOVB, AMOVBZ: 3402 zRIL(_b, op_LARL, REGTMP, 0, asm) 3403 adj := uint32(0) // adjustment needed for odd addresses 3404 if i2&1 != 0 { 3405 i2 -= 1 3406 adj = 1 3407 } 3408 switch p.As { 3409 case AMOVB: 3410 zRXY(op_LGB, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3411 case AMOVBZ: 3412 zRXY(op_LLGC, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3413 } 3414 case AFMOVD: 3415 zRIL(_a, op_LARL, REGTMP, 0, asm) 3416 zRX(op_LD, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3417 case AFMOVS: 3418 zRIL(_a, op_LARL, REGTMP, 0, asm) 3419 zRX(op_LE, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3420 } 3421 c.addrilreloc(p.From.Sym, int64(i2)) 3422 3423 case 77: // syscall $constant 3424 if p.From.Offset > 255 || p.From.Offset < 1 { 3425 c.ctxt.Diag("illegal system call; system call number out of range: %v", p) 3426 zE(op_TRAP2, asm) // trap always 3427 } else { 3428 zI(op_SVC, uint32(p.From.Offset), asm) 3429 } 3430 3431 case 78: // undef 3432 // "An instruction consisting entirely of binary 0s is guaranteed 3433 // always to be an illegal instruction." 3434 *asm = append(*asm, 0, 0, 0, 0) 3435 3436 case 79: // compare and swap reg reg reg 3437 v := c.regoff(&p.To) 3438 if v < 0 { 3439 v = 0 3440 } 3441 if p.As == ACS { 3442 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3443 } else if p.As == ACSG { 3444 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3445 } 3446 3447 case 80: // sync 3448 zRR(op_BCR, 0xE, 0, asm) 3449 3450 case 81: // float to fixed and fixed to float moves (no conversion) 3451 switch p.As { 3452 case ALDGR: 3453 zRRE(op_LDGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3454 case ALGDR: 3455 zRRE(op_LGDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3456 } 3457 3458 case 82: // fixed to float conversion 3459 var opcode uint32 3460 switch p.As { 3461 default: 3462 log.Fatalf("unexpected opcode %v", p.As) 3463 case ACEFBRA: 3464 opcode = op_CEFBRA 3465 case ACDFBRA: 3466 opcode = op_CDFBRA 3467 case ACEGBRA: 3468 opcode = op_CEGBRA 3469 case ACDGBRA: 3470 opcode = op_CDGBRA 3471 case ACELFBR: 3472 opcode = op_CELFBR 3473 case ACDLFBR: 3474 opcode = op_CDLFBR 3475 case ACELGBR: 3476 opcode = op_CELGBR 3477 case ACDLGBR: 3478 opcode = op_CDLGBR 3479 } 3480 // set immediate operand M3 to 0 to use the default BFP rounding mode 3481 // (usually round to nearest, ties to even) 3482 // TODO(mundaym): should this be fixed at round to nearest, ties to even? 3483 // M4 is reserved and must be 0 3484 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3485 3486 case 83: // float to fixed conversion 3487 var opcode uint32 3488 switch p.As { 3489 default: 3490 log.Fatalf("unexpected opcode %v", p.As) 3491 case ACFEBRA: 3492 opcode = op_CFEBRA 3493 case ACFDBRA: 3494 opcode = op_CFDBRA 3495 case ACGEBRA: 3496 opcode = op_CGEBRA 3497 case ACGDBRA: 3498 opcode = op_CGDBRA 3499 case ACLFEBR: 3500 opcode = op_CLFEBR 3501 case ACLFDBR: 3502 opcode = op_CLFDBR 3503 case ACLGEBR: 3504 opcode = op_CLGEBR 3505 case ACLGDBR: 3506 opcode = op_CLGDBR 3507 } 3508 // set immediate operand M3 to 5 for rounding toward zero (required by Go spec) 3509 // M4 is reserved and must be 0 3510 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3511 3512 case 84: // storage-and-storage operations $length mem mem 3513 l := c.regoff(&p.From) 3514 if l < 1 || l > 256 { 3515 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l) 3516 } 3517 if p.From3.Index != 0 || p.To.Index != 0 { 3518 c.ctxt.Diag("cannot use index reg") 3519 } 3520 b1 := p.To.Reg 3521 b2 := p.From3.Reg 3522 if b1 == 0 { 3523 b1 = o.param 3524 } 3525 if b2 == 0 { 3526 b2 = o.param 3527 } 3528 d1 := c.regoff(&p.To) 3529 d2 := c.regoff(p.From3) 3530 if d1 < 0 || d1 >= DISP12 { 3531 if b2 == REGTMP { 3532 c.ctxt.Diag("REGTMP conflict") 3533 } 3534 if b1 != REGTMP { 3535 zRRE(op_LGR, REGTMP, uint32(b1), asm) 3536 } 3537 zRIL(_a, op_AGFI, REGTMP, uint32(d1), asm) 3538 if d1 == d2 && b1 == b2 { 3539 d2 = 0 3540 b2 = REGTMP 3541 } 3542 d1 = 0 3543 b1 = REGTMP 3544 } 3545 if d2 < 0 || d2 >= DISP12 { 3546 if b1 == REGTMP2 { 3547 c.ctxt.Diag("REGTMP2 conflict") 3548 } 3549 if b2 != REGTMP2 { 3550 zRRE(op_LGR, REGTMP2, uint32(b2), asm) 3551 } 3552 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm) 3553 d2 = 0 3554 b2 = REGTMP2 3555 } 3556 var opcode uint32 3557 switch p.As { 3558 default: 3559 c.ctxt.Diag("unexpected opcode %v", p.As) 3560 case AMVC: 3561 opcode = op_MVC 3562 case ACLC: 3563 opcode = op_CLC 3564 // swap operand order for CLC so that it matches CMP 3565 b1, b2 = b2, b1 3566 d1, d2 = d2, d1 3567 case AXC: 3568 opcode = op_XC 3569 case AOC: 3570 opcode = op_OC 3571 case ANC: 3572 opcode = op_NC 3573 } 3574 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm) 3575 3576 case 85: // load address relative long 3577 v := c.regoff(&p.From) 3578 if p.From.Sym == nil { 3579 if (v & 1) != 0 { 3580 c.ctxt.Diag("cannot use LARL with odd offset: %v", v) 3581 } 3582 } else { 3583 c.addrilreloc(p.From.Sym, int64(v)) 3584 v = 0 3585 } 3586 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm) 3587 3588 case 86: // load address 3589 d := c.vregoff(&p.From) 3590 x := p.From.Index 3591 b := p.From.Reg 3592 if b == 0 { 3593 b = o.param 3594 } 3595 switch p.As { 3596 case ALA: 3597 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3598 case ALAY: 3599 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3600 } 3601 3602 case 87: // execute relative long 3603 v := c.vregoff(&p.From) 3604 if p.From.Sym == nil { 3605 if v&1 != 0 { 3606 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v) 3607 } 3608 } else { 3609 c.addrilreloc(p.From.Sym, v) 3610 v = 0 3611 } 3612 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm) 3613 3614 case 88: // store clock 3615 var opcode uint32 3616 switch p.As { 3617 case ASTCK: 3618 opcode = op_STCK 3619 case ASTCKC: 3620 opcode = op_STCKC 3621 case ASTCKE: 3622 opcode = op_STCKE 3623 case ASTCKF: 3624 opcode = op_STCKF 3625 } 3626 v := c.vregoff(&p.To) 3627 r := int(p.To.Reg) 3628 if r == 0 { 3629 r = int(o.param) 3630 } 3631 zS(opcode, uint32(r), uint32(v), asm) 3632 3633 case 89: // compare and branch reg reg 3634 var v int32 3635 if p.Pcond != nil { 3636 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3637 } 3638 var opcode, opcode2 uint32 3639 switch p.As { 3640 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3641 opcode = op_CGRJ 3642 opcode2 = op_CGR 3643 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3644 opcode = op_CLGRJ 3645 opcode2 = op_CLGR 3646 } 3647 mask := c.branchMask(p) 3648 if int32(int16(v)) != v { 3649 zRRE(opcode2, uint32(p.From.Reg), uint32(p.Reg), asm) 3650 zRIL(_c, op_BRCL, mask, uint32(v-sizeRRE/2), asm) 3651 } else { 3652 zRIE(_b, opcode, uint32(p.From.Reg), uint32(p.Reg), uint32(v), 0, 0, mask, 0, asm) 3653 } 3654 3655 case 90: // compare and branch reg $constant 3656 var v int32 3657 if p.Pcond != nil { 3658 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3659 } 3660 var opcode, opcode2 uint32 3661 switch p.As { 3662 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3663 opcode = op_CGIJ 3664 opcode2 = op_CGFI 3665 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3666 opcode = op_CLGIJ 3667 opcode2 = op_CLGFI 3668 } 3669 mask := c.branchMask(p) 3670 if int32(int16(v)) != v { 3671 zRIL(_a, opcode2, uint32(p.From.Reg), uint32(c.regoff(p.From3)), asm) 3672 zRIL(_c, op_BRCL, mask, uint32(v-sizeRIL/2), asm) 3673 } else { 3674 zRIE(_c, opcode, uint32(p.From.Reg), mask, uint32(v), 0, 0, 0, uint32(c.regoff(p.From3)), asm) 3675 } 3676 3677 case 93: // GOT lookup 3678 v := c.vregoff(&p.To) 3679 if v != 0 { 3680 c.ctxt.Diag("invalid offset against GOT slot %v", p) 3681 } 3682 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3683 rel := obj.Addrel(c.cursym) 3684 rel.Off = int32(c.pc + 2) 3685 rel.Siz = 4 3686 rel.Sym = p.From.Sym 3687 rel.Type = objabi.R_GOTPCREL 3688 rel.Add = 2 + int64(rel.Siz) 3689 3690 case 94: // TLS local exec model 3691 zRIL(_b, op_LARL, REGTMP, (sizeRIL+sizeRXY+sizeRI)>>1, asm) 3692 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3693 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm) 3694 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0) 3695 rel := obj.Addrel(c.cursym) 3696 rel.Off = int32(c.pc + sizeRIL + sizeRXY + sizeRI) 3697 rel.Siz = 8 3698 rel.Sym = p.From.Sym 3699 rel.Type = objabi.R_TLS_LE 3700 rel.Add = 0 3701 3702 case 95: // TLS initial exec model 3703 // Assembly | Relocation symbol | Done Here? 3704 // -------------------------------------------------------------- 3705 // ear %r11, %a0 | | 3706 // sllg %r11, %r11, 32 | | 3707 // ear %r11, %a1 | | 3708 // larl %r10, <var>@indntpoff | R_390_TLS_IEENT | Y 3709 // lg %r10, 0(%r10) | R_390_TLS_LOAD (tag) | Y 3710 // la %r10, 0(%r10, %r11) | | 3711 // -------------------------------------------------------------- 3712 3713 // R_390_TLS_IEENT 3714 zRIL(_b, op_LARL, REGTMP, 0, asm) 3715 ieent := obj.Addrel(c.cursym) 3716 ieent.Off = int32(c.pc + 2) 3717 ieent.Siz = 4 3718 ieent.Sym = p.From.Sym 3719 ieent.Type = objabi.R_TLS_IE 3720 ieent.Add = 2 + int64(ieent.Siz) 3721 3722 // R_390_TLS_LOAD 3723 zRXY(op_LGF, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3724 // TODO(mundaym): add R_390_TLS_LOAD relocation here 3725 // not strictly required but might allow the linker to optimize 3726 3727 case 96: // clear macro 3728 length := c.vregoff(&p.From) 3729 offset := c.vregoff(&p.To) 3730 reg := p.To.Reg 3731 if reg == 0 { 3732 reg = o.param 3733 } 3734 if length <= 0 { 3735 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length) 3736 } 3737 for length > 0 { 3738 if offset < 0 || offset >= DISP12 { 3739 if offset >= -DISP20/2 && offset < DISP20/2 { 3740 zRXY(op_LAY, REGTMP, uint32(reg), 0, uint32(offset), asm) 3741 } else { 3742 if reg != REGTMP { 3743 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3744 } 3745 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3746 } 3747 reg = REGTMP 3748 offset = 0 3749 } 3750 size := length 3751 if size > 256 { 3752 size = 256 3753 } 3754 3755 switch size { 3756 case 1: 3757 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm) 3758 case 2: 3759 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm) 3760 case 4: 3761 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm) 3762 case 8: 3763 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm) 3764 default: 3765 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm) 3766 } 3767 3768 length -= size 3769 offset += size 3770 } 3771 3772 case 97: // store multiple 3773 rstart := p.From.Reg 3774 rend := p.Reg 3775 offset := c.regoff(&p.To) 3776 reg := p.To.Reg 3777 if reg == 0 { 3778 reg = o.param 3779 } 3780 if offset < -DISP20/2 || offset >= DISP20/2 { 3781 if reg != REGTMP { 3782 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3783 } 3784 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3785 reg = REGTMP 3786 offset = 0 3787 } 3788 switch p.As { 3789 case ASTMY: 3790 if offset >= 0 && offset < DISP12 { 3791 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3792 } else { 3793 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3794 } 3795 case ASTMG: 3796 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3797 } 3798 3799 case 98: // load multiple 3800 rstart := p.Reg 3801 rend := p.To.Reg 3802 offset := c.regoff(&p.From) 3803 reg := p.From.Reg 3804 if reg == 0 { 3805 reg = o.param 3806 } 3807 if offset < -DISP20/2 || offset >= DISP20/2 { 3808 if reg != REGTMP { 3809 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3810 } 3811 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3812 reg = REGTMP 3813 offset = 0 3814 } 3815 switch p.As { 3816 case ALMY: 3817 if offset >= 0 && offset < DISP12 { 3818 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3819 } else { 3820 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3821 } 3822 case ALMG: 3823 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3824 } 3825 3826 case 99: // interlocked load and op 3827 if p.To.Index != 0 { 3828 c.ctxt.Diag("cannot use indexed address") 3829 } 3830 offset := c.regoff(&p.To) 3831 if offset < -DISP20/2 || offset >= DISP20/2 { 3832 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset) 3833 } 3834 var opcode uint32 3835 switch p.As { 3836 case ALAA: 3837 opcode = op_LAA 3838 case ALAAG: 3839 opcode = op_LAAG 3840 case ALAAL: 3841 opcode = op_LAAL 3842 case ALAALG: 3843 opcode = op_LAALG 3844 case ALAN: 3845 opcode = op_LAN 3846 case ALANG: 3847 opcode = op_LANG 3848 case ALAX: 3849 opcode = op_LAX 3850 case ALAXG: 3851 opcode = op_LAXG 3852 case ALAO: 3853 opcode = op_LAO 3854 case ALAOG: 3855 opcode = op_LAOG 3856 } 3857 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm) 3858 3859 case 100: // VRX STORE 3860 op, m3, _ := vop(p.As) 3861 v1 := p.From.Reg 3862 if p.Reg != 0 { 3863 m3 = uint32(c.vregoff(&p.From)) 3864 v1 = p.Reg 3865 } 3866 b2 := p.To.Reg 3867 if b2 == 0 { 3868 b2 = o.param 3869 } 3870 d2 := uint32(c.vregoff(&p.To)) 3871 zVRX(op, uint32(v1), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3872 3873 case 101: // VRX LOAD 3874 op, m3, _ := vop(p.As) 3875 src := &p.From 3876 if p.From3 != nil { 3877 m3 = uint32(c.vregoff(&p.From)) 3878 src = p.From3 3879 } 3880 b2 := src.Reg 3881 if b2 == 0 { 3882 b2 = o.param 3883 } 3884 d2 := uint32(c.vregoff(src)) 3885 zVRX(op, uint32(p.To.Reg), uint32(src.Index), uint32(b2), d2, m3, asm) 3886 3887 case 102: // VRV SCATTER 3888 op, _, _ := vop(p.As) 3889 m3 := uint32(c.vregoff(&p.From)) 3890 b2 := p.To.Reg 3891 if b2 == 0 { 3892 b2 = o.param 3893 } 3894 d2 := uint32(c.vregoff(&p.To)) 3895 zVRV(op, uint32(p.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3896 3897 case 103: // VRV GATHER 3898 op, _, _ := vop(p.As) 3899 m3 := uint32(c.vregoff(&p.From)) 3900 b2 := p.From3.Reg 3901 if b2 == 0 { 3902 b2 = o.param 3903 } 3904 d2 := uint32(c.vregoff(p.From3)) 3905 zVRV(op, uint32(p.To.Reg), uint32(p.From3.Index), uint32(b2), d2, m3, asm) 3906 3907 case 104: // VRS SHIFT/ROTATE and LOAD GR FROM VR ELEMENT 3908 op, m4, _ := vop(p.As) 3909 fr := p.Reg 3910 if fr == 0 { 3911 fr = p.To.Reg 3912 } 3913 bits := uint32(c.vregoff(&p.From)) 3914 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm) 3915 3916 case 105: // VRS STORE MULTIPLE 3917 op, _, _ := vop(p.As) 3918 offset := uint32(c.vregoff(&p.To)) 3919 reg := p.To.Reg 3920 if reg == 0 { 3921 reg = o.param 3922 } 3923 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm) 3924 3925 case 106: // VRS LOAD MULTIPLE 3926 op, _, _ := vop(p.As) 3927 offset := uint32(c.vregoff(&p.From)) 3928 reg := p.From.Reg 3929 if reg == 0 { 3930 reg = o.param 3931 } 3932 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm) 3933 3934 case 107: // VRS STORE WITH LENGTH 3935 op, _, _ := vop(p.As) 3936 offset := uint32(c.vregoff(&p.To)) 3937 reg := p.To.Reg 3938 if reg == 0 { 3939 reg = o.param 3940 } 3941 zVRS(op, uint32(p.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 3942 3943 case 108: // VRS LOAD WITH LENGTH 3944 op, _, _ := vop(p.As) 3945 offset := uint32(c.vregoff(p.From3)) 3946 reg := p.From3.Reg 3947 if reg == 0 { 3948 reg = o.param 3949 } 3950 zVRS(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 3951 3952 case 109: // VRI-a 3953 op, m3, _ := vop(p.As) 3954 i2 := uint32(c.vregoff(&p.From)) 3955 if p.From3 != nil { 3956 m3 = uint32(c.vregoff(&p.From)) 3957 i2 = uint32(c.vregoff(p.From3)) 3958 } 3959 switch p.As { 3960 case AVZERO: 3961 i2 = 0 3962 case AVONE: 3963 i2 = 0xffff 3964 } 3965 zVRIa(op, uint32(p.To.Reg), i2, m3, asm) 3966 3967 case 110: 3968 op, m4, _ := vop(p.As) 3969 i2 := uint32(c.vregoff(&p.From)) 3970 i3 := uint32(c.vregoff(p.From3)) 3971 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm) 3972 3973 case 111: 3974 op, m4, _ := vop(p.As) 3975 i2 := uint32(c.vregoff(&p.From)) 3976 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm) 3977 3978 case 112: 3979 op, m5, _ := vop(p.As) 3980 i4 := uint32(c.vregoff(&p.From)) 3981 zVRId(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), i4, m5, asm) 3982 3983 case 113: 3984 op, m4, _ := vop(p.As) 3985 m5 := singleElementMask(p.As) 3986 i3 := uint32(c.vregoff(&p.From)) 3987 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm) 3988 3989 case 114: // VRR-a 3990 op, m3, m5 := vop(p.As) 3991 m4 := singleElementMask(p.As) 3992 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm) 3993 3994 case 115: // VRR-a COMPARE 3995 op, m3, m5 := vop(p.As) 3996 m4 := singleElementMask(p.As) 3997 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm) 3998 3999 case 117: // VRR-b 4000 op, m4, m5 := vop(p.As) 4001 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm) 4002 4003 case 118: // VRR-c 4004 op, m4, m6 := vop(p.As) 4005 m5 := singleElementMask(p.As) 4006 v3 := p.Reg 4007 if v3 == 0 { 4008 v3 = p.To.Reg 4009 } 4010 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm) 4011 4012 case 119: // VRR-c SHIFT/ROTATE/DIVIDE/SUB (rhs value on the left, like SLD, DIV etc.) 4013 op, m4, m6 := vop(p.As) 4014 m5 := singleElementMask(p.As) 4015 v2 := p.Reg 4016 if v2 == 0 { 4017 v2 = p.To.Reg 4018 } 4019 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm) 4020 4021 case 120: // VRR-d 4022 op, m6, _ := vop(p.As) 4023 m5 := singleElementMask(p.As) 4024 v1 := uint32(p.To.Reg) 4025 v2 := uint32(p.From.Reg) 4026 v3 := uint32(p.Reg) 4027 v4 := uint32(p.From3.Reg) 4028 zVRRd(op, v1, v2, v3, m6, m5, v4, asm) 4029 4030 case 121: // VRR-e 4031 op, m6, _ := vop(p.As) 4032 m5 := singleElementMask(p.As) 4033 v1 := uint32(p.To.Reg) 4034 v2 := uint32(p.From.Reg) 4035 v3 := uint32(p.Reg) 4036 v4 := uint32(p.From3.Reg) 4037 zVRRe(op, v1, v2, v3, m6, m5, v4, asm) 4038 4039 case 122: // VRR-f LOAD VRS FROM GRS DISJOINT 4040 op, _, _ := vop(p.As) 4041 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 4042 4043 case 123: // VPDI $m4, V2, V3, V1 4044 op, _, _ := vop(p.As) 4045 m4 := c.regoff(&p.From) 4046 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), 0, 0, uint32(m4), asm) 4047 } 4048 } 4049 4050 func (c *ctxtz) vregoff(a *obj.Addr) int64 { 4051 c.instoffset = 0 4052 if a != nil { 4053 c.aclass(a) 4054 } 4055 return c.instoffset 4056 } 4057 4058 func (c *ctxtz) regoff(a *obj.Addr) int32 { 4059 return int32(c.vregoff(a)) 4060 } 4061 4062 // zopload returns the RXY op for the given load 4063 func (c *ctxtz) zopload(a obj.As) uint32 { 4064 switch a { 4065 // fixed point load 4066 case AMOVD: 4067 return op_LG 4068 case AMOVW: 4069 return op_LGF 4070 case AMOVWZ: 4071 return op_LLGF 4072 case AMOVH: 4073 return op_LGH 4074 case AMOVHZ: 4075 return op_LLGH 4076 case AMOVB: 4077 return op_LGB 4078 case AMOVBZ: 4079 return op_LLGC 4080 4081 // floating point load 4082 case AFMOVD: 4083 return op_LDY 4084 case AFMOVS: 4085 return op_LEY 4086 4087 // byte reversed load 4088 case AMOVDBR: 4089 return op_LRVG 4090 case AMOVWBR: 4091 return op_LRV 4092 case AMOVHBR: 4093 return op_LRVH 4094 } 4095 4096 c.ctxt.Diag("unknown store opcode %v", a) 4097 return 0 4098 } 4099 4100 // zopstore returns the RXY op for the given store 4101 func (c *ctxtz) zopstore(a obj.As) uint32 { 4102 switch a { 4103 // fixed point store 4104 case AMOVD: 4105 return op_STG 4106 case AMOVW, AMOVWZ: 4107 return op_STY 4108 case AMOVH, AMOVHZ: 4109 return op_STHY 4110 case AMOVB, AMOVBZ: 4111 return op_STCY 4112 4113 // floating point store 4114 case AFMOVD: 4115 return op_STDY 4116 case AFMOVS: 4117 return op_STEY 4118 4119 // byte reversed store 4120 case AMOVDBR: 4121 return op_STRVG 4122 case AMOVWBR: 4123 return op_STRV 4124 case AMOVHBR: 4125 return op_STRVH 4126 } 4127 4128 c.ctxt.Diag("unknown store opcode %v", a) 4129 return 0 4130 } 4131 4132 // zoprre returns the RRE op for the given a 4133 func (c *ctxtz) zoprre(a obj.As) uint32 { 4134 switch a { 4135 case ACMP: 4136 return op_CGR 4137 case ACMPU: 4138 return op_CLGR 4139 case AFCMPO: //ordered 4140 return op_KDBR 4141 case AFCMPU: //unordered 4142 return op_CDBR 4143 case ACEBR: 4144 return op_CEBR 4145 } 4146 c.ctxt.Diag("unknown rre opcode %v", a) 4147 return 0 4148 } 4149 4150 // zoprr returns the RR op for the given a 4151 func (c *ctxtz) zoprr(a obj.As) uint32 { 4152 switch a { 4153 case ACMPW: 4154 return op_CR 4155 case ACMPWU: 4156 return op_CLR 4157 } 4158 c.ctxt.Diag("unknown rr opcode %v", a) 4159 return 0 4160 } 4161 4162 // zopril returns the RIL op for the given a 4163 func (c *ctxtz) zopril(a obj.As) uint32 { 4164 switch a { 4165 case ACMP: 4166 return op_CGFI 4167 case ACMPU: 4168 return op_CLGFI 4169 case ACMPW: 4170 return op_CFI 4171 case ACMPWU: 4172 return op_CLFI 4173 } 4174 c.ctxt.Diag("unknown ril opcode %v", a) 4175 return 0 4176 } 4177 4178 // z instructions sizes 4179 const ( 4180 sizeE = 2 4181 sizeI = 2 4182 sizeIE = 4 4183 sizeMII = 6 4184 sizeRI = 4 4185 sizeRI1 = 4 4186 sizeRI2 = 4 4187 sizeRI3 = 4 4188 sizeRIE = 6 4189 sizeRIE1 = 6 4190 sizeRIE2 = 6 4191 sizeRIE3 = 6 4192 sizeRIE4 = 6 4193 sizeRIE5 = 6 4194 sizeRIE6 = 6 4195 sizeRIL = 6 4196 sizeRIL1 = 6 4197 sizeRIL2 = 6 4198 sizeRIL3 = 6 4199 sizeRIS = 6 4200 sizeRR = 2 4201 sizeRRD = 4 4202 sizeRRE = 4 4203 sizeRRF = 4 4204 sizeRRF1 = 4 4205 sizeRRF2 = 4 4206 sizeRRF3 = 4 4207 sizeRRF4 = 4 4208 sizeRRF5 = 4 4209 sizeRRR = 2 4210 sizeRRS = 6 4211 sizeRS = 4 4212 sizeRS1 = 4 4213 sizeRS2 = 4 4214 sizeRSI = 4 4215 sizeRSL = 6 4216 sizeRSY = 6 4217 sizeRSY1 = 6 4218 sizeRSY2 = 6 4219 sizeRX = 4 4220 sizeRX1 = 4 4221 sizeRX2 = 4 4222 sizeRXE = 6 4223 sizeRXF = 6 4224 sizeRXY = 6 4225 sizeRXY1 = 6 4226 sizeRXY2 = 6 4227 sizeS = 4 4228 sizeSI = 4 4229 sizeSIL = 6 4230 sizeSIY = 6 4231 sizeSMI = 6 4232 sizeSS = 6 4233 sizeSS1 = 6 4234 sizeSS2 = 6 4235 sizeSS3 = 6 4236 sizeSS4 = 6 4237 sizeSS5 = 6 4238 sizeSS6 = 6 4239 sizeSSE = 6 4240 sizeSSF = 6 4241 ) 4242 4243 // instruction format variations 4244 type form int 4245 4246 const ( 4247 _a form = iota 4248 _b 4249 _c 4250 _d 4251 _e 4252 _f 4253 ) 4254 4255 func zE(op uint32, asm *[]byte) { 4256 *asm = append(*asm, uint8(op>>8), uint8(op)) 4257 } 4258 4259 func zI(op, i1 uint32, asm *[]byte) { 4260 *asm = append(*asm, uint8(op>>8), uint8(i1)) 4261 } 4262 4263 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) { 4264 *asm = append(*asm, 4265 uint8(op>>8), 4266 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F), 4267 uint8(ri2), 4268 uint8(ri3>>16), 4269 uint8(ri3>>8), 4270 uint8(ri3)) 4271 } 4272 4273 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4274 *asm = append(*asm, 4275 uint8(op>>8), 4276 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4277 uint8(i2_ri2>>8), 4278 uint8(i2_ri2)) 4279 } 4280 4281 // Expected argument values for the instruction formats. 4282 // 4283 // Format a1 a2 a3 a4 a5 a6 a7 4284 // ------------------------------------ 4285 // a r1, 0, i2, 0, 0, m3, 0 4286 // b r1, r2, ri4, 0, 0, m3, 0 4287 // c r1, m3, ri4, 0, 0, 0, i2 4288 // d r1, r3, i2, 0, 0, 0, 0 4289 // e r1, r3, ri2, 0, 0, 0, 0 4290 // f r1, r2, 0, i3, i4, 0, i5 4291 // g r1, m3, i2, 0, 0, 0, 0 4292 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) { 4293 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F)) 4294 4295 switch f { 4296 default: 4297 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2)) 4298 case _f: 4299 *asm = append(*asm, uint8(i3), uint8(i4)) 4300 } 4301 4302 switch f { 4303 case _a, _b: 4304 *asm = append(*asm, uint8(m3)<<4) 4305 default: 4306 *asm = append(*asm, uint8(i2_i5)) 4307 } 4308 4309 *asm = append(*asm, uint8(op)) 4310 } 4311 4312 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4313 if f == _a || f == _b { 4314 r1_m1 = r1_m1 - obj.RBaseS390X // this is a register base 4315 } 4316 *asm = append(*asm, 4317 uint8(op>>8), 4318 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4319 uint8(i2_ri2>>24), 4320 uint8(i2_ri2>>16), 4321 uint8(i2_ri2>>8), 4322 uint8(i2_ri2)) 4323 } 4324 4325 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) { 4326 *asm = append(*asm, 4327 uint8(op>>8), 4328 (uint8(r1)<<4)|uint8(m3&0x0F), 4329 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F), 4330 uint8(d4), 4331 uint8(i2), 4332 uint8(op)) 4333 } 4334 4335 func zRR(op, r1, r2 uint32, asm *[]byte) { 4336 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F)) 4337 } 4338 4339 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) { 4340 *asm = append(*asm, 4341 uint8(op>>8), 4342 uint8(op), 4343 uint8(r1)<<4, 4344 (uint8(r3)<<4)|uint8(r2&0x0F)) 4345 } 4346 4347 func zRRE(op, r1, r2 uint32, asm *[]byte) { 4348 *asm = append(*asm, 4349 uint8(op>>8), 4350 uint8(op), 4351 0, 4352 (uint8(r1)<<4)|uint8(r2&0x0F)) 4353 } 4354 4355 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) { 4356 *asm = append(*asm, 4357 uint8(op>>8), 4358 uint8(op), 4359 (uint8(r3_m3)<<4)|uint8(m4&0x0F), 4360 (uint8(r1)<<4)|uint8(r2&0x0F)) 4361 } 4362 4363 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) { 4364 *asm = append(*asm, 4365 uint8(op>>8), 4366 (uint8(r1)<<4)|uint8(r2&0x0F), 4367 (uint8(b4)<<4)|uint8((d4>>8)&0x0F), 4368 uint8(d4), 4369 uint8(m3)<<4, 4370 uint8(op)) 4371 } 4372 4373 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4374 *asm = append(*asm, 4375 uint8(op>>8), 4376 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4377 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4378 uint8(d2)) 4379 } 4380 4381 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) { 4382 *asm = append(*asm, 4383 uint8(op>>8), 4384 (uint8(r1)<<4)|uint8(r3&0x0F), 4385 uint8(ri2>>8), 4386 uint8(ri2)) 4387 } 4388 4389 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) { 4390 *asm = append(*asm, 4391 uint8(op>>8), 4392 uint8(l1), 4393 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4394 uint8(d2), 4395 uint8(op)) 4396 } 4397 4398 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4399 dl2 := uint16(d2) & 0x0FFF 4400 *asm = append(*asm, 4401 uint8(op>>8), 4402 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4403 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4404 uint8(dl2), 4405 uint8(d2>>12), 4406 uint8(op)) 4407 } 4408 4409 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4410 *asm = append(*asm, 4411 uint8(op>>8), 4412 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4413 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4414 uint8(d2)) 4415 } 4416 4417 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) { 4418 *asm = append(*asm, 4419 uint8(op>>8), 4420 (uint8(r1)<<4)|uint8(x2&0x0F), 4421 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4422 uint8(d2), 4423 uint8(m3)<<4, 4424 uint8(op)) 4425 } 4426 4427 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) { 4428 *asm = append(*asm, 4429 uint8(op>>8), 4430 (uint8(r3)<<4)|uint8(x2&0x0F), 4431 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4432 uint8(d2), 4433 uint8(m1)<<4, 4434 uint8(op)) 4435 } 4436 4437 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4438 dl2 := uint16(d2) & 0x0FFF 4439 *asm = append(*asm, 4440 uint8(op>>8), 4441 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4442 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4443 uint8(dl2), 4444 uint8(d2>>12), 4445 uint8(op)) 4446 } 4447 4448 func zS(op, b2, d2 uint32, asm *[]byte) { 4449 *asm = append(*asm, 4450 uint8(op>>8), 4451 uint8(op), 4452 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4453 uint8(d2)) 4454 } 4455 4456 func zSI(op, i2, b1, d1 uint32, asm *[]byte) { 4457 *asm = append(*asm, 4458 uint8(op>>8), 4459 uint8(i2), 4460 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4461 uint8(d1)) 4462 } 4463 4464 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) { 4465 *asm = append(*asm, 4466 uint8(op>>8), 4467 uint8(op), 4468 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4469 uint8(d1), 4470 uint8(i2>>8), 4471 uint8(i2)) 4472 } 4473 4474 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) { 4475 dl1 := uint16(d1) & 0x0FFF 4476 *asm = append(*asm, 4477 uint8(op>>8), 4478 uint8(i2), 4479 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F), 4480 uint8(dl1), 4481 uint8(d1>>12), 4482 uint8(op)) 4483 } 4484 4485 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) { 4486 *asm = append(*asm, 4487 uint8(op>>8), 4488 uint8(m1)<<4, 4489 (uint8(b3)<<4)|uint8((d3>>8)&0x0F), 4490 uint8(d3), 4491 uint8(ri2>>8), 4492 uint8(ri2)) 4493 } 4494 4495 // Expected argument values for the instruction formats. 4496 // 4497 // Format a1 a2 a3 a4 a5 a6 4498 // ------------------------------- 4499 // a l1, 0, b1, d1, b2, d2 4500 // b l1, l2, b1, d1, b2, d2 4501 // c l1, i3, b1, d1, b2, d2 4502 // d r1, r3, b1, d1, b2, d2 4503 // e r1, r3, b2, d2, b4, d4 4504 // f 0, l2, b1, d1, b2, d2 4505 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) { 4506 *asm = append(*asm, uint8(op>>8)) 4507 4508 switch f { 4509 case _a: 4510 *asm = append(*asm, uint8(l1_r1)) 4511 case _b, _c, _d, _e: 4512 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F)) 4513 case _f: 4514 *asm = append(*asm, uint8(l2_i3_r3)) 4515 } 4516 4517 *asm = append(*asm, 4518 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F), 4519 uint8(d1_d2), 4520 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F), 4521 uint8(d2_d4)) 4522 } 4523 4524 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) { 4525 *asm = append(*asm, 4526 uint8(op>>8), 4527 uint8(op), 4528 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4529 uint8(d1), 4530 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4531 uint8(d2)) 4532 } 4533 4534 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) { 4535 *asm = append(*asm, 4536 uint8(op>>8), 4537 (uint8(r3)<<4)|(uint8(op)&0x0F), 4538 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4539 uint8(d1), 4540 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4541 uint8(d2)) 4542 } 4543 4544 func rxb(va, vb, vc, vd uint32) uint8 { 4545 mask := uint8(0) 4546 if va >= REG_V16 && va <= REG_V31 { 4547 mask |= 0x8 4548 } 4549 if vb >= REG_V16 && vb <= REG_V31 { 4550 mask |= 0x4 4551 } 4552 if vc >= REG_V16 && vc <= REG_V31 { 4553 mask |= 0x2 4554 } 4555 if vd >= REG_V16 && vd <= REG_V31 { 4556 mask |= 0x1 4557 } 4558 return mask 4559 } 4560 4561 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) { 4562 *asm = append(*asm, 4563 uint8(op>>8), 4564 (uint8(v1)<<4)|(uint8(x2)&0xf), 4565 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4566 uint8(d2), 4567 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4568 uint8(op)) 4569 } 4570 4571 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) { 4572 *asm = append(*asm, 4573 uint8(op>>8), 4574 (uint8(v1)<<4)|(uint8(v2)&0xf), 4575 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4576 uint8(d2), 4577 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4578 uint8(op)) 4579 } 4580 4581 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) { 4582 *asm = append(*asm, 4583 uint8(op>>8), 4584 (uint8(v1)<<4)|(uint8(v3_r3)&0xf), 4585 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4586 uint8(d2), 4587 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0), 4588 uint8(op)) 4589 } 4590 4591 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) { 4592 *asm = append(*asm, 4593 uint8(op>>8), 4594 (uint8(v1)<<4)|(uint8(v2)&0xf), 4595 0, 4596 (uint8(m5)<<4)|(uint8(m4)&0xf), 4597 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4598 uint8(op)) 4599 } 4600 4601 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) { 4602 *asm = append(*asm, 4603 uint8(op>>8), 4604 (uint8(v1)<<4)|(uint8(v2)&0xf), 4605 uint8(v3)<<4, 4606 uint8(m5)<<4, 4607 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4608 uint8(op)) 4609 } 4610 4611 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) { 4612 *asm = append(*asm, 4613 uint8(op>>8), 4614 (uint8(v1)<<4)|(uint8(v2)&0xf), 4615 uint8(v3)<<4, 4616 (uint8(m6)<<4)|(uint8(m5)&0xf), 4617 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4618 uint8(op)) 4619 } 4620 4621 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) { 4622 *asm = append(*asm, 4623 uint8(op>>8), 4624 (uint8(v1)<<4)|(uint8(v2)&0xf), 4625 (uint8(v3)<<4)|(uint8(m5)&0xf), 4626 uint8(m6)<<4, 4627 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4628 uint8(op)) 4629 } 4630 4631 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) { 4632 *asm = append(*asm, 4633 uint8(op>>8), 4634 (uint8(v1)<<4)|(uint8(v2)&0xf), 4635 (uint8(v3)<<4)|(uint8(m6)&0xf), 4636 uint8(m5), 4637 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4638 uint8(op)) 4639 } 4640 4641 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) { 4642 *asm = append(*asm, 4643 uint8(op>>8), 4644 (uint8(v1)<<4)|(uint8(r2)&0xf), 4645 uint8(r3)<<4, 4646 0, 4647 rxb(v1, 0, 0, 0), 4648 uint8(op)) 4649 } 4650 4651 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) { 4652 *asm = append(*asm, 4653 uint8(op>>8), 4654 uint8(v1)<<4, 4655 uint8(i2>>8), 4656 uint8(i2), 4657 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4658 uint8(op)) 4659 } 4660 4661 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) { 4662 *asm = append(*asm, 4663 uint8(op>>8), 4664 uint8(v1)<<4, 4665 uint8(i2), 4666 uint8(i3), 4667 (uint8(m4)<<4)|rxb(v1, 0, 0, 0), 4668 uint8(op)) 4669 } 4670 4671 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) { 4672 *asm = append(*asm, 4673 uint8(op>>8), 4674 (uint8(v1)<<4)|(uint8(v3)&0xf), 4675 uint8(i2>>8), 4676 uint8(i2), 4677 (uint8(m4)<<4)|rxb(v1, v3, 0, 0), 4678 uint8(op)) 4679 } 4680 4681 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) { 4682 *asm = append(*asm, 4683 uint8(op>>8), 4684 (uint8(v1)<<4)|(uint8(v2)&0xf), 4685 uint8(v3)<<4, 4686 uint8(i4), 4687 (uint8(m5)<<4)|rxb(v1, v2, v3, 0), 4688 uint8(op)) 4689 } 4690 4691 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) { 4692 *asm = append(*asm, 4693 uint8(op>>8), 4694 (uint8(v1)<<4)|(uint8(v2)&0xf), 4695 uint8(i3>>4), 4696 (uint8(i3)<<4)|(uint8(m5)&0xf), 4697 (uint8(m4)<<4)|rxb(v1, v2, 0, 0), 4698 uint8(op)) 4699 }