github.com/sbinet/go@v0.0.0-20160827155028-54d7de7dd62b/src/cmd/compile/internal/ssa/opGen.go (about) 1 // autogenerated: do not edit! 2 // generated from gen/*Ops.go 3 4 package ssa 5 6 import ( 7 "cmd/internal/obj" 8 "cmd/internal/obj/arm" 9 "cmd/internal/obj/arm64" 10 "cmd/internal/obj/mips" 11 "cmd/internal/obj/ppc64" 12 "cmd/internal/obj/x86" 13 ) 14 15 const ( 16 BlockInvalid BlockKind = iota 17 18 Block386EQ 19 Block386NE 20 Block386LT 21 Block386LE 22 Block386GT 23 Block386GE 24 Block386ULT 25 Block386ULE 26 Block386UGT 27 Block386UGE 28 Block386EQF 29 Block386NEF 30 Block386ORD 31 Block386NAN 32 33 BlockAMD64EQ 34 BlockAMD64NE 35 BlockAMD64LT 36 BlockAMD64LE 37 BlockAMD64GT 38 BlockAMD64GE 39 BlockAMD64ULT 40 BlockAMD64ULE 41 BlockAMD64UGT 42 BlockAMD64UGE 43 BlockAMD64EQF 44 BlockAMD64NEF 45 BlockAMD64ORD 46 BlockAMD64NAN 47 48 BlockARMEQ 49 BlockARMNE 50 BlockARMLT 51 BlockARMLE 52 BlockARMGT 53 BlockARMGE 54 BlockARMULT 55 BlockARMULE 56 BlockARMUGT 57 BlockARMUGE 58 59 BlockARM64EQ 60 BlockARM64NE 61 BlockARM64LT 62 BlockARM64LE 63 BlockARM64GT 64 BlockARM64GE 65 BlockARM64ULT 66 BlockARM64ULE 67 BlockARM64UGT 68 BlockARM64UGE 69 70 BlockMIPS64EQ 71 BlockMIPS64NE 72 BlockMIPS64LTZ 73 BlockMIPS64LEZ 74 BlockMIPS64GTZ 75 BlockMIPS64GEZ 76 BlockMIPS64FPT 77 BlockMIPS64FPF 78 79 BlockPPC64EQ 80 BlockPPC64NE 81 BlockPPC64LT 82 BlockPPC64LE 83 BlockPPC64GT 84 BlockPPC64GE 85 BlockPPC64FLT 86 BlockPPC64FLE 87 BlockPPC64FGT 88 BlockPPC64FGE 89 90 BlockPlain 91 BlockIf 92 BlockCall 93 BlockDefer 94 BlockCheck 95 BlockRet 96 BlockRetJmp 97 BlockExit 98 BlockFirst 99 ) 100 101 var blockString = [...]string{ 102 BlockInvalid: "BlockInvalid", 103 104 Block386EQ: "EQ", 105 Block386NE: "NE", 106 Block386LT: "LT", 107 Block386LE: "LE", 108 Block386GT: "GT", 109 Block386GE: "GE", 110 Block386ULT: "ULT", 111 Block386ULE: "ULE", 112 Block386UGT: "UGT", 113 Block386UGE: "UGE", 114 Block386EQF: "EQF", 115 Block386NEF: "NEF", 116 Block386ORD: "ORD", 117 Block386NAN: "NAN", 118 119 BlockAMD64EQ: "EQ", 120 BlockAMD64NE: "NE", 121 BlockAMD64LT: "LT", 122 BlockAMD64LE: "LE", 123 BlockAMD64GT: "GT", 124 BlockAMD64GE: "GE", 125 BlockAMD64ULT: "ULT", 126 BlockAMD64ULE: "ULE", 127 BlockAMD64UGT: "UGT", 128 BlockAMD64UGE: "UGE", 129 BlockAMD64EQF: "EQF", 130 BlockAMD64NEF: "NEF", 131 BlockAMD64ORD: "ORD", 132 BlockAMD64NAN: "NAN", 133 134 BlockARMEQ: "EQ", 135 BlockARMNE: "NE", 136 BlockARMLT: "LT", 137 BlockARMLE: "LE", 138 BlockARMGT: "GT", 139 BlockARMGE: "GE", 140 BlockARMULT: "ULT", 141 BlockARMULE: "ULE", 142 BlockARMUGT: "UGT", 143 BlockARMUGE: "UGE", 144 145 BlockARM64EQ: "EQ", 146 BlockARM64NE: "NE", 147 BlockARM64LT: "LT", 148 BlockARM64LE: "LE", 149 BlockARM64GT: "GT", 150 BlockARM64GE: "GE", 151 BlockARM64ULT: "ULT", 152 BlockARM64ULE: "ULE", 153 BlockARM64UGT: "UGT", 154 BlockARM64UGE: "UGE", 155 156 BlockMIPS64EQ: "EQ", 157 BlockMIPS64NE: "NE", 158 BlockMIPS64LTZ: "LTZ", 159 BlockMIPS64LEZ: "LEZ", 160 BlockMIPS64GTZ: "GTZ", 161 BlockMIPS64GEZ: "GEZ", 162 BlockMIPS64FPT: "FPT", 163 BlockMIPS64FPF: "FPF", 164 165 BlockPPC64EQ: "EQ", 166 BlockPPC64NE: "NE", 167 BlockPPC64LT: "LT", 168 BlockPPC64LE: "LE", 169 BlockPPC64GT: "GT", 170 BlockPPC64GE: "GE", 171 BlockPPC64FLT: "FLT", 172 BlockPPC64FLE: "FLE", 173 BlockPPC64FGT: "FGT", 174 BlockPPC64FGE: "FGE", 175 176 BlockPlain: "Plain", 177 BlockIf: "If", 178 BlockCall: "Call", 179 BlockDefer: "Defer", 180 BlockCheck: "Check", 181 BlockRet: "Ret", 182 BlockRetJmp: "RetJmp", 183 BlockExit: "Exit", 184 BlockFirst: "First", 185 } 186 187 func (k BlockKind) String() string { return blockString[k] } 188 189 const ( 190 OpInvalid Op = iota 191 192 Op386ADDSS 193 Op386ADDSD 194 Op386SUBSS 195 Op386SUBSD 196 Op386MULSS 197 Op386MULSD 198 Op386DIVSS 199 Op386DIVSD 200 Op386MOVSSload 201 Op386MOVSDload 202 Op386MOVSSconst 203 Op386MOVSDconst 204 Op386MOVSSloadidx1 205 Op386MOVSSloadidx4 206 Op386MOVSDloadidx1 207 Op386MOVSDloadidx8 208 Op386MOVSSstore 209 Op386MOVSDstore 210 Op386MOVSSstoreidx1 211 Op386MOVSSstoreidx4 212 Op386MOVSDstoreidx1 213 Op386MOVSDstoreidx8 214 Op386ADDL 215 Op386ADDLconst 216 Op386ADDLcarry 217 Op386ADDLconstcarry 218 Op386ADCL 219 Op386ADCLconst 220 Op386SUBL 221 Op386SUBLconst 222 Op386SUBLcarry 223 Op386SUBLconstcarry 224 Op386SBBL 225 Op386SBBLconst 226 Op386MULL 227 Op386MULLconst 228 Op386HMULL 229 Op386HMULLU 230 Op386HMULW 231 Op386HMULB 232 Op386HMULWU 233 Op386HMULBU 234 Op386MULLQU 235 Op386DIVL 236 Op386DIVW 237 Op386DIVLU 238 Op386DIVWU 239 Op386MODL 240 Op386MODW 241 Op386MODLU 242 Op386MODWU 243 Op386ANDL 244 Op386ANDLconst 245 Op386ORL 246 Op386ORLconst 247 Op386XORL 248 Op386XORLconst 249 Op386CMPL 250 Op386CMPW 251 Op386CMPB 252 Op386CMPLconst 253 Op386CMPWconst 254 Op386CMPBconst 255 Op386UCOMISS 256 Op386UCOMISD 257 Op386TESTL 258 Op386TESTW 259 Op386TESTB 260 Op386TESTLconst 261 Op386TESTWconst 262 Op386TESTBconst 263 Op386SHLL 264 Op386SHLLconst 265 Op386SHRL 266 Op386SHRW 267 Op386SHRB 268 Op386SHRLconst 269 Op386SHRWconst 270 Op386SHRBconst 271 Op386SARL 272 Op386SARW 273 Op386SARB 274 Op386SARLconst 275 Op386SARWconst 276 Op386SARBconst 277 Op386ROLLconst 278 Op386ROLWconst 279 Op386ROLBconst 280 Op386NEGL 281 Op386NOTL 282 Op386BSFL 283 Op386BSFW 284 Op386BSRL 285 Op386BSRW 286 Op386BSWAPL 287 Op386SQRTSD 288 Op386SBBLcarrymask 289 Op386SETEQ 290 Op386SETNE 291 Op386SETL 292 Op386SETLE 293 Op386SETG 294 Op386SETGE 295 Op386SETB 296 Op386SETBE 297 Op386SETA 298 Op386SETAE 299 Op386SETEQF 300 Op386SETNEF 301 Op386SETORD 302 Op386SETNAN 303 Op386SETGF 304 Op386SETGEF 305 Op386MOVBLSX 306 Op386MOVBLZX 307 Op386MOVWLSX 308 Op386MOVWLZX 309 Op386MOVLconst 310 Op386CVTTSD2SL 311 Op386CVTTSS2SL 312 Op386CVTSL2SS 313 Op386CVTSL2SD 314 Op386CVTSD2SS 315 Op386CVTSS2SD 316 Op386PXOR 317 Op386LEAL 318 Op386LEAL1 319 Op386LEAL2 320 Op386LEAL4 321 Op386LEAL8 322 Op386MOVBload 323 Op386MOVBLSXload 324 Op386MOVWload 325 Op386MOVWLSXload 326 Op386MOVLload 327 Op386MOVBstore 328 Op386MOVWstore 329 Op386MOVLstore 330 Op386MOVBloadidx1 331 Op386MOVWloadidx1 332 Op386MOVWloadidx2 333 Op386MOVLloadidx1 334 Op386MOVLloadidx4 335 Op386MOVBstoreidx1 336 Op386MOVWstoreidx1 337 Op386MOVWstoreidx2 338 Op386MOVLstoreidx1 339 Op386MOVLstoreidx4 340 Op386MOVBstoreconst 341 Op386MOVWstoreconst 342 Op386MOVLstoreconst 343 Op386MOVBstoreconstidx1 344 Op386MOVWstoreconstidx1 345 Op386MOVWstoreconstidx2 346 Op386MOVLstoreconstidx1 347 Op386MOVLstoreconstidx4 348 Op386DUFFZERO 349 Op386REPSTOSL 350 Op386CALLstatic 351 Op386CALLclosure 352 Op386CALLdefer 353 Op386CALLgo 354 Op386CALLinter 355 Op386DUFFCOPY 356 Op386REPMOVSL 357 Op386InvertFlags 358 Op386LoweredGetG 359 Op386LoweredGetClosurePtr 360 Op386LoweredNilCheck 361 Op386MOVLconvert 362 Op386FlagEQ 363 Op386FlagLT_ULT 364 Op386FlagLT_UGT 365 Op386FlagGT_UGT 366 Op386FlagGT_ULT 367 Op386FCHS 368 Op386MOVSSconst1 369 Op386MOVSDconst1 370 Op386MOVSSconst2 371 Op386MOVSDconst2 372 373 OpAMD64ADDSS 374 OpAMD64ADDSD 375 OpAMD64SUBSS 376 OpAMD64SUBSD 377 OpAMD64MULSS 378 OpAMD64MULSD 379 OpAMD64DIVSS 380 OpAMD64DIVSD 381 OpAMD64MOVSSload 382 OpAMD64MOVSDload 383 OpAMD64MOVSSconst 384 OpAMD64MOVSDconst 385 OpAMD64MOVSSloadidx1 386 OpAMD64MOVSSloadidx4 387 OpAMD64MOVSDloadidx1 388 OpAMD64MOVSDloadidx8 389 OpAMD64MOVSSstore 390 OpAMD64MOVSDstore 391 OpAMD64MOVSSstoreidx1 392 OpAMD64MOVSSstoreidx4 393 OpAMD64MOVSDstoreidx1 394 OpAMD64MOVSDstoreidx8 395 OpAMD64ADDQ 396 OpAMD64ADDL 397 OpAMD64ADDQconst 398 OpAMD64ADDLconst 399 OpAMD64SUBQ 400 OpAMD64SUBL 401 OpAMD64SUBQconst 402 OpAMD64SUBLconst 403 OpAMD64MULQ 404 OpAMD64MULL 405 OpAMD64MULQconst 406 OpAMD64MULLconst 407 OpAMD64HMULQ 408 OpAMD64HMULL 409 OpAMD64HMULW 410 OpAMD64HMULB 411 OpAMD64HMULQU 412 OpAMD64HMULLU 413 OpAMD64HMULWU 414 OpAMD64HMULBU 415 OpAMD64AVGQU 416 OpAMD64DIVQ 417 OpAMD64DIVL 418 OpAMD64DIVW 419 OpAMD64DIVQU 420 OpAMD64DIVLU 421 OpAMD64DIVWU 422 OpAMD64ANDQ 423 OpAMD64ANDL 424 OpAMD64ANDQconst 425 OpAMD64ANDLconst 426 OpAMD64ORQ 427 OpAMD64ORL 428 OpAMD64ORQconst 429 OpAMD64ORLconst 430 OpAMD64XORQ 431 OpAMD64XORL 432 OpAMD64XORQconst 433 OpAMD64XORLconst 434 OpAMD64CMPQ 435 OpAMD64CMPL 436 OpAMD64CMPW 437 OpAMD64CMPB 438 OpAMD64CMPQconst 439 OpAMD64CMPLconst 440 OpAMD64CMPWconst 441 OpAMD64CMPBconst 442 OpAMD64UCOMISS 443 OpAMD64UCOMISD 444 OpAMD64TESTQ 445 OpAMD64TESTL 446 OpAMD64TESTW 447 OpAMD64TESTB 448 OpAMD64TESTQconst 449 OpAMD64TESTLconst 450 OpAMD64TESTWconst 451 OpAMD64TESTBconst 452 OpAMD64SHLQ 453 OpAMD64SHLL 454 OpAMD64SHLQconst 455 OpAMD64SHLLconst 456 OpAMD64SHRQ 457 OpAMD64SHRL 458 OpAMD64SHRW 459 OpAMD64SHRB 460 OpAMD64SHRQconst 461 OpAMD64SHRLconst 462 OpAMD64SHRWconst 463 OpAMD64SHRBconst 464 OpAMD64SARQ 465 OpAMD64SARL 466 OpAMD64SARW 467 OpAMD64SARB 468 OpAMD64SARQconst 469 OpAMD64SARLconst 470 OpAMD64SARWconst 471 OpAMD64SARBconst 472 OpAMD64ROLQconst 473 OpAMD64ROLLconst 474 OpAMD64ROLWconst 475 OpAMD64ROLBconst 476 OpAMD64NEGQ 477 OpAMD64NEGL 478 OpAMD64NOTQ 479 OpAMD64NOTL 480 OpAMD64BSFQ 481 OpAMD64BSFL 482 OpAMD64CMOVQEQ 483 OpAMD64CMOVLEQ 484 OpAMD64BSWAPQ 485 OpAMD64BSWAPL 486 OpAMD64SQRTSD 487 OpAMD64SBBQcarrymask 488 OpAMD64SBBLcarrymask 489 OpAMD64SETEQ 490 OpAMD64SETNE 491 OpAMD64SETL 492 OpAMD64SETLE 493 OpAMD64SETG 494 OpAMD64SETGE 495 OpAMD64SETB 496 OpAMD64SETBE 497 OpAMD64SETA 498 OpAMD64SETAE 499 OpAMD64SETEQF 500 OpAMD64SETNEF 501 OpAMD64SETORD 502 OpAMD64SETNAN 503 OpAMD64SETGF 504 OpAMD64SETGEF 505 OpAMD64MOVBQSX 506 OpAMD64MOVBQZX 507 OpAMD64MOVWQSX 508 OpAMD64MOVWQZX 509 OpAMD64MOVLQSX 510 OpAMD64MOVLQZX 511 OpAMD64MOVLconst 512 OpAMD64MOVQconst 513 OpAMD64CVTTSD2SL 514 OpAMD64CVTTSD2SQ 515 OpAMD64CVTTSS2SL 516 OpAMD64CVTTSS2SQ 517 OpAMD64CVTSL2SS 518 OpAMD64CVTSL2SD 519 OpAMD64CVTSQ2SS 520 OpAMD64CVTSQ2SD 521 OpAMD64CVTSD2SS 522 OpAMD64CVTSS2SD 523 OpAMD64PXOR 524 OpAMD64LEAQ 525 OpAMD64LEAQ1 526 OpAMD64LEAQ2 527 OpAMD64LEAQ4 528 OpAMD64LEAQ8 529 OpAMD64LEAL 530 OpAMD64MOVBload 531 OpAMD64MOVBQSXload 532 OpAMD64MOVWload 533 OpAMD64MOVWQSXload 534 OpAMD64MOVLload 535 OpAMD64MOVLQSXload 536 OpAMD64MOVQload 537 OpAMD64MOVBstore 538 OpAMD64MOVWstore 539 OpAMD64MOVLstore 540 OpAMD64MOVQstore 541 OpAMD64MOVOload 542 OpAMD64MOVOstore 543 OpAMD64MOVBloadidx1 544 OpAMD64MOVWloadidx1 545 OpAMD64MOVWloadidx2 546 OpAMD64MOVLloadidx1 547 OpAMD64MOVLloadidx4 548 OpAMD64MOVQloadidx1 549 OpAMD64MOVQloadidx8 550 OpAMD64MOVBstoreidx1 551 OpAMD64MOVWstoreidx1 552 OpAMD64MOVWstoreidx2 553 OpAMD64MOVLstoreidx1 554 OpAMD64MOVLstoreidx4 555 OpAMD64MOVQstoreidx1 556 OpAMD64MOVQstoreidx8 557 OpAMD64MOVBstoreconst 558 OpAMD64MOVWstoreconst 559 OpAMD64MOVLstoreconst 560 OpAMD64MOVQstoreconst 561 OpAMD64MOVBstoreconstidx1 562 OpAMD64MOVWstoreconstidx1 563 OpAMD64MOVWstoreconstidx2 564 OpAMD64MOVLstoreconstidx1 565 OpAMD64MOVLstoreconstidx4 566 OpAMD64MOVQstoreconstidx1 567 OpAMD64MOVQstoreconstidx8 568 OpAMD64DUFFZERO 569 OpAMD64MOVOconst 570 OpAMD64REPSTOSQ 571 OpAMD64CALLstatic 572 OpAMD64CALLclosure 573 OpAMD64CALLdefer 574 OpAMD64CALLgo 575 OpAMD64CALLinter 576 OpAMD64DUFFCOPY 577 OpAMD64REPMOVSQ 578 OpAMD64InvertFlags 579 OpAMD64LoweredGetG 580 OpAMD64LoweredGetClosurePtr 581 OpAMD64LoweredNilCheck 582 OpAMD64MOVQconvert 583 OpAMD64MOVLconvert 584 OpAMD64FlagEQ 585 OpAMD64FlagLT_ULT 586 OpAMD64FlagLT_UGT 587 OpAMD64FlagGT_UGT 588 OpAMD64FlagGT_ULT 589 OpAMD64MOVLatomicload 590 OpAMD64MOVQatomicload 591 OpAMD64XCHGL 592 OpAMD64XCHGQ 593 594 OpARMADD 595 OpARMADDconst 596 OpARMSUB 597 OpARMSUBconst 598 OpARMRSB 599 OpARMRSBconst 600 OpARMMUL 601 OpARMHMUL 602 OpARMHMULU 603 OpARMDIV 604 OpARMDIVU 605 OpARMMOD 606 OpARMMODU 607 OpARMADDS 608 OpARMADDSconst 609 OpARMADC 610 OpARMADCconst 611 OpARMSUBS 612 OpARMSUBSconst 613 OpARMRSBSconst 614 OpARMSBC 615 OpARMSBCconst 616 OpARMRSCconst 617 OpARMMULLU 618 OpARMMULA 619 OpARMADDF 620 OpARMADDD 621 OpARMSUBF 622 OpARMSUBD 623 OpARMMULF 624 OpARMMULD 625 OpARMDIVF 626 OpARMDIVD 627 OpARMAND 628 OpARMANDconst 629 OpARMOR 630 OpARMORconst 631 OpARMXOR 632 OpARMXORconst 633 OpARMBIC 634 OpARMBICconst 635 OpARMMVN 636 OpARMNEGF 637 OpARMNEGD 638 OpARMSQRTD 639 OpARMSLL 640 OpARMSLLconst 641 OpARMSRL 642 OpARMSRLconst 643 OpARMSRA 644 OpARMSRAconst 645 OpARMSRRconst 646 OpARMADDshiftLL 647 OpARMADDshiftRL 648 OpARMADDshiftRA 649 OpARMSUBshiftLL 650 OpARMSUBshiftRL 651 OpARMSUBshiftRA 652 OpARMRSBshiftLL 653 OpARMRSBshiftRL 654 OpARMRSBshiftRA 655 OpARMANDshiftLL 656 OpARMANDshiftRL 657 OpARMANDshiftRA 658 OpARMORshiftLL 659 OpARMORshiftRL 660 OpARMORshiftRA 661 OpARMXORshiftLL 662 OpARMXORshiftRL 663 OpARMXORshiftRA 664 OpARMBICshiftLL 665 OpARMBICshiftRL 666 OpARMBICshiftRA 667 OpARMMVNshiftLL 668 OpARMMVNshiftRL 669 OpARMMVNshiftRA 670 OpARMADCshiftLL 671 OpARMADCshiftRL 672 OpARMADCshiftRA 673 OpARMSBCshiftLL 674 OpARMSBCshiftRL 675 OpARMSBCshiftRA 676 OpARMRSCshiftLL 677 OpARMRSCshiftRL 678 OpARMRSCshiftRA 679 OpARMADDSshiftLL 680 OpARMADDSshiftRL 681 OpARMADDSshiftRA 682 OpARMSUBSshiftLL 683 OpARMSUBSshiftRL 684 OpARMSUBSshiftRA 685 OpARMRSBSshiftLL 686 OpARMRSBSshiftRL 687 OpARMRSBSshiftRA 688 OpARMADDshiftLLreg 689 OpARMADDshiftRLreg 690 OpARMADDshiftRAreg 691 OpARMSUBshiftLLreg 692 OpARMSUBshiftRLreg 693 OpARMSUBshiftRAreg 694 OpARMRSBshiftLLreg 695 OpARMRSBshiftRLreg 696 OpARMRSBshiftRAreg 697 OpARMANDshiftLLreg 698 OpARMANDshiftRLreg 699 OpARMANDshiftRAreg 700 OpARMORshiftLLreg 701 OpARMORshiftRLreg 702 OpARMORshiftRAreg 703 OpARMXORshiftLLreg 704 OpARMXORshiftRLreg 705 OpARMXORshiftRAreg 706 OpARMBICshiftLLreg 707 OpARMBICshiftRLreg 708 OpARMBICshiftRAreg 709 OpARMMVNshiftLLreg 710 OpARMMVNshiftRLreg 711 OpARMMVNshiftRAreg 712 OpARMADCshiftLLreg 713 OpARMADCshiftRLreg 714 OpARMADCshiftRAreg 715 OpARMSBCshiftLLreg 716 OpARMSBCshiftRLreg 717 OpARMSBCshiftRAreg 718 OpARMRSCshiftLLreg 719 OpARMRSCshiftRLreg 720 OpARMRSCshiftRAreg 721 OpARMADDSshiftLLreg 722 OpARMADDSshiftRLreg 723 OpARMADDSshiftRAreg 724 OpARMSUBSshiftLLreg 725 OpARMSUBSshiftRLreg 726 OpARMSUBSshiftRAreg 727 OpARMRSBSshiftLLreg 728 OpARMRSBSshiftRLreg 729 OpARMRSBSshiftRAreg 730 OpARMCMP 731 OpARMCMPconst 732 OpARMCMN 733 OpARMCMNconst 734 OpARMTST 735 OpARMTSTconst 736 OpARMTEQ 737 OpARMTEQconst 738 OpARMCMPF 739 OpARMCMPD 740 OpARMCMPshiftLL 741 OpARMCMPshiftRL 742 OpARMCMPshiftRA 743 OpARMCMPshiftLLreg 744 OpARMCMPshiftRLreg 745 OpARMCMPshiftRAreg 746 OpARMCMPF0 747 OpARMCMPD0 748 OpARMMOVWconst 749 OpARMMOVFconst 750 OpARMMOVDconst 751 OpARMMOVWaddr 752 OpARMMOVBload 753 OpARMMOVBUload 754 OpARMMOVHload 755 OpARMMOVHUload 756 OpARMMOVWload 757 OpARMMOVFload 758 OpARMMOVDload 759 OpARMMOVBstore 760 OpARMMOVHstore 761 OpARMMOVWstore 762 OpARMMOVFstore 763 OpARMMOVDstore 764 OpARMMOVWloadidx 765 OpARMMOVWloadshiftLL 766 OpARMMOVWloadshiftRL 767 OpARMMOVWloadshiftRA 768 OpARMMOVWstoreidx 769 OpARMMOVWstoreshiftLL 770 OpARMMOVWstoreshiftRL 771 OpARMMOVWstoreshiftRA 772 OpARMMOVBreg 773 OpARMMOVBUreg 774 OpARMMOVHreg 775 OpARMMOVHUreg 776 OpARMMOVWreg 777 OpARMMOVWnop 778 OpARMMOVWF 779 OpARMMOVWD 780 OpARMMOVWUF 781 OpARMMOVWUD 782 OpARMMOVFW 783 OpARMMOVDW 784 OpARMMOVFWU 785 OpARMMOVDWU 786 OpARMMOVFD 787 OpARMMOVDF 788 OpARMCMOVWHSconst 789 OpARMCMOVWLSconst 790 OpARMSRAcond 791 OpARMCALLstatic 792 OpARMCALLclosure 793 OpARMCALLdefer 794 OpARMCALLgo 795 OpARMCALLinter 796 OpARMLoweredNilCheck 797 OpARMEqual 798 OpARMNotEqual 799 OpARMLessThan 800 OpARMLessEqual 801 OpARMGreaterThan 802 OpARMGreaterEqual 803 OpARMLessThanU 804 OpARMLessEqualU 805 OpARMGreaterThanU 806 OpARMGreaterEqualU 807 OpARMDUFFZERO 808 OpARMDUFFCOPY 809 OpARMLoweredZero 810 OpARMLoweredMove 811 OpARMLoweredGetClosurePtr 812 OpARMMOVWconvert 813 OpARMFlagEQ 814 OpARMFlagLT_ULT 815 OpARMFlagLT_UGT 816 OpARMFlagGT_UGT 817 OpARMFlagGT_ULT 818 OpARMInvertFlags 819 820 OpARM64ADD 821 OpARM64ADDconst 822 OpARM64SUB 823 OpARM64SUBconst 824 OpARM64MUL 825 OpARM64MULW 826 OpARM64MULH 827 OpARM64UMULH 828 OpARM64MULL 829 OpARM64UMULL 830 OpARM64DIV 831 OpARM64UDIV 832 OpARM64DIVW 833 OpARM64UDIVW 834 OpARM64MOD 835 OpARM64UMOD 836 OpARM64MODW 837 OpARM64UMODW 838 OpARM64FADDS 839 OpARM64FADDD 840 OpARM64FSUBS 841 OpARM64FSUBD 842 OpARM64FMULS 843 OpARM64FMULD 844 OpARM64FDIVS 845 OpARM64FDIVD 846 OpARM64AND 847 OpARM64ANDconst 848 OpARM64OR 849 OpARM64ORconst 850 OpARM64XOR 851 OpARM64XORconst 852 OpARM64BIC 853 OpARM64BICconst 854 OpARM64MVN 855 OpARM64NEG 856 OpARM64FNEGS 857 OpARM64FNEGD 858 OpARM64FSQRTD 859 OpARM64REV 860 OpARM64REVW 861 OpARM64REV16W 862 OpARM64SLL 863 OpARM64SLLconst 864 OpARM64SRL 865 OpARM64SRLconst 866 OpARM64SRA 867 OpARM64SRAconst 868 OpARM64RORconst 869 OpARM64RORWconst 870 OpARM64CMP 871 OpARM64CMPconst 872 OpARM64CMPW 873 OpARM64CMPWconst 874 OpARM64CMN 875 OpARM64CMNconst 876 OpARM64CMNW 877 OpARM64CMNWconst 878 OpARM64FCMPS 879 OpARM64FCMPD 880 OpARM64ADDshiftLL 881 OpARM64ADDshiftRL 882 OpARM64ADDshiftRA 883 OpARM64SUBshiftLL 884 OpARM64SUBshiftRL 885 OpARM64SUBshiftRA 886 OpARM64ANDshiftLL 887 OpARM64ANDshiftRL 888 OpARM64ANDshiftRA 889 OpARM64ORshiftLL 890 OpARM64ORshiftRL 891 OpARM64ORshiftRA 892 OpARM64XORshiftLL 893 OpARM64XORshiftRL 894 OpARM64XORshiftRA 895 OpARM64BICshiftLL 896 OpARM64BICshiftRL 897 OpARM64BICshiftRA 898 OpARM64CMPshiftLL 899 OpARM64CMPshiftRL 900 OpARM64CMPshiftRA 901 OpARM64MOVDconst 902 OpARM64FMOVSconst 903 OpARM64FMOVDconst 904 OpARM64MOVDaddr 905 OpARM64MOVBload 906 OpARM64MOVBUload 907 OpARM64MOVHload 908 OpARM64MOVHUload 909 OpARM64MOVWload 910 OpARM64MOVWUload 911 OpARM64MOVDload 912 OpARM64FMOVSload 913 OpARM64FMOVDload 914 OpARM64MOVBstore 915 OpARM64MOVHstore 916 OpARM64MOVWstore 917 OpARM64MOVDstore 918 OpARM64FMOVSstore 919 OpARM64FMOVDstore 920 OpARM64MOVBstorezero 921 OpARM64MOVHstorezero 922 OpARM64MOVWstorezero 923 OpARM64MOVDstorezero 924 OpARM64MOVBreg 925 OpARM64MOVBUreg 926 OpARM64MOVHreg 927 OpARM64MOVHUreg 928 OpARM64MOVWreg 929 OpARM64MOVWUreg 930 OpARM64MOVDreg 931 OpARM64MOVDnop 932 OpARM64SCVTFWS 933 OpARM64SCVTFWD 934 OpARM64UCVTFWS 935 OpARM64UCVTFWD 936 OpARM64SCVTFS 937 OpARM64SCVTFD 938 OpARM64UCVTFS 939 OpARM64UCVTFD 940 OpARM64FCVTZSSW 941 OpARM64FCVTZSDW 942 OpARM64FCVTZUSW 943 OpARM64FCVTZUDW 944 OpARM64FCVTZSS 945 OpARM64FCVTZSD 946 OpARM64FCVTZUS 947 OpARM64FCVTZUD 948 OpARM64FCVTSD 949 OpARM64FCVTDS 950 OpARM64CSELULT 951 OpARM64CSELULT0 952 OpARM64CALLstatic 953 OpARM64CALLclosure 954 OpARM64CALLdefer 955 OpARM64CALLgo 956 OpARM64CALLinter 957 OpARM64LoweredNilCheck 958 OpARM64Equal 959 OpARM64NotEqual 960 OpARM64LessThan 961 OpARM64LessEqual 962 OpARM64GreaterThan 963 OpARM64GreaterEqual 964 OpARM64LessThanU 965 OpARM64LessEqualU 966 OpARM64GreaterThanU 967 OpARM64GreaterEqualU 968 OpARM64DUFFZERO 969 OpARM64LoweredZero 970 OpARM64LoweredMove 971 OpARM64LoweredGetClosurePtr 972 OpARM64MOVDconvert 973 OpARM64FlagEQ 974 OpARM64FlagLT_ULT 975 OpARM64FlagLT_UGT 976 OpARM64FlagGT_UGT 977 OpARM64FlagGT_ULT 978 OpARM64InvertFlags 979 980 OpMIPS64ADDV 981 OpMIPS64ADDVconst 982 OpMIPS64SUBV 983 OpMIPS64SUBVconst 984 OpMIPS64MULV 985 OpMIPS64MULVU 986 OpMIPS64DIVV 987 OpMIPS64DIVVU 988 OpMIPS64ADDF 989 OpMIPS64ADDD 990 OpMIPS64SUBF 991 OpMIPS64SUBD 992 OpMIPS64MULF 993 OpMIPS64MULD 994 OpMIPS64DIVF 995 OpMIPS64DIVD 996 OpMIPS64AND 997 OpMIPS64ANDconst 998 OpMIPS64OR 999 OpMIPS64ORconst 1000 OpMIPS64XOR 1001 OpMIPS64XORconst 1002 OpMIPS64NOR 1003 OpMIPS64NORconst 1004 OpMIPS64NEGV 1005 OpMIPS64NEGF 1006 OpMIPS64NEGD 1007 OpMIPS64SLLV 1008 OpMIPS64SLLVconst 1009 OpMIPS64SRLV 1010 OpMIPS64SRLVconst 1011 OpMIPS64SRAV 1012 OpMIPS64SRAVconst 1013 OpMIPS64SGT 1014 OpMIPS64SGTconst 1015 OpMIPS64SGTU 1016 OpMIPS64SGTUconst 1017 OpMIPS64CMPEQF 1018 OpMIPS64CMPEQD 1019 OpMIPS64CMPGEF 1020 OpMIPS64CMPGED 1021 OpMIPS64CMPGTF 1022 OpMIPS64CMPGTD 1023 OpMIPS64MOVVconst 1024 OpMIPS64MOVFconst 1025 OpMIPS64MOVDconst 1026 OpMIPS64MOVVaddr 1027 OpMIPS64MOVBload 1028 OpMIPS64MOVBUload 1029 OpMIPS64MOVHload 1030 OpMIPS64MOVHUload 1031 OpMIPS64MOVWload 1032 OpMIPS64MOVWUload 1033 OpMIPS64MOVVload 1034 OpMIPS64MOVFload 1035 OpMIPS64MOVDload 1036 OpMIPS64MOVBstore 1037 OpMIPS64MOVHstore 1038 OpMIPS64MOVWstore 1039 OpMIPS64MOVVstore 1040 OpMIPS64MOVFstore 1041 OpMIPS64MOVDstore 1042 OpMIPS64MOVBstorezero 1043 OpMIPS64MOVHstorezero 1044 OpMIPS64MOVWstorezero 1045 OpMIPS64MOVVstorezero 1046 OpMIPS64MOVBreg 1047 OpMIPS64MOVBUreg 1048 OpMIPS64MOVHreg 1049 OpMIPS64MOVHUreg 1050 OpMIPS64MOVWreg 1051 OpMIPS64MOVWUreg 1052 OpMIPS64MOVVreg 1053 OpMIPS64MOVVnop 1054 OpMIPS64MOVWF 1055 OpMIPS64MOVWD 1056 OpMIPS64MOVVF 1057 OpMIPS64MOVVD 1058 OpMIPS64TRUNCFW 1059 OpMIPS64TRUNCDW 1060 OpMIPS64TRUNCFV 1061 OpMIPS64TRUNCDV 1062 OpMIPS64MOVFD 1063 OpMIPS64MOVDF 1064 OpMIPS64CALLstatic 1065 OpMIPS64CALLclosure 1066 OpMIPS64CALLdefer 1067 OpMIPS64CALLgo 1068 OpMIPS64CALLinter 1069 OpMIPS64DUFFZERO 1070 OpMIPS64LoweredZero 1071 OpMIPS64LoweredMove 1072 OpMIPS64LoweredNilCheck 1073 OpMIPS64FPFlagTrue 1074 OpMIPS64FPFlagFalse 1075 OpMIPS64LoweredGetClosurePtr 1076 OpMIPS64MOVVconvert 1077 1078 OpPPC64ADD 1079 OpPPC64ADDconst 1080 OpPPC64FADD 1081 OpPPC64FADDS 1082 OpPPC64SUB 1083 OpPPC64FSUB 1084 OpPPC64FSUBS 1085 OpPPC64MULLD 1086 OpPPC64MULLW 1087 OpPPC64MULHD 1088 OpPPC64MULHW 1089 OpPPC64MULHDU 1090 OpPPC64MULHWU 1091 OpPPC64FMUL 1092 OpPPC64FMULS 1093 OpPPC64SRAD 1094 OpPPC64SRAW 1095 OpPPC64SRD 1096 OpPPC64SRW 1097 OpPPC64SLD 1098 OpPPC64SLW 1099 OpPPC64ADDconstForCarry 1100 OpPPC64MaskIfNotCarry 1101 OpPPC64SRADconst 1102 OpPPC64SRAWconst 1103 OpPPC64SRDconst 1104 OpPPC64SRWconst 1105 OpPPC64SLDconst 1106 OpPPC64SLWconst 1107 OpPPC64FDIV 1108 OpPPC64FDIVS 1109 OpPPC64DIVD 1110 OpPPC64DIVW 1111 OpPPC64DIVDU 1112 OpPPC64DIVWU 1113 OpPPC64FCTIDZ 1114 OpPPC64FCTIWZ 1115 OpPPC64FCFID 1116 OpPPC64FRSP 1117 OpPPC64Xf2i64 1118 OpPPC64Xi2f64 1119 OpPPC64AND 1120 OpPPC64ANDN 1121 OpPPC64OR 1122 OpPPC64ORN 1123 OpPPC64XOR 1124 OpPPC64EQV 1125 OpPPC64NEG 1126 OpPPC64FNEG 1127 OpPPC64FSQRT 1128 OpPPC64FSQRTS 1129 OpPPC64ORconst 1130 OpPPC64XORconst 1131 OpPPC64ANDconst 1132 OpPPC64MOVBreg 1133 OpPPC64MOVBZreg 1134 OpPPC64MOVHreg 1135 OpPPC64MOVHZreg 1136 OpPPC64MOVWreg 1137 OpPPC64MOVWZreg 1138 OpPPC64MOVBload 1139 OpPPC64MOVBZload 1140 OpPPC64MOVHload 1141 OpPPC64MOVHZload 1142 OpPPC64MOVWload 1143 OpPPC64MOVWZload 1144 OpPPC64MOVDload 1145 OpPPC64FMOVDload 1146 OpPPC64FMOVSload 1147 OpPPC64MOVBstore 1148 OpPPC64MOVHstore 1149 OpPPC64MOVWstore 1150 OpPPC64MOVDstore 1151 OpPPC64FMOVDstore 1152 OpPPC64FMOVSstore 1153 OpPPC64MOVBstorezero 1154 OpPPC64MOVHstorezero 1155 OpPPC64MOVWstorezero 1156 OpPPC64MOVDstorezero 1157 OpPPC64MOVDaddr 1158 OpPPC64MOVDconst 1159 OpPPC64MOVWconst 1160 OpPPC64FMOVDconst 1161 OpPPC64FMOVSconst 1162 OpPPC64FCMPU 1163 OpPPC64CMP 1164 OpPPC64CMPU 1165 OpPPC64CMPW 1166 OpPPC64CMPWU 1167 OpPPC64CMPconst 1168 OpPPC64CMPUconst 1169 OpPPC64CMPWconst 1170 OpPPC64CMPWUconst 1171 OpPPC64Equal 1172 OpPPC64NotEqual 1173 OpPPC64LessThan 1174 OpPPC64FLessThan 1175 OpPPC64LessEqual 1176 OpPPC64FLessEqual 1177 OpPPC64GreaterThan 1178 OpPPC64FGreaterThan 1179 OpPPC64GreaterEqual 1180 OpPPC64FGreaterEqual 1181 OpPPC64LoweredGetClosurePtr 1182 OpPPC64LoweredNilCheck 1183 OpPPC64MOVDconvert 1184 OpPPC64CALLstatic 1185 OpPPC64CALLclosure 1186 OpPPC64CALLdefer 1187 OpPPC64CALLgo 1188 OpPPC64CALLinter 1189 OpPPC64LoweredZero 1190 OpPPC64LoweredMove 1191 OpPPC64InvertFlags 1192 OpPPC64FlagEQ 1193 OpPPC64FlagLT 1194 OpPPC64FlagGT 1195 1196 OpAdd8 1197 OpAdd16 1198 OpAdd32 1199 OpAdd64 1200 OpAddPtr 1201 OpAdd32F 1202 OpAdd64F 1203 OpSub8 1204 OpSub16 1205 OpSub32 1206 OpSub64 1207 OpSubPtr 1208 OpSub32F 1209 OpSub64F 1210 OpMul8 1211 OpMul16 1212 OpMul32 1213 OpMul64 1214 OpMul32F 1215 OpMul64F 1216 OpDiv32F 1217 OpDiv64F 1218 OpHmul8 1219 OpHmul8u 1220 OpHmul16 1221 OpHmul16u 1222 OpHmul32 1223 OpHmul32u 1224 OpHmul64 1225 OpHmul64u 1226 OpAvg64u 1227 OpDiv8 1228 OpDiv8u 1229 OpDiv16 1230 OpDiv16u 1231 OpDiv32 1232 OpDiv32u 1233 OpDiv64 1234 OpDiv64u 1235 OpMod8 1236 OpMod8u 1237 OpMod16 1238 OpMod16u 1239 OpMod32 1240 OpMod32u 1241 OpMod64 1242 OpMod64u 1243 OpAnd8 1244 OpAnd16 1245 OpAnd32 1246 OpAnd64 1247 OpOr8 1248 OpOr16 1249 OpOr32 1250 OpOr64 1251 OpXor8 1252 OpXor16 1253 OpXor32 1254 OpXor64 1255 OpLsh8x8 1256 OpLsh8x16 1257 OpLsh8x32 1258 OpLsh8x64 1259 OpLsh16x8 1260 OpLsh16x16 1261 OpLsh16x32 1262 OpLsh16x64 1263 OpLsh32x8 1264 OpLsh32x16 1265 OpLsh32x32 1266 OpLsh32x64 1267 OpLsh64x8 1268 OpLsh64x16 1269 OpLsh64x32 1270 OpLsh64x64 1271 OpRsh8x8 1272 OpRsh8x16 1273 OpRsh8x32 1274 OpRsh8x64 1275 OpRsh16x8 1276 OpRsh16x16 1277 OpRsh16x32 1278 OpRsh16x64 1279 OpRsh32x8 1280 OpRsh32x16 1281 OpRsh32x32 1282 OpRsh32x64 1283 OpRsh64x8 1284 OpRsh64x16 1285 OpRsh64x32 1286 OpRsh64x64 1287 OpRsh8Ux8 1288 OpRsh8Ux16 1289 OpRsh8Ux32 1290 OpRsh8Ux64 1291 OpRsh16Ux8 1292 OpRsh16Ux16 1293 OpRsh16Ux32 1294 OpRsh16Ux64 1295 OpRsh32Ux8 1296 OpRsh32Ux16 1297 OpRsh32Ux32 1298 OpRsh32Ux64 1299 OpRsh64Ux8 1300 OpRsh64Ux16 1301 OpRsh64Ux32 1302 OpRsh64Ux64 1303 OpLrot8 1304 OpLrot16 1305 OpLrot32 1306 OpLrot64 1307 OpEq8 1308 OpEq16 1309 OpEq32 1310 OpEq64 1311 OpEqPtr 1312 OpEqInter 1313 OpEqSlice 1314 OpEq32F 1315 OpEq64F 1316 OpNeq8 1317 OpNeq16 1318 OpNeq32 1319 OpNeq64 1320 OpNeqPtr 1321 OpNeqInter 1322 OpNeqSlice 1323 OpNeq32F 1324 OpNeq64F 1325 OpLess8 1326 OpLess8U 1327 OpLess16 1328 OpLess16U 1329 OpLess32 1330 OpLess32U 1331 OpLess64 1332 OpLess64U 1333 OpLess32F 1334 OpLess64F 1335 OpLeq8 1336 OpLeq8U 1337 OpLeq16 1338 OpLeq16U 1339 OpLeq32 1340 OpLeq32U 1341 OpLeq64 1342 OpLeq64U 1343 OpLeq32F 1344 OpLeq64F 1345 OpGreater8 1346 OpGreater8U 1347 OpGreater16 1348 OpGreater16U 1349 OpGreater32 1350 OpGreater32U 1351 OpGreater64 1352 OpGreater64U 1353 OpGreater32F 1354 OpGreater64F 1355 OpGeq8 1356 OpGeq8U 1357 OpGeq16 1358 OpGeq16U 1359 OpGeq32 1360 OpGeq32U 1361 OpGeq64 1362 OpGeq64U 1363 OpGeq32F 1364 OpGeq64F 1365 OpAndB 1366 OpOrB 1367 OpEqB 1368 OpNeqB 1369 OpNot 1370 OpNeg8 1371 OpNeg16 1372 OpNeg32 1373 OpNeg64 1374 OpNeg32F 1375 OpNeg64F 1376 OpCom8 1377 OpCom16 1378 OpCom32 1379 OpCom64 1380 OpCtz32 1381 OpCtz64 1382 OpBswap32 1383 OpBswap64 1384 OpSqrt 1385 OpPhi 1386 OpCopy 1387 OpConvert 1388 OpConstBool 1389 OpConstString 1390 OpConstNil 1391 OpConst8 1392 OpConst16 1393 OpConst32 1394 OpConst64 1395 OpConst32F 1396 OpConst64F 1397 OpConstInterface 1398 OpConstSlice 1399 OpInitMem 1400 OpArg 1401 OpAddr 1402 OpSP 1403 OpSB 1404 OpFunc 1405 OpLoad 1406 OpStore 1407 OpMove 1408 OpZero 1409 OpClosureCall 1410 OpStaticCall 1411 OpDeferCall 1412 OpGoCall 1413 OpInterCall 1414 OpSignExt8to16 1415 OpSignExt8to32 1416 OpSignExt8to64 1417 OpSignExt16to32 1418 OpSignExt16to64 1419 OpSignExt32to64 1420 OpZeroExt8to16 1421 OpZeroExt8to32 1422 OpZeroExt8to64 1423 OpZeroExt16to32 1424 OpZeroExt16to64 1425 OpZeroExt32to64 1426 OpTrunc16to8 1427 OpTrunc32to8 1428 OpTrunc32to16 1429 OpTrunc64to8 1430 OpTrunc64to16 1431 OpTrunc64to32 1432 OpCvt32to32F 1433 OpCvt32to64F 1434 OpCvt64to32F 1435 OpCvt64to64F 1436 OpCvt32Fto32 1437 OpCvt32Fto64 1438 OpCvt64Fto32 1439 OpCvt64Fto64 1440 OpCvt32Fto64F 1441 OpCvt64Fto32F 1442 OpIsNonNil 1443 OpIsInBounds 1444 OpIsSliceInBounds 1445 OpNilCheck 1446 OpGetG 1447 OpGetClosurePtr 1448 OpArrayIndex 1449 OpPtrIndex 1450 OpOffPtr 1451 OpSliceMake 1452 OpSlicePtr 1453 OpSliceLen 1454 OpSliceCap 1455 OpComplexMake 1456 OpComplexReal 1457 OpComplexImag 1458 OpStringMake 1459 OpStringPtr 1460 OpStringLen 1461 OpIMake 1462 OpITab 1463 OpIData 1464 OpStructMake0 1465 OpStructMake1 1466 OpStructMake2 1467 OpStructMake3 1468 OpStructMake4 1469 OpStructSelect 1470 OpStoreReg 1471 OpLoadReg 1472 OpFwdRef 1473 OpUnknown 1474 OpVarDef 1475 OpVarKill 1476 OpVarLive 1477 OpKeepAlive 1478 OpInt64Make 1479 OpInt64Hi 1480 OpInt64Lo 1481 OpAdd32carry 1482 OpAdd32withcarry 1483 OpSub32carry 1484 OpSub32withcarry 1485 OpMul32uhilo 1486 OpSignmask 1487 OpZeromask 1488 OpCvt32Uto32F 1489 OpCvt32Uto64F 1490 OpCvt32Fto32U 1491 OpCvt64Fto32U 1492 OpCvt64Uto32F 1493 OpCvt64Uto64F 1494 OpCvt32Fto64U 1495 OpCvt64Fto64U 1496 OpSelect0 1497 OpSelect1 1498 OpAtomicLoad32 1499 OpAtomicLoad64 1500 OpAtomicLoadPtr 1501 OpAtomicStore32 1502 OpAtomicStore64 1503 OpAtomicStorePtrNoWB 1504 ) 1505 1506 var opcodeTable = [...]opInfo{ 1507 {name: "OpInvalid"}, 1508 1509 { 1510 name: "ADDSS", 1511 argLen: 2, 1512 commutative: true, 1513 resultInArg0: true, 1514 asm: x86.AADDSS, 1515 reg: regInfo{ 1516 inputs: []inputInfo{ 1517 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1518 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1519 }, 1520 outputs: []outputInfo{ 1521 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1522 }, 1523 }, 1524 }, 1525 { 1526 name: "ADDSD", 1527 argLen: 2, 1528 commutative: true, 1529 resultInArg0: true, 1530 asm: x86.AADDSD, 1531 reg: regInfo{ 1532 inputs: []inputInfo{ 1533 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1534 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1535 }, 1536 outputs: []outputInfo{ 1537 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1538 }, 1539 }, 1540 }, 1541 { 1542 name: "SUBSS", 1543 argLen: 2, 1544 resultInArg0: true, 1545 asm: x86.ASUBSS, 1546 reg: regInfo{ 1547 inputs: []inputInfo{ 1548 {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 1549 {1, 32512}, // X0 X1 X2 X3 X4 X5 X6 1550 }, 1551 clobbers: 32768, // X7 1552 outputs: []outputInfo{ 1553 {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 1554 }, 1555 }, 1556 }, 1557 { 1558 name: "SUBSD", 1559 argLen: 2, 1560 resultInArg0: true, 1561 asm: x86.ASUBSD, 1562 reg: regInfo{ 1563 inputs: []inputInfo{ 1564 {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 1565 {1, 32512}, // X0 X1 X2 X3 X4 X5 X6 1566 }, 1567 clobbers: 32768, // X7 1568 outputs: []outputInfo{ 1569 {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 1570 }, 1571 }, 1572 }, 1573 { 1574 name: "MULSS", 1575 argLen: 2, 1576 commutative: true, 1577 resultInArg0: true, 1578 asm: x86.AMULSS, 1579 reg: regInfo{ 1580 inputs: []inputInfo{ 1581 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1582 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1583 }, 1584 outputs: []outputInfo{ 1585 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1586 }, 1587 }, 1588 }, 1589 { 1590 name: "MULSD", 1591 argLen: 2, 1592 commutative: true, 1593 resultInArg0: true, 1594 asm: x86.AMULSD, 1595 reg: regInfo{ 1596 inputs: []inputInfo{ 1597 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1598 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1599 }, 1600 outputs: []outputInfo{ 1601 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1602 }, 1603 }, 1604 }, 1605 { 1606 name: "DIVSS", 1607 argLen: 2, 1608 resultInArg0: true, 1609 asm: x86.ADIVSS, 1610 reg: regInfo{ 1611 inputs: []inputInfo{ 1612 {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 1613 {1, 32512}, // X0 X1 X2 X3 X4 X5 X6 1614 }, 1615 clobbers: 32768, // X7 1616 outputs: []outputInfo{ 1617 {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 1618 }, 1619 }, 1620 }, 1621 { 1622 name: "DIVSD", 1623 argLen: 2, 1624 resultInArg0: true, 1625 asm: x86.ADIVSD, 1626 reg: regInfo{ 1627 inputs: []inputInfo{ 1628 {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 1629 {1, 32512}, // X0 X1 X2 X3 X4 X5 X6 1630 }, 1631 clobbers: 32768, // X7 1632 outputs: []outputInfo{ 1633 {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 1634 }, 1635 }, 1636 }, 1637 { 1638 name: "MOVSSload", 1639 auxType: auxSymOff, 1640 argLen: 2, 1641 asm: x86.AMOVSS, 1642 reg: regInfo{ 1643 inputs: []inputInfo{ 1644 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1645 }, 1646 outputs: []outputInfo{ 1647 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1648 }, 1649 }, 1650 }, 1651 { 1652 name: "MOVSDload", 1653 auxType: auxSymOff, 1654 argLen: 2, 1655 asm: x86.AMOVSD, 1656 reg: regInfo{ 1657 inputs: []inputInfo{ 1658 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1659 }, 1660 outputs: []outputInfo{ 1661 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1662 }, 1663 }, 1664 }, 1665 { 1666 name: "MOVSSconst", 1667 auxType: auxFloat32, 1668 argLen: 0, 1669 rematerializeable: true, 1670 asm: x86.AMOVSS, 1671 reg: regInfo{ 1672 outputs: []outputInfo{ 1673 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1674 }, 1675 }, 1676 }, 1677 { 1678 name: "MOVSDconst", 1679 auxType: auxFloat64, 1680 argLen: 0, 1681 rematerializeable: true, 1682 asm: x86.AMOVSD, 1683 reg: regInfo{ 1684 outputs: []outputInfo{ 1685 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1686 }, 1687 }, 1688 }, 1689 { 1690 name: "MOVSSloadidx1", 1691 auxType: auxSymOff, 1692 argLen: 3, 1693 asm: x86.AMOVSS, 1694 reg: regInfo{ 1695 inputs: []inputInfo{ 1696 {1, 255}, // AX CX DX BX SP BP SI DI 1697 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1698 }, 1699 outputs: []outputInfo{ 1700 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1701 }, 1702 }, 1703 }, 1704 { 1705 name: "MOVSSloadidx4", 1706 auxType: auxSymOff, 1707 argLen: 3, 1708 asm: x86.AMOVSS, 1709 reg: regInfo{ 1710 inputs: []inputInfo{ 1711 {1, 255}, // AX CX DX BX SP BP SI DI 1712 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1713 }, 1714 outputs: []outputInfo{ 1715 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1716 }, 1717 }, 1718 }, 1719 { 1720 name: "MOVSDloadidx1", 1721 auxType: auxSymOff, 1722 argLen: 3, 1723 asm: x86.AMOVSD, 1724 reg: regInfo{ 1725 inputs: []inputInfo{ 1726 {1, 255}, // AX CX DX BX SP BP SI DI 1727 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1728 }, 1729 outputs: []outputInfo{ 1730 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1731 }, 1732 }, 1733 }, 1734 { 1735 name: "MOVSDloadidx8", 1736 auxType: auxSymOff, 1737 argLen: 3, 1738 asm: x86.AMOVSD, 1739 reg: regInfo{ 1740 inputs: []inputInfo{ 1741 {1, 255}, // AX CX DX BX SP BP SI DI 1742 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1743 }, 1744 outputs: []outputInfo{ 1745 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1746 }, 1747 }, 1748 }, 1749 { 1750 name: "MOVSSstore", 1751 auxType: auxSymOff, 1752 argLen: 3, 1753 asm: x86.AMOVSS, 1754 reg: regInfo{ 1755 inputs: []inputInfo{ 1756 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1757 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1758 }, 1759 }, 1760 }, 1761 { 1762 name: "MOVSDstore", 1763 auxType: auxSymOff, 1764 argLen: 3, 1765 asm: x86.AMOVSD, 1766 reg: regInfo{ 1767 inputs: []inputInfo{ 1768 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1769 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1770 }, 1771 }, 1772 }, 1773 { 1774 name: "MOVSSstoreidx1", 1775 auxType: auxSymOff, 1776 argLen: 4, 1777 asm: x86.AMOVSS, 1778 reg: regInfo{ 1779 inputs: []inputInfo{ 1780 {1, 255}, // AX CX DX BX SP BP SI DI 1781 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1782 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1783 }, 1784 }, 1785 }, 1786 { 1787 name: "MOVSSstoreidx4", 1788 auxType: auxSymOff, 1789 argLen: 4, 1790 asm: x86.AMOVSS, 1791 reg: regInfo{ 1792 inputs: []inputInfo{ 1793 {1, 255}, // AX CX DX BX SP BP SI DI 1794 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1795 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1796 }, 1797 }, 1798 }, 1799 { 1800 name: "MOVSDstoreidx1", 1801 auxType: auxSymOff, 1802 argLen: 4, 1803 asm: x86.AMOVSD, 1804 reg: regInfo{ 1805 inputs: []inputInfo{ 1806 {1, 255}, // AX CX DX BX SP BP SI DI 1807 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1808 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1809 }, 1810 }, 1811 }, 1812 { 1813 name: "MOVSDstoreidx8", 1814 auxType: auxSymOff, 1815 argLen: 4, 1816 asm: x86.AMOVSD, 1817 reg: regInfo{ 1818 inputs: []inputInfo{ 1819 {1, 255}, // AX CX DX BX SP BP SI DI 1820 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1821 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1822 }, 1823 }, 1824 }, 1825 { 1826 name: "ADDL", 1827 argLen: 2, 1828 commutative: true, 1829 clobberFlags: true, 1830 asm: x86.AADDL, 1831 reg: regInfo{ 1832 inputs: []inputInfo{ 1833 {1, 239}, // AX CX DX BX BP SI DI 1834 {0, 255}, // AX CX DX BX SP BP SI DI 1835 }, 1836 outputs: []outputInfo{ 1837 {0, 239}, // AX CX DX BX BP SI DI 1838 }, 1839 }, 1840 }, 1841 { 1842 name: "ADDLconst", 1843 auxType: auxInt32, 1844 argLen: 1, 1845 clobberFlags: true, 1846 asm: x86.AADDL, 1847 reg: regInfo{ 1848 inputs: []inputInfo{ 1849 {0, 255}, // AX CX DX BX SP BP SI DI 1850 }, 1851 outputs: []outputInfo{ 1852 {0, 239}, // AX CX DX BX BP SI DI 1853 }, 1854 }, 1855 }, 1856 { 1857 name: "ADDLcarry", 1858 argLen: 2, 1859 commutative: true, 1860 resultInArg0: true, 1861 asm: x86.AADDL, 1862 reg: regInfo{ 1863 inputs: []inputInfo{ 1864 {0, 239}, // AX CX DX BX BP SI DI 1865 {1, 239}, // AX CX DX BX BP SI DI 1866 }, 1867 outputs: []outputInfo{ 1868 {1, 0}, 1869 {0, 239}, // AX CX DX BX BP SI DI 1870 }, 1871 }, 1872 }, 1873 { 1874 name: "ADDLconstcarry", 1875 auxType: auxInt32, 1876 argLen: 1, 1877 resultInArg0: true, 1878 asm: x86.AADDL, 1879 reg: regInfo{ 1880 inputs: []inputInfo{ 1881 {0, 239}, // AX CX DX BX BP SI DI 1882 }, 1883 outputs: []outputInfo{ 1884 {1, 0}, 1885 {0, 239}, // AX CX DX BX BP SI DI 1886 }, 1887 }, 1888 }, 1889 { 1890 name: "ADCL", 1891 argLen: 3, 1892 commutative: true, 1893 resultInArg0: true, 1894 clobberFlags: true, 1895 asm: x86.AADCL, 1896 reg: regInfo{ 1897 inputs: []inputInfo{ 1898 {0, 239}, // AX CX DX BX BP SI DI 1899 {1, 239}, // AX CX DX BX BP SI DI 1900 }, 1901 outputs: []outputInfo{ 1902 {0, 239}, // AX CX DX BX BP SI DI 1903 }, 1904 }, 1905 }, 1906 { 1907 name: "ADCLconst", 1908 auxType: auxInt32, 1909 argLen: 2, 1910 resultInArg0: true, 1911 clobberFlags: true, 1912 asm: x86.AADCL, 1913 reg: regInfo{ 1914 inputs: []inputInfo{ 1915 {0, 239}, // AX CX DX BX BP SI DI 1916 }, 1917 outputs: []outputInfo{ 1918 {0, 239}, // AX CX DX BX BP SI DI 1919 }, 1920 }, 1921 }, 1922 { 1923 name: "SUBL", 1924 argLen: 2, 1925 resultInArg0: true, 1926 clobberFlags: true, 1927 asm: x86.ASUBL, 1928 reg: regInfo{ 1929 inputs: []inputInfo{ 1930 {0, 239}, // AX CX DX BX BP SI DI 1931 {1, 239}, // AX CX DX BX BP SI DI 1932 }, 1933 outputs: []outputInfo{ 1934 {0, 239}, // AX CX DX BX BP SI DI 1935 }, 1936 }, 1937 }, 1938 { 1939 name: "SUBLconst", 1940 auxType: auxInt32, 1941 argLen: 1, 1942 resultInArg0: true, 1943 clobberFlags: true, 1944 asm: x86.ASUBL, 1945 reg: regInfo{ 1946 inputs: []inputInfo{ 1947 {0, 239}, // AX CX DX BX BP SI DI 1948 }, 1949 outputs: []outputInfo{ 1950 {0, 239}, // AX CX DX BX BP SI DI 1951 }, 1952 }, 1953 }, 1954 { 1955 name: "SUBLcarry", 1956 argLen: 2, 1957 resultInArg0: true, 1958 asm: x86.ASUBL, 1959 reg: regInfo{ 1960 inputs: []inputInfo{ 1961 {0, 239}, // AX CX DX BX BP SI DI 1962 {1, 239}, // AX CX DX BX BP SI DI 1963 }, 1964 outputs: []outputInfo{ 1965 {1, 0}, 1966 {0, 239}, // AX CX DX BX BP SI DI 1967 }, 1968 }, 1969 }, 1970 { 1971 name: "SUBLconstcarry", 1972 auxType: auxInt32, 1973 argLen: 1, 1974 resultInArg0: true, 1975 asm: x86.ASUBL, 1976 reg: regInfo{ 1977 inputs: []inputInfo{ 1978 {0, 239}, // AX CX DX BX BP SI DI 1979 }, 1980 outputs: []outputInfo{ 1981 {1, 0}, 1982 {0, 239}, // AX CX DX BX BP SI DI 1983 }, 1984 }, 1985 }, 1986 { 1987 name: "SBBL", 1988 argLen: 3, 1989 resultInArg0: true, 1990 clobberFlags: true, 1991 asm: x86.ASBBL, 1992 reg: regInfo{ 1993 inputs: []inputInfo{ 1994 {0, 239}, // AX CX DX BX BP SI DI 1995 {1, 239}, // AX CX DX BX BP SI DI 1996 }, 1997 outputs: []outputInfo{ 1998 {0, 239}, // AX CX DX BX BP SI DI 1999 }, 2000 }, 2001 }, 2002 { 2003 name: "SBBLconst", 2004 auxType: auxInt32, 2005 argLen: 2, 2006 resultInArg0: true, 2007 clobberFlags: true, 2008 asm: x86.ASBBL, 2009 reg: regInfo{ 2010 inputs: []inputInfo{ 2011 {0, 239}, // AX CX DX BX BP SI DI 2012 }, 2013 outputs: []outputInfo{ 2014 {0, 239}, // AX CX DX BX BP SI DI 2015 }, 2016 }, 2017 }, 2018 { 2019 name: "MULL", 2020 argLen: 2, 2021 commutative: true, 2022 resultInArg0: true, 2023 clobberFlags: true, 2024 asm: x86.AIMULL, 2025 reg: regInfo{ 2026 inputs: []inputInfo{ 2027 {0, 239}, // AX CX DX BX BP SI DI 2028 {1, 239}, // AX CX DX BX BP SI DI 2029 }, 2030 outputs: []outputInfo{ 2031 {0, 239}, // AX CX DX BX BP SI DI 2032 }, 2033 }, 2034 }, 2035 { 2036 name: "MULLconst", 2037 auxType: auxInt32, 2038 argLen: 1, 2039 resultInArg0: true, 2040 clobberFlags: true, 2041 asm: x86.AIMULL, 2042 reg: regInfo{ 2043 inputs: []inputInfo{ 2044 {0, 239}, // AX CX DX BX BP SI DI 2045 }, 2046 outputs: []outputInfo{ 2047 {0, 239}, // AX CX DX BX BP SI DI 2048 }, 2049 }, 2050 }, 2051 { 2052 name: "HMULL", 2053 argLen: 2, 2054 clobberFlags: true, 2055 asm: x86.AIMULL, 2056 reg: regInfo{ 2057 inputs: []inputInfo{ 2058 {0, 1}, // AX 2059 {1, 255}, // AX CX DX BX SP BP SI DI 2060 }, 2061 clobbers: 1, // AX 2062 outputs: []outputInfo{ 2063 {0, 4}, // DX 2064 }, 2065 }, 2066 }, 2067 { 2068 name: "HMULLU", 2069 argLen: 2, 2070 clobberFlags: true, 2071 asm: x86.AMULL, 2072 reg: regInfo{ 2073 inputs: []inputInfo{ 2074 {0, 1}, // AX 2075 {1, 255}, // AX CX DX BX SP BP SI DI 2076 }, 2077 clobbers: 1, // AX 2078 outputs: []outputInfo{ 2079 {0, 4}, // DX 2080 }, 2081 }, 2082 }, 2083 { 2084 name: "HMULW", 2085 argLen: 2, 2086 clobberFlags: true, 2087 asm: x86.AIMULW, 2088 reg: regInfo{ 2089 inputs: []inputInfo{ 2090 {0, 1}, // AX 2091 {1, 255}, // AX CX DX BX SP BP SI DI 2092 }, 2093 clobbers: 1, // AX 2094 outputs: []outputInfo{ 2095 {0, 4}, // DX 2096 }, 2097 }, 2098 }, 2099 { 2100 name: "HMULB", 2101 argLen: 2, 2102 clobberFlags: true, 2103 asm: x86.AIMULB, 2104 reg: regInfo{ 2105 inputs: []inputInfo{ 2106 {0, 1}, // AX 2107 {1, 255}, // AX CX DX BX SP BP SI DI 2108 }, 2109 clobbers: 1, // AX 2110 outputs: []outputInfo{ 2111 {0, 4}, // DX 2112 }, 2113 }, 2114 }, 2115 { 2116 name: "HMULWU", 2117 argLen: 2, 2118 clobberFlags: true, 2119 asm: x86.AMULW, 2120 reg: regInfo{ 2121 inputs: []inputInfo{ 2122 {0, 1}, // AX 2123 {1, 255}, // AX CX DX BX SP BP SI DI 2124 }, 2125 clobbers: 1, // AX 2126 outputs: []outputInfo{ 2127 {0, 4}, // DX 2128 }, 2129 }, 2130 }, 2131 { 2132 name: "HMULBU", 2133 argLen: 2, 2134 clobberFlags: true, 2135 asm: x86.AMULB, 2136 reg: regInfo{ 2137 inputs: []inputInfo{ 2138 {0, 1}, // AX 2139 {1, 255}, // AX CX DX BX SP BP SI DI 2140 }, 2141 clobbers: 1, // AX 2142 outputs: []outputInfo{ 2143 {0, 4}, // DX 2144 }, 2145 }, 2146 }, 2147 { 2148 name: "MULLQU", 2149 argLen: 2, 2150 clobberFlags: true, 2151 asm: x86.AMULL, 2152 reg: regInfo{ 2153 inputs: []inputInfo{ 2154 {0, 1}, // AX 2155 {1, 255}, // AX CX DX BX SP BP SI DI 2156 }, 2157 outputs: []outputInfo{ 2158 {0, 4}, // DX 2159 {1, 1}, // AX 2160 }, 2161 }, 2162 }, 2163 { 2164 name: "DIVL", 2165 argLen: 2, 2166 clobberFlags: true, 2167 asm: x86.AIDIVL, 2168 reg: regInfo{ 2169 inputs: []inputInfo{ 2170 {0, 1}, // AX 2171 {1, 251}, // AX CX BX SP BP SI DI 2172 }, 2173 clobbers: 4, // DX 2174 outputs: []outputInfo{ 2175 {0, 1}, // AX 2176 }, 2177 }, 2178 }, 2179 { 2180 name: "DIVW", 2181 argLen: 2, 2182 clobberFlags: true, 2183 asm: x86.AIDIVW, 2184 reg: regInfo{ 2185 inputs: []inputInfo{ 2186 {0, 1}, // AX 2187 {1, 251}, // AX CX BX SP BP SI DI 2188 }, 2189 clobbers: 4, // DX 2190 outputs: []outputInfo{ 2191 {0, 1}, // AX 2192 }, 2193 }, 2194 }, 2195 { 2196 name: "DIVLU", 2197 argLen: 2, 2198 clobberFlags: true, 2199 asm: x86.ADIVL, 2200 reg: regInfo{ 2201 inputs: []inputInfo{ 2202 {0, 1}, // AX 2203 {1, 251}, // AX CX BX SP BP SI DI 2204 }, 2205 clobbers: 4, // DX 2206 outputs: []outputInfo{ 2207 {0, 1}, // AX 2208 }, 2209 }, 2210 }, 2211 { 2212 name: "DIVWU", 2213 argLen: 2, 2214 clobberFlags: true, 2215 asm: x86.ADIVW, 2216 reg: regInfo{ 2217 inputs: []inputInfo{ 2218 {0, 1}, // AX 2219 {1, 251}, // AX CX BX SP BP SI DI 2220 }, 2221 clobbers: 4, // DX 2222 outputs: []outputInfo{ 2223 {0, 1}, // AX 2224 }, 2225 }, 2226 }, 2227 { 2228 name: "MODL", 2229 argLen: 2, 2230 clobberFlags: true, 2231 asm: x86.AIDIVL, 2232 reg: regInfo{ 2233 inputs: []inputInfo{ 2234 {0, 1}, // AX 2235 {1, 251}, // AX CX BX SP BP SI DI 2236 }, 2237 clobbers: 1, // AX 2238 outputs: []outputInfo{ 2239 {0, 4}, // DX 2240 }, 2241 }, 2242 }, 2243 { 2244 name: "MODW", 2245 argLen: 2, 2246 clobberFlags: true, 2247 asm: x86.AIDIVW, 2248 reg: regInfo{ 2249 inputs: []inputInfo{ 2250 {0, 1}, // AX 2251 {1, 251}, // AX CX BX SP BP SI DI 2252 }, 2253 clobbers: 1, // AX 2254 outputs: []outputInfo{ 2255 {0, 4}, // DX 2256 }, 2257 }, 2258 }, 2259 { 2260 name: "MODLU", 2261 argLen: 2, 2262 clobberFlags: true, 2263 asm: x86.ADIVL, 2264 reg: regInfo{ 2265 inputs: []inputInfo{ 2266 {0, 1}, // AX 2267 {1, 251}, // AX CX BX SP BP SI DI 2268 }, 2269 clobbers: 1, // AX 2270 outputs: []outputInfo{ 2271 {0, 4}, // DX 2272 }, 2273 }, 2274 }, 2275 { 2276 name: "MODWU", 2277 argLen: 2, 2278 clobberFlags: true, 2279 asm: x86.ADIVW, 2280 reg: regInfo{ 2281 inputs: []inputInfo{ 2282 {0, 1}, // AX 2283 {1, 251}, // AX CX BX SP BP SI DI 2284 }, 2285 clobbers: 1, // AX 2286 outputs: []outputInfo{ 2287 {0, 4}, // DX 2288 }, 2289 }, 2290 }, 2291 { 2292 name: "ANDL", 2293 argLen: 2, 2294 commutative: true, 2295 resultInArg0: true, 2296 clobberFlags: true, 2297 asm: x86.AANDL, 2298 reg: regInfo{ 2299 inputs: []inputInfo{ 2300 {0, 239}, // AX CX DX BX BP SI DI 2301 {1, 239}, // AX CX DX BX BP SI DI 2302 }, 2303 outputs: []outputInfo{ 2304 {0, 239}, // AX CX DX BX BP SI DI 2305 }, 2306 }, 2307 }, 2308 { 2309 name: "ANDLconst", 2310 auxType: auxInt32, 2311 argLen: 1, 2312 resultInArg0: true, 2313 clobberFlags: true, 2314 asm: x86.AANDL, 2315 reg: regInfo{ 2316 inputs: []inputInfo{ 2317 {0, 239}, // AX CX DX BX BP SI DI 2318 }, 2319 outputs: []outputInfo{ 2320 {0, 239}, // AX CX DX BX BP SI DI 2321 }, 2322 }, 2323 }, 2324 { 2325 name: "ORL", 2326 argLen: 2, 2327 commutative: true, 2328 resultInArg0: true, 2329 clobberFlags: true, 2330 asm: x86.AORL, 2331 reg: regInfo{ 2332 inputs: []inputInfo{ 2333 {0, 239}, // AX CX DX BX BP SI DI 2334 {1, 239}, // AX CX DX BX BP SI DI 2335 }, 2336 outputs: []outputInfo{ 2337 {0, 239}, // AX CX DX BX BP SI DI 2338 }, 2339 }, 2340 }, 2341 { 2342 name: "ORLconst", 2343 auxType: auxInt32, 2344 argLen: 1, 2345 resultInArg0: true, 2346 clobberFlags: true, 2347 asm: x86.AORL, 2348 reg: regInfo{ 2349 inputs: []inputInfo{ 2350 {0, 239}, // AX CX DX BX BP SI DI 2351 }, 2352 outputs: []outputInfo{ 2353 {0, 239}, // AX CX DX BX BP SI DI 2354 }, 2355 }, 2356 }, 2357 { 2358 name: "XORL", 2359 argLen: 2, 2360 commutative: true, 2361 resultInArg0: true, 2362 clobberFlags: true, 2363 asm: x86.AXORL, 2364 reg: regInfo{ 2365 inputs: []inputInfo{ 2366 {0, 239}, // AX CX DX BX BP SI DI 2367 {1, 239}, // AX CX DX BX BP SI DI 2368 }, 2369 outputs: []outputInfo{ 2370 {0, 239}, // AX CX DX BX BP SI DI 2371 }, 2372 }, 2373 }, 2374 { 2375 name: "XORLconst", 2376 auxType: auxInt32, 2377 argLen: 1, 2378 resultInArg0: true, 2379 clobberFlags: true, 2380 asm: x86.AXORL, 2381 reg: regInfo{ 2382 inputs: []inputInfo{ 2383 {0, 239}, // AX CX DX BX BP SI DI 2384 }, 2385 outputs: []outputInfo{ 2386 {0, 239}, // AX CX DX BX BP SI DI 2387 }, 2388 }, 2389 }, 2390 { 2391 name: "CMPL", 2392 argLen: 2, 2393 asm: x86.ACMPL, 2394 reg: regInfo{ 2395 inputs: []inputInfo{ 2396 {0, 255}, // AX CX DX BX SP BP SI DI 2397 {1, 255}, // AX CX DX BX SP BP SI DI 2398 }, 2399 }, 2400 }, 2401 { 2402 name: "CMPW", 2403 argLen: 2, 2404 asm: x86.ACMPW, 2405 reg: regInfo{ 2406 inputs: []inputInfo{ 2407 {0, 255}, // AX CX DX BX SP BP SI DI 2408 {1, 255}, // AX CX DX BX SP BP SI DI 2409 }, 2410 }, 2411 }, 2412 { 2413 name: "CMPB", 2414 argLen: 2, 2415 asm: x86.ACMPB, 2416 reg: regInfo{ 2417 inputs: []inputInfo{ 2418 {0, 255}, // AX CX DX BX SP BP SI DI 2419 {1, 255}, // AX CX DX BX SP BP SI DI 2420 }, 2421 }, 2422 }, 2423 { 2424 name: "CMPLconst", 2425 auxType: auxInt32, 2426 argLen: 1, 2427 asm: x86.ACMPL, 2428 reg: regInfo{ 2429 inputs: []inputInfo{ 2430 {0, 255}, // AX CX DX BX SP BP SI DI 2431 }, 2432 }, 2433 }, 2434 { 2435 name: "CMPWconst", 2436 auxType: auxInt16, 2437 argLen: 1, 2438 asm: x86.ACMPW, 2439 reg: regInfo{ 2440 inputs: []inputInfo{ 2441 {0, 255}, // AX CX DX BX SP BP SI DI 2442 }, 2443 }, 2444 }, 2445 { 2446 name: "CMPBconst", 2447 auxType: auxInt8, 2448 argLen: 1, 2449 asm: x86.ACMPB, 2450 reg: regInfo{ 2451 inputs: []inputInfo{ 2452 {0, 255}, // AX CX DX BX SP BP SI DI 2453 }, 2454 }, 2455 }, 2456 { 2457 name: "UCOMISS", 2458 argLen: 2, 2459 asm: x86.AUCOMISS, 2460 reg: regInfo{ 2461 inputs: []inputInfo{ 2462 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2463 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2464 }, 2465 }, 2466 }, 2467 { 2468 name: "UCOMISD", 2469 argLen: 2, 2470 asm: x86.AUCOMISD, 2471 reg: regInfo{ 2472 inputs: []inputInfo{ 2473 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2474 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2475 }, 2476 }, 2477 }, 2478 { 2479 name: "TESTL", 2480 argLen: 2, 2481 asm: x86.ATESTL, 2482 reg: regInfo{ 2483 inputs: []inputInfo{ 2484 {0, 255}, // AX CX DX BX SP BP SI DI 2485 {1, 255}, // AX CX DX BX SP BP SI DI 2486 }, 2487 }, 2488 }, 2489 { 2490 name: "TESTW", 2491 argLen: 2, 2492 asm: x86.ATESTW, 2493 reg: regInfo{ 2494 inputs: []inputInfo{ 2495 {0, 255}, // AX CX DX BX SP BP SI DI 2496 {1, 255}, // AX CX DX BX SP BP SI DI 2497 }, 2498 }, 2499 }, 2500 { 2501 name: "TESTB", 2502 argLen: 2, 2503 asm: x86.ATESTB, 2504 reg: regInfo{ 2505 inputs: []inputInfo{ 2506 {0, 255}, // AX CX DX BX SP BP SI DI 2507 {1, 255}, // AX CX DX BX SP BP SI DI 2508 }, 2509 }, 2510 }, 2511 { 2512 name: "TESTLconst", 2513 auxType: auxInt32, 2514 argLen: 1, 2515 asm: x86.ATESTL, 2516 reg: regInfo{ 2517 inputs: []inputInfo{ 2518 {0, 255}, // AX CX DX BX SP BP SI DI 2519 }, 2520 }, 2521 }, 2522 { 2523 name: "TESTWconst", 2524 auxType: auxInt16, 2525 argLen: 1, 2526 asm: x86.ATESTW, 2527 reg: regInfo{ 2528 inputs: []inputInfo{ 2529 {0, 255}, // AX CX DX BX SP BP SI DI 2530 }, 2531 }, 2532 }, 2533 { 2534 name: "TESTBconst", 2535 auxType: auxInt8, 2536 argLen: 1, 2537 asm: x86.ATESTB, 2538 reg: regInfo{ 2539 inputs: []inputInfo{ 2540 {0, 255}, // AX CX DX BX SP BP SI DI 2541 }, 2542 }, 2543 }, 2544 { 2545 name: "SHLL", 2546 argLen: 2, 2547 resultInArg0: true, 2548 clobberFlags: true, 2549 asm: x86.ASHLL, 2550 reg: regInfo{ 2551 inputs: []inputInfo{ 2552 {1, 2}, // CX 2553 {0, 239}, // AX CX DX BX BP SI DI 2554 }, 2555 outputs: []outputInfo{ 2556 {0, 239}, // AX CX DX BX BP SI DI 2557 }, 2558 }, 2559 }, 2560 { 2561 name: "SHLLconst", 2562 auxType: auxInt32, 2563 argLen: 1, 2564 resultInArg0: true, 2565 clobberFlags: true, 2566 asm: x86.ASHLL, 2567 reg: regInfo{ 2568 inputs: []inputInfo{ 2569 {0, 239}, // AX CX DX BX BP SI DI 2570 }, 2571 outputs: []outputInfo{ 2572 {0, 239}, // AX CX DX BX BP SI DI 2573 }, 2574 }, 2575 }, 2576 { 2577 name: "SHRL", 2578 argLen: 2, 2579 resultInArg0: true, 2580 clobberFlags: true, 2581 asm: x86.ASHRL, 2582 reg: regInfo{ 2583 inputs: []inputInfo{ 2584 {1, 2}, // CX 2585 {0, 239}, // AX CX DX BX BP SI DI 2586 }, 2587 outputs: []outputInfo{ 2588 {0, 239}, // AX CX DX BX BP SI DI 2589 }, 2590 }, 2591 }, 2592 { 2593 name: "SHRW", 2594 argLen: 2, 2595 resultInArg0: true, 2596 clobberFlags: true, 2597 asm: x86.ASHRW, 2598 reg: regInfo{ 2599 inputs: []inputInfo{ 2600 {1, 2}, // CX 2601 {0, 239}, // AX CX DX BX BP SI DI 2602 }, 2603 outputs: []outputInfo{ 2604 {0, 239}, // AX CX DX BX BP SI DI 2605 }, 2606 }, 2607 }, 2608 { 2609 name: "SHRB", 2610 argLen: 2, 2611 resultInArg0: true, 2612 clobberFlags: true, 2613 asm: x86.ASHRB, 2614 reg: regInfo{ 2615 inputs: []inputInfo{ 2616 {1, 2}, // CX 2617 {0, 239}, // AX CX DX BX BP SI DI 2618 }, 2619 outputs: []outputInfo{ 2620 {0, 239}, // AX CX DX BX BP SI DI 2621 }, 2622 }, 2623 }, 2624 { 2625 name: "SHRLconst", 2626 auxType: auxInt32, 2627 argLen: 1, 2628 resultInArg0: true, 2629 clobberFlags: true, 2630 asm: x86.ASHRL, 2631 reg: regInfo{ 2632 inputs: []inputInfo{ 2633 {0, 239}, // AX CX DX BX BP SI DI 2634 }, 2635 outputs: []outputInfo{ 2636 {0, 239}, // AX CX DX BX BP SI DI 2637 }, 2638 }, 2639 }, 2640 { 2641 name: "SHRWconst", 2642 auxType: auxInt16, 2643 argLen: 1, 2644 resultInArg0: true, 2645 clobberFlags: true, 2646 asm: x86.ASHRW, 2647 reg: regInfo{ 2648 inputs: []inputInfo{ 2649 {0, 239}, // AX CX DX BX BP SI DI 2650 }, 2651 outputs: []outputInfo{ 2652 {0, 239}, // AX CX DX BX BP SI DI 2653 }, 2654 }, 2655 }, 2656 { 2657 name: "SHRBconst", 2658 auxType: auxInt8, 2659 argLen: 1, 2660 resultInArg0: true, 2661 clobberFlags: true, 2662 asm: x86.ASHRB, 2663 reg: regInfo{ 2664 inputs: []inputInfo{ 2665 {0, 239}, // AX CX DX BX BP SI DI 2666 }, 2667 outputs: []outputInfo{ 2668 {0, 239}, // AX CX DX BX BP SI DI 2669 }, 2670 }, 2671 }, 2672 { 2673 name: "SARL", 2674 argLen: 2, 2675 resultInArg0: true, 2676 clobberFlags: true, 2677 asm: x86.ASARL, 2678 reg: regInfo{ 2679 inputs: []inputInfo{ 2680 {1, 2}, // CX 2681 {0, 239}, // AX CX DX BX BP SI DI 2682 }, 2683 outputs: []outputInfo{ 2684 {0, 239}, // AX CX DX BX BP SI DI 2685 }, 2686 }, 2687 }, 2688 { 2689 name: "SARW", 2690 argLen: 2, 2691 resultInArg0: true, 2692 clobberFlags: true, 2693 asm: x86.ASARW, 2694 reg: regInfo{ 2695 inputs: []inputInfo{ 2696 {1, 2}, // CX 2697 {0, 239}, // AX CX DX BX BP SI DI 2698 }, 2699 outputs: []outputInfo{ 2700 {0, 239}, // AX CX DX BX BP SI DI 2701 }, 2702 }, 2703 }, 2704 { 2705 name: "SARB", 2706 argLen: 2, 2707 resultInArg0: true, 2708 clobberFlags: true, 2709 asm: x86.ASARB, 2710 reg: regInfo{ 2711 inputs: []inputInfo{ 2712 {1, 2}, // CX 2713 {0, 239}, // AX CX DX BX BP SI DI 2714 }, 2715 outputs: []outputInfo{ 2716 {0, 239}, // AX CX DX BX BP SI DI 2717 }, 2718 }, 2719 }, 2720 { 2721 name: "SARLconst", 2722 auxType: auxInt32, 2723 argLen: 1, 2724 resultInArg0: true, 2725 clobberFlags: true, 2726 asm: x86.ASARL, 2727 reg: regInfo{ 2728 inputs: []inputInfo{ 2729 {0, 239}, // AX CX DX BX BP SI DI 2730 }, 2731 outputs: []outputInfo{ 2732 {0, 239}, // AX CX DX BX BP SI DI 2733 }, 2734 }, 2735 }, 2736 { 2737 name: "SARWconst", 2738 auxType: auxInt16, 2739 argLen: 1, 2740 resultInArg0: true, 2741 clobberFlags: true, 2742 asm: x86.ASARW, 2743 reg: regInfo{ 2744 inputs: []inputInfo{ 2745 {0, 239}, // AX CX DX BX BP SI DI 2746 }, 2747 outputs: []outputInfo{ 2748 {0, 239}, // AX CX DX BX BP SI DI 2749 }, 2750 }, 2751 }, 2752 { 2753 name: "SARBconst", 2754 auxType: auxInt8, 2755 argLen: 1, 2756 resultInArg0: true, 2757 clobberFlags: true, 2758 asm: x86.ASARB, 2759 reg: regInfo{ 2760 inputs: []inputInfo{ 2761 {0, 239}, // AX CX DX BX BP SI DI 2762 }, 2763 outputs: []outputInfo{ 2764 {0, 239}, // AX CX DX BX BP SI DI 2765 }, 2766 }, 2767 }, 2768 { 2769 name: "ROLLconst", 2770 auxType: auxInt32, 2771 argLen: 1, 2772 resultInArg0: true, 2773 clobberFlags: true, 2774 asm: x86.AROLL, 2775 reg: regInfo{ 2776 inputs: []inputInfo{ 2777 {0, 239}, // AX CX DX BX BP SI DI 2778 }, 2779 outputs: []outputInfo{ 2780 {0, 239}, // AX CX DX BX BP SI DI 2781 }, 2782 }, 2783 }, 2784 { 2785 name: "ROLWconst", 2786 auxType: auxInt16, 2787 argLen: 1, 2788 resultInArg0: true, 2789 clobberFlags: true, 2790 asm: x86.AROLW, 2791 reg: regInfo{ 2792 inputs: []inputInfo{ 2793 {0, 239}, // AX CX DX BX BP SI DI 2794 }, 2795 outputs: []outputInfo{ 2796 {0, 239}, // AX CX DX BX BP SI DI 2797 }, 2798 }, 2799 }, 2800 { 2801 name: "ROLBconst", 2802 auxType: auxInt8, 2803 argLen: 1, 2804 resultInArg0: true, 2805 clobberFlags: true, 2806 asm: x86.AROLB, 2807 reg: regInfo{ 2808 inputs: []inputInfo{ 2809 {0, 239}, // AX CX DX BX BP SI DI 2810 }, 2811 outputs: []outputInfo{ 2812 {0, 239}, // AX CX DX BX BP SI DI 2813 }, 2814 }, 2815 }, 2816 { 2817 name: "NEGL", 2818 argLen: 1, 2819 resultInArg0: true, 2820 clobberFlags: true, 2821 asm: x86.ANEGL, 2822 reg: regInfo{ 2823 inputs: []inputInfo{ 2824 {0, 239}, // AX CX DX BX BP SI DI 2825 }, 2826 outputs: []outputInfo{ 2827 {0, 239}, // AX CX DX BX BP SI DI 2828 }, 2829 }, 2830 }, 2831 { 2832 name: "NOTL", 2833 argLen: 1, 2834 resultInArg0: true, 2835 clobberFlags: true, 2836 asm: x86.ANOTL, 2837 reg: regInfo{ 2838 inputs: []inputInfo{ 2839 {0, 239}, // AX CX DX BX BP SI DI 2840 }, 2841 outputs: []outputInfo{ 2842 {0, 239}, // AX CX DX BX BP SI DI 2843 }, 2844 }, 2845 }, 2846 { 2847 name: "BSFL", 2848 argLen: 1, 2849 clobberFlags: true, 2850 asm: x86.ABSFL, 2851 reg: regInfo{ 2852 inputs: []inputInfo{ 2853 {0, 239}, // AX CX DX BX BP SI DI 2854 }, 2855 outputs: []outputInfo{ 2856 {0, 239}, // AX CX DX BX BP SI DI 2857 }, 2858 }, 2859 }, 2860 { 2861 name: "BSFW", 2862 argLen: 1, 2863 clobberFlags: true, 2864 asm: x86.ABSFW, 2865 reg: regInfo{ 2866 inputs: []inputInfo{ 2867 {0, 239}, // AX CX DX BX BP SI DI 2868 }, 2869 outputs: []outputInfo{ 2870 {0, 239}, // AX CX DX BX BP SI DI 2871 }, 2872 }, 2873 }, 2874 { 2875 name: "BSRL", 2876 argLen: 1, 2877 clobberFlags: true, 2878 asm: x86.ABSRL, 2879 reg: regInfo{ 2880 inputs: []inputInfo{ 2881 {0, 239}, // AX CX DX BX BP SI DI 2882 }, 2883 outputs: []outputInfo{ 2884 {0, 239}, // AX CX DX BX BP SI DI 2885 }, 2886 }, 2887 }, 2888 { 2889 name: "BSRW", 2890 argLen: 1, 2891 clobberFlags: true, 2892 asm: x86.ABSRW, 2893 reg: regInfo{ 2894 inputs: []inputInfo{ 2895 {0, 239}, // AX CX DX BX BP SI DI 2896 }, 2897 outputs: []outputInfo{ 2898 {0, 239}, // AX CX DX BX BP SI DI 2899 }, 2900 }, 2901 }, 2902 { 2903 name: "BSWAPL", 2904 argLen: 1, 2905 resultInArg0: true, 2906 clobberFlags: true, 2907 asm: x86.ABSWAPL, 2908 reg: regInfo{ 2909 inputs: []inputInfo{ 2910 {0, 239}, // AX CX DX BX BP SI DI 2911 }, 2912 outputs: []outputInfo{ 2913 {0, 239}, // AX CX DX BX BP SI DI 2914 }, 2915 }, 2916 }, 2917 { 2918 name: "SQRTSD", 2919 argLen: 1, 2920 asm: x86.ASQRTSD, 2921 reg: regInfo{ 2922 inputs: []inputInfo{ 2923 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2924 }, 2925 outputs: []outputInfo{ 2926 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2927 }, 2928 }, 2929 }, 2930 { 2931 name: "SBBLcarrymask", 2932 argLen: 1, 2933 asm: x86.ASBBL, 2934 reg: regInfo{ 2935 outputs: []outputInfo{ 2936 {0, 239}, // AX CX DX BX BP SI DI 2937 }, 2938 }, 2939 }, 2940 { 2941 name: "SETEQ", 2942 argLen: 1, 2943 asm: x86.ASETEQ, 2944 reg: regInfo{ 2945 outputs: []outputInfo{ 2946 {0, 239}, // AX CX DX BX BP SI DI 2947 }, 2948 }, 2949 }, 2950 { 2951 name: "SETNE", 2952 argLen: 1, 2953 asm: x86.ASETNE, 2954 reg: regInfo{ 2955 outputs: []outputInfo{ 2956 {0, 239}, // AX CX DX BX BP SI DI 2957 }, 2958 }, 2959 }, 2960 { 2961 name: "SETL", 2962 argLen: 1, 2963 asm: x86.ASETLT, 2964 reg: regInfo{ 2965 outputs: []outputInfo{ 2966 {0, 239}, // AX CX DX BX BP SI DI 2967 }, 2968 }, 2969 }, 2970 { 2971 name: "SETLE", 2972 argLen: 1, 2973 asm: x86.ASETLE, 2974 reg: regInfo{ 2975 outputs: []outputInfo{ 2976 {0, 239}, // AX CX DX BX BP SI DI 2977 }, 2978 }, 2979 }, 2980 { 2981 name: "SETG", 2982 argLen: 1, 2983 asm: x86.ASETGT, 2984 reg: regInfo{ 2985 outputs: []outputInfo{ 2986 {0, 239}, // AX CX DX BX BP SI DI 2987 }, 2988 }, 2989 }, 2990 { 2991 name: "SETGE", 2992 argLen: 1, 2993 asm: x86.ASETGE, 2994 reg: regInfo{ 2995 outputs: []outputInfo{ 2996 {0, 239}, // AX CX DX BX BP SI DI 2997 }, 2998 }, 2999 }, 3000 { 3001 name: "SETB", 3002 argLen: 1, 3003 asm: x86.ASETCS, 3004 reg: regInfo{ 3005 outputs: []outputInfo{ 3006 {0, 239}, // AX CX DX BX BP SI DI 3007 }, 3008 }, 3009 }, 3010 { 3011 name: "SETBE", 3012 argLen: 1, 3013 asm: x86.ASETLS, 3014 reg: regInfo{ 3015 outputs: []outputInfo{ 3016 {0, 239}, // AX CX DX BX BP SI DI 3017 }, 3018 }, 3019 }, 3020 { 3021 name: "SETA", 3022 argLen: 1, 3023 asm: x86.ASETHI, 3024 reg: regInfo{ 3025 outputs: []outputInfo{ 3026 {0, 239}, // AX CX DX BX BP SI DI 3027 }, 3028 }, 3029 }, 3030 { 3031 name: "SETAE", 3032 argLen: 1, 3033 asm: x86.ASETCC, 3034 reg: regInfo{ 3035 outputs: []outputInfo{ 3036 {0, 239}, // AX CX DX BX BP SI DI 3037 }, 3038 }, 3039 }, 3040 { 3041 name: "SETEQF", 3042 argLen: 1, 3043 clobberFlags: true, 3044 asm: x86.ASETEQ, 3045 reg: regInfo{ 3046 clobbers: 1, // AX 3047 outputs: []outputInfo{ 3048 {0, 238}, // CX DX BX BP SI DI 3049 }, 3050 }, 3051 }, 3052 { 3053 name: "SETNEF", 3054 argLen: 1, 3055 clobberFlags: true, 3056 asm: x86.ASETNE, 3057 reg: regInfo{ 3058 clobbers: 1, // AX 3059 outputs: []outputInfo{ 3060 {0, 238}, // CX DX BX BP SI DI 3061 }, 3062 }, 3063 }, 3064 { 3065 name: "SETORD", 3066 argLen: 1, 3067 asm: x86.ASETPC, 3068 reg: regInfo{ 3069 outputs: []outputInfo{ 3070 {0, 239}, // AX CX DX BX BP SI DI 3071 }, 3072 }, 3073 }, 3074 { 3075 name: "SETNAN", 3076 argLen: 1, 3077 asm: x86.ASETPS, 3078 reg: regInfo{ 3079 outputs: []outputInfo{ 3080 {0, 239}, // AX CX DX BX BP SI DI 3081 }, 3082 }, 3083 }, 3084 { 3085 name: "SETGF", 3086 argLen: 1, 3087 asm: x86.ASETHI, 3088 reg: regInfo{ 3089 outputs: []outputInfo{ 3090 {0, 239}, // AX CX DX BX BP SI DI 3091 }, 3092 }, 3093 }, 3094 { 3095 name: "SETGEF", 3096 argLen: 1, 3097 asm: x86.ASETCC, 3098 reg: regInfo{ 3099 outputs: []outputInfo{ 3100 {0, 239}, // AX CX DX BX BP SI DI 3101 }, 3102 }, 3103 }, 3104 { 3105 name: "MOVBLSX", 3106 argLen: 1, 3107 asm: x86.AMOVBLSX, 3108 reg: regInfo{ 3109 inputs: []inputInfo{ 3110 {0, 239}, // AX CX DX BX BP SI DI 3111 }, 3112 outputs: []outputInfo{ 3113 {0, 239}, // AX CX DX BX BP SI DI 3114 }, 3115 }, 3116 }, 3117 { 3118 name: "MOVBLZX", 3119 argLen: 1, 3120 asm: x86.AMOVBLZX, 3121 reg: regInfo{ 3122 inputs: []inputInfo{ 3123 {0, 239}, // AX CX DX BX BP SI DI 3124 }, 3125 outputs: []outputInfo{ 3126 {0, 239}, // AX CX DX BX BP SI DI 3127 }, 3128 }, 3129 }, 3130 { 3131 name: "MOVWLSX", 3132 argLen: 1, 3133 asm: x86.AMOVWLSX, 3134 reg: regInfo{ 3135 inputs: []inputInfo{ 3136 {0, 239}, // AX CX DX BX BP SI DI 3137 }, 3138 outputs: []outputInfo{ 3139 {0, 239}, // AX CX DX BX BP SI DI 3140 }, 3141 }, 3142 }, 3143 { 3144 name: "MOVWLZX", 3145 argLen: 1, 3146 asm: x86.AMOVWLZX, 3147 reg: regInfo{ 3148 inputs: []inputInfo{ 3149 {0, 239}, // AX CX DX BX BP SI DI 3150 }, 3151 outputs: []outputInfo{ 3152 {0, 239}, // AX CX DX BX BP SI DI 3153 }, 3154 }, 3155 }, 3156 { 3157 name: "MOVLconst", 3158 auxType: auxInt32, 3159 argLen: 0, 3160 rematerializeable: true, 3161 asm: x86.AMOVL, 3162 reg: regInfo{ 3163 outputs: []outputInfo{ 3164 {0, 239}, // AX CX DX BX BP SI DI 3165 }, 3166 }, 3167 }, 3168 { 3169 name: "CVTTSD2SL", 3170 argLen: 1, 3171 asm: x86.ACVTTSD2SL, 3172 reg: regInfo{ 3173 inputs: []inputInfo{ 3174 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3175 }, 3176 outputs: []outputInfo{ 3177 {0, 239}, // AX CX DX BX BP SI DI 3178 }, 3179 }, 3180 }, 3181 { 3182 name: "CVTTSS2SL", 3183 argLen: 1, 3184 asm: x86.ACVTTSS2SL, 3185 reg: regInfo{ 3186 inputs: []inputInfo{ 3187 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3188 }, 3189 outputs: []outputInfo{ 3190 {0, 239}, // AX CX DX BX BP SI DI 3191 }, 3192 }, 3193 }, 3194 { 3195 name: "CVTSL2SS", 3196 argLen: 1, 3197 asm: x86.ACVTSL2SS, 3198 reg: regInfo{ 3199 inputs: []inputInfo{ 3200 {0, 239}, // AX CX DX BX BP SI DI 3201 }, 3202 outputs: []outputInfo{ 3203 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3204 }, 3205 }, 3206 }, 3207 { 3208 name: "CVTSL2SD", 3209 argLen: 1, 3210 asm: x86.ACVTSL2SD, 3211 reg: regInfo{ 3212 inputs: []inputInfo{ 3213 {0, 239}, // AX CX DX BX BP SI DI 3214 }, 3215 outputs: []outputInfo{ 3216 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3217 }, 3218 }, 3219 }, 3220 { 3221 name: "CVTSD2SS", 3222 argLen: 1, 3223 asm: x86.ACVTSD2SS, 3224 reg: regInfo{ 3225 inputs: []inputInfo{ 3226 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3227 }, 3228 outputs: []outputInfo{ 3229 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3230 }, 3231 }, 3232 }, 3233 { 3234 name: "CVTSS2SD", 3235 argLen: 1, 3236 asm: x86.ACVTSS2SD, 3237 reg: regInfo{ 3238 inputs: []inputInfo{ 3239 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3240 }, 3241 outputs: []outputInfo{ 3242 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3243 }, 3244 }, 3245 }, 3246 { 3247 name: "PXOR", 3248 argLen: 2, 3249 commutative: true, 3250 resultInArg0: true, 3251 asm: x86.APXOR, 3252 reg: regInfo{ 3253 inputs: []inputInfo{ 3254 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3255 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3256 }, 3257 outputs: []outputInfo{ 3258 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3259 }, 3260 }, 3261 }, 3262 { 3263 name: "LEAL", 3264 auxType: auxSymOff, 3265 argLen: 1, 3266 rematerializeable: true, 3267 reg: regInfo{ 3268 inputs: []inputInfo{ 3269 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3270 }, 3271 outputs: []outputInfo{ 3272 {0, 239}, // AX CX DX BX BP SI DI 3273 }, 3274 }, 3275 }, 3276 { 3277 name: "LEAL1", 3278 auxType: auxSymOff, 3279 argLen: 2, 3280 reg: regInfo{ 3281 inputs: []inputInfo{ 3282 {1, 255}, // AX CX DX BX SP BP SI DI 3283 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3284 }, 3285 outputs: []outputInfo{ 3286 {0, 239}, // AX CX DX BX BP SI DI 3287 }, 3288 }, 3289 }, 3290 { 3291 name: "LEAL2", 3292 auxType: auxSymOff, 3293 argLen: 2, 3294 reg: regInfo{ 3295 inputs: []inputInfo{ 3296 {1, 255}, // AX CX DX BX SP BP SI DI 3297 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3298 }, 3299 outputs: []outputInfo{ 3300 {0, 239}, // AX CX DX BX BP SI DI 3301 }, 3302 }, 3303 }, 3304 { 3305 name: "LEAL4", 3306 auxType: auxSymOff, 3307 argLen: 2, 3308 reg: regInfo{ 3309 inputs: []inputInfo{ 3310 {1, 255}, // AX CX DX BX SP BP SI DI 3311 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3312 }, 3313 outputs: []outputInfo{ 3314 {0, 239}, // AX CX DX BX BP SI DI 3315 }, 3316 }, 3317 }, 3318 { 3319 name: "LEAL8", 3320 auxType: auxSymOff, 3321 argLen: 2, 3322 reg: regInfo{ 3323 inputs: []inputInfo{ 3324 {1, 255}, // AX CX DX BX SP BP SI DI 3325 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3326 }, 3327 outputs: []outputInfo{ 3328 {0, 239}, // AX CX DX BX BP SI DI 3329 }, 3330 }, 3331 }, 3332 { 3333 name: "MOVBload", 3334 auxType: auxSymOff, 3335 argLen: 2, 3336 asm: x86.AMOVBLZX, 3337 reg: regInfo{ 3338 inputs: []inputInfo{ 3339 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3340 }, 3341 outputs: []outputInfo{ 3342 {0, 239}, // AX CX DX BX BP SI DI 3343 }, 3344 }, 3345 }, 3346 { 3347 name: "MOVBLSXload", 3348 auxType: auxSymOff, 3349 argLen: 2, 3350 asm: x86.AMOVBLSX, 3351 reg: regInfo{ 3352 inputs: []inputInfo{ 3353 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3354 }, 3355 outputs: []outputInfo{ 3356 {0, 239}, // AX CX DX BX BP SI DI 3357 }, 3358 }, 3359 }, 3360 { 3361 name: "MOVWload", 3362 auxType: auxSymOff, 3363 argLen: 2, 3364 asm: x86.AMOVWLZX, 3365 reg: regInfo{ 3366 inputs: []inputInfo{ 3367 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3368 }, 3369 outputs: []outputInfo{ 3370 {0, 239}, // AX CX DX BX BP SI DI 3371 }, 3372 }, 3373 }, 3374 { 3375 name: "MOVWLSXload", 3376 auxType: auxSymOff, 3377 argLen: 2, 3378 asm: x86.AMOVWLSX, 3379 reg: regInfo{ 3380 inputs: []inputInfo{ 3381 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3382 }, 3383 outputs: []outputInfo{ 3384 {0, 239}, // AX CX DX BX BP SI DI 3385 }, 3386 }, 3387 }, 3388 { 3389 name: "MOVLload", 3390 auxType: auxSymOff, 3391 argLen: 2, 3392 asm: x86.AMOVL, 3393 reg: regInfo{ 3394 inputs: []inputInfo{ 3395 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3396 }, 3397 outputs: []outputInfo{ 3398 {0, 239}, // AX CX DX BX BP SI DI 3399 }, 3400 }, 3401 }, 3402 { 3403 name: "MOVBstore", 3404 auxType: auxSymOff, 3405 argLen: 3, 3406 asm: x86.AMOVB, 3407 reg: regInfo{ 3408 inputs: []inputInfo{ 3409 {1, 255}, // AX CX DX BX SP BP SI DI 3410 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3411 }, 3412 }, 3413 }, 3414 { 3415 name: "MOVWstore", 3416 auxType: auxSymOff, 3417 argLen: 3, 3418 asm: x86.AMOVW, 3419 reg: regInfo{ 3420 inputs: []inputInfo{ 3421 {1, 255}, // AX CX DX BX SP BP SI DI 3422 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3423 }, 3424 }, 3425 }, 3426 { 3427 name: "MOVLstore", 3428 auxType: auxSymOff, 3429 argLen: 3, 3430 asm: x86.AMOVL, 3431 reg: regInfo{ 3432 inputs: []inputInfo{ 3433 {1, 255}, // AX CX DX BX SP BP SI DI 3434 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3435 }, 3436 }, 3437 }, 3438 { 3439 name: "MOVBloadidx1", 3440 auxType: auxSymOff, 3441 argLen: 3, 3442 asm: x86.AMOVBLZX, 3443 reg: regInfo{ 3444 inputs: []inputInfo{ 3445 {1, 255}, // AX CX DX BX SP BP SI DI 3446 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3447 }, 3448 outputs: []outputInfo{ 3449 {0, 239}, // AX CX DX BX BP SI DI 3450 }, 3451 }, 3452 }, 3453 { 3454 name: "MOVWloadidx1", 3455 auxType: auxSymOff, 3456 argLen: 3, 3457 asm: x86.AMOVWLZX, 3458 reg: regInfo{ 3459 inputs: []inputInfo{ 3460 {1, 255}, // AX CX DX BX SP BP SI DI 3461 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3462 }, 3463 outputs: []outputInfo{ 3464 {0, 239}, // AX CX DX BX BP SI DI 3465 }, 3466 }, 3467 }, 3468 { 3469 name: "MOVWloadidx2", 3470 auxType: auxSymOff, 3471 argLen: 3, 3472 asm: x86.AMOVWLZX, 3473 reg: regInfo{ 3474 inputs: []inputInfo{ 3475 {1, 255}, // AX CX DX BX SP BP SI DI 3476 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3477 }, 3478 outputs: []outputInfo{ 3479 {0, 239}, // AX CX DX BX BP SI DI 3480 }, 3481 }, 3482 }, 3483 { 3484 name: "MOVLloadidx1", 3485 auxType: auxSymOff, 3486 argLen: 3, 3487 asm: x86.AMOVL, 3488 reg: regInfo{ 3489 inputs: []inputInfo{ 3490 {1, 255}, // AX CX DX BX SP BP SI DI 3491 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3492 }, 3493 outputs: []outputInfo{ 3494 {0, 239}, // AX CX DX BX BP SI DI 3495 }, 3496 }, 3497 }, 3498 { 3499 name: "MOVLloadidx4", 3500 auxType: auxSymOff, 3501 argLen: 3, 3502 asm: x86.AMOVL, 3503 reg: regInfo{ 3504 inputs: []inputInfo{ 3505 {1, 255}, // AX CX DX BX SP BP SI DI 3506 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3507 }, 3508 outputs: []outputInfo{ 3509 {0, 239}, // AX CX DX BX BP SI DI 3510 }, 3511 }, 3512 }, 3513 { 3514 name: "MOVBstoreidx1", 3515 auxType: auxSymOff, 3516 argLen: 4, 3517 asm: x86.AMOVB, 3518 reg: regInfo{ 3519 inputs: []inputInfo{ 3520 {1, 255}, // AX CX DX BX SP BP SI DI 3521 {2, 255}, // AX CX DX BX SP BP SI DI 3522 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3523 }, 3524 }, 3525 }, 3526 { 3527 name: "MOVWstoreidx1", 3528 auxType: auxSymOff, 3529 argLen: 4, 3530 asm: x86.AMOVW, 3531 reg: regInfo{ 3532 inputs: []inputInfo{ 3533 {1, 255}, // AX CX DX BX SP BP SI DI 3534 {2, 255}, // AX CX DX BX SP BP SI DI 3535 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3536 }, 3537 }, 3538 }, 3539 { 3540 name: "MOVWstoreidx2", 3541 auxType: auxSymOff, 3542 argLen: 4, 3543 asm: x86.AMOVW, 3544 reg: regInfo{ 3545 inputs: []inputInfo{ 3546 {1, 255}, // AX CX DX BX SP BP SI DI 3547 {2, 255}, // AX CX DX BX SP BP SI DI 3548 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3549 }, 3550 }, 3551 }, 3552 { 3553 name: "MOVLstoreidx1", 3554 auxType: auxSymOff, 3555 argLen: 4, 3556 asm: x86.AMOVL, 3557 reg: regInfo{ 3558 inputs: []inputInfo{ 3559 {1, 255}, // AX CX DX BX SP BP SI DI 3560 {2, 255}, // AX CX DX BX SP BP SI DI 3561 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3562 }, 3563 }, 3564 }, 3565 { 3566 name: "MOVLstoreidx4", 3567 auxType: auxSymOff, 3568 argLen: 4, 3569 asm: x86.AMOVL, 3570 reg: regInfo{ 3571 inputs: []inputInfo{ 3572 {1, 255}, // AX CX DX BX SP BP SI DI 3573 {2, 255}, // AX CX DX BX SP BP SI DI 3574 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3575 }, 3576 }, 3577 }, 3578 { 3579 name: "MOVBstoreconst", 3580 auxType: auxSymValAndOff, 3581 argLen: 2, 3582 asm: x86.AMOVB, 3583 reg: regInfo{ 3584 inputs: []inputInfo{ 3585 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3586 }, 3587 }, 3588 }, 3589 { 3590 name: "MOVWstoreconst", 3591 auxType: auxSymValAndOff, 3592 argLen: 2, 3593 asm: x86.AMOVW, 3594 reg: regInfo{ 3595 inputs: []inputInfo{ 3596 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3597 }, 3598 }, 3599 }, 3600 { 3601 name: "MOVLstoreconst", 3602 auxType: auxSymValAndOff, 3603 argLen: 2, 3604 asm: x86.AMOVL, 3605 reg: regInfo{ 3606 inputs: []inputInfo{ 3607 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3608 }, 3609 }, 3610 }, 3611 { 3612 name: "MOVBstoreconstidx1", 3613 auxType: auxSymValAndOff, 3614 argLen: 3, 3615 asm: x86.AMOVB, 3616 reg: regInfo{ 3617 inputs: []inputInfo{ 3618 {1, 255}, // AX CX DX BX SP BP SI DI 3619 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3620 }, 3621 }, 3622 }, 3623 { 3624 name: "MOVWstoreconstidx1", 3625 auxType: auxSymValAndOff, 3626 argLen: 3, 3627 asm: x86.AMOVW, 3628 reg: regInfo{ 3629 inputs: []inputInfo{ 3630 {1, 255}, // AX CX DX BX SP BP SI DI 3631 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3632 }, 3633 }, 3634 }, 3635 { 3636 name: "MOVWstoreconstidx2", 3637 auxType: auxSymValAndOff, 3638 argLen: 3, 3639 asm: x86.AMOVW, 3640 reg: regInfo{ 3641 inputs: []inputInfo{ 3642 {1, 255}, // AX CX DX BX SP BP SI DI 3643 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3644 }, 3645 }, 3646 }, 3647 { 3648 name: "MOVLstoreconstidx1", 3649 auxType: auxSymValAndOff, 3650 argLen: 3, 3651 asm: x86.AMOVL, 3652 reg: regInfo{ 3653 inputs: []inputInfo{ 3654 {1, 255}, // AX CX DX BX SP BP SI DI 3655 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3656 }, 3657 }, 3658 }, 3659 { 3660 name: "MOVLstoreconstidx4", 3661 auxType: auxSymValAndOff, 3662 argLen: 3, 3663 asm: x86.AMOVL, 3664 reg: regInfo{ 3665 inputs: []inputInfo{ 3666 {1, 255}, // AX CX DX BX SP BP SI DI 3667 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3668 }, 3669 }, 3670 }, 3671 { 3672 name: "DUFFZERO", 3673 auxType: auxInt64, 3674 argLen: 3, 3675 reg: regInfo{ 3676 inputs: []inputInfo{ 3677 {0, 128}, // DI 3678 {1, 1}, // AX 3679 }, 3680 clobbers: 130, // CX DI 3681 }, 3682 }, 3683 { 3684 name: "REPSTOSL", 3685 argLen: 4, 3686 reg: regInfo{ 3687 inputs: []inputInfo{ 3688 {0, 128}, // DI 3689 {1, 2}, // CX 3690 {2, 1}, // AX 3691 }, 3692 clobbers: 130, // CX DI 3693 }, 3694 }, 3695 { 3696 name: "CALLstatic", 3697 auxType: auxSymOff, 3698 argLen: 1, 3699 clobberFlags: true, 3700 reg: regInfo{ 3701 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 3702 }, 3703 }, 3704 { 3705 name: "CALLclosure", 3706 auxType: auxInt64, 3707 argLen: 3, 3708 clobberFlags: true, 3709 reg: regInfo{ 3710 inputs: []inputInfo{ 3711 {1, 4}, // DX 3712 {0, 255}, // AX CX DX BX SP BP SI DI 3713 }, 3714 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 3715 }, 3716 }, 3717 { 3718 name: "CALLdefer", 3719 auxType: auxInt64, 3720 argLen: 1, 3721 clobberFlags: true, 3722 reg: regInfo{ 3723 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 3724 }, 3725 }, 3726 { 3727 name: "CALLgo", 3728 auxType: auxInt64, 3729 argLen: 1, 3730 clobberFlags: true, 3731 reg: regInfo{ 3732 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 3733 }, 3734 }, 3735 { 3736 name: "CALLinter", 3737 auxType: auxInt64, 3738 argLen: 2, 3739 clobberFlags: true, 3740 reg: regInfo{ 3741 inputs: []inputInfo{ 3742 {0, 239}, // AX CX DX BX BP SI DI 3743 }, 3744 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 3745 }, 3746 }, 3747 { 3748 name: "DUFFCOPY", 3749 auxType: auxInt64, 3750 argLen: 3, 3751 clobberFlags: true, 3752 reg: regInfo{ 3753 inputs: []inputInfo{ 3754 {0, 128}, // DI 3755 {1, 64}, // SI 3756 }, 3757 clobbers: 194, // CX SI DI 3758 }, 3759 }, 3760 { 3761 name: "REPMOVSL", 3762 argLen: 4, 3763 reg: regInfo{ 3764 inputs: []inputInfo{ 3765 {0, 128}, // DI 3766 {1, 64}, // SI 3767 {2, 2}, // CX 3768 }, 3769 clobbers: 194, // CX SI DI 3770 }, 3771 }, 3772 { 3773 name: "InvertFlags", 3774 argLen: 1, 3775 reg: regInfo{}, 3776 }, 3777 { 3778 name: "LoweredGetG", 3779 argLen: 1, 3780 reg: regInfo{ 3781 outputs: []outputInfo{ 3782 {0, 239}, // AX CX DX BX BP SI DI 3783 }, 3784 }, 3785 }, 3786 { 3787 name: "LoweredGetClosurePtr", 3788 argLen: 0, 3789 reg: regInfo{ 3790 outputs: []outputInfo{ 3791 {0, 4}, // DX 3792 }, 3793 }, 3794 }, 3795 { 3796 name: "LoweredNilCheck", 3797 argLen: 2, 3798 clobberFlags: true, 3799 reg: regInfo{ 3800 inputs: []inputInfo{ 3801 {0, 255}, // AX CX DX BX SP BP SI DI 3802 }, 3803 }, 3804 }, 3805 { 3806 name: "MOVLconvert", 3807 argLen: 2, 3808 asm: x86.AMOVL, 3809 reg: regInfo{ 3810 inputs: []inputInfo{ 3811 {0, 239}, // AX CX DX BX BP SI DI 3812 }, 3813 outputs: []outputInfo{ 3814 {0, 239}, // AX CX DX BX BP SI DI 3815 }, 3816 }, 3817 }, 3818 { 3819 name: "FlagEQ", 3820 argLen: 0, 3821 reg: regInfo{}, 3822 }, 3823 { 3824 name: "FlagLT_ULT", 3825 argLen: 0, 3826 reg: regInfo{}, 3827 }, 3828 { 3829 name: "FlagLT_UGT", 3830 argLen: 0, 3831 reg: regInfo{}, 3832 }, 3833 { 3834 name: "FlagGT_UGT", 3835 argLen: 0, 3836 reg: regInfo{}, 3837 }, 3838 { 3839 name: "FlagGT_ULT", 3840 argLen: 0, 3841 reg: regInfo{}, 3842 }, 3843 { 3844 name: "FCHS", 3845 argLen: 1, 3846 reg: regInfo{ 3847 inputs: []inputInfo{ 3848 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3849 }, 3850 outputs: []outputInfo{ 3851 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3852 }, 3853 }, 3854 }, 3855 { 3856 name: "MOVSSconst1", 3857 auxType: auxFloat32, 3858 argLen: 0, 3859 reg: regInfo{ 3860 outputs: []outputInfo{ 3861 {0, 239}, // AX CX DX BX BP SI DI 3862 }, 3863 }, 3864 }, 3865 { 3866 name: "MOVSDconst1", 3867 auxType: auxFloat64, 3868 argLen: 0, 3869 reg: regInfo{ 3870 outputs: []outputInfo{ 3871 {0, 239}, // AX CX DX BX BP SI DI 3872 }, 3873 }, 3874 }, 3875 { 3876 name: "MOVSSconst2", 3877 argLen: 1, 3878 asm: x86.AMOVSS, 3879 reg: regInfo{ 3880 inputs: []inputInfo{ 3881 {0, 239}, // AX CX DX BX BP SI DI 3882 }, 3883 outputs: []outputInfo{ 3884 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3885 }, 3886 }, 3887 }, 3888 { 3889 name: "MOVSDconst2", 3890 argLen: 1, 3891 asm: x86.AMOVSD, 3892 reg: regInfo{ 3893 inputs: []inputInfo{ 3894 {0, 239}, // AX CX DX BX BP SI DI 3895 }, 3896 outputs: []outputInfo{ 3897 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3898 }, 3899 }, 3900 }, 3901 3902 { 3903 name: "ADDSS", 3904 argLen: 2, 3905 commutative: true, 3906 resultInArg0: true, 3907 asm: x86.AADDSS, 3908 reg: regInfo{ 3909 inputs: []inputInfo{ 3910 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3911 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3912 }, 3913 outputs: []outputInfo{ 3914 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3915 }, 3916 }, 3917 }, 3918 { 3919 name: "ADDSD", 3920 argLen: 2, 3921 commutative: true, 3922 resultInArg0: true, 3923 asm: x86.AADDSD, 3924 reg: regInfo{ 3925 inputs: []inputInfo{ 3926 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3927 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3928 }, 3929 outputs: []outputInfo{ 3930 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3931 }, 3932 }, 3933 }, 3934 { 3935 name: "SUBSS", 3936 argLen: 2, 3937 resultInArg0: true, 3938 asm: x86.ASUBSS, 3939 reg: regInfo{ 3940 inputs: []inputInfo{ 3941 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 3942 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 3943 }, 3944 clobbers: 2147483648, // X15 3945 outputs: []outputInfo{ 3946 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 3947 }, 3948 }, 3949 }, 3950 { 3951 name: "SUBSD", 3952 argLen: 2, 3953 resultInArg0: true, 3954 asm: x86.ASUBSD, 3955 reg: regInfo{ 3956 inputs: []inputInfo{ 3957 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 3958 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 3959 }, 3960 clobbers: 2147483648, // X15 3961 outputs: []outputInfo{ 3962 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 3963 }, 3964 }, 3965 }, 3966 { 3967 name: "MULSS", 3968 argLen: 2, 3969 commutative: true, 3970 resultInArg0: true, 3971 asm: x86.AMULSS, 3972 reg: regInfo{ 3973 inputs: []inputInfo{ 3974 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3975 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3976 }, 3977 outputs: []outputInfo{ 3978 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3979 }, 3980 }, 3981 }, 3982 { 3983 name: "MULSD", 3984 argLen: 2, 3985 commutative: true, 3986 resultInArg0: true, 3987 asm: x86.AMULSD, 3988 reg: regInfo{ 3989 inputs: []inputInfo{ 3990 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3991 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3992 }, 3993 outputs: []outputInfo{ 3994 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3995 }, 3996 }, 3997 }, 3998 { 3999 name: "DIVSS", 4000 argLen: 2, 4001 resultInArg0: true, 4002 asm: x86.ADIVSS, 4003 reg: regInfo{ 4004 inputs: []inputInfo{ 4005 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 4006 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 4007 }, 4008 clobbers: 2147483648, // X15 4009 outputs: []outputInfo{ 4010 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 4011 }, 4012 }, 4013 }, 4014 { 4015 name: "DIVSD", 4016 argLen: 2, 4017 resultInArg0: true, 4018 asm: x86.ADIVSD, 4019 reg: regInfo{ 4020 inputs: []inputInfo{ 4021 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 4022 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 4023 }, 4024 clobbers: 2147483648, // X15 4025 outputs: []outputInfo{ 4026 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 4027 }, 4028 }, 4029 }, 4030 { 4031 name: "MOVSSload", 4032 auxType: auxSymOff, 4033 argLen: 2, 4034 asm: x86.AMOVSS, 4035 reg: regInfo{ 4036 inputs: []inputInfo{ 4037 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4038 }, 4039 outputs: []outputInfo{ 4040 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4041 }, 4042 }, 4043 }, 4044 { 4045 name: "MOVSDload", 4046 auxType: auxSymOff, 4047 argLen: 2, 4048 asm: x86.AMOVSD, 4049 reg: regInfo{ 4050 inputs: []inputInfo{ 4051 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4052 }, 4053 outputs: []outputInfo{ 4054 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4055 }, 4056 }, 4057 }, 4058 { 4059 name: "MOVSSconst", 4060 auxType: auxFloat32, 4061 argLen: 0, 4062 rematerializeable: true, 4063 asm: x86.AMOVSS, 4064 reg: regInfo{ 4065 outputs: []outputInfo{ 4066 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4067 }, 4068 }, 4069 }, 4070 { 4071 name: "MOVSDconst", 4072 auxType: auxFloat64, 4073 argLen: 0, 4074 rematerializeable: true, 4075 asm: x86.AMOVSD, 4076 reg: regInfo{ 4077 outputs: []outputInfo{ 4078 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4079 }, 4080 }, 4081 }, 4082 { 4083 name: "MOVSSloadidx1", 4084 auxType: auxSymOff, 4085 argLen: 3, 4086 asm: x86.AMOVSS, 4087 reg: regInfo{ 4088 inputs: []inputInfo{ 4089 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4090 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4091 }, 4092 outputs: []outputInfo{ 4093 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4094 }, 4095 }, 4096 }, 4097 { 4098 name: "MOVSSloadidx4", 4099 auxType: auxSymOff, 4100 argLen: 3, 4101 asm: x86.AMOVSS, 4102 reg: regInfo{ 4103 inputs: []inputInfo{ 4104 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4105 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4106 }, 4107 outputs: []outputInfo{ 4108 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4109 }, 4110 }, 4111 }, 4112 { 4113 name: "MOVSDloadidx1", 4114 auxType: auxSymOff, 4115 argLen: 3, 4116 asm: x86.AMOVSD, 4117 reg: regInfo{ 4118 inputs: []inputInfo{ 4119 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4120 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4121 }, 4122 outputs: []outputInfo{ 4123 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4124 }, 4125 }, 4126 }, 4127 { 4128 name: "MOVSDloadidx8", 4129 auxType: auxSymOff, 4130 argLen: 3, 4131 asm: x86.AMOVSD, 4132 reg: regInfo{ 4133 inputs: []inputInfo{ 4134 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4135 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4136 }, 4137 outputs: []outputInfo{ 4138 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4139 }, 4140 }, 4141 }, 4142 { 4143 name: "MOVSSstore", 4144 auxType: auxSymOff, 4145 argLen: 3, 4146 asm: x86.AMOVSS, 4147 reg: regInfo{ 4148 inputs: []inputInfo{ 4149 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4150 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4151 }, 4152 }, 4153 }, 4154 { 4155 name: "MOVSDstore", 4156 auxType: auxSymOff, 4157 argLen: 3, 4158 asm: x86.AMOVSD, 4159 reg: regInfo{ 4160 inputs: []inputInfo{ 4161 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4162 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4163 }, 4164 }, 4165 }, 4166 { 4167 name: "MOVSSstoreidx1", 4168 auxType: auxSymOff, 4169 argLen: 4, 4170 asm: x86.AMOVSS, 4171 reg: regInfo{ 4172 inputs: []inputInfo{ 4173 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4174 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4175 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4176 }, 4177 }, 4178 }, 4179 { 4180 name: "MOVSSstoreidx4", 4181 auxType: auxSymOff, 4182 argLen: 4, 4183 asm: x86.AMOVSS, 4184 reg: regInfo{ 4185 inputs: []inputInfo{ 4186 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4187 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4188 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4189 }, 4190 }, 4191 }, 4192 { 4193 name: "MOVSDstoreidx1", 4194 auxType: auxSymOff, 4195 argLen: 4, 4196 asm: x86.AMOVSD, 4197 reg: regInfo{ 4198 inputs: []inputInfo{ 4199 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4200 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4201 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4202 }, 4203 }, 4204 }, 4205 { 4206 name: "MOVSDstoreidx8", 4207 auxType: auxSymOff, 4208 argLen: 4, 4209 asm: x86.AMOVSD, 4210 reg: regInfo{ 4211 inputs: []inputInfo{ 4212 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4213 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4214 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4215 }, 4216 }, 4217 }, 4218 { 4219 name: "ADDQ", 4220 argLen: 2, 4221 commutative: true, 4222 clobberFlags: true, 4223 asm: x86.AADDQ, 4224 reg: regInfo{ 4225 inputs: []inputInfo{ 4226 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4227 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4228 }, 4229 outputs: []outputInfo{ 4230 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4231 }, 4232 }, 4233 }, 4234 { 4235 name: "ADDL", 4236 argLen: 2, 4237 commutative: true, 4238 clobberFlags: true, 4239 asm: x86.AADDL, 4240 reg: regInfo{ 4241 inputs: []inputInfo{ 4242 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4243 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4244 }, 4245 outputs: []outputInfo{ 4246 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4247 }, 4248 }, 4249 }, 4250 { 4251 name: "ADDQconst", 4252 auxType: auxInt64, 4253 argLen: 1, 4254 clobberFlags: true, 4255 asm: x86.AADDQ, 4256 reg: regInfo{ 4257 inputs: []inputInfo{ 4258 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4259 }, 4260 outputs: []outputInfo{ 4261 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4262 }, 4263 }, 4264 }, 4265 { 4266 name: "ADDLconst", 4267 auxType: auxInt32, 4268 argLen: 1, 4269 clobberFlags: true, 4270 asm: x86.AADDL, 4271 reg: regInfo{ 4272 inputs: []inputInfo{ 4273 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4274 }, 4275 outputs: []outputInfo{ 4276 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4277 }, 4278 }, 4279 }, 4280 { 4281 name: "SUBQ", 4282 argLen: 2, 4283 resultInArg0: true, 4284 clobberFlags: true, 4285 asm: x86.ASUBQ, 4286 reg: regInfo{ 4287 inputs: []inputInfo{ 4288 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4289 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4290 }, 4291 outputs: []outputInfo{ 4292 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4293 }, 4294 }, 4295 }, 4296 { 4297 name: "SUBL", 4298 argLen: 2, 4299 resultInArg0: true, 4300 clobberFlags: true, 4301 asm: x86.ASUBL, 4302 reg: regInfo{ 4303 inputs: []inputInfo{ 4304 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4305 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4306 }, 4307 outputs: []outputInfo{ 4308 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4309 }, 4310 }, 4311 }, 4312 { 4313 name: "SUBQconst", 4314 auxType: auxInt64, 4315 argLen: 1, 4316 resultInArg0: true, 4317 clobberFlags: true, 4318 asm: x86.ASUBQ, 4319 reg: regInfo{ 4320 inputs: []inputInfo{ 4321 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4322 }, 4323 outputs: []outputInfo{ 4324 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4325 }, 4326 }, 4327 }, 4328 { 4329 name: "SUBLconst", 4330 auxType: auxInt32, 4331 argLen: 1, 4332 resultInArg0: true, 4333 clobberFlags: true, 4334 asm: x86.ASUBL, 4335 reg: regInfo{ 4336 inputs: []inputInfo{ 4337 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4338 }, 4339 outputs: []outputInfo{ 4340 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4341 }, 4342 }, 4343 }, 4344 { 4345 name: "MULQ", 4346 argLen: 2, 4347 commutative: true, 4348 resultInArg0: true, 4349 clobberFlags: true, 4350 asm: x86.AIMULQ, 4351 reg: regInfo{ 4352 inputs: []inputInfo{ 4353 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4354 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4355 }, 4356 outputs: []outputInfo{ 4357 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4358 }, 4359 }, 4360 }, 4361 { 4362 name: "MULL", 4363 argLen: 2, 4364 commutative: true, 4365 resultInArg0: true, 4366 clobberFlags: true, 4367 asm: x86.AIMULL, 4368 reg: regInfo{ 4369 inputs: []inputInfo{ 4370 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4371 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4372 }, 4373 outputs: []outputInfo{ 4374 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4375 }, 4376 }, 4377 }, 4378 { 4379 name: "MULQconst", 4380 auxType: auxInt64, 4381 argLen: 1, 4382 resultInArg0: true, 4383 clobberFlags: true, 4384 asm: x86.AIMULQ, 4385 reg: regInfo{ 4386 inputs: []inputInfo{ 4387 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4388 }, 4389 outputs: []outputInfo{ 4390 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4391 }, 4392 }, 4393 }, 4394 { 4395 name: "MULLconst", 4396 auxType: auxInt32, 4397 argLen: 1, 4398 resultInArg0: true, 4399 clobberFlags: true, 4400 asm: x86.AIMULL, 4401 reg: regInfo{ 4402 inputs: []inputInfo{ 4403 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4404 }, 4405 outputs: []outputInfo{ 4406 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4407 }, 4408 }, 4409 }, 4410 { 4411 name: "HMULQ", 4412 argLen: 2, 4413 clobberFlags: true, 4414 asm: x86.AIMULQ, 4415 reg: regInfo{ 4416 inputs: []inputInfo{ 4417 {0, 1}, // AX 4418 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4419 }, 4420 clobbers: 1, // AX 4421 outputs: []outputInfo{ 4422 {0, 4}, // DX 4423 }, 4424 }, 4425 }, 4426 { 4427 name: "HMULL", 4428 argLen: 2, 4429 clobberFlags: true, 4430 asm: x86.AIMULL, 4431 reg: regInfo{ 4432 inputs: []inputInfo{ 4433 {0, 1}, // AX 4434 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4435 }, 4436 clobbers: 1, // AX 4437 outputs: []outputInfo{ 4438 {0, 4}, // DX 4439 }, 4440 }, 4441 }, 4442 { 4443 name: "HMULW", 4444 argLen: 2, 4445 clobberFlags: true, 4446 asm: x86.AIMULW, 4447 reg: regInfo{ 4448 inputs: []inputInfo{ 4449 {0, 1}, // AX 4450 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4451 }, 4452 clobbers: 1, // AX 4453 outputs: []outputInfo{ 4454 {0, 4}, // DX 4455 }, 4456 }, 4457 }, 4458 { 4459 name: "HMULB", 4460 argLen: 2, 4461 clobberFlags: true, 4462 asm: x86.AIMULB, 4463 reg: regInfo{ 4464 inputs: []inputInfo{ 4465 {0, 1}, // AX 4466 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4467 }, 4468 clobbers: 1, // AX 4469 outputs: []outputInfo{ 4470 {0, 4}, // DX 4471 }, 4472 }, 4473 }, 4474 { 4475 name: "HMULQU", 4476 argLen: 2, 4477 clobberFlags: true, 4478 asm: x86.AMULQ, 4479 reg: regInfo{ 4480 inputs: []inputInfo{ 4481 {0, 1}, // AX 4482 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4483 }, 4484 clobbers: 1, // AX 4485 outputs: []outputInfo{ 4486 {0, 4}, // DX 4487 }, 4488 }, 4489 }, 4490 { 4491 name: "HMULLU", 4492 argLen: 2, 4493 clobberFlags: true, 4494 asm: x86.AMULL, 4495 reg: regInfo{ 4496 inputs: []inputInfo{ 4497 {0, 1}, // AX 4498 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4499 }, 4500 clobbers: 1, // AX 4501 outputs: []outputInfo{ 4502 {0, 4}, // DX 4503 }, 4504 }, 4505 }, 4506 { 4507 name: "HMULWU", 4508 argLen: 2, 4509 clobberFlags: true, 4510 asm: x86.AMULW, 4511 reg: regInfo{ 4512 inputs: []inputInfo{ 4513 {0, 1}, // AX 4514 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4515 }, 4516 clobbers: 1, // AX 4517 outputs: []outputInfo{ 4518 {0, 4}, // DX 4519 }, 4520 }, 4521 }, 4522 { 4523 name: "HMULBU", 4524 argLen: 2, 4525 clobberFlags: true, 4526 asm: x86.AMULB, 4527 reg: regInfo{ 4528 inputs: []inputInfo{ 4529 {0, 1}, // AX 4530 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4531 }, 4532 clobbers: 1, // AX 4533 outputs: []outputInfo{ 4534 {0, 4}, // DX 4535 }, 4536 }, 4537 }, 4538 { 4539 name: "AVGQU", 4540 argLen: 2, 4541 commutative: true, 4542 resultInArg0: true, 4543 clobberFlags: true, 4544 reg: regInfo{ 4545 inputs: []inputInfo{ 4546 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4547 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4548 }, 4549 outputs: []outputInfo{ 4550 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4551 }, 4552 }, 4553 }, 4554 { 4555 name: "DIVQ", 4556 argLen: 2, 4557 clobberFlags: true, 4558 asm: x86.AIDIVQ, 4559 reg: regInfo{ 4560 inputs: []inputInfo{ 4561 {0, 1}, // AX 4562 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4563 }, 4564 outputs: []outputInfo{ 4565 {0, 1}, // AX 4566 {1, 4}, // DX 4567 }, 4568 }, 4569 }, 4570 { 4571 name: "DIVL", 4572 argLen: 2, 4573 clobberFlags: true, 4574 asm: x86.AIDIVL, 4575 reg: regInfo{ 4576 inputs: []inputInfo{ 4577 {0, 1}, // AX 4578 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4579 }, 4580 outputs: []outputInfo{ 4581 {0, 1}, // AX 4582 {1, 4}, // DX 4583 }, 4584 }, 4585 }, 4586 { 4587 name: "DIVW", 4588 argLen: 2, 4589 clobberFlags: true, 4590 asm: x86.AIDIVW, 4591 reg: regInfo{ 4592 inputs: []inputInfo{ 4593 {0, 1}, // AX 4594 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4595 }, 4596 outputs: []outputInfo{ 4597 {0, 1}, // AX 4598 {1, 4}, // DX 4599 }, 4600 }, 4601 }, 4602 { 4603 name: "DIVQU", 4604 argLen: 2, 4605 clobberFlags: true, 4606 asm: x86.ADIVQ, 4607 reg: regInfo{ 4608 inputs: []inputInfo{ 4609 {0, 1}, // AX 4610 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4611 }, 4612 outputs: []outputInfo{ 4613 {0, 1}, // AX 4614 {1, 4}, // DX 4615 }, 4616 }, 4617 }, 4618 { 4619 name: "DIVLU", 4620 argLen: 2, 4621 clobberFlags: true, 4622 asm: x86.ADIVL, 4623 reg: regInfo{ 4624 inputs: []inputInfo{ 4625 {0, 1}, // AX 4626 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4627 }, 4628 outputs: []outputInfo{ 4629 {0, 1}, // AX 4630 {1, 4}, // DX 4631 }, 4632 }, 4633 }, 4634 { 4635 name: "DIVWU", 4636 argLen: 2, 4637 clobberFlags: true, 4638 asm: x86.ADIVW, 4639 reg: regInfo{ 4640 inputs: []inputInfo{ 4641 {0, 1}, // AX 4642 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4643 }, 4644 outputs: []outputInfo{ 4645 {0, 1}, // AX 4646 {1, 4}, // DX 4647 }, 4648 }, 4649 }, 4650 { 4651 name: "ANDQ", 4652 argLen: 2, 4653 commutative: true, 4654 resultInArg0: true, 4655 clobberFlags: true, 4656 asm: x86.AANDQ, 4657 reg: regInfo{ 4658 inputs: []inputInfo{ 4659 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4660 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4661 }, 4662 outputs: []outputInfo{ 4663 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4664 }, 4665 }, 4666 }, 4667 { 4668 name: "ANDL", 4669 argLen: 2, 4670 commutative: true, 4671 resultInArg0: true, 4672 clobberFlags: true, 4673 asm: x86.AANDL, 4674 reg: regInfo{ 4675 inputs: []inputInfo{ 4676 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4677 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4678 }, 4679 outputs: []outputInfo{ 4680 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4681 }, 4682 }, 4683 }, 4684 { 4685 name: "ANDQconst", 4686 auxType: auxInt64, 4687 argLen: 1, 4688 resultInArg0: true, 4689 clobberFlags: true, 4690 asm: x86.AANDQ, 4691 reg: regInfo{ 4692 inputs: []inputInfo{ 4693 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4694 }, 4695 outputs: []outputInfo{ 4696 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4697 }, 4698 }, 4699 }, 4700 { 4701 name: "ANDLconst", 4702 auxType: auxInt32, 4703 argLen: 1, 4704 resultInArg0: true, 4705 clobberFlags: true, 4706 asm: x86.AANDL, 4707 reg: regInfo{ 4708 inputs: []inputInfo{ 4709 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4710 }, 4711 outputs: []outputInfo{ 4712 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4713 }, 4714 }, 4715 }, 4716 { 4717 name: "ORQ", 4718 argLen: 2, 4719 commutative: true, 4720 resultInArg0: true, 4721 clobberFlags: true, 4722 asm: x86.AORQ, 4723 reg: regInfo{ 4724 inputs: []inputInfo{ 4725 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4726 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4727 }, 4728 outputs: []outputInfo{ 4729 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4730 }, 4731 }, 4732 }, 4733 { 4734 name: "ORL", 4735 argLen: 2, 4736 commutative: true, 4737 resultInArg0: true, 4738 clobberFlags: true, 4739 asm: x86.AORL, 4740 reg: regInfo{ 4741 inputs: []inputInfo{ 4742 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4743 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4744 }, 4745 outputs: []outputInfo{ 4746 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4747 }, 4748 }, 4749 }, 4750 { 4751 name: "ORQconst", 4752 auxType: auxInt64, 4753 argLen: 1, 4754 resultInArg0: true, 4755 clobberFlags: true, 4756 asm: x86.AORQ, 4757 reg: regInfo{ 4758 inputs: []inputInfo{ 4759 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4760 }, 4761 outputs: []outputInfo{ 4762 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4763 }, 4764 }, 4765 }, 4766 { 4767 name: "ORLconst", 4768 auxType: auxInt32, 4769 argLen: 1, 4770 resultInArg0: true, 4771 clobberFlags: true, 4772 asm: x86.AORL, 4773 reg: regInfo{ 4774 inputs: []inputInfo{ 4775 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4776 }, 4777 outputs: []outputInfo{ 4778 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4779 }, 4780 }, 4781 }, 4782 { 4783 name: "XORQ", 4784 argLen: 2, 4785 commutative: true, 4786 resultInArg0: true, 4787 clobberFlags: true, 4788 asm: x86.AXORQ, 4789 reg: regInfo{ 4790 inputs: []inputInfo{ 4791 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4792 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4793 }, 4794 outputs: []outputInfo{ 4795 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4796 }, 4797 }, 4798 }, 4799 { 4800 name: "XORL", 4801 argLen: 2, 4802 commutative: true, 4803 resultInArg0: true, 4804 clobberFlags: true, 4805 asm: x86.AXORL, 4806 reg: regInfo{ 4807 inputs: []inputInfo{ 4808 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4809 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4810 }, 4811 outputs: []outputInfo{ 4812 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4813 }, 4814 }, 4815 }, 4816 { 4817 name: "XORQconst", 4818 auxType: auxInt64, 4819 argLen: 1, 4820 resultInArg0: true, 4821 clobberFlags: true, 4822 asm: x86.AXORQ, 4823 reg: regInfo{ 4824 inputs: []inputInfo{ 4825 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4826 }, 4827 outputs: []outputInfo{ 4828 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4829 }, 4830 }, 4831 }, 4832 { 4833 name: "XORLconst", 4834 auxType: auxInt32, 4835 argLen: 1, 4836 resultInArg0: true, 4837 clobberFlags: true, 4838 asm: x86.AXORL, 4839 reg: regInfo{ 4840 inputs: []inputInfo{ 4841 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4842 }, 4843 outputs: []outputInfo{ 4844 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4845 }, 4846 }, 4847 }, 4848 { 4849 name: "CMPQ", 4850 argLen: 2, 4851 asm: x86.ACMPQ, 4852 reg: regInfo{ 4853 inputs: []inputInfo{ 4854 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4855 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4856 }, 4857 }, 4858 }, 4859 { 4860 name: "CMPL", 4861 argLen: 2, 4862 asm: x86.ACMPL, 4863 reg: regInfo{ 4864 inputs: []inputInfo{ 4865 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4866 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4867 }, 4868 }, 4869 }, 4870 { 4871 name: "CMPW", 4872 argLen: 2, 4873 asm: x86.ACMPW, 4874 reg: regInfo{ 4875 inputs: []inputInfo{ 4876 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4877 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4878 }, 4879 }, 4880 }, 4881 { 4882 name: "CMPB", 4883 argLen: 2, 4884 asm: x86.ACMPB, 4885 reg: regInfo{ 4886 inputs: []inputInfo{ 4887 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4888 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4889 }, 4890 }, 4891 }, 4892 { 4893 name: "CMPQconst", 4894 auxType: auxInt64, 4895 argLen: 1, 4896 asm: x86.ACMPQ, 4897 reg: regInfo{ 4898 inputs: []inputInfo{ 4899 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4900 }, 4901 }, 4902 }, 4903 { 4904 name: "CMPLconst", 4905 auxType: auxInt32, 4906 argLen: 1, 4907 asm: x86.ACMPL, 4908 reg: regInfo{ 4909 inputs: []inputInfo{ 4910 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4911 }, 4912 }, 4913 }, 4914 { 4915 name: "CMPWconst", 4916 auxType: auxInt16, 4917 argLen: 1, 4918 asm: x86.ACMPW, 4919 reg: regInfo{ 4920 inputs: []inputInfo{ 4921 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4922 }, 4923 }, 4924 }, 4925 { 4926 name: "CMPBconst", 4927 auxType: auxInt8, 4928 argLen: 1, 4929 asm: x86.ACMPB, 4930 reg: regInfo{ 4931 inputs: []inputInfo{ 4932 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4933 }, 4934 }, 4935 }, 4936 { 4937 name: "UCOMISS", 4938 argLen: 2, 4939 asm: x86.AUCOMISS, 4940 reg: regInfo{ 4941 inputs: []inputInfo{ 4942 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4943 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4944 }, 4945 }, 4946 }, 4947 { 4948 name: "UCOMISD", 4949 argLen: 2, 4950 asm: x86.AUCOMISD, 4951 reg: regInfo{ 4952 inputs: []inputInfo{ 4953 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4954 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4955 }, 4956 }, 4957 }, 4958 { 4959 name: "TESTQ", 4960 argLen: 2, 4961 asm: x86.ATESTQ, 4962 reg: regInfo{ 4963 inputs: []inputInfo{ 4964 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4965 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4966 }, 4967 }, 4968 }, 4969 { 4970 name: "TESTL", 4971 argLen: 2, 4972 asm: x86.ATESTL, 4973 reg: regInfo{ 4974 inputs: []inputInfo{ 4975 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4976 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4977 }, 4978 }, 4979 }, 4980 { 4981 name: "TESTW", 4982 argLen: 2, 4983 asm: x86.ATESTW, 4984 reg: regInfo{ 4985 inputs: []inputInfo{ 4986 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4987 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4988 }, 4989 }, 4990 }, 4991 { 4992 name: "TESTB", 4993 argLen: 2, 4994 asm: x86.ATESTB, 4995 reg: regInfo{ 4996 inputs: []inputInfo{ 4997 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4998 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4999 }, 5000 }, 5001 }, 5002 { 5003 name: "TESTQconst", 5004 auxType: auxInt64, 5005 argLen: 1, 5006 asm: x86.ATESTQ, 5007 reg: regInfo{ 5008 inputs: []inputInfo{ 5009 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5010 }, 5011 }, 5012 }, 5013 { 5014 name: "TESTLconst", 5015 auxType: auxInt32, 5016 argLen: 1, 5017 asm: x86.ATESTL, 5018 reg: regInfo{ 5019 inputs: []inputInfo{ 5020 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5021 }, 5022 }, 5023 }, 5024 { 5025 name: "TESTWconst", 5026 auxType: auxInt16, 5027 argLen: 1, 5028 asm: x86.ATESTW, 5029 reg: regInfo{ 5030 inputs: []inputInfo{ 5031 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5032 }, 5033 }, 5034 }, 5035 { 5036 name: "TESTBconst", 5037 auxType: auxInt8, 5038 argLen: 1, 5039 asm: x86.ATESTB, 5040 reg: regInfo{ 5041 inputs: []inputInfo{ 5042 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5043 }, 5044 }, 5045 }, 5046 { 5047 name: "SHLQ", 5048 argLen: 2, 5049 resultInArg0: true, 5050 clobberFlags: true, 5051 asm: x86.ASHLQ, 5052 reg: regInfo{ 5053 inputs: []inputInfo{ 5054 {1, 2}, // CX 5055 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5056 }, 5057 outputs: []outputInfo{ 5058 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5059 }, 5060 }, 5061 }, 5062 { 5063 name: "SHLL", 5064 argLen: 2, 5065 resultInArg0: true, 5066 clobberFlags: true, 5067 asm: x86.ASHLL, 5068 reg: regInfo{ 5069 inputs: []inputInfo{ 5070 {1, 2}, // CX 5071 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5072 }, 5073 outputs: []outputInfo{ 5074 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5075 }, 5076 }, 5077 }, 5078 { 5079 name: "SHLQconst", 5080 auxType: auxInt64, 5081 argLen: 1, 5082 resultInArg0: true, 5083 clobberFlags: true, 5084 asm: x86.ASHLQ, 5085 reg: regInfo{ 5086 inputs: []inputInfo{ 5087 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5088 }, 5089 outputs: []outputInfo{ 5090 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5091 }, 5092 }, 5093 }, 5094 { 5095 name: "SHLLconst", 5096 auxType: auxInt32, 5097 argLen: 1, 5098 resultInArg0: true, 5099 clobberFlags: true, 5100 asm: x86.ASHLL, 5101 reg: regInfo{ 5102 inputs: []inputInfo{ 5103 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5104 }, 5105 outputs: []outputInfo{ 5106 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5107 }, 5108 }, 5109 }, 5110 { 5111 name: "SHRQ", 5112 argLen: 2, 5113 resultInArg0: true, 5114 clobberFlags: true, 5115 asm: x86.ASHRQ, 5116 reg: regInfo{ 5117 inputs: []inputInfo{ 5118 {1, 2}, // CX 5119 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5120 }, 5121 outputs: []outputInfo{ 5122 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5123 }, 5124 }, 5125 }, 5126 { 5127 name: "SHRL", 5128 argLen: 2, 5129 resultInArg0: true, 5130 clobberFlags: true, 5131 asm: x86.ASHRL, 5132 reg: regInfo{ 5133 inputs: []inputInfo{ 5134 {1, 2}, // CX 5135 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5136 }, 5137 outputs: []outputInfo{ 5138 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5139 }, 5140 }, 5141 }, 5142 { 5143 name: "SHRW", 5144 argLen: 2, 5145 resultInArg0: true, 5146 clobberFlags: true, 5147 asm: x86.ASHRW, 5148 reg: regInfo{ 5149 inputs: []inputInfo{ 5150 {1, 2}, // CX 5151 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5152 }, 5153 outputs: []outputInfo{ 5154 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5155 }, 5156 }, 5157 }, 5158 { 5159 name: "SHRB", 5160 argLen: 2, 5161 resultInArg0: true, 5162 clobberFlags: true, 5163 asm: x86.ASHRB, 5164 reg: regInfo{ 5165 inputs: []inputInfo{ 5166 {1, 2}, // CX 5167 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5168 }, 5169 outputs: []outputInfo{ 5170 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5171 }, 5172 }, 5173 }, 5174 { 5175 name: "SHRQconst", 5176 auxType: auxInt64, 5177 argLen: 1, 5178 resultInArg0: true, 5179 clobberFlags: true, 5180 asm: x86.ASHRQ, 5181 reg: regInfo{ 5182 inputs: []inputInfo{ 5183 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5184 }, 5185 outputs: []outputInfo{ 5186 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5187 }, 5188 }, 5189 }, 5190 { 5191 name: "SHRLconst", 5192 auxType: auxInt32, 5193 argLen: 1, 5194 resultInArg0: true, 5195 clobberFlags: true, 5196 asm: x86.ASHRL, 5197 reg: regInfo{ 5198 inputs: []inputInfo{ 5199 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5200 }, 5201 outputs: []outputInfo{ 5202 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5203 }, 5204 }, 5205 }, 5206 { 5207 name: "SHRWconst", 5208 auxType: auxInt16, 5209 argLen: 1, 5210 resultInArg0: true, 5211 clobberFlags: true, 5212 asm: x86.ASHRW, 5213 reg: regInfo{ 5214 inputs: []inputInfo{ 5215 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5216 }, 5217 outputs: []outputInfo{ 5218 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5219 }, 5220 }, 5221 }, 5222 { 5223 name: "SHRBconst", 5224 auxType: auxInt8, 5225 argLen: 1, 5226 resultInArg0: true, 5227 clobberFlags: true, 5228 asm: x86.ASHRB, 5229 reg: regInfo{ 5230 inputs: []inputInfo{ 5231 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5232 }, 5233 outputs: []outputInfo{ 5234 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5235 }, 5236 }, 5237 }, 5238 { 5239 name: "SARQ", 5240 argLen: 2, 5241 resultInArg0: true, 5242 clobberFlags: true, 5243 asm: x86.ASARQ, 5244 reg: regInfo{ 5245 inputs: []inputInfo{ 5246 {1, 2}, // CX 5247 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5248 }, 5249 outputs: []outputInfo{ 5250 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5251 }, 5252 }, 5253 }, 5254 { 5255 name: "SARL", 5256 argLen: 2, 5257 resultInArg0: true, 5258 clobberFlags: true, 5259 asm: x86.ASARL, 5260 reg: regInfo{ 5261 inputs: []inputInfo{ 5262 {1, 2}, // CX 5263 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5264 }, 5265 outputs: []outputInfo{ 5266 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5267 }, 5268 }, 5269 }, 5270 { 5271 name: "SARW", 5272 argLen: 2, 5273 resultInArg0: true, 5274 clobberFlags: true, 5275 asm: x86.ASARW, 5276 reg: regInfo{ 5277 inputs: []inputInfo{ 5278 {1, 2}, // CX 5279 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5280 }, 5281 outputs: []outputInfo{ 5282 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5283 }, 5284 }, 5285 }, 5286 { 5287 name: "SARB", 5288 argLen: 2, 5289 resultInArg0: true, 5290 clobberFlags: true, 5291 asm: x86.ASARB, 5292 reg: regInfo{ 5293 inputs: []inputInfo{ 5294 {1, 2}, // CX 5295 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5296 }, 5297 outputs: []outputInfo{ 5298 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5299 }, 5300 }, 5301 }, 5302 { 5303 name: "SARQconst", 5304 auxType: auxInt64, 5305 argLen: 1, 5306 resultInArg0: true, 5307 clobberFlags: true, 5308 asm: x86.ASARQ, 5309 reg: regInfo{ 5310 inputs: []inputInfo{ 5311 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5312 }, 5313 outputs: []outputInfo{ 5314 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5315 }, 5316 }, 5317 }, 5318 { 5319 name: "SARLconst", 5320 auxType: auxInt32, 5321 argLen: 1, 5322 resultInArg0: true, 5323 clobberFlags: true, 5324 asm: x86.ASARL, 5325 reg: regInfo{ 5326 inputs: []inputInfo{ 5327 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5328 }, 5329 outputs: []outputInfo{ 5330 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5331 }, 5332 }, 5333 }, 5334 { 5335 name: "SARWconst", 5336 auxType: auxInt16, 5337 argLen: 1, 5338 resultInArg0: true, 5339 clobberFlags: true, 5340 asm: x86.ASARW, 5341 reg: regInfo{ 5342 inputs: []inputInfo{ 5343 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5344 }, 5345 outputs: []outputInfo{ 5346 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5347 }, 5348 }, 5349 }, 5350 { 5351 name: "SARBconst", 5352 auxType: auxInt8, 5353 argLen: 1, 5354 resultInArg0: true, 5355 clobberFlags: true, 5356 asm: x86.ASARB, 5357 reg: regInfo{ 5358 inputs: []inputInfo{ 5359 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5360 }, 5361 outputs: []outputInfo{ 5362 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5363 }, 5364 }, 5365 }, 5366 { 5367 name: "ROLQconst", 5368 auxType: auxInt64, 5369 argLen: 1, 5370 resultInArg0: true, 5371 clobberFlags: true, 5372 asm: x86.AROLQ, 5373 reg: regInfo{ 5374 inputs: []inputInfo{ 5375 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5376 }, 5377 outputs: []outputInfo{ 5378 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5379 }, 5380 }, 5381 }, 5382 { 5383 name: "ROLLconst", 5384 auxType: auxInt32, 5385 argLen: 1, 5386 resultInArg0: true, 5387 clobberFlags: true, 5388 asm: x86.AROLL, 5389 reg: regInfo{ 5390 inputs: []inputInfo{ 5391 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5392 }, 5393 outputs: []outputInfo{ 5394 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5395 }, 5396 }, 5397 }, 5398 { 5399 name: "ROLWconst", 5400 auxType: auxInt16, 5401 argLen: 1, 5402 resultInArg0: true, 5403 clobberFlags: true, 5404 asm: x86.AROLW, 5405 reg: regInfo{ 5406 inputs: []inputInfo{ 5407 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5408 }, 5409 outputs: []outputInfo{ 5410 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5411 }, 5412 }, 5413 }, 5414 { 5415 name: "ROLBconst", 5416 auxType: auxInt8, 5417 argLen: 1, 5418 resultInArg0: true, 5419 clobberFlags: true, 5420 asm: x86.AROLB, 5421 reg: regInfo{ 5422 inputs: []inputInfo{ 5423 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5424 }, 5425 outputs: []outputInfo{ 5426 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5427 }, 5428 }, 5429 }, 5430 { 5431 name: "NEGQ", 5432 argLen: 1, 5433 resultInArg0: true, 5434 clobberFlags: true, 5435 asm: x86.ANEGQ, 5436 reg: regInfo{ 5437 inputs: []inputInfo{ 5438 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5439 }, 5440 outputs: []outputInfo{ 5441 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5442 }, 5443 }, 5444 }, 5445 { 5446 name: "NEGL", 5447 argLen: 1, 5448 resultInArg0: true, 5449 clobberFlags: true, 5450 asm: x86.ANEGL, 5451 reg: regInfo{ 5452 inputs: []inputInfo{ 5453 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5454 }, 5455 outputs: []outputInfo{ 5456 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5457 }, 5458 }, 5459 }, 5460 { 5461 name: "NOTQ", 5462 argLen: 1, 5463 resultInArg0: true, 5464 clobberFlags: true, 5465 asm: x86.ANOTQ, 5466 reg: regInfo{ 5467 inputs: []inputInfo{ 5468 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5469 }, 5470 outputs: []outputInfo{ 5471 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5472 }, 5473 }, 5474 }, 5475 { 5476 name: "NOTL", 5477 argLen: 1, 5478 resultInArg0: true, 5479 clobberFlags: true, 5480 asm: x86.ANOTL, 5481 reg: regInfo{ 5482 inputs: []inputInfo{ 5483 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5484 }, 5485 outputs: []outputInfo{ 5486 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5487 }, 5488 }, 5489 }, 5490 { 5491 name: "BSFQ", 5492 argLen: 1, 5493 asm: x86.ABSFQ, 5494 reg: regInfo{ 5495 inputs: []inputInfo{ 5496 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5497 }, 5498 outputs: []outputInfo{ 5499 {1, 0}, 5500 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5501 }, 5502 }, 5503 }, 5504 { 5505 name: "BSFL", 5506 argLen: 1, 5507 asm: x86.ABSFL, 5508 reg: regInfo{ 5509 inputs: []inputInfo{ 5510 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5511 }, 5512 outputs: []outputInfo{ 5513 {1, 0}, 5514 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5515 }, 5516 }, 5517 }, 5518 { 5519 name: "CMOVQEQ", 5520 argLen: 3, 5521 resultInArg0: true, 5522 asm: x86.ACMOVQEQ, 5523 reg: regInfo{ 5524 inputs: []inputInfo{ 5525 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5526 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5527 }, 5528 outputs: []outputInfo{ 5529 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5530 }, 5531 }, 5532 }, 5533 { 5534 name: "CMOVLEQ", 5535 argLen: 3, 5536 resultInArg0: true, 5537 asm: x86.ACMOVLEQ, 5538 reg: regInfo{ 5539 inputs: []inputInfo{ 5540 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5541 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5542 }, 5543 outputs: []outputInfo{ 5544 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5545 }, 5546 }, 5547 }, 5548 { 5549 name: "BSWAPQ", 5550 argLen: 1, 5551 resultInArg0: true, 5552 clobberFlags: true, 5553 asm: x86.ABSWAPQ, 5554 reg: regInfo{ 5555 inputs: []inputInfo{ 5556 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5557 }, 5558 outputs: []outputInfo{ 5559 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5560 }, 5561 }, 5562 }, 5563 { 5564 name: "BSWAPL", 5565 argLen: 1, 5566 resultInArg0: true, 5567 clobberFlags: true, 5568 asm: x86.ABSWAPL, 5569 reg: regInfo{ 5570 inputs: []inputInfo{ 5571 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5572 }, 5573 outputs: []outputInfo{ 5574 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5575 }, 5576 }, 5577 }, 5578 { 5579 name: "SQRTSD", 5580 argLen: 1, 5581 asm: x86.ASQRTSD, 5582 reg: regInfo{ 5583 inputs: []inputInfo{ 5584 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5585 }, 5586 outputs: []outputInfo{ 5587 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5588 }, 5589 }, 5590 }, 5591 { 5592 name: "SBBQcarrymask", 5593 argLen: 1, 5594 asm: x86.ASBBQ, 5595 reg: regInfo{ 5596 outputs: []outputInfo{ 5597 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5598 }, 5599 }, 5600 }, 5601 { 5602 name: "SBBLcarrymask", 5603 argLen: 1, 5604 asm: x86.ASBBL, 5605 reg: regInfo{ 5606 outputs: []outputInfo{ 5607 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5608 }, 5609 }, 5610 }, 5611 { 5612 name: "SETEQ", 5613 argLen: 1, 5614 asm: x86.ASETEQ, 5615 reg: regInfo{ 5616 outputs: []outputInfo{ 5617 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5618 }, 5619 }, 5620 }, 5621 { 5622 name: "SETNE", 5623 argLen: 1, 5624 asm: x86.ASETNE, 5625 reg: regInfo{ 5626 outputs: []outputInfo{ 5627 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5628 }, 5629 }, 5630 }, 5631 { 5632 name: "SETL", 5633 argLen: 1, 5634 asm: x86.ASETLT, 5635 reg: regInfo{ 5636 outputs: []outputInfo{ 5637 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5638 }, 5639 }, 5640 }, 5641 { 5642 name: "SETLE", 5643 argLen: 1, 5644 asm: x86.ASETLE, 5645 reg: regInfo{ 5646 outputs: []outputInfo{ 5647 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5648 }, 5649 }, 5650 }, 5651 { 5652 name: "SETG", 5653 argLen: 1, 5654 asm: x86.ASETGT, 5655 reg: regInfo{ 5656 outputs: []outputInfo{ 5657 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5658 }, 5659 }, 5660 }, 5661 { 5662 name: "SETGE", 5663 argLen: 1, 5664 asm: x86.ASETGE, 5665 reg: regInfo{ 5666 outputs: []outputInfo{ 5667 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5668 }, 5669 }, 5670 }, 5671 { 5672 name: "SETB", 5673 argLen: 1, 5674 asm: x86.ASETCS, 5675 reg: regInfo{ 5676 outputs: []outputInfo{ 5677 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5678 }, 5679 }, 5680 }, 5681 { 5682 name: "SETBE", 5683 argLen: 1, 5684 asm: x86.ASETLS, 5685 reg: regInfo{ 5686 outputs: []outputInfo{ 5687 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5688 }, 5689 }, 5690 }, 5691 { 5692 name: "SETA", 5693 argLen: 1, 5694 asm: x86.ASETHI, 5695 reg: regInfo{ 5696 outputs: []outputInfo{ 5697 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5698 }, 5699 }, 5700 }, 5701 { 5702 name: "SETAE", 5703 argLen: 1, 5704 asm: x86.ASETCC, 5705 reg: regInfo{ 5706 outputs: []outputInfo{ 5707 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5708 }, 5709 }, 5710 }, 5711 { 5712 name: "SETEQF", 5713 argLen: 1, 5714 clobberFlags: true, 5715 asm: x86.ASETEQ, 5716 reg: regInfo{ 5717 clobbers: 1, // AX 5718 outputs: []outputInfo{ 5719 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5720 }, 5721 }, 5722 }, 5723 { 5724 name: "SETNEF", 5725 argLen: 1, 5726 clobberFlags: true, 5727 asm: x86.ASETNE, 5728 reg: regInfo{ 5729 clobbers: 1, // AX 5730 outputs: []outputInfo{ 5731 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5732 }, 5733 }, 5734 }, 5735 { 5736 name: "SETORD", 5737 argLen: 1, 5738 asm: x86.ASETPC, 5739 reg: regInfo{ 5740 outputs: []outputInfo{ 5741 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5742 }, 5743 }, 5744 }, 5745 { 5746 name: "SETNAN", 5747 argLen: 1, 5748 asm: x86.ASETPS, 5749 reg: regInfo{ 5750 outputs: []outputInfo{ 5751 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5752 }, 5753 }, 5754 }, 5755 { 5756 name: "SETGF", 5757 argLen: 1, 5758 asm: x86.ASETHI, 5759 reg: regInfo{ 5760 outputs: []outputInfo{ 5761 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5762 }, 5763 }, 5764 }, 5765 { 5766 name: "SETGEF", 5767 argLen: 1, 5768 asm: x86.ASETCC, 5769 reg: regInfo{ 5770 outputs: []outputInfo{ 5771 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5772 }, 5773 }, 5774 }, 5775 { 5776 name: "MOVBQSX", 5777 argLen: 1, 5778 asm: x86.AMOVBQSX, 5779 reg: regInfo{ 5780 inputs: []inputInfo{ 5781 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5782 }, 5783 outputs: []outputInfo{ 5784 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5785 }, 5786 }, 5787 }, 5788 { 5789 name: "MOVBQZX", 5790 argLen: 1, 5791 asm: x86.AMOVBLZX, 5792 reg: regInfo{ 5793 inputs: []inputInfo{ 5794 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5795 }, 5796 outputs: []outputInfo{ 5797 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5798 }, 5799 }, 5800 }, 5801 { 5802 name: "MOVWQSX", 5803 argLen: 1, 5804 asm: x86.AMOVWQSX, 5805 reg: regInfo{ 5806 inputs: []inputInfo{ 5807 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5808 }, 5809 outputs: []outputInfo{ 5810 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5811 }, 5812 }, 5813 }, 5814 { 5815 name: "MOVWQZX", 5816 argLen: 1, 5817 asm: x86.AMOVWLZX, 5818 reg: regInfo{ 5819 inputs: []inputInfo{ 5820 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5821 }, 5822 outputs: []outputInfo{ 5823 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5824 }, 5825 }, 5826 }, 5827 { 5828 name: "MOVLQSX", 5829 argLen: 1, 5830 asm: x86.AMOVLQSX, 5831 reg: regInfo{ 5832 inputs: []inputInfo{ 5833 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5834 }, 5835 outputs: []outputInfo{ 5836 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5837 }, 5838 }, 5839 }, 5840 { 5841 name: "MOVLQZX", 5842 argLen: 1, 5843 asm: x86.AMOVL, 5844 reg: regInfo{ 5845 inputs: []inputInfo{ 5846 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5847 }, 5848 outputs: []outputInfo{ 5849 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5850 }, 5851 }, 5852 }, 5853 { 5854 name: "MOVLconst", 5855 auxType: auxInt32, 5856 argLen: 0, 5857 rematerializeable: true, 5858 asm: x86.AMOVL, 5859 reg: regInfo{ 5860 outputs: []outputInfo{ 5861 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5862 }, 5863 }, 5864 }, 5865 { 5866 name: "MOVQconst", 5867 auxType: auxInt64, 5868 argLen: 0, 5869 rematerializeable: true, 5870 asm: x86.AMOVQ, 5871 reg: regInfo{ 5872 outputs: []outputInfo{ 5873 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5874 }, 5875 }, 5876 }, 5877 { 5878 name: "CVTTSD2SL", 5879 argLen: 1, 5880 asm: x86.ACVTTSD2SL, 5881 reg: regInfo{ 5882 inputs: []inputInfo{ 5883 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5884 }, 5885 outputs: []outputInfo{ 5886 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5887 }, 5888 }, 5889 }, 5890 { 5891 name: "CVTTSD2SQ", 5892 argLen: 1, 5893 asm: x86.ACVTTSD2SQ, 5894 reg: regInfo{ 5895 inputs: []inputInfo{ 5896 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5897 }, 5898 outputs: []outputInfo{ 5899 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5900 }, 5901 }, 5902 }, 5903 { 5904 name: "CVTTSS2SL", 5905 argLen: 1, 5906 asm: x86.ACVTTSS2SL, 5907 reg: regInfo{ 5908 inputs: []inputInfo{ 5909 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5910 }, 5911 outputs: []outputInfo{ 5912 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5913 }, 5914 }, 5915 }, 5916 { 5917 name: "CVTTSS2SQ", 5918 argLen: 1, 5919 asm: x86.ACVTTSS2SQ, 5920 reg: regInfo{ 5921 inputs: []inputInfo{ 5922 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5923 }, 5924 outputs: []outputInfo{ 5925 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5926 }, 5927 }, 5928 }, 5929 { 5930 name: "CVTSL2SS", 5931 argLen: 1, 5932 asm: x86.ACVTSL2SS, 5933 reg: regInfo{ 5934 inputs: []inputInfo{ 5935 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5936 }, 5937 outputs: []outputInfo{ 5938 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5939 }, 5940 }, 5941 }, 5942 { 5943 name: "CVTSL2SD", 5944 argLen: 1, 5945 asm: x86.ACVTSL2SD, 5946 reg: regInfo{ 5947 inputs: []inputInfo{ 5948 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5949 }, 5950 outputs: []outputInfo{ 5951 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5952 }, 5953 }, 5954 }, 5955 { 5956 name: "CVTSQ2SS", 5957 argLen: 1, 5958 asm: x86.ACVTSQ2SS, 5959 reg: regInfo{ 5960 inputs: []inputInfo{ 5961 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5962 }, 5963 outputs: []outputInfo{ 5964 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5965 }, 5966 }, 5967 }, 5968 { 5969 name: "CVTSQ2SD", 5970 argLen: 1, 5971 asm: x86.ACVTSQ2SD, 5972 reg: regInfo{ 5973 inputs: []inputInfo{ 5974 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5975 }, 5976 outputs: []outputInfo{ 5977 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5978 }, 5979 }, 5980 }, 5981 { 5982 name: "CVTSD2SS", 5983 argLen: 1, 5984 asm: x86.ACVTSD2SS, 5985 reg: regInfo{ 5986 inputs: []inputInfo{ 5987 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5988 }, 5989 outputs: []outputInfo{ 5990 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5991 }, 5992 }, 5993 }, 5994 { 5995 name: "CVTSS2SD", 5996 argLen: 1, 5997 asm: x86.ACVTSS2SD, 5998 reg: regInfo{ 5999 inputs: []inputInfo{ 6000 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6001 }, 6002 outputs: []outputInfo{ 6003 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6004 }, 6005 }, 6006 }, 6007 { 6008 name: "PXOR", 6009 argLen: 2, 6010 commutative: true, 6011 resultInArg0: true, 6012 asm: x86.APXOR, 6013 reg: regInfo{ 6014 inputs: []inputInfo{ 6015 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6016 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6017 }, 6018 outputs: []outputInfo{ 6019 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6020 }, 6021 }, 6022 }, 6023 { 6024 name: "LEAQ", 6025 auxType: auxSymOff, 6026 argLen: 1, 6027 rematerializeable: true, 6028 asm: x86.ALEAQ, 6029 reg: regInfo{ 6030 inputs: []inputInfo{ 6031 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6032 }, 6033 outputs: []outputInfo{ 6034 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6035 }, 6036 }, 6037 }, 6038 { 6039 name: "LEAQ1", 6040 auxType: auxSymOff, 6041 argLen: 2, 6042 reg: regInfo{ 6043 inputs: []inputInfo{ 6044 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6045 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6046 }, 6047 outputs: []outputInfo{ 6048 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6049 }, 6050 }, 6051 }, 6052 { 6053 name: "LEAQ2", 6054 auxType: auxSymOff, 6055 argLen: 2, 6056 reg: regInfo{ 6057 inputs: []inputInfo{ 6058 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6059 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6060 }, 6061 outputs: []outputInfo{ 6062 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6063 }, 6064 }, 6065 }, 6066 { 6067 name: "LEAQ4", 6068 auxType: auxSymOff, 6069 argLen: 2, 6070 reg: regInfo{ 6071 inputs: []inputInfo{ 6072 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6073 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6074 }, 6075 outputs: []outputInfo{ 6076 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6077 }, 6078 }, 6079 }, 6080 { 6081 name: "LEAQ8", 6082 auxType: auxSymOff, 6083 argLen: 2, 6084 reg: regInfo{ 6085 inputs: []inputInfo{ 6086 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6087 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6088 }, 6089 outputs: []outputInfo{ 6090 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6091 }, 6092 }, 6093 }, 6094 { 6095 name: "LEAL", 6096 auxType: auxSymOff, 6097 argLen: 1, 6098 rematerializeable: true, 6099 asm: x86.ALEAL, 6100 reg: regInfo{ 6101 inputs: []inputInfo{ 6102 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6103 }, 6104 outputs: []outputInfo{ 6105 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6106 }, 6107 }, 6108 }, 6109 { 6110 name: "MOVBload", 6111 auxType: auxSymOff, 6112 argLen: 2, 6113 asm: x86.AMOVBLZX, 6114 reg: regInfo{ 6115 inputs: []inputInfo{ 6116 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6117 }, 6118 outputs: []outputInfo{ 6119 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6120 }, 6121 }, 6122 }, 6123 { 6124 name: "MOVBQSXload", 6125 auxType: auxSymOff, 6126 argLen: 2, 6127 asm: x86.AMOVBQSX, 6128 reg: regInfo{ 6129 inputs: []inputInfo{ 6130 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6131 }, 6132 outputs: []outputInfo{ 6133 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6134 }, 6135 }, 6136 }, 6137 { 6138 name: "MOVWload", 6139 auxType: auxSymOff, 6140 argLen: 2, 6141 asm: x86.AMOVWLZX, 6142 reg: regInfo{ 6143 inputs: []inputInfo{ 6144 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6145 }, 6146 outputs: []outputInfo{ 6147 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6148 }, 6149 }, 6150 }, 6151 { 6152 name: "MOVWQSXload", 6153 auxType: auxSymOff, 6154 argLen: 2, 6155 asm: x86.AMOVWQSX, 6156 reg: regInfo{ 6157 inputs: []inputInfo{ 6158 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6159 }, 6160 outputs: []outputInfo{ 6161 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6162 }, 6163 }, 6164 }, 6165 { 6166 name: "MOVLload", 6167 auxType: auxSymOff, 6168 argLen: 2, 6169 asm: x86.AMOVL, 6170 reg: regInfo{ 6171 inputs: []inputInfo{ 6172 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6173 }, 6174 outputs: []outputInfo{ 6175 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6176 }, 6177 }, 6178 }, 6179 { 6180 name: "MOVLQSXload", 6181 auxType: auxSymOff, 6182 argLen: 2, 6183 asm: x86.AMOVLQSX, 6184 reg: regInfo{ 6185 inputs: []inputInfo{ 6186 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6187 }, 6188 outputs: []outputInfo{ 6189 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6190 }, 6191 }, 6192 }, 6193 { 6194 name: "MOVQload", 6195 auxType: auxSymOff, 6196 argLen: 2, 6197 asm: x86.AMOVQ, 6198 reg: regInfo{ 6199 inputs: []inputInfo{ 6200 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6201 }, 6202 outputs: []outputInfo{ 6203 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6204 }, 6205 }, 6206 }, 6207 { 6208 name: "MOVBstore", 6209 auxType: auxSymOff, 6210 argLen: 3, 6211 asm: x86.AMOVB, 6212 reg: regInfo{ 6213 inputs: []inputInfo{ 6214 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6215 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6216 }, 6217 }, 6218 }, 6219 { 6220 name: "MOVWstore", 6221 auxType: auxSymOff, 6222 argLen: 3, 6223 asm: x86.AMOVW, 6224 reg: regInfo{ 6225 inputs: []inputInfo{ 6226 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6227 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6228 }, 6229 }, 6230 }, 6231 { 6232 name: "MOVLstore", 6233 auxType: auxSymOff, 6234 argLen: 3, 6235 asm: x86.AMOVL, 6236 reg: regInfo{ 6237 inputs: []inputInfo{ 6238 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6239 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6240 }, 6241 }, 6242 }, 6243 { 6244 name: "MOVQstore", 6245 auxType: auxSymOff, 6246 argLen: 3, 6247 asm: x86.AMOVQ, 6248 reg: regInfo{ 6249 inputs: []inputInfo{ 6250 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6251 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6252 }, 6253 }, 6254 }, 6255 { 6256 name: "MOVOload", 6257 auxType: auxSymOff, 6258 argLen: 2, 6259 asm: x86.AMOVUPS, 6260 reg: regInfo{ 6261 inputs: []inputInfo{ 6262 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6263 }, 6264 outputs: []outputInfo{ 6265 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6266 }, 6267 }, 6268 }, 6269 { 6270 name: "MOVOstore", 6271 auxType: auxSymOff, 6272 argLen: 3, 6273 asm: x86.AMOVUPS, 6274 reg: regInfo{ 6275 inputs: []inputInfo{ 6276 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6277 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6278 }, 6279 }, 6280 }, 6281 { 6282 name: "MOVBloadidx1", 6283 auxType: auxSymOff, 6284 argLen: 3, 6285 asm: x86.AMOVBLZX, 6286 reg: regInfo{ 6287 inputs: []inputInfo{ 6288 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6289 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6290 }, 6291 outputs: []outputInfo{ 6292 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6293 }, 6294 }, 6295 }, 6296 { 6297 name: "MOVWloadidx1", 6298 auxType: auxSymOff, 6299 argLen: 3, 6300 asm: x86.AMOVWLZX, 6301 reg: regInfo{ 6302 inputs: []inputInfo{ 6303 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6304 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6305 }, 6306 outputs: []outputInfo{ 6307 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6308 }, 6309 }, 6310 }, 6311 { 6312 name: "MOVWloadidx2", 6313 auxType: auxSymOff, 6314 argLen: 3, 6315 asm: x86.AMOVWLZX, 6316 reg: regInfo{ 6317 inputs: []inputInfo{ 6318 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6319 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6320 }, 6321 outputs: []outputInfo{ 6322 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6323 }, 6324 }, 6325 }, 6326 { 6327 name: "MOVLloadidx1", 6328 auxType: auxSymOff, 6329 argLen: 3, 6330 asm: x86.AMOVL, 6331 reg: regInfo{ 6332 inputs: []inputInfo{ 6333 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6334 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6335 }, 6336 outputs: []outputInfo{ 6337 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6338 }, 6339 }, 6340 }, 6341 { 6342 name: "MOVLloadidx4", 6343 auxType: auxSymOff, 6344 argLen: 3, 6345 asm: x86.AMOVL, 6346 reg: regInfo{ 6347 inputs: []inputInfo{ 6348 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6349 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6350 }, 6351 outputs: []outputInfo{ 6352 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6353 }, 6354 }, 6355 }, 6356 { 6357 name: "MOVQloadidx1", 6358 auxType: auxSymOff, 6359 argLen: 3, 6360 asm: x86.AMOVQ, 6361 reg: regInfo{ 6362 inputs: []inputInfo{ 6363 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6364 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6365 }, 6366 outputs: []outputInfo{ 6367 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6368 }, 6369 }, 6370 }, 6371 { 6372 name: "MOVQloadidx8", 6373 auxType: auxSymOff, 6374 argLen: 3, 6375 asm: x86.AMOVQ, 6376 reg: regInfo{ 6377 inputs: []inputInfo{ 6378 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6379 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6380 }, 6381 outputs: []outputInfo{ 6382 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6383 }, 6384 }, 6385 }, 6386 { 6387 name: "MOVBstoreidx1", 6388 auxType: auxSymOff, 6389 argLen: 4, 6390 asm: x86.AMOVB, 6391 reg: regInfo{ 6392 inputs: []inputInfo{ 6393 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6394 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6395 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6396 }, 6397 }, 6398 }, 6399 { 6400 name: "MOVWstoreidx1", 6401 auxType: auxSymOff, 6402 argLen: 4, 6403 asm: x86.AMOVW, 6404 reg: regInfo{ 6405 inputs: []inputInfo{ 6406 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6407 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6408 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6409 }, 6410 }, 6411 }, 6412 { 6413 name: "MOVWstoreidx2", 6414 auxType: auxSymOff, 6415 argLen: 4, 6416 asm: x86.AMOVW, 6417 reg: regInfo{ 6418 inputs: []inputInfo{ 6419 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6420 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6421 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6422 }, 6423 }, 6424 }, 6425 { 6426 name: "MOVLstoreidx1", 6427 auxType: auxSymOff, 6428 argLen: 4, 6429 asm: x86.AMOVL, 6430 reg: regInfo{ 6431 inputs: []inputInfo{ 6432 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6433 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6434 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6435 }, 6436 }, 6437 }, 6438 { 6439 name: "MOVLstoreidx4", 6440 auxType: auxSymOff, 6441 argLen: 4, 6442 asm: x86.AMOVL, 6443 reg: regInfo{ 6444 inputs: []inputInfo{ 6445 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6446 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6447 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6448 }, 6449 }, 6450 }, 6451 { 6452 name: "MOVQstoreidx1", 6453 auxType: auxSymOff, 6454 argLen: 4, 6455 asm: x86.AMOVQ, 6456 reg: regInfo{ 6457 inputs: []inputInfo{ 6458 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6459 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6460 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6461 }, 6462 }, 6463 }, 6464 { 6465 name: "MOVQstoreidx8", 6466 auxType: auxSymOff, 6467 argLen: 4, 6468 asm: x86.AMOVQ, 6469 reg: regInfo{ 6470 inputs: []inputInfo{ 6471 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6472 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6473 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6474 }, 6475 }, 6476 }, 6477 { 6478 name: "MOVBstoreconst", 6479 auxType: auxSymValAndOff, 6480 argLen: 2, 6481 asm: x86.AMOVB, 6482 reg: regInfo{ 6483 inputs: []inputInfo{ 6484 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6485 }, 6486 }, 6487 }, 6488 { 6489 name: "MOVWstoreconst", 6490 auxType: auxSymValAndOff, 6491 argLen: 2, 6492 asm: x86.AMOVW, 6493 reg: regInfo{ 6494 inputs: []inputInfo{ 6495 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6496 }, 6497 }, 6498 }, 6499 { 6500 name: "MOVLstoreconst", 6501 auxType: auxSymValAndOff, 6502 argLen: 2, 6503 asm: x86.AMOVL, 6504 reg: regInfo{ 6505 inputs: []inputInfo{ 6506 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6507 }, 6508 }, 6509 }, 6510 { 6511 name: "MOVQstoreconst", 6512 auxType: auxSymValAndOff, 6513 argLen: 2, 6514 asm: x86.AMOVQ, 6515 reg: regInfo{ 6516 inputs: []inputInfo{ 6517 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6518 }, 6519 }, 6520 }, 6521 { 6522 name: "MOVBstoreconstidx1", 6523 auxType: auxSymValAndOff, 6524 argLen: 3, 6525 asm: x86.AMOVB, 6526 reg: regInfo{ 6527 inputs: []inputInfo{ 6528 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6529 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6530 }, 6531 }, 6532 }, 6533 { 6534 name: "MOVWstoreconstidx1", 6535 auxType: auxSymValAndOff, 6536 argLen: 3, 6537 asm: x86.AMOVW, 6538 reg: regInfo{ 6539 inputs: []inputInfo{ 6540 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6541 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6542 }, 6543 }, 6544 }, 6545 { 6546 name: "MOVWstoreconstidx2", 6547 auxType: auxSymValAndOff, 6548 argLen: 3, 6549 asm: x86.AMOVW, 6550 reg: regInfo{ 6551 inputs: []inputInfo{ 6552 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6553 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6554 }, 6555 }, 6556 }, 6557 { 6558 name: "MOVLstoreconstidx1", 6559 auxType: auxSymValAndOff, 6560 argLen: 3, 6561 asm: x86.AMOVL, 6562 reg: regInfo{ 6563 inputs: []inputInfo{ 6564 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6565 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6566 }, 6567 }, 6568 }, 6569 { 6570 name: "MOVLstoreconstidx4", 6571 auxType: auxSymValAndOff, 6572 argLen: 3, 6573 asm: x86.AMOVL, 6574 reg: regInfo{ 6575 inputs: []inputInfo{ 6576 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6577 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6578 }, 6579 }, 6580 }, 6581 { 6582 name: "MOVQstoreconstidx1", 6583 auxType: auxSymValAndOff, 6584 argLen: 3, 6585 asm: x86.AMOVQ, 6586 reg: regInfo{ 6587 inputs: []inputInfo{ 6588 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6589 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6590 }, 6591 }, 6592 }, 6593 { 6594 name: "MOVQstoreconstidx8", 6595 auxType: auxSymValAndOff, 6596 argLen: 3, 6597 asm: x86.AMOVQ, 6598 reg: regInfo{ 6599 inputs: []inputInfo{ 6600 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6601 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6602 }, 6603 }, 6604 }, 6605 { 6606 name: "DUFFZERO", 6607 auxType: auxInt64, 6608 argLen: 3, 6609 clobberFlags: true, 6610 reg: regInfo{ 6611 inputs: []inputInfo{ 6612 {0, 128}, // DI 6613 {1, 65536}, // X0 6614 }, 6615 clobbers: 128, // DI 6616 }, 6617 }, 6618 { 6619 name: "MOVOconst", 6620 auxType: auxInt128, 6621 argLen: 0, 6622 rematerializeable: true, 6623 reg: regInfo{ 6624 outputs: []outputInfo{ 6625 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6626 }, 6627 }, 6628 }, 6629 { 6630 name: "REPSTOSQ", 6631 argLen: 4, 6632 reg: regInfo{ 6633 inputs: []inputInfo{ 6634 {0, 128}, // DI 6635 {1, 2}, // CX 6636 {2, 1}, // AX 6637 }, 6638 clobbers: 130, // CX DI 6639 }, 6640 }, 6641 { 6642 name: "CALLstatic", 6643 auxType: auxSymOff, 6644 argLen: 1, 6645 clobberFlags: true, 6646 reg: regInfo{ 6647 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6648 }, 6649 }, 6650 { 6651 name: "CALLclosure", 6652 auxType: auxInt64, 6653 argLen: 3, 6654 clobberFlags: true, 6655 reg: regInfo{ 6656 inputs: []inputInfo{ 6657 {1, 4}, // DX 6658 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6659 }, 6660 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6661 }, 6662 }, 6663 { 6664 name: "CALLdefer", 6665 auxType: auxInt64, 6666 argLen: 1, 6667 clobberFlags: true, 6668 reg: regInfo{ 6669 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6670 }, 6671 }, 6672 { 6673 name: "CALLgo", 6674 auxType: auxInt64, 6675 argLen: 1, 6676 clobberFlags: true, 6677 reg: regInfo{ 6678 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6679 }, 6680 }, 6681 { 6682 name: "CALLinter", 6683 auxType: auxInt64, 6684 argLen: 2, 6685 clobberFlags: true, 6686 reg: regInfo{ 6687 inputs: []inputInfo{ 6688 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6689 }, 6690 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6691 }, 6692 }, 6693 { 6694 name: "DUFFCOPY", 6695 auxType: auxInt64, 6696 argLen: 3, 6697 clobberFlags: true, 6698 reg: regInfo{ 6699 inputs: []inputInfo{ 6700 {0, 128}, // DI 6701 {1, 64}, // SI 6702 }, 6703 clobbers: 65728, // SI DI X0 6704 }, 6705 }, 6706 { 6707 name: "REPMOVSQ", 6708 argLen: 4, 6709 reg: regInfo{ 6710 inputs: []inputInfo{ 6711 {0, 128}, // DI 6712 {1, 64}, // SI 6713 {2, 2}, // CX 6714 }, 6715 clobbers: 194, // CX SI DI 6716 }, 6717 }, 6718 { 6719 name: "InvertFlags", 6720 argLen: 1, 6721 reg: regInfo{}, 6722 }, 6723 { 6724 name: "LoweredGetG", 6725 argLen: 1, 6726 reg: regInfo{ 6727 outputs: []outputInfo{ 6728 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6729 }, 6730 }, 6731 }, 6732 { 6733 name: "LoweredGetClosurePtr", 6734 argLen: 0, 6735 reg: regInfo{ 6736 outputs: []outputInfo{ 6737 {0, 4}, // DX 6738 }, 6739 }, 6740 }, 6741 { 6742 name: "LoweredNilCheck", 6743 argLen: 2, 6744 clobberFlags: true, 6745 reg: regInfo{ 6746 inputs: []inputInfo{ 6747 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6748 }, 6749 }, 6750 }, 6751 { 6752 name: "MOVQconvert", 6753 argLen: 2, 6754 asm: x86.AMOVQ, 6755 reg: regInfo{ 6756 inputs: []inputInfo{ 6757 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6758 }, 6759 outputs: []outputInfo{ 6760 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6761 }, 6762 }, 6763 }, 6764 { 6765 name: "MOVLconvert", 6766 argLen: 2, 6767 asm: x86.AMOVL, 6768 reg: regInfo{ 6769 inputs: []inputInfo{ 6770 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6771 }, 6772 outputs: []outputInfo{ 6773 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6774 }, 6775 }, 6776 }, 6777 { 6778 name: "FlagEQ", 6779 argLen: 0, 6780 reg: regInfo{}, 6781 }, 6782 { 6783 name: "FlagLT_ULT", 6784 argLen: 0, 6785 reg: regInfo{}, 6786 }, 6787 { 6788 name: "FlagLT_UGT", 6789 argLen: 0, 6790 reg: regInfo{}, 6791 }, 6792 { 6793 name: "FlagGT_UGT", 6794 argLen: 0, 6795 reg: regInfo{}, 6796 }, 6797 { 6798 name: "FlagGT_ULT", 6799 argLen: 0, 6800 reg: regInfo{}, 6801 }, 6802 { 6803 name: "MOVLatomicload", 6804 auxType: auxSymOff, 6805 argLen: 2, 6806 asm: x86.AMOVL, 6807 reg: regInfo{ 6808 inputs: []inputInfo{ 6809 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6810 }, 6811 outputs: []outputInfo{ 6812 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6813 }, 6814 }, 6815 }, 6816 { 6817 name: "MOVQatomicload", 6818 auxType: auxSymOff, 6819 argLen: 2, 6820 asm: x86.AMOVQ, 6821 reg: regInfo{ 6822 inputs: []inputInfo{ 6823 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6824 }, 6825 outputs: []outputInfo{ 6826 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6827 }, 6828 }, 6829 }, 6830 { 6831 name: "XCHGL", 6832 auxType: auxSymOff, 6833 argLen: 3, 6834 resultInArg0: true, 6835 asm: x86.AXCHGL, 6836 reg: regInfo{ 6837 inputs: []inputInfo{ 6838 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6839 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6840 }, 6841 outputs: []outputInfo{ 6842 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6843 }, 6844 }, 6845 }, 6846 { 6847 name: "XCHGQ", 6848 auxType: auxSymOff, 6849 argLen: 3, 6850 resultInArg0: true, 6851 asm: x86.AXCHGQ, 6852 reg: regInfo{ 6853 inputs: []inputInfo{ 6854 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6855 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6856 }, 6857 outputs: []outputInfo{ 6858 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6859 }, 6860 }, 6861 }, 6862 6863 { 6864 name: "ADD", 6865 argLen: 2, 6866 commutative: true, 6867 asm: arm.AADD, 6868 reg: regInfo{ 6869 inputs: []inputInfo{ 6870 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 6871 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 6872 }, 6873 outputs: []outputInfo{ 6874 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 6875 }, 6876 }, 6877 }, 6878 { 6879 name: "ADDconst", 6880 auxType: auxInt32, 6881 argLen: 1, 6882 asm: arm.AADD, 6883 reg: regInfo{ 6884 inputs: []inputInfo{ 6885 {0, 14335}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP 6886 }, 6887 outputs: []outputInfo{ 6888 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 6889 }, 6890 }, 6891 }, 6892 { 6893 name: "SUB", 6894 argLen: 2, 6895 asm: arm.ASUB, 6896 reg: regInfo{ 6897 inputs: []inputInfo{ 6898 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 6899 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 6900 }, 6901 outputs: []outputInfo{ 6902 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 6903 }, 6904 }, 6905 }, 6906 { 6907 name: "SUBconst", 6908 auxType: auxInt32, 6909 argLen: 1, 6910 asm: arm.ASUB, 6911 reg: regInfo{ 6912 inputs: []inputInfo{ 6913 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 6914 }, 6915 outputs: []outputInfo{ 6916 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 6917 }, 6918 }, 6919 }, 6920 { 6921 name: "RSB", 6922 argLen: 2, 6923 asm: arm.ARSB, 6924 reg: regInfo{ 6925 inputs: []inputInfo{ 6926 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 6927 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 6928 }, 6929 outputs: []outputInfo{ 6930 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 6931 }, 6932 }, 6933 }, 6934 { 6935 name: "RSBconst", 6936 auxType: auxInt32, 6937 argLen: 1, 6938 asm: arm.ARSB, 6939 reg: regInfo{ 6940 inputs: []inputInfo{ 6941 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 6942 }, 6943 outputs: []outputInfo{ 6944 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 6945 }, 6946 }, 6947 }, 6948 { 6949 name: "MUL", 6950 argLen: 2, 6951 commutative: true, 6952 asm: arm.AMUL, 6953 reg: regInfo{ 6954 inputs: []inputInfo{ 6955 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 6956 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 6957 }, 6958 outputs: []outputInfo{ 6959 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 6960 }, 6961 }, 6962 }, 6963 { 6964 name: "HMUL", 6965 argLen: 2, 6966 commutative: true, 6967 asm: arm.AMULL, 6968 reg: regInfo{ 6969 inputs: []inputInfo{ 6970 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 6971 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 6972 }, 6973 outputs: []outputInfo{ 6974 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 6975 }, 6976 }, 6977 }, 6978 { 6979 name: "HMULU", 6980 argLen: 2, 6981 commutative: true, 6982 asm: arm.AMULLU, 6983 reg: regInfo{ 6984 inputs: []inputInfo{ 6985 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 6986 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 6987 }, 6988 outputs: []outputInfo{ 6989 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 6990 }, 6991 }, 6992 }, 6993 { 6994 name: "DIV", 6995 argLen: 2, 6996 clobberFlags: true, 6997 asm: arm.ADIV, 6998 reg: regInfo{ 6999 inputs: []inputInfo{ 7000 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7001 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7002 }, 7003 outputs: []outputInfo{ 7004 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7005 }, 7006 }, 7007 }, 7008 { 7009 name: "DIVU", 7010 argLen: 2, 7011 clobberFlags: true, 7012 asm: arm.ADIVU, 7013 reg: regInfo{ 7014 inputs: []inputInfo{ 7015 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7016 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7017 }, 7018 outputs: []outputInfo{ 7019 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7020 }, 7021 }, 7022 }, 7023 { 7024 name: "MOD", 7025 argLen: 2, 7026 clobberFlags: true, 7027 asm: arm.AMOD, 7028 reg: regInfo{ 7029 inputs: []inputInfo{ 7030 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7031 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7032 }, 7033 outputs: []outputInfo{ 7034 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7035 }, 7036 }, 7037 }, 7038 { 7039 name: "MODU", 7040 argLen: 2, 7041 clobberFlags: true, 7042 asm: arm.AMODU, 7043 reg: regInfo{ 7044 inputs: []inputInfo{ 7045 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7046 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7047 }, 7048 outputs: []outputInfo{ 7049 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7050 }, 7051 }, 7052 }, 7053 { 7054 name: "ADDS", 7055 argLen: 2, 7056 commutative: true, 7057 asm: arm.AADD, 7058 reg: regInfo{ 7059 inputs: []inputInfo{ 7060 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7061 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7062 }, 7063 outputs: []outputInfo{ 7064 {1, 0}, 7065 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7066 }, 7067 }, 7068 }, 7069 { 7070 name: "ADDSconst", 7071 auxType: auxInt32, 7072 argLen: 1, 7073 asm: arm.AADD, 7074 reg: regInfo{ 7075 inputs: []inputInfo{ 7076 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7077 }, 7078 outputs: []outputInfo{ 7079 {1, 0}, 7080 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7081 }, 7082 }, 7083 }, 7084 { 7085 name: "ADC", 7086 argLen: 3, 7087 commutative: true, 7088 asm: arm.AADC, 7089 reg: regInfo{ 7090 inputs: []inputInfo{ 7091 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7092 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7093 }, 7094 outputs: []outputInfo{ 7095 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7096 }, 7097 }, 7098 }, 7099 { 7100 name: "ADCconst", 7101 auxType: auxInt32, 7102 argLen: 2, 7103 asm: arm.AADC, 7104 reg: regInfo{ 7105 inputs: []inputInfo{ 7106 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7107 }, 7108 outputs: []outputInfo{ 7109 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7110 }, 7111 }, 7112 }, 7113 { 7114 name: "SUBS", 7115 argLen: 2, 7116 asm: arm.ASUB, 7117 reg: regInfo{ 7118 inputs: []inputInfo{ 7119 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7120 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7121 }, 7122 outputs: []outputInfo{ 7123 {1, 0}, 7124 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7125 }, 7126 }, 7127 }, 7128 { 7129 name: "SUBSconst", 7130 auxType: auxInt32, 7131 argLen: 1, 7132 asm: arm.ASUB, 7133 reg: regInfo{ 7134 inputs: []inputInfo{ 7135 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7136 }, 7137 outputs: []outputInfo{ 7138 {1, 0}, 7139 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7140 }, 7141 }, 7142 }, 7143 { 7144 name: "RSBSconst", 7145 auxType: auxInt32, 7146 argLen: 1, 7147 asm: arm.ARSB, 7148 reg: regInfo{ 7149 inputs: []inputInfo{ 7150 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7151 }, 7152 outputs: []outputInfo{ 7153 {1, 0}, 7154 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7155 }, 7156 }, 7157 }, 7158 { 7159 name: "SBC", 7160 argLen: 3, 7161 asm: arm.ASBC, 7162 reg: regInfo{ 7163 inputs: []inputInfo{ 7164 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7165 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7166 }, 7167 outputs: []outputInfo{ 7168 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7169 }, 7170 }, 7171 }, 7172 { 7173 name: "SBCconst", 7174 auxType: auxInt32, 7175 argLen: 2, 7176 asm: arm.ASBC, 7177 reg: regInfo{ 7178 inputs: []inputInfo{ 7179 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7180 }, 7181 outputs: []outputInfo{ 7182 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7183 }, 7184 }, 7185 }, 7186 { 7187 name: "RSCconst", 7188 auxType: auxInt32, 7189 argLen: 2, 7190 asm: arm.ARSC, 7191 reg: regInfo{ 7192 inputs: []inputInfo{ 7193 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7194 }, 7195 outputs: []outputInfo{ 7196 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7197 }, 7198 }, 7199 }, 7200 { 7201 name: "MULLU", 7202 argLen: 2, 7203 commutative: true, 7204 asm: arm.AMULLU, 7205 reg: regInfo{ 7206 inputs: []inputInfo{ 7207 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7208 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7209 }, 7210 outputs: []outputInfo{ 7211 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7212 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7213 }, 7214 }, 7215 }, 7216 { 7217 name: "MULA", 7218 argLen: 3, 7219 asm: arm.AMULA, 7220 reg: regInfo{ 7221 inputs: []inputInfo{ 7222 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7223 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7224 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7225 }, 7226 outputs: []outputInfo{ 7227 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7228 }, 7229 }, 7230 }, 7231 { 7232 name: "ADDF", 7233 argLen: 2, 7234 commutative: true, 7235 asm: arm.AADDF, 7236 reg: regInfo{ 7237 inputs: []inputInfo{ 7238 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7239 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7240 }, 7241 outputs: []outputInfo{ 7242 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7243 }, 7244 }, 7245 }, 7246 { 7247 name: "ADDD", 7248 argLen: 2, 7249 commutative: true, 7250 asm: arm.AADDD, 7251 reg: regInfo{ 7252 inputs: []inputInfo{ 7253 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7254 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7255 }, 7256 outputs: []outputInfo{ 7257 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7258 }, 7259 }, 7260 }, 7261 { 7262 name: "SUBF", 7263 argLen: 2, 7264 asm: arm.ASUBF, 7265 reg: regInfo{ 7266 inputs: []inputInfo{ 7267 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7268 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7269 }, 7270 outputs: []outputInfo{ 7271 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7272 }, 7273 }, 7274 }, 7275 { 7276 name: "SUBD", 7277 argLen: 2, 7278 asm: arm.ASUBD, 7279 reg: regInfo{ 7280 inputs: []inputInfo{ 7281 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7282 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7283 }, 7284 outputs: []outputInfo{ 7285 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7286 }, 7287 }, 7288 }, 7289 { 7290 name: "MULF", 7291 argLen: 2, 7292 commutative: true, 7293 asm: arm.AMULF, 7294 reg: regInfo{ 7295 inputs: []inputInfo{ 7296 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7297 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7298 }, 7299 outputs: []outputInfo{ 7300 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7301 }, 7302 }, 7303 }, 7304 { 7305 name: "MULD", 7306 argLen: 2, 7307 commutative: true, 7308 asm: arm.AMULD, 7309 reg: regInfo{ 7310 inputs: []inputInfo{ 7311 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7312 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7313 }, 7314 outputs: []outputInfo{ 7315 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7316 }, 7317 }, 7318 }, 7319 { 7320 name: "DIVF", 7321 argLen: 2, 7322 asm: arm.ADIVF, 7323 reg: regInfo{ 7324 inputs: []inputInfo{ 7325 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7326 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7327 }, 7328 outputs: []outputInfo{ 7329 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7330 }, 7331 }, 7332 }, 7333 { 7334 name: "DIVD", 7335 argLen: 2, 7336 asm: arm.ADIVD, 7337 reg: regInfo{ 7338 inputs: []inputInfo{ 7339 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7340 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7341 }, 7342 outputs: []outputInfo{ 7343 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7344 }, 7345 }, 7346 }, 7347 { 7348 name: "AND", 7349 argLen: 2, 7350 commutative: true, 7351 asm: arm.AAND, 7352 reg: regInfo{ 7353 inputs: []inputInfo{ 7354 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7355 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7356 }, 7357 outputs: []outputInfo{ 7358 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7359 }, 7360 }, 7361 }, 7362 { 7363 name: "ANDconst", 7364 auxType: auxInt32, 7365 argLen: 1, 7366 asm: arm.AAND, 7367 reg: regInfo{ 7368 inputs: []inputInfo{ 7369 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7370 }, 7371 outputs: []outputInfo{ 7372 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7373 }, 7374 }, 7375 }, 7376 { 7377 name: "OR", 7378 argLen: 2, 7379 commutative: true, 7380 asm: arm.AORR, 7381 reg: regInfo{ 7382 inputs: []inputInfo{ 7383 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7384 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7385 }, 7386 outputs: []outputInfo{ 7387 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7388 }, 7389 }, 7390 }, 7391 { 7392 name: "ORconst", 7393 auxType: auxInt32, 7394 argLen: 1, 7395 asm: arm.AORR, 7396 reg: regInfo{ 7397 inputs: []inputInfo{ 7398 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7399 }, 7400 outputs: []outputInfo{ 7401 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7402 }, 7403 }, 7404 }, 7405 { 7406 name: "XOR", 7407 argLen: 2, 7408 commutative: true, 7409 asm: arm.AEOR, 7410 reg: regInfo{ 7411 inputs: []inputInfo{ 7412 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7413 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7414 }, 7415 outputs: []outputInfo{ 7416 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7417 }, 7418 }, 7419 }, 7420 { 7421 name: "XORconst", 7422 auxType: auxInt32, 7423 argLen: 1, 7424 asm: arm.AEOR, 7425 reg: regInfo{ 7426 inputs: []inputInfo{ 7427 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7428 }, 7429 outputs: []outputInfo{ 7430 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7431 }, 7432 }, 7433 }, 7434 { 7435 name: "BIC", 7436 argLen: 2, 7437 asm: arm.ABIC, 7438 reg: regInfo{ 7439 inputs: []inputInfo{ 7440 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7441 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7442 }, 7443 outputs: []outputInfo{ 7444 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7445 }, 7446 }, 7447 }, 7448 { 7449 name: "BICconst", 7450 auxType: auxInt32, 7451 argLen: 1, 7452 asm: arm.ABIC, 7453 reg: regInfo{ 7454 inputs: []inputInfo{ 7455 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7456 }, 7457 outputs: []outputInfo{ 7458 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7459 }, 7460 }, 7461 }, 7462 { 7463 name: "MVN", 7464 argLen: 1, 7465 asm: arm.AMVN, 7466 reg: regInfo{ 7467 inputs: []inputInfo{ 7468 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7469 }, 7470 outputs: []outputInfo{ 7471 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7472 }, 7473 }, 7474 }, 7475 { 7476 name: "NEGF", 7477 argLen: 1, 7478 asm: arm.ANEGF, 7479 reg: regInfo{ 7480 inputs: []inputInfo{ 7481 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7482 }, 7483 outputs: []outputInfo{ 7484 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7485 }, 7486 }, 7487 }, 7488 { 7489 name: "NEGD", 7490 argLen: 1, 7491 asm: arm.ANEGD, 7492 reg: regInfo{ 7493 inputs: []inputInfo{ 7494 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7495 }, 7496 outputs: []outputInfo{ 7497 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7498 }, 7499 }, 7500 }, 7501 { 7502 name: "SQRTD", 7503 argLen: 1, 7504 asm: arm.ASQRTD, 7505 reg: regInfo{ 7506 inputs: []inputInfo{ 7507 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7508 }, 7509 outputs: []outputInfo{ 7510 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7511 }, 7512 }, 7513 }, 7514 { 7515 name: "SLL", 7516 argLen: 2, 7517 asm: arm.ASLL, 7518 reg: regInfo{ 7519 inputs: []inputInfo{ 7520 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7521 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7522 }, 7523 outputs: []outputInfo{ 7524 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7525 }, 7526 }, 7527 }, 7528 { 7529 name: "SLLconst", 7530 auxType: auxInt32, 7531 argLen: 1, 7532 asm: arm.ASLL, 7533 reg: regInfo{ 7534 inputs: []inputInfo{ 7535 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7536 }, 7537 outputs: []outputInfo{ 7538 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7539 }, 7540 }, 7541 }, 7542 { 7543 name: "SRL", 7544 argLen: 2, 7545 asm: arm.ASRL, 7546 reg: regInfo{ 7547 inputs: []inputInfo{ 7548 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7549 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7550 }, 7551 outputs: []outputInfo{ 7552 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7553 }, 7554 }, 7555 }, 7556 { 7557 name: "SRLconst", 7558 auxType: auxInt32, 7559 argLen: 1, 7560 asm: arm.ASRL, 7561 reg: regInfo{ 7562 inputs: []inputInfo{ 7563 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7564 }, 7565 outputs: []outputInfo{ 7566 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7567 }, 7568 }, 7569 }, 7570 { 7571 name: "SRA", 7572 argLen: 2, 7573 asm: arm.ASRA, 7574 reg: regInfo{ 7575 inputs: []inputInfo{ 7576 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7577 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7578 }, 7579 outputs: []outputInfo{ 7580 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7581 }, 7582 }, 7583 }, 7584 { 7585 name: "SRAconst", 7586 auxType: auxInt32, 7587 argLen: 1, 7588 asm: arm.ASRA, 7589 reg: regInfo{ 7590 inputs: []inputInfo{ 7591 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7592 }, 7593 outputs: []outputInfo{ 7594 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7595 }, 7596 }, 7597 }, 7598 { 7599 name: "SRRconst", 7600 auxType: auxInt32, 7601 argLen: 1, 7602 reg: regInfo{ 7603 inputs: []inputInfo{ 7604 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7605 }, 7606 outputs: []outputInfo{ 7607 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7608 }, 7609 }, 7610 }, 7611 { 7612 name: "ADDshiftLL", 7613 auxType: auxInt32, 7614 argLen: 2, 7615 asm: arm.AADD, 7616 reg: regInfo{ 7617 inputs: []inputInfo{ 7618 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7619 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7620 }, 7621 outputs: []outputInfo{ 7622 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7623 }, 7624 }, 7625 }, 7626 { 7627 name: "ADDshiftRL", 7628 auxType: auxInt32, 7629 argLen: 2, 7630 asm: arm.AADD, 7631 reg: regInfo{ 7632 inputs: []inputInfo{ 7633 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7634 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7635 }, 7636 outputs: []outputInfo{ 7637 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7638 }, 7639 }, 7640 }, 7641 { 7642 name: "ADDshiftRA", 7643 auxType: auxInt32, 7644 argLen: 2, 7645 asm: arm.AADD, 7646 reg: regInfo{ 7647 inputs: []inputInfo{ 7648 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7649 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7650 }, 7651 outputs: []outputInfo{ 7652 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7653 }, 7654 }, 7655 }, 7656 { 7657 name: "SUBshiftLL", 7658 auxType: auxInt32, 7659 argLen: 2, 7660 asm: arm.ASUB, 7661 reg: regInfo{ 7662 inputs: []inputInfo{ 7663 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7664 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7665 }, 7666 outputs: []outputInfo{ 7667 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7668 }, 7669 }, 7670 }, 7671 { 7672 name: "SUBshiftRL", 7673 auxType: auxInt32, 7674 argLen: 2, 7675 asm: arm.ASUB, 7676 reg: regInfo{ 7677 inputs: []inputInfo{ 7678 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7679 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7680 }, 7681 outputs: []outputInfo{ 7682 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7683 }, 7684 }, 7685 }, 7686 { 7687 name: "SUBshiftRA", 7688 auxType: auxInt32, 7689 argLen: 2, 7690 asm: arm.ASUB, 7691 reg: regInfo{ 7692 inputs: []inputInfo{ 7693 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7694 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7695 }, 7696 outputs: []outputInfo{ 7697 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7698 }, 7699 }, 7700 }, 7701 { 7702 name: "RSBshiftLL", 7703 auxType: auxInt32, 7704 argLen: 2, 7705 asm: arm.ARSB, 7706 reg: regInfo{ 7707 inputs: []inputInfo{ 7708 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7709 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7710 }, 7711 outputs: []outputInfo{ 7712 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7713 }, 7714 }, 7715 }, 7716 { 7717 name: "RSBshiftRL", 7718 auxType: auxInt32, 7719 argLen: 2, 7720 asm: arm.ARSB, 7721 reg: regInfo{ 7722 inputs: []inputInfo{ 7723 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7724 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7725 }, 7726 outputs: []outputInfo{ 7727 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7728 }, 7729 }, 7730 }, 7731 { 7732 name: "RSBshiftRA", 7733 auxType: auxInt32, 7734 argLen: 2, 7735 asm: arm.ARSB, 7736 reg: regInfo{ 7737 inputs: []inputInfo{ 7738 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7739 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7740 }, 7741 outputs: []outputInfo{ 7742 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7743 }, 7744 }, 7745 }, 7746 { 7747 name: "ANDshiftLL", 7748 auxType: auxInt32, 7749 argLen: 2, 7750 asm: arm.AAND, 7751 reg: regInfo{ 7752 inputs: []inputInfo{ 7753 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7754 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7755 }, 7756 outputs: []outputInfo{ 7757 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7758 }, 7759 }, 7760 }, 7761 { 7762 name: "ANDshiftRL", 7763 auxType: auxInt32, 7764 argLen: 2, 7765 asm: arm.AAND, 7766 reg: regInfo{ 7767 inputs: []inputInfo{ 7768 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7769 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7770 }, 7771 outputs: []outputInfo{ 7772 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7773 }, 7774 }, 7775 }, 7776 { 7777 name: "ANDshiftRA", 7778 auxType: auxInt32, 7779 argLen: 2, 7780 asm: arm.AAND, 7781 reg: regInfo{ 7782 inputs: []inputInfo{ 7783 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7784 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7785 }, 7786 outputs: []outputInfo{ 7787 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7788 }, 7789 }, 7790 }, 7791 { 7792 name: "ORshiftLL", 7793 auxType: auxInt32, 7794 argLen: 2, 7795 asm: arm.AORR, 7796 reg: regInfo{ 7797 inputs: []inputInfo{ 7798 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7799 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7800 }, 7801 outputs: []outputInfo{ 7802 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7803 }, 7804 }, 7805 }, 7806 { 7807 name: "ORshiftRL", 7808 auxType: auxInt32, 7809 argLen: 2, 7810 asm: arm.AORR, 7811 reg: regInfo{ 7812 inputs: []inputInfo{ 7813 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7814 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7815 }, 7816 outputs: []outputInfo{ 7817 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7818 }, 7819 }, 7820 }, 7821 { 7822 name: "ORshiftRA", 7823 auxType: auxInt32, 7824 argLen: 2, 7825 asm: arm.AORR, 7826 reg: regInfo{ 7827 inputs: []inputInfo{ 7828 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7829 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7830 }, 7831 outputs: []outputInfo{ 7832 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7833 }, 7834 }, 7835 }, 7836 { 7837 name: "XORshiftLL", 7838 auxType: auxInt32, 7839 argLen: 2, 7840 asm: arm.AEOR, 7841 reg: regInfo{ 7842 inputs: []inputInfo{ 7843 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7844 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7845 }, 7846 outputs: []outputInfo{ 7847 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7848 }, 7849 }, 7850 }, 7851 { 7852 name: "XORshiftRL", 7853 auxType: auxInt32, 7854 argLen: 2, 7855 asm: arm.AEOR, 7856 reg: regInfo{ 7857 inputs: []inputInfo{ 7858 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7859 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7860 }, 7861 outputs: []outputInfo{ 7862 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7863 }, 7864 }, 7865 }, 7866 { 7867 name: "XORshiftRA", 7868 auxType: auxInt32, 7869 argLen: 2, 7870 asm: arm.AEOR, 7871 reg: regInfo{ 7872 inputs: []inputInfo{ 7873 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7874 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7875 }, 7876 outputs: []outputInfo{ 7877 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7878 }, 7879 }, 7880 }, 7881 { 7882 name: "BICshiftLL", 7883 auxType: auxInt32, 7884 argLen: 2, 7885 asm: arm.ABIC, 7886 reg: regInfo{ 7887 inputs: []inputInfo{ 7888 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7889 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7890 }, 7891 outputs: []outputInfo{ 7892 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7893 }, 7894 }, 7895 }, 7896 { 7897 name: "BICshiftRL", 7898 auxType: auxInt32, 7899 argLen: 2, 7900 asm: arm.ABIC, 7901 reg: regInfo{ 7902 inputs: []inputInfo{ 7903 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7904 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7905 }, 7906 outputs: []outputInfo{ 7907 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7908 }, 7909 }, 7910 }, 7911 { 7912 name: "BICshiftRA", 7913 auxType: auxInt32, 7914 argLen: 2, 7915 asm: arm.ABIC, 7916 reg: regInfo{ 7917 inputs: []inputInfo{ 7918 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7919 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7920 }, 7921 outputs: []outputInfo{ 7922 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7923 }, 7924 }, 7925 }, 7926 { 7927 name: "MVNshiftLL", 7928 auxType: auxInt32, 7929 argLen: 1, 7930 asm: arm.AMVN, 7931 reg: regInfo{ 7932 inputs: []inputInfo{ 7933 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7934 }, 7935 outputs: []outputInfo{ 7936 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7937 }, 7938 }, 7939 }, 7940 { 7941 name: "MVNshiftRL", 7942 auxType: auxInt32, 7943 argLen: 1, 7944 asm: arm.AMVN, 7945 reg: regInfo{ 7946 inputs: []inputInfo{ 7947 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7948 }, 7949 outputs: []outputInfo{ 7950 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7951 }, 7952 }, 7953 }, 7954 { 7955 name: "MVNshiftRA", 7956 auxType: auxInt32, 7957 argLen: 1, 7958 asm: arm.AMVN, 7959 reg: regInfo{ 7960 inputs: []inputInfo{ 7961 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7962 }, 7963 outputs: []outputInfo{ 7964 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7965 }, 7966 }, 7967 }, 7968 { 7969 name: "ADCshiftLL", 7970 auxType: auxInt32, 7971 argLen: 3, 7972 asm: arm.AADC, 7973 reg: regInfo{ 7974 inputs: []inputInfo{ 7975 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7976 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7977 }, 7978 outputs: []outputInfo{ 7979 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7980 }, 7981 }, 7982 }, 7983 { 7984 name: "ADCshiftRL", 7985 auxType: auxInt32, 7986 argLen: 3, 7987 asm: arm.AADC, 7988 reg: regInfo{ 7989 inputs: []inputInfo{ 7990 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7991 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7992 }, 7993 outputs: []outputInfo{ 7994 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7995 }, 7996 }, 7997 }, 7998 { 7999 name: "ADCshiftRA", 8000 auxType: auxInt32, 8001 argLen: 3, 8002 asm: arm.AADC, 8003 reg: regInfo{ 8004 inputs: []inputInfo{ 8005 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8006 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8007 }, 8008 outputs: []outputInfo{ 8009 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8010 }, 8011 }, 8012 }, 8013 { 8014 name: "SBCshiftLL", 8015 auxType: auxInt32, 8016 argLen: 3, 8017 asm: arm.ASBC, 8018 reg: regInfo{ 8019 inputs: []inputInfo{ 8020 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8021 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8022 }, 8023 outputs: []outputInfo{ 8024 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8025 }, 8026 }, 8027 }, 8028 { 8029 name: "SBCshiftRL", 8030 auxType: auxInt32, 8031 argLen: 3, 8032 asm: arm.ASBC, 8033 reg: regInfo{ 8034 inputs: []inputInfo{ 8035 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8036 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8037 }, 8038 outputs: []outputInfo{ 8039 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8040 }, 8041 }, 8042 }, 8043 { 8044 name: "SBCshiftRA", 8045 auxType: auxInt32, 8046 argLen: 3, 8047 asm: arm.ASBC, 8048 reg: regInfo{ 8049 inputs: []inputInfo{ 8050 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8051 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8052 }, 8053 outputs: []outputInfo{ 8054 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8055 }, 8056 }, 8057 }, 8058 { 8059 name: "RSCshiftLL", 8060 auxType: auxInt32, 8061 argLen: 3, 8062 asm: arm.ARSC, 8063 reg: regInfo{ 8064 inputs: []inputInfo{ 8065 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8066 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8067 }, 8068 outputs: []outputInfo{ 8069 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8070 }, 8071 }, 8072 }, 8073 { 8074 name: "RSCshiftRL", 8075 auxType: auxInt32, 8076 argLen: 3, 8077 asm: arm.ARSC, 8078 reg: regInfo{ 8079 inputs: []inputInfo{ 8080 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8081 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8082 }, 8083 outputs: []outputInfo{ 8084 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8085 }, 8086 }, 8087 }, 8088 { 8089 name: "RSCshiftRA", 8090 auxType: auxInt32, 8091 argLen: 3, 8092 asm: arm.ARSC, 8093 reg: regInfo{ 8094 inputs: []inputInfo{ 8095 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8096 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8097 }, 8098 outputs: []outputInfo{ 8099 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8100 }, 8101 }, 8102 }, 8103 { 8104 name: "ADDSshiftLL", 8105 auxType: auxInt32, 8106 argLen: 2, 8107 asm: arm.AADD, 8108 reg: regInfo{ 8109 inputs: []inputInfo{ 8110 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8111 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8112 }, 8113 outputs: []outputInfo{ 8114 {1, 0}, 8115 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8116 }, 8117 }, 8118 }, 8119 { 8120 name: "ADDSshiftRL", 8121 auxType: auxInt32, 8122 argLen: 2, 8123 asm: arm.AADD, 8124 reg: regInfo{ 8125 inputs: []inputInfo{ 8126 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8127 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8128 }, 8129 outputs: []outputInfo{ 8130 {1, 0}, 8131 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8132 }, 8133 }, 8134 }, 8135 { 8136 name: "ADDSshiftRA", 8137 auxType: auxInt32, 8138 argLen: 2, 8139 asm: arm.AADD, 8140 reg: regInfo{ 8141 inputs: []inputInfo{ 8142 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8143 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8144 }, 8145 outputs: []outputInfo{ 8146 {1, 0}, 8147 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8148 }, 8149 }, 8150 }, 8151 { 8152 name: "SUBSshiftLL", 8153 auxType: auxInt32, 8154 argLen: 2, 8155 asm: arm.ASUB, 8156 reg: regInfo{ 8157 inputs: []inputInfo{ 8158 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8159 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8160 }, 8161 outputs: []outputInfo{ 8162 {1, 0}, 8163 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8164 }, 8165 }, 8166 }, 8167 { 8168 name: "SUBSshiftRL", 8169 auxType: auxInt32, 8170 argLen: 2, 8171 asm: arm.ASUB, 8172 reg: regInfo{ 8173 inputs: []inputInfo{ 8174 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8175 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8176 }, 8177 outputs: []outputInfo{ 8178 {1, 0}, 8179 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8180 }, 8181 }, 8182 }, 8183 { 8184 name: "SUBSshiftRA", 8185 auxType: auxInt32, 8186 argLen: 2, 8187 asm: arm.ASUB, 8188 reg: regInfo{ 8189 inputs: []inputInfo{ 8190 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8191 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8192 }, 8193 outputs: []outputInfo{ 8194 {1, 0}, 8195 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8196 }, 8197 }, 8198 }, 8199 { 8200 name: "RSBSshiftLL", 8201 auxType: auxInt32, 8202 argLen: 2, 8203 asm: arm.ARSB, 8204 reg: regInfo{ 8205 inputs: []inputInfo{ 8206 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8207 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8208 }, 8209 outputs: []outputInfo{ 8210 {1, 0}, 8211 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8212 }, 8213 }, 8214 }, 8215 { 8216 name: "RSBSshiftRL", 8217 auxType: auxInt32, 8218 argLen: 2, 8219 asm: arm.ARSB, 8220 reg: regInfo{ 8221 inputs: []inputInfo{ 8222 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8223 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8224 }, 8225 outputs: []outputInfo{ 8226 {1, 0}, 8227 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8228 }, 8229 }, 8230 }, 8231 { 8232 name: "RSBSshiftRA", 8233 auxType: auxInt32, 8234 argLen: 2, 8235 asm: arm.ARSB, 8236 reg: regInfo{ 8237 inputs: []inputInfo{ 8238 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8239 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8240 }, 8241 outputs: []outputInfo{ 8242 {1, 0}, 8243 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8244 }, 8245 }, 8246 }, 8247 { 8248 name: "ADDshiftLLreg", 8249 argLen: 3, 8250 asm: arm.AADD, 8251 reg: regInfo{ 8252 inputs: []inputInfo{ 8253 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8254 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8255 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8256 }, 8257 outputs: []outputInfo{ 8258 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8259 }, 8260 }, 8261 }, 8262 { 8263 name: "ADDshiftRLreg", 8264 argLen: 3, 8265 asm: arm.AADD, 8266 reg: regInfo{ 8267 inputs: []inputInfo{ 8268 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8269 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8270 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8271 }, 8272 outputs: []outputInfo{ 8273 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8274 }, 8275 }, 8276 }, 8277 { 8278 name: "ADDshiftRAreg", 8279 argLen: 3, 8280 asm: arm.AADD, 8281 reg: regInfo{ 8282 inputs: []inputInfo{ 8283 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8284 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8285 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8286 }, 8287 outputs: []outputInfo{ 8288 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8289 }, 8290 }, 8291 }, 8292 { 8293 name: "SUBshiftLLreg", 8294 argLen: 3, 8295 asm: arm.ASUB, 8296 reg: regInfo{ 8297 inputs: []inputInfo{ 8298 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8299 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8300 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8301 }, 8302 outputs: []outputInfo{ 8303 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8304 }, 8305 }, 8306 }, 8307 { 8308 name: "SUBshiftRLreg", 8309 argLen: 3, 8310 asm: arm.ASUB, 8311 reg: regInfo{ 8312 inputs: []inputInfo{ 8313 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8314 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8315 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8316 }, 8317 outputs: []outputInfo{ 8318 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8319 }, 8320 }, 8321 }, 8322 { 8323 name: "SUBshiftRAreg", 8324 argLen: 3, 8325 asm: arm.ASUB, 8326 reg: regInfo{ 8327 inputs: []inputInfo{ 8328 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8329 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8330 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8331 }, 8332 outputs: []outputInfo{ 8333 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8334 }, 8335 }, 8336 }, 8337 { 8338 name: "RSBshiftLLreg", 8339 argLen: 3, 8340 asm: arm.ARSB, 8341 reg: regInfo{ 8342 inputs: []inputInfo{ 8343 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8344 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8345 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8346 }, 8347 outputs: []outputInfo{ 8348 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8349 }, 8350 }, 8351 }, 8352 { 8353 name: "RSBshiftRLreg", 8354 argLen: 3, 8355 asm: arm.ARSB, 8356 reg: regInfo{ 8357 inputs: []inputInfo{ 8358 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8359 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8360 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8361 }, 8362 outputs: []outputInfo{ 8363 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8364 }, 8365 }, 8366 }, 8367 { 8368 name: "RSBshiftRAreg", 8369 argLen: 3, 8370 asm: arm.ARSB, 8371 reg: regInfo{ 8372 inputs: []inputInfo{ 8373 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8374 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8375 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8376 }, 8377 outputs: []outputInfo{ 8378 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8379 }, 8380 }, 8381 }, 8382 { 8383 name: "ANDshiftLLreg", 8384 argLen: 3, 8385 asm: arm.AAND, 8386 reg: regInfo{ 8387 inputs: []inputInfo{ 8388 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8389 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8390 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8391 }, 8392 outputs: []outputInfo{ 8393 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8394 }, 8395 }, 8396 }, 8397 { 8398 name: "ANDshiftRLreg", 8399 argLen: 3, 8400 asm: arm.AAND, 8401 reg: regInfo{ 8402 inputs: []inputInfo{ 8403 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8404 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8405 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8406 }, 8407 outputs: []outputInfo{ 8408 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8409 }, 8410 }, 8411 }, 8412 { 8413 name: "ANDshiftRAreg", 8414 argLen: 3, 8415 asm: arm.AAND, 8416 reg: regInfo{ 8417 inputs: []inputInfo{ 8418 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8419 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8420 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8421 }, 8422 outputs: []outputInfo{ 8423 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8424 }, 8425 }, 8426 }, 8427 { 8428 name: "ORshiftLLreg", 8429 argLen: 3, 8430 asm: arm.AORR, 8431 reg: regInfo{ 8432 inputs: []inputInfo{ 8433 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8434 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8435 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8436 }, 8437 outputs: []outputInfo{ 8438 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8439 }, 8440 }, 8441 }, 8442 { 8443 name: "ORshiftRLreg", 8444 argLen: 3, 8445 asm: arm.AORR, 8446 reg: regInfo{ 8447 inputs: []inputInfo{ 8448 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8449 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8450 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8451 }, 8452 outputs: []outputInfo{ 8453 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8454 }, 8455 }, 8456 }, 8457 { 8458 name: "ORshiftRAreg", 8459 argLen: 3, 8460 asm: arm.AORR, 8461 reg: regInfo{ 8462 inputs: []inputInfo{ 8463 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8464 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8465 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8466 }, 8467 outputs: []outputInfo{ 8468 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8469 }, 8470 }, 8471 }, 8472 { 8473 name: "XORshiftLLreg", 8474 argLen: 3, 8475 asm: arm.AEOR, 8476 reg: regInfo{ 8477 inputs: []inputInfo{ 8478 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8479 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8480 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8481 }, 8482 outputs: []outputInfo{ 8483 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8484 }, 8485 }, 8486 }, 8487 { 8488 name: "XORshiftRLreg", 8489 argLen: 3, 8490 asm: arm.AEOR, 8491 reg: regInfo{ 8492 inputs: []inputInfo{ 8493 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8494 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8495 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8496 }, 8497 outputs: []outputInfo{ 8498 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8499 }, 8500 }, 8501 }, 8502 { 8503 name: "XORshiftRAreg", 8504 argLen: 3, 8505 asm: arm.AEOR, 8506 reg: regInfo{ 8507 inputs: []inputInfo{ 8508 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8509 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8510 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8511 }, 8512 outputs: []outputInfo{ 8513 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8514 }, 8515 }, 8516 }, 8517 { 8518 name: "BICshiftLLreg", 8519 argLen: 3, 8520 asm: arm.ABIC, 8521 reg: regInfo{ 8522 inputs: []inputInfo{ 8523 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8524 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8525 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8526 }, 8527 outputs: []outputInfo{ 8528 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8529 }, 8530 }, 8531 }, 8532 { 8533 name: "BICshiftRLreg", 8534 argLen: 3, 8535 asm: arm.ABIC, 8536 reg: regInfo{ 8537 inputs: []inputInfo{ 8538 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8539 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8540 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8541 }, 8542 outputs: []outputInfo{ 8543 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8544 }, 8545 }, 8546 }, 8547 { 8548 name: "BICshiftRAreg", 8549 argLen: 3, 8550 asm: arm.ABIC, 8551 reg: regInfo{ 8552 inputs: []inputInfo{ 8553 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8554 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8555 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8556 }, 8557 outputs: []outputInfo{ 8558 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8559 }, 8560 }, 8561 }, 8562 { 8563 name: "MVNshiftLLreg", 8564 argLen: 2, 8565 asm: arm.AMVN, 8566 reg: regInfo{ 8567 inputs: []inputInfo{ 8568 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8569 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8570 }, 8571 outputs: []outputInfo{ 8572 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8573 }, 8574 }, 8575 }, 8576 { 8577 name: "MVNshiftRLreg", 8578 argLen: 2, 8579 asm: arm.AMVN, 8580 reg: regInfo{ 8581 inputs: []inputInfo{ 8582 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8583 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8584 }, 8585 outputs: []outputInfo{ 8586 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8587 }, 8588 }, 8589 }, 8590 { 8591 name: "MVNshiftRAreg", 8592 argLen: 2, 8593 asm: arm.AMVN, 8594 reg: regInfo{ 8595 inputs: []inputInfo{ 8596 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8597 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8598 }, 8599 outputs: []outputInfo{ 8600 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8601 }, 8602 }, 8603 }, 8604 { 8605 name: "ADCshiftLLreg", 8606 argLen: 4, 8607 asm: arm.AADC, 8608 reg: regInfo{ 8609 inputs: []inputInfo{ 8610 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8611 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8612 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8613 }, 8614 outputs: []outputInfo{ 8615 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8616 }, 8617 }, 8618 }, 8619 { 8620 name: "ADCshiftRLreg", 8621 argLen: 4, 8622 asm: arm.AADC, 8623 reg: regInfo{ 8624 inputs: []inputInfo{ 8625 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8626 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8627 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8628 }, 8629 outputs: []outputInfo{ 8630 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8631 }, 8632 }, 8633 }, 8634 { 8635 name: "ADCshiftRAreg", 8636 argLen: 4, 8637 asm: arm.AADC, 8638 reg: regInfo{ 8639 inputs: []inputInfo{ 8640 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8641 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8642 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8643 }, 8644 outputs: []outputInfo{ 8645 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8646 }, 8647 }, 8648 }, 8649 { 8650 name: "SBCshiftLLreg", 8651 argLen: 4, 8652 asm: arm.ASBC, 8653 reg: regInfo{ 8654 inputs: []inputInfo{ 8655 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8656 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8657 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8658 }, 8659 outputs: []outputInfo{ 8660 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8661 }, 8662 }, 8663 }, 8664 { 8665 name: "SBCshiftRLreg", 8666 argLen: 4, 8667 asm: arm.ASBC, 8668 reg: regInfo{ 8669 inputs: []inputInfo{ 8670 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8671 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8672 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8673 }, 8674 outputs: []outputInfo{ 8675 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8676 }, 8677 }, 8678 }, 8679 { 8680 name: "SBCshiftRAreg", 8681 argLen: 4, 8682 asm: arm.ASBC, 8683 reg: regInfo{ 8684 inputs: []inputInfo{ 8685 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8686 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8687 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8688 }, 8689 outputs: []outputInfo{ 8690 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8691 }, 8692 }, 8693 }, 8694 { 8695 name: "RSCshiftLLreg", 8696 argLen: 4, 8697 asm: arm.ARSC, 8698 reg: regInfo{ 8699 inputs: []inputInfo{ 8700 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8701 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8702 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8703 }, 8704 outputs: []outputInfo{ 8705 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8706 }, 8707 }, 8708 }, 8709 { 8710 name: "RSCshiftRLreg", 8711 argLen: 4, 8712 asm: arm.ARSC, 8713 reg: regInfo{ 8714 inputs: []inputInfo{ 8715 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8716 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8717 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8718 }, 8719 outputs: []outputInfo{ 8720 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8721 }, 8722 }, 8723 }, 8724 { 8725 name: "RSCshiftRAreg", 8726 argLen: 4, 8727 asm: arm.ARSC, 8728 reg: regInfo{ 8729 inputs: []inputInfo{ 8730 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8731 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8732 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8733 }, 8734 outputs: []outputInfo{ 8735 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8736 }, 8737 }, 8738 }, 8739 { 8740 name: "ADDSshiftLLreg", 8741 argLen: 3, 8742 asm: arm.AADD, 8743 reg: regInfo{ 8744 inputs: []inputInfo{ 8745 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8746 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8747 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8748 }, 8749 outputs: []outputInfo{ 8750 {1, 0}, 8751 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8752 }, 8753 }, 8754 }, 8755 { 8756 name: "ADDSshiftRLreg", 8757 argLen: 3, 8758 asm: arm.AADD, 8759 reg: regInfo{ 8760 inputs: []inputInfo{ 8761 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8762 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8763 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8764 }, 8765 outputs: []outputInfo{ 8766 {1, 0}, 8767 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8768 }, 8769 }, 8770 }, 8771 { 8772 name: "ADDSshiftRAreg", 8773 argLen: 3, 8774 asm: arm.AADD, 8775 reg: regInfo{ 8776 inputs: []inputInfo{ 8777 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8778 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8779 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8780 }, 8781 outputs: []outputInfo{ 8782 {1, 0}, 8783 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8784 }, 8785 }, 8786 }, 8787 { 8788 name: "SUBSshiftLLreg", 8789 argLen: 3, 8790 asm: arm.ASUB, 8791 reg: regInfo{ 8792 inputs: []inputInfo{ 8793 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8794 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8795 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8796 }, 8797 outputs: []outputInfo{ 8798 {1, 0}, 8799 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8800 }, 8801 }, 8802 }, 8803 { 8804 name: "SUBSshiftRLreg", 8805 argLen: 3, 8806 asm: arm.ASUB, 8807 reg: regInfo{ 8808 inputs: []inputInfo{ 8809 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8810 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8811 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8812 }, 8813 outputs: []outputInfo{ 8814 {1, 0}, 8815 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8816 }, 8817 }, 8818 }, 8819 { 8820 name: "SUBSshiftRAreg", 8821 argLen: 3, 8822 asm: arm.ASUB, 8823 reg: regInfo{ 8824 inputs: []inputInfo{ 8825 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8826 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8827 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8828 }, 8829 outputs: []outputInfo{ 8830 {1, 0}, 8831 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8832 }, 8833 }, 8834 }, 8835 { 8836 name: "RSBSshiftLLreg", 8837 argLen: 3, 8838 asm: arm.ARSB, 8839 reg: regInfo{ 8840 inputs: []inputInfo{ 8841 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8842 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8843 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8844 }, 8845 outputs: []outputInfo{ 8846 {1, 0}, 8847 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8848 }, 8849 }, 8850 }, 8851 { 8852 name: "RSBSshiftRLreg", 8853 argLen: 3, 8854 asm: arm.ARSB, 8855 reg: regInfo{ 8856 inputs: []inputInfo{ 8857 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8858 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8859 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8860 }, 8861 outputs: []outputInfo{ 8862 {1, 0}, 8863 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8864 }, 8865 }, 8866 }, 8867 { 8868 name: "RSBSshiftRAreg", 8869 argLen: 3, 8870 asm: arm.ARSB, 8871 reg: regInfo{ 8872 inputs: []inputInfo{ 8873 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8874 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8875 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8876 }, 8877 outputs: []outputInfo{ 8878 {1, 0}, 8879 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8880 }, 8881 }, 8882 }, 8883 { 8884 name: "CMP", 8885 argLen: 2, 8886 asm: arm.ACMP, 8887 reg: regInfo{ 8888 inputs: []inputInfo{ 8889 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8890 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8891 }, 8892 }, 8893 }, 8894 { 8895 name: "CMPconst", 8896 auxType: auxInt32, 8897 argLen: 1, 8898 asm: arm.ACMP, 8899 reg: regInfo{ 8900 inputs: []inputInfo{ 8901 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8902 }, 8903 }, 8904 }, 8905 { 8906 name: "CMN", 8907 argLen: 2, 8908 asm: arm.ACMN, 8909 reg: regInfo{ 8910 inputs: []inputInfo{ 8911 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8912 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8913 }, 8914 }, 8915 }, 8916 { 8917 name: "CMNconst", 8918 auxType: auxInt32, 8919 argLen: 1, 8920 asm: arm.ACMN, 8921 reg: regInfo{ 8922 inputs: []inputInfo{ 8923 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8924 }, 8925 }, 8926 }, 8927 { 8928 name: "TST", 8929 argLen: 2, 8930 commutative: true, 8931 asm: arm.ATST, 8932 reg: regInfo{ 8933 inputs: []inputInfo{ 8934 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8935 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8936 }, 8937 }, 8938 }, 8939 { 8940 name: "TSTconst", 8941 auxType: auxInt32, 8942 argLen: 1, 8943 asm: arm.ATST, 8944 reg: regInfo{ 8945 inputs: []inputInfo{ 8946 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8947 }, 8948 }, 8949 }, 8950 { 8951 name: "TEQ", 8952 argLen: 2, 8953 commutative: true, 8954 asm: arm.ATEQ, 8955 reg: regInfo{ 8956 inputs: []inputInfo{ 8957 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8958 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8959 }, 8960 }, 8961 }, 8962 { 8963 name: "TEQconst", 8964 auxType: auxInt32, 8965 argLen: 1, 8966 asm: arm.ATEQ, 8967 reg: regInfo{ 8968 inputs: []inputInfo{ 8969 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8970 }, 8971 }, 8972 }, 8973 { 8974 name: "CMPF", 8975 argLen: 2, 8976 asm: arm.ACMPF, 8977 reg: regInfo{ 8978 inputs: []inputInfo{ 8979 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8980 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8981 }, 8982 }, 8983 }, 8984 { 8985 name: "CMPD", 8986 argLen: 2, 8987 asm: arm.ACMPD, 8988 reg: regInfo{ 8989 inputs: []inputInfo{ 8990 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8991 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8992 }, 8993 }, 8994 }, 8995 { 8996 name: "CMPshiftLL", 8997 auxType: auxInt32, 8998 argLen: 2, 8999 asm: arm.ACMP, 9000 reg: regInfo{ 9001 inputs: []inputInfo{ 9002 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9003 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9004 }, 9005 }, 9006 }, 9007 { 9008 name: "CMPshiftRL", 9009 auxType: auxInt32, 9010 argLen: 2, 9011 asm: arm.ACMP, 9012 reg: regInfo{ 9013 inputs: []inputInfo{ 9014 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9015 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9016 }, 9017 }, 9018 }, 9019 { 9020 name: "CMPshiftRA", 9021 auxType: auxInt32, 9022 argLen: 2, 9023 asm: arm.ACMP, 9024 reg: regInfo{ 9025 inputs: []inputInfo{ 9026 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9027 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9028 }, 9029 }, 9030 }, 9031 { 9032 name: "CMPshiftLLreg", 9033 argLen: 3, 9034 asm: arm.ACMP, 9035 reg: regInfo{ 9036 inputs: []inputInfo{ 9037 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9038 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9039 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9040 }, 9041 }, 9042 }, 9043 { 9044 name: "CMPshiftRLreg", 9045 argLen: 3, 9046 asm: arm.ACMP, 9047 reg: regInfo{ 9048 inputs: []inputInfo{ 9049 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9050 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9051 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9052 }, 9053 }, 9054 }, 9055 { 9056 name: "CMPshiftRAreg", 9057 argLen: 3, 9058 asm: arm.ACMP, 9059 reg: regInfo{ 9060 inputs: []inputInfo{ 9061 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9062 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9063 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9064 }, 9065 }, 9066 }, 9067 { 9068 name: "CMPF0", 9069 argLen: 1, 9070 asm: arm.ACMPF, 9071 reg: regInfo{ 9072 inputs: []inputInfo{ 9073 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9074 }, 9075 }, 9076 }, 9077 { 9078 name: "CMPD0", 9079 argLen: 1, 9080 asm: arm.ACMPD, 9081 reg: regInfo{ 9082 inputs: []inputInfo{ 9083 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9084 }, 9085 }, 9086 }, 9087 { 9088 name: "MOVWconst", 9089 auxType: auxInt32, 9090 argLen: 0, 9091 rematerializeable: true, 9092 asm: arm.AMOVW, 9093 reg: regInfo{ 9094 outputs: []outputInfo{ 9095 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9096 }, 9097 }, 9098 }, 9099 { 9100 name: "MOVFconst", 9101 auxType: auxFloat64, 9102 argLen: 0, 9103 rematerializeable: true, 9104 asm: arm.AMOVF, 9105 reg: regInfo{ 9106 outputs: []outputInfo{ 9107 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9108 }, 9109 }, 9110 }, 9111 { 9112 name: "MOVDconst", 9113 auxType: auxFloat64, 9114 argLen: 0, 9115 rematerializeable: true, 9116 asm: arm.AMOVD, 9117 reg: regInfo{ 9118 outputs: []outputInfo{ 9119 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9120 }, 9121 }, 9122 }, 9123 { 9124 name: "MOVWaddr", 9125 auxType: auxSymOff, 9126 argLen: 1, 9127 rematerializeable: true, 9128 asm: arm.AMOVW, 9129 reg: regInfo{ 9130 inputs: []inputInfo{ 9131 {0, 4294975488}, // SP SB 9132 }, 9133 outputs: []outputInfo{ 9134 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9135 }, 9136 }, 9137 }, 9138 { 9139 name: "MOVBload", 9140 auxType: auxSymOff, 9141 argLen: 2, 9142 asm: arm.AMOVB, 9143 reg: regInfo{ 9144 inputs: []inputInfo{ 9145 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9146 }, 9147 outputs: []outputInfo{ 9148 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9149 }, 9150 }, 9151 }, 9152 { 9153 name: "MOVBUload", 9154 auxType: auxSymOff, 9155 argLen: 2, 9156 asm: arm.AMOVBU, 9157 reg: regInfo{ 9158 inputs: []inputInfo{ 9159 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9160 }, 9161 outputs: []outputInfo{ 9162 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9163 }, 9164 }, 9165 }, 9166 { 9167 name: "MOVHload", 9168 auxType: auxSymOff, 9169 argLen: 2, 9170 asm: arm.AMOVH, 9171 reg: regInfo{ 9172 inputs: []inputInfo{ 9173 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9174 }, 9175 outputs: []outputInfo{ 9176 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9177 }, 9178 }, 9179 }, 9180 { 9181 name: "MOVHUload", 9182 auxType: auxSymOff, 9183 argLen: 2, 9184 asm: arm.AMOVHU, 9185 reg: regInfo{ 9186 inputs: []inputInfo{ 9187 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9188 }, 9189 outputs: []outputInfo{ 9190 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9191 }, 9192 }, 9193 }, 9194 { 9195 name: "MOVWload", 9196 auxType: auxSymOff, 9197 argLen: 2, 9198 asm: arm.AMOVW, 9199 reg: regInfo{ 9200 inputs: []inputInfo{ 9201 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9202 }, 9203 outputs: []outputInfo{ 9204 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9205 }, 9206 }, 9207 }, 9208 { 9209 name: "MOVFload", 9210 auxType: auxSymOff, 9211 argLen: 2, 9212 asm: arm.AMOVF, 9213 reg: regInfo{ 9214 inputs: []inputInfo{ 9215 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9216 }, 9217 outputs: []outputInfo{ 9218 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9219 }, 9220 }, 9221 }, 9222 { 9223 name: "MOVDload", 9224 auxType: auxSymOff, 9225 argLen: 2, 9226 asm: arm.AMOVD, 9227 reg: regInfo{ 9228 inputs: []inputInfo{ 9229 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9230 }, 9231 outputs: []outputInfo{ 9232 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9233 }, 9234 }, 9235 }, 9236 { 9237 name: "MOVBstore", 9238 auxType: auxSymOff, 9239 argLen: 3, 9240 asm: arm.AMOVB, 9241 reg: regInfo{ 9242 inputs: []inputInfo{ 9243 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9244 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9245 }, 9246 }, 9247 }, 9248 { 9249 name: "MOVHstore", 9250 auxType: auxSymOff, 9251 argLen: 3, 9252 asm: arm.AMOVH, 9253 reg: regInfo{ 9254 inputs: []inputInfo{ 9255 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9256 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9257 }, 9258 }, 9259 }, 9260 { 9261 name: "MOVWstore", 9262 auxType: auxSymOff, 9263 argLen: 3, 9264 asm: arm.AMOVW, 9265 reg: regInfo{ 9266 inputs: []inputInfo{ 9267 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9268 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9269 }, 9270 }, 9271 }, 9272 { 9273 name: "MOVFstore", 9274 auxType: auxSymOff, 9275 argLen: 3, 9276 asm: arm.AMOVF, 9277 reg: regInfo{ 9278 inputs: []inputInfo{ 9279 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9280 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9281 }, 9282 }, 9283 }, 9284 { 9285 name: "MOVDstore", 9286 auxType: auxSymOff, 9287 argLen: 3, 9288 asm: arm.AMOVD, 9289 reg: regInfo{ 9290 inputs: []inputInfo{ 9291 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9292 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9293 }, 9294 }, 9295 }, 9296 { 9297 name: "MOVWloadidx", 9298 argLen: 3, 9299 asm: arm.AMOVW, 9300 reg: regInfo{ 9301 inputs: []inputInfo{ 9302 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9303 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9304 }, 9305 outputs: []outputInfo{ 9306 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9307 }, 9308 }, 9309 }, 9310 { 9311 name: "MOVWloadshiftLL", 9312 auxType: auxInt32, 9313 argLen: 3, 9314 asm: arm.AMOVW, 9315 reg: regInfo{ 9316 inputs: []inputInfo{ 9317 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9318 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9319 }, 9320 outputs: []outputInfo{ 9321 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9322 }, 9323 }, 9324 }, 9325 { 9326 name: "MOVWloadshiftRL", 9327 auxType: auxInt32, 9328 argLen: 3, 9329 asm: arm.AMOVW, 9330 reg: regInfo{ 9331 inputs: []inputInfo{ 9332 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9333 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9334 }, 9335 outputs: []outputInfo{ 9336 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9337 }, 9338 }, 9339 }, 9340 { 9341 name: "MOVWloadshiftRA", 9342 auxType: auxInt32, 9343 argLen: 3, 9344 asm: arm.AMOVW, 9345 reg: regInfo{ 9346 inputs: []inputInfo{ 9347 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9348 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9349 }, 9350 outputs: []outputInfo{ 9351 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9352 }, 9353 }, 9354 }, 9355 { 9356 name: "MOVWstoreidx", 9357 argLen: 4, 9358 asm: arm.AMOVW, 9359 reg: regInfo{ 9360 inputs: []inputInfo{ 9361 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9362 {2, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9363 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9364 }, 9365 }, 9366 }, 9367 { 9368 name: "MOVWstoreshiftLL", 9369 auxType: auxInt32, 9370 argLen: 4, 9371 asm: arm.AMOVW, 9372 reg: regInfo{ 9373 inputs: []inputInfo{ 9374 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9375 {2, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9376 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9377 }, 9378 }, 9379 }, 9380 { 9381 name: "MOVWstoreshiftRL", 9382 auxType: auxInt32, 9383 argLen: 4, 9384 asm: arm.AMOVW, 9385 reg: regInfo{ 9386 inputs: []inputInfo{ 9387 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9388 {2, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9389 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9390 }, 9391 }, 9392 }, 9393 { 9394 name: "MOVWstoreshiftRA", 9395 auxType: auxInt32, 9396 argLen: 4, 9397 asm: arm.AMOVW, 9398 reg: regInfo{ 9399 inputs: []inputInfo{ 9400 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9401 {2, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9402 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9403 }, 9404 }, 9405 }, 9406 { 9407 name: "MOVBreg", 9408 argLen: 1, 9409 asm: arm.AMOVBS, 9410 reg: regInfo{ 9411 inputs: []inputInfo{ 9412 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9413 }, 9414 outputs: []outputInfo{ 9415 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9416 }, 9417 }, 9418 }, 9419 { 9420 name: "MOVBUreg", 9421 argLen: 1, 9422 asm: arm.AMOVBU, 9423 reg: regInfo{ 9424 inputs: []inputInfo{ 9425 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9426 }, 9427 outputs: []outputInfo{ 9428 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9429 }, 9430 }, 9431 }, 9432 { 9433 name: "MOVHreg", 9434 argLen: 1, 9435 asm: arm.AMOVHS, 9436 reg: regInfo{ 9437 inputs: []inputInfo{ 9438 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9439 }, 9440 outputs: []outputInfo{ 9441 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9442 }, 9443 }, 9444 }, 9445 { 9446 name: "MOVHUreg", 9447 argLen: 1, 9448 asm: arm.AMOVHU, 9449 reg: regInfo{ 9450 inputs: []inputInfo{ 9451 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9452 }, 9453 outputs: []outputInfo{ 9454 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9455 }, 9456 }, 9457 }, 9458 { 9459 name: "MOVWreg", 9460 argLen: 1, 9461 asm: arm.AMOVW, 9462 reg: regInfo{ 9463 inputs: []inputInfo{ 9464 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9465 }, 9466 outputs: []outputInfo{ 9467 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9468 }, 9469 }, 9470 }, 9471 { 9472 name: "MOVWnop", 9473 argLen: 1, 9474 resultInArg0: true, 9475 reg: regInfo{ 9476 inputs: []inputInfo{ 9477 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9478 }, 9479 outputs: []outputInfo{ 9480 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9481 }, 9482 }, 9483 }, 9484 { 9485 name: "MOVWF", 9486 argLen: 1, 9487 asm: arm.AMOVWF, 9488 reg: regInfo{ 9489 inputs: []inputInfo{ 9490 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9491 }, 9492 outputs: []outputInfo{ 9493 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9494 }, 9495 }, 9496 }, 9497 { 9498 name: "MOVWD", 9499 argLen: 1, 9500 asm: arm.AMOVWD, 9501 reg: regInfo{ 9502 inputs: []inputInfo{ 9503 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9504 }, 9505 outputs: []outputInfo{ 9506 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9507 }, 9508 }, 9509 }, 9510 { 9511 name: "MOVWUF", 9512 argLen: 1, 9513 asm: arm.AMOVWF, 9514 reg: regInfo{ 9515 inputs: []inputInfo{ 9516 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9517 }, 9518 outputs: []outputInfo{ 9519 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9520 }, 9521 }, 9522 }, 9523 { 9524 name: "MOVWUD", 9525 argLen: 1, 9526 asm: arm.AMOVWD, 9527 reg: regInfo{ 9528 inputs: []inputInfo{ 9529 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9530 }, 9531 outputs: []outputInfo{ 9532 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9533 }, 9534 }, 9535 }, 9536 { 9537 name: "MOVFW", 9538 argLen: 1, 9539 asm: arm.AMOVFW, 9540 reg: regInfo{ 9541 inputs: []inputInfo{ 9542 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9543 }, 9544 outputs: []outputInfo{ 9545 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9546 }, 9547 }, 9548 }, 9549 { 9550 name: "MOVDW", 9551 argLen: 1, 9552 asm: arm.AMOVDW, 9553 reg: regInfo{ 9554 inputs: []inputInfo{ 9555 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9556 }, 9557 outputs: []outputInfo{ 9558 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9559 }, 9560 }, 9561 }, 9562 { 9563 name: "MOVFWU", 9564 argLen: 1, 9565 asm: arm.AMOVFW, 9566 reg: regInfo{ 9567 inputs: []inputInfo{ 9568 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9569 }, 9570 outputs: []outputInfo{ 9571 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9572 }, 9573 }, 9574 }, 9575 { 9576 name: "MOVDWU", 9577 argLen: 1, 9578 asm: arm.AMOVDW, 9579 reg: regInfo{ 9580 inputs: []inputInfo{ 9581 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9582 }, 9583 outputs: []outputInfo{ 9584 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9585 }, 9586 }, 9587 }, 9588 { 9589 name: "MOVFD", 9590 argLen: 1, 9591 asm: arm.AMOVFD, 9592 reg: regInfo{ 9593 inputs: []inputInfo{ 9594 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9595 }, 9596 outputs: []outputInfo{ 9597 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9598 }, 9599 }, 9600 }, 9601 { 9602 name: "MOVDF", 9603 argLen: 1, 9604 asm: arm.AMOVDF, 9605 reg: regInfo{ 9606 inputs: []inputInfo{ 9607 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9608 }, 9609 outputs: []outputInfo{ 9610 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9611 }, 9612 }, 9613 }, 9614 { 9615 name: "CMOVWHSconst", 9616 auxType: auxInt32, 9617 argLen: 2, 9618 resultInArg0: true, 9619 asm: arm.AMOVW, 9620 reg: regInfo{ 9621 inputs: []inputInfo{ 9622 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9623 }, 9624 outputs: []outputInfo{ 9625 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9626 }, 9627 }, 9628 }, 9629 { 9630 name: "CMOVWLSconst", 9631 auxType: auxInt32, 9632 argLen: 2, 9633 resultInArg0: true, 9634 asm: arm.AMOVW, 9635 reg: regInfo{ 9636 inputs: []inputInfo{ 9637 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9638 }, 9639 outputs: []outputInfo{ 9640 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9641 }, 9642 }, 9643 }, 9644 { 9645 name: "SRAcond", 9646 argLen: 3, 9647 asm: arm.ASRA, 9648 reg: regInfo{ 9649 inputs: []inputInfo{ 9650 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9651 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9652 }, 9653 outputs: []outputInfo{ 9654 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9655 }, 9656 }, 9657 }, 9658 { 9659 name: "CALLstatic", 9660 auxType: auxSymOff, 9661 argLen: 1, 9662 clobberFlags: true, 9663 reg: regInfo{ 9664 clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9665 }, 9666 }, 9667 { 9668 name: "CALLclosure", 9669 auxType: auxInt64, 9670 argLen: 3, 9671 clobberFlags: true, 9672 reg: regInfo{ 9673 inputs: []inputInfo{ 9674 {1, 128}, // R7 9675 {0, 13311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP 9676 }, 9677 clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9678 }, 9679 }, 9680 { 9681 name: "CALLdefer", 9682 auxType: auxInt64, 9683 argLen: 1, 9684 clobberFlags: true, 9685 reg: regInfo{ 9686 clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9687 }, 9688 }, 9689 { 9690 name: "CALLgo", 9691 auxType: auxInt64, 9692 argLen: 1, 9693 clobberFlags: true, 9694 reg: regInfo{ 9695 clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9696 }, 9697 }, 9698 { 9699 name: "CALLinter", 9700 auxType: auxInt64, 9701 argLen: 2, 9702 clobberFlags: true, 9703 reg: regInfo{ 9704 inputs: []inputInfo{ 9705 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9706 }, 9707 clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9708 }, 9709 }, 9710 { 9711 name: "LoweredNilCheck", 9712 argLen: 2, 9713 reg: regInfo{ 9714 inputs: []inputInfo{ 9715 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9716 }, 9717 }, 9718 }, 9719 { 9720 name: "Equal", 9721 argLen: 1, 9722 reg: regInfo{ 9723 outputs: []outputInfo{ 9724 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9725 }, 9726 }, 9727 }, 9728 { 9729 name: "NotEqual", 9730 argLen: 1, 9731 reg: regInfo{ 9732 outputs: []outputInfo{ 9733 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9734 }, 9735 }, 9736 }, 9737 { 9738 name: "LessThan", 9739 argLen: 1, 9740 reg: regInfo{ 9741 outputs: []outputInfo{ 9742 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9743 }, 9744 }, 9745 }, 9746 { 9747 name: "LessEqual", 9748 argLen: 1, 9749 reg: regInfo{ 9750 outputs: []outputInfo{ 9751 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9752 }, 9753 }, 9754 }, 9755 { 9756 name: "GreaterThan", 9757 argLen: 1, 9758 reg: regInfo{ 9759 outputs: []outputInfo{ 9760 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9761 }, 9762 }, 9763 }, 9764 { 9765 name: "GreaterEqual", 9766 argLen: 1, 9767 reg: regInfo{ 9768 outputs: []outputInfo{ 9769 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9770 }, 9771 }, 9772 }, 9773 { 9774 name: "LessThanU", 9775 argLen: 1, 9776 reg: regInfo{ 9777 outputs: []outputInfo{ 9778 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9779 }, 9780 }, 9781 }, 9782 { 9783 name: "LessEqualU", 9784 argLen: 1, 9785 reg: regInfo{ 9786 outputs: []outputInfo{ 9787 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9788 }, 9789 }, 9790 }, 9791 { 9792 name: "GreaterThanU", 9793 argLen: 1, 9794 reg: regInfo{ 9795 outputs: []outputInfo{ 9796 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9797 }, 9798 }, 9799 }, 9800 { 9801 name: "GreaterEqualU", 9802 argLen: 1, 9803 reg: regInfo{ 9804 outputs: []outputInfo{ 9805 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9806 }, 9807 }, 9808 }, 9809 { 9810 name: "DUFFZERO", 9811 auxType: auxInt64, 9812 argLen: 3, 9813 reg: regInfo{ 9814 inputs: []inputInfo{ 9815 {0, 2}, // R1 9816 {1, 1}, // R0 9817 }, 9818 clobbers: 2, // R1 9819 }, 9820 }, 9821 { 9822 name: "DUFFCOPY", 9823 auxType: auxInt64, 9824 argLen: 3, 9825 reg: regInfo{ 9826 inputs: []inputInfo{ 9827 {0, 4}, // R2 9828 {1, 2}, // R1 9829 }, 9830 clobbers: 7, // R0 R1 R2 9831 }, 9832 }, 9833 { 9834 name: "LoweredZero", 9835 auxType: auxInt64, 9836 argLen: 4, 9837 clobberFlags: true, 9838 reg: regInfo{ 9839 inputs: []inputInfo{ 9840 {0, 2}, // R1 9841 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9842 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9843 }, 9844 clobbers: 2, // R1 9845 }, 9846 }, 9847 { 9848 name: "LoweredMove", 9849 auxType: auxInt64, 9850 argLen: 4, 9851 clobberFlags: true, 9852 reg: regInfo{ 9853 inputs: []inputInfo{ 9854 {0, 4}, // R2 9855 {1, 2}, // R1 9856 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9857 }, 9858 clobbers: 6, // R1 R2 9859 }, 9860 }, 9861 { 9862 name: "LoweredGetClosurePtr", 9863 argLen: 0, 9864 reg: regInfo{ 9865 outputs: []outputInfo{ 9866 {0, 128}, // R7 9867 }, 9868 }, 9869 }, 9870 { 9871 name: "MOVWconvert", 9872 argLen: 2, 9873 asm: arm.AMOVW, 9874 reg: regInfo{ 9875 inputs: []inputInfo{ 9876 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9877 }, 9878 outputs: []outputInfo{ 9879 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9880 }, 9881 }, 9882 }, 9883 { 9884 name: "FlagEQ", 9885 argLen: 0, 9886 reg: regInfo{}, 9887 }, 9888 { 9889 name: "FlagLT_ULT", 9890 argLen: 0, 9891 reg: regInfo{}, 9892 }, 9893 { 9894 name: "FlagLT_UGT", 9895 argLen: 0, 9896 reg: regInfo{}, 9897 }, 9898 { 9899 name: "FlagGT_UGT", 9900 argLen: 0, 9901 reg: regInfo{}, 9902 }, 9903 { 9904 name: "FlagGT_ULT", 9905 argLen: 0, 9906 reg: regInfo{}, 9907 }, 9908 { 9909 name: "InvertFlags", 9910 argLen: 1, 9911 reg: regInfo{}, 9912 }, 9913 9914 { 9915 name: "ADD", 9916 argLen: 2, 9917 commutative: true, 9918 asm: arm64.AADD, 9919 reg: regInfo{ 9920 inputs: []inputInfo{ 9921 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 9922 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 9923 }, 9924 outputs: []outputInfo{ 9925 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 9926 }, 9927 }, 9928 }, 9929 { 9930 name: "ADDconst", 9931 auxType: auxInt64, 9932 argLen: 1, 9933 asm: arm64.AADD, 9934 reg: regInfo{ 9935 inputs: []inputInfo{ 9936 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP 9937 }, 9938 outputs: []outputInfo{ 9939 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 9940 }, 9941 }, 9942 }, 9943 { 9944 name: "SUB", 9945 argLen: 2, 9946 asm: arm64.ASUB, 9947 reg: regInfo{ 9948 inputs: []inputInfo{ 9949 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 9950 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 9951 }, 9952 outputs: []outputInfo{ 9953 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 9954 }, 9955 }, 9956 }, 9957 { 9958 name: "SUBconst", 9959 auxType: auxInt64, 9960 argLen: 1, 9961 asm: arm64.ASUB, 9962 reg: regInfo{ 9963 inputs: []inputInfo{ 9964 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 9965 }, 9966 outputs: []outputInfo{ 9967 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 9968 }, 9969 }, 9970 }, 9971 { 9972 name: "MUL", 9973 argLen: 2, 9974 commutative: true, 9975 asm: arm64.AMUL, 9976 reg: regInfo{ 9977 inputs: []inputInfo{ 9978 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 9979 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 9980 }, 9981 outputs: []outputInfo{ 9982 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 9983 }, 9984 }, 9985 }, 9986 { 9987 name: "MULW", 9988 argLen: 2, 9989 commutative: true, 9990 asm: arm64.AMULW, 9991 reg: regInfo{ 9992 inputs: []inputInfo{ 9993 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 9994 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 9995 }, 9996 outputs: []outputInfo{ 9997 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 9998 }, 9999 }, 10000 }, 10001 { 10002 name: "MULH", 10003 argLen: 2, 10004 commutative: true, 10005 asm: arm64.ASMULH, 10006 reg: regInfo{ 10007 inputs: []inputInfo{ 10008 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10009 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10010 }, 10011 outputs: []outputInfo{ 10012 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10013 }, 10014 }, 10015 }, 10016 { 10017 name: "UMULH", 10018 argLen: 2, 10019 commutative: true, 10020 asm: arm64.AUMULH, 10021 reg: regInfo{ 10022 inputs: []inputInfo{ 10023 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10024 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10025 }, 10026 outputs: []outputInfo{ 10027 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10028 }, 10029 }, 10030 }, 10031 { 10032 name: "MULL", 10033 argLen: 2, 10034 commutative: true, 10035 asm: arm64.ASMULL, 10036 reg: regInfo{ 10037 inputs: []inputInfo{ 10038 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10039 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10040 }, 10041 outputs: []outputInfo{ 10042 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10043 }, 10044 }, 10045 }, 10046 { 10047 name: "UMULL", 10048 argLen: 2, 10049 commutative: true, 10050 asm: arm64.AUMULL, 10051 reg: regInfo{ 10052 inputs: []inputInfo{ 10053 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10054 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10055 }, 10056 outputs: []outputInfo{ 10057 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10058 }, 10059 }, 10060 }, 10061 { 10062 name: "DIV", 10063 argLen: 2, 10064 asm: arm64.ASDIV, 10065 reg: regInfo{ 10066 inputs: []inputInfo{ 10067 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10068 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10069 }, 10070 outputs: []outputInfo{ 10071 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10072 }, 10073 }, 10074 }, 10075 { 10076 name: "UDIV", 10077 argLen: 2, 10078 asm: arm64.AUDIV, 10079 reg: regInfo{ 10080 inputs: []inputInfo{ 10081 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10082 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10083 }, 10084 outputs: []outputInfo{ 10085 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10086 }, 10087 }, 10088 }, 10089 { 10090 name: "DIVW", 10091 argLen: 2, 10092 asm: arm64.ASDIVW, 10093 reg: regInfo{ 10094 inputs: []inputInfo{ 10095 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10096 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10097 }, 10098 outputs: []outputInfo{ 10099 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10100 }, 10101 }, 10102 }, 10103 { 10104 name: "UDIVW", 10105 argLen: 2, 10106 asm: arm64.AUDIVW, 10107 reg: regInfo{ 10108 inputs: []inputInfo{ 10109 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10110 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10111 }, 10112 outputs: []outputInfo{ 10113 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10114 }, 10115 }, 10116 }, 10117 { 10118 name: "MOD", 10119 argLen: 2, 10120 asm: arm64.AREM, 10121 reg: regInfo{ 10122 inputs: []inputInfo{ 10123 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10124 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10125 }, 10126 outputs: []outputInfo{ 10127 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10128 }, 10129 }, 10130 }, 10131 { 10132 name: "UMOD", 10133 argLen: 2, 10134 asm: arm64.AUREM, 10135 reg: regInfo{ 10136 inputs: []inputInfo{ 10137 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10138 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10139 }, 10140 outputs: []outputInfo{ 10141 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10142 }, 10143 }, 10144 }, 10145 { 10146 name: "MODW", 10147 argLen: 2, 10148 asm: arm64.AREMW, 10149 reg: regInfo{ 10150 inputs: []inputInfo{ 10151 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10152 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10153 }, 10154 outputs: []outputInfo{ 10155 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10156 }, 10157 }, 10158 }, 10159 { 10160 name: "UMODW", 10161 argLen: 2, 10162 asm: arm64.AUREMW, 10163 reg: regInfo{ 10164 inputs: []inputInfo{ 10165 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10166 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10167 }, 10168 outputs: []outputInfo{ 10169 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10170 }, 10171 }, 10172 }, 10173 { 10174 name: "FADDS", 10175 argLen: 2, 10176 commutative: true, 10177 asm: arm64.AFADDS, 10178 reg: regInfo{ 10179 inputs: []inputInfo{ 10180 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10181 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10182 }, 10183 outputs: []outputInfo{ 10184 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10185 }, 10186 }, 10187 }, 10188 { 10189 name: "FADDD", 10190 argLen: 2, 10191 commutative: true, 10192 asm: arm64.AFADDD, 10193 reg: regInfo{ 10194 inputs: []inputInfo{ 10195 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10196 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10197 }, 10198 outputs: []outputInfo{ 10199 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10200 }, 10201 }, 10202 }, 10203 { 10204 name: "FSUBS", 10205 argLen: 2, 10206 asm: arm64.AFSUBS, 10207 reg: regInfo{ 10208 inputs: []inputInfo{ 10209 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10210 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10211 }, 10212 outputs: []outputInfo{ 10213 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10214 }, 10215 }, 10216 }, 10217 { 10218 name: "FSUBD", 10219 argLen: 2, 10220 asm: arm64.AFSUBD, 10221 reg: regInfo{ 10222 inputs: []inputInfo{ 10223 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10224 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10225 }, 10226 outputs: []outputInfo{ 10227 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10228 }, 10229 }, 10230 }, 10231 { 10232 name: "FMULS", 10233 argLen: 2, 10234 commutative: true, 10235 asm: arm64.AFMULS, 10236 reg: regInfo{ 10237 inputs: []inputInfo{ 10238 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10239 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10240 }, 10241 outputs: []outputInfo{ 10242 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10243 }, 10244 }, 10245 }, 10246 { 10247 name: "FMULD", 10248 argLen: 2, 10249 commutative: true, 10250 asm: arm64.AFMULD, 10251 reg: regInfo{ 10252 inputs: []inputInfo{ 10253 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10254 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10255 }, 10256 outputs: []outputInfo{ 10257 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10258 }, 10259 }, 10260 }, 10261 { 10262 name: "FDIVS", 10263 argLen: 2, 10264 asm: arm64.AFDIVS, 10265 reg: regInfo{ 10266 inputs: []inputInfo{ 10267 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10268 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10269 }, 10270 outputs: []outputInfo{ 10271 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10272 }, 10273 }, 10274 }, 10275 { 10276 name: "FDIVD", 10277 argLen: 2, 10278 asm: arm64.AFDIVD, 10279 reg: regInfo{ 10280 inputs: []inputInfo{ 10281 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10282 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10283 }, 10284 outputs: []outputInfo{ 10285 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10286 }, 10287 }, 10288 }, 10289 { 10290 name: "AND", 10291 argLen: 2, 10292 commutative: true, 10293 asm: arm64.AAND, 10294 reg: regInfo{ 10295 inputs: []inputInfo{ 10296 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10297 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10298 }, 10299 outputs: []outputInfo{ 10300 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10301 }, 10302 }, 10303 }, 10304 { 10305 name: "ANDconst", 10306 auxType: auxInt64, 10307 argLen: 1, 10308 asm: arm64.AAND, 10309 reg: regInfo{ 10310 inputs: []inputInfo{ 10311 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10312 }, 10313 outputs: []outputInfo{ 10314 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10315 }, 10316 }, 10317 }, 10318 { 10319 name: "OR", 10320 argLen: 2, 10321 commutative: true, 10322 asm: arm64.AORR, 10323 reg: regInfo{ 10324 inputs: []inputInfo{ 10325 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10326 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10327 }, 10328 outputs: []outputInfo{ 10329 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10330 }, 10331 }, 10332 }, 10333 { 10334 name: "ORconst", 10335 auxType: auxInt64, 10336 argLen: 1, 10337 asm: arm64.AORR, 10338 reg: regInfo{ 10339 inputs: []inputInfo{ 10340 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10341 }, 10342 outputs: []outputInfo{ 10343 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10344 }, 10345 }, 10346 }, 10347 { 10348 name: "XOR", 10349 argLen: 2, 10350 commutative: true, 10351 asm: arm64.AEOR, 10352 reg: regInfo{ 10353 inputs: []inputInfo{ 10354 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10355 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10356 }, 10357 outputs: []outputInfo{ 10358 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10359 }, 10360 }, 10361 }, 10362 { 10363 name: "XORconst", 10364 auxType: auxInt64, 10365 argLen: 1, 10366 asm: arm64.AEOR, 10367 reg: regInfo{ 10368 inputs: []inputInfo{ 10369 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10370 }, 10371 outputs: []outputInfo{ 10372 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10373 }, 10374 }, 10375 }, 10376 { 10377 name: "BIC", 10378 argLen: 2, 10379 asm: arm64.ABIC, 10380 reg: regInfo{ 10381 inputs: []inputInfo{ 10382 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10383 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10384 }, 10385 outputs: []outputInfo{ 10386 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10387 }, 10388 }, 10389 }, 10390 { 10391 name: "BICconst", 10392 auxType: auxInt64, 10393 argLen: 1, 10394 asm: arm64.ABIC, 10395 reg: regInfo{ 10396 inputs: []inputInfo{ 10397 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10398 }, 10399 outputs: []outputInfo{ 10400 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10401 }, 10402 }, 10403 }, 10404 { 10405 name: "MVN", 10406 argLen: 1, 10407 asm: arm64.AMVN, 10408 reg: regInfo{ 10409 inputs: []inputInfo{ 10410 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10411 }, 10412 outputs: []outputInfo{ 10413 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10414 }, 10415 }, 10416 }, 10417 { 10418 name: "NEG", 10419 argLen: 1, 10420 asm: arm64.ANEG, 10421 reg: regInfo{ 10422 inputs: []inputInfo{ 10423 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10424 }, 10425 outputs: []outputInfo{ 10426 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10427 }, 10428 }, 10429 }, 10430 { 10431 name: "FNEGS", 10432 argLen: 1, 10433 asm: arm64.AFNEGS, 10434 reg: regInfo{ 10435 inputs: []inputInfo{ 10436 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10437 }, 10438 outputs: []outputInfo{ 10439 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10440 }, 10441 }, 10442 }, 10443 { 10444 name: "FNEGD", 10445 argLen: 1, 10446 asm: arm64.AFNEGD, 10447 reg: regInfo{ 10448 inputs: []inputInfo{ 10449 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10450 }, 10451 outputs: []outputInfo{ 10452 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10453 }, 10454 }, 10455 }, 10456 { 10457 name: "FSQRTD", 10458 argLen: 1, 10459 asm: arm64.AFSQRTD, 10460 reg: regInfo{ 10461 inputs: []inputInfo{ 10462 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10463 }, 10464 outputs: []outputInfo{ 10465 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10466 }, 10467 }, 10468 }, 10469 { 10470 name: "REV", 10471 argLen: 1, 10472 asm: arm64.AREV, 10473 reg: regInfo{ 10474 inputs: []inputInfo{ 10475 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10476 }, 10477 outputs: []outputInfo{ 10478 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10479 }, 10480 }, 10481 }, 10482 { 10483 name: "REVW", 10484 argLen: 1, 10485 asm: arm64.AREVW, 10486 reg: regInfo{ 10487 inputs: []inputInfo{ 10488 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10489 }, 10490 outputs: []outputInfo{ 10491 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10492 }, 10493 }, 10494 }, 10495 { 10496 name: "REV16W", 10497 argLen: 1, 10498 asm: arm64.AREV16W, 10499 reg: regInfo{ 10500 inputs: []inputInfo{ 10501 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10502 }, 10503 outputs: []outputInfo{ 10504 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10505 }, 10506 }, 10507 }, 10508 { 10509 name: "SLL", 10510 argLen: 2, 10511 asm: arm64.ALSL, 10512 reg: regInfo{ 10513 inputs: []inputInfo{ 10514 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10515 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10516 }, 10517 outputs: []outputInfo{ 10518 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10519 }, 10520 }, 10521 }, 10522 { 10523 name: "SLLconst", 10524 auxType: auxInt64, 10525 argLen: 1, 10526 asm: arm64.ALSL, 10527 reg: regInfo{ 10528 inputs: []inputInfo{ 10529 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10530 }, 10531 outputs: []outputInfo{ 10532 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10533 }, 10534 }, 10535 }, 10536 { 10537 name: "SRL", 10538 argLen: 2, 10539 asm: arm64.ALSR, 10540 reg: regInfo{ 10541 inputs: []inputInfo{ 10542 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10543 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10544 }, 10545 outputs: []outputInfo{ 10546 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10547 }, 10548 }, 10549 }, 10550 { 10551 name: "SRLconst", 10552 auxType: auxInt64, 10553 argLen: 1, 10554 asm: arm64.ALSR, 10555 reg: regInfo{ 10556 inputs: []inputInfo{ 10557 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10558 }, 10559 outputs: []outputInfo{ 10560 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10561 }, 10562 }, 10563 }, 10564 { 10565 name: "SRA", 10566 argLen: 2, 10567 asm: arm64.AASR, 10568 reg: regInfo{ 10569 inputs: []inputInfo{ 10570 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10571 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10572 }, 10573 outputs: []outputInfo{ 10574 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10575 }, 10576 }, 10577 }, 10578 { 10579 name: "SRAconst", 10580 auxType: auxInt64, 10581 argLen: 1, 10582 asm: arm64.AASR, 10583 reg: regInfo{ 10584 inputs: []inputInfo{ 10585 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10586 }, 10587 outputs: []outputInfo{ 10588 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10589 }, 10590 }, 10591 }, 10592 { 10593 name: "RORconst", 10594 auxType: auxInt64, 10595 argLen: 1, 10596 asm: arm64.AROR, 10597 reg: regInfo{ 10598 inputs: []inputInfo{ 10599 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10600 }, 10601 outputs: []outputInfo{ 10602 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10603 }, 10604 }, 10605 }, 10606 { 10607 name: "RORWconst", 10608 auxType: auxInt64, 10609 argLen: 1, 10610 asm: arm64.ARORW, 10611 reg: regInfo{ 10612 inputs: []inputInfo{ 10613 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10614 }, 10615 outputs: []outputInfo{ 10616 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10617 }, 10618 }, 10619 }, 10620 { 10621 name: "CMP", 10622 argLen: 2, 10623 asm: arm64.ACMP, 10624 reg: regInfo{ 10625 inputs: []inputInfo{ 10626 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10627 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10628 }, 10629 }, 10630 }, 10631 { 10632 name: "CMPconst", 10633 auxType: auxInt64, 10634 argLen: 1, 10635 asm: arm64.ACMP, 10636 reg: regInfo{ 10637 inputs: []inputInfo{ 10638 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10639 }, 10640 }, 10641 }, 10642 { 10643 name: "CMPW", 10644 argLen: 2, 10645 asm: arm64.ACMPW, 10646 reg: regInfo{ 10647 inputs: []inputInfo{ 10648 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10649 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10650 }, 10651 }, 10652 }, 10653 { 10654 name: "CMPWconst", 10655 auxType: auxInt32, 10656 argLen: 1, 10657 asm: arm64.ACMPW, 10658 reg: regInfo{ 10659 inputs: []inputInfo{ 10660 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10661 }, 10662 }, 10663 }, 10664 { 10665 name: "CMN", 10666 argLen: 2, 10667 asm: arm64.ACMN, 10668 reg: regInfo{ 10669 inputs: []inputInfo{ 10670 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10671 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10672 }, 10673 }, 10674 }, 10675 { 10676 name: "CMNconst", 10677 auxType: auxInt64, 10678 argLen: 1, 10679 asm: arm64.ACMN, 10680 reg: regInfo{ 10681 inputs: []inputInfo{ 10682 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10683 }, 10684 }, 10685 }, 10686 { 10687 name: "CMNW", 10688 argLen: 2, 10689 asm: arm64.ACMNW, 10690 reg: regInfo{ 10691 inputs: []inputInfo{ 10692 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10693 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10694 }, 10695 }, 10696 }, 10697 { 10698 name: "CMNWconst", 10699 auxType: auxInt32, 10700 argLen: 1, 10701 asm: arm64.ACMNW, 10702 reg: regInfo{ 10703 inputs: []inputInfo{ 10704 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10705 }, 10706 }, 10707 }, 10708 { 10709 name: "FCMPS", 10710 argLen: 2, 10711 asm: arm64.AFCMPS, 10712 reg: regInfo{ 10713 inputs: []inputInfo{ 10714 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10715 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10716 }, 10717 }, 10718 }, 10719 { 10720 name: "FCMPD", 10721 argLen: 2, 10722 asm: arm64.AFCMPD, 10723 reg: regInfo{ 10724 inputs: []inputInfo{ 10725 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10726 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10727 }, 10728 }, 10729 }, 10730 { 10731 name: "ADDshiftLL", 10732 auxType: auxInt64, 10733 argLen: 2, 10734 asm: arm64.AADD, 10735 reg: regInfo{ 10736 inputs: []inputInfo{ 10737 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10738 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10739 }, 10740 outputs: []outputInfo{ 10741 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10742 }, 10743 }, 10744 }, 10745 { 10746 name: "ADDshiftRL", 10747 auxType: auxInt64, 10748 argLen: 2, 10749 asm: arm64.AADD, 10750 reg: regInfo{ 10751 inputs: []inputInfo{ 10752 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10753 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10754 }, 10755 outputs: []outputInfo{ 10756 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10757 }, 10758 }, 10759 }, 10760 { 10761 name: "ADDshiftRA", 10762 auxType: auxInt64, 10763 argLen: 2, 10764 asm: arm64.AADD, 10765 reg: regInfo{ 10766 inputs: []inputInfo{ 10767 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10768 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10769 }, 10770 outputs: []outputInfo{ 10771 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10772 }, 10773 }, 10774 }, 10775 { 10776 name: "SUBshiftLL", 10777 auxType: auxInt64, 10778 argLen: 2, 10779 asm: arm64.ASUB, 10780 reg: regInfo{ 10781 inputs: []inputInfo{ 10782 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10783 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10784 }, 10785 outputs: []outputInfo{ 10786 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10787 }, 10788 }, 10789 }, 10790 { 10791 name: "SUBshiftRL", 10792 auxType: auxInt64, 10793 argLen: 2, 10794 asm: arm64.ASUB, 10795 reg: regInfo{ 10796 inputs: []inputInfo{ 10797 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10798 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10799 }, 10800 outputs: []outputInfo{ 10801 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10802 }, 10803 }, 10804 }, 10805 { 10806 name: "SUBshiftRA", 10807 auxType: auxInt64, 10808 argLen: 2, 10809 asm: arm64.ASUB, 10810 reg: regInfo{ 10811 inputs: []inputInfo{ 10812 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10813 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10814 }, 10815 outputs: []outputInfo{ 10816 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10817 }, 10818 }, 10819 }, 10820 { 10821 name: "ANDshiftLL", 10822 auxType: auxInt64, 10823 argLen: 2, 10824 asm: arm64.AAND, 10825 reg: regInfo{ 10826 inputs: []inputInfo{ 10827 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10828 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10829 }, 10830 outputs: []outputInfo{ 10831 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10832 }, 10833 }, 10834 }, 10835 { 10836 name: "ANDshiftRL", 10837 auxType: auxInt64, 10838 argLen: 2, 10839 asm: arm64.AAND, 10840 reg: regInfo{ 10841 inputs: []inputInfo{ 10842 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10843 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10844 }, 10845 outputs: []outputInfo{ 10846 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10847 }, 10848 }, 10849 }, 10850 { 10851 name: "ANDshiftRA", 10852 auxType: auxInt64, 10853 argLen: 2, 10854 asm: arm64.AAND, 10855 reg: regInfo{ 10856 inputs: []inputInfo{ 10857 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10858 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10859 }, 10860 outputs: []outputInfo{ 10861 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10862 }, 10863 }, 10864 }, 10865 { 10866 name: "ORshiftLL", 10867 auxType: auxInt64, 10868 argLen: 2, 10869 asm: arm64.AORR, 10870 reg: regInfo{ 10871 inputs: []inputInfo{ 10872 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10873 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10874 }, 10875 outputs: []outputInfo{ 10876 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10877 }, 10878 }, 10879 }, 10880 { 10881 name: "ORshiftRL", 10882 auxType: auxInt64, 10883 argLen: 2, 10884 asm: arm64.AORR, 10885 reg: regInfo{ 10886 inputs: []inputInfo{ 10887 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10888 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10889 }, 10890 outputs: []outputInfo{ 10891 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10892 }, 10893 }, 10894 }, 10895 { 10896 name: "ORshiftRA", 10897 auxType: auxInt64, 10898 argLen: 2, 10899 asm: arm64.AORR, 10900 reg: regInfo{ 10901 inputs: []inputInfo{ 10902 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10903 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10904 }, 10905 outputs: []outputInfo{ 10906 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10907 }, 10908 }, 10909 }, 10910 { 10911 name: "XORshiftLL", 10912 auxType: auxInt64, 10913 argLen: 2, 10914 asm: arm64.AEOR, 10915 reg: regInfo{ 10916 inputs: []inputInfo{ 10917 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10918 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10919 }, 10920 outputs: []outputInfo{ 10921 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10922 }, 10923 }, 10924 }, 10925 { 10926 name: "XORshiftRL", 10927 auxType: auxInt64, 10928 argLen: 2, 10929 asm: arm64.AEOR, 10930 reg: regInfo{ 10931 inputs: []inputInfo{ 10932 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10933 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10934 }, 10935 outputs: []outputInfo{ 10936 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10937 }, 10938 }, 10939 }, 10940 { 10941 name: "XORshiftRA", 10942 auxType: auxInt64, 10943 argLen: 2, 10944 asm: arm64.AEOR, 10945 reg: regInfo{ 10946 inputs: []inputInfo{ 10947 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10948 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10949 }, 10950 outputs: []outputInfo{ 10951 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10952 }, 10953 }, 10954 }, 10955 { 10956 name: "BICshiftLL", 10957 auxType: auxInt64, 10958 argLen: 2, 10959 asm: arm64.ABIC, 10960 reg: regInfo{ 10961 inputs: []inputInfo{ 10962 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10963 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10964 }, 10965 outputs: []outputInfo{ 10966 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10967 }, 10968 }, 10969 }, 10970 { 10971 name: "BICshiftRL", 10972 auxType: auxInt64, 10973 argLen: 2, 10974 asm: arm64.ABIC, 10975 reg: regInfo{ 10976 inputs: []inputInfo{ 10977 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10978 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10979 }, 10980 outputs: []outputInfo{ 10981 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10982 }, 10983 }, 10984 }, 10985 { 10986 name: "BICshiftRA", 10987 auxType: auxInt64, 10988 argLen: 2, 10989 asm: arm64.ABIC, 10990 reg: regInfo{ 10991 inputs: []inputInfo{ 10992 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10993 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10994 }, 10995 outputs: []outputInfo{ 10996 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10997 }, 10998 }, 10999 }, 11000 { 11001 name: "CMPshiftLL", 11002 auxType: auxInt64, 11003 argLen: 2, 11004 asm: arm64.ACMP, 11005 reg: regInfo{ 11006 inputs: []inputInfo{ 11007 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11008 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11009 }, 11010 }, 11011 }, 11012 { 11013 name: "CMPshiftRL", 11014 auxType: auxInt64, 11015 argLen: 2, 11016 asm: arm64.ACMP, 11017 reg: regInfo{ 11018 inputs: []inputInfo{ 11019 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11020 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11021 }, 11022 }, 11023 }, 11024 { 11025 name: "CMPshiftRA", 11026 auxType: auxInt64, 11027 argLen: 2, 11028 asm: arm64.ACMP, 11029 reg: regInfo{ 11030 inputs: []inputInfo{ 11031 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11032 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11033 }, 11034 }, 11035 }, 11036 { 11037 name: "MOVDconst", 11038 auxType: auxInt64, 11039 argLen: 0, 11040 rematerializeable: true, 11041 asm: arm64.AMOVD, 11042 reg: regInfo{ 11043 outputs: []outputInfo{ 11044 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11045 }, 11046 }, 11047 }, 11048 { 11049 name: "FMOVSconst", 11050 auxType: auxFloat64, 11051 argLen: 0, 11052 rematerializeable: true, 11053 asm: arm64.AFMOVS, 11054 reg: regInfo{ 11055 outputs: []outputInfo{ 11056 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11057 }, 11058 }, 11059 }, 11060 { 11061 name: "FMOVDconst", 11062 auxType: auxFloat64, 11063 argLen: 0, 11064 rematerializeable: true, 11065 asm: arm64.AFMOVD, 11066 reg: regInfo{ 11067 outputs: []outputInfo{ 11068 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11069 }, 11070 }, 11071 }, 11072 { 11073 name: "MOVDaddr", 11074 auxType: auxSymOff, 11075 argLen: 1, 11076 rematerializeable: true, 11077 asm: arm64.AMOVD, 11078 reg: regInfo{ 11079 inputs: []inputInfo{ 11080 {0, 4611686018964258816}, // SP SB 11081 }, 11082 outputs: []outputInfo{ 11083 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11084 }, 11085 }, 11086 }, 11087 { 11088 name: "MOVBload", 11089 auxType: auxSymOff, 11090 argLen: 2, 11091 asm: arm64.AMOVB, 11092 reg: regInfo{ 11093 inputs: []inputInfo{ 11094 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11095 }, 11096 outputs: []outputInfo{ 11097 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11098 }, 11099 }, 11100 }, 11101 { 11102 name: "MOVBUload", 11103 auxType: auxSymOff, 11104 argLen: 2, 11105 asm: arm64.AMOVBU, 11106 reg: regInfo{ 11107 inputs: []inputInfo{ 11108 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11109 }, 11110 outputs: []outputInfo{ 11111 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11112 }, 11113 }, 11114 }, 11115 { 11116 name: "MOVHload", 11117 auxType: auxSymOff, 11118 argLen: 2, 11119 asm: arm64.AMOVH, 11120 reg: regInfo{ 11121 inputs: []inputInfo{ 11122 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11123 }, 11124 outputs: []outputInfo{ 11125 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11126 }, 11127 }, 11128 }, 11129 { 11130 name: "MOVHUload", 11131 auxType: auxSymOff, 11132 argLen: 2, 11133 asm: arm64.AMOVHU, 11134 reg: regInfo{ 11135 inputs: []inputInfo{ 11136 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11137 }, 11138 outputs: []outputInfo{ 11139 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11140 }, 11141 }, 11142 }, 11143 { 11144 name: "MOVWload", 11145 auxType: auxSymOff, 11146 argLen: 2, 11147 asm: arm64.AMOVW, 11148 reg: regInfo{ 11149 inputs: []inputInfo{ 11150 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11151 }, 11152 outputs: []outputInfo{ 11153 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11154 }, 11155 }, 11156 }, 11157 { 11158 name: "MOVWUload", 11159 auxType: auxSymOff, 11160 argLen: 2, 11161 asm: arm64.AMOVWU, 11162 reg: regInfo{ 11163 inputs: []inputInfo{ 11164 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11165 }, 11166 outputs: []outputInfo{ 11167 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11168 }, 11169 }, 11170 }, 11171 { 11172 name: "MOVDload", 11173 auxType: auxSymOff, 11174 argLen: 2, 11175 asm: arm64.AMOVD, 11176 reg: regInfo{ 11177 inputs: []inputInfo{ 11178 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11179 }, 11180 outputs: []outputInfo{ 11181 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11182 }, 11183 }, 11184 }, 11185 { 11186 name: "FMOVSload", 11187 auxType: auxSymOff, 11188 argLen: 2, 11189 asm: arm64.AFMOVS, 11190 reg: regInfo{ 11191 inputs: []inputInfo{ 11192 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11193 }, 11194 outputs: []outputInfo{ 11195 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11196 }, 11197 }, 11198 }, 11199 { 11200 name: "FMOVDload", 11201 auxType: auxSymOff, 11202 argLen: 2, 11203 asm: arm64.AFMOVD, 11204 reg: regInfo{ 11205 inputs: []inputInfo{ 11206 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11207 }, 11208 outputs: []outputInfo{ 11209 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11210 }, 11211 }, 11212 }, 11213 { 11214 name: "MOVBstore", 11215 auxType: auxSymOff, 11216 argLen: 3, 11217 asm: arm64.AMOVB, 11218 reg: regInfo{ 11219 inputs: []inputInfo{ 11220 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11221 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11222 }, 11223 }, 11224 }, 11225 { 11226 name: "MOVHstore", 11227 auxType: auxSymOff, 11228 argLen: 3, 11229 asm: arm64.AMOVH, 11230 reg: regInfo{ 11231 inputs: []inputInfo{ 11232 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11233 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11234 }, 11235 }, 11236 }, 11237 { 11238 name: "MOVWstore", 11239 auxType: auxSymOff, 11240 argLen: 3, 11241 asm: arm64.AMOVW, 11242 reg: regInfo{ 11243 inputs: []inputInfo{ 11244 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11245 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11246 }, 11247 }, 11248 }, 11249 { 11250 name: "MOVDstore", 11251 auxType: auxSymOff, 11252 argLen: 3, 11253 asm: arm64.AMOVD, 11254 reg: regInfo{ 11255 inputs: []inputInfo{ 11256 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11257 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11258 }, 11259 }, 11260 }, 11261 { 11262 name: "FMOVSstore", 11263 auxType: auxSymOff, 11264 argLen: 3, 11265 asm: arm64.AFMOVS, 11266 reg: regInfo{ 11267 inputs: []inputInfo{ 11268 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11269 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11270 }, 11271 }, 11272 }, 11273 { 11274 name: "FMOVDstore", 11275 auxType: auxSymOff, 11276 argLen: 3, 11277 asm: arm64.AFMOVD, 11278 reg: regInfo{ 11279 inputs: []inputInfo{ 11280 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11281 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11282 }, 11283 }, 11284 }, 11285 { 11286 name: "MOVBstorezero", 11287 auxType: auxSymOff, 11288 argLen: 2, 11289 asm: arm64.AMOVB, 11290 reg: regInfo{ 11291 inputs: []inputInfo{ 11292 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11293 }, 11294 }, 11295 }, 11296 { 11297 name: "MOVHstorezero", 11298 auxType: auxSymOff, 11299 argLen: 2, 11300 asm: arm64.AMOVH, 11301 reg: regInfo{ 11302 inputs: []inputInfo{ 11303 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11304 }, 11305 }, 11306 }, 11307 { 11308 name: "MOVWstorezero", 11309 auxType: auxSymOff, 11310 argLen: 2, 11311 asm: arm64.AMOVW, 11312 reg: regInfo{ 11313 inputs: []inputInfo{ 11314 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11315 }, 11316 }, 11317 }, 11318 { 11319 name: "MOVDstorezero", 11320 auxType: auxSymOff, 11321 argLen: 2, 11322 asm: arm64.AMOVD, 11323 reg: regInfo{ 11324 inputs: []inputInfo{ 11325 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11326 }, 11327 }, 11328 }, 11329 { 11330 name: "MOVBreg", 11331 argLen: 1, 11332 asm: arm64.AMOVB, 11333 reg: regInfo{ 11334 inputs: []inputInfo{ 11335 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11336 }, 11337 outputs: []outputInfo{ 11338 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11339 }, 11340 }, 11341 }, 11342 { 11343 name: "MOVBUreg", 11344 argLen: 1, 11345 asm: arm64.AMOVBU, 11346 reg: regInfo{ 11347 inputs: []inputInfo{ 11348 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11349 }, 11350 outputs: []outputInfo{ 11351 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11352 }, 11353 }, 11354 }, 11355 { 11356 name: "MOVHreg", 11357 argLen: 1, 11358 asm: arm64.AMOVH, 11359 reg: regInfo{ 11360 inputs: []inputInfo{ 11361 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11362 }, 11363 outputs: []outputInfo{ 11364 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11365 }, 11366 }, 11367 }, 11368 { 11369 name: "MOVHUreg", 11370 argLen: 1, 11371 asm: arm64.AMOVHU, 11372 reg: regInfo{ 11373 inputs: []inputInfo{ 11374 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11375 }, 11376 outputs: []outputInfo{ 11377 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11378 }, 11379 }, 11380 }, 11381 { 11382 name: "MOVWreg", 11383 argLen: 1, 11384 asm: arm64.AMOVW, 11385 reg: regInfo{ 11386 inputs: []inputInfo{ 11387 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11388 }, 11389 outputs: []outputInfo{ 11390 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11391 }, 11392 }, 11393 }, 11394 { 11395 name: "MOVWUreg", 11396 argLen: 1, 11397 asm: arm64.AMOVWU, 11398 reg: regInfo{ 11399 inputs: []inputInfo{ 11400 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11401 }, 11402 outputs: []outputInfo{ 11403 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11404 }, 11405 }, 11406 }, 11407 { 11408 name: "MOVDreg", 11409 argLen: 1, 11410 asm: arm64.AMOVD, 11411 reg: regInfo{ 11412 inputs: []inputInfo{ 11413 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11414 }, 11415 outputs: []outputInfo{ 11416 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11417 }, 11418 }, 11419 }, 11420 { 11421 name: "MOVDnop", 11422 argLen: 1, 11423 resultInArg0: true, 11424 reg: regInfo{ 11425 inputs: []inputInfo{ 11426 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11427 }, 11428 outputs: []outputInfo{ 11429 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11430 }, 11431 }, 11432 }, 11433 { 11434 name: "SCVTFWS", 11435 argLen: 1, 11436 asm: arm64.ASCVTFWS, 11437 reg: regInfo{ 11438 inputs: []inputInfo{ 11439 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11440 }, 11441 outputs: []outputInfo{ 11442 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11443 }, 11444 }, 11445 }, 11446 { 11447 name: "SCVTFWD", 11448 argLen: 1, 11449 asm: arm64.ASCVTFWD, 11450 reg: regInfo{ 11451 inputs: []inputInfo{ 11452 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11453 }, 11454 outputs: []outputInfo{ 11455 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11456 }, 11457 }, 11458 }, 11459 { 11460 name: "UCVTFWS", 11461 argLen: 1, 11462 asm: arm64.AUCVTFWS, 11463 reg: regInfo{ 11464 inputs: []inputInfo{ 11465 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11466 }, 11467 outputs: []outputInfo{ 11468 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11469 }, 11470 }, 11471 }, 11472 { 11473 name: "UCVTFWD", 11474 argLen: 1, 11475 asm: arm64.AUCVTFWD, 11476 reg: regInfo{ 11477 inputs: []inputInfo{ 11478 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11479 }, 11480 outputs: []outputInfo{ 11481 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11482 }, 11483 }, 11484 }, 11485 { 11486 name: "SCVTFS", 11487 argLen: 1, 11488 asm: arm64.ASCVTFS, 11489 reg: regInfo{ 11490 inputs: []inputInfo{ 11491 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11492 }, 11493 outputs: []outputInfo{ 11494 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11495 }, 11496 }, 11497 }, 11498 { 11499 name: "SCVTFD", 11500 argLen: 1, 11501 asm: arm64.ASCVTFD, 11502 reg: regInfo{ 11503 inputs: []inputInfo{ 11504 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11505 }, 11506 outputs: []outputInfo{ 11507 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11508 }, 11509 }, 11510 }, 11511 { 11512 name: "UCVTFS", 11513 argLen: 1, 11514 asm: arm64.AUCVTFS, 11515 reg: regInfo{ 11516 inputs: []inputInfo{ 11517 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11518 }, 11519 outputs: []outputInfo{ 11520 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11521 }, 11522 }, 11523 }, 11524 { 11525 name: "UCVTFD", 11526 argLen: 1, 11527 asm: arm64.AUCVTFD, 11528 reg: regInfo{ 11529 inputs: []inputInfo{ 11530 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11531 }, 11532 outputs: []outputInfo{ 11533 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11534 }, 11535 }, 11536 }, 11537 { 11538 name: "FCVTZSSW", 11539 argLen: 1, 11540 asm: arm64.AFCVTZSSW, 11541 reg: regInfo{ 11542 inputs: []inputInfo{ 11543 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11544 }, 11545 outputs: []outputInfo{ 11546 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11547 }, 11548 }, 11549 }, 11550 { 11551 name: "FCVTZSDW", 11552 argLen: 1, 11553 asm: arm64.AFCVTZSDW, 11554 reg: regInfo{ 11555 inputs: []inputInfo{ 11556 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11557 }, 11558 outputs: []outputInfo{ 11559 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11560 }, 11561 }, 11562 }, 11563 { 11564 name: "FCVTZUSW", 11565 argLen: 1, 11566 asm: arm64.AFCVTZUSW, 11567 reg: regInfo{ 11568 inputs: []inputInfo{ 11569 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11570 }, 11571 outputs: []outputInfo{ 11572 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11573 }, 11574 }, 11575 }, 11576 { 11577 name: "FCVTZUDW", 11578 argLen: 1, 11579 asm: arm64.AFCVTZUDW, 11580 reg: regInfo{ 11581 inputs: []inputInfo{ 11582 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11583 }, 11584 outputs: []outputInfo{ 11585 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11586 }, 11587 }, 11588 }, 11589 { 11590 name: "FCVTZSS", 11591 argLen: 1, 11592 asm: arm64.AFCVTZSS, 11593 reg: regInfo{ 11594 inputs: []inputInfo{ 11595 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11596 }, 11597 outputs: []outputInfo{ 11598 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11599 }, 11600 }, 11601 }, 11602 { 11603 name: "FCVTZSD", 11604 argLen: 1, 11605 asm: arm64.AFCVTZSD, 11606 reg: regInfo{ 11607 inputs: []inputInfo{ 11608 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11609 }, 11610 outputs: []outputInfo{ 11611 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11612 }, 11613 }, 11614 }, 11615 { 11616 name: "FCVTZUS", 11617 argLen: 1, 11618 asm: arm64.AFCVTZUS, 11619 reg: regInfo{ 11620 inputs: []inputInfo{ 11621 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11622 }, 11623 outputs: []outputInfo{ 11624 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11625 }, 11626 }, 11627 }, 11628 { 11629 name: "FCVTZUD", 11630 argLen: 1, 11631 asm: arm64.AFCVTZUD, 11632 reg: regInfo{ 11633 inputs: []inputInfo{ 11634 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11635 }, 11636 outputs: []outputInfo{ 11637 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11638 }, 11639 }, 11640 }, 11641 { 11642 name: "FCVTSD", 11643 argLen: 1, 11644 asm: arm64.AFCVTSD, 11645 reg: regInfo{ 11646 inputs: []inputInfo{ 11647 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11648 }, 11649 outputs: []outputInfo{ 11650 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11651 }, 11652 }, 11653 }, 11654 { 11655 name: "FCVTDS", 11656 argLen: 1, 11657 asm: arm64.AFCVTDS, 11658 reg: regInfo{ 11659 inputs: []inputInfo{ 11660 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11661 }, 11662 outputs: []outputInfo{ 11663 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11664 }, 11665 }, 11666 }, 11667 { 11668 name: "CSELULT", 11669 argLen: 3, 11670 asm: arm64.ACSEL, 11671 reg: regInfo{ 11672 inputs: []inputInfo{ 11673 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11674 {1, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11675 }, 11676 outputs: []outputInfo{ 11677 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11678 }, 11679 }, 11680 }, 11681 { 11682 name: "CSELULT0", 11683 argLen: 2, 11684 asm: arm64.ACSEL, 11685 reg: regInfo{ 11686 inputs: []inputInfo{ 11687 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11688 }, 11689 outputs: []outputInfo{ 11690 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11691 }, 11692 }, 11693 }, 11694 { 11695 name: "CALLstatic", 11696 auxType: auxSymOff, 11697 argLen: 1, 11698 clobberFlags: true, 11699 reg: regInfo{ 11700 clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11701 }, 11702 }, 11703 { 11704 name: "CALLclosure", 11705 auxType: auxInt64, 11706 argLen: 3, 11707 clobberFlags: true, 11708 reg: regInfo{ 11709 inputs: []inputInfo{ 11710 {1, 67108864}, // R26 11711 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 SP 11712 }, 11713 clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11714 }, 11715 }, 11716 { 11717 name: "CALLdefer", 11718 auxType: auxInt64, 11719 argLen: 1, 11720 clobberFlags: true, 11721 reg: regInfo{ 11722 clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11723 }, 11724 }, 11725 { 11726 name: "CALLgo", 11727 auxType: auxInt64, 11728 argLen: 1, 11729 clobberFlags: true, 11730 reg: regInfo{ 11731 clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11732 }, 11733 }, 11734 { 11735 name: "CALLinter", 11736 auxType: auxInt64, 11737 argLen: 2, 11738 clobberFlags: true, 11739 reg: regInfo{ 11740 inputs: []inputInfo{ 11741 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11742 }, 11743 clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11744 }, 11745 }, 11746 { 11747 name: "LoweredNilCheck", 11748 argLen: 2, 11749 reg: regInfo{ 11750 inputs: []inputInfo{ 11751 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11752 }, 11753 }, 11754 }, 11755 { 11756 name: "Equal", 11757 argLen: 1, 11758 reg: regInfo{ 11759 outputs: []outputInfo{ 11760 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11761 }, 11762 }, 11763 }, 11764 { 11765 name: "NotEqual", 11766 argLen: 1, 11767 reg: regInfo{ 11768 outputs: []outputInfo{ 11769 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11770 }, 11771 }, 11772 }, 11773 { 11774 name: "LessThan", 11775 argLen: 1, 11776 reg: regInfo{ 11777 outputs: []outputInfo{ 11778 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11779 }, 11780 }, 11781 }, 11782 { 11783 name: "LessEqual", 11784 argLen: 1, 11785 reg: regInfo{ 11786 outputs: []outputInfo{ 11787 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11788 }, 11789 }, 11790 }, 11791 { 11792 name: "GreaterThan", 11793 argLen: 1, 11794 reg: regInfo{ 11795 outputs: []outputInfo{ 11796 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11797 }, 11798 }, 11799 }, 11800 { 11801 name: "GreaterEqual", 11802 argLen: 1, 11803 reg: regInfo{ 11804 outputs: []outputInfo{ 11805 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11806 }, 11807 }, 11808 }, 11809 { 11810 name: "LessThanU", 11811 argLen: 1, 11812 reg: regInfo{ 11813 outputs: []outputInfo{ 11814 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11815 }, 11816 }, 11817 }, 11818 { 11819 name: "LessEqualU", 11820 argLen: 1, 11821 reg: regInfo{ 11822 outputs: []outputInfo{ 11823 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11824 }, 11825 }, 11826 }, 11827 { 11828 name: "GreaterThanU", 11829 argLen: 1, 11830 reg: regInfo{ 11831 outputs: []outputInfo{ 11832 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11833 }, 11834 }, 11835 }, 11836 { 11837 name: "GreaterEqualU", 11838 argLen: 1, 11839 reg: regInfo{ 11840 outputs: []outputInfo{ 11841 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11842 }, 11843 }, 11844 }, 11845 { 11846 name: "DUFFZERO", 11847 auxType: auxInt64, 11848 argLen: 2, 11849 reg: regInfo{ 11850 inputs: []inputInfo{ 11851 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11852 }, 11853 clobbers: 65536, // R16 11854 }, 11855 }, 11856 { 11857 name: "LoweredZero", 11858 argLen: 3, 11859 clobberFlags: true, 11860 reg: regInfo{ 11861 inputs: []inputInfo{ 11862 {0, 65536}, // R16 11863 {1, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11864 }, 11865 clobbers: 65536, // R16 11866 }, 11867 }, 11868 { 11869 name: "LoweredMove", 11870 argLen: 4, 11871 clobberFlags: true, 11872 reg: regInfo{ 11873 inputs: []inputInfo{ 11874 {0, 131072}, // R17 11875 {1, 65536}, // R16 11876 {2, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11877 }, 11878 clobbers: 196608, // R16 R17 11879 }, 11880 }, 11881 { 11882 name: "LoweredGetClosurePtr", 11883 argLen: 0, 11884 reg: regInfo{ 11885 outputs: []outputInfo{ 11886 {0, 67108864}, // R26 11887 }, 11888 }, 11889 }, 11890 { 11891 name: "MOVDconvert", 11892 argLen: 2, 11893 asm: arm64.AMOVD, 11894 reg: regInfo{ 11895 inputs: []inputInfo{ 11896 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11897 }, 11898 outputs: []outputInfo{ 11899 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11900 }, 11901 }, 11902 }, 11903 { 11904 name: "FlagEQ", 11905 argLen: 0, 11906 reg: regInfo{}, 11907 }, 11908 { 11909 name: "FlagLT_ULT", 11910 argLen: 0, 11911 reg: regInfo{}, 11912 }, 11913 { 11914 name: "FlagLT_UGT", 11915 argLen: 0, 11916 reg: regInfo{}, 11917 }, 11918 { 11919 name: "FlagGT_UGT", 11920 argLen: 0, 11921 reg: regInfo{}, 11922 }, 11923 { 11924 name: "FlagGT_ULT", 11925 argLen: 0, 11926 reg: regInfo{}, 11927 }, 11928 { 11929 name: "InvertFlags", 11930 argLen: 1, 11931 reg: regInfo{}, 11932 }, 11933 11934 { 11935 name: "ADDV", 11936 argLen: 2, 11937 commutative: true, 11938 asm: mips.AADDVU, 11939 reg: regInfo{ 11940 inputs: []inputInfo{ 11941 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 11942 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 11943 }, 11944 outputs: []outputInfo{ 11945 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 11946 }, 11947 }, 11948 }, 11949 { 11950 name: "ADDVconst", 11951 auxType: auxInt64, 11952 argLen: 1, 11953 asm: mips.AADDVU, 11954 reg: regInfo{ 11955 inputs: []inputInfo{ 11956 {0, 134217726}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g 11957 }, 11958 outputs: []outputInfo{ 11959 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 11960 }, 11961 }, 11962 }, 11963 { 11964 name: "SUBV", 11965 argLen: 2, 11966 asm: mips.ASUBVU, 11967 reg: regInfo{ 11968 inputs: []inputInfo{ 11969 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 11970 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 11971 }, 11972 outputs: []outputInfo{ 11973 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 11974 }, 11975 }, 11976 }, 11977 { 11978 name: "SUBVconst", 11979 auxType: auxInt64, 11980 argLen: 1, 11981 asm: mips.ASUBVU, 11982 reg: regInfo{ 11983 inputs: []inputInfo{ 11984 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 11985 }, 11986 outputs: []outputInfo{ 11987 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 11988 }, 11989 }, 11990 }, 11991 { 11992 name: "MULV", 11993 argLen: 2, 11994 commutative: true, 11995 asm: mips.AMULV, 11996 reg: regInfo{ 11997 inputs: []inputInfo{ 11998 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 11999 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12000 }, 12001 outputs: []outputInfo{ 12002 {0, 576460752303423488}, // HI 12003 {1, 1152921504606846976}, // LO 12004 }, 12005 }, 12006 }, 12007 { 12008 name: "MULVU", 12009 argLen: 2, 12010 commutative: true, 12011 asm: mips.AMULVU, 12012 reg: regInfo{ 12013 inputs: []inputInfo{ 12014 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12015 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12016 }, 12017 outputs: []outputInfo{ 12018 {0, 576460752303423488}, // HI 12019 {1, 1152921504606846976}, // LO 12020 }, 12021 }, 12022 }, 12023 { 12024 name: "DIVV", 12025 argLen: 2, 12026 asm: mips.ADIVV, 12027 reg: regInfo{ 12028 inputs: []inputInfo{ 12029 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12030 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12031 }, 12032 outputs: []outputInfo{ 12033 {0, 576460752303423488}, // HI 12034 {1, 1152921504606846976}, // LO 12035 }, 12036 }, 12037 }, 12038 { 12039 name: "DIVVU", 12040 argLen: 2, 12041 asm: mips.ADIVVU, 12042 reg: regInfo{ 12043 inputs: []inputInfo{ 12044 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12045 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12046 }, 12047 outputs: []outputInfo{ 12048 {0, 576460752303423488}, // HI 12049 {1, 1152921504606846976}, // LO 12050 }, 12051 }, 12052 }, 12053 { 12054 name: "ADDF", 12055 argLen: 2, 12056 commutative: true, 12057 asm: mips.AADDF, 12058 reg: regInfo{ 12059 inputs: []inputInfo{ 12060 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12061 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12062 }, 12063 outputs: []outputInfo{ 12064 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12065 }, 12066 }, 12067 }, 12068 { 12069 name: "ADDD", 12070 argLen: 2, 12071 commutative: true, 12072 asm: mips.AADDD, 12073 reg: regInfo{ 12074 inputs: []inputInfo{ 12075 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12076 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12077 }, 12078 outputs: []outputInfo{ 12079 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12080 }, 12081 }, 12082 }, 12083 { 12084 name: "SUBF", 12085 argLen: 2, 12086 asm: mips.ASUBF, 12087 reg: regInfo{ 12088 inputs: []inputInfo{ 12089 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12090 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12091 }, 12092 outputs: []outputInfo{ 12093 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12094 }, 12095 }, 12096 }, 12097 { 12098 name: "SUBD", 12099 argLen: 2, 12100 asm: mips.ASUBD, 12101 reg: regInfo{ 12102 inputs: []inputInfo{ 12103 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12104 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12105 }, 12106 outputs: []outputInfo{ 12107 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12108 }, 12109 }, 12110 }, 12111 { 12112 name: "MULF", 12113 argLen: 2, 12114 commutative: true, 12115 asm: mips.AMULF, 12116 reg: regInfo{ 12117 inputs: []inputInfo{ 12118 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12119 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12120 }, 12121 outputs: []outputInfo{ 12122 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12123 }, 12124 }, 12125 }, 12126 { 12127 name: "MULD", 12128 argLen: 2, 12129 commutative: true, 12130 asm: mips.AMULD, 12131 reg: regInfo{ 12132 inputs: []inputInfo{ 12133 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12134 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12135 }, 12136 outputs: []outputInfo{ 12137 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12138 }, 12139 }, 12140 }, 12141 { 12142 name: "DIVF", 12143 argLen: 2, 12144 asm: mips.ADIVF, 12145 reg: regInfo{ 12146 inputs: []inputInfo{ 12147 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12148 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12149 }, 12150 outputs: []outputInfo{ 12151 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12152 }, 12153 }, 12154 }, 12155 { 12156 name: "DIVD", 12157 argLen: 2, 12158 asm: mips.ADIVD, 12159 reg: regInfo{ 12160 inputs: []inputInfo{ 12161 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12162 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12163 }, 12164 outputs: []outputInfo{ 12165 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12166 }, 12167 }, 12168 }, 12169 { 12170 name: "AND", 12171 argLen: 2, 12172 commutative: true, 12173 asm: mips.AAND, 12174 reg: regInfo{ 12175 inputs: []inputInfo{ 12176 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12177 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12178 }, 12179 outputs: []outputInfo{ 12180 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12181 }, 12182 }, 12183 }, 12184 { 12185 name: "ANDconst", 12186 auxType: auxInt64, 12187 argLen: 1, 12188 asm: mips.AAND, 12189 reg: regInfo{ 12190 inputs: []inputInfo{ 12191 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12192 }, 12193 outputs: []outputInfo{ 12194 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12195 }, 12196 }, 12197 }, 12198 { 12199 name: "OR", 12200 argLen: 2, 12201 commutative: true, 12202 asm: mips.AOR, 12203 reg: regInfo{ 12204 inputs: []inputInfo{ 12205 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12206 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12207 }, 12208 outputs: []outputInfo{ 12209 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12210 }, 12211 }, 12212 }, 12213 { 12214 name: "ORconst", 12215 auxType: auxInt64, 12216 argLen: 1, 12217 asm: mips.AOR, 12218 reg: regInfo{ 12219 inputs: []inputInfo{ 12220 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12221 }, 12222 outputs: []outputInfo{ 12223 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12224 }, 12225 }, 12226 }, 12227 { 12228 name: "XOR", 12229 argLen: 2, 12230 commutative: true, 12231 asm: mips.AXOR, 12232 reg: regInfo{ 12233 inputs: []inputInfo{ 12234 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12235 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12236 }, 12237 outputs: []outputInfo{ 12238 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12239 }, 12240 }, 12241 }, 12242 { 12243 name: "XORconst", 12244 auxType: auxInt64, 12245 argLen: 1, 12246 asm: mips.AXOR, 12247 reg: regInfo{ 12248 inputs: []inputInfo{ 12249 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12250 }, 12251 outputs: []outputInfo{ 12252 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12253 }, 12254 }, 12255 }, 12256 { 12257 name: "NOR", 12258 argLen: 2, 12259 commutative: true, 12260 asm: mips.ANOR, 12261 reg: regInfo{ 12262 inputs: []inputInfo{ 12263 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12264 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12265 }, 12266 outputs: []outputInfo{ 12267 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12268 }, 12269 }, 12270 }, 12271 { 12272 name: "NORconst", 12273 auxType: auxInt64, 12274 argLen: 1, 12275 asm: mips.ANOR, 12276 reg: regInfo{ 12277 inputs: []inputInfo{ 12278 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12279 }, 12280 outputs: []outputInfo{ 12281 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12282 }, 12283 }, 12284 }, 12285 { 12286 name: "NEGV", 12287 argLen: 1, 12288 reg: regInfo{ 12289 inputs: []inputInfo{ 12290 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12291 }, 12292 outputs: []outputInfo{ 12293 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12294 }, 12295 }, 12296 }, 12297 { 12298 name: "NEGF", 12299 argLen: 1, 12300 asm: mips.ANEGF, 12301 reg: regInfo{ 12302 inputs: []inputInfo{ 12303 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12304 }, 12305 outputs: []outputInfo{ 12306 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12307 }, 12308 }, 12309 }, 12310 { 12311 name: "NEGD", 12312 argLen: 1, 12313 asm: mips.ANEGD, 12314 reg: regInfo{ 12315 inputs: []inputInfo{ 12316 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12317 }, 12318 outputs: []outputInfo{ 12319 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12320 }, 12321 }, 12322 }, 12323 { 12324 name: "SLLV", 12325 argLen: 2, 12326 asm: mips.ASLLV, 12327 reg: regInfo{ 12328 inputs: []inputInfo{ 12329 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12330 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12331 }, 12332 outputs: []outputInfo{ 12333 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12334 }, 12335 }, 12336 }, 12337 { 12338 name: "SLLVconst", 12339 auxType: auxInt64, 12340 argLen: 1, 12341 asm: mips.ASLLV, 12342 reg: regInfo{ 12343 inputs: []inputInfo{ 12344 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12345 }, 12346 outputs: []outputInfo{ 12347 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12348 }, 12349 }, 12350 }, 12351 { 12352 name: "SRLV", 12353 argLen: 2, 12354 asm: mips.ASRLV, 12355 reg: regInfo{ 12356 inputs: []inputInfo{ 12357 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12358 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12359 }, 12360 outputs: []outputInfo{ 12361 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12362 }, 12363 }, 12364 }, 12365 { 12366 name: "SRLVconst", 12367 auxType: auxInt64, 12368 argLen: 1, 12369 asm: mips.ASRLV, 12370 reg: regInfo{ 12371 inputs: []inputInfo{ 12372 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12373 }, 12374 outputs: []outputInfo{ 12375 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12376 }, 12377 }, 12378 }, 12379 { 12380 name: "SRAV", 12381 argLen: 2, 12382 asm: mips.ASRAV, 12383 reg: regInfo{ 12384 inputs: []inputInfo{ 12385 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12386 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12387 }, 12388 outputs: []outputInfo{ 12389 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12390 }, 12391 }, 12392 }, 12393 { 12394 name: "SRAVconst", 12395 auxType: auxInt64, 12396 argLen: 1, 12397 asm: mips.ASRAV, 12398 reg: regInfo{ 12399 inputs: []inputInfo{ 12400 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12401 }, 12402 outputs: []outputInfo{ 12403 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12404 }, 12405 }, 12406 }, 12407 { 12408 name: "SGT", 12409 argLen: 2, 12410 asm: mips.ASGT, 12411 reg: regInfo{ 12412 inputs: []inputInfo{ 12413 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12414 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12415 }, 12416 outputs: []outputInfo{ 12417 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12418 }, 12419 }, 12420 }, 12421 { 12422 name: "SGTconst", 12423 auxType: auxInt64, 12424 argLen: 1, 12425 asm: mips.ASGT, 12426 reg: regInfo{ 12427 inputs: []inputInfo{ 12428 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12429 }, 12430 outputs: []outputInfo{ 12431 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12432 }, 12433 }, 12434 }, 12435 { 12436 name: "SGTU", 12437 argLen: 2, 12438 asm: mips.ASGTU, 12439 reg: regInfo{ 12440 inputs: []inputInfo{ 12441 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12442 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12443 }, 12444 outputs: []outputInfo{ 12445 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12446 }, 12447 }, 12448 }, 12449 { 12450 name: "SGTUconst", 12451 auxType: auxInt64, 12452 argLen: 1, 12453 asm: mips.ASGTU, 12454 reg: regInfo{ 12455 inputs: []inputInfo{ 12456 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12457 }, 12458 outputs: []outputInfo{ 12459 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12460 }, 12461 }, 12462 }, 12463 { 12464 name: "CMPEQF", 12465 argLen: 2, 12466 asm: mips.ACMPEQF, 12467 reg: regInfo{ 12468 inputs: []inputInfo{ 12469 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12470 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12471 }, 12472 }, 12473 }, 12474 { 12475 name: "CMPEQD", 12476 argLen: 2, 12477 asm: mips.ACMPEQD, 12478 reg: regInfo{ 12479 inputs: []inputInfo{ 12480 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12481 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12482 }, 12483 }, 12484 }, 12485 { 12486 name: "CMPGEF", 12487 argLen: 2, 12488 asm: mips.ACMPGEF, 12489 reg: regInfo{ 12490 inputs: []inputInfo{ 12491 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12492 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12493 }, 12494 }, 12495 }, 12496 { 12497 name: "CMPGED", 12498 argLen: 2, 12499 asm: mips.ACMPGED, 12500 reg: regInfo{ 12501 inputs: []inputInfo{ 12502 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12503 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12504 }, 12505 }, 12506 }, 12507 { 12508 name: "CMPGTF", 12509 argLen: 2, 12510 asm: mips.ACMPGTF, 12511 reg: regInfo{ 12512 inputs: []inputInfo{ 12513 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12514 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12515 }, 12516 }, 12517 }, 12518 { 12519 name: "CMPGTD", 12520 argLen: 2, 12521 asm: mips.ACMPGTD, 12522 reg: regInfo{ 12523 inputs: []inputInfo{ 12524 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12525 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12526 }, 12527 }, 12528 }, 12529 { 12530 name: "MOVVconst", 12531 auxType: auxInt64, 12532 argLen: 0, 12533 rematerializeable: true, 12534 asm: mips.AMOVV, 12535 reg: regInfo{ 12536 outputs: []outputInfo{ 12537 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12538 }, 12539 }, 12540 }, 12541 { 12542 name: "MOVFconst", 12543 auxType: auxFloat64, 12544 argLen: 0, 12545 rematerializeable: true, 12546 asm: mips.AMOVF, 12547 reg: regInfo{ 12548 outputs: []outputInfo{ 12549 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12550 }, 12551 }, 12552 }, 12553 { 12554 name: "MOVDconst", 12555 auxType: auxFloat64, 12556 argLen: 0, 12557 rematerializeable: true, 12558 asm: mips.AMOVD, 12559 reg: regInfo{ 12560 outputs: []outputInfo{ 12561 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12562 }, 12563 }, 12564 }, 12565 { 12566 name: "MOVVaddr", 12567 auxType: auxSymOff, 12568 argLen: 1, 12569 rematerializeable: true, 12570 asm: mips.AMOVV, 12571 reg: regInfo{ 12572 inputs: []inputInfo{ 12573 {0, 2305843009247248384}, // SP SB 12574 }, 12575 outputs: []outputInfo{ 12576 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12577 }, 12578 }, 12579 }, 12580 { 12581 name: "MOVBload", 12582 auxType: auxSymOff, 12583 argLen: 2, 12584 asm: mips.AMOVB, 12585 reg: regInfo{ 12586 inputs: []inputInfo{ 12587 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12588 }, 12589 outputs: []outputInfo{ 12590 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12591 }, 12592 }, 12593 }, 12594 { 12595 name: "MOVBUload", 12596 auxType: auxSymOff, 12597 argLen: 2, 12598 asm: mips.AMOVBU, 12599 reg: regInfo{ 12600 inputs: []inputInfo{ 12601 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12602 }, 12603 outputs: []outputInfo{ 12604 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12605 }, 12606 }, 12607 }, 12608 { 12609 name: "MOVHload", 12610 auxType: auxSymOff, 12611 argLen: 2, 12612 asm: mips.AMOVH, 12613 reg: regInfo{ 12614 inputs: []inputInfo{ 12615 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12616 }, 12617 outputs: []outputInfo{ 12618 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12619 }, 12620 }, 12621 }, 12622 { 12623 name: "MOVHUload", 12624 auxType: auxSymOff, 12625 argLen: 2, 12626 asm: mips.AMOVHU, 12627 reg: regInfo{ 12628 inputs: []inputInfo{ 12629 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12630 }, 12631 outputs: []outputInfo{ 12632 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12633 }, 12634 }, 12635 }, 12636 { 12637 name: "MOVWload", 12638 auxType: auxSymOff, 12639 argLen: 2, 12640 asm: mips.AMOVW, 12641 reg: regInfo{ 12642 inputs: []inputInfo{ 12643 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12644 }, 12645 outputs: []outputInfo{ 12646 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12647 }, 12648 }, 12649 }, 12650 { 12651 name: "MOVWUload", 12652 auxType: auxSymOff, 12653 argLen: 2, 12654 asm: mips.AMOVWU, 12655 reg: regInfo{ 12656 inputs: []inputInfo{ 12657 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12658 }, 12659 outputs: []outputInfo{ 12660 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12661 }, 12662 }, 12663 }, 12664 { 12665 name: "MOVVload", 12666 auxType: auxSymOff, 12667 argLen: 2, 12668 asm: mips.AMOVV, 12669 reg: regInfo{ 12670 inputs: []inputInfo{ 12671 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12672 }, 12673 outputs: []outputInfo{ 12674 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12675 }, 12676 }, 12677 }, 12678 { 12679 name: "MOVFload", 12680 auxType: auxSymOff, 12681 argLen: 2, 12682 asm: mips.AMOVF, 12683 reg: regInfo{ 12684 inputs: []inputInfo{ 12685 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12686 }, 12687 outputs: []outputInfo{ 12688 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12689 }, 12690 }, 12691 }, 12692 { 12693 name: "MOVDload", 12694 auxType: auxSymOff, 12695 argLen: 2, 12696 asm: mips.AMOVD, 12697 reg: regInfo{ 12698 inputs: []inputInfo{ 12699 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12700 }, 12701 outputs: []outputInfo{ 12702 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12703 }, 12704 }, 12705 }, 12706 { 12707 name: "MOVBstore", 12708 auxType: auxSymOff, 12709 argLen: 3, 12710 asm: mips.AMOVB, 12711 reg: regInfo{ 12712 inputs: []inputInfo{ 12713 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12714 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12715 }, 12716 }, 12717 }, 12718 { 12719 name: "MOVHstore", 12720 auxType: auxSymOff, 12721 argLen: 3, 12722 asm: mips.AMOVH, 12723 reg: regInfo{ 12724 inputs: []inputInfo{ 12725 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12726 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12727 }, 12728 }, 12729 }, 12730 { 12731 name: "MOVWstore", 12732 auxType: auxSymOff, 12733 argLen: 3, 12734 asm: mips.AMOVW, 12735 reg: regInfo{ 12736 inputs: []inputInfo{ 12737 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12738 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12739 }, 12740 }, 12741 }, 12742 { 12743 name: "MOVVstore", 12744 auxType: auxSymOff, 12745 argLen: 3, 12746 asm: mips.AMOVV, 12747 reg: regInfo{ 12748 inputs: []inputInfo{ 12749 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12750 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12751 }, 12752 }, 12753 }, 12754 { 12755 name: "MOVFstore", 12756 auxType: auxSymOff, 12757 argLen: 3, 12758 asm: mips.AMOVF, 12759 reg: regInfo{ 12760 inputs: []inputInfo{ 12761 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12762 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12763 }, 12764 }, 12765 }, 12766 { 12767 name: "MOVDstore", 12768 auxType: auxSymOff, 12769 argLen: 3, 12770 asm: mips.AMOVD, 12771 reg: regInfo{ 12772 inputs: []inputInfo{ 12773 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12774 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12775 }, 12776 }, 12777 }, 12778 { 12779 name: "MOVBstorezero", 12780 auxType: auxSymOff, 12781 argLen: 2, 12782 asm: mips.AMOVB, 12783 reg: regInfo{ 12784 inputs: []inputInfo{ 12785 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12786 }, 12787 }, 12788 }, 12789 { 12790 name: "MOVHstorezero", 12791 auxType: auxSymOff, 12792 argLen: 2, 12793 asm: mips.AMOVH, 12794 reg: regInfo{ 12795 inputs: []inputInfo{ 12796 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12797 }, 12798 }, 12799 }, 12800 { 12801 name: "MOVWstorezero", 12802 auxType: auxSymOff, 12803 argLen: 2, 12804 asm: mips.AMOVW, 12805 reg: regInfo{ 12806 inputs: []inputInfo{ 12807 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12808 }, 12809 }, 12810 }, 12811 { 12812 name: "MOVVstorezero", 12813 auxType: auxSymOff, 12814 argLen: 2, 12815 asm: mips.AMOVV, 12816 reg: regInfo{ 12817 inputs: []inputInfo{ 12818 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12819 }, 12820 }, 12821 }, 12822 { 12823 name: "MOVBreg", 12824 argLen: 1, 12825 asm: mips.AMOVB, 12826 reg: regInfo{ 12827 inputs: []inputInfo{ 12828 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12829 }, 12830 outputs: []outputInfo{ 12831 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12832 }, 12833 }, 12834 }, 12835 { 12836 name: "MOVBUreg", 12837 argLen: 1, 12838 asm: mips.AMOVBU, 12839 reg: regInfo{ 12840 inputs: []inputInfo{ 12841 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12842 }, 12843 outputs: []outputInfo{ 12844 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12845 }, 12846 }, 12847 }, 12848 { 12849 name: "MOVHreg", 12850 argLen: 1, 12851 asm: mips.AMOVH, 12852 reg: regInfo{ 12853 inputs: []inputInfo{ 12854 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12855 }, 12856 outputs: []outputInfo{ 12857 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12858 }, 12859 }, 12860 }, 12861 { 12862 name: "MOVHUreg", 12863 argLen: 1, 12864 asm: mips.AMOVHU, 12865 reg: regInfo{ 12866 inputs: []inputInfo{ 12867 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12868 }, 12869 outputs: []outputInfo{ 12870 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12871 }, 12872 }, 12873 }, 12874 { 12875 name: "MOVWreg", 12876 argLen: 1, 12877 asm: mips.AMOVW, 12878 reg: regInfo{ 12879 inputs: []inputInfo{ 12880 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12881 }, 12882 outputs: []outputInfo{ 12883 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12884 }, 12885 }, 12886 }, 12887 { 12888 name: "MOVWUreg", 12889 argLen: 1, 12890 asm: mips.AMOVWU, 12891 reg: regInfo{ 12892 inputs: []inputInfo{ 12893 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12894 }, 12895 outputs: []outputInfo{ 12896 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12897 }, 12898 }, 12899 }, 12900 { 12901 name: "MOVVreg", 12902 argLen: 1, 12903 asm: mips.AMOVV, 12904 reg: regInfo{ 12905 inputs: []inputInfo{ 12906 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12907 }, 12908 outputs: []outputInfo{ 12909 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12910 }, 12911 }, 12912 }, 12913 { 12914 name: "MOVVnop", 12915 argLen: 1, 12916 resultInArg0: true, 12917 reg: regInfo{ 12918 inputs: []inputInfo{ 12919 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12920 }, 12921 outputs: []outputInfo{ 12922 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12923 }, 12924 }, 12925 }, 12926 { 12927 name: "MOVWF", 12928 argLen: 1, 12929 asm: mips.AMOVWF, 12930 reg: regInfo{ 12931 inputs: []inputInfo{ 12932 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12933 }, 12934 outputs: []outputInfo{ 12935 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12936 }, 12937 }, 12938 }, 12939 { 12940 name: "MOVWD", 12941 argLen: 1, 12942 asm: mips.AMOVWD, 12943 reg: regInfo{ 12944 inputs: []inputInfo{ 12945 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12946 }, 12947 outputs: []outputInfo{ 12948 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12949 }, 12950 }, 12951 }, 12952 { 12953 name: "MOVVF", 12954 argLen: 1, 12955 asm: mips.AMOVVF, 12956 reg: regInfo{ 12957 inputs: []inputInfo{ 12958 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12959 }, 12960 outputs: []outputInfo{ 12961 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12962 }, 12963 }, 12964 }, 12965 { 12966 name: "MOVVD", 12967 argLen: 1, 12968 asm: mips.AMOVVD, 12969 reg: regInfo{ 12970 inputs: []inputInfo{ 12971 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12972 }, 12973 outputs: []outputInfo{ 12974 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12975 }, 12976 }, 12977 }, 12978 { 12979 name: "TRUNCFW", 12980 argLen: 1, 12981 asm: mips.ATRUNCFW, 12982 reg: regInfo{ 12983 inputs: []inputInfo{ 12984 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12985 }, 12986 outputs: []outputInfo{ 12987 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12988 }, 12989 }, 12990 }, 12991 { 12992 name: "TRUNCDW", 12993 argLen: 1, 12994 asm: mips.ATRUNCDW, 12995 reg: regInfo{ 12996 inputs: []inputInfo{ 12997 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12998 }, 12999 outputs: []outputInfo{ 13000 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13001 }, 13002 }, 13003 }, 13004 { 13005 name: "TRUNCFV", 13006 argLen: 1, 13007 asm: mips.ATRUNCFV, 13008 reg: regInfo{ 13009 inputs: []inputInfo{ 13010 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13011 }, 13012 outputs: []outputInfo{ 13013 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13014 }, 13015 }, 13016 }, 13017 { 13018 name: "TRUNCDV", 13019 argLen: 1, 13020 asm: mips.ATRUNCDV, 13021 reg: regInfo{ 13022 inputs: []inputInfo{ 13023 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13024 }, 13025 outputs: []outputInfo{ 13026 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13027 }, 13028 }, 13029 }, 13030 { 13031 name: "MOVFD", 13032 argLen: 1, 13033 asm: mips.AMOVFD, 13034 reg: regInfo{ 13035 inputs: []inputInfo{ 13036 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13037 }, 13038 outputs: []outputInfo{ 13039 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13040 }, 13041 }, 13042 }, 13043 { 13044 name: "MOVDF", 13045 argLen: 1, 13046 asm: mips.AMOVDF, 13047 reg: regInfo{ 13048 inputs: []inputInfo{ 13049 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13050 }, 13051 outputs: []outputInfo{ 13052 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13053 }, 13054 }, 13055 }, 13056 { 13057 name: "CALLstatic", 13058 auxType: auxSymOff, 13059 argLen: 1, 13060 clobberFlags: true, 13061 reg: regInfo{ 13062 clobbers: 2114440025016893438, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 HI LO 13063 }, 13064 }, 13065 { 13066 name: "CALLclosure", 13067 auxType: auxInt64, 13068 argLen: 3, 13069 clobberFlags: true, 13070 reg: regInfo{ 13071 inputs: []inputInfo{ 13072 {1, 4194304}, // R22 13073 {0, 67108862}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP 13074 }, 13075 clobbers: 2114440025016893438, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 HI LO 13076 }, 13077 }, 13078 { 13079 name: "CALLdefer", 13080 auxType: auxInt64, 13081 argLen: 1, 13082 clobberFlags: true, 13083 reg: regInfo{ 13084 clobbers: 2114440025016893438, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 HI LO 13085 }, 13086 }, 13087 { 13088 name: "CALLgo", 13089 auxType: auxInt64, 13090 argLen: 1, 13091 clobberFlags: true, 13092 reg: regInfo{ 13093 clobbers: 2114440025016893438, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 HI LO 13094 }, 13095 }, 13096 { 13097 name: "CALLinter", 13098 auxType: auxInt64, 13099 argLen: 2, 13100 clobberFlags: true, 13101 reg: regInfo{ 13102 inputs: []inputInfo{ 13103 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13104 }, 13105 clobbers: 2114440025016893438, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 HI LO 13106 }, 13107 }, 13108 { 13109 name: "DUFFZERO", 13110 auxType: auxInt64, 13111 argLen: 2, 13112 reg: regInfo{ 13113 inputs: []inputInfo{ 13114 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13115 }, 13116 clobbers: 2, // R1 13117 }, 13118 }, 13119 { 13120 name: "LoweredZero", 13121 auxType: auxInt64, 13122 argLen: 3, 13123 clobberFlags: true, 13124 reg: regInfo{ 13125 inputs: []inputInfo{ 13126 {0, 2}, // R1 13127 {1, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13128 }, 13129 clobbers: 2, // R1 13130 }, 13131 }, 13132 { 13133 name: "LoweredMove", 13134 auxType: auxInt64, 13135 argLen: 4, 13136 clobberFlags: true, 13137 reg: regInfo{ 13138 inputs: []inputInfo{ 13139 {0, 4}, // R2 13140 {1, 2}, // R1 13141 {2, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13142 }, 13143 clobbers: 6, // R1 R2 13144 }, 13145 }, 13146 { 13147 name: "LoweredNilCheck", 13148 argLen: 2, 13149 reg: regInfo{ 13150 inputs: []inputInfo{ 13151 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 13152 }, 13153 }, 13154 }, 13155 { 13156 name: "FPFlagTrue", 13157 argLen: 1, 13158 reg: regInfo{ 13159 outputs: []outputInfo{ 13160 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13161 }, 13162 }, 13163 }, 13164 { 13165 name: "FPFlagFalse", 13166 argLen: 1, 13167 reg: regInfo{ 13168 outputs: []outputInfo{ 13169 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13170 }, 13171 }, 13172 }, 13173 { 13174 name: "LoweredGetClosurePtr", 13175 argLen: 0, 13176 reg: regInfo{ 13177 outputs: []outputInfo{ 13178 {0, 4194304}, // R22 13179 }, 13180 }, 13181 }, 13182 { 13183 name: "MOVVconvert", 13184 argLen: 2, 13185 asm: mips.AMOVV, 13186 reg: regInfo{ 13187 inputs: []inputInfo{ 13188 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 13189 }, 13190 outputs: []outputInfo{ 13191 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13192 }, 13193 }, 13194 }, 13195 13196 { 13197 name: "ADD", 13198 argLen: 2, 13199 commutative: true, 13200 asm: ppc64.AADD, 13201 reg: regInfo{ 13202 inputs: []inputInfo{ 13203 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13204 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13205 }, 13206 outputs: []outputInfo{ 13207 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13208 }, 13209 }, 13210 }, 13211 { 13212 name: "ADDconst", 13213 auxType: auxSymOff, 13214 argLen: 1, 13215 asm: ppc64.AADD, 13216 reg: regInfo{ 13217 inputs: []inputInfo{ 13218 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13219 }, 13220 outputs: []outputInfo{ 13221 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13222 }, 13223 }, 13224 }, 13225 { 13226 name: "FADD", 13227 argLen: 2, 13228 commutative: true, 13229 asm: ppc64.AFADD, 13230 reg: regInfo{ 13231 inputs: []inputInfo{ 13232 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13233 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13234 }, 13235 outputs: []outputInfo{ 13236 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13237 }, 13238 }, 13239 }, 13240 { 13241 name: "FADDS", 13242 argLen: 2, 13243 commutative: true, 13244 asm: ppc64.AFADDS, 13245 reg: regInfo{ 13246 inputs: []inputInfo{ 13247 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13248 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13249 }, 13250 outputs: []outputInfo{ 13251 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13252 }, 13253 }, 13254 }, 13255 { 13256 name: "SUB", 13257 argLen: 2, 13258 asm: ppc64.ASUB, 13259 reg: regInfo{ 13260 inputs: []inputInfo{ 13261 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13262 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13263 }, 13264 outputs: []outputInfo{ 13265 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13266 }, 13267 }, 13268 }, 13269 { 13270 name: "FSUB", 13271 argLen: 2, 13272 asm: ppc64.AFSUB, 13273 reg: regInfo{ 13274 inputs: []inputInfo{ 13275 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13276 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13277 }, 13278 outputs: []outputInfo{ 13279 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13280 }, 13281 }, 13282 }, 13283 { 13284 name: "FSUBS", 13285 argLen: 2, 13286 asm: ppc64.AFSUBS, 13287 reg: regInfo{ 13288 inputs: []inputInfo{ 13289 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13290 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13291 }, 13292 outputs: []outputInfo{ 13293 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13294 }, 13295 }, 13296 }, 13297 { 13298 name: "MULLD", 13299 argLen: 2, 13300 commutative: true, 13301 asm: ppc64.AMULLD, 13302 reg: regInfo{ 13303 inputs: []inputInfo{ 13304 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13305 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13306 }, 13307 outputs: []outputInfo{ 13308 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13309 }, 13310 }, 13311 }, 13312 { 13313 name: "MULLW", 13314 argLen: 2, 13315 commutative: true, 13316 asm: ppc64.AMULLW, 13317 reg: regInfo{ 13318 inputs: []inputInfo{ 13319 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13320 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13321 }, 13322 outputs: []outputInfo{ 13323 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13324 }, 13325 }, 13326 }, 13327 { 13328 name: "MULHD", 13329 argLen: 2, 13330 commutative: true, 13331 asm: ppc64.AMULHD, 13332 reg: regInfo{ 13333 inputs: []inputInfo{ 13334 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13335 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13336 }, 13337 outputs: []outputInfo{ 13338 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13339 }, 13340 }, 13341 }, 13342 { 13343 name: "MULHW", 13344 argLen: 2, 13345 commutative: true, 13346 asm: ppc64.AMULHW, 13347 reg: regInfo{ 13348 inputs: []inputInfo{ 13349 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13350 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13351 }, 13352 outputs: []outputInfo{ 13353 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13354 }, 13355 }, 13356 }, 13357 { 13358 name: "MULHDU", 13359 argLen: 2, 13360 commutative: true, 13361 asm: ppc64.AMULHDU, 13362 reg: regInfo{ 13363 inputs: []inputInfo{ 13364 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13365 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13366 }, 13367 outputs: []outputInfo{ 13368 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13369 }, 13370 }, 13371 }, 13372 { 13373 name: "MULHWU", 13374 argLen: 2, 13375 commutative: true, 13376 asm: ppc64.AMULHWU, 13377 reg: regInfo{ 13378 inputs: []inputInfo{ 13379 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13380 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13381 }, 13382 outputs: []outputInfo{ 13383 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13384 }, 13385 }, 13386 }, 13387 { 13388 name: "FMUL", 13389 argLen: 2, 13390 commutative: true, 13391 asm: ppc64.AFMUL, 13392 reg: regInfo{ 13393 inputs: []inputInfo{ 13394 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13395 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13396 }, 13397 outputs: []outputInfo{ 13398 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13399 }, 13400 }, 13401 }, 13402 { 13403 name: "FMULS", 13404 argLen: 2, 13405 commutative: true, 13406 asm: ppc64.AFMULS, 13407 reg: regInfo{ 13408 inputs: []inputInfo{ 13409 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13410 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13411 }, 13412 outputs: []outputInfo{ 13413 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13414 }, 13415 }, 13416 }, 13417 { 13418 name: "SRAD", 13419 argLen: 2, 13420 asm: ppc64.ASRAD, 13421 reg: regInfo{ 13422 inputs: []inputInfo{ 13423 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13424 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13425 }, 13426 outputs: []outputInfo{ 13427 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13428 }, 13429 }, 13430 }, 13431 { 13432 name: "SRAW", 13433 argLen: 2, 13434 asm: ppc64.ASRAW, 13435 reg: regInfo{ 13436 inputs: []inputInfo{ 13437 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13438 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13439 }, 13440 outputs: []outputInfo{ 13441 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13442 }, 13443 }, 13444 }, 13445 { 13446 name: "SRD", 13447 argLen: 2, 13448 asm: ppc64.ASRD, 13449 reg: regInfo{ 13450 inputs: []inputInfo{ 13451 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13452 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13453 }, 13454 outputs: []outputInfo{ 13455 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13456 }, 13457 }, 13458 }, 13459 { 13460 name: "SRW", 13461 argLen: 2, 13462 asm: ppc64.ASRW, 13463 reg: regInfo{ 13464 inputs: []inputInfo{ 13465 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13466 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13467 }, 13468 outputs: []outputInfo{ 13469 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13470 }, 13471 }, 13472 }, 13473 { 13474 name: "SLD", 13475 argLen: 2, 13476 asm: ppc64.ASLD, 13477 reg: regInfo{ 13478 inputs: []inputInfo{ 13479 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13480 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13481 }, 13482 outputs: []outputInfo{ 13483 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13484 }, 13485 }, 13486 }, 13487 { 13488 name: "SLW", 13489 argLen: 2, 13490 asm: ppc64.ASLW, 13491 reg: regInfo{ 13492 inputs: []inputInfo{ 13493 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13494 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13495 }, 13496 outputs: []outputInfo{ 13497 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13498 }, 13499 }, 13500 }, 13501 { 13502 name: "ADDconstForCarry", 13503 auxType: auxInt16, 13504 argLen: 1, 13505 asm: ppc64.AADDC, 13506 reg: regInfo{ 13507 inputs: []inputInfo{ 13508 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13509 }, 13510 clobbers: 1073741824, // R31 13511 }, 13512 }, 13513 { 13514 name: "MaskIfNotCarry", 13515 argLen: 1, 13516 asm: ppc64.AADDME, 13517 reg: regInfo{ 13518 outputs: []outputInfo{ 13519 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13520 }, 13521 }, 13522 }, 13523 { 13524 name: "SRADconst", 13525 auxType: auxInt64, 13526 argLen: 1, 13527 asm: ppc64.ASRAD, 13528 reg: regInfo{ 13529 inputs: []inputInfo{ 13530 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13531 }, 13532 outputs: []outputInfo{ 13533 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13534 }, 13535 }, 13536 }, 13537 { 13538 name: "SRAWconst", 13539 auxType: auxInt64, 13540 argLen: 1, 13541 asm: ppc64.ASRAW, 13542 reg: regInfo{ 13543 inputs: []inputInfo{ 13544 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13545 }, 13546 outputs: []outputInfo{ 13547 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13548 }, 13549 }, 13550 }, 13551 { 13552 name: "SRDconst", 13553 auxType: auxInt64, 13554 argLen: 1, 13555 asm: ppc64.ASRD, 13556 reg: regInfo{ 13557 inputs: []inputInfo{ 13558 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13559 }, 13560 outputs: []outputInfo{ 13561 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13562 }, 13563 }, 13564 }, 13565 { 13566 name: "SRWconst", 13567 auxType: auxInt64, 13568 argLen: 1, 13569 asm: ppc64.ASRW, 13570 reg: regInfo{ 13571 inputs: []inputInfo{ 13572 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13573 }, 13574 outputs: []outputInfo{ 13575 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13576 }, 13577 }, 13578 }, 13579 { 13580 name: "SLDconst", 13581 auxType: auxInt64, 13582 argLen: 1, 13583 asm: ppc64.ASLD, 13584 reg: regInfo{ 13585 inputs: []inputInfo{ 13586 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13587 }, 13588 outputs: []outputInfo{ 13589 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13590 }, 13591 }, 13592 }, 13593 { 13594 name: "SLWconst", 13595 auxType: auxInt64, 13596 argLen: 1, 13597 asm: ppc64.ASLW, 13598 reg: regInfo{ 13599 inputs: []inputInfo{ 13600 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13601 }, 13602 outputs: []outputInfo{ 13603 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13604 }, 13605 }, 13606 }, 13607 { 13608 name: "FDIV", 13609 argLen: 2, 13610 asm: ppc64.AFDIV, 13611 reg: regInfo{ 13612 inputs: []inputInfo{ 13613 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13614 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13615 }, 13616 outputs: []outputInfo{ 13617 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13618 }, 13619 }, 13620 }, 13621 { 13622 name: "FDIVS", 13623 argLen: 2, 13624 asm: ppc64.AFDIVS, 13625 reg: regInfo{ 13626 inputs: []inputInfo{ 13627 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13628 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13629 }, 13630 outputs: []outputInfo{ 13631 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13632 }, 13633 }, 13634 }, 13635 { 13636 name: "DIVD", 13637 argLen: 2, 13638 asm: ppc64.ADIVD, 13639 reg: regInfo{ 13640 inputs: []inputInfo{ 13641 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13642 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13643 }, 13644 outputs: []outputInfo{ 13645 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13646 }, 13647 }, 13648 }, 13649 { 13650 name: "DIVW", 13651 argLen: 2, 13652 asm: ppc64.ADIVW, 13653 reg: regInfo{ 13654 inputs: []inputInfo{ 13655 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13656 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13657 }, 13658 outputs: []outputInfo{ 13659 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13660 }, 13661 }, 13662 }, 13663 { 13664 name: "DIVDU", 13665 argLen: 2, 13666 asm: ppc64.ADIVDU, 13667 reg: regInfo{ 13668 inputs: []inputInfo{ 13669 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13670 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13671 }, 13672 outputs: []outputInfo{ 13673 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13674 }, 13675 }, 13676 }, 13677 { 13678 name: "DIVWU", 13679 argLen: 2, 13680 asm: ppc64.ADIVWU, 13681 reg: regInfo{ 13682 inputs: []inputInfo{ 13683 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13684 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13685 }, 13686 outputs: []outputInfo{ 13687 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13688 }, 13689 }, 13690 }, 13691 { 13692 name: "FCTIDZ", 13693 argLen: 1, 13694 asm: ppc64.AFCTIDZ, 13695 reg: regInfo{ 13696 inputs: []inputInfo{ 13697 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13698 }, 13699 outputs: []outputInfo{ 13700 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13701 }, 13702 }, 13703 }, 13704 { 13705 name: "FCTIWZ", 13706 argLen: 1, 13707 asm: ppc64.AFCTIWZ, 13708 reg: regInfo{ 13709 inputs: []inputInfo{ 13710 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13711 }, 13712 outputs: []outputInfo{ 13713 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13714 }, 13715 }, 13716 }, 13717 { 13718 name: "FCFID", 13719 argLen: 1, 13720 asm: ppc64.AFCFID, 13721 reg: regInfo{ 13722 inputs: []inputInfo{ 13723 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13724 }, 13725 outputs: []outputInfo{ 13726 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13727 }, 13728 }, 13729 }, 13730 { 13731 name: "FRSP", 13732 argLen: 1, 13733 asm: ppc64.AFRSP, 13734 reg: regInfo{ 13735 inputs: []inputInfo{ 13736 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13737 }, 13738 outputs: []outputInfo{ 13739 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13740 }, 13741 }, 13742 }, 13743 { 13744 name: "Xf2i64", 13745 argLen: 1, 13746 reg: regInfo{ 13747 inputs: []inputInfo{ 13748 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13749 }, 13750 outputs: []outputInfo{ 13751 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13752 }, 13753 }, 13754 }, 13755 { 13756 name: "Xi2f64", 13757 argLen: 1, 13758 reg: regInfo{ 13759 inputs: []inputInfo{ 13760 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13761 }, 13762 outputs: []outputInfo{ 13763 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13764 }, 13765 }, 13766 }, 13767 { 13768 name: "AND", 13769 argLen: 2, 13770 commutative: true, 13771 asm: ppc64.AAND, 13772 reg: regInfo{ 13773 inputs: []inputInfo{ 13774 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13775 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13776 }, 13777 outputs: []outputInfo{ 13778 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13779 }, 13780 }, 13781 }, 13782 { 13783 name: "ANDN", 13784 argLen: 2, 13785 asm: ppc64.AANDN, 13786 reg: regInfo{ 13787 inputs: []inputInfo{ 13788 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13789 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13790 }, 13791 outputs: []outputInfo{ 13792 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13793 }, 13794 }, 13795 }, 13796 { 13797 name: "OR", 13798 argLen: 2, 13799 commutative: true, 13800 asm: ppc64.AOR, 13801 reg: regInfo{ 13802 inputs: []inputInfo{ 13803 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13804 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13805 }, 13806 outputs: []outputInfo{ 13807 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13808 }, 13809 }, 13810 }, 13811 { 13812 name: "ORN", 13813 argLen: 2, 13814 asm: ppc64.AORN, 13815 reg: regInfo{ 13816 inputs: []inputInfo{ 13817 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13818 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13819 }, 13820 outputs: []outputInfo{ 13821 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13822 }, 13823 }, 13824 }, 13825 { 13826 name: "XOR", 13827 argLen: 2, 13828 commutative: true, 13829 asm: ppc64.AXOR, 13830 reg: regInfo{ 13831 inputs: []inputInfo{ 13832 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13833 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13834 }, 13835 outputs: []outputInfo{ 13836 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13837 }, 13838 }, 13839 }, 13840 { 13841 name: "EQV", 13842 argLen: 2, 13843 commutative: true, 13844 asm: ppc64.AEQV, 13845 reg: regInfo{ 13846 inputs: []inputInfo{ 13847 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13848 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13849 }, 13850 outputs: []outputInfo{ 13851 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13852 }, 13853 }, 13854 }, 13855 { 13856 name: "NEG", 13857 argLen: 1, 13858 asm: ppc64.ANEG, 13859 reg: regInfo{ 13860 inputs: []inputInfo{ 13861 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13862 }, 13863 outputs: []outputInfo{ 13864 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13865 }, 13866 }, 13867 }, 13868 { 13869 name: "FNEG", 13870 argLen: 1, 13871 asm: ppc64.AFNEG, 13872 reg: regInfo{ 13873 inputs: []inputInfo{ 13874 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13875 }, 13876 outputs: []outputInfo{ 13877 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13878 }, 13879 }, 13880 }, 13881 { 13882 name: "FSQRT", 13883 argLen: 1, 13884 asm: ppc64.AFSQRT, 13885 reg: regInfo{ 13886 inputs: []inputInfo{ 13887 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13888 }, 13889 outputs: []outputInfo{ 13890 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13891 }, 13892 }, 13893 }, 13894 { 13895 name: "FSQRTS", 13896 argLen: 1, 13897 asm: ppc64.AFSQRTS, 13898 reg: regInfo{ 13899 inputs: []inputInfo{ 13900 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13901 }, 13902 outputs: []outputInfo{ 13903 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13904 }, 13905 }, 13906 }, 13907 { 13908 name: "ORconst", 13909 auxType: auxInt64, 13910 argLen: 1, 13911 asm: ppc64.AOR, 13912 reg: regInfo{ 13913 inputs: []inputInfo{ 13914 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13915 }, 13916 outputs: []outputInfo{ 13917 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13918 }, 13919 }, 13920 }, 13921 { 13922 name: "XORconst", 13923 auxType: auxInt64, 13924 argLen: 1, 13925 asm: ppc64.AXOR, 13926 reg: regInfo{ 13927 inputs: []inputInfo{ 13928 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13929 }, 13930 outputs: []outputInfo{ 13931 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13932 }, 13933 }, 13934 }, 13935 { 13936 name: "ANDconst", 13937 auxType: auxInt64, 13938 argLen: 1, 13939 clobberFlags: true, 13940 asm: ppc64.AANDCC, 13941 reg: regInfo{ 13942 inputs: []inputInfo{ 13943 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13944 }, 13945 outputs: []outputInfo{ 13946 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13947 }, 13948 }, 13949 }, 13950 { 13951 name: "MOVBreg", 13952 argLen: 1, 13953 asm: ppc64.AMOVB, 13954 reg: regInfo{ 13955 inputs: []inputInfo{ 13956 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13957 }, 13958 outputs: []outputInfo{ 13959 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13960 }, 13961 }, 13962 }, 13963 { 13964 name: "MOVBZreg", 13965 argLen: 1, 13966 asm: ppc64.AMOVBZ, 13967 reg: regInfo{ 13968 inputs: []inputInfo{ 13969 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13970 }, 13971 outputs: []outputInfo{ 13972 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13973 }, 13974 }, 13975 }, 13976 { 13977 name: "MOVHreg", 13978 argLen: 1, 13979 asm: ppc64.AMOVH, 13980 reg: regInfo{ 13981 inputs: []inputInfo{ 13982 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13983 }, 13984 outputs: []outputInfo{ 13985 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13986 }, 13987 }, 13988 }, 13989 { 13990 name: "MOVHZreg", 13991 argLen: 1, 13992 asm: ppc64.AMOVHZ, 13993 reg: regInfo{ 13994 inputs: []inputInfo{ 13995 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13996 }, 13997 outputs: []outputInfo{ 13998 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13999 }, 14000 }, 14001 }, 14002 { 14003 name: "MOVWreg", 14004 argLen: 1, 14005 asm: ppc64.AMOVW, 14006 reg: regInfo{ 14007 inputs: []inputInfo{ 14008 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14009 }, 14010 outputs: []outputInfo{ 14011 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14012 }, 14013 }, 14014 }, 14015 { 14016 name: "MOVWZreg", 14017 argLen: 1, 14018 asm: ppc64.AMOVWZ, 14019 reg: regInfo{ 14020 inputs: []inputInfo{ 14021 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14022 }, 14023 outputs: []outputInfo{ 14024 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14025 }, 14026 }, 14027 }, 14028 { 14029 name: "MOVBload", 14030 auxType: auxSymOff, 14031 argLen: 2, 14032 asm: ppc64.AMOVB, 14033 reg: regInfo{ 14034 inputs: []inputInfo{ 14035 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14036 }, 14037 outputs: []outputInfo{ 14038 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14039 }, 14040 }, 14041 }, 14042 { 14043 name: "MOVBZload", 14044 auxType: auxSymOff, 14045 argLen: 2, 14046 asm: ppc64.AMOVBZ, 14047 reg: regInfo{ 14048 inputs: []inputInfo{ 14049 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14050 }, 14051 outputs: []outputInfo{ 14052 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14053 }, 14054 }, 14055 }, 14056 { 14057 name: "MOVHload", 14058 auxType: auxSymOff, 14059 argLen: 2, 14060 asm: ppc64.AMOVH, 14061 reg: regInfo{ 14062 inputs: []inputInfo{ 14063 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14064 }, 14065 outputs: []outputInfo{ 14066 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14067 }, 14068 }, 14069 }, 14070 { 14071 name: "MOVHZload", 14072 auxType: auxSymOff, 14073 argLen: 2, 14074 asm: ppc64.AMOVHZ, 14075 reg: regInfo{ 14076 inputs: []inputInfo{ 14077 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14078 }, 14079 outputs: []outputInfo{ 14080 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14081 }, 14082 }, 14083 }, 14084 { 14085 name: "MOVWload", 14086 auxType: auxSymOff, 14087 argLen: 2, 14088 asm: ppc64.AMOVW, 14089 reg: regInfo{ 14090 inputs: []inputInfo{ 14091 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14092 }, 14093 outputs: []outputInfo{ 14094 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14095 }, 14096 }, 14097 }, 14098 { 14099 name: "MOVWZload", 14100 auxType: auxSymOff, 14101 argLen: 2, 14102 asm: ppc64.AMOVWZ, 14103 reg: regInfo{ 14104 inputs: []inputInfo{ 14105 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14106 }, 14107 outputs: []outputInfo{ 14108 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14109 }, 14110 }, 14111 }, 14112 { 14113 name: "MOVDload", 14114 auxType: auxSymOff, 14115 argLen: 2, 14116 asm: ppc64.AMOVD, 14117 reg: regInfo{ 14118 inputs: []inputInfo{ 14119 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14120 }, 14121 outputs: []outputInfo{ 14122 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14123 }, 14124 }, 14125 }, 14126 { 14127 name: "FMOVDload", 14128 auxType: auxSymOff, 14129 argLen: 2, 14130 asm: ppc64.AFMOVD, 14131 reg: regInfo{ 14132 inputs: []inputInfo{ 14133 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14134 }, 14135 outputs: []outputInfo{ 14136 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14137 }, 14138 }, 14139 }, 14140 { 14141 name: "FMOVSload", 14142 auxType: auxSymOff, 14143 argLen: 2, 14144 asm: ppc64.AFMOVS, 14145 reg: regInfo{ 14146 inputs: []inputInfo{ 14147 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14148 }, 14149 outputs: []outputInfo{ 14150 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14151 }, 14152 }, 14153 }, 14154 { 14155 name: "MOVBstore", 14156 auxType: auxSymOff, 14157 argLen: 3, 14158 asm: ppc64.AMOVB, 14159 reg: regInfo{ 14160 inputs: []inputInfo{ 14161 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14162 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14163 }, 14164 }, 14165 }, 14166 { 14167 name: "MOVHstore", 14168 auxType: auxSymOff, 14169 argLen: 3, 14170 asm: ppc64.AMOVH, 14171 reg: regInfo{ 14172 inputs: []inputInfo{ 14173 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14174 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14175 }, 14176 }, 14177 }, 14178 { 14179 name: "MOVWstore", 14180 auxType: auxSymOff, 14181 argLen: 3, 14182 asm: ppc64.AMOVW, 14183 reg: regInfo{ 14184 inputs: []inputInfo{ 14185 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14186 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14187 }, 14188 }, 14189 }, 14190 { 14191 name: "MOVDstore", 14192 auxType: auxSymOff, 14193 argLen: 3, 14194 asm: ppc64.AMOVD, 14195 reg: regInfo{ 14196 inputs: []inputInfo{ 14197 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14198 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14199 }, 14200 }, 14201 }, 14202 { 14203 name: "FMOVDstore", 14204 auxType: auxSymOff, 14205 argLen: 3, 14206 asm: ppc64.AFMOVD, 14207 reg: regInfo{ 14208 inputs: []inputInfo{ 14209 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14210 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14211 }, 14212 }, 14213 }, 14214 { 14215 name: "FMOVSstore", 14216 auxType: auxSymOff, 14217 argLen: 3, 14218 asm: ppc64.AFMOVS, 14219 reg: regInfo{ 14220 inputs: []inputInfo{ 14221 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14222 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14223 }, 14224 }, 14225 }, 14226 { 14227 name: "MOVBstorezero", 14228 auxType: auxSymOff, 14229 argLen: 2, 14230 asm: ppc64.AMOVB, 14231 reg: regInfo{ 14232 inputs: []inputInfo{ 14233 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14234 }, 14235 }, 14236 }, 14237 { 14238 name: "MOVHstorezero", 14239 auxType: auxSymOff, 14240 argLen: 2, 14241 asm: ppc64.AMOVH, 14242 reg: regInfo{ 14243 inputs: []inputInfo{ 14244 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14245 }, 14246 }, 14247 }, 14248 { 14249 name: "MOVWstorezero", 14250 auxType: auxSymOff, 14251 argLen: 2, 14252 asm: ppc64.AMOVW, 14253 reg: regInfo{ 14254 inputs: []inputInfo{ 14255 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14256 }, 14257 }, 14258 }, 14259 { 14260 name: "MOVDstorezero", 14261 auxType: auxSymOff, 14262 argLen: 2, 14263 asm: ppc64.AMOVD, 14264 reg: regInfo{ 14265 inputs: []inputInfo{ 14266 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14267 }, 14268 }, 14269 }, 14270 { 14271 name: "MOVDaddr", 14272 auxType: auxSymOff, 14273 argLen: 1, 14274 rematerializeable: true, 14275 asm: ppc64.AMOVD, 14276 reg: regInfo{ 14277 inputs: []inputInfo{ 14278 {0, 3}, // SP SB 14279 }, 14280 outputs: []outputInfo{ 14281 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14282 }, 14283 }, 14284 }, 14285 { 14286 name: "MOVDconst", 14287 auxType: auxInt64, 14288 argLen: 0, 14289 rematerializeable: true, 14290 asm: ppc64.AMOVD, 14291 reg: regInfo{ 14292 outputs: []outputInfo{ 14293 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14294 }, 14295 }, 14296 }, 14297 { 14298 name: "MOVWconst", 14299 auxType: auxInt32, 14300 argLen: 0, 14301 rematerializeable: true, 14302 asm: ppc64.AMOVW, 14303 reg: regInfo{ 14304 outputs: []outputInfo{ 14305 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14306 }, 14307 }, 14308 }, 14309 { 14310 name: "FMOVDconst", 14311 auxType: auxFloat64, 14312 argLen: 0, 14313 rematerializeable: true, 14314 asm: ppc64.AFMOVD, 14315 reg: regInfo{ 14316 outputs: []outputInfo{ 14317 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14318 }, 14319 }, 14320 }, 14321 { 14322 name: "FMOVSconst", 14323 auxType: auxFloat32, 14324 argLen: 0, 14325 rematerializeable: true, 14326 asm: ppc64.AFMOVS, 14327 reg: regInfo{ 14328 outputs: []outputInfo{ 14329 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14330 }, 14331 }, 14332 }, 14333 { 14334 name: "FCMPU", 14335 argLen: 2, 14336 asm: ppc64.AFCMPU, 14337 reg: regInfo{ 14338 inputs: []inputInfo{ 14339 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14340 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14341 }, 14342 }, 14343 }, 14344 { 14345 name: "CMP", 14346 argLen: 2, 14347 asm: ppc64.ACMP, 14348 reg: regInfo{ 14349 inputs: []inputInfo{ 14350 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14351 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14352 }, 14353 }, 14354 }, 14355 { 14356 name: "CMPU", 14357 argLen: 2, 14358 asm: ppc64.ACMPU, 14359 reg: regInfo{ 14360 inputs: []inputInfo{ 14361 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14362 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14363 }, 14364 }, 14365 }, 14366 { 14367 name: "CMPW", 14368 argLen: 2, 14369 asm: ppc64.ACMPW, 14370 reg: regInfo{ 14371 inputs: []inputInfo{ 14372 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14373 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14374 }, 14375 }, 14376 }, 14377 { 14378 name: "CMPWU", 14379 argLen: 2, 14380 asm: ppc64.ACMPWU, 14381 reg: regInfo{ 14382 inputs: []inputInfo{ 14383 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14384 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14385 }, 14386 }, 14387 }, 14388 { 14389 name: "CMPconst", 14390 auxType: auxInt64, 14391 argLen: 1, 14392 asm: ppc64.ACMP, 14393 reg: regInfo{ 14394 inputs: []inputInfo{ 14395 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14396 }, 14397 }, 14398 }, 14399 { 14400 name: "CMPUconst", 14401 auxType: auxInt64, 14402 argLen: 1, 14403 asm: ppc64.ACMPU, 14404 reg: regInfo{ 14405 inputs: []inputInfo{ 14406 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14407 }, 14408 }, 14409 }, 14410 { 14411 name: "CMPWconst", 14412 auxType: auxInt32, 14413 argLen: 1, 14414 asm: ppc64.ACMPW, 14415 reg: regInfo{ 14416 inputs: []inputInfo{ 14417 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14418 }, 14419 }, 14420 }, 14421 { 14422 name: "CMPWUconst", 14423 auxType: auxInt32, 14424 argLen: 1, 14425 asm: ppc64.ACMPWU, 14426 reg: regInfo{ 14427 inputs: []inputInfo{ 14428 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14429 }, 14430 }, 14431 }, 14432 { 14433 name: "Equal", 14434 argLen: 1, 14435 reg: regInfo{ 14436 outputs: []outputInfo{ 14437 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14438 }, 14439 }, 14440 }, 14441 { 14442 name: "NotEqual", 14443 argLen: 1, 14444 reg: regInfo{ 14445 outputs: []outputInfo{ 14446 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14447 }, 14448 }, 14449 }, 14450 { 14451 name: "LessThan", 14452 argLen: 1, 14453 reg: regInfo{ 14454 outputs: []outputInfo{ 14455 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14456 }, 14457 }, 14458 }, 14459 { 14460 name: "FLessThan", 14461 argLen: 1, 14462 reg: regInfo{ 14463 outputs: []outputInfo{ 14464 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14465 }, 14466 }, 14467 }, 14468 { 14469 name: "LessEqual", 14470 argLen: 1, 14471 reg: regInfo{ 14472 outputs: []outputInfo{ 14473 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14474 }, 14475 }, 14476 }, 14477 { 14478 name: "FLessEqual", 14479 argLen: 1, 14480 reg: regInfo{ 14481 outputs: []outputInfo{ 14482 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14483 }, 14484 }, 14485 }, 14486 { 14487 name: "GreaterThan", 14488 argLen: 1, 14489 reg: regInfo{ 14490 outputs: []outputInfo{ 14491 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14492 }, 14493 }, 14494 }, 14495 { 14496 name: "FGreaterThan", 14497 argLen: 1, 14498 reg: regInfo{ 14499 outputs: []outputInfo{ 14500 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14501 }, 14502 }, 14503 }, 14504 { 14505 name: "GreaterEqual", 14506 argLen: 1, 14507 reg: regInfo{ 14508 outputs: []outputInfo{ 14509 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14510 }, 14511 }, 14512 }, 14513 { 14514 name: "FGreaterEqual", 14515 argLen: 1, 14516 reg: regInfo{ 14517 outputs: []outputInfo{ 14518 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14519 }, 14520 }, 14521 }, 14522 { 14523 name: "LoweredGetClosurePtr", 14524 argLen: 0, 14525 reg: regInfo{ 14526 outputs: []outputInfo{ 14527 {0, 1024}, // R11 14528 }, 14529 }, 14530 }, 14531 { 14532 name: "LoweredNilCheck", 14533 argLen: 2, 14534 clobberFlags: true, 14535 reg: regInfo{ 14536 inputs: []inputInfo{ 14537 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14538 }, 14539 clobbers: 1073741824, // R31 14540 }, 14541 }, 14542 { 14543 name: "MOVDconvert", 14544 argLen: 2, 14545 asm: ppc64.AMOVD, 14546 reg: regInfo{ 14547 inputs: []inputInfo{ 14548 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14549 }, 14550 outputs: []outputInfo{ 14551 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14552 }, 14553 }, 14554 }, 14555 { 14556 name: "CALLstatic", 14557 auxType: auxSymOff, 14558 argLen: 1, 14559 clobberFlags: true, 14560 reg: regInfo{ 14561 clobbers: 288230372930482172, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14562 }, 14563 }, 14564 { 14565 name: "CALLclosure", 14566 auxType: auxInt64, 14567 argLen: 3, 14568 clobberFlags: true, 14569 reg: regInfo{ 14570 inputs: []inputInfo{ 14571 {1, 1024}, // R11 14572 {0, 536866813}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14573 }, 14574 clobbers: 288230372930482172, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14575 }, 14576 }, 14577 { 14578 name: "CALLdefer", 14579 auxType: auxInt64, 14580 argLen: 1, 14581 clobberFlags: true, 14582 reg: regInfo{ 14583 clobbers: 288230372930482172, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14584 }, 14585 }, 14586 { 14587 name: "CALLgo", 14588 auxType: auxInt64, 14589 argLen: 1, 14590 clobberFlags: true, 14591 reg: regInfo{ 14592 clobbers: 288230372930482172, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14593 }, 14594 }, 14595 { 14596 name: "CALLinter", 14597 auxType: auxInt64, 14598 argLen: 2, 14599 clobberFlags: true, 14600 reg: regInfo{ 14601 inputs: []inputInfo{ 14602 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14603 }, 14604 clobbers: 288230372930482172, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14605 }, 14606 }, 14607 { 14608 name: "LoweredZero", 14609 auxType: auxInt64, 14610 argLen: 3, 14611 clobberFlags: true, 14612 reg: regInfo{ 14613 inputs: []inputInfo{ 14614 {0, 4}, // R3 14615 {1, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14616 }, 14617 clobbers: 4, // R3 14618 }, 14619 }, 14620 { 14621 name: "LoweredMove", 14622 auxType: auxInt64, 14623 argLen: 4, 14624 clobberFlags: true, 14625 reg: regInfo{ 14626 inputs: []inputInfo{ 14627 {0, 4}, // R3 14628 {1, 8}, // R4 14629 {2, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14630 }, 14631 clobbers: 12, // R3 R4 14632 }, 14633 }, 14634 { 14635 name: "InvertFlags", 14636 argLen: 1, 14637 reg: regInfo{}, 14638 }, 14639 { 14640 name: "FlagEQ", 14641 argLen: 0, 14642 reg: regInfo{}, 14643 }, 14644 { 14645 name: "FlagLT", 14646 argLen: 0, 14647 reg: regInfo{}, 14648 }, 14649 { 14650 name: "FlagGT", 14651 argLen: 0, 14652 reg: regInfo{}, 14653 }, 14654 14655 { 14656 name: "Add8", 14657 argLen: 2, 14658 commutative: true, 14659 generic: true, 14660 }, 14661 { 14662 name: "Add16", 14663 argLen: 2, 14664 commutative: true, 14665 generic: true, 14666 }, 14667 { 14668 name: "Add32", 14669 argLen: 2, 14670 commutative: true, 14671 generic: true, 14672 }, 14673 { 14674 name: "Add64", 14675 argLen: 2, 14676 commutative: true, 14677 generic: true, 14678 }, 14679 { 14680 name: "AddPtr", 14681 argLen: 2, 14682 generic: true, 14683 }, 14684 { 14685 name: "Add32F", 14686 argLen: 2, 14687 generic: true, 14688 }, 14689 { 14690 name: "Add64F", 14691 argLen: 2, 14692 generic: true, 14693 }, 14694 { 14695 name: "Sub8", 14696 argLen: 2, 14697 generic: true, 14698 }, 14699 { 14700 name: "Sub16", 14701 argLen: 2, 14702 generic: true, 14703 }, 14704 { 14705 name: "Sub32", 14706 argLen: 2, 14707 generic: true, 14708 }, 14709 { 14710 name: "Sub64", 14711 argLen: 2, 14712 generic: true, 14713 }, 14714 { 14715 name: "SubPtr", 14716 argLen: 2, 14717 generic: true, 14718 }, 14719 { 14720 name: "Sub32F", 14721 argLen: 2, 14722 generic: true, 14723 }, 14724 { 14725 name: "Sub64F", 14726 argLen: 2, 14727 generic: true, 14728 }, 14729 { 14730 name: "Mul8", 14731 argLen: 2, 14732 commutative: true, 14733 generic: true, 14734 }, 14735 { 14736 name: "Mul16", 14737 argLen: 2, 14738 commutative: true, 14739 generic: true, 14740 }, 14741 { 14742 name: "Mul32", 14743 argLen: 2, 14744 commutative: true, 14745 generic: true, 14746 }, 14747 { 14748 name: "Mul64", 14749 argLen: 2, 14750 commutative: true, 14751 generic: true, 14752 }, 14753 { 14754 name: "Mul32F", 14755 argLen: 2, 14756 generic: true, 14757 }, 14758 { 14759 name: "Mul64F", 14760 argLen: 2, 14761 generic: true, 14762 }, 14763 { 14764 name: "Div32F", 14765 argLen: 2, 14766 generic: true, 14767 }, 14768 { 14769 name: "Div64F", 14770 argLen: 2, 14771 generic: true, 14772 }, 14773 { 14774 name: "Hmul8", 14775 argLen: 2, 14776 generic: true, 14777 }, 14778 { 14779 name: "Hmul8u", 14780 argLen: 2, 14781 generic: true, 14782 }, 14783 { 14784 name: "Hmul16", 14785 argLen: 2, 14786 generic: true, 14787 }, 14788 { 14789 name: "Hmul16u", 14790 argLen: 2, 14791 generic: true, 14792 }, 14793 { 14794 name: "Hmul32", 14795 argLen: 2, 14796 generic: true, 14797 }, 14798 { 14799 name: "Hmul32u", 14800 argLen: 2, 14801 generic: true, 14802 }, 14803 { 14804 name: "Hmul64", 14805 argLen: 2, 14806 generic: true, 14807 }, 14808 { 14809 name: "Hmul64u", 14810 argLen: 2, 14811 generic: true, 14812 }, 14813 { 14814 name: "Avg64u", 14815 argLen: 2, 14816 generic: true, 14817 }, 14818 { 14819 name: "Div8", 14820 argLen: 2, 14821 generic: true, 14822 }, 14823 { 14824 name: "Div8u", 14825 argLen: 2, 14826 generic: true, 14827 }, 14828 { 14829 name: "Div16", 14830 argLen: 2, 14831 generic: true, 14832 }, 14833 { 14834 name: "Div16u", 14835 argLen: 2, 14836 generic: true, 14837 }, 14838 { 14839 name: "Div32", 14840 argLen: 2, 14841 generic: true, 14842 }, 14843 { 14844 name: "Div32u", 14845 argLen: 2, 14846 generic: true, 14847 }, 14848 { 14849 name: "Div64", 14850 argLen: 2, 14851 generic: true, 14852 }, 14853 { 14854 name: "Div64u", 14855 argLen: 2, 14856 generic: true, 14857 }, 14858 { 14859 name: "Mod8", 14860 argLen: 2, 14861 generic: true, 14862 }, 14863 { 14864 name: "Mod8u", 14865 argLen: 2, 14866 generic: true, 14867 }, 14868 { 14869 name: "Mod16", 14870 argLen: 2, 14871 generic: true, 14872 }, 14873 { 14874 name: "Mod16u", 14875 argLen: 2, 14876 generic: true, 14877 }, 14878 { 14879 name: "Mod32", 14880 argLen: 2, 14881 generic: true, 14882 }, 14883 { 14884 name: "Mod32u", 14885 argLen: 2, 14886 generic: true, 14887 }, 14888 { 14889 name: "Mod64", 14890 argLen: 2, 14891 generic: true, 14892 }, 14893 { 14894 name: "Mod64u", 14895 argLen: 2, 14896 generic: true, 14897 }, 14898 { 14899 name: "And8", 14900 argLen: 2, 14901 commutative: true, 14902 generic: true, 14903 }, 14904 { 14905 name: "And16", 14906 argLen: 2, 14907 commutative: true, 14908 generic: true, 14909 }, 14910 { 14911 name: "And32", 14912 argLen: 2, 14913 commutative: true, 14914 generic: true, 14915 }, 14916 { 14917 name: "And64", 14918 argLen: 2, 14919 commutative: true, 14920 generic: true, 14921 }, 14922 { 14923 name: "Or8", 14924 argLen: 2, 14925 commutative: true, 14926 generic: true, 14927 }, 14928 { 14929 name: "Or16", 14930 argLen: 2, 14931 commutative: true, 14932 generic: true, 14933 }, 14934 { 14935 name: "Or32", 14936 argLen: 2, 14937 commutative: true, 14938 generic: true, 14939 }, 14940 { 14941 name: "Or64", 14942 argLen: 2, 14943 commutative: true, 14944 generic: true, 14945 }, 14946 { 14947 name: "Xor8", 14948 argLen: 2, 14949 commutative: true, 14950 generic: true, 14951 }, 14952 { 14953 name: "Xor16", 14954 argLen: 2, 14955 commutative: true, 14956 generic: true, 14957 }, 14958 { 14959 name: "Xor32", 14960 argLen: 2, 14961 commutative: true, 14962 generic: true, 14963 }, 14964 { 14965 name: "Xor64", 14966 argLen: 2, 14967 commutative: true, 14968 generic: true, 14969 }, 14970 { 14971 name: "Lsh8x8", 14972 argLen: 2, 14973 generic: true, 14974 }, 14975 { 14976 name: "Lsh8x16", 14977 argLen: 2, 14978 generic: true, 14979 }, 14980 { 14981 name: "Lsh8x32", 14982 argLen: 2, 14983 generic: true, 14984 }, 14985 { 14986 name: "Lsh8x64", 14987 argLen: 2, 14988 generic: true, 14989 }, 14990 { 14991 name: "Lsh16x8", 14992 argLen: 2, 14993 generic: true, 14994 }, 14995 { 14996 name: "Lsh16x16", 14997 argLen: 2, 14998 generic: true, 14999 }, 15000 { 15001 name: "Lsh16x32", 15002 argLen: 2, 15003 generic: true, 15004 }, 15005 { 15006 name: "Lsh16x64", 15007 argLen: 2, 15008 generic: true, 15009 }, 15010 { 15011 name: "Lsh32x8", 15012 argLen: 2, 15013 generic: true, 15014 }, 15015 { 15016 name: "Lsh32x16", 15017 argLen: 2, 15018 generic: true, 15019 }, 15020 { 15021 name: "Lsh32x32", 15022 argLen: 2, 15023 generic: true, 15024 }, 15025 { 15026 name: "Lsh32x64", 15027 argLen: 2, 15028 generic: true, 15029 }, 15030 { 15031 name: "Lsh64x8", 15032 argLen: 2, 15033 generic: true, 15034 }, 15035 { 15036 name: "Lsh64x16", 15037 argLen: 2, 15038 generic: true, 15039 }, 15040 { 15041 name: "Lsh64x32", 15042 argLen: 2, 15043 generic: true, 15044 }, 15045 { 15046 name: "Lsh64x64", 15047 argLen: 2, 15048 generic: true, 15049 }, 15050 { 15051 name: "Rsh8x8", 15052 argLen: 2, 15053 generic: true, 15054 }, 15055 { 15056 name: "Rsh8x16", 15057 argLen: 2, 15058 generic: true, 15059 }, 15060 { 15061 name: "Rsh8x32", 15062 argLen: 2, 15063 generic: true, 15064 }, 15065 { 15066 name: "Rsh8x64", 15067 argLen: 2, 15068 generic: true, 15069 }, 15070 { 15071 name: "Rsh16x8", 15072 argLen: 2, 15073 generic: true, 15074 }, 15075 { 15076 name: "Rsh16x16", 15077 argLen: 2, 15078 generic: true, 15079 }, 15080 { 15081 name: "Rsh16x32", 15082 argLen: 2, 15083 generic: true, 15084 }, 15085 { 15086 name: "Rsh16x64", 15087 argLen: 2, 15088 generic: true, 15089 }, 15090 { 15091 name: "Rsh32x8", 15092 argLen: 2, 15093 generic: true, 15094 }, 15095 { 15096 name: "Rsh32x16", 15097 argLen: 2, 15098 generic: true, 15099 }, 15100 { 15101 name: "Rsh32x32", 15102 argLen: 2, 15103 generic: true, 15104 }, 15105 { 15106 name: "Rsh32x64", 15107 argLen: 2, 15108 generic: true, 15109 }, 15110 { 15111 name: "Rsh64x8", 15112 argLen: 2, 15113 generic: true, 15114 }, 15115 { 15116 name: "Rsh64x16", 15117 argLen: 2, 15118 generic: true, 15119 }, 15120 { 15121 name: "Rsh64x32", 15122 argLen: 2, 15123 generic: true, 15124 }, 15125 { 15126 name: "Rsh64x64", 15127 argLen: 2, 15128 generic: true, 15129 }, 15130 { 15131 name: "Rsh8Ux8", 15132 argLen: 2, 15133 generic: true, 15134 }, 15135 { 15136 name: "Rsh8Ux16", 15137 argLen: 2, 15138 generic: true, 15139 }, 15140 { 15141 name: "Rsh8Ux32", 15142 argLen: 2, 15143 generic: true, 15144 }, 15145 { 15146 name: "Rsh8Ux64", 15147 argLen: 2, 15148 generic: true, 15149 }, 15150 { 15151 name: "Rsh16Ux8", 15152 argLen: 2, 15153 generic: true, 15154 }, 15155 { 15156 name: "Rsh16Ux16", 15157 argLen: 2, 15158 generic: true, 15159 }, 15160 { 15161 name: "Rsh16Ux32", 15162 argLen: 2, 15163 generic: true, 15164 }, 15165 { 15166 name: "Rsh16Ux64", 15167 argLen: 2, 15168 generic: true, 15169 }, 15170 { 15171 name: "Rsh32Ux8", 15172 argLen: 2, 15173 generic: true, 15174 }, 15175 { 15176 name: "Rsh32Ux16", 15177 argLen: 2, 15178 generic: true, 15179 }, 15180 { 15181 name: "Rsh32Ux32", 15182 argLen: 2, 15183 generic: true, 15184 }, 15185 { 15186 name: "Rsh32Ux64", 15187 argLen: 2, 15188 generic: true, 15189 }, 15190 { 15191 name: "Rsh64Ux8", 15192 argLen: 2, 15193 generic: true, 15194 }, 15195 { 15196 name: "Rsh64Ux16", 15197 argLen: 2, 15198 generic: true, 15199 }, 15200 { 15201 name: "Rsh64Ux32", 15202 argLen: 2, 15203 generic: true, 15204 }, 15205 { 15206 name: "Rsh64Ux64", 15207 argLen: 2, 15208 generic: true, 15209 }, 15210 { 15211 name: "Lrot8", 15212 auxType: auxInt64, 15213 argLen: 1, 15214 generic: true, 15215 }, 15216 { 15217 name: "Lrot16", 15218 auxType: auxInt64, 15219 argLen: 1, 15220 generic: true, 15221 }, 15222 { 15223 name: "Lrot32", 15224 auxType: auxInt64, 15225 argLen: 1, 15226 generic: true, 15227 }, 15228 { 15229 name: "Lrot64", 15230 auxType: auxInt64, 15231 argLen: 1, 15232 generic: true, 15233 }, 15234 { 15235 name: "Eq8", 15236 argLen: 2, 15237 commutative: true, 15238 generic: true, 15239 }, 15240 { 15241 name: "Eq16", 15242 argLen: 2, 15243 commutative: true, 15244 generic: true, 15245 }, 15246 { 15247 name: "Eq32", 15248 argLen: 2, 15249 commutative: true, 15250 generic: true, 15251 }, 15252 { 15253 name: "Eq64", 15254 argLen: 2, 15255 commutative: true, 15256 generic: true, 15257 }, 15258 { 15259 name: "EqPtr", 15260 argLen: 2, 15261 commutative: true, 15262 generic: true, 15263 }, 15264 { 15265 name: "EqInter", 15266 argLen: 2, 15267 generic: true, 15268 }, 15269 { 15270 name: "EqSlice", 15271 argLen: 2, 15272 generic: true, 15273 }, 15274 { 15275 name: "Eq32F", 15276 argLen: 2, 15277 generic: true, 15278 }, 15279 { 15280 name: "Eq64F", 15281 argLen: 2, 15282 generic: true, 15283 }, 15284 { 15285 name: "Neq8", 15286 argLen: 2, 15287 commutative: true, 15288 generic: true, 15289 }, 15290 { 15291 name: "Neq16", 15292 argLen: 2, 15293 commutative: true, 15294 generic: true, 15295 }, 15296 { 15297 name: "Neq32", 15298 argLen: 2, 15299 commutative: true, 15300 generic: true, 15301 }, 15302 { 15303 name: "Neq64", 15304 argLen: 2, 15305 commutative: true, 15306 generic: true, 15307 }, 15308 { 15309 name: "NeqPtr", 15310 argLen: 2, 15311 commutative: true, 15312 generic: true, 15313 }, 15314 { 15315 name: "NeqInter", 15316 argLen: 2, 15317 generic: true, 15318 }, 15319 { 15320 name: "NeqSlice", 15321 argLen: 2, 15322 generic: true, 15323 }, 15324 { 15325 name: "Neq32F", 15326 argLen: 2, 15327 generic: true, 15328 }, 15329 { 15330 name: "Neq64F", 15331 argLen: 2, 15332 generic: true, 15333 }, 15334 { 15335 name: "Less8", 15336 argLen: 2, 15337 generic: true, 15338 }, 15339 { 15340 name: "Less8U", 15341 argLen: 2, 15342 generic: true, 15343 }, 15344 { 15345 name: "Less16", 15346 argLen: 2, 15347 generic: true, 15348 }, 15349 { 15350 name: "Less16U", 15351 argLen: 2, 15352 generic: true, 15353 }, 15354 { 15355 name: "Less32", 15356 argLen: 2, 15357 generic: true, 15358 }, 15359 { 15360 name: "Less32U", 15361 argLen: 2, 15362 generic: true, 15363 }, 15364 { 15365 name: "Less64", 15366 argLen: 2, 15367 generic: true, 15368 }, 15369 { 15370 name: "Less64U", 15371 argLen: 2, 15372 generic: true, 15373 }, 15374 { 15375 name: "Less32F", 15376 argLen: 2, 15377 generic: true, 15378 }, 15379 { 15380 name: "Less64F", 15381 argLen: 2, 15382 generic: true, 15383 }, 15384 { 15385 name: "Leq8", 15386 argLen: 2, 15387 generic: true, 15388 }, 15389 { 15390 name: "Leq8U", 15391 argLen: 2, 15392 generic: true, 15393 }, 15394 { 15395 name: "Leq16", 15396 argLen: 2, 15397 generic: true, 15398 }, 15399 { 15400 name: "Leq16U", 15401 argLen: 2, 15402 generic: true, 15403 }, 15404 { 15405 name: "Leq32", 15406 argLen: 2, 15407 generic: true, 15408 }, 15409 { 15410 name: "Leq32U", 15411 argLen: 2, 15412 generic: true, 15413 }, 15414 { 15415 name: "Leq64", 15416 argLen: 2, 15417 generic: true, 15418 }, 15419 { 15420 name: "Leq64U", 15421 argLen: 2, 15422 generic: true, 15423 }, 15424 { 15425 name: "Leq32F", 15426 argLen: 2, 15427 generic: true, 15428 }, 15429 { 15430 name: "Leq64F", 15431 argLen: 2, 15432 generic: true, 15433 }, 15434 { 15435 name: "Greater8", 15436 argLen: 2, 15437 generic: true, 15438 }, 15439 { 15440 name: "Greater8U", 15441 argLen: 2, 15442 generic: true, 15443 }, 15444 { 15445 name: "Greater16", 15446 argLen: 2, 15447 generic: true, 15448 }, 15449 { 15450 name: "Greater16U", 15451 argLen: 2, 15452 generic: true, 15453 }, 15454 { 15455 name: "Greater32", 15456 argLen: 2, 15457 generic: true, 15458 }, 15459 { 15460 name: "Greater32U", 15461 argLen: 2, 15462 generic: true, 15463 }, 15464 { 15465 name: "Greater64", 15466 argLen: 2, 15467 generic: true, 15468 }, 15469 { 15470 name: "Greater64U", 15471 argLen: 2, 15472 generic: true, 15473 }, 15474 { 15475 name: "Greater32F", 15476 argLen: 2, 15477 generic: true, 15478 }, 15479 { 15480 name: "Greater64F", 15481 argLen: 2, 15482 generic: true, 15483 }, 15484 { 15485 name: "Geq8", 15486 argLen: 2, 15487 generic: true, 15488 }, 15489 { 15490 name: "Geq8U", 15491 argLen: 2, 15492 generic: true, 15493 }, 15494 { 15495 name: "Geq16", 15496 argLen: 2, 15497 generic: true, 15498 }, 15499 { 15500 name: "Geq16U", 15501 argLen: 2, 15502 generic: true, 15503 }, 15504 { 15505 name: "Geq32", 15506 argLen: 2, 15507 generic: true, 15508 }, 15509 { 15510 name: "Geq32U", 15511 argLen: 2, 15512 generic: true, 15513 }, 15514 { 15515 name: "Geq64", 15516 argLen: 2, 15517 generic: true, 15518 }, 15519 { 15520 name: "Geq64U", 15521 argLen: 2, 15522 generic: true, 15523 }, 15524 { 15525 name: "Geq32F", 15526 argLen: 2, 15527 generic: true, 15528 }, 15529 { 15530 name: "Geq64F", 15531 argLen: 2, 15532 generic: true, 15533 }, 15534 { 15535 name: "AndB", 15536 argLen: 2, 15537 generic: true, 15538 }, 15539 { 15540 name: "OrB", 15541 argLen: 2, 15542 generic: true, 15543 }, 15544 { 15545 name: "EqB", 15546 argLen: 2, 15547 generic: true, 15548 }, 15549 { 15550 name: "NeqB", 15551 argLen: 2, 15552 generic: true, 15553 }, 15554 { 15555 name: "Not", 15556 argLen: 1, 15557 generic: true, 15558 }, 15559 { 15560 name: "Neg8", 15561 argLen: 1, 15562 generic: true, 15563 }, 15564 { 15565 name: "Neg16", 15566 argLen: 1, 15567 generic: true, 15568 }, 15569 { 15570 name: "Neg32", 15571 argLen: 1, 15572 generic: true, 15573 }, 15574 { 15575 name: "Neg64", 15576 argLen: 1, 15577 generic: true, 15578 }, 15579 { 15580 name: "Neg32F", 15581 argLen: 1, 15582 generic: true, 15583 }, 15584 { 15585 name: "Neg64F", 15586 argLen: 1, 15587 generic: true, 15588 }, 15589 { 15590 name: "Com8", 15591 argLen: 1, 15592 generic: true, 15593 }, 15594 { 15595 name: "Com16", 15596 argLen: 1, 15597 generic: true, 15598 }, 15599 { 15600 name: "Com32", 15601 argLen: 1, 15602 generic: true, 15603 }, 15604 { 15605 name: "Com64", 15606 argLen: 1, 15607 generic: true, 15608 }, 15609 { 15610 name: "Ctz32", 15611 argLen: 1, 15612 generic: true, 15613 }, 15614 { 15615 name: "Ctz64", 15616 argLen: 1, 15617 generic: true, 15618 }, 15619 { 15620 name: "Bswap32", 15621 argLen: 1, 15622 generic: true, 15623 }, 15624 { 15625 name: "Bswap64", 15626 argLen: 1, 15627 generic: true, 15628 }, 15629 { 15630 name: "Sqrt", 15631 argLen: 1, 15632 generic: true, 15633 }, 15634 { 15635 name: "Phi", 15636 argLen: -1, 15637 generic: true, 15638 }, 15639 { 15640 name: "Copy", 15641 argLen: 1, 15642 generic: true, 15643 }, 15644 { 15645 name: "Convert", 15646 argLen: 2, 15647 generic: true, 15648 }, 15649 { 15650 name: "ConstBool", 15651 auxType: auxBool, 15652 argLen: 0, 15653 generic: true, 15654 }, 15655 { 15656 name: "ConstString", 15657 auxType: auxString, 15658 argLen: 0, 15659 generic: true, 15660 }, 15661 { 15662 name: "ConstNil", 15663 argLen: 0, 15664 generic: true, 15665 }, 15666 { 15667 name: "Const8", 15668 auxType: auxInt8, 15669 argLen: 0, 15670 generic: true, 15671 }, 15672 { 15673 name: "Const16", 15674 auxType: auxInt16, 15675 argLen: 0, 15676 generic: true, 15677 }, 15678 { 15679 name: "Const32", 15680 auxType: auxInt32, 15681 argLen: 0, 15682 generic: true, 15683 }, 15684 { 15685 name: "Const64", 15686 auxType: auxInt64, 15687 argLen: 0, 15688 generic: true, 15689 }, 15690 { 15691 name: "Const32F", 15692 auxType: auxFloat32, 15693 argLen: 0, 15694 generic: true, 15695 }, 15696 { 15697 name: "Const64F", 15698 auxType: auxFloat64, 15699 argLen: 0, 15700 generic: true, 15701 }, 15702 { 15703 name: "ConstInterface", 15704 argLen: 0, 15705 generic: true, 15706 }, 15707 { 15708 name: "ConstSlice", 15709 argLen: 0, 15710 generic: true, 15711 }, 15712 { 15713 name: "InitMem", 15714 argLen: 0, 15715 generic: true, 15716 }, 15717 { 15718 name: "Arg", 15719 auxType: auxSymOff, 15720 argLen: 0, 15721 generic: true, 15722 }, 15723 { 15724 name: "Addr", 15725 auxType: auxSym, 15726 argLen: 1, 15727 generic: true, 15728 }, 15729 { 15730 name: "SP", 15731 argLen: 0, 15732 generic: true, 15733 }, 15734 { 15735 name: "SB", 15736 argLen: 0, 15737 generic: true, 15738 }, 15739 { 15740 name: "Func", 15741 auxType: auxSym, 15742 argLen: 0, 15743 generic: true, 15744 }, 15745 { 15746 name: "Load", 15747 argLen: 2, 15748 generic: true, 15749 }, 15750 { 15751 name: "Store", 15752 auxType: auxInt64, 15753 argLen: 3, 15754 generic: true, 15755 }, 15756 { 15757 name: "Move", 15758 auxType: auxInt64, 15759 argLen: 3, 15760 generic: true, 15761 }, 15762 { 15763 name: "Zero", 15764 auxType: auxInt64, 15765 argLen: 2, 15766 generic: true, 15767 }, 15768 { 15769 name: "ClosureCall", 15770 auxType: auxInt64, 15771 argLen: 3, 15772 generic: true, 15773 }, 15774 { 15775 name: "StaticCall", 15776 auxType: auxSymOff, 15777 argLen: 1, 15778 generic: true, 15779 }, 15780 { 15781 name: "DeferCall", 15782 auxType: auxInt64, 15783 argLen: 1, 15784 generic: true, 15785 }, 15786 { 15787 name: "GoCall", 15788 auxType: auxInt64, 15789 argLen: 1, 15790 generic: true, 15791 }, 15792 { 15793 name: "InterCall", 15794 auxType: auxInt64, 15795 argLen: 2, 15796 generic: true, 15797 }, 15798 { 15799 name: "SignExt8to16", 15800 argLen: 1, 15801 generic: true, 15802 }, 15803 { 15804 name: "SignExt8to32", 15805 argLen: 1, 15806 generic: true, 15807 }, 15808 { 15809 name: "SignExt8to64", 15810 argLen: 1, 15811 generic: true, 15812 }, 15813 { 15814 name: "SignExt16to32", 15815 argLen: 1, 15816 generic: true, 15817 }, 15818 { 15819 name: "SignExt16to64", 15820 argLen: 1, 15821 generic: true, 15822 }, 15823 { 15824 name: "SignExt32to64", 15825 argLen: 1, 15826 generic: true, 15827 }, 15828 { 15829 name: "ZeroExt8to16", 15830 argLen: 1, 15831 generic: true, 15832 }, 15833 { 15834 name: "ZeroExt8to32", 15835 argLen: 1, 15836 generic: true, 15837 }, 15838 { 15839 name: "ZeroExt8to64", 15840 argLen: 1, 15841 generic: true, 15842 }, 15843 { 15844 name: "ZeroExt16to32", 15845 argLen: 1, 15846 generic: true, 15847 }, 15848 { 15849 name: "ZeroExt16to64", 15850 argLen: 1, 15851 generic: true, 15852 }, 15853 { 15854 name: "ZeroExt32to64", 15855 argLen: 1, 15856 generic: true, 15857 }, 15858 { 15859 name: "Trunc16to8", 15860 argLen: 1, 15861 generic: true, 15862 }, 15863 { 15864 name: "Trunc32to8", 15865 argLen: 1, 15866 generic: true, 15867 }, 15868 { 15869 name: "Trunc32to16", 15870 argLen: 1, 15871 generic: true, 15872 }, 15873 { 15874 name: "Trunc64to8", 15875 argLen: 1, 15876 generic: true, 15877 }, 15878 { 15879 name: "Trunc64to16", 15880 argLen: 1, 15881 generic: true, 15882 }, 15883 { 15884 name: "Trunc64to32", 15885 argLen: 1, 15886 generic: true, 15887 }, 15888 { 15889 name: "Cvt32to32F", 15890 argLen: 1, 15891 generic: true, 15892 }, 15893 { 15894 name: "Cvt32to64F", 15895 argLen: 1, 15896 generic: true, 15897 }, 15898 { 15899 name: "Cvt64to32F", 15900 argLen: 1, 15901 generic: true, 15902 }, 15903 { 15904 name: "Cvt64to64F", 15905 argLen: 1, 15906 generic: true, 15907 }, 15908 { 15909 name: "Cvt32Fto32", 15910 argLen: 1, 15911 generic: true, 15912 }, 15913 { 15914 name: "Cvt32Fto64", 15915 argLen: 1, 15916 generic: true, 15917 }, 15918 { 15919 name: "Cvt64Fto32", 15920 argLen: 1, 15921 generic: true, 15922 }, 15923 { 15924 name: "Cvt64Fto64", 15925 argLen: 1, 15926 generic: true, 15927 }, 15928 { 15929 name: "Cvt32Fto64F", 15930 argLen: 1, 15931 generic: true, 15932 }, 15933 { 15934 name: "Cvt64Fto32F", 15935 argLen: 1, 15936 generic: true, 15937 }, 15938 { 15939 name: "IsNonNil", 15940 argLen: 1, 15941 generic: true, 15942 }, 15943 { 15944 name: "IsInBounds", 15945 argLen: 2, 15946 generic: true, 15947 }, 15948 { 15949 name: "IsSliceInBounds", 15950 argLen: 2, 15951 generic: true, 15952 }, 15953 { 15954 name: "NilCheck", 15955 argLen: 2, 15956 generic: true, 15957 }, 15958 { 15959 name: "GetG", 15960 argLen: 1, 15961 generic: true, 15962 }, 15963 { 15964 name: "GetClosurePtr", 15965 argLen: 0, 15966 generic: true, 15967 }, 15968 { 15969 name: "ArrayIndex", 15970 auxType: auxInt64, 15971 argLen: 1, 15972 generic: true, 15973 }, 15974 { 15975 name: "PtrIndex", 15976 argLen: 2, 15977 generic: true, 15978 }, 15979 { 15980 name: "OffPtr", 15981 auxType: auxInt64, 15982 argLen: 1, 15983 generic: true, 15984 }, 15985 { 15986 name: "SliceMake", 15987 argLen: 3, 15988 generic: true, 15989 }, 15990 { 15991 name: "SlicePtr", 15992 argLen: 1, 15993 generic: true, 15994 }, 15995 { 15996 name: "SliceLen", 15997 argLen: 1, 15998 generic: true, 15999 }, 16000 { 16001 name: "SliceCap", 16002 argLen: 1, 16003 generic: true, 16004 }, 16005 { 16006 name: "ComplexMake", 16007 argLen: 2, 16008 generic: true, 16009 }, 16010 { 16011 name: "ComplexReal", 16012 argLen: 1, 16013 generic: true, 16014 }, 16015 { 16016 name: "ComplexImag", 16017 argLen: 1, 16018 generic: true, 16019 }, 16020 { 16021 name: "StringMake", 16022 argLen: 2, 16023 generic: true, 16024 }, 16025 { 16026 name: "StringPtr", 16027 argLen: 1, 16028 generic: true, 16029 }, 16030 { 16031 name: "StringLen", 16032 argLen: 1, 16033 generic: true, 16034 }, 16035 { 16036 name: "IMake", 16037 argLen: 2, 16038 generic: true, 16039 }, 16040 { 16041 name: "ITab", 16042 argLen: 1, 16043 generic: true, 16044 }, 16045 { 16046 name: "IData", 16047 argLen: 1, 16048 generic: true, 16049 }, 16050 { 16051 name: "StructMake0", 16052 argLen: 0, 16053 generic: true, 16054 }, 16055 { 16056 name: "StructMake1", 16057 argLen: 1, 16058 generic: true, 16059 }, 16060 { 16061 name: "StructMake2", 16062 argLen: 2, 16063 generic: true, 16064 }, 16065 { 16066 name: "StructMake3", 16067 argLen: 3, 16068 generic: true, 16069 }, 16070 { 16071 name: "StructMake4", 16072 argLen: 4, 16073 generic: true, 16074 }, 16075 { 16076 name: "StructSelect", 16077 auxType: auxInt64, 16078 argLen: 1, 16079 generic: true, 16080 }, 16081 { 16082 name: "StoreReg", 16083 argLen: 1, 16084 generic: true, 16085 }, 16086 { 16087 name: "LoadReg", 16088 argLen: 1, 16089 generic: true, 16090 }, 16091 { 16092 name: "FwdRef", 16093 auxType: auxSym, 16094 argLen: 0, 16095 generic: true, 16096 }, 16097 { 16098 name: "Unknown", 16099 argLen: 0, 16100 generic: true, 16101 }, 16102 { 16103 name: "VarDef", 16104 auxType: auxSym, 16105 argLen: 1, 16106 generic: true, 16107 }, 16108 { 16109 name: "VarKill", 16110 auxType: auxSym, 16111 argLen: 1, 16112 generic: true, 16113 }, 16114 { 16115 name: "VarLive", 16116 auxType: auxSym, 16117 argLen: 1, 16118 generic: true, 16119 }, 16120 { 16121 name: "KeepAlive", 16122 argLen: 2, 16123 generic: true, 16124 }, 16125 { 16126 name: "Int64Make", 16127 argLen: 2, 16128 generic: true, 16129 }, 16130 { 16131 name: "Int64Hi", 16132 argLen: 1, 16133 generic: true, 16134 }, 16135 { 16136 name: "Int64Lo", 16137 argLen: 1, 16138 generic: true, 16139 }, 16140 { 16141 name: "Add32carry", 16142 argLen: 2, 16143 commutative: true, 16144 generic: true, 16145 }, 16146 { 16147 name: "Add32withcarry", 16148 argLen: 3, 16149 commutative: true, 16150 generic: true, 16151 }, 16152 { 16153 name: "Sub32carry", 16154 argLen: 2, 16155 generic: true, 16156 }, 16157 { 16158 name: "Sub32withcarry", 16159 argLen: 3, 16160 generic: true, 16161 }, 16162 { 16163 name: "Mul32uhilo", 16164 argLen: 2, 16165 generic: true, 16166 }, 16167 { 16168 name: "Signmask", 16169 argLen: 1, 16170 generic: true, 16171 }, 16172 { 16173 name: "Zeromask", 16174 argLen: 1, 16175 generic: true, 16176 }, 16177 { 16178 name: "Cvt32Uto32F", 16179 argLen: 1, 16180 generic: true, 16181 }, 16182 { 16183 name: "Cvt32Uto64F", 16184 argLen: 1, 16185 generic: true, 16186 }, 16187 { 16188 name: "Cvt32Fto32U", 16189 argLen: 1, 16190 generic: true, 16191 }, 16192 { 16193 name: "Cvt64Fto32U", 16194 argLen: 1, 16195 generic: true, 16196 }, 16197 { 16198 name: "Cvt64Uto32F", 16199 argLen: 1, 16200 generic: true, 16201 }, 16202 { 16203 name: "Cvt64Uto64F", 16204 argLen: 1, 16205 generic: true, 16206 }, 16207 { 16208 name: "Cvt32Fto64U", 16209 argLen: 1, 16210 generic: true, 16211 }, 16212 { 16213 name: "Cvt64Fto64U", 16214 argLen: 1, 16215 generic: true, 16216 }, 16217 { 16218 name: "Select0", 16219 argLen: 1, 16220 generic: true, 16221 }, 16222 { 16223 name: "Select1", 16224 argLen: 1, 16225 generic: true, 16226 }, 16227 { 16228 name: "AtomicLoad32", 16229 argLen: 2, 16230 generic: true, 16231 }, 16232 { 16233 name: "AtomicLoad64", 16234 argLen: 2, 16235 generic: true, 16236 }, 16237 { 16238 name: "AtomicLoadPtr", 16239 argLen: 2, 16240 generic: true, 16241 }, 16242 { 16243 name: "AtomicStore32", 16244 argLen: 3, 16245 generic: true, 16246 }, 16247 { 16248 name: "AtomicStore64", 16249 argLen: 3, 16250 generic: true, 16251 }, 16252 { 16253 name: "AtomicStorePtrNoWB", 16254 argLen: 3, 16255 generic: true, 16256 }, 16257 } 16258 16259 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 16260 func (o Op) String() string { return opcodeTable[o].name } 16261 16262 var registers386 = [...]Register{ 16263 {0, "AX"}, 16264 {1, "CX"}, 16265 {2, "DX"}, 16266 {3, "BX"}, 16267 {4, "SP"}, 16268 {5, "BP"}, 16269 {6, "SI"}, 16270 {7, "DI"}, 16271 {8, "X0"}, 16272 {9, "X1"}, 16273 {10, "X2"}, 16274 {11, "X3"}, 16275 {12, "X4"}, 16276 {13, "X5"}, 16277 {14, "X6"}, 16278 {15, "X7"}, 16279 {16, "SB"}, 16280 } 16281 var gpRegMask386 = regMask(239) 16282 var fpRegMask386 = regMask(65280) 16283 var specialRegMask386 = regMask(0) 16284 var framepointerReg386 = int8(5) 16285 var registersAMD64 = [...]Register{ 16286 {0, "AX"}, 16287 {1, "CX"}, 16288 {2, "DX"}, 16289 {3, "BX"}, 16290 {4, "SP"}, 16291 {5, "BP"}, 16292 {6, "SI"}, 16293 {7, "DI"}, 16294 {8, "R8"}, 16295 {9, "R9"}, 16296 {10, "R10"}, 16297 {11, "R11"}, 16298 {12, "R12"}, 16299 {13, "R13"}, 16300 {14, "R14"}, 16301 {15, "R15"}, 16302 {16, "X0"}, 16303 {17, "X1"}, 16304 {18, "X2"}, 16305 {19, "X3"}, 16306 {20, "X4"}, 16307 {21, "X5"}, 16308 {22, "X6"}, 16309 {23, "X7"}, 16310 {24, "X8"}, 16311 {25, "X9"}, 16312 {26, "X10"}, 16313 {27, "X11"}, 16314 {28, "X12"}, 16315 {29, "X13"}, 16316 {30, "X14"}, 16317 {31, "X15"}, 16318 {32, "SB"}, 16319 } 16320 var gpRegMaskAMD64 = regMask(65519) 16321 var fpRegMaskAMD64 = regMask(4294901760) 16322 var specialRegMaskAMD64 = regMask(0) 16323 var framepointerRegAMD64 = int8(5) 16324 var registersARM = [...]Register{ 16325 {0, "R0"}, 16326 {1, "R1"}, 16327 {2, "R2"}, 16328 {3, "R3"}, 16329 {4, "R4"}, 16330 {5, "R5"}, 16331 {6, "R6"}, 16332 {7, "R7"}, 16333 {8, "R8"}, 16334 {9, "R9"}, 16335 {10, "g"}, 16336 {11, "R11"}, 16337 {12, "R12"}, 16338 {13, "SP"}, 16339 {14, "R14"}, 16340 {15, "R15"}, 16341 {16, "F0"}, 16342 {17, "F1"}, 16343 {18, "F2"}, 16344 {19, "F3"}, 16345 {20, "F4"}, 16346 {21, "F5"}, 16347 {22, "F6"}, 16348 {23, "F7"}, 16349 {24, "F8"}, 16350 {25, "F9"}, 16351 {26, "F10"}, 16352 {27, "F11"}, 16353 {28, "F12"}, 16354 {29, "F13"}, 16355 {30, "F14"}, 16356 {31, "F15"}, 16357 {32, "SB"}, 16358 } 16359 var gpRegMaskARM = regMask(5119) 16360 var fpRegMaskARM = regMask(4294901760) 16361 var specialRegMaskARM = regMask(0) 16362 var framepointerRegARM = int8(-1) 16363 var registersARM64 = [...]Register{ 16364 {0, "R0"}, 16365 {1, "R1"}, 16366 {2, "R2"}, 16367 {3, "R3"}, 16368 {4, "R4"}, 16369 {5, "R5"}, 16370 {6, "R6"}, 16371 {7, "R7"}, 16372 {8, "R8"}, 16373 {9, "R9"}, 16374 {10, "R10"}, 16375 {11, "R11"}, 16376 {12, "R12"}, 16377 {13, "R13"}, 16378 {14, "R14"}, 16379 {15, "R15"}, 16380 {16, "R16"}, 16381 {17, "R17"}, 16382 {18, "R18"}, 16383 {19, "R19"}, 16384 {20, "R20"}, 16385 {21, "R21"}, 16386 {22, "R22"}, 16387 {23, "R23"}, 16388 {24, "R24"}, 16389 {25, "R25"}, 16390 {26, "R26"}, 16391 {27, "g"}, 16392 {28, "R29"}, 16393 {29, "SP"}, 16394 {30, "F0"}, 16395 {31, "F1"}, 16396 {32, "F2"}, 16397 {33, "F3"}, 16398 {34, "F4"}, 16399 {35, "F5"}, 16400 {36, "F6"}, 16401 {37, "F7"}, 16402 {38, "F8"}, 16403 {39, "F9"}, 16404 {40, "F10"}, 16405 {41, "F11"}, 16406 {42, "F12"}, 16407 {43, "F13"}, 16408 {44, "F14"}, 16409 {45, "F15"}, 16410 {46, "F16"}, 16411 {47, "F17"}, 16412 {48, "F18"}, 16413 {49, "F19"}, 16414 {50, "F20"}, 16415 {51, "F21"}, 16416 {52, "F22"}, 16417 {53, "F23"}, 16418 {54, "F24"}, 16419 {55, "F25"}, 16420 {56, "F26"}, 16421 {57, "F27"}, 16422 {58, "F28"}, 16423 {59, "F29"}, 16424 {60, "F30"}, 16425 {61, "F31"}, 16426 {62, "SB"}, 16427 } 16428 var gpRegMaskARM64 = regMask(133955583) 16429 var fpRegMaskARM64 = regMask(288230375077969920) 16430 var specialRegMaskARM64 = regMask(0) 16431 var framepointerRegARM64 = int8(-1) 16432 var registersMIPS64 = [...]Register{ 16433 {0, "R0"}, 16434 {1, "R1"}, 16435 {2, "R2"}, 16436 {3, "R3"}, 16437 {4, "R4"}, 16438 {5, "R5"}, 16439 {6, "R6"}, 16440 {7, "R7"}, 16441 {8, "R8"}, 16442 {9, "R9"}, 16443 {10, "R10"}, 16444 {11, "R11"}, 16445 {12, "R12"}, 16446 {13, "R13"}, 16447 {14, "R14"}, 16448 {15, "R15"}, 16449 {16, "R16"}, 16450 {17, "R17"}, 16451 {18, "R18"}, 16452 {19, "R19"}, 16453 {20, "R20"}, 16454 {21, "R21"}, 16455 {22, "R22"}, 16456 {23, "R24"}, 16457 {24, "R25"}, 16458 {25, "SP"}, 16459 {26, "g"}, 16460 {27, "F0"}, 16461 {28, "F1"}, 16462 {29, "F2"}, 16463 {30, "F3"}, 16464 {31, "F4"}, 16465 {32, "F5"}, 16466 {33, "F6"}, 16467 {34, "F7"}, 16468 {35, "F8"}, 16469 {36, "F9"}, 16470 {37, "F10"}, 16471 {38, "F11"}, 16472 {39, "F12"}, 16473 {40, "F13"}, 16474 {41, "F14"}, 16475 {42, "F15"}, 16476 {43, "F16"}, 16477 {44, "F17"}, 16478 {45, "F18"}, 16479 {46, "F19"}, 16480 {47, "F20"}, 16481 {48, "F21"}, 16482 {49, "F22"}, 16483 {50, "F23"}, 16484 {51, "F24"}, 16485 {52, "F25"}, 16486 {53, "F26"}, 16487 {54, "F27"}, 16488 {55, "F28"}, 16489 {56, "F29"}, 16490 {57, "F30"}, 16491 {58, "F31"}, 16492 {59, "HI"}, 16493 {60, "LO"}, 16494 {61, "SB"}, 16495 } 16496 var gpRegMaskMIPS64 = regMask(33554430) 16497 var fpRegMaskMIPS64 = regMask(385057768005959680) 16498 var specialRegMaskMIPS64 = regMask(1729382256910270464) 16499 var framepointerRegMIPS64 = int8(-1) 16500 var registersPPC64 = [...]Register{ 16501 {0, "SP"}, 16502 {1, "SB"}, 16503 {2, "R3"}, 16504 {3, "R4"}, 16505 {4, "R5"}, 16506 {5, "R6"}, 16507 {6, "R7"}, 16508 {7, "R8"}, 16509 {8, "R9"}, 16510 {9, "R10"}, 16511 {10, "R11"}, 16512 {11, "R12"}, 16513 {12, "R13"}, 16514 {13, "R14"}, 16515 {14, "R15"}, 16516 {15, "R16"}, 16517 {16, "R17"}, 16518 {17, "R18"}, 16519 {18, "R19"}, 16520 {19, "R20"}, 16521 {20, "R21"}, 16522 {21, "R22"}, 16523 {22, "R23"}, 16524 {23, "R24"}, 16525 {24, "R25"}, 16526 {25, "R26"}, 16527 {26, "R27"}, 16528 {27, "R28"}, 16529 {28, "R29"}, 16530 {29, "g"}, 16531 {30, "R31"}, 16532 {31, "F0"}, 16533 {32, "F1"}, 16534 {33, "F2"}, 16535 {34, "F3"}, 16536 {35, "F4"}, 16537 {36, "F5"}, 16538 {37, "F6"}, 16539 {38, "F7"}, 16540 {39, "F8"}, 16541 {40, "F9"}, 16542 {41, "F10"}, 16543 {42, "F11"}, 16544 {43, "F12"}, 16545 {44, "F13"}, 16546 {45, "F14"}, 16547 {46, "F15"}, 16548 {47, "F16"}, 16549 {48, "F17"}, 16550 {49, "F18"}, 16551 {50, "F19"}, 16552 {51, "F20"}, 16553 {52, "F21"}, 16554 {53, "F22"}, 16555 {54, "F23"}, 16556 {55, "F24"}, 16557 {56, "F25"}, 16558 {57, "F26"}, 16559 } 16560 var gpRegMaskPPC64 = regMask(536866812) 16561 var fpRegMaskPPC64 = regMask(288230371856744448) 16562 var specialRegMaskPPC64 = regMask(0) 16563 var framepointerRegPPC64 = int8(0)