github.com/shogo82148/std@v1.22.1-0.20240327122250-4e474527810c/cmd/internal/obj/arm/a.out.go (about) 1 // Inferno utils/5c/5.out.h 2 // https://bitbucket.org/inferno-os/inferno-os/src/master/utils/5c/5.out.h 3 // 4 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 5 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 6 // Portions Copyright © 1997-1999 Vita Nuova Limited 7 // Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com) 8 // Portions Copyright © 2004,2006 Bruce Ellis 9 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 10 // Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others 11 // Portions Copyright © 2009 The Go Authors. All rights reserved. 12 // 13 // Permission is hereby granted, free of charge, to any person obtaining a copy 14 // of this software and associated documentation files (the "Software"), to deal 15 // in the Software without restriction, including without limitation the rights 16 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 // copies of the Software, and to permit persons to whom the Software is 18 // furnished to do so, subject to the following conditions: 19 // 20 // The above copyright notice and this permission notice shall be included in 21 // all copies or substantial portions of the Software. 22 // 23 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 26 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 // THE SOFTWARE. 30 31 package arm 32 33 import "github.com/shogo82148/std/cmd/internal/obj" 34 35 const ( 36 NSNAME = 8 37 NSYM = 50 38 NREG = 16 39 ) 40 41 /* -1 disables use of REGARG */ 42 const ( 43 REGARG = -1 44 ) 45 46 const ( 47 REG_R0 = obj.RBaseARM + iota 48 REG_R1 49 REG_R2 50 REG_R3 51 REG_R4 52 REG_R5 53 REG_R6 54 REG_R7 55 REG_R8 56 REG_R9 57 REG_R10 58 REG_R11 59 REG_R12 60 REG_R13 61 REG_R14 62 REG_R15 63 64 REG_F0 65 REG_F1 66 REG_F2 67 REG_F3 68 REG_F4 69 REG_F5 70 REG_F6 71 REG_F7 72 REG_F8 73 REG_F9 74 REG_F10 75 REG_F11 76 REG_F12 77 REG_F13 78 REG_F14 79 REG_F15 80 81 REG_FPSR 82 REG_FPCR 83 84 REG_CPSR 85 REG_SPSR 86 87 REGRET = REG_R0 88 /* compiler allocates R1 up as temps */ 89 /* compiler allocates register variables R3 up */ 90 /* compiler allocates external registers R10 down */ 91 REGEXT = REG_R10 92 /* these two registers are declared in runtime.h */ 93 REGG = REGEXT - 0 94 REGM = REGEXT - 1 95 96 REGCTXT = REG_R7 97 REGTMP = REG_R11 98 REGSP = REG_R13 99 REGLINK = REG_R14 100 REGPC = REG_R15 101 102 NFREG = 16 103 /* compiler allocates register variables F0 up */ 104 /* compiler allocates external registers F7 down */ 105 FREGRET = REG_F0 106 FREGEXT = REG_F7 107 FREGTMP = REG_F15 108 ) 109 110 // http://infocenter.arm.com/help/topic/com.arm.doc.ihi0040b/IHI0040B_aadwarf.pdf 111 var ARMDWARFRegisters = map[int16]int16{} 112 113 // Special registers, after subtracting obj.RBaseARM, bit 9 indicates 114 // a special register and the low bits select the register. 115 const ( 116 REG_SPECIAL = obj.RBaseARM + 1<<9 + iota 117 REG_MB_SY 118 REG_MB_ST 119 REG_MB_ISH 120 REG_MB_ISHST 121 REG_MB_NSH 122 REG_MB_NSHST 123 REG_MB_OSH 124 REG_MB_OSHST 125 126 MAXREG 127 ) 128 129 const ( 130 C_NONE = iota 131 C_REG 132 C_REGREG 133 C_REGREG2 134 C_REGLIST 135 C_SHIFT 136 C_SHIFTADDR 137 C_FREG 138 C_PSR 139 C_FCR 140 C_SPR 141 142 C_RCON 143 C_NCON 144 C_RCON2A 145 C_RCON2S 146 C_SCON 147 C_LCON 148 C_LCONADDR 149 C_ZFCON 150 C_SFCON 151 C_LFCON 152 153 C_RACON 154 C_LACON 155 156 C_SBRA 157 C_LBRA 158 159 C_HAUTO 160 C_FAUTO 161 C_HFAUTO 162 C_SAUTO 163 C_LAUTO 164 165 C_HOREG 166 C_FOREG 167 C_HFOREG 168 C_SOREG 169 C_ROREG 170 C_SROREG 171 C_LOREG 172 173 C_PC 174 C_SP 175 C_HREG 176 177 C_ADDR 178 179 // TLS "var" in local exec mode: will become a constant offset from 180 // thread local base that is ultimately chosen by the program linker. 181 C_TLS_LE 182 183 // TLS "var" in initial exec mode: will become a memory address (chosen 184 // by the program linker) that the dynamic linker will fill with the 185 // offset from the thread local base. 186 C_TLS_IE 187 188 C_TEXTSIZE 189 190 C_GOK 191 192 C_NCLASS 193 ) 194 195 const ( 196 AAND = obj.ABaseARM + obj.A_ARCHSPECIFIC + iota 197 AEOR 198 ASUB 199 ARSB 200 AADD 201 AADC 202 ASBC 203 ARSC 204 ATST 205 ATEQ 206 ACMP 207 ACMN 208 AORR 209 ABIC 210 211 AMVN 212 213 /* 214 * Do not reorder or fragment the conditional branch 215 * opcodes, or the predication code will break 216 */ 217 ABEQ 218 ABNE 219 ABCS 220 ABHS 221 ABCC 222 ABLO 223 ABMI 224 ABPL 225 ABVS 226 ABVC 227 ABHI 228 ABLS 229 ABGE 230 ABLT 231 ABGT 232 ABLE 233 234 AMOVWD 235 AMOVWF 236 AMOVDW 237 AMOVFW 238 AMOVFD 239 AMOVDF 240 AMOVF 241 AMOVD 242 243 ACMPF 244 ACMPD 245 AADDF 246 AADDD 247 ASUBF 248 ASUBD 249 AMULF 250 AMULD 251 ANMULF 252 ANMULD 253 AMULAF 254 AMULAD 255 ANMULAF 256 ANMULAD 257 AMULSF 258 AMULSD 259 ANMULSF 260 ANMULSD 261 AFMULAF 262 AFMULAD 263 AFNMULAF 264 AFNMULAD 265 AFMULSF 266 AFMULSD 267 AFNMULSF 268 AFNMULSD 269 ADIVF 270 ADIVD 271 ASQRTF 272 ASQRTD 273 AABSF 274 AABSD 275 ANEGF 276 ANEGD 277 278 ASRL 279 ASRA 280 ASLL 281 AMULU 282 ADIVU 283 AMUL 284 AMMUL 285 ADIV 286 AMOD 287 AMODU 288 ADIVHW 289 ADIVUHW 290 291 AMOVB 292 AMOVBS 293 AMOVBU 294 AMOVH 295 AMOVHS 296 AMOVHU 297 AMOVW 298 AMOVM 299 ASWPBU 300 ASWPW 301 302 ARFE 303 ASWI 304 AMULA 305 AMULS 306 AMMULA 307 AMMULS 308 309 AWORD 310 311 AMULL 312 AMULAL 313 AMULLU 314 AMULALU 315 316 ABX 317 ABXRET 318 ADWORD 319 320 ALDREX 321 ASTREX 322 ALDREXD 323 ASTREXD 324 325 ADMB 326 327 APLD 328 329 ACLZ 330 AREV 331 AREV16 332 AREVSH 333 ARBIT 334 335 AXTAB 336 AXTAH 337 AXTABU 338 AXTAHU 339 340 ABFX 341 ABFXU 342 ABFC 343 ABFI 344 345 AMULWT 346 AMULWB 347 AMULBB 348 AMULAWT 349 AMULAWB 350 AMULABB 351 352 AMRC 353 354 ALAST 355 356 // aliases 357 AB = obj.AJMP 358 ABL = obj.ACALL 359 ) 360 361 /* scond byte */ 362 const ( 363 C_SCOND = (1 << 4) - 1 364 C_SBIT = 1 << 4 365 C_PBIT = 1 << 5 366 C_WBIT = 1 << 6 367 C_FBIT = 1 << 7 368 C_UBIT = 1 << 7 369 370 // These constants are the ARM condition codes encodings, 371 // XORed with 14 so that C_SCOND_NONE has value 0, 372 // so that a zeroed Prog.scond means "always execute". 373 C_SCOND_XOR = 14 374 375 C_SCOND_EQ = 0 ^ C_SCOND_XOR 376 C_SCOND_NE = 1 ^ C_SCOND_XOR 377 C_SCOND_HS = 2 ^ C_SCOND_XOR 378 C_SCOND_LO = 3 ^ C_SCOND_XOR 379 C_SCOND_MI = 4 ^ C_SCOND_XOR 380 C_SCOND_PL = 5 ^ C_SCOND_XOR 381 C_SCOND_VS = 6 ^ C_SCOND_XOR 382 C_SCOND_VC = 7 ^ C_SCOND_XOR 383 C_SCOND_HI = 8 ^ C_SCOND_XOR 384 C_SCOND_LS = 9 ^ C_SCOND_XOR 385 C_SCOND_GE = 10 ^ C_SCOND_XOR 386 C_SCOND_LT = 11 ^ C_SCOND_XOR 387 C_SCOND_GT = 12 ^ C_SCOND_XOR 388 C_SCOND_LE = 13 ^ C_SCOND_XOR 389 C_SCOND_NONE = 14 ^ C_SCOND_XOR 390 C_SCOND_NV = 15 ^ C_SCOND_XOR 391 392 /* D_SHIFT type */ 393 SHIFT_LL = 0 << 5 394 SHIFT_LR = 1 << 5 395 SHIFT_AR = 2 << 5 396 SHIFT_RR = 3 << 5 397 )