github.com/shogo82148/std@v1.22.1-0.20240327122250-4e474527810c/cmd/internal/obj/arm64/a.out.go (about) 1 // cmd/7c/7.out.h from Vita Nuova. 2 // https://bitbucket.org/plan9-from-bell-labs/9-cc/src/master/src/cmd/7c/7.out.h 3 // 4 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 5 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 6 // Portions Copyright © 1997-1999 Vita Nuova Limited 7 // Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com) 8 // Portions Copyright © 2004,2006 Bruce Ellis 9 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 10 // Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others 11 // Portions Copyright © 2009 The Go Authors. All rights reserved. 12 // 13 // Permission is hereby granted, free of charge, to any person obtaining a copy 14 // of this software and associated documentation files (the "Software"), to deal 15 // in the Software without restriction, including without limitation the rights 16 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 // copies of the Software, and to permit persons to whom the Software is 18 // furnished to do so, subject to the following conditions: 19 // 20 // The above copyright notice and this permission notice shall be included in 21 // all copies or substantial portions of the Software. 22 // 23 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 26 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 // THE SOFTWARE. 30 31 package arm64 32 33 import "github.com/shogo82148/std/cmd/internal/obj" 34 35 const ( 36 NSNAME = 8 37 NSYM = 50 38 NREG = 32 39 NFREG = 32 40 ) 41 42 // General purpose registers, kept in the low bits of Prog.Reg. 43 const ( 44 // integer 45 REG_R0 = obj.RBaseARM64 + iota 46 REG_R1 47 REG_R2 48 REG_R3 49 REG_R4 50 REG_R5 51 REG_R6 52 REG_R7 53 REG_R8 54 REG_R9 55 REG_R10 56 REG_R11 57 REG_R12 58 REG_R13 59 REG_R14 60 REG_R15 61 REG_R16 62 REG_R17 63 REG_R18 64 REG_R19 65 REG_R20 66 REG_R21 67 REG_R22 68 REG_R23 69 REG_R24 70 REG_R25 71 REG_R26 72 REG_R27 73 REG_R28 74 REG_R29 75 REG_R30 76 REG_R31 77 78 // scalar floating point 79 REG_F0 80 REG_F1 81 REG_F2 82 REG_F3 83 REG_F4 84 REG_F5 85 REG_F6 86 REG_F7 87 REG_F8 88 REG_F9 89 REG_F10 90 REG_F11 91 REG_F12 92 REG_F13 93 REG_F14 94 REG_F15 95 REG_F16 96 REG_F17 97 REG_F18 98 REG_F19 99 REG_F20 100 REG_F21 101 REG_F22 102 REG_F23 103 REG_F24 104 REG_F25 105 REG_F26 106 REG_F27 107 REG_F28 108 REG_F29 109 REG_F30 110 REG_F31 111 112 // SIMD 113 REG_V0 114 REG_V1 115 REG_V2 116 REG_V3 117 REG_V4 118 REG_V5 119 REG_V6 120 REG_V7 121 REG_V8 122 REG_V9 123 REG_V10 124 REG_V11 125 REG_V12 126 REG_V13 127 REG_V14 128 REG_V15 129 REG_V16 130 REG_V17 131 REG_V18 132 REG_V19 133 REG_V20 134 REG_V21 135 REG_V22 136 REG_V23 137 REG_V24 138 REG_V25 139 REG_V26 140 REG_V27 141 REG_V28 142 REG_V29 143 REG_V30 144 REG_V31 145 146 REG_RSP = REG_V31 + 32 147 ) 148 149 // bits 0-4 indicates register: Vn 150 // bits 5-8 indicates arrangement: <T> 151 const ( 152 REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 153 REG_ELEM 154 REG_ELEM_END 155 ) 156 157 // Not registers, but flags that can be combined with regular register 158 // constants to indicate extended register conversion. When checking, 159 // you should subtract obj.RBaseARM64 first. From this difference, bit 11 160 // indicates extended register, bits 8-10 select the conversion mode. 161 // REG_LSL is the index shift specifier, bit 9 indicates shifted offset register. 162 const REG_LSL = obj.RBaseARM64 + 1<<9 163 const REG_EXT = obj.RBaseARM64 + 1<<11 164 165 const ( 166 REG_UXTB = REG_EXT + iota<<8 167 REG_UXTH 168 REG_UXTW 169 REG_UXTX 170 REG_SXTB 171 REG_SXTH 172 REG_SXTW 173 REG_SXTX 174 ) 175 176 // Special registers, after subtracting obj.RBaseARM64, bit 12 indicates 177 // a special register and the low bits select the register. 178 // SYSREG_END is the last item in the automatically generated system register 179 // declaration, and it is defined in the sysRegEnc.go file. 180 // Define the special register after REG_SPECIAL, the first value of it should be 181 // REG_{name} = SYSREG_END + iota. 182 const ( 183 REG_SPECIAL = obj.RBaseARM64 + 1<<12 184 ) 185 186 // Register assignments: 187 // 188 // compiler allocates R0 up as temps 189 // compiler allocates register variables R7-R25 190 // compiler allocates external registers R26 down 191 // 192 // compiler allocates register variables F7-F26 193 // compiler allocates external registers F26 down 194 const ( 195 REGMIN = REG_R7 196 REGRT1 = REG_R16 197 REGRT2 = REG_R17 198 REGPR = REG_R18 199 REGMAX = REG_R25 200 201 REGCTXT = REG_R26 202 REGTMP = REG_R27 203 REGG = REG_R28 204 REGFP = REG_R29 205 REGLINK = REG_R30 206 207 // ARM64 uses R31 as both stack pointer and zero register, 208 // depending on the instruction. To differentiate RSP from ZR, 209 // we use a different numeric value for REGZERO and REGSP. 210 REGZERO = REG_R31 211 REGSP = REG_RSP 212 213 FREGRET = REG_F0 214 FREGMIN = REG_F7 215 FREGMAX = REG_F26 216 FREGEXT = REG_F26 217 ) 218 219 // http://infocenter.arm.com/help/topic/com.arm.doc.ecm0665627/abi_sve_aadwarf_100985_0000_00_en.pdf 220 var ARM64DWARFRegisters = map[int16]int16{ 221 REG_R0: 0, 222 REG_R1: 1, 223 REG_R2: 2, 224 REG_R3: 3, 225 REG_R4: 4, 226 REG_R5: 5, 227 REG_R6: 6, 228 REG_R7: 7, 229 REG_R8: 8, 230 REG_R9: 9, 231 REG_R10: 10, 232 REG_R11: 11, 233 REG_R12: 12, 234 REG_R13: 13, 235 REG_R14: 14, 236 REG_R15: 15, 237 REG_R16: 16, 238 REG_R17: 17, 239 REG_R18: 18, 240 REG_R19: 19, 241 REG_R20: 20, 242 REG_R21: 21, 243 REG_R22: 22, 244 REG_R23: 23, 245 REG_R24: 24, 246 REG_R25: 25, 247 REG_R26: 26, 248 REG_R27: 27, 249 REG_R28: 28, 250 REG_R29: 29, 251 REG_R30: 30, 252 253 REG_F0: 64, 254 REG_F1: 65, 255 REG_F2: 66, 256 REG_F3: 67, 257 REG_F4: 68, 258 REG_F5: 69, 259 REG_F6: 70, 260 REG_F7: 71, 261 REG_F8: 72, 262 REG_F9: 73, 263 REG_F10: 74, 264 REG_F11: 75, 265 REG_F12: 76, 266 REG_F13: 77, 267 REG_F14: 78, 268 REG_F15: 79, 269 REG_F16: 80, 270 REG_F17: 81, 271 REG_F18: 82, 272 REG_F19: 83, 273 REG_F20: 84, 274 REG_F21: 85, 275 REG_F22: 86, 276 REG_F23: 87, 277 REG_F24: 88, 278 REG_F25: 89, 279 REG_F26: 90, 280 REG_F27: 91, 281 REG_F28: 92, 282 REG_F29: 93, 283 REG_F30: 94, 284 REG_F31: 95, 285 286 REG_V0: 64, 287 REG_V1: 65, 288 REG_V2: 66, 289 REG_V3: 67, 290 REG_V4: 68, 291 REG_V5: 69, 292 REG_V6: 70, 293 REG_V7: 71, 294 REG_V8: 72, 295 REG_V9: 73, 296 REG_V10: 74, 297 REG_V11: 75, 298 REG_V12: 76, 299 REG_V13: 77, 300 REG_V14: 78, 301 REG_V15: 79, 302 REG_V16: 80, 303 REG_V17: 81, 304 REG_V18: 82, 305 REG_V19: 83, 306 REG_V20: 84, 307 REG_V21: 85, 308 REG_V22: 86, 309 REG_V23: 87, 310 REG_V24: 88, 311 REG_V25: 89, 312 REG_V26: 90, 313 REG_V27: 91, 314 REG_V28: 92, 315 REG_V29: 93, 316 REG_V30: 94, 317 REG_V31: 95, 318 } 319 320 const ( 321 BIG = 2048 - 8 322 ) 323 324 const ( 325 /* mark flags */ 326 LABEL = 1 << iota 327 LEAF 328 FLOAT 329 BRANCH 330 LOAD 331 FCMP 332 SYNC 333 LIST 334 FOLL 335 NOSCHED 336 ) 337 338 const ( 339 // optab is sorted based on the order of these constants 340 // and the first match is chosen. 341 // The more specific class needs to come earlier. 342 C_NONE = iota + 1 343 C_REG 344 C_ZREG 345 C_RSP 346 C_FREG 347 C_VREG 348 C_PAIR 349 C_SHIFT 350 C_EXTREG 351 C_SPR 352 C_COND 353 C_SPOP 354 C_ARNG 355 C_ELEM 356 C_LIST 357 358 C_ZCON 359 C_ABCON0 360 C_ADDCON0 361 C_ABCON 362 C_AMCON 363 C_ADDCON 364 C_MBCON 365 C_MOVCON 366 C_BITCON 367 C_ADDCON2 368 C_LCON 369 C_MOVCON2 370 C_MOVCON3 371 C_VCON 372 C_FCON 373 C_VCONADDR 374 375 C_AACON 376 C_AACON2 377 C_LACON 378 C_AECON 379 380 // TODO(aram): only one branch class should be enough 381 C_SBRA 382 C_LBRA 383 384 C_ZAUTO 385 C_NSAUTO_16 386 C_NSAUTO_8 387 C_NSAUTO_4 388 C_NSAUTO 389 C_NPAUTO_16 390 C_NPAUTO 391 C_NQAUTO_16 392 C_NAUTO4K 393 C_PSAUTO_16 394 C_PSAUTO_8 395 C_PSAUTO_4 396 C_PSAUTO 397 C_PPAUTO_16 398 C_PPAUTO 399 C_PQAUTO_16 400 C_UAUTO4K_16 401 C_UAUTO4K_8 402 C_UAUTO4K_4 403 C_UAUTO4K_2 404 C_UAUTO4K 405 C_UAUTO8K_16 406 C_UAUTO8K_8 407 C_UAUTO8K_4 408 C_UAUTO8K 409 C_UAUTO16K_16 410 C_UAUTO16K_8 411 C_UAUTO16K 412 C_UAUTO32K_16 413 C_UAUTO32K 414 C_UAUTO64K 415 C_LAUTOPOOL 416 C_LAUTO 417 418 C_SEXT1 419 C_SEXT2 420 C_SEXT4 421 C_SEXT8 422 C_SEXT16 423 C_LEXT 424 425 C_ZOREG 426 C_NSOREG_16 427 C_NSOREG_8 428 C_NSOREG_4 429 C_NSOREG 430 C_NPOREG_16 431 C_NPOREG 432 C_NQOREG_16 433 C_NOREG4K 434 C_PSOREG_16 435 C_PSOREG_8 436 C_PSOREG_4 437 C_PSOREG 438 C_PPOREG_16 439 C_PPOREG 440 C_PQOREG_16 441 C_UOREG4K_16 442 C_UOREG4K_8 443 C_UOREG4K_4 444 C_UOREG4K_2 445 C_UOREG4K 446 C_UOREG8K_16 447 C_UOREG8K_8 448 C_UOREG8K_4 449 C_UOREG8K 450 C_UOREG16K_16 451 C_UOREG16K_8 452 C_UOREG16K 453 C_UOREG32K_16 454 C_UOREG32K 455 C_UOREG64K 456 C_LOREGPOOL 457 C_LOREG 458 459 C_ADDR 460 461 // The GOT slot for a symbol in -dynlink mode. 462 C_GOTADDR 463 464 // TLS "var" in local exec mode: will become a constant offset from 465 // thread local base that is ultimately chosen by the program linker. 466 C_TLS_LE 467 468 // TLS "var" in initial exec mode: will become a memory address (chosen 469 // by the program linker) that the dynamic linker will fill with the 470 // offset from the thread local base. 471 C_TLS_IE 472 473 C_ROFF 474 475 C_GOK 476 C_TEXTSIZE 477 C_NCLASS 478 ) 479 480 const ( 481 C_XPRE = 1 << 6 482 C_XPOST = 1 << 5 483 ) 484 485 const ( 486 AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota 487 AADCS 488 AADCSW 489 AADCW 490 AADD 491 AADDS 492 AADDSW 493 AADDW 494 AADR 495 AADRP 496 AAESD 497 AAESE 498 AAESIMC 499 AAESMC 500 AAND 501 AANDS 502 AANDSW 503 AANDW 504 AASR 505 AASRW 506 AAT 507 ABCC 508 ABCS 509 ABEQ 510 ABFI 511 ABFIW 512 ABFM 513 ABFMW 514 ABFXIL 515 ABFXILW 516 ABGE 517 ABGT 518 ABHI 519 ABHS 520 ABIC 521 ABICS 522 ABICSW 523 ABICW 524 ABLE 525 ABLO 526 ABLS 527 ABLT 528 ABMI 529 ABNE 530 ABPL 531 ABRK 532 ABVC 533 ABVS 534 ACASAD 535 ACASALB 536 ACASALD 537 ACASALH 538 ACASALW 539 ACASAW 540 ACASB 541 ACASD 542 ACASH 543 ACASLD 544 ACASLW 545 ACASPD 546 ACASPW 547 ACASW 548 ACBNZ 549 ACBNZW 550 ACBZ 551 ACBZW 552 ACCMN 553 ACCMNW 554 ACCMP 555 ACCMPW 556 ACINC 557 ACINCW 558 ACINV 559 ACINVW 560 ACLREX 561 ACLS 562 ACLSW 563 ACLZ 564 ACLZW 565 ACMN 566 ACMNW 567 ACMP 568 ACMPW 569 ACNEG 570 ACNEGW 571 ACRC32B 572 ACRC32CB 573 ACRC32CH 574 ACRC32CW 575 ACRC32CX 576 ACRC32H 577 ACRC32W 578 ACRC32X 579 ACSEL 580 ACSELW 581 ACSET 582 ACSETM 583 ACSETMW 584 ACSETW 585 ACSINC 586 ACSINCW 587 ACSINV 588 ACSINVW 589 ACSNEG 590 ACSNEGW 591 ADC 592 ADCPS1 593 ADCPS2 594 ADCPS3 595 ADMB 596 ADRPS 597 ADSB 598 ADWORD 599 AEON 600 AEONW 601 AEOR 602 AEORW 603 AERET 604 AEXTR 605 AEXTRW 606 AFABSD 607 AFABSS 608 AFADDD 609 AFADDS 610 AFCCMPD 611 AFCCMPED 612 AFCCMPES 613 AFCCMPS 614 AFCMPD 615 AFCMPED 616 AFCMPES 617 AFCMPS 618 AFCSELD 619 AFCSELS 620 AFCVTDH 621 AFCVTDS 622 AFCVTHD 623 AFCVTHS 624 AFCVTSD 625 AFCVTSH 626 AFCVTZSD 627 AFCVTZSDW 628 AFCVTZSS 629 AFCVTZSSW 630 AFCVTZUD 631 AFCVTZUDW 632 AFCVTZUS 633 AFCVTZUSW 634 AFDIVD 635 AFDIVS 636 AFLDPD 637 AFLDPQ 638 AFLDPS 639 AFMADDD 640 AFMADDS 641 AFMAXD 642 AFMAXNMD 643 AFMAXNMS 644 AFMAXS 645 AFMIND 646 AFMINNMD 647 AFMINNMS 648 AFMINS 649 AFMOVD 650 AFMOVQ 651 AFMOVS 652 AFMSUBD 653 AFMSUBS 654 AFMULD 655 AFMULS 656 AFNEGD 657 AFNEGS 658 AFNMADDD 659 AFNMADDS 660 AFNMSUBD 661 AFNMSUBS 662 AFNMULD 663 AFNMULS 664 AFRINTAD 665 AFRINTAS 666 AFRINTID 667 AFRINTIS 668 AFRINTMD 669 AFRINTMS 670 AFRINTND 671 AFRINTNS 672 AFRINTPD 673 AFRINTPS 674 AFRINTXD 675 AFRINTXS 676 AFRINTZD 677 AFRINTZS 678 AFSQRTD 679 AFSQRTS 680 AFSTPD 681 AFSTPQ 682 AFSTPS 683 AFSUBD 684 AFSUBS 685 AHINT 686 AHLT 687 AHVC 688 AIC 689 AISB 690 ALDADDAB 691 ALDADDAD 692 ALDADDAH 693 ALDADDALB 694 ALDADDALD 695 ALDADDALH 696 ALDADDALW 697 ALDADDAW 698 ALDADDB 699 ALDADDD 700 ALDADDH 701 ALDADDLB 702 ALDADDLD 703 ALDADDLH 704 ALDADDLW 705 ALDADDW 706 ALDAR 707 ALDARB 708 ALDARH 709 ALDARW 710 ALDAXP 711 ALDAXPW 712 ALDAXR 713 ALDAXRB 714 ALDAXRH 715 ALDAXRW 716 ALDCLRAB 717 ALDCLRAD 718 ALDCLRAH 719 ALDCLRALB 720 ALDCLRALD 721 ALDCLRALH 722 ALDCLRALW 723 ALDCLRAW 724 ALDCLRB 725 ALDCLRD 726 ALDCLRH 727 ALDCLRLB 728 ALDCLRLD 729 ALDCLRLH 730 ALDCLRLW 731 ALDCLRW 732 ALDEORAB 733 ALDEORAD 734 ALDEORAH 735 ALDEORALB 736 ALDEORALD 737 ALDEORALH 738 ALDEORALW 739 ALDEORAW 740 ALDEORB 741 ALDEORD 742 ALDEORH 743 ALDEORLB 744 ALDEORLD 745 ALDEORLH 746 ALDEORLW 747 ALDEORW 748 ALDORAB 749 ALDORAD 750 ALDORAH 751 ALDORALB 752 ALDORALD 753 ALDORALH 754 ALDORALW 755 ALDORAW 756 ALDORB 757 ALDORD 758 ALDORH 759 ALDORLB 760 ALDORLD 761 ALDORLH 762 ALDORLW 763 ALDORW 764 ALDP 765 ALDPSW 766 ALDPW 767 ALDXP 768 ALDXPW 769 ALDXR 770 ALDXRB 771 ALDXRH 772 ALDXRW 773 ALSL 774 ALSLW 775 ALSR 776 ALSRW 777 AMADD 778 AMADDW 779 AMNEG 780 AMNEGW 781 AMOVB 782 AMOVBU 783 AMOVD 784 AMOVH 785 AMOVHU 786 AMOVK 787 AMOVKW 788 AMOVN 789 AMOVNW 790 AMOVP 791 AMOVPD 792 AMOVPQ 793 AMOVPS 794 AMOVPSW 795 AMOVPW 796 AMOVW 797 AMOVWU 798 AMOVZ 799 AMOVZW 800 AMRS 801 AMSR 802 AMSUB 803 AMSUBW 804 AMUL 805 AMULW 806 AMVN 807 AMVNW 808 ANEG 809 ANEGS 810 ANEGSW 811 ANEGW 812 ANGC 813 ANGCS 814 ANGCSW 815 ANGCW 816 ANOOP 817 AORN 818 AORNW 819 AORR 820 AORRW 821 APRFM 822 APRFUM 823 ARBIT 824 ARBITW 825 AREM 826 AREMW 827 AREV 828 AREV16 829 AREV16W 830 AREV32 831 AREVW 832 AROR 833 ARORW 834 ASBC 835 ASBCS 836 ASBCSW 837 ASBCW 838 ASBFIZ 839 ASBFIZW 840 ASBFM 841 ASBFMW 842 ASBFX 843 ASBFXW 844 ASCVTFD 845 ASCVTFS 846 ASCVTFWD 847 ASCVTFWS 848 ASDIV 849 ASDIVW 850 ASEV 851 ASEVL 852 ASHA1C 853 ASHA1H 854 ASHA1M 855 ASHA1P 856 ASHA1SU0 857 ASHA1SU1 858 ASHA256H 859 ASHA256H2 860 ASHA256SU0 861 ASHA256SU1 862 ASHA512H 863 ASHA512H2 864 ASHA512SU0 865 ASHA512SU1 866 ASMADDL 867 ASMC 868 ASMNEGL 869 ASMSUBL 870 ASMULH 871 ASMULL 872 ASTLR 873 ASTLRB 874 ASTLRH 875 ASTLRW 876 ASTLXP 877 ASTLXPW 878 ASTLXR 879 ASTLXRB 880 ASTLXRH 881 ASTLXRW 882 ASTP 883 ASTPW 884 ASTXP 885 ASTXPW 886 ASTXR 887 ASTXRB 888 ASTXRH 889 ASTXRW 890 ASUB 891 ASUBS 892 ASUBSW 893 ASUBW 894 ASVC 895 ASWPAB 896 ASWPAD 897 ASWPAH 898 ASWPALB 899 ASWPALD 900 ASWPALH 901 ASWPALW 902 ASWPAW 903 ASWPB 904 ASWPD 905 ASWPH 906 ASWPLB 907 ASWPLD 908 ASWPLH 909 ASWPLW 910 ASWPW 911 ASXTB 912 ASXTBW 913 ASXTH 914 ASXTHW 915 ASXTW 916 ASYS 917 ASYSL 918 ATBNZ 919 ATBZ 920 ATLBI 921 ATST 922 ATSTW 923 AUBFIZ 924 AUBFIZW 925 AUBFM 926 AUBFMW 927 AUBFX 928 AUBFXW 929 AUCVTFD 930 AUCVTFS 931 AUCVTFWD 932 AUCVTFWS 933 AUDIV 934 AUDIVW 935 AUMADDL 936 AUMNEGL 937 AUMSUBL 938 AUMULH 939 AUMULL 940 AUREM 941 AUREMW 942 AUXTB 943 AUXTBW 944 AUXTH 945 AUXTHW 946 AUXTW 947 AVADD 948 AVADDP 949 AVADDV 950 AVAND 951 AVBCAX 952 AVBIF 953 AVBIT 954 AVBSL 955 AVCMEQ 956 AVCMTST 957 AVCNT 958 AVDUP 959 AVEOR 960 AVEOR3 961 AVEXT 962 AVFMLA 963 AVFMLS 964 AVLD1 965 AVLD1R 966 AVLD2 967 AVLD2R 968 AVLD3 969 AVLD3R 970 AVLD4 971 AVLD4R 972 AVMOV 973 AVMOVD 974 AVMOVI 975 AVMOVQ 976 AVMOVS 977 AVORR 978 AVPMULL 979 AVPMULL2 980 AVRAX1 981 AVRBIT 982 AVREV16 983 AVREV32 984 AVREV64 985 AVSHL 986 AVSLI 987 AVSRI 988 AVST1 989 AVST2 990 AVST3 991 AVST4 992 AVSUB 993 AVTBL 994 AVTBX 995 AVTRN1 996 AVTRN2 997 AVUADDLV 998 AVUADDW 999 AVUADDW2 1000 AVUMAX 1001 AVUMIN 1002 AVUSHLL 1003 AVUSHLL2 1004 AVUSHR 1005 AVUSRA 1006 AVUXTL 1007 AVUXTL2 1008 AVUZP1 1009 AVUZP2 1010 AVXAR 1011 AVZIP1 1012 AVZIP2 1013 AWFE 1014 AWFI 1015 AWORD 1016 AYIELD 1017 ALAST 1018 AB = obj.AJMP 1019 ABL = obj.ACALL 1020 ) 1021 1022 const ( 1023 // shift types 1024 SHIFT_LL = 0 << 22 1025 SHIFT_LR = 1 << 22 1026 SHIFT_AR = 2 << 22 1027 SHIFT_ROR = 3 << 22 1028 ) 1029 1030 // Arrangement for ARM64 SIMD instructions 1031 const ( 1032 // arrangement types 1033 ARNG_8B = iota 1034 ARNG_16B 1035 ARNG_1D 1036 ARNG_4H 1037 ARNG_8H 1038 ARNG_2S 1039 ARNG_4S 1040 ARNG_2D 1041 ARNG_1Q 1042 ARNG_B 1043 ARNG_H 1044 ARNG_S 1045 ARNG_D 1046 ) 1047 1048 //go:generate stringer -type SpecialOperand -trimprefix SPOP_ 1049 type SpecialOperand int 1050 1051 const ( 1052 // PRFM 1053 SPOP_PLDL1KEEP SpecialOperand = iota 1054 SPOP_BEGIN SpecialOperand = iota - 1 1055 SPOP_PLDL1STRM 1056 SPOP_PLDL2KEEP 1057 SPOP_PLDL2STRM 1058 SPOP_PLDL3KEEP 1059 SPOP_PLDL3STRM 1060 SPOP_PLIL1KEEP 1061 SPOP_PLIL1STRM 1062 SPOP_PLIL2KEEP 1063 SPOP_PLIL2STRM 1064 SPOP_PLIL3KEEP 1065 SPOP_PLIL3STRM 1066 SPOP_PSTL1KEEP 1067 SPOP_PSTL1STRM 1068 SPOP_PSTL2KEEP 1069 SPOP_PSTL2STRM 1070 SPOP_PSTL3KEEP 1071 SPOP_PSTL3STRM 1072 1073 // TLBI 1074 SPOP_VMALLE1IS 1075 SPOP_VAE1IS 1076 SPOP_ASIDE1IS 1077 SPOP_VAAE1IS 1078 SPOP_VALE1IS 1079 SPOP_VAALE1IS 1080 SPOP_VMALLE1 1081 SPOP_VAE1 1082 SPOP_ASIDE1 1083 SPOP_VAAE1 1084 SPOP_VALE1 1085 SPOP_VAALE1 1086 SPOP_IPAS2E1IS 1087 SPOP_IPAS2LE1IS 1088 SPOP_ALLE2IS 1089 SPOP_VAE2IS 1090 SPOP_ALLE1IS 1091 SPOP_VALE2IS 1092 SPOP_VMALLS12E1IS 1093 SPOP_IPAS2E1 1094 SPOP_IPAS2LE1 1095 SPOP_ALLE2 1096 SPOP_VAE2 1097 SPOP_ALLE1 1098 SPOP_VALE2 1099 SPOP_VMALLS12E1 1100 SPOP_ALLE3IS 1101 SPOP_VAE3IS 1102 SPOP_VALE3IS 1103 SPOP_ALLE3 1104 SPOP_VAE3 1105 SPOP_VALE3 1106 SPOP_VMALLE1OS 1107 SPOP_VAE1OS 1108 SPOP_ASIDE1OS 1109 SPOP_VAAE1OS 1110 SPOP_VALE1OS 1111 SPOP_VAALE1OS 1112 SPOP_RVAE1IS 1113 SPOP_RVAAE1IS 1114 SPOP_RVALE1IS 1115 SPOP_RVAALE1IS 1116 SPOP_RVAE1OS 1117 SPOP_RVAAE1OS 1118 SPOP_RVALE1OS 1119 SPOP_RVAALE1OS 1120 SPOP_RVAE1 1121 SPOP_RVAAE1 1122 SPOP_RVALE1 1123 SPOP_RVAALE1 1124 SPOP_RIPAS2E1IS 1125 SPOP_RIPAS2LE1IS 1126 SPOP_ALLE2OS 1127 SPOP_VAE2OS 1128 SPOP_ALLE1OS 1129 SPOP_VALE2OS 1130 SPOP_VMALLS12E1OS 1131 SPOP_RVAE2IS 1132 SPOP_RVALE2IS 1133 SPOP_IPAS2E1OS 1134 SPOP_RIPAS2E1 1135 SPOP_RIPAS2E1OS 1136 SPOP_IPAS2LE1OS 1137 SPOP_RIPAS2LE1 1138 SPOP_RIPAS2LE1OS 1139 SPOP_RVAE2OS 1140 SPOP_RVALE2OS 1141 SPOP_RVAE2 1142 SPOP_RVALE2 1143 SPOP_ALLE3OS 1144 SPOP_VAE3OS 1145 SPOP_VALE3OS 1146 SPOP_RVAE3IS 1147 SPOP_RVALE3IS 1148 SPOP_RVAE3OS 1149 SPOP_RVALE3OS 1150 SPOP_RVAE3 1151 SPOP_RVALE3 1152 1153 // DC 1154 SPOP_IVAC 1155 SPOP_ISW 1156 SPOP_CSW 1157 SPOP_CISW 1158 SPOP_ZVA 1159 SPOP_CVAC 1160 SPOP_CVAU 1161 SPOP_CIVAC 1162 SPOP_IGVAC 1163 SPOP_IGSW 1164 SPOP_IGDVAC 1165 SPOP_IGDSW 1166 SPOP_CGSW 1167 SPOP_CGDSW 1168 SPOP_CIGSW 1169 SPOP_CIGDSW 1170 SPOP_GVA 1171 SPOP_GZVA 1172 SPOP_CGVAC 1173 SPOP_CGDVAC 1174 SPOP_CGVAP 1175 SPOP_CGDVAP 1176 SPOP_CGVADP 1177 SPOP_CGDVADP 1178 SPOP_CIGVAC 1179 SPOP_CIGDVAC 1180 SPOP_CVAP 1181 SPOP_CVADP 1182 1183 // PSTATE fields 1184 SPOP_DAIFSet 1185 SPOP_DAIFClr 1186 1187 // Condition code, EQ, NE, etc. Their relative order to EQ is matter. 1188 SPOP_EQ 1189 SPOP_NE 1190 SPOP_HS 1191 SPOP_LO 1192 SPOP_MI 1193 SPOP_PL 1194 SPOP_VS 1195 SPOP_VC 1196 SPOP_HI 1197 SPOP_LS 1198 SPOP_GE 1199 SPOP_LT 1200 SPOP_GT 1201 SPOP_LE 1202 SPOP_AL 1203 SPOP_NV 1204 1205 SPOP_END 1206 )