github.com/shogo82148/std@v1.22.1-0.20240327122250-4e474527810c/cmd/internal/obj/mips/a.out.go (about) 1 // cmd/9c/9.out.h from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package mips 31 32 import ( 33 "github.com/shogo82148/std/cmd/internal/obj" 34 ) 35 36 /* 37 * mips 64 38 */ 39 const ( 40 NSNAME = 8 41 NSYM = 50 42 NREG = 32 43 NFREG = 32 44 NWREG = 32 45 ) 46 47 const ( 48 REG_R0 = obj.RBaseMIPS + iota 49 REG_R1 50 REG_R2 51 REG_R3 52 REG_R4 53 REG_R5 54 REG_R6 55 REG_R7 56 REG_R8 57 REG_R9 58 REG_R10 59 REG_R11 60 REG_R12 61 REG_R13 62 REG_R14 63 REG_R15 64 REG_R16 65 REG_R17 66 REG_R18 67 REG_R19 68 REG_R20 69 REG_R21 70 REG_R22 71 REG_R23 72 REG_R24 73 REG_R25 74 REG_R26 75 REG_R27 76 REG_R28 77 REG_R29 78 REG_R30 79 REG_R31 80 81 REG_F0 82 REG_F1 83 REG_F2 84 REG_F3 85 REG_F4 86 REG_F5 87 REG_F6 88 REG_F7 89 REG_F8 90 REG_F9 91 REG_F10 92 REG_F11 93 REG_F12 94 REG_F13 95 REG_F14 96 REG_F15 97 REG_F16 98 REG_F17 99 REG_F18 100 REG_F19 101 REG_F20 102 REG_F21 103 REG_F22 104 REG_F23 105 REG_F24 106 REG_F25 107 REG_F26 108 REG_F27 109 REG_F28 110 REG_F29 111 REG_F30 112 REG_F31 113 114 // co-processor 0 control registers 115 REG_M0 116 REG_M1 117 REG_M2 118 REG_M3 119 REG_M4 120 REG_M5 121 REG_M6 122 REG_M7 123 REG_M8 124 REG_M9 125 REG_M10 126 REG_M11 127 REG_M12 128 REG_M13 129 REG_M14 130 REG_M15 131 REG_M16 132 REG_M17 133 REG_M18 134 REG_M19 135 REG_M20 136 REG_M21 137 REG_M22 138 REG_M23 139 REG_M24 140 REG_M25 141 REG_M26 142 REG_M27 143 REG_M28 144 REG_M29 145 REG_M30 146 REG_M31 147 148 // FPU control registers 149 REG_FCR0 150 REG_FCR1 151 REG_FCR2 152 REG_FCR3 153 REG_FCR4 154 REG_FCR5 155 REG_FCR6 156 REG_FCR7 157 REG_FCR8 158 REG_FCR9 159 REG_FCR10 160 REG_FCR11 161 REG_FCR12 162 REG_FCR13 163 REG_FCR14 164 REG_FCR15 165 REG_FCR16 166 REG_FCR17 167 REG_FCR18 168 REG_FCR19 169 REG_FCR20 170 REG_FCR21 171 REG_FCR22 172 REG_FCR23 173 REG_FCR24 174 REG_FCR25 175 REG_FCR26 176 REG_FCR27 177 REG_FCR28 178 REG_FCR29 179 REG_FCR30 180 REG_FCR31 181 182 // MSA registers 183 // The lower bits of W registers are alias to F registers 184 REG_W0 185 REG_W1 186 REG_W2 187 REG_W3 188 REG_W4 189 REG_W5 190 REG_W6 191 REG_W7 192 REG_W8 193 REG_W9 194 REG_W10 195 REG_W11 196 REG_W12 197 REG_W13 198 REG_W14 199 REG_W15 200 REG_W16 201 REG_W17 202 REG_W18 203 REG_W19 204 REG_W20 205 REG_W21 206 REG_W22 207 REG_W23 208 REG_W24 209 REG_W25 210 REG_W26 211 REG_W27 212 REG_W28 213 REG_W29 214 REG_W30 215 REG_W31 216 217 REG_HI 218 REG_LO 219 220 REG_LAST = REG_LO 221 222 REG_SPECIAL = REG_M0 223 224 REGZERO = REG_R0 225 REGSP = REG_R29 226 REGSB = REG_R28 227 REGLINK = REG_R31 228 REGRET = REG_R1 229 REGARG = -1 230 REGRT1 = REG_R1 231 REGRT2 = REG_R2 232 REGCTXT = REG_R22 233 REGG = REG_R30 234 REGTMP = REG_R23 235 FREGRET = REG_F0 236 ) 237 238 // https://llvm.org/svn/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td search for DwarfRegNum 239 // https://gcc.gnu.org/viewcvs/gcc/trunk/gcc/config/mips/mips.c?view=co&revision=258099&content-type=text%2Fplain search for mips_dwarf_regno 240 // For now, this is adequate for both 32 and 64 bit. 241 var MIPSDWARFRegisters = map[int16]int16{} 242 243 const ( 244 BIG = 32766 245 ) 246 247 const ( 248 /* mark flags */ 249 FOLL = 1 << 0 250 LABEL = 1 << 1 251 LEAF = 1 << 2 252 SYNC = 1 << 3 253 BRANCH = 1 << 4 254 LOAD = 1 << 5 255 FCMP = 1 << 6 256 NOSCHED = 1 << 7 257 258 NSCHED = 20 259 ) 260 261 const ( 262 C_NONE = iota 263 C_REG 264 C_FREG 265 C_FCREG 266 C_MREG 267 C_WREG 268 C_HI 269 C_LO 270 C_ZCON 271 C_SCON 272 C_UCON 273 C_ADD0CON 274 C_AND0CON 275 C_ADDCON 276 C_ANDCON 277 C_LCON 278 C_DCON 279 C_SACON 280 C_SECON 281 C_LACON 282 C_LECON 283 C_DACON 284 C_STCON 285 C_SBRA 286 C_LBRA 287 C_SAUTO 288 C_LAUTO 289 C_SEXT 290 C_LEXT 291 C_ZOREG 292 C_SOREG 293 C_LOREG 294 C_GOK 295 C_ADDR 296 C_TLS 297 C_TEXTSIZE 298 299 C_NCLASS 300 ) 301 302 const ( 303 AABSD = obj.ABaseMIPS + obj.A_ARCHSPECIFIC + iota 304 AABSF 305 AABSW 306 AADD 307 AADDD 308 AADDF 309 AADDU 310 AADDW 311 AAND 312 ABEQ 313 ABFPF 314 ABFPT 315 ABGEZ 316 ABGEZAL 317 ABGTZ 318 ABLEZ 319 ABLTZ 320 ABLTZAL 321 ABNE 322 ABREAK 323 ACLO 324 ACLZ 325 ACMOVF 326 ACMOVN 327 ACMOVT 328 ACMOVZ 329 ACMPEQD 330 ACMPEQF 331 ACMPGED 332 ACMPGEF 333 ACMPGTD 334 ACMPGTF 335 ADIV 336 ADIVD 337 ADIVF 338 ADIVU 339 ADIVW 340 AGOK 341 ALL 342 ALLV 343 ALUI 344 AMADD 345 AMOVB 346 AMOVBU 347 AMOVD 348 AMOVDF 349 AMOVDW 350 AMOVF 351 AMOVFD 352 AMOVFW 353 AMOVH 354 AMOVHU 355 AMOVW 356 AMOVWD 357 AMOVWF 358 AMOVWL 359 AMOVWR 360 AMSUB 361 AMUL 362 AMULD 363 AMULF 364 AMULU 365 AMULW 366 ANEGD 367 ANEGF 368 ANEGW 369 ANEGV 370 ANOOP 371 ANOR 372 AOR 373 AREM 374 AREMU 375 ARFE 376 AROTR 377 AROTRV 378 ASC 379 ASCV 380 ASEB 381 ASEH 382 ASGT 383 ASGTU 384 ASLL 385 ASQRTD 386 ASQRTF 387 ASRA 388 ASRL 389 ASUB 390 ASUBD 391 ASUBF 392 ASUBU 393 ASUBW 394 ASYNC 395 ASYSCALL 396 ATEQ 397 ATLBP 398 ATLBR 399 ATLBWI 400 ATLBWR 401 ATNE 402 AWORD 403 AWSBH 404 AXOR 405 406 /* 64-bit */ 407 AMOVV 408 AMOVVL 409 AMOVVR 410 ASLLV 411 ASRAV 412 ASRLV 413 ADIVV 414 ADIVVU 415 AREMV 416 AREMVU 417 AMULV 418 AMULVU 419 AADDV 420 AADDVU 421 ASUBV 422 ASUBVU 423 ADSBH 424 ADSHD 425 426 /* 64-bit FP */ 427 ATRUNCFV 428 ATRUNCDV 429 ATRUNCFW 430 ATRUNCDW 431 AMOVWU 432 AMOVFV 433 AMOVDV 434 AMOVVF 435 AMOVVD 436 437 /* MSA */ 438 AVMOVB 439 AVMOVH 440 AVMOVW 441 AVMOVD 442 443 ALAST 444 445 // aliases 446 AJMP = obj.AJMP 447 AJAL = obj.ACALL 448 ARET = obj.ARET 449 )